Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 23:58:55.482690 lava-dispatcher, installed at version: 2024.01
2 23:58:55.483486 start: 0 validate
3 23:58:55.483974 Start time: 2024-11-07 23:58:55.483943+00:00 (UTC)
4 23:58:55.484544 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 23:58:55.485140 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:58:55.529887 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 23:58:55.530459 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 23:58:55.567618 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 23:58:55.568515 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 23:58:55.603347 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 23:58:55.603858 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:58:55.637678 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 23:58:55.638170 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 23:58:55.677596 validate duration: 0.19
16 23:58:55.678407 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:58:55.678726 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:58:55.679038 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:58:55.679598 Not decompressing ramdisk as can be used compressed.
20 23:58:55.680066 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:58:55.680353 saving as /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/ramdisk/initrd.cpio.gz
22 23:58:55.680611 total size: 5628169 (5 MB)
23 23:58:55.713791 progress 0 % (0 MB)
24 23:58:55.718013 progress 5 % (0 MB)
25 23:58:55.722382 progress 10 % (0 MB)
26 23:58:55.726177 progress 15 % (0 MB)
27 23:58:55.730370 progress 20 % (1 MB)
28 23:58:55.734010 progress 25 % (1 MB)
29 23:58:55.738140 progress 30 % (1 MB)
30 23:58:55.742271 progress 35 % (1 MB)
31 23:58:55.745977 progress 40 % (2 MB)
32 23:58:55.750013 progress 45 % (2 MB)
33 23:58:55.753725 progress 50 % (2 MB)
34 23:58:55.757822 progress 55 % (2 MB)
35 23:58:55.761918 progress 60 % (3 MB)
36 23:58:55.765636 progress 65 % (3 MB)
37 23:58:55.769765 progress 70 % (3 MB)
38 23:58:55.773525 progress 75 % (4 MB)
39 23:58:55.777558 progress 80 % (4 MB)
40 23:58:55.781194 progress 85 % (4 MB)
41 23:58:55.785289 progress 90 % (4 MB)
42 23:58:55.789186 progress 95 % (5 MB)
43 23:58:55.792504 progress 100 % (5 MB)
44 23:58:55.793162 5 MB downloaded in 0.11 s (47.70 MB/s)
45 23:58:55.793718 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:58:55.794624 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:58:55.794929 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:58:55.795211 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:58:55.795674 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/kernel/Image
51 23:58:55.795926 saving as /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/kernel/Image
52 23:58:55.796168 total size: 45713920 (43 MB)
53 23:58:55.796386 No compression specified
54 23:58:55.840385 progress 0 % (0 MB)
55 23:58:55.868049 progress 5 % (2 MB)
56 23:58:55.896247 progress 10 % (4 MB)
57 23:58:55.923894 progress 15 % (6 MB)
58 23:58:55.951833 progress 20 % (8 MB)
59 23:58:55.979232 progress 25 % (10 MB)
60 23:58:56.007210 progress 30 % (13 MB)
61 23:58:56.035237 progress 35 % (15 MB)
62 23:58:56.063347 progress 40 % (17 MB)
63 23:58:56.090813 progress 45 % (19 MB)
64 23:58:56.118699 progress 50 % (21 MB)
65 23:58:56.146642 progress 55 % (24 MB)
66 23:58:56.174574 progress 60 % (26 MB)
67 23:58:56.202008 progress 65 % (28 MB)
68 23:58:56.229945 progress 70 % (30 MB)
69 23:58:56.258071 progress 75 % (32 MB)
70 23:58:56.285803 progress 80 % (34 MB)
71 23:58:56.313398 progress 85 % (37 MB)
72 23:58:56.341343 progress 90 % (39 MB)
73 23:58:56.369601 progress 95 % (41 MB)
74 23:58:56.397522 progress 100 % (43 MB)
75 23:58:56.398068 43 MB downloaded in 0.60 s (72.43 MB/s)
76 23:58:56.398575 end: 1.2.1 http-download (duration 00:00:01) [common]
78 23:58:56.399499 end: 1.2 download-retry (duration 00:00:01) [common]
79 23:58:56.399832 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:58:56.400172 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:58:56.400685 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 23:58:56.400997 saving as /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/dtb/meson-g12b-a311d-libretech-cc.dtb
83 23:58:56.401216 total size: 54703 (0 MB)
84 23:58:56.401428 No compression specified
85 23:58:56.445640 progress 59 % (0 MB)
86 23:58:56.446526 progress 100 % (0 MB)
87 23:58:56.447090 0 MB downloaded in 0.05 s (1.14 MB/s)
88 23:58:56.447562 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:58:56.448446 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:58:56.448720 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:58:56.448989 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:58:56.449472 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:58:56.449724 saving as /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/nfsrootfs/full.rootfs.tar
95 23:58:56.449929 total size: 120894716 (115 MB)
96 23:58:56.450139 Using unxz to decompress xz
97 23:58:56.487677 progress 0 % (0 MB)
98 23:58:57.288889 progress 5 % (5 MB)
99 23:58:58.141804 progress 10 % (11 MB)
100 23:58:58.938792 progress 15 % (17 MB)
101 23:58:59.677894 progress 20 % (23 MB)
102 23:59:00.268152 progress 25 % (28 MB)
103 23:59:01.089921 progress 30 % (34 MB)
104 23:59:01.876040 progress 35 % (40 MB)
105 23:59:02.238984 progress 40 % (46 MB)
106 23:59:02.616827 progress 45 % (51 MB)
107 23:59:03.344578 progress 50 % (57 MB)
108 23:59:04.242369 progress 55 % (63 MB)
109 23:59:05.022540 progress 60 % (69 MB)
110 23:59:05.776787 progress 65 % (74 MB)
111 23:59:06.549389 progress 70 % (80 MB)
112 23:59:07.366106 progress 75 % (86 MB)
113 23:59:08.151435 progress 80 % (92 MB)
114 23:59:08.909596 progress 85 % (98 MB)
115 23:59:09.761486 progress 90 % (103 MB)
116 23:59:10.534842 progress 95 % (109 MB)
117 23:59:11.365753 progress 100 % (115 MB)
118 23:59:11.378816 115 MB downloaded in 14.93 s (7.72 MB/s)
119 23:59:11.379685 end: 1.4.1 http-download (duration 00:00:15) [common]
121 23:59:11.381317 end: 1.4 download-retry (duration 00:00:15) [common]
122 23:59:11.381831 start: 1.5 download-retry (timeout 00:09:44) [common]
123 23:59:11.382332 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 23:59:11.383096 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/modules.tar.xz
125 23:59:11.383544 saving as /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/modules/modules.tar
126 23:59:11.383947 total size: 11603932 (11 MB)
127 23:59:11.384391 Using unxz to decompress xz
128 23:59:11.428948 progress 0 % (0 MB)
129 23:59:11.496418 progress 5 % (0 MB)
130 23:59:11.572500 progress 10 % (1 MB)
131 23:59:11.670447 progress 15 % (1 MB)
132 23:59:11.764087 progress 20 % (2 MB)
133 23:59:11.843785 progress 25 % (2 MB)
134 23:59:11.919677 progress 30 % (3 MB)
135 23:59:11.993823 progress 35 % (3 MB)
136 23:59:12.071009 progress 40 % (4 MB)
137 23:59:12.147004 progress 45 % (5 MB)
138 23:59:12.230787 progress 50 % (5 MB)
139 23:59:12.308396 progress 55 % (6 MB)
140 23:59:12.393770 progress 60 % (6 MB)
141 23:59:12.474671 progress 65 % (7 MB)
142 23:59:12.551540 progress 70 % (7 MB)
143 23:59:12.634612 progress 75 % (8 MB)
144 23:59:12.718110 progress 80 % (8 MB)
145 23:59:12.798080 progress 85 % (9 MB)
146 23:59:12.876455 progress 90 % (9 MB)
147 23:59:12.955281 progress 95 % (10 MB)
148 23:59:13.033080 progress 100 % (11 MB)
149 23:59:13.044156 11 MB downloaded in 1.66 s (6.67 MB/s)
150 23:59:13.044725 end: 1.5.1 http-download (duration 00:00:02) [common]
152 23:59:13.045548 end: 1.5 download-retry (duration 00:00:02) [common]
153 23:59:13.045816 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 23:59:13.046079 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 23:59:29.442826 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/955849/extract-nfsrootfs-ujssrma3
156 23:59:29.443437 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 23:59:29.443722 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 23:59:29.444452 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw
159 23:59:29.444905 makedir: /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin
160 23:59:29.445233 makedir: /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/tests
161 23:59:29.445544 makedir: /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/results
162 23:59:29.445873 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-add-keys
163 23:59:29.446396 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-add-sources
164 23:59:29.446897 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-background-process-start
165 23:59:29.447385 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-background-process-stop
166 23:59:29.447910 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-common-functions
167 23:59:29.448449 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-echo-ipv4
168 23:59:29.448940 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-install-packages
169 23:59:29.449533 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-installed-packages
170 23:59:29.450009 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-os-build
171 23:59:29.450561 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-probe-channel
172 23:59:29.451059 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-probe-ip
173 23:59:29.451601 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-target-ip
174 23:59:29.452110 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-target-mac
175 23:59:29.452587 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-target-storage
176 23:59:29.453099 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-case
177 23:59:29.453599 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-event
178 23:59:29.454091 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-feedback
179 23:59:29.454561 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-raise
180 23:59:29.455024 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-reference
181 23:59:29.455488 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-runner
182 23:59:29.455954 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-set
183 23:59:29.456481 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-test-shell
184 23:59:29.456991 Updating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-add-keys (debian)
185 23:59:29.457528 Updating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-add-sources (debian)
186 23:59:29.458023 Updating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-install-packages (debian)
187 23:59:29.458519 Updating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-installed-packages (debian)
188 23:59:29.459005 Updating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/bin/lava-os-build (debian)
189 23:59:29.459435 Creating /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/environment
190 23:59:29.459803 LAVA metadata
191 23:59:29.460144 - LAVA_JOB_ID=955849
192 23:59:29.460371 - LAVA_DISPATCHER_IP=192.168.6.2
193 23:59:29.460736 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 23:59:29.461694 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 23:59:29.462002 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 23:59:29.462211 skipped lava-vland-overlay
197 23:59:29.462450 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 23:59:29.462705 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 23:59:29.462922 skipped lava-multinode-overlay
200 23:59:29.463164 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 23:59:29.463414 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 23:59:29.463657 Loading test definitions
203 23:59:29.463930 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 23:59:29.464175 Using /lava-955849 at stage 0
205 23:59:29.465268 uuid=955849_1.6.2.4.1 testdef=None
206 23:59:29.465569 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 23:59:29.465830 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 23:59:29.467365 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 23:59:29.468168 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 23:59:29.470060 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 23:59:29.470870 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 23:59:29.472691 runner path: /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/0/tests/0_timesync-off test_uuid 955849_1.6.2.4.1
215 23:59:29.473229 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 23:59:29.474031 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 23:59:29.474251 Using /lava-955849 at stage 0
219 23:59:29.474597 Fetching tests from https://github.com/kernelci/test-definitions.git
220 23:59:29.474883 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/0/tests/1_kselftest-dt'
221 23:59:32.778795 Running '/usr/bin/git checkout kernelci.org
222 23:59:33.226935 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 23:59:33.228389 uuid=955849_1.6.2.4.5 testdef=None
224 23:59:33.228731 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 23:59:33.229475 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 23:59:33.232308 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 23:59:33.233122 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 23:59:33.236819 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 23:59:33.237664 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 23:59:33.241237 runner path: /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/0/tests/1_kselftest-dt test_uuid 955849_1.6.2.4.5
234 23:59:33.241517 BOARD='meson-g12b-a311d-libretech-cc'
235 23:59:33.241720 BRANCH='broonie-spi'
236 23:59:33.241917 SKIPFILE='/dev/null'
237 23:59:33.242112 SKIP_INSTALL='True'
238 23:59:33.242306 TESTPROG_URL='http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 23:59:33.242529 TST_CASENAME=''
240 23:59:33.242726 TST_CMDFILES='dt'
241 23:59:33.243254 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 23:59:33.244053 Creating lava-test-runner.conf files
244 23:59:33.244262 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955849/lava-overlay-idznzrqw/lava-955849/0 for stage 0
245 23:59:33.244608 - 0_timesync-off
246 23:59:33.244845 - 1_kselftest-dt
247 23:59:33.245171 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 23:59:33.245448 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 23:59:56.628510 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 23:59:56.628964 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 23:59:56.629242 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 23:59:56.629521 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 23:59:56.629790 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 23:59:57.280415 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 23:59:57.281002 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 23:59:57.281335 extracting modules file /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955849/extract-nfsrootfs-ujssrma3
257 23:59:58.717576 extracting modules file /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955849/extract-overlay-ramdisk-7gtfdl5g/ramdisk
258 00:00:00.106376 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 00:00:00.106856 start: 1.6.5 apply-overlay-tftp (timeout 00:08:56) [common]
260 00:00:00.107154 [common] Applying overlay to NFS
261 00:00:00.107382 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955849/compress-overlay-0uuxouhw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955849/extract-nfsrootfs-ujssrma3
262 00:00:02.842279 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 00:00:02.842736 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 00:00:02.843037 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 00:00:02.843294 Converting downloaded kernel to a uImage
266 00:00:02.843621 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/kernel/Image /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/kernel/uImage
267 00:00:03.296018 output: Image Name:
268 00:00:03.296447 output: Created: Fri Nov 8 00:00:02 2024
269 00:00:03.296656 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 00:00:03.296861 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 00:00:03.297061 output: Load Address: 01080000
272 00:00:03.297263 output: Entry Point: 01080000
273 00:00:03.297463 output:
274 00:00:03.297799 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 00:00:03.298065 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 00:00:03.298333 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 00:00:03.298588 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 00:00:03.298846 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 00:00:03.299101 Building ramdisk /var/lib/lava/dispatcher/tmp/955849/extract-overlay-ramdisk-7gtfdl5g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955849/extract-overlay-ramdisk-7gtfdl5g/ramdisk
280 00:00:05.484263 >> 166774 blocks
281 00:00:13.443771 Adding RAMdisk u-boot header.
282 00:00:13.444489 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955849/extract-overlay-ramdisk-7gtfdl5g/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955849/extract-overlay-ramdisk-7gtfdl5g/ramdisk.cpio.gz.uboot
283 00:00:13.687250 output: Image Name:
284 00:00:13.687882 output: Created: Fri Nov 8 00:00:13 2024
285 00:00:13.688366 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 00:00:13.688786 output: Data Size: 23429103 Bytes = 22879.98 KiB = 22.34 MiB
287 00:00:13.689190 output: Load Address: 00000000
288 00:00:13.689588 output: Entry Point: 00000000
289 00:00:13.689985 output:
290 00:00:13.691035 rename /var/lib/lava/dispatcher/tmp/955849/extract-overlay-ramdisk-7gtfdl5g/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot
291 00:00:13.691763 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 00:00:13.692356 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 00:00:13.692920 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:42) [common]
294 00:00:13.693365 No LXC device requested
295 00:00:13.693865 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 00:00:13.694377 start: 1.8 deploy-device-env (timeout 00:08:42) [common]
297 00:00:13.694871 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 00:00:13.695282 Checking files for TFTP limit of 4294967296 bytes.
299 00:00:13.697957 end: 1 tftp-deploy (duration 00:01:18) [common]
300 00:00:13.698544 start: 2 uboot-action (timeout 00:05:00) [common]
301 00:00:13.699099 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 00:00:13.699620 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 00:00:13.700174 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 00:00:13.700721 Using kernel file from prepare-kernel: 955849/tftp-deploy-2nxhdpr_/kernel/uImage
305 00:00:13.701371 substitutions:
306 00:00:13.701787 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 00:00:13.702195 - {DTB_ADDR}: 0x01070000
308 00:00:13.702611 - {DTB}: 955849/tftp-deploy-2nxhdpr_/dtb/meson-g12b-a311d-libretech-cc.dtb
309 00:00:13.703026 - {INITRD}: 955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot
310 00:00:13.703435 - {KERNEL_ADDR}: 0x01080000
311 00:00:13.703833 - {KERNEL}: 955849/tftp-deploy-2nxhdpr_/kernel/uImage
312 00:00:13.704291 - {LAVA_MAC}: None
313 00:00:13.704742 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/955849/extract-nfsrootfs-ujssrma3
314 00:00:13.705166 - {NFS_SERVER_IP}: 192.168.6.2
315 00:00:13.705565 - {PRESEED_CONFIG}: None
316 00:00:13.705967 - {PRESEED_LOCAL}: None
317 00:00:13.706365 - {RAMDISK_ADDR}: 0x08000000
318 00:00:13.706760 - {RAMDISK}: 955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot
319 00:00:13.707159 - {ROOT_PART}: None
320 00:00:13.707553 - {ROOT}: None
321 00:00:13.707950 - {SERVER_IP}: 192.168.6.2
322 00:00:13.708376 - {TEE_ADDR}: 0x83000000
323 00:00:13.708768 - {TEE}: None
324 00:00:13.709162 Parsed boot commands:
325 00:00:13.709543 - setenv autoload no
326 00:00:13.709944 - setenv initrd_high 0xffffffff
327 00:00:13.710360 - setenv fdt_high 0xffffffff
328 00:00:13.710757 - dhcp
329 00:00:13.711398 - setenv serverip 192.168.6.2
330 00:00:13.711884 - tftpboot 0x01080000 955849/tftp-deploy-2nxhdpr_/kernel/uImage
331 00:00:13.712351 - tftpboot 0x08000000 955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot
332 00:00:13.712796 - tftpboot 0x01070000 955849/tftp-deploy-2nxhdpr_/dtb/meson-g12b-a311d-libretech-cc.dtb
333 00:00:13.713230 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/955849/extract-nfsrootfs-ujssrma3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 00:00:13.713676 - bootm 0x01080000 0x08000000 0x01070000
335 00:00:13.714241 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 00:00:13.716065 start: 2.3 connect-device (timeout 00:05:00) [common]
338 00:00:13.716553 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 00:00:13.731447 Setting prompt string to ['lava-test: # ']
340 00:00:13.733098 end: 2.3 connect-device (duration 00:00:00) [common]
341 00:00:13.733806 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 00:00:13.734689 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 00:00:13.735466 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 00:00:13.736202 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 00:00:13.768960 >> OK - accepted request
346 00:00:13.770720 Returned 0 in 0 seconds
347 00:00:13.871594 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 00:00:13.873326 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 00:00:13.873882 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 00:00:13.874392 Setting prompt string to ['Hit any key to stop autoboot']
352 00:00:13.874842 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 00:00:13.876413 Trying 192.168.56.21...
354 00:00:13.876898 Connected to conserv1.
355 00:00:13.877324 Escape character is '^]'.
356 00:00:13.877747
357 00:00:13.878164 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 00:00:13.878583
359 00:00:25.333213 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 00:00:25.333838 bl2_stage_init 0x01
361 00:00:25.334280 bl2_stage_init 0x81
362 00:00:25.338881 hw id: 0x0000 - pwm id 0x01
363 00:00:25.339473 bl2_stage_init 0xc1
364 00:00:25.339904 bl2_stage_init 0x02
365 00:00:25.340378
366 00:00:25.344529 L0:00000000
367 00:00:25.345109 L1:20000703
368 00:00:25.345535 L2:00008067
369 00:00:25.345980 L3:14000000
370 00:00:25.347375 B2:00402000
371 00:00:25.347846 B1:e0f83180
372 00:00:25.348320
373 00:00:25.348734 TE: 58124
374 00:00:25.349148
375 00:00:25.358574 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 00:00:25.359087
377 00:00:25.359502 Board ID = 1
378 00:00:25.359900 Set A53 clk to 24M
379 00:00:25.360338 Set A73 clk to 24M
380 00:00:25.364030 Set clk81 to 24M
381 00:00:25.364482 A53 clk: 1200 MHz
382 00:00:25.364890 A73 clk: 1200 MHz
383 00:00:25.367516 CLK81: 166.6M
384 00:00:25.367949 smccc: 00012a92
385 00:00:25.373241 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 00:00:25.378658 board id: 1
387 00:00:25.383782 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 00:00:25.394463 fw parse done
389 00:00:25.400463 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 00:00:25.443061 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 00:00:25.454053 PIEI prepare done
392 00:00:25.454482 fastboot data load
393 00:00:25.454876 fastboot data verify
394 00:00:25.459542 verify result: 266
395 00:00:25.465279 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 00:00:25.465934 LPDDR4 probe
397 00:00:25.466419 ddr clk to 1584MHz
398 00:00:25.473263 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 00:00:25.510560
400 00:00:25.511155 dmc_version 0001
401 00:00:25.517171 Check phy result
402 00:00:25.523066 INFO : End of CA training
403 00:00:25.523588 INFO : End of initialization
404 00:00:25.528608 INFO : Training has run successfully!
405 00:00:25.529141 Check phy result
406 00:00:25.534297 INFO : End of initialization
407 00:00:25.534837 INFO : End of read enable training
408 00:00:25.539798 INFO : End of fine write leveling
409 00:00:25.545439 INFO : End of Write leveling coarse delay
410 00:00:25.545991 INFO : Training has run successfully!
411 00:00:25.546481 Check phy result
412 00:00:25.551134 INFO : End of initialization
413 00:00:25.551678 INFO : End of read dq deskew training
414 00:00:25.556689 INFO : End of MPR read delay center optimization
415 00:00:25.562270 INFO : End of write delay center optimization
416 00:00:25.567945 INFO : End of read delay center optimization
417 00:00:25.568587 INFO : End of max read latency training
418 00:00:25.573566 INFO : Training has run successfully!
419 00:00:25.574145 1D training succeed
420 00:00:25.582696 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 00:00:25.630261 Check phy result
422 00:00:25.631141 INFO : End of initialization
423 00:00:25.651975 INFO : End of 2D read delay Voltage center optimization
424 00:00:25.672292 INFO : End of 2D read delay Voltage center optimization
425 00:00:25.724256 INFO : End of 2D write delay Voltage center optimization
426 00:00:25.773631 INFO : End of 2D write delay Voltage center optimization
427 00:00:25.779108 INFO : Training has run successfully!
428 00:00:25.779660
429 00:00:25.780160 channel==0
430 00:00:25.784680 RxClkDly_Margin_A0==88 ps 9
431 00:00:25.785215 TxDqDly_Margin_A0==98 ps 10
432 00:00:25.790300 RxClkDly_Margin_A1==88 ps 9
433 00:00:25.790833 TxDqDly_Margin_A1==98 ps 10
434 00:00:25.791278 TrainedVREFDQ_A0==74
435 00:00:25.795864 TrainedVREFDQ_A1==74
436 00:00:25.796434 VrefDac_Margin_A0==25
437 00:00:25.796878 DeviceVref_Margin_A0==40
438 00:00:25.801491 VrefDac_Margin_A1==26
439 00:00:25.802025 DeviceVref_Margin_A1==40
440 00:00:25.802469
441 00:00:25.802910
442 00:00:25.807080 channel==1
443 00:00:25.807615 RxClkDly_Margin_A0==98 ps 10
444 00:00:25.808093 TxDqDly_Margin_A0==98 ps 10
445 00:00:25.812694 RxClkDly_Margin_A1==98 ps 10
446 00:00:25.813235 TxDqDly_Margin_A1==88 ps 9
447 00:00:25.818313 TrainedVREFDQ_A0==77
448 00:00:25.818853 TrainedVREFDQ_A1==77
449 00:00:25.819298 VrefDac_Margin_A0==22
450 00:00:25.823879 DeviceVref_Margin_A0==37
451 00:00:25.824462 VrefDac_Margin_A1==22
452 00:00:25.829555 DeviceVref_Margin_A1==37
453 00:00:25.830138
454 00:00:25.830588 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 00:00:25.835125
456 00:00:25.863044 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 00:00:25.863710 2D training succeed
458 00:00:25.868731 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 00:00:25.874436 auto size-- 65535DDR cs0 size: 2048MB
460 00:00:25.875010 DDR cs1 size: 2048MB
461 00:00:25.879953 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 00:00:25.880531 cs0 DataBus test pass
463 00:00:25.885539 cs1 DataBus test pass
464 00:00:25.886065 cs0 AddrBus test pass
465 00:00:25.886507 cs1 AddrBus test pass
466 00:00:25.886941
467 00:00:25.891126 100bdlr_step_size ps== 420
468 00:00:25.891658 result report
469 00:00:25.896738 boot times 0Enable ddr reg access
470 00:00:25.902168 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 00:00:25.915642 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 00:00:26.489306 0.0;M3 CHK:0;cm4_sp_mode 0
473 00:00:26.489989 MVN_1=0x00000000
474 00:00:26.494782 MVN_2=0x00000000
475 00:00:26.500574 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 00:00:26.501124 OPS=0x10
477 00:00:26.501596 ring efuse init
478 00:00:26.502051 chipver efuse init
479 00:00:26.506156 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 00:00:26.511749 [0.018961 Inits done]
481 00:00:26.512358 secure task start!
482 00:00:26.512824 high task start!
483 00:00:26.516330 low task start!
484 00:00:26.516861 run into bl31
485 00:00:26.523016 NOTICE: BL31: v1.3(release):4fc40b1
486 00:00:26.530857 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 00:00:26.531405 NOTICE: BL31: G12A normal boot!
488 00:00:26.556236 NOTICE: BL31: BL33 decompress pass
489 00:00:26.561911 ERROR: Error initializing runtime service opteed_fast
490 00:00:27.794866
491 00:00:27.795543
492 00:00:27.803166 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 00:00:27.803738
494 00:00:27.804258 Model: Libre Computer AML-A311D-CC Alta
495 00:00:28.012126 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 00:00:28.035082 DRAM: 2 GiB (effective 3.8 GiB)
497 00:00:28.178092 Core: 408 devices, 31 uclasses, devicetree: separate
498 00:00:28.183912 WDT: Not starting watchdog@f0d0
499 00:00:28.216233 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 00:00:28.228632 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 00:00:28.233600 ** Bad device specification mmc 0 **
502 00:00:28.243947 Card did not respond to voltage select! : -110
503 00:00:28.251600 ** Bad device specification mmc 0 **
504 00:00:28.252165 Couldn't find partition mmc 0
505 00:00:28.259906 Card did not respond to voltage select! : -110
506 00:00:28.265453 ** Bad device specification mmc 0 **
507 00:00:28.265975 Couldn't find partition mmc 0
508 00:00:28.270482 Error: could not access storage.
509 00:00:29.533528 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 00:00:29.534202 bl2_stage_init 0x01
511 00:00:29.534687 bl2_stage_init 0x81
512 00:00:29.539073 hw id: 0x0000 - pwm id 0x01
513 00:00:29.539614 bl2_stage_init 0xc1
514 00:00:29.540130 bl2_stage_init 0x02
515 00:00:29.540593
516 00:00:29.544653 L0:00000000
517 00:00:29.545194 L1:20000703
518 00:00:29.545654 L2:00008067
519 00:00:29.546102 L3:14000000
520 00:00:29.550263 B2:00402000
521 00:00:29.550805 B1:e0f83180
522 00:00:29.551271
523 00:00:29.551724 TE: 58167
524 00:00:29.552232
525 00:00:29.555859 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 00:00:29.556427
527 00:00:29.556891 Board ID = 1
528 00:00:29.561442 Set A53 clk to 24M
529 00:00:29.561968 Set A73 clk to 24M
530 00:00:29.562428 Set clk81 to 24M
531 00:00:29.567010 A53 clk: 1200 MHz
532 00:00:29.567547 A73 clk: 1200 MHz
533 00:00:29.568033 CLK81: 166.6M
534 00:00:29.568494 smccc: 00012abe
535 00:00:29.572648 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 00:00:29.578208 board id: 1
537 00:00:29.584102 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 00:00:29.594805 fw parse done
539 00:00:29.600722 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 00:00:29.643333 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 00:00:29.654248 PIEI prepare done
542 00:00:29.654774 fastboot data load
543 00:00:29.655235 fastboot data verify
544 00:00:29.659910 verify result: 266
545 00:00:29.665443 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 00:00:29.665965 LPDDR4 probe
547 00:00:29.666416 ddr clk to 1584MHz
548 00:00:29.673436 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 00:00:29.710762
550 00:00:29.711347 dmc_version 0001
551 00:00:29.717408 Check phy result
552 00:00:29.723283 INFO : End of CA training
553 00:00:29.723799 INFO : End of initialization
554 00:00:29.728900 INFO : Training has run successfully!
555 00:00:29.729411 Check phy result
556 00:00:29.734461 INFO : End of initialization
557 00:00:29.734967 INFO : End of read enable training
558 00:00:29.740085 INFO : End of fine write leveling
559 00:00:29.745693 INFO : End of Write leveling coarse delay
560 00:00:29.746228 INFO : Training has run successfully!
561 00:00:29.746681 Check phy result
562 00:00:29.751274 INFO : End of initialization
563 00:00:29.751801 INFO : End of read dq deskew training
564 00:00:29.756892 INFO : End of MPR read delay center optimization
565 00:00:29.762459 INFO : End of write delay center optimization
566 00:00:29.768082 INFO : End of read delay center optimization
567 00:00:29.768602 INFO : End of max read latency training
568 00:00:29.773641 INFO : Training has run successfully!
569 00:00:29.774155 1D training succeed
570 00:00:29.782787 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 00:00:29.830454 Check phy result
572 00:00:29.831035 INFO : End of initialization
573 00:00:29.852284 INFO : End of 2D read delay Voltage center optimization
574 00:00:29.872483 INFO : End of 2D read delay Voltage center optimization
575 00:00:29.924589 INFO : End of 2D write delay Voltage center optimization
576 00:00:29.973868 INFO : End of 2D write delay Voltage center optimization
577 00:00:29.979405 INFO : Training has run successfully!
578 00:00:29.979923
579 00:00:29.980430 channel==0
580 00:00:29.985061 RxClkDly_Margin_A0==88 ps 9
581 00:00:29.985581 TxDqDly_Margin_A0==98 ps 10
582 00:00:29.990627 RxClkDly_Margin_A1==88 ps 9
583 00:00:29.991132 TxDqDly_Margin_A1==98 ps 10
584 00:00:29.991586 TrainedVREFDQ_A0==74
585 00:00:29.996309 TrainedVREFDQ_A1==74
586 00:00:29.996849 VrefDac_Margin_A0==25
587 00:00:29.997301 DeviceVref_Margin_A0==40
588 00:00:30.001833 VrefDac_Margin_A1==25
589 00:00:30.002348 DeviceVref_Margin_A1==40
590 00:00:30.002799
591 00:00:30.003251
592 00:00:30.007402 channel==1
593 00:00:30.007913 RxClkDly_Margin_A0==98 ps 10
594 00:00:30.008402 TxDqDly_Margin_A0==88 ps 9
595 00:00:30.013041 RxClkDly_Margin_A1==98 ps 10
596 00:00:30.013590 TxDqDly_Margin_A1==98 ps 10
597 00:00:30.018739 TrainedVREFDQ_A0==75
598 00:00:30.019324 TrainedVREFDQ_A1==77
599 00:00:30.019786 VrefDac_Margin_A0==22
600 00:00:30.024328 DeviceVref_Margin_A0==39
601 00:00:30.024872 VrefDac_Margin_A1==22
602 00:00:30.029857 DeviceVref_Margin_A1==37
603 00:00:30.030371
604 00:00:30.030810 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 00:00:30.035422
606 00:00:30.063394 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 00:00:30.064011 2D training succeed
608 00:00:30.069053 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 00:00:30.074628 auto size-- 65535DDR cs0 size: 2048MB
610 00:00:30.075133 DDR cs1 size: 2048MB
611 00:00:30.080245 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 00:00:30.080755 cs0 DataBus test pass
613 00:00:30.085889 cs1 DataBus test pass
614 00:00:30.086414 cs0 AddrBus test pass
615 00:00:30.086854 cs1 AddrBus test pass
616 00:00:30.087286
617 00:00:30.091458 100bdlr_step_size ps== 420
618 00:00:30.092034 result report
619 00:00:30.097135 boot times 0Enable ddr reg access
620 00:00:30.102520 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 00:00:30.115976 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 00:00:30.689754 0.0;M3 CHK:0;cm4_sp_mode 0
623 00:00:30.690724 MVN_1=0x00000000
624 00:00:30.695332 MVN_2=0x00000000
625 00:00:30.701253 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 00:00:30.701648 OPS=0x10
627 00:00:30.701888 ring efuse init
628 00:00:30.702119 chipver efuse init
629 00:00:30.706506 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 00:00:30.712291 [0.018961 Inits done]
631 00:00:30.712677 secure task start!
632 00:00:30.712906 high task start!
633 00:00:30.715856 low task start!
634 00:00:30.716179 run into bl31
635 00:00:30.723373 NOTICE: BL31: v1.3(release):4fc40b1
636 00:00:30.731532 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 00:00:30.731887 NOTICE: BL31: G12A normal boot!
638 00:00:30.756494 NOTICE: BL31: BL33 decompress pass
639 00:00:30.762258 ERROR: Error initializing runtime service opteed_fast
640 00:00:31.995026
641 00:00:31.995467
642 00:00:32.003574 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 00:00:32.004054
644 00:00:32.004294 Model: Libre Computer AML-A311D-CC Alta
645 00:00:32.211951 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 00:00:32.235327 DRAM: 2 GiB (effective 3.8 GiB)
647 00:00:32.378359 Core: 408 devices, 31 uclasses, devicetree: separate
648 00:00:32.384269 WDT: Not starting watchdog@f0d0
649 00:00:32.416647 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 00:00:32.428834 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 00:00:32.434007 ** Bad device specification mmc 0 **
652 00:00:32.444202 Card did not respond to voltage select! : -110
653 00:00:32.451948 ** Bad device specification mmc 0 **
654 00:00:32.452525 Couldn't find partition mmc 0
655 00:00:32.460273 Card did not respond to voltage select! : -110
656 00:00:32.465652 ** Bad device specification mmc 0 **
657 00:00:32.466176 Couldn't find partition mmc 0
658 00:00:32.470837 Error: could not access storage.
659 00:00:32.813309 Net: eth0: ethernet@ff3f0000
660 00:00:32.813957 starting USB...
661 00:00:33.065119 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 00:00:33.065788 Starting the controller
663 00:00:33.072061 USB XHCI 1.10
664 00:00:34.783785 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 00:00:34.784244 bl2_stage_init 0x01
666 00:00:34.784477 bl2_stage_init 0x81
667 00:00:34.789353 hw id: 0x0000 - pwm id 0x01
668 00:00:34.789653 bl2_stage_init 0xc1
669 00:00:34.789871 bl2_stage_init 0x02
670 00:00:34.790095
671 00:00:34.794861 L0:00000000
672 00:00:34.795157 L1:20000703
673 00:00:34.795377 L2:00008067
674 00:00:34.795595 L3:14000000
675 00:00:34.800570 B2:00402000
676 00:00:34.800991 B1:e0f83180
677 00:00:34.801332
678 00:00:34.801575 TE: 58124
679 00:00:34.801790
680 00:00:34.806030 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 00:00:34.806447
682 00:00:34.806792 Board ID = 1
683 00:00:34.811712 Set A53 clk to 24M
684 00:00:34.812021 Set A73 clk to 24M
685 00:00:34.812255 Set clk81 to 24M
686 00:00:34.817490 A53 clk: 1200 MHz
687 00:00:34.818170 A73 clk: 1200 MHz
688 00:00:34.818748 CLK81: 166.6M
689 00:00:34.819291 smccc: 00012a92
690 00:00:34.822938 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 00:00:34.828546 board id: 1
692 00:00:34.834636 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 00:00:34.844962 fw parse done
694 00:00:34.850924 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 00:00:34.893675 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 00:00:34.904538 PIEI prepare done
697 00:00:34.905285 fastboot data load
698 00:00:34.905872 fastboot data verify
699 00:00:34.910080 verify result: 266
700 00:00:34.915755 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 00:00:34.916537 LPDDR4 probe
702 00:00:34.917126 ddr clk to 1584MHz
703 00:00:34.923773 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 00:00:34.961038
705 00:00:34.961660 dmc_version 0001
706 00:00:34.967801 Check phy result
707 00:00:34.973566 INFO : End of CA training
708 00:00:34.974003 INFO : End of initialization
709 00:00:34.979216 INFO : Training has run successfully!
710 00:00:34.980000 Check phy result
711 00:00:34.984721 INFO : End of initialization
712 00:00:34.985396 INFO : End of read enable training
713 00:00:34.990388 INFO : End of fine write leveling
714 00:00:34.996031 INFO : End of Write leveling coarse delay
715 00:00:34.996760 INFO : Training has run successfully!
716 00:00:34.997388 Check phy result
717 00:00:35.001545 INFO : End of initialization
718 00:00:35.002196 INFO : End of read dq deskew training
719 00:00:35.007158 INFO : End of MPR read delay center optimization
720 00:00:35.012728 INFO : End of write delay center optimization
721 00:00:35.018405 INFO : End of read delay center optimization
722 00:00:35.019139 INFO : End of max read latency training
723 00:00:35.023963 INFO : Training has run successfully!
724 00:00:35.024729 1D training succeed
725 00:00:35.033251 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 00:00:35.080899 Check phy result
727 00:00:35.081521 INFO : End of initialization
728 00:00:35.102533 INFO : End of 2D read delay Voltage center optimization
729 00:00:35.123816 INFO : End of 2D read delay Voltage center optimization
730 00:00:35.174942 INFO : End of 2D write delay Voltage center optimization
731 00:00:35.224425 INFO : End of 2D write delay Voltage center optimization
732 00:00:35.230593 INFO : Training has run successfully!
733 00:00:35.231145
734 00:00:35.231571 channel==0
735 00:00:35.235444 RxClkDly_Margin_A0==88 ps 9
736 00:00:35.236027 TxDqDly_Margin_A0==98 ps 10
737 00:00:35.238767 RxClkDly_Margin_A1==88 ps 9
738 00:00:35.239273 TxDqDly_Margin_A1==98 ps 10
739 00:00:35.244303 TrainedVREFDQ_A0==74
740 00:00:35.244835 TrainedVREFDQ_A1==74
741 00:00:35.245276 VrefDac_Margin_A0==25
742 00:00:35.249955 DeviceVref_Margin_A0==40
743 00:00:35.250666 VrefDac_Margin_A1==25
744 00:00:35.255582 DeviceVref_Margin_A1==40
745 00:00:35.256379
746 00:00:35.256938
747 00:00:35.257471 channel==1
748 00:00:35.258007 RxClkDly_Margin_A0==98 ps 10
749 00:00:35.261169 TxDqDly_Margin_A0==88 ps 9
750 00:00:35.261806 RxClkDly_Margin_A1==98 ps 10
751 00:00:35.266765 TxDqDly_Margin_A1==88 ps 9
752 00:00:35.267375 TrainedVREFDQ_A0==75
753 00:00:35.267908 TrainedVREFDQ_A1==77
754 00:00:35.272338 VrefDac_Margin_A0==22
755 00:00:35.272916 DeviceVref_Margin_A0==39
756 00:00:35.277904 VrefDac_Margin_A1==22
757 00:00:35.278497 DeviceVref_Margin_A1==37
758 00:00:35.279027
759 00:00:35.283639 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 00:00:35.284403
761 00:00:35.311477 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000018 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
762 00:00:35.317052 2D training succeed
763 00:00:35.322783 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 00:00:35.323527 auto size-- 65535DDR cs0 size: 2048MB
765 00:00:35.328344 DDR cs1 size: 2048MB
766 00:00:35.328987 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 00:00:35.333875 cs0 DataBus test pass
768 00:00:35.334466 cs1 DataBus test pass
769 00:00:35.334985 cs0 AddrBus test pass
770 00:00:35.339487 cs1 AddrBus test pass
771 00:00:35.340258
772 00:00:35.340848 100bdlr_step_size ps== 420
773 00:00:35.341394 result report
774 00:00:35.345034 boot times 0Enable ddr reg access
775 00:00:35.352675 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 00:00:35.366080 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 00:00:35.940210 0.0;M3 CHK:0;cm4_sp_mode 0
778 00:00:35.941060 MVN_1=0x00000000
779 00:00:35.945339 MVN_2=0x00000000
780 00:00:35.951079 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 00:00:35.951409 OPS=0x10
782 00:00:35.951665 ring efuse init
783 00:00:35.951883 chipver efuse init
784 00:00:35.956737 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 00:00:35.962355 [0.018960 Inits done]
786 00:00:35.962734 secure task start!
787 00:00:35.962971 high task start!
788 00:00:35.967010 low task start!
789 00:00:35.967353 run into bl31
790 00:00:35.973615 NOTICE: BL31: v1.3(release):4fc40b1
791 00:00:35.981466 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 00:00:35.981823 NOTICE: BL31: G12A normal boot!
793 00:00:36.007334 NOTICE: BL31: BL33 decompress pass
794 00:00:36.013114 ERROR: Error initializing runtime service opteed_fast
795 00:00:37.246494
796 00:00:37.247141
797 00:00:37.254329 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 00:00:37.254892
799 00:00:37.255320 Model: Libre Computer AML-A311D-CC Alta
800 00:00:37.462755 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 00:00:37.486275 DRAM: 2 GiB (effective 3.8 GiB)
802 00:00:37.629199 Core: 408 devices, 31 uclasses, devicetree: separate
803 00:00:37.635028 WDT: Not starting watchdog@f0d0
804 00:00:37.667119 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 00:00:37.679669 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 00:00:37.684669 ** Bad device specification mmc 0 **
807 00:00:37.695078 Card did not respond to voltage select! : -110
808 00:00:37.702666 ** Bad device specification mmc 0 **
809 00:00:37.703115 Couldn't find partition mmc 0
810 00:00:37.710928 Card did not respond to voltage select! : -110
811 00:00:37.716361 ** Bad device specification mmc 0 **
812 00:00:37.716807 Couldn't find partition mmc 0
813 00:00:37.721445 Error: could not access storage.
814 00:00:38.064205 Net: eth0: ethernet@ff3f0000
815 00:00:38.064662 starting USB...
816 00:00:38.315919 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 00:00:38.316592 Starting the controller
818 00:00:38.322751 USB XHCI 1.10
819 00:00:40.483775 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 00:00:40.484461 bl2_stage_init 0x01
821 00:00:40.484885 bl2_stage_init 0x81
822 00:00:40.489344 hw id: 0x0000 - pwm id 0x01
823 00:00:40.489805 bl2_stage_init 0xc1
824 00:00:40.490216 bl2_stage_init 0x02
825 00:00:40.490618
826 00:00:40.494888 L0:00000000
827 00:00:40.495344 L1:20000703
828 00:00:40.495747 L2:00008067
829 00:00:40.496192 L3:14000000
830 00:00:40.497919 B2:00402000
831 00:00:40.498361 B1:e0f83180
832 00:00:40.498761
833 00:00:40.499161 TE: 58159
834 00:00:40.499566
835 00:00:40.509043 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 00:00:40.509558
837 00:00:40.509969 Board ID = 1
838 00:00:40.510368 Set A53 clk to 24M
839 00:00:40.510765 Set A73 clk to 24M
840 00:00:40.514643 Set clk81 to 24M
841 00:00:40.515104 A53 clk: 1200 MHz
842 00:00:40.515507 A73 clk: 1200 MHz
843 00:00:40.518088 CLK81: 166.6M
844 00:00:40.518530 smccc: 00012ab5
845 00:00:40.523640 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 00:00:40.529227 board id: 1
847 00:00:40.534417 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 00:00:40.545034 fw parse done
849 00:00:40.550952 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 00:00:40.593423 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 00:00:40.604433 PIEI prepare done
852 00:00:40.604952 fastboot data load
853 00:00:40.605393 fastboot data verify
854 00:00:40.610039 verify result: 266
855 00:00:40.615610 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 00:00:40.616139 LPDDR4 probe
857 00:00:40.616563 ddr clk to 1584MHz
858 00:00:40.623618 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 00:00:40.660926
860 00:00:40.661503 dmc_version 0001
861 00:00:40.667522 Check phy result
862 00:00:40.673426 INFO : End of CA training
863 00:00:40.673919 INFO : End of initialization
864 00:00:40.678978 INFO : Training has run successfully!
865 00:00:40.679425 Check phy result
866 00:00:40.684639 INFO : End of initialization
867 00:00:40.685140 INFO : End of read enable training
868 00:00:40.690205 INFO : End of fine write leveling
869 00:00:40.695809 INFO : End of Write leveling coarse delay
870 00:00:40.696328 INFO : Training has run successfully!
871 00:00:40.696777 Check phy result
872 00:00:40.701435 INFO : End of initialization
873 00:00:40.701912 INFO : End of read dq deskew training
874 00:00:40.706967 INFO : End of MPR read delay center optimization
875 00:00:40.712577 INFO : End of write delay center optimization
876 00:00:40.718202 INFO : End of read delay center optimization
877 00:00:40.718685 INFO : End of max read latency training
878 00:00:40.723813 INFO : Training has run successfully!
879 00:00:40.724354 1D training succeed
880 00:00:40.733135 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 00:00:40.780688 Check phy result
882 00:00:40.781252 INFO : End of initialization
883 00:00:40.803155 INFO : End of 2D read delay Voltage center optimization
884 00:00:40.823461 INFO : End of 2D read delay Voltage center optimization
885 00:00:40.875555 INFO : End of 2D write delay Voltage center optimization
886 00:00:40.924845 INFO : End of 2D write delay Voltage center optimization
887 00:00:40.930330 INFO : Training has run successfully!
888 00:00:40.930813
889 00:00:40.931251 channel==0
890 00:00:40.935935 RxClkDly_Margin_A0==88 ps 9
891 00:00:40.936447 TxDqDly_Margin_A0==108 ps 11
892 00:00:40.941510 RxClkDly_Margin_A1==88 ps 9
893 00:00:40.941960 TxDqDly_Margin_A1==98 ps 10
894 00:00:40.942387 TrainedVREFDQ_A0==74
895 00:00:40.947145 TrainedVREFDQ_A1==74
896 00:00:40.947626 VrefDac_Margin_A0==24
897 00:00:40.952741 DeviceVref_Margin_A0==40
898 00:00:40.953231 VrefDac_Margin_A1==24
899 00:00:40.953624 DeviceVref_Margin_A1==40
900 00:00:40.954012
901 00:00:40.954402
902 00:00:40.958346 channel==1
903 00:00:40.958786 RxClkDly_Margin_A0==98 ps 10
904 00:00:40.959176 TxDqDly_Margin_A0==98 ps 10
905 00:00:40.963947 RxClkDly_Margin_A1==98 ps 10
906 00:00:40.964407 TxDqDly_Margin_A1==88 ps 9
907 00:00:40.969522 TrainedVREFDQ_A0==77
908 00:00:40.969953 TrainedVREFDQ_A1==77
909 00:00:40.970346 VrefDac_Margin_A0==22
910 00:00:40.975135 DeviceVref_Margin_A0==37
911 00:00:40.975559 VrefDac_Margin_A1==22
912 00:00:40.980731 DeviceVref_Margin_A1==37
913 00:00:40.981150
914 00:00:40.981540 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 00:00:40.986313
916 00:00:41.014348 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000017 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
917 00:00:41.014908 2D training succeed
918 00:00:41.019916 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 00:00:41.025539 auto size-- 65535DDR cs0 size: 2048MB
920 00:00:41.025986 DDR cs1 size: 2048MB
921 00:00:41.031161 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 00:00:41.031590 cs0 DataBus test pass
923 00:00:41.036803 cs1 DataBus test pass
924 00:00:41.037235 cs0 AddrBus test pass
925 00:00:41.037622 cs1 AddrBus test pass
926 00:00:41.038006
927 00:00:41.042327 100bdlr_step_size ps== 426
928 00:00:41.042767 result report
929 00:00:41.047918 boot times 0Enable ddr reg access
930 00:00:41.053565 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 00:00:41.066921 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 00:00:41.640709 0.0;M3 CHK:0;cm4_sp_mode 0
933 00:00:41.641352 MVN_1=0x00000000
934 00:00:41.646038 MVN_2=0x00000000
935 00:00:41.651806 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 00:00:41.652291 OPS=0x10
937 00:00:41.652706 ring efuse init
938 00:00:41.653107 chipver efuse init
939 00:00:41.660036 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 00:00:41.660493 [0.018961 Inits done]
941 00:00:41.667616 secure task start!
942 00:00:41.668111 high task start!
943 00:00:41.668526 low task start!
944 00:00:41.668925 run into bl31
945 00:00:41.674252 NOTICE: BL31: v1.3(release):4fc40b1
946 00:00:41.682076 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 00:00:41.682519 NOTICE: BL31: G12A normal boot!
948 00:00:41.707519 NOTICE: BL31: BL33 decompress pass
949 00:00:41.713201 ERROR: Error initializing runtime service opteed_fast
950 00:00:42.946092
951 00:00:42.946746
952 00:00:42.954503 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 00:00:42.955013
954 00:00:42.955470 Model: Libre Computer AML-A311D-CC Alta
955 00:00:43.163037 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 00:00:43.186391 DRAM: 2 GiB (effective 3.8 GiB)
957 00:00:43.329326 Core: 408 devices, 31 uclasses, devicetree: separate
958 00:00:43.335209 WDT: Not starting watchdog@f0d0
959 00:00:43.367494 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 00:00:43.380015 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 00:00:43.384819 ** Bad device specification mmc 0 **
962 00:00:43.395261 Card did not respond to voltage select! : -110
963 00:00:43.402900 ** Bad device specification mmc 0 **
964 00:00:43.403456 Couldn't find partition mmc 0
965 00:00:43.411367 Card did not respond to voltage select! : -110
966 00:00:43.416868 ** Bad device specification mmc 0 **
967 00:00:43.417426 Couldn't find partition mmc 0
968 00:00:43.421844 Error: could not access storage.
969 00:00:43.764240 Net: eth0: ethernet@ff3f0000
970 00:00:43.764675 starting USB...
971 00:00:44.016131 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 00:00:44.016572 Starting the controller
973 00:00:44.023071 USB XHCI 1.10
974 00:00:45.883717 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 00:00:45.884424 bl2_stage_init 0x01
976 00:00:45.884902 bl2_stage_init 0x81
977 00:00:45.889469 hw id: 0x0000 - pwm id 0x01
978 00:00:45.890006 bl2_stage_init 0xc1
979 00:00:45.890464 bl2_stage_init 0x02
980 00:00:45.890910
981 00:00:45.894994 L0:00000000
982 00:00:45.895544 L1:20000703
983 00:00:45.896041 L2:00008067
984 00:00:45.896494 L3:14000000
985 00:00:45.897870 B2:00402000
986 00:00:45.898379 B1:e0f83180
987 00:00:45.898833
988 00:00:45.899283 TE: 58124
989 00:00:45.899728
990 00:00:45.908943 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 00:00:45.909500
992 00:00:45.909961 Board ID = 1
993 00:00:45.910401 Set A53 clk to 24M
994 00:00:45.910836 Set A73 clk to 24M
995 00:00:45.914588 Set clk81 to 24M
996 00:00:45.915104 A53 clk: 1200 MHz
997 00:00:45.915559 A73 clk: 1200 MHz
998 00:00:45.918124 CLK81: 166.6M
999 00:00:45.918639 smccc: 00012a92
1000 00:00:45.923661 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 00:00:45.929237 board id: 1
1002 00:00:45.935026 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 00:00:45.945016 fw parse done
1004 00:00:45.951077 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 00:00:45.992811 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 00:00:46.004561 PIEI prepare done
1007 00:00:46.005075 fastboot data load
1008 00:00:46.005515 fastboot data verify
1009 00:00:46.010146 verify result: 266
1010 00:00:46.015780 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 00:00:46.016375 LPDDR4 probe
1012 00:00:46.016826 ddr clk to 1584MHz
1013 00:00:46.023759 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 00:00:46.061003
1015 00:00:46.061599 dmc_version 0001
1016 00:00:46.067652 Check phy result
1017 00:00:46.073534 INFO : End of CA training
1018 00:00:46.074057 INFO : End of initialization
1019 00:00:46.079185 INFO : Training has run successfully!
1020 00:00:46.079731 Check phy result
1021 00:00:46.084748 INFO : End of initialization
1022 00:00:46.085323 INFO : End of read enable training
1023 00:00:46.090321 INFO : End of fine write leveling
1024 00:00:46.095973 INFO : End of Write leveling coarse delay
1025 00:00:46.096564 INFO : Training has run successfully!
1026 00:00:46.097052 Check phy result
1027 00:00:46.101585 INFO : End of initialization
1028 00:00:46.102159 INFO : End of read dq deskew training
1029 00:00:46.107181 INFO : End of MPR read delay center optimization
1030 00:00:46.112731 INFO : End of write delay center optimization
1031 00:00:46.118347 INFO : End of read delay center optimization
1032 00:00:46.118916 INFO : End of max read latency training
1033 00:00:46.123970 INFO : Training has run successfully!
1034 00:00:46.124608 1D training succeed
1035 00:00:46.133129 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 00:00:46.180807 Check phy result
1037 00:00:46.181449 INFO : End of initialization
1038 00:00:46.203280 INFO : End of 2D read delay Voltage center optimization
1039 00:00:46.223407 INFO : End of 2D read delay Voltage center optimization
1040 00:00:46.275257 INFO : End of 2D write delay Voltage center optimization
1041 00:00:46.324620 INFO : End of 2D write delay Voltage center optimization
1042 00:00:46.330142 INFO : Training has run successfully!
1043 00:00:46.330709
1044 00:00:46.331177 channel==0
1045 00:00:46.335671 RxClkDly_Margin_A0==88 ps 9
1046 00:00:46.336272 TxDqDly_Margin_A0==98 ps 10
1047 00:00:46.339090 RxClkDly_Margin_A1==88 ps 9
1048 00:00:46.339626 TxDqDly_Margin_A1==88 ps 9
1049 00:00:46.344650 TrainedVREFDQ_A0==74
1050 00:00:46.345205 TrainedVREFDQ_A1==74
1051 00:00:46.345663 VrefDac_Margin_A0==24
1052 00:00:46.350191 DeviceVref_Margin_A0==40
1053 00:00:46.350735 VrefDac_Margin_A1==24
1054 00:00:46.355813 DeviceVref_Margin_A1==40
1055 00:00:46.356450
1056 00:00:46.356942
1057 00:00:46.357394 channel==1
1058 00:00:46.357838 RxClkDly_Margin_A0==98 ps 10
1059 00:00:46.361580 TxDqDly_Margin_A0==98 ps 10
1060 00:00:46.362136 RxClkDly_Margin_A1==98 ps 10
1061 00:00:46.367045 TxDqDly_Margin_A1==88 ps 9
1062 00:00:46.367626 TrainedVREFDQ_A0==77
1063 00:00:46.368151 TrainedVREFDQ_A1==77
1064 00:00:46.372668 VrefDac_Margin_A0==22
1065 00:00:46.373252 DeviceVref_Margin_A0==37
1066 00:00:46.378282 VrefDac_Margin_A1==22
1067 00:00:46.378884 DeviceVref_Margin_A1==37
1068 00:00:46.379354
1069 00:00:46.383790 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 00:00:46.384437
1071 00:00:46.411929 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 00:00:46.417553 2D training succeed
1073 00:00:46.422872 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 00:00:46.423439 auto size-- 65535DDR cs0 size: 2048MB
1075 00:00:46.428478 DDR cs1 size: 2048MB
1076 00:00:46.429038 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 00:00:46.434088 cs0 DataBus test pass
1078 00:00:46.434638 cs1 DataBus test pass
1079 00:00:46.435095 cs0 AddrBus test pass
1080 00:00:46.439660 cs1 AddrBus test pass
1081 00:00:46.440257
1082 00:00:46.440725 100bdlr_step_size ps== 420
1083 00:00:46.441185 result report
1084 00:00:46.445325 boot times 0Enable ddr reg access
1085 00:00:46.452911 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 00:00:46.466328 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 00:00:47.038321 0.0;M3 CHK:0;cm4_sp_mode 0
1088 00:00:47.039003 MVN_1=0x00000000
1089 00:00:47.043910 MVN_2=0x00000000
1090 00:00:47.049669 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 00:00:47.050229 OPS=0x10
1092 00:00:47.050697 ring efuse init
1093 00:00:47.051154 chipver efuse init
1094 00:00:47.057756 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 00:00:47.058355 [0.018961 Inits done]
1096 00:00:47.064487 secure task start!
1097 00:00:47.065022 high task start!
1098 00:00:47.065482 low task start!
1099 00:00:47.065938 run into bl31
1100 00:00:47.072036 NOTICE: BL31: v1.3(release):4fc40b1
1101 00:00:47.079811 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 00:00:47.080385 NOTICE: BL31: G12A normal boot!
1103 00:00:47.105238 NOTICE: BL31: BL33 decompress pass
1104 00:00:47.110875 ERROR: Error initializing runtime service opteed_fast
1105 00:00:48.343654
1106 00:00:48.344115
1107 00:00:48.352169 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 00:00:48.352696
1109 00:00:48.353129 Model: Libre Computer AML-A311D-CC Alta
1110 00:00:48.560611 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 00:00:48.583916 DRAM: 2 GiB (effective 3.8 GiB)
1112 00:00:48.727007 Core: 408 devices, 31 uclasses, devicetree: separate
1113 00:00:48.732798 WDT: Not starting watchdog@f0d0
1114 00:00:48.765064 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 00:00:48.777498 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 00:00:48.782485 ** Bad device specification mmc 0 **
1117 00:00:48.792834 Card did not respond to voltage select! : -110
1118 00:00:48.800621 ** Bad device specification mmc 0 **
1119 00:00:48.801259 Couldn't find partition mmc 0
1120 00:00:48.808783 Card did not respond to voltage select! : -110
1121 00:00:48.814328 ** Bad device specification mmc 0 **
1122 00:00:48.814896 Couldn't find partition mmc 0
1123 00:00:48.819386 Error: could not access storage.
1124 00:00:49.161899 Net: eth0: ethernet@ff3f0000
1125 00:00:49.162518 starting USB...
1126 00:00:49.413698 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 00:00:49.414275 Starting the controller
1128 00:00:49.420586 USB XHCI 1.10
1129 00:00:50.977978 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 00:00:50.986161 scanning usb for storage devices... 0 Storage Device(s) found
1132 00:00:51.037279 Hit any key to stop autoboot: 1
1133 00:00:51.037959 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 00:00:51.038324 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 00:00:51.038897 Setting prompt string to ['=>']
1136 00:00:51.039475 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 00:00:51.053737 0
1138 00:00:51.054473 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 00:00:51.054752 Sending with 10 millisecond of delay
1141 00:00:52.200093 => setenv autoload no
1142 00:00:52.210921 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 00:00:52.213776 setenv autoload no
1144 00:00:52.214492 Sending with 10 millisecond of delay
1146 00:00:54.011780 => setenv initrd_high 0xffffffff
1147 00:00:54.022640 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 00:00:54.023646 setenv initrd_high 0xffffffff
1149 00:00:54.024459 Sending with 10 millisecond of delay
1151 00:00:55.641902 => setenv fdt_high 0xffffffff
1152 00:00:55.652712 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 00:00:55.653572 setenv fdt_high 0xffffffff
1154 00:00:55.654247 Sending with 10 millisecond of delay
1156 00:00:55.945939 => dhcp
1157 00:00:55.956721 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 00:00:55.957570 dhcp
1159 00:00:55.958014 Speed: 1000, full duplex
1160 00:00:55.958431 BOOTP broadcast 1
1161 00:00:56.169749 DHCP client bound to address 192.168.6.27 (213 ms)
1162 00:00:56.170399 Sending with 10 millisecond of delay
1164 00:00:57.847145 => setenv serverip 192.168.6.2
1165 00:00:57.857924 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 00:00:57.858547 setenv serverip 192.168.6.2
1167 00:00:57.859028 Sending with 10 millisecond of delay
1169 00:01:01.583419 => tftpboot 0x01080000 955849/tftp-deploy-2nxhdpr_/kernel/uImage
1170 00:01:01.594018 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 00:01:01.594593 tftpboot 0x01080000 955849/tftp-deploy-2nxhdpr_/kernel/uImage
1172 00:01:01.594818 Speed: 1000, full duplex
1173 00:01:01.595020 Using ethernet@ff3f0000 device
1174 00:01:01.596467 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 00:01:01.602025 Filename '955849/tftp-deploy-2nxhdpr_/kernel/uImage'.
1176 00:01:01.605854 Load address: 0x1080000
1177 00:01:04.666283 Loading: *################################################## 43.6 MiB
1178 00:01:04.666718 14.2 MiB/s
1179 00:01:04.666944 done
1180 00:01:04.670718 Bytes transferred = 45713984 (2b98a40 hex)
1181 00:01:04.671241 Sending with 10 millisecond of delay
1183 00:01:09.360548 => tftpboot 0x08000000 955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot
1184 00:01:09.371955 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 00:01:09.372626 tftpboot 0x08000000 955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot
1186 00:01:09.372909 Speed: 1000, full duplex
1187 00:01:09.373144 Using ethernet@ff3f0000 device
1188 00:01:09.373845 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 00:01:09.385639 Filename '955849/tftp-deploy-2nxhdpr_/ramdisk/ramdisk.cpio.gz.uboot'.
1190 00:01:09.386205 Load address: 0x8000000
1191 00:01:15.955815 Loading: *##############T ################################### UDP wrong checksum 00000005 0000cb14
1192 00:01:20.956684 T UDP wrong checksum 00000005 0000cb14
1193 00:01:24.897018 UDP wrong checksum 000000ff 0000cd93
1194 00:01:24.953131 UDP wrong checksum 000000ff 00005286
1195 00:01:30.958941 T T UDP wrong checksum 00000005 0000cb14
1196 00:01:50.960972 T T T UDP wrong checksum 00000005 0000cb14
1197 00:02:05.967729 T T T
1198 00:02:05.968167 Retry count exceeded; starting again
1200 00:02:05.970547 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1203 00:02:05.972924 end: 2.4 uboot-commands (duration 00:01:52) [common]
1205 00:02:05.974547 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 00:02:05.976144 end: 2 uboot-action (duration 00:01:52) [common]
1209 00:02:05.977880 Cleaning after the job
1210 00:02:05.978487 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/ramdisk
1211 00:02:05.979935 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/kernel
1212 00:02:06.026986 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/dtb
1213 00:02:06.027899 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/nfsrootfs
1214 00:02:06.199005 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955849/tftp-deploy-2nxhdpr_/modules
1215 00:02:06.220379 start: 4.1 power-off (timeout 00:00:30) [common]
1216 00:02:06.221075 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 00:02:06.254016 >> OK - accepted request
1218 00:02:06.256087 Returned 0 in 0 seconds
1219 00:02:06.357033 end: 4.1 power-off (duration 00:00:00) [common]
1221 00:02:06.358332 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 00:02:06.358996 Listened to connection for namespace 'common' for up to 1s
1223 00:02:07.359936 Finalising connection for namespace 'common'
1224 00:02:07.360502 Disconnecting from shell: Finalise
1225 00:02:07.360786 =>
1226 00:02:07.461507 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 00:02:07.461996 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955849
1228 00:02:10.682131 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955849
1229 00:02:10.682741 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.