Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:13:16.249842 lava-dispatcher, installed at version: 2024.01
2 00:13:16.250580 start: 0 validate
3 00:13:16.251056 Start time: 2024-11-08 00:13:16.251027+00:00 (UTC)
4 00:13:16.251584 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:13:16.252154 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 00:13:16.289399 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:13:16.290065 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:13:16.318435 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:13:16.319062 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:13:16.350259 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:13:16.350728 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 00:13:16.377803 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 00:13:16.378289 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc5-63-g2e9baed573ee%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 00:13:16.416935 validate duration: 0.17
16 00:13:16.417788 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 00:13:16.418111 start: 1.1 download-retry (timeout 00:10:00) [common]
18 00:13:16.418418 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 00:13:16.418976 Not decompressing ramdisk as can be used compressed.
20 00:13:16.419375 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 00:13:16.419648 saving as /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/ramdisk/initrd.cpio.gz
22 00:13:16.419907 total size: 5628140 (5 MB)
23 00:13:16.459655 progress 0 % (0 MB)
24 00:13:16.463837 progress 5 % (0 MB)
25 00:13:16.468275 progress 10 % (0 MB)
26 00:13:16.472050 progress 15 % (0 MB)
27 00:13:16.476191 progress 20 % (1 MB)
28 00:13:16.479841 progress 25 % (1 MB)
29 00:13:16.484088 progress 30 % (1 MB)
30 00:13:16.488184 progress 35 % (1 MB)
31 00:13:16.491791 progress 40 % (2 MB)
32 00:13:16.495892 progress 45 % (2 MB)
33 00:13:16.499531 progress 50 % (2 MB)
34 00:13:16.503608 progress 55 % (2 MB)
35 00:13:16.507684 progress 60 % (3 MB)
36 00:13:16.511319 progress 65 % (3 MB)
37 00:13:16.515320 progress 70 % (3 MB)
38 00:13:16.518940 progress 75 % (4 MB)
39 00:13:16.523011 progress 80 % (4 MB)
40 00:13:16.526647 progress 85 % (4 MB)
41 00:13:16.530800 progress 90 % (4 MB)
42 00:13:16.534717 progress 95 % (5 MB)
43 00:13:16.538075 progress 100 % (5 MB)
44 00:13:16.538753 5 MB downloaded in 0.12 s (45.17 MB/s)
45 00:13:16.539305 end: 1.1.1 http-download (duration 00:00:00) [common]
47 00:13:16.540232 end: 1.1 download-retry (duration 00:00:00) [common]
48 00:13:16.540547 start: 1.2 download-retry (timeout 00:10:00) [common]
49 00:13:16.540823 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 00:13:16.541427 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/kernel/Image
51 00:13:16.541729 saving as /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/kernel/Image
52 00:13:16.541943 total size: 45713920 (43 MB)
53 00:13:16.542159 No compression specified
54 00:13:16.578121 progress 0 % (0 MB)
55 00:13:16.606291 progress 5 % (2 MB)
56 00:13:16.634078 progress 10 % (4 MB)
57 00:13:16.661893 progress 15 % (6 MB)
58 00:13:16.689513 progress 20 % (8 MB)
59 00:13:16.716935 progress 25 % (10 MB)
60 00:13:16.745970 progress 30 % (13 MB)
61 00:13:16.774073 progress 35 % (15 MB)
62 00:13:16.801778 progress 40 % (17 MB)
63 00:13:16.829703 progress 45 % (19 MB)
64 00:13:16.857371 progress 50 % (21 MB)
65 00:13:16.885904 progress 55 % (24 MB)
66 00:13:16.913652 progress 60 % (26 MB)
67 00:13:16.940933 progress 65 % (28 MB)
68 00:13:16.968505 progress 70 % (30 MB)
69 00:13:16.996270 progress 75 % (32 MB)
70 00:13:17.024712 progress 80 % (34 MB)
71 00:13:17.053368 progress 85 % (37 MB)
72 00:13:17.081054 progress 90 % (39 MB)
73 00:13:17.108612 progress 95 % (41 MB)
74 00:13:17.135896 progress 100 % (43 MB)
75 00:13:17.136446 43 MB downloaded in 0.59 s (73.33 MB/s)
76 00:13:17.137014 end: 1.2.1 http-download (duration 00:00:01) [common]
78 00:13:17.137854 end: 1.2 download-retry (duration 00:00:01) [common]
79 00:13:17.138132 start: 1.3 download-retry (timeout 00:09:59) [common]
80 00:13:17.138403 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 00:13:17.138859 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 00:13:17.139135 saving as /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/dtb/meson-g12b-a311d-libretech-cc.dtb
83 00:13:17.139347 total size: 54703 (0 MB)
84 00:13:17.139558 No compression specified
85 00:13:17.173161 progress 59 % (0 MB)
86 00:13:17.174067 progress 100 % (0 MB)
87 00:13:17.174658 0 MB downloaded in 0.04 s (1.48 MB/s)
88 00:13:17.175148 end: 1.3.1 http-download (duration 00:00:00) [common]
90 00:13:17.176234 end: 1.3 download-retry (duration 00:00:00) [common]
91 00:13:17.176529 start: 1.4 download-retry (timeout 00:09:59) [common]
92 00:13:17.176799 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 00:13:17.177270 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 00:13:17.177520 saving as /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/nfsrootfs/full.rootfs.tar
95 00:13:17.177730 total size: 474398908 (452 MB)
96 00:13:17.177940 Using unxz to decompress xz
97 00:13:17.215958 progress 0 % (0 MB)
98 00:13:18.324476 progress 5 % (22 MB)
99 00:13:19.804415 progress 10 % (45 MB)
100 00:13:20.279970 progress 15 % (67 MB)
101 00:13:21.090284 progress 20 % (90 MB)
102 00:13:21.644113 progress 25 % (113 MB)
103 00:13:21.999065 progress 30 % (135 MB)
104 00:13:22.615515 progress 35 % (158 MB)
105 00:13:23.503029 progress 40 % (181 MB)
106 00:13:24.325524 progress 45 % (203 MB)
107 00:13:24.892729 progress 50 % (226 MB)
108 00:13:25.523954 progress 55 % (248 MB)
109 00:13:26.711045 progress 60 % (271 MB)
110 00:13:28.117624 progress 65 % (294 MB)
111 00:13:29.746632 progress 70 % (316 MB)
112 00:13:32.924828 progress 75 % (339 MB)
113 00:13:35.376907 progress 80 % (361 MB)
114 00:13:38.293981 progress 85 % (384 MB)
115 00:13:41.482804 progress 90 % (407 MB)
116 00:13:44.701987 progress 95 % (429 MB)
117 00:13:47.891541 progress 100 % (452 MB)
118 00:13:47.904342 452 MB downloaded in 30.73 s (14.72 MB/s)
119 00:13:47.905292 end: 1.4.1 http-download (duration 00:00:31) [common]
121 00:13:47.907051 end: 1.4 download-retry (duration 00:00:31) [common]
122 00:13:47.907620 start: 1.5 download-retry (timeout 00:09:29) [common]
123 00:13:47.908234 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 00:13:47.909203 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc5-63-g2e9baed573ee/arm64/defconfig/gcc-12/modules.tar.xz
125 00:13:47.909717 saving as /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/modules/modules.tar
126 00:13:47.910165 total size: 11603932 (11 MB)
127 00:13:47.910626 Using unxz to decompress xz
128 00:13:47.954824 progress 0 % (0 MB)
129 00:13:48.030000 progress 5 % (0 MB)
130 00:13:48.103536 progress 10 % (1 MB)
131 00:13:48.198797 progress 15 % (1 MB)
132 00:13:48.290960 progress 20 % (2 MB)
133 00:13:48.369380 progress 25 % (2 MB)
134 00:13:48.444662 progress 30 % (3 MB)
135 00:13:48.518279 progress 35 % (3 MB)
136 00:13:48.595300 progress 40 % (4 MB)
137 00:13:48.670906 progress 45 % (5 MB)
138 00:13:48.754017 progress 50 % (5 MB)
139 00:13:48.830223 progress 55 % (6 MB)
140 00:13:48.916158 progress 60 % (6 MB)
141 00:13:48.998133 progress 65 % (7 MB)
142 00:13:49.075514 progress 70 % (7 MB)
143 00:13:49.160256 progress 75 % (8 MB)
144 00:13:49.242218 progress 80 % (8 MB)
145 00:13:49.332751 progress 85 % (9 MB)
146 00:13:49.414446 progress 90 % (9 MB)
147 00:13:49.491339 progress 95 % (10 MB)
148 00:13:49.567916 progress 100 % (11 MB)
149 00:13:49.578399 11 MB downloaded in 1.67 s (6.63 MB/s)
150 00:13:49.579271 end: 1.5.1 http-download (duration 00:00:02) [common]
152 00:13:49.580927 end: 1.5 download-retry (duration 00:00:02) [common]
153 00:13:49.581457 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 00:13:49.581979 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 00:14:05.140300 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/955859/extract-nfsrootfs-o70g0eci
156 00:14:05.140937 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 00:14:05.141261 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 00:14:05.141956 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj
159 00:14:05.142867 makedir: /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin
160 00:14:05.143270 makedir: /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/tests
161 00:14:05.143640 makedir: /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/results
162 00:14:05.144032 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-add-keys
163 00:14:05.144675 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-add-sources
164 00:14:05.145308 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-background-process-start
165 00:14:05.145897 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-background-process-stop
166 00:14:05.146541 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-common-functions
167 00:14:05.147155 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-echo-ipv4
168 00:14:05.147721 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-install-packages
169 00:14:05.148298 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-installed-packages
170 00:14:05.148881 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-os-build
171 00:14:05.149472 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-probe-channel
172 00:14:05.150012 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-probe-ip
173 00:14:05.150526 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-target-ip
174 00:14:05.151015 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-target-mac
175 00:14:05.151496 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-target-storage
176 00:14:05.152057 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-case
177 00:14:05.152642 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-event
178 00:14:05.153282 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-feedback
179 00:14:05.153819 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-raise
180 00:14:05.154371 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-reference
181 00:14:05.154906 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-runner
182 00:14:05.155480 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-set
183 00:14:05.156143 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-test-shell
184 00:14:05.156770 Updating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-install-packages (oe)
185 00:14:05.157362 Updating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/bin/lava-installed-packages (oe)
186 00:14:05.157849 Creating /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/environment
187 00:14:05.158302 LAVA metadata
188 00:14:05.158624 - LAVA_JOB_ID=955859
189 00:14:05.158871 - LAVA_DISPATCHER_IP=192.168.6.2
190 00:14:05.159288 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 00:14:05.160412 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 00:14:05.160764 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 00:14:05.160989 skipped lava-vland-overlay
194 00:14:05.161311 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 00:14:05.161661 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 00:14:05.161923 skipped lava-multinode-overlay
197 00:14:05.162196 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 00:14:05.162457 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 00:14:05.162726 Loading test definitions
200 00:14:05.163029 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 00:14:05.163255 Using /lava-955859 at stage 0
202 00:14:05.164590 uuid=955859_1.6.2.4.1 testdef=None
203 00:14:05.164967 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 00:14:05.165278 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 00:14:05.167233 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 00:14:05.168159 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 00:14:05.170770 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 00:14:05.171703 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 00:14:05.174203 runner path: /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 955859_1.6.2.4.1
212 00:14:05.174943 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 00:14:05.175789 Creating lava-test-runner.conf files
215 00:14:05.176102 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955859/lava-overlay-pdu6y5uj/lava-955859/0 for stage 0
216 00:14:05.176511 - 0_v4l2-decoder-conformance-h264
217 00:14:05.176905 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 00:14:05.177207 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 00:14:05.201694 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 00:14:05.202144 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 00:14:05.202411 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 00:14:05.202683 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 00:14:05.202949 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 00:14:05.902223 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 00:14:05.902739 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 00:14:05.903002 extracting modules file /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955859/extract-nfsrootfs-o70g0eci
227 00:14:07.327700 extracting modules file /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955859/extract-overlay-ramdisk-5hyenmdl/ramdisk
228 00:14:08.733259 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 00:14:08.733741 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 00:14:08.734041 [common] Applying overlay to NFS
231 00:14:08.734273 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955859/compress-overlay-6b9op9zq/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955859/extract-nfsrootfs-o70g0eci
232 00:14:08.763260 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 00:14:08.763628 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 00:14:08.763926 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 00:14:08.764201 Converting downloaded kernel to a uImage
236 00:14:08.764523 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/kernel/Image /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/kernel/uImage
237 00:14:09.244912 output: Image Name:
238 00:14:09.245339 output: Created: Fri Nov 8 00:14:08 2024
239 00:14:09.245550 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 00:14:09.245755 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 00:14:09.245957 output: Load Address: 01080000
242 00:14:09.246158 output: Entry Point: 01080000
243 00:14:09.246355 output:
244 00:14:09.246697 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 00:14:09.246969 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 00:14:09.247240 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 00:14:09.247496 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 00:14:09.247757 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 00:14:09.248057 Building ramdisk /var/lib/lava/dispatcher/tmp/955859/extract-overlay-ramdisk-5hyenmdl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955859/extract-overlay-ramdisk-5hyenmdl/ramdisk
250 00:14:11.400123 >> 166774 blocks
251 00:14:19.533231 Adding RAMdisk u-boot header.
252 00:14:19.533691 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955859/extract-overlay-ramdisk-5hyenmdl/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955859/extract-overlay-ramdisk-5hyenmdl/ramdisk.cpio.gz.uboot
253 00:14:19.789716 output: Image Name:
254 00:14:19.790331 output: Created: Fri Nov 8 00:14:19 2024
255 00:14:19.790840 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 00:14:19.791312 output: Data Size: 23429477 Bytes = 22880.35 KiB = 22.34 MiB
257 00:14:19.791772 output: Load Address: 00000000
258 00:14:19.792374 output: Entry Point: 00000000
259 00:14:19.792896 output:
260 00:14:19.794097 rename /var/lib/lava/dispatcher/tmp/955859/extract-overlay-ramdisk-5hyenmdl/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot
261 00:14:19.795024 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 00:14:19.795700 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 00:14:19.796341 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 00:14:19.796862 No LXC device requested
265 00:14:19.797416 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 00:14:19.797981 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 00:14:19.798534 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 00:14:19.799077 Checking files for TFTP limit of 4294967296 bytes.
269 00:14:19.802539 end: 1 tftp-deploy (duration 00:01:03) [common]
270 00:14:19.803308 start: 2 uboot-action (timeout 00:05:00) [common]
271 00:14:19.803957 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 00:14:19.804686 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 00:14:19.805259 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 00:14:19.805845 Using kernel file from prepare-kernel: 955859/tftp-deploy-019ra8hq/kernel/uImage
275 00:14:19.806543 substitutions:
276 00:14:19.807080 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 00:14:19.807584 - {DTB_ADDR}: 0x01070000
278 00:14:19.808065 - {DTB}: 955859/tftp-deploy-019ra8hq/dtb/meson-g12b-a311d-libretech-cc.dtb
279 00:14:19.808514 - {INITRD}: 955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot
280 00:14:19.808960 - {KERNEL_ADDR}: 0x01080000
281 00:14:19.809400 - {KERNEL}: 955859/tftp-deploy-019ra8hq/kernel/uImage
282 00:14:19.809839 - {LAVA_MAC}: None
283 00:14:19.810322 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/955859/extract-nfsrootfs-o70g0eci
284 00:14:19.810769 - {NFS_SERVER_IP}: 192.168.6.2
285 00:14:19.811205 - {PRESEED_CONFIG}: None
286 00:14:19.811727 - {PRESEED_LOCAL}: None
287 00:14:19.812264 - {RAMDISK_ADDR}: 0x08000000
288 00:14:19.812705 - {RAMDISK}: 955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot
289 00:14:19.813142 - {ROOT_PART}: None
290 00:14:19.813643 - {ROOT}: None
291 00:14:19.814139 - {SERVER_IP}: 192.168.6.2
292 00:14:19.814631 - {TEE_ADDR}: 0x83000000
293 00:14:19.815074 - {TEE}: None
294 00:14:19.815571 Parsed boot commands:
295 00:14:19.816021 - setenv autoload no
296 00:14:19.816459 - setenv initrd_high 0xffffffff
297 00:14:19.816893 - setenv fdt_high 0xffffffff
298 00:14:19.817322 - dhcp
299 00:14:19.817751 - setenv serverip 192.168.6.2
300 00:14:19.818243 - tftpboot 0x01080000 955859/tftp-deploy-019ra8hq/kernel/uImage
301 00:14:19.818738 - tftpboot 0x08000000 955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot
302 00:14:19.819278 - tftpboot 0x01070000 955859/tftp-deploy-019ra8hq/dtb/meson-g12b-a311d-libretech-cc.dtb
303 00:14:19.819772 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/955859/extract-nfsrootfs-o70g0eci,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 00:14:19.820327 - bootm 0x01080000 0x08000000 0x01070000
305 00:14:19.821014 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 00:14:19.822973 start: 2.3 connect-device (timeout 00:05:00) [common]
308 00:14:19.823520 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 00:14:19.838724 Setting prompt string to ['lava-test: # ']
310 00:14:19.840438 end: 2.3 connect-device (duration 00:00:00) [common]
311 00:14:19.841256 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 00:14:19.841980 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 00:14:19.842839 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 00:14:19.844344 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 00:14:19.887521 >> OK - accepted request
316 00:14:19.889757 Returned 0 in 0 seconds
317 00:14:19.991242 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 00:14:19.993230 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 00:14:19.993967 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 00:14:19.994627 Setting prompt string to ['Hit any key to stop autoboot']
322 00:14:19.995225 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 00:14:19.997266 Trying 192.168.56.21...
324 00:14:19.997924 Connected to conserv1.
325 00:14:19.998470 Escape character is '^]'.
326 00:14:19.999041
327 00:14:19.999629 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 00:14:20.000242
329 00:14:32.048320 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 00:14:32.048984 bl2_stage_init 0x01
331 00:14:32.049443 bl2_stage_init 0x81
332 00:14:32.053855 hw id: 0x0000 - pwm id 0x01
333 00:14:32.054343 bl2_stage_init 0xc1
334 00:14:32.054787 bl2_stage_init 0x02
335 00:14:32.055223
336 00:14:32.059363 L0:00000000
337 00:14:32.059829 L1:20000703
338 00:14:32.060315 L2:00008067
339 00:14:32.060752 L3:14000000
340 00:14:32.064837 B2:00402000
341 00:14:32.065303 B1:e0f83180
342 00:14:32.065736
343 00:14:32.066168 TE: 58124
344 00:14:32.066607
345 00:14:32.070506 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 00:14:32.070978
347 00:14:32.071413 Board ID = 1
348 00:14:32.076089 Set A53 clk to 24M
349 00:14:32.076553 Set A73 clk to 24M
350 00:14:32.076989 Set clk81 to 24M
351 00:14:32.081680 A53 clk: 1200 MHz
352 00:14:32.082143 A73 clk: 1200 MHz
353 00:14:32.082577 CLK81: 166.6M
354 00:14:32.083004 smccc: 00012a92
355 00:14:32.087237 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 00:14:32.092796 board id: 1
357 00:14:32.098777 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 00:14:32.109379 fw parse done
359 00:14:32.115375 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 00:14:32.158017 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 00:14:32.168836 PIEI prepare done
362 00:14:32.169303 fastboot data load
363 00:14:32.169742 fastboot data verify
364 00:14:32.174566 verify result: 266
365 00:14:32.180144 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 00:14:32.180605 LPDDR4 probe
367 00:14:32.181049 ddr clk to 1584MHz
368 00:14:32.188232 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 00:14:32.225391
370 00:14:32.225873 dmc_version 0001
371 00:14:32.232078 Check phy result
372 00:14:32.237891 INFO : End of CA training
373 00:14:32.238364 INFO : End of initialization
374 00:14:32.243489 INFO : Training has run successfully!
375 00:14:32.243961 Check phy result
376 00:14:32.249112 INFO : End of initialization
377 00:14:32.249581 INFO : End of read enable training
378 00:14:32.254733 INFO : End of fine write leveling
379 00:14:32.260271 INFO : End of Write leveling coarse delay
380 00:14:32.260733 INFO : Training has run successfully!
381 00:14:32.261178 Check phy result
382 00:14:32.265861 INFO : End of initialization
383 00:14:32.266329 INFO : End of read dq deskew training
384 00:14:32.271480 INFO : End of MPR read delay center optimization
385 00:14:32.277098 INFO : End of write delay center optimization
386 00:14:32.282814 INFO : End of read delay center optimization
387 00:14:32.283282 INFO : End of max read latency training
388 00:14:32.288272 INFO : Training has run successfully!
389 00:14:32.288742 1D training succeed
390 00:14:32.296608 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 00:14:32.344150 Check phy result
392 00:14:32.344650 INFO : End of initialization
393 00:14:32.366695 INFO : End of 2D read delay Voltage center optimization
394 00:14:32.386906 INFO : End of 2D read delay Voltage center optimization
395 00:14:32.438879 INFO : End of 2D write delay Voltage center optimization
396 00:14:32.488056 INFO : End of 2D write delay Voltage center optimization
397 00:14:32.493624 INFO : Training has run successfully!
398 00:14:32.494139
399 00:14:32.494602 channel==0
400 00:14:32.499212 RxClkDly_Margin_A0==88 ps 9
401 00:14:32.499691 TxDqDly_Margin_A0==98 ps 10
402 00:14:32.502583 RxClkDly_Margin_A1==88 ps 9
403 00:14:32.503082 TxDqDly_Margin_A1==88 ps 9
404 00:14:32.508244 TrainedVREFDQ_A0==74
405 00:14:32.508722 TrainedVREFDQ_A1==74
406 00:14:32.509175 VrefDac_Margin_A0==25
407 00:14:32.513710 DeviceVref_Margin_A0==40
408 00:14:32.514188 VrefDac_Margin_A1==25
409 00:14:32.519337 DeviceVref_Margin_A1==40
410 00:14:32.519814
411 00:14:32.520303
412 00:14:32.520750 channel==1
413 00:14:32.521188 RxClkDly_Margin_A0==88 ps 9
414 00:14:32.522789 TxDqDly_Margin_A0==98 ps 10
415 00:14:32.528338 RxClkDly_Margin_A1==98 ps 10
416 00:14:32.528816 TxDqDly_Margin_A1==88 ps 9
417 00:14:32.529264 TrainedVREFDQ_A0==77
418 00:14:32.533955 TrainedVREFDQ_A1==77
419 00:14:32.534443 VrefDac_Margin_A0==22
420 00:14:32.539457 DeviceVref_Margin_A0==37
421 00:14:32.539943 VrefDac_Margin_A1==22
422 00:14:32.540426 DeviceVref_Margin_A1==37
423 00:14:32.540868
424 00:14:32.548600 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 00:14:32.549116
426 00:14:32.574527 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
427 00:14:32.580071 2D training succeed
428 00:14:32.585667 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 00:14:32.586147 auto size-- 65535DDR cs0 size: 2048MB
430 00:14:32.591110 DDR cs1 size: 2048MB
431 00:14:32.591581 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 00:14:32.596724 cs0 DataBus test pass
433 00:14:32.597201 cs1 DataBus test pass
434 00:14:32.602316 cs0 AddrBus test pass
435 00:14:32.602788 cs1 AddrBus test pass
436 00:14:32.603233
437 00:14:32.603679 100bdlr_step_size ps== 420
438 00:14:32.607919 result report
439 00:14:32.608413 boot times 0Enable ddr reg access
440 00:14:32.616344 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 00:14:32.629815 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 00:14:33.201781 0.0;M3 CHK:0;cm4_sp_mode 0
443 00:14:33.202330 MVN_1=0x00000000
444 00:14:33.207279 MVN_2=0x00000000
445 00:14:33.213147 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 00:14:33.213634 OPS=0x10
447 00:14:33.214088 ring efuse init
448 00:14:33.214530 chipver efuse init
449 00:14:33.218630 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 00:14:33.224214 [0.018961 Inits done]
451 00:14:33.224676 secure task start!
452 00:14:33.225121 high task start!
453 00:14:33.228815 low task start!
454 00:14:33.229283 run into bl31
455 00:14:33.235444 NOTICE: BL31: v1.3(release):4fc40b1
456 00:14:33.243212 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 00:14:33.243697 NOTICE: BL31: G12A normal boot!
458 00:14:33.269195 NOTICE: BL31: BL33 decompress pass
459 00:14:33.274884 ERROR: Error initializing runtime service opteed_fast
460 00:14:34.507825
461 00:14:34.508512
462 00:14:34.516216 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 00:14:34.516712
464 00:14:34.517168 Model: Libre Computer AML-A311D-CC Alta
465 00:14:34.724645 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 00:14:34.748028 DRAM: 2 GiB (effective 3.8 GiB)
467 00:14:34.890926 Core: 408 devices, 31 uclasses, devicetree: separate
468 00:14:34.895934 WDT: Not starting watchdog@f0d0
469 00:14:34.929078 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 00:14:34.941584 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 00:14:34.946574 ** Bad device specification mmc 0 **
472 00:14:34.956869 Card did not respond to voltage select! : -110
473 00:14:34.964492 ** Bad device specification mmc 0 **
474 00:14:34.965005 Couldn't find partition mmc 0
475 00:14:34.972827 Card did not respond to voltage select! : -110
476 00:14:34.978361 ** Bad device specification mmc 0 **
477 00:14:34.978844 Couldn't find partition mmc 0
478 00:14:34.982470 Error: could not access storage.
479 00:14:36.249266 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 00:14:36.249931 bl2_stage_init 0x01
481 00:14:36.250415 bl2_stage_init 0x81
482 00:14:36.254059 hw id: 0x0000 - pwm id 0x01
483 00:14:36.254567 bl2_stage_init 0xc1
484 00:14:36.255028 bl2_stage_init 0x02
485 00:14:36.255482
486 00:14:36.259668 L0:00000000
487 00:14:36.260213 L1:20000703
488 00:14:36.260673 L2:00008067
489 00:14:36.261123 L3:14000000
490 00:14:36.262567 B2:00402000
491 00:14:36.263046 B1:e0f83180
492 00:14:36.263495
493 00:14:36.263942 TE: 58124
494 00:14:36.264432
495 00:14:36.273716 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 00:14:36.274218
497 00:14:36.274691 Board ID = 1
498 00:14:36.275176 Set A53 clk to 24M
499 00:14:36.275663 Set A73 clk to 24M
500 00:14:36.279356 Set clk81 to 24M
501 00:14:36.279913 A53 clk: 1200 MHz
502 00:14:36.280439 A73 clk: 1200 MHz
503 00:14:36.284968 CLK81: 166.6M
504 00:14:36.285521 smccc: 00012a92
505 00:14:36.290588 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 00:14:36.291146 board id: 1
507 00:14:36.299128 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 00:14:36.309852 fw parse done
509 00:14:36.315758 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 00:14:36.358410 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 00:14:36.369264 PIEI prepare done
512 00:14:36.369737 fastboot data load
513 00:14:36.370185 fastboot data verify
514 00:14:36.375007 verify result: 266
515 00:14:36.380753 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 00:14:36.381235 LPDDR4 probe
517 00:14:36.381680 ddr clk to 1584MHz
518 00:14:36.388601 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 00:14:36.425916
520 00:14:36.426448 dmc_version 0001
521 00:14:36.432479 Check phy result
522 00:14:36.438299 INFO : End of CA training
523 00:14:36.438778 INFO : End of initialization
524 00:14:36.443878 INFO : Training has run successfully!
525 00:14:36.444394 Check phy result
526 00:14:36.449574 INFO : End of initialization
527 00:14:36.450039 INFO : End of read enable training
528 00:14:36.455133 INFO : End of fine write leveling
529 00:14:36.460735 INFO : End of Write leveling coarse delay
530 00:14:36.461232 INFO : Training has run successfully!
531 00:14:36.461673 Check phy result
532 00:14:36.466304 INFO : End of initialization
533 00:14:36.466779 INFO : End of read dq deskew training
534 00:14:36.471925 INFO : End of MPR read delay center optimization
535 00:14:36.477749 INFO : End of write delay center optimization
536 00:14:36.483124 INFO : End of read delay center optimization
537 00:14:36.483428 INFO : End of max read latency training
538 00:14:36.488746 INFO : Training has run successfully!
539 00:14:36.489064 1D training succeed
540 00:14:36.497858 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 00:14:36.544658 Check phy result
542 00:14:36.545060 INFO : End of initialization
543 00:14:36.567297 INFO : End of 2D read delay Voltage center optimization
544 00:14:36.587520 INFO : End of 2D read delay Voltage center optimization
545 00:14:36.639678 INFO : End of 2D write delay Voltage center optimization
546 00:14:36.689099 INFO : End of 2D write delay Voltage center optimization
547 00:14:36.694469 INFO : Training has run successfully!
548 00:14:36.694990
549 00:14:36.695444 channel==0
550 00:14:36.700067 RxClkDly_Margin_A0==88 ps 9
551 00:14:36.700554 TxDqDly_Margin_A0==98 ps 10
552 00:14:36.705700 RxClkDly_Margin_A1==88 ps 9
553 00:14:36.706192 TxDqDly_Margin_A1==98 ps 10
554 00:14:36.706641 TrainedVREFDQ_A0==74
555 00:14:36.711293 TrainedVREFDQ_A1==74
556 00:14:36.711787 VrefDac_Margin_A0==25
557 00:14:36.712275 DeviceVref_Margin_A0==40
558 00:14:36.716839 VrefDac_Margin_A1==23
559 00:14:36.717311 DeviceVref_Margin_A1==40
560 00:14:36.717750
561 00:14:36.718185
562 00:14:36.722468 channel==1
563 00:14:36.722935 RxClkDly_Margin_A0==98 ps 10
564 00:14:36.723373 TxDqDly_Margin_A0==88 ps 9
565 00:14:36.728072 RxClkDly_Margin_A1==98 ps 10
566 00:14:36.728545 TxDqDly_Margin_A1==88 ps 9
567 00:14:36.733698 TrainedVREFDQ_A0==77
568 00:14:36.734200 TrainedVREFDQ_A1==77
569 00:14:36.734646 VrefDac_Margin_A0==22
570 00:14:36.739326 DeviceVref_Margin_A0==37
571 00:14:36.739800 VrefDac_Margin_A1==22
572 00:14:36.744882 DeviceVref_Margin_A1==37
573 00:14:36.745352
574 00:14:36.745795 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 00:14:36.746229
576 00:14:36.778473 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 00:14:36.779012 2D training succeed
578 00:14:36.784087 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 00:14:36.789697 auto size-- 65535DDR cs0 size: 2048MB
580 00:14:36.790202 DDR cs1 size: 2048MB
581 00:14:36.795329 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 00:14:36.795820 cs0 DataBus test pass
583 00:14:36.800897 cs1 DataBus test pass
584 00:14:36.801376 cs0 AddrBus test pass
585 00:14:36.801816 cs1 AddrBus test pass
586 00:14:36.802251
587 00:14:36.806475 100bdlr_step_size ps== 420
588 00:14:36.806966 result report
589 00:14:36.812089 boot times 0Enable ddr reg access
590 00:14:36.817434 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 00:14:36.830925 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 00:14:37.404583 0.0;M3 CHK:0;cm4_sp_mode 0
593 00:14:37.405253 MVN_1=0x00000000
594 00:14:37.410053 MVN_2=0x00000000
595 00:14:37.415822 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 00:14:37.416459 OPS=0x10
597 00:14:37.416911 ring efuse init
598 00:14:37.417351 chipver efuse init
599 00:14:37.421444 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 00:14:37.426985 [0.018961 Inits done]
601 00:14:37.427489 secure task start!
602 00:14:37.427935 high task start!
603 00:14:37.431599 low task start!
604 00:14:37.432103 run into bl31
605 00:14:37.438240 NOTICE: BL31: v1.3(release):4fc40b1
606 00:14:37.446021 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 00:14:37.446511 NOTICE: BL31: G12A normal boot!
608 00:14:37.471446 NOTICE: BL31: BL33 decompress pass
609 00:14:37.477102 ERROR: Error initializing runtime service opteed_fast
610 00:14:38.710270
611 00:14:38.710721
612 00:14:38.718546 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 00:14:38.718898
614 00:14:38.719144 Model: Libre Computer AML-A311D-CC Alta
615 00:14:38.927170 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 00:14:38.950408 DRAM: 2 GiB (effective 3.8 GiB)
617 00:14:39.093399 Core: 408 devices, 31 uclasses, devicetree: separate
618 00:14:39.099227 WDT: Not starting watchdog@f0d0
619 00:14:39.131508 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 00:14:39.143917 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 00:14:39.148884 ** Bad device specification mmc 0 **
622 00:14:39.159348 Card did not respond to voltage select! : -110
623 00:14:39.166906 ** Bad device specification mmc 0 **
624 00:14:39.167420 Couldn't find partition mmc 0
625 00:14:39.175186 Card did not respond to voltage select! : -110
626 00:14:39.180659 ** Bad device specification mmc 0 **
627 00:14:39.181153 Couldn't find partition mmc 0
628 00:14:39.185740 Error: could not access storage.
629 00:14:39.528372 Net: eth0: ethernet@ff3f0000
630 00:14:39.529019 starting USB...
631 00:14:39.780176 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 00:14:39.780825 Starting the controller
633 00:14:39.787090 USB XHCI 1.10
634 00:14:41.498838 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 00:14:41.499495 bl2_stage_init 0x01
636 00:14:41.499934 bl2_stage_init 0x81
637 00:14:41.504512 hw id: 0x0000 - pwm id 0x01
638 00:14:41.505043 bl2_stage_init 0xc1
639 00:14:41.505473 bl2_stage_init 0x02
640 00:14:41.505910
641 00:14:41.509930 L0:00000000
642 00:14:41.510435 L1:20000703
643 00:14:41.510852 L2:00008067
644 00:14:41.511262 L3:14000000
645 00:14:41.512850 B2:00402000
646 00:14:41.513335 B1:e0f83180
647 00:14:41.513749
648 00:14:41.514155 TE: 58124
649 00:14:41.514560
650 00:14:41.523892 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 00:14:41.524461
652 00:14:41.524883 Board ID = 1
653 00:14:41.525286 Set A53 clk to 24M
654 00:14:41.525685 Set A73 clk to 24M
655 00:14:41.529523 Set clk81 to 24M
656 00:14:41.530034 A53 clk: 1200 MHz
657 00:14:41.530444 A73 clk: 1200 MHz
658 00:14:41.535167 CLK81: 166.6M
659 00:14:41.535669 smccc: 00012a92
660 00:14:41.540723 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 00:14:41.541235 board id: 1
662 00:14:41.546427 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 00:14:41.559962 fw parse done
664 00:14:41.565919 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 00:14:41.608535 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 00:14:41.619453 PIEI prepare done
667 00:14:41.619977 fastboot data load
668 00:14:41.620448 fastboot data verify
669 00:14:41.625150 verify result: 266
670 00:14:41.630748 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 00:14:41.631250 LPDDR4 probe
672 00:14:41.631669 ddr clk to 1584MHz
673 00:14:41.638745 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 00:14:41.676091
675 00:14:41.676631 dmc_version 0001
676 00:14:41.682747 Check phy result
677 00:14:41.688571 INFO : End of CA training
678 00:14:41.689051 INFO : End of initialization
679 00:14:41.694180 INFO : Training has run successfully!
680 00:14:41.694663 Check phy result
681 00:14:41.699760 INFO : End of initialization
682 00:14:41.700271 INFO : End of read enable training
683 00:14:41.703048 INFO : End of fine write leveling
684 00:14:41.708606 INFO : End of Write leveling coarse delay
685 00:14:41.714215 INFO : Training has run successfully!
686 00:14:41.714698 Check phy result
687 00:14:41.715109 INFO : End of initialization
688 00:14:41.719836 INFO : End of read dq deskew training
689 00:14:41.723242 INFO : End of MPR read delay center optimization
690 00:14:41.728778 INFO : End of write delay center optimization
691 00:14:41.734405 INFO : End of read delay center optimization
692 00:14:41.734890 INFO : End of max read latency training
693 00:14:41.740041 INFO : Training has run successfully!
694 00:14:41.740528 1D training succeed
695 00:14:41.748307 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 00:14:41.795610 Check phy result
697 00:14:41.796056 INFO : End of initialization
698 00:14:41.817388 INFO : End of 2D read delay Voltage center optimization
699 00:14:41.837555 INFO : End of 2D read delay Voltage center optimization
700 00:14:41.888731 INFO : End of 2D write delay Voltage center optimization
701 00:14:41.939035 INFO : End of 2D write delay Voltage center optimization
702 00:14:41.944556 INFO : Training has run successfully!
703 00:14:41.944910
704 00:14:41.945159 channel==0
705 00:14:41.950299 RxClkDly_Margin_A0==88 ps 9
706 00:14:41.950624 TxDqDly_Margin_A0==98 ps 10
707 00:14:41.955775 RxClkDly_Margin_A1==88 ps 9
708 00:14:41.956267 TxDqDly_Margin_A1==98 ps 10
709 00:14:41.956656 TrainedVREFDQ_A0==74
710 00:14:41.961340 TrainedVREFDQ_A1==74
711 00:14:41.961668 VrefDac_Margin_A0==25
712 00:14:41.961909 DeviceVref_Margin_A0==40
713 00:14:41.966960 VrefDac_Margin_A1==26
714 00:14:41.967308 DeviceVref_Margin_A1==40
715 00:14:41.967547
716 00:14:41.967774
717 00:14:41.972556 channel==1
718 00:14:41.972889 RxClkDly_Margin_A0==98 ps 10
719 00:14:41.973142 TxDqDly_Margin_A0==88 ps 9
720 00:14:41.978257 RxClkDly_Margin_A1==98 ps 10
721 00:14:41.978729 TxDqDly_Margin_A1==88 ps 9
722 00:14:41.983733 TrainedVREFDQ_A0==77
723 00:14:41.984229 TrainedVREFDQ_A1==77
724 00:14:41.984666 VrefDac_Margin_A0==22
725 00:14:41.989355 DeviceVref_Margin_A0==37
726 00:14:41.989687 VrefDac_Margin_A1==22
727 00:14:41.994931 DeviceVref_Margin_A1==37
728 00:14:41.995421
729 00:14:41.995864 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 00:14:41.996335
731 00:14:42.028592 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 00:14:42.029033 2D training succeed
733 00:14:42.034300 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 00:14:42.039735 auto size-- 65535DDR cs0 size: 2048MB
735 00:14:42.040271 DDR cs1 size: 2048MB
736 00:14:42.045344 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 00:14:42.045704 cs0 DataBus test pass
738 00:14:42.050950 cs1 DataBus test pass
739 00:14:42.051313 cs0 AddrBus test pass
740 00:14:42.051594 cs1 AddrBus test pass
741 00:14:42.051858
742 00:14:42.056550 100bdlr_step_size ps== 420
743 00:14:42.056927 result report
744 00:14:42.062140 boot times 0Enable ddr reg access
745 00:14:42.067464 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 00:14:42.081013 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 00:14:42.654635 0.0;M3 CHK:0;cm4_sp_mode 0
748 00:14:42.655293 MVN_1=0x00000000
749 00:14:42.660224 MVN_2=0x00000000
750 00:14:42.665897 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 00:14:42.666427 OPS=0x10
752 00:14:42.666754 ring efuse init
753 00:14:42.666973 chipver efuse init
754 00:14:42.671390 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 00:14:42.677024 [0.018961 Inits done]
756 00:14:42.677323 secure task start!
757 00:14:42.677527 high task start!
758 00:14:42.681661 low task start!
759 00:14:42.682180 run into bl31
760 00:14:42.688367 NOTICE: BL31: v1.3(release):4fc40b1
761 00:14:42.696200 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 00:14:42.696728 NOTICE: BL31: G12A normal boot!
763 00:14:42.721550 NOTICE: BL31: BL33 decompress pass
764 00:14:42.727245 ERROR: Error initializing runtime service opteed_fast
765 00:14:43.960045
766 00:14:43.960681
767 00:14:43.968468 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 00:14:43.968982
769 00:14:43.969415 Model: Libre Computer AML-A311D-CC Alta
770 00:14:44.176894 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 00:14:44.200284 DRAM: 2 GiB (effective 3.8 GiB)
772 00:14:44.343236 Core: 408 devices, 31 uclasses, devicetree: separate
773 00:14:44.349134 WDT: Not starting watchdog@f0d0
774 00:14:44.381398 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 00:14:44.393789 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 00:14:44.398812 ** Bad device specification mmc 0 **
777 00:14:44.409214 Card did not respond to voltage select! : -110
778 00:14:44.416530 ** Bad device specification mmc 0 **
779 00:14:44.417052 Couldn't find partition mmc 0
780 00:14:44.425150 Card did not respond to voltage select! : -110
781 00:14:44.430709 ** Bad device specification mmc 0 **
782 00:14:44.430997 Couldn't find partition mmc 0
783 00:14:44.435695 Error: could not access storage.
784 00:14:44.777802 Net: eth0: ethernet@ff3f0000
785 00:14:44.778195 starting USB...
786 00:14:45.029939 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 00:14:45.030525 Starting the controller
788 00:14:45.036966 USB XHCI 1.10
789 00:14:47.200445 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 00:14:47.201092 bl2_stage_init 0x01
791 00:14:47.201531 bl2_stage_init 0x81
792 00:14:47.206030 hw id: 0x0000 - pwm id 0x01
793 00:14:47.206559 bl2_stage_init 0xc1
794 00:14:47.206989 bl2_stage_init 0x02
795 00:14:47.207403
796 00:14:47.211668 L0:00000000
797 00:14:47.212232 L1:20000703
798 00:14:47.212657 L2:00008067
799 00:14:47.213069 L3:14000000
800 00:14:47.214596 B2:00402000
801 00:14:47.215092 B1:e0f83180
802 00:14:47.215505
803 00:14:47.215913 TE: 58167
804 00:14:47.216372
805 00:14:47.225732 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 00:14:47.226283
807 00:14:47.226703 Board ID = 1
808 00:14:47.227107 Set A53 clk to 24M
809 00:14:47.227504 Set A73 clk to 24M
810 00:14:47.231438 Set clk81 to 24M
811 00:14:47.231958 A53 clk: 1200 MHz
812 00:14:47.232418 A73 clk: 1200 MHz
813 00:14:47.237005 CLK81: 166.6M
814 00:14:47.237499 smccc: 00012abe
815 00:14:47.242585 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 00:14:47.243074 board id: 1
817 00:14:47.251144 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 00:14:47.261770 fw parse done
819 00:14:47.267777 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 00:14:47.310194 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 00:14:47.321147 PIEI prepare done
822 00:14:47.321635 fastboot data load
823 00:14:47.322054 fastboot data verify
824 00:14:47.326739 verify result: 266
825 00:14:47.332374 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 00:14:47.332890 LPDDR4 probe
827 00:14:47.333313 ddr clk to 1584MHz
828 00:14:47.340368 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 00:14:47.377560
830 00:14:47.378099 dmc_version 0001
831 00:14:47.384448 Check phy result
832 00:14:47.390088 INFO : End of CA training
833 00:14:47.390584 INFO : End of initialization
834 00:14:47.395684 INFO : Training has run successfully!
835 00:14:47.396265 Check phy result
836 00:14:47.401502 INFO : End of initialization
837 00:14:47.402044 INFO : End of read enable training
838 00:14:47.404661 INFO : End of fine write leveling
839 00:14:47.410160 INFO : End of Write leveling coarse delay
840 00:14:47.415780 INFO : Training has run successfully!
841 00:14:47.416324 Check phy result
842 00:14:47.416771 INFO : End of initialization
843 00:14:47.421327 INFO : End of read dq deskew training
844 00:14:47.426946 INFO : End of MPR read delay center optimization
845 00:14:47.427469 INFO : End of write delay center optimization
846 00:14:47.432605 INFO : End of read delay center optimization
847 00:14:47.438160 INFO : End of max read latency training
848 00:14:47.438678 INFO : Training has run successfully!
849 00:14:47.443725 1D training succeed
850 00:14:47.449236 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 00:14:47.497286 Check phy result
852 00:14:47.497862 INFO : End of initialization
853 00:14:47.519070 INFO : End of 2D read delay Voltage center optimization
854 00:14:47.538383 INFO : End of 2D read delay Voltage center optimization
855 00:14:47.591290 INFO : End of 2D write delay Voltage center optimization
856 00:14:47.640693 INFO : End of 2D write delay Voltage center optimization
857 00:14:47.646236 INFO : Training has run successfully!
858 00:14:47.646710
859 00:14:47.647127 channel==0
860 00:14:47.651829 RxClkDly_Margin_A0==88 ps 9
861 00:14:47.652356 TxDqDly_Margin_A0==98 ps 10
862 00:14:47.657430 RxClkDly_Margin_A1==88 ps 9
863 00:14:47.657908 TxDqDly_Margin_A1==88 ps 9
864 00:14:47.658341 TrainedVREFDQ_A0==74
865 00:14:47.663065 TrainedVREFDQ_A1==74
866 00:14:47.663579 VrefDac_Margin_A0==25
867 00:14:47.664027 DeviceVref_Margin_A0==40
868 00:14:47.668638 VrefDac_Margin_A1==25
869 00:14:47.669139 DeviceVref_Margin_A1==40
870 00:14:47.669531
871 00:14:47.669921
872 00:14:47.670307 channel==1
873 00:14:47.674694 RxClkDly_Margin_A0==98 ps 10
874 00:14:47.675428 TxDqDly_Margin_A0==98 ps 10
875 00:14:47.679759 RxClkDly_Margin_A1==98 ps 10
876 00:14:47.680456 TxDqDly_Margin_A1==88 ps 9
877 00:14:47.685333 TrainedVREFDQ_A0==77
878 00:14:47.686016 TrainedVREFDQ_A1==77
879 00:14:47.686647 VrefDac_Margin_A0==22
880 00:14:47.690954 DeviceVref_Margin_A0==37
881 00:14:47.691698 VrefDac_Margin_A1==24
882 00:14:47.696514 DeviceVref_Margin_A1==37
883 00:14:47.697205
884 00:14:47.697838 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 00:14:47.698456
886 00:14:47.730212 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 00:14:47.731000 2D training succeed
888 00:14:47.735851 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 00:14:47.741357 auto size-- 65535DDR cs0 size: 2048MB
890 00:14:47.742079 DDR cs1 size: 2048MB
891 00:14:47.746908 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 00:14:47.747637 cs0 DataBus test pass
893 00:14:47.752533 cs1 DataBus test pass
894 00:14:47.753304 cs0 AddrBus test pass
895 00:14:47.753895 cs1 AddrBus test pass
896 00:14:47.754419
897 00:14:47.758189 100bdlr_step_size ps== 420
898 00:14:47.758883 result report
899 00:14:47.763717 boot times 0Enable ddr reg access
900 00:14:47.769197 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 00:14:47.782537 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 00:14:48.356518 0.0;M3 CHK:0;cm4_sp_mode 0
903 00:14:48.357187 MVN_1=0x00000000
904 00:14:48.361804 MVN_2=0x00000000
905 00:14:48.367552 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 00:14:48.368179 OPS=0x10
907 00:14:48.368684 ring efuse init
908 00:14:48.369153 chipver efuse init
909 00:14:48.375795 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 00:14:48.376362 [0.018961 Inits done]
911 00:14:48.383329 secure task start!
912 00:14:48.383834 high task start!
913 00:14:48.384333 low task start!
914 00:14:48.384786 run into bl31
915 00:14:48.389930 NOTICE: BL31: v1.3(release):4fc40b1
916 00:14:48.397880 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 00:14:48.398571 NOTICE: BL31: G12A normal boot!
918 00:14:48.423375 NOTICE: BL31: BL33 decompress pass
919 00:14:48.428853 ERROR: Error initializing runtime service opteed_fast
920 00:14:49.661800
921 00:14:49.662463
922 00:14:49.669705 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 00:14:49.670214
924 00:14:49.670683 Model: Libre Computer AML-A311D-CC Alta
925 00:14:49.878606 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 00:14:49.902010 DRAM: 2 GiB (effective 3.8 GiB)
927 00:14:50.044948 Core: 408 devices, 31 uclasses, devicetree: separate
928 00:14:50.050716 WDT: Not starting watchdog@f0d0
929 00:14:50.083092 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 00:14:50.095492 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 00:14:50.100476 ** Bad device specification mmc 0 **
932 00:14:50.110827 Card did not respond to voltage select! : -110
933 00:14:50.118430 ** Bad device specification mmc 0 **
934 00:14:50.118752 Couldn't find partition mmc 0
935 00:14:50.126784 Card did not respond to voltage select! : -110
936 00:14:50.132359 ** Bad device specification mmc 0 **
937 00:14:50.132779 Couldn't find partition mmc 0
938 00:14:50.137430 Error: could not access storage.
939 00:14:50.481565 Net: eth0: ethernet@ff3f0000
940 00:14:50.482000 starting USB...
941 00:14:50.732768 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 00:14:50.733434 Starting the controller
943 00:14:50.739616 USB XHCI 1.10
944 00:14:52.600348 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 00:14:52.601025 bl2_stage_init 0x01
946 00:14:52.601503 bl2_stage_init 0x81
947 00:14:52.605875 hw id: 0x0000 - pwm id 0x01
948 00:14:52.606377 bl2_stage_init 0xc1
949 00:14:52.606835 bl2_stage_init 0x02
950 00:14:52.607287
951 00:14:52.611464 L0:00000000
952 00:14:52.611962 L1:20000703
953 00:14:52.612452 L2:00008067
954 00:14:52.612897 L3:14000000
955 00:14:52.614413 B2:00402000
956 00:14:52.614893 B1:e0f83180
957 00:14:52.615341
958 00:14:52.615792 TE: 58124
959 00:14:52.616284
960 00:14:52.625390 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 00:14:52.625909
962 00:14:52.626363 Board ID = 1
963 00:14:52.626805 Set A53 clk to 24M
964 00:14:52.627245 Set A73 clk to 24M
965 00:14:52.631046 Set clk81 to 24M
966 00:14:52.631533 A53 clk: 1200 MHz
967 00:14:52.632009 A73 clk: 1200 MHz
968 00:14:52.634583 CLK81: 166.6M
969 00:14:52.635061 smccc: 00012a92
970 00:14:52.640058 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 00:14:52.645601 board id: 1
972 00:14:52.650935 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 00:14:52.661628 fw parse done
974 00:14:52.667646 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 00:14:52.710207 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 00:14:52.721046 PIEI prepare done
977 00:14:52.721528 fastboot data load
978 00:14:52.721964 fastboot data verify
979 00:14:52.726598 verify result: 266
980 00:14:52.732271 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 00:14:52.732738 LPDDR4 probe
982 00:14:52.733166 ddr clk to 1584MHz
983 00:14:52.740262 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 00:14:52.777502
985 00:14:52.777981 dmc_version 0001
986 00:14:52.784264 Check phy result
987 00:14:52.790026 INFO : End of CA training
988 00:14:52.790511 INFO : End of initialization
989 00:14:52.795604 INFO : Training has run successfully!
990 00:14:52.796179 Check phy result
991 00:14:52.801214 INFO : End of initialization
992 00:14:52.801701 INFO : End of read enable training
993 00:14:52.804633 INFO : End of fine write leveling
994 00:14:52.810190 INFO : End of Write leveling coarse delay
995 00:14:52.815907 INFO : Training has run successfully!
996 00:14:52.816420 Check phy result
997 00:14:52.816871 INFO : End of initialization
998 00:14:52.821383 INFO : End of read dq deskew training
999 00:14:52.826948 INFO : End of MPR read delay center optimization
1000 00:14:52.827432 INFO : End of write delay center optimization
1001 00:14:52.832546 INFO : End of read delay center optimization
1002 00:14:52.838140 INFO : End of max read latency training
1003 00:14:52.838625 INFO : Training has run successfully!
1004 00:14:52.843880 1D training succeed
1005 00:14:52.849655 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 00:14:52.897205 Check phy result
1007 00:14:52.897731 INFO : End of initialization
1008 00:14:52.919644 INFO : End of 2D read delay Voltage center optimization
1009 00:14:52.939801 INFO : End of 2D read delay Voltage center optimization
1010 00:14:52.991561 INFO : End of 2D write delay Voltage center optimization
1011 00:14:53.041094 INFO : End of 2D write delay Voltage center optimization
1012 00:14:53.046578 INFO : Training has run successfully!
1013 00:14:53.047071
1014 00:14:53.047531 channel==0
1015 00:14:53.052181 RxClkDly_Margin_A0==88 ps 9
1016 00:14:53.052678 TxDqDly_Margin_A0==98 ps 10
1017 00:14:53.057750 RxClkDly_Margin_A1==88 ps 9
1018 00:14:53.058249 TxDqDly_Margin_A1==98 ps 10
1019 00:14:53.058711 TrainedVREFDQ_A0==74
1020 00:14:53.063456 TrainedVREFDQ_A1==74
1021 00:14:53.063949 VrefDac_Margin_A0==25
1022 00:14:53.064452 DeviceVref_Margin_A0==40
1023 00:14:53.068941 VrefDac_Margin_A1==25
1024 00:14:53.069425 DeviceVref_Margin_A1==40
1025 00:14:53.069871
1026 00:14:53.070317
1027 00:14:53.074474 channel==1
1028 00:14:53.074944 RxClkDly_Margin_A0==98 ps 10
1029 00:14:53.075426 TxDqDly_Margin_A0==98 ps 10
1030 00:14:53.080072 RxClkDly_Margin_A1==98 ps 10
1031 00:14:53.080570 TxDqDly_Margin_A1==88 ps 9
1032 00:14:53.085730 TrainedVREFDQ_A0==77
1033 00:14:53.086255 TrainedVREFDQ_A1==77
1034 00:14:53.086729 VrefDac_Margin_A0==22
1035 00:14:53.091302 DeviceVref_Margin_A0==37
1036 00:14:53.091789 VrefDac_Margin_A1==24
1037 00:14:53.096948 DeviceVref_Margin_A1==37
1038 00:14:53.097446
1039 00:14:53.097907 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 00:14:53.102487
1041 00:14:53.130491 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 00:14:53.131043 2D training succeed
1043 00:14:53.136176 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 00:14:53.141595 auto size-- 65535DDR cs0 size: 2048MB
1045 00:14:53.142085 DDR cs1 size: 2048MB
1046 00:14:53.147193 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 00:14:53.147680 cs0 DataBus test pass
1048 00:14:53.152831 cs1 DataBus test pass
1049 00:14:53.153319 cs0 AddrBus test pass
1050 00:14:53.153777 cs1 AddrBus test pass
1051 00:14:53.154229
1052 00:14:53.158352 100bdlr_step_size ps== 420
1053 00:14:53.158848 result report
1054 00:14:53.164044 boot times 0Enable ddr reg access
1055 00:14:53.168521 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 00:14:53.182903 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 00:14:53.755053 0.0;M3 CHK:0;cm4_sp_mode 0
1058 00:14:53.755720 MVN_1=0x00000000
1059 00:14:53.760425 MVN_2=0x00000000
1060 00:14:53.766183 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 00:14:53.766673 OPS=0x10
1062 00:14:53.767136 ring efuse init
1063 00:14:53.767586 chipver efuse init
1064 00:14:53.774470 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 00:14:53.774971 [0.018961 Inits done]
1066 00:14:53.775425 secure task start!
1067 00:14:53.781981 high task start!
1068 00:14:53.782470 low task start!
1069 00:14:53.782919 run into bl31
1070 00:14:53.788673 NOTICE: BL31: v1.3(release):4fc40b1
1071 00:14:53.796389 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 00:14:53.796876 NOTICE: BL31: G12A normal boot!
1073 00:14:53.821741 NOTICE: BL31: BL33 decompress pass
1074 00:14:53.827344 ERROR: Error initializing runtime service opteed_fast
1075 00:14:55.060329
1076 00:14:55.061010
1077 00:14:55.068650 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 00:14:55.069208
1079 00:14:55.069677 Model: Libre Computer AML-A311D-CC Alta
1080 00:14:55.277108 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 00:14:55.300410 DRAM: 2 GiB (effective 3.8 GiB)
1082 00:14:55.443571 Core: 408 devices, 31 uclasses, devicetree: separate
1083 00:14:55.449295 WDT: Not starting watchdog@f0d0
1084 00:14:55.481614 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 00:14:55.494090 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 00:14:55.498967 ** Bad device specification mmc 0 **
1087 00:14:55.509300 Card did not respond to voltage select! : -110
1088 00:14:55.516964 ** Bad device specification mmc 0 **
1089 00:14:55.517498 Couldn't find partition mmc 0
1090 00:14:55.525295 Card did not respond to voltage select! : -110
1091 00:14:55.530870 ** Bad device specification mmc 0 **
1092 00:14:55.531406 Couldn't find partition mmc 0
1093 00:14:55.535922 Error: could not access storage.
1094 00:14:55.878711 Net: eth0: ethernet@ff3f0000
1095 00:14:55.879400 starting USB...
1096 00:14:56.130242 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 00:14:56.130692 Starting the controller
1098 00:14:56.137194 USB XHCI 1.10
1099 00:14:57.691334 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 00:14:57.699578 scanning usb for storage devices... 0 Storage Device(s) found
1102 00:14:57.751293 Hit any key to stop autoboot: 1
1103 00:14:57.752186 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1104 00:14:57.752815 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1105 00:14:57.753329 Setting prompt string to ['=>']
1106 00:14:57.753845 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1107 00:14:57.766993 0
1108 00:14:57.767913 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 00:14:57.768496 Sending with 10 millisecond of delay
1111 00:14:58.903418 => setenv autoload no
1112 00:14:58.914335 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 00:14:58.919802 setenv autoload no
1114 00:14:58.920636 Sending with 10 millisecond of delay
1116 00:15:00.718135 => setenv initrd_high 0xffffffff
1117 00:15:00.729022 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1118 00:15:00.730891 setenv initrd_high 0xffffffff
1119 00:15:00.731441 Sending with 10 millisecond of delay
1121 00:15:02.347291 => setenv fdt_high 0xffffffff
1122 00:15:02.357876 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1123 00:15:02.358432 setenv fdt_high 0xffffffff
1124 00:15:02.358946 Sending with 10 millisecond of delay
1126 00:15:02.650459 => dhcp
1127 00:15:02.661216 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1128 00:15:02.661769 dhcp
1129 00:15:02.662007 Speed: 1000, full duplex
1130 00:15:02.662219 BOOTP broadcast 1
1131 00:15:02.673300 DHCP client bound to address 192.168.6.27 (12 ms)
1132 00:15:02.673980 Sending with 10 millisecond of delay
1134 00:15:04.350504 => setenv serverip 192.168.6.2
1135 00:15:04.362042 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1136 00:15:04.362636 setenv serverip 192.168.6.2
1137 00:15:04.363129 Sending with 10 millisecond of delay
1139 00:15:08.087422 => tftpboot 0x01080000 955859/tftp-deploy-019ra8hq/kernel/uImage
1140 00:15:08.098187 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 00:15:08.098699 tftpboot 0x01080000 955859/tftp-deploy-019ra8hq/kernel/uImage
1142 00:15:08.098941 Speed: 1000, full duplex
1143 00:15:08.099148 Using ethernet@ff3f0000 device
1144 00:15:08.100780 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 00:15:08.106402 Filename '955859/tftp-deploy-019ra8hq/kernel/uImage'.
1146 00:15:08.110295 Load address: 0x1080000
1147 00:15:11.348037 Loading: *################################################## 43.6 MiB
1148 00:15:11.349091 13.5 MiB/s
1149 00:15:11.349391 done
1150 00:15:11.352391 Bytes transferred = 45713984 (2b98a40 hex)
1151 00:15:11.352930 Sending with 10 millisecond of delay
1153 00:15:16.041681 => tftpboot 0x08000000 955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot
1154 00:15:16.052749 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1155 00:15:16.053399 tftpboot 0x08000000 955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot
1156 00:15:16.053660 Speed: 1000, full duplex
1157 00:15:16.054456 Using ethernet@ff3f0000 device
1158 00:15:16.055183 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 00:15:16.066569 Filename '955859/tftp-deploy-019ra8hq/ramdisk/ramdisk.cpio.gz.uboot'.
1160 00:15:16.066969 Load address: 0x8000000
1161 00:15:22.684269 Loading: *##########T ####################################### UDP wrong checksum 00000005 0000c509
1162 00:15:27.685334 T UDP wrong checksum 00000005 0000c509
1163 00:15:37.688356 T T UDP wrong checksum 00000005 0000c509
1164 00:15:48.445181 T T UDP wrong checksum 000000ff 0000d821
1165 00:15:48.465742 UDP wrong checksum 000000ff 00006f14
1166 00:15:48.576289 UDP wrong checksum 000000ff 00007310
1167 00:15:48.625850 UDP wrong checksum 000000ff 0000cb88
1168 00:15:57.692415 T T UDP wrong checksum 00000005 0000c509
1169 00:16:12.695745 T T
1170 00:16:12.696407 Retry count exceeded; starting again
1172 00:16:12.697859 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 00:16:12.699736 end: 2.4 uboot-commands (duration 00:01:53) [common]
1177 00:16:12.701198 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 00:16:12.702270 end: 2 uboot-action (duration 00:01:53) [common]
1181 00:16:12.703780 Cleaning after the job
1182 00:16:12.704363 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/ramdisk
1183 00:16:12.705528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/kernel
1184 00:16:12.754362 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/dtb
1185 00:16:12.755647 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/nfsrootfs
1186 00:16:13.069838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955859/tftp-deploy-019ra8hq/modules
1187 00:16:13.090769 start: 4.1 power-off (timeout 00:00:30) [common]
1188 00:16:13.091450 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 00:16:13.124606 >> OK - accepted request
1190 00:16:13.126384 Returned 0 in 0 seconds
1191 00:16:13.227159 end: 4.1 power-off (duration 00:00:00) [common]
1193 00:16:13.228242 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 00:16:13.228926 Listened to connection for namespace 'common' for up to 1s
1195 00:16:14.229871 Finalising connection for namespace 'common'
1196 00:16:14.230379 Disconnecting from shell: Finalise
1197 00:16:14.230679 =>
1198 00:16:14.331315 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 00:16:14.331683 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955859
1200 00:16:16.927470 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955859
1201 00:16:16.928114 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.