Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 18:39:04.705759 lava-dispatcher, installed at version: 2024.01
2 18:39:04.706564 start: 0 validate
3 18:39:04.707046 Start time: 2024-11-11 18:39:04.707013+00:00 (UTC)
4 18:39:04.707618 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 18:39:04.708230 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:39:04.750391 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 18:39:04.750949 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 18:39:04.785518 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 18:39:04.786179 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 18:39:04.820781 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 18:39:04.821337 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:39:04.850888 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 18:39:04.851418 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 18:39:04.888077 validate duration: 0.18
16 18:39:04.888954 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:39:04.889287 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:39:04.889639 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:39:04.890225 Not decompressing ramdisk as can be used compressed.
20 18:39:04.890664 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 18:39:04.890962 saving as /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/ramdisk/initrd.cpio.gz
22 18:39:04.891237 total size: 5628169 (5 MB)
23 18:39:04.928452 progress 0 % (0 MB)
24 18:39:04.932865 progress 5 % (0 MB)
25 18:39:04.937532 progress 10 % (0 MB)
26 18:39:04.941440 progress 15 % (0 MB)
27 18:39:04.945844 progress 20 % (1 MB)
28 18:39:04.949786 progress 25 % (1 MB)
29 18:39:04.954129 progress 30 % (1 MB)
30 18:39:04.960854 progress 35 % (1 MB)
31 18:39:04.964941 progress 40 % (2 MB)
32 18:39:04.969260 progress 45 % (2 MB)
33 18:39:04.973237 progress 50 % (2 MB)
34 18:39:04.977562 progress 55 % (2 MB)
35 18:39:04.982152 progress 60 % (3 MB)
36 18:39:04.986180 progress 65 % (3 MB)
37 18:39:04.990491 progress 70 % (3 MB)
38 18:39:04.994622 progress 75 % (4 MB)
39 18:39:04.999041 progress 80 % (4 MB)
40 18:39:05.002873 progress 85 % (4 MB)
41 18:39:05.007376 progress 90 % (4 MB)
42 18:39:05.011388 progress 95 % (5 MB)
43 18:39:05.015208 progress 100 % (5 MB)
44 18:39:05.016126 5 MB downloaded in 0.12 s (42.99 MB/s)
45 18:39:05.016706 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:39:05.017675 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:39:05.018000 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:39:05.018294 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:39:05.018782 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/kernel/Image
51 18:39:05.019053 saving as /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/kernel/Image
52 18:39:05.019289 total size: 45713920 (43 MB)
53 18:39:05.019517 No compression specified
54 18:39:05.059333 progress 0 % (0 MB)
55 18:39:05.088988 progress 5 % (2 MB)
56 18:39:05.119376 progress 10 % (4 MB)
57 18:39:05.148674 progress 15 % (6 MB)
58 18:39:05.178004 progress 20 % (8 MB)
59 18:39:05.206777 progress 25 % (10 MB)
60 18:39:05.235777 progress 30 % (13 MB)
61 18:39:05.264609 progress 35 % (15 MB)
62 18:39:05.293898 progress 40 % (17 MB)
63 18:39:05.322710 progress 45 % (19 MB)
64 18:39:05.353764 progress 50 % (21 MB)
65 18:39:05.388502 progress 55 % (24 MB)
66 18:39:05.422953 progress 60 % (26 MB)
67 18:39:05.456228 progress 65 % (28 MB)
68 18:39:05.490076 progress 70 % (30 MB)
69 18:39:05.524337 progress 75 % (32 MB)
70 18:39:05.558058 progress 80 % (34 MB)
71 18:39:05.591210 progress 85 % (37 MB)
72 18:39:05.625055 progress 90 % (39 MB)
73 18:39:05.659016 progress 95 % (41 MB)
74 18:39:05.692049 progress 100 % (43 MB)
75 18:39:05.692710 43 MB downloaded in 0.67 s (64.74 MB/s)
76 18:39:05.693293 end: 1.2.1 http-download (duration 00:00:01) [common]
78 18:39:05.694292 end: 1.2 download-retry (duration 00:00:01) [common]
79 18:39:05.694625 start: 1.3 download-retry (timeout 00:09:59) [common]
80 18:39:05.694950 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 18:39:05.695609 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 18:39:05.695950 saving as /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/dtb/meson-g12b-a311d-libretech-cc.dtb
83 18:39:05.696239 total size: 54703 (0 MB)
84 18:39:05.696497 No compression specified
85 18:39:05.739580 progress 59 % (0 MB)
86 18:39:05.740692 progress 100 % (0 MB)
87 18:39:05.741374 0 MB downloaded in 0.05 s (1.16 MB/s)
88 18:39:05.741958 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:39:05.742980 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:39:05.743315 start: 1.4 download-retry (timeout 00:09:59) [common]
92 18:39:05.743651 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 18:39:05.744252 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 18:39:05.744572 saving as /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/nfsrootfs/full.rootfs.tar
95 18:39:05.744836 total size: 120894716 (115 MB)
96 18:39:05.745107 Using unxz to decompress xz
97 18:39:05.778372 progress 0 % (0 MB)
98 18:39:06.621347 progress 5 % (5 MB)
99 18:39:07.524544 progress 10 % (11 MB)
100 18:39:08.325532 progress 15 % (17 MB)
101 18:39:09.090029 progress 20 % (23 MB)
102 18:39:09.682954 progress 25 % (28 MB)
103 18:39:10.537322 progress 30 % (34 MB)
104 18:39:11.340947 progress 35 % (40 MB)
105 18:39:11.708686 progress 40 % (46 MB)
106 18:39:12.107408 progress 45 % (51 MB)
107 18:39:12.838065 progress 50 % (57 MB)
108 18:39:13.732985 progress 55 % (63 MB)
109 18:39:14.524174 progress 60 % (69 MB)
110 18:39:15.292936 progress 65 % (74 MB)
111 18:39:16.107717 progress 70 % (80 MB)
112 18:39:16.956676 progress 75 % (86 MB)
113 18:39:17.768103 progress 80 % (92 MB)
114 18:39:18.550327 progress 85 % (98 MB)
115 18:39:19.419919 progress 90 % (103 MB)
116 18:39:20.213129 progress 95 % (109 MB)
117 18:39:21.050212 progress 100 % (115 MB)
118 18:39:21.063338 115 MB downloaded in 15.32 s (7.53 MB/s)
119 18:39:21.064039 end: 1.4.1 http-download (duration 00:00:15) [common]
121 18:39:21.064964 end: 1.4 download-retry (duration 00:00:15) [common]
122 18:39:21.065242 start: 1.5 download-retry (timeout 00:09:44) [common]
123 18:39:21.065517 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 18:39:21.066062 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/modules.tar.xz
125 18:39:21.066343 saving as /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/modules/modules.tar
126 18:39:21.066553 total size: 11600216 (11 MB)
127 18:39:21.066770 Using unxz to decompress xz
128 18:39:21.105118 progress 0 % (0 MB)
129 18:39:21.176992 progress 5 % (0 MB)
130 18:39:21.256646 progress 10 % (1 MB)
131 18:39:21.358125 progress 15 % (1 MB)
132 18:39:21.451609 progress 20 % (2 MB)
133 18:39:21.531942 progress 25 % (2 MB)
134 18:39:21.608575 progress 30 % (3 MB)
135 18:39:21.683921 progress 35 % (3 MB)
136 18:39:21.761970 progress 40 % (4 MB)
137 18:39:21.838346 progress 45 % (5 MB)
138 18:39:21.922643 progress 50 % (5 MB)
139 18:39:22.002543 progress 55 % (6 MB)
140 18:39:22.088698 progress 60 % (6 MB)
141 18:39:22.170127 progress 65 % (7 MB)
142 18:39:22.247073 progress 70 % (7 MB)
143 18:39:22.329074 progress 75 % (8 MB)
144 18:39:22.412882 progress 80 % (8 MB)
145 18:39:22.489056 progress 85 % (9 MB)
146 18:39:22.571752 progress 90 % (9 MB)
147 18:39:22.650813 progress 95 % (10 MB)
148 18:39:22.729709 progress 100 % (11 MB)
149 18:39:22.740010 11 MB downloaded in 1.67 s (6.61 MB/s)
150 18:39:22.740652 end: 1.5.1 http-download (duration 00:00:02) [common]
152 18:39:22.741559 end: 1.5 download-retry (duration 00:00:02) [common]
153 18:39:22.741876 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 18:39:22.742205 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 18:39:40.696789 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/976283/extract-nfsrootfs-jcjeohh8
156 18:39:40.697384 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 18:39:40.697674 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 18:39:40.698401 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf
159 18:39:40.698876 makedir: /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin
160 18:39:40.699222 makedir: /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/tests
161 18:39:40.699547 makedir: /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/results
162 18:39:40.699882 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-add-keys
163 18:39:40.700463 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-add-sources
164 18:39:40.701072 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-background-process-start
165 18:39:40.701613 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-background-process-stop
166 18:39:40.702176 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-common-functions
167 18:39:40.702743 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-echo-ipv4
168 18:39:40.703273 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-install-packages
169 18:39:40.703775 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-installed-packages
170 18:39:40.704321 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-os-build
171 18:39:40.704877 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-probe-channel
172 18:39:40.705395 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-probe-ip
173 18:39:40.705895 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-target-ip
174 18:39:40.706505 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-target-mac
175 18:39:40.707044 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-target-storage
176 18:39:40.707613 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-case
177 18:39:40.708174 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-event
178 18:39:40.708697 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-feedback
179 18:39:40.709208 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-raise
180 18:39:40.709710 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-reference
181 18:39:40.710275 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-runner
182 18:39:40.710812 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-set
183 18:39:40.711377 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-test-shell
184 18:39:40.711916 Updating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-add-keys (debian)
185 18:39:40.712545 Updating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-add-sources (debian)
186 18:39:40.713104 Updating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-install-packages (debian)
187 18:39:40.713633 Updating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-installed-packages (debian)
188 18:39:40.714202 Updating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/bin/lava-os-build (debian)
189 18:39:40.714689 Creating /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/environment
190 18:39:40.715103 LAVA metadata
191 18:39:40.715377 - LAVA_JOB_ID=976283
192 18:39:40.715596 - LAVA_DISPATCHER_IP=192.168.6.2
193 18:39:40.716006 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 18:39:40.717081 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 18:39:40.717420 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 18:39:40.717627 skipped lava-vland-overlay
197 18:39:40.717868 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 18:39:40.718122 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 18:39:40.718344 skipped lava-multinode-overlay
200 18:39:40.718588 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 18:39:40.718839 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 18:39:40.719089 Loading test definitions
203 18:39:40.719370 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 18:39:40.719590 Using /lava-976283 at stage 0
205 18:39:40.720814 uuid=976283_1.6.2.4.1 testdef=None
206 18:39:40.721156 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 18:39:40.721423 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 18:39:40.723066 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 18:39:40.723867 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 18:39:40.725945 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 18:39:40.726794 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 18:39:40.728795 runner path: /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/0/tests/0_timesync-off test_uuid 976283_1.6.2.4.1
215 18:39:40.729420 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 18:39:40.730241 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 18:39:40.730471 Using /lava-976283 at stage 0
219 18:39:40.730839 Fetching tests from https://github.com/kernelci/test-definitions.git
220 18:39:40.731137 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/0/tests/1_kselftest-alsa'
221 18:39:47.967670 Running '/usr/bin/git checkout kernelci.org
222 18:39:48.415683 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 18:39:48.417181 uuid=976283_1.6.2.4.5 testdef=None
224 18:39:48.417530 end: 1.6.2.4.5 git-repo-action (duration 00:00:08) [common]
226 18:39:48.418273 start: 1.6.2.4.6 test-overlay (timeout 00:09:16) [common]
227 18:39:48.421182 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 18:39:48.422003 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:16) [common]
230 18:39:48.425789 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 18:39:48.426649 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:16) [common]
233 18:39:48.430349 runner path: /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/0/tests/1_kselftest-alsa test_uuid 976283_1.6.2.4.5
234 18:39:48.430648 BOARD='meson-g12b-a311d-libretech-cc'
235 18:39:48.430855 BRANCH='broonie-spi'
236 18:39:48.431053 SKIPFILE='/dev/null'
237 18:39:48.431250 SKIP_INSTALL='True'
238 18:39:48.431446 TESTPROG_URL='http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 18:39:48.431672 TST_CASENAME=''
240 18:39:48.431870 TST_CMDFILES='alsa'
241 18:39:48.432488 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 18:39:48.433279 Creating lava-test-runner.conf files
244 18:39:48.433485 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/976283/lava-overlay-u9bvnyqf/lava-976283/0 for stage 0
245 18:39:48.433847 - 0_timesync-off
246 18:39:48.434098 - 1_kselftest-alsa
247 18:39:48.434439 end: 1.6.2.4 test-definition (duration 00:00:08) [common]
248 18:39:48.434723 start: 1.6.2.5 compress-overlay (timeout 00:09:16) [common]
249 18:40:12.784049 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 18:40:12.784558 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:52) [common]
251 18:40:12.784879 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 18:40:12.785209 end: 1.6.2 lava-overlay (duration 00:00:32) [common]
253 18:40:12.785525 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:52) [common]
254 18:40:13.410226 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 18:40:13.410718 start: 1.6.4 extract-modules (timeout 00:08:51) [common]
256 18:40:13.411007 extracting modules file /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976283/extract-nfsrootfs-jcjeohh8
257 18:40:14.862994 extracting modules file /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976283/extract-overlay-ramdisk-_b_s8d0m/ramdisk
258 18:40:16.389625 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 18:40:16.390222 start: 1.6.5 apply-overlay-tftp (timeout 00:08:48) [common]
260 18:40:16.390594 [common] Applying overlay to NFS
261 18:40:16.390881 [common] Applying overlay /var/lib/lava/dispatcher/tmp/976283/compress-overlay-_fjc7ya6/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/976283/extract-nfsrootfs-jcjeohh8
262 18:40:19.685754 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 18:40:19.686342 start: 1.6.6 prepare-kernel (timeout 00:08:45) [common]
264 18:40:19.686720 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:45) [common]
265 18:40:19.687043 Converting downloaded kernel to a uImage
266 18:40:19.687440 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/kernel/Image /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/kernel/uImage
267 18:40:20.128793 output: Image Name:
268 18:40:20.129224 output: Created: Mon Nov 11 18:40:19 2024
269 18:40:20.129434 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 18:40:20.129640 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 18:40:20.129842 output: Load Address: 01080000
272 18:40:20.130041 output: Entry Point: 01080000
273 18:40:20.130238 output:
274 18:40:20.130573 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 18:40:20.130839 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 18:40:20.131109 start: 1.6.7 configure-preseed-file (timeout 00:08:45) [common]
277 18:40:20.131362 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 18:40:20.131617 start: 1.6.8 compress-ramdisk (timeout 00:08:45) [common]
279 18:40:20.131874 Building ramdisk /var/lib/lava/dispatcher/tmp/976283/extract-overlay-ramdisk-_b_s8d0m/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/976283/extract-overlay-ramdisk-_b_s8d0m/ramdisk
280 18:40:22.333391 >> 166774 blocks
281 18:40:30.047310 Adding RAMdisk u-boot header.
282 18:40:30.048099 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/976283/extract-overlay-ramdisk-_b_s8d0m/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/976283/extract-overlay-ramdisk-_b_s8d0m/ramdisk.cpio.gz.uboot
283 18:40:30.289009 output: Image Name:
284 18:40:30.289833 output: Created: Mon Nov 11 18:40:30 2024
285 18:40:30.290516 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 18:40:30.291128 output: Data Size: 23427987 Bytes = 22878.89 KiB = 22.34 MiB
287 18:40:30.291733 output: Load Address: 00000000
288 18:40:30.292394 output: Entry Point: 00000000
289 18:40:30.292997 output:
290 18:40:30.294351 rename /var/lib/lava/dispatcher/tmp/976283/extract-overlay-ramdisk-_b_s8d0m/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot
291 18:40:30.295345 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 18:40:30.296247 end: 1.6 prepare-tftp-overlay (duration 00:01:08) [common]
293 18:40:30.297091 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:35) [common]
294 18:40:30.297757 No LXC device requested
295 18:40:30.298544 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 18:40:30.299339 start: 1.8 deploy-device-env (timeout 00:08:35) [common]
297 18:40:30.300147 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 18:40:30.300774 Checking files for TFTP limit of 4294967296 bytes.
299 18:40:30.304418 end: 1 tftp-deploy (duration 00:01:25) [common]
300 18:40:30.304909 start: 2 uboot-action (timeout 00:05:00) [common]
301 18:40:30.305285 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 18:40:30.305689 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 18:40:30.306059 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 18:40:30.306487 Using kernel file from prepare-kernel: 976283/tftp-deploy-a0_gf7ya/kernel/uImage
305 18:40:30.306905 substitutions:
306 18:40:30.307251 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 18:40:30.307540 - {DTB_ADDR}: 0x01070000
308 18:40:30.307817 - {DTB}: 976283/tftp-deploy-a0_gf7ya/dtb/meson-g12b-a311d-libretech-cc.dtb
309 18:40:30.308211 - {INITRD}: 976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot
310 18:40:30.308817 - {KERNEL_ADDR}: 0x01080000
311 18:40:30.309392 - {KERNEL}: 976283/tftp-deploy-a0_gf7ya/kernel/uImage
312 18:40:30.309950 - {LAVA_MAC}: None
313 18:40:30.310634 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/976283/extract-nfsrootfs-jcjeohh8
314 18:40:30.311206 - {NFS_SERVER_IP}: 192.168.6.2
315 18:40:30.311770 - {PRESEED_CONFIG}: None
316 18:40:30.312378 - {PRESEED_LOCAL}: None
317 18:40:30.313000 - {RAMDISK_ADDR}: 0x08000000
318 18:40:30.313558 - {RAMDISK}: 976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot
319 18:40:30.314110 - {ROOT_PART}: None
320 18:40:30.314672 - {ROOT}: None
321 18:40:30.315219 - {SERVER_IP}: 192.168.6.2
322 18:40:30.315773 - {TEE_ADDR}: 0x83000000
323 18:40:30.316361 - {TEE}: None
324 18:40:30.316974 Parsed boot commands:
325 18:40:30.317512 - setenv autoload no
326 18:40:30.318062 - setenv initrd_high 0xffffffff
327 18:40:30.318606 - setenv fdt_high 0xffffffff
328 18:40:30.319161 - dhcp
329 18:40:30.319706 - setenv serverip 192.168.6.2
330 18:40:30.320306 - tftpboot 0x01080000 976283/tftp-deploy-a0_gf7ya/kernel/uImage
331 18:40:30.320868 - tftpboot 0x08000000 976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot
332 18:40:30.321432 - tftpboot 0x01070000 976283/tftp-deploy-a0_gf7ya/dtb/meson-g12b-a311d-libretech-cc.dtb
333 18:40:30.322043 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976283/extract-nfsrootfs-jcjeohh8,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 18:40:30.322617 - bootm 0x01080000 0x08000000 0x01070000
335 18:40:30.323320 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 18:40:30.325542 start: 2.3 connect-device (timeout 00:05:00) [common]
338 18:40:30.326139 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 18:40:30.343369 Setting prompt string to ['lava-test: # ']
340 18:40:30.345379 end: 2.3 connect-device (duration 00:00:00) [common]
341 18:40:30.346210 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 18:40:30.347102 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 18:40:30.347811 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 18:40:30.349337 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 18:40:30.388753 >> OK - accepted request
346 18:40:30.391225 Returned 0 in 0 seconds
347 18:40:30.492770 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 18:40:30.494701 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 18:40:30.495379 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 18:40:30.496029 Setting prompt string to ['Hit any key to stop autoboot']
352 18:40:30.496591 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 18:40:30.498428 Trying 192.168.56.21...
354 18:40:30.498998 Connected to conserv1.
355 18:40:30.499501 Escape character is '^]'.
356 18:40:30.500052
357 18:40:30.500559 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 18:40:30.501071
359 18:40:41.769157 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 18:40:41.769862 bl2_stage_init 0x81
361 18:40:41.770327 hw id: 0x0000 - pwm id 0x01
362 18:40:41.770799 bl2_stage_init 0xc1
363 18:40:41.771253 bl2_stage_init 0x02
364 18:40:41.771708
365 18:40:41.772224 L0:00000000
366 18:40:41.772685 L1:20000703
367 18:40:41.773142 L2:00008067
368 18:40:41.773590 L3:14000000
369 18:40:41.774030 B2:00402000
370 18:40:41.774475 B1:e0f83180
371 18:40:41.774913
372 18:40:41.775354 TE: 58150
373 18:40:41.775782
374 18:40:41.787816 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 18:40:41.788382
376 18:40:41.788827 Board ID = 1
377 18:40:41.789255 Set A53 clk to 24M
378 18:40:41.789679 Set A73 clk to 24M
379 18:40:41.790105 Set clk81 to 24M
380 18:40:41.790529 A53 clk: 1200 MHz
381 18:40:41.790956 A73 clk: 1200 MHz
382 18:40:41.791380 CLK81: 166.6M
383 18:40:41.791803 smccc: 00012aac
384 18:40:41.807596 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 18:40:41.808156 board id: 1
386 18:40:41.812893 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 18:40:41.813766 fw parse done
388 18:40:41.818496 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 18:40:41.862610 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 18:40:41.871942 PIEI prepare done
391 18:40:41.872665 fastboot data load
392 18:40:41.873111 fastboot data verify
393 18:40:41.877545 verify result: 266
394 18:40:41.883045 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 18:40:41.883538 LPDDR4 probe
396 18:40:41.883973 ddr clk to 1584MHz
397 18:40:41.890983 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 18:40:41.928253
399 18:40:41.928734 dmc_version 0001
400 18:40:41.934938 Check phy result
401 18:40:41.940824 INFO : End of CA training
402 18:40:41.941290 INFO : End of initialization
403 18:40:41.946504 INFO : Training has run successfully!
404 18:40:41.946969 Check phy result
405 18:40:41.952110 INFO : End of initialization
406 18:40:41.952579 INFO : End of read enable training
407 18:40:41.957731 INFO : End of fine write leveling
408 18:40:41.963333 INFO : End of Write leveling coarse delay
409 18:40:41.963804 INFO : Training has run successfully!
410 18:40:41.964274 Check phy result
411 18:40:41.968881 INFO : End of initialization
412 18:40:41.969344 INFO : End of read dq deskew training
413 18:40:41.974512 INFO : End of MPR read delay center optimization
414 18:40:41.980104 INFO : End of write delay center optimization
415 18:40:41.985703 INFO : End of read delay center optimization
416 18:40:41.986174 INFO : End of max read latency training
417 18:40:41.991325 INFO : Training has run successfully!
418 18:40:41.991789 1D training succeed
419 18:40:42.000518 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 18:40:42.048212 Check phy result
421 18:40:42.048706 INFO : End of initialization
422 18:40:42.069882 INFO : End of 2D read delay Voltage center optimization
423 18:40:42.090094 INFO : End of 2D read delay Voltage center optimization
424 18:40:42.142139 INFO : End of 2D write delay Voltage center optimization
425 18:40:42.191457 INFO : End of 2D write delay Voltage center optimization
426 18:40:42.197036 INFO : Training has run successfully!
427 18:40:42.197507
428 18:40:42.197950 channel==0
429 18:40:42.202731 RxClkDly_Margin_A0==88 ps 9
430 18:40:42.203212 TxDqDly_Margin_A0==108 ps 11
431 18:40:42.208254 RxClkDly_Margin_A1==88 ps 9
432 18:40:42.208721 TxDqDly_Margin_A1==98 ps 10
433 18:40:42.209160 TrainedVREFDQ_A0==74
434 18:40:42.213855 TrainedVREFDQ_A1==74
435 18:40:42.214319 VrefDac_Margin_A0==25
436 18:40:42.219431 DeviceVref_Margin_A0==40
437 18:40:42.219890 VrefDac_Margin_A1==25
438 18:40:42.220418 DeviceVref_Margin_A1==40
439 18:40:42.220855
440 18:40:42.221286
441 18:40:42.225035 channel==1
442 18:40:42.225502 RxClkDly_Margin_A0==98 ps 10
443 18:40:42.225936 TxDqDly_Margin_A0==98 ps 10
444 18:40:42.230723 RxClkDly_Margin_A1==98 ps 10
445 18:40:42.231194 TxDqDly_Margin_A1==88 ps 9
446 18:40:42.236228 TrainedVREFDQ_A0==77
447 18:40:42.236696 TrainedVREFDQ_A1==77
448 18:40:42.237130 VrefDac_Margin_A0==22
449 18:40:42.241854 DeviceVref_Margin_A0==37
450 18:40:42.242314 VrefDac_Margin_A1==23
451 18:40:42.247419 DeviceVref_Margin_A1==37
452 18:40:42.247878
453 18:40:42.248348 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 18:40:42.253012
455 18:40:42.281051 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
456 18:40:42.281660 2D training succeed
457 18:40:42.286741 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 18:40:42.292238 auto size-- 65535DDR cs0 size: 2048MB
459 18:40:42.292709 DDR cs1 size: 2048MB
460 18:40:42.297894 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 18:40:42.298397 cs0 DataBus test pass
462 18:40:42.303497 cs1 DataBus test pass
463 18:40:42.303968 cs0 AddrBus test pass
464 18:40:42.304440 cs1 AddrBus test pass
465 18:40:42.304870
466 18:40:42.308994 100bdlr_step_size ps== 420
467 18:40:42.309470 result report
468 18:40:42.314756 boot times 0Enable ddr reg access
469 18:40:42.320223 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 18:40:42.333672 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 18:40:42.907417 0.0;M3 CHK:0;cm4_sp_mode 0
472 18:40:42.908122 MVN_1=0x00000000
473 18:40:42.912870 MVN_2=0x00000000
474 18:40:42.918604 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 18:40:42.919108 OPS=0x10
476 18:40:42.919551 ring efuse init
477 18:40:42.920018 chipver efuse init
478 18:40:42.924193 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 18:40:42.929800 [0.018960 Inits done]
480 18:40:42.930263 secure task start!
481 18:40:42.930697 high task start!
482 18:40:42.934375 low task start!
483 18:40:42.934839 run into bl31
484 18:40:42.941014 NOTICE: BL31: v1.3(release):4fc40b1
485 18:40:42.948857 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 18:40:42.949337 NOTICE: BL31: G12A normal boot!
487 18:40:42.974212 NOTICE: BL31: BL33 decompress pass
488 18:40:42.979888 ERROR: Error initializing runtime service opteed_fast
489 18:40:44.212861
490 18:40:44.213506
491 18:40:44.221164 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 18:40:44.221646
493 18:40:44.222090 Model: Libre Computer AML-A311D-CC Alta
494 18:40:44.429703 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 18:40:44.452992 DRAM: 2 GiB (effective 3.8 GiB)
496 18:40:44.596013 Core: 408 devices, 31 uclasses, devicetree: separate
497 18:40:44.601799 WDT: Not starting watchdog@f0d0
498 18:40:44.634115 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 18:40:44.646542 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 18:40:44.650523 ** Bad device specification mmc 0 **
501 18:40:44.661873 Card did not respond to voltage select! : -110
502 18:40:44.669493 ** Bad device specification mmc 0 **
503 18:40:44.669966 Couldn't find partition mmc 0
504 18:40:44.677816 Card did not respond to voltage select! : -110
505 18:40:44.683363 ** Bad device specification mmc 0 **
506 18:40:44.683829 Couldn't find partition mmc 0
507 18:40:44.688394 Error: could not access storage.
508 18:40:45.951443 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 18:40:45.952144 bl2_stage_init 0x01
510 18:40:45.952614 bl2_stage_init 0x81
511 18:40:45.957044 hw id: 0x0000 - pwm id 0x01
512 18:40:45.957530 bl2_stage_init 0xc1
513 18:40:45.957975 bl2_stage_init 0x02
514 18:40:45.958418
515 18:40:45.962674 L0:00000000
516 18:40:45.963168 L1:20000703
517 18:40:45.963608 L2:00008067
518 18:40:45.964082 L3:14000000
519 18:40:45.968344 B2:00402000
520 18:40:45.968815 B1:e0f83180
521 18:40:45.969257
522 18:40:45.969692 TE: 58167
523 18:40:45.970126
524 18:40:45.973867 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 18:40:45.974340
526 18:40:45.974780 Board ID = 1
527 18:40:45.979395 Set A53 clk to 24M
528 18:40:45.979870 Set A73 clk to 24M
529 18:40:45.980357 Set clk81 to 24M
530 18:40:45.985079 A53 clk: 1200 MHz
531 18:40:45.985552 A73 clk: 1200 MHz
532 18:40:45.985987 CLK81: 166.6M
533 18:40:45.986417 smccc: 00012abe
534 18:40:45.990912 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 18:40:45.996488 board id: 1
536 18:40:46.001363 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 18:40:46.012828 fw parse done
538 18:40:46.018821 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 18:40:46.061326 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 18:40:46.072234 PIEI prepare done
541 18:40:46.072707 fastboot data load
542 18:40:46.073149 fastboot data verify
543 18:40:46.077858 verify result: 266
544 18:40:46.083455 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 18:40:46.083926 LPDDR4 probe
546 18:40:46.084412 ddr clk to 1584MHz
547 18:40:46.090669 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 18:40:46.128760
549 18:40:46.129334 dmc_version 0001
550 18:40:46.135418 Check phy result
551 18:40:46.141293 INFO : End of CA training
552 18:40:46.141768 INFO : End of initialization
553 18:40:46.146914 INFO : Training has run successfully!
554 18:40:46.147382 Check phy result
555 18:40:46.152450 INFO : End of initialization
556 18:40:46.152914 INFO : End of read enable training
557 18:40:46.158048 INFO : End of fine write leveling
558 18:40:46.163644 INFO : End of Write leveling coarse delay
559 18:40:46.164183 INFO : Training has run successfully!
560 18:40:46.164628 Check phy result
561 18:40:46.169395 INFO : End of initialization
562 18:40:46.169860 INFO : End of read dq deskew training
563 18:40:46.174981 INFO : End of MPR read delay center optimization
564 18:40:46.180413 INFO : End of write delay center optimization
565 18:40:46.186114 INFO : End of read delay center optimization
566 18:40:46.186576 INFO : End of max read latency training
567 18:40:46.191765 INFO : Training has run successfully!
568 18:40:46.192278 1D training succeed
569 18:40:46.201035 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 18:40:46.248544 Check phy result
571 18:40:46.249080 INFO : End of initialization
572 18:40:46.270248 INFO : End of 2D read delay Voltage center optimization
573 18:40:46.291322 INFO : End of 2D read delay Voltage center optimization
574 18:40:46.343718 INFO : End of 2D write delay Voltage center optimization
575 18:40:46.392849 INFO : End of 2D write delay Voltage center optimization
576 18:40:46.398383 INFO : Training has run successfully!
577 18:40:46.398909
578 18:40:46.399367 channel==0
579 18:40:46.403882 RxClkDly_Margin_A0==88 ps 9
580 18:40:46.404403 TxDqDly_Margin_A0==98 ps 10
581 18:40:46.409528 RxClkDly_Margin_A1==78 ps 8
582 18:40:46.410005 TxDqDly_Margin_A1==98 ps 10
583 18:40:46.410451 TrainedVREFDQ_A0==74
584 18:40:46.415099 TrainedVREFDQ_A1==74
585 18:40:46.415566 VrefDac_Margin_A0==25
586 18:40:46.416033 DeviceVref_Margin_A0==40
587 18:40:46.420707 VrefDac_Margin_A1==26
588 18:40:46.421175 DeviceVref_Margin_A1==40
589 18:40:46.421616
590 18:40:46.422056
591 18:40:46.426476 channel==1
592 18:40:46.426947 RxClkDly_Margin_A0==98 ps 10
593 18:40:46.427387 TxDqDly_Margin_A0==98 ps 10
594 18:40:46.431897 RxClkDly_Margin_A1==88 ps 9
595 18:40:46.432405 TxDqDly_Margin_A1==88 ps 9
596 18:40:46.437576 TrainedVREFDQ_A0==77
597 18:40:46.438062 TrainedVREFDQ_A1==77
598 18:40:46.438506 VrefDac_Margin_A0==22
599 18:40:46.443091 DeviceVref_Margin_A0==37
600 18:40:46.443568 VrefDac_Margin_A1==24
601 18:40:46.448791 DeviceVref_Margin_A1==37
602 18:40:46.449271
603 18:40:46.449714 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 18:40:46.450149
605 18:40:46.482288 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
606 18:40:46.482896 2D training succeed
607 18:40:46.487783 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 18:40:46.493385 auto size-- 65535DDR cs0 size: 2048MB
609 18:40:46.493928 DDR cs1 size: 2048MB
610 18:40:46.498948 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 18:40:46.499431 cs0 DataBus test pass
612 18:40:46.504624 cs1 DataBus test pass
613 18:40:46.505143 cs0 AddrBus test pass
614 18:40:46.505553 cs1 AddrBus test pass
615 18:40:46.505956
616 18:40:46.510407 100bdlr_step_size ps== 420
617 18:40:46.510947 result report
618 18:40:46.515890 boot times 0Enable ddr reg access
619 18:40:46.521258 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 18:40:46.533795 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 18:40:47.108489 0.0;M3 CHK:0;cm4_sp_mode 0
622 18:40:47.109092 MVN_1=0x00000000
623 18:40:47.113939 MVN_2=0x00000000
624 18:40:47.119765 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 18:40:47.120363 OPS=0x10
626 18:40:47.120844 ring efuse init
627 18:40:47.122094 chipver efuse init
628 18:40:47.125188 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 18:40:47.130766 [0.018961 Inits done]
630 18:40:47.131304 secure task start!
631 18:40:47.131771 high task start!
632 18:40:47.135407 low task start!
633 18:40:47.135939 run into bl31
634 18:40:47.142025 NOTICE: BL31: v1.3(release):4fc40b1
635 18:40:47.149820 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 18:40:47.150365 NOTICE: BL31: G12A normal boot!
637 18:40:47.175247 NOTICE: BL31: BL33 decompress pass
638 18:40:47.180877 ERROR: Error initializing runtime service opteed_fast
639 18:40:48.413897
640 18:40:48.414693
641 18:40:48.421324 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 18:40:48.422126
643 18:40:48.422744 Model: Libre Computer AML-A311D-CC Alta
644 18:40:48.629724 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 18:40:48.654155 DRAM: 2 GiB (effective 3.8 GiB)
646 18:40:48.797048 Core: 408 devices, 31 uclasses, devicetree: separate
647 18:40:48.801935 WDT: Not starting watchdog@f0d0
648 18:40:48.835163 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 18:40:48.847666 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 18:40:48.852621 ** Bad device specification mmc 0 **
651 18:40:48.862948 Card did not respond to voltage select! : -110
652 18:40:48.870653 ** Bad device specification mmc 0 **
653 18:40:48.871344 Couldn't find partition mmc 0
654 18:40:48.878941 Card did not respond to voltage select! : -110
655 18:40:48.884521 ** Bad device specification mmc 0 **
656 18:40:48.885063 Couldn't find partition mmc 0
657 18:40:48.889611 Error: could not access storage.
658 18:40:49.232032 Net: eth0: ethernet@ff3f0000
659 18:40:49.232877 starting USB...
660 18:40:49.483867 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 18:40:49.484847 Starting the controller
662 18:40:49.490802 USB XHCI 1.10
663 18:40:51.203183 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 18:40:51.204039 bl2_stage_init 0x01
665 18:40:51.204618 bl2_stage_init 0x81
666 18:40:51.208840 hw id: 0x0000 - pwm id 0x01
667 18:40:51.209431 bl2_stage_init 0xc1
668 18:40:51.209951 bl2_stage_init 0x02
669 18:40:51.210459
670 18:40:51.214334 L0:00000000
671 18:40:51.214922 L1:20000703
672 18:40:51.215436 L2:00008067
673 18:40:51.215945 L3:14000000
674 18:40:51.219903 B2:00402000
675 18:40:51.220518 B1:e0f83180
676 18:40:51.221036
677 18:40:51.221546 TE: 58124
678 18:40:51.222056
679 18:40:51.225520 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 18:40:51.226099
681 18:40:51.226621 Board ID = 1
682 18:40:51.231126 Set A53 clk to 24M
683 18:40:51.231706 Set A73 clk to 24M
684 18:40:51.232259 Set clk81 to 24M
685 18:40:51.236809 A53 clk: 1200 MHz
686 18:40:51.237372 A73 clk: 1200 MHz
687 18:40:51.237884 CLK81: 166.6M
688 18:40:51.238388 smccc: 00012a92
689 18:40:51.242325 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 18:40:51.247900 board id: 1
691 18:40:51.253906 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 18:40:51.264618 fw parse done
693 18:40:51.270480 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 18:40:51.313065 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 18:40:51.324083 PIEI prepare done
696 18:40:51.324828 fastboot data load
697 18:40:51.325362 fastboot data verify
698 18:40:51.329630 verify result: 266
699 18:40:51.335250 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 18:40:51.335828 LPDDR4 probe
701 18:40:51.336390 ddr clk to 1584MHz
702 18:40:51.343233 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 18:40:51.380568
704 18:40:51.381324 dmc_version 0001
705 18:40:51.387152 Check phy result
706 18:40:51.392990 INFO : End of CA training
707 18:40:51.393564 INFO : End of initialization
708 18:40:51.398616 INFO : Training has run successfully!
709 18:40:51.399188 Check phy result
710 18:40:51.404229 INFO : End of initialization
711 18:40:51.404795 INFO : End of read enable training
712 18:40:51.409884 INFO : End of fine write leveling
713 18:40:51.415402 INFO : End of Write leveling coarse delay
714 18:40:51.415976 INFO : Training has run successfully!
715 18:40:51.416671 Check phy result
716 18:40:51.421030 INFO : End of initialization
717 18:40:51.421623 INFO : End of read dq deskew training
718 18:40:51.426619 INFO : End of MPR read delay center optimization
719 18:40:51.432236 INFO : End of write delay center optimization
720 18:40:51.437895 INFO : End of read delay center optimization
721 18:40:51.438512 INFO : End of max read latency training
722 18:40:51.443366 INFO : Training has run successfully!
723 18:40:51.443955 1D training succeed
724 18:40:51.452581 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 18:40:51.499679 Check phy result
726 18:40:51.500516 INFO : End of initialization
727 18:40:51.522128 INFO : End of 2D read delay Voltage center optimization
728 18:40:51.542370 INFO : End of 2D read delay Voltage center optimization
729 18:40:51.594481 INFO : End of 2D write delay Voltage center optimization
730 18:40:51.643795 INFO : End of 2D write delay Voltage center optimization
731 18:40:51.649364 INFO : Training has run successfully!
732 18:40:51.650095
733 18:40:51.650676 channel==0
734 18:40:51.654993 RxClkDly_Margin_A0==88 ps 9
735 18:40:51.655612 TxDqDly_Margin_A0==98 ps 10
736 18:40:51.660505 RxClkDly_Margin_A1==88 ps 9
737 18:40:51.661178 TxDqDly_Margin_A1==98 ps 10
738 18:40:51.661725 TrainedVREFDQ_A0==74
739 18:40:51.666086 TrainedVREFDQ_A1==74
740 18:40:51.666704 VrefDac_Margin_A0==25
741 18:40:51.667243 DeviceVref_Margin_A0==40
742 18:40:51.671659 VrefDac_Margin_A1==25
743 18:40:51.672523 DeviceVref_Margin_A1==40
744 18:40:51.673094
745 18:40:51.673616
746 18:40:51.677252 channel==1
747 18:40:51.677859 RxClkDly_Margin_A0==98 ps 10
748 18:40:51.678382 TxDqDly_Margin_A0==98 ps 10
749 18:40:51.683298 RxClkDly_Margin_A1==98 ps 10
750 18:40:51.683929 TxDqDly_Margin_A1==88 ps 9
751 18:40:51.688474 TrainedVREFDQ_A0==77
752 18:40:51.689139 TrainedVREFDQ_A1==77
753 18:40:51.689723 VrefDac_Margin_A0==22
754 18:40:51.694168 DeviceVref_Margin_A0==37
755 18:40:51.694839 VrefDac_Margin_A1==22
756 18:40:51.699715 DeviceVref_Margin_A1==37
757 18:40:51.700361
758 18:40:51.700792 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 18:40:51.705384
760 18:40:51.733258 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 18:40:51.733965 2D training succeed
762 18:40:51.739117 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 18:40:51.744642 auto size-- 65535DDR cs0 size: 2048MB
764 18:40:51.745203 DDR cs1 size: 2048MB
765 18:40:51.750144 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 18:40:51.750668 cs0 DataBus test pass
767 18:40:51.755777 cs1 DataBus test pass
768 18:40:51.756381 cs0 AddrBus test pass
769 18:40:51.756805 cs1 AddrBus test pass
770 18:40:51.757214
771 18:40:51.761354 100bdlr_step_size ps== 420
772 18:40:51.761905 result report
773 18:40:51.766934 boot times 0Enable ddr reg access
774 18:40:51.772432 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 18:40:51.785860 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 18:40:52.359441 0.0;M3 CHK:0;cm4_sp_mode 0
777 18:40:52.360165 MVN_1=0x00000000
778 18:40:52.365046 MVN_2=0x00000000
779 18:40:52.370690 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 18:40:52.371267 OPS=0x10
781 18:40:52.371673 ring efuse init
782 18:40:52.372109 chipver efuse init
783 18:40:52.376287 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 18:40:52.381964 [0.018961 Inits done]
785 18:40:52.382450 secure task start!
786 18:40:52.382845 high task start!
787 18:40:52.386404 low task start!
788 18:40:52.386876 run into bl31
789 18:40:52.393103 NOTICE: BL31: v1.3(release):4fc40b1
790 18:40:52.400924 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 18:40:52.401420 NOTICE: BL31: G12A normal boot!
792 18:40:52.426346 NOTICE: BL31: BL33 decompress pass
793 18:40:52.432087 ERROR: Error initializing runtime service opteed_fast
794 18:40:53.664941
795 18:40:53.665563
796 18:40:53.673312 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 18:40:53.673809
798 18:40:53.674211 Model: Libre Computer AML-A311D-CC Alta
799 18:40:53.881748 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 18:40:53.905139 DRAM: 2 GiB (effective 3.8 GiB)
801 18:40:54.048305 Core: 408 devices, 31 uclasses, devicetree: separate
802 18:40:54.054065 WDT: Not starting watchdog@f0d0
803 18:40:54.086273 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 18:40:54.098696 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 18:40:54.103710 ** Bad device specification mmc 0 **
806 18:40:54.114041 Card did not respond to voltage select! : -110
807 18:40:54.121698 ** Bad device specification mmc 0 **
808 18:40:54.122210 Couldn't find partition mmc 0
809 18:40:54.130043 Card did not respond to voltage select! : -110
810 18:40:54.135549 ** Bad device specification mmc 0 **
811 18:40:54.136081 Couldn't find partition mmc 0
812 18:40:54.140585 Error: could not access storage.
813 18:40:54.483030 Net: eth0: ethernet@ff3f0000
814 18:40:54.483657 starting USB...
815 18:40:54.734886 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 18:40:54.735483 Starting the controller
817 18:40:54.741862 USB XHCI 1.10
818 18:40:56.901975 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 18:40:56.902585 bl2_stage_init 0x01
820 18:40:56.903012 bl2_stage_init 0x81
821 18:40:56.907745 hw id: 0x0000 - pwm id 0x01
822 18:40:56.908269 bl2_stage_init 0xc1
823 18:40:56.908691 bl2_stage_init 0x02
824 18:40:56.909095
825 18:40:56.913032 L0:00000000
826 18:40:56.913508 L1:20000703
827 18:40:56.913915 L2:00008067
828 18:40:56.914309 L3:14000000
829 18:40:56.918752 B2:00402000
830 18:40:56.919220 B1:e0f83180
831 18:40:56.919624
832 18:40:56.920066 TE: 58167
833 18:40:56.920476
834 18:40:56.924151 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 18:40:56.924625
836 18:40:56.925034 Board ID = 1
837 18:40:56.929664 Set A53 clk to 24M
838 18:40:56.930133 Set A73 clk to 24M
839 18:40:56.930540 Set clk81 to 24M
840 18:40:56.935278 A53 clk: 1200 MHz
841 18:40:56.935743 A73 clk: 1200 MHz
842 18:40:56.936185 CLK81: 166.6M
843 18:40:56.936593 smccc: 00012abe
844 18:40:56.940883 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 18:40:56.946467 board id: 1
846 18:40:56.951373 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 18:40:56.963000 fw parse done
848 18:40:56.968070 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 18:40:57.010703 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 18:40:57.022598 PIEI prepare done
851 18:40:57.022976 fastboot data load
852 18:40:57.023236 fastboot data verify
853 18:40:57.028308 verify result: 266
854 18:40:57.033800 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 18:40:57.034342 LPDDR4 probe
856 18:40:57.034770 ddr clk to 1584MHz
857 18:40:57.041667 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 18:40:57.077985
859 18:40:57.078570 dmc_version 0001
860 18:40:57.085782 Check phy result
861 18:40:57.091536 INFO : End of CA training
862 18:40:57.092296 INFO : End of initialization
863 18:40:57.097131 INFO : Training has run successfully!
864 18:40:57.097622 Check phy result
865 18:40:57.102771 INFO : End of initialization
866 18:40:57.103310 INFO : End of read enable training
867 18:40:57.108404 INFO : End of fine write leveling
868 18:40:57.114022 INFO : End of Write leveling coarse delay
869 18:40:57.114553 INFO : Training has run successfully!
870 18:40:57.114997 Check phy result
871 18:40:57.119511 INFO : End of initialization
872 18:40:57.120046 INFO : End of read dq deskew training
873 18:40:57.125125 INFO : End of MPR read delay center optimization
874 18:40:57.130755 INFO : End of write delay center optimization
875 18:40:57.136373 INFO : End of read delay center optimization
876 18:40:57.136864 INFO : End of max read latency training
877 18:40:57.141927 INFO : Training has run successfully!
878 18:40:57.142414 1D training succeed
879 18:40:57.151072 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 18:40:57.198962 Check phy result
881 18:40:57.199379 INFO : End of initialization
882 18:40:57.219494 INFO : End of 2D read delay Voltage center optimization
883 18:40:57.240168 INFO : End of 2D read delay Voltage center optimization
884 18:40:57.292719 INFO : End of 2D write delay Voltage center optimization
885 18:40:57.342096 INFO : End of 2D write delay Voltage center optimization
886 18:40:57.347734 INFO : Training has run successfully!
887 18:40:57.348218
888 18:40:57.348536 channel==0
889 18:40:57.353488 RxClkDly_Margin_A0==88 ps 9
890 18:40:57.354123 TxDqDly_Margin_A0==98 ps 10
891 18:40:57.358952 RxClkDly_Margin_A1==88 ps 9
892 18:40:57.359711 TxDqDly_Margin_A1==98 ps 10
893 18:40:57.360375 TrainedVREFDQ_A0==74
894 18:40:57.365115 TrainedVREFDQ_A1==74
895 18:40:57.365577 VrefDac_Margin_A0==25
896 18:40:57.365823 DeviceVref_Margin_A0==40
897 18:40:57.370202 VrefDac_Margin_A1==26
898 18:40:57.370832 DeviceVref_Margin_A1==40
899 18:40:57.371236
900 18:40:57.371553
901 18:40:57.375863 channel==1
902 18:40:57.376510 RxClkDly_Margin_A0==98 ps 10
903 18:40:57.376921 TxDqDly_Margin_A0==88 ps 9
904 18:40:57.381446 RxClkDly_Margin_A1==88 ps 9
905 18:40:57.382075 TxDqDly_Margin_A1==88 ps 9
906 18:40:57.386983 TrainedVREFDQ_A0==76
907 18:40:57.387591 TrainedVREFDQ_A1==77
908 18:40:57.387966 VrefDac_Margin_A0==22
909 18:40:57.392627 DeviceVref_Margin_A0==38
910 18:40:57.393159 VrefDac_Margin_A1==24
911 18:40:57.398121 DeviceVref_Margin_A1==37
912 18:40:57.398685
913 18:40:57.399131 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 18:40:57.399569
915 18:40:57.431808 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
916 18:40:57.432451 2D training succeed
917 18:40:57.437263 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 18:40:57.442881 auto size-- 65535DDR cs0 size: 2048MB
919 18:40:57.443388 DDR cs1 size: 2048MB
920 18:40:57.448524 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 18:40:57.448856 cs0 DataBus test pass
922 18:40:57.453899 cs1 DataBus test pass
923 18:40:57.454203 cs0 AddrBus test pass
924 18:40:57.454429 cs1 AddrBus test pass
925 18:40:57.454651
926 18:40:57.459650 100bdlr_step_size ps== 420
927 18:40:57.459970 result report
928 18:40:57.465169 boot times 0Enable ddr reg access
929 18:40:57.469614 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 18:40:57.483024 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 18:40:58.057717 0.0;M3 CHK:0;cm4_sp_mode 0
932 18:40:58.058160 MVN_1=0x00000000
933 18:40:58.063109 MVN_2=0x00000000
934 18:40:58.068874 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 18:40:58.069212 OPS=0x10
936 18:40:58.069472 ring efuse init
937 18:40:58.069718 chipver efuse init
938 18:40:58.074479 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 18:40:58.080130 [0.018961 Inits done]
940 18:40:58.080463 secure task start!
941 18:40:58.080709 high task start!
942 18:40:58.084803 low task start!
943 18:40:58.085130 run into bl31
944 18:40:58.091301 NOTICE: BL31: v1.3(release):4fc40b1
945 18:40:58.099333 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 18:40:58.099733 NOTICE: BL31: G12A normal boot!
947 18:40:58.124698 NOTICE: BL31: BL33 decompress pass
948 18:40:58.130281 ERROR: Error initializing runtime service opteed_fast
949 18:40:59.363220
950 18:40:59.363846
951 18:40:59.371642 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 18:40:59.372196
953 18:40:59.372630 Model: Libre Computer AML-A311D-CC Alta
954 18:40:59.580114 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 18:40:59.603468 DRAM: 2 GiB (effective 3.8 GiB)
956 18:40:59.746437 Core: 408 devices, 31 uclasses, devicetree: separate
957 18:40:59.752343 WDT: Not starting watchdog@f0d0
958 18:40:59.784571 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 18:40:59.797050 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 18:40:59.801999 ** Bad device specification mmc 0 **
961 18:40:59.812387 Card did not respond to voltage select! : -110
962 18:40:59.820063 ** Bad device specification mmc 0 **
963 18:40:59.820604 Couldn't find partition mmc 0
964 18:40:59.828314 Card did not respond to voltage select! : -110
965 18:40:59.833806 ** Bad device specification mmc 0 **
966 18:40:59.834294 Couldn't find partition mmc 0
967 18:40:59.838927 Error: could not access storage.
968 18:41:00.181371 Net: eth0: ethernet@ff3f0000
969 18:41:00.181990 starting USB...
970 18:41:00.433275 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 18:41:00.433859 Starting the controller
972 18:41:00.440133 USB XHCI 1.10
973 18:41:02.301843 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
974 18:41:02.302499 bl2_stage_init 0x81
975 18:41:02.307432 hw id: 0x0000 - pwm id 0x01
976 18:41:02.307933 bl2_stage_init 0xc1
977 18:41:02.308406 bl2_stage_init 0x02
978 18:41:02.308822
979 18:41:02.313094 L0:00000000
980 18:41:02.313583 L1:20000703
981 18:41:02.313994 L2:00008067
982 18:41:02.314393 L3:14000000
983 18:41:02.314790 B2:00402000
984 18:41:02.318609 B1:e0f83180
985 18:41:02.319091
986 18:41:02.319505 TE: 58150
987 18:41:02.319910
988 18:41:02.324327 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
989 18:41:02.324810
990 18:41:02.325222 Board ID = 1
991 18:41:02.329744 Set A53 clk to 24M
992 18:41:02.330245 Set A73 clk to 24M
993 18:41:02.330654 Set clk81 to 24M
994 18:41:02.335358 A53 clk: 1200 MHz
995 18:41:02.335832 A73 clk: 1200 MHz
996 18:41:02.336271 CLK81: 166.6M
997 18:41:02.336672 smccc: 00012aab
998 18:41:02.340877 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
999 18:41:02.346562 board id: 1
1000 18:41:02.352407 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1001 18:41:02.363041 fw parse done
1002 18:41:02.369031 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1003 18:41:02.411425 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1004 18:41:02.422324 PIEI prepare done
1005 18:41:02.422698 fastboot data load
1006 18:41:02.422926 fastboot data verify
1007 18:41:02.427922 verify result: 266
1008 18:41:02.433565 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1009 18:41:02.433930 LPDDR4 probe
1010 18:41:02.434153 ddr clk to 1584MHz
1011 18:41:02.441548 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1012 18:41:02.478048
1013 18:41:02.478674 dmc_version 0001
1014 18:41:02.484662 Check phy result
1015 18:41:02.491516 INFO : End of CA training
1016 18:41:02.492094 INFO : End of initialization
1017 18:41:02.497147 INFO : Training has run successfully!
1018 18:41:02.497821 Check phy result
1019 18:41:02.502765 INFO : End of initialization
1020 18:41:02.503378 INFO : End of read enable training
1021 18:41:02.506108 INFO : End of fine write leveling
1022 18:41:02.511966 INFO : End of Write leveling coarse delay
1023 18:41:02.517194 INFO : Training has run successfully!
1024 18:41:02.517715 Check phy result
1025 18:41:02.518142 INFO : End of initialization
1026 18:41:02.523330 INFO : End of read dq deskew training
1027 18:41:02.526784 INFO : End of MPR read delay center optimization
1028 18:41:02.532400 INFO : End of write delay center optimization
1029 18:41:02.537991 INFO : End of read delay center optimization
1030 18:41:02.538382 INFO : End of max read latency training
1031 18:41:02.543321 INFO : Training has run successfully!
1032 18:41:02.543724 1D training succeed
1033 18:41:02.551039 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1034 18:41:02.599325 Check phy result
1035 18:41:02.600042 INFO : End of initialization
1036 18:41:02.620537 INFO : End of 2D read delay Voltage center optimization
1037 18:41:02.639810 INFO : End of 2D read delay Voltage center optimization
1038 18:41:02.691940 INFO : End of 2D write delay Voltage center optimization
1039 18:41:02.742148 INFO : End of 2D write delay Voltage center optimization
1040 18:41:02.747649 INFO : Training has run successfully!
1041 18:41:02.748142
1042 18:41:02.748426 channel==0
1043 18:41:02.753419 RxClkDly_Margin_A0==88 ps 9
1044 18:41:02.753878 TxDqDly_Margin_A0==98 ps 10
1045 18:41:02.759015 RxClkDly_Margin_A1==88 ps 9
1046 18:41:02.759646 TxDqDly_Margin_A1==88 ps 9
1047 18:41:02.760122 TrainedVREFDQ_A0==74
1048 18:41:02.764727 TrainedVREFDQ_A1==74
1049 18:41:02.765136 VrefDac_Margin_A0==25
1050 18:41:02.765346 DeviceVref_Margin_A0==40
1051 18:41:02.770082 VrefDac_Margin_A1==25
1052 18:41:02.770796 DeviceVref_Margin_A1==40
1053 18:41:02.771336
1054 18:41:02.771852
1055 18:41:02.772456 channel==1
1056 18:41:02.775683 RxClkDly_Margin_A0==98 ps 10
1057 18:41:02.776345 TxDqDly_Margin_A0==88 ps 9
1058 18:41:02.781282 RxClkDly_Margin_A1==98 ps 10
1059 18:41:02.781939 TxDqDly_Margin_A1==88 ps 9
1060 18:41:02.786831 TrainedVREFDQ_A0==77
1061 18:41:02.787534 TrainedVREFDQ_A1==77
1062 18:41:02.788126 VrefDac_Margin_A0==22
1063 18:41:02.792418 DeviceVref_Margin_A0==37
1064 18:41:02.793087 VrefDac_Margin_A1==22
1065 18:41:02.797851 DeviceVref_Margin_A1==37
1066 18:41:02.798254
1067 18:41:02.798501 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1068 18:41:02.798739
1069 18:41:02.831516 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1070 18:41:02.832000 2D training succeed
1071 18:41:02.836992 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1072 18:41:02.842572 auto size-- 65535DDR cs0 size: 2048MB
1073 18:41:02.842994 DDR cs1 size: 2048MB
1074 18:41:02.848251 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1075 18:41:02.848654 cs0 DataBus test pass
1076 18:41:02.853886 cs1 DataBus test pass
1077 18:41:02.854301 cs0 AddrBus test pass
1078 18:41:02.854539 cs1 AddrBus test pass
1079 18:41:02.854762
1080 18:41:02.859582 100bdlr_step_size ps== 420
1081 18:41:02.860023 result report
1082 18:41:02.864991 boot times 0Enable ddr reg access
1083 18:41:02.869379 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1084 18:41:02.883964 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1085 18:41:03.457514 0.0;M3 CHK:0;cm4_sp_mode 0
1086 18:41:03.457981 MVN_1=0x00000000
1087 18:41:03.462914 MVN_2=0x00000000
1088 18:41:03.468653 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1089 18:41:03.469614 OPS=0x10
1090 18:41:03.470073 ring efuse init
1091 18:41:03.470313 chipver efuse init
1092 18:41:03.474340 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1093 18:41:03.481362 [0.018961 Inits done]
1094 18:41:03.481975 secure task start!
1095 18:41:03.482389 high task start!
1096 18:41:03.484623 low task start!
1097 18:41:03.485115 run into bl31
1098 18:41:03.492115 NOTICE: BL31: v1.3(release):4fc40b1
1099 18:41:03.498995 NOTICE: BL31: Built : 15:58:17, May 22 2019
1100 18:41:03.499588 NOTICE: BL31: G12A normal boot!
1101 18:41:03.527205 NOTICE: BL31: BL33 decompress pass
1102 18:41:03.530911 ERROR: Error initializing runtime service opteed_fast
1103 18:41:04.763033
1104 18:41:04.763660
1105 18:41:04.771294 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1106 18:41:04.771777
1107 18:41:04.772225 Model: Libre Computer AML-A311D-CC Alta
1108 18:41:04.979909 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1109 18:41:05.003200 DRAM: 2 GiB (effective 3.8 GiB)
1110 18:41:05.146173 Core: 408 devices, 31 uclasses, devicetree: separate
1111 18:41:05.152064 WDT: Not starting watchdog@f0d0
1112 18:41:05.184244 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1113 18:41:05.196744 Loading Environment from FAT... Card did not respond to voltage select! : -110
1114 18:41:05.201753 ** Bad device specification mmc 0 **
1115 18:41:05.211937 Card did not respond to voltage select! : -110
1116 18:41:05.219628 ** Bad device specification mmc 0 **
1117 18:41:05.220154 Couldn't find partition mmc 0
1118 18:41:05.227947 Card did not respond to voltage select! : -110
1119 18:41:05.233496 ** Bad device specification mmc 0 **
1120 18:41:05.233996 Couldn't find partition mmc 0
1121 18:41:05.238559 Error: could not access storage.
1122 18:41:05.581035 Net: eth0: ethernet@ff3f0000
1123 18:41:05.581626 starting USB...
1124 18:41:05.832872 Bus usb@ff500000: Register 3000140 NbrPorts 3
1125 18:41:05.833281 Starting the controller
1126 18:41:05.839808 USB XHCI 1.10
1127 18:41:07.396928 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1128 18:41:07.405252 scanning usb for storage devices... 0 Storage Device(s) found
1130 18:41:07.457102 Hit any key to stop autoboot: 1
1131 18:41:07.458100 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1132 18:41:07.458758 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1133 18:41:07.459330 Setting prompt string to ['=>']
1134 18:41:07.459897 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1135 18:41:07.472682 0
1136 18:41:07.473728 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1137 18:41:07.474303 Sending with 10 millisecond of delay
1139 18:41:08.609685 => setenv autoload no
1140 18:41:08.620566 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1141 18:41:08.626065 setenv autoload no
1142 18:41:08.626990 Sending with 10 millisecond of delay
1144 18:41:10.424878 => setenv initrd_high 0xffffffff
1145 18:41:10.435699 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1146 18:41:10.436690 setenv initrd_high 0xffffffff
1147 18:41:10.437466 Sending with 10 millisecond of delay
1149 18:41:12.054818 => setenv fdt_high 0xffffffff
1150 18:41:12.065719 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1151 18:41:12.066698 setenv fdt_high 0xffffffff
1152 18:41:12.067580 Sending with 10 millisecond of delay
1154 18:41:12.360049 => dhcp
1155 18:41:12.370910 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1156 18:41:12.371930 dhcp
1157 18:41:12.372528 Speed: 1000, full duplex
1158 18:41:12.373019 BOOTP broadcast 1
1159 18:41:12.382784 DHCP client bound to address 192.168.6.27 (13 ms)
1160 18:41:12.383663 Sending with 10 millisecond of delay
1162 18:41:14.061290 => setenv serverip 192.168.6.2
1163 18:41:14.072153 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1164 18:41:14.073149 setenv serverip 192.168.6.2
1165 18:41:14.073935 Sending with 10 millisecond of delay
1167 18:41:17.800212 => tftpboot 0x01080000 976283/tftp-deploy-a0_gf7ya/kernel/uImage
1168 18:41:17.811556 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1169 18:41:17.812665 tftpboot 0x01080000 976283/tftp-deploy-a0_gf7ya/kernel/uImage
1170 18:41:17.813188 Speed: 1000, full duplex
1171 18:41:17.813849 Using ethernet@ff3f0000 device
1172 18:41:17.814427 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1173 18:41:17.819431 Filename '976283/tftp-deploy-a0_gf7ya/kernel/uImage'.
1174 18:41:17.823336 Load address: 0x1080000
1175 18:41:20.871245 Loading: *################################################## 43.6 MiB
1176 18:41:20.871928 14.3 MiB/s
1177 18:41:20.872400 done
1178 18:41:20.875592 Bytes transferred = 45713984 (2b98a40 hex)
1179 18:41:20.876486 Sending with 10 millisecond of delay
1181 18:41:25.568197 => tftpboot 0x08000000 976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot
1182 18:41:25.578979 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1183 18:41:25.580072 tftpboot 0x08000000 976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot
1184 18:41:25.580578 Speed: 1000, full duplex
1185 18:41:25.581038 Using ethernet@ff3f0000 device
1186 18:41:25.581829 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1187 18:41:25.593580 Filename '976283/tftp-deploy-a0_gf7ya/ramdisk/ramdisk.cpio.gz.uboot'.
1188 18:41:25.594015 Load address: 0x8000000
1189 18:41:30.306118 Loading: *########### UDP wrong checksum 000000ff 0000a78d
1190 18:41:30.365038 UDP wrong checksum 000000ff 00003380
1191 18:41:32.243165 T ###################################### UDP wrong checksum 00000005 0000ae4b
1192 18:41:37.245012 T UDP wrong checksum 00000005 0000ae4b
1193 18:41:47.247104 T T UDP wrong checksum 00000005 0000ae4b
1194 18:42:07.250985 T T T T UDP wrong checksum 00000005 0000ae4b
1195 18:42:22.255048 T T
1196 18:42:22.255682 Retry count exceeded; starting again
1198 18:42:22.257155 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1201 18:42:22.259055 end: 2.4 uboot-commands (duration 00:01:52) [common]
1203 18:42:22.260588 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1205 18:42:22.261649 end: 2 uboot-action (duration 00:01:52) [common]
1207 18:42:22.263156 Cleaning after the job
1208 18:42:22.263700 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/ramdisk
1209 18:42:22.264979 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/kernel
1210 18:42:22.309951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/dtb
1211 18:42:22.310741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/nfsrootfs
1212 18:42:22.477964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976283/tftp-deploy-a0_gf7ya/modules
1213 18:42:22.499308 start: 4.1 power-off (timeout 00:00:30) [common]
1214 18:42:22.500007 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1215 18:42:22.538036 >> OK - accepted request
1216 18:42:22.540518 Returned 0 in 0 seconds
1217 18:42:22.641233 end: 4.1 power-off (duration 00:00:00) [common]
1219 18:42:22.642137 start: 4.2 read-feedback (timeout 00:10:00) [common]
1220 18:42:22.642770 Listened to connection for namespace 'common' for up to 1s
1221 18:42:23.643717 Finalising connection for namespace 'common'
1222 18:42:23.644218 Disconnecting from shell: Finalise
1223 18:42:23.644499 =>
1224 18:42:23.745163 end: 4.2 read-feedback (duration 00:00:01) [common]
1225 18:42:23.745517 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/976283
1226 18:42:26.823501 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/976283
1227 18:42:26.824111 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.