Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:43:42.680843 lava-dispatcher, installed at version: 2024.01
2 17:43:42.681648 start: 0 validate
3 17:43:42.682135 Start time: 2024-11-11 17:43:42.682103+00:00 (UTC)
4 17:43:42.682671 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:43:42.683201 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:43:42.723871 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:43:42.724467 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:43:42.754910 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:43:42.755537 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:43:42.785813 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:43:42.786308 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:43:42.817255 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:43:42.817772 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:43:42.852384 validate duration: 0.17
16 17:43:42.853190 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:43:42.853505 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:43:42.853807 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:43:42.854357 Not decompressing ramdisk as can be used compressed.
20 17:43:42.854784 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 17:43:42.855055 saving as /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/ramdisk/initrd.cpio.gz
22 17:43:42.855311 total size: 5628169 (5 MB)
23 17:43:42.890323 progress 0 % (0 MB)
24 17:43:42.894680 progress 5 % (0 MB)
25 17:43:42.898724 progress 10 % (0 MB)
26 17:43:42.902300 progress 15 % (0 MB)
27 17:43:42.906213 progress 20 % (1 MB)
28 17:43:42.909712 progress 25 % (1 MB)
29 17:43:42.913626 progress 30 % (1 MB)
30 17:43:42.917484 progress 35 % (1 MB)
31 17:43:42.921104 progress 40 % (2 MB)
32 17:43:42.924970 progress 45 % (2 MB)
33 17:43:42.928488 progress 50 % (2 MB)
34 17:43:42.932416 progress 55 % (2 MB)
35 17:43:42.936316 progress 60 % (3 MB)
36 17:43:42.939840 progress 65 % (3 MB)
37 17:43:42.943682 progress 70 % (3 MB)
38 17:43:42.947278 progress 75 % (4 MB)
39 17:43:42.951068 progress 80 % (4 MB)
40 17:43:42.954389 progress 85 % (4 MB)
41 17:43:42.957993 progress 90 % (4 MB)
42 17:43:42.961576 progress 95 % (5 MB)
43 17:43:42.964861 progress 100 % (5 MB)
44 17:43:42.965511 5 MB downloaded in 0.11 s (48.72 MB/s)
45 17:43:42.966054 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:43:42.966938 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:43:42.967228 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:43:42.967499 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:43:42.967968 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/kernel/Image
51 17:43:42.968248 saving as /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/kernel/Image
52 17:43:42.968459 total size: 45713920 (43 MB)
53 17:43:42.968668 No compression specified
54 17:43:43.007099 progress 0 % (0 MB)
55 17:43:43.034656 progress 5 % (2 MB)
56 17:43:43.062162 progress 10 % (4 MB)
57 17:43:43.090162 progress 15 % (6 MB)
58 17:43:43.117839 progress 20 % (8 MB)
59 17:43:43.144866 progress 25 % (10 MB)
60 17:43:43.172405 progress 30 % (13 MB)
61 17:43:43.199447 progress 35 % (15 MB)
62 17:43:43.227049 progress 40 % (17 MB)
63 17:43:43.254714 progress 45 % (19 MB)
64 17:43:43.282991 progress 50 % (21 MB)
65 17:43:43.311065 progress 55 % (24 MB)
66 17:43:43.339063 progress 60 % (26 MB)
67 17:43:43.366630 progress 65 % (28 MB)
68 17:43:43.394925 progress 70 % (30 MB)
69 17:43:43.422851 progress 75 % (32 MB)
70 17:43:43.451252 progress 80 % (34 MB)
71 17:43:43.478756 progress 85 % (37 MB)
72 17:43:43.506771 progress 90 % (39 MB)
73 17:43:43.534597 progress 95 % (41 MB)
74 17:43:43.561309 progress 100 % (43 MB)
75 17:43:43.561848 43 MB downloaded in 0.59 s (73.47 MB/s)
76 17:43:43.562321 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:43:43.563142 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:43:43.563416 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:43:43.563684 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:43:43.564164 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 17:43:43.564442 saving as /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/dtb/meson-g12b-a311d-libretech-cc.dtb
83 17:43:43.564651 total size: 54703 (0 MB)
84 17:43:43.564859 No compression specified
85 17:43:43.597707 progress 59 % (0 MB)
86 17:43:43.598560 progress 100 % (0 MB)
87 17:43:43.599111 0 MB downloaded in 0.03 s (1.51 MB/s)
88 17:43:43.599569 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:43:43.600426 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:43:43.600693 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:43:43.600959 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:43:43.601420 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 17:43:43.601659 saving as /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/nfsrootfs/full.rootfs.tar
95 17:43:43.601864 total size: 120894716 (115 MB)
96 17:43:43.602073 Using unxz to decompress xz
97 17:43:43.636181 progress 0 % (0 MB)
98 17:43:44.425391 progress 5 % (5 MB)
99 17:43:45.261715 progress 10 % (11 MB)
100 17:43:46.056972 progress 15 % (17 MB)
101 17:43:46.800345 progress 20 % (23 MB)
102 17:43:47.394209 progress 25 % (28 MB)
103 17:43:48.218856 progress 30 % (34 MB)
104 17:43:49.011443 progress 35 % (40 MB)
105 17:43:49.380742 progress 40 % (46 MB)
106 17:43:49.767607 progress 45 % (51 MB)
107 17:43:50.485346 progress 50 % (57 MB)
108 17:43:51.360753 progress 55 % (63 MB)
109 17:43:52.138722 progress 60 % (69 MB)
110 17:43:52.889546 progress 65 % (74 MB)
111 17:43:53.660693 progress 70 % (80 MB)
112 17:43:54.480235 progress 75 % (86 MB)
113 17:43:55.272417 progress 80 % (92 MB)
114 17:43:56.036049 progress 85 % (98 MB)
115 17:43:56.892375 progress 90 % (103 MB)
116 17:43:57.670906 progress 95 % (109 MB)
117 17:43:58.512552 progress 100 % (115 MB)
118 17:43:58.525192 115 MB downloaded in 14.92 s (7.73 MB/s)
119 17:43:58.525808 end: 1.4.1 http-download (duration 00:00:15) [common]
121 17:43:58.526629 end: 1.4 download-retry (duration 00:00:15) [common]
122 17:43:58.526895 start: 1.5 download-retry (timeout 00:09:44) [common]
123 17:43:58.527155 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 17:43:58.527624 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/modules.tar.xz
125 17:43:58.527868 saving as /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/modules/modules.tar
126 17:43:58.528242 total size: 11600216 (11 MB)
127 17:43:58.528663 Using unxz to decompress xz
128 17:43:58.566389 progress 0 % (0 MB)
129 17:43:58.633509 progress 5 % (0 MB)
130 17:43:58.707880 progress 10 % (1 MB)
131 17:43:58.804157 progress 15 % (1 MB)
132 17:43:58.897479 progress 20 % (2 MB)
133 17:43:58.976974 progress 25 % (2 MB)
134 17:43:59.053634 progress 30 % (3 MB)
135 17:43:59.128464 progress 35 % (3 MB)
136 17:43:59.205980 progress 40 % (4 MB)
137 17:43:59.282971 progress 45 % (5 MB)
138 17:43:59.368140 progress 50 % (5 MB)
139 17:43:59.446058 progress 55 % (6 MB)
140 17:43:59.531833 progress 60 % (6 MB)
141 17:43:59.612922 progress 65 % (7 MB)
142 17:43:59.689968 progress 70 % (7 MB)
143 17:43:59.772710 progress 75 % (8 MB)
144 17:43:59.856844 progress 80 % (8 MB)
145 17:43:59.934563 progress 85 % (9 MB)
146 17:44:00.018640 progress 90 % (9 MB)
147 17:44:00.096866 progress 95 % (10 MB)
148 17:44:00.174958 progress 100 % (11 MB)
149 17:44:00.185038 11 MB downloaded in 1.66 s (6.68 MB/s)
150 17:44:00.185627 end: 1.5.1 http-download (duration 00:00:02) [common]
152 17:44:00.186437 end: 1.5 download-retry (duration 00:00:02) [common]
153 17:44:00.186703 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 17:44:00.186966 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 17:44:16.968677 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/976221/extract-nfsrootfs-_w193aqj
156 17:44:16.969292 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 17:44:16.969578 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 17:44:16.970184 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx
159 17:44:16.970608 makedir: /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin
160 17:44:16.970930 makedir: /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/tests
161 17:44:16.971242 makedir: /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/results
162 17:44:16.971570 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-add-keys
163 17:44:16.972126 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-add-sources
164 17:44:16.972641 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-background-process-start
165 17:44:16.973132 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-background-process-stop
166 17:44:16.973647 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-common-functions
167 17:44:16.974137 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-echo-ipv4
168 17:44:16.974608 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-install-packages
169 17:44:16.975074 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-installed-packages
170 17:44:16.975535 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-os-build
171 17:44:16.976026 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-probe-channel
172 17:44:16.976513 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-probe-ip
173 17:44:16.976976 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-target-ip
174 17:44:16.977527 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-target-mac
175 17:44:16.978007 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-target-storage
176 17:44:16.978482 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-case
177 17:44:16.978954 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-event
178 17:44:16.979414 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-feedback
179 17:44:16.979877 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-raise
180 17:44:16.980376 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-reference
181 17:44:16.980840 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-runner
182 17:44:16.981310 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-set
183 17:44:16.981773 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-test-shell
184 17:44:16.982244 Updating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-add-keys (debian)
185 17:44:16.982760 Updating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-add-sources (debian)
186 17:44:16.983255 Updating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-install-packages (debian)
187 17:44:16.983745 Updating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-installed-packages (debian)
188 17:44:16.984266 Updating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/bin/lava-os-build (debian)
189 17:44:16.984701 Creating /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/environment
190 17:44:16.985063 LAVA metadata
191 17:44:16.985320 - LAVA_JOB_ID=976221
192 17:44:16.985533 - LAVA_DISPATCHER_IP=192.168.6.2
193 17:44:16.985889 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 17:44:16.986831 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 17:44:16.987136 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 17:44:16.987340 skipped lava-vland-overlay
197 17:44:16.987576 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 17:44:16.987826 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 17:44:16.988073 skipped lava-multinode-overlay
200 17:44:16.988317 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 17:44:16.988565 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 17:44:16.988808 Loading test definitions
203 17:44:16.989078 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 17:44:16.989296 Using /lava-976221 at stage 0
205 17:44:16.990373 uuid=976221_1.6.2.4.1 testdef=None
206 17:44:16.990675 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 17:44:16.990936 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 17:44:16.992506 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 17:44:16.993288 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 17:44:16.995170 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 17:44:16.995998 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 17:44:16.997794 runner path: /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/0/tests/0_timesync-off test_uuid 976221_1.6.2.4.1
215 17:44:16.998330 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 17:44:16.999139 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 17:44:16.999360 Using /lava-976221 at stage 0
219 17:44:16.999707 Fetching tests from https://github.com/kernelci/test-definitions.git
220 17:44:17.000023 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/0/tests/1_kselftest-dt'
221 17:44:20.498574 Running '/usr/bin/git checkout kernelci.org
222 17:44:20.883219 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 17:44:20.884688 uuid=976221_1.6.2.4.5 testdef=None
224 17:44:20.885038 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 17:44:20.885783 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 17:44:20.888663 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 17:44:20.889485 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 17:44:20.893208 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 17:44:20.894054 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 17:44:20.897679 runner path: /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/0/tests/1_kselftest-dt test_uuid 976221_1.6.2.4.5
234 17:44:20.897976 BOARD='meson-g12b-a311d-libretech-cc'
235 17:44:20.898182 BRANCH='broonie-spi'
236 17:44:20.898379 SKIPFILE='/dev/null'
237 17:44:20.898575 SKIP_INSTALL='True'
238 17:44:20.898769 TESTPROG_URL='http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 17:44:20.898995 TST_CASENAME=''
240 17:44:20.899193 TST_CMDFILES='dt'
241 17:44:20.899763 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 17:44:20.900578 Creating lava-test-runner.conf files
244 17:44:20.900784 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/976221/lava-overlay-16jpjenx/lava-976221/0 for stage 0
245 17:44:20.901138 - 0_timesync-off
246 17:44:20.901378 - 1_kselftest-dt
247 17:44:20.901706 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 17:44:20.901983 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 17:44:45.175966 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 17:44:45.176485 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 17:44:45.176758 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 17:44:45.177037 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 17:44:45.177309 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 17:44:45.880795 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 17:44:45.881258 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 17:44:45.881513 extracting modules file /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976221/extract-nfsrootfs-_w193aqj
257 17:44:47.713765 extracting modules file /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976221/extract-overlay-ramdisk-6elapgi4/ramdisk
258 17:44:49.268589 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 17:44:49.269152 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 17:44:49.269481 [common] Applying overlay to NFS
261 17:44:49.269741 [common] Applying overlay /var/lib/lava/dispatcher/tmp/976221/compress-overlay-cagkk28u/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/976221/extract-nfsrootfs-_w193aqj
262 17:44:52.032554 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 17:44:52.033026 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 17:44:52.033299 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 17:44:52.033529 Converting downloaded kernel to a uImage
266 17:44:52.033840 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/kernel/Image /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/kernel/uImage
267 17:44:52.543750 output: Image Name:
268 17:44:52.544292 output: Created: Mon Nov 11 17:44:52 2024
269 17:44:52.544550 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 17:44:52.544799 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 17:44:52.545044 output: Load Address: 01080000
272 17:44:52.545279 output: Entry Point: 01080000
273 17:44:52.545519 output:
274 17:44:52.545921 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 17:44:52.546248 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 17:44:52.546568 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 17:44:52.546882 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 17:44:52.547191 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 17:44:52.547506 Building ramdisk /var/lib/lava/dispatcher/tmp/976221/extract-overlay-ramdisk-6elapgi4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/976221/extract-overlay-ramdisk-6elapgi4/ramdisk
280 17:44:54.773185 >> 166774 blocks
281 17:45:02.587750 Adding RAMdisk u-boot header.
282 17:45:02.588237 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/976221/extract-overlay-ramdisk-6elapgi4/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/976221/extract-overlay-ramdisk-6elapgi4/ramdisk.cpio.gz.uboot
283 17:45:02.842686 output: Image Name:
284 17:45:02.843126 output: Created: Mon Nov 11 17:45:02 2024
285 17:45:02.843334 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 17:45:02.843535 output: Data Size: 23426363 Bytes = 22877.31 KiB = 22.34 MiB
287 17:45:02.843737 output: Load Address: 00000000
288 17:45:02.843936 output: Entry Point: 00000000
289 17:45:02.844333 output:
290 17:45:02.845367 rename /var/lib/lava/dispatcher/tmp/976221/extract-overlay-ramdisk-6elapgi4/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot
291 17:45:02.846112 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 17:45:02.846656 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 17:45:02.847215 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 17:45:02.847659 No LXC device requested
295 17:45:02.848219 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 17:45:02.848756 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 17:45:02.849250 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 17:45:02.849658 Checking files for TFTP limit of 4294967296 bytes.
299 17:45:02.852505 end: 1 tftp-deploy (duration 00:01:20) [common]
300 17:45:02.853156 start: 2 uboot-action (timeout 00:05:00) [common]
301 17:45:02.853684 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 17:45:02.854177 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 17:45:02.854681 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 17:45:02.855216 Using kernel file from prepare-kernel: 976221/tftp-deploy-g5t5onf1/kernel/uImage
305 17:45:02.855840 substitutions:
306 17:45:02.856292 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 17:45:02.856698 - {DTB_ADDR}: 0x01070000
308 17:45:02.857097 - {DTB}: 976221/tftp-deploy-g5t5onf1/dtb/meson-g12b-a311d-libretech-cc.dtb
309 17:45:02.857497 - {INITRD}: 976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot
310 17:45:02.857893 - {KERNEL_ADDR}: 0x01080000
311 17:45:02.858304 - {KERNEL}: 976221/tftp-deploy-g5t5onf1/kernel/uImage
312 17:45:02.858719 - {LAVA_MAC}: None
313 17:45:02.859162 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/976221/extract-nfsrootfs-_w193aqj
314 17:45:02.859562 - {NFS_SERVER_IP}: 192.168.6.2
315 17:45:02.859953 - {PRESEED_CONFIG}: None
316 17:45:02.860383 - {PRESEED_LOCAL}: None
317 17:45:02.860777 - {RAMDISK_ADDR}: 0x08000000
318 17:45:02.861165 - {RAMDISK}: 976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot
319 17:45:02.861554 - {ROOT_PART}: None
320 17:45:02.861944 - {ROOT}: None
321 17:45:02.862329 - {SERVER_IP}: 192.168.6.2
322 17:45:02.862711 - {TEE_ADDR}: 0x83000000
323 17:45:02.863096 - {TEE}: None
324 17:45:02.863483 Parsed boot commands:
325 17:45:02.863859 - setenv autoload no
326 17:45:02.864295 - setenv initrd_high 0xffffffff
327 17:45:02.864698 - setenv fdt_high 0xffffffff
328 17:45:02.865123 - dhcp
329 17:45:02.865529 - setenv serverip 192.168.6.2
330 17:45:02.865923 - tftpboot 0x01080000 976221/tftp-deploy-g5t5onf1/kernel/uImage
331 17:45:02.866313 - tftpboot 0x08000000 976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot
332 17:45:02.866703 - tftpboot 0x01070000 976221/tftp-deploy-g5t5onf1/dtb/meson-g12b-a311d-libretech-cc.dtb
333 17:45:02.867091 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976221/extract-nfsrootfs-_w193aqj,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 17:45:02.867489 - bootm 0x01080000 0x08000000 0x01070000
335 17:45:02.868047 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 17:45:02.869606 start: 2.3 connect-device (timeout 00:05:00) [common]
338 17:45:02.870072 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 17:45:02.885195 Setting prompt string to ['lava-test: # ']
340 17:45:02.886743 end: 2.3 connect-device (duration 00:00:00) [common]
341 17:45:02.887385 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 17:45:02.888047 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 17:45:02.888600 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 17:45:02.889939 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 17:45:02.924716 >> OK - accepted request
346 17:45:02.926705 Returned 0 in 0 seconds
347 17:45:03.027838 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 17:45:03.029563 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 17:45:03.030100 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 17:45:03.030603 Setting prompt string to ['Hit any key to stop autoboot']
352 17:45:03.031044 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 17:45:03.032619 Trying 192.168.56.21...
354 17:45:03.033101 Connected to conserv1.
355 17:45:03.033511 Escape character is '^]'.
356 17:45:03.033921
357 17:45:03.034327 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 17:45:03.034746
359 17:45:13.730202 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 17:45:13.730811 bl2_stage_init 0x01
361 17:45:13.731214 bl2_stage_init 0x81
362 17:45:13.735886 hw id: 0x0000 - pwm id 0x01
363 17:45:13.736422 bl2_stage_init 0xc1
364 17:45:13.736843 bl2_stage_init 0x02
365 17:45:13.737245
366 17:45:13.741324 L0:00000000
367 17:45:13.741809 L1:20000703
368 17:45:13.742211 L2:00008067
369 17:45:13.742610 L3:14000000
370 17:45:13.744292 B2:00402000
371 17:45:13.744750 B1:e0f83180
372 17:45:13.745146
373 17:45:13.745532 TE: 58159
374 17:45:13.745917
375 17:45:13.755621 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 17:45:13.756113
377 17:45:13.756508 Board ID = 1
378 17:45:13.756893 Set A53 clk to 24M
379 17:45:13.757275 Set A73 clk to 24M
380 17:45:13.761204 Set clk81 to 24M
381 17:45:13.761656 A53 clk: 1200 MHz
382 17:45:13.762044 A73 clk: 1200 MHz
383 17:45:13.766540 CLK81: 166.6M
384 17:45:13.766987 smccc: 00012ab5
385 17:45:13.772089 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 17:45:13.772538 board id: 1
387 17:45:13.777747 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 17:45:13.791407 fw parse done
389 17:45:13.796511 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 17:45:13.839638 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 17:45:13.850911 PIEI prepare done
392 17:45:13.851365 fastboot data load
393 17:45:13.851759 fastboot data verify
394 17:45:13.856565 verify result: 266
395 17:45:13.862141 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 17:45:13.862609 LPDDR4 probe
397 17:45:13.863000 ddr clk to 1584MHz
398 17:45:13.869812 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 17:45:13.906939
400 17:45:13.907402 dmc_version 0001
401 17:45:13.913255 Check phy result
402 17:45:13.919907 INFO : End of CA training
403 17:45:13.920375 INFO : End of initialization
404 17:45:13.925531 INFO : Training has run successfully!
405 17:45:13.925965 Check phy result
406 17:45:13.931099 INFO : End of initialization
407 17:45:13.931534 INFO : End of read enable training
408 17:45:13.936874 INFO : End of fine write leveling
409 17:45:13.942318 INFO : End of Write leveling coarse delay
410 17:45:13.942760 INFO : Training has run successfully!
411 17:45:13.943151 Check phy result
412 17:45:13.947916 INFO : End of initialization
413 17:45:13.948388 INFO : End of read dq deskew training
414 17:45:13.953486 INFO : End of MPR read delay center optimization
415 17:45:13.959100 INFO : End of write delay center optimization
416 17:45:13.964855 INFO : End of read delay center optimization
417 17:45:13.965307 INFO : End of max read latency training
418 17:45:13.970295 INFO : Training has run successfully!
419 17:45:13.970731 1D training succeed
420 17:45:13.979562 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 17:45:14.026254 Check phy result
422 17:45:14.026794 INFO : End of initialization
423 17:45:14.048858 INFO : End of 2D read delay Voltage center optimization
424 17:45:14.068541 INFO : End of 2D read delay Voltage center optimization
425 17:45:14.120507 INFO : End of 2D write delay Voltage center optimization
426 17:45:14.170822 INFO : End of 2D write delay Voltage center optimization
427 17:45:14.176032 INFO : Training has run successfully!
428 17:45:14.176538
429 17:45:14.176948 channel==0
430 17:45:14.181692 RxClkDly_Margin_A0==88 ps 9
431 17:45:14.182192 TxDqDly_Margin_A0==98 ps 10
432 17:45:14.187299 RxClkDly_Margin_A1==88 ps 9
433 17:45:14.187748 TxDqDly_Margin_A1==88 ps 9
434 17:45:14.188201 TrainedVREFDQ_A0==74
435 17:45:14.192940 TrainedVREFDQ_A1==74
436 17:45:14.193437 VrefDac_Margin_A0==25
437 17:45:14.193833 DeviceVref_Margin_A0==40
438 17:45:14.198508 VrefDac_Margin_A1==25
439 17:45:14.198973 DeviceVref_Margin_A1==40
440 17:45:14.199386
441 17:45:14.199783
442 17:45:14.200212 channel==1
443 17:45:14.204042 RxClkDly_Margin_A0==98 ps 10
444 17:45:14.204510 TxDqDly_Margin_A0==98 ps 10
445 17:45:14.209669 RxClkDly_Margin_A1==98 ps 10
446 17:45:14.210155 TxDqDly_Margin_A1==88 ps 9
447 17:45:14.215250 TrainedVREFDQ_A0==77
448 17:45:14.215719 TrainedVREFDQ_A1==77
449 17:45:14.216155 VrefDac_Margin_A0==22
450 17:45:14.220880 DeviceVref_Margin_A0==37
451 17:45:14.221329 VrefDac_Margin_A1==22
452 17:45:14.226525 DeviceVref_Margin_A1==37
453 17:45:14.226976
454 17:45:14.227374 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 17:45:14.227773
456 17:45:14.260060 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 17:45:14.260614 2D training succeed
458 17:45:14.265653 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 17:45:14.271258 auto size-- 65535DDR cs0 size: 2048MB
460 17:45:14.271707 DDR cs1 size: 2048MB
461 17:45:14.276800 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 17:45:14.277245 cs0 DataBus test pass
463 17:45:14.282448 cs1 DataBus test pass
464 17:45:14.282898 cs0 AddrBus test pass
465 17:45:14.283289 cs1 AddrBus test pass
466 17:45:14.283674
467 17:45:14.287956 100bdlr_step_size ps== 420
468 17:45:14.288436 result report
469 17:45:14.293525 boot times 0Enable ddr reg access
470 17:45:14.298003 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 17:45:14.311697 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 17:45:14.886151 0.0;M3 CHK:0;cm4_sp_mode 0
473 17:45:14.886758 MVN_1=0x00000000
474 17:45:14.891622 MVN_2=0x00000000
475 17:45:14.897493 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 17:45:14.897983 OPS=0x10
477 17:45:14.898394 ring efuse init
478 17:45:14.898797 chipver efuse init
479 17:45:14.905669 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 17:45:14.906147 [0.018961 Inits done]
481 17:45:14.912584 secure task start!
482 17:45:14.913034 high task start!
483 17:45:14.913431 low task start!
484 17:45:14.913832 run into bl31
485 17:45:14.919929 NOTICE: BL31: v1.3(release):4fc40b1
486 17:45:14.927221 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 17:45:14.927698 NOTICE: BL31: G12A normal boot!
488 17:45:14.953593 NOTICE: BL31: BL33 decompress pass
489 17:45:14.958501 ERROR: Error initializing runtime service opteed_fast
490 17:45:16.192239
491 17:45:16.192842
492 17:45:16.200089 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 17:45:16.200575
494 17:45:16.200995 Model: Libre Computer AML-A311D-CC Alta
495 17:45:16.408304 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 17:45:16.431817 DRAM: 2 GiB (effective 3.8 GiB)
497 17:45:16.575374 Core: 408 devices, 31 uclasses, devicetree: separate
498 17:45:16.580362 WDT: Not starting watchdog@f0d0
499 17:45:16.613447 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 17:45:16.625873 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 17:45:16.629935 ** Bad device specification mmc 0 **
502 17:45:16.641266 Card did not respond to voltage select! : -110
503 17:45:16.648286 ** Bad device specification mmc 0 **
504 17:45:16.648751 Couldn't find partition mmc 0
505 17:45:16.657207 Card did not respond to voltage select! : -110
506 17:45:16.662759 ** Bad device specification mmc 0 **
507 17:45:16.663218 Couldn't find partition mmc 0
508 17:45:16.667447 Error: could not access storage.
509 17:45:17.930619 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 17:45:17.931228 bl2_stage_init 0x01
511 17:45:17.931655 bl2_stage_init 0x81
512 17:45:17.935931 hw id: 0x0000 - pwm id 0x01
513 17:45:17.936435 bl2_stage_init 0xc1
514 17:45:17.936852 bl2_stage_init 0x02
515 17:45:17.937259
516 17:45:17.941470 L0:00000000
517 17:45:17.941925 L1:20000703
518 17:45:17.942331 L2:00008067
519 17:45:17.942731 L3:14000000
520 17:45:17.944328 B2:00402000
521 17:45:17.944783 B1:e0f83180
522 17:45:17.945190
523 17:45:17.945594 TE: 58159
524 17:45:17.945994
525 17:45:17.955408 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 17:45:17.955867
527 17:45:17.956317 Board ID = 1
528 17:45:17.956720 Set A53 clk to 24M
529 17:45:17.957118 Set A73 clk to 24M
530 17:45:17.961078 Set clk81 to 24M
531 17:45:17.961529 A53 clk: 1200 MHz
532 17:45:17.961938 A73 clk: 1200 MHz
533 17:45:17.966662 CLK81: 166.6M
534 17:45:17.967115 smccc: 00012ab5
535 17:45:17.972314 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 17:45:17.972768 board id: 1
537 17:45:17.977906 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 17:45:17.991564 fw parse done
539 17:45:17.997230 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 17:45:18.039871 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 17:45:18.051089 PIEI prepare done
542 17:45:18.051619 fastboot data load
543 17:45:18.052078 fastboot data verify
544 17:45:18.056692 verify result: 266
545 17:45:18.062477 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 17:45:18.062981 LPDDR4 probe
547 17:45:18.063400 ddr clk to 1584MHz
548 17:45:18.070159 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 17:45:18.107035
550 17:45:18.107556 dmc_version 0001
551 17:45:18.113316 Check phy result
552 17:45:18.120228 INFO : End of CA training
553 17:45:18.120708 INFO : End of initialization
554 17:45:18.125770 INFO : Training has run successfully!
555 17:45:18.126236 Check phy result
556 17:45:18.131383 INFO : End of initialization
557 17:45:18.131851 INFO : End of read enable training
558 17:45:18.136947 INFO : End of fine write leveling
559 17:45:18.142583 INFO : End of Write leveling coarse delay
560 17:45:18.143064 INFO : Training has run successfully!
561 17:45:18.143476 Check phy result
562 17:45:18.148237 INFO : End of initialization
563 17:45:18.148705 INFO : End of read dq deskew training
564 17:45:18.153763 INFO : End of MPR read delay center optimization
565 17:45:18.159438 INFO : End of write delay center optimization
566 17:45:18.164941 INFO : End of read delay center optimization
567 17:45:18.165402 INFO : End of max read latency training
568 17:45:18.170559 INFO : Training has run successfully!
569 17:45:18.171013 1D training succeed
570 17:45:18.179319 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 17:45:18.226708 Check phy result
572 17:45:18.227179 INFO : End of initialization
573 17:45:18.248565 INFO : End of 2D read delay Voltage center optimization
574 17:45:18.268382 INFO : End of 2D read delay Voltage center optimization
575 17:45:18.320513 INFO : End of 2D write delay Voltage center optimization
576 17:45:18.370305 INFO : End of 2D write delay Voltage center optimization
577 17:45:18.375819 INFO : Training has run successfully!
578 17:45:18.376351
579 17:45:18.376773 channel==0
580 17:45:18.381471 RxClkDly_Margin_A0==88 ps 9
581 17:45:18.381929 TxDqDly_Margin_A0==98 ps 10
582 17:45:18.384669 RxClkDly_Margin_A1==88 ps 9
583 17:45:18.385131 TxDqDly_Margin_A1==98 ps 10
584 17:45:18.390200 TrainedVREFDQ_A0==74
585 17:45:18.390662 TrainedVREFDQ_A1==75
586 17:45:18.395918 VrefDac_Margin_A0==25
587 17:45:18.396458 DeviceVref_Margin_A0==40
588 17:45:18.396899 VrefDac_Margin_A1==25
589 17:45:18.401521 DeviceVref_Margin_A1==39
590 17:45:18.402054
591 17:45:18.402516
592 17:45:18.402963 channel==1
593 17:45:18.403398 RxClkDly_Margin_A0==98 ps 10
594 17:45:18.407151 TxDqDly_Margin_A0==88 ps 9
595 17:45:18.407657 RxClkDly_Margin_A1==88 ps 9
596 17:45:18.412628 TxDqDly_Margin_A1==88 ps 9
597 17:45:18.413094 TrainedVREFDQ_A0==77
598 17:45:18.413508 TrainedVREFDQ_A1==77
599 17:45:18.418217 VrefDac_Margin_A0==22
600 17:45:18.418677 DeviceVref_Margin_A0==37
601 17:45:18.423811 VrefDac_Margin_A1==24
602 17:45:18.424300 DeviceVref_Margin_A1==37
603 17:45:18.424708
604 17:45:18.429464 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 17:45:18.429924
606 17:45:18.457422 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 17:45:18.463087 2D training succeed
608 17:45:18.468583 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 17:45:18.469045 auto size-- 65535DDR cs0 size: 2048MB
610 17:45:18.474240 DDR cs1 size: 2048MB
611 17:45:18.474756 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 17:45:18.479875 cs0 DataBus test pass
613 17:45:18.480408 cs1 DataBus test pass
614 17:45:18.480828 cs0 AddrBus test pass
615 17:45:18.485468 cs1 AddrBus test pass
616 17:45:18.485931
617 17:45:18.486339 100bdlr_step_size ps== 420
618 17:45:18.486747 result report
619 17:45:18.490992 boot times 0Enable ddr reg access
620 17:45:18.498187 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 17:45:18.511702 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 17:45:19.084141 0.0;M3 CHK:0;cm4_sp_mode 0
623 17:45:19.084731 MVN_1=0x00000000
624 17:45:19.089633 MVN_2=0x00000000
625 17:45:19.095426 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 17:45:19.095915 OPS=0x10
627 17:45:19.096404 ring efuse init
628 17:45:19.096802 chipver efuse init
629 17:45:19.100961 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 17:45:19.106549 [0.018960 Inits done]
631 17:45:19.106996 secure task start!
632 17:45:19.107387 high task start!
633 17:45:19.110469 low task start!
634 17:45:19.110914 run into bl31
635 17:45:19.117772 NOTICE: BL31: v1.3(release):4fc40b1
636 17:45:19.125028 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 17:45:19.125479 NOTICE: BL31: G12A normal boot!
638 17:45:19.150872 NOTICE: BL31: BL33 decompress pass
639 17:45:19.156258 ERROR: Error initializing runtime service opteed_fast
640 17:45:20.389609
641 17:45:20.390200
642 17:45:20.397912 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 17:45:20.398417
644 17:45:20.398838 Model: Libre Computer AML-A311D-CC Alta
645 17:45:20.606503 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 17:45:20.629851 DRAM: 2 GiB (effective 3.8 GiB)
647 17:45:20.772775 Core: 408 devices, 31 uclasses, devicetree: separate
648 17:45:20.778708 WDT: Not starting watchdog@f0d0
649 17:45:20.810975 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 17:45:20.823313 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 17:45:20.828362 ** Bad device specification mmc 0 **
652 17:45:20.838657 Card did not respond to voltage select! : -110
653 17:45:20.846267 ** Bad device specification mmc 0 **
654 17:45:20.846721 Couldn't find partition mmc 0
655 17:45:20.854665 Card did not respond to voltage select! : -110
656 17:45:20.860158 ** Bad device specification mmc 0 **
657 17:45:20.860614 Couldn't find partition mmc 0
658 17:45:20.865284 Error: could not access storage.
659 17:45:21.207922 Net: eth0: ethernet@ff3f0000
660 17:45:21.208535 starting USB...
661 17:45:21.459630 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 17:45:21.460304 Starting the controller
663 17:45:21.466571 USB XHCI 1.10
664 17:45:23.182217 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 17:45:23.182824 bl2_stage_init 0x01
666 17:45:23.183244 bl2_stage_init 0x81
667 17:45:23.187834 hw id: 0x0000 - pwm id 0x01
668 17:45:23.188351 bl2_stage_init 0xc1
669 17:45:23.188766 bl2_stage_init 0x02
670 17:45:23.189167
671 17:45:23.193399 L0:00000000
672 17:45:23.193880 L1:20000703
673 17:45:23.194291 L2:00008067
674 17:45:23.194688 L3:14000000
675 17:45:23.196278 B2:00402000
676 17:45:23.196758 B1:e0f83180
677 17:45:23.197171
678 17:45:23.197600 TE: 58124
679 17:45:23.198015
680 17:45:23.207336 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 17:45:23.207829
682 17:45:23.208303 Board ID = 1
683 17:45:23.208711 Set A53 clk to 24M
684 17:45:23.209131 Set A73 clk to 24M
685 17:45:23.212975 Set clk81 to 24M
686 17:45:23.213467 A53 clk: 1200 MHz
687 17:45:23.213881 A73 clk: 1200 MHz
688 17:45:23.216407 CLK81: 166.6M
689 17:45:23.216881 smccc: 00012a91
690 17:45:23.221964 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 17:45:23.227456 board id: 1
692 17:45:23.232030 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 17:45:23.243411 fw parse done
694 17:45:23.248365 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 17:45:23.291088 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 17:45:23.303063 PIEI prepare done
697 17:45:23.303404 fastboot data load
698 17:45:23.303647 fastboot data verify
699 17:45:23.308579 verify result: 266
700 17:45:23.314271 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 17:45:23.314603 LPDDR4 probe
702 17:45:23.314829 ddr clk to 1584MHz
703 17:45:23.321253 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 17:45:23.358552
705 17:45:23.358932 dmc_version 0001
706 17:45:23.365184 Check phy result
707 17:45:23.371855 INFO : End of CA training
708 17:45:23.372468 INFO : End of initialization
709 17:45:23.377604 INFO : Training has run successfully!
710 17:45:23.378160 Check phy result
711 17:45:23.383197 INFO : End of initialization
712 17:45:23.383705 INFO : End of read enable training
713 17:45:23.388777 INFO : End of fine write leveling
714 17:45:23.394363 INFO : End of Write leveling coarse delay
715 17:45:23.394899 INFO : Training has run successfully!
716 17:45:23.395367 Check phy result
717 17:45:23.399961 INFO : End of initialization
718 17:45:23.400510 INFO : End of read dq deskew training
719 17:45:23.405658 INFO : End of MPR read delay center optimization
720 17:45:23.411185 INFO : End of write delay center optimization
721 17:45:23.416765 INFO : End of read delay center optimization
722 17:45:23.417288 INFO : End of max read latency training
723 17:45:23.422306 INFO : Training has run successfully!
724 17:45:23.422809 1D training succeed
725 17:45:23.430565 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 17:45:23.478389 Check phy result
727 17:45:23.478976 INFO : End of initialization
728 17:45:23.500124 INFO : End of 2D read delay Voltage center optimization
729 17:45:23.520168 INFO : End of 2D read delay Voltage center optimization
730 17:45:23.572134 INFO : End of 2D write delay Voltage center optimization
731 17:45:23.622559 INFO : End of 2D write delay Voltage center optimization
732 17:45:23.628249 INFO : Training has run successfully!
733 17:45:23.628806
734 17:45:23.629282 channel==0
735 17:45:23.633745 RxClkDly_Margin_A0==88 ps 9
736 17:45:23.634278 TxDqDly_Margin_A0==108 ps 11
737 17:45:23.636989 RxClkDly_Margin_A1==88 ps 9
738 17:45:23.637504 TxDqDly_Margin_A1==98 ps 10
739 17:45:23.642525 TrainedVREFDQ_A0==74
740 17:45:23.643045 TrainedVREFDQ_A1==74
741 17:45:23.648175 VrefDac_Margin_A0==25
742 17:45:23.648694 DeviceVref_Margin_A0==40
743 17:45:23.649157 VrefDac_Margin_A1==25
744 17:45:23.653717 DeviceVref_Margin_A1==40
745 17:45:23.654216
746 17:45:23.654675
747 17:45:23.655121 channel==1
748 17:45:23.655563 RxClkDly_Margin_A0==98 ps 10
749 17:45:23.657061 TxDqDly_Margin_A0==88 ps 9
750 17:45:23.662556 RxClkDly_Margin_A1==98 ps 10
751 17:45:23.663086 TxDqDly_Margin_A1==88 ps 9
752 17:45:23.668190 TrainedVREFDQ_A0==77
753 17:45:23.668761 TrainedVREFDQ_A1==77
754 17:45:23.669248 VrefDac_Margin_A0==22
755 17:45:23.673877 DeviceVref_Margin_A0==37
756 17:45:23.674413 VrefDac_Margin_A1==22
757 17:45:23.674933 DeviceVref_Margin_A1==37
758 17:45:23.675439
759 17:45:23.679429 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 17:45:23.680083
761 17:45:23.712875 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 17:45:23.713467 2D training succeed
763 17:45:23.718553 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 17:45:23.724138 auto size-- 65535DDR cs0 size: 2048MB
765 17:45:23.724642 DDR cs1 size: 2048MB
766 17:45:23.729839 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 17:45:23.730321 cs0 DataBus test pass
768 17:45:23.730762 cs1 DataBus test pass
769 17:45:23.735284 cs0 AddrBus test pass
770 17:45:23.735760 cs1 AddrBus test pass
771 17:45:23.736240
772 17:45:23.740894 100bdlr_step_size ps== 420
773 17:45:23.741384 result report
774 17:45:23.741818 boot times 0Enable ddr reg access
775 17:45:23.750186 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 17:45:23.763541 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 17:45:24.337626 0.0;M3 CHK:0;cm4_sp_mode 0
778 17:45:24.338266 MVN_1=0x00000000
779 17:45:24.343353 MVN_2=0x00000000
780 17:45:24.348917 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 17:45:24.349427 OPS=0x10
782 17:45:24.349899 ring efuse init
783 17:45:24.350336 chipver efuse init
784 17:45:24.354421 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 17:45:24.360093 [0.018961 Inits done]
786 17:45:24.360597 secure task start!
787 17:45:24.361036 high task start!
788 17:45:24.363600 low task start!
789 17:45:24.364118 run into bl31
790 17:45:24.371266 NOTICE: BL31: v1.3(release):4fc40b1
791 17:45:24.378510 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 17:45:24.378996 NOTICE: BL31: G12A normal boot!
793 17:45:24.404412 NOTICE: BL31: BL33 decompress pass
794 17:45:24.409367 ERROR: Error initializing runtime service opteed_fast
795 17:45:25.642976
796 17:45:25.643652
797 17:45:25.651437 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 17:45:25.652029
799 17:45:25.652506 Model: Libre Computer AML-A311D-CC Alta
800 17:45:25.859741 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 17:45:25.883112 DRAM: 2 GiB (effective 3.8 GiB)
802 17:45:26.026227 Core: 408 devices, 31 uclasses, devicetree: separate
803 17:45:26.032060 WDT: Not starting watchdog@f0d0
804 17:45:26.064256 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 17:45:26.076677 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 17:45:26.081625 ** Bad device specification mmc 0 **
807 17:45:26.092025 Card did not respond to voltage select! : -110
808 17:45:26.099601 ** Bad device specification mmc 0 **
809 17:45:26.100148 Couldn't find partition mmc 0
810 17:45:26.108025 Card did not respond to voltage select! : -110
811 17:45:26.113452 ** Bad device specification mmc 0 **
812 17:45:26.113946 Couldn't find partition mmc 0
813 17:45:26.118823 Error: could not access storage.
814 17:45:26.462179 Net: eth0: ethernet@ff3f0000
815 17:45:26.462598 starting USB...
816 17:45:26.713888 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 17:45:26.714414 Starting the controller
818 17:45:26.720048 USB XHCI 1.10
819 17:45:28.880838 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 17:45:28.881506 bl2_stage_init 0x01
821 17:45:28.881984 bl2_stage_init 0x81
822 17:45:28.886426 hw id: 0x0000 - pwm id 0x01
823 17:45:28.886922 bl2_stage_init 0xc1
824 17:45:28.887381 bl2_stage_init 0x02
825 17:45:28.887828
826 17:45:28.892041 L0:00000000
827 17:45:28.892532 L1:20000703
828 17:45:28.892982 L2:00008067
829 17:45:28.893429 L3:14000000
830 17:45:28.895034 B2:00402000
831 17:45:28.895513 B1:e0f83180
832 17:45:28.895962
833 17:45:28.896454 TE: 58124
834 17:45:28.896904
835 17:45:28.906085 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 17:45:28.906578
837 17:45:28.907035 Board ID = 1
838 17:45:28.907476 Set A53 clk to 24M
839 17:45:28.907913 Set A73 clk to 24M
840 17:45:28.911739 Set clk81 to 24M
841 17:45:28.912250 A53 clk: 1200 MHz
842 17:45:28.912697 A73 clk: 1200 MHz
843 17:45:28.917264 CLK81: 166.6M
844 17:45:28.917742 smccc: 00012a92
845 17:45:28.922996 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 17:45:28.923481 board id: 1
847 17:45:28.931626 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 17:45:28.942002 fw parse done
849 17:45:28.948019 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 17:45:28.990622 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 17:45:29.001521 PIEI prepare done
852 17:45:29.002064 fastboot data load
853 17:45:29.002519 fastboot data verify
854 17:45:29.007141 verify result: 266
855 17:45:29.012700 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 17:45:29.013185 LPDDR4 probe
857 17:45:29.013638 ddr clk to 1584MHz
858 17:45:29.020721 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 17:45:29.057998
860 17:45:29.058505 dmc_version 0001
861 17:45:29.064630 Check phy result
862 17:45:29.070560 INFO : End of CA training
863 17:45:29.071036 INFO : End of initialization
864 17:45:29.076078 INFO : Training has run successfully!
865 17:45:29.076559 Check phy result
866 17:45:29.081728 INFO : End of initialization
867 17:45:29.082210 INFO : End of read enable training
868 17:45:29.087346 INFO : End of fine write leveling
869 17:45:29.092913 INFO : End of Write leveling coarse delay
870 17:45:29.093392 INFO : Training has run successfully!
871 17:45:29.093839 Check phy result
872 17:45:29.098542 INFO : End of initialization
873 17:45:29.099021 INFO : End of read dq deskew training
874 17:45:29.104201 INFO : End of MPR read delay center optimization
875 17:45:29.109729 INFO : End of write delay center optimization
876 17:45:29.115312 INFO : End of read delay center optimization
877 17:45:29.115789 INFO : End of max read latency training
878 17:45:29.120888 INFO : Training has run successfully!
879 17:45:29.121369 1D training succeed
880 17:45:29.130146 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 17:45:29.177699 Check phy result
882 17:45:29.178235 INFO : End of initialization
883 17:45:29.199316 INFO : End of 2D read delay Voltage center optimization
884 17:45:29.219423 INFO : End of 2D read delay Voltage center optimization
885 17:45:29.271377 INFO : End of 2D write delay Voltage center optimization
886 17:45:29.320668 INFO : End of 2D write delay Voltage center optimization
887 17:45:29.326130 INFO : Training has run successfully!
888 17:45:29.326617
889 17:45:29.327080 channel==0
890 17:45:29.331815 RxClkDly_Margin_A0==88 ps 9
891 17:45:29.332351 TxDqDly_Margin_A0==98 ps 10
892 17:45:29.337354 RxClkDly_Margin_A1==88 ps 9
893 17:45:29.337842 TxDqDly_Margin_A1==98 ps 10
894 17:45:29.338297 TrainedVREFDQ_A0==74
895 17:45:29.343120 TrainedVREFDQ_A1==74
896 17:45:29.343697 VrefDac_Margin_A0==25
897 17:45:29.344186 DeviceVref_Margin_A0==40
898 17:45:29.348650 VrefDac_Margin_A1==26
899 17:45:29.349202 DeviceVref_Margin_A1==40
900 17:45:29.349635
901 17:45:29.350064
902 17:45:29.354259 channel==1
903 17:45:29.354724 RxClkDly_Margin_A0==98 ps 10
904 17:45:29.355179 TxDqDly_Margin_A0==88 ps 9
905 17:45:29.359763 RxClkDly_Margin_A1==98 ps 10
906 17:45:29.360287 TxDqDly_Margin_A1==88 ps 9
907 17:45:29.365400 TrainedVREFDQ_A0==77
908 17:45:29.365902 TrainedVREFDQ_A1==77
909 17:45:29.366337 VrefDac_Margin_A0==22
910 17:45:29.370990 DeviceVref_Margin_A0==37
911 17:45:29.371464 VrefDac_Margin_A1==23
912 17:45:29.376595 DeviceVref_Margin_A1==37
913 17:45:29.377073
914 17:45:29.377503 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 17:45:29.377933
916 17:45:29.410167 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 17:45:29.410720 2D training succeed
918 17:45:29.415701 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 17:45:29.421314 auto size-- 65535DDR cs0 size: 2048MB
920 17:45:29.421787 DDR cs1 size: 2048MB
921 17:45:29.426926 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 17:45:29.427387 cs0 DataBus test pass
923 17:45:29.432603 cs1 DataBus test pass
924 17:45:29.433092 cs0 AddrBus test pass
925 17:45:29.433524 cs1 AddrBus test pass
926 17:45:29.433948
927 17:45:29.438135 100bdlr_step_size ps== 420
928 17:45:29.438614 result report
929 17:45:29.443794 boot times 0Enable ddr reg access
930 17:45:29.449165 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 17:45:29.462589 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 17:45:30.034503 0.0;M3 CHK:0;cm4_sp_mode 0
933 17:45:30.035196 MVN_1=0x00000000
934 17:45:30.040046 MVN_2=0x00000000
935 17:45:30.045747 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 17:45:30.046353 OPS=0x10
937 17:45:30.046846 ring efuse init
938 17:45:30.047296 chipver efuse init
939 17:45:30.053966 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 17:45:30.054537 [0.018961 Inits done]
941 17:45:30.061181 secure task start!
942 17:45:30.061727 high task start!
943 17:45:30.062221 low task start!
944 17:45:30.062684 run into bl31
945 17:45:30.068263 NOTICE: BL31: v1.3(release):4fc40b1
946 17:45:30.075973 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 17:45:30.076521 NOTICE: BL31: G12A normal boot!
948 17:45:30.101320 NOTICE: BL31: BL33 decompress pass
949 17:45:30.106698 ERROR: Error initializing runtime service opteed_fast
950 17:45:31.340062
951 17:45:31.340734
952 17:45:31.347511 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 17:45:31.348140
954 17:45:31.348618 Model: Libre Computer AML-A311D-CC Alta
955 17:45:31.555908 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 17:45:31.579270 DRAM: 2 GiB (effective 3.8 GiB)
957 17:45:31.723263 Core: 408 devices, 31 uclasses, devicetree: separate
958 17:45:31.728999 WDT: Not starting watchdog@f0d0
959 17:45:31.761249 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 17:45:31.773719 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 17:45:31.778645 ** Bad device specification mmc 0 **
962 17:45:31.789055 Card did not respond to voltage select! : -110
963 17:45:31.796680 ** Bad device specification mmc 0 **
964 17:45:31.797242 Couldn't find partition mmc 0
965 17:45:31.805031 Card did not respond to voltage select! : -110
966 17:45:31.810538 ** Bad device specification mmc 0 **
967 17:45:31.811154 Couldn't find partition mmc 0
968 17:45:31.815568 Error: could not access storage.
969 17:45:32.158217 Net: eth0: ethernet@ff3f0000
970 17:45:32.158818 starting USB...
971 17:45:32.410000 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 17:45:32.410593 Starting the controller
973 17:45:32.416872 USB XHCI 1.10
974 17:45:34.280559 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 17:45:34.281150 bl2_stage_init 0x01
976 17:45:34.281579 bl2_stage_init 0x81
977 17:45:34.286100 hw id: 0x0000 - pwm id 0x01
978 17:45:34.286555 bl2_stage_init 0xc1
979 17:45:34.286967 bl2_stage_init 0x02
980 17:45:34.287372
981 17:45:34.291720 L0:00000000
982 17:45:34.292306 L1:20000703
983 17:45:34.292735 L2:00008067
984 17:45:34.293138 L3:14000000
985 17:45:34.297269 B2:00402000
986 17:45:34.297737 B1:e0f83180
987 17:45:34.298169
988 17:45:34.298599 TE: 58167
989 17:45:34.299011
990 17:45:34.302884 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 17:45:34.303341
992 17:45:34.303866 Board ID = 1
993 17:45:34.308555 Set A53 clk to 24M
994 17:45:34.309031 Set A73 clk to 24M
995 17:45:34.309435 Set clk81 to 24M
996 17:45:34.314154 A53 clk: 1200 MHz
997 17:45:34.314628 A73 clk: 1200 MHz
998 17:45:34.315036 CLK81: 166.6M
999 17:45:34.315436 smccc: 00012abd
1000 17:45:34.319660 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 17:45:34.325296 board id: 1
1002 17:45:34.331204 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 17:45:34.341943 fw parse done
1004 17:45:34.346952 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 17:45:34.390511 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 17:45:34.401441 PIEI prepare done
1007 17:45:34.402028 fastboot data load
1008 17:45:34.402602 fastboot data verify
1009 17:45:34.407132 verify result: 266
1010 17:45:34.412697 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 17:45:34.413301 LPDDR4 probe
1012 17:45:34.413810 ddr clk to 1584MHz
1013 17:45:34.419793 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 17:45:34.457928
1015 17:45:34.458518 dmc_version 0001
1016 17:45:34.464598 Check phy result
1017 17:45:34.470418 INFO : End of CA training
1018 17:45:34.470980 INFO : End of initialization
1019 17:45:34.476372 INFO : Training has run successfully!
1020 17:45:34.476940 Check phy result
1021 17:45:34.481825 INFO : End of initialization
1022 17:45:34.482428 INFO : End of read enable training
1023 17:45:34.485236 INFO : End of fine write leveling
1024 17:45:34.490597 INFO : End of Write leveling coarse delay
1025 17:45:34.496091 INFO : Training has run successfully!
1026 17:45:34.496711 Check phy result
1027 17:45:34.497254 INFO : End of initialization
1028 17:45:34.501580 INFO : End of read dq deskew training
1029 17:45:34.505506 INFO : End of MPR read delay center optimization
1030 17:45:34.511148 INFO : End of write delay center optimization
1031 17:45:34.511776 INFO : End of read delay center optimization
1032 17:45:34.516647 INFO : End of max read latency training
1033 17:45:34.522209 INFO : Training has run successfully!
1034 17:45:34.522804 1D training succeed
1035 17:45:34.530172 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 17:45:34.577837 Check phy result
1037 17:45:34.578491 INFO : End of initialization
1038 17:45:34.598554 INFO : End of 2D read delay Voltage center optimization
1039 17:45:34.619627 INFO : End of 2D read delay Voltage center optimization
1040 17:45:34.671667 INFO : End of 2D write delay Voltage center optimization
1041 17:45:34.721053 INFO : End of 2D write delay Voltage center optimization
1042 17:45:34.726554 INFO : Training has run successfully!
1043 17:45:34.727059
1044 17:45:34.727483 channel==0
1045 17:45:34.732248 RxClkDly_Margin_A0==88 ps 9
1046 17:45:34.732813 TxDqDly_Margin_A0==98 ps 10
1047 17:45:34.737759 RxClkDly_Margin_A1==88 ps 9
1048 17:45:34.738260 TxDqDly_Margin_A1==98 ps 10
1049 17:45:34.738683 TrainedVREFDQ_A0==74
1050 17:45:34.743370 TrainedVREFDQ_A1==74
1051 17:45:34.743942 VrefDac_Margin_A0==25
1052 17:45:34.744430 DeviceVref_Margin_A0==40
1053 17:45:34.749028 VrefDac_Margin_A1==25
1054 17:45:34.749597 DeviceVref_Margin_A1==40
1055 17:45:34.750131
1056 17:45:34.750651
1057 17:45:34.754701 channel==1
1058 17:45:34.755254 RxClkDly_Margin_A0==98 ps 10
1059 17:45:34.755675 TxDqDly_Margin_A0==88 ps 9
1060 17:45:34.760171 RxClkDly_Margin_A1==88 ps 9
1061 17:45:34.760671 TxDqDly_Margin_A1==98 ps 10
1062 17:45:34.765790 TrainedVREFDQ_A0==76
1063 17:45:34.766363 TrainedVREFDQ_A1==78
1064 17:45:34.766818 VrefDac_Margin_A0==22
1065 17:45:34.771411 DeviceVref_Margin_A0==38
1066 17:45:34.772002 VrefDac_Margin_A1==24
1067 17:45:34.776958 DeviceVref_Margin_A1==36
1068 17:45:34.777455
1069 17:45:34.777869 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 17:45:34.778273
1071 17:45:34.810524 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 17:45:34.811177 2D training succeed
1073 17:45:34.816186 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 17:45:34.821774 auto size-- 65535DDR cs0 size: 2048MB
1075 17:45:34.822343 DDR cs1 size: 2048MB
1076 17:45:34.827335 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 17:45:34.827894 cs0 DataBus test pass
1078 17:45:34.832945 cs1 DataBus test pass
1079 17:45:34.833489 cs0 AddrBus test pass
1080 17:45:34.833901 cs1 AddrBus test pass
1081 17:45:34.834306
1082 17:45:34.838572 100bdlr_step_size ps== 420
1083 17:45:34.839137 result report
1084 17:45:34.844205 boot times 0Enable ddr reg access
1085 17:45:34.848536 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 17:45:34.863064 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 17:45:35.436529 0.0;M3 CHK:0;cm4_sp_mode 0
1088 17:45:35.436937 MVN_1=0x00000000
1089 17:45:35.442077 MVN_2=0x00000000
1090 17:45:35.447800 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 17:45:35.448135 OPS=0x10
1092 17:45:35.448368 ring efuse init
1093 17:45:35.448591 chipver efuse init
1094 17:45:35.455974 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 17:45:35.456547 [0.018961 Inits done]
1096 17:45:35.463597 secure task start!
1097 17:45:35.464225 high task start!
1098 17:45:35.464675 low task start!
1099 17:45:35.465128 run into bl31
1100 17:45:35.470282 NOTICE: BL31: v1.3(release):4fc40b1
1101 17:45:35.477849 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 17:45:35.478406 NOTICE: BL31: G12A normal boot!
1103 17:45:35.503483 NOTICE: BL31: BL33 decompress pass
1104 17:45:35.508184 ERROR: Error initializing runtime service opteed_fast
1105 17:45:36.742013
1106 17:45:36.742616
1107 17:45:36.750440 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 17:45:36.750965
1109 17:45:36.751397 Model: Libre Computer AML-A311D-CC Alta
1110 17:45:36.958888 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 17:45:36.981320 DRAM: 2 GiB (effective 3.8 GiB)
1112 17:45:37.125213 Core: 408 devices, 31 uclasses, devicetree: separate
1113 17:45:37.130293 WDT: Not starting watchdog@f0d0
1114 17:45:37.163337 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 17:45:37.175947 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 17:45:37.179833 ** Bad device specification mmc 0 **
1117 17:45:37.191131 Card did not respond to voltage select! : -110
1118 17:45:37.197814 ** Bad device specification mmc 0 **
1119 17:45:37.198302 Couldn't find partition mmc 0
1120 17:45:37.207105 Card did not respond to voltage select! : -110
1121 17:45:37.212598 ** Bad device specification mmc 0 **
1122 17:45:37.213108 Couldn't find partition mmc 0
1123 17:45:37.216726 Error: could not access storage.
1124 17:45:37.560243 Net: eth0: ethernet@ff3f0000
1125 17:45:37.560756 starting USB...
1126 17:45:37.812325 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 17:45:37.813558 Starting the controller
1128 17:45:37.819160 USB XHCI 1.10
1129 17:45:39.376171 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 17:45:39.384383 scanning usb for storage devices... 0 Storage Device(s) found
1132 17:45:39.435891 Hit any key to stop autoboot: 1
1133 17:45:39.436680 end: 2.4.2 bootloader-interrupt (duration 00:00:36) [common]
1134 17:45:39.437239 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 17:45:39.437692 Setting prompt string to ['=>']
1136 17:45:39.438155 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 17:45:39.451932 0
1138 17:45:39.452796 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 17:45:39.453273 Sending with 10 millisecond of delay
1141 17:45:40.587953 => setenv autoload no
1142 17:45:40.598753 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 17:45:40.603560 setenv autoload no
1144 17:45:40.604331 Sending with 10 millisecond of delay
1146 17:45:42.401190 => setenv initrd_high 0xffffffff
1147 17:45:42.412049 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 17:45:42.412942 setenv initrd_high 0xffffffff
1149 17:45:42.413656 Sending with 10 millisecond of delay
1151 17:45:44.030410 => setenv fdt_high 0xffffffff
1152 17:45:44.041183 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 17:45:44.042003 setenv fdt_high 0xffffffff
1154 17:45:44.042706 Sending with 10 millisecond of delay
1156 17:45:44.334621 => dhcp
1157 17:45:44.345375 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1158 17:45:44.346025 dhcp
1159 17:45:44.346287 Speed: 1000, full duplex
1160 17:45:44.346503 BOOTP broadcast 1
1161 17:45:44.356349 DHCP client bound to address 192.168.6.27 (12 ms)
1162 17:45:44.357087 Sending with 10 millisecond of delay
1164 17:45:46.033759 => setenv serverip 192.168.6.2
1165 17:45:46.044549 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 17:45:46.045459 setenv serverip 192.168.6.2
1167 17:45:46.046172 Sending with 10 millisecond of delay
1169 17:45:49.769345 => tftpboot 0x01080000 976221/tftp-deploy-g5t5onf1/kernel/uImage
1170 17:45:49.780090 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 17:45:49.780627 tftpboot 0x01080000 976221/tftp-deploy-g5t5onf1/kernel/uImage
1172 17:45:49.780884 Speed: 1000, full duplex
1173 17:45:49.781100 Using ethernet@ff3f0000 device
1174 17:45:49.782383 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 17:45:49.787920 Filename '976221/tftp-deploy-g5t5onf1/kernel/uImage'.
1176 17:45:49.791918 Load address: 0x1080000
1177 17:45:52.645702 Loading: *################################################## 43.6 MiB
1178 17:45:52.646293 15.3 MiB/s
1179 17:45:52.646726 done
1180 17:45:52.650082 Bytes transferred = 45713984 (2b98a40 hex)
1181 17:45:52.650852 Sending with 10 millisecond of delay
1183 17:45:57.336775 => tftpboot 0x08000000 976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot
1184 17:45:57.348114 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:06)
1185 17:45:57.349330 tftpboot 0x08000000 976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot
1186 17:45:57.350022 Speed: 1000, full duplex
1187 17:45:57.350627 Using ethernet@ff3f0000 device
1188 17:45:57.351607 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 17:45:57.359209 Filename '976221/tftp-deploy-g5t5onf1/ramdisk/ramdisk.cpio.gz.uboot'.
1190 17:45:57.360013 Load address: 0x8000000
1191 17:46:03.839897 Loading: *####################T ############################# UDP wrong checksum 00000005 00007209
1192 17:46:08.841008 T UDP wrong checksum 00000005 00007209
1193 17:46:13.330982 UDP wrong checksum 000000ff 0000d7b5
1194 17:46:13.380382 UDP wrong checksum 000000ff 000068a8
1195 17:46:18.843967 T T UDP wrong checksum 00000005 00007209
1196 17:46:38.845437 T T T UDP wrong checksum 00000005 00007209
1197 17:46:53.852238 T T T
1198 17:46:53.852866 Retry count exceeded; starting again
1200 17:46:53.854286 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1203 17:46:53.856178 end: 2.4 uboot-commands (duration 00:01:51) [common]
1205 17:46:53.857574 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 17:46:53.858647 end: 2 uboot-action (duration 00:01:51) [common]
1209 17:46:53.860154 Cleaning after the job
1210 17:46:53.860710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/ramdisk
1211 17:46:53.861999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/kernel
1212 17:46:53.906948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/dtb
1213 17:46:53.907746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/nfsrootfs
1214 17:46:53.960682 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976221/tftp-deploy-g5t5onf1/modules
1215 17:46:53.983379 start: 4.1 power-off (timeout 00:00:30) [common]
1216 17:46:53.984057 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 17:46:54.017260 >> OK - accepted request
1218 17:46:54.019370 Returned 0 in 0 seconds
1219 17:46:54.120160 end: 4.1 power-off (duration 00:00:00) [common]
1221 17:46:54.121131 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 17:46:54.121789 Listened to connection for namespace 'common' for up to 1s
1223 17:46:55.122729 Finalising connection for namespace 'common'
1224 17:46:55.123245 Disconnecting from shell: Finalise
1225 17:46:55.123529 =>
1226 17:46:55.224310 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 17:46:55.224913 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/976221
1228 17:46:58.037252 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/976221
1229 17:46:58.037881 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.