Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:47:23.192932 lava-dispatcher, installed at version: 2024.01
2 17:47:23.193792 start: 0 validate
3 17:47:23.194293 Start time: 2024-11-11 17:47:23.194264+00:00 (UTC)
4 17:47:23.194821 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:47:23.195341 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:47:23.233909 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:47:23.234458 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:47:23.264564 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:47:23.265177 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:47:23.293915 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:47:23.294552 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:47:23.324545 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:47:23.325048 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fbroonie-spi%2Ffor-next%2Fspi-fix-v6.12-rc6-63-g38408d27f529%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:47:23.365530 validate duration: 0.17
16 17:47:23.366404 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:47:23.366735 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:47:23.367060 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:47:23.367633 Not decompressing ramdisk as can be used compressed.
20 17:47:23.368050 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 17:47:23.368343 saving as /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/ramdisk/initrd.cpio.gz
22 17:47:23.368615 total size: 5628140 (5 MB)
23 17:47:23.404992 progress 0 % (0 MB)
24 17:47:23.409442 progress 5 % (0 MB)
25 17:47:23.413629 progress 10 % (0 MB)
26 17:47:23.417289 progress 15 % (0 MB)
27 17:47:23.421235 progress 20 % (1 MB)
28 17:47:23.424858 progress 25 % (1 MB)
29 17:47:23.428926 progress 30 % (1 MB)
30 17:47:23.433027 progress 35 % (1 MB)
31 17:47:23.436600 progress 40 % (2 MB)
32 17:47:23.440646 progress 45 % (2 MB)
33 17:47:23.444268 progress 50 % (2 MB)
34 17:47:23.448255 progress 55 % (2 MB)
35 17:47:23.452393 progress 60 % (3 MB)
36 17:47:23.456102 progress 65 % (3 MB)
37 17:47:23.460223 progress 70 % (3 MB)
38 17:47:23.463864 progress 75 % (4 MB)
39 17:47:23.467862 progress 80 % (4 MB)
40 17:47:23.471566 progress 85 % (4 MB)
41 17:47:23.475518 progress 90 % (4 MB)
42 17:47:23.479215 progress 95 % (5 MB)
43 17:47:23.482547 progress 100 % (5 MB)
44 17:47:23.483193 5 MB downloaded in 0.11 s (46.85 MB/s)
45 17:47:23.483763 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:47:23.484667 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:47:23.484961 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:47:23.485229 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:47:23.485699 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/kernel/Image
51 17:47:23.485949 saving as /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/kernel/Image
52 17:47:23.486158 total size: 45713920 (43 MB)
53 17:47:23.486375 No compression specified
54 17:47:23.522874 progress 0 % (0 MB)
55 17:47:23.551297 progress 5 % (2 MB)
56 17:47:23.579919 progress 10 % (4 MB)
57 17:47:23.608338 progress 15 % (6 MB)
58 17:47:23.636883 progress 20 % (8 MB)
59 17:47:23.664896 progress 25 % (10 MB)
60 17:47:23.692960 progress 30 % (13 MB)
61 17:47:23.721314 progress 35 % (15 MB)
62 17:47:23.749321 progress 40 % (17 MB)
63 17:47:23.777701 progress 45 % (19 MB)
64 17:47:23.806449 progress 50 % (21 MB)
65 17:47:23.835664 progress 55 % (24 MB)
66 17:47:23.867395 progress 60 % (26 MB)
67 17:47:23.896640 progress 65 % (28 MB)
68 17:47:23.926252 progress 70 % (30 MB)
69 17:47:23.955548 progress 75 % (32 MB)
70 17:47:23.985122 progress 80 % (34 MB)
71 17:47:24.014020 progress 85 % (37 MB)
72 17:47:24.043552 progress 90 % (39 MB)
73 17:47:24.073395 progress 95 % (41 MB)
74 17:47:24.101640 progress 100 % (43 MB)
75 17:47:24.102163 43 MB downloaded in 0.62 s (70.77 MB/s)
76 17:47:24.102635 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:47:24.103445 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:47:24.103718 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:47:24.104006 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:47:24.104487 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 17:47:24.104761 saving as /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/dtb/meson-g12b-a311d-libretech-cc.dtb
83 17:47:24.104970 total size: 54703 (0 MB)
84 17:47:24.105177 No compression specified
85 17:47:24.143922 progress 59 % (0 MB)
86 17:47:24.144807 progress 100 % (0 MB)
87 17:47:24.145353 0 MB downloaded in 0.04 s (1.29 MB/s)
88 17:47:24.145824 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:47:24.146641 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:47:24.146904 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:47:24.147167 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:47:24.147629 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 17:47:24.147873 saving as /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/nfsrootfs/full.rootfs.tar
95 17:47:24.148129 total size: 474398908 (452 MB)
96 17:47:24.148343 Using unxz to decompress xz
97 17:47:24.180906 progress 0 % (0 MB)
98 17:47:25.280013 progress 5 % (22 MB)
99 17:47:26.725131 progress 10 % (45 MB)
100 17:47:27.158676 progress 15 % (67 MB)
101 17:47:27.985462 progress 20 % (90 MB)
102 17:47:28.558819 progress 25 % (113 MB)
103 17:47:28.912660 progress 30 % (135 MB)
104 17:47:29.509472 progress 35 % (158 MB)
105 17:47:30.362027 progress 40 % (181 MB)
106 17:47:31.089715 progress 45 % (203 MB)
107 17:47:31.641811 progress 50 % (226 MB)
108 17:47:32.287687 progress 55 % (248 MB)
109 17:47:33.494247 progress 60 % (271 MB)
110 17:47:34.966004 progress 65 % (294 MB)
111 17:47:36.581377 progress 70 % (316 MB)
112 17:47:39.674678 progress 75 % (339 MB)
113 17:47:42.119340 progress 80 % (361 MB)
114 17:47:45.036089 progress 85 % (384 MB)
115 17:47:48.212162 progress 90 % (407 MB)
116 17:47:51.936092 progress 95 % (429 MB)
117 17:47:55.108954 progress 100 % (452 MB)
118 17:47:55.121936 452 MB downloaded in 30.97 s (14.61 MB/s)
119 17:47:55.122882 end: 1.4.1 http-download (duration 00:00:31) [common]
121 17:47:55.124682 end: 1.4 download-retry (duration 00:00:31) [common]
122 17:47:55.125245 start: 1.5 download-retry (timeout 00:09:28) [common]
123 17:47:55.125798 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 17:47:55.126942 downloading http://storage.kernelci.org/broonie-spi/for-next/spi-fix-v6.12-rc6-63-g38408d27f529/arm64/defconfig/gcc-12/modules.tar.xz
125 17:47:55.127464 saving as /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/modules/modules.tar
126 17:47:55.127905 total size: 11600216 (11 MB)
127 17:47:55.128401 Using unxz to decompress xz
128 17:47:55.169648 progress 0 % (0 MB)
129 17:47:55.236023 progress 5 % (0 MB)
130 17:47:55.310112 progress 10 % (1 MB)
131 17:47:55.406193 progress 15 % (1 MB)
132 17:47:55.498513 progress 20 % (2 MB)
133 17:47:55.577305 progress 25 % (2 MB)
134 17:47:55.653064 progress 30 % (3 MB)
135 17:47:55.727749 progress 35 % (3 MB)
136 17:47:55.804679 progress 40 % (4 MB)
137 17:47:55.880960 progress 45 % (5 MB)
138 17:47:55.964954 progress 50 % (5 MB)
139 17:47:56.042102 progress 55 % (6 MB)
140 17:47:56.126904 progress 60 % (6 MB)
141 17:47:56.207340 progress 65 % (7 MB)
142 17:47:56.283458 progress 70 % (7 MB)
143 17:47:56.366095 progress 75 % (8 MB)
144 17:47:56.449341 progress 80 % (8 MB)
145 17:47:56.525585 progress 85 % (9 MB)
146 17:47:56.608246 progress 90 % (9 MB)
147 17:47:56.685475 progress 95 % (10 MB)
148 17:47:56.762391 progress 100 % (11 MB)
149 17:47:56.772438 11 MB downloaded in 1.64 s (6.73 MB/s)
150 17:47:56.772997 end: 1.5.1 http-download (duration 00:00:02) [common]
152 17:47:56.773823 end: 1.5 download-retry (duration 00:00:02) [common]
153 17:47:56.774091 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 17:47:56.774355 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 17:48:12.075432 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/976223/extract-nfsrootfs-7glk_335
156 17:48:12.076069 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 17:48:12.076360 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 17:48:12.077080 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58
159 17:48:12.077521 makedir: /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin
160 17:48:12.077845 makedir: /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/tests
161 17:48:12.078156 makedir: /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/results
162 17:48:12.078486 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-add-keys
163 17:48:12.079000 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-add-sources
164 17:48:12.079513 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-background-process-start
165 17:48:12.080060 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-background-process-stop
166 17:48:12.080592 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-common-functions
167 17:48:12.081085 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-echo-ipv4
168 17:48:12.081559 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-install-packages
169 17:48:12.082029 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-installed-packages
170 17:48:12.082497 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-os-build
171 17:48:12.083030 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-probe-channel
172 17:48:12.083523 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-probe-ip
173 17:48:12.084035 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-target-ip
174 17:48:12.084558 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-target-mac
175 17:48:12.085036 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-target-storage
176 17:48:12.085511 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-case
177 17:48:12.085981 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-event
178 17:48:12.086439 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-feedback
179 17:48:12.086895 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-raise
180 17:48:12.087379 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-reference
181 17:48:12.087873 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-runner
182 17:48:12.088386 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-set
183 17:48:12.088859 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-test-shell
184 17:48:12.089333 Updating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-install-packages (oe)
185 17:48:12.089858 Updating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/bin/lava-installed-packages (oe)
186 17:48:12.090285 Creating /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/environment
187 17:48:12.090647 LAVA metadata
188 17:48:12.090900 - LAVA_JOB_ID=976223
189 17:48:12.091112 - LAVA_DISPATCHER_IP=192.168.6.2
190 17:48:12.091471 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 17:48:12.092444 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 17:48:12.092761 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 17:48:12.092966 skipped lava-vland-overlay
194 17:48:12.093203 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 17:48:12.093454 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 17:48:12.093668 skipped lava-multinode-overlay
197 17:48:12.093907 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 17:48:12.094153 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 17:48:12.094397 Loading test definitions
200 17:48:12.094672 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 17:48:12.094891 Using /lava-976223 at stage 0
202 17:48:12.096060 uuid=976223_1.6.2.4.1 testdef=None
203 17:48:12.096374 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 17:48:12.096633 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 17:48:12.098351 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 17:48:12.099174 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 17:48:12.101327 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 17:48:12.102150 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 17:48:12.104208 runner path: /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 976223_1.6.2.4.1
212 17:48:12.104778 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 17:48:12.105533 Creating lava-test-runner.conf files
215 17:48:12.105732 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/976223/lava-overlay-7irjhu58/lava-976223/0 for stage 0
216 17:48:12.106058 - 0_v4l2-decoder-conformance-vp9
217 17:48:12.106392 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 17:48:12.106660 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 17:48:12.127732 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 17:48:12.128155 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 17:48:12.128413 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 17:48:12.128675 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 17:48:12.128937 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 17:48:12.751918 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 17:48:12.752424 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 17:48:12.752671 extracting modules file /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976223/extract-nfsrootfs-7glk_335
227 17:48:14.104229 extracting modules file /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976223/extract-overlay-ramdisk-_27qbrl4/ramdisk
228 17:48:15.504215 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 17:48:15.504689 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 17:48:15.504963 [common] Applying overlay to NFS
231 17:48:15.505174 [common] Applying overlay /var/lib/lava/dispatcher/tmp/976223/compress-overlay-ld6kgx67/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/976223/extract-nfsrootfs-7glk_335
232 17:48:15.534547 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 17:48:15.534953 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 17:48:15.535224 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 17:48:15.535469 Converting downloaded kernel to a uImage
236 17:48:15.535793 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/kernel/Image /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/kernel/uImage
237 17:48:16.044646 output: Image Name:
238 17:48:16.045065 output: Created: Mon Nov 11 17:48:15 2024
239 17:48:16.045271 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 17:48:16.045475 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 17:48:16.045675 output: Load Address: 01080000
242 17:48:16.045871 output: Entry Point: 01080000
243 17:48:16.046067 output:
244 17:48:16.046401 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 17:48:16.046665 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 17:48:16.046932 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 17:48:16.047181 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 17:48:16.047436 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 17:48:16.047688 Building ramdisk /var/lib/lava/dispatcher/tmp/976223/extract-overlay-ramdisk-_27qbrl4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/976223/extract-overlay-ramdisk-_27qbrl4/ramdisk
250 17:48:18.193220 >> 166774 blocks
251 17:48:25.947777 Adding RAMdisk u-boot header.
252 17:48:25.948534 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/976223/extract-overlay-ramdisk-_27qbrl4/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/976223/extract-overlay-ramdisk-_27qbrl4/ramdisk.cpio.gz.uboot
253 17:48:26.196786 output: Image Name:
254 17:48:26.197185 output: Created: Mon Nov 11 17:48:25 2024
255 17:48:26.197400 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 17:48:26.197606 output: Data Size: 23425931 Bytes = 22876.89 KiB = 22.34 MiB
257 17:48:26.197807 output: Load Address: 00000000
258 17:48:26.198004 output: Entry Point: 00000000
259 17:48:26.198201 output:
260 17:48:26.198807 rename /var/lib/lava/dispatcher/tmp/976223/extract-overlay-ramdisk-_27qbrl4/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot
261 17:48:26.199226 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 17:48:26.199513 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 17:48:26.199806 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 17:48:26.200179 No LXC device requested
265 17:48:26.200754 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 17:48:26.201318 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 17:48:26.201863 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 17:48:26.202311 Checking files for TFTP limit of 4294967296 bytes.
269 17:48:26.205310 end: 1 tftp-deploy (duration 00:01:03) [common]
270 17:48:26.205935 start: 2 uboot-action (timeout 00:05:00) [common]
271 17:48:26.206508 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 17:48:26.207049 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 17:48:26.207596 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 17:48:26.208198 Using kernel file from prepare-kernel: 976223/tftp-deploy-ed4d1q8g/kernel/uImage
275 17:48:26.208886 substitutions:
276 17:48:26.209331 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 17:48:26.209769 - {DTB_ADDR}: 0x01070000
278 17:48:26.210203 - {DTB}: 976223/tftp-deploy-ed4d1q8g/dtb/meson-g12b-a311d-libretech-cc.dtb
279 17:48:26.210637 - {INITRD}: 976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot
280 17:48:26.211073 - {KERNEL_ADDR}: 0x01080000
281 17:48:26.211500 - {KERNEL}: 976223/tftp-deploy-ed4d1q8g/kernel/uImage
282 17:48:26.211929 - {LAVA_MAC}: None
283 17:48:26.212438 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/976223/extract-nfsrootfs-7glk_335
284 17:48:26.212876 - {NFS_SERVER_IP}: 192.168.6.2
285 17:48:26.213302 - {PRESEED_CONFIG}: None
286 17:48:26.213729 - {PRESEED_LOCAL}: None
287 17:48:26.214154 - {RAMDISK_ADDR}: 0x08000000
288 17:48:26.214577 - {RAMDISK}: 976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot
289 17:48:26.215002 - {ROOT_PART}: None
290 17:48:26.215425 - {ROOT}: None
291 17:48:26.215847 - {SERVER_IP}: 192.168.6.2
292 17:48:26.216304 - {TEE_ADDR}: 0x83000000
293 17:48:26.216735 - {TEE}: None
294 17:48:26.217160 Parsed boot commands:
295 17:48:26.217574 - setenv autoload no
296 17:48:26.217997 - setenv initrd_high 0xffffffff
297 17:48:26.218415 - setenv fdt_high 0xffffffff
298 17:48:26.218835 - dhcp
299 17:48:26.219256 - setenv serverip 192.168.6.2
300 17:48:26.219674 - tftpboot 0x01080000 976223/tftp-deploy-ed4d1q8g/kernel/uImage
301 17:48:26.220124 - tftpboot 0x08000000 976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot
302 17:48:26.220549 - tftpboot 0x01070000 976223/tftp-deploy-ed4d1q8g/dtb/meson-g12b-a311d-libretech-cc.dtb
303 17:48:26.220972 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976223/extract-nfsrootfs-7glk_335,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 17:48:26.221407 - bootm 0x01080000 0x08000000 0x01070000
305 17:48:26.221945 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 17:48:26.223544 start: 2.3 connect-device (timeout 00:05:00) [common]
308 17:48:26.224052 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 17:48:26.239456 Setting prompt string to ['lava-test: # ']
310 17:48:26.241099 end: 2.3 connect-device (duration 00:00:00) [common]
311 17:48:26.241747 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 17:48:26.242341 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 17:48:26.242927 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 17:48:26.244169 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 17:48:26.282085 >> OK - accepted request
316 17:48:26.284167 Returned 0 in 0 seconds
317 17:48:26.385465 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 17:48:26.387283 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 17:48:26.387917 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 17:48:26.388558 Setting prompt string to ['Hit any key to stop autoboot']
322 17:48:26.389084 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 17:48:26.390830 Trying 192.168.56.21...
324 17:48:26.391351 Connected to conserv1.
325 17:48:26.391822 Escape character is '^]'.
326 17:48:26.392357
327 17:48:26.392848 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 17:48:26.393317
329 17:48:38.001897 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 17:48:38.002319 bl2_stage_init 0x01
331 17:48:38.002536 bl2_stage_init 0x81
332 17:48:38.007525 hw id: 0x0000 - pwm id 0x01
333 17:48:38.007838 bl2_stage_init 0xc1
334 17:48:38.008107 bl2_stage_init 0x02
335 17:48:38.008313
336 17:48:38.013132 L0:00000000
337 17:48:38.013824 L1:20000703
338 17:48:38.014344 L2:00008067
339 17:48:38.014853 L3:14000000
340 17:48:38.015953 B2:00402000
341 17:48:38.016450 B1:e0f83180
342 17:48:38.016867
343 17:48:38.017265 TE: 58124
344 17:48:38.017657
345 17:48:38.027201 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 17:48:38.027668
347 17:48:38.028099 Board ID = 1
348 17:48:38.028492 Set A53 clk to 24M
349 17:48:38.028877 Set A73 clk to 24M
350 17:48:38.032804 Set clk81 to 24M
351 17:48:38.033242 A53 clk: 1200 MHz
352 17:48:38.033628 A73 clk: 1200 MHz
353 17:48:38.036210 CLK81: 166.6M
354 17:48:38.036645 smccc: 00012a92
355 17:48:38.041744 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 17:48:38.047282 board id: 1
357 17:48:38.051760 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 17:48:38.063272 fw parse done
359 17:48:38.068490 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 17:48:38.111325 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 17:48:38.122721 PIEI prepare done
362 17:48:38.123192 fastboot data load
363 17:48:38.123586 fastboot data verify
364 17:48:38.128227 verify result: 266
365 17:48:38.133896 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 17:48:38.134380 LPDDR4 probe
367 17:48:38.134796 ddr clk to 1584MHz
368 17:48:38.141016 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 17:48:38.178812
370 17:48:38.179309 dmc_version 0001
371 17:48:38.185184 Check phy result
372 17:48:38.191782 INFO : End of CA training
373 17:48:38.192288 INFO : End of initialization
374 17:48:38.197274 INFO : Training has run successfully!
375 17:48:38.197758 Check phy result
376 17:48:38.202881 INFO : End of initialization
377 17:48:38.203363 INFO : End of read enable training
378 17:48:38.208442 INFO : End of fine write leveling
379 17:48:38.214044 INFO : End of Write leveling coarse delay
380 17:48:38.214525 INFO : Training has run successfully!
381 17:48:38.214937 Check phy result
382 17:48:38.219805 INFO : End of initialization
383 17:48:38.220313 INFO : End of read dq deskew training
384 17:48:38.225263 INFO : End of MPR read delay center optimization
385 17:48:38.230831 INFO : End of write delay center optimization
386 17:48:38.236468 INFO : End of read delay center optimization
387 17:48:38.236949 INFO : End of max read latency training
388 17:48:38.242045 INFO : Training has run successfully!
389 17:48:38.242523 1D training succeed
390 17:48:38.250935 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 17:48:38.298924 Check phy result
392 17:48:38.299438 INFO : End of initialization
393 17:48:38.319818 INFO : End of 2D read delay Voltage center optimization
394 17:48:38.340610 INFO : End of 2D read delay Voltage center optimization
395 17:48:38.393158 INFO : End of 2D write delay Voltage center optimization
396 17:48:38.442235 INFO : End of 2D write delay Voltage center optimization
397 17:48:38.447772 INFO : Training has run successfully!
398 17:48:38.448266
399 17:48:38.448697 channel==0
400 17:48:38.453349 RxClkDly_Margin_A0==88 ps 9
401 17:48:38.453791 TxDqDly_Margin_A0==98 ps 10
402 17:48:38.456744 RxClkDly_Margin_A1==88 ps 9
403 17:48:38.457196 TxDqDly_Margin_A1==98 ps 10
404 17:48:38.462166 TrainedVREFDQ_A0==74
405 17:48:38.462600 TrainedVREFDQ_A1==74
406 17:48:38.467754 VrefDac_Margin_A0==25
407 17:48:38.468224 DeviceVref_Margin_A0==40
408 17:48:38.468629 VrefDac_Margin_A1==25
409 17:48:38.473425 DeviceVref_Margin_A1==40
410 17:48:38.473870
411 17:48:38.474277
412 17:48:38.474673 channel==1
413 17:48:38.475065 RxClkDly_Margin_A0==98 ps 10
414 17:48:38.478954 TxDqDly_Margin_A0==88 ps 9
415 17:48:38.479398 RxClkDly_Margin_A1==98 ps 10
416 17:48:38.484563 TxDqDly_Margin_A1==88 ps 9
417 17:48:38.485002 TrainedVREFDQ_A0==75
418 17:48:38.485407 TrainedVREFDQ_A1==77
419 17:48:38.490167 VrefDac_Margin_A0==22
420 17:48:38.490600 DeviceVref_Margin_A0==38
421 17:48:38.495823 VrefDac_Margin_A1==22
422 17:48:38.496316 DeviceVref_Margin_A1==37
423 17:48:38.496725
424 17:48:38.501374 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 17:48:38.501825
426 17:48:38.529366 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 17:48:38.534934 2D training succeed
428 17:48:38.540564 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 17:48:38.541003 auto size-- 65535DDR cs0 size: 2048MB
430 17:48:38.546147 DDR cs1 size: 2048MB
431 17:48:38.546596 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 17:48:38.551744 cs0 DataBus test pass
433 17:48:38.552225 cs1 DataBus test pass
434 17:48:38.552635 cs0 AddrBus test pass
435 17:48:38.557350 cs1 AddrBus test pass
436 17:48:38.557783
437 17:48:38.558189 100bdlr_step_size ps== 420
438 17:48:38.558592 result report
439 17:48:38.562969 boot times 0Enable ddr reg access
440 17:48:38.570049 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 17:48:38.583727 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 17:48:39.157918 0.0;M3 CHK:0;cm4_sp_mode 0
443 17:48:39.158509 MVN_1=0x00000000
444 17:48:39.163327 MVN_2=0x00000000
445 17:48:39.169063 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 17:48:39.169508 OPS=0x10
447 17:48:39.169918 ring efuse init
448 17:48:39.170316 chipver efuse init
449 17:48:39.177433 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 17:48:39.177878 [0.018961 Inits done]
451 17:48:39.178277 secure task start!
452 17:48:39.184898 high task start!
453 17:48:39.185331 low task start!
454 17:48:39.185736 run into bl31
455 17:48:39.191529 NOTICE: BL31: v1.3(release):4fc40b1
456 17:48:39.198447 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 17:48:39.198897 NOTICE: BL31: G12A normal boot!
458 17:48:39.224814 NOTICE: BL31: BL33 decompress pass
459 17:48:39.230083 ERROR: Error initializing runtime service opteed_fast
460 17:48:40.463317
461 17:48:40.463913
462 17:48:40.471007 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 17:48:40.471462
464 17:48:40.471873 Model: Libre Computer AML-A311D-CC Alta
465 17:48:40.679289 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 17:48:40.702597 DRAM: 2 GiB (effective 3.8 GiB)
467 17:48:40.846467 Core: 408 devices, 31 uclasses, devicetree: separate
468 17:48:40.852030 WDT: Not starting watchdog@f0d0
469 17:48:40.884604 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 17:48:40.897178 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 17:48:40.901359 ** Bad device specification mmc 0 **
472 17:48:40.912390 Card did not respond to voltage select! : -110
473 17:48:40.919788 ** Bad device specification mmc 0 **
474 17:48:40.920263 Couldn't find partition mmc 0
475 17:48:40.928374 Card did not respond to voltage select! : -110
476 17:48:40.933896 ** Bad device specification mmc 0 **
477 17:48:40.934328 Couldn't find partition mmc 0
478 17:48:40.938451 Error: could not access storage.
479 17:48:42.202171 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 17:48:42.202774 bl2_stage_init 0x01
481 17:48:42.203202 bl2_stage_init 0x81
482 17:48:42.207589 hw id: 0x0000 - pwm id 0x01
483 17:48:42.208095 bl2_stage_init 0xc1
484 17:48:42.208510 bl2_stage_init 0x02
485 17:48:42.208905
486 17:48:42.213193 L0:00000000
487 17:48:42.213636 L1:20000703
488 17:48:42.214040 L2:00008067
489 17:48:42.214432 L3:14000000
490 17:48:42.218773 B2:00402000
491 17:48:42.219224 B1:e0f83180
492 17:48:42.219621
493 17:48:42.220050 TE: 58124
494 17:48:42.220455
495 17:48:42.224378 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 17:48:42.224831
497 17:48:42.225236 Board ID = 1
498 17:48:42.230083 Set A53 clk to 24M
499 17:48:42.230517 Set A73 clk to 24M
500 17:48:42.230915 Set clk81 to 24M
501 17:48:42.235573 A53 clk: 1200 MHz
502 17:48:42.236031 A73 clk: 1200 MHz
503 17:48:42.236436 CLK81: 166.6M
504 17:48:42.236831 smccc: 00012a92
505 17:48:42.241154 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 17:48:42.246773 board id: 1
507 17:48:42.252086 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 17:48:42.263309 fw parse done
509 17:48:42.268679 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 17:48:42.311058 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 17:48:42.322833 PIEI prepare done
512 17:48:42.323291 fastboot data load
513 17:48:42.323697 fastboot data verify
514 17:48:42.328554 verify result: 266
515 17:48:42.334212 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 17:48:42.334692 LPDDR4 probe
517 17:48:42.335097 ddr clk to 1584MHz
518 17:48:42.341243 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 17:48:42.378897
520 17:48:42.379516 dmc_version 0001
521 17:48:42.385400 Check phy result
522 17:48:42.391875 INFO : End of CA training
523 17:48:42.392353 INFO : End of initialization
524 17:48:42.397475 INFO : Training has run successfully!
525 17:48:42.397924 Check phy result
526 17:48:42.403183 INFO : End of initialization
527 17:48:42.403629 INFO : End of read enable training
528 17:48:42.408669 INFO : End of fine write leveling
529 17:48:42.414302 INFO : End of Write leveling coarse delay
530 17:48:42.414750 INFO : Training has run successfully!
531 17:48:42.415149 Check phy result
532 17:48:42.419844 INFO : End of initialization
533 17:48:42.420330 INFO : End of read dq deskew training
534 17:48:42.425441 INFO : End of MPR read delay center optimization
535 17:48:42.431035 INFO : End of write delay center optimization
536 17:48:42.436687 INFO : End of read delay center optimization
537 17:48:42.437121 INFO : End of max read latency training
538 17:48:42.442303 INFO : Training has run successfully!
539 17:48:42.442776 1D training succeed
540 17:48:42.451309 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 17:48:42.498949 Check phy result
542 17:48:42.499454 INFO : End of initialization
543 17:48:42.520767 INFO : End of 2D read delay Voltage center optimization
544 17:48:42.540751 INFO : End of 2D read delay Voltage center optimization
545 17:48:42.592492 INFO : End of 2D write delay Voltage center optimization
546 17:48:42.642419 INFO : End of 2D write delay Voltage center optimization
547 17:48:42.648023 INFO : Training has run successfully!
548 17:48:42.648489
549 17:48:42.648895 channel==0
550 17:48:42.653637 RxClkDly_Margin_A0==88 ps 9
551 17:48:42.654103 TxDqDly_Margin_A0==98 ps 10
552 17:48:42.659234 RxClkDly_Margin_A1==88 ps 9
553 17:48:42.659683 TxDqDly_Margin_A1==98 ps 10
554 17:48:42.660117 TrainedVREFDQ_A0==74
555 17:48:42.664774 TrainedVREFDQ_A1==74
556 17:48:42.665221 VrefDac_Margin_A0==25
557 17:48:42.665622 DeviceVref_Margin_A0==40
558 17:48:42.670355 VrefDac_Margin_A1==25
559 17:48:42.670774 DeviceVref_Margin_A1==40
560 17:48:42.671168
561 17:48:42.671561
562 17:48:42.675963 channel==1
563 17:48:42.676419 RxClkDly_Margin_A0==98 ps 10
564 17:48:42.676815 TxDqDly_Margin_A0==98 ps 10
565 17:48:42.681529 RxClkDly_Margin_A1==88 ps 9
566 17:48:42.681971 TxDqDly_Margin_A1==98 ps 10
567 17:48:42.687176 TrainedVREFDQ_A0==77
568 17:48:42.687609 TrainedVREFDQ_A1==77
569 17:48:42.688036 VrefDac_Margin_A0==22
570 17:48:42.692760 DeviceVref_Margin_A0==37
571 17:48:42.693184 VrefDac_Margin_A1==24
572 17:48:42.698354 DeviceVref_Margin_A1==37
573 17:48:42.698782
574 17:48:42.699178 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 17:48:42.703948
576 17:48:42.732049 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 17:48:42.732561 2D training succeed
578 17:48:42.737613 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 17:48:42.743254 auto size-- 65535DDR cs0 size: 2048MB
580 17:48:42.743697 DDR cs1 size: 2048MB
581 17:48:42.748779 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 17:48:42.749212 cs0 DataBus test pass
583 17:48:42.754325 cs1 DataBus test pass
584 17:48:42.754757 cs0 AddrBus test pass
585 17:48:42.755153 cs1 AddrBus test pass
586 17:48:42.755542
587 17:48:42.759924 100bdlr_step_size ps== 420
588 17:48:42.760409 result report
589 17:48:42.765526 boot times 0Enable ddr reg access
590 17:48:42.770354 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 17:48:42.783783 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 17:48:43.358468 0.0;M3 CHK:0;cm4_sp_mode 0
593 17:48:43.359105 MVN_1=0x00000000
594 17:48:43.363829 MVN_2=0x00000000
595 17:48:43.369497 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 17:48:43.369978 OPS=0x10
597 17:48:43.370388 ring efuse init
598 17:48:43.370807 chipver efuse init
599 17:48:43.375336 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 17:48:43.380791 [0.018961 Inits done]
601 17:48:43.381240 secure task start!
602 17:48:43.381633 high task start!
603 17:48:43.384864 low task start!
604 17:48:43.385291 run into bl31
605 17:48:43.392010 NOTICE: BL31: v1.3(release):4fc40b1
606 17:48:43.399007 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 17:48:43.399496 NOTICE: BL31: G12A normal boot!
608 17:48:43.425282 NOTICE: BL31: BL33 decompress pass
609 17:48:43.430874 ERROR: Error initializing runtime service opteed_fast
610 17:48:44.663753
611 17:48:44.664387
612 17:48:44.672176 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 17:48:44.672624
614 17:48:44.673050 Model: Libre Computer AML-A311D-CC Alta
615 17:48:44.880655 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 17:48:44.904057 DRAM: 2 GiB (effective 3.8 GiB)
617 17:48:45.047108 Core: 408 devices, 31 uclasses, devicetree: separate
618 17:48:45.052788 WDT: Not starting watchdog@f0d0
619 17:48:45.085225 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 17:48:45.097584 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 17:48:45.102520 ** Bad device specification mmc 0 **
622 17:48:45.112856 Card did not respond to voltage select! : -110
623 17:48:45.120520 ** Bad device specification mmc 0 **
624 17:48:45.120961 Couldn't find partition mmc 0
625 17:48:45.128786 Card did not respond to voltage select! : -110
626 17:48:45.134324 ** Bad device specification mmc 0 **
627 17:48:45.134762 Couldn't find partition mmc 0
628 17:48:45.139359 Error: could not access storage.
629 17:48:45.481938 Net: eth0: ethernet@ff3f0000
630 17:48:45.482555 starting USB...
631 17:48:45.733813 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 17:48:45.734369 Starting the controller
633 17:48:45.740841 USB XHCI 1.10
634 17:48:47.452960 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 17:48:47.453563 bl2_stage_init 0x01
636 17:48:47.453987 bl2_stage_init 0x81
637 17:48:47.458480 hw id: 0x0000 - pwm id 0x01
638 17:48:47.458936 bl2_stage_init 0xc1
639 17:48:47.459343 bl2_stage_init 0x02
640 17:48:47.459740
641 17:48:47.464079 L0:00000000
642 17:48:47.464518 L1:20000703
643 17:48:47.464919 L2:00008067
644 17:48:47.465316 L3:14000000
645 17:48:47.469736 B2:00402000
646 17:48:47.470171 B1:e0f83180
647 17:48:47.470575
648 17:48:47.470971 TE: 58124
649 17:48:47.471365
650 17:48:47.475247 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 17:48:47.475684
652 17:48:47.476121 Board ID = 1
653 17:48:47.480819 Set A53 clk to 24M
654 17:48:47.481264 Set A73 clk to 24M
655 17:48:47.481665 Set clk81 to 24M
656 17:48:47.486438 A53 clk: 1200 MHz
657 17:48:47.486903 A73 clk: 1200 MHz
658 17:48:47.487309 CLK81: 166.6M
659 17:48:47.487706 smccc: 00012a92
660 17:48:47.492083 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 17:48:47.497736 board id: 1
662 17:48:47.502926 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 17:48:47.514193 fw parse done
664 17:48:47.519162 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 17:48:47.562865 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 17:48:47.573695 PIEI prepare done
667 17:48:47.574161 fastboot data load
668 17:48:47.574571 fastboot data verify
669 17:48:47.579441 verify result: 266
670 17:48:47.584956 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 17:48:47.585418 LPDDR4 probe
672 17:48:47.585824 ddr clk to 1584MHz
673 17:48:47.591951 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 17:48:47.629206
675 17:48:47.629667 dmc_version 0001
676 17:48:47.636780 Check phy result
677 17:48:47.642698 INFO : End of CA training
678 17:48:47.643125 INFO : End of initialization
679 17:48:47.648262 INFO : Training has run successfully!
680 17:48:47.648691 Check phy result
681 17:48:47.653889 INFO : End of initialization
682 17:48:47.654314 INFO : End of read enable training
683 17:48:47.659454 INFO : End of fine write leveling
684 17:48:47.665078 INFO : End of Write leveling coarse delay
685 17:48:47.665508 INFO : Training has run successfully!
686 17:48:47.665907 Check phy result
687 17:48:47.670820 INFO : End of initialization
688 17:48:47.671245 INFO : End of read dq deskew training
689 17:48:47.676289 INFO : End of MPR read delay center optimization
690 17:48:47.681933 INFO : End of write delay center optimization
691 17:48:47.687470 INFO : End of read delay center optimization
692 17:48:47.687895 INFO : End of max read latency training
693 17:48:47.693115 INFO : Training has run successfully!
694 17:48:47.693541 1D training succeed
695 17:48:47.702266 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 17:48:47.749000 Check phy result
697 17:48:47.749450 INFO : End of initialization
698 17:48:47.771518 INFO : End of 2D read delay Voltage center optimization
699 17:48:47.791808 INFO : End of 2D read delay Voltage center optimization
700 17:48:47.843734 INFO : End of 2D write delay Voltage center optimization
701 17:48:47.894148 INFO : End of 2D write delay Voltage center optimization
702 17:48:47.899637 INFO : Training has run successfully!
703 17:48:47.900094
704 17:48:47.900515 channel==0
705 17:48:47.905245 RxClkDly_Margin_A0==88 ps 9
706 17:48:47.905688 TxDqDly_Margin_A0==98 ps 10
707 17:48:47.910879 RxClkDly_Margin_A1==88 ps 9
708 17:48:47.911307 TxDqDly_Margin_A1==98 ps 10
709 17:48:47.911713 TrainedVREFDQ_A0==74
710 17:48:47.916409 TrainedVREFDQ_A1==74
711 17:48:47.916842 VrefDac_Margin_A0==24
712 17:48:47.917243 DeviceVref_Margin_A0==40
713 17:48:47.922011 VrefDac_Margin_A1==24
714 17:48:47.922439 DeviceVref_Margin_A1==40
715 17:48:47.922839
716 17:48:47.923233
717 17:48:47.927651 channel==1
718 17:48:47.928142 RxClkDly_Margin_A0==98 ps 10
719 17:48:47.928552 TxDqDly_Margin_A0==98 ps 10
720 17:48:47.933210 RxClkDly_Margin_A1==88 ps 9
721 17:48:47.933646 TxDqDly_Margin_A1==88 ps 9
722 17:48:47.938880 TrainedVREFDQ_A0==77
723 17:48:47.939310 TrainedVREFDQ_A1==77
724 17:48:47.939713 VrefDac_Margin_A0==22
725 17:48:47.944393 DeviceVref_Margin_A0==37
726 17:48:47.944822 VrefDac_Margin_A1==24
727 17:48:47.950001 DeviceVref_Margin_A1==37
728 17:48:47.950427
729 17:48:47.950829 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 17:48:47.951223
731 17:48:47.983614 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 17:48:47.984113 2D training succeed
733 17:48:47.989412 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 17:48:47.994893 auto size-- 65535DDR cs0 size: 2048MB
735 17:48:47.995320 DDR cs1 size: 2048MB
736 17:48:48.000417 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 17:48:48.000845 cs0 DataBus test pass
738 17:48:48.006051 cs1 DataBus test pass
739 17:48:48.006508 cs0 AddrBus test pass
740 17:48:48.006912 cs1 AddrBus test pass
741 17:48:48.007305
742 17:48:48.011637 100bdlr_step_size ps== 420
743 17:48:48.012131 result report
744 17:48:48.017243 boot times 0Enable ddr reg access
745 17:48:48.023251 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 17:48:48.035183 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 17:48:48.609821 0.0;M3 CHK:0;cm4_sp_mode 0
748 17:48:48.610439 MVN_1=0x00000000
749 17:48:48.615290 MVN_2=0x00000000
750 17:48:48.621076 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 17:48:48.621578 OPS=0x10
752 17:48:48.621974 ring efuse init
753 17:48:48.622389 chipver efuse init
754 17:48:48.626625 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 17:48:48.632244 [0.018960 Inits done]
756 17:48:48.632676 secure task start!
757 17:48:48.633065 high task start!
758 17:48:48.636841 low task start!
759 17:48:48.637261 run into bl31
760 17:48:48.643471 NOTICE: BL31: v1.3(release):4fc40b1
761 17:48:48.651237 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 17:48:48.651660 NOTICE: BL31: G12A normal boot!
763 17:48:48.676680 NOTICE: BL31: BL33 decompress pass
764 17:48:48.682329 ERROR: Error initializing runtime service opteed_fast
765 17:48:49.915495
766 17:48:49.916161
767 17:48:49.923661 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 17:48:49.924138
769 17:48:49.924549 Model: Libre Computer AML-A311D-CC Alta
770 17:48:50.132262 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 17:48:50.154735 DRAM: 2 GiB (effective 3.8 GiB)
772 17:48:50.298431 Core: 408 devices, 31 uclasses, devicetree: separate
773 17:48:50.304338 WDT: Not starting watchdog@f0d0
774 17:48:50.336590 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 17:48:50.349143 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 17:48:50.354017 ** Bad device specification mmc 0 **
777 17:48:50.364391 Card did not respond to voltage select! : -110
778 17:48:50.372027 ** Bad device specification mmc 0 **
779 17:48:50.372480 Couldn't find partition mmc 0
780 17:48:50.380339 Card did not respond to voltage select! : -110
781 17:48:50.385849 ** Bad device specification mmc 0 **
782 17:48:50.386281 Couldn't find partition mmc 0
783 17:48:50.390925 Error: could not access storage.
784 17:48:50.734428 Net: eth0: ethernet@ff3f0000
785 17:48:50.734988 starting USB...
786 17:48:50.986614 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 17:48:50.987086 Starting the controller
788 17:48:50.993457 USB XHCI 1.10
789 17:48:53.063905 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 17:48:53.064532 bl2_stage_init 0x01
791 17:48:53.064946 bl2_stage_init 0x81
792 17:48:53.069440 hw id: 0x0000 - pwm id 0x01
793 17:48:53.069874 bl2_stage_init 0xc1
794 17:48:53.070274 bl2_stage_init 0x02
795 17:48:53.070671
796 17:48:53.075049 L0:00000000
797 17:48:53.075479 L1:20000703
798 17:48:53.075876 L2:00008067
799 17:48:53.076307 L3:14000000
800 17:48:53.080650 B2:00402000
801 17:48:53.081078 B1:e0f83180
802 17:48:53.081479
803 17:48:53.081870 TE: 58167
804 17:48:53.082264
805 17:48:53.086233 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 17:48:53.086664
807 17:48:53.087064 Board ID = 1
808 17:48:53.091814 Set A53 clk to 24M
809 17:48:53.092266 Set A73 clk to 24M
810 17:48:53.092664 Set clk81 to 24M
811 17:48:53.097405 A53 clk: 1200 MHz
812 17:48:53.097833 A73 clk: 1200 MHz
813 17:48:53.098229 CLK81: 166.6M
814 17:48:53.098618 smccc: 00012abe
815 17:48:53.103003 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 17:48:53.108656 board id: 1
817 17:48:53.114444 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 17:48:53.125119 fw parse done
819 17:48:53.131123 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 17:48:53.173700 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 17:48:53.184627 PIEI prepare done
822 17:48:53.185053 fastboot data load
823 17:48:53.185455 fastboot data verify
824 17:48:53.190276 verify result: 266
825 17:48:53.195858 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 17:48:53.196321 LPDDR4 probe
827 17:48:53.196722 ddr clk to 1584MHz
828 17:48:53.203838 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 17:48:53.241159
830 17:48:53.241598 dmc_version 0001
831 17:48:53.247796 Check phy result
832 17:48:53.253682 INFO : End of CA training
833 17:48:53.254105 INFO : End of initialization
834 17:48:53.259279 INFO : Training has run successfully!
835 17:48:53.259697 Check phy result
836 17:48:53.264823 INFO : End of initialization
837 17:48:53.265243 INFO : End of read enable training
838 17:48:53.270511 INFO : End of fine write leveling
839 17:48:53.276193 INFO : End of Write leveling coarse delay
840 17:48:53.276746 INFO : Training has run successfully!
841 17:48:53.277156 Check phy result
842 17:48:53.281742 INFO : End of initialization
843 17:48:53.282206 INFO : End of read dq deskew training
844 17:48:53.287254 INFO : End of MPR read delay center optimization
845 17:48:53.292828 INFO : End of write delay center optimization
846 17:48:53.298507 INFO : End of read delay center optimization
847 17:48:53.298961 INFO : End of max read latency training
848 17:48:53.304290 INFO : Training has run successfully!
849 17:48:53.304786 1D training succeed
850 17:48:53.313268 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 17:48:53.360308 Check phy result
852 17:48:53.360877 INFO : End of initialization
853 17:48:53.381844 INFO : End of 2D read delay Voltage center optimization
854 17:48:53.402090 INFO : End of 2D read delay Voltage center optimization
855 17:48:53.453508 INFO : End of 2D write delay Voltage center optimization
856 17:48:53.503865 INFO : End of 2D write delay Voltage center optimization
857 17:48:53.509254 INFO : Training has run successfully!
858 17:48:53.509702
859 17:48:53.510142 channel==0
860 17:48:53.514966 RxClkDly_Margin_A0==88 ps 9
861 17:48:53.515417 TxDqDly_Margin_A0==98 ps 10
862 17:48:53.520449 RxClkDly_Margin_A1==88 ps 9
863 17:48:53.520884 TxDqDly_Margin_A1==98 ps 10
864 17:48:53.521289 TrainedVREFDQ_A0==74
865 17:48:53.526044 TrainedVREFDQ_A1==74
866 17:48:53.526479 VrefDac_Margin_A0==25
867 17:48:53.526876 DeviceVref_Margin_A0==40
868 17:48:53.531720 VrefDac_Margin_A1==25
869 17:48:53.532178 DeviceVref_Margin_A1==40
870 17:48:53.532576
871 17:48:53.532967
872 17:48:53.537228 channel==1
873 17:48:53.537656 RxClkDly_Margin_A0==98 ps 10
874 17:48:53.538058 TxDqDly_Margin_A0==88 ps 9
875 17:48:53.542877 RxClkDly_Margin_A1==88 ps 9
876 17:48:53.543321 TxDqDly_Margin_A1==88 ps 9
877 17:48:53.548459 TrainedVREFDQ_A0==76
878 17:48:53.548910 TrainedVREFDQ_A1==77
879 17:48:53.549313 VrefDac_Margin_A0==22
880 17:48:53.554052 DeviceVref_Margin_A0==38
881 17:48:53.554489 VrefDac_Margin_A1==24
882 17:48:53.559723 DeviceVref_Margin_A1==37
883 17:48:53.560204
884 17:48:53.560610 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 17:48:53.561001
886 17:48:53.593230 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 17:48:53.593699 2D training succeed
888 17:48:53.598864 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 17:48:53.604458 auto size-- 65535DDR cs0 size: 2048MB
890 17:48:53.604913 DDR cs1 size: 2048MB
891 17:48:53.610033 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 17:48:53.610477 cs0 DataBus test pass
893 17:48:53.615761 cs1 DataBus test pass
894 17:48:53.616270 cs0 AddrBus test pass
895 17:48:53.616659 cs1 AddrBus test pass
896 17:48:53.617041
897 17:48:53.621268 100bdlr_step_size ps== 420
898 17:48:53.621740 result report
899 17:48:53.626899 boot times 0Enable ddr reg access
900 17:48:53.632267 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 17:48:53.644633 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 17:48:54.217655 0.0;M3 CHK:0;cm4_sp_mode 0
903 17:48:54.218237 MVN_1=0x00000000
904 17:48:54.223091 MVN_2=0x00000000
905 17:48:54.228831 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 17:48:54.229263 OPS=0x10
907 17:48:54.229667 ring efuse init
908 17:48:54.230060 chipver efuse init
909 17:48:54.234435 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 17:48:54.240074 [0.018961 Inits done]
911 17:48:54.240499 secure task start!
912 17:48:54.240895 high task start!
913 17:48:54.243739 low task start!
914 17:48:54.244205 run into bl31
915 17:48:54.251248 NOTICE: BL31: v1.3(release):4fc40b1
916 17:48:54.258182 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 17:48:54.258619 NOTICE: BL31: G12A normal boot!
918 17:48:54.284374 NOTICE: BL31: BL33 decompress pass
919 17:48:54.289662 ERROR: Error initializing runtime service opteed_fast
920 17:48:55.523208
921 17:48:55.523836
922 17:48:55.531299 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 17:48:55.531825
924 17:48:55.532292 Model: Libre Computer AML-A311D-CC Alta
925 17:48:55.739893 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 17:48:55.763252 DRAM: 2 GiB (effective 3.8 GiB)
927 17:48:55.906278 Core: 408 devices, 31 uclasses, devicetree: separate
928 17:48:55.912101 WDT: Not starting watchdog@f0d0
929 17:48:55.944298 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 17:48:55.956808 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 17:48:55.961803 ** Bad device specification mmc 0 **
932 17:48:55.972067 Card did not respond to voltage select! : -110
933 17:48:55.979726 ** Bad device specification mmc 0 **
934 17:48:55.980200 Couldn't find partition mmc 0
935 17:48:55.988072 Card did not respond to voltage select! : -110
936 17:48:55.993572 ** Bad device specification mmc 0 **
937 17:48:55.994033 Couldn't find partition mmc 0
938 17:48:55.998613 Error: could not access storage.
939 17:48:56.341387 Net: eth0: ethernet@ff3f0000
940 17:48:56.342023 starting USB...
941 17:48:56.594097 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 17:48:56.594751 Starting the controller
943 17:48:56.601013 USB XHCI 1.10
944 17:48:58.464074 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 17:48:58.464708 bl2_stage_init 0x01
946 17:48:58.465176 bl2_stage_init 0x81
947 17:48:58.469699 hw id: 0x0000 - pwm id 0x01
948 17:48:58.470211 bl2_stage_init 0xc1
949 17:48:58.470669 bl2_stage_init 0x02
950 17:48:58.471110
951 17:48:58.475184 L0:00000000
952 17:48:58.475690 L1:20000703
953 17:48:58.476179 L2:00008067
954 17:48:58.476624 L3:14000000
955 17:48:58.480861 B2:00402000
956 17:48:58.481359 B1:e0f83180
957 17:48:58.481801
958 17:48:58.482240 TE: 58167
959 17:48:58.482680
960 17:48:58.486251 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 17:48:58.486766
962 17:48:58.487220 Board ID = 1
963 17:48:58.492066 Set A53 clk to 24M
964 17:48:58.492598 Set A73 clk to 24M
965 17:48:58.493050 Set clk81 to 24M
966 17:48:58.497747 A53 clk: 1200 MHz
967 17:48:58.498252 A73 clk: 1200 MHz
968 17:48:58.498699 CLK81: 166.6M
969 17:48:58.499138 smccc: 00012abe
970 17:48:58.503084 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 17:48:58.508684 board id: 1
972 17:48:58.514606 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 17:48:58.525172 fw parse done
974 17:48:58.531153 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 17:48:58.573779 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 17:48:58.584682 PIEI prepare done
977 17:48:58.585176 fastboot data load
978 17:48:58.585624 fastboot data verify
979 17:48:58.590316 verify result: 266
980 17:48:58.595927 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 17:48:58.596465 LPDDR4 probe
982 17:48:58.596911 ddr clk to 1584MHz
983 17:48:58.603940 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 17:48:58.641218
985 17:48:58.641747 dmc_version 0001
986 17:48:58.647870 Check phy result
987 17:48:58.653721 INFO : End of CA training
988 17:48:58.654226 INFO : End of initialization
989 17:48:58.659289 INFO : Training has run successfully!
990 17:48:58.659782 Check phy result
991 17:48:58.664867 INFO : End of initialization
992 17:48:58.665359 INFO : End of read enable training
993 17:48:58.668196 INFO : End of fine write leveling
994 17:48:58.673688 INFO : End of Write leveling coarse delay
995 17:48:58.679302 INFO : Training has run successfully!
996 17:48:58.679786 Check phy result
997 17:48:58.680268 INFO : End of initialization
998 17:48:58.684947 INFO : End of read dq deskew training
999 17:48:58.690581 INFO : End of MPR read delay center optimization
1000 17:48:58.691071 INFO : End of write delay center optimization
1001 17:48:58.696158 INFO : End of read delay center optimization
1002 17:48:58.701691 INFO : End of max read latency training
1003 17:48:58.702179 INFO : Training has run successfully!
1004 17:48:58.707295 1D training succeed
1005 17:48:58.713279 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 17:48:58.760834 Check phy result
1007 17:48:58.761332 INFO : End of initialization
1008 17:48:58.783461 INFO : End of 2D read delay Voltage center optimization
1009 17:48:58.803652 INFO : End of 2D read delay Voltage center optimization
1010 17:48:58.854927 INFO : End of 2D write delay Voltage center optimization
1011 17:48:58.905259 INFO : End of 2D write delay Voltage center optimization
1012 17:48:58.910805 INFO : Training has run successfully!
1013 17:48:58.911298
1014 17:48:58.911764 channel==0
1015 17:48:58.916519 RxClkDly_Margin_A0==88 ps 9
1016 17:48:58.917017 TxDqDly_Margin_A0==98 ps 10
1017 17:48:58.919808 RxClkDly_Margin_A1==88 ps 9
1018 17:48:58.920335 TxDqDly_Margin_A1==98 ps 10
1019 17:48:58.925498 TrainedVREFDQ_A0==74
1020 17:48:58.925997 TrainedVREFDQ_A1==74
1021 17:48:58.926454 VrefDac_Margin_A0==25
1022 17:48:58.931254 DeviceVref_Margin_A0==40
1023 17:48:58.931752 VrefDac_Margin_A1==25
1024 17:48:58.936743 DeviceVref_Margin_A1==40
1025 17:48:58.937238
1026 17:48:58.937687
1027 17:48:58.938130 channel==1
1028 17:48:58.938561 RxClkDly_Margin_A0==98 ps 10
1029 17:48:58.942381 TxDqDly_Margin_A0==98 ps 10
1030 17:48:58.942880 RxClkDly_Margin_A1==98 ps 10
1031 17:48:58.947603 TxDqDly_Margin_A1==88 ps 9
1032 17:48:58.948131 TrainedVREFDQ_A0==77
1033 17:48:58.948587 TrainedVREFDQ_A1==77
1034 17:48:58.953265 VrefDac_Margin_A0==22
1035 17:48:58.953761 DeviceVref_Margin_A0==37
1036 17:48:58.958849 VrefDac_Margin_A1==22
1037 17:48:58.959341 DeviceVref_Margin_A1==37
1038 17:48:58.959783
1039 17:48:58.964438 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 17:48:58.964930
1041 17:48:58.992373 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 17:48:58.998044 2D training succeed
1043 17:48:59.003621 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 17:48:59.004146 auto size-- 65535DDR cs0 size: 2048MB
1045 17:48:59.009262 DDR cs1 size: 2048MB
1046 17:48:59.009762 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 17:48:59.014863 cs0 DataBus test pass
1048 17:48:59.015377 cs1 DataBus test pass
1049 17:48:59.015824 cs0 AddrBus test pass
1050 17:48:59.020471 cs1 AddrBus test pass
1051 17:48:59.020988
1052 17:48:59.021439 100bdlr_step_size ps== 420
1053 17:48:59.021886 result report
1054 17:48:59.026036 boot times 0Enable ddr reg access
1055 17:48:59.032759 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 17:48:59.047099 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 17:48:59.620710 0.0;M3 CHK:0;cm4_sp_mode 0
1058 17:48:59.621324 MVN_1=0x00000000
1059 17:48:59.626223 MVN_2=0x00000000
1060 17:48:59.631969 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 17:48:59.632509 OPS=0x10
1062 17:48:59.632961 ring efuse init
1063 17:48:59.633400 chipver efuse init
1064 17:48:59.637613 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 17:48:59.643175 [0.018961 Inits done]
1066 17:48:59.643668 secure task start!
1067 17:48:59.644152 high task start!
1068 17:48:59.647788 low task start!
1069 17:48:59.648312 run into bl31
1070 17:48:59.654428 NOTICE: BL31: v1.3(release):4fc40b1
1071 17:48:59.662272 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 17:48:59.662769 NOTICE: BL31: G12A normal boot!
1073 17:48:59.687608 NOTICE: BL31: BL33 decompress pass
1074 17:48:59.693289 ERROR: Error initializing runtime service opteed_fast
1075 17:49:00.926195
1076 17:49:00.926831
1077 17:49:00.934723 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 17:49:00.935237
1079 17:49:00.935698 Model: Libre Computer AML-A311D-CC Alta
1080 17:49:01.143035 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 17:49:01.166453 DRAM: 2 GiB (effective 3.8 GiB)
1082 17:49:01.309409 Core: 408 devices, 31 uclasses, devicetree: separate
1083 17:49:01.315326 WDT: Not starting watchdog@f0d0
1084 17:49:01.347589 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 17:49:01.360048 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 17:49:01.364132 ** Bad device specification mmc 0 **
1087 17:49:01.375355 Card did not respond to voltage select! : -110
1088 17:49:01.382002 ** Bad device specification mmc 0 **
1089 17:49:01.382510 Couldn't find partition mmc 0
1090 17:49:01.391303 Card did not respond to voltage select! : -110
1091 17:49:01.396846 ** Bad device specification mmc 0 **
1092 17:49:01.397362 Couldn't find partition mmc 0
1093 17:49:01.401874 Error: could not access storage.
1094 17:49:01.743389 Net: eth0: ethernet@ff3f0000
1095 17:49:01.743943 starting USB...
1096 17:49:01.996170 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 17:49:01.996750 Starting the controller
1098 17:49:02.002243 USB XHCI 1.10
1099 17:49:03.556947 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 17:49:03.565082 scanning usb for storage devices... 0 Storage Device(s) found
1102 17:49:03.617089 Hit any key to stop autoboot: 1
1103 17:49:03.618298 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 17:49:03.619097 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 17:49:03.619738 Setting prompt string to ['=>']
1106 17:49:03.620457 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 17:49:03.632832 0
1108 17:49:03.634041 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 17:49:03.634724 Sending with 10 millisecond of delay
1111 17:49:04.770646 => setenv autoload no
1112 17:49:04.781678 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1113 17:49:04.788053 setenv autoload no
1114 17:49:04.788940 Sending with 10 millisecond of delay
1116 17:49:06.587024 => setenv initrd_high 0xffffffff
1117 17:49:06.597618 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 17:49:06.598195 setenv initrd_high 0xffffffff
1119 17:49:06.598666 Sending with 10 millisecond of delay
1121 17:49:08.215700 => setenv fdt_high 0xffffffff
1122 17:49:08.226506 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 17:49:08.227338 setenv fdt_high 0xffffffff
1124 17:49:08.228060 Sending with 10 millisecond of delay
1126 17:49:08.520080 => dhcp
1127 17:49:08.530663 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 17:49:08.531234 dhcp
1129 17:49:08.531484 Speed: 1000, full duplex
1130 17:49:08.531701 BOOTP broadcast 1
1131 17:49:08.539093 DHCP client bound to address 192.168.6.27 (8 ms)
1132 17:49:08.539733 Sending with 10 millisecond of delay
1134 17:49:10.217471 => setenv serverip 192.168.6.2
1135 17:49:10.228328 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 17:49:10.229364 setenv serverip 192.168.6.2
1137 17:49:10.230105 Sending with 10 millisecond of delay
1139 17:49:13.955092 => tftpboot 0x01080000 976223/tftp-deploy-ed4d1q8g/kernel/uImage
1140 17:49:13.965943 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 17:49:13.966832 tftpboot 0x01080000 976223/tftp-deploy-ed4d1q8g/kernel/uImage
1142 17:49:13.967343 Speed: 1000, full duplex
1143 17:49:13.967806 Using ethernet@ff3f0000 device
1144 17:49:13.968677 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 17:49:13.974284 Filename '976223/tftp-deploy-ed4d1q8g/kernel/uImage'.
1146 17:49:13.978035 Load address: 0x1080000
1147 17:49:15.495375 Loading: *######################### UDP wrong checksum 000000ff 00004b94
1148 17:49:15.508447 UDP wrong checksum 000000ff 0000df86
1149 17:49:16.362333 ############## UDP wrong checksum 000000ff 0000ff6a
1150 17:49:16.369102 UDP wrong checksum 000000ff 00008c5d
1151 17:49:17.003017 ########### 43.6 MiB
1152 17:49:17.003660 14.4 MiB/s
1153 17:49:17.004182 done
1154 17:49:17.007389 Bytes transferred = 45713984 (2b98a40 hex)
1155 17:49:17.008185 Sending with 10 millisecond of delay
1157 17:49:21.698164 => tftpboot 0x08000000 976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot
1158 17:49:21.708962 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1159 17:49:21.709815 tftpboot 0x08000000 976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot
1160 17:49:21.710231 Speed: 1000, full duplex
1161 17:49:21.710621 Using ethernet@ff3f0000 device
1162 17:49:21.711824 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1163 17:49:21.720455 Filename '976223/tftp-deploy-ed4d1q8g/ramdisk/ramdisk.cpio.gz.uboot'.
1164 17:49:21.720892 Load address: 0x8000000
1165 17:49:28.365283 Loading: *################T ################################# UDP wrong checksum 00000005 0000ba87
1166 17:49:33.364436 T UDP wrong checksum 00000005 0000ba87
1167 17:49:34.548176 UDP wrong checksum 000000ff 000024fe
1168 17:49:34.556131 UDP wrong checksum 000000ff 0000b2f0
1169 17:49:43.366995 T T UDP wrong checksum 00000005 0000ba87
1170 17:50:03.370975 T T T T UDP wrong checksum 00000005 0000ba87
1171 17:50:18.375306 T T
1172 17:50:18.376017 Retry count exceeded; starting again
1174 17:50:18.377558 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1177 17:50:18.379598 end: 2.4 uboot-commands (duration 00:01:52) [common]
1179 17:50:18.381853 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1181 17:50:18.382983 end: 2 uboot-action (duration 00:01:52) [common]
1183 17:50:18.384677 Cleaning after the job
1184 17:50:18.385274 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/ramdisk
1185 17:50:18.386744 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/kernel
1186 17:50:18.419735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/dtb
1187 17:50:18.421211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/nfsrootfs
1188 17:50:18.477579 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976223/tftp-deploy-ed4d1q8g/modules
1189 17:50:18.484156 start: 4.1 power-off (timeout 00:00:30) [common]
1190 17:50:18.484758 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1191 17:50:18.518220 >> OK - accepted request
1192 17:50:18.520397 Returned 0 in 0 seconds
1193 17:50:18.621516 end: 4.1 power-off (duration 00:00:00) [common]
1195 17:50:18.622549 start: 4.2 read-feedback (timeout 00:10:00) [common]
1196 17:50:18.623215 Listened to connection for namespace 'common' for up to 1s
1197 17:50:19.623539 Finalising connection for namespace 'common'
1198 17:50:19.624339 Disconnecting from shell: Finalise
1199 17:50:19.624896 =>
1200 17:50:19.726037 end: 4.2 read-feedback (duration 00:00:01) [common]
1201 17:50:19.726740 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/976223
1202 17:50:22.164576 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/976223
1203 17:50:22.165190 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.