Boot log: hip07-d05
- Warnings: 2
- Kernel Warnings: 0
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
1 07:45:27.809717 Action timeout for pdu-reboot exceeds Job timeout
2 07:45:27.867166 lava-dispatcher, installed at version: 2023.01
3 07:45:27.867434 start: 0 validate
4 07:45:27.867706 Start time: 2023-03-12 07:45:27.867693+00:00 (UTC)
5 07:45:27.867993 Using caching service: 'http://localhost/cache/?uri=%s'
6 07:45:27.868305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230303.0%2Farm64%2Finitrd.cpio.gz exists
7 07:45:28.189114 Using caching service: 'http://localhost/cache/?uri=%s'
8 07:45:28.189490 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.273-cip92-277-g507c8d80b9e20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
9 07:45:28.480820 Using caching service: 'http://localhost/cache/?uri=%s'
10 07:45:28.481190 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.273-cip92-277-g507c8d80b9e20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fhisilicon%2Fhip07-d05.dtb exists
11 07:45:28.771197 Using caching service: 'http://localhost/cache/?uri=%s'
12 07:45:28.771527 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230303.0%2Farm64%2Ffull.rootfs.tar.xz exists
13 07:45:29.062327 Using caching service: 'http://localhost/cache/?uri=%s'
14 07:45:29.062702 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.273-cip92-277-g507c8d80b9e20%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
15 07:45:29.351157 validate duration: 1.48
17 07:45:29.351805 start: 1 tftp-deploy (timeout 00:10:00) [common]
18 07:45:29.352047 start: 1.1 download-retry (timeout 00:10:00) [common]
19 07:45:29.352283 start: 1.1.1 http-download (timeout 00:10:00) [common]
20 07:45:29.352558 Not decompressing ramdisk as can be used compressed.
21 07:45:29.352769 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230303.0/arm64/initrd.cpio.gz
22 07:45:29.352934 saving as /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/ramdisk/initrd.cpio.gz
23 07:45:29.353098 total size: 4662262 (4MB)
24 07:45:29.354949 progress 0% (0MB)
25 07:45:29.358260 progress 5% (0MB)
26 07:45:29.361246 progress 10% (0MB)
27 07:45:29.364248 progress 15% (0MB)
28 07:45:29.367125 progress 20% (0MB)
29 07:45:29.369995 progress 25% (1MB)
30 07:45:29.372902 progress 30% (1MB)
31 07:45:29.375760 progress 35% (1MB)
32 07:45:29.378625 progress 40% (1MB)
33 07:45:29.381849 progress 45% (2MB)
34 07:45:29.384751 progress 50% (2MB)
35 07:45:29.387609 progress 55% (2MB)
36 07:45:29.390470 progress 60% (2MB)
37 07:45:29.393370 progress 65% (2MB)
38 07:45:29.396220 progress 70% (3MB)
39 07:45:29.399023 progress 75% (3MB)
40 07:45:29.401883 progress 80% (3MB)
41 07:45:29.404804 progress 85% (3MB)
42 07:45:29.408017 progress 90% (4MB)
43 07:45:29.410890 progress 95% (4MB)
44 07:45:29.413743 progress 100% (4MB)
45 07:45:29.414080 4MB downloaded in 0.06s (72.92MB/s)
46 07:45:29.414432 end: 1.1.1 http-download (duration 00:00:00) [common]
48 07:45:29.415019 end: 1.1 download-retry (duration 00:00:00) [common]
49 07:45:29.415237 start: 1.2 download-retry (timeout 00:10:00) [common]
50 07:45:29.415454 start: 1.2.1 http-download (timeout 00:10:00) [common]
51 07:45:29.415760 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.273-cip92-277-g507c8d80b9e20/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
52 07:45:29.415927 saving as /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/kernel/Image
53 07:45:29.416089 total size: 24465920 (23MB)
54 07:45:29.416262 No compression specified
55 07:45:29.418095 progress 0% (0MB)
56 07:45:29.432833 progress 5% (1MB)
57 07:45:29.447362 progress 10% (2MB)
58 07:45:29.461940 progress 15% (3MB)
59 07:45:29.477075 progress 20% (4MB)
60 07:45:29.491569 progress 25% (5MB)
61 07:45:29.506077 progress 30% (7MB)
62 07:45:29.521174 progress 35% (8MB)
63 07:45:29.535746 progress 40% (9MB)
64 07:45:29.550130 progress 45% (10MB)
65 07:45:29.565098 progress 50% (11MB)
66 07:45:29.579590 progress 55% (12MB)
67 07:45:29.594159 progress 60% (14MB)
68 07:45:29.609118 progress 65% (15MB)
69 07:45:29.624044 progress 70% (16MB)
70 07:45:29.638747 progress 75% (17MB)
71 07:45:29.653786 progress 80% (18MB)
72 07:45:29.668322 progress 85% (19MB)
73 07:45:29.682596 progress 90% (21MB)
74 07:45:29.697199 progress 95% (22MB)
75 07:45:29.711377 progress 100% (23MB)
76 07:45:29.711835 23MB downloaded in 0.30s (78.90MB/s)
77 07:45:29.712224 end: 1.2.1 http-download (duration 00:00:00) [common]
79 07:45:29.712819 end: 1.2 download-retry (duration 00:00:00) [common]
80 07:45:29.713046 start: 1.3 download-retry (timeout 00:10:00) [common]
81 07:45:29.713270 start: 1.3.1 http-download (timeout 00:10:00) [common]
82 07:45:29.713583 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.273-cip92-277-g507c8d80b9e20/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/hisilicon/hip07-d05.dtb
83 07:45:29.713752 saving as /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/dtb/hip07-d05.dtb
84 07:45:29.713924 total size: 34901 (0MB)
85 07:45:29.714084 No compression specified
86 07:45:29.715949 progress 93% (0MB)
87 07:45:29.716561 progress 100% (0MB)
88 07:45:29.716811 0MB downloaded in 0.00s (11.56MB/s)
89 07:45:29.717110 end: 1.3.1 http-download (duration 00:00:00) [common]
91 07:45:29.717706 end: 1.3 download-retry (duration 00:00:00) [common]
92 07:45:29.717930 start: 1.4 download-retry (timeout 00:10:00) [common]
93 07:45:29.718145 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 07:45:29.718415 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230303.0/arm64/full.rootfs.tar.xz
95 07:45:29.718600 saving as /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/nfsrootfs/full.rootfs.tar
96 07:45:29.718763 total size: 200798964 (191MB)
97 07:45:29.718923 Using unxz to decompress xz
98 07:45:29.724528 progress 0% (0MB)
99 07:45:30.670919 progress 5% (9MB)
100 07:45:31.561364 progress 10% (19MB)
101 07:45:32.650958 progress 15% (28MB)
102 07:45:33.307514 progress 20% (38MB)
103 07:45:33.992503 progress 25% (47MB)
104 07:45:35.099893 progress 30% (57MB)
105 07:45:36.090375 progress 35% (67MB)
106 07:45:37.179855 progress 40% (76MB)
107 07:45:38.195328 progress 45% (86MB)
108 07:45:39.294161 progress 50% (95MB)
109 07:45:40.637274 progress 55% (105MB)
110 07:45:41.844897 progress 60% (114MB)
111 07:45:42.075530 progress 65% (124MB)
112 07:45:42.371931 progress 70% (134MB)
113 07:45:42.564127 progress 75% (143MB)
114 07:45:42.715545 progress 80% (153MB)
115 07:45:42.870002 progress 85% (162MB)
116 07:45:43.073425 progress 90% (172MB)
117 07:45:43.960084 progress 95% (181MB)
118 07:45:45.125583 progress 100% (191MB)
119 07:45:45.138205 191MB downloaded in 15.42s (12.42MB/s)
120 07:45:45.139134 end: 1.4.1 http-download (duration 00:00:15) [common]
122 07:45:45.140132 end: 1.4 download-retry (duration 00:00:15) [common]
123 07:45:45.140456 start: 1.5 download-retry (timeout 00:09:44) [common]
124 07:45:45.140814 start: 1.5.1 http-download (timeout 00:09:44) [common]
125 07:45:45.141308 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.273-cip92-277-g507c8d80b9e20/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
126 07:45:45.141581 saving as /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/modules/modules.tar
127 07:45:45.141817 total size: 4134496 (3MB)
128 07:45:45.142063 Using unxz to decompress xz
129 07:45:45.442389 progress 0% (0MB)
130 07:45:45.467439 progress 5% (0MB)
131 07:45:45.488031 progress 10% (0MB)
132 07:45:45.510833 progress 15% (0MB)
133 07:45:45.540541 progress 20% (0MB)
134 07:45:45.564014 progress 25% (1MB)
135 07:45:45.588225 progress 30% (1MB)
136 07:45:45.620017 progress 35% (1MB)
137 07:45:45.644863 progress 40% (1MB)
138 07:45:45.667389 progress 45% (1MB)
139 07:45:45.695342 progress 50% (2MB)
140 07:45:45.718969 progress 55% (2MB)
141 07:45:45.742500 progress 60% (2MB)
142 07:45:45.767848 progress 65% (2MB)
143 07:45:45.789997 progress 70% (2MB)
144 07:45:45.817328 progress 75% (2MB)
145 07:45:45.843050 progress 80% (3MB)
146 07:45:45.869392 progress 85% (3MB)
147 07:45:45.890434 progress 90% (3MB)
148 07:45:45.914010 progress 95% (3MB)
149 07:45:45.939904 progress 100% (3MB)
150 07:45:45.950224 3MB downloaded in 0.81s (4.88MB/s)
151 07:45:45.951151 end: 1.5.1 http-download (duration 00:00:01) [common]
153 07:45:45.952175 end: 1.5 download-retry (duration 00:00:01) [common]
154 07:45:45.952529 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
155 07:45:45.953005 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
156 07:46:05.207760 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a
157 07:46:05.208302 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
158 07:46:05.208573 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
159 07:46:05.209060 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy
160 07:46:05.209414 makedir: /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin
161 07:46:05.209698 makedir: /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/tests
162 07:46:05.209965 makedir: /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/results
163 07:46:05.210264 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-add-keys
164 07:46:05.210726 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-add-sources
165 07:46:05.211107 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-background-process-start
166 07:46:05.211486 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-background-process-stop
167 07:46:05.211860 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-common-functions
168 07:46:05.212245 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-echo-ipv4
169 07:46:05.212617 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-install-packages
170 07:46:05.212987 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-installed-packages
171 07:46:05.213354 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-os-build
172 07:46:05.213726 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-probe-channel
173 07:46:05.214112 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-probe-ip
174 07:46:05.214478 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-target-ip
175 07:46:05.214930 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-target-mac
176 07:46:05.215309 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-target-storage
177 07:46:05.215687 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-case
178 07:46:05.216060 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-event
179 07:46:05.216444 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-feedback
180 07:46:05.216813 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-raise
181 07:46:05.217183 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-reference
182 07:46:05.217553 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-runner
183 07:46:05.217925 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-set
184 07:46:05.218334 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-test-shell
185 07:46:05.218730 Updating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-add-keys (debian)
186 07:46:05.219121 Updating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-add-sources (debian)
187 07:46:05.219504 Updating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-install-packages (debian)
188 07:46:05.219884 Updating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-installed-packages (debian)
189 07:46:05.220276 Updating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/bin/lava-os-build (debian)
190 07:46:05.220605 Creating /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/environment
191 07:46:05.220871 LAVA metadata
192 07:46:05.221063 - LAVA_JOB_ID=9568079
193 07:46:05.221243 - LAVA_DISPATCHER_IP=192.168.101.1
194 07:46:05.221543 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:24) [common]
195 07:46:05.221718 skipped lava-vland-overlay
196 07:46:05.221933 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
197 07:46:05.222165 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:24) [common]
198 07:46:05.222341 skipped lava-multinode-overlay
199 07:46:05.222619 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
200 07:46:05.222869 start: 1.6.2.3 test-definition (timeout 00:09:24) [common]
201 07:46:05.223076 Loading test definitions
202 07:46:05.223348 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:24) [common]
203 07:46:05.223546 Using /lava-9568079 at stage 0
204 07:46:05.224365 uuid=9568079_1.6.2.3.1 testdef=None
205 07:46:05.224596 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
206 07:46:05.224834 start: 1.6.2.3.2 test-overlay (timeout 00:09:24) [common]
207 07:46:05.226145 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
209 07:46:05.226829 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:24) [common]
210 07:46:05.228370 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
212 07:46:05.228977 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:24) [common]
213 07:46:05.230415 runner path: /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/0/tests/0_timesync-off test_uuid 9568079_1.6.2.3.1
214 07:46:05.230873 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
216 07:46:05.231501 start: 1.6.2.3.5 git-repo-action (timeout 00:09:24) [common]
217 07:46:05.231709 Using /lava-9568079 at stage 0
218 07:46:05.231999 Fetching tests from https://github.com/kernelci/test-definitions.git
219 07:46:05.232241 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/0/tests/1_kselftest-futex'
220 07:46:14.728764 Running '/usr/bin/git checkout kernelci.org
221 07:46:15.020530 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/0/tests/1_kselftest-futex/automated/linux/kselftest/kselftest.yaml
222 07:46:15.023171 uuid=9568079_1.6.2.3.5 testdef=None
223 07:46:15.023758 end: 1.6.2.3.5 git-repo-action (duration 00:00:10) [common]
225 07:46:15.024846 start: 1.6.2.3.6 test-overlay (timeout 00:09:14) [common]
226 07:46:15.027690 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
228 07:46:15.028683 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:14) [common]
229 07:46:15.032415 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
231 07:46:15.033427 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:14) [common]
232 07:46:15.036864 runner path: /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/0/tests/1_kselftest-futex test_uuid 9568079_1.6.2.3.5
233 07:46:15.037140 BOARD='hip07-d05'
234 07:46:15.037387 BRANCH='cip-gitlab'
235 07:46:15.037631 SKIPFILE='skipfile-lkft.yaml'
236 07:46:15.037897 SKIP_INSTALL='True'
237 07:46:15.038147 TESTPROG_URL='None'
238 07:46:15.038417 TST_CASENAME=''
239 07:46:15.038719 TST_CMDFILES='futex'
240 07:46:15.039301 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
242 07:46:15.040000 Creating lava-test-runner.conf files
243 07:46:15.040291 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9568079/lava-overlay-wv0_k1fy/lava-9568079/0 for stage 0
244 07:46:15.040656 - 0_timesync-off
245 07:46:15.040905 - 1_kselftest-futex
246 07:46:15.041302 end: 1.6.2.3 test-definition (duration 00:00:10) [common]
247 07:46:15.041622 start: 1.6.2.4 compress-overlay (timeout 00:09:14) [common]
248 07:46:29.049479 end: 1.6.2.4 compress-overlay (duration 00:00:14) [common]
249 07:46:29.049850 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:00) [common]
250 07:46:29.050101 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
251 07:46:29.050375 end: 1.6.2 lava-overlay (duration 00:00:24) [common]
252 07:46:29.050655 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
253 07:46:29.332474 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
254 07:46:29.333416 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
255 07:46:29.333707 extracting modules file /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a
256 07:46:29.729053 extracting modules file /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9568079/extract-overlay-ramdisk-vw7np0vs/ramdisk
257 07:46:30.137782 end: 1.6.4 extract-modules (duration 00:00:01) [common]
258 07:46:30.138154 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
259 07:46:30.138394 [common] Applying overlay to NFS
260 07:46:30.138642 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9568079/compress-overlay-z9530v29/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a
261 07:46:32.709410 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
262 07:46:32.709793 start: 1.6.6 prepare-kernel (timeout 00:08:57) [common]
263 07:46:32.710037 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
264 07:46:32.710295 start: 1.6.7 configure-preseed-file (timeout 00:08:57) [common]
265 07:46:32.710540 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
266 07:46:32.710803 start: 1.6.8 compress-ramdisk (timeout 00:08:57) [common]
267 07:46:32.711030 Building ramdisk /var/lib/lava/dispatcher/tmp/9568079/extract-overlay-ramdisk-vw7np0vs/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9568079/extract-overlay-ramdisk-vw7np0vs/ramdisk
268 07:46:33.157886 >> 62171 blocks
269 07:46:35.075620 rename /var/lib/lava/dispatcher/tmp/9568079/extract-overlay-ramdisk-vw7np0vs/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/ramdisk/ramdisk.cpio.gz
270 07:46:35.076698 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
271 07:46:35.077017 end: 1.6 prepare-tftp-overlay (duration 00:00:49) [common]
272 07:46:35.077324 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:54) [common]
273 07:46:35.077555 No LXC device requested
274 07:46:35.077828 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
275 07:46:35.078093 start: 1.8 deploy-device-env (timeout 00:08:54) [common]
276 07:46:35.078333 end: 1.8 deploy-device-env (duration 00:00:00) [common]
277 07:46:35.078527 Checking files for TFTP limit of 4294967296 bytes.
278 07:46:35.079965 end: 1 tftp-deploy (duration 00:01:06) [common]
279 07:46:35.080282 start: 2 grub-main-action (timeout 00:05:00) [common]
280 07:46:35.080559 start: 2.1 bootloader-from-media (timeout 00:05:00) [common]
281 07:46:35.080814 end: 2.1 bootloader-from-media (duration 00:00:00) [common]
282 07:46:35.081070 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
283 07:46:35.081430 substitutions:
284 07:46:35.081613 - {DTB}: 9568079/tftp-deploy-6ednswe7/dtb/hip07-d05.dtb
285 07:46:35.081786 - {INITRD}: 9568079/tftp-deploy-6ednswe7/ramdisk/ramdisk.cpio.gz
286 07:46:35.081958 - {KERNEL}: 9568079/tftp-deploy-6ednswe7/kernel/Image
287 07:46:35.082126 - {LAVA_MAC}: None
288 07:46:35.082307 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a
289 07:46:35.082475 - {NFS_SERVER_IP}: 192.168.101.1
290 07:46:35.082675 - {PRESEED_CONFIG}: None
291 07:46:35.082840 - {PRESEED_LOCAL}: None
292 07:46:35.083003 - {RAMDISK}: 9568079/tftp-deploy-6ednswe7/ramdisk/ramdisk.cpio.gz
293 07:46:35.083167 - {ROOT_PART}: None
294 07:46:35.083331 - {ROOT}: None
295 07:46:35.083493 - {SERVER_IP}: 192.168.101.1
296 07:46:35.083656 - {TEE}: None
297 07:46:35.083818 Parsed boot commands:
298 07:46:35.083976 - linux (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/nfs rw nfsroot=192.168.101.1:/var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a,tcp,hard,vers=3 ip=:::::eth0:dhcp
299 07:46:35.084166 - devicetree (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/dtb/hip07-d05.dtb
300 07:46:35.084345 - boot
301 07:46:35.084569 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
302 07:46:35.084832 start: 2.3 connect-device (timeout 00:05:00) [common]
303 07:46:35.085038 [common] connect-device Connecting to device using '/usr/local/bin/d05-console.sh hip07-d05-cbg-0-bmc'
304 07:46:35.091765 Setting prompt string to ['lava-test: # ']
305 07:46:35.092602 end: 2.3 connect-device (duration 00:00:00) [common]
306 07:46:35.092922 start: 2.4 reset-device (timeout 00:05:00) [common]
307 07:46:35.093172 start: 2.4.1 pdu-reboot (timeout 00:05:00) [common]
308 07:46:35.093608 Calling: 'nice' '/usr/local/bin/d05-power.sh' 'hip07-d05-cbg-0-bmc' 'reset'
309 07:46:36.450353 >> Chassis Power Control: Down/Off
310 07:46:46.713054 >> Chassis Power Control: Up/On
311 07:46:56.717560 Returned 0 in 21 seconds
312 07:46:56.820694 end: 2.4.1 pdu-reboot (duration 00:00:22) [common]
314 07:46:56.821987 end: 2.4 reset-device (duration 00:00:22) [common]
315 07:46:56.822537 start: 2.5 bootloader-interrupt (timeout 00:04:38) [common]
316 07:46:56.823313 Setting prompt string to ['PCIE MEM CONFIG']
317 07:46:56.823722 bootloader-interrupt: Wait for prompt ['PCIE MEM CONFIG'] (timeout 00:05:00)
318 07:46:56.824940 Info: SOL payload already de-activated
319 07:46:56.825360 Never mind
320 07:46:56.825726 [SOL Session operational. Use ~? for help]
321 07:46:56.826107 [serdes_init]:SerDes0 init success!
322 07:46:56.826447 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 5G
323 07:46:58.530752 [serdes_cs_hw_calibration_optionV2_exec]:Macro1 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms
324 07:46:58.531135 [SerdesCsCalib]:Macro1 CS1 PLL lock success!(0 ms)
325 07:47:00.850263 [serdes_init]:SerDes1 init success!
326 07:47:00.932006 Continue to dreset PCS
327 07:47:00.932467 Continue to dreset HLLC
328 07:47:01.920539 Continue to open PCS RX
329 07:47:01.994655 Wait for HLLC Training........OK
330 07:47:01.994951 Wait for HLLC1 Training........OK
331 07:47:01.995139 Wait for S1 HLLC Training........OK
332 07:47:01.995318 Wait for S1 HLLC1 Training........OK
333 07:47:01.995495 Open Secondary socket Window
334 07:47:01.995673 Djtag secondary 0x4004001d818 and 0x400d000d818 init
335 07:47:02.931217 Macro 0 Download Firmware Success!!
336 07:47:03.930361 Macro 1 Download Firmware Success!!
337 07:47:04.841808 Macro 0 Download Firmware Success!!
338 07:47:05.796857 Macro 1 Download Firmware Success!!
339 07:47:05.797204 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit
340 07:47:05.797406 Halt Macro 0 MCU!!
341 07:47:05.797591 Release Macro 0 MCU!!
342 07:47:05.870640 Temperature: 27 (0x1B)
343 07:47:05.960389 [serdes_init]:SerDes0 init success!
344 07:47:05.960806 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit
345 07:47:05.961082 Halt Macro 1 MCU!!
346 07:47:05.961391 Release Macro 1 MCU!!
347 07:47:06.060159 Temperature: 27 (0x1B)
348 07:47:06.110397 [serdes_init]:SerDes1 init success!
349 07:47:06.140293 [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit
350 07:47:06.330830 Halt Macro 0 MCU!!
351 07:47:06.572345 Release Macro 0 MCU!!
352 07:47:08.242945 Temperature: 27 (0x1B)
353 07:47:08.951692 [serdes_init]:SerDes0 init success!
354 07:47:08.952410 [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit
355 07:47:09.160703 Halt Macro 1 MCU!!
356 07:47:09.390777 Release Macro 1 MCU!!
357 07:47:11.040171 Temperature: 27 (0x1B)
358 07:47:11.735286 [serdes_init]:SerDes1 init success!
359 07:47:11.821546 Continue to dreset PCS
360 07:47:11.822033 Continue to dreset HLLC
361 07:47:11.822535 Continue to Enable CTLE
362 07:47:13.040450 Continue to open PCS RX
363 07:47:13.071440 Wait for HLLC Training........OK
364 07:47:13.071809 Wait for HLLC1 Training........OK
365 07:47:13.072226 Wait for S1 HLLC Training........OK
366 07:47:13.072623 Wait for S1 HLLC1 Training........OK
367 07:47:13.092751 S0 HLLC0 Interrupt status(0x4) = 0x0
368 07:47:13.093322 S0 HLLC1 Interrupt status(0x4) = 0x0
369 07:47:13.093711 S1 HLLC0 Interrupt status(0x4) = 0x0
370 07:47:13.094072 S1 HLLC1 Interrupt status(0x4) = 0x0
371 07:47:13.094379
372 07:47:13.094785 Config Secondary socket
373 07:47:13.095089 Open Secondary socket Window
374 07:47:13.095401 close NB CS2 to PA
375 07:47:13.131212 Config socket0 NA PA
376 07:47:13.131673 Enable socket0 PA 2+2 Mode
377 07:47:13.132073 Config Secondary socket PA
378 07:47:13.132510 clean S0 remap for PA....Done
379 07:47:13.132895 clean remap for PA....Done
380 07:47:13.133270 Enable socket1 PA 2+2 Mode
381 07:47:13.133637 Djtag Secondary 0x4006001d818 Init
382 07:47:13.134028 S1 Preinit
383 07:47:13.134394 S1 Preinit End
384 07:47:13.134842 Config Secondary socket AA&LLC
385 07:47:13.205744 close S1 NB CS2 to PA
386 07:47:13.206141 OK1OK2OK3Djtag Secondary 0x408d000d818 Init
387 07:47:13.206581 Visit S1 NB
388 07:47:13.206959 Visit S1 NB DONE
389 07:47:13.207305 S1 NA PCIE clean remap.........Done
390 07:47:13.207731 S1 NA PCIE MEM CONFIG.........Done
391 07:47:13.208139 S1 NB PCIE clean remap.........Done
392 07:47:13.259420 end: 2.5 bootloader-interrupt (duration 00:00:16) [common]
393 07:47:13.259746 start: 2.6 bootloader-commands (timeout 00:04:22) [common]
394 07:47:13.260036 Setting prompt string to ['grub>']
395 07:47:13.260334 bootloader-commands: Wait for prompt ['grub>'] (timeout 00:04:22)
396 07:47:13.260888 S1 NB PCIE MEM CcONFIG.........Done
397 07:47:13.261090 NB/TB PLL Init
398 07:47:13.261346 TB PLL init....OK
399 07:47:13.261604 NB PLL init....OK
400 07:47:13.261817 [LPC] S1 MBIGEN CONFIG Done
401 07:47:13.262033 add-symbol-file /home/s00296804/Edk2/Build/D05Source/RELEASE_GCC49/AARCH64/HwPkg/Override/ArmPlatformPkg/Sec/Sec/DEBUG/ArmPlatformSec.dll 0xA4801800
402 07:47:13.262255 Trust Zone Configuration is disabled
403 07:47:13.262520
404 07:47:14.580962
405 07:47:14.581589 Boot firmware (version Hisilicon D05 UEFI 16.12 Release built at 05/15/2017 07:53)
406 07:47:14.582028
407 07:47:14.582451 init BMC.
408 07:47:14.582994 TempVer:0x20
409 07:47:14.583410 GetDeviceId return Success
410 07:47:14.612629 GetVariable Not Found!
411 07:47:14.613132 Get Default Setup Configration
412 07:47:14.613567 &&&Now config iBMC BIOS WDT [action:0 countdown:3928 timeruse 2!
413 07:47:14.672100 Memory Init PEIM Loaded
414 07:47:14.672555 GetVariable Not Found!
415 07:47:14.672908 Get Default Setup Configration
416 07:47:14.673242 -------------------
417 07:47:14.673654 Start RegisterTest:
418 07:47:14.673979 RegisterTest OK!
419 07:47:14.690479 -------------------
420 07:47:14.691077 socket[0] Totem B I2C0 init ok.
421 07:47:14.691474 socket[0] Totem B I2C1 init ok.
422 07:47:14.691957 socket[1] Totem B I2C0 init ok.
423 07:47:14.692392 socket[1] Totem B I2C1 init ok.
424 07:47:14.692778
425 07:47:14.693145 socket[0] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54
426 07:47:14.700571 ---------------------------------------------------------------------
427 07:47:14.701165 SPD_KEY_BYTE : DDR4
428 07:47:14.701577 SPD_KEY_BYTE2 : RDIMM
429 07:47:14.701962 SPD_MODULE_ORG_DDR4 : 0x8
430 07:47:14.702380 SPD_MIN_TCK_DDR4 : 0x7
431 07:47:14.715875 SPD_MAX_TCK_DDR4 : 0xD
432 07:47:14.716288 SPD_FTB_MIN_TCK_DDR4 : 0xD6
433 07:47:14.716494 DimmMaxFreq : 2401Mbps
434 07:47:14.716689 pGblData->Channel[0][0].Dimm[0].DramWidth : X4
435 07:47:14.734024 pGblData->Channel[0][0].Dimm[0].RankNum : 2
436 07:47:14.734428 pGblData->Channel[0][0].Dimm[0].ddrFreq : 2400Mbps
437 07:47:14.734657 pGblData->Channel[0][0].Dimm[0].minTck : 8330
438 07:47:14.734870 ---------------------------------------------------------------------
439 07:47:14.735062
440 07:47:14.788915 socket[0] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55
441 07:47:14.789307 ---------------------------------------------------------------------
442 07:47:14.802709 SPD_KEY_BYTE : Empty
443 07:47:14.803122 Socket[0] Channel[0] Dimm[1] is empty.
444 07:47:14.803490 ---------------------------------------------------------------------
445 07:47:14.803815 pGblData->Channel[0][0].RankPresent : 0x3
446 07:47:14.804078
447 07:47:14.804360
448 07:47:14.820700 socket[0] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54
449 07:47:14.821105 ---------------------------------------------------------------------
450 07:47:14.821415 SPD_KEY_BYTE : DDR4
451 07:47:14.821762 SPD_KEY_BYTE2 : RDIMM
452 07:47:14.835879 SPD_MODULE_ORG_DDR4 : 0x8
453 07:47:14.836466 SPD_MIN_TCK_DDR4 : 0x7
454 07:47:14.837281 SPD_MAX_TCK_DDR4 : 0xD
455 07:47:14.837730 SPD_FTB_MIN_TCK_DDR4 : 0xD6
456 07:47:14.838122 DimmMaxFreq : 2401Mbps
457 07:47:14.857409 pGblData->Channel[0][1].Dimm[0].DramWidth : X4
458 07:47:14.857767 pGblData->Channel[0][1].Dimm[0].RankNum : 2
459 07:47:14.858134 pGblData->Channel[0][1].Dimm[0].ddrFreq : 2400Mbps
460 07:47:14.858475 pGblData->Channel[0][1].Dimm[0].minTck : 8330
461 07:47:14.880346 ---------------------------------------------------------------------
462 07:47:14.880705
463 07:47:14.881034 socket[0] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55
464 07:47:14.881744 ---------------------------------------------------------------------
465 07:47:14.918388 SPD_KEY_BYTE : Empty
466 07:47:14.918879 Socket[0] Channel[1] Dimm[1] is empty.
467 07:47:14.919620 ---------------------------------------------------------------------
468 07:47:14.919997 pGblData->Channel[0][1].RankPresent : 0x3
469 07:47:14.920436
470 07:47:14.920833
471 07:47:14.942509 socket[0] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50
472 07:47:14.943041 ---------------------------------------------------------------------
473 07:47:14.943446 SPD_KEY_BYTE : DDR4
474 07:47:14.943833 SPD_KEY_BYTE2 : RDIMM
475 07:47:14.974089 SPD_MODULE_ORG_DDR4 : 0x8
476 07:47:14.974617 SPD_MIN_TCK_DDR4 : 0x7
477 07:47:14.975183 SPD_MAX_TCK_DDR4 : 0xD
478 07:47:14.975668 SPD_FTB_MIN_TCK_DDR4 : 0xD6
479 07:47:14.976055 DimmMaxFreq : 2401Mbps
480 07:47:14.990641 pGblData->Channel[0][2].Dimm[0].DramWidth : X4
481 07:47:14.991112 pGblData->Channel[0][2].Dimm[0].RankNum : 2
482 07:47:14.991540 pGblData->Channel[0][2].Dimm[0].ddrFreq : 2400Mbps
483 07:47:14.991959 pGblData->Channel[0][2].Dimm[0].minTck : 8330
484 07:47:15.030450 ---------------------------------------------------------------------
485 07:47:15.031076
486 07:47:15.031521 socket[0] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51
487 07:47:15.032007 ---------------------------------------------------------------------
488 07:47:15.044733 SPD_KEY_BYTE : Empty
489 07:47:15.045062 Socket[0] Channel[2] Dimm[1] is empty.
490 07:47:15.045379 ---------------------------------------------------------------------
491 07:47:15.045767 pGblData->Channel[0][2].RankPresent : 0x3
492 07:47:15.046013
493 07:47:15.046254
494 07:47:15.074522 socket[0] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50
495 07:47:15.075047 ---------------------------------------------------------------------
496 07:47:15.075463 SPD_KEY_BYTE : DDR4
497 07:47:15.075860 SPD_KEY_BYTE2 : RDIMM
498 07:47:15.098136 SPD_MODULE_ORG_DDR4 : 0x8
499 07:47:15.098657 SPD_MIN_TCK_DDR4 : 0x7
500 07:47:15.099027 SPD_MAX_TCK_DDR4 : 0xD
501 07:47:15.099362 SPD_FTB_MIN_TCK_DDR4 : 0xD6
502 07:47:15.100094 DimmMaxFreq : 2401Mbps
503 07:47:15.117274 pGblData->Channel[0][3].Dimm[0].DramWidth : X4
504 07:47:15.117714 pGblData->Channel[0][3].Dimm[0].RankNum : 2
505 07:47:15.130785 pGblData->Channel[0][3].Dimm[0].ddrFreq : 2400Mbps
506 07:47:15.131249 pGblData->Channel[0][3].Dimm[0].minTck : 8330
507 07:47:15.131650 ---------------------------------------------------------------------
508 07:47:15.132043
509 07:47:15.132459 socket[0] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51
510 07:47:15.159681 ---------------------------------------------------------------------
511 07:47:15.160190 SPD_KEY_BYTE : Empty
512 07:47:15.160704 Socket[0] Channel[3] Dimm[1] is empty.
513 07:47:15.181532 ---------------------------------------------------------------------
514 07:47:15.182085 pGblData->Channel[0][3].RankPresent : 0x3
515 07:47:15.182604
516 07:47:15.183056
517 07:47:15.183456 socket[1] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54
518 07:47:15.183906 ---------------------------------------------------------------------
519 07:47:15.205385 SPD_KEY_BYTE : DDR4
520 07:47:15.205718 SPD_KEY_BYTE2 : RDIMM
521 07:47:15.205989 SPD_MODULE_ORG_DDR4 : 0x8
522 07:47:15.206281 SPD_MIN_TCK_DDR4 : 0x7
523 07:47:15.206573 SPD_MAX_TCK_DDR4 : 0xD
524 07:47:15.250146 SPD_F0].Dimm[0].DramWidth : X4
525 07:47:15.250475 pGblData->Channel[1][0].Dimm[0].RankNum : 2
526 07:47:15.250769 pGblData->Channel[1][0].Dimm[0].ddrFreq : 2400Mbps
527 07:47:15.251036 pGblData->Channel[1][0].Dimm[0].minTck : 8330
528 07:47:15.274725 ---------------------------------------------------------------------
529 07:47:15.274991
530 07:47:15.275213 socket[1] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55
531 07:47:15.275438 ---------------------------------------------------------------------
532 07:47:15.296571 SPD_KEY_BYTE : Empty
533 07:47:15.296898 Socket[1] Channel[0] Dimm[1] is empty.
534 07:47:15.297144 ---------------------------------------------------------------------
535 07:47:15.297387 pGblData->Channel[1][0].RankPresent : 0x3
536 07:47:15.297639
537 07:47:15.297888
538 07:47:15.318496 socket[1] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54
539 07:47:15.318778 ---------------------------------------------------------------------
540 07:47:15.319016 SPD_KEY_BYTE : DDR4
541 07:47:15.319247 SPD_KEY_BYTE2 : RDIMM
542 07:47:15.341059 SPD_MODULE_ORG_DDR4 : 0x8
543 07:47:15.341338 SPD_MIN_TCK_DDR4 : 0x7
544 07:47:15.341565 SPD_MAX_TCK_DDR4 : 0xD
545 07:47:15.341810 SPD_FTB_MIN_TCK_DDR4 : 0xD6
546 07:47:15.342050 DimmMaxFreq : 2401Mbps
547 07:47:15.362256 pGblData->Channel[1][1].Dimm[0].DramWidth : X4
548 07:47:15.362519 pGblData->Channel[1][1].Dimm[0].RankNum : 2
549 07:47:15.362775 pGblData->Channel[1][1].Dimm[0].ddrFreq : 2400Mbps
550 07:47:15.363006 pGblData->Channel[1][1].Dimm[0].minTck : 8330
551 07:47:15.390461 ---------------------------------------------------------------------
552 07:47:15.390834
553 07:47:15.391127 socket[1] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55
554 07:47:15.391419 ---------------------------------------------------------------------
555 07:47:15.422922 SPD_KEY_BYTE : Empty
556 07:47:15.423238 Socket[1] Channel[1] Dimm[1] is empty.
557 07:47:15.423501 ---------------------------------------------------------------------
558 07:47:15.423762 pGblData->Channel[1][1].RankPresent : 0x3
559 07:47:15.424012
560 07:47:15.424298
561 07:47:15.489592 socket[1] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50
562 07:47:15.489882 ---------------------------------------------------------------------
563 07:47:15.500569 SPD_KEY_BYTE : DDR4
564 07:47:15.500829 SPD_KEY_BYTE2 : RDIMM
565 07:47:15.501066 SPD_MODULE_ORG_DDR4 : 0x8
566 07:47:15.501310 SPD_MIN_TCK_DDR4 : 0x7
567 07:47:15.501548 SPD_MAX_TCK_DDR4 : 0xD
568 07:47:15.520347 SPD_FTB_MIN_TCK_DDR4 : 0xD6
569 07:47:15.520636 DimmMaxFreq : 2401Mbps
570 07:47:15.520893 pGblData->Channel[1][2].Dimm[0].DramWidth : X4
571 07:47:15.521159 pGblData->Channel[1][2].Dimm[0].RankNum : 2
572 07:47:15.530715 pGblData->Channel[1][2].Dimm[0].ddrFreq : 2400Mbps
573 07:47:15.530968 pGblData->Channel[1][2].Dimm[0].minTck : 8330
574 07:47:15.531203 ---------------------------------------------------------------------
575 07:47:15.531450
576 07:47:15.531661 socket[1] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51
577 07:47:15.551152 ---------------------------------------------------------------------
578 07:47:15.551437 SPD_KEY_BYTE : Empty
579 07:47:15.551681 Socket[1] Channel[2] Dimm[1] is empty.
580 07:47:15.570323 ---------------------------------------------------------------------
581 07:47:15.570657 pGblData->Channel[1][2].RankPresent : 0x3
582 07:47:15.570922
583 07:47:15.571176
584 07:47:15.571425 socket[1] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50
585 07:47:15.571678 ---------------------------------------------------------------------
586 07:47:15.594761 SPD_KEY_BYTE : DDR4
587 07:47:15.595035 SPD_KEY_BYTE2 : RDIMM
588 07:47:15.595277 SPD_MODULE_ORG_DDR4 : 0x8
589 07:47:15.595509 SPD_MIN_TCK_DDR4 : 0x7
590 07:47:15.595739 SPD_MAX_TCK_DDR4 : 0xD
591 07:47:15.669089 SPD_FTB_MIN_TCK_DDR4 : 0xD6
592 07:47:15.669892 DimmMaxFreq : 2401Mbps
593 07:47:15.670256 pGblData->Channel[1][3].Dimm[0].DramWidth : X4
594 07:47:15.670611 pGblData->Channel[1][3].Dimm[0].RankNum : 2
595 07:47:15.680523 pGblData->Channel[1][3].Dimm[0].ddrFreq : 2400Mbps
596 07:47:15.680903 pGblData->Channel[1][3].Dimm[0].minTck : 8330
597 07:47:15.697347 ---------------------------------------------------------------------
598 07:47:15.697693
599 07:47:15.697934 socket[1] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51
600 07:47:15.698181 ---------------------------------------------------------------------
601 07:47:15.698535 SPD_KEY_BYTE : Empty
602 07:47:15.698840 Socket[1] Channel[3] Dimm[1] is empty.
603 07:47:15.713277 ---------------------------------------------------------------------
604 07:47:15.713614 pGblData->Channel[1][3].RankPresent : 0x3
605 07:47:15.713925
606 07:47:15.734751 DimmMaxFreq : 2401Mbps
607 07:47:15.735082 GblData->Freq : 2400
608 07:47:15.735317 GblData->Tck : 8333
609 07:47:15.735546 GblData->DdrFreqIdx : 13
610 07:47:15.735753 Check dimm status ok!
611 07:47:15.735965 pGblData->MaxSPCNum = 2
612 07:47:15.736181 skt[0] ch[0] maxPORFreqIdx = 13
613 07:47:15.736715 skt[0] ch[1] maxPORFreqIdx = 13
614 07:47:15.740389 skt[0] ch[2] maxPORFreqIdx = 13
615 07:47:15.740617 skt[0] ch[3] maxPORFreqIdx = 13
616 07:47:15.740834 skt[1] ch[0] maxPORFreqIdx = 13
617 07:47:15.741034 skt[1] ch[1] maxPORFreqIdx = 13
618 07:47:15.741218 skt[1] ch[2] maxPORFreqIdx = 13
619 07:47:15.741401 skt[1] ch[3] maxPORFreqIdx = 13
620 07:47:15.741599 ---------------------------------------------------------------------
621 07:47:15.751242 ---------------------------------------------------------------------
622 07:47:15.751470 PORFreqTable result(max system ddr frequency):
623 07:47:15.751671 pGblData->DdrFreqIdx = 13
624 07:47:15.751882 pGblData->DevParaFreqIdx = 13
625 07:47:15.752078 pGblData->Tck = 8333
626 07:47:15.752300 pGblData->Freq = 2400
627 07:47:15.770363 ---------------------------------------------------------------------
628 07:47:15.770658 ---------------------------------------------------------------------
629 07:47:15.770893 Set ddr frequency ok!
630 07:47:15.771103 Get dimm spd information
631 07:47:15.771332
632 07:47:15.838652 socket[0] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information:
633 07:47:16.476776 SPD_MIN_TRCD_DDR4: 0x6E
634 07:47:16.477235 SPD_FTB_TRCD_DDR4: 0x0
635 07:47:16.477497 SPD_MIN_TRRDL_DDR4: 0x28
636 07:47:16.477758 SPD_FTB_TRRDL_DDR4: 0x9C
637 07:47:16.477999 SPD_MIN_TRRDS_DDR4: 0x1B
638 07:47:16.478281 SPD_FTB_TRRDS_DDR4: 0xB5
639 07:47:16.478607 SPD_EXT_TRC_TRAS_DDR4: 0x11
640 07:47:16.478964 SPD_MIN_TRAS_DDR4: 0x0
641 07:47:16.479253 SPD_MIN_TRC_DDR4: 0x6E
642 07:47:16.498433 SPD_FTB_TRC_DDR4: 0x0
643 07:47:16.498831 SPD_MIN_TRFC1_MSB_DDR4: 0xA
644 07:47:16.499119 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
645 07:47:16.499486 tRFC: 0xAF0
646 07:47:16.499971 tempCkNum: 0x55730
647 07:47:16.500345 SPD_MIN_TAA_DDR4: 0x6E
648 07:47:16.500624 SPD_FTB_TAA: 0x0
649 07:47:16.500915 SPD_TFAW_UPPER_DDR4: 0x0
650 07:47:16.501179 SPD_MIN_TFAW_DDR4: 0x68
651 07:47:16.501440 SPD_MIN_TRP_DDR4: 0x6E
652 07:47:16.501699 SPD_FTB_TRP_DDR4: 0x0
653 07:47:16.521970 SPD_MIN_TCCDL_DDR4: 0x28
654 07:47:16.522312 SPD_FTB_TCCDL_DDR4: 0x0
655 07:47:16.522592 ---------------------------------------------------------------------
656 07:47:16.522890 pGblData item skt ch dimm value
657 07:47:16.523135 ---------------------------------------------------------------------
658 07:47:16.542049 SDRAMCapacity 0 0 0 0x5
659 07:47:16.542429 BGNum 0 0 0 4
660 07:47:16.542846 BankNum 0 0 0 16
661 07:47:16.543196 ColBits 0 0 0 10
662 07:47:16.543487 RowBits 0 0 0 17
663 07:47:16.563789 SpdMirror 0 0 0 1
664 07:47:16.564064 SpdVdd 0 0 0 3
665 07:47:16.564330 PrimaryBusWidth 0 0 0 64
666 07:47:16.564572 ExtensionBusWidth 0 0 0 8
667 07:47:16.613092 RankSize 0 0 0 163 SpdMMDate 0 0 0 0x2817
668 07:47:16.613388 SpdSerialNum 0 0 0 0x4F82936
669 07:47:16.613647 SpdMinTRCD 0 0 0 0x6E
670 07:47:16.613891 SpdMinTRCDFtb 0 0 0 0x0
671 07:47:16.631485 nRCD 0 0 0 0x35B6
672 07:47:16.631735 SpdMinTRRDL 0 0 0 0x28
673 07:47:16.632000 SpdMinTRRD 0 0 0 0x1B
674 07:47:16.632274 SpdMinTRAS 0 0 0 0x100
675 07:47:16.632563 SpdMinTRC 0 0 0 0x16E
676 07:47:16.651251 SpdMinTRCFtb 0 0 0 0x0
677 07:47:16.651533 SpdMinTRFC 0 0 0 0xAF0
678 07:47:16.651750 SpdMinTAA 0 0 0 0x6E
679 07:47:16.651985 SpdMinTAAFtb 0 0 0 0x0
680 07:47:16.850666 SpdMinTFAW 0 0 nRP 0 0 0 0x35B6
681 07:47:16.851147 SpdMinTCCDL 0 0 0 0x28
682 07:47:16.851473 SpdMinTCCDLFtb 0 0 0 0x0
683 07:47:16.851806 SpdModuleAttr 0 0 0 0x0
684 07:47:16.905036 SpdAddrMap 0 0 0 0x1
685 07:47:16.905431 ---------------------------------------------------------------------
686 07:47:16.905754
687 07:47:16.922964 socket[0] channel[0] SPD information:
688 07:47:16.923268 ---------------------------------------------------------------------
689 07:47:16.923521 item skt ch value
690 07:47:16.923837 ---------------------------------------------------------------------
691 07:47:16.924081 nWR 0 0 0ps
692 07:47:16.940580 nRCD 0 0 13750ps
693 07:47:16.940915 nRRDL 0 0 4900ps
694 07:47:16.941227 nRRD 0 0 3300ps
695 07:47:16.941508 nRAS 0 0 32000ps
696 07:47:16.941784 nRC 0 0 45750ps
697 07:47:16.942055 nRFC 0 0 350000ps
698 07:47:16.942346 nWTR 0 0 0ps
699 07:47:16.960358 nRTP 0 0 0ps
700 07:47:16.960639 nAA 0 0 13750ps
701 07:47:16.960915 nFAW 0 0 13000ps
702 07:47:16.961156 nRP 0 0 13750ps
703 07:47:16.961390 nCCDL 0 0 5000ps
704 07:47:16.961650 ---------------------------------------------------------------------
705 07:47:16.961923
706 07:47:16.991630 socket[0] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information:
707 07:47:17.467925 SPD_MIN_TRCD_DDR4: 0x6E
708 07:47:17.468492 SPD_FTB_TRCD_DDR4: 0x0
709 07:47:17.468879 SPD_MIN_TRRDL_DDR4: 0x28
710 07:47:17.469216 SPD_FTB_TRRDL_DDR4: 0x9C
711 07:47:17.469511 SPD_MIN_TRRDS_DDR4: 0x1B
712 07:47:17.469810 SPD_FTB_TRRDS_DDR4: 0xB5
713 07:47:17.470182 SPD_EXT_TRC_TRAS_DDR4: 0x11
714 07:47:17.470576 SPD_MIN_TRAS_DDR4: 0x0
715 07:47:17.470946 SPD_MIN_TRC_DDR4: 0x6E
716 07:47:17.489197 SPD_FTB_TRC_DDR4: 0x0
717 07:47:17.489430 SPD_MIN_TRFC1_MSB_DDR4: 0xA
718 07:47:17.489632 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
719 07:47:17.489824 tRFC: 0xAF0
720 07:47:17.490030 tempCkNum: 0x55730
721 07:47:17.490229 SPD_MIN_TAA_DDR4: 0x6E
722 07:47:17.490457 SPD_FTB_TAA: 0x0
723 07:47:17.490708 SPD_TFAW_UPPER_DDR4: 0x0
724 07:47:17.490948 SPD_MIN_TFAW_DDR4: 0x68
725 07:47:17.491166 SPD_MIN_TRP_DDR4: 0x6E
726 07:47:17.491382 SPD_FTB_TRP_DDR4: 0x0
727 07:47:17.511273 SPD_MIN_TCCDL_DDR4: 0x28
728 07:47:17.511556 SPD_FTB_TCCDL_DDR4: 0x0
729 07:47:17.511826 ---------------------------------------------------------------------
730 07:47:17.512109 pGblData item skt ch dimm value
731 07:47:17.512356 ---------------------------------------------------------------------
732 07:47:17.532883 SDRAMCapacity 0 1 0 0x5
733 07:47:17.533180 BGNum 0 1 0 4
734 07:47:17.533419 BankNum 0 1 0 16
735 07:47:17.533686 ColBits 0 1 0 10
736 07:47:17.533980 RowBits 0 1 0 17
737 07:47:17.554736 SpdMirror 0 1 0 1
738 07:47:17.555003 SpdVdd 0 1 0 3
739 07:47:17.555259 PrimaryBusWidth 0 1 0 64
740 07:47:17.555489 ExtensionBusWidth 0 1 0 8
741 07:47:17.576723 RankSize 0 1 0 16384
742 07:47:17.577088 SpdRMId 0 1 0 0x3206
743 07:47:17.577436 SpdMMfgId 0 1 0 0xCE00
744 07:47:17.577861 SpdMMDate 0 1 0 0x2817
745 07:47:17.578153 SpdSerialNum 0 1 0 0xE3F82936
746 07:47:17.598537 SpdMinTRCD 0 1 0 0x6E
747 07:47:17.598886 SpdMinTRCDFtb 0 1 0 0x0
748 07:47:17.599176 nRCD 0 1 0 0x35B6
749 07:47:17.599443 SpdMinTRRDL 0 1 0 0x28
750 07:47:17.620703 SpdMinTRRD 0 1 0 0x1B
751 07:47:17.620969 SpdMinTRAS 0 1 0 0x100
752 07:47:17.621235 SpdMinTRC 0 1 0 0x16E
753 07:47:17.621486 SpdMinTRCFtb 0 1 0 0x0
754 07:47:17.621707 SpdMinTRFC 0 1 0 0xAF0
755 07:47:17.645855 SpdMinTAA 0 1 0 0x6E
756 07:47:17.646149 SpdMinTAAFtb 0 1 0 0x0
757 07:47:17.646410 SpdMinTFAW 0 1 0 0x68
758 07:47:17.646693 SpdMinTRP 0 1 0 0x6E
759 07:47:17.646932 SpdMinTRPFtb 0 1 0 0x0
760 07:47:17.664366 nRP 0 1 0 0x35B6
761 07:47:17.664788 SpdMinTCCDL 0 1 0 0x28
762 07:47:17.665115 SpdMinTCCDLFtb 0 1 0 0x0
763 07:47:17.665402 SpdModuleAttr 0 1 0 0x0
764 07:47:17.686206 SpdAddrMap 0 1 0 0x1
765 07:47:17.686599 ---------------------------------------------------------------------
766 07:47:17.686973
767 07:47:17.687348 socket[0] channel[1] SPD information:
768 07:47:17.687786 ---------------------------------------------------------------------
769 07:47:17.688257 item skt ch value
770 07:47:17.714491 ---------------------------------------------------------------------
771 07:47:17.714954 nWR 0 1 0ps
772 07:47:17.715297 nRCD 0 1 13750ps
773 07:47:17.715679 nRRDL 0 1 4900ps
774 07:47:17.716024 nRRD 0 1 3300ps
775 07:47:17.716403 nRAS 0 1 32000ps
776 07:47:17.730763 nRC 0 1 45750ps
777 07:47:17.731036 nRFC 0 1 350000ps
778 07:47:17.731312 nWTR 0 1 0ps
779 07:47:17.731561 nRTP 0 1 0ps
780 07:47:17.731803 nAA 0 1 13750ps
781 07:47:17.732040 nFAW 0 1 13000ps
782 07:47:17.762824 nRP 0 1 13750ps
783 07:47:17.763088 nCCDL 0 1 5000ps
784 07:47:17.763354 ---------------------------------------------------------------------
785 07:47:17.763582
786 07:47:17.763793 socket[0] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information:
787 07:47:18.461484 SPD_MIN_TRCD_DDR4: 0x6E
788 07:47:18.461842 SPD_FTB_TRCD_DDR4: 0x0
789 07:47:18.462067 SPD_MIN_TRRDL_DDR4: 0x28
790 07:47:18.462282 SPD_FTB_TRRDL_DDR4: 0x9C
791 07:47:18.462521 SPD_MIN_TRRDS_DDR4: 0x1B
792 07:47:18.462829 SPD_FTB_TRRDS_DDR4: 0xB5
793 07:47:18.463096 SPD_EXT_TRC_TRAS_DDR4: 0x11
794 07:47:18.463399 SPD_MIN_TRAS_DDR4: 0x0
795 07:47:18.463670 SPD_MIN_TRC_DDR4: 0x6E
796 07:47:18.511238 SPD_FTB_TRC_DDR4: 0x0
797 07:47:18.511562 SPD_MIN_TRFC1_MSB_DDR4: 0xA
798 07:47:18.511857 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
799 07:47:18.512164 tRFC: 0xAF0
800 07:47:18.512429 tempCkNum: 0x55730
801 07:47:18.512663 SPD_MIN_TAA_DDR4: 0x6E
802 07:47:18.530581 SPD_FTB_TAA: 0x0
803 07:47:18.530871 SPD_TFAW_UPPER_DDR4: 0x0
804 07:47:18.531131 SPD_MIN_TFAW_DDR4: 0x68
805 07:47:18.531356 SPD_MIN_TRP_DDR4: 0x6E
806 07:47:18.531588 SPD_FTB_TRP_DDR4: 0x0
807 07:47:18.531817 SPD_MIN_TCCDL_DDR4: 0x28
808 07:47:18.532034 SPD_FTB_TCCDL_DDR4: 0x0
809 07:47:18.532253 ---------------------------------------------------------------------
810 07:47:18.540722 pGblData item skt ch dimm value
811 07:47:18.540996 ---------------------------------------------------------------------
812 07:47:18.541272 SDRAMCapacity 0 2 0 0x5
813 07:47:18.541583 BGNum 0 2 0 4
814 07:47:18.552488 BankNum 0 2 0 16
815 07:47:18.552824 ColBits 0 2 0 10
816 07:47:18.553077 RowBits 0 2 0 17
817 07:47:18.553307 SpdMirror 0 2 0 1
818 07:47:18.553533 SpdVdd 0 2 0 3
819 07:47:18.570442 PrimaryBusWidth 0 2 0 64
820 07:47:18.570805 ExtensionBusWidth 0 2 0 8
821 07:47:18.571068 RankSize 0 2 0 16384
822 07:47:18.571341 SpdRMId 0 2 0 0x3206
823 07:47:18.571609 SpdMMfgId 0 2 0 0xCE00
824 07:47:18.581197 SpdMMDate 0 2 0 0x2817
825 07:47:18.581439 SpdSerialNum 0 2 0 0xDFF32936
826 07:47:18.581648 SpdMinTRCD 0 2 0 0x6E
827 07:47:18.581858 SpdMinTRCDFtb 0 2 0 0x0
828 07:47:18.602582 nRCD 0 2 0 0x35B6
829 07:47:18.602922 SpdMinTRRDL 0 2 0 0x28
830 07:47:18.603208 SpdMinTRRD 0 2 0 0x1B
831 07:47:18.603497 SpdMinTRAS 0 2 0 0x100
832 07:47:18.603825 SpdMinTRC 0 2 0 0x16E
833 07:47:18.625615 SpdMinTRCFtb 0 2 0 0x0
834 07:47:18.625965 SpdMinTRFC 0 2 0 0xAF0
835 07:47:18.626274 SpdMinTAA 0 2 0 0x6E
836 07:47:18.626595 SpdMinTAAFtb 0 2 0 0x0
837 07:47:18.644318 SpdMinTFAW 0 2 0 0x68
838 07:47:18.644665 SpdMinTRP 0 2 0 0x6E
839 07:47:18.644968 SpdMinTRPFtb 0 2 0 0x0
840 07:47:18.645237 nRP 0 2 0 0x35B6
841 07:47:18.645500 SpdMinTCCDL 0 2 0 0x28
842 07:47:18.706320 SpdMinTCCDLFtb 0 2 0 0x0
843 07:47:18.706696 SpdModuleAttr 0 2 0 0x0
844 07:47:18.706990 SpdAddrMap 0 2 0 0x1
845 07:47:18.707299 ---------------------------------------------------------------------
846 07:47:18.707628
847 07:47:18.722346 socket[0] channel[2] SPD information:
848 07:47:18.722674 ---------------------------------------------------------------------
849 07:47:18.722985 item skt ch value
850 07:47:18.723273 ---------------------------------------------------------------------
851 07:47:18.723511 nWR 0 2 0ps
852 07:47:18.740289 nRCD 0 2 13750ps
853 07:47:18.740572 nRRDL 0 2 4900ps
854 07:47:18.740849 nRRD 0 2 3300ps
855 07:47:18.741100 nRAS 0 2 32000ps
856 07:47:18.741366 nRC 0 2 45750ps
857 07:47:18.741615 nRFC 0 2 350000ps
858 07:47:18.742243 nWTR 0 2 0ps
859 07:47:18.751330 nRTP 0 2 0ps
860 07:47:18.751564 nAA 0 2 13750ps
861 07:47:18.751776 nFAW 0 2 13000ps
862 07:47:18.751966 nRP 0 2 13750ps
863 07:47:18.752175 nCCDL 0 2 5000ps
864 07:47:18.752387 ---------------------------------------------------------------------
865 07:47:18.752583
866 07:47:18.780835 socket[0] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information:
867 07:47:19.449400 SPD_MIN_TRCD_DDR4: 0x6E
868 07:47:19.449845 SPD_FTB_TRCD_DDR4: 0x0
869 07:47:19.450180 SPD_MIN_TRRDL_DDR4: 0x28
870 07:47:19.450498 SPD_FTB_TRRDL_DDR4: 0x9C
871 07:47:19.450922 SPD_MIN_TRRDS_DDR4: 0x1B
872 07:47:19.451341 SPD_FTB_TRRDS_DDR4: 0xB5
873 07:47:19.451753 SPD_EXT_TRC_TRAS_DDR4: 0x11
874 07:47:19.452162 SPD_MIN_TRAS_DDR4: 0x0
875 07:47:19.452497 SPD_MIN_TRC_DDR4: 0x6E
876 07:47:19.470473 SPD_FTB_TRC_DDR4: 0x0
877 07:47:19.470869 SPD_MIN_TRFC1_MSB_DDR4: 0xA
878 07:47:19.471157 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
879 07:47:19.471538 tRFC: 0xAF0
880 07:47:19.471885 tempCkNum: 0x55730
881 07:47:19.472233 SPD_MIN_TAA_DDR4: 0x6E
882 07:47:19.472553 SPD_FTB_TAA: 0x0
883 07:47:19.472881 SPD_TFAW_UPPER_DDR4: 0x0
884 07:47:19.473169 SPD_MIN_TFAW_DDR4: 0x68
885 07:47:19.473495 SPD_MIN_TRP_DDR4: 0x6E
886 07:47:19.473811 SPD_FTB_TRP_DDR4: 0x0
887 07:47:19.493063 SPD_MIN_TCCDL_DDR4: 0x28
888 07:47:19.493476 SPD_FTB_TCCDL_DDR4: 0x0
889 07:47:19.493825 ---------------------------------------------------------------------
890 07:47:19.494129 pGblData item skt ch dimm value
891 07:47:19.494507 ---------------------------------------------------------------------
892 07:47:19.515185 SDRAMCapacity 0 3 0 0x5
893 07:47:19.515649 BGNum 0 3 0 4
894 07:47:19.516075 BankNum 0 3 0 16
895 07:47:19.516543 ColBits 0 3 0 10
896 07:47:19.516962 RowBits 0 3 0 17
897 07:47:19.537227 SpdMirror 0 3 0 1
898 07:47:19.537734 SpdVdd 0 3 0 3
899 07:47:19.538193 PrimaryBusWidth 0 3 0 64
900 07:47:19.538684 ExtensionBusWidth 0 3 0 8
901 07:47:19.605683 RankSize 0 3 0 16384
902 07:47:19.605973 SpdRMId 0 3 0 0x3206
903 07:47:19.606220 SpdMMfgId 0 3 0 0xCE00
904 07:47:19.606460 SpdMMDate 0 3 0 0x2817
905 07:47:19.606746 SpdSerialNum 0 3 0 0xF5F02936
906 07:47:19.620475 SpdMinTRCD 0 3 0 0x6E
907 07:47:19.620979 SpdMinTRCDFtb 0 3 0 0x0
908 07:47:19.621328 nRCD 0 3 0 0x35B6
909 07:47:19.621665 SpdMinTRRDL 0 3 0 0x28
910 07:47:19.633314 SpdMinTRRD 0 3 0 0x1B
911 07:47:19.633761 SpdMinTRAS 0 3 0 0x100
912 07:47:19.634137 SpdMinTRC 0 3 0 0x16E
913 07:47:19.634499 SpdMinTRCFtb 0 3 0 0x0
914 07:47:19.634922 SpdMinTRFC 0 3 0 0xAF0
915 07:47:19.650619 SpdMinTAA 0 3 0 0x6E
916 07:47:19.651163 SpdMinTAAFtb 0 3 0 0x0
917 07:47:19.651629 SpdMinTFAW 0 3 0 0x68
918 07:47:19.652078 SpdMinTRP 0 3 0 0x6E
919 07:47:19.652584 SpdMinTRPFtb 0 3 0 0x0
920 07:47:19.660703 nRP 0 3 0 0x35B6
921 07:47:19.661017 SpdMinTCCDL 0 3 0 0x28
922 07:47:19.661278 SpdMinTCCDLFtb 0 3 0 0x0
923 07:47:19.661531 SpdModuleAttr 0 3 0 0x0
924 07:47:19.672919 SpdAddrMap 0 3 0 0x1
925 07:47:19.673323 ---------------------------------------------------------------------
926 07:47:19.673675
927 07:47:19.674009 socket[0] channel[3] SPD information:
928 07:47:19.674339 ---------------------------------------------------------------------
929 07:47:19.674713 item skt ch value
930 07:47:19.690725 ---------------------------------------------------------------------
931 07:47:19.691132 nWR 0 3 0ps
932 07:47:19.691479 nRCD 0 3 13750ps
933 07:47:19.691813 nRRDL 0 3 4900ps
934 07:47:19.692143 nRRD 0 3 3300ps
935 07:47:19.692558 nRAS 0 3 32000ps
936 07:47:19.710624 nRC 0 3 45750ps
937 07:47:19.711085 nRFC 0 3 350000ps
938 07:47:19.711485 nWTR 0 3 0ps
939 07:47:19.711869 nRTP 0 3 0ps
940 07:47:19.712293 nAA 0 3 13750ps
941 07:47:19.712704 nFAW 0 3 13000ps
942 07:47:19.775474 nRP 0 3 13750ps
943 07:47:19.775963 nCCDL 0 3 5000ps
944 07:47:19.776450 ---------------------------------------------------------------------
945 07:47:19.776846
946 07:47:19.777226 socket[1] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information:
947 07:47:20.442733 SPD_MIN_TRCD_DDR4: 0x6E
948 07:47:20.443164 SPD_FTB_TRCD_DDR4: 0x0
949 07:47:20.443497 SPD_MIN_TRRDL_DDR4: 0x28
950 07:47:20.443791 SPD_FTB_TRRDL_DDR4: 0x9C
951 07:47:20.444076 SPD_MIN_TRRDS_DDR4: 0x1B
952 07:47:20.444414 SPD_FTB_TRRDS_DDR4: 0xB5
953 07:47:20.444712 SPD_EXT_TRC_TRAS_DDR4: 0x11
954 07:47:20.445124 SPD_MIN_TRAS_DDR4: 0x0
955 07:47:20.445507 SPD_MIN_TRC_DDR4: 0x6E
956 07:47:20.462855 SPD_FTB_TRC_DDR4: 0x0
957 07:47:20.463107 SPD_MIN_TRFC1_MSB_DDR4: 0xA
958 07:47:20.463330 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
959 07:47:20.463539 tRFC: 0xAF0
960 07:47:20.463738 tempCkNum: 0x55730
961 07:47:20.463948 SPD_MIN_TAA_DDR4: 0x6E
962 07:47:20.464147 SPD_FTB_TAA: 0x0
963 07:47:20.464369 SPD_TFAW_UPPER_DDR4: 0x0
964 07:47:20.464571 SPD_MIN_TFAW_DDR4: 0x68
965 07:47:20.464769 SPD_MIN_TRP_DDR4: 0x6E
966 07:47:20.464958 SPD_FTB_TRP_DDR4: 0x0
967 07:47:20.484677 SPD_MIN_TCCDL_DDR4: 0x28
968 07:47:20.484924 SPD_FTB_TCCDL_DDR4: 0x0
969 07:47:20.485135 ---------------------------------------------------------------------
970 07:47:20.485341 pGblData item skt ch dimm value
971 07:47:20.485555 ---------------------------------------------------------------------
972 07:47:20.506491 SDRAMCapacity 1 0 0 0x5
973 07:47:20.506770 BGNum 1 0 0 4
974 07:47:20.506994 BankNum 1 0 0 16
975 07:47:20.507204 ColBits 1 0 0 10
976 07:47:20.507402 RowBits 1 0 0 17
977 07:47:20.528255 SpdMirror 1 0 0 1
978 07:47:20.528510 SpdVdd 1 0 0 3
979 07:47:20.528730 PrimaryBusWidth 1 0 0 64
980 07:47:20.528939 ExtensionBusWidth 1 0 0 8
981 07:47:20.550945 RankSize 1 0 0 16384
982 07:47:20.551181 SpdRMId 1 0 0 0x3206
983 07:47:20.551393 SpdMMfgId 1 0 0 0xCE00
984 07:47:20.551609 SpdMMDate 1 0 0 0x2817
985 07:47:20.551813 SpdSerialNum 1 0 0 0xE2F32936
986 07:47:20.572299 SpdMinTRCD 1 0 0 0x6E
987 07:47:20.572539 SpdMinTRCDFtb 1 0 0 0x0
988 07:47:20.572743 nRCD 1 0 0 0x35B6
989 07:47:20.572961 SpdMinTRRDL 1 0 0 0x28
990 07:47:20.593865 SpdMinTRRD 1 0 0 0x1B
991 07:47:20.594112 SpdMinTRAS 1 0 0 0x100
992 07:47:20.594326 SpdMinTRC 1 0 0 0x16E
993 07:47:20.594526 SpdMinTRCFtb 1 0 0 0x0
994 07:47:20.594752 SpdMinTRFC 1 0 0 0xAF0
995 07:47:20.615891 SpdMinTAA 1 0 0 0x6E
996 07:47:20.616126 SpdMinTAAFtb 1 0 0 0x0
997 07:47:20.616364 SpdMinTFAW 1 0 0 0x68
998 07:47:20.616558 SpdMinTRP 1 0 0 0x6E
999 07:47:20.616763 SpdMinTRPFtb 1 0 0 0x0
1000 07:47:20.679147 nRP 1 0 0 0x35B6
1001 07:47:20.679395 SpdMinTCCDL 1 0 0 0x28
1002 07:47:20.679607 SpdMinTCCDLFtb 1 0 0 0x0
1003 07:47:20.679810 SpdModuleAttr 1 0 0 0x0
1004 07:47:20.692074 SpdAddrMap 1 0 0 0x1
1005 07:47:20.692331 ---------------------------------------------------------------------
1006 07:47:20.692550
1007 07:47:20.692753 socket[1] channel[0] SPD information:
1008 07:47:20.692952 ---------------------------------------------------------------------
1009 07:47:20.693148 item skt ch value
1010 07:47:20.710479 ---------------------------------------------------------------------
1011 07:47:20.710751 nWR 1 0 0ps
1012 07:47:20.710958 nRCD 1 0 13750ps
1013 07:47:20.711160 nRRDL 1 0 4900ps
1014 07:47:20.711350 nRRD 1 0 3300ps
1015 07:47:20.711552 nRAS 1 0 32000ps
1016 07:47:20.722464 nRC 1 0 45750ps
1017 07:47:20.722750 nRFC 1 0 350000ps
1018 07:47:20.722961 nWTR 1 0 0ps
1019 07:47:20.723160 nRTP 1 0 0ps
1020 07:47:20.723351 nAA 1 0 13750ps
1021 07:47:20.723549 nFAW 1 0 13000ps
1022 07:47:20.751589 nRP 1 0 13750ps
1023 07:47:20.751843 nCCDL 1 0 5000ps
1024 07:47:20.752044 ---------------------------------------------------------------------
1025 07:47:20.752272
1026 07:47:20.752485 socket[1] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information:
1027 07:47:21.460868 SPD_MIN_TRCD_DDR4: 0x6E
1028 07:47:21.461231 SPD_FTB_TRCD_DDR4: 0x0
1029 07:47:21.461432 SPD_MIN_TRRDL_DDR4: 0x28
1030 07:47:21.461640 SPD_FTB_TRRDL_DDR4: 0x9C
1031 07:47:21.461845 SPD_MIN_TRRDS_DDR4: 0x1B
1032 07:47:21.462040 SPD_FTB_TRRDS_DDR4: 0xB5
1033 07:47:21.462232 SPD_EXT_TRC_TRAS_DDR4: 0x11
1034 07:47:21.462414 SPD_MIN_TRAS_DDR4: 0x0
1035 07:47:21.462658 SPD_MIN_TRC_DDR4: 0x6E
1036 07:47:21.475225 SPD_FTB_TRC_DDR4: 0x0
1037 07:47:21.475476 AA: 0x0
1038 07:47:21.475677 SPD_TFAW_UPPER_DDR4: 0x0
1039 07:47:21.475885 SPD_MIN_TFAW_DDR4: 0x68
1040 07:47:21.476091 SPD_MIN_TRP_DDR4: 0x6E
1041 07:47:21.476310 SPD_FTB_TRP_DDR4: 0x0
1042 07:47:21.476506 SPD_MIN_TCCDL_DDR4: 0x28
1043 07:47:21.476710 SPD_FTB_TCCDL_DDR4: 0x0
1044 07:47:21.476893 ---------------------------------------------------------------------
1045 07:47:21.491138 pGblData item skt ch dimm value
1046 07:47:21.491394 ---------------------------------------------------------------------
1047 07:47:21.491614 SDRAMCapacity 1 1 0 0x5
1048 07:47:21.491828 BGNum 1 1 0 4
1049 07:47:21.508770 BankNum 1 1 0 16
1050 07:47:21.509031 ColBits 1 1 0 10
1051 07:47:21.509232 RowBits 1 1 0 17
1052 07:47:21.509441 SpdMirror 1 1 0 1
1053 07:47:21.509647 SpdVdd 1 1 0 3
1054 07:47:21.531098 PrimaryBusWidth 1 1 0 64
1055 07:47:21.531351 ExtensionBusWidth 1 1 0 8
1056 07:47:21.531552 RankSize 1 1 0 16384
1057 07:47:21.531761 SpdRMId 1 1 0 0x3206
1058 07:47:21.531968 SpdMMfgId 1 1 0 0xCE00
1059 07:47:21.553558 SpdMMDate 1 1 0 0x2817
1060 07:47:21.553898 SpdSerialNum 1 1 0 0x9AF22936
1061 07:47:21.554188 SpdMinTRCD 1 1 0 0x6E
1062 07:47:21.554491 SpdMinTRCDFtb 1 1 0 0x0
1063 07:47:21.574538 nRCD 1 1 0 0x35B6
1064 07:47:21.574958 SpdMinTRRDL 1 1 0 0x28
1065 07:47:21.575340 SpdMinTRRD 1 1 0 0x1B
1066 07:47:21.575672 SpdMinTRAS 1 1 0 0x100
1067 07:47:21.576024 SpdMinTRC 1 1 0 0x16E
1068 07:47:21.596335 SpdMinTRCFtb 1 1 0 0x0
1069 07:47:21.596743 SpdMinTRFC 1 1 0 0xAF0
1070 07:47:21.597092 SpdMinTAA 1 1 0 0x6E
1071 07:47:21.597426 SpdMinTAAFtb 1 1 0 0x0
1072 07:47:21.617983 SpdMinTFAW 1 1 0 0x68
1073 07:47:21.618269 SpdMinTRP 1 1 0 0x6E
1074 07:47:21.618594 SpdMinTRPFtb 1 1 0 0x0
1075 07:47:21.618789 nRP 1 1 0 0x35B6
1076 07:47:21.619068 SpdMinTCCDL 1 1 0 0x28
1077 07:47:21.640879 SpdMinTCCDLFtb 1 1 0 0x0
1078 07:47:21.641244 SpdModuleAttr 1 1 0 0x0
1079 07:47:21.641610 SpdAddrMap 1 1 0 0x1
1080 07:47:21.641940 ---------------------------------------------------------------------
1081 07:47:21.642216
1082 07:47:21.661993 socket[1] channel[1] SPD information:
1083 07:47:21.662432 ---------------------------------------------------------------------
1084 07:47:21.662933 item skt ch value
1085 07:47:21.663275 ---------------------------------------------------------------------
1086 07:47:21.663611 nWR 1 1 0ps
1087 07:47:21.683885 nRCD 1 1 13750ps
1088 07:47:21.684411 nRRDL 1 1 4900ps
1089 07:47:21.684812 nRRD 1 1 3300ps
1090 07:47:21.685213 nRAS 1 1 32000ps
1091 07:47:21.685592 nRC 1 1 45750ps
1092 07:47:21.685967 nRFC 1 1 350000ps
1093 07:47:21.686351 nWTR 1 1 0ps
1094 07:47:21.701754 nRTP 1 1 0ps
1095 07:47:21.702353 nAA 1 1 13750ps
1096 07:47:21.702880 nFAW 1 1 13000ps
1097 07:47:21.703288 nRP 1 1 13750ps
1098 07:47:21.703687 nCCDL 1 1 5000ps
1099 07:47:21.704092 ---------------------------------------------------------------------
1100 07:47:21.704504
1101 07:47:21.731066 socket[1] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information:
1102 07:47:22.424665 SPD_MIN_TRCD_DDR4: 0x6E
1103 07:47:22.425133 SPD_FTB_TRCD_DDR4: 0x0
1104 07:47:22.425335 SPD_MIN_TRRDL_DDR4: 0x28
1105 07:47:22.425529 SPD_FTB_TRRDL_DDR4: 0x9C
1106 07:47:22.425732 SPD_MIN_TRRDS_DDR4: 0x1B
1107 07:47:22.425921 SPD_FTB_TRRDS_DDR4: 0xB5
1108 07:47:22.426107 SPD_EXT_TRC_TRAS_DDR4: 0x11
1109 07:47:22.426291 SPD_MIN_TRAS_DDR4: 0x0
1110 07:47:22.426478 SPD_MIN_TRC_DDR4: 0x6E
1111 07:47:22.445801 SPD_FTB_TRC_DDR4: 0x0
1112 07:47:22.446162 SPD_MIN_TRFC1_MSB_DDR4: 0xA
1113 07:47:22.446427 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
1114 07:47:22.446733 tRFC: 0xAF0
1115 07:47:22.447022 tempCkNum: 0x55730
1116 07:47:22.447314 SPD_MIN_TAA_DDR4: 0x6E
1117 07:47:22.447584 SPD_FTB_TAA: 0x0
1118 07:47:22.447862 SPD_TFAW_UPPER_DDR4: 0x0
1119 07:47:22.448123 SPD_MIN_TFAW_DDR4: 0x68
1120 07:47:22.448435 SPD_MIN_TRP_DDR4: 0x6E
1121 07:47:22.448729 SPD_FTB_TRP_DDR4: 0x0
1122 07:47:22.467134 SPD_MIN_TCCDL_DDR4: 0x28
1123 07:47:22.467407 SPD_FTB_TCCDL_DDR4: 0x0
1124 07:47:22.467643 ---------------------------------------------------------------------
1125 07:47:22.467886 pGblData item skt ch dimm value
1126 07:47:22.468127 ---------------------------------------------------------------------
1127 07:47:22.489224 SDRAMCapacity 1 2 0 0x5
1128 07:47:22.489755 BGNum 1 2 0 4
1129 07:47:22.490140 BankNum 1 2 0 16
1130 07:47:22.490480 ColBits 1 2 0 10
1131 07:47:22.490859 RowBits 1 2 0 17
1132 07:47:22.513088 SpdMirror 1 2 0 1
1133 07:47:22.513445 SpdVdd 1 2 0 3
1134 07:47:22.513775 PrimaryBusWidth 1 2 0 64
1135 07:47:22.514088 ExtensionBusWidth 1 2 0 8
1136 07:47:22.532925 RankSize 1 2 0 16384
1137 07:47:22.533282 SpdRMId 1 2 0 0x3206
1138 07:47:22.533611 SpdMMfgId 1 2 0 0xCE00
1139 07:47:22.533920 SpdMMDate 1 2 0 0x2817
1140 07:47:22.534233 SpdSerialNum 1 2 0 0x9BF22936
1141 07:47:22.554876 SpdMinTRCD 1 2 0 0x6E
1142 07:47:22.555308 SpdMinTRCDFtb 1 2 0 0x0
1143 07:47:22.555634 nRCD 1 2 0 0x35B6
1144 07:47:22.555842 SpdMinTRRDL 1 2 0 0x28
1145 07:47:22.618363 SpdMinTRRD 1 2 0 0x1B
1146 07:47:22.618635 SpdMinTRAS 1 2 0 0x100
1147 07:47:22.618849 SpdMinTRC 1 2 0 0x16E
1148 07:47:22.619055 SpdMinTRCFtb 1 2 0 0x0
1149 07:47:22.619252 SpdMinTRFC 1 2 0 0xAF0
1150 07:47:22.631063 SpdMinTAA 1 2 0 0x6E
1151 07:47:22.631520 SpdMinTAAFtb 1 2 0 0x0
1152 07:47:22.631901 SpdMinTFAW 1 2 0 0x68
1153 07:47:22.632183 SpdMinTRP 1 2 0 0x6E
1154 07:47:22.632515 SpdMinTRPFtb 1 2 0 0x0
1155 07:47:22.640708 nRP 1 2 0 0x35B6
1156 07:47:22.641079 SpdMinTCCDL 1 2 0 0x28
1157 07:47:22.641390 SpdMinTCCDLFtb 1 2 0 0x0
1158 07:47:22.641693 SpdModuleAttr 1 2 0 0x0
1159 07:47:22.652352 SpdAddrMap 1 2 0 0x1
1160 07:47:22.652575 ---------------------------------------------------------------------
1161 07:47:22.652775
1162 07:47:22.652981 socket[1] channel[2] SPD information:
1163 07:47:22.653169 ---------------------------------------------------------------------
1164 07:47:22.653358 item skt ch value
1165 07:47:22.671728 ---------------------------------------------------------------------
1166 07:47:22.672096 nWR 1 2 0ps
1167 07:47:22.672413 nRCD 1 2 13750ps
1168 07:47:22.672693 nRRDL 1 2 4900ps
1169 07:47:22.673095 nRRD 1 2 3300ps
1170 07:47:22.673486 nRAS 1 2 32000ps
1171 07:47:22.690507 nRC 1 2 45750ps
1172 07:47:22.691000 nRFC 1 2 350000ps
1173 07:47:22.691365 nWTR 1 2 0ps
1174 07:47:22.691731 nRTP 1 2 0ps
1175 07:47:22.692074 nAA 1 2 13750ps
1176 07:47:22.692461 nFAW 1 2 13000ps
1177 07:47:22.717791 nRP 1 2 13750ps
1178 07:47:22.718121 nCCDL 1 2 5000ps
1179 07:47:22.718396 ---------------------------------------------------------------------
1180 07:47:22.718717
1181 07:47:22.718977 socket[1] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information:
1182 07:47:23.415577 SPD_MIN_TRCD_DDR4: 0x6E
1183 07:47:23.416782 SPD_FTB_TRCD_DDR4: 0x0
1184 07:47:23.417392 SPD_MIN_TRRDL_DDR4: 0x28
1185 07:47:23.417734 SPD_FTB_TRRDL_DDR4: 0x9C
1186 07:47:23.418271 SPD_MIN_TRRDS_DDR4: 0x1B
1187 07:47:23.419587 SPD_FTB_TRRDS_DDR4: 0xB5
1188 07:47:23.419940 SPD_EXT_TRC_TRAS_DDR4: 0x11
1189 07:47:23.420341 SPD_MIN_TRAS_DDR4: 0x0
1190 07:47:23.420640 SPD_MIN_TRC_DDR4: 0x6E
1191 07:47:23.437826 SPD_FTB_TRC_DDR4: 0x0
1192 07:47:23.438300 SPD_MIN_TRFC1_MSB_DDR4: 0xA
1193 07:47:23.438803 SPD_MIN_TRFC1_LSB_DDR4: 0xF0
1194 07:47:23.439253 tRFC: 0xAF0
1195 07:47:23.439657 tempCkNum: 0x55730
1196 07:47:23.440099 SPD_MIN_TAA_DDR4: 0x6E
1197 07:47:23.440409 SPD_FTB_TAA: 0x0
1198 07:47:23.440803 SPD_TFAW_UPPER_DDR4: 0x0
1199 07:47:23.441234 SPD_MIN_TFAW_DDR4: 0x68
1200 07:47:23.441470 SPD_MIN_TRP_DDR4: 0x6E
1201 07:47:23.441697 SPD_FTB_TRP_DDR4: 0x0
1202 07:47:23.501403 SPD_MIN_TCCDL_DDR4: 0x28
1203 07:47:23.501755 SPD_FTB_TCCDL_DDR4: 0x0
1204 07:47:23.502033 ---------------------------------------------------------------------
1205 07:47:23.502357 pGblData item skt ch dimm value
1206 07:47:23.502857 ---------------------------------------------------------------------
1207 07:47:23.520409 SDRAMCapacity 1 3 0 0x5
1208 07:47:23.520725 BGNum 1 3 0 4
1209 07:47:23.520995 BankNum 1 3 0 16
1210 07:47:23.521364 ColBits 1 3 0 10
1211 07:47:23.521720 RowBits 1 3 0 17
1212 07:47:23.532169 SpdMirror 1 3 0 1
1213 07:47:23.532503 SpdVdd 1 3 0 3
1214 07:47:23.532792 PrimaryBusWidth 1 3 0 64
1215 07:47:23.533082 ExtensionBusWidth 1 3 0 8
1216 07:47:23.552831 RankSize 1 3 0 16384
1217 07:47:23.553117 SpdRMId 1 3 0 0x3206
1218 07:47:23.553396 SpdMMfgId 1 3 0 0xCE00
1219 07:47:23.553656 SpdMMDate 1 3 0 0x2817
1220 07:47:23.553879 SpdSerialNum 1 3 0 0x84E82936
1221 07:47:23.570524 SpdMinTRCD 1 3 0 0x6E
1222 07:47:23.570832 SpdMinTRCDFtb 1 3 0 0x0
1223 07:47:23.571060 nRCD 1 3 0 0x35B6
1224 07:47:23.571308 SpdMinTRRDL 1 3 0 0x28
1225 07:47:23.580600 SpdMinTRRD 1 3 0 0x1B
1226 07:47:23.580821 SpdMinTRAS 1 3 0 0x100
1227 07:47:23.581012 SpdMinTRC 1 3 0 0x16E
1228 07:47:23.581197 SpdMinTRCFtb 1 3 0 0x0
1229 07:47:23.581379 SpdMinTRFC 1 3 0 0xAF0
1230 07:47:23.590949 SpdMinTAA 1 3 0 0x6E
1231 07:47:23.591209 SpdMinTAAFtb 1 3 0 0x0
1232 07:47:23.591429 SpdMinTFAW 1 3 0 0x68
1233 07:47:23.591645 SpdMinTRP 1 3 0 0x6E
1234 07:47:23.591858 SpdMinTRPFtb 1 3 0 0x0
1235 07:47:23.611723 nRP 1 3 0 0x35B6
1236 07:47:23.612046 SpdMinTCCDL 1 3 0 0x28
1237 07:47:23.612331 SpdMinTCCDLFtb 1 3 0 0x0
1238 07:47:23.612576 SpdModuleAttr 1 3 0 0x0
1239 07:47:23.633363 SpdAddrMap 1 3 0 0x1
1240 07:47:23.633599 ---------------------------------------------------------------------
1241 07:47:23.633801
1242 07:47:23.633991 socket[1] channel[3] SPD information:
1243 07:47:23.634180 ---------------------------------------------------------------------
1244 07:47:23.634440 item skt ch value
1245 07:47:23.703049 ---------------------------------------------------------------------
1246 07:47:23.703444 nWR 1 3 0ps
1247 07:47:23.720725 nRCD 1 3 13750ps
1248 07:47:23.721438 nRRDL 1 3 4900ps
1249 07:47:23.721887 nRRD 1 3 3300ps
1250 07:47:23.722158 nRAS 1 3 32000ps
1251 07:47:23.722423 nRC 1 3 45750ps
1252 07:47:23.722735 nRFC 1 3 350000ps
1253 07:47:23.723010 nWTR 1 3 0ps
1254 07:47:23.731046 nRTP 1 3 0ps
1255 07:47:23.731307 nAA 1 3 13750ps
1256 07:47:23.731532 nFAW 1 3 13000ps
1257 07:47:23.731794 nRP 1 3 13750ps
1258 07:47:23.732126 nCCDL 1 3 5000ps
1259 07:47:23.732448 ---------------------------------------------------------------------
1260 07:47:23.743440 ---------------------------------------------------------------------
1261 07:47:23.743958 Socket Channel Dimm Present Rank0 Rank1 Rank2 Rank3
1262 07:47:23.744478 0 0 0 YES YES YES NOT NOT
1263 07:47:23.760517 0 0 1 NOT NOT NOT NOT NOT
1264 07:47:23.760840 0 0 2 NOT NOT NOT NOT NOT
1265 07:47:23.761201 0 1 0 YES YES YES NOT NOT
1266 07:47:23.770793 0 1 1 NOT NOT NOT NOT NOT
1267 07:47:23.771079 0 1 2 NOT NOT NOT NOT NOT
1268 07:47:23.771338 0 2 0 YES YES YES NOT NOT
1269 07:47:23.771650 0 2 1 NOT NOT NOT NOT NOT
1270 07:47:23.780411 0 2 2 NOT NOT NOT NOT NOT
1271 07:47:23.780662 0 3 0 YES YES YES NOT NOT
1272 07:47:23.780894 0 3 1 NOT NOT NOT NOT NOT
1273 07:47:23.797556 0 3 2 NOT NOT NOT NOT NOT
1274 07:47:23.797927 1 0 0 YES YES YES NOT NOT
1275 07:47:23.798282 1 0 1 NOT NOT NOT NOT NOT
1276 07:47:23.798716 1 0 2 NOT NOT NOT NOT NOT
1277 07:47:23.819389 1 1 0 YES YES YES NOT NOT
1278 07:47:23.819652 1 1 1 NOT NOT NOT NOT NOT
1279 07:47:23.819921 1 1 2 NOT NOT NOT NOT NOT
1280 07:47:23.840418 1 2 0 YES YES YES NOT NOT
1281 07:47:23.840677 1 2 1 NOT NOT NOT NOT NOT
1282 07:47:23.841117 1 2 2 NOT NOT NOT NOT NOT
1283 07:47:23.898847 1 3 0 YES YES YES NOT NOT
1284 07:47:23.899203 1 3 1 NOT NOT NOT NOT NOT
1285 07:47:23.914213 1 3 2 NOT NOT NOT NOT NOT
1286 07:47:23.914499 ---------------------------------------------------------------------
1287 07:47:23.914791 **********************************************************************
1288 07:47:23.915153 Socket[0] Channel[0] Base:[0x60340000] Speed:[2400]
1289 07:47:23.930496 **********************************************************************
1290 07:47:23.930781 ==========================
1291 07:47:23.931099 config parameters from SPD
1292 07:47:23.931432 ==========================
1293 07:47:23.931689 DDR PHY PLL config.....................................OK!
1294 07:47:23.931897 Top module cfg.........................................OK
1295 07:47:23.943154 ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1296 07:47:23.943438 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2
1297 07:47:23.943789 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1
1298 07:47:23.944168 Dmc init static........................................OK
1299 07:47:23.960532 Phy init dynamic.......................................OK
1300 07:47:23.960939
1301 07:47:23.961328 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1302 07:47:23.961705 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD
1303 07:47:23.971055 dimm[0] rcd init finished!
1304 07:47:23.971545 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1305 07:47:23.971933 rank[0] sdram init finished!
1306 07:47:23.972363 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1307 07:47:23.972904 rank[1] sdram init finished!
1308 07:47:23.973329 -----------------------------------------------------
1309 07:47:24.006459 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1310 07:47:24.006735 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1311 07:47:24.006976 -----------------------------------------------------
1312 07:47:24.007181 Dram init..............................................OK
1313 07:47:24.007380 socket[0] channel[0] rank[0] Phy gate leveling.....OK
1314 07:47:24.020341 socket[0] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1315 07:47:24.020593 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1316 07:47:24.020816 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1317 07:47:24.081919 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1318 07:47:24.082223 OK
1319 07:47:24.082460 socket[0] channel[0] rank[0] Phy write leveling.....OK
1320 07:47:24.082856 socket[0] channel[0] rank[1] Phy write leveling.....OK
1321 07:47:24.100672 socket[0] channel[0] rank[0] Phy write leveling 2...OK
1322 07:47:24.101148 socket[0] channel[0] rank[1] Phy write leveling 2...OK
1323 07:47:24.101399 socket[0] channel[0] rank[0] Read data eye training start:
1324 07:47:24.140313 socket[0] channel[0] rank[0] Read data eye training end
1325 07:47:24.140679
1326 07:47:24.141048 socket[0] channel[0] rank[1] Read data eye training start:
1327 07:47:24.200844 socket[0] channel[0] rank[1] Read data eye training end
1328 07:47:24.201204
1329 07:47:24.201491 socket[0] channel[0] rank[0] Write data eye training start:
1330 07:47:24.251699 socket[0] channel[0] rank[0] Write data eye training end
1331 07:47:24.252227
1332 07:47:24.252662 socket[0] channel[0] rank[1] Write data eye training start:
1333 07:47:24.310577 socket[0] channel[0] rank[1] Write data eye training end
1334 07:47:24.310984
1335 07:47:24.311270 socket[0] channel[0] Rx vref training start
1336 07:47:24.674709 socket[0] channel[0] Rx vref training end
1337 07:47:24.675136
1338 07:47:24.675590 socket[0] channel[0] rank[0] Read data eye training start:
1339 07:47:24.755119 socket[0] channel[0] rank[0] Read data eye training end
1340 07:47:24.755526
1341 07:47:24.755817 socket[0] channel[0] rank[1] Read data eye training start:
1342 07:47:24.780310 socket[0] channel[0] rank[1] Read data eye training end
1343 07:47:24.780695
1344 07:47:24.781001 socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start:
1345 07:47:24.810722 socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end
1346 07:47:24.811063
1347 07:47:24.811288 socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start:
1348 07:47:24.811507 socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end
1349 07:47:24.811722
1350 07:47:24.811931 socket[0] channel[0] Tx vref training start
1351 07:47:26.300585 socket[0] channel[0] Tx vref training end
1352 07:47:26.301213
1353 07:47:26.301645 socket[0] channel[0] rank[0] Write data eye training start:
1354 07:47:26.350778 socket[0] channel[0] rank[0] Write data eye training end
1355 07:47:26.351180
1356 07:47:26.351525 socket[0] channel[0] rank[1] Write data eye training start:
1357 07:47:26.423032 socket[0] channel[0] rank[1] Write data eye training end
1358 07:47:26.423389
1359 07:47:26.423707 //----------------------------------
1360 07:47:26.423993 sfc test rank0
1361 07:47:26.424321 [0]wdata: 0x11111111 - 0x11111111 rdata
1362 07:47:26.424581 [1]wdata: 0x11111111 - 0x11111111 rdata
1363 07:47:26.424838 [2]wdata: 0x22222222 - 0x22222222 rdata
1364 07:47:26.441893 [3]wdata: 0x22222222 - 0x22222222 rdata
1365 07:47:26.442281 [4]wdata: 0x33333333 - 0x33333333 rdata
1366 07:47:26.442690 [5]wdata: 0x33333333 - 0x33333333 rdata
1367 07:47:26.443070 [6]wdata: 0x44444444 - 0x44444444 rdata
1368 07:47:26.443387 [7]wdata: 0x44444444 - 0x44444444 rdata
1369 07:47:26.443699 [8]wdata: 0x55555555 - 0x55555555 rdata
1370 07:47:26.461754 [9]wdata: 0x55555555 - 0x55555555 rdata
1371 07:47:26.461986 [10]wdata: 0x66666666 - 0x66666666 rdata
1372 07:47:26.462188 [11]wdata: 0x66666666 - 0x66666666 rdata
1373 07:47:26.462381 [12]wdata: 0x77777777 - 0x77777777 rdata
1374 07:47:26.462605 [13]wdata: 0x77777777 - 0x77777777 rdata
1375 07:47:26.462800 [14]wdata: 0x88888888 - 0x88888888 rdata
1376 07:47:26.483577 [15]wdata: 0x88888888 - 0x88888888 rdata
1377 07:47:26.483809 [16]wdata: 0x44332211 - 0x44332211 rdata
1378 07:47:26.484010 [17]wdata: 0x88776655 - 0x88776655 rdata
1379 07:47:26.484203 sfc test rank1
1380 07:47:26.484409 [0]wdata: 0x11111111 - 0x11111111 rdata
1381 07:47:26.484598 [1]wdata: 0x11111111 - 0x11111111 rdata
1382 07:47:26.484785 [2]wdata: 0x22222222 - 0x22222222 rdata
1383 07:47:26.505458 [3]wdata: 0x22222222 - 0x22222222 rdata
1384 07:47:26.505688 [4]wdata: 0x33333333 - 0x33333333 rdata
1385 07:47:26.505888 [5]wdata: 0x33333333 - 0x33333333 rdata
1386 07:47:26.506081 [6]wdata: 0x44444444 - 0x44444444 rdata
1387 07:47:26.506271 [7]wdata: 0x44444444 - 0x44444444 rdata
1388 07:47:26.506456 [8]wdata: 0x55555555 - 0x55555555 rdata
1389 07:47:26.527369 [9]wdata: 0x55555555 - 0x55555555 rdata
1390 07:47:26.527753 [10]wdata: 0x66666666 - 0x66666666 rdata
1391 07:47:26.528062 [11]wdata: 0x66666666 - 0x66666666 rdata
1392 07:47:26.528709 [12]wdata: 0x77777777 - 0x77777777 rdata
1393 07:47:26.529015 [13]wdata: 0x77777777 - 0x77777777 rdata
1394 07:47:26.529310 [14]wdata: 0x88888888 - 0x88888888 rdata
1395 07:47:26.549284 [15]wdata: 0x88888888 - 0x88888888 rdata
1396 07:47:26.549578 [16]wdata: 0x44332211 - 0x44332211 rdata
1397 07:47:26.549778 [17]wdata: 0x88776655 - 0x88776655 rdata
1398 07:47:26.549991 //----------------------------------
1399 07:47:26.550183 **********************************************************************
1400 07:47:26.572573 Socket[0] Channel[0] DDR Init Finished!
1401 07:47:26.572970 **********************************************************************
1402 07:47:26.573318 **********************************************************************
1403 07:47:26.573649 Socket[0] Channel[1] Base:[0x60350000] Speed:[2400]
1404 07:47:26.593357 **********************************************************************
1405 07:47:26.593632 ==========================
1406 07:47:26.593908 config parameters from SPD
1407 07:47:26.594135 ==========================
1408 07:47:26.594396 DDR PHY PLL config.....................................OK!
1409 07:47:26.594640 Top module cfg.........................................OK
1410 07:47:26.615200 ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1411 07:47:26.615431 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2
1412 07:47:26.615685 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1
1413 07:47:26.615897 Dmc init static........................................OK
1414 07:47:26.630382 Phy init dynamic.......................................OK
1415 07:47:26.630637
1416 07:47:26.630837 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
1417 07:47:26.631029 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1418 07:47:26.654044 dimm[0] rcd init finished!
1419 07:47:26.654275 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1420 07:47:26.654473 rank[0] sdram init finished!
1421 07:47:26.654697 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1422 07:47:26.654886 rank[1] sdram init finished!
1423 07:47:26.655073 -----------------------------------------------------
1424 07:47:26.701774 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1425 07:47:26.702160 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1426 07:47:26.702493 -----------------------------------------------------
1427 07:47:26.702859 Dram init..............................................OK
1428 07:47:26.703160 socket[0] channel[1] rank[0] Phy gate leveling.....OK
1429 07:47:26.720731 socket[0] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1430 07:47:26.721189 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1431 07:47:26.721600 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1432 07:47:26.758601 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1433 07:47:26.759070 OK
1434 07:47:26.759591 socket[0] channel[1] rank[0] Phy write leveling.....OK
1435 07:47:26.760016 socket[0] channel[1] rank[1] Phy write leveling.....OK
1436 07:47:26.790603 socket[0] channel[1] rank[0] Phy write leveling 2...OK
1437 07:47:26.791091 socket[0] channel[1] rank[1] Phy write leveling 2...OK
1438 07:47:26.791577 socket[0] channel[1] rank[0] Read data eye training start:
1439 07:47:26.830314 socket[0] channel[1] rank[0] Read data eye training end
1440 07:47:26.830677
1441 07:47:26.830915 socket[0] channel[1] rank[1] Read data eye training start:
1442 07:47:26.893009 socket[0] channel[1] rank[1] Read data eye training end
1443 07:47:26.893377
1444 07:47:26.893579 socket[0] channel[1] rank[0] Write data eye training start:
1445 07:47:26.950696 socket[0] channel[1] rank[0] Write data eye training end
1446 07:47:26.951080
1447 07:47:26.951271 socket[0] channel[1] rank[1] Write data eye training start:
1448 07:47:27.031589 socket[0] channel[1] rank[1] Write data eye training end
1449 07:47:27.032053
1450 07:47:27.032454 socket[0] channel[1] Rx vref training start
1451 07:47:27.382540 socket[0] channel[1] Rx vref training end
1452 07:47:27.382903
1453 07:47:27.383092 socket[0] channel[1] rank[0] Read data eye training start:
1454 07:47:27.454378 socket[0] channel[1] rank[0] Read data eye training end
1455 07:47:27.454669
1456 07:47:27.454863 socket[0] channel[1] rank[1] Read data eye training start:
1457 07:47:27.473875 socket[0] channel[1] rank[1] Read data eye training end
1458 07:47:27.474191
1459 07:47:27.474472 socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start:
1460 07:47:27.474776 socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end
1461 07:47:27.475051
1462 07:47:27.502878 socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start:
1463 07:47:27.503113 socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end
1464 07:47:27.503312
1465 07:47:27.503498 socket[0] channel[1] Tx vref training start
1466 07:47:29.041590 socket[0] channel[1] Tx vref training end
1467 07:47:29.042092
1468 07:47:29.042424 socket[0] channel[1] rank[0] Write data eye training start:
1469 07:47:29.092274 socket[0] channel[1] rank[0] Write data eye training end
1470 07:47:29.092538
1471 07:47:29.092852 socket[0] channel[1] rank[1] Write data eye training start:
1472 07:47:29.150807 socket[0] channel[1] rank[1] Write data eye training end
1473 07:47:29.151227
1474 07:47:29.151550 //----------------------------------
1475 07:47:29.151863 sfc test rank0
1476 07:47:29.173402 [0]wdata: 0x11111111 - 0x11111111 rdata
1477 07:47:29.173807 [1]wdata: 0x11111111 - 0x11111111 rdata
1478 07:47:29.174153 [2]wdata: 0x22222222 - 0x22222222 rdata
1479 07:47:29.174488 [3]wdata: 0x22222222 - 0x22222222 rdata
1480 07:47:29.174901 [4]wdata: 0x33333333 - 0x33333333 rdata
1481 07:47:29.175248 [5]wdata: 0x33333333 - 0x33333333 rdata
1482 07:47:29.195056 [6]wdata: 0x44444444 - 0x44444444 rdata
1483 07:47:29.195523 [7]wdata: 0x44444444 - 0x44444444 rdata
1484 07:47:29.195962 [8]wdata: 0x55555555 - 0x55555555 rdata
1485 07:47:29.196361 [9]wdata: 0x55555555 - 0x55555555 rdata
1486 07:47:29.196657 [10]wdata: 0x66666666 - 0x66666666 rdata
1487 07:47:29.196938 [11]wdata: 0x66666666 - 0x66666666 rdata
1488 07:47:29.216787 [12]wdata: 0x77777777 - 0x77777777 rdata
1489 07:47:29.217019 [13]wdata: 0x77777777 - 0x77777777 rdata
1490 07:47:29.217210 [14]wdata: 0x88888888 - 0x88888888 rdata
1491 07:47:29.217394 [15]wdata: 0x88888888 - 0x88888888 rdata
1492 07:47:29.217575 [16]wdata: 0x44332211 - 0x44332211 rdata
1493 07:47:29.217754 [17]wdata: 0x88776655 - 0x88776655 rdata
1494 07:47:29.217930 sfc test rank1
1495 07:47:29.238822 [0]wdata: 0x11111111 - 0x11111111 rdata
1496 07:47:29.239072 [1]wdata: 0x11111111 - 0x11111111 rdata
1497 07:47:29.239263 [2]wdata: 0x22222222 - 0x22222222 rdata
1498 07:47:29.239447 [3]wdata: 0x22222222 - 0x22222222 rdata
1499 07:47:29.239629 [4]wdata: 0x33333333 - 0x33333333 rdata
1500 07:47:29.239808 [5]wdata: 0x33333333 - 0x33333333 rdata
1501 07:47:29.260714 [6]wdata: 0x44444444 - 0x44444444 rdata
1502 07:47:29.260951 [7]wdata: 0x44444444 - 0x44444444 rdata
1503 07:47:29.261142 [8]wdata: 0x55555555 - 0x55555555 rdata
1504 07:47:29.261325 [9]wdata: 0x55555555 - 0x55555555 rdata
1505 07:47:29.261506 [10]wdata: 0x66666666 - 0x66666666 rdata
1506 07:47:29.261685 [11]wdata: 0x66666666 - 0x66666666 rdata
1507 07:47:29.282624 [12]wdata: 0x77777777 - 0x77777777 rdata
1508 07:47:29.282876 [13]wdata: 0x77777777 - 0x77777777 rdata
1509 07:47:29.283068 [14]wdata: 0x88888888 - 0x88888888 rdata
1510 07:47:29.283253 [15]wdata: 0x88888888 - 0x88888888 rdata
1511 07:47:29.283435 [16]wdata: 0x44332211 - 0x44332211 rdata
1512 07:47:29.283614 [17]wdata: 0x88776655 - 0x88776655 rdata
1513 07:47:29.304636 //----------------------------------
1514 07:47:29.304900 **********************************************************************
1515 07:47:29.305094 Socket[0] Channel[1] DDR Init Finished!
1516 07:47:29.305279 **********************************************************************
1517 07:47:29.326938 **********************************************************************
1518 07:47:29.327193 Socket[0] Channel[2] Base:[0x40340000] Speed:[2400]
1519 07:47:29.327399 **********************************************************************
1520 07:47:29.327587 ==========================
1521 07:47:29.327784 config parameters from SPD
1522 07:47:29.327978 ==========================
1523 07:47:29.353239 DDR PHY PLL config.....................................OK!
1524 07:47:29.353496 Top module cfg.........................................OK
1525 07:47:29.353702 ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1526 07:47:29.353886 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2
1527 07:47:29.373034 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1
1528 07:47:29.373421 Dmc init static........................................OK
1529 07:47:29.373729 Phy init dynamic.......................................OK
1530 07:47:29.373935
1531 07:47:29.374220 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1532 07:47:29.390330 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1533 07:47:29.390611 dimm[0] rcd init finished!
1534 07:47:29.390834 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1535 07:47:29.391041 rank[0] sdram init finished!
1536 07:47:29.405980 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1537 07:47:29.406224 rank[1] sdram init finished!
1538 07:47:29.406436 -----------------------------------------------------
1539 07:47:29.406676 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1540 07:47:29.406892 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1541 07:47:29.455705 -----------------------------------------------------
1542 07:47:29.455950 Dram init..............................................OK
1543 07:47:29.456161 socket[0] channel[2] rank[0] Phy gate leveling.....OK
1544 07:47:29.456380 socket[0] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1545 07:47:29.472718 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1546 07:47:29.472969 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1547 07:47:29.473182 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1548 07:47:29.473391 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1549 07:47:29.473592 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1550 07:47:29.512914 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1551 07:47:29.513267 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1552 07:47:29.513572 OK
1553 07:47:29.513872 socket[0] channel[2] rank[0] Phy write leveling.....OK
1554 07:47:29.514165 socket[0] channel[2] rank[1] Phy write leveling.....OK
1555 07:47:29.540975 socket[0] channel[2] rank[0] Phy write leveling 2...OK
1556 07:47:29.541435 socket[0] channel[2] rank[1] Phy write leveling 2...OK
1557 07:47:29.541835 socket[0] channel[2] rank[0] Read data eye training start:
1558 07:47:29.590370 socket[0] channel[2] rank[0] Read data eye training end
1559 07:47:29.590641
1560 07:47:29.590873 socket[0] channel[2] rank[1] Read data eye training start:
1561 07:47:29.660729 socket[0] channel[2] rank[1] Read data eye training end
1562 07:47:29.661179
1563 07:47:29.661640 socket[0] channel[2] rank[0] Write data eye training start:
1564 07:47:29.700322 socket[0] channel[2] rank[0] Write data eye training end
1565 07:47:29.700554
1566 07:47:29.700753 socket[0] channel[2] rank[1] Write data eye training start:
1567 07:47:29.770878 socket[0] channel[2] rank[1] Write data eye training end
1568 07:47:29.771616
1569 07:47:29.772097 socket[0] channel[2] Rx vref training start
1570 07:47:30.111253 socket[0] channel[2] Rx vref training end
1571 07:47:30.111843
1572 07:47:30.112333 socket[0] channel[2] rank[0] Read data eye training start:
1573 07:47:30.160524 socket[0] channel[2] rank[0] Read data eye training end
1574 07:47:30.161074
1575 07:47:30.161541 socket[0] channel[2] rank[1] Read data eye training start:
1576 07:47:30.216975 socket[0] channel[2] rank[1] Read data eye training end
1577 07:47:30.217506
1578 07:47:30.217932 socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start:
1579 07:47:30.218354 socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end
1580 07:47:30.218829
1581 07:47:30.241530 socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start:
1582 07:47:30.241953 socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end
1583 07:47:30.242518
1584 07:47:30.242926 socket[0] channel[2] Tx vref training start
1585 07:47:31.690539 socket[0] channel[2] Tx vref training end
1586 07:47:31.690951
1587 07:47:31.691142 socket[0] channel[2] rank[0] Write data eye training start:
1588 07:47:31.740400 socket[0] channel[2] rank[0] Write data eye training end
1589 07:47:31.740797
1590 07:47:31.741072 socket[0] channel[2] rank[1] Write data eye training start:
1591 07:47:31.804841 socket[0] channel[2] rank[1] Write data eye training end
1592 07:47:31.805346
1593 07:47:31.805755 //----------------------------------
1594 07:47:31.806151 sfc test rank0
1595 07:47:31.806538 [0]wdata: 0x11111111 - 0x11111111 rdata
1596 07:47:31.806997 [1]wdata: 0x11111111 - 0x11111111 rdata
1597 07:47:31.807489 [2]wdata: 0x22222222 - 0x22222222 rdata
1598 07:47:31.826382 [3]wdata: 0x22222222 - 0x22222222 rdata
1599 07:47:31.826640 [4]wdata: 0x33333333 - 0x33333333 rdata
1600 07:47:31.826832 [5]wdata: 0x33333333 - 0x33333333 rdata
1601 07:47:31.827013 [6]wdata: 0x44444444 - 0x44444444 rdata
1602 07:47:31.827251 [7]wdata: 0x44444444 - 0x44444444 rdata
1603 07:47:31.827430 [8]wdata: 0x55555555 - 0x55555555 rdata
1604 07:47:31.848169 [9]wdata: 0x55555555 - 0x55555555 rdata
1605 07:47:31.848446 [10]wdata: 0x66666666 - 0x66666666 rdata
1606 07:47:31.848676 [11]wdata: 0x66666666 - 0x66666666 rdata
1607 07:47:31.848889 [12]wdata: 0x77777777 - 0x77777777 rdata
1608 07:47:31.849100 [13]wdata: 0x77777777 - 0x77777777 rdata
1609 07:47:31.849304 [14]wdata: 0x88888888 - 0x88888888 rdata
1610 07:47:31.870440 [15]wdata: 0x88888888 - 0x88888888 rdata
1611 07:47:31.870769 [16]wdata: 0x44332211 - 0x44332211 rdata
1612 07:47:31.871174 [17]wdata: 0x88776655 - 0x88776655 rdata
1613 07:47:31.871515 sfc test rank1
1614 07:47:31.871886 [0]wdata: 0x11111111 - 0x11111111 rdata
1615 07:47:31.872194 [1]wdata: 0x11111111 - 0x11111111 rdata
1616 07:47:31.872538 [2]wdata: 0x22222222 - 0x22222222 rdata
1617 07:47:31.891718 [3]wdata: 0x22222222 - 0x22222222 rdata
1618 07:47:31.892170 [4]wdata: 0x33333333 - 0x33333333 rdata
1619 07:47:31.892597 [5]wdata: 0x33333333 - 0x33333333 rdata
1620 07:47:31.892960 [6]wdata: 0x44444444 - 0x44444444 rdata
1621 07:47:31.893367 [7]wdata: 0x44444444 - 0x44444444 rdata
1622 07:47:31.893731 [8]wdata: 0x55555555 - 0x55555555 rdata
1623 07:47:31.914506 [9]wdata: 0x55555555 - 0x55555555 rdata
1624 07:47:31.915125 [10]wdata: 0x66666666 - 0x66666666 rdata
1625 07:47:31.915593 [11]wdata: 0x66666666 - 0x66666666 rdata
1626 07:47:31.916004 [12]wdata: 0x77777777 - 0x77777777 rdata
1627 07:47:31.916492 [13]wdata: 0x77777777 - 0x77777777 rdata
1628 07:47:31.916864 [14]wdata: 0x88888888 - 0x88888888 rdata
1629 07:47:31.936023 [15]wdata: 0x88888888 - 0x88888888 rdata
1630 07:47:31.936482 [16]wdata: 0x44332211 - 0x44332211 rdata
1631 07:47:31.936874 [17]wdata: 0x88776655 - 0x88776655 rdata
1632 07:47:31.937292 //----------------------------------
1633 07:47:31.937701 **********************************************************************
1634 07:47:31.956713 Socket[0] Channel[2] DDR Init Finished!
1635 07:47:31.957230 **********************************************************************
1636 07:47:31.957696 **********************************************************************
1637 07:47:31.958133 Socket[0] Channel[3] Base:[0x40350000] Speed:[2400]
1638 07:47:31.989175 **********************************************************************
1639 07:47:31.989722 ==========================
1640 07:47:31.990228 config parameters from SPD
1641 07:47:31.990781 ==========================
1642 07:47:31.991247 DDR PHY PLL config.....................................OK!
1643 07:47:31.991677 Top module cfg.........................................OK
1644 07:47:32.002199 ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1645 07:47:32.002607 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2
1646 07:47:32.002994 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1
1647 07:47:32.003317 Dmc init static........................................OK
1648 07:47:32.020741 Phy init dynamic.......................................OK
1649 07:47:32.021206
1650 07:47:32.021604 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
1651 07:47:32.021989 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD
1652 07:47:32.038203 dimm[0] rcd init finished!
1653 07:47:32.038742 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1654 07:47:32.039144 rank[0] sdram init finished!
1655 07:47:32.039528 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1656 07:47:32.039905 rank[1] sdram init finished!
1657 07:47:32.040310 -----------------------------------------------------
1658 07:47:32.062407 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1659 07:47:32.062976 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1660 07:47:32.063410 -----------------------------------------------------
1661 07:47:32.063832 Dram init..............................................OK
1662 07:47:32.095174 socket[0] channel[3] rank[0] Phy gate leveling.....OK
1663 07:47:32.095789 socket[0] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1664 07:47:32.114978 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1665 07:47:32.115569 lat_adj_start of rank 1 byte 2 is set to 0x00000001
1666 07:47:32.116098 lat_adj_start of rank 1 byte 3 is set to 0x00000001
1667 07:47:32.116632 lat_adj_start of rank 1 byte 4 is set to 0x00000001
1668 07:47:32.117148 lat_adj_start of rank 1 byte 5 is set to 0x00000001
1669 07:47:32.155539 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1670 07:47:32.155968 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1671 07:47:32.156304 OK
1672 07:47:32.156529 socket[0] channel[3] rank[0] Phy write leveling.....OK
1673 07:47:32.156873 socket[0] channel[3] rank[1] Phy write leveling.....OK
1674 07:47:32.214485 socket[0] channel[3] rank[0] Phy write leveling 2...OK
1675 07:47:32.214833 socket[0] channel[3] rank[1] Phy write leveling 2...OK
1676 07:47:32.215033 socket[0] channel[3] rank[0] Read data eye training start:
1677 07:47:32.240659 socket[0] channel[3] rank[0] Read data eye training end
1678 07:47:32.240932
1679 07:47:32.241146 socket[0] channel[3] rank[1] Read data eye training start:
1680 07:47:32.281930 socket[0] channel[3] rank[1] Read data eye training end
1681 07:47:32.282196
1682 07:47:32.282450 socket[0] channel[3] rank[0] Write data eye training start:
1683 07:47:32.341550 socket[0] channel[3] rank[0] Write data eye training end
1684 07:47:32.341822
1685 07:47:32.342016 socket[0] channel[3] rank[1] Write data eye training start:
1686 07:47:32.440279 socket[0] channel[3] rank[1] Write data eye training end
1687 07:47:32.440509
1688 07:47:32.440699 socket[0] channel[3] Rx vref training start
1689 07:47:32.750527 socket[0] channel[3] Rx vref training end
1690 07:47:32.750815
1691 07:47:32.751004 socket[0] channel[3] rank[0] Read data eye training start:
1692 07:47:32.820400 socket[0] channel[3] rank[0] Read data eye training end
1693 07:47:32.820629
1694 07:47:32.820818 socket[0] channel[3] rank[1] Read data eye training start:
1695 07:47:32.859193 socket[0] channel[3] rank[1] Read data eye training end
1696 07:47:32.859456
1697 07:47:32.859685 socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start:
1698 07:47:32.859904 socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end
1699 07:47:32.860125
1700 07:47:32.880690 socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start:
1701 07:47:32.880942 socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end
1702 07:47:32.881167
1703 07:47:32.881423 socket[0] channel[3] Tx vref training start
1704 07:47:34.271069 socket[0] channel[3] Tx vref training end
1705 07:47:34.271462
1706 07:47:34.271718 socket[0] channel[3] rank[0] Write data eye training start:
1707 07:47:34.352333 socket[0] channel[3] rank[0] Write data eye training end
1708 07:47:34.352616
1709 07:47:34.352837 socket[0] channel[3] rank[1] Write data eye training start:
1710 07:47:34.397573 socket[0] channel[3] rank[1] Write data eye training end
1711 07:47:34.397811
1712 07:47:34.398028 //----------------------------------
1713 07:47:34.398241 sfc test rank0
1714 07:47:34.398453 [0]wdata: 0x11111111 - 0x11111111 rdata
1715 07:47:34.398682 [1]wdata: 0x11111111 - 0x11111111 rdata
1716 07:47:34.398893 [2]wdata: 0x22222222 - 0x22222222 rdata
1717 07:47:34.419847 [3]wdata: 0x22222222 - 0x22222222 rdata
1718 07:47:34.420083 [4]wdata: 0x33333333 - 0x33333333 rdata
1719 07:47:34.420312 [5]wdata: 0x33333333 - 0x33333333 rdata
1720 07:47:34.420528 [6]wdata: 0x44444444 - 0x44444444 rdata
1721 07:47:34.420743 [7]wdata: 0x44444444 - 0x44444444 rdata
1722 07:47:34.420954 [8]wdata: 0x55555555 - 0x55555555 rdata
1723 07:47:34.449093 [9]wdata: 0x55555555 - 0x55555555 rdata
1724 07:47:34.449336 [10]wdata: 0x66666666 - 0x66666666 rdata
1725 07:47:34.449580 [11]wdata: 0x66666666 - 0x66666666 rdata
1726 07:47:34.449790 [12]wdata: 0x77777777 - 0x77777777 rdata
1727 07:47:34.449996 [13]wdata: 0x77777777 - 0x77777777 rdata
1728 07:47:34.450197 [14]wdata: 0x88888888 - 0x88888888 rdata
1729 07:47:34.463202 [15]wdata: 0x88888888 - 0x88888888 rdata
1730 07:47:34.463439 [16]wdata: 0x44332211 - 0x44332211 rdata
1731 07:47:34.463657 [17]wdata: 0x88776655 - 0x88776655 rdata
1732 07:47:34.463872 sfc test rank1
1733 07:47:34.464085 [0]wdata: 0x11111111 - 0x11111111 rdata
1734 07:47:34.464308 [1]wdata: 0x11111111 - 0x11111111 rdata
1735 07:47:34.464515 [2]wdata: 0x22222222 - 0x22222222 rdata
1736 07:47:34.484967 [3]wdata: 0x22222222 - 0x22222222 rdata
1737 07:47:34.485204 [4]wdata: 0x33333333 - 0x33333333 rdata
1738 07:47:34.485427 [5]wdata: 0x33333333 - 0x33333333 rdata
1739 07:47:34.485643 [6]wdata: 0x44444444 - 0x44444444 rdata
1740 07:47:34.485855 [7]wdata: 0x44444444 - 0x44444444 rdata
1741 07:47:34.486065 [8]wdata: 0x55555555 - 0x55555555 rdata
1742 07:47:34.506908 [9]wdata: 0x55555555 - 0x55555555 rdata
1743 07:47:34.507183 [10]wdata: 0x66666666 - 0x66666666 rdata
1744 07:47:34.507433 [11]wdata: 0x66666666 - 0x66666666 rdata
1745 07:47:34.507673 [12]wdata: 0x77777777 - 0x77777777 rdata
1746 07:47:34.507911 [13]wdata: 0x77777777 - 0x77777777 rdata
1747 07:47:34.508172 [14]wdata: 0x88888888 - 0x88888888 rdata
1748 07:47:34.529089 [15]wdata: 0x88888888 - 0x88888888 rdata
1749 07:47:34.529353 [16]wdata: 0x44332211 - 0x44332211 rdata
1750 07:47:34.529577 [17]wdata: 0x88776655 - 0x88776655 rdata
1751 07:47:34.529827 //----------------------------------
1752 07:47:34.530090 **********************************************************************
1753 07:47:34.550570 Socket[0] Channel[3] DDR Init Finished!
1754 07:47:34.550845 **********************************************************************
1755 07:47:34.551090 **********************************************************************
1756 07:47:34.551341 Socket[1] Channel[0] Base:[0x40060340000] Speed:[2400]
1757 07:47:34.573617 **********************************************************************
1758 07:47:34.573892 ==========================
1759 07:47:34.574148 config parameters from SPD
1760 07:47:34.574387 ==========================
1761 07:47:34.574656 DDR PHY PLL config.....................................OK!
1762 07:47:34.574902 Top module cfg.........................................OK
1763 07:47:34.595785 ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1764 07:47:34.596069 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2
1765 07:47:34.596328 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1
1766 07:47:34.596573 Dmc init static........................................OK
1767 07:47:34.610573 Phy init dynamic.......................................OK
1768 07:47:34.610850
1769 07:47:34.611093 [software pad_cal_0]: pvtr=0x1F; pvtn=0x19; pvtp=0xB
1770 07:47:34.611332 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1771 07:47:34.671754 dimm[0] rcd init finished!
1772 07:47:34.671997 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1773 07:47:34.672233 rank[0] sdram init finished!
1774 07:47:34.672448 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1775 07:47:34.672660 rank[1] sdram init finished!
1776 07:47:34.672871 -----------------------------------------------------
1777 07:47:34.701592 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1778 07:47:34.701852 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1779 07:47:34.702076 -----------------------------------------------------
1780 07:47:34.702296 Dram init..............................................OK
1781 07:47:34.702531 socket[1] channel[0] rank[0] Phy gate leveling.....OK
1782 07:47:34.720353 socket[1] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1783 07:47:34.720614 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1784 07:47:34.720843 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1785 07:47:34.778587 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1786 07:47:34.778832 OK
1787 07:47:34.779057 socket[1] channel[0] rank[0] Phy write leveling.....OK
1788 07:47:34.779320 socket[1] channel[0] rank[1] Phy write leveling.....OK
1789 07:47:34.801546 socket[1] channel[0] rank[0] Phy write leveling 2...OK
1790 07:47:34.801785 socket[1] channel[0] rank[1] Phy write leveling 2...OK
1791 07:47:34.802001 socket[1] channel[0] rank[0] Read data eye training start:
1792 07:47:34.897545 socket[1] channel[0] rank[0] Read data eye training end
1793 07:47:34.897822
1794 07:47:34.898077 socket[1] channel[0] rank[1] Read data eye training start:
1795 07:47:34.920870 socket[1] channel[0] rank[1] Read data eye training end
1796 07:47:34.921135
1797 07:47:34.921390 socket[1] channel[0] rank[0] Write data eye training start:
1798 07:47:35.013162 socket[1] channel[0] rank[0] Write data eye training end
1799 07:47:35.013408
1800 07:47:35.013630 socket[1] channel[0] rank[1] Write data eye training start:
1801 07:47:35.088507 socket[1] channel[0] rank[1] Write data eye training end
1802 07:47:35.088773
1803 07:47:35.088995 socket[1] channel[0] Rx vref training start
1804 07:47:35.410608 socket[1] channel[0] Rx vref training end
1805 07:47:35.411012
1806 07:47:35.411236 socket[1] channel[0] rank[0] Read data eye training start:
1807 07:47:35.470472 socket[1] channel[0] rank[0] Read data eye training end
1808 07:47:35.470767
1809 07:47:35.470986 socket[1] channel[0] rank[1] Read data eye training start:
1810 07:47:35.541733 socket[1] channel[0] rank[1] Read data eye training end
1811 07:47:35.542017
1812 07:47:35.542264 socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start:
1813 07:47:35.542504 socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end
1814 07:47:35.543017
1815 07:47:35.580802 socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start:
1816 07:47:35.581096 socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end
1817 07:47:35.581366
1818 07:47:35.581646 socket[1] channel[0] Tx vref training start
1819 07:47:37.391432 socket[1] channel[0] Tx vref training end
1820 07:47:37.391893
1821 07:47:37.392145 socket[1] channel[0] rank[0] Write data eye training start:
1822 07:47:37.420369 socket[1] channel[0] rank[0] Write data eye training end
1823 07:47:37.420849
1824 07:47:37.421121 socket[1] channel[0] rank[1] Write data eye training start:
1825 07:47:37.480341 socket[1] channel[0] rank[1] Write data eye training end
1826 07:47:37.480693
1827 07:47:37.480958 //----------------------------------
1828 07:47:37.481222 sfc test rank0
1829 07:47:37.503154 [0]wdata: 0x11111111 - 0x11111111 rdata
1830 07:47:37.504143 [1]wdata: 0x11111111 - 0x11111111 rdata
1831 07:47:37.504419 [2]wdata: 0x22222222 - 0x22222222 rdata
1832 07:47:37.504626 [3]wdata: 0x22222222 - 0x22222222 rdata
1833 07:47:37.504834 [4]wdata: 0x33333333 - 0x33333333 rdata
1834 07:47:37.505040 [5]wdata: 0x33333333 - 0x33333333 rdata
1835 07:47:37.524352 [6]wdata: 0x44444444 - 0x44444444 rdata
1836 07:47:37.524618 [7]wdata: 0x44444444 - 0x44444444 rdata
1837 07:47:37.524859 [8]wdata: 0x55555555 - 0x55555555 rdata
1838 07:47:37.525106 [9]wdata: 0x55555555 - 0x55555555 rdata
1839 07:47:37.525360 [10]wdata: 0x66666666 - 0x66666666 rdata
1840 07:47:37.525574 [11]wdata: 0x66666666 - 0x66666666 rdata
1841 07:47:37.589060 [12]wdata: 0x77777777 - 0x77777777 rdata
1842 07:47:37.589333 [13]wdata: 0x77777777 - 0x77777777 rdata
1843 07:47:37.589556 [14]wdata: 0x88888888 - 0x88888888 rdata
1844 07:47:37.589774 [15]wdata: 0x88888888 - 0x88888888 rdata
1845 07:47:37.589986 [16]wdata: 0x44332211 - 0x44332211 rdata
1846 07:47:37.590195 [17]wdata: 0x88776655 - 0x88776655 rdata
1847 07:47:37.590433 sfc test rank1
1848 07:47:37.600732 [0]wdata: 0x11111111 - 0x11111111 rdata
1849 07:47:37.600999 [1]wdata: 0x11111111 - 0x11111111 rdata
1850 07:47:37.601224 [2]wdata: 0x22222222 - 0x22222222 rdata
1851 07:47:37.601450 [3]wdata: 0x22222222 - 0x22222222 rdata
1852 07:47:37.601687 [4]wdata: 0x33333333 - 0x33333333 rdata
1853 07:47:37.601912 [5]wdata: 0x33333333 - 0x33333333 rdata
1854 07:47:37.610989 [6]wdata: 0x44444444 - 0x44444444 rdata
1855 07:47:37.611247 [7]wdata: 0x44444444 - 0x44444444 rdata
1856 07:47:37.611497 [8]wdata: 0x55555555 - 0x55555555 rdata
1857 07:47:37.611733 [9]wdata: 0x55555555 - 0x55555555 rdata
1858 07:47:37.611965 [10]wdata: 0x66666666 - 0x66666666 rdata
1859 07:47:37.612204 [11]wdata: 0x66666666 - 0x66666666 rdata
1860 07:47:37.620513 [12]wdata: 0x77777777 - 0x77777777 rdata
1861 07:47:37.620777 [13]wdata: 0x77777777 - 0x77777777 rdata
1862 07:47:37.621027 [14]wdata: 0x88888888 - 0x88888888 rdata
1863 07:47:37.621266 [15]wdata: 0x88888888 - 0x88888888 rdata
1864 07:47:37.621503 [16]wdata: 0x44332211 - 0x44332211 rdata
1865 07:47:37.621745 [17]wdata: 0x88776655 - 0x88776655 rdata
1866 07:47:37.633800 //----------------------------------
1867 07:47:37.634070 **********************************************************************
1868 07:47:37.634316 Socket[1] Channel[0] DDR Init Finished!
1869 07:47:37.634523 **********************************************************************
1870 07:47:37.656580 **********************************************************************
1871 07:47:37.656849 Socket[1] Channel[1] Base:[0x40060350000] Speed:[2400]
1872 07:47:37.657094 **********************************************************************
1873 07:47:37.657335 ==========================
1874 07:47:37.657587 config parameters from SPD
1875 07:47:37.657821 ==========================
1876 07:47:37.678464 DDR PHY PLL config.....................................OK!
1877 07:47:37.678725 Top module cfg.........................................OK
1878 07:47:37.678944 ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1879 07:47:37.679177 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2
1880 07:47:37.690716 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1
1881 07:47:37.690976 Dmc init static........................................OK
1882 07:47:37.691188 Phy init dynamic.......................................OK
1883 07:47:37.691391
1884 07:47:37.691590 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC
1885 07:47:37.713769 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
1886 07:47:37.714003 dimm[0] rcd init finished!
1887 07:47:37.714219 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1888 07:47:37.714431 rank[0] sdram init finished!
1889 07:47:37.735827 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
1890 07:47:37.736065 rank[1] sdram init finished!
1891 07:47:37.736316 -----------------------------------------------------
1892 07:47:37.736525 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
1893 07:47:37.736725 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
1894 07:47:37.807949 -----------------------------------------------------
1895 07:47:37.808335 Dram init..............................................OK
1896 07:47:37.808616 socket[1] channel[1] rank[0] Phy gate leveling.....OK
1897 07:47:37.808864 socket[1] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
1898 07:47:37.840530 lat_adj_start of rank 1 byte 1 is set to 0x00000001
1899 07:47:37.840797 lat_adj_start of rank 1 byte 6 is set to 0x00000001
1900 07:47:37.841040 lat_adj_start of rank 1 byte 7 is set to 0x00000001
1901 07:47:37.877521 OK
1902 07:47:37.877793 socket[1] channel[1] rank[0] Phy write leveling.....OK
1903 07:47:37.878035 socket[1] channel[1] rank[1] Phy write leveling.....OK
1904 07:47:37.901816 socket[1] channel[1] rank[0] Phy write leveling 2...OK
1905 07:47:37.902080 socket[1] channel[1] rank[1] Phy write leveling 2...OK
1906 07:47:37.902269 socket[1] channel[1] rank[0] Read data eye training start:
1907 07:47:37.950384 socket[1] channel[1] rank[0] Read data eye training end
1908 07:47:37.950735
1909 07:47:37.951008 socket[1] channel[1] rank[1] Read data eye training start:
1910 07:47:38.031216 socket[1] channel[1] rank[1] Read data eye training end
1911 07:47:38.031575
1912 07:47:38.031822 socket[1] channel[1] rank[0] Write data eye training start:
1913 07:47:38.081088 socket[1] channel[1] rank[0] Write data eye training end
1914 07:47:38.081399
1915 07:47:38.081627 socket[1] channel[1] rank[1] Write data eye training start:
1916 07:47:38.150525 socket[1] channel[1] rank[1] Write data eye training end
1917 07:47:38.150830
1918 07:47:38.151052 socket[1] channel[1] Rx vref training start
1919 07:47:38.522409 socket[1] channel[1] Rx vref training end
1920 07:47:38.522806
1921 07:47:38.523030 socket[1] channel[1] rank[0] Read data eye training start:
1922 07:47:38.570874 socket[1] channel[1] rank[0] Read data eye training end
1923 07:47:38.571187
1924 07:47:38.571432 socket[1] channel[1] rank[1] Read data eye training start:
1925 07:47:38.634121 socket[1] channel[1] rank[1] Read data eye training end
1926 07:47:38.634442
1927 07:47:38.634689 socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start:
1928 07:47:38.634907 socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end
1929 07:47:38.635156
1930 07:47:38.660525 socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start:
1931 07:47:38.660807 socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end
1932 07:47:38.661026
1933 07:47:38.661239 socket[1] channel[1] Tx vref training start
1934 07:47:40.233692 socket[1] channel[1] Tx vref training end
1935 07:47:40.234046
1936 07:47:40.234241 socket[1] channel[1] rank[0] Write data eye training start:
1937 07:47:40.355673 socket[1] channel[1] rank[0] Write data eye training end
1938 07:47:40.356020
1939 07:47:40.356278 socket[1] channel[1] rank[1] Write data eye training start:
1940 07:47:40.356511 socket[1] channel[1] rank[1] Write data eye training end
1941 07:47:40.356739
1942 07:47:40.356999 //----------------------------------
1943 07:47:40.357214 sfc test rank0
1944 07:47:40.370533 [0]wdata: 0x11111111 - 0x11111111 rdata
1945 07:47:40.370818 [1]wdata: 0x11111111 - 0x11111111 rdata
1946 07:47:40.371033 [2]wdata: 0x22222222 - 0x22222222 rdata
1947 07:47:40.371218 [3]wdata: 0x22222222 - 0x22222222 rdata
1948 07:47:40.371434 [4]wdata: 0x33333333 - 0x33333333 rdata
1949 07:47:40.371654 [5]wdata: 0x33333333 - 0x33333333 rdata
1950 07:47:40.392704 [6]wdata: 0x44444444 - 0x44444444 rdata
1951 07:47:40.392931 [7]wdata: 0x44444444 - 0x44444444 rdata
1952 07:47:40.393120 [8]wdata: 0x55555555 - 0x55555555 rdata
1953 07:47:40.393334 [9]wdata: 0x55555555 - 0x55555555 rdata
1954 07:47:40.393559 [10]wdata: 0x66666666 - 0x66666666 rdata
1955 07:47:40.393770 [11]wdata: 0x66666666 - 0x66666666 rdata
1956 07:47:40.413048 [12]wdata: 0x77777777 - 0x77777777 rdata
1957 07:47:40.413313 [13]wdata: 0x77777777 - 0x77777777 rdata
1958 07:47:40.413531 [14]wdata: 0x88888888 - 0x88888888 rdata
1959 07:47:40.413755 [15]wdata: 0x88888888 - 0x88888888 rdata
1960 07:47:40.413966 [16]wdata: 0x44332211 - 0x44332211 rdata
1961 07:47:40.414187 [17]wdata: 0x88776655 - 0x88776655 rdata
1962 07:47:40.414395 sfc test rank1
1963 07:47:40.434921 [0]wdata: 0x11111111 - 0x11111111 rdata
1964 07:47:40.435248 [1]wdata: 0x11111111 - 0x11111111 rdata
1965 07:47:40.435441 [2]wdata: 0x22222222 - 0x22222222 rdata
1966 07:47:40.435656 [3]wdata: 0x22222222 - 0x22222222 rdata
1967 07:47:40.435877 [4]wdata: 0x33333333 - 0x33333333 rdata
1968 07:47:40.436090 [5]wdata: 0x33333333 - 0x33333333 rdata
1969 07:47:40.457261 [6]wdata: 0x44444444 - 0x44444444 rdata
1970 07:47:40.457489 [7]wdata: 0x44444444 - 0x44444444 rdata
1971 07:47:40.457679 [8]wdata: 0x55555555 - 0x55555555 rdata
1972 07:47:40.457860 [9]wdata: 0x55555555 - 0x55555555 rdata
1973 07:47:40.458038 [10]wdata: 0x66666666 - 0x66666666 rdata
1974 07:47:40.458213 [11]wdata: 0x66666666 - 0x66666666 rdata
1975 07:47:40.478747 [12]wdata: 0x77777777 - 0x77777777 rdata
1976 07:47:40.478979 [13]wdata: 0x77777777 - 0x77777777 rdata
1977 07:47:40.479168 [14]wdata: 0x88888888 - 0x88888888 rdata
1978 07:47:40.479350 [15]wdata: 0x88888888 - 0x88888888 rdata
1979 07:47:40.479527 [16]wdata: 0x44332211 - 0x44332211 rdata
1980 07:47:40.479703 [17]wdata: 0x88776655 - 0x88776655 rdata
1981 07:47:40.500481 //----------------------------------
1982 07:47:40.500710 **********************************************************************
1983 07:47:40.500904 Socket[1] Channel[1] DDR Init Finished!
1984 07:47:40.501087 **********************************************************************
1985 07:47:40.521887 **********************************************************************
1986 07:47:40.522120 Socket[1] Channel[2] Base:[0x40040340000] Speed:[2400]
1987 07:47:40.522317 **********************************************************************
1988 07:47:40.522501 ==========================
1989 07:47:40.522720 config parameters from SPD
1990 07:47:40.522896 ==========================
1991 07:47:40.545382 DDR PHY PLL config.....................................OK!
1992 07:47:40.545614 Top module cfg.........................................OK
1993 07:47:40.545806 ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
1994 07:47:40.545989 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2
1995 07:47:40.560488 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1
1996 07:47:40.560716 Dmc init static........................................OK
1997 07:47:40.560905 Phy init dynamic.......................................OK
1998 07:47:40.561088
1999 07:47:40.561268 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1C; pvtp=0xC
2000 07:47:40.582122 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
2001 07:47:40.582378 dimm[0] rcd init finished!
2002 07:47:40.582725 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2003 07:47:40.582956 rank[0] sdram init finished!
2004 07:47:40.602844 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2005 07:47:40.603106 rank[1] sdram init finished!
2006 07:47:40.603321 -----------------------------------------------------
2007 07:47:40.603530 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
2008 07:47:40.603714 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
2009 07:47:40.630365 -----------------------------------------------------
2010 07:47:40.630706 Dram init..............................................OK
2011 07:47:40.685516 socket[1] channel[2] rank[0] Phy gate leveling.....OK
2012 07:47:40.685847 socket[1] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
2013 07:47:40.701996 lat_adj_start of rank 1 byte 1 is set to 0x00000001
2014 07:47:40.702245 lat_adj_start of rank 1 byte 2 is set to 0x00000001
2015 07:47:40.702457 lat_adj_start of rank 1 byte 3 is set to 0x00000001
2016 07:47:40.702715 lat_adj_start of rank 1 byte 4 is set to 0x00000001
2017 07:47:40.702901 lat_adj_start of rank 1 byte 5 is set to 0x00000001
2018 07:47:40.720429 lat_adj_start of rank 1 byte 6 is set to 0x00000001
2019 07:47:40.720690 lat_adj_start of rank 1 byte 7 is set to 0x00000001
2020 07:47:40.755862 OK
2021 07:47:40.756096 socket[1] channel[2] rank[0] Phy write leveling.....OK
2022 07:47:40.756304 socket[1] channel[2] rank[1] Phy write leveling.....OK
2023 07:47:40.780393 socket[1] channel[2] rank[0] Phy write leveling 2...OK
2024 07:47:40.780622 socket[1] channel[2] rank[1] Phy write leveling 2...OK
2025 07:47:40.780812 socket[1] channel[2] rank[0] Read data eye training start:
2026 07:47:40.832115 socket[1] channel[2] rank[0] Read data eye training end
2027 07:47:40.832385
2028 07:47:40.832575 socket[1] channel[2] rank[1] Read data eye training start:
2029 07:47:40.901093 socket[1] channel[2] rank[1] Read data eye training end
2030 07:47:40.901391
2031 07:47:40.901624 socket[1] channel[2] rank[0] Write data eye training start:
2032 07:47:40.980456 socket[1] channel[2] rank[0] Write data eye training end
2033 07:47:40.980776
2034 07:47:40.980999 socket[1] channel[2] rank[1] Write data eye training start:
2035 07:47:41.021188 socket[1] channel[2] rank[1] Write data eye training end
2036 07:47:41.021441
2037 07:47:41.021634 socket[1] channel[2] Rx vref training start
2038 07:47:41.390682 socket[1] channel[2] Rx vref training end
2039 07:47:41.391014
2040 07:47:41.391204 socket[1] channel[2] rank[0] Read data eye training start:
2041 07:47:41.442909 socket[1] channel[2] rank[0] Read data eye training end
2042 07:47:41.443197
2043 07:47:41.443417 socket[1] channel[2] rank[1] Read data eye training start:
2044 07:47:41.501654 socket[1] channel[2] rank[1] Read data eye training end
2045 07:47:41.501939
2046 07:47:41.502166 socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start:
2047 07:47:41.530452 socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end
2048 07:47:41.530767
2049 07:47:41.530989 socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start:
2050 07:47:41.531199 socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end
2051 07:47:41.531416
2052 07:47:41.531617 socket[1] channel[2] Tx vref training start
2053 07:47:42.990833 socket[1] channel[2] Tx vref training end
2054 07:47:42.991161
2055 07:47:42.991350 socket[1] channel[2] rank[0] Write data eye training start:
2056 07:47:43.071521 socket[1] channel[2] rank[0] Write data eye training end
2057 07:47:43.071870
2058 07:47:43.072061 socket[1] channel[2] rank[1] Write data eye training start:
2059 07:47:43.121798 socket[1] channel[2] rank[1] Write data eye training end
2060 07:47:43.122138
2061 07:47:43.122350 //----------------------------------
2062 07:47:43.122536 sfc test rank0
2063 07:47:43.145683 [0]wdata: 0x11111111 - 0x11111111 rdata
2064 07:47:43.145981 [1]wdata: 0x11111111 - 0x11111111 rdata
2065 07:47:43.146203 [2]wdata: 0x22222222 - 0x22222222 rdata
2066 07:47:43.146430 [3]wdata: 0x22222222 - 0x22222222 rdata
2067 07:47:43.146673 [4]wdata: 0x33333333 - 0x33333333 rdata
2068 07:47:43.146893 [5]wdata: 0x33333333 - 0x33333333 rdata
2069 07:47:43.167574 [6]wdata: 0x44444444 - 0x44444444 rdata
2070 07:47:43.167896 [7]wdata: 0x44444444 - 0x44444444 rdata
2071 07:47:43.168129 [8]wdata: 0x55555555 - 0x55555555 rdata
2072 07:47:43.168364 [9]wdata: 0x55555555 - 0x55555555 rdata
2073 07:47:43.168577 [10]wdata: 0x66666666 - 0x66666666 rdata
2074 07:47:43.168791 [11]wdata: 0x66666666 - 0x66666666 rdata
2075 07:47:43.189384 [12]wdata: 0x77777777 - 0x77777777 rdata
2076 07:47:43.189669 [13]wdata: 0x77777777 - 0x77777777 rdata
2077 07:47:43.189867 [14]wdata: 0x88888888 - 0x88888888 rdata
2078 07:47:43.190154 [15]wdata: 0x88888888 - 0x88888888 rdata
2079 07:47:43.190394 [16]wdata: 0x44332211 - 0x44332211 rdata
2080 07:47:43.190650 [17]wdata: 0x88776655 - 0x88776655 rdata
2081 07:47:43.190875 sfc test rank1
2082 07:47:43.211850 [0]wdata: 0x11111111 - 0x11111111 rdata
2083 07:47:43.212129 [1]wdata: 0x11111111 - 0x11111111 rdata
2084 07:47:43.212367 [2]wdata: 0x22222222 - 0x22222222 rdata
2085 07:47:43.212594 [3]wdata: 0x22222222 - 0x22222222 rdata
2086 07:47:43.212806 [4]wdata: 0x33333333 - 0x33333333 rdata
2087 07:47:43.213028 [5]wdata: 0x33333333 - 0x33333333 rdata
2088 07:47:43.232711 [6]wdata: 0x44444444 - 0x44444444 rdata
2089 07:47:43.233003 [7]wdata: 0x44444444 - 0x44444444 rdata
2090 07:47:43.233196 [8]wdata: 0x55555555 - 0x55555555 rdata
2091 07:47:43.233414 [9]wdata: 0x55555555 - 0x55555555 rdata
2092 07:47:43.233620 [10]wdata: 0x66666666 - 0x66666666 rdata
2093 07:47:43.233801 [11]wdata: 0x66666666 - 0x66666666 rdata
2094 07:47:43.252991 [12]wdata: 0x77777777 - 0x77777777 rdata
2095 07:47:43.253220 [13]wdata: 0x77777777 - 0x77777777 rdata
2096 07:47:43.253411 [14]wdata: 0x88888888 - 0x88888888 rdata
2097 07:47:43.253596 [15]wdata: 0x88888888 - 0x88888888 rdata
2098 07:47:43.253778 [16]wdata: 0x44332211 - 0x44332211 rdata
2099 07:47:43.253958 [17]wdata: 0x88776655 - 0x88776655 rdata
2100 07:47:43.276985 //----------------------------------
2101 07:47:43.277217 **********************************************************************
2102 07:47:43.277410 Socket[1] Channel[2] DDR Init Finished!
2103 07:47:43.277595 **********************************************************************
2104 07:47:43.301685 **********************************************************************
2105 07:47:43.301914 Socket[1] Channel[3] Base:[0x40040350000] Speed:[2400]
2106 07:47:43.302106 **********************************************************************
2107 07:47:43.302291 ==========================
2108 07:47:43.302472 config parameters from SPD
2109 07:47:43.302942 ==========================
2110 07:47:43.322482 DDR PHY PLL config.....................................OK!
2111 07:47:43.322785 Top module cfg.........................................OK
2112 07:47:43.323000 ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8
2113 07:47:43.323187 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2
2114 07:47:43.334986 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1
2115 07:47:43.335291 Dmc init static........................................OK
2116 07:47:43.353740 Phy init dynamic.......................................OK
2117 07:47:43.354006
2118 07:47:43.354195 [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC
2119 07:47:43.354381 [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD
2120 07:47:43.368033 dimm[0] rcd init finished!
2121 07:47:43.368277 rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2122 07:47:43.368468 rank[0] sdram init finished!
2123 07:47:43.368651 rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4;
2124 07:47:43.368831 rank[1] sdram init finished!
2125 07:47:43.369007 -----------------------------------------------------
2126 07:47:43.390824 Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6
2127 07:47:43.391065 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810
2128 07:47:43.391257 -----------------------------------------------------
2129 07:47:43.391447 Dram init..............................................OK
2130 07:47:43.450529 socket[1] channel[3] rank[0] Phy gate leveling.....OK
2131 07:47:43.450850 socket[1] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001
2132 07:47:43.470526 lat_adj_start of rank 1 byte 1 is set to 0x00000001
2133 07:47:43.470871 lat_adj_start of rank 1 byte 2 is set to 0x00000001
2134 07:47:43.471092 lat_adj_start of rank 1 byte 3 is set to 0x00000001
2135 07:47:43.471308 lat_adj_start of rank 1 byte 4 is set to 0x00000001
2136 07:47:43.471497 lat_adj_start of rank 1 byte 5 is set to 0x00000001
2137 07:47:43.490470 lat_adj_start of rank 1 byte 6 is set to 0x00000001
2138 07:47:43.490756 lat_adj_start of rank 1 byte 7 is set to 0x00000001
2139 07:47:43.541712 OK
2140 07:47:43.541989 socket[1] channel[3] rank[0] Phy write leveling.....OK
2141 07:47:43.542214 socket[1] channel[3] rank[1] Phy write leveling.....OK
2142 07:47:43.542402 socket[1] channel[3] rank[0] Phy write leveling 2...OK
2143 07:47:43.542684 socket[1] channel[3] rank[1] Phy write leveling 2...OK
2144 07:47:43.561313 socket[1] channel[3] rank[0] Read data eye training start:
2145 07:47:43.610660 socket[1] channel[3] rank[0] Read data eye training end
2146 07:47:43.610904
2147 07:47:43.611093 socket[1] channel[3] rank[1] Read data eye training start:
2148 07:47:43.720516 socket[1] channel[3] rank[1] Read data eye training end
2149 07:47:43.720911
2150 07:47:43.721126 socket[1] channel[3] rank[0] Write data eye training start:
2151 07:47:43.741674 socket[1] channel[3] rank[0] Write data eye training end
2152 07:47:43.741931
2153 07:47:43.742165 socket[1] channel[3] rank[1] Write data eye training start:
2154 07:47:43.821904 socket[1] channel[3] rank[1] Write data eye training end
2155 07:47:43.822244
2156 07:47:43.822457 socket[1] channel[3] Rx vref training start
2157 07:47:44.177034 socket[1] channel[3] Rx vref training end
2158 07:47:44.177360
2159 07:47:44.177550 socket[1] channel[3] rank[0] Read data eye training start:
2160 07:47:44.221926 socket[1] channel[3] rank[0] Read data eye training end
2161 07:47:44.222199
2162 07:47:44.222416 socket[1] channel[3] rank[1] Read data eye training start:
2163 07:47:44.290793 socket[1] channel[3] rank[1] Read data eye training end
2164 07:47:44.291058
2165 07:47:44.291248 socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start:
2166 07:47:44.291433 socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end
2167 07:47:44.291625
2168 07:47:44.310597 socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start:
2169 07:47:44.310881 socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end
2170 07:47:44.311077
2171 07:47:44.311290 socket[1] channel[3] Tx vref training start
2172 07:47:46.050443 socket[1] channel[3] Tx vref training end
2173 07:47:46.054526
2174 07:47:46.054752 socket[1] channel[3] rank[0] Write data eye training start:
2175 07:47:46.120348 socket[1] channel[3] rank[0] Write data eye training end
2176 07:47:46.120891
2177 07:47:46.121092 socket[1] channel[3] rank[1] Write data eye training start:
2178 07:47:46.193259 socket[1] channel[3] rank[1] Write data eye training end
2179 07:47:46.193524
2180 07:47:46.193715 //----------------------------------
2181 07:47:46.193898 sfc test rank0
2182 07:47:46.194078 [0]wdata: 0x11111111 - 0x11111111 rdata
2183 07:47:46.194256 [1]wdata: 0x11111111 - 0x11111111 rdata
2184 07:47:46.194432 [2]wdata: 0x22222222 - 0x22222222 rdata
2185 07:47:46.211171 [3]wdata: 0x22222222 - 0x22222222 rdata
2186 07:47:46.211396 [4]wdata: 0x33333333 - 0x33333333 rdata
2187 07:47:46.211586 [5]wdata: 0x33333333 - 0x33333333 rdata
2188 07:47:46.211769 [6]wdata: 0x44444444 - 0x44444444 rdata
2189 07:47:46.211950 [7]wdata: 0x44444444 - 0x44444444 rdata
2190 07:47:46.212127 [8]wdata: 0x55555555 - 0x55555555 rdata
2191 07:47:46.230663 [9]wdata: 0x55555555 - 0x55555555 rdata
2192 07:47:46.230889 [10]wdata: 0x66666666 - 0x66666666 rdata
2193 07:47:46.231080 [11]wdata: 0x66666666 - 0x66666666 rdata
2194 07:47:46.231264 [12]wdata: 0x77777777 - 0x77777777 rdata
2195 07:47:46.231443 [13]wdata: 0x77777777 - 0x77777777 rdata
2196 07:47:46.231621 [14]wdata: 0x88888888 - 0x88888888 rdata
2197 07:47:46.252488 [15]wdata: 0x88888888 - 0x88888888 rdata
2198 07:47:46.252745 [16]wdata: 0x44332211 - 0x44332211 rdata
2199 07:47:46.252977 [17]wdata: 0x88776655 - 0x88776655 rdata
2200 07:47:46.253200 sfc test rank1
2201 07:47:46.253414 [0]wdata: 0x11111111 - 0x11111111 rdata
2202 07:47:46.253620 [1]wdata: 0x11111111 - 0x11111111 rdata
2203 07:47:46.253831 [2]wdata: 0x22222222 - 0x22222222 rdata
2204 07:47:46.277552 [3]wdata: 0x22222222 - 0x22222222 rdata
2205 07:47:46.277804 [4]wdata: 0x33333333 - 0x33333333 rdata
2206 07:47:46.278017 [5]wdata: 0x33333333 - 0x33333333 rdata
2207 07:47:46.278236 [6]wdata: 0x44444444 - 0x44444444 rdata
2208 07:47:46.278421 [7]wdata: 0x44444444 - 0x44444444 rdata
2209 07:47:46.278663 [8]wdata: 0x55555555 - 0x55555555 rdata
2210 07:47:46.299423 [9]wdata: 0x55555555 - 0x55555555 rdata
2211 07:47:46.299675 [10]wdata: 0x66666666 - 0x66666666 rdata
2212 07:47:46.299938 [11]wdata: 0x66666666 - 0x66666666 rdata
2213 07:47:46.300152 [12]wdata: 0x77777777 - 0x77777777 rdata
2214 07:47:46.300375 [13]wdata: 0x77777777 - 0x77777777 rdata
2215 07:47:46.300559 [14]wdata: 0x88888888 - 0x88888888 rdata
2216 07:47:46.320782 [15]wdata: 0x88888888 - 0x88888888 rdata
2217 07:47:46.321031 [16]wdata: 0x44332211 - 0x44332211 rdata
2218 07:47:46.321252 [17]wdata: 0x88776655 - 0x88776655 rdata
2219 07:47:46.321474 //----------------------------------
2220 07:47:46.321681 **********************************************************************
2221 07:47:46.385841 Socket[1] Channel[3] DDR Init Finished!
2222 07:47:46.386141 **********************************************************************
2223 07:47:46.386338 ========================================================================================
2224 07:47:46.400555 | socekt 0 |
2225 07:47:46.400784 ========================================================================================
2226 07:47:46.400976 | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
2227 07:47:46.411504 ========================================================================================
2228 07:47:46.411734 | 0 | Samsung | Samsung | Samsung | Samsung |
2229 07:47:46.411926 | | Montage | Montage | Montage | Montage |
2230 07:47:46.420760 | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) |
2231 07:47:46.420987 | | 2400 | 2400 | 2400 | 2400 |
2232 07:47:46.421178 | | ww282017 | ww282017 | ww282017 | ww282017 |
2233 07:47:46.432362 | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC |
2234 07:47:46.432590 | | | | | |
2235 07:47:46.432782 ----------------------------------------------------------------------------------------
2236 07:47:46.451477 | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2237 07:47:46.451704 | | | | | |
2238 07:47:46.470656 | | | | | |
2239 07:47:46.470884 | | | | | |
2240 07:47:46.471076 | | | | | |
2241 07:47:46.496315 | | | | | |
2242 07:47:46.496581 | | | | | |
2243 07:47:46.496812 ----------------------------------------------------------------------------------------
2244 07:47:46.519304 | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2245 07:47:46.519563 | | | | | |
2246 07:47:46.519787 | | | | | |
2247 07:47:46.602796 | | | | | |
2248 07:47:46.603122 | | | | | |
2249 07:47:46.603316 | | | | | |
2250 07:47:46.610614 | | | | | |
2251 07:47:46.620343 ----------------------------------------------------------------------------------------
2252 07:47:46.620604 ========================================================================================
2253 07:47:46.620824 | socekt 1 |
2254 07:47:46.634478 ========================================================================================
2255 07:47:46.634789 | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 |
2256 07:47:46.635005 ========================================================================================
2257 07:47:46.640851 | 0 | Samsung | Samsung | Samsung | Samsung |
2258 07:47:46.641107 | | Montage | Montage | Montage | Montage |
2259 07:47:46.651908 | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) |
2260 07:47:46.652174 | | 2400 | 2400 | 2400 | 2400 |
2261 07:47:46.652416 | | ww282017 | ww282017 | ww282017 | ww282017 |
2262 07:47:46.662858 | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC |
2263 07:47:46.663110 | | | | | |
2264 07:47:46.663323 ----------------------------------------------------------------------------------------
2265 07:47:46.683157 | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2266 07:47:46.683385 | | | | | |
2267 07:47:46.683577 | | | | | |
2268 07:47:46.704137 | | | | | |
2269 07:47:46.704381 | | | | | |
2270 07:47:46.721462 | | | | | |
2271 07:47:46.721767 | | | | | |
2272 07:47:46.722046 ----------------------------------------------------------------------------------------
2273 07:47:46.747839 | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM |
2274 07:47:46.748109 | | | | | |
2275 07:47:46.748344 | | | | | |
2276 07:47:46.769777 | | | | | |
2277 07:47:46.770043 | | | | | |
2278 07:47:46.770303 | | | | | |
2279 07:47:46.790578 | | | | | |
2280 07:47:46.790858 ----------------------------------------------------------------------------------------
2281 07:47:46.791077 socket[0] channel[0] rank[0] memory clean start.
2282 07:47:46.791290 socket[0] channel[1] rank[0] memory clean start.
2283 07:47:46.807038 socket[0] channel[2] rank[0] memory clean start.
2284 07:47:46.807266 socket[0] channel[3] rank[0] memory clean start.
2285 07:47:46.807500 socket[1] channel[0] rank[0] memory clean start.
2286 07:47:46.807689 socket[1] channel[1] rank[0] memory clean start.
2287 07:47:46.807872 socket[1] channel[2] rank[0] memory clean start.
2288 07:47:46.830650 socket[1] channel[3] rank[0] memory clean start.
2289 07:47:47.855596 all rank[0] memory clean ok!
2290 07:47:47.855933
2291 07:47:47.856122 socket[0] channel[0] rank[0] memory clean read start.
2292 07:47:47.856328 socket[0] channel[1] rank[0] memory clean read start.
2293 07:47:47.856509 socket[0] channel[2] rank[0] memory clean read start.
2294 07:47:47.856687 socket[0] channel[3] rank[0] memory clean read start.
2295 07:47:47.882010 socket[1] channel[0] rank[0] memory clean read start.
2296 07:47:47.882279 socket[1] channel[1] rank[0] memory clean read start.
2297 07:47:47.882496 socket[1] channel[2] rank[0] memory clean read start.
2298 07:47:47.882720 socket[1] channel[3] rank[0] memory clean read start.
2299 07:47:48.909087 all rank[0] memory clean read ok!
2300 07:47:48.909506
2301 07:47:48.909725 socket[0] channel[0] rank[1] memory clean start.
2302 07:47:48.909944 socket[0] channel[1] rank[1] memory clean start.
2303 07:47:48.910130 socket[0] channel[2] rank[1] memory clean start.
2304 07:47:48.910342 socket[0] channel[3] rank[1] memory clean start.
2305 07:47:48.940313 socket[1] channel[0] rank[1] memory clean start.
2306 07:47:48.940543 socket[1] channel[1] rank[1] memory clean start.
2307 07:47:48.940734 socket[1] channel[2] rank[1] memory clean start.
2308 07:47:48.940917 socket[1] channel[3] rank[1] memory clean start.
2309 07:47:49.967488 all rank[1] memory clean ok!
2310 07:47:49.967846
2311 07:47:49.968037 socket[0] channel[0] rank[1] memory clean read start.
2312 07:47:49.968239 socket[0] channel[1] rank[1] memory clean read start.
2313 07:47:49.968424 socket[0] channel[2] rank[1] memory clean read start.
2314 07:47:49.968603 socket[0] channel[3] rank[1] memory clean read start.
2315 07:47:49.993237 socket[1] channel[0] rank[1] memory clean read start.
2316 07:47:49.993465 socket[1] channel[1] rank[1] memory clean read start.
2317 07:47:49.993655 socket[1] channel[2] rank[1] memory clean read start.
2318 07:47:49.993840 socket[1] channel[3] rank[1] memory clean read start.
2319 07:47:51.044899 all rank[1] memory clean read ok!
2320 07:47:51.045537
2321 07:47:51.060655 RAM Diagnose or not ?
2322 07:47:51.060881 (Press 'Ctrl+t' or 'Ctrl+T' to Begin Memory Diagnose)
2323 07:47:51.061071 Now wait for 3 seconds...
2324 07:47:51.061257 Not Press 'Ctrl+t' or 'Ctrl+T', The RAM Diagnose Exit
2325 07:47:51.061439 Start config DAW.
2326 07:47:51.061617 Record Interrupts
2327 07:47:51.073483 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC0] = 0xB0111168
2328 07:47:51.073714 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC1] = 0xA0311168
2329 07:47:51.073904 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC0] = 0x10201041
2330 07:47:51.074089 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC1] = 0x80301164
2331 07:47:51.091488 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC0] = 0x16223
2332 07:47:51.091726 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC1] = 0x403103
2333 07:47:51.091918 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC0] = 0x613010
2334 07:47:51.092103 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC1] = 0xB07132
2335 07:47:51.112086 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT0] = 0x8A
2336 07:47:51.112326 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT0] = 0x10
2337 07:47:51.112517 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT0] = 0x220
2338 07:47:51.112701 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT0] = 0x709
2339 07:47:51.130344 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS4_INT0] = 0x40
2340 07:47:51.130616 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS5_INT0] = 0x48
2341 07:47:51.130811 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS6_INT0] = 0x4
2342 07:47:51.130998 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT1] = 0x8089
2343 07:47:51.147085 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT1] = 0x1980
2344 07:47:51.147333 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT1] = 0xA00C0
2345 07:47:51.147607 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT1] = 0x42AC0C
2346 07:47:51.147860 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS4_INT1] = 0x2
2347 07:47:51.236562 Interrupt Status:[SocketId: 0] [DieId: 1] [T] [T_CS0_INT0] = 0x6
2348 07:47:51.236858 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT0] = 0x36
2349 07:47:51.237051 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT0] = 0x38
2350 07:47:51.237239 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT0] = 0x10
2351 07:47:51.251503 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT0] = 0x2
2352 07:47:51.251730 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT0] = 0x40
2353 07:47:51.272287 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS0_INT1] = 0x1400
2354 07:47:51.272559 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT1] = 0x22C4
2355 07:47:51.272783 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT1] = 0xC044
2356 07:47:51.273001 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT1] = 0x80820
2357 07:47:51.297188 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT1] = 0x9008
2358 07:47:51.297445 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT1] = 0xF06
2359 07:47:51.297666 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS6_INT1] = 0x181
2360 07:47:51.297895 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT0] = 0x60
2361 07:47:51.310524 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT0] = 0xF4
2362 07:47:51.310785 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT0] = 0x74
2363 07:47:51.310979 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT1] = 0x3CBC
2364 07:47:51.311165 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT1] = 0x2010
2365 07:47:51.321064 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT1] = 0x41
2366 07:47:51.321292 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT0] = 0xAC
2367 07:47:51.321485 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT0] = 0x3B
2368 07:47:51.321670 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT0] = 0xF8
2369 07:47:51.330352 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT1] = 0xB144
2370 07:47:51.330599 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT1] = 0x346D
2371 07:47:51.330793 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT1] = 0xA8B1
2372 07:47:51.343058 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA0] = 0x88030
2373 07:47:51.343286 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA1] = 0x400
2374 07:47:51.343477 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA0] = 0x9131
2375 07:47:51.343664 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA1] = 0x80200
2376 07:47:51.360483 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC0] = 0x2A0
2377 07:47:51.360710 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC1] = 0xA81
2378 07:47:51.360902 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC3] = 0x20000
2379 07:47:51.361087 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC0] = 0x400
2380 07:47:51.421860 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC1] = 0x4020
2381 07:47:51.422156 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC2] = 0x10001
2382 07:47:51.422388 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC3] = 0x280
2383 07:47:51.422639 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER0] = 0x3
2384 07:47:51.440361 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER1] = 0x4
2385 07:47:51.440613 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER2] = 0x3
2386 07:47:51.440837 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER3] = 0x2
2387 07:47:51.441046 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_POE] = 0x7
2388 07:47:51.450770 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER2] = 0x4
2389 07:47:51.451031 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER3] = 0x2
2390 07:47:51.451255 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_POE] = 0x3
2391 07:47:51.451469 Interrupt Status:[SocketId: 0] [DieId: 0] [AA_SAS] = 0x1
2392 07:47:51.451688 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_ALG] = 0x3
2393 07:47:51.461862 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_PCIE] = 0x3
2394 07:47:51.462117 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_SAS] = 0x1
2395 07:47:51.462335 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_SRAM] = 0x8
2396 07:47:51.462581 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_SRAM] = 0xEB
2397 07:47:51.483137 Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC0] = 0x9111115C
2398 07:47:51.483459 Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC1] = 0xC1501000
2399 07:47:51.483694 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC0] = 0xC1001028
2400 07:47:51.483954 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC1] = 0xA0301050
2401 07:47:51.500592 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC0] = 0xA10321
2402 07:47:51.500853 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC1] = 0x207222
2403 07:47:51.501072 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC0] = 0x31A123
2404 07:47:51.501281 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC1] = 0x6110
2405 07:47:51.510443 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT0] = 0x60
2406 07:47:51.510700 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT0] = 0x20
2407 07:47:51.510892 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT0] = 0xA
2408 07:47:51.511078 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT0] = 0x412
2409 07:47:51.522442 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT0] = 0x12
2410 07:47:51.522698 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT1] = 0x764
2411 07:47:51.544460 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT1] = 0x305
2412 07:47:51.544729 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT1] = 0x524000
2413 07:47:51.544924 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT1] = 0x823068
2414 07:47:51.545138 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT1] = 0x201
2415 07:47:51.566194 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS5_INT1] = 0xB5E
2416 07:47:51.566450 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS6_INT1] = 0x1D55
2417 07:47:51.566713 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT0] = 0x2
2418 07:47:51.566937 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT0] = 0x800
2419 07:47:51.621526 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT0] = 0x84
2420 07:47:51.621773 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT0] = 0x20
2421 07:47:51.640415 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT0] = 0x8D
2422 07:47:51.640643 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT1] = 0x100
2423 07:47:51.640835 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS1_INT1] = 0x5C85
2424 07:47:51.641022 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT1] = 0x64A4C
2425 07:47:51.655704 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS3_INT1] = 0x58388
2426 07:47:51.655947 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT1] = 0x4180
2427 07:47:51.656138 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT1] = 0x882
2428 07:47:51.656344 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT1] = 0xB104
2429 07:47:51.670445 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT0] = 0x60
2430 07:47:51.670703 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT0] = 0x3C
2431 07:47:51.670949 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT0] = 0xC9
2432 07:47:51.671137 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT1] = 0x810
2433 07:47:51.685419 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT1] = 0x3063
2434 07:47:51.685675 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT1] = 0x400D
2435 07:47:51.685897 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT0] = 0x8
2436 07:47:51.686124 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT0] = 0xC
2437 07:47:51.702017 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT1] = 0xA074
2438 07:47:51.702282 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS1_INT1] = 0x4940
2439 07:47:51.702519 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT1] = 0x2D49
2440 07:47:51.720352 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA0] = 0xC019
2441 07:47:51.720606 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA1] = 0x8A041
2442 07:47:51.720835 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA0] = 0x20
2443 07:47:51.721050 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA1] = 0x48000
2444 07:47:51.735991 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC0] = 0x8200
2445 07:47:51.736273 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC3] = 0x20
2446 07:47:51.736494 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC0] = 0x5000
2447 07:47:51.736711 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC2] = 0x20
2448 07:47:51.758416 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_CLUSTER3] = 0x2
2449 07:47:51.758671 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_POE] = 0x6
2450 07:47:51.758865 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER1] = 0x2
2451 07:47:51.759086 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER3] = 0x1
2452 07:47:51.779576 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_POE] = 0x2
2453 07:47:51.779803 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_ALG] = 0x1
2454 07:47:51.779995 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_PCIE] = 0x2
2455 07:47:51.780179 Interrupt Status:[SocketId: 1] [DieId: 2] [AA_ALG] = 0x1
2456 07:47:51.802563 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_SRAM] = 0xFD
2457 07:47:51.802795 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_SRAM] = 0xFB
2458 07:47:51.802987 Clear Interrupts
2459 07:47:51.803173 Clear DDRC
2460 07:47:51.803354 Clear RASC
2461 07:47:51.803571 Clear CS
2462 07:47:51.803778 Clear SLLC
2463 07:47:51.803954 Clear HHA
2464 07:47:51.804161 Clear LLC
2465 07:47:51.804386 Clear AA
2466 07:47:51.804562 Clear SRAM
2467 07:47:51.804773 Clear DDRC
2468 07:47:51.804982 Clear RASC
2469 07:47:51.820577 Clear CS
2470 07:47:51.820858 Clear SLLC
2471 07:47:51.821054 Clear HHA
2472 07:47:51.821276 Clear LLC
2473 07:47:51.821486 Clear AA
2474 07:47:51.821706 Clear SRAM
2475 07:47:51.821907 Clear Interrupt End
2476 07:47:51.822112 Enable Channel Interleave for socket[0]
2477 07:47:51.822291 Enable Channel Interleave for socket[0]
2478 07:47:51.836039 Daw Cinfig :Skt 0 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0
2479 07:47:51.836283 ColBits = 0xA
2480 07:47:51.836475 RowBits = 0x11
2481 07:47:51.836660 Banknum = 0x10
2482 07:47:51.836841 RankSize = 0x400000000
2483 07:47:51.837019 Ranknum = 0x2
2484 07:47:51.837195 DramWidth = 0x4
2485 07:47:51.837368 Size = 0x1000000000
2486 07:47:51.857999 Daw Config: Skt 0 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2487 07:47:51.858267 LowMemory(<4G):Base=0x0, Size=0x40000000
2488 07:47:51.858500 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000
2489 07:47:51.858748 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000
2490 07:47:51.872606 HighMemory(>4G):Base=0x1800000000, Size=0x7FC000000
2491 07:47:51.872865 ColBits = 0xA
2492 07:47:51.873065 RowBits = 0x11
2493 07:47:51.873279 Banknum = 0x10
2494 07:47:51.873490 RankSize = 0x400000000
2495 07:47:51.873696 Ranknum = 0x2
2496 07:47:51.873942 DramWidth = 0x4
2497 07:47:51.874147 Size = 0x1000000000
2498 07:47:51.894500 Daw Config: Skt 0 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2499 07:47:51.894771 HighMemory(>4G):Base=0x2000000000, Size=0xFFC000000
2500 07:47:51.894961 Enable Channel Interleave for socket[1]
2501 07:47:51.895144 Enable Channel Interleave for socket[1]
2502 07:47:51.913571 Daw Cinfig :Skt 1 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0
2503 07:47:51.913830 ColBits = 0xA
2504 07:47:51.914054 RowBits = 0x11
2505 07:47:51.914304 Banknum = 0x10
2506 07:47:51.914517 RankSize = 0x400000000
2507 07:47:51.914766 Ranknum = 0x2
2508 07:47:51.914975 DramWidth = 0x4
2509 07:47:51.915221 Size = 0x1000000000
2510 07:47:51.930734 Daw Config: Skt 1 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2511 07:47:51.931000 HighMemory(>4G):Base=0x41000000000, Size=0xFFC000000
2512 07:47:51.931248 ColBits = 0xA
2513 07:47:51.931472 RowBits = 0x11
2514 07:47:51.931686 Banknum = 0x10
2515 07:47:51.931907 RankSize = 0x400000000
2516 07:47:51.932108 Ranknum = 0x2
2517 07:47:51.932333 DramWidth = 0x4
2518 07:47:51.950701 Size = 0x1000000000
2519 07:47:51.950956 Daw Config: Skt 1 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0
2520 07:47:51.951149 HighMemory(>4G):Base=0x42000000000, Size=0xFFC000000
2521 07:47:51.972829 Finish Config DAW.
2522 07:47:51.973090
2523 07:47:51.973303 Start config RAS or ECC.
2524 07:47:51.973491 pGblData->mem.rascBypass = 1
2525 07:47:51.973699 pGblData->mem.demandScrubMode = 0
2526 07:47:51.973911 pGblData->mem.patrolScrubMode = 0
2527 07:47:51.974087 skt[0] ch[0] ecc enable.
2528 07:47:51.974292 skt[0] ch[1] ecc enable.
2529 07:47:51.999037 skt[0] ch[2] ecc enable.
2530 07:47:51.999262 skt[0] ch[3] ecc enable.
2531 07:47:51.999454 skt[1] ch[0] ecc enable.
2532 07:47:51.999638 skt[1] ch[1] ecc enable.
2533 07:47:51.999818 skt[1] ch[2] ecc enable.
2534 07:47:51.999995 skt[1] ch[3] ecc enable.
2535 07:47:52.000171 Finish config RAS or ECC.
2536 07:47:52.000406
2537 07:47:52.000582 Clean ddrc or rasc interrupt OK
2538 07:47:52.021314 NOTICE: PL011_UART_BASE: 0x602b0000
2539 07:47:52.021574
2540 07:47:52.021807 NOTICE: BL1: 0x3fc8a000 - 0x3fc8b000 [size = 4096]
2541 07:47:52.022021 NOTICE: Booting Trusted Firmware
2542 07:47:52.022229 NOTICE: BL1: v1.1(release):50e18f8
2543 07:47:52.022434 NOTICE: BL1: Built : 08:50:23, Feb 25 2017
2544 07:47:52.083255 NOTICE: BL1: Booting BL2
2545 07:47:52.083530 NOTICE: BL2: v1.1(release):50e18f8
2546 07:47:52.083724 NOTICE: BL2: Built : 08:50:24, Feb 25 2017
2547 07:47:52.152943 NOTICE: BL1: Booting BL3-1
2548 07:47:52.599768 NOTICE: Before BL31 EL3 MMU
2549 07:47:52.600097
2550 07:47:52.600304 NOTICE: After BL31 EL3 MMU
2551 07:47:52.600490
2552 07:47:52.600670 NOTICE: BL3-1: v1.1(release):50e18f8
2553 07:47:52.600850 NOTICE: BL3-1: Built : 08:50:27, Feb 25 2017
2554 07:47:52.601028 NOTICE: [runtime_svc_init]:[94L] rt_svc_descs_num=0x1
2555 07:47:52.649411 NOTICE: [runtime_svc_init]:[109L] start_oen=4 end_oen=4 call_type=1 std_svc
2556 07:47:52.649773 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2557 07:47:52.660604 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2558 07:47:52.660926 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 0
2559 07:47:52.661118 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2560 07:47:52.661305 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2561 07:47:52.661488 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 1
2562 07:47:52.670665 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2563 07:47:52.670947 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2564 07:47:52.671174 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 2
2565 07:47:52.671396 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2566 07:47:52.671614 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2567 07:47:52.720485 NOTICE: [psci_init_aff_map]:[298L] a [psci_init_aff_map]:[298L] affmap_idx = 4
2568 07:47:52.720816 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2569 07:47:52.721012 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2570 07:47:52.721199 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 5
2571 07:47:52.721382 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2572 07:47:52.736324 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2573 07:47:52.736553 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 6
2574 07:47:52.736745 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2575 07:47:52.736932 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2
2576 07:47:52.750537 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 7
2577 07:47:52.750804 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2578 07:47:52.750997 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2579 07:47:52.751232 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 8
2580 07:47:52.751416 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100
2581 07:47:52.764737 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2582 07:47:52.765049 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 9
2583 07:47:52.765311 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200
2584 07:47:52.765566 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2585 07:47:52.765818 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 10
2586 07:47:52.780691 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300
2587 07:47:52.781090 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2588 07:47:52.781357 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 11
2589 07:47:52.781757 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2590 07:47:52.782071 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2591 07:47:52.796833 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 12
2592 07:47:52.797229 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100
2593 07:47:52.797566 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2594 07:47:52.797888 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 13
2595 07:47:52.798207 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200
2596 07:47:52.861626 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2597 07:47:52.862628 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 14
2598 07:47:52.862868 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300
2599 07:47:52.863213 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2600 07:47:52.863580 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 15
2601 07:47:52.883432 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2602 07:47:52.883804 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2603 07:47:52.884573 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 16
2604 07:47:52.884878 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100
2605 07:47:52.885177 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2606 07:47:52.900745 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 17
2607 07:47:52.901167 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200
2608 07:47:52.901528 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2609 07:47:52.901874 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 18
2610 07:47:52.902214 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300
2611 07:47:52.913243 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2612 07:47:52.913668 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 19
2613 07:47:52.914026 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2614 07:47:52.914881 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2615 07:47:52.930420 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 20
2616 07:47:52.930729 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100
2617 07:47:52.930978 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2618 07:47:52.931221 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 21
2619 07:47:52.931593 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200
2620 07:47:52.940813 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2621 07:47:52.941080 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 22
2622 07:47:52.941316 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300
2623 07:47:52.941540 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2624 07:47:52.941742 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 23
2625 07:47:52.950662 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2626 07:47:52.950955 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2627 07:47:52.951163 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 24
2628 07:47:52.951398 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100
2629 07:47:52.951632 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2630 07:47:52.973919 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 25
2631 07:47:52.974220 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200
2632 07:47:52.974427 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2633 07:47:52.974712 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 26
2634 07:47:52.974911 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300
2635 07:47:52.994744 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2636 07:47:52.995027 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 27
2637 07:47:52.995275 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2638 07:47:52.995561 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2639 07:47:52.995807 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 28
2640 07:47:53.015400 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100
2641 07:47:53.015640 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2642 07:47:53.015843 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 29
2643 07:47:53.016040 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200
2644 07:47:53.016246 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2645 07:47:53.037343 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 30
2646 07:47:53.037627 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300
2647 07:47:53.037831 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2648 07:47:53.038027 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 31
2649 07:47:53.060989 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2650 07:47:53.061226 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2651 07:47:53.061429 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 32
2652 07:47:53.061625 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100
2653 07:47:53.061819 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2654 07:47:53.080623 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 33
2655 07:47:53.080871 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200
2656 07:47:53.081075 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2657 07:47:53.081272 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 34
2658 07:47:53.081466 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300
2659 07:47:53.102869 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2660 07:47:53.103199 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 35
2661 07:47:53.103403 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
2662 07:47:53.103676 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2663 07:47:53.103933 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 36
2664 07:47:53.124663 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100
2665 07:47:53.124934 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2666 07:47:53.125396 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 37
2667 07:47:53.125598 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200
2668 07:47:53.125795 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2669 07:47:53.146606 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 38
2670 07:47:53.146912 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300
2671 07:47:53.147142 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1
2672 07:47:53.147371 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 39
2673 07:47:53.147591 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0
2674 07:47:53.168546 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2675 07:47:53.168804 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 40
2676 07:47:53.169039 NOTICE: [psci_init_aff_map]:[296L] mpidr = 1
2677 07:47:53.169263 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2678 07:47:53.169481 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 41
2679 07:47:53.191906 NOTICE: [psci_init_aff_map]:[296L] mpidr = 2
2680 07:47:53.192163 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2681 07:47:53.192383 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 42
2682 07:47:53.192580 NOTICE: [psci_init_aff_map]:[296L] mpidr = 3
2683 07:47:53.192773 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2684 07:47:53.216577 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 43
2685 07:47:53.216816 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100
2686 07:47:53.217326 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2687 07:47:53.217525 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 44
2688 07:47:53.217719 NOTICE: [psci_init_aff_map]:[296L] mpidr = 101
2689 07:47:53.234380 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2690 07:47:53.254723 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 45
2691 07:47:53.255012 NOTICE: [psci_init_aff_map]:[296L] mpidr = 102
2692 07:47:53.255212 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2693 07:47:53.264125 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 46
2694 07:47:53.264450 NOTICE: [psci_init_aff_map]:[296L] mpidr = 103
2695 07:47:53.264641 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2696 07:47:53.264825 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 47
2697 07:47:53.265008 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200
2698 07:47:53.277816 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2699 07:47:53.278056 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 48
2700 07:47:53.278259 NOTICE: [psci_init_aff_map]:[296L] mpidr = 201
2701 07:47:53.278456 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2702 07:47:53.278694 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 49
2703 07:47:53.299710 NOTICE: [psci_init_aff_map]:[296L] mpidr = 202
2704 07:47:53.299989 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2705 07:47:53.300192 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 50
2706 07:47:53.300406 NOTICE: [psci_init_aff_map]:[296L] mpidr = 203
2707 07:47:53.300600 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2708 07:47:53.321557 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 51
2709 07:47:53.321791 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300
2710 07:47:53.321995 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2711 07:47:53.322192 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 52
2712 07:47:53.322385 NOTICE: [psci_init_aff_map]:[296L] mpidr = 301
2713 07:47:53.347276 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2714 07:47:53.347629 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 53
2715 07:47:53.347842 NOTICE: [psci_init_aff_map]:[296L] mpidr = 302
2716 07:47:53.360581 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2717 07:47:53.360852 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 54
2718 07:47:53.361084 NOTICE: [psci_init_aff_map]:[296L] mpidr = 303
2719 07:47:53.361311 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2720 07:47:53.376196 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 55
2721 07:47:53.376467 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000
2722 07:47:53.376694 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2723 07:47:53.376895 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 56
2724 07:47:53.377118 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10001
2725 07:47:53.398060 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2726 07:47:53.398321 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 57
2727 07:47:53.398598 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10002
2728 07:47:53.398801 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2729 07:47:53.399023 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 58
2730 07:47:53.422982 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10003
2731 07:47:53.423253 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2732 07:47:53.423483 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 59
2733 07:47:53.423715 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100
2734 07:47:53.423931 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2735 07:47:53.441830 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 60
2736 07:47:53.442093 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10101
2737 07:47:53.442297 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2738 07:47:53.442495 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 61
2739 07:47:53.442794 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10102
2740 07:47:53.477270 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2741 07:47:53.477711 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 62
2742 07:47:53.477954 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10103
2743 07:47:53.478224 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2744 07:47:53.478463 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 63
2745 07:47:53.485558 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200
2746 07:47:53.485790 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2747 07:47:53.485994 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 64
2748 07:47:53.486228 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10201
2749 07:47:53.507515 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2750 07:47:53.507754 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 65
2751 07:47:53.507957 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10202
2752 07:47:53.508154 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2753 07:47:53.508365 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 66
2754 07:47:53.574418 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10203
2755 07:47:53.574801 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2756 07:47:53.575034 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 67
2757 07:47:53.575261 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300
2758 07:47:53.575486 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2759 07:47:53.590536 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 68
2760 07:47:53.590794 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10301
2761 07:47:53.590997 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2762 07:47:53.591193 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 69
2763 07:47:53.591387 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10302
2764 07:47:53.600602 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2765 07:47:53.600859 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 70
2766 07:47:53.601087 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10303
2767 07:47:53.601318 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2768 07:47:53.601518 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 71
2769 07:47:53.611502 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000
2770 07:47:53.611777 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2771 07:47:53.612013 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 72
2772 07:47:53.612256 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20001
2773 07:47:53.612480 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2774 07:47:53.631635 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 73
2775 07:47:53.631898 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20002
2776 07:47:53.632130 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2777 07:47:53.632387 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 74
2778 07:47:53.632614 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20003
2779 07:47:53.650691 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2780 07:47:53.650925 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 75
2781 07:47:53.651129 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100
2782 07:47:53.651326 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2783 07:47:53.661046 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 76
2784 07:47:53.661293 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20101
2785 07:47:53.661495 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2786 07:47:53.661691 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 77
2787 07:47:53.661885 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20102
2788 07:47:53.681133 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2789 07:47:53.681368 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 78
2790 07:47:53.681570 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20103
2791 07:47:53.681803 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2792 07:47:53.681998 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 79
2793 07:47:53.704345 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200
2794 07:47:53.704618 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2795 07:47:53.704821 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 80
2796 07:47:53.705018 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20201
2797 07:47:53.705211 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2798 07:47:53.768625 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 81
2799 07:47:53.769036 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20202
2800 07:47:53.769272 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2801 07:47:53.769501 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 82
2802 07:47:53.769730 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20203
2803 07:47:53.781295 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2804 07:47:53.781559 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 83
2805 07:47:53.781833 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300
2806 07:47:53.782060 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2807 07:47:53.782257 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 84
2808 07:47:53.800566 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20301
2809 07:47:53.800875 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2810 07:47:53.801102 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 85
2811 07:47:53.801306 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20302
2812 07:47:53.816382 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2813 07:47:53.816699 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 86
2814 07:47:53.816944 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20303
2815 07:47:53.817175 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2816 07:47:53.817402 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 87
2817 07:47:53.834071 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000
2818 07:47:53.834361 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2819 07:47:53.834610 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 88
2820 07:47:53.834812 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30001
2821 07:47:53.835044 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2822 07:47:53.850471 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 89
2823 07:47:53.850762 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30002
2824 07:47:53.850999 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2825 07:47:53.851227 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 90
2826 07:47:53.851464 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30003
2827 07:47:53.860413 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2828 07:47:53.860700 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 91
2829 07:47:53.860909 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100
2830 07:47:53.861128 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2831 07:47:53.861354 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 92
2832 07:47:53.879440 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30101
2833 07:47:53.879696 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2834 07:47:53.879928 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 93
2835 07:47:53.880155 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30102
2836 07:47:53.880422 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2837 07:47:53.901096 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 94
2838 07:47:53.901358 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30103
2839 07:47:53.901593 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2840 07:47:53.901816 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 95
2841 07:47:53.902015 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200
2842 07:47:53.962358 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2843 07:47:53.962719 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 96
2844 07:47:53.980470 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30201
2845 07:47:53.980710 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2846 07:47:53.980913 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 97
2847 07:47:53.981109 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30202
2848 07:47:53.981302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2849 07:47:53.991152 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 98
2850 07:47:53.991386 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30203
2851 07:47:53.991588 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2852 07:47:53.991784 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 99
2853 07:47:53.991977 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300
2854 07:47:54.010679 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2855 07:47:54.010985 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 100
2856 07:47:54.011188 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30301
2857 07:47:54.011385 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2858 07:47:54.020729 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 101
2859 07:47:54.021057 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30302
2860 07:47:54.021258 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2861 07:47:54.021453 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 102
2862 07:47:54.021646 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30303
2863 07:47:54.031715 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2864 07:47:54.031951 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 103
2865 07:47:54.032404 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000
2866 07:47:54.032607 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2867 07:47:54.032833 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 104
2868 07:47:54.050492 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40001
2869 07:47:54.050813 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2870 07:47:54.051020 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 105
2871 07:47:54.051250 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40002
2872 07:47:54.051479 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2873 07:47:54.065310 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 106
2874 07:47:54.065542 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40003
2875 07:47:54.065747 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2876 07:47:54.065947 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 107
2877 07:47:54.066142 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100
2878 07:47:54.087180 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2879 07:47:54.087447 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 108
2880 07:47:54.087680 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40101
2881 07:47:54.087902 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2882 07:47:54.088130 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 109
2883 07:47:54.108985 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40102
2884 07:47:54.109256 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2885 07:47:54.109488 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 110
2886 07:47:54.109715 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40103
2887 07:47:54.130629 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2888 07:47:54.130900 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 111
2889 07:47:54.131130 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200
2890 07:47:54.131366 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2891 07:47:54.131602 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 112
2892 07:47:54.195816 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40201
2893 07:47:54.196096 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2894 07:47:54.196314 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 113
2895 07:47:54.210646 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40202
2896 07:47:54.210880 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2897 07:47:54.211081 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 114
2898 07:47:54.211278 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40203
2899 07:47:54.221796 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2900 07:47:54.222030 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 115
2901 07:47:54.222232 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300
2902 07:47:54.222429 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2903 07:47:54.222647 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 116
2904 07:47:54.244208 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40301
2905 07:47:54.244458 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2906 07:47:54.244662 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 117
2907 07:47:54.244859 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40302
2908 07:47:54.245054 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2909 07:47:54.260735 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 118
2910 07:47:54.260981 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40303
2911 07:47:54.261184 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2912 07:47:54.261381 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 119
2913 07:47:54.261575 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000
2914 07:47:54.271359 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2915 07:47:54.271593 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 120
2916 07:47:54.271794 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50001
2917 07:47:54.271989 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2918 07:47:54.272183 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 121
2919 07:47:54.291202 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50002
2920 07:47:54.291437 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2921 07:47:54.291640 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 122
2922 07:47:54.291837 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50003
2923 07:47:54.292031 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2924 07:47:54.314862 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 123
2925 07:47:54.315097 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100
2926 07:47:54.315300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2927 07:47:54.315497 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 124
2928 07:47:54.330666 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50101
2929 07:47:54.330900 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2930 07:47:54.331102 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 125
2931 07:47:54.331297 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50102
2932 07:47:54.331490 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2933 07:47:54.341422 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 126
2934 07:47:54.341656 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50103
2935 07:47:54.341860 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2936 07:47:54.342057 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 127
2937 07:47:54.342244 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200
2938 07:47:54.364376 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2939 07:47:54.364637 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 128
2940 07:47:54.364879 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50201
2941 07:47:54.365107 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2942 07:47:54.365333 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 129
2943 07:47:54.382857 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50202
2944 07:47:54.383185 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2945 07:47:54.383409 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 130
2946 07:47:54.383628 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50203
2947 07:47:54.383830 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2948 07:47:54.404753 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 131
2949 07:47:54.405023 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300
2950 07:47:54.405260 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2951 07:47:54.405483 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 132
2952 07:47:54.426247 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50301
2953 07:47:54.426510 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2954 07:47:54.426780 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 133
2955 07:47:54.427012 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50302
2956 07:47:54.427212 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2957 07:47:54.448124 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 134
2958 07:47:54.448405 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50303
2959 07:47:54.448642 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2960 07:47:54.448881 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 135
2961 07:47:54.449105 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000
2962 07:47:54.472462 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2963 07:47:54.472724 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 136
2964 07:47:54.472957 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60001
2965 07:47:54.473194 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2966 07:47:54.473421 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 137
2967 07:47:54.491950 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60002
2968 07:47:54.492259 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2969 07:47:54.492506 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 138
2970 07:47:54.492754 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60003
2971 07:47:54.492987 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2972 07:47:54.514425 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 139
2973 07:47:54.514691 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100
2974 07:47:54.514893 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2975 07:47:54.515090 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 140
2976 07:47:54.536105 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60101
2977 07:47:54.536372 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2978 07:47:54.536575 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 141
2979 07:47:54.536773 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60102
2980 07:47:54.536966 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2981 07:47:54.557957 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 142
2982 07:47:54.558191 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60103
2983 07:47:54.558394 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2984 07:47:54.558613 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 143
2985 07:47:54.558808 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200
2986 07:47:54.579354 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2987 07:47:54.579587 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 144
2988 07:47:54.579789 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60201
2989 07:47:54.579985 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2990 07:47:54.580178 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 145
2991 07:47:54.603477 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60202
2992 07:47:54.603737 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2993 07:47:54.604010 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 146
2994 07:47:54.604211 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60203
2995 07:47:54.604465 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2996 07:47:54.623050 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 147
2997 07:47:54.623321 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300
2998 07:47:54.623554 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
2999 07:47:54.623794 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 148
3000 07:47:54.624021 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60301
3001 07:47:54.644959 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3002 07:47:54.645264 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 149
3003 07:47:54.645541 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60302
3004 07:47:54.645807 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3005 07:47:54.666861 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 150
3006 07:47:54.667094 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60303
3007 07:47:54.667296 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3008 07:47:54.667492 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 151
3009 07:47:54.667686 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000
3010 07:47:54.688650 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3011 07:47:54.688884 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 152
3012 07:47:54.689085 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70001
3013 07:47:54.689281 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3014 07:47:54.689472 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 153
3015 07:47:54.710635 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70002
3016 07:47:54.710908 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3017 07:47:54.711144 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 154
3018 07:47:54.711371 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70003
3019 07:47:54.711596 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3020 07:47:54.732447 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 155
3021 07:47:54.732754 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100
3022 07:47:54.732995 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3023 07:47:54.733260 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 156
3024 07:47:54.733496 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70101
3025 07:47:54.808849 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3026 07:47:54.809135 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 157
3027 07:47:54.809338 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70102
3028 07:47:54.809535 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3029 07:47:54.820539 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 158
3030 07:47:54.820773 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70103
3031 07:47:54.820974 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3032 07:47:54.821171 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 159
3033 07:47:54.821364 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200
3034 07:47:54.830990 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3035 07:47:54.831238 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 160
3036 07:47:54.831440 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70201
3037 07:47:54.831637 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3038 07:47:54.831830 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 161
3039 07:47:54.843748 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70202
3040 07:47:54.844027 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3041 07:47:54.844282 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 162
3042 07:47:54.844524 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70203
3043 07:47:54.844755 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3044 07:47:54.864531 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 163
3045 07:47:54.864767 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300
3046 07:47:54.864971 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3047 07:47:54.865170 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 164
3048 07:47:54.865366 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70301
3049 07:47:54.881046 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3050 07:47:54.881305 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 165
3051 07:47:54.881535 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70302
3052 07:47:54.881767 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3053 07:47:54.893247 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 166
3054 07:47:54.893514 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70303
3055 07:47:54.893748 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0
3056 07:47:54.893973 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 167
3057 07:47:54.894198 NOTICE: [cm_prepare_el3_exit]:[262L] read_tpidr_el3 = 3fc5e800
3058 07:47:54.931780 NOTICE: [cm_prepare_el3_exit]:[319L] ctx add = 3fc7ef80
3059 07:47:54.932049
3060 07:47:54.932293 :486=170
3061 07:47:57.732505 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane
3062 07:47:57.733878 Halt Macro 2 MCU!!
3063 07:47:57.801007 Macro 2 Download Firmware Success!!
3064 07:47:57.801705 Release Macro 2 MCU!!
3065 07:47:57.925516 Temperature: 28 (0x1C)
3066 07:47:57.926186 Temperature: 28 (0x1C)
3067 07:47:57.980843 [serdes_init]:SerDes2 init success!
3068 07:47:57.981357 Halt Macro 3 MCU!!
3069 07:47:58.000642 Macro 3 Download Firmware Success!!
3070 07:47:58.001111 Release Macro 3 MCU!!
3071 07:47:58.030687 Temperature: 30 (0x1E)
3072 07:47:58.080682 Temperature: 30 (0x1E)
3073 07:47:58.110685 [serdes_init]:SerDes3 init success!
3074 07:47:58.111233 Halt Macro 4 MCU!!
3075 07:47:58.131397 Macro 4 Download Firmware Success!!
3076 07:47:58.131835 Release Macro 4 MCU!!
3077 07:47:58.191577 Temperature: 30 (0x1E)
3078 07:47:58.241824 Temperature: 30 (0x1E)
3079 07:47:58.242183 [serdes_init]:SerDes4 init success!
3080 07:47:58.242457 [serdes_hilink5_init]:hilink5_mode sas1 4 lane
3081 07:47:58.242776 Halt Macro 5 MCU!!
3082 07:47:58.330513 Macro 5 Download Firmware Success!!
3083 07:47:58.330859 Release Macro 5 MCU!!
3084 07:47:58.411900 Temperature: 30 (0x1E)
3085 07:47:58.412255 Temperature: 30 (0x1E)
3086 07:47:58.470596 [serdes_init]:SerDes5 init success!
3087 07:47:58.470912 [serdes_hilink6_init] lane 0 =>sas1 lane 0
3088 07:47:58.471145 [serdes_hilink6_init] lane 1 =>sas1 lane 1
3089 07:47:58.471366 [serdes_hilink6_init] lane 2 =>sas1 lane 2
3090 07:47:58.471558 [serdes_hilink6_init] lane 3 =>sas1 lane 3
3091 07:47:58.471746 Halt Macro 6 MCU!!
3092 07:47:58.610891 Macro 6 Download Firmware Success!!
3093 07:47:58.611218 Release Macro 6 MCU!!
3094 07:47:58.611419 Temperature: 30 (0x1E)
3095 07:47:58.680426 Temperature: 30 (0x1E)
3096 07:47:58.680692 [serdes_init]:SerDes6 init success!
3097 07:47:58.680920 [serdes_hilink0_init]:hilink0_mode pcie5 8 lane
3098 07:47:58.681141 Halt Macro 0 MCU!!
3099 07:47:58.822055 Macro 0 Download Firmware Success!!
3100 07:47:58.822327 Release Macro 0 MCU!!
3101 07:47:58.822527 Temperature: 27 (0x1B)
3102 07:47:58.902851 Temperature: 27 (0x1B)
3103 07:47:58.951262 [serdes_init]:SerDes0 init success!
3104 07:47:58.951562 [serdes_hilink1_init]:hilink1_mode pcie4 8 lane
3105 07:47:58.951788 Halt Macro 1 MCU!!
3106 07:47:59.042672 Macro 1 Download Firmware Success!!
3107 07:47:59.042935 Release Macro 1 MCU!!
3108 07:47:59.110725 Temperature: 27 (0x1B)
3109 07:47:59.170772 Temperature: 27 (0x1B)
3110 07:47:59.260299 [serdes_init]:SerDes1 init success!
3111 07:47:59.260556 [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane
3112 07:47:59.260784 Halt Macro 5 MCU!!
3113 07:47:59.312145 Macro 5 Download Firmware Success!!
3114 07:47:59.312437 Release Macro 5 MCU!!
3115 07:47:59.405737 Temperature: 27 (0x1B)
3116 07:47:59.406093 Temperature: 27 (0x1B)
3117 07:47:59.440419 [serdes_init]:SerDes5 init success!
3118 07:47:59.440650 [serdes_hilink6_init] lane 0 =>sas5 lane 0
3119 07:47:59.440895 [serdes_hilink6_init] lane 1 =>sas5 lane 1
3120 07:47:59.441114 Halt Macro 6 MCU!!
3121 07:47:59.530767 Macro 6 Download Firmware Success!!
3122 07:47:59.531286 Release Macro 6 MCU!!
3123 07:47:59.621821 Temperature: 27 (0x1B)
3124 07:47:59.622255 Temperature: 27 (0x1B)
3125 07:47:59.650485 [serdes_init]:SerDes6 init success!
3126 07:47:59.650967 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane
3127 07:47:59.651287 Halt Macro 2 MCU!!
3128 07:47:59.750977 Macro 2 Download Firmware Success!!
3129 07:47:59.751273 Release Macro 2 MCU!!
3130 07:47:59.821959 Temperature: 28 (0x1C)
3131 07:47:59.890355 Temperature: 28 (0x1C)
3132 07:47:59.935453 [serdes_init]:SerDes2 init success!
3133 07:47:59.936027 Halt Macro 3 MCU!!
3134 07:47:59.950687 Macro 3 Download Firmware Success!!
3135 07:47:59.950997 Release Macro 3 MCU!!
3136 07:48:00.060810 Temperature: 29 (0x1D)
3137 07:48:00.061425 Temperature: 30 (0x1E)
3138 07:48:00.061941 [serdes_init]:SerDes3 init success!
3139 07:48:00.062420 Halt Macro 4 MCU!!
3140 07:48:00.091892 Macro 4 Download Firmware Success!!
3141 07:48:00.092463 Release Macro 4 MCU!!
3142 07:48:00.161241 Temperature: 30 (0x1E)
3143 07:48:00.161868 Temperature: 30 (0x1E)
3144 07:48:00.190874 [serdes_init]:SerDes4 init success!
3145 07:48:00.191517 [serdes_hilink5_init]:hilink5_mode sas1 4 lane
3146 07:48:00.191950 Halt Macro 5 MCU!!
3147 07:48:00.310770 Macro 5 Download Firmware Success!!
3148 07:48:00.311211 Release Macro 5 MCU!!
3149 07:48:00.391768 Temperature: 30 (0x1E)
3150 07:48:00.392147 Temperature: 30 (0x1E)
3151 07:48:00.430302 [serdes_init]:SerDes5 init success!
3152 07:48:00.430577 [serdes_hilink6_init] lane 0 =>sas1 lane 0
3153 07:48:00.430916 [serdes_hilink6_init] lane 1 =>sas1 lane 1
3154 07:48:00.450628 [serdes_hilink6_init] lane 2 =>sas1 lane 2
3155 07:48:00.451060 [serdes_hilink6_init] lane 3 =>sas1 lane 3
3156 07:48:00.451372 Halt Macro 6 MCU!!
3157 07:48:00.570845 Macro 6 Download Firmware Success!!
3158 07:48:00.571752 Release Macro 6 MCU!!
3159 07:48:00.650644 Temperature: 30 (0x1E)
3160 07:48:00.651090 Temperature: 30 (0x1E)
3161 07:48:00.691107 [serdes_init]:SerDes6 init success!
3162 07:48:00.691582 [serdes_hilink0_init]:hilink0_mode pcie5 8 lane
3163 07:48:00.691917 Halt Macro 0 MCU!!
3164 07:48:00.830502 Macro 0 Download Firmware Success!!
3165 07:48:00.830907 Release Macro 0 MCU!!
3166 07:48:00.902188 Temperature: 27 (0x1B)
3167 07:48:00.962521 Temperature: 27 (0x1B)
3168 07:48:01.010661 [serdes_init]:SerDes0 init success!
3169 07:48:01.011212 [serdes_hilink1_init]:hilink1_mode pcie4 8 lane
3170 07:48:01.011672 Halt Macro 1 MCU!!
3171 07:48:01.171281 Macro 1 Download Firmware Success!!
3172 07:48:01.171582 Release Macro 1 MCU!!
3173 07:48:01.230425 Temperature: 27 (0x1B)
3174 07:48:01.282316 Temperature: 27 (0x1B)
3175 07:48:01.350735 [serdes_init]:SerDes1 init success!
3176 07:48:01.351094 [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane
3177 07:48:01.351380 Halt Macro 5 MCU!!
3178 07:48:01.530777 Macro 5 Download Firmware Success!!
3179 07:48:01.531317 Release Macro 5 MCU!!
3180 07:48:01.531887 Temperature: 27 (0x1B)
3181 07:48:01.600934 Temperature: 27 (0x1B)
3182 07:48:01.620856 [serdes_init]:SerDes5 init success!
3183 07:48:01.621450 [serdes_hilink6_init] lane 0 =>sas5 lane 0
3184 07:48:01.621858 [serdes_hilink6_init] lane 1 =>sas5 lane 1
3185 07:48:01.622223 Halt Macro 6 MCU!!
3186 07:48:01.760898 Macro 6 Download Firmware Success!!
3187 07:48:01.761450 Release Macro 6 MCU!!
3188 07:48:01.840758 Temperature: 27 (0x1B)
3189 07:48:01.841387 Temperature: 27 (0x1B)
3190 07:48:01.861883 [serdes_init]:SerDes6 init success!
3191 07:48:02.158212 InfoFromBmc.ProductName TaiShan 2280
3192 07:48:02.158817 InfoFromBmc.SerialNum 2102311TBJ10H8000087
3193 07:48:02.159317 InfoFromBmc.ManufactureType02 Huawei
3194 07:48:02.159745 InfoFromBmc.AssetTag
3195 07:48:02.160131 InfoFromBmc.SrNumType02 024APL10H8000090
3196 07:48:02.160514 InfoFromBmc.AssetTagType03
3197 07:48:02.194481 InfoFromBmc.SrNumType03 To be filled by O.E.M.
3198 07:48:02.194997 InfoFromBmc.VersionType03
3199 07:48:02.195511 InfoFromBmc.ChassisType03
3200 07:48:02.195901 InfoFromBmc.ManufacturerType03 Huawei
3201 07:48:02.196481 Create event for smbios table transfer success.
3202 07:48:02.196870 VerStr:1.12
3203 07:48:02.221036 Create event for miscellaneous ipmi operation success.
3204 07:48:11.120548 Locate gEfiPciIoProtocol Failed.
3205 07:48:11.235745 DawNum[0] = 2,DawNum[1] = 1,DawNum[2] =2,DawNum[3] =1
3206 07:48:11.236214 0 Base = 0x0, Size = 0x40000000
3207 07:48:11.236554 0 Base = 0x1000000000, Size = 0x1000000000
3208 07:48:11.236868 1 Base = 0x2000000000, Size = 0x1000000000
3209 07:48:11.237180 2 Base = 0x40000000000, Size = 0x40000000
3210 07:48:11.260491 2 Base = 0x41000000000, Size = 0x1000000000
3211 07:48:11.260826 3 Base = 0x42000000000, Size = 0x1000000000
3212 07:48:11.281290 [gmac_initialize]:[3650L] GpriData=0x3E8DE018
3213 07:48:11.303271 pPriv->ulMacSpeed:9
3214 07:48:11.303832 pPriv->ulMacDuplex:1
3215 07:48:11.304368 pPriv->ulPort:0
3216 07:48:11.304907 pPriv->ulGEBase:0xC7040000
3217 07:48:11.305493 pPriv->ulPpeCommonBase:0xC5070000
3218 07:48:11.331968 pPriv->ulPpeTNLBase:0xC5000000
3219 07:48:11.332421 pPriv->ulRCBCommonBase:0xC5080000
3220 07:48:11.332796 pPriv->ulRCBCommonEntryBase:0xC5080000
3221 07:48:11.333158 pPriv->ulRCBSramEntryBase:0xC5090000
3222 07:48:11.333511 pPriv->ulRingNum:0
3223 07:48:11.333860 pPriv->ulRingAddr:0
3224 07:48:11.334204 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE8
3225 07:48:11.432610 DSAF_init
3226 07:48:11.433019 tbl_tcam_data
3227 07:48:11.433348 0x3F196CA0:0xA0A33BC1 0x40E80000 0x00000000 0x00000001
3228 07:48:11.433675 0x3F196CB0:0x00000000
3229 07:48:11.433998 tbl_tcam_ucast
3230 07:48:11.463080 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3231 07:48:11.463526 0x3F196CB8:0x0000007F 0x00000000 0x0000007F 0x00000000
3232 07:48:11.480890 0x3F196CC8:0x01000204
3233 07:48:11.481230 ----ok
3234 07:48:11.481520 LocateProtocol mOemXgeStatusProtocol success.
3235 07:48:11.481801 RXRING = 0x3E8D9000
3236 07:48:11.482076 TXRING = 0x3E8D4000
3237 07:48:11.482350 pPriv->ulTxMask = 512
3238 07:48:11.482650 RXBUFF = 0x3E6D3000
3239 07:48:11.482916 TXBUFF = 0x3E4D2000
3240 07:48:11.483180 [gmac_initialize]:[3650L] GpriData=0x3E44C018
3241 07:48:11.506923 pPriv->ulMacSpeed:9
3242 07:48:11.507351 pPriv->ulMacDuplex:1
3243 07:48:11.507638 pPriv->ulPort:1
3244 07:48:11.507917 pPriv->ulGEBase:0xC7044000
3245 07:48:11.508190 pPriv->ulPpeCommonBase:0xC5070000
3246 07:48:11.508487 pPriv->ulPpeTNLBase:0xC5010000
3247 07:48:11.508756 pPriv->ulRCBCommonBase:0xC5080000
3248 07:48:11.509019 pPriv->ulRCBCommonEntryBase:0xC5080000
3249 07:48:11.531411 pPriv->ulRCBSramEntryBase:0xC5090000
3250 07:48:11.531785 pPriv->ulRingNum:16
3251 07:48:11.532127 pPriv->ulRingAddr:1048576
3252 07:48:11.532492 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE9
3253 07:48:11.532826 DSAF_init
3254 07:48:11.533153 tbl_tcam_data
3255 07:48:11.533481 0x3F196CA0:0xA0A33BC1 0x40E90001 0x00000000 0x00000001
3256 07:48:11.533808 0x3F196CB0:0x00000000
3257 07:48:11.534132 tbl_tcam_ucast
3258 07:48:11.554231 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3259 07:48:11.554478 0x3F196CB8:0x0000008F 0x00000000 0x0000008F 0xC13BA3A0
3260 07:48:11.554730 0x3F196CC8:0x0000E940
3261 07:48:11.554966 ----ok
3262 07:48:11.555185 LocateProtocol mOemXgeStatusProtocol success.
3263 07:48:11.555556 RXRING = 0x3E447000
3264 07:48:11.555751 TXRING = 0x3E442000
3265 07:48:11.556082 pPriv->ulTxMask = 512
3266 07:48:11.582153 RXBUFF = 0x3E241000
3267 07:48:11.582593 TXBUFF = 0x3E040000
3268 07:48:11.582912 [gmac_initialize]:[3650L] GpriData=0x3DFB8018
3269 07:48:11.638511 pPriv->ulMacSpeed:8
3270 07:48:11.638797 pPriv->ulMacDuplex:1
3271 07:48:11.639093 pPriv->ulPort:4
3272 07:48:11.639372 pPriv->ulGEBase:0xC7050000
3273 07:48:11.639645 pPriv->ulPpeCommonBase:0xC5070000
3274 07:48:11.654397 pPriv->ulPpeTNLBase:0xC5040000
3275 07:48:11.654782 pPriv->ulRCBCommonBase:0xC5080000
3276 07:48:11.655124 pPriv->ulRCBCommonEntryBase:0xC5080000
3277 07:48:11.655457 pPriv->ulRCBSramEntryBase:0xC5090000
3278 07:48:11.655785 pPriv->ulRingNum:64
3279 07:48:11.656109 pPriv->ulRingAddr:4194304
3280 07:48:11.656459 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE6
3281 07:48:11.680865 PhyID : 0x1410DD0
3282 07:48:11.681280 PhyAddr: 0x0
3283 07:48:11.681624 ETH_PhyInit 1928; Marvell 88E1512 detect!
3284 07:48:12.092700 MII_CTRL_REG = 0x3100
3285 07:48:12.093047 MII_STAT_REG = 0x7949
3286 07:48:12.093240 page 18, reg20:0x1
3287 07:48:12.105502 page 0, reg17:0x4000
3288 07:48:12.105804 Phy Init OK
3289 07:48:12.106062 DSAF_init
3290 07:48:12.106331 tbl_tcam_data
3291 07:48:12.106656 0x3F196CA0:0xA0A33BC1 0x40E60004 0x00000000 0x00000001
3292 07:48:12.106953 0x3F196CB0:0x00000000
3293 07:48:12.107242 tbl_tcam_ucast
3294 07:48:12.107521 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3295 07:48:12.133117 0x3F196CB8:0x000000BF 0x00000000 0x000000BF 0xAFAFAFAF
3296 07:48:12.133398 0x3F196CC8:0xAFAFAFAF
3297 07:48:12.133638 ----ok
3298 07:48:12.227424 RXRING = 0x3DFB3000
3299 07:48:12.227707 TXRING = 0x3DFAD000
3300 07:48:12.227944 pPriv->ulTxMask = 512
3301 07:48:12.228171 RXBUFF = 0x3DDAB000
3302 07:48:12.228424 TXBUFF = 0x3DBA9000
3303 07:48:12.250807 [gmac_initialize]:[3650L] GpriData=0x3DB21018
3304 07:48:12.290966 pPriv->ulMacSpeed:8
3305 07:48:12.291377 pPriv->ulMacDuplex:1
3306 07:48:12.291722 pPriv->ulPort:5
3307 07:48:12.292052 pPriv->ulGEBase:0xC7054000
3308 07:48:12.292409 pPriv->ulPpeCommonBase:0xC5070000
3309 07:48:12.292735 pPriv->ulPpeTNLBase:0xC5050000
3310 07:48:12.293053 pPriv->ulRCBCommonBase:0xC5080000
3311 07:48:12.293369 pPriv->ulRCBCommonEntryBase:0xC5080000
3312 07:48:12.370862 pPriv->ulRCBSramEntryBase:0xC5090000
3313 07:48:12.371305 pPriv->ulRingNum:80
3314 07:48:12.371655 pPriv->ulRingAddr:5242880
3315 07:48:12.371994 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE7
3316 07:48:12.372449 PhyID : 0x1410DD0
3317 07:48:12.372824 PhyAddr: 0x1
3318 07:48:12.373099 ETH_PhyInit 1928; Marvell 88E1512 detect!
3319 07:48:12.750848 MII_CTRL_REG = 0x3100
3320 07:48:12.751205 MII_STAT_REG = 0x7949
3321 07:48:12.813805 page 18, reg20:0x1
3322 07:48:12.814138 page 0, reg17:0x4000
3323 07:48:12.846734 Phy Init OK
3324 07:48:12.847071 DSAF_init
3325 07:48:12.847317 tbl_tcam_data
3326 07:48:12.847554 0x3F196CA0:0xA0A33BC1 0x40E70005 0x00000000 0x00000001
3327 07:48:12.847780 0x3F196CB0:0x00000000
3328 07:48:12.872039 tbl_tcam_ucast
3329 07:48:12.872373 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001
3330 07:48:12.872670 0x3F196CB8:0x000000CF 0x00000000 0x000000CF 0xAFAFAFAF
3331 07:48:12.872909 0x3F196CC8:0xAFAFAFAF
3332 07:48:12.873140 ----ok
3333 07:48:12.953098 RXRING = 0x3DB1C000
3334 07:48:12.953512 TXRING = 0x3DB17000
3335 07:48:12.953844 pPriv->ulTxMask = 512
3336 07:48:12.954138 RXBUFF = 0x3D916000
3337 07:48:12.954461 TXBUFF = 0x3D714000
3338 07:48:13.110950 SasDriverInitialize Ok!!!
3339 07:48:13.130969 [sas_init,2173]Card:1 init ok
3340 07:48:13.131493 [Higgs_StartPhy,185]Card:1 no cable on phy:0, default as electric cable
3341 07:48:13.731184 [Higgs_IntrInquiryOperation,219]Identify info:0x20010202,DevType:2--2,uiPhyContext:0x0
3342 07:48:13.752762 [Higgs_PhyCtrlUpDown,332]Higgs_PhyCtrlUpDown at uiPhyId = 0x0
3343 07:48:13.753161 [Higgs_PhyCtrlUpDown,346]uiPhyId:0x0, uiIrqVal:0x26
3344 07:48:13.753405 [Higgs_PhyUp,503]phyid:0,Rate is 11
3345 07:48:13.781189 [SAINI_ClearPortRsc,449]Card:1 port:0 clr port rsc,remove all device from device list of Disc
3346 07:48:13.801035 [SAINI_ExpanderBufferSwitch,1306]EXPANDER Buffer function is 2 !
3347 07:48:13.801430 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CC9F0(uni id:0x0) to dev addr:0x500E004AAAAAAA00(sal dev:3D5D42D8) done func is NULL,v_pstMsg->stStatus.enDrvResp803
3348 07:48:13.819427 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CCFD8(uni id:0x0) to dev addr:0x500E004AAAAAAA01(sal dev:3D5D4598) done func is NULL,v_pstMsg->stStatus.enDrvResp803
3349 07:48:13.840797 [SAL_AbortTaskSet,646]Now let's start abort SAS dev Io Card:1 msg:3D5CD5C0 to dev addr:0x500E004AAAAAAA1E(sal dev:3D5D4858),v_pstMsg->stStatus.enDrvResp803,pstMsg->pfnDone:31B85BF8
3350 07:48:13.841151 [SasScanDisk,838]Open Card:1 Phy:0 success!
3351 07:48:13.841461
3352 07:48:13.863529 Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA00, status = Success
3353 07:48:13.863884 Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA01, status = Success
3354 07:48:13.864192 SasDriverStart Ok!!!
3355 07:48:16.899809 SmiControllerDriverSupported - Status:Success
3356 07:48:16.900372 Install GopDevicePath Handle 0
3357 07:48:16.900705 Install GopDevicePath Handle 3D54D898
3358 07:48:16.901072 Install GopDevicePath Status Success
3359 07:48:16.901443 SmiGraphicsOutputSetMode +
3360 07:48:16.901799 Resetting Memory
3361 07:48:16.902135 setModeEx +
3362 07:48:16.902448 programModeRegisters +
3363 07:48:16.921225 [LPC] CRT_PLL1_750HS = 0x1D40A02
3364 07:48:16.921635 [LPC] CRT_PLL2_750HS = 0x206B851E
3365 07:48:16.921879 [LPC] SECONDARY_DISPLAY_CTRL = 0x2087106
3366 07:48:16.922098 setModeEx -
3367 07:48:16.979786 SmiGraphicsOutputSetMode x=640 y=480
3368 07:48:16.980107 SmiGraphicsOutputSetMode -
3369 07:48:16.980324 SmiGraphicsOutputConstructor -
3370 07:48:17.010718 [2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[2J[01;01H[=3h[2J[01;01H[0m[35m[40mSmiGraphicsOutputQueryMode +
3371 07:48:17.011032 SmiGraphicsOutputQueryMode -
3372 07:48:17.011232 SmiGraphicsOutputQueryMode +
3373 07:48:17.011425 SmiGraphicsOutputQueryMode -
3374 07:48:17.091394 SmiGraphicsOutputQueryMode +
3375 07:48:17.091731 SmiGraphicsOutputQueryMode -
3376 07:48:17.091921 SmiGraphicsOutputQueryMode +
3377 07:48:17.092113 SmiGraphicsOutputQueryMode -
3378 07:48:17.167451 [2J[01;01H[=3h[2J[01;01H[0m[37m[40mSmiGraphicsOutputQueryMode +
3379 07:48:17.167930 SmiGraphicsOutputQueryMode -
3380 07:48:18.981215 [2J[01;01H[=3h[2J[01;01H[0m[35m[40mSmiControllerDriverSupported - Status:Unsupported
3381 07:48:18.981685 SmiControllerDriverSupported - Status:Unsupported
3382 07:48:18.981977 SmiControllerDriverSupported - Status:Unsupported
3383 07:48:18.982256 SmiControllerDriverSupported - Status:Unsupported
3384 07:48:19.025252 SmiControllerDriverSupported - Status:Unsupported
3385 07:48:19.025610 SmiControllerDriverSupported - Status:Unsupported
3386 07:48:19.040904 SmiControllerDriverSupported - Status:Unsupported
3387 07:48:19.041322 SmiControllerDriverSupported - Status:Unsupported
3388 07:48:20.060691 SmiControllerDriverSupported - Status:Unsupported
3389 07:48:20.061080 SmiControllerDriverSupported - Status:Unsupported
3390 07:48:20.061273 SmiControllerDriverSupported - Status:Unsupported
3391 07:48:20.061469 SmiControllerDriverSupported - Status:Unsupported
3392 07:48:20.080881 SmiControllerDriverSupported - Status:Unsupported
3393 07:48:20.081180 SmiControllerDriverSupported - Status:Unsupported
3394 07:48:20.081426 SmiControllerDriverSupported - Status:Unsupported
3395 07:48:20.081703 SmiControllerDriverSupported - Status:Unsupported
3396 07:48:20.732274 [0m[37m[40mPress Enter to boot OS immediately.
3397 07:48:20.732871 Press any other key in 10 seconds to stop automatical booting...
3398 07:48:31.230681 [2J[01;01HSmiGraphicsOutputQueryMode +
3399 07:48:31.231004 SmiGraphicsOutputQueryMode -
3400 07:48:39.220847 ..[0m[30m[47mWelcome to GRUB!
3401 07:48:39.221446
3402 07:48:39.221831
3403 07:48:39.490762 [0m[37m[40m[0m[30m[40m[2J[01;01H[0m[37m[40m[02;27HGNU GRUB version 2.02~beta3
3404 07:48:39.491098
3405 07:48:39.491288
3406 07:48:39.491471 Minimal BASH-like line editing is supported. For the first word, TAB
3407 07:48:39.491652
3408 07:48:39.574475 lists possible command completions. Anywhere else TAB lists possible
3409 07:48:39.574831
3410 07:48:39.575090 device or file completions.
3411 07:48:39.575340
3412 07:48:39.575582
3413 07:48:39.575823
3414 07:48:39.577496 Setting prompt string to ['grub>', 'error: missing (.*) symbol.']
3415 07:48:39.577856 Sending with 10 millisecond of delay
3417 07:48:54.009093 grub> linux (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/nfs rw nfsroot=192.168.101.1:/var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a,tcp,hard,vers=3 ip=:::::eth0:dhcp
3418 07:48:54.020008 bootloader-commands: Wait for prompt ['grub>', 'error: missing (.*) symbol.'] (timeout 00:02:41)
3419 07:48:54.020855 [09;07Hl[09;08H[09;08Hi[09;09H[09;09Hn[09;10H[09;10Hu[09;11H[09;11Hx[09;12H[09;12H [09;13H[09;13H([09;14H[09;14Ht[09;15H[09;15Hf[09;16H[09;16Ht[09;17H[09;17Hp[09;18H[09;18H,[09;19H[09;19H1[09;20H[09;20H9[09;21H[09;21H2[09;22H[09;22H.[09;23H[09;23H1[09;24H[09;24H6[09;25H[09;25H8[09;26H[09;26H.[09;27H[09;27H1[09;28H[09;28H0[09;29H[09;29H1[09;30H[09;30H.[09;31H[09;31H1[09;32H[09;32H)[09;33H[09;33H/[09;34H[09;34H9[09;35H[09;35H5[09;36H[09;36H6[09;37H[09;37H8[09;38H[09;38H0[09;39H[09;39H7[09;40H[09;40H9[09;41H[09;41H/[09;42H[09;42Ht[09;43H[09;43Hf[09;44H[09;44Ht[09;45H[09;45Hp[09;46H[09;46H-[09;47H[09;47Hd[09;48H[09;48He[09;49H[09;49Hp[09;50H[09;50Hl[09;51H[09;51Ho[09;52H[09;52Hy[09;53H[09;53H-[09;54H[09;54H6[09;55H[09;55He[09;56H[09;56Hd[09;57H[09;57Hn[09;58H[09;58Hs[09;59H[09;59Hw[09;60H[09;60He[09;61H[09;61H7[09;62H[09;62H/[09;63H[09;63Hk[09;64H[09;64He[09;65H[09;65Hr[09;66H[09;66Hn[09;67H[09;67He[09;68H[09;68Hl[09;69H[09;69H/[09;70H[09;70HI[09;71H[09;71Hm[09;72H[09;72Ha[09;73H[09;73Hg[09;74H[09;74He[09;75H[09;75H [09;76H[09;76Hp[09;77H[09;77Hc[09;78H[09;78Hi[09;79H[09;79He
3420 07:48:54.021164
3421 07:48:54.021518 [09;80H[09;80H_
3422 07:48:54.021843
3423 07:48:54.022146 [10;01H[10;01Ha[10;02H[10;02Hs[10;03H[10;03Hp[10;04H[10;04Hm[10;05H[10;05H=[10;06H[10;06Ho[10;07H[10;07Hf[10;08H[10;08Hf[10;09H[10;09H [10;10H[10;10Hp[10;11H[10;11Hc[10;12H[10;12Hi[10;13H[10;13H=[10;14H[10;14Hp[10;15H[10;15Hc[10;16H[10;16Hi[10;17H[10;17He[10;18H[10;18H_[10;19H[10;19Hb[10;20H[10;20Hu[10;21H[10;21Hs[10;22H[10;22H_[10;23H[10;23Hp[10;24H[10;24He[10;25H[10;25Hr[10;26H[10;26Hf[10;27H[10;27H [10;28H[10;28Hr[10;29H[10;29Ho[10;30H[10;30Ho[10;31H[10;31Ht[10;32H[10;32H=[10;33H[10;33H/[10;34H[10;34Hd[10;35H[10;35He[10;36H[10;36Hv[10;37H[10;37H/[10;38H[10;38Hn[10;39H[10;39Hf[10;40H[10;40Hs[10;41H[10;41H [10;42H[10;42Hr[10;43H[10;43Hw[10;44H[10;44H [10;45H[10;45Hn[10;46H[10;46Hf[10;47H[10;47Hs[10;48H[10;48Hr[10;49H[10;49Ho[10;50H[10;50Ho[10;51H[10;51Ht[10;52H[10;52H=[10;53H[10;53H1[10;54H[10;54H9[10;55H[10;55H2[10;56H[10;56H.[10;57H[10;57H1[10;58H[10;58H6[10;59H[10;59H8[10;60H[10;60H.[10;61H[10;61H1[10;62H[10;62H0[10;63H[10;63H1[10;64H[10;64H.[10;65H[10;65H1[10;66H[10;66H:[10;67H[10;67H/[10;68H[10;68Hv[10;69H[10;69Ha[10;70H[10;70Hr[10;71H[10;71H/[10;72H[10;72Hl[10;73H[10;73Hi[10;74H[10;74Hb[10;75H[10;75H/[10;76H[10;76Hl[10;77H[10;77Ha[10;78H[10;78Hv[10;79H[10;79Ha
3424 07:48:54.022835
3425 07:48:54.023137 [10;80H[10;80H/
3426 07:48:54.023417
3427 07:48:54.023729 [11;01H[11;01Hd[11;02H[11;02Hi[11;03H[11;03Hs[11;04H[11;04Hp[11;05H[11;05Ha[11;06H[11;06Ht[11;07H[11;07Hc[11;08H[11;08Hh[11;09H[11;09He[11;10H[11;10Hr[11;11H[11;11H/[11;12H[11;12Ht[11;13H[11;13Hm[11;14H[11;14Hp[11;15H[11;15H/[11;16H[11;16H9[11;17H[11;17H5[11;18H[11;18H6[11;19H[11;19H8[11;20H[11;20H0[11;21H[11;21H7[11;22H[11;22H9[11;23H[11;23H/[11;24H[11;24He[11;25H[11;25Hx[11;26H[11;26Ht[11;27H[11;27Hr[11;28H[11;28Ha[11;29H[11;29Hc[11;30H[11;30Ht[11;31H[11;31H-[11;32H[11;32Hn[11;33H[11;33Hf[11;34H[11;34Hs[11;35H[11;35Hr[11;36H[11;36Ho[11;37H[11;37Ho[11;38H[11;38Ht[11;39H[11;39Hf[11;40H[11;40Hs[11;41H[11;41H-[11;42H[11;42H1[11;43H[11;43Hn[11;44H[11;44H9[11;45H[11;45Hu[11;46H[11;46Hw[11;47H[11;47H7[11;48H[11;48H9[11;49H[11;49Ha[11;50H[11;50H,[11;51H[11;51Ht[11;52H[11;52Hc[11;53H[11;53Hp[11;54H[11;54H,[11;55H[11;55Hh[11;56H[11;56Ha[11;57H[11;57Hr[11;58H[11;58Hd[11;59H[11;59H,[11;60H[11;60Hv[11;61H[11;61He[11;62H[11;62Hr[11;63H[11;63Hs[11;64H[11;64H=[11;65H[11;65H3[11;66H[11;66H [11;67H[11;67Hi[11;68H[11;68Hp[11;69H[11;69H=[11;70H[11;70H:[11;71H[11;71H:[11;72H[11;72H:[11;73H[11;73H:[11;74H[11;74H:[11;75H[11;75He[11;76H[11;76Ht[11;77H[11;77Hh[11;78H[11;78H0[11;79H[11;79H:
3428 07:48:54.024093
3429 07:48:54.024473 [11;80H[11;80Hd
3430 07:48:54.024765
3431 07:48:54.124363 [12;01H[12;01Hh[12;02H[12;02Hc[12;03H[12;03Hp[12;04H
3432 07:51:11.736414
3433 07:51:11.738878 Sending with 10 millisecond of delay
3435 07:51:16.516461 grub> devicetree (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/dtb/hip07-d05.dtb
3436 07:51:16.527399 bootloader-commands: Wait for prompt ['grub>', 'error: missing (.*) symbol.'] (timeout 00:00:19)
3437 07:51:16.528278 [13;07Hd[13;08H[13;08He[13;09H[13;09Hv[13;10H[13;10Hi[13;11H[13;11Hc[13;12H[13;12He[13;13H[13;13Ht[13;14H[13;14Hr[13;15H[13;15He[13;16H[13;16He[13;17H[13;17H [13;18H[13;18H([13;19H[13;19Ht[13;20H[13;20Hf[13;21H[13;21Ht[13;22H[13;22Hp[13;23H[13;23H,[13;24H[13;24H1[13;25H[13;25H9[13;26H[13;26H2[13;27H[13;27H.[13;28H[13;28H1[13;29H[13;29H6[13;30H[13;30H8[13;31H[13;31H.[13;32H[13;32H1[13;33H[13;33H0[13;34H[13;34H1[13;35H[13;35H.[13;36H[13;36H1[13;37H[13;37H)[13;38H[13;38H/[13;39H[13;39H9[13;40H[13;40H5[13;41H[13;41H6[13;42H[13;42H8[13;43H[13;43H0[13;44H[13;44H7[13;45H[13;45H9[13;46H[13;46H/[13;47H[13;47Ht[13;48H[13;48Hf[13;49H[13;49Ht[13;50H[13;50Hp[13;51H[13;51H-[13;52H[13;52Hd[13;53H[13;53He[13;54H[13;54Hp[13;55H[13;55Hl[13;56H[13;56Ho[13;57H[13;57Hy[13;58H[13;58H-[13;59H[13;59H6[13;60H[13;60He[13;61H[13;61Hd[13;62H[13;62Hn[13;63H[13;63Hs[13;64H[13;64Hw[13;65H[13;65He[13;66H[13;66H7[13;67H[13;67H/[13;68H[13;68Hd[13;69H[13;69Ht[13;70H[13;70Hb[13;71H[13;71H/[13;72H[13;72Hh[13;73H[13;73Hi[13;74H[13;74Hp[13;75H[13;75H0[13;76H[13;76H7[13;77H[13;77H-[13;78H[13;78Hd[13;79H[13;79H0
3438 07:51:16.528888
3439 07:51:16.529323 [13;80H[13;80H5
3440 07:51:16.529747
3441 07:51:16.721628 [14;01H[14;01H.[14;02H[14;02Hd[14;03H[14;03Ht[14;04H[14;04Hb[14;05H
3442 07:51:16.771998
3443 07:51:16.772828 Sending with 10 millisecond of delay
3445 07:51:17.065970 grub> boot
3446 07:51:17.077083 end: 2.6 bootloader-commands (duration 00:04:04) [common]
3447 07:51:17.077524 start: 2.7 auto-login-action (timeout 00:00:18) [common]
3448 07:51:17.077894 Setting prompt string to ['Linux version [0-9]']
3449 07:51:17.078178 boot_message is being deprecated in favour of kernel-start-message in constants
3450 07:51:17.078588 Setting prompt string to ['Linux version']
3451 07:51:17.078861 Setting prompt string to ['Linux version', 'error: missing (.*) symbol.']
3452 07:51:17.079129 auto-login-action: Wait for prompt ['Linux version', 'error: missing (.*) symbol.'] (timeout 00:05:00)
3453 07:51:17.143187 [15;07Hb[15;08H[15;08Ho[15;09H[15;09Ho[15;10H[15;10Ht[15;11H
3454 07:51:17.572162
3455 07:51:17.572731 EFI stub: Booting Linux Kernel...
3456 07:51:17.641653 EFI stub: Using DTB from configuration table
3457 07:51:17.642037 EFI stub: Exiting boot services and installing virtual address map...
3458 07:51:17.661576 [SAL_ClearAffiliationSMP,325]it is going to hard reset dev:0x500E004AAAAAAA1F
3459 07:51:17.682822 [SAL_ClearAffiliationSMP,325]it is going to hard reset dev:0x500E004AAAAAAA1F
3460 07:51:17.683353 SAS ExitBootServicesEvent
3461 07:51:17.683830 GMAC ExitBootServicesEvent
3462 07:51:17.684322 GMAC ExitBootServicesEvent
3463 07:51:17.684637 GMAC ExitBootServicesEvent
3464 07:51:17.684947 GMAC ExitBootServicesEvent
3465 07:51:17.771685 OHCI ExitBootServicesEvent
3466 07:51:17.772387 IPMI ExitBootService Event
3467 07:51:17.772752 TransferSmbiosToBMC EVENT.
3468 07:51:17.961713 Transfer Smbios Table To iBMC Success.
3469 07:51:17.962081 GetVariable Status : Not Found.
3471 07:51:35.078674 end: 2.7 auto-login-action (duration 00:00:18) [common]
3473 07:51:35.079928 grub-main-action failed: 1 of 3 attempts. 'auto-login-action timed out after 18 seconds'
3475 07:51:35.081047 end: 2 grub-main-action (duration 00:05:00) [common]
3477 07:51:35.082407 Cleaning after the job
3478 07:51:35.082957 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/ramdisk
3479 07:51:35.087167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/kernel
3480 07:51:35.091908 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/dtb
3481 07:51:35.092342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/nfsrootfs
3482 07:51:35.116419 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9568079/tftp-deploy-6ednswe7/modules
3483 07:51:35.120103 start: 4.1 power-off (timeout 00:00:30) [common]
3484 07:51:35.120499 Calling: 'nice' '/usr/local/bin/d05-power.sh' 'hip07-d05-cbg-0-bmc' 'off'
3485 07:51:35.393008 >> Chassis Power Control: Down/Off
3486 07:51:45.402167 Returned 0 in 10 seconds
3487 07:51:45.503996 end: 4.1 power-off (duration 00:00:10) [common]
3489 07:51:45.505695 start: 4.2 read-feedback (timeout 00:09:50) [common]
3490 07:51:45.507344 Listened to connection for namespace 'common' for up to 1s
3492 07:51:45.509161 Listened to connection for namespace 'common' for up to 1s
3493 07:51:46.511753 Finalising connection for namespace 'common'
3494 07:51:46.512458 Disconnecting from shell: Finalise
3495 07:51:46.512727
3496 07:51:46.614301 end: 4.2 read-feedback (duration 00:00:01) [common]
3497 07:51:46.615052 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9568079
3498 07:51:48.093442 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9568079
3499 07:51:48.093978 JobError: Your job cannot terminate cleanly.