Info: SOL payload already de-activated Never mind [SOL Session operational. Use ~? for help] [serdes_init]:SerDes0 init success! [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 5G [serdes_cs_hw_calibration_optionV2_exec]:Macro1 CS1 LC Vco Cal done!(LCVCOCALDONE) in 0ms [SerdesCsCalib]:Macro1 CS1 PLL lock success!(0 ms) [serdes_init]:SerDes1 init success! Continue to dreset PCS Continue to dreset HLLC Continue to open PCS RX Wait for HLLC Training........OK Wait for HLLC1 Training........OK Wait for S1 HLLC Training........OK Wait for S1 HLLC1 Training........OK Open Secondary socket Window Djtag secondary 0x4004001d818 and 0x400d000d818 init Macro 0 Download Firmware Success!! Macro 1 Download Firmware Success!! Macro 0 Download Firmware Success!! Macro 1 Download Firmware Success!! [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit Halt Macro 0 MCU!! Release Macro 0 MCU!! Temperature: 27 (0x1B) [serdes_init]:SerDes0 init success! [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit Halt Macro 1 MCU!! Release Macro 1 MCU!! Temperature: 27 (0x1B) [serdes_init]:SerDes1 init success! [serdes_hilink0_init]:hilink0_mode hccs1 8 lane 16 bit Halt Macro 0 MCU!! Release Macro 0 MCU!! Temperature: 27 (0x1B) [serdes_init]:SerDes0 init success! [serdes_hilink1_init]:hilink1_mode hccs0 8 lane 16 bit Halt Macro 1 MCU!! Release Macro 1 MCU!! Temperature: 27 (0x1B) [serdes_init]:SerDes1 init success! Continue to dreset PCS Continue to dreset HLLC Continue to Enable CTLE Continue to open PCS RX Wait for HLLC Training........OK Wait for HLLC1 Training........OK Wait for S1 HLLC Training........OK Wait for S1 HLLC1 Training........OK S0 HLLC0 Interrupt status(0x4) = 0x0 S0 HLLC1 Interrupt status(0x4) = 0x0 S1 HLLC0 Interrupt status(0x4) = 0x0 S1 HLLC1 Interrupt status(0x4) = 0x0 Config Secondary socket Open Secondary socket Window close NB CS2 to PA Config socket0 NA PA Enable socket0 PA 2+2 Mode Config Secondary socket PA clean S0 remap for PA....Done clean remap for PA....Done Enable socket1 PA 2+2 Mode Djtag Secondary 0x4006001d818 Init S1 Preinit S1 Preinit End Config Secondary socket AA&LLC close S1 NB CS2 to PA OK1OK2OK3Djtag Secondary 0x408d000d818 Init Visit S1 NB Visit S1 NB DONE S1 NA PCIE clean remap.........Done S1 NA PCIE MEM CONFIG.........Done S1 NB PCIE clean remap.........Done S1 NB PCIE MEM CcONFIG.........Done NB/TB PLL Init TB PLL init....OK NB PLL init....OK [LPC] S1 MBIGEN CONFIG Done add-symbol-file /home/s00296804/Edk2/Build/D05Source/RELEASE_GCC49/AARCH64/HwPkg/Override/ArmPlatformPkg/Sec/Sec/DEBUG/ArmPlatformSec.dll 0xA4801800 Trust Zone Configuration is disabled Boot firmware (version Hisilicon D05 UEFI 16.12 Release built at 05/15/2017 07:53) init BMC. TempVer:0x20 GetDeviceId return Success GetVariable Not Found! Get Default Setup Configration &&&Now config iBMC BIOS WDT [action:0 countdown:3928 timeruse 2! Memory Init PEIM Loaded GetVariable Not Found! Get Default Setup Configration ------------------- Start RegisterTest: RegisterTest OK! ------------------- socket[0] Totem B I2C0 init ok. socket[0] Totem B I2C1 init ok. socket[1] Totem B I2C0 init ok. socket[1] Totem B I2C1 init ok. socket[0] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[0][0].Dimm[0].DramWidth : X4 pGblData->Channel[0][0].Dimm[0].RankNum : 2 pGblData->Channel[0][0].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[0][0].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[0] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[0] Channel[0] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[0][0].RankPresent : 0x3 socket[0] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[0][1].Dimm[0].DramWidth : X4 pGblData->Channel[0][1].Dimm[0].RankNum : 2 pGblData->Channel[0][1].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[0][1].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[0] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[0] Channel[1] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[0][1].RankPresent : 0x3 socket[0] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[0][2].Dimm[0].DramWidth : X4 pGblData->Channel[0][2].Dimm[0].RankNum : 2 pGblData->Channel[0][2].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[0][2].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[0] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[0] Channel[2] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[0][2].RankPresent : 0x3 socket[0] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[0][3].Dimm[0].DramWidth : X4 pGblData->Channel[0][3].Dimm[0].RankNum : 2 pGblData->Channel[0][3].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[0][3].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[0] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[0] Channel[3] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[0][3].RankPresent : 0x3 socket[1] channel[0] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x54 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_F0].Dimm[0].DramWidth : X4 pGblData->Channel[1][0].Dimm[0].RankNum : 2 pGblData->Channel[1][0].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[1][0].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[1] channel[0] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x55 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[1] Channel[0] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[1][0].RankPresent : 0x3 socket[1] channel[1] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x54 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[1][1].Dimm[0].DramWidth : X4 pGblData->Channel[1][1].Dimm[0].RankNum : 2 pGblData->Channel[1][1].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[1][1].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[1] channel[1] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x55 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[1] Channel[1] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[1][1].RankPresent : 0x3 socket[1] channel[2] dimm[0] read from SPD, I2C Port:1 SlaveAddr:0x50 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[1][2].Dimm[0].DramWidth : X4 pGblData->Channel[1][2].Dimm[0].RankNum : 2 pGblData->Channel[1][2].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[1][2].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[1] channel[2] dimm[1] read from SPD, I2C Port:1 SlaveAddr:0x51 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[1] Channel[2] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[1][2].RankPresent : 0x3 socket[1] channel[3] dimm[0] read from SPD, I2C Port:0 SlaveAddr:0x50 --------------------------------------------------------------------- SPD_KEY_BYTE : DDR4 SPD_KEY_BYTE2 : RDIMM SPD_MODULE_ORG_DDR4 : 0x8 SPD_MIN_TCK_DDR4 : 0x7 SPD_MAX_TCK_DDR4 : 0xD SPD_FTB_MIN_TCK_DDR4 : 0xD6 DimmMaxFreq : 2401Mbps pGblData->Channel[1][3].Dimm[0].DramWidth : X4 pGblData->Channel[1][3].Dimm[0].RankNum : 2 pGblData->Channel[1][3].Dimm[0].ddrFreq : 2400Mbps pGblData->Channel[1][3].Dimm[0].minTck : 8330 --------------------------------------------------------------------- socket[1] channel[3] dimm[1] read from SPD, I2C Port:0 SlaveAddr:0x51 --------------------------------------------------------------------- SPD_KEY_BYTE : Empty Socket[1] Channel[3] Dimm[1] is empty. --------------------------------------------------------------------- pGblData->Channel[1][3].RankPresent : 0x3 DimmMaxFreq : 2401Mbps GblData->Freq : 2400 GblData->Tck : 8333 GblData->DdrFreqIdx : 13 Check dimm status ok! pGblData->MaxSPCNum = 2 skt[0] ch[0] maxPORFreqIdx = 13 skt[0] ch[1] maxPORFreqIdx = 13 skt[0] ch[2] maxPORFreqIdx = 13 skt[0] ch[3] maxPORFreqIdx = 13 skt[1] ch[0] maxPORFreqIdx = 13 skt[1] ch[1] maxPORFreqIdx = 13 skt[1] ch[2] maxPORFreqIdx = 13 skt[1] ch[3] maxPORFreqIdx = 13 --------------------------------------------------------------------- --------------------------------------------------------------------- PORFreqTable result(max system ddr frequency): pGblData->DdrFreqIdx = 13 pGblData->DevParaFreqIdx = 13 pGblData->Tck = 8333 pGblData->Freq = 2400 --------------------------------------------------------------------- --------------------------------------------------------------------- Set ddr frequency ok! Get dimm spd information socket[0] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 0 0 0 0x5 BGNum 0 0 0 4 BankNum 0 0 0 16 ColBits 0 0 0 10 RowBits 0 0 0 17 SpdMirror 0 0 0 1 SpdVdd 0 0 0 3 PrimaryBusWidth 0 0 0 64 ExtensionBusWidth 0 0 0 8 RankSize 0 0 0 163 SpdMMDate 0 0 0 0x2817 SpdSerialNum 0 0 0 0x4F82936 SpdMinTRCD 0 0 0 0x6E SpdMinTRCDFtb 0 0 0 0x0 nRCD 0 0 0 0x35B6 SpdMinTRRDL 0 0 0 0x28 SpdMinTRRD 0 0 0 0x1B SpdMinTRAS 0 0 0 0x100 SpdMinTRC 0 0 0 0x16E SpdMinTRCFtb 0 0 0 0x0 SpdMinTRFC 0 0 0 0xAF0 SpdMinTAA 0 0 0 0x6E SpdMinTAAFtb 0 0 0 0x0 SpdMinTFAW 0 0 nRP 0 0 0 0x35B6 SpdMinTCCDL 0 0 0 0x28 SpdMinTCCDLFtb 0 0 0 0x0 SpdModuleAttr 0 0 0 0x0 SpdAddrMap 0 0 0 0x1 --------------------------------------------------------------------- socket[0] channel[0] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 0 0 0ps nRCD 0 0 13750ps nRRDL 0 0 4900ps nRRD 0 0 3300ps nRAS 0 0 32000ps nRC 0 0 45750ps nRFC 0 0 350000ps nWTR 0 0 0ps nRTP 0 0 0ps nAA 0 0 13750ps nFAW 0 0 13000ps nRP 0 0 13750ps nCCDL 0 0 5000ps --------------------------------------------------------------------- socket[0] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 0 1 0 0x5 BGNum 0 1 0 4 BankNum 0 1 0 16 ColBits 0 1 0 10 RowBits 0 1 0 17 SpdMirror 0 1 0 1 SpdVdd 0 1 0 3 PrimaryBusWidth 0 1 0 64 ExtensionBusWidth 0 1 0 8 RankSize 0 1 0 16384 SpdRMId 0 1 0 0x3206 SpdMMfgId 0 1 0 0xCE00 SpdMMDate 0 1 0 0x2817 SpdSerialNum 0 1 0 0xE3F82936 SpdMinTRCD 0 1 0 0x6E SpdMinTRCDFtb 0 1 0 0x0 nRCD 0 1 0 0x35B6 SpdMinTRRDL 0 1 0 0x28 SpdMinTRRD 0 1 0 0x1B SpdMinTRAS 0 1 0 0x100 SpdMinTRC 0 1 0 0x16E SpdMinTRCFtb 0 1 0 0x0 SpdMinTRFC 0 1 0 0xAF0 SpdMinTAA 0 1 0 0x6E SpdMinTAAFtb 0 1 0 0x0 SpdMinTFAW 0 1 0 0x68 SpdMinTRP 0 1 0 0x6E SpdMinTRPFtb 0 1 0 0x0 nRP 0 1 0 0x35B6 SpdMinTCCDL 0 1 0 0x28 SpdMinTCCDLFtb 0 1 0 0x0 SpdModuleAttr 0 1 0 0x0 SpdAddrMap 0 1 0 0x1 --------------------------------------------------------------------- socket[0] channel[1] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 0 1 0ps nRCD 0 1 13750ps nRRDL 0 1 4900ps nRRD 0 1 3300ps nRAS 0 1 32000ps nRC 0 1 45750ps nRFC 0 1 350000ps nWTR 0 1 0ps nRTP 0 1 0ps nAA 0 1 13750ps nFAW 0 1 13000ps nRP 0 1 13750ps nCCDL 0 1 5000ps --------------------------------------------------------------------- socket[0] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 0 2 0 0x5 BGNum 0 2 0 4 BankNum 0 2 0 16 ColBits 0 2 0 10 RowBits 0 2 0 17 SpdMirror 0 2 0 1 SpdVdd 0 2 0 3 PrimaryBusWidth 0 2 0 64 ExtensionBusWidth 0 2 0 8 RankSize 0 2 0 16384 SpdRMId 0 2 0 0x3206 SpdMMfgId 0 2 0 0xCE00 SpdMMDate 0 2 0 0x2817 SpdSerialNum 0 2 0 0xDFF32936 SpdMinTRCD 0 2 0 0x6E SpdMinTRCDFtb 0 2 0 0x0 nRCD 0 2 0 0x35B6 SpdMinTRRDL 0 2 0 0x28 SpdMinTRRD 0 2 0 0x1B SpdMinTRAS 0 2 0 0x100 SpdMinTRC 0 2 0 0x16E SpdMinTRCFtb 0 2 0 0x0 SpdMinTRFC 0 2 0 0xAF0 SpdMinTAA 0 2 0 0x6E SpdMinTAAFtb 0 2 0 0x0 SpdMinTFAW 0 2 0 0x68 SpdMinTRP 0 2 0 0x6E SpdMinTRPFtb 0 2 0 0x0 nRP 0 2 0 0x35B6 SpdMinTCCDL 0 2 0 0x28 SpdMinTCCDLFtb 0 2 0 0x0 SpdModuleAttr 0 2 0 0x0 SpdAddrMap 0 2 0 0x1 --------------------------------------------------------------------- socket[0] channel[2] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 0 2 0ps nRCD 0 2 13750ps nRRDL 0 2 4900ps nRRD 0 2 3300ps nRAS 0 2 32000ps nRC 0 2 45750ps nRFC 0 2 350000ps nWTR 0 2 0ps nRTP 0 2 0ps nAA 0 2 13750ps nFAW 0 2 13000ps nRP 0 2 13750ps nCCDL 0 2 5000ps --------------------------------------------------------------------- socket[0] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 0 3 0 0x5 BGNum 0 3 0 4 BankNum 0 3 0 16 ColBits 0 3 0 10 RowBits 0 3 0 17 SpdMirror 0 3 0 1 SpdVdd 0 3 0 3 PrimaryBusWidth 0 3 0 64 ExtensionBusWidth 0 3 0 8 RankSize 0 3 0 16384 SpdRMId 0 3 0 0x3206 SpdMMfgId 0 3 0 0xCE00 SpdMMDate 0 3 0 0x2817 SpdSerialNum 0 3 0 0xF5F02936 SpdMinTRCD 0 3 0 0x6E SpdMinTRCDFtb 0 3 0 0x0 nRCD 0 3 0 0x35B6 SpdMinTRRDL 0 3 0 0x28 SpdMinTRRD 0 3 0 0x1B SpdMinTRAS 0 3 0 0x100 SpdMinTRC 0 3 0 0x16E SpdMinTRCFtb 0 3 0 0x0 SpdMinTRFC 0 3 0 0xAF0 SpdMinTAA 0 3 0 0x6E SpdMinTAAFtb 0 3 0 0x0 SpdMinTFAW 0 3 0 0x68 SpdMinTRP 0 3 0 0x6E SpdMinTRPFtb 0 3 0 0x0 nRP 0 3 0 0x35B6 SpdMinTCCDL 0 3 0 0x28 SpdMinTCCDLFtb 0 3 0 0x0 SpdModuleAttr 0 3 0 0x0 SpdAddrMap 0 3 0 0x1 --------------------------------------------------------------------- socket[0] channel[3] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 0 3 0ps nRCD 0 3 13750ps nRRDL 0 3 4900ps nRRD 0 3 3300ps nRAS 0 3 32000ps nRC 0 3 45750ps nRFC 0 3 350000ps nWTR 0 3 0ps nRTP 0 3 0ps nAA 0 3 13750ps nFAW 0 3 13000ps nRP 0 3 13750ps nCCDL 0 3 5000ps --------------------------------------------------------------------- socket[1] channel[0] dimm[0] i2c port[1] slaveAddr[0x54] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 1 0 0 0x5 BGNum 1 0 0 4 BankNum 1 0 0 16 ColBits 1 0 0 10 RowBits 1 0 0 17 SpdMirror 1 0 0 1 SpdVdd 1 0 0 3 PrimaryBusWidth 1 0 0 64 ExtensionBusWidth 1 0 0 8 RankSize 1 0 0 16384 SpdRMId 1 0 0 0x3206 SpdMMfgId 1 0 0 0xCE00 SpdMMDate 1 0 0 0x2817 SpdSerialNum 1 0 0 0xE2F32936 SpdMinTRCD 1 0 0 0x6E SpdMinTRCDFtb 1 0 0 0x0 nRCD 1 0 0 0x35B6 SpdMinTRRDL 1 0 0 0x28 SpdMinTRRD 1 0 0 0x1B SpdMinTRAS 1 0 0 0x100 SpdMinTRC 1 0 0 0x16E SpdMinTRCFtb 1 0 0 0x0 SpdMinTRFC 1 0 0 0xAF0 SpdMinTAA 1 0 0 0x6E SpdMinTAAFtb 1 0 0 0x0 SpdMinTFAW 1 0 0 0x68 SpdMinTRP 1 0 0 0x6E SpdMinTRPFtb 1 0 0 0x0 nRP 1 0 0 0x35B6 SpdMinTCCDL 1 0 0 0x28 SpdMinTCCDLFtb 1 0 0 0x0 SpdModuleAttr 1 0 0 0x0 SpdAddrMap 1 0 0 0x1 --------------------------------------------------------------------- socket[1] channel[0] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 1 0 0ps nRCD 1 0 13750ps nRRDL 1 0 4900ps nRRD 1 0 3300ps nRAS 1 0 32000ps nRC 1 0 45750ps nRFC 1 0 350000ps nWTR 1 0 0ps nRTP 1 0 0ps nAA 1 0 13750ps nFAW 1 0 13000ps nRP 1 0 13750ps nCCDL 1 0 5000ps --------------------------------------------------------------------- socket[1] channel[1] dimm[0] i2c port[0] slaveAddr[0x54] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 AA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 1 1 0 0x5 BGNum 1 1 0 4 BankNum 1 1 0 16 ColBits 1 1 0 10 RowBits 1 1 0 17 SpdMirror 1 1 0 1 SpdVdd 1 1 0 3 PrimaryBusWidth 1 1 0 64 ExtensionBusWidth 1 1 0 8 RankSize 1 1 0 16384 SpdRMId 1 1 0 0x3206 SpdMMfgId 1 1 0 0xCE00 SpdMMDate 1 1 0 0x2817 SpdSerialNum 1 1 0 0x9AF22936 SpdMinTRCD 1 1 0 0x6E SpdMinTRCDFtb 1 1 0 0x0 nRCD 1 1 0 0x35B6 SpdMinTRRDL 1 1 0 0x28 SpdMinTRRD 1 1 0 0x1B SpdMinTRAS 1 1 0 0x100 SpdMinTRC 1 1 0 0x16E SpdMinTRCFtb 1 1 0 0x0 SpdMinTRFC 1 1 0 0xAF0 SpdMinTAA 1 1 0 0x6E SpdMinTAAFtb 1 1 0 0x0 SpdMinTFAW 1 1 0 0x68 SpdMinTRP 1 1 0 0x6E SpdMinTRPFtb 1 1 0 0x0 nRP 1 1 0 0x35B6 SpdMinTCCDL 1 1 0 0x28 SpdMinTCCDLFtb 1 1 0 0x0 SpdModuleAttr 1 1 0 0x0 SpdAddrMap 1 1 0 0x1 --------------------------------------------------------------------- socket[1] channel[1] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 1 1 0ps nRCD 1 1 13750ps nRRDL 1 1 4900ps nRRD 1 1 3300ps nRAS 1 1 32000ps nRC 1 1 45750ps nRFC 1 1 350000ps nWTR 1 1 0ps nRTP 1 1 0ps nAA 1 1 13750ps nFAW 1 1 13000ps nRP 1 1 13750ps nCCDL 1 1 5000ps --------------------------------------------------------------------- socket[1] channel[2] dimm[0] i2c port[1] slaveAddr[0x50] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 1 2 0 0x5 BGNum 1 2 0 4 BankNum 1 2 0 16 ColBits 1 2 0 10 RowBits 1 2 0 17 SpdMirror 1 2 0 1 SpdVdd 1 2 0 3 PrimaryBusWidth 1 2 0 64 ExtensionBusWidth 1 2 0 8 RankSize 1 2 0 16384 SpdRMId 1 2 0 0x3206 SpdMMfgId 1 2 0 0xCE00 SpdMMDate 1 2 0 0x2817 SpdSerialNum 1 2 0 0x9BF22936 SpdMinTRCD 1 2 0 0x6E SpdMinTRCDFtb 1 2 0 0x0 nRCD 1 2 0 0x35B6 SpdMinTRRDL 1 2 0 0x28 SpdMinTRRD 1 2 0 0x1B SpdMinTRAS 1 2 0 0x100 SpdMinTRC 1 2 0 0x16E SpdMinTRCFtb 1 2 0 0x0 SpdMinTRFC 1 2 0 0xAF0 SpdMinTAA 1 2 0 0x6E SpdMinTAAFtb 1 2 0 0x0 SpdMinTFAW 1 2 0 0x68 SpdMinTRP 1 2 0 0x6E SpdMinTRPFtb 1 2 0 0x0 nRP 1 2 0 0x35B6 SpdMinTCCDL 1 2 0 0x28 SpdMinTCCDLFtb 1 2 0 0x0 SpdModuleAttr 1 2 0 0x0 SpdAddrMap 1 2 0 0x1 --------------------------------------------------------------------- socket[1] channel[2] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 1 2 0ps nRCD 1 2 13750ps nRRDL 1 2 4900ps nRRD 1 2 3300ps nRAS 1 2 32000ps nRC 1 2 45750ps nRFC 1 2 350000ps nWTR 1 2 0ps nRTP 1 2 0ps nAA 1 2 13750ps nFAW 1 2 13000ps nRP 1 2 13750ps nCCDL 1 2 5000ps --------------------------------------------------------------------- socket[1] channel[3] dimm[0] i2c port[0] slaveAddr[0x50] SPD information: SPD_MIN_TRCD_DDR4: 0x6E SPD_FTB_TRCD_DDR4: 0x0 SPD_MIN_TRRDL_DDR4: 0x28 SPD_FTB_TRRDL_DDR4: 0x9C SPD_MIN_TRRDS_DDR4: 0x1B SPD_FTB_TRRDS_DDR4: 0xB5 SPD_EXT_TRC_TRAS_DDR4: 0x11 SPD_MIN_TRAS_DDR4: 0x0 SPD_MIN_TRC_DDR4: 0x6E SPD_FTB_TRC_DDR4: 0x0 SPD_MIN_TRFC1_MSB_DDR4: 0xA SPD_MIN_TRFC1_LSB_DDR4: 0xF0 tRFC: 0xAF0 tempCkNum: 0x55730 SPD_MIN_TAA_DDR4: 0x6E SPD_FTB_TAA: 0x0 SPD_TFAW_UPPER_DDR4: 0x0 SPD_MIN_TFAW_DDR4: 0x68 SPD_MIN_TRP_DDR4: 0x6E SPD_FTB_TRP_DDR4: 0x0 SPD_MIN_TCCDL_DDR4: 0x28 SPD_FTB_TCCDL_DDR4: 0x0 --------------------------------------------------------------------- pGblData item skt ch dimm value --------------------------------------------------------------------- SDRAMCapacity 1 3 0 0x5 BGNum 1 3 0 4 BankNum 1 3 0 16 ColBits 1 3 0 10 RowBits 1 3 0 17 SpdMirror 1 3 0 1 SpdVdd 1 3 0 3 PrimaryBusWidth 1 3 0 64 ExtensionBusWidth 1 3 0 8 RankSize 1 3 0 16384 SpdRMId 1 3 0 0x3206 SpdMMfgId 1 3 0 0xCE00 SpdMMDate 1 3 0 0x2817 SpdSerialNum 1 3 0 0x84E82936 SpdMinTRCD 1 3 0 0x6E SpdMinTRCDFtb 1 3 0 0x0 nRCD 1 3 0 0x35B6 SpdMinTRRDL 1 3 0 0x28 SpdMinTRRD 1 3 0 0x1B SpdMinTRAS 1 3 0 0x100 SpdMinTRC 1 3 0 0x16E SpdMinTRCFtb 1 3 0 0x0 SpdMinTRFC 1 3 0 0xAF0 SpdMinTAA 1 3 0 0x6E SpdMinTAAFtb 1 3 0 0x0 SpdMinTFAW 1 3 0 0x68 SpdMinTRP 1 3 0 0x6E SpdMinTRPFtb 1 3 0 0x0 nRP 1 3 0 0x35B6 SpdMinTCCDL 1 3 0 0x28 SpdMinTCCDLFtb 1 3 0 0x0 SpdModuleAttr 1 3 0 0x0 SpdAddrMap 1 3 0 0x1 --------------------------------------------------------------------- socket[1] channel[3] SPD information: --------------------------------------------------------------------- item skt ch value --------------------------------------------------------------------- nWR 1 3 0ps nRCD 1 3 13750ps nRRDL 1 3 4900ps nRRD 1 3 3300ps nRAS 1 3 32000ps nRC 1 3 45750ps nRFC 1 3 350000ps nWTR 1 3 0ps nRTP 1 3 0ps nAA 1 3 13750ps nFAW 1 3 13000ps nRP 1 3 13750ps nCCDL 1 3 5000ps --------------------------------------------------------------------- --------------------------------------------------------------------- Socket Channel Dimm Present Rank0 Rank1 Rank2 Rank3 0 0 0 YES YES YES NOT NOT 0 0 1 NOT NOT NOT NOT NOT 0 0 2 NOT NOT NOT NOT NOT 0 1 0 YES YES YES NOT NOT 0 1 1 NOT NOT NOT NOT NOT 0 1 2 NOT NOT NOT NOT NOT 0 2 0 YES YES YES NOT NOT 0 2 1 NOT NOT NOT NOT NOT 0 2 2 NOT NOT NOT NOT NOT 0 3 0 YES YES YES NOT NOT 0 3 1 NOT NOT NOT NOT NOT 0 3 2 NOT NOT NOT NOT NOT 1 0 0 YES YES YES NOT NOT 1 0 1 NOT NOT NOT NOT NOT 1 0 2 NOT NOT NOT NOT NOT 1 1 0 YES YES YES NOT NOT 1 1 1 NOT NOT NOT NOT NOT 1 1 2 NOT NOT NOT NOT NOT 1 2 0 YES YES YES NOT NOT 1 2 1 NOT NOT NOT NOT NOT 1 2 2 NOT NOT NOT NOT NOT 1 3 0 YES YES YES NOT NOT 1 3 1 NOT NOT NOT NOT NOT 1 3 2 NOT NOT NOT NOT NOT --------------------------------------------------------------------- ********************************************************************** Socket[0] Channel[0] Base:[0x60340000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[0] channel[0] rank[0] Phy gate leveling.....OK socket[0] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[0] channel[0] rank[0] Phy write leveling.....OK socket[0] channel[0] rank[1] Phy write leveling.....OK socket[0] channel[0] rank[0] Phy write leveling 2...OK socket[0] channel[0] rank[1] Phy write leveling 2...OK socket[0] channel[0] rank[0] Read data eye training start: socket[0] channel[0] rank[0] Read data eye training end socket[0] channel[0] rank[1] Read data eye training start: socket[0] channel[0] rank[1] Read data eye training end socket[0] channel[0] rank[0] Write data eye training start: socket[0] channel[0] rank[0] Write data eye training end socket[0] channel[0] rank[1] Write data eye training start: socket[0] channel[0] rank[1] Write data eye training end socket[0] channel[0] Rx vref training start socket[0] channel[0] Rx vref training end socket[0] channel[0] rank[0] Read data eye training start: socket[0] channel[0] rank[0] Read data eye training end socket[0] channel[0] rank[1] Read data eye training start: socket[0] channel[0] rank[1] Read data eye training end socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start: socket[0] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start: socket[0] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end socket[0] channel[0] Tx vref training start socket[0] channel[0] Tx vref training end socket[0] channel[0] rank[0] Write data eye training start: socket[0] channel[0] rank[0] Write data eye training end socket[0] channel[0] rank[1] Write data eye training start: socket[0] channel[0] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[0] Channel[0] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[0] Channel[1] Base:[0x60350000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[0] channel[1] rank[0] Phy gate leveling.....OK socket[0] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[0] channel[1] rank[0] Phy write leveling.....OK socket[0] channel[1] rank[1] Phy write leveling.....OK socket[0] channel[1] rank[0] Phy write leveling 2...OK socket[0] channel[1] rank[1] Phy write leveling 2...OK socket[0] channel[1] rank[0] Read data eye training start: socket[0] channel[1] rank[0] Read data eye training end socket[0] channel[1] rank[1] Read data eye training start: socket[0] channel[1] rank[1] Read data eye training end socket[0] channel[1] rank[0] Write data eye training start: socket[0] channel[1] rank[0] Write data eye training end socket[0] channel[1] rank[1] Write data eye training start: socket[0] channel[1] rank[1] Write data eye training end socket[0] channel[1] Rx vref training start socket[0] channel[1] Rx vref training end socket[0] channel[1] rank[0] Read data eye training start: socket[0] channel[1] rank[0] Read data eye training end socket[0] channel[1] rank[1] Read data eye training start: socket[0] channel[1] rank[1] Read data eye training end socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start: socket[0] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start: socket[0] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end socket[0] channel[1] Tx vref training start socket[0] channel[1] Tx vref training end socket[0] channel[1] rank[0] Write data eye training start: socket[0] channel[1] rank[0] Write data eye training end socket[0] channel[1] rank[1] Write data eye training start: socket[0] channel[1] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[0] Channel[1] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[0] Channel[2] Base:[0x40340000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[0] channel[2] rank[0] Phy gate leveling.....OK socket[0] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 2 is set to 0x00000001 lat_adj_start of rank 1 byte 3 is set to 0x00000001 lat_adj_start of rank 1 byte 4 is set to 0x00000001 lat_adj_start of rank 1 byte 5 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[0] channel[2] rank[0] Phy write leveling.....OK socket[0] channel[2] rank[1] Phy write leveling.....OK socket[0] channel[2] rank[0] Phy write leveling 2...OK socket[0] channel[2] rank[1] Phy write leveling 2...OK socket[0] channel[2] rank[0] Read data eye training start: socket[0] channel[2] rank[0] Read data eye training end socket[0] channel[2] rank[1] Read data eye training start: socket[0] channel[2] rank[1] Read data eye training end socket[0] channel[2] rank[0] Write data eye training start: socket[0] channel[2] rank[0] Write data eye training end socket[0] channel[2] rank[1] Write data eye training start: socket[0] channel[2] rank[1] Write data eye training end socket[0] channel[2] Rx vref training start socket[0] channel[2] Rx vref training end socket[0] channel[2] rank[0] Read data eye training start: socket[0] channel[2] rank[0] Read data eye training end socket[0] channel[2] rank[1] Read data eye training start: socket[0] channel[2] rank[1] Read data eye training end socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start: socket[0] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start: socket[0] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end socket[0] channel[2] Tx vref training start socket[0] channel[2] Tx vref training end socket[0] channel[2] rank[0] Write data eye training start: socket[0] channel[2] rank[0] Write data eye training end socket[0] channel[2] rank[1] Write data eye training start: socket[0] channel[2] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[0] Channel[2] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[0] Channel[3] Base:[0x40350000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1C; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[0] channel[3] rank[0] Phy gate leveling.....OK socket[0] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 2 is set to 0x00000001 lat_adj_start of rank 1 byte 3 is set to 0x00000001 lat_adj_start of rank 1 byte 4 is set to 0x00000001 lat_adj_start of rank 1 byte 5 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[0] channel[3] rank[0] Phy write leveling.....OK socket[0] channel[3] rank[1] Phy write leveling.....OK socket[0] channel[3] rank[0] Phy write leveling 2...OK socket[0] channel[3] rank[1] Phy write leveling 2...OK socket[0] channel[3] rank[0] Read data eye training start: socket[0] channel[3] rank[0] Read data eye training end socket[0] channel[3] rank[1] Read data eye training start: socket[0] channel[3] rank[1] Read data eye training end socket[0] channel[3] rank[0] Write data eye training start: socket[0] channel[3] rank[0] Write data eye training end socket[0] channel[3] rank[1] Write data eye training start: socket[0] channel[3] rank[1] Write data eye training end socket[0] channel[3] Rx vref training start socket[0] channel[3] Rx vref training end socket[0] channel[3] rank[0] Read data eye training start: socket[0] channel[3] rank[0] Read data eye training end socket[0] channel[3] rank[1] Read data eye training start: socket[0] channel[3] rank[1] Read data eye training end socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start: socket[0] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start: socket[0] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end socket[0] channel[3] Tx vref training start socket[0] channel[3] Tx vref training end socket[0] channel[3] rank[0] Write data eye training start: socket[0] channel[3] rank[0] Write data eye training end socket[0] channel[3] rank[1] Write data eye training start: socket[0] channel[3] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[0] Channel[3] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[1] Channel[0] Base:[0x40060340000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[0] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x603480A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x603480A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x19; pvtp=0xB [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[1] channel[0] rank[0] Phy gate leveling.....OK socket[1] channel[0] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[1] channel[0] rank[0] Phy write leveling.....OK socket[1] channel[0] rank[1] Phy write leveling.....OK socket[1] channel[0] rank[0] Phy write leveling 2...OK socket[1] channel[0] rank[1] Phy write leveling 2...OK socket[1] channel[0] rank[0] Read data eye training start: socket[1] channel[0] rank[0] Read data eye training end socket[1] channel[0] rank[1] Read data eye training start: socket[1] channel[0] rank[1] Read data eye training end socket[1] channel[0] rank[0] Write data eye training start: socket[1] channel[0] rank[0] Write data eye training end socket[1] channel[0] rank[1] Write data eye training start: socket[1] channel[0] rank[1] Write data eye training end socket[1] channel[0] Rx vref training start socket[1] channel[0] Rx vref training end socket[1] channel[0] rank[0] Read data eye training start: socket[1] channel[0] rank[0] Read data eye training end socket[1] channel[0] rank[1] Read data eye training start: socket[1] channel[0] rank[1] Read data eye training end socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize start: socket[1] channel[0] rank[0] RxPerBitTrainingExmbistOptimize end socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize start: socket[1] channel[0] rank[1] RxPerBitTrainingExmbistOptimize end socket[1] channel[0] Tx vref training start socket[1] channel[0] Tx vref training end socket[1] channel[0] rank[0] Write data eye training start: socket[1] channel[0] rank[0] Write data eye training end socket[1] channel[0] rank[1] Write data eye training start: socket[1] channel[0] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[1] Channel[0] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[1] Channel[1] Base:[0x40060350000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[1] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x603580A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x603580A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1A; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[1] channel[1] rank[0] Phy gate leveling.....OK socket[1] channel[1] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[1] channel[1] rank[0] Phy write leveling.....OK socket[1] channel[1] rank[1] Phy write leveling.....OK socket[1] channel[1] rank[0] Phy write leveling 2...OK socket[1] channel[1] rank[1] Phy write leveling 2...OK socket[1] channel[1] rank[0] Read data eye training start: socket[1] channel[1] rank[0] Read data eye training end socket[1] channel[1] rank[1] Read data eye training start: socket[1] channel[1] rank[1] Read data eye training end socket[1] channel[1] rank[0] Write data eye training start: socket[1] channel[1] rank[0] Write data eye training end socket[1] channel[1] rank[1] Write data eye training start: socket[1] channel[1] rank[1] Write data eye training end socket[1] channel[1] Rx vref training start socket[1] channel[1] Rx vref training end socket[1] channel[1] rank[0] Read data eye training start: socket[1] channel[1] rank[0] Read data eye training end socket[1] channel[1] rank[1] Read data eye training start: socket[1] channel[1] rank[1] Read data eye training end socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize start: socket[1] channel[1] rank[0] RxPerBitTrainingExmbistOptimize end socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize start: socket[1] channel[1] rank[1] RxPerBitTrainingExmbistOptimize end socket[1] channel[1] Tx vref training start socket[1] channel[1] Tx vref training end socket[1] channel[1] rank[0] Write data eye training start: socket[1] channel[1] rank[0] Write data eye training end socket[1] channel[1] rank[1] Write data eye training start: socket[1] channel[1] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[1] Channel[1] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[1] Channel[2] Base:[0x40040340000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[2] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x403480A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x403480A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1C; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[1] channel[2] rank[0] Phy gate leveling.....OK socket[1] channel[2] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 2 is set to 0x00000001 lat_adj_start of rank 1 byte 3 is set to 0x00000001 lat_adj_start of rank 1 byte 4 is set to 0x00000001 lat_adj_start of rank 1 byte 5 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[1] channel[2] rank[0] Phy write leveling.....OK socket[1] channel[2] rank[1] Phy write leveling.....OK socket[1] channel[2] rank[0] Phy write leveling 2...OK socket[1] channel[2] rank[1] Phy write leveling 2...OK socket[1] channel[2] rank[0] Read data eye training start: socket[1] channel[2] rank[0] Read data eye training end socket[1] channel[2] rank[1] Read data eye training start: socket[1] channel[2] rank[1] Read data eye training end socket[1] channel[2] rank[0] Write data eye training start: socket[1] channel[2] rank[0] Write data eye training end socket[1] channel[2] rank[1] Write data eye training start: socket[1] channel[2] rank[1] Write data eye training end socket[1] channel[2] Rx vref training start socket[1] channel[2] Rx vref training end socket[1] channel[2] rank[0] Read data eye training start: socket[1] channel[2] rank[0] Read data eye training end socket[1] channel[2] rank[1] Read data eye training start: socket[1] channel[2] rank[1] Read data eye training end socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize start: socket[1] channel[2] rank[0] RxPerBitTrainingExmbistOptimize end socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize start: socket[1] channel[2] rank[1] RxPerBitTrainingExmbistOptimize end socket[1] channel[2] Tx vref training start socket[1] channel[2] Tx vref training end socket[1] channel[2] rank[0] Write data eye training start: socket[1] channel[2] rank[0] Write data eye training end socket[1] channel[2] rank[1] Write data eye training start: socket[1] channel[2] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[1] Channel[2] DDR Init Finished! ********************************************************************** ********************************************************************** Socket[1] Channel[3] Base:[0x40040350000] Speed:[2400] ********************************************************************** ========================== config parameters from SPD ========================== DDR PHY PLL config.....................................OK! Top module cfg.........................................OK ch[3] : phy_rdata_en_dly:14;wden:15;wdcs:11;wdda:8 rank[0]: dmc_odt_config [0x403580A0]:wodt:0x1;rodt:0x2 rank[1]: dmc_odt_config [0x403580A4]:wodt:0x2;rodt:0x1 Dmc init static........................................OK Phy init dynamic.......................................OK [software pad_cal_0]: pvtr=0x1F; pvtn=0x1B; pvtp=0xC [software pad_cal_1]: pvtr=0x1F; pvtn=0x1B; pvtp=0xD dimm[0] rcd init finished! rank[0] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[0] sdram init finished! rank[1] RTT_WR:2; RTT_PARK:1; RTT_NOM:4; rank[1] sdram init finished! ----------------------------------------------------- Rank MR0 MR1 MR2 MR3 MR4 MR5 MR6 rank0 0X0964,0X0401,0X0498,0X0000,0X0008,0X0040,0X0810 ----------------------------------------------------- Dram init..............................................OK socket[1] channel[3] rank[0] Phy gate leveling.....OK socket[1] channel[3] rank[1] Phy gate leveling.....lat_adj_start of rank 1 byte 0 is set to 0x00000001 lat_adj_start of rank 1 byte 1 is set to 0x00000001 lat_adj_start of rank 1 byte 2 is set to 0x00000001 lat_adj_start of rank 1 byte 3 is set to 0x00000001 lat_adj_start of rank 1 byte 4 is set to 0x00000001 lat_adj_start of rank 1 byte 5 is set to 0x00000001 lat_adj_start of rank 1 byte 6 is set to 0x00000001 lat_adj_start of rank 1 byte 7 is set to 0x00000001 OK socket[1] channel[3] rank[0] Phy write leveling.....OK socket[1] channel[3] rank[1] Phy write leveling.....OK socket[1] channel[3] rank[0] Phy write leveling 2...OK socket[1] channel[3] rank[1] Phy write leveling 2...OK socket[1] channel[3] rank[0] Read data eye training start: socket[1] channel[3] rank[0] Read data eye training end socket[1] channel[3] rank[1] Read data eye training start: socket[1] channel[3] rank[1] Read data eye training end socket[1] channel[3] rank[0] Write data eye training start: socket[1] channel[3] rank[0] Write data eye training end socket[1] channel[3] rank[1] Write data eye training start: socket[1] channel[3] rank[1] Write data eye training end socket[1] channel[3] Rx vref training start socket[1] channel[3] Rx vref training end socket[1] channel[3] rank[0] Read data eye training start: socket[1] channel[3] rank[0] Read data eye training end socket[1] channel[3] rank[1] Read data eye training start: socket[1] channel[3] rank[1] Read data eye training end socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize start: socket[1] channel[3] rank[0] RxPerBitTrainingExmbistOptimize end socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize start: socket[1] channel[3] rank[1] RxPerBitTrainingExmbistOptimize end socket[1] channel[3] Tx vref training start socket[1] channel[3] Tx vref training end socket[1] channel[3] rank[0] Write data eye training start: socket[1] channel[3] rank[0] Write data eye training end socket[1] channel[3] rank[1] Write data eye training start: socket[1] channel[3] rank[1] Write data eye training end //---------------------------------- sfc test rank0 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata sfc test rank1 [0]wdata: 0x11111111 - 0x11111111 rdata [1]wdata: 0x11111111 - 0x11111111 rdata [2]wdata: 0x22222222 - 0x22222222 rdata [3]wdata: 0x22222222 - 0x22222222 rdata [4]wdata: 0x33333333 - 0x33333333 rdata [5]wdata: 0x33333333 - 0x33333333 rdata [6]wdata: 0x44444444 - 0x44444444 rdata [7]wdata: 0x44444444 - 0x44444444 rdata [8]wdata: 0x55555555 - 0x55555555 rdata [9]wdata: 0x55555555 - 0x55555555 rdata [10]wdata: 0x66666666 - 0x66666666 rdata [11]wdata: 0x66666666 - 0x66666666 rdata [12]wdata: 0x77777777 - 0x77777777 rdata [13]wdata: 0x77777777 - 0x77777777 rdata [14]wdata: 0x88888888 - 0x88888888 rdata [15]wdata: 0x88888888 - 0x88888888 rdata [16]wdata: 0x44332211 - 0x44332211 rdata [17]wdata: 0x88776655 - 0x88776655 rdata //---------------------------------- ********************************************************************** Socket[1] Channel[3] DDR Init Finished! ********************************************************************** ======================================================================================== | socekt 0 | ======================================================================================== | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 | ======================================================================================== | 0 | Samsung | Samsung | Samsung | Samsung | | | Montage | Montage | Montage | Montage | | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | | | 2400 | 2400 | 2400 | 2400 | | | ww282017 | ww282017 | ww282017 | ww282017 | | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | | | | | | | ---------------------------------------------------------------------------------------- | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ---------------------------------------------------------------------------------------- | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ---------------------------------------------------------------------------------------- ======================================================================================== | socekt 1 | ======================================================================================== | Slot | Channel 0 | Channel 1 | Channel 2 | Channel 3 | ======================================================================================== | 0 | Samsung | Samsung | Samsung | Samsung | | | Montage | Montage | Montage | Montage | | | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | 32GB(2RX4) | | | 2400 | 2400 | 2400 | 2400 | | | ww282017 | ww282017 | ww282017 | ww282017 | | | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | M393A4K40BB1-CRC | | | | | | | ---------------------------------------------------------------------------------------- | 1 | NO DIMM | NO DIMM | NO DIMM | NO DIMM | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ---------------------------------------------------------------------------------------- | 2 | NO DIMM | NO DIMM | NO DIMM | NO DIMM | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ---------------------------------------------------------------------------------------- socket[0] channel[0] rank[0] memory clean start. socket[0] channel[1] rank[0] memory clean start. socket[0] channel[2] rank[0] memory clean start. socket[0] channel[3] rank[0] memory clean start. socket[1] channel[0] rank[0] memory clean start. socket[1] channel[1] rank[0] memory clean start. socket[1] channel[2] rank[0] memory clean start. socket[1] channel[3] rank[0] memory clean start. all rank[0] memory clean ok! socket[0] channel[0] rank[0] memory clean read start. socket[0] channel[1] rank[0] memory clean read start. socket[0] channel[2] rank[0] memory clean read start. socket[0] channel[3] rank[0] memory clean read start. socket[1] channel[0] rank[0] memory clean read start. socket[1] channel[1] rank[0] memory clean read start. socket[1] channel[2] rank[0] memory clean read start. socket[1] channel[3] rank[0] memory clean read start. all rank[0] memory clean read ok! socket[0] channel[0] rank[1] memory clean start. socket[0] channel[1] rank[1] memory clean start. socket[0] channel[2] rank[1] memory clean start. socket[0] channel[3] rank[1] memory clean start. socket[1] channel[0] rank[1] memory clean start. socket[1] channel[1] rank[1] memory clean start. socket[1] channel[2] rank[1] memory clean start. socket[1] channel[3] rank[1] memory clean start. all rank[1] memory clean ok! socket[0] channel[0] rank[1] memory clean read start. socket[0] channel[1] rank[1] memory clean read start. socket[0] channel[2] rank[1] memory clean read start. socket[0] channel[3] rank[1] memory clean read start. socket[1] channel[0] rank[1] memory clean read start. socket[1] channel[1] rank[1] memory clean read start. socket[1] channel[2] rank[1] memory clean read start. socket[1] channel[3] rank[1] memory clean read start. all rank[1] memory clean read ok! RAM Diagnose or not ? (Press 'Ctrl+t' or 'Ctrl+T' to Begin Memory Diagnose) Now wait for 3 seconds... Not Press 'Ctrl+t' or 'Ctrl+T', The RAM Diagnose Exit Start config DAW. Record Interrupts Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC0] = 0xB0111168 Interrupt Status:[SocketId: 0] [DieId: 1] [DDRC1] = 0xA0311168 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC0] = 0x10201041 Interrupt Status:[SocketId: 0] [DieId: 3] [DDRC1] = 0x80301164 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC0] = 0x16223 Interrupt Status:[SocketId: 0] [DieId: 1] [RASC1] = 0x403103 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC0] = 0x613010 Interrupt Status:[SocketId: 0] [DieId: 3] [RASC1] = 0xB07132 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT0] = 0x8A Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT0] = 0x10 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT0] = 0x220 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT0] = 0x709 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS4_INT0] = 0x40 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS5_INT0] = 0x48 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS6_INT0] = 0x4 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS0_INT1] = 0x8089 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS1_INT1] = 0x1980 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS2_INT1] = 0xA00C0 Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS3_INT1] = 0x42AC0C Interrupt Status:[SocketId: 0] [DieId: 1] [T_CS4_INT1] = 0x2 Interrupt Status:[SocketId: 0] [DieId: 1] [T] [T_CS0_INT0] = 0x6 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT0] = 0x36 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT0] = 0x38 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT0] = 0x10 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT0] = 0x2 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT0] = 0x40 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS0_INT1] = 0x1400 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS1_INT1] = 0x22C4 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS2_INT1] = 0xC044 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS3_INT1] = 0x80820 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS4_INT1] = 0x9008 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS5_INT1] = 0xF06 Interrupt Status:[SocketId: 0] [DieId: 3] [T_CS6_INT1] = 0x181 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT0] = 0x60 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT0] = 0xF4 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT0] = 0x74 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS0_INT1] = 0x3CBC Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS1_INT1] = 0x2010 Interrupt Status:[SocketId: 0] [DieId: 0] [I_CS2_INT1] = 0x41 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT0] = 0xAC Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT0] = 0x3B Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT0] = 0xF8 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS0_INT1] = 0xB144 Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS1_INT1] = 0x346D Interrupt Status:[SocketId: 0] [DieId: 2] [I_CS2_INT1] = 0xA8B1 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA0] = 0x88030 Interrupt Status:[SocketId: 0] [DieId: 1] [HHA1] = 0x400 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA0] = 0x9131 Interrupt Status:[SocketId: 0] [DieId: 3] [HHA1] = 0x80200 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC0] = 0x2A0 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC1] = 0xA81 Interrupt Status:[SocketId: 0] [DieId: 1] [LLC3] = 0x20000 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC0] = 0x400 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC1] = 0x4020 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC2] = 0x10001 Interrupt Status:[SocketId: 0] [DieId: 3] [LLC3] = 0x280 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER0] = 0x3 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER1] = 0x4 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER2] = 0x3 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_CLUSTER3] = 0x2 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_POE] = 0x7 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER2] = 0x4 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_CLUSTER3] = 0x2 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_POE] = 0x3 Interrupt Status:[SocketId: 0] [DieId: 0] [AA_SAS] = 0x1 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_ALG] = 0x3 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_PCIE] = 0x3 Interrupt Status:[SocketId: 0] [DieId: 2] [AA_SAS] = 0x1 Interrupt Status:[SocketId: 0] [DieId: 1] [AA_SRAM] = 0x8 Interrupt Status:[SocketId: 0] [DieId: 3] [AA_SRAM] = 0xEB Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC0] = 0x9111115C Interrupt Status:[SocketId: 1] [DieId: 1] [DDRC1] = 0xC1501000 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC0] = 0xC1001028 Interrupt Status:[SocketId: 1] [DieId: 3] [DDRC1] = 0xA0301050 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC0] = 0xA10321 Interrupt Status:[SocketId: 1] [DieId: 1] [RASC1] = 0x207222 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC0] = 0x31A123 Interrupt Status:[SocketId: 1] [DieId: 3] [RASC1] = 0x6110 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT0] = 0x60 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT0] = 0x20 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT0] = 0xA Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT0] = 0x412 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT0] = 0x12 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS0_INT1] = 0x764 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS1_INT1] = 0x305 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS2_INT1] = 0x524000 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS3_INT1] = 0x823068 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS4_INT1] = 0x201 Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS5_INT1] = 0xB5E Interrupt Status:[SocketId: 1] [DieId: 1] [T_CS6_INT1] = 0x1D55 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT0] = 0x2 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT0] = 0x800 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT0] = 0x84 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT0] = 0x20 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT0] = 0x8D Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS0_INT1] = 0x100 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS1_INT1] = 0x5C85 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS2_INT1] = 0x64A4C Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS3_INT1] = 0x58388 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS4_INT1] = 0x4180 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS5_INT1] = 0x882 Interrupt Status:[SocketId: 1] [DieId: 3] [T_CS6_INT1] = 0xB104 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT0] = 0x60 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT0] = 0x3C Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT0] = 0xC9 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS0_INT1] = 0x810 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS1_INT1] = 0x3063 Interrupt Status:[SocketId: 1] [DieId: 0] [I_CS2_INT1] = 0x400D Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT0] = 0x8 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT0] = 0xC Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS0_INT1] = 0xA074 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS1_INT1] = 0x4940 Interrupt Status:[SocketId: 1] [DieId: 2] [I_CS2_INT1] = 0x2D49 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA0] = 0xC019 Interrupt Status:[SocketId: 1] [DieId: 1] [HHA1] = 0x8A041 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA0] = 0x20 Interrupt Status:[SocketId: 1] [DieId: 3] [HHA1] = 0x48000 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC0] = 0x8200 Interrupt Status:[SocketId: 1] [DieId: 1] [LLC3] = 0x20 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC0] = 0x5000 Interrupt Status:[SocketId: 1] [DieId: 3] [LLC2] = 0x20 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_CLUSTER3] = 0x2 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_POE] = 0x6 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER1] = 0x2 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_CLUSTER3] = 0x1 Interrupt Status:[SocketId: 1] [DieId: 3] [AA_POE] = 0x2 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_ALG] = 0x1 Interrupt Status:[SocketId: 1] [DieId: 0] [AA_PCIE] = 0x2 Interrupt Status:[SocketId: 1] [DieId: 2] [AA_ALG] = 0x1 Interrupt Status:[SocketId: 1] [DieId: 1] [AA_SRAM] = 0xFD Interrupt Status:[SocketId: 1] [DieId: 3] [AA_SRAM] = 0xFB Clear Interrupts Clear DDRC Clear RASC Clear CS Clear SLLC Clear HHA Clear LLC Clear AA Clear SRAM Clear DDRC Clear RASC Clear CS Clear SLLC Clear HHA Clear LLC Clear AA Clear SRAM Clear Interrupt End Enable Channel Interleave for socket[0] Enable Channel Interleave for socket[0] Daw Cinfig :Skt 0 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0 ColBits = 0xA RowBits = 0x11 Banknum = 0x10 RankSize = 0x400000000 Ranknum = 0x2 DramWidth = 0x4 Size = 0x1000000000 Daw Config: Skt 0 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0 LowMemory(<4G):Base=0x0, Size=0x40000000 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000 HighMemory(>4G):Base=0x1040000000, Size=0x7C0000000 HighMemory(>4G):Base=0x1800000000, Size=0x7FC000000 ColBits = 0xA RowBits = 0x11 Banknum = 0x10 RankSize = 0x400000000 Ranknum = 0x2 DramWidth = 0x4 Size = 0x1000000000 Daw Config: Skt 0 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0 HighMemory(>4G):Base=0x2000000000, Size=0xFFC000000 Enable Channel Interleave for socket[1] Enable Channel Interleave for socket[1] Daw Cinfig :Skt 1 Ch: 3 , Base = 0x0, Size = 0x40000000, DieInterLeaveEn = 0 ColBits = 0xA RowBits = 0x11 Banknum = 0x10 RankSize = 0x400000000 Ranknum = 0x2 DramWidth = 0x4 Size = 0x1000000000 Daw Config: Skt 1 Ch: 3 , Base = 0x1000000000, Size = 0x1000000000, DieInterLeaveEn = 0 HighMemory(>4G):Base=0x41000000000, Size=0xFFC000000 ColBits = 0xA RowBits = 0x11 Banknum = 0x10 RankSize = 0x400000000 Ranknum = 0x2 DramWidth = 0x4 Size = 0x1000000000 Daw Config: Skt 1 Ch: 1 , Base = 0x2000000000, Size = 0x1000000000, DieInterLeaveEn = 0 HighMemory(>4G):Base=0x42000000000, Size=0xFFC000000 Finish Config DAW. Start config RAS or ECC. pGblData->mem.rascBypass = 1 pGblData->mem.demandScrubMode = 0 pGblData->mem.patrolScrubMode = 0 skt[0] ch[0] ecc enable. skt[0] ch[1] ecc enable. skt[0] ch[2] ecc enable. skt[0] ch[3] ecc enable. skt[1] ch[0] ecc enable. skt[1] ch[1] ecc enable. skt[1] ch[2] ecc enable. skt[1] ch[3] ecc enable. Finish config RAS or ECC. Clean ddrc or rasc interrupt OK NOTICE: PL011_UART_BASE: 0x602b0000 NOTICE: BL1: 0x3fc8a000 - 0x3fc8b000 [size = 4096] NOTICE: Booting Trusted Firmware NOTICE: BL1: v1.1(release):50e18f8 NOTICE: BL1: Built : 08:50:23, Feb 25 2017 NOTICE: BL1: Booting BL2 NOTICE: BL2: v1.1(release):50e18f8 NOTICE: BL2: Built : 08:50:24, Feb 25 2017 NOTICE: BL1: Booting BL3-1 NOTICE: Before BL31 EL3 MMU NOTICE: After BL31 EL3 MMU NOTICE: BL3-1: v1.1(release):50e18f8 NOTICE: BL3-1: Built : 08:50:27, Feb 25 2017 NOTICE: [runtime_svc_init]:[94L] rt_svc_descs_num=0x1 NOTICE: [runtime_svc_init]:[109L] start_oen=4 end_oen=4 call_type=1 std_svc NOTICE: [psci_init_aff_map]:[296L] mpidr = 0 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 0 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 1 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 2 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] a [psci_init_aff_map]:[298L] affmap_idx = 4 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 5 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 6 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 2 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 7 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 8 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 9 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 10 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 11 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 12 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 13 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 14 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 15 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 16 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 17 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 18 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 19 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 20 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 21 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 22 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 23 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 24 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 25 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 26 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 27 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 28 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 29 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 30 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 31 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 32 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 33 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 34 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 35 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 36 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 37 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 38 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 1 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 39 NOTICE: [psci_init_aff_map]:[296L] mpidr = 0 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 40 NOTICE: [psci_init_aff_map]:[296L] mpidr = 1 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 41 NOTICE: [psci_init_aff_map]:[296L] mpidr = 2 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 42 NOTICE: [psci_init_aff_map]:[296L] mpidr = 3 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 43 NOTICE: [psci_init_aff_map]:[296L] mpidr = 100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 44 NOTICE: [psci_init_aff_map]:[296L] mpidr = 101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 45 NOTICE: [psci_init_aff_map]:[296L] mpidr = 102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 46 NOTICE: [psci_init_aff_map]:[296L] mpidr = 103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 47 NOTICE: [psci_init_aff_map]:[296L] mpidr = 200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 48 NOTICE: [psci_init_aff_map]:[296L] mpidr = 201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 49 NOTICE: [psci_init_aff_map]:[296L] mpidr = 202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 50 NOTICE: [psci_init_aff_map]:[296L] mpidr = 203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 51 NOTICE: [psci_init_aff_map]:[296L] mpidr = 300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 52 NOTICE: [psci_init_aff_map]:[296L] mpidr = 301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 53 NOTICE: [psci_init_aff_map]:[296L] mpidr = 302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 54 NOTICE: [psci_init_aff_map]:[296L] mpidr = 303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 55 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 56 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 57 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 58 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 59 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 60 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 61 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 62 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 63 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 64 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 65 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 66 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 67 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 68 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 69 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 70 NOTICE: [psci_init_aff_map]:[296L] mpidr = 10303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 71 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 72 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 73 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 74 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 75 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 76 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 77 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 78 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 79 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 80 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 81 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 82 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 83 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 84 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 85 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 86 NOTICE: [psci_init_aff_map]:[296L] mpidr = 20303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 87 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 88 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 89 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 90 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 91 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 92 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 93 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 94 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 95 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 96 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 97 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 98 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 99 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 100 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 101 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 102 NOTICE: [psci_init_aff_map]:[296L] mpidr = 30303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 103 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 104 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 105 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 106 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 107 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 108 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 109 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 110 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 111 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 112 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 113 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 114 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 115 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 116 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 117 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 118 NOTICE: [psci_init_aff_map]:[296L] mpidr = 40303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 119 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 120 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 121 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 122 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 123 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 124 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 125 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 126 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 127 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 128 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 129 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 130 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 131 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 132 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 133 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 134 NOTICE: [psci_init_aff_map]:[296L] mpidr = 50303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 135 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 136 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 137 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 138 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 139 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 140 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 141 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 142 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 143 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 144 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 145 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 146 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 147 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 148 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 149 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 150 NOTICE: [psci_init_aff_map]:[296L] mpidr = 60303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 151 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70000 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 152 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70001 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 153 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70002 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 154 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70003 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 155 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70100 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 156 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70101 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 157 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70102 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 158 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70103 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 159 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70200 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 160 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70201 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 161 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70202 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 162 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70203 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 163 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70300 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 164 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70301 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 165 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70302 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 166 NOTICE: [psci_init_aff_map]:[296L] mpidr = 70303 NOTICE: [psci_init_aff_map]:[297L] cur_afflvl = 0 NOTICE: [psci_init_aff_map]:[298L] affmap_idx = 167 NOTICE: [cm_prepare_el3_exit]:[262L] read_tpidr_el3 = 3fc5e800 NOTICE: [cm_prepare_el3_exit]:[319L] ctx add = 3fc7ef80 :486=170 [serdes_hilink2_init]:hilink2_mode pcie2 8 lane Halt Macro 2 MCU!! Macro 2 Download Firmware Success!! Release Macro 2 MCU!! Temperature: 28 (0x1C) Temperature: 28 (0x1C) [serdes_init]:SerDes2 init success! Halt Macro 3 MCU!! Macro 3 Download Firmware Success!! Release Macro 3 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes3 init success! Halt Macro 4 MCU!! Macro 4 Download Firmware Success!! Release Macro 4 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes4 init success! [serdes_hilink5_init]:hilink5_mode sas1 4 lane Halt Macro 5 MCU!! Macro 5 Download Firmware Success!! Release Macro 5 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes5 init success! [serdes_hilink6_init] lane 0 =>sas1 lane 0 [serdes_hilink6_init] lane 1 =>sas1 lane 1 [serdes_hilink6_init] lane 2 =>sas1 lane 2 [serdes_hilink6_init] lane 3 =>sas1 lane 3 Halt Macro 6 MCU!! Macro 6 Download Firmware Success!! Release Macro 6 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes6 init success! [serdes_hilink0_init]:hilink0_mode pcie5 8 lane Halt Macro 0 MCU!! Macro 0 Download Firmware Success!! Release Macro 0 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes0 init success! [serdes_hilink1_init]:hilink1_mode pcie4 8 lane Halt Macro 1 MCU!! Macro 1 Download Firmware Success!! Release Macro 1 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes1 init success! [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane Halt Macro 5 MCU!! Macro 5 Download Firmware Success!! Release Macro 5 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes5 init success! [serdes_hilink6_init] lane 0 =>sas5 lane 0 [serdes_hilink6_init] lane 1 =>sas5 lane 1 Halt Macro 6 MCU!! Macro 6 Download Firmware Success!! Release Macro 6 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes6 init success! [serdes_hilink2_init]:hilink2_mode pcie2 8 lane Halt Macro 2 MCU!! Macro 2 Download Firmware Success!! Release Macro 2 MCU!! Temperature: 28 (0x1C) Temperature: 28 (0x1C) [serdes_init]:SerDes2 init success! Halt Macro 3 MCU!! Macro 3 Download Firmware Success!! Release Macro 3 MCU!! Temperature: 29 (0x1D) Temperature: 30 (0x1E) [serdes_init]:SerDes3 init success! Halt Macro 4 MCU!! Macro 4 Download Firmware Success!! Release Macro 4 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes4 init success! [serdes_hilink5_init]:hilink5_mode sas1 4 lane Halt Macro 5 MCU!! Macro 5 Download Firmware Success!! Release Macro 5 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes5 init success! [serdes_hilink6_init] lane 0 =>sas1 lane 0 [serdes_hilink6_init] lane 1 =>sas1 lane 1 [serdes_hilink6_init] lane 2 =>sas1 lane 2 [serdes_hilink6_init] lane 3 =>sas1 lane 3 Halt Macro 6 MCU!! Macro 6 Download Firmware Success!! Release Macro 6 MCU!! Temperature: 30 (0x1E) Temperature: 30 (0x1E) [serdes_init]:SerDes6 init success! [serdes_hilink0_init]:hilink0_mode pcie5 8 lane Halt Macro 0 MCU!! Macro 0 Download Firmware Success!! Release Macro 0 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes0 init success! [serdes_hilink1_init]:hilink1_mode pcie4 8 lane Halt Macro 1 MCU!! Macro 1 Download Firmware Success!! Release Macro 1 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes1 init success! [serdes_hilink5_init]:hilink5_mode pcie6 1 lane and pcie7 1 lane Halt Macro 5 MCU!! Macro 5 Download Firmware Success!! Release Macro 5 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes5 init success! [serdes_hilink6_init] lane 0 =>sas5 lane 0 [serdes_hilink6_init] lane 1 =>sas5 lane 1 Halt Macro 6 MCU!! Macro 6 Download Firmware Success!! Release Macro 6 MCU!! Temperature: 27 (0x1B) Temperature: 27 (0x1B) [serdes_init]:SerDes6 init success! InfoFromBmc.ProductName TaiShan 2280 InfoFromBmc.SerialNum 2102311TBJ10H8000087 InfoFromBmc.ManufactureType02 Huawei InfoFromBmc.AssetTag InfoFromBmc.SrNumType02 024APL10H8000090 InfoFromBmc.AssetTagType03 InfoFromBmc.SrNumType03 To be filled by O.E.M. InfoFromBmc.VersionType03 InfoFromBmc.ChassisType03 InfoFromBmc.ManufacturerType03 Huawei Create event for smbios table transfer success. VerStr:1.12 Create event for miscellaneous ipmi operation success. Locate gEfiPciIoProtocol Failed. DawNum[0] = 2,DawNum[1] = 1,DawNum[2] =2,DawNum[3] =1 0 Base = 0x0, Size = 0x40000000 0 Base = 0x1000000000, Size = 0x1000000000 1 Base = 0x2000000000, Size = 0x1000000000 2 Base = 0x40000000000, Size = 0x40000000 2 Base = 0x41000000000, Size = 0x1000000000 3 Base = 0x42000000000, Size = 0x1000000000 [gmac_initialize]:[3650L] GpriData=0x3E8DE018 pPriv->ulMacSpeed:9 pPriv->ulMacDuplex:1 pPriv->ulPort:0 pPriv->ulGEBase:0xC7040000 pPriv->ulPpeCommonBase:0xC5070000 pPriv->ulPpeTNLBase:0xC5000000 pPriv->ulRCBCommonBase:0xC5080000 pPriv->ulRCBCommonEntryBase:0xC5080000 pPriv->ulRCBSramEntryBase:0xC5090000 pPriv->ulRingNum:0 pPriv->ulRingAddr:0 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE8 DSAF_init tbl_tcam_data 0x3F196CA0:0xA0A33BC1 0x40E80000 0x00000000 0x00000001 0x3F196CB0:0x00000000 tbl_tcam_ucast 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001 0x3F196CB8:0x0000007F 0x00000000 0x0000007F 0x00000000 0x3F196CC8:0x01000204 ----ok LocateProtocol mOemXgeStatusProtocol success. RXRING = 0x3E8D9000 TXRING = 0x3E8D4000 pPriv->ulTxMask = 512 RXBUFF = 0x3E6D3000 TXBUFF = 0x3E4D2000 [gmac_initialize]:[3650L] GpriData=0x3E44C018 pPriv->ulMacSpeed:9 pPriv->ulMacDuplex:1 pPriv->ulPort:1 pPriv->ulGEBase:0xC7044000 pPriv->ulPpeCommonBase:0xC5070000 pPriv->ulPpeTNLBase:0xC5010000 pPriv->ulRCBCommonBase:0xC5080000 pPriv->ulRCBCommonEntryBase:0xC5080000 pPriv->ulRCBSramEntryBase:0xC5090000 pPriv->ulRingNum:16 pPriv->ulRingAddr:1048576 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE9 DSAF_init tbl_tcam_data 0x3F196CA0:0xA0A33BC1 0x40E90001 0x00000000 0x00000001 0x3F196CB0:0x00000000 tbl_tcam_ucast 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001 0x3F196CB8:0x0000008F 0x00000000 0x0000008F 0xC13BA3A0 0x3F196CC8:0x0000E940 ----ok LocateProtocol mOemXgeStatusProtocol success. RXRING = 0x3E447000 TXRING = 0x3E442000 pPriv->ulTxMask = 512 RXBUFF = 0x3E241000 TXBUFF = 0x3E040000 [gmac_initialize]:[3650L] GpriData=0x3DFB8018 pPriv->ulMacSpeed:8 pPriv->ulMacDuplex:1 pPriv->ulPort:4 pPriv->ulGEBase:0xC7050000 pPriv->ulPpeCommonBase:0xC5070000 pPriv->ulPpeTNLBase:0xC5040000 pPriv->ulRCBCommonBase:0xC5080000 pPriv->ulRCBCommonEntryBase:0xC5080000 pPriv->ulRCBSramEntryBase:0xC5090000 pPriv->ulRingNum:64 pPriv->ulRingAddr:4194304 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE6 PhyID : 0x1410DD0 PhyAddr: 0x0 ETH_PhyInit 1928; Marvell 88E1512 detect! MII_CTRL_REG = 0x3100 MII_STAT_REG = 0x7949 page 18, reg20:0x1 page 0, reg17:0x4000 Phy Init OK DSAF_init tbl_tcam_data 0x3F196CA0:0xA0A33BC1 0x40E60004 0x00000000 0x00000001 0x3F196CB0:0x00000000 tbl_tcam_ucast 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001 0x3F196CB8:0x000000BF 0x00000000 0x000000BF 0xAFAFAFAF 0x3F196CC8:0xAFAFAFAF ----ok RXRING = 0x3DFB3000 TXRING = 0x3DFAD000 pPriv->ulTxMask = 512 RXBUFF = 0x3DDAB000 TXBUFF = 0x3DBA9000 [gmac_initialize]:[3650L] GpriData=0x3DB21018 pPriv->ulMacSpeed:8 pPriv->ulMacDuplex:1 pPriv->ulPort:5 pPriv->ulGEBase:0xC7054000 pPriv->ulPpeCommonBase:0xC5070000 pPriv->ulPpeTNLBase:0xC5050000 pPriv->ulRCBCommonBase:0xC5080000 pPriv->ulRCBCommonEntryBase:0xC5080000 pPriv->ulRCBSramEntryBase:0xC5090000 pPriv->ulRingNum:80 pPriv->ulRingAddr:5242880 pPriv->ulMacAddr:0xA0 0xA3 0x3B 0xC1 0x40 0xE7 PhyID : 0x1410DD0 PhyAddr: 0x1 ETH_PhyInit 1928; Marvell 88E1512 detect! MII_CTRL_REG = 0x3100 MII_STAT_REG = 0x7949 page 18, reg20:0x1 page 0, reg17:0x4000 Phy Init OK DSAF_init tbl_tcam_data 0x3F196CA0:0xA0A33BC1 0x40E70005 0x00000000 0x00000001 0x3F196CB0:0x00000000 tbl_tcam_ucast 0x3F196CA8:0x00000000 0x00000001 0x00000000 0x00000001 0x3F196CB8:0x000000CF 0x00000000 0x000000CF 0xAFAFAFAF 0x3F196CC8:0xAFAFAFAF ----ok RXRING = 0x3DB1C000 TXRING = 0x3DB17000 pPriv->ulTxMask = 512 RXBUFF = 0x3D916000 TXBUFF = 0x3D714000 SasDriverInitialize Ok!!! [sas_init,2173]Card:1 init ok [Higgs_StartPhy,185]Card:1 no cable on phy:0, default as electric cable [Higgs_IntrInquiryOperation,219]Identify info:0x20010202,DevType:2--2,uiPhyContext:0x0 [Higgs_PhyCtrlUpDown,332]Higgs_PhyCtrlUpDown at uiPhyId = 0x0 [Higgs_PhyCtrlUpDown,346]uiPhyId:0x0, uiIrqVal:0x26 [Higgs_PhyUp,503]phyid:0,Rate is 11 [SAINI_ClearPortRsc,449]Card:1 port:0 clr port rsc,remove all device from device list of Disc [SAINI_ExpanderBufferSwitch,1306]EXPANDER Buffer function is 2 ! [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CC9F0(uni id:0x0) to dev addr:0x500E004AAAAAAA00(sal dev:3D5D42D8) done func is NULL,v_pstMsg->stStatus.enDrvResp803 [SAL_AbortSataDevIo,175]Now let's start AbortSataDev reset Io Card:1 msg:3D5CCFD8(uni id:0x0) to dev addr:0x500E004AAAAAAA01(sal dev:3D5D4598) done func is NULL,v_pstMsg->stStatus.enDrvResp803 [SAL_AbortTaskSet,646]Now let's start abort SAS dev Io Card:1 msg:3D5CD5C0 to dev addr:0x500E004AAAAAAA1E(sal dev:3D5D4858),v_pstMsg->stStatus.enDrvResp803,pstMsg->pfnDone:31B85BF8 [SasScanDisk,838]Open Card:1 Phy:0 success! Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA00, status = Success Success to register SasDevice:Port 0 SasAddr 0x500E004AAAAAAA01, status = Success SasDriverStart Ok!!! SmiControllerDriverSupported - Status:Success Install GopDevicePath Handle 0 Install GopDevicePath Handle 3D54D898 Install GopDevicePath Status Success SmiGraphicsOutputSetMode + Resetting Memory setModeEx + programModeRegisters + [LPC] CRT_PLL1_750HS = 0x1D40A02 [LPC] CRT_PLL2_750HS = 0x206B851E [LPC] SECONDARY_DISPLAY_CTRL = 0x2087106 setModeEx - SmiGraphicsOutputSetMode x=640 y=480 SmiGraphicsOutputSetMode - SmiGraphicsOutputConstructor - [=3h[=3h[=3h[=3h[=3h[=3hSmiGraphicsOutputQueryMode + SmiGraphicsOutputQueryMode - SmiGraphicsOutputQueryMode + SmiGraphicsOutputQueryMode - SmiGraphicsOutputQueryMode + SmiGraphicsOutputQueryMode - SmiGraphicsOutputQueryMode + SmiGraphicsOutputQueryMode - [=3hSmiGraphicsOutputQueryMode + SmiGraphicsOutputQueryMode - [=3hSmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported SmiControllerDriverSupported - Status:Unsupported Press Enter to boot OS immediately. Press any other key in 10 seconds to stop automatical booting... SmiGraphicsOutputQueryMode + SmiGraphicsOutputQueryMode - ..Welcome to GRUB! GNU GRUB version 2.02~beta3 Minimal BASH-like line editing is supported. For the first word, TAB lists possible command completions. Anywhere else TAB lists possible device or file completions. grub> linux (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/kernel/Image pcie_aspm=off pci=pcie_bus_perf root=/dev/nfs rw nfsroot=192.168.101.1:/var/lib/lava/dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a,tcp,hard,vers=3 ip=:::::eth0:dhcp linux (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/kernel/Image pcie _ aspm=off pci=pcie_bus_perf root=/dev/nfs rw nfsroot=192.168.101.1:/var/lib/lava / dispatcher/tmp/9568079/extract-nfsrootfs-1n9uw79a,tcp,hard,vers=3 ip=:::::eth0: d hcp grub> devicetree (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/dtb/hip07-d05.dtb devicetree (tftp,192.168.101.1)/9568079/tftp-deploy-6ednswe7/dtb/hip07-d0 5 .dtb grub> boot boot EFI stub: Booting Linux Kernel... EFI stub: Using DTB from configuration table EFI stub: Exiting boot services and installing virtual address map... [SAL_ClearAffiliationSMP,325]it is going to hard reset dev:0x500E004AAAAAAA1F [SAL_ClearAffiliationSMP,325]it is going to hard reset dev:0x500E004AAAAAAA1F SAS ExitBootServicesEvent GMAC ExitBootServicesEvent GMAC ExitBootServicesEvent GMAC ExitBootServicesEvent GMAC ExitBootServicesEvent OHCI ExitBootServicesEvent IPMI ExitBootService Event TransferSmbiosToBMC EVENT. Transfer Smbios Table To iBMC Success. GetVariable Status : Not Found.