Boot log: asus-cx9400-volteer
- Kernel Errors: 0
- Kernel Warnings: 0
- Boot result: FAIL
- Warnings: 0
- Errors: 2
1 12:53:43.660714 lava-dispatcher, installed at version: 2023.01
2 12:53:43.660923 start: 0 validate
3 12:53:43.661056 Start time: 2023-04-05 12:53:43.661049+00:00 (UTC)
4 12:53:43.661178 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:53:43.661305 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230324.0%2Fx86%2Frootfs.cpio.gz exists
6 12:53:43.949460 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:53:43.949654 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.279-cip95-86-g16c082d0be46%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:53:44.240488 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:53:44.241239 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.279-cip95-86-g16c082d0be46%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 12:53:47.965862 validate duration: 4.30
12 12:53:47.967202 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:53:47.967774 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:53:47.968265 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:53:47.968775 Not decompressing ramdisk as can be used compressed.
16 12:53:47.969216 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230324.0/x86/rootfs.cpio.gz
17 12:53:47.969580 saving as /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/ramdisk/rootfs.cpio.gz
18 12:53:47.969902 total size: 8429597 (8MB)
19 12:53:48.692003 progress 0% (0MB)
20 12:53:48.703563 progress 5% (0MB)
21 12:53:48.714968 progress 10% (0MB)
22 12:53:48.723414 progress 15% (1MB)
23 12:53:48.728873 progress 20% (1MB)
24 12:53:48.733378 progress 25% (2MB)
25 12:53:48.737261 progress 30% (2MB)
26 12:53:48.740642 progress 35% (2MB)
27 12:53:48.743620 progress 40% (3MB)
28 12:53:48.746605 progress 45% (3MB)
29 12:53:48.749350 progress 50% (4MB)
30 12:53:48.751933 progress 55% (4MB)
31 12:53:48.754309 progress 60% (4MB)
32 12:53:48.756642 progress 65% (5MB)
33 12:53:48.758891 progress 70% (5MB)
34 12:53:48.760852 progress 75% (6MB)
35 12:53:48.762966 progress 80% (6MB)
36 12:53:48.765060 progress 85% (6MB)
37 12:53:48.767106 progress 90% (7MB)
38 12:53:48.769164 progress 95% (7MB)
39 12:53:48.771244 progress 100% (8MB)
40 12:53:48.771376 8MB downloaded in 0.80s (10.03MB/s)
41 12:53:48.771523 end: 1.1.1 http-download (duration 00:00:01) [common]
43 12:53:48.771818 end: 1.1 download-retry (duration 00:00:01) [common]
44 12:53:48.771905 start: 1.2 download-retry (timeout 00:09:59) [common]
45 12:53:48.771989 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 12:53:48.772098 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.279-cip95-86-g16c082d0be46/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 12:53:48.772165 saving as /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/kernel/bzImage
48 12:53:48.772225 total size: 10854400 (10MB)
49 12:53:48.772284 No compression specified
50 12:53:48.773395 progress 0% (0MB)
51 12:53:48.776075 progress 5% (0MB)
52 12:53:48.778885 progress 10% (1MB)
53 12:53:48.781593 progress 15% (1MB)
54 12:53:48.784464 progress 20% (2MB)
55 12:53:48.787057 progress 25% (2MB)
56 12:53:48.789808 progress 30% (3MB)
57 12:53:48.792405 progress 35% (3MB)
58 12:53:48.795214 progress 40% (4MB)
59 12:53:48.798108 progress 45% (4MB)
60 12:53:48.800818 progress 50% (5MB)
61 12:53:48.803540 progress 55% (5MB)
62 12:53:48.806124 progress 60% (6MB)
63 12:53:48.808846 progress 65% (6MB)
64 12:53:48.811364 progress 70% (7MB)
65 12:53:48.814055 progress 75% (7MB)
66 12:53:48.816663 progress 80% (8MB)
67 12:53:48.819345 progress 85% (8MB)
68 12:53:48.822056 progress 90% (9MB)
69 12:53:48.824646 progress 95% (9MB)
70 12:53:48.827333 progress 100% (10MB)
71 12:53:48.827464 10MB downloaded in 0.06s (187.41MB/s)
72 12:53:48.827639 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:53:48.827872 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:53:48.827962 start: 1.3 download-retry (timeout 00:09:59) [common]
76 12:53:48.828049 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 12:53:48.828161 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.279-cip95-86-g16c082d0be46/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 12:53:48.828236 saving as /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/modules/modules.tar
79 12:53:48.828322 total size: 484468 (0MB)
80 12:53:48.828388 Using unxz to decompress xz
81 12:53:48.832641 progress 6% (0MB)
82 12:53:48.833041 progress 13% (0MB)
83 12:53:48.833279 progress 20% (0MB)
84 12:53:48.834621 progress 27% (0MB)
85 12:53:48.836744 progress 33% (0MB)
86 12:53:48.838927 progress 40% (0MB)
87 12:53:48.841395 progress 47% (0MB)
88 12:53:48.843520 progress 54% (0MB)
89 12:53:48.845349 progress 60% (0MB)
90 12:53:48.847318 progress 67% (0MB)
91 12:53:48.849394 progress 74% (0MB)
92 12:53:48.851489 progress 81% (0MB)
93 12:53:48.853353 progress 87% (0MB)
94 12:53:48.855243 progress 94% (0MB)
95 12:53:48.857039 progress 100% (0MB)
96 12:53:48.862918 0MB downloaded in 0.03s (13.36MB/s)
97 12:53:48.863170 end: 1.3.1 http-download (duration 00:00:00) [common]
99 12:53:48.863430 end: 1.3 download-retry (duration 00:00:00) [common]
100 12:53:48.863545 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
101 12:53:48.863692 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
102 12:53:48.863778 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 12:53:48.863865 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
104 12:53:48.864050 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170
105 12:53:48.864155 makedir: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin
106 12:53:48.864246 makedir: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/tests
107 12:53:48.864331 makedir: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/results
108 12:53:48.864446 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-add-keys
109 12:53:48.864578 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-add-sources
110 12:53:48.864718 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-background-process-start
111 12:53:48.864868 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-background-process-stop
112 12:53:48.864987 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-common-functions
113 12:53:48.865101 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-echo-ipv4
114 12:53:48.865213 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-install-packages
115 12:53:48.865324 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-installed-packages
116 12:53:48.865432 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-os-build
117 12:53:48.865544 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-probe-channel
118 12:53:48.865655 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-probe-ip
119 12:53:48.865765 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-target-ip
120 12:53:48.865875 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-target-mac
121 12:53:48.865983 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-target-storage
122 12:53:48.866098 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-case
123 12:53:48.866208 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-event
124 12:53:48.866316 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-feedback
125 12:53:48.866424 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-raise
126 12:53:48.866533 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-reference
127 12:53:48.866657 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-runner
128 12:53:48.866767 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-set
129 12:53:48.866879 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-test-shell
130 12:53:48.866992 Updating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-install-packages (oe)
131 12:53:48.867106 Updating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/bin/lava-installed-packages (oe)
132 12:53:48.867205 Creating /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/environment
133 12:53:48.867297 LAVA metadata
134 12:53:48.867370 - LAVA_JOB_ID=9879076
135 12:53:48.867434 - LAVA_DISPATCHER_IP=192.168.201.1
136 12:53:48.867533 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
137 12:53:48.867631 skipped lava-vland-overlay
138 12:53:48.867725 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 12:53:48.867811 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
140 12:53:48.867874 skipped lava-multinode-overlay
141 12:53:48.867948 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 12:53:48.868030 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
143 12:53:48.868104 Loading test definitions
144 12:53:48.868199 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
145 12:53:48.868279 Using /lava-9879076 at stage 0
146 12:53:48.868537 uuid=9879076_1.4.2.3.1 testdef=None
147 12:53:48.868638 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 12:53:48.868728 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
149 12:53:48.869223 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 12:53:48.869447 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
152 12:53:48.870003 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 12:53:48.870234 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
155 12:53:48.870768 runner path: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/0/tests/0_dmesg test_uuid 9879076_1.4.2.3.1
156 12:53:48.870910 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 12:53:48.871138 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
159 12:53:48.871211 Using /lava-9879076 at stage 1
160 12:53:48.871451 uuid=9879076_1.4.2.3.5 testdef=None
161 12:53:48.871537 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 12:53:48.871665 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
163 12:53:48.872098 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 12:53:48.872316 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
166 12:53:48.872896 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 12:53:48.873137 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
169 12:53:48.873670 runner path: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/1/tests/1_bootrr test_uuid 9879076_1.4.2.3.5
170 12:53:48.873806 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 12:53:48.874011 Creating lava-test-runner.conf files
173 12:53:48.874075 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/0 for stage 0
174 12:53:48.874159 - 0_dmesg
175 12:53:48.874235 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9879076/lava-overlay-18lko170/lava-9879076/1 for stage 1
176 12:53:48.874318 - 1_bootrr
177 12:53:48.874406 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 12:53:48.874490 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
179 12:53:48.882663 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 12:53:48.882791 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
181 12:53:48.882905 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 12:53:48.883030 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 12:53:48.883149 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
184 12:53:49.088656 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 12:53:49.089059 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
186 12:53:49.089179 extracting modules file /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9879076/extract-overlay-ramdisk-gi1cu1x9/ramdisk
187 12:53:49.102592 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 12:53:49.102727 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
189 12:53:49.102824 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9879076/compress-overlay-kxiku3tx/overlay-1.4.2.4.tar.gz to ramdisk
190 12:53:49.102901 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9879076/compress-overlay-kxiku3tx/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9879076/extract-overlay-ramdisk-gi1cu1x9/ramdisk
191 12:53:49.108635 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 12:53:49.108752 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
193 12:53:49.108850 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 12:53:49.108945 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
195 12:53:49.109024 Building ramdisk /var/lib/lava/dispatcher/tmp/9879076/extract-overlay-ramdisk-gi1cu1x9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9879076/extract-overlay-ramdisk-gi1cu1x9/ramdisk
196 12:53:49.202604 >> 53976 blocks
197 12:53:50.091156 rename /var/lib/lava/dispatcher/tmp/9879076/extract-overlay-ramdisk-gi1cu1x9/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/ramdisk/ramdisk.cpio.gz
198 12:53:50.091590 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 12:53:50.091747 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 12:53:50.091853 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 12:53:50.091954 No mkimage arch provided, not using FIT.
202 12:53:50.092044 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 12:53:50.092130 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 12:53:50.092231 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
205 12:53:50.092343 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 12:53:50.092432 No LXC device requested
207 12:53:50.092517 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 12:53:50.092605 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 12:53:50.092691 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 12:53:50.092765 Checking files for TFTP limit of 4294967296 bytes.
211 12:53:50.093154 end: 1 tftp-deploy (duration 00:00:02) [common]
212 12:53:50.093276 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 12:53:50.093371 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 12:53:50.093490 substitutions:
215 12:53:50.093559 - {DTB}: None
216 12:53:50.093623 - {INITRD}: 9879076/tftp-deploy-m4wlirzz/ramdisk/ramdisk.cpio.gz
217 12:53:50.093683 - {KERNEL}: 9879076/tftp-deploy-m4wlirzz/kernel/bzImage
218 12:53:50.093743 - {LAVA_MAC}: None
219 12:53:50.093801 - {PRESEED_CONFIG}: None
220 12:53:50.093858 - {PRESEED_LOCAL}: None
221 12:53:50.093914 - {RAMDISK}: 9879076/tftp-deploy-m4wlirzz/ramdisk/ramdisk.cpio.gz
222 12:53:50.093970 - {ROOT_PART}: None
223 12:53:50.094025 - {ROOT}: None
224 12:53:50.094080 - {SERVER_IP}: 192.168.201.1
225 12:53:50.094135 - {TEE}: None
226 12:53:50.094189 Parsed boot commands:
227 12:53:50.094243 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 12:53:50.094394 Parsed boot commands: tftpboot 192.168.201.1 9879076/tftp-deploy-m4wlirzz/kernel/bzImage 9879076/tftp-deploy-m4wlirzz/kernel/cmdline 9879076/tftp-deploy-m4wlirzz/ramdisk/ramdisk.cpio.gz
229 12:53:50.094485 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 12:53:50.094570 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 12:53:50.094662 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 12:53:50.094750 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 12:53:50.094819 Not connected, no need to disconnect.
234 12:53:50.094895 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 12:53:50.094973 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 12:53:50.095041 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-3'
237 12:53:50.098437 Setting prompt string to ['lava-test: # ']
238 12:53:50.098929 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 12:53:50.099031 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 12:53:50.099124 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 12:53:50.099211 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 12:53:50.099387 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=reboot'
243 12:53:55.249496 >> Command sent successfully.
244 12:53:55.259672 Returned 0 in 5 seconds
245 12:53:55.361325 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 12:53:55.362805 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 12:53:55.363368 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 12:53:55.363908 Setting prompt string to 'Starting depthcharge on Voema...'
250 12:53:55.364274 Changing prompt to 'Starting depthcharge on Voema...'
251 12:53:55.364711 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
252 12:53:55.365943 [Enter `^Ec?' for help]
253 12:53:56.954156
254 12:53:56.954759
255 12:53:56.964150 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
256 12:53:56.967405 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
257 12:53:56.974282 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
258 12:53:56.977459 CPU: AES supported, TXT NOT supported, VT supported
259 12:53:56.984178 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
260 12:53:56.990721 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
261 12:53:56.994229 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
262 12:53:56.997222 VBOOT: Loading verstage.
263 12:53:57.004020 FMAP: Found "FLASH" version 1.1 at 0x1804000.
264 12:53:57.007365 FMAP: base = 0x0 size = 0x2000000 #areas = 32
265 12:53:57.010424 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
266 12:53:57.021439 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
267 12:53:57.027879 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
268 12:53:57.028351
269 12:53:57.028707
270 12:53:57.041233 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
271 12:53:57.055178 Probing TPM: . done!
272 12:53:57.058621 TPM ready after 0 ms
273 12:53:57.061845 Connected to device vid:did:rid of 1ae0:0028:00
274 12:53:57.073287 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
275 12:53:57.079488 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
276 12:53:57.083111 Initialized TPM device CR50 revision 0
277 12:53:57.134125 tlcl_send_startup: Startup return code is 0
278 12:53:57.134654 TPM: setup succeeded
279 12:53:57.148350 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
280 12:53:57.162797 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
281 12:53:57.175461 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
282 12:53:57.185429 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
283 12:53:57.189347 Chrome EC: UHEPI supported
284 12:53:57.192507 Phase 1
285 12:53:57.195992 FMAP: area GBB found @ 1805000 (458752 bytes)
286 12:53:57.205930 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
287 12:53:57.212317 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
288 12:53:57.219333 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
289 12:53:57.225571 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
290 12:53:57.229040 Recovery requested (1009000e)
291 12:53:57.232435 TPM: Extending digest for VBOOT: boot mode into PCR 0
292 12:53:57.243787 tlcl_extend: response is 0
293 12:53:57.250244 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
294 12:53:57.260425 tlcl_extend: response is 0
295 12:53:57.267058 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
296 12:53:57.273325 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
297 12:53:57.280298 BS: verstage times (exec / console): total (unknown) / 142 ms
298 12:53:57.280841
299 12:53:57.281190
300 12:53:57.293690 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
301 12:53:57.300180 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
302 12:53:57.303779 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
303 12:53:57.307061 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
304 12:53:57.313089 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
305 12:53:57.316210 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
306 12:53:57.319851 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
307 12:53:57.323073 TCO_STS: 0000 0000
308 12:53:57.326231 GEN_PMCON: d0015038 00002200
309 12:53:57.329328 GBLRST_CAUSE: 00000000 00000000
310 12:53:57.333200 HPR_CAUSE0: 00000000
311 12:53:57.333773 prev_sleep_state 5
312 12:53:57.336314 Boot Count incremented to 18203
313 12:53:57.342919 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
314 12:53:57.349564 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
315 12:53:57.359482 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
316 12:53:57.366124 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
317 12:53:57.369122 Chrome EC: UHEPI supported
318 12:53:57.376000 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
319 12:53:57.388103 Probing TPM: done!
320 12:53:57.395268 Connected to device vid:did:rid of 1ae0:0028:00
321 12:53:57.402801 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
322 12:53:57.412599 Initialized TPM device CR50 revision 0
323 12:53:57.422625 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
324 12:53:57.429250 MRC: Hash idx 0x100b comparison successful.
325 12:53:57.432456 MRC cache found, size faa8
326 12:53:57.432993 bootmode is set to: 2
327 12:53:57.435950 SPD index = 0
328 12:53:57.442515 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
329 12:53:57.445972 SPD: module type is LPDDR4X
330 12:53:57.449065 SPD: module part number is MT53E512M64D4NW-046
331 12:53:57.455413 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
332 12:53:57.458898 SPD: device width 16 bits, bus width 16 bits
333 12:53:57.465407 SPD: module size is 1024 MB (per channel)
334 12:53:57.896718 CBMEM:
335 12:53:57.899687 IMD: root @ 0x76fff000 254 entries.
336 12:53:57.903047 IMD: root @ 0x76ffec00 62 entries.
337 12:53:57.906353 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
338 12:53:57.912847 FMAP: area RW_VPD found @ f35000 (8192 bytes)
339 12:53:57.916281 External stage cache:
340 12:53:57.919553 IMD: root @ 0x7b3ff000 254 entries.
341 12:53:57.923305 IMD: root @ 0x7b3fec00 62 entries.
342 12:53:57.938349 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
343 12:53:57.944649 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
344 12:53:57.951347 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
345 12:53:57.965688 MRC: 'RECOVERY_MRC_CACHE' does not need update.
346 12:53:57.972087 cse_lite: Skip switching to RW in the recovery path
347 12:53:57.972614 8 DIMMs found
348 12:53:57.972982 SMM Memory Map
349 12:53:57.976052 SMRAM : 0x7b000000 0x800000
350 12:53:57.979661 Subregion 0: 0x7b000000 0x200000
351 12:53:57.983480 Subregion 1: 0x7b200000 0x200000
352 12:53:57.986800 Subregion 2: 0x7b400000 0x400000
353 12:53:57.990176 top_of_ram = 0x77000000
354 12:53:57.996585 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
355 12:53:57.999809 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
356 12:53:58.006487 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
357 12:53:58.009750 MTRR Range: Start=ff000000 End=0 (Size 1000000)
358 12:53:58.019739 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
359 12:53:58.025889 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
360 12:53:58.035848 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
361 12:53:58.039257 Processing 211 relocs. Offset value of 0x74c0b000
362 12:53:58.047964 BS: romstage times (exec / console): total (unknown) / 277 ms
363 12:53:58.054293
364 12:53:58.054843
365 12:53:58.064379 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
366 12:53:58.067721 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
367 12:53:58.077316 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
368 12:53:58.083960 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
369 12:53:58.091037 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
370 12:53:58.097445 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
371 12:53:58.144253 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
372 12:53:58.150872 Processing 5008 relocs. Offset value of 0x75d98000
373 12:53:58.153979 BS: postcar times (exec / console): total (unknown) / 59 ms
374 12:53:58.157648
375 12:53:58.158100
376 12:53:58.167356 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
377 12:53:58.167904 Normal boot
378 12:53:58.171163 FW_CONFIG value is 0x804c02
379 12:53:58.174534 PCI: 00:07.0 disabled by fw_config
380 12:53:58.177601 PCI: 00:07.1 disabled by fw_config
381 12:53:58.180718 PCI: 00:0d.2 disabled by fw_config
382 12:53:58.184819 PCI: 00:1c.7 disabled by fw_config
383 12:53:58.191643 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
384 12:53:58.198214 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
385 12:53:58.200730 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
386 12:53:58.204084 GENERIC: 0.0 disabled by fw_config
387 12:53:58.208285 GENERIC: 1.0 disabled by fw_config
388 12:53:58.214291 fw_config match found: DB_USB=USB3_ACTIVE
389 12:53:58.217806 fw_config match found: DB_USB=USB3_ACTIVE
390 12:53:58.221269 fw_config match found: DB_USB=USB3_ACTIVE
391 12:53:58.227637 fw_config match found: DB_USB=USB3_ACTIVE
392 12:53:58.231222 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
393 12:53:58.237676 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
394 12:53:58.247447 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
395 12:53:58.254387 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
396 12:53:58.257504 microcode: sig=0x806c1 pf=0x80 revision=0x86
397 12:53:58.264060 microcode: Update skipped, already up-to-date
398 12:53:58.270572 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
399 12:53:58.298277 Detected 4 core, 8 thread CPU.
400 12:53:58.301239 Setting up SMI for CPU
401 12:53:58.304653 IED base = 0x7b400000
402 12:53:58.305191 IED size = 0x00400000
403 12:53:58.307902 Will perform SMM setup.
404 12:53:58.314597 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
405 12:53:58.321379 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
406 12:53:58.328257 Processing 16 relocs. Offset value of 0x00030000
407 12:53:58.331630 Attempting to start 7 APs
408 12:53:58.334348 Waiting for 10ms after sending INIT.
409 12:53:58.349949 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
410 12:53:58.350476 done.
411 12:53:58.353245 AP: slot 2 apic_id 3.
412 12:53:58.356430 AP: slot 6 apic_id 2.
413 12:53:58.356952 AP: slot 3 apic_id 5.
414 12:53:58.359575 AP: slot 7 apic_id 4.
415 12:53:58.363083 AP: slot 5 apic_id 6.
416 12:53:58.367010 Waiting for 2nd SIPI to complete...done.
417 12:53:58.369965 AP: slot 4 apic_id 7.
418 12:53:58.376517 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
419 12:53:58.383267 Processing 13 relocs. Offset value of 0x00038000
420 12:53:58.386544 Unable to locate Global NVS
421 12:53:58.393317 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
422 12:53:58.396804 Installing permanent SMM handler to 0x7b000000
423 12:53:58.406279 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
424 12:53:58.409731 Processing 794 relocs. Offset value of 0x7b010000
425 12:53:58.419693 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
426 12:53:58.422914 Processing 13 relocs. Offset value of 0x7b008000
427 12:53:58.429357 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
428 12:53:58.436446 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
429 12:53:58.439365 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
430 12:53:58.446001 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
431 12:53:58.452542 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
432 12:53:58.459090 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
433 12:53:58.465487 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
434 12:53:58.465928 Unable to locate Global NVS
435 12:53:58.475905 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
436 12:53:58.479470 Clearing SMI status registers
437 12:53:58.480014 SMI_STS: PM1
438 12:53:58.482424 PM1_STS: PWRBTN
439 12:53:58.488956 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
440 12:53:58.492213 In relocation handler: CPU 0
441 12:53:58.495958 New SMBASE=0x7b000000 IEDBASE=0x7b400000
442 12:53:58.501978 Writing SMRR. base = 0x7b000006, mask=0xff800c00
443 12:53:58.502555 Relocation complete.
444 12:53:58.512052 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
445 12:53:58.515384 In relocation handler: CPU 1
446 12:53:58.518734 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
447 12:53:58.519255 Relocation complete.
448 12:53:58.528649 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
449 12:53:58.532265 In relocation handler: CPU 4
450 12:53:58.536013 New SMBASE=0x7afff000 IEDBASE=0x7b400000
451 12:53:58.536614 Relocation complete.
452 12:53:58.545062 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
453 12:53:58.545498 In relocation handler: CPU 5
454 12:53:58.551838 New SMBASE=0x7affec00 IEDBASE=0x7b400000
455 12:53:58.555150 Writing SMRR. base = 0x7b000006, mask=0xff800c00
456 12:53:58.558467 Relocation complete.
457 12:53:58.565417 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
458 12:53:58.568419 In relocation handler: CPU 3
459 12:53:58.571920 New SMBASE=0x7afff400 IEDBASE=0x7b400000
460 12:53:58.575215 Relocation complete.
461 12:53:58.581792 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
462 12:53:58.585268 In relocation handler: CPU 7
463 12:53:58.588376 New SMBASE=0x7affe400 IEDBASE=0x7b400000
464 12:53:58.595388 Writing SMRR. base = 0x7b000006, mask=0xff800c00
465 12:53:58.595984 Relocation complete.
466 12:53:58.601751 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
467 12:53:58.604887 In relocation handler: CPU 2
468 12:53:58.611439 New SMBASE=0x7afff800 IEDBASE=0x7b400000
469 12:53:58.612082 Relocation complete.
470 12:53:58.618171 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
471 12:53:58.621520 In relocation handler: CPU 6
472 12:53:58.627865 New SMBASE=0x7affe800 IEDBASE=0x7b400000
473 12:53:58.631120 Writing SMRR. base = 0x7b000006, mask=0xff800c00
474 12:53:58.634792 Relocation complete.
475 12:53:58.635328 Initializing CPU #0
476 12:53:58.638640 CPU: vendor Intel device 806c1
477 12:53:58.641950 CPU: family 06, model 8c, stepping 01
478 12:53:58.644890 Clearing out pending MCEs
479 12:53:58.648253 Setting up local APIC...
480 12:53:58.651708 apic_id: 0x00 done.
481 12:53:58.655268 Turbo is available but hidden
482 12:53:58.655863 Turbo is available and visible
483 12:53:58.661965 microcode: Update skipped, already up-to-date
484 12:53:58.665054 CPU #0 initialized
485 12:53:58.665576 Initializing CPU #4
486 12:53:58.668652 Initializing CPU #5
487 12:53:58.671853 CPU: vendor Intel device 806c1
488 12:53:58.675037 CPU: family 06, model 8c, stepping 01
489 12:53:58.678600 CPU: vendor Intel device 806c1
490 12:53:58.681857 CPU: family 06, model 8c, stepping 01
491 12:53:58.684923 Clearing out pending MCEs
492 12:53:58.688487 Clearing out pending MCEs
493 12:53:58.688926 Setting up local APIC...
494 12:53:58.691491 Initializing CPU #1
495 12:53:58.695379 Setting up local APIC...
496 12:53:58.695987 Initializing CPU #6
497 12:53:58.698585 Initializing CPU #2
498 12:53:58.701323 CPU: vendor Intel device 806c1
499 12:53:58.705095 CPU: family 06, model 8c, stepping 01
500 12:53:58.708316 Initializing CPU #7
501 12:53:58.708841 Initializing CPU #3
502 12:53:58.711699 CPU: vendor Intel device 806c1
503 12:53:58.714712 CPU: family 06, model 8c, stepping 01
504 12:53:58.718093 CPU: vendor Intel device 806c1
505 12:53:58.721458 CPU: family 06, model 8c, stepping 01
506 12:53:58.724698 Clearing out pending MCEs
507 12:53:58.728301 Clearing out pending MCEs
508 12:53:58.731720 Setting up local APIC...
509 12:53:58.734980 CPU: vendor Intel device 806c1
510 12:53:58.738067 CPU: family 06, model 8c, stepping 01
511 12:53:58.741374 Clearing out pending MCEs
512 12:53:58.741821 Clearing out pending MCEs
513 12:53:58.744591 Setting up local APIC...
514 12:53:58.748096 apic_id: 0x07 done.
515 12:53:58.751552 apic_id: 0x06 done.
516 12:53:58.754877 microcode: Update skipped, already up-to-date
517 12:53:58.758109 microcode: Update skipped, already up-to-date
518 12:53:58.761510 CPU #4 initialized
519 12:53:58.761948 CPU #5 initialized
520 12:53:58.764790 apic_id: 0x02 done.
521 12:53:58.768195 Setting up local APIC...
522 12:53:58.770998 CPU: vendor Intel device 806c1
523 12:53:58.774181 CPU: family 06, model 8c, stepping 01
524 12:53:58.777605 Setting up local APIC...
525 12:53:58.778043 apic_id: 0x03 done.
526 12:53:58.781431 Clearing out pending MCEs
527 12:53:58.784767 apic_id: 0x04 done.
528 12:53:58.785415 apic_id: 0x05 done.
529 12:53:58.791313 microcode: Update skipped, already up-to-date
530 12:53:58.794202 microcode: Update skipped, already up-to-date
531 12:53:58.797650 CPU #7 initialized
532 12:53:58.798085 CPU #3 initialized
533 12:53:58.804210 microcode: Update skipped, already up-to-date
534 12:53:58.808079 microcode: Update skipped, already up-to-date
535 12:53:58.811544 CPU #6 initialized
536 12:53:58.812158 CPU #2 initialized
537 12:53:58.814465 Setting up local APIC...
538 12:53:58.817781 apic_id: 0x01 done.
539 12:53:58.821220 microcode: Update skipped, already up-to-date
540 12:53:58.824400 CPU #1 initialized
541 12:53:58.827452 bsp_do_flight_plan done after 457 msecs.
542 12:53:58.831512 CPU: frequency set to 4000 MHz
543 12:53:58.834365 Enabling SMIs.
544 12:53:58.837815 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
545 12:53:58.855160 SATAXPCIE1 indicates PCIe NVMe is present
546 12:53:58.858303 Probing TPM: done!
547 12:53:58.862320 Connected to device vid:did:rid of 1ae0:0028:00
548 12:53:58.872553 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
549 12:53:58.875906 Initialized TPM device CR50 revision 0
550 12:53:58.878668 Enabling S0i3.4
551 12:53:58.885525 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
552 12:53:58.888865 Found a VBT of 8704 bytes after decompression
553 12:53:58.895720 cse_lite: CSE RO boot. HybridStorageMode disabled
554 12:53:58.901994 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
555 12:53:58.977656 FSPS returned 0
556 12:53:58.981197 Executing Phase 1 of FspMultiPhaseSiInit
557 12:53:58.991149 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
558 12:53:58.994727 port C0 DISC req: usage 1 usb3 1 usb2 5
559 12:53:58.998039 Raw Buffer output 0 00000511
560 12:53:59.001100 Raw Buffer output 1 00000000
561 12:53:59.004980 pmc_send_ipc_cmd succeeded
562 12:53:59.011028 port C1 DISC req: usage 1 usb3 2 usb2 3
563 12:53:59.011462 Raw Buffer output 0 00000321
564 12:53:59.014616 Raw Buffer output 1 00000000
565 12:53:59.018949 pmc_send_ipc_cmd succeeded
566 12:53:59.023808 Detected 4 core, 8 thread CPU.
567 12:53:59.027361 Detected 4 core, 8 thread CPU.
568 12:53:59.260986 Display FSP Version Info HOB
569 12:53:59.264638 Reference Code - CPU = a.0.4c.31
570 12:53:59.267830 uCode Version = 0.0.0.86
571 12:53:59.271111 TXT ACM version = ff.ff.ff.ffff
572 12:53:59.274487 Reference Code - ME = a.0.4c.31
573 12:53:59.277716 MEBx version = 0.0.0.0
574 12:53:59.281119 ME Firmware Version = Consumer SKU
575 12:53:59.284431 Reference Code - PCH = a.0.4c.31
576 12:53:59.287772 PCH-CRID Status = Disabled
577 12:53:59.291077 PCH-CRID Original Value = ff.ff.ff.ffff
578 12:53:59.294372 PCH-CRID New Value = ff.ff.ff.ffff
579 12:53:59.297755 OPROM - RST - RAID = ff.ff.ff.ffff
580 12:53:59.301006 PCH Hsio Version = 4.0.0.0
581 12:53:59.304132 Reference Code - SA - System Agent = a.0.4c.31
582 12:53:59.307572 Reference Code - MRC = 2.0.0.1
583 12:53:59.310973 SA - PCIe Version = a.0.4c.31
584 12:53:59.314515 SA-CRID Status = Disabled
585 12:53:59.317438 SA-CRID Original Value = 0.0.0.1
586 12:53:59.320807 SA-CRID New Value = 0.0.0.1
587 12:53:59.324016 OPROM - VBIOS = ff.ff.ff.ffff
588 12:53:59.327546 IO Manageability Engine FW Version = 11.1.4.0
589 12:53:59.330549 PHY Build Version = 0.0.0.e0
590 12:53:59.334135 Thunderbolt(TM) FW Version = 0.0.0.0
591 12:53:59.340899 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
592 12:53:59.344421 ITSS IRQ Polarities Before:
593 12:53:59.344855 IPC0: 0xffffffff
594 12:53:59.347207 IPC1: 0xffffffff
595 12:53:59.347676 IPC2: 0xffffffff
596 12:53:59.350818 IPC3: 0xffffffff
597 12:53:59.353992 ITSS IRQ Polarities After:
598 12:53:59.354528 IPC0: 0xffffffff
599 12:53:59.357331 IPC1: 0xffffffff
600 12:53:59.357869 IPC2: 0xffffffff
601 12:53:59.360500 IPC3: 0xffffffff
602 12:53:59.363831 Found PCIe Root Port #9 at PCI: 00:1d.0.
603 12:53:59.377441 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
604 12:53:59.387229 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
605 12:53:59.400536 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
606 12:53:59.407343 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
607 12:53:59.410768 Enumerating buses...
608 12:53:59.413944 Show all devs... Before device enumeration.
609 12:53:59.417148 Root Device: enabled 1
610 12:53:59.417584 DOMAIN: 0000: enabled 1
611 12:53:59.420541 CPU_CLUSTER: 0: enabled 1
612 12:53:59.423912 PCI: 00:00.0: enabled 1
613 12:53:59.427008 PCI: 00:02.0: enabled 1
614 12:53:59.427467 PCI: 00:04.0: enabled 1
615 12:53:59.430262 PCI: 00:05.0: enabled 1
616 12:53:59.433927 PCI: 00:06.0: enabled 0
617 12:53:59.434461 PCI: 00:07.0: enabled 0
618 12:53:59.437009 PCI: 00:07.1: enabled 0
619 12:53:59.440331 PCI: 00:07.2: enabled 0
620 12:53:59.443572 PCI: 00:07.3: enabled 0
621 12:53:59.444026 PCI: 00:08.0: enabled 1
622 12:53:59.446762 PCI: 00:09.0: enabled 0
623 12:53:59.450005 PCI: 00:0a.0: enabled 0
624 12:53:59.453500 PCI: 00:0d.0: enabled 1
625 12:53:59.453941 PCI: 00:0d.1: enabled 0
626 12:53:59.457267 PCI: 00:0d.2: enabled 0
627 12:53:59.460424 PCI: 00:0d.3: enabled 0
628 12:53:59.463286 PCI: 00:0e.0: enabled 0
629 12:53:59.463808 PCI: 00:10.2: enabled 1
630 12:53:59.466967 PCI: 00:10.6: enabled 0
631 12:53:59.470594 PCI: 00:10.7: enabled 0
632 12:53:59.473369 PCI: 00:12.0: enabled 0
633 12:53:59.473871 PCI: 00:12.6: enabled 0
634 12:53:59.477186 PCI: 00:13.0: enabled 0
635 12:53:59.480051 PCI: 00:14.0: enabled 1
636 12:53:59.480497 PCI: 00:14.1: enabled 0
637 12:53:59.483704 PCI: 00:14.2: enabled 1
638 12:53:59.486993 PCI: 00:14.3: enabled 1
639 12:53:59.490222 PCI: 00:15.0: enabled 1
640 12:53:59.490656 PCI: 00:15.1: enabled 1
641 12:53:59.493919 PCI: 00:15.2: enabled 1
642 12:53:59.497221 PCI: 00:15.3: enabled 1
643 12:53:59.500423 PCI: 00:16.0: enabled 1
644 12:53:59.500966 PCI: 00:16.1: enabled 0
645 12:53:59.503539 PCI: 00:16.2: enabled 0
646 12:53:59.507072 PCI: 00:16.3: enabled 0
647 12:53:59.510510 PCI: 00:16.4: enabled 0
648 12:53:59.511067 PCI: 00:16.5: enabled 0
649 12:53:59.513503 PCI: 00:17.0: enabled 1
650 12:53:59.516813 PCI: 00:19.0: enabled 0
651 12:53:59.517349 PCI: 00:19.1: enabled 1
652 12:53:59.520012 PCI: 00:19.2: enabled 0
653 12:53:59.523860 PCI: 00:1c.0: enabled 1
654 12:53:59.527092 PCI: 00:1c.1: enabled 0
655 12:53:59.527709 PCI: 00:1c.2: enabled 0
656 12:53:59.530202 PCI: 00:1c.3: enabled 0
657 12:53:59.533456 PCI: 00:1c.4: enabled 0
658 12:53:59.536964 PCI: 00:1c.5: enabled 0
659 12:53:59.537512 PCI: 00:1c.6: enabled 1
660 12:53:59.540470 PCI: 00:1c.7: enabled 0
661 12:53:59.543641 PCI: 00:1d.0: enabled 1
662 12:53:59.546474 PCI: 00:1d.1: enabled 0
663 12:53:59.546910 PCI: 00:1d.2: enabled 1
664 12:53:59.549728 PCI: 00:1d.3: enabled 0
665 12:53:59.553433 PCI: 00:1e.0: enabled 1
666 12:53:59.556782 PCI: 00:1e.1: enabled 0
667 12:53:59.557318 PCI: 00:1e.2: enabled 1
668 12:53:59.559764 PCI: 00:1e.3: enabled 1
669 12:53:59.563473 PCI: 00:1f.0: enabled 1
670 12:53:59.564115 PCI: 00:1f.1: enabled 0
671 12:53:59.566326 PCI: 00:1f.2: enabled 1
672 12:53:59.569803 PCI: 00:1f.3: enabled 1
673 12:53:59.573439 PCI: 00:1f.4: enabled 0
674 12:53:59.573878 PCI: 00:1f.5: enabled 1
675 12:53:59.576458 PCI: 00:1f.6: enabled 0
676 12:53:59.579824 PCI: 00:1f.7: enabled 0
677 12:53:59.580294 APIC: 00: enabled 1
678 12:53:59.583052 GENERIC: 0.0: enabled 1
679 12:53:59.586721 GENERIC: 0.0: enabled 1
680 12:53:59.590336 GENERIC: 1.0: enabled 1
681 12:53:59.590942 GENERIC: 0.0: enabled 1
682 12:53:59.593436 GENERIC: 1.0: enabled 1
683 12:53:59.596774 USB0 port 0: enabled 1
684 12:53:59.600435 GENERIC: 0.0: enabled 1
685 12:53:59.600978 USB0 port 0: enabled 1
686 12:53:59.602877 GENERIC: 0.0: enabled 1
687 12:53:59.606353 I2C: 00:1a: enabled 1
688 12:53:59.606792 I2C: 00:31: enabled 1
689 12:53:59.609599 I2C: 00:32: enabled 1
690 12:53:59.613018 I2C: 00:10: enabled 1
691 12:53:59.613460 I2C: 00:15: enabled 1
692 12:53:59.616223 GENERIC: 0.0: enabled 0
693 12:53:59.619702 GENERIC: 1.0: enabled 0
694 12:53:59.622878 GENERIC: 0.0: enabled 1
695 12:53:59.623417 SPI: 00: enabled 1
696 12:53:59.626734 SPI: 00: enabled 1
697 12:53:59.629796 PNP: 0c09.0: enabled 1
698 12:53:59.630338 GENERIC: 0.0: enabled 1
699 12:53:59.632964 USB3 port 0: enabled 1
700 12:53:59.636629 USB3 port 1: enabled 1
701 12:53:59.637107 USB3 port 2: enabled 0
702 12:53:59.639358 USB3 port 3: enabled 0
703 12:53:59.642906 USB2 port 0: enabled 0
704 12:53:59.643338 USB2 port 1: enabled 1
705 12:53:59.646521 USB2 port 2: enabled 1
706 12:53:59.649580 USB2 port 3: enabled 0
707 12:53:59.652738 USB2 port 4: enabled 1
708 12:53:59.653172 USB2 port 5: enabled 0
709 12:53:59.656127 USB2 port 6: enabled 0
710 12:53:59.659402 USB2 port 7: enabled 0
711 12:53:59.659885 USB2 port 8: enabled 0
712 12:53:59.662650 USB2 port 9: enabled 0
713 12:53:59.666414 USB3 port 0: enabled 0
714 12:53:59.669237 USB3 port 1: enabled 1
715 12:53:59.669815 USB3 port 2: enabled 0
716 12:53:59.673032 USB3 port 3: enabled 0
717 12:53:59.676135 GENERIC: 0.0: enabled 1
718 12:53:59.676714 GENERIC: 1.0: enabled 1
719 12:53:59.679629 APIC: 01: enabled 1
720 12:53:59.682526 APIC: 03: enabled 1
721 12:53:59.683045 APIC: 05: enabled 1
722 12:53:59.686024 APIC: 07: enabled 1
723 12:53:59.689241 APIC: 06: enabled 1
724 12:53:59.689671 APIC: 02: enabled 1
725 12:53:59.693088 APIC: 04: enabled 1
726 12:53:59.693629 Compare with tree...
727 12:53:59.696097 Root Device: enabled 1
728 12:53:59.699223 DOMAIN: 0000: enabled 1
729 12:53:59.702513 PCI: 00:00.0: enabled 1
730 12:53:59.702974 PCI: 00:02.0: enabled 1
731 12:53:59.705641 PCI: 00:04.0: enabled 1
732 12:53:59.709162 GENERIC: 0.0: enabled 1
733 12:53:59.712475 PCI: 00:05.0: enabled 1
734 12:53:59.715641 PCI: 00:06.0: enabled 0
735 12:53:59.716097 PCI: 00:07.0: enabled 0
736 12:53:59.718964 GENERIC: 0.0: enabled 1
737 12:53:59.722169 PCI: 00:07.1: enabled 0
738 12:53:59.725994 GENERIC: 1.0: enabled 1
739 12:53:59.729334 PCI: 00:07.2: enabled 0
740 12:53:59.732170 GENERIC: 0.0: enabled 1
741 12:53:59.732605 PCI: 00:07.3: enabled 0
742 12:53:59.736024 GENERIC: 1.0: enabled 1
743 12:53:59.739280 PCI: 00:08.0: enabled 1
744 12:53:59.742620 PCI: 00:09.0: enabled 0
745 12:53:59.745787 PCI: 00:0a.0: enabled 0
746 12:53:59.746221 PCI: 00:0d.0: enabled 1
747 12:53:59.748918 USB0 port 0: enabled 1
748 12:53:59.752199 USB3 port 0: enabled 1
749 12:53:59.755887 USB3 port 1: enabled 1
750 12:53:59.759345 USB3 port 2: enabled 0
751 12:53:59.759811 USB3 port 3: enabled 0
752 12:53:59.762593 PCI: 00:0d.1: enabled 0
753 12:53:59.765944 PCI: 00:0d.2: enabled 0
754 12:53:59.768958 GENERIC: 0.0: enabled 1
755 12:53:59.772019 PCI: 00:0d.3: enabled 0
756 12:53:59.772484 PCI: 00:0e.0: enabled 0
757 12:53:59.775285 PCI: 00:10.2: enabled 1
758 12:53:59.778694 PCI: 00:10.6: enabled 0
759 12:53:59.782097 PCI: 00:10.7: enabled 0
760 12:53:59.785591 PCI: 00:12.0: enabled 0
761 12:53:59.786029 PCI: 00:12.6: enabled 0
762 12:53:59.788582 PCI: 00:13.0: enabled 0
763 12:53:59.792048 PCI: 00:14.0: enabled 1
764 12:53:59.795305 USB0 port 0: enabled 1
765 12:53:59.798702 USB2 port 0: enabled 0
766 12:53:59.799143 USB2 port 1: enabled 1
767 12:53:59.802262 USB2 port 2: enabled 1
768 12:53:59.805901 USB2 port 3: enabled 0
769 12:53:59.808706 USB2 port 4: enabled 1
770 12:53:59.812074 USB2 port 5: enabled 0
771 12:53:59.815274 USB2 port 6: enabled 0
772 12:53:59.815739 USB2 port 7: enabled 0
773 12:53:59.818604 USB2 port 8: enabled 0
774 12:53:59.821964 USB2 port 9: enabled 0
775 12:53:59.825611 USB3 port 0: enabled 0
776 12:53:59.828503 USB3 port 1: enabled 1
777 12:53:59.831929 USB3 port 2: enabled 0
778 12:53:59.832448 USB3 port 3: enabled 0
779 12:53:59.835114 PCI: 00:14.1: enabled 0
780 12:53:59.838466 PCI: 00:14.2: enabled 1
781 12:53:59.842262 PCI: 00:14.3: enabled 1
782 12:53:59.845641 GENERIC: 0.0: enabled 1
783 12:53:59.846075 PCI: 00:15.0: enabled 1
784 12:53:59.848758 I2C: 00:1a: enabled 1
785 12:53:59.851971 I2C: 00:31: enabled 1
786 12:53:59.855232 I2C: 00:32: enabled 1
787 12:53:59.855708 PCI: 00:15.1: enabled 1
788 12:53:59.858438 I2C: 00:10: enabled 1
789 12:53:59.861857 PCI: 00:15.2: enabled 1
790 12:53:59.865085 PCI: 00:15.3: enabled 1
791 12:53:59.868333 PCI: 00:16.0: enabled 1
792 12:53:59.868769 PCI: 00:16.1: enabled 0
793 12:53:59.871660 PCI: 00:16.2: enabled 0
794 12:53:59.874987 PCI: 00:16.3: enabled 0
795 12:53:59.878986 PCI: 00:16.4: enabled 0
796 12:53:59.881562 PCI: 00:16.5: enabled 0
797 12:53:59.882000 PCI: 00:17.0: enabled 1
798 12:53:59.885383 PCI: 00:19.0: enabled 0
799 12:53:59.888907 PCI: 00:19.1: enabled 1
800 12:53:59.892651 I2C: 00:15: enabled 1
801 12:53:59.893091 PCI: 00:19.2: enabled 0
802 12:53:59.896008 PCI: 00:1d.0: enabled 1
803 12:53:59.899842 GENERIC: 0.0: enabled 1
804 12:53:59.902758 PCI: 00:1e.0: enabled 1
805 12:53:59.903297 PCI: 00:1e.1: enabled 0
806 12:53:59.906119 PCI: 00:1e.2: enabled 1
807 12:53:59.910199 SPI: 00: enabled 1
808 12:53:59.912912 PCI: 00:1e.3: enabled 1
809 12:53:59.913378 SPI: 00: enabled 1
810 12:53:59.963261 PCI: 00:1f.0: enabled 1
811 12:53:59.963912 PNP: 0c09.0: enabled 1
812 12:53:59.964289 PCI: 00:1f.1: enabled 0
813 12:53:59.964624 PCI: 00:1f.2: enabled 1
814 12:53:59.964938 GENERIC: 0.0: enabled 1
815 12:53:59.965259 GENERIC: 0.0: enabled 1
816 12:53:59.965592 GENERIC: 1.0: enabled 1
817 12:53:59.966224 PCI: 00:1f.3: enabled 1
818 12:53:59.966556 PCI: 00:1f.4: enabled 0
819 12:53:59.966862 PCI: 00:1f.5: enabled 1
820 12:53:59.967164 PCI: 00:1f.6: enabled 0
821 12:53:59.967488 PCI: 00:1f.7: enabled 0
822 12:53:59.967872 CPU_CLUSTER: 0: enabled 1
823 12:53:59.968170 APIC: 00: enabled 1
824 12:53:59.968461 APIC: 01: enabled 1
825 12:53:59.968751 APIC: 03: enabled 1
826 12:53:59.969043 APIC: 05: enabled 1
827 12:53:59.969328 APIC: 07: enabled 1
828 12:53:59.969611 APIC: 06: enabled 1
829 12:53:59.969896 APIC: 02: enabled 1
830 12:54:00.015281 APIC: 04: enabled 1
831 12:54:00.015885 Root Device scanning...
832 12:54:00.016323 scan_static_bus for Root Device
833 12:54:00.016665 DOMAIN: 0000 enabled
834 12:54:00.016992 CPU_CLUSTER: 0 enabled
835 12:54:00.017624 DOMAIN: 0000 scanning...
836 12:54:00.017979 PCI: pci_scan_bus for bus 00
837 12:54:00.018332 PCI: 00:00.0 [8086/0000] ops
838 12:54:00.018641 PCI: 00:00.0 [8086/9a12] enabled
839 12:54:00.018944 PCI: 00:02.0 [8086/0000] bus ops
840 12:54:00.019242 PCI: 00:02.0 [8086/9a40] enabled
841 12:54:00.019535 PCI: 00:04.0 [8086/0000] bus ops
842 12:54:00.019871 PCI: 00:04.0 [8086/9a03] enabled
843 12:54:00.020202 PCI: 00:05.0 [8086/9a19] enabled
844 12:54:00.020519 PCI: 00:07.0 [0000/0000] hidden
845 12:54:00.020807 PCI: 00:08.0 [8086/9a11] enabled
846 12:54:00.031626 PCI: 00:0a.0 [8086/9a0d] disabled
847 12:54:00.032165 PCI: 00:0d.0 [8086/0000] bus ops
848 12:54:00.032522 PCI: 00:0d.0 [8086/9a13] enabled
849 12:54:00.032855 PCI: 00:14.0 [8086/0000] bus ops
850 12:54:00.035493 PCI: 00:14.0 [8086/a0ed] enabled
851 12:54:00.036082 PCI: 00:14.2 [8086/a0ef] enabled
852 12:54:00.038076 PCI: 00:14.3 [8086/0000] bus ops
853 12:54:00.041865 PCI: 00:14.3 [8086/a0f0] enabled
854 12:54:00.045246 PCI: 00:15.0 [8086/0000] bus ops
855 12:54:00.048982 PCI: 00:15.0 [8086/a0e8] enabled
856 12:54:00.051312 PCI: 00:15.1 [8086/0000] bus ops
857 12:54:00.054965 PCI: 00:15.1 [8086/a0e9] enabled
858 12:54:00.058421 PCI: 00:15.2 [8086/0000] bus ops
859 12:54:00.061743 PCI: 00:15.2 [8086/a0ea] enabled
860 12:54:00.064858 PCI: 00:15.3 [8086/0000] bus ops
861 12:54:00.068223 PCI: 00:15.3 [8086/a0eb] enabled
862 12:54:00.071569 PCI: 00:16.0 [8086/0000] ops
863 12:54:00.075149 PCI: 00:16.0 [8086/a0e0] enabled
864 12:54:00.078229 PCI: Static device PCI: 00:17.0 not found, disabling it.
865 12:54:00.081545 PCI: 00:19.0 [8086/0000] bus ops
866 12:54:00.084940 PCI: 00:19.0 [8086/a0c5] disabled
867 12:54:00.088107 PCI: 00:19.1 [8086/0000] bus ops
868 12:54:00.091951 PCI: 00:19.1 [8086/a0c6] enabled
869 12:54:00.095191 PCI: 00:1d.0 [8086/0000] bus ops
870 12:54:00.098079 PCI: 00:1d.0 [8086/a0b0] enabled
871 12:54:00.101171 PCI: 00:1e.0 [8086/0000] ops
872 12:54:00.104810 PCI: 00:1e.0 [8086/a0a8] enabled
873 12:54:00.108266 PCI: 00:1e.2 [8086/0000] bus ops
874 12:54:00.111246 PCI: 00:1e.2 [8086/a0aa] enabled
875 12:54:00.115002 PCI: 00:1e.3 [8086/0000] bus ops
876 12:54:00.117830 PCI: 00:1e.3 [8086/a0ab] enabled
877 12:54:00.121211 PCI: 00:1f.0 [8086/0000] bus ops
878 12:54:00.124492 PCI: 00:1f.0 [8086/a087] enabled
879 12:54:00.128000 RTC Init
880 12:54:00.130840 Set power on after power failure.
881 12:54:00.131286 Disabling Deep S3
882 12:54:00.134125 Disabling Deep S3
883 12:54:00.137661 Disabling Deep S4
884 12:54:00.138093 Disabling Deep S4
885 12:54:00.140763 Disabling Deep S5
886 12:54:00.141311 Disabling Deep S5
887 12:54:00.144213 PCI: 00:1f.2 [0000/0000] hidden
888 12:54:00.147415 PCI: 00:1f.3 [8086/0000] bus ops
889 12:54:00.150897 PCI: 00:1f.3 [8086/a0c8] enabled
890 12:54:00.154026 PCI: 00:1f.5 [8086/0000] bus ops
891 12:54:00.157525 PCI: 00:1f.5 [8086/a0a4] enabled
892 12:54:00.160543 PCI: Leftover static devices:
893 12:54:00.164474 PCI: 00:10.2
894 12:54:00.164927 PCI: 00:10.6
895 12:54:00.165271 PCI: 00:10.7
896 12:54:00.167714 PCI: 00:06.0
897 12:54:00.168148 PCI: 00:07.1
898 12:54:00.171275 PCI: 00:07.2
899 12:54:00.171748 PCI: 00:07.3
900 12:54:00.172104 PCI: 00:09.0
901 12:54:00.174568 PCI: 00:0d.1
902 12:54:00.174930 PCI: 00:0d.2
903 12:54:00.177970 PCI: 00:0d.3
904 12:54:00.178401 PCI: 00:0e.0
905 12:54:00.178748 PCI: 00:12.0
906 12:54:00.181136 PCI: 00:12.6
907 12:54:00.181564 PCI: 00:13.0
908 12:54:00.184572 PCI: 00:14.1
909 12:54:00.185102 PCI: 00:16.1
910 12:54:00.188140 PCI: 00:16.2
911 12:54:00.188666 PCI: 00:16.3
912 12:54:00.189015 PCI: 00:16.4
913 12:54:00.191512 PCI: 00:16.5
914 12:54:00.192206 PCI: 00:17.0
915 12:54:00.194750 PCI: 00:19.2
916 12:54:00.195278 PCI: 00:1e.1
917 12:54:00.195671 PCI: 00:1f.1
918 12:54:00.197231 PCI: 00:1f.4
919 12:54:00.197660 PCI: 00:1f.6
920 12:54:00.201228 PCI: 00:1f.7
921 12:54:00.204268 PCI: Check your devicetree.cb.
922 12:54:00.204802 PCI: 00:02.0 scanning...
923 12:54:00.210732 scan_generic_bus for PCI: 00:02.0
924 12:54:00.214170 scan_generic_bus for PCI: 00:02.0 done
925 12:54:00.217420 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
926 12:54:00.220498 PCI: 00:04.0 scanning...
927 12:54:00.224143 scan_generic_bus for PCI: 00:04.0
928 12:54:00.227392 GENERIC: 0.0 enabled
929 12:54:00.230427 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
930 12:54:00.237202 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
931 12:54:00.240887 PCI: 00:0d.0 scanning...
932 12:54:00.243898 scan_static_bus for PCI: 00:0d.0
933 12:54:00.244347 USB0 port 0 enabled
934 12:54:00.247109 USB0 port 0 scanning...
935 12:54:00.250049 scan_static_bus for USB0 port 0
936 12:54:00.253704 USB3 port 0 enabled
937 12:54:00.254160 USB3 port 1 enabled
938 12:54:00.256961 USB3 port 2 disabled
939 12:54:00.260529 USB3 port 3 disabled
940 12:54:00.261087 USB3 port 0 scanning...
941 12:54:00.263832 scan_static_bus for USB3 port 0
942 12:54:00.270081 scan_static_bus for USB3 port 0 done
943 12:54:00.273853 scan_bus: bus USB3 port 0 finished in 6 msecs
944 12:54:00.276736 USB3 port 1 scanning...
945 12:54:00.280171 scan_static_bus for USB3 port 1
946 12:54:00.283536 scan_static_bus for USB3 port 1 done
947 12:54:00.286918 scan_bus: bus USB3 port 1 finished in 6 msecs
948 12:54:00.289982 scan_static_bus for USB0 port 0 done
949 12:54:00.297002 scan_bus: bus USB0 port 0 finished in 43 msecs
950 12:54:00.300030 scan_static_bus for PCI: 00:0d.0 done
951 12:54:00.303495 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
952 12:54:00.306517 PCI: 00:14.0 scanning...
953 12:54:00.310512 scan_static_bus for PCI: 00:14.0
954 12:54:00.313734 USB0 port 0 enabled
955 12:54:00.317037 USB0 port 0 scanning...
956 12:54:00.320030 scan_static_bus for USB0 port 0
957 12:54:00.320470 USB2 port 0 disabled
958 12:54:00.323513 USB2 port 1 enabled
959 12:54:00.326641 USB2 port 2 enabled
960 12:54:00.327079 USB2 port 3 disabled
961 12:54:00.330019 USB2 port 4 enabled
962 12:54:00.330571 USB2 port 5 disabled
963 12:54:00.333480 USB2 port 6 disabled
964 12:54:00.336872 USB2 port 7 disabled
965 12:54:00.337421 USB2 port 8 disabled
966 12:54:00.340117 USB2 port 9 disabled
967 12:54:00.343113 USB3 port 0 disabled
968 12:54:00.343549 USB3 port 1 enabled
969 12:54:00.346992 USB3 port 2 disabled
970 12:54:00.350319 USB3 port 3 disabled
971 12:54:00.350875 USB2 port 1 scanning...
972 12:54:00.353092 scan_static_bus for USB2 port 1
973 12:54:00.356233 scan_static_bus for USB2 port 1 done
974 12:54:00.363003 scan_bus: bus USB2 port 1 finished in 6 msecs
975 12:54:00.366314 USB2 port 2 scanning...
976 12:54:00.369962 scan_static_bus for USB2 port 2
977 12:54:00.372956 scan_static_bus for USB2 port 2 done
978 12:54:00.376129 scan_bus: bus USB2 port 2 finished in 6 msecs
979 12:54:00.379246 USB2 port 4 scanning...
980 12:54:00.382969 scan_static_bus for USB2 port 4
981 12:54:00.386404 scan_static_bus for USB2 port 4 done
982 12:54:00.389669 scan_bus: bus USB2 port 4 finished in 6 msecs
983 12:54:00.392996 USB3 port 1 scanning...
984 12:54:00.396571 scan_static_bus for USB3 port 1
985 12:54:00.399938 scan_static_bus for USB3 port 1 done
986 12:54:00.406083 scan_bus: bus USB3 port 1 finished in 6 msecs
987 12:54:00.409227 scan_static_bus for USB0 port 0 done
988 12:54:00.412880 scan_bus: bus USB0 port 0 finished in 93 msecs
989 12:54:00.416135 scan_static_bus for PCI: 00:14.0 done
990 12:54:00.422419 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
991 12:54:00.425686 PCI: 00:14.3 scanning...
992 12:54:00.429036 scan_static_bus for PCI: 00:14.3
993 12:54:00.429481 GENERIC: 0.0 enabled
994 12:54:00.436527 scan_static_bus for PCI: 00:14.3 done
995 12:54:00.439461 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
996 12:54:00.442703 PCI: 00:15.0 scanning...
997 12:54:00.445762 scan_static_bus for PCI: 00:15.0
998 12:54:00.446291 I2C: 00:1a enabled
999 12:54:00.449264 I2C: 00:31 enabled
1000 12:54:00.452759 I2C: 00:32 enabled
1001 12:54:00.455465 scan_static_bus for PCI: 00:15.0 done
1002 12:54:00.459069 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1003 12:54:00.462028 PCI: 00:15.1 scanning...
1004 12:54:00.465608 scan_static_bus for PCI: 00:15.1
1005 12:54:00.469269 I2C: 00:10 enabled
1006 12:54:00.472847 scan_static_bus for PCI: 00:15.1 done
1007 12:54:00.475897 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1008 12:54:00.479310 PCI: 00:15.2 scanning...
1009 12:54:00.482810 scan_static_bus for PCI: 00:15.2
1010 12:54:00.486325 scan_static_bus for PCI: 00:15.2 done
1011 12:54:00.489979 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1012 12:54:00.493035 PCI: 00:15.3 scanning...
1013 12:54:00.495873 scan_static_bus for PCI: 00:15.3
1014 12:54:00.499545 scan_static_bus for PCI: 00:15.3 done
1015 12:54:00.505867 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1016 12:54:00.509630 PCI: 00:19.1 scanning...
1017 12:54:00.512472 scan_static_bus for PCI: 00:19.1
1018 12:54:00.513015 I2C: 00:15 enabled
1019 12:54:00.515952 scan_static_bus for PCI: 00:19.1 done
1020 12:54:00.522218 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1021 12:54:00.525861 PCI: 00:1d.0 scanning...
1022 12:54:00.529315 do_pci_scan_bridge for PCI: 00:1d.0
1023 12:54:00.532454 PCI: pci_scan_bus for bus 01
1024 12:54:00.535454 PCI: 01:00.0 [1c5c/174a] enabled
1025 12:54:00.536054 GENERIC: 0.0 enabled
1026 12:54:00.542082 Enabling Common Clock Configuration
1027 12:54:00.545033 L1 Sub-State supported from root port 29
1028 12:54:00.549216 L1 Sub-State Support = 0xf
1029 12:54:00.551920 CommonModeRestoreTime = 0x28
1030 12:54:00.555362 Power On Value = 0x16, Power On Scale = 0x0
1031 12:54:00.555866 ASPM: Enabled L1
1032 12:54:00.561905 PCIe: Max_Payload_Size adjusted to 128
1033 12:54:00.565312 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1034 12:54:00.568176 PCI: 00:1e.2 scanning...
1035 12:54:00.571688 scan_generic_bus for PCI: 00:1e.2
1036 12:54:00.572221 SPI: 00 enabled
1037 12:54:00.578614 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1038 12:54:00.584947 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1039 12:54:00.588106 PCI: 00:1e.3 scanning...
1040 12:54:00.591486 scan_generic_bus for PCI: 00:1e.3
1041 12:54:00.591964 SPI: 00 enabled
1042 12:54:00.598749 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1043 12:54:00.601809 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1044 12:54:00.605089 PCI: 00:1f.0 scanning...
1045 12:54:00.608215 scan_static_bus for PCI: 00:1f.0
1046 12:54:00.612013 PNP: 0c09.0 enabled
1047 12:54:00.615298 PNP: 0c09.0 scanning...
1048 12:54:00.618268 scan_static_bus for PNP: 0c09.0
1049 12:54:00.621571 scan_static_bus for PNP: 0c09.0 done
1050 12:54:00.625059 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1051 12:54:00.628225 scan_static_bus for PCI: 00:1f.0 done
1052 12:54:00.634737 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1053 12:54:00.638306 PCI: 00:1f.2 scanning...
1054 12:54:00.641641 scan_static_bus for PCI: 00:1f.2
1055 12:54:00.642180 GENERIC: 0.0 enabled
1056 12:54:00.644463 GENERIC: 0.0 scanning...
1057 12:54:00.647763 scan_static_bus for GENERIC: 0.0
1058 12:54:00.651232 GENERIC: 0.0 enabled
1059 12:54:00.651705 GENERIC: 1.0 enabled
1060 12:54:00.657866 scan_static_bus for GENERIC: 0.0 done
1061 12:54:00.661194 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1062 12:54:00.664630 scan_static_bus for PCI: 00:1f.2 done
1063 12:54:00.671015 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1064 12:54:00.671444 PCI: 00:1f.3 scanning...
1065 12:54:00.674498 scan_static_bus for PCI: 00:1f.3
1066 12:54:00.680856 scan_static_bus for PCI: 00:1f.3 done
1067 12:54:00.684228 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1068 12:54:00.687745 PCI: 00:1f.5 scanning...
1069 12:54:00.690598 scan_generic_bus for PCI: 00:1f.5
1070 12:54:00.694006 scan_generic_bus for PCI: 00:1f.5 done
1071 12:54:00.697583 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1072 12:54:00.704044 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1073 12:54:00.707413 scan_static_bus for Root Device done
1074 12:54:00.714070 scan_bus: bus Root Device finished in 736 msecs
1075 12:54:00.714596 done
1076 12:54:00.720610 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1077 12:54:00.724181 Chrome EC: UHEPI supported
1078 12:54:00.730764 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1079 12:54:00.737195 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1080 12:54:00.741189 SPI flash protection: WPSW=0 SRP0=0
1081 12:54:00.744153 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1082 12:54:00.750559 BS: BS_DEV_ENUMERATE exit times (exec / console): 3 / 23 ms
1083 12:54:00.753602 found VGA at PCI: 00:02.0
1084 12:54:00.756941 Setting up VGA for PCI: 00:02.0
1085 12:54:00.760397 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1086 12:54:00.767037 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1087 12:54:00.770329 Allocating resources...
1088 12:54:00.770863 Reading resources...
1089 12:54:00.777235 Root Device read_resources bus 0 link: 0
1090 12:54:00.780585 DOMAIN: 0000 read_resources bus 0 link: 0
1091 12:54:00.783465 PCI: 00:04.0 read_resources bus 1 link: 0
1092 12:54:00.790730 PCI: 00:04.0 read_resources bus 1 link: 0 done
1093 12:54:00.793863 PCI: 00:0d.0 read_resources bus 0 link: 0
1094 12:54:00.800713 USB0 port 0 read_resources bus 0 link: 0
1095 12:54:00.804117 USB0 port 0 read_resources bus 0 link: 0 done
1096 12:54:00.810356 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1097 12:54:00.813901 PCI: 00:14.0 read_resources bus 0 link: 0
1098 12:54:00.817139 USB0 port 0 read_resources bus 0 link: 0
1099 12:54:00.824686 USB0 port 0 read_resources bus 0 link: 0 done
1100 12:54:00.828101 PCI: 00:14.0 read_resources bus 0 link: 0 done
1101 12:54:00.835027 PCI: 00:14.3 read_resources bus 0 link: 0
1102 12:54:00.838273 PCI: 00:14.3 read_resources bus 0 link: 0 done
1103 12:54:00.845148 PCI: 00:15.0 read_resources bus 0 link: 0
1104 12:54:00.848177 PCI: 00:15.0 read_resources bus 0 link: 0 done
1105 12:54:00.854987 PCI: 00:15.1 read_resources bus 0 link: 0
1106 12:54:00.857964 PCI: 00:15.1 read_resources bus 0 link: 0 done
1107 12:54:00.866115 PCI: 00:19.1 read_resources bus 0 link: 0
1108 12:54:00.868592 PCI: 00:19.1 read_resources bus 0 link: 0 done
1109 12:54:00.875416 PCI: 00:1d.0 read_resources bus 1 link: 0
1110 12:54:00.878827 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1111 12:54:00.885749 PCI: 00:1e.2 read_resources bus 2 link: 0
1112 12:54:00.888577 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1113 12:54:00.895467 PCI: 00:1e.3 read_resources bus 3 link: 0
1114 12:54:00.899030 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1115 12:54:00.905557 PCI: 00:1f.0 read_resources bus 0 link: 0
1116 12:54:00.908341 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1117 12:54:00.915293 PCI: 00:1f.2 read_resources bus 0 link: 0
1118 12:54:00.918272 GENERIC: 0.0 read_resources bus 0 link: 0
1119 12:54:00.925024 GENERIC: 0.0 read_resources bus 0 link: 0 done
1120 12:54:00.928404 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1121 12:54:00.934990 DOMAIN: 0000 read_resources bus 0 link: 0 done
1122 12:54:00.938100 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1123 12:54:00.944685 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1124 12:54:00.948262 Root Device read_resources bus 0 link: 0 done
1125 12:54:00.951933 Done reading resources.
1126 12:54:00.958083 Show resources in subtree (Root Device)...After reading.
1127 12:54:00.961774 Root Device child on link 0 DOMAIN: 0000
1128 12:54:00.964735 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1129 12:54:00.974823 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1130 12:54:00.984640 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1131 12:54:00.985105 PCI: 00:00.0
1132 12:54:00.994803 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1133 12:54:01.004864 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1134 12:54:01.014691 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1135 12:54:01.024663 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1136 12:54:01.034301 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1137 12:54:01.044314 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1138 12:54:01.051455 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1139 12:54:01.060950 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1140 12:54:01.071091 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1141 12:54:01.080837 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1142 12:54:01.090872 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1143 12:54:01.097597 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1144 12:54:01.107218 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1145 12:54:01.117068 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1146 12:54:01.127274 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1147 12:54:01.137329 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1148 12:54:01.147244 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1149 12:54:01.157337 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1150 12:54:01.163799 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1151 12:54:01.173697 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1152 12:54:01.176886 PCI: 00:02.0
1153 12:54:01.187358 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 12:54:01.197437 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1155 12:54:01.207000 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1156 12:54:01.210340 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1157 12:54:01.220120 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1158 12:54:01.220633 GENERIC: 0.0
1159 12:54:01.223145 PCI: 00:05.0
1160 12:54:01.233370 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1161 12:54:01.236528 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1162 12:54:01.240027 GENERIC: 0.0
1163 12:54:01.240497 PCI: 00:08.0
1164 12:54:01.249807 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1165 12:54:01.253170 PCI: 00:0a.0
1166 12:54:01.256720 PCI: 00:0d.0 child on link 0 USB0 port 0
1167 12:54:01.266594 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 12:54:01.273147 USB0 port 0 child on link 0 USB3 port 0
1169 12:54:01.273677 USB3 port 0
1170 12:54:01.276403 USB3 port 1
1171 12:54:01.276836 USB3 port 2
1172 12:54:01.279787 USB3 port 3
1173 12:54:01.282745 PCI: 00:14.0 child on link 0 USB0 port 0
1174 12:54:01.292967 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1175 12:54:01.296219 USB0 port 0 child on link 0 USB2 port 0
1176 12:54:01.299950 USB2 port 0
1177 12:54:01.303011 USB2 port 1
1178 12:54:01.303534 USB2 port 2
1179 12:54:01.306554 USB2 port 3
1180 12:54:01.307081 USB2 port 4
1181 12:54:01.309320 USB2 port 5
1182 12:54:01.309752 USB2 port 6
1183 12:54:01.312784 USB2 port 7
1184 12:54:01.313217 USB2 port 8
1185 12:54:01.316194 USB2 port 9
1186 12:54:01.316628 USB3 port 0
1187 12:54:01.319792 USB3 port 1
1188 12:54:01.320323 USB3 port 2
1189 12:54:01.322806 USB3 port 3
1190 12:54:01.323234 PCI: 00:14.2
1191 12:54:01.332790 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1192 12:54:01.342795 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1193 12:54:01.349585 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1194 12:54:01.359028 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1195 12:54:01.359772 GENERIC: 0.0
1196 12:54:01.366147 PCI: 00:15.0 child on link 0 I2C: 00:1a
1197 12:54:01.376286 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1198 12:54:01.376894 I2C: 00:1a
1199 12:54:01.379279 I2C: 00:31
1200 12:54:01.379866 I2C: 00:32
1201 12:54:01.382390 PCI: 00:15.1 child on link 0 I2C: 00:10
1202 12:54:01.392325 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 12:54:01.395342 I2C: 00:10
1204 12:54:01.395818 PCI: 00:15.2
1205 12:54:01.405443 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 12:54:01.408890 PCI: 00:15.3
1207 12:54:01.418960 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1208 12:54:01.419509 PCI: 00:16.0
1209 12:54:01.429073 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1210 12:54:01.432387 PCI: 00:19.0
1211 12:54:01.435704 PCI: 00:19.1 child on link 0 I2C: 00:15
1212 12:54:01.445050 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1213 12:54:01.448871 I2C: 00:15
1214 12:54:01.452237 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1215 12:54:01.461883 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1216 12:54:01.472059 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1217 12:54:01.478919 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1218 12:54:01.481984 GENERIC: 0.0
1219 12:54:01.482513 PCI: 01:00.0
1220 12:54:01.491842 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1221 12:54:01.502040 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1222 12:54:01.511668 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1223 12:54:01.515201 PCI: 00:1e.0
1224 12:54:01.524997 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1225 12:54:01.528473 PCI: 00:1e.2 child on link 0 SPI: 00
1226 12:54:01.538150 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1227 12:54:01.538688 SPI: 00
1228 12:54:01.544956 PCI: 00:1e.3 child on link 0 SPI: 00
1229 12:54:01.554660 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 12:54:01.555195 SPI: 00
1231 12:54:01.557936 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1232 12:54:01.568335 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1233 12:54:01.571305 PNP: 0c09.0
1234 12:54:01.578014 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1235 12:54:01.584368 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1236 12:54:01.591140 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1237 12:54:01.601049 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1238 12:54:01.607775 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1239 12:54:01.608323 GENERIC: 0.0
1240 12:54:01.610853 GENERIC: 1.0
1241 12:54:01.611380 PCI: 00:1f.3
1242 12:54:01.621269 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1243 12:54:01.631407 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1244 12:54:01.634832 PCI: 00:1f.5
1245 12:54:01.640794 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1246 12:54:01.647724 CPU_CLUSTER: 0 child on link 0 APIC: 00
1247 12:54:01.648246 APIC: 00
1248 12:54:01.648596 APIC: 01
1249 12:54:01.651100 APIC: 03
1250 12:54:01.651663 APIC: 05
1251 12:54:01.654158 APIC: 07
1252 12:54:01.654583 APIC: 06
1253 12:54:01.654924 APIC: 02
1254 12:54:01.657704 APIC: 04
1255 12:54:01.664113 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1256 12:54:01.670935 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1257 12:54:01.677056 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1258 12:54:01.683714 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1259 12:54:01.687624 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1260 12:54:01.690734 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1261 12:54:01.693934 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1262 12:54:01.704183 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1263 12:54:01.710742 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1264 12:54:01.717352 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1265 12:54:01.723724 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1266 12:54:01.730616 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1267 12:54:01.737003 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1268 12:54:01.747235 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1269 12:54:01.754085 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1270 12:54:01.756945 DOMAIN: 0000: Resource ranges:
1271 12:54:01.760383 * Base: 1000, Size: 800, Tag: 100
1272 12:54:01.763683 * Base: 1900, Size: e700, Tag: 100
1273 12:54:01.770349 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1274 12:54:01.777125 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1275 12:54:01.784080 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1276 12:54:01.790412 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1277 12:54:01.796445 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1278 12:54:01.807197 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1279 12:54:01.813767 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1280 12:54:01.819723 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1281 12:54:01.830005 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1282 12:54:01.836045 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1283 12:54:01.842763 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1284 12:54:01.852974 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1285 12:54:01.859613 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1286 12:54:01.865864 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1287 12:54:01.876263 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1288 12:54:01.883139 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1289 12:54:01.889553 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1290 12:54:01.899459 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1291 12:54:01.905763 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1292 12:54:01.912531 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1293 12:54:01.922495 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1294 12:54:01.929080 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1295 12:54:01.935562 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1296 12:54:01.945447 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1297 12:54:01.951962 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1298 12:54:01.955743 DOMAIN: 0000: Resource ranges:
1299 12:54:01.958914 * Base: 7fc00000, Size: 40400000, Tag: 200
1300 12:54:01.965541 * Base: d0000000, Size: 28000000, Tag: 200
1301 12:54:01.968889 * Base: fa000000, Size: 1000000, Tag: 200
1302 12:54:01.972172 * Base: fb001000, Size: 2fff000, Tag: 200
1303 12:54:01.975848 * Base: fe010000, Size: 2e000, Tag: 200
1304 12:54:01.982122 * Base: fe03f000, Size: d41000, Tag: 200
1305 12:54:01.985293 * Base: fed88000, Size: 8000, Tag: 200
1306 12:54:01.988680 * Base: fed93000, Size: d000, Tag: 200
1307 12:54:01.992432 * Base: feda2000, Size: 1e000, Tag: 200
1308 12:54:01.998589 * Base: fede0000, Size: 1220000, Tag: 200
1309 12:54:02.001932 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1310 12:54:02.008891 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1311 12:54:02.015077 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1312 12:54:02.022128 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1313 12:54:02.028586 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1314 12:54:02.035133 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1315 12:54:02.042263 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1316 12:54:02.048223 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1317 12:54:02.055253 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1318 12:54:02.061540 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1319 12:54:02.068299 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1320 12:54:02.074930 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1321 12:54:02.081634 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1322 12:54:02.088395 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1323 12:54:02.094889 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1324 12:54:02.101323 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1325 12:54:02.108172 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1326 12:54:02.114610 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1327 12:54:02.121373 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1328 12:54:02.127948 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1329 12:54:02.134436 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1330 12:54:02.141744 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1331 12:54:02.147897 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1332 12:54:02.158334 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1333 12:54:02.164124 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1334 12:54:02.167501 PCI: 00:1d.0: Resource ranges:
1335 12:54:02.171533 * Base: 7fc00000, Size: 100000, Tag: 200
1336 12:54:02.177943 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1337 12:54:02.184413 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1338 12:54:02.191140 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1339 12:54:02.200897 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1340 12:54:02.207493 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1341 12:54:02.210518 Root Device assign_resources, bus 0 link: 0
1342 12:54:02.217414 DOMAIN: 0000 assign_resources, bus 0 link: 0
1343 12:54:02.224234 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1344 12:54:02.234225 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1345 12:54:02.240451 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1346 12:54:02.250660 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1347 12:54:02.253846 PCI: 00:04.0 assign_resources, bus 1 link: 0
1348 12:54:02.256841 PCI: 00:04.0 assign_resources, bus 1 link: 0
1349 12:54:02.266787 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1350 12:54:02.273574 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1351 12:54:02.283110 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1352 12:54:02.286538 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1353 12:54:02.292811 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1354 12:54:02.299398 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1355 12:54:02.306714 PCI: 00:14.0 assign_resources, bus 0 link: 0
1356 12:54:02.309487 PCI: 00:14.0 assign_resources, bus 0 link: 0
1357 12:54:02.316348 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1358 12:54:02.326277 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1359 12:54:02.332571 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1360 12:54:02.339365 PCI: 00:14.3 assign_resources, bus 0 link: 0
1361 12:54:02.342635 PCI: 00:14.3 assign_resources, bus 0 link: 0
1362 12:54:02.352454 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1363 12:54:02.355773 PCI: 00:15.0 assign_resources, bus 0 link: 0
1364 12:54:02.359360 PCI: 00:15.0 assign_resources, bus 0 link: 0
1365 12:54:02.369438 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1366 12:54:02.373204 PCI: 00:15.1 assign_resources, bus 0 link: 0
1367 12:54:02.379446 PCI: 00:15.1 assign_resources, bus 0 link: 0
1368 12:54:02.386314 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1369 12:54:02.396110 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1370 12:54:02.402915 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1371 12:54:02.412330 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1372 12:54:02.415666 PCI: 00:19.1 assign_resources, bus 0 link: 0
1373 12:54:02.418742 PCI: 00:19.1 assign_resources, bus 0 link: 0
1374 12:54:02.429248 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1375 12:54:02.439054 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1376 12:54:02.449467 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1377 12:54:02.452404 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1378 12:54:02.459061 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1379 12:54:02.468900 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1380 12:54:02.475760 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1381 12:54:02.482256 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1382 12:54:02.488595 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1383 12:54:02.495208 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1384 12:54:02.498768 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1385 12:54:02.504975 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1386 12:54:02.511736 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1387 12:54:02.515449 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1388 12:54:02.522297 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1389 12:54:02.525159 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1390 12:54:02.531851 LPC: Trying to open IO window from 800 size 1ff
1391 12:54:02.538392 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1392 12:54:02.548120 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1393 12:54:02.555009 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1394 12:54:02.558541 DOMAIN: 0000 assign_resources, bus 0 link: 0
1395 12:54:02.564715 Root Device assign_resources, bus 0 link: 0
1396 12:54:02.568472 Done setting resources.
1397 12:54:02.575132 Show resources in subtree (Root Device)...After assigning values.
1398 12:54:02.578560 Root Device child on link 0 DOMAIN: 0000
1399 12:54:02.581847 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1400 12:54:02.592003 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1401 12:54:02.601653 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1402 12:54:02.602205 PCI: 00:00.0
1403 12:54:02.611717 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1404 12:54:02.621666 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1405 12:54:02.631551 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1406 12:54:02.641179 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1407 12:54:02.651079 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1408 12:54:02.661249 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1409 12:54:02.667476 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1410 12:54:02.677824 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1411 12:54:02.687562 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1412 12:54:02.697428 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1413 12:54:02.707788 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1414 12:54:02.713962 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1415 12:54:02.723819 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1416 12:54:02.734191 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1417 12:54:02.744055 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1418 12:54:02.754012 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1419 12:54:02.764143 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1420 12:54:02.773798 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1421 12:54:02.779793 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1422 12:54:02.790359 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1423 12:54:02.793467 PCI: 00:02.0
1424 12:54:02.803271 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1425 12:54:02.813178 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1426 12:54:02.823317 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1427 12:54:02.826336 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1428 12:54:02.840098 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1429 12:54:02.840658 GENERIC: 0.0
1430 12:54:02.843371 PCI: 00:05.0
1431 12:54:02.853048 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1432 12:54:02.856492 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1433 12:54:02.859394 GENERIC: 0.0
1434 12:54:02.859949 PCI: 00:08.0
1435 12:54:02.869375 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1436 12:54:02.873132 PCI: 00:0a.0
1437 12:54:02.876379 PCI: 00:0d.0 child on link 0 USB0 port 0
1438 12:54:02.885656 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1439 12:54:02.892484 USB0 port 0 child on link 0 USB3 port 0
1440 12:54:02.893036 USB3 port 0
1441 12:54:02.895860 USB3 port 1
1442 12:54:02.896389 USB3 port 2
1443 12:54:02.899719 USB3 port 3
1444 12:54:02.902747 PCI: 00:14.0 child on link 0 USB0 port 0
1445 12:54:02.912588 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1446 12:54:02.919381 USB0 port 0 child on link 0 USB2 port 0
1447 12:54:02.920043 USB2 port 0
1448 12:54:02.922480 USB2 port 1
1449 12:54:02.922913 USB2 port 2
1450 12:54:02.925232 USB2 port 3
1451 12:54:02.925667 USB2 port 4
1452 12:54:02.929054 USB2 port 5
1453 12:54:02.929489 USB2 port 6
1454 12:54:02.932208 USB2 port 7
1455 12:54:02.932749 USB2 port 8
1456 12:54:02.935527 USB2 port 9
1457 12:54:02.939042 USB3 port 0
1458 12:54:02.939616 USB3 port 1
1459 12:54:02.942172 USB3 port 2
1460 12:54:02.942605 USB3 port 3
1461 12:54:02.945217 PCI: 00:14.2
1462 12:54:02.955344 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1463 12:54:02.965034 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1464 12:54:02.968462 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1465 12:54:02.978425 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1466 12:54:02.981601 GENERIC: 0.0
1467 12:54:02.984866 PCI: 00:15.0 child on link 0 I2C: 00:1a
1468 12:54:02.994696 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1469 12:54:02.998298 I2C: 00:1a
1470 12:54:02.998739 I2C: 00:31
1471 12:54:03.001928 I2C: 00:32
1472 12:54:03.005336 PCI: 00:15.1 child on link 0 I2C: 00:10
1473 12:54:03.015040 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1474 12:54:03.018061 I2C: 00:10
1475 12:54:03.018494 PCI: 00:15.2
1476 12:54:03.028176 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1477 12:54:03.031719 PCI: 00:15.3
1478 12:54:03.041407 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1479 12:54:03.041957 PCI: 00:16.0
1480 12:54:03.054356 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1481 12:54:03.054884 PCI: 00:19.0
1482 12:54:03.057597 PCI: 00:19.1 child on link 0 I2C: 00:15
1483 12:54:03.067652 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1484 12:54:03.071507 I2C: 00:15
1485 12:54:03.074490 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1486 12:54:03.084027 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1487 12:54:03.097203 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1488 12:54:03.107730 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1489 12:54:03.108264 GENERIC: 0.0
1490 12:54:03.110790 PCI: 01:00.0
1491 12:54:03.120418 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1492 12:54:03.130418 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1493 12:54:03.140730 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1494 12:54:03.143955 PCI: 00:1e.0
1495 12:54:03.153316 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1496 12:54:03.156777 PCI: 00:1e.2 child on link 0 SPI: 00
1497 12:54:03.170213 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1498 12:54:03.171039 SPI: 00
1499 12:54:03.173488 PCI: 00:1e.3 child on link 0 SPI: 00
1500 12:54:03.183167 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1501 12:54:03.186534 SPI: 00
1502 12:54:03.189725 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1503 12:54:03.199927 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1504 12:54:03.200241 PNP: 0c09.0
1505 12:54:03.209489 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1506 12:54:03.212488 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1507 12:54:03.222688 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1508 12:54:03.232322 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1509 12:54:03.235680 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1510 12:54:03.239488 GENERIC: 0.0
1511 12:54:03.239576 GENERIC: 1.0
1512 12:54:03.242252 PCI: 00:1f.3
1513 12:54:03.252451 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1514 12:54:03.262294 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1515 12:54:03.265476 PCI: 00:1f.5
1516 12:54:03.275367 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1517 12:54:03.278845 CPU_CLUSTER: 0 child on link 0 APIC: 00
1518 12:54:03.278941 APIC: 00
1519 12:54:03.282184 APIC: 01
1520 12:54:03.282269 APIC: 03
1521 12:54:03.285507 APIC: 05
1522 12:54:03.285614 APIC: 07
1523 12:54:03.285684 APIC: 06
1524 12:54:03.288691 APIC: 02
1525 12:54:03.288790 APIC: 04
1526 12:54:03.291887 Done allocating resources.
1527 12:54:03.298745 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1528 12:54:03.305227 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1529 12:54:03.308324 Configure GPIOs for I2S audio on UP4.
1530 12:54:03.315101 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1531 12:54:03.318110 Enabling resources...
1532 12:54:03.321705 PCI: 00:00.0 subsystem <- 8086/9a12
1533 12:54:03.321816 PCI: 00:00.0 cmd <- 06
1534 12:54:03.328746 PCI: 00:02.0 subsystem <- 8086/9a40
1535 12:54:03.328886 PCI: 00:02.0 cmd <- 03
1536 12:54:03.331917 PCI: 00:04.0 subsystem <- 8086/9a03
1537 12:54:03.335207 PCI: 00:04.0 cmd <- 02
1538 12:54:03.338461 PCI: 00:05.0 subsystem <- 8086/9a19
1539 12:54:03.341647 PCI: 00:05.0 cmd <- 02
1540 12:54:03.345082 PCI: 00:08.0 subsystem <- 8086/9a11
1541 12:54:03.348363 PCI: 00:08.0 cmd <- 06
1542 12:54:03.351584 PCI: 00:0d.0 subsystem <- 8086/9a13
1543 12:54:03.354766 PCI: 00:0d.0 cmd <- 02
1544 12:54:03.358439 PCI: 00:14.0 subsystem <- 8086/a0ed
1545 12:54:03.361629 PCI: 00:14.0 cmd <- 02
1546 12:54:03.364996 PCI: 00:14.2 subsystem <- 8086/a0ef
1547 12:54:03.368177 PCI: 00:14.2 cmd <- 02
1548 12:54:03.371735 PCI: 00:14.3 subsystem <- 8086/a0f0
1549 12:54:03.371865 PCI: 00:14.3 cmd <- 02
1550 12:54:03.378094 PCI: 00:15.0 subsystem <- 8086/a0e8
1551 12:54:03.378237 PCI: 00:15.0 cmd <- 02
1552 12:54:03.381384 PCI: 00:15.1 subsystem <- 8086/a0e9
1553 12:54:03.384697 PCI: 00:15.1 cmd <- 02
1554 12:54:03.388042 PCI: 00:15.2 subsystem <- 8086/a0ea
1555 12:54:03.391293 PCI: 00:15.2 cmd <- 02
1556 12:54:03.394519 PCI: 00:15.3 subsystem <- 8086/a0eb
1557 12:54:03.398041 PCI: 00:15.3 cmd <- 02
1558 12:54:03.401221 PCI: 00:16.0 subsystem <- 8086/a0e0
1559 12:54:03.404413 PCI: 00:16.0 cmd <- 02
1560 12:54:03.407552 PCI: 00:19.1 subsystem <- 8086/a0c6
1561 12:54:03.410758 PCI: 00:19.1 cmd <- 02
1562 12:54:03.414381 PCI: 00:1d.0 bridge ctrl <- 0013
1563 12:54:03.417521 PCI: 00:1d.0 subsystem <- 8086/a0b0
1564 12:54:03.420827 PCI: 00:1d.0 cmd <- 06
1565 12:54:03.424177 PCI: 00:1e.0 subsystem <- 8086/a0a8
1566 12:54:03.427300 PCI: 00:1e.0 cmd <- 06
1567 12:54:03.430946 PCI: 00:1e.2 subsystem <- 8086/a0aa
1568 12:54:03.431081 PCI: 00:1e.2 cmd <- 06
1569 12:54:03.437442 PCI: 00:1e.3 subsystem <- 8086/a0ab
1570 12:54:03.437582 PCI: 00:1e.3 cmd <- 02
1571 12:54:03.440541 PCI: 00:1f.0 subsystem <- 8086/a087
1572 12:54:03.443787 PCI: 00:1f.0 cmd <- 407
1573 12:54:03.447101 PCI: 00:1f.3 subsystem <- 8086/a0c8
1574 12:54:03.450353 PCI: 00:1f.3 cmd <- 02
1575 12:54:03.454077 PCI: 00:1f.5 subsystem <- 8086/a0a4
1576 12:54:03.457355 PCI: 00:1f.5 cmd <- 406
1577 12:54:03.461467 PCI: 01:00.0 cmd <- 02
1578 12:54:03.466214 done.
1579 12:54:03.469480 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1580 12:54:03.472764 Initializing devices...
1581 12:54:03.475946 Root Device init
1582 12:54:03.479337 Chrome EC: Set SMI mask to 0x0000000000000000
1583 12:54:03.485972 Chrome EC: clear events_b mask to 0x0000000000000000
1584 12:54:03.492097 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1585 12:54:03.498920 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1586 12:54:03.505995 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1587 12:54:03.508756 Chrome EC: Set WAKE mask to 0x0000000000000000
1588 12:54:03.516411 fw_config match found: DB_USB=USB3_ACTIVE
1589 12:54:03.519545 Configure Right Type-C port orientation for retimer
1590 12:54:03.522681 Root Device init finished in 45 msecs
1591 12:54:03.526926 PCI: 00:00.0 init
1592 12:54:03.530373 CPU TDP = 9 Watts
1593 12:54:03.530470 CPU PL1 = 9 Watts
1594 12:54:03.533472 CPU PL2 = 40 Watts
1595 12:54:03.537339 CPU PL4 = 83 Watts
1596 12:54:03.540230 PCI: 00:00.0 init finished in 8 msecs
1597 12:54:03.543745 PCI: 00:02.0 init
1598 12:54:03.543830 GMA: Found VBT in CBFS
1599 12:54:03.546965 GMA: Found valid VBT in CBFS
1600 12:54:03.553546 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1601 12:54:03.560175 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1602 12:54:03.563408 PCI: 00:02.0 init finished in 18 msecs
1603 12:54:03.566703 PCI: 00:05.0 init
1604 12:54:03.570156 PCI: 00:05.0 init finished in 0 msecs
1605 12:54:03.573584 PCI: 00:08.0 init
1606 12:54:03.576773 PCI: 00:08.0 init finished in 0 msecs
1607 12:54:03.580029 PCI: 00:14.0 init
1608 12:54:03.583193 PCI: 00:14.0 init finished in 0 msecs
1609 12:54:03.586631 PCI: 00:14.2 init
1610 12:54:03.589847 PCI: 00:14.2 init finished in 0 msecs
1611 12:54:03.593084 PCI: 00:15.0 init
1612 12:54:03.596440 I2C bus 0 version 0x3230302a
1613 12:54:03.599787 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1614 12:54:03.603102 PCI: 00:15.0 init finished in 6 msecs
1615 12:54:03.606352 PCI: 00:15.1 init
1616 12:54:03.606438 I2C bus 1 version 0x3230302a
1617 12:54:03.612680 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1618 12:54:03.616112 PCI: 00:15.1 init finished in 6 msecs
1619 12:54:03.616199 PCI: 00:15.2 init
1620 12:54:03.619404 I2C bus 2 version 0x3230302a
1621 12:54:03.622664 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1622 12:54:03.629247 PCI: 00:15.2 init finished in 6 msecs
1623 12:54:03.629362 PCI: 00:15.3 init
1624 12:54:03.632843 I2C bus 3 version 0x3230302a
1625 12:54:03.636162 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1626 12:54:03.639392 PCI: 00:15.3 init finished in 6 msecs
1627 12:54:03.642627 PCI: 00:16.0 init
1628 12:54:03.645596 PCI: 00:16.0 init finished in 0 msecs
1629 12:54:03.649152 PCI: 00:19.1 init
1630 12:54:03.652264 I2C bus 5 version 0x3230302a
1631 12:54:03.655570 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1632 12:54:03.659326 PCI: 00:19.1 init finished in 6 msecs
1633 12:54:03.662550 PCI: 00:1d.0 init
1634 12:54:03.665959 Initializing PCH PCIe bridge.
1635 12:54:03.669168 PCI: 00:1d.0 init finished in 3 msecs
1636 12:54:03.672177 PCI: 00:1f.0 init
1637 12:54:03.675361 IOAPIC: Initializing IOAPIC at 0xfec00000
1638 12:54:03.678713 IOAPIC: Bootstrap Processor Local APIC = 0x00
1639 12:54:03.682346 IOAPIC: ID = 0x02
1640 12:54:03.685686 IOAPIC: Dumping registers
1641 12:54:03.688909 reg 0x0000: 0x02000000
1642 12:54:03.689007 reg 0x0001: 0x00770020
1643 12:54:03.692197 reg 0x0002: 0x00000000
1644 12:54:03.695507 PCI: 00:1f.0 init finished in 21 msecs
1645 12:54:03.698916 PCI: 00:1f.2 init
1646 12:54:03.702171 Disabling ACPI via APMC.
1647 12:54:03.705494 APMC done.
1648 12:54:03.708735 PCI: 00:1f.2 init finished in 5 msecs
1649 12:54:03.719496 PCI: 01:00.0 init
1650 12:54:03.722601 PCI: 01:00.0 init finished in 0 msecs
1651 12:54:03.726430 PNP: 0c09.0 init
1652 12:54:03.729684 Google Chrome EC uptime: 8.400 seconds
1653 12:54:03.736104 Google Chrome AP resets since EC boot: 1
1654 12:54:03.739708 Google Chrome most recent AP reset causes:
1655 12:54:03.742983 0.348: 32775 shutdown: entering G3
1656 12:54:03.749323 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1657 12:54:03.752806 PNP: 0c09.0 init finished in 22 msecs
1658 12:54:03.758379 Devices initialized
1659 12:54:03.761579 Show all devs... After init.
1660 12:54:03.764944 Root Device: enabled 1
1661 12:54:03.765031 DOMAIN: 0000: enabled 1
1662 12:54:03.768189 CPU_CLUSTER: 0: enabled 1
1663 12:54:03.771389 PCI: 00:00.0: enabled 1
1664 12:54:03.775166 PCI: 00:02.0: enabled 1
1665 12:54:03.775251 PCI: 00:04.0: enabled 1
1666 12:54:03.778242 PCI: 00:05.0: enabled 1
1667 12:54:03.781567 PCI: 00:06.0: enabled 0
1668 12:54:03.784894 PCI: 00:07.0: enabled 0
1669 12:54:03.784986 PCI: 00:07.1: enabled 0
1670 12:54:03.788344 PCI: 00:07.2: enabled 0
1671 12:54:03.791523 PCI: 00:07.3: enabled 0
1672 12:54:03.795331 PCI: 00:08.0: enabled 1
1673 12:54:03.795490 PCI: 00:09.0: enabled 0
1674 12:54:03.798595 PCI: 00:0a.0: enabled 0
1675 12:54:03.801979 PCI: 00:0d.0: enabled 1
1676 12:54:03.804747 PCI: 00:0d.1: enabled 0
1677 12:54:03.804843 PCI: 00:0d.2: enabled 0
1678 12:54:03.808498 PCI: 00:0d.3: enabled 0
1679 12:54:03.811611 PCI: 00:0e.0: enabled 0
1680 12:54:03.815264 PCI: 00:10.2: enabled 1
1681 12:54:03.815426 PCI: 00:10.6: enabled 0
1682 12:54:03.818313 PCI: 00:10.7: enabled 0
1683 12:54:03.821776 PCI: 00:12.0: enabled 0
1684 12:54:03.821937 PCI: 00:12.6: enabled 0
1685 12:54:03.824862 PCI: 00:13.0: enabled 0
1686 12:54:03.828343 PCI: 00:14.0: enabled 1
1687 12:54:03.831388 PCI: 00:14.1: enabled 0
1688 12:54:03.831557 PCI: 00:14.2: enabled 1
1689 12:54:03.834822 PCI: 00:14.3: enabled 1
1690 12:54:03.837882 PCI: 00:15.0: enabled 1
1691 12:54:03.841530 PCI: 00:15.1: enabled 1
1692 12:54:03.841713 PCI: 00:15.2: enabled 1
1693 12:54:03.844975 PCI: 00:15.3: enabled 1
1694 12:54:03.847694 PCI: 00:16.0: enabled 1
1695 12:54:03.852028 PCI: 00:16.1: enabled 0
1696 12:54:03.852485 PCI: 00:16.2: enabled 0
1697 12:54:03.854824 PCI: 00:16.3: enabled 0
1698 12:54:03.858167 PCI: 00:16.4: enabled 0
1699 12:54:03.861561 PCI: 00:16.5: enabled 0
1700 12:54:03.862091 PCI: 00:17.0: enabled 0
1701 12:54:03.864827 PCI: 00:19.0: enabled 0
1702 12:54:03.868579 PCI: 00:19.1: enabled 1
1703 12:54:03.869034 PCI: 00:19.2: enabled 0
1704 12:54:03.871768 PCI: 00:1c.0: enabled 1
1705 12:54:03.874484 PCI: 00:1c.1: enabled 0
1706 12:54:03.877922 PCI: 00:1c.2: enabled 0
1707 12:54:03.878503 PCI: 00:1c.3: enabled 0
1708 12:54:03.881971 PCI: 00:1c.4: enabled 0
1709 12:54:03.884660 PCI: 00:1c.5: enabled 0
1710 12:54:03.888052 PCI: 00:1c.6: enabled 1
1711 12:54:03.888481 PCI: 00:1c.7: enabled 0
1712 12:54:03.891491 PCI: 00:1d.0: enabled 1
1713 12:54:03.895142 PCI: 00:1d.1: enabled 0
1714 12:54:03.898372 PCI: 00:1d.2: enabled 1
1715 12:54:03.898905 PCI: 00:1d.3: enabled 0
1716 12:54:03.901542 PCI: 00:1e.0: enabled 1
1717 12:54:03.904645 PCI: 00:1e.1: enabled 0
1718 12:54:03.905075 PCI: 00:1e.2: enabled 1
1719 12:54:03.907918 PCI: 00:1e.3: enabled 1
1720 12:54:03.911154 PCI: 00:1f.0: enabled 1
1721 12:54:03.914510 PCI: 00:1f.1: enabled 0
1722 12:54:03.915048 PCI: 00:1f.2: enabled 1
1723 12:54:03.917738 PCI: 00:1f.3: enabled 1
1724 12:54:03.921315 PCI: 00:1f.4: enabled 0
1725 12:54:03.924978 PCI: 00:1f.5: enabled 1
1726 12:54:03.925513 PCI: 00:1f.6: enabled 0
1727 12:54:03.928128 PCI: 00:1f.7: enabled 0
1728 12:54:03.931437 APIC: 00: enabled 1
1729 12:54:03.932024 GENERIC: 0.0: enabled 1
1730 12:54:03.934741 GENERIC: 0.0: enabled 1
1731 12:54:03.937920 GENERIC: 1.0: enabled 1
1732 12:54:03.941600 GENERIC: 0.0: enabled 1
1733 12:54:03.942039 GENERIC: 1.0: enabled 1
1734 12:54:03.944949 USB0 port 0: enabled 1
1735 12:54:03.948191 GENERIC: 0.0: enabled 1
1736 12:54:03.951262 USB0 port 0: enabled 1
1737 12:54:03.951825 GENERIC: 0.0: enabled 1
1738 12:54:03.954890 I2C: 00:1a: enabled 1
1739 12:54:03.957842 I2C: 00:31: enabled 1
1740 12:54:03.958382 I2C: 00:32: enabled 1
1741 12:54:03.960946 I2C: 00:10: enabled 1
1742 12:54:03.964411 I2C: 00:15: enabled 1
1743 12:54:03.964957 GENERIC: 0.0: enabled 0
1744 12:54:03.968119 GENERIC: 1.0: enabled 0
1745 12:54:03.971024 GENERIC: 0.0: enabled 1
1746 12:54:03.971459 SPI: 00: enabled 1
1747 12:54:03.974589 SPI: 00: enabled 1
1748 12:54:03.977536 PNP: 0c09.0: enabled 1
1749 12:54:03.977971 GENERIC: 0.0: enabled 1
1750 12:54:03.981387 USB3 port 0: enabled 1
1751 12:54:03.984654 USB3 port 1: enabled 1
1752 12:54:03.987620 USB3 port 2: enabled 0
1753 12:54:03.988078 USB3 port 3: enabled 0
1754 12:54:03.991149 USB2 port 0: enabled 0
1755 12:54:03.994874 USB2 port 1: enabled 1
1756 12:54:03.995423 USB2 port 2: enabled 1
1757 12:54:03.997871 USB2 port 3: enabled 0
1758 12:54:04.001323 USB2 port 4: enabled 1
1759 12:54:04.004520 USB2 port 5: enabled 0
1760 12:54:04.004956 USB2 port 6: enabled 0
1761 12:54:04.007989 USB2 port 7: enabled 0
1762 12:54:04.011350 USB2 port 8: enabled 0
1763 12:54:04.011991 USB2 port 9: enabled 0
1764 12:54:04.014448 USB3 port 0: enabled 0
1765 12:54:04.017848 USB3 port 1: enabled 1
1766 12:54:04.018491 USB3 port 2: enabled 0
1767 12:54:04.021196 USB3 port 3: enabled 0
1768 12:54:04.024521 GENERIC: 0.0: enabled 1
1769 12:54:04.027918 GENERIC: 1.0: enabled 1
1770 12:54:04.028451 APIC: 01: enabled 1
1771 12:54:04.031072 APIC: 03: enabled 1
1772 12:54:04.034778 APIC: 05: enabled 1
1773 12:54:04.035305 APIC: 07: enabled 1
1774 12:54:04.037978 APIC: 06: enabled 1
1775 12:54:04.038530 APIC: 02: enabled 1
1776 12:54:04.040630 APIC: 04: enabled 1
1777 12:54:04.044482 PCI: 01:00.0: enabled 1
1778 12:54:04.047861 BS: BS_DEV_INIT run times (exec / console): 32 / 540 ms
1779 12:54:04.054676 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1780 12:54:04.057426 ELOG: NV offset 0xf30000 size 0x1000
1781 12:54:04.064050 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1782 12:54:04.070247 ELOG: Event(17) added with size 13 at 2023-04-05 12:54:04 UTC
1783 12:54:04.077479 ELOG: Event(92) added with size 9 at 2023-04-05 12:54:04 UTC
1784 12:54:04.083933 ELOG: Event(93) added with size 9 at 2023-04-05 12:54:04 UTC
1785 12:54:04.090676 ELOG: Event(9E) added with size 10 at 2023-04-05 12:54:04 UTC
1786 12:54:04.097288 ELOG: Event(9F) added with size 14 at 2023-04-05 12:54:04 UTC
1787 12:54:04.103920 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1788 12:54:04.107306 ELOG: Event(A1) added with size 10 at 2023-04-05 12:54:04 UTC
1789 12:54:04.114057 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1790 12:54:04.120549 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1791 12:54:04.124210 Finalize devices...
1792 12:54:04.124750 Devices finalized
1793 12:54:04.130682 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1794 12:54:04.137509 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1795 12:54:04.140993 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1796 12:54:04.147452 ME: HFSTS1 : 0x80030055
1797 12:54:04.150835 ME: HFSTS2 : 0x30280116
1798 12:54:04.153798 ME: HFSTS3 : 0x00000050
1799 12:54:04.160386 ME: HFSTS4 : 0x00004000
1800 12:54:04.163369 ME: HFSTS5 : 0x00000000
1801 12:54:04.167408 ME: HFSTS6 : 0x00400006
1802 12:54:04.173666 ME: Manufacturing Mode : YES
1803 12:54:04.177346 ME: SPI Protection Mode Enabled : NO
1804 12:54:04.180103 ME: FW Partition Table : OK
1805 12:54:04.183552 ME: Bringup Loader Failure : NO
1806 12:54:04.187137 ME: Firmware Init Complete : NO
1807 12:54:04.190468 ME: Boot Options Present : NO
1808 12:54:04.193327 ME: Update In Progress : NO
1809 12:54:04.196641 ME: D0i3 Support : YES
1810 12:54:04.203533 ME: Low Power State Enabled : NO
1811 12:54:04.207322 ME: CPU Replaced : YES
1812 12:54:04.210302 ME: CPU Replacement Valid : YES
1813 12:54:04.213214 ME: Current Working State : 5
1814 12:54:04.216734 ME: Current Operation State : 1
1815 12:54:04.220204 ME: Current Operation Mode : 3
1816 12:54:04.223543 ME: Error Code : 0
1817 12:54:04.226926 ME: Enhanced Debug Mode : NO
1818 12:54:04.230213 ME: CPU Debug Disabled : YES
1819 12:54:04.236725 ME: TXT Support : NO
1820 12:54:04.240015 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1821 12:54:04.249979 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1822 12:54:04.253281 CBFS: 'fallback/slic' not found.
1823 12:54:04.256214 ACPI: Writing ACPI tables at 76b01000.
1824 12:54:04.256654 ACPI: * FACS
1825 12:54:04.259730 ACPI: * DSDT
1826 12:54:04.262929 Ramoops buffer: 0x100000@0x76a00000.
1827 12:54:04.270148 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1828 12:54:04.273054 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1829 12:54:04.276231 Google Chrome EC: version:
1830 12:54:04.279206 ro: voema_v2.0.7540-147f8d37d1
1831 12:54:04.283037 rw: voema_v2.0.7540-147f8d37d1
1832 12:54:04.286266 running image: 2
1833 12:54:04.289371 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1834 12:54:04.294695 ACPI: * FADT
1835 12:54:04.295123 SCI is IRQ9
1836 12:54:04.301744 ACPI: added table 1/32, length now 40
1837 12:54:04.302169 ACPI: * SSDT
1838 12:54:04.305134 Found 1 CPU(s) with 8 core(s) each.
1839 12:54:04.311168 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1840 12:54:04.314799 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1841 12:54:04.317948 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1842 12:54:04.321094 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1843 12:54:04.327712 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1844 12:54:04.334367 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1845 12:54:04.337636 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1846 12:54:04.344259 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1847 12:54:04.351196 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1848 12:54:04.354534 \_SB.PCI0.RP09: Added StorageD3Enable property
1849 12:54:04.360641 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1850 12:54:04.364294 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1851 12:54:04.370856 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1852 12:54:04.373791 PS2K: Passing 80 keymaps to kernel
1853 12:54:04.380854 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1854 12:54:04.387638 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1855 12:54:04.394162 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1856 12:54:04.400796 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1857 12:54:04.407360 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1858 12:54:04.413677 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1859 12:54:04.420605 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1860 12:54:04.426806 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1861 12:54:04.430710 ACPI: added table 2/32, length now 44
1862 12:54:04.430836 ACPI: * MCFG
1863 12:54:04.433522 ACPI: added table 3/32, length now 48
1864 12:54:04.436894 ACPI: * TPM2
1865 12:54:04.440142 TPM2 log created at 0x769f0000
1866 12:54:04.443426 ACPI: added table 4/32, length now 52
1867 12:54:04.443538 ACPI: * MADT
1868 12:54:04.446823 SCI is IRQ9
1869 12:54:04.450452 ACPI: added table 5/32, length now 56
1870 12:54:04.453594 current = 76b09850
1871 12:54:04.453709 ACPI: * DMAR
1872 12:54:04.456977 ACPI: added table 6/32, length now 60
1873 12:54:04.460286 ACPI: added table 7/32, length now 64
1874 12:54:04.463484 ACPI: * HPET
1875 12:54:04.466851 ACPI: added table 8/32, length now 68
1876 12:54:04.466974 ACPI: done.
1877 12:54:04.470192 ACPI tables: 35216 bytes.
1878 12:54:04.473411 smbios_write_tables: 769ef000
1879 12:54:04.476699 EC returned error result code 3
1880 12:54:04.480295 Couldn't obtain OEM name from CBI
1881 12:54:04.483510 Create SMBIOS type 16
1882 12:54:04.486692 Create SMBIOS type 17
1883 12:54:04.489854 GENERIC: 0.0 (WIFI Device)
1884 12:54:04.489957 SMBIOS tables: 1750 bytes.
1885 12:54:04.496902 Writing table forward entry at 0x00000500
1886 12:54:04.503372 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1887 12:54:04.506368 Writing coreboot table at 0x76b25000
1888 12:54:04.509828 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1889 12:54:04.516633 1. 0000000000001000-000000000009ffff: RAM
1890 12:54:04.520050 2. 00000000000a0000-00000000000fffff: RESERVED
1891 12:54:04.523200 3. 0000000000100000-00000000769eefff: RAM
1892 12:54:04.529959 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1893 12:54:04.536283 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1894 12:54:04.539590 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1895 12:54:04.546202 7. 0000000077000000-000000007fbfffff: RESERVED
1896 12:54:04.550003 8. 00000000c0000000-00000000cfffffff: RESERVED
1897 12:54:04.556389 9. 00000000f8000000-00000000f9ffffff: RESERVED
1898 12:54:04.559715 10. 00000000fb000000-00000000fb000fff: RESERVED
1899 12:54:04.566235 11. 00000000fe000000-00000000fe00ffff: RESERVED
1900 12:54:04.569541 12. 00000000fed80000-00000000fed87fff: RESERVED
1901 12:54:04.576198 13. 00000000fed90000-00000000fed92fff: RESERVED
1902 12:54:04.579876 14. 00000000feda0000-00000000feda1fff: RESERVED
1903 12:54:04.583058 15. 00000000fedc0000-00000000feddffff: RESERVED
1904 12:54:04.589795 16. 0000000100000000-00000002803fffff: RAM
1905 12:54:04.592844 Passing 4 GPIOs to payload:
1906 12:54:04.596582 NAME | PORT | POLARITY | VALUE
1907 12:54:04.603056 lid | undefined | high | high
1908 12:54:04.606294 power | undefined | high | low
1909 12:54:04.613009 oprom | undefined | high | low
1910 12:54:04.619379 EC in RW | 0x000000e5 | high | high
1911 12:54:04.622699 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 2900
1912 12:54:04.625993 coreboot table: 1576 bytes.
1913 12:54:04.629331 IMD ROOT 0. 0x76fff000 0x00001000
1914 12:54:04.636143 IMD SMALL 1. 0x76ffe000 0x00001000
1915 12:54:04.639173 FSP MEMORY 2. 0x76c4e000 0x003b0000
1916 12:54:04.642423 VPD 3. 0x76c4d000 0x00000367
1917 12:54:04.646249 RO MCACHE 4. 0x76c4c000 0x00000fdc
1918 12:54:04.649539 CONSOLE 5. 0x76c2c000 0x00020000
1919 12:54:04.652891 FMAP 6. 0x76c2b000 0x00000578
1920 12:54:04.655625 TIME STAMP 7. 0x76c2a000 0x00000910
1921 12:54:04.659191 VBOOT WORK 8. 0x76c16000 0x00014000
1922 12:54:04.666182 ROMSTG STCK 9. 0x76c15000 0x00001000
1923 12:54:04.669596 AFTER CAR 10. 0x76c0a000 0x0000b000
1924 12:54:04.672633 RAMSTAGE 11. 0x76b97000 0x00073000
1925 12:54:04.676053 REFCODE 12. 0x76b42000 0x00055000
1926 12:54:04.679222 SMM BACKUP 13. 0x76b32000 0x00010000
1927 12:54:04.682508 4f444749 14. 0x76b30000 0x00002000
1928 12:54:04.685896 EXT VBT15. 0x76b2d000 0x0000219f
1929 12:54:04.689112 COREBOOT 16. 0x76b25000 0x00008000
1930 12:54:04.692300 ACPI 17. 0x76b01000 0x00024000
1931 12:54:04.699135 ACPI GNVS 18. 0x76b00000 0x00001000
1932 12:54:04.702185 RAMOOPS 19. 0x76a00000 0x00100000
1933 12:54:04.705878 TPM2 TCGLOG20. 0x769f0000 0x00010000
1934 12:54:04.709158 SMBIOS 21. 0x769ef000 0x00000800
1935 12:54:04.709246 IMD small region:
1936 12:54:04.716108 IMD ROOT 0. 0x76ffec00 0x00000400
1937 12:54:04.719282 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1938 12:54:04.722155 POWER STATE 2. 0x76ffeb80 0x00000044
1939 12:54:04.725889 ROMSTAGE 3. 0x76ffeb60 0x00000004
1940 12:54:04.728748 MEM INFO 4. 0x76ffe980 0x000001e0
1941 12:54:04.735409 BS: BS_WRITE_TABLES run times (exec / console): 5 / 484 ms
1942 12:54:04.739010 MTRR: Physical address space:
1943 12:54:04.745578 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1944 12:54:04.752009 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1945 12:54:04.758572 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1946 12:54:04.765274 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1947 12:54:04.768481 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1948 12:54:04.775060 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1949 12:54:04.782275 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1950 12:54:04.788650 MTRR: Fixed MSR 0x250 0x0606060606060606
1951 12:54:04.791973 MTRR: Fixed MSR 0x258 0x0606060606060606
1952 12:54:04.795344 MTRR: Fixed MSR 0x259 0x0000000000000000
1953 12:54:04.798467 MTRR: Fixed MSR 0x268 0x0606060606060606
1954 12:54:04.801844 MTRR: Fixed MSR 0x269 0x0606060606060606
1955 12:54:04.808624 MTRR: Fixed MSR 0x26a 0x0606060606060606
1956 12:54:04.811543 MTRR: Fixed MSR 0x26b 0x0606060606060606
1957 12:54:04.815029 MTRR: Fixed MSR 0x26c 0x0606060606060606
1958 12:54:04.818747 MTRR: Fixed MSR 0x26d 0x0606060606060606
1959 12:54:04.825187 MTRR: Fixed MSR 0x26e 0x0606060606060606
1960 12:54:04.828280 MTRR: Fixed MSR 0x26f 0x0606060606060606
1961 12:54:04.831860 call enable_fixed_mtrr()
1962 12:54:04.835149 CPU physical address size: 39 bits
1963 12:54:04.838505 MTRR: default type WB/UC MTRR counts: 6/6.
1964 12:54:04.841755 MTRR: UC selected as default type.
1965 12:54:04.848117 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1966 12:54:04.855052 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1967 12:54:04.861767 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1968 12:54:04.868071 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1969 12:54:04.875169 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1970 12:54:04.881611 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1971 12:54:04.881706
1972 12:54:04.885119 MTRR check
1973 12:54:04.885203 Fixed MTRRs : Enabled
1974 12:54:04.887972 Variable MTRRs: Enabled
1975 12:54:04.888075
1976 12:54:04.891337 MTRR: Fixed MSR 0x250 0x0606060606060606
1977 12:54:04.897944 MTRR: Fixed MSR 0x258 0x0606060606060606
1978 12:54:04.901207 MTRR: Fixed MSR 0x259 0x0000000000000000
1979 12:54:04.904540 MTRR: Fixed MSR 0x268 0x0606060606060606
1980 12:54:04.907784 MTRR: Fixed MSR 0x269 0x0606060606060606
1981 12:54:04.914404 MTRR: Fixed MSR 0x26a 0x0606060606060606
1982 12:54:04.918150 MTRR: Fixed MSR 0x26b 0x0606060606060606
1983 12:54:04.921410 MTRR: Fixed MSR 0x26c 0x0606060606060606
1984 12:54:04.924687 MTRR: Fixed MSR 0x26d 0x0606060606060606
1985 12:54:04.928125 MTRR: Fixed MSR 0x26e 0x0606060606060606
1986 12:54:04.934504 MTRR: Fixed MSR 0x26f 0x0606060606060606
1987 12:54:04.940883 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
1988 12:54:04.944558 call enable_fixed_mtrr()
1989 12:54:04.948226 Checking cr50 for pending updates
1990 12:54:04.951506 CPU physical address size: 39 bits
1991 12:54:04.954902 MTRR: Fixed MSR 0x250 0x0606060606060606
1992 12:54:04.958055 MTRR: Fixed MSR 0x250 0x0606060606060606
1993 12:54:04.961355 MTRR: Fixed MSR 0x258 0x0606060606060606
1994 12:54:04.964656 MTRR: Fixed MSR 0x259 0x0000000000000000
1995 12:54:04.971171 MTRR: Fixed MSR 0x268 0x0606060606060606
1996 12:54:04.974746 MTRR: Fixed MSR 0x269 0x0606060606060606
1997 12:54:04.978017 MTRR: Fixed MSR 0x26a 0x0606060606060606
1998 12:54:04.981194 MTRR: Fixed MSR 0x26b 0x0606060606060606
1999 12:54:04.988313 MTRR: Fixed MSR 0x26c 0x0606060606060606
2000 12:54:04.991668 MTRR: Fixed MSR 0x26d 0x0606060606060606
2001 12:54:04.994400 MTRR: Fixed MSR 0x26e 0x0606060606060606
2002 12:54:04.998173 MTRR: Fixed MSR 0x26f 0x0606060606060606
2003 12:54:05.005185 MTRR: Fixed MSR 0x258 0x0606060606060606
2004 12:54:05.005269 call enable_fixed_mtrr()
2005 12:54:05.012156 MTRR: Fixed MSR 0x259 0x0000000000000000
2006 12:54:05.015414 MTRR: Fixed MSR 0x268 0x0606060606060606
2007 12:54:05.018692 MTRR: Fixed MSR 0x269 0x0606060606060606
2008 12:54:05.022144 MTRR: Fixed MSR 0x26a 0x0606060606060606
2009 12:54:05.028443 MTRR: Fixed MSR 0x26b 0x0606060606060606
2010 12:54:05.031917 MTRR: Fixed MSR 0x26c 0x0606060606060606
2011 12:54:05.035181 MTRR: Fixed MSR 0x26d 0x0606060606060606
2012 12:54:05.038458 MTRR: Fixed MSR 0x26e 0x0606060606060606
2013 12:54:05.044672 MTRR: Fixed MSR 0x26f 0x0606060606060606
2014 12:54:05.048459 CPU physical address size: 39 bits
2015 12:54:05.051399 call enable_fixed_mtrr()
2016 12:54:05.055047 Reading cr50 TPM mode
2017 12:54:05.058717 MTRR: Fixed MSR 0x250 0x0606060606060606
2018 12:54:05.062079 MTRR: Fixed MSR 0x250 0x0606060606060606
2019 12:54:05.065783 MTRR: Fixed MSR 0x258 0x0606060606060606
2020 12:54:05.068942 MTRR: Fixed MSR 0x259 0x0000000000000000
2021 12:54:05.075424 MTRR: Fixed MSR 0x268 0x0606060606060606
2022 12:54:05.078456 MTRR: Fixed MSR 0x269 0x0606060606060606
2023 12:54:05.082302 MTRR: Fixed MSR 0x26a 0x0606060606060606
2024 12:54:05.085388 MTRR: Fixed MSR 0x26b 0x0606060606060606
2025 12:54:05.091963 MTRR: Fixed MSR 0x26c 0x0606060606060606
2026 12:54:05.095400 MTRR: Fixed MSR 0x26d 0x0606060606060606
2027 12:54:05.098685 MTRR: Fixed MSR 0x26e 0x0606060606060606
2028 12:54:05.102082 MTRR: Fixed MSR 0x26f 0x0606060606060606
2029 12:54:05.109658 MTRR: Fixed MSR 0x258 0x0606060606060606
2030 12:54:05.109766 call enable_fixed_mtrr()
2031 12:54:05.116220 MTRR: Fixed MSR 0x259 0x0000000000000000
2032 12:54:05.119440 MTRR: Fixed MSR 0x268 0x0606060606060606
2033 12:54:05.122812 MTRR: Fixed MSR 0x269 0x0606060606060606
2034 12:54:05.126293 MTRR: Fixed MSR 0x26a 0x0606060606060606
2035 12:54:05.132687 MTRR: Fixed MSR 0x26b 0x0606060606060606
2036 12:54:05.135759 MTRR: Fixed MSR 0x26c 0x0606060606060606
2037 12:54:05.139080 MTRR: Fixed MSR 0x26d 0x0606060606060606
2038 12:54:05.142882 MTRR: Fixed MSR 0x26e 0x0606060606060606
2039 12:54:05.149109 MTRR: Fixed MSR 0x26f 0x0606060606060606
2040 12:54:05.152389 CPU physical address size: 39 bits
2041 12:54:05.155718 call enable_fixed_mtrr()
2042 12:54:05.158876 MTRR: Fixed MSR 0x250 0x0606060606060606
2043 12:54:05.162286 MTRR: Fixed MSR 0x250 0x0606060606060606
2044 12:54:05.168796 MTRR: Fixed MSR 0x258 0x0606060606060606
2045 12:54:05.172368 MTRR: Fixed MSR 0x259 0x0000000000000000
2046 12:54:05.175499 MTRR: Fixed MSR 0x268 0x0606060606060606
2047 12:54:05.178886 MTRR: Fixed MSR 0x269 0x0606060606060606
2048 12:54:05.185655 MTRR: Fixed MSR 0x26a 0x0606060606060606
2049 12:54:05.188827 MTRR: Fixed MSR 0x26b 0x0606060606060606
2050 12:54:05.192115 MTRR: Fixed MSR 0x26c 0x0606060606060606
2051 12:54:05.195385 MTRR: Fixed MSR 0x26d 0x0606060606060606
2052 12:54:05.202425 MTRR: Fixed MSR 0x26e 0x0606060606060606
2053 12:54:05.205702 MTRR: Fixed MSR 0x26f 0x0606060606060606
2054 12:54:05.209054 MTRR: Fixed MSR 0x258 0x0606060606060606
2055 12:54:05.212370 call enable_fixed_mtrr()
2056 12:54:05.215662 MTRR: Fixed MSR 0x259 0x0000000000000000
2057 12:54:05.222179 MTRR: Fixed MSR 0x268 0x0606060606060606
2058 12:54:05.225432 MTRR: Fixed MSR 0x269 0x0606060606060606
2059 12:54:05.228827 MTRR: Fixed MSR 0x26a 0x0606060606060606
2060 12:54:05.232119 MTRR: Fixed MSR 0x26b 0x0606060606060606
2061 12:54:05.238889 MTRR: Fixed MSR 0x26c 0x0606060606060606
2062 12:54:05.242081 MTRR: Fixed MSR 0x26d 0x0606060606060606
2063 12:54:05.245261 MTRR: Fixed MSR 0x26e 0x0606060606060606
2064 12:54:05.248523 MTRR: Fixed MSR 0x26f 0x0606060606060606
2065 12:54:05.252724 CPU physical address size: 39 bits
2066 12:54:05.259286 call enable_fixed_mtrr()
2067 12:54:05.262539 CPU physical address size: 39 bits
2068 12:54:05.265757 CPU physical address size: 39 bits
2069 12:54:05.272509 BS: BS_PAYLOAD_LOAD entry times (exec / console): 112 / 6 ms
2070 12:54:05.275734 CPU physical address size: 39 bits
2071 12:54:05.282383 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2072 12:54:05.285578 Checking segment from ROM address 0xffc02b38
2073 12:54:05.292464 Checking segment from ROM address 0xffc02b54
2074 12:54:05.295733 Loading segment from ROM address 0xffc02b38
2075 12:54:05.298989 code (compression=0)
2076 12:54:05.305612 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2077 12:54:05.315613 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2078 12:54:05.315714 it's not compressed!
2079 12:54:05.456318 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2080 12:54:05.462817 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2081 12:54:05.469233 Loading segment from ROM address 0xffc02b54
2082 12:54:05.469336 Entry Point 0x30000000
2083 12:54:05.472944 Loaded segments
2084 12:54:05.479227 BS: BS_PAYLOAD_LOAD run times (exec / console): 139 / 63 ms
2085 12:54:05.522123 Finalizing chipset.
2086 12:54:05.525584 Finalizing SMM.
2087 12:54:05.525682 APMC done.
2088 12:54:05.532504 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2089 12:54:05.535859 mp_park_aps done after 0 msecs.
2090 12:54:05.539076 Jumping to boot code at 0x30000000(0x76b25000)
2091 12:54:05.549007 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2092 12:54:05.549094
2093 12:54:05.549160
2094 12:54:05.552305
2095 12:54:05.552388 Starting depthcharge on Voema...
2096 12:54:05.552795 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2097 12:54:05.552897 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2098 12:54:05.552986 Setting prompt string to ['volteer:']
2099 12:54:05.553067 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2100 12:54:05.555536
2101 12:54:05.562154 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2102 12:54:05.562235
2103 12:54:05.568990 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2104 12:54:05.569092
2105 12:54:05.575089 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2106 12:54:05.575183
2107 12:54:05.578300 Failed to find eMMC card reader
2108 12:54:05.578387
2109 12:54:05.578455 Wipe memory regions:
2110 12:54:05.582032
2111 12:54:05.585313 [0x00000000001000, 0x000000000a0000)
2112 12:54:05.585426
2113 12:54:05.588452 [0x00000000100000, 0x00000030000000)
2114 12:54:05.613797
2115 12:54:05.617137 [0x00000032662db0, 0x000000769ef000)
2116 12:54:05.652278
2117 12:54:05.655131 [0x00000100000000, 0x00000280400000)
2118 12:54:05.857215
2119 12:54:05.860615 ec_init: CrosEC protocol v3 supported (256, 256)
2120 12:54:05.860708
2121 12:54:05.867072 update_port_state: port C0 state: usb enable 1 mux conn 0
2122 12:54:05.867176
2123 12:54:05.877008 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2124 12:54:05.877164
2125 12:54:05.880332 pmc_check_ipc_sts: STS_BUSY done after 1616 us
2126 12:54:05.880467
2127 12:54:05.887023 send_conn_disc_msg: pmc_send_cmd succeeded
2128 12:54:06.319849
2129 12:54:06.320008 R8152: Initializing
2130 12:54:06.320078
2131 12:54:06.323101 Version 6 (ocp_data = 5c30)
2132 12:54:06.323185
2133 12:54:06.326420 R8152: Done initializing
2134 12:54:06.326504
2135 12:54:06.329238 Adding net device
2136 12:54:06.632061
2137 12:54:06.635482 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2138 12:54:06.635568
2139 12:54:06.635643
2140 12:54:06.635706
2141 12:54:06.639173 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2143 12:54:06.739922 volteer: tftpboot 192.168.201.1 9879076/tftp-deploy-m4wlirzz/kernel/bzImage 9879076/tftp-deploy-m4wlirzz/kernel/cmdline 9879076/tftp-deploy-m4wlirzz/ramdisk/ramdisk.cpio.gz
2144 12:54:06.740101 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2145 12:54:06.740190 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2146 12:54:06.744290 tftpboot 192.168.201.1 9879076/tftp-deploy-m4wlirzz/kernel/bzImoy-m4wlirzz/kernel/cmdline 9879076/tftp-deploy-m4wlirzz/ramdisk/ramdisk.cpio.gz
2147 12:54:06.744378
2148 12:54:06.744444 Waiting for link
2149 12:54:06.947804
2150 12:54:06.947958 done.
2151 12:54:06.948025
2152 12:54:06.948087 MAC: 00:24:32:30:7c:e4
2153 12:54:06.948148
2154 12:54:06.951207 Sending DHCP discover... done.
2155 12:54:06.951292
2156 12:54:06.954044 Waiting for reply... done.
2157 12:54:06.954127
2158 12:54:06.957558 Sending DHCP request... done.
2159 12:54:06.957646
2160 12:54:06.961181 Waiting for reply... done.
2161 12:54:06.961265
2162 12:54:06.964117 My ip is 192.168.201.23
2163 12:54:06.964200
2164 12:54:06.967512 The DHCP server ip is 192.168.201.1
2165 12:54:06.967651
2166 12:54:06.974251 TFTP server IP predefined by user: 192.168.201.1
2167 12:54:06.974336
2168 12:54:06.980743 Bootfile predefined by user: 9879076/tftp-deploy-m4wlirzz/kernel/bzImage
2169 12:54:06.980829
2170 12:54:06.984226 Sending tftp read request... done.
2171 12:54:06.984311
2172 12:54:06.987065 Waiting for the transfer...
2173 12:54:06.987155
2174 12:54:07.582934 00000000 ################################################################
2175 12:54:07.583087
2176 12:54:08.165371 00080000 ################################################################
2177 12:54:08.165510
2178 12:54:08.738102 00100000 ################################################################
2179 12:54:08.738245
2180 12:54:09.318577 00180000 ################################################################
2181 12:54:09.318721
2182 12:54:09.889494 00200000 ################################################################
2183 12:54:09.889635
2184 12:54:10.458074 00280000 ################################################################
2185 12:54:10.458251
2186 12:54:11.027782 00300000 ################################################################
2187 12:54:11.027958
2188 12:54:11.570154 00380000 ################################################################
2189 12:54:11.570327
2190 12:54:12.125385 00400000 ################################################################
2191 12:54:12.125531
2192 12:54:12.676423 00480000 ################################################################
2193 12:54:12.676597
2194 12:54:13.218453 00500000 ################################################################
2195 12:54:13.218604
2196 12:54:13.748885 00580000 ################################################################
2197 12:54:13.749045
2198 12:54:14.290722 00600000 ################################################################
2199 12:54:14.290865
2200 12:54:14.833847 00680000 ################################################################
2201 12:54:14.833991
2202 12:54:15.379509 00700000 ################################################################
2203 12:54:15.379691
2204 12:54:15.923109 00780000 ################################################################
2205 12:54:15.923270
2206 12:54:16.514600 00800000 ################################################################
2207 12:54:16.514794
2208 12:54:17.133603 00880000 ################################################################
2209 12:54:17.133749
2210 12:54:17.776545 00900000 ################################################################
2211 12:54:17.777057
2212 12:54:18.373411 00980000 ################################################################
2213 12:54:18.373550
2214 12:54:18.762567 00a00000 ############################################## done.
2215 12:54:18.762726
2216 12:54:18.765387 The bootfile was 10854400 bytes long.
2217 12:54:18.765467
2218 12:54:18.768804 Sending tftp read request... done.
2219 12:54:18.768909
2220 12:54:18.772188 Waiting for the transfer...
2221 12:54:18.772307
2222 12:54:19.311910 00000000 ################################################################
2223 12:54:19.312077
2224 12:54:19.841335 00080000 ################################################################
2225 12:54:19.841486
2226 12:54:20.395191 00100000 ################################################################
2227 12:54:20.395330
2228 12:54:20.935115 00180000 ################################################################
2229 12:54:20.935257
2230 12:54:21.454149 00200000 ################################################################
2231 12:54:21.454321
2232 12:54:21.978154 00280000 ################################################################
2233 12:54:21.978299
2234 12:54:22.491954 00300000 ################################################################
2235 12:54:22.492088
2236 12:54:23.018897 00380000 ################################################################
2237 12:54:23.019038
2238 12:54:23.541787 00400000 ################################################################
2239 12:54:23.542001
2240 12:54:24.061550 00480000 ################################################################
2241 12:54:24.061730
2242 12:54:24.579291 00500000 ################################################################
2243 12:54:24.579458
2244 12:54:25.107033 00580000 ################################################################
2245 12:54:25.107221
2246 12:54:25.628104 00600000 ################################################################
2247 12:54:25.628285
2248 12:54:26.164086 00680000 ################################################################
2249 12:54:26.164270
2250 12:54:26.688460 00700000 ################################################################
2251 12:54:26.688646
2252 12:54:27.208555 00780000 ################################################################
2253 12:54:27.208717
2254 12:54:27.733765 00800000 ################################################################
2255 12:54:27.733939
2256 12:54:28.033131 00880000 ###################################### done.
2257 12:54:28.033287
2258 12:54:28.036402 Sending tftp read request... done.
2259 12:54:28.036493
2260 12:54:28.039475 Waiting for the transfer...
2261 12:54:28.039603
2262 12:54:28.039675 00000000 # done.
2263 12:54:28.039763
2264 12:54:28.049472 Command line loaded dynamically from TFTP file: 9879076/tftp-deploy-m4wlirzz/kernel/cmdline
2265 12:54:28.049604
2266 12:54:28.062321 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2267 12:54:28.067617
2268 12:54:28.071166 Shutting down all USB controllers.
2269 12:54:28.071274
2270 12:54:28.071384 Removing current net device
2271 12:54:28.071478
2272 12:54:28.073994 Finalizing coreboot
2273 12:54:28.074108
2274 12:54:28.080989 Exiting depthcharge with code 4 at timestamp: 31166955
2275 12:54:28.081099
2276 12:54:28.081207
2277 12:54:28.081300 Starting kernel ...
2278 12:54:28.081401
2279 12:54:28.081492
2280 12:54:28.082141 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
2281 12:54:28.082278 start: 2.2.5 auto-login-action (timeout 00:04:22) [common]
2282 12:54:28.082392 Setting prompt string to ['Linux version [0-9]']
2283 12:54:28.082495 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2284 12:54:28.082607 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2286 12:58:50.083243 end: 2.2.5 auto-login-action (duration 00:04:22) [common]
2288 12:58:50.084465 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 262 seconds'
2290 12:58:50.085413 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2293 12:58:50.086968 end: 2 depthcharge-action (duration 00:05:00) [common]
2295 12:58:50.088427 Cleaning after the job
2296 12:58:50.088916 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/ramdisk
2297 12:58:50.093291 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/kernel
2298 12:58:50.098215 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9879076/tftp-deploy-m4wlirzz/modules
2299 12:58:50.100597 start: 5.1 power-off (timeout 00:00:30) [common]
2300 12:58:50.101477 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=off'
2301 12:58:50.185001 >> Command sent successfully.
2302 12:58:50.189044 Returned 0 in 0 seconds
2303 12:58:50.289967 end: 5.1 power-off (duration 00:00:00) [common]
2305 12:58:50.290296 start: 5.2 read-feedback (timeout 00:10:00) [common]
2306 12:58:50.290548 Listened to connection for namespace 'common' for up to 1s
2307 12:58:51.291762 Finalising connection for namespace 'common'
2308 12:58:51.291975 Disconnecting from shell: Finalise
2309 12:58:51.292064
2310 12:58:51.393077 end: 5.2 read-feedback (duration 00:00:01) [common]
2311 12:58:51.393687 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9879076
2312 12:58:51.404874 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9879076
2313 12:58:51.405029 JobError: Your job cannot terminate cleanly.