Boot log: asus-cx9400-volteer
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Kernel Warnings: 0
1 12:51:01.165179 lava-dispatcher, installed at version: 2023.06
2 12:51:01.165402 start: 0 validate
3 12:51:01.165536 Start time: 2023-09-23 12:51:01.165529+00:00 (UTC)
4 12:51:01.165679 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:51:01.165832 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 12:51:01.433598 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:51:01.433794 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.292-cip102-406-g9efaa60a8cb4%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:51:01.699899 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:51:01.700094 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.292-cip102-406-g9efaa60a8cb4%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 12:51:08.202742 validate duration: 7.04
12 12:51:08.203003 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:51:08.203100 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:51:08.203185 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:51:08.203301 Not decompressing ramdisk as can be used compressed.
16 12:51:08.203387 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 12:51:08.203452 saving as /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/ramdisk/rootfs.cpio.gz
18 12:51:08.203516 total size: 8418130 (8 MB)
19 12:51:08.838877 progress 0 % (0 MB)
20 12:51:08.843267 progress 5 % (0 MB)
21 12:51:08.845479 progress 10 % (0 MB)
22 12:51:08.847617 progress 15 % (1 MB)
23 12:51:08.849844 progress 20 % (1 MB)
24 12:51:08.851992 progress 25 % (2 MB)
25 12:51:08.854183 progress 30 % (2 MB)
26 12:51:08.856174 progress 35 % (2 MB)
27 12:51:08.858334 progress 40 % (3 MB)
28 12:51:08.860453 progress 45 % (3 MB)
29 12:51:08.862610 progress 50 % (4 MB)
30 12:51:08.864732 progress 55 % (4 MB)
31 12:51:08.866852 progress 60 % (4 MB)
32 12:51:08.868810 progress 65 % (5 MB)
33 12:51:08.870939 progress 70 % (5 MB)
34 12:51:08.873060 progress 75 % (6 MB)
35 12:51:08.875169 progress 80 % (6 MB)
36 12:51:08.877321 progress 85 % (6 MB)
37 12:51:08.879435 progress 90 % (7 MB)
38 12:51:08.881553 progress 95 % (7 MB)
39 12:51:08.883530 progress 100 % (8 MB)
40 12:51:08.883752 8 MB downloaded in 0.68 s (11.80 MB/s)
41 12:51:08.883902 end: 1.1.1 http-download (duration 00:00:01) [common]
43 12:51:08.884137 end: 1.1 download-retry (duration 00:00:01) [common]
44 12:51:08.884223 start: 1.2 download-retry (timeout 00:09:59) [common]
45 12:51:08.884309 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 12:51:08.884441 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.292-cip102-406-g9efaa60a8cb4/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 12:51:08.884510 saving as /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/kernel/bzImage
48 12:51:08.884570 total size: 11473408 (10 MB)
49 12:51:08.884630 No compression specified
50 12:51:08.885826 progress 0 % (0 MB)
51 12:51:08.889004 progress 5 % (0 MB)
52 12:51:08.892004 progress 10 % (1 MB)
53 12:51:08.894914 progress 15 % (1 MB)
54 12:51:08.897892 progress 20 % (2 MB)
55 12:51:08.900689 progress 25 % (2 MB)
56 12:51:08.903698 progress 30 % (3 MB)
57 12:51:08.906539 progress 35 % (3 MB)
58 12:51:08.909533 progress 40 % (4 MB)
59 12:51:08.912305 progress 45 % (4 MB)
60 12:51:08.915489 progress 50 % (5 MB)
61 12:51:08.918284 progress 55 % (6 MB)
62 12:51:08.921274 progress 60 % (6 MB)
63 12:51:08.924013 progress 65 % (7 MB)
64 12:51:08.926915 progress 70 % (7 MB)
65 12:51:08.929774 progress 75 % (8 MB)
66 12:51:08.932671 progress 80 % (8 MB)
67 12:51:08.935453 progress 85 % (9 MB)
68 12:51:08.938349 progress 90 % (9 MB)
69 12:51:08.941097 progress 95 % (10 MB)
70 12:51:08.944013 progress 100 % (10 MB)
71 12:51:08.944139 10 MB downloaded in 0.06 s (183.70 MB/s)
72 12:51:08.944286 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:51:08.944515 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:51:08.944606 start: 1.3 download-retry (timeout 00:09:59) [common]
76 12:51:08.944691 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 12:51:08.944827 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.292-cip102-406-g9efaa60a8cb4/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 12:51:08.944896 saving as /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/modules/modules.tar
79 12:51:08.944981 total size: 484692 (0 MB)
80 12:51:08.945057 Using unxz to decompress xz
81 12:51:08.948684 progress 6 % (0 MB)
82 12:51:08.949093 progress 13 % (0 MB)
83 12:51:08.949343 progress 20 % (0 MB)
84 12:51:08.950749 progress 27 % (0 MB)
85 12:51:08.952909 progress 33 % (0 MB)
86 12:51:08.954722 progress 40 % (0 MB)
87 12:51:08.956691 progress 47 % (0 MB)
88 12:51:08.958615 progress 54 % (0 MB)
89 12:51:08.960593 progress 60 % (0 MB)
90 12:51:08.962943 progress 67 % (0 MB)
91 12:51:08.964926 progress 74 % (0 MB)
92 12:51:08.966930 progress 81 % (0 MB)
93 12:51:08.969153 progress 87 % (0 MB)
94 12:51:08.970806 progress 94 % (0 MB)
95 12:51:08.972891 progress 100 % (0 MB)
96 12:51:08.978820 0 MB downloaded in 0.03 s (13.66 MB/s)
97 12:51:08.979076 end: 1.3.1 http-download (duration 00:00:00) [common]
99 12:51:08.979373 end: 1.3 download-retry (duration 00:00:00) [common]
100 12:51:08.979496 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
101 12:51:08.979623 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
102 12:51:08.979731 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 12:51:08.979851 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
104 12:51:08.980175 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m
105 12:51:08.980335 makedir: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin
106 12:51:08.980444 makedir: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/tests
107 12:51:08.980554 makedir: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/results
108 12:51:08.980706 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-add-keys
109 12:51:08.980986 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-add-sources
110 12:51:08.981219 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-background-process-start
111 12:51:08.981387 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-background-process-stop
112 12:51:08.981527 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-common-functions
113 12:51:08.981651 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-echo-ipv4
114 12:51:08.981774 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-install-packages
115 12:51:08.981896 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-installed-packages
116 12:51:08.982017 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-os-build
117 12:51:08.982139 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-probe-channel
118 12:51:08.982260 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-probe-ip
119 12:51:08.982381 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-target-ip
120 12:51:08.982503 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-target-mac
121 12:51:08.982627 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-target-storage
122 12:51:08.982831 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-case
123 12:51:08.982983 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-event
124 12:51:08.983117 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-feedback
125 12:51:08.983238 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-raise
126 12:51:08.983361 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-reference
127 12:51:08.983486 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-runner
128 12:51:08.983606 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-set
129 12:51:08.983729 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-test-shell
130 12:51:08.983854 Updating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-install-packages (oe)
131 12:51:08.984005 Updating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/bin/lava-installed-packages (oe)
132 12:51:08.984125 Creating /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/environment
133 12:51:08.984224 LAVA metadata
134 12:51:08.984298 - LAVA_JOB_ID=11602091
135 12:51:08.984364 - LAVA_DISPATCHER_IP=192.168.201.1
136 12:51:08.984471 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
137 12:51:08.984538 skipped lava-vland-overlay
138 12:51:08.984619 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 12:51:08.984699 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
140 12:51:08.984764 skipped lava-multinode-overlay
141 12:51:08.984839 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 12:51:08.984920 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
143 12:51:08.985073 Loading test definitions
144 12:51:08.985181 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
145 12:51:08.985255 Using /lava-11602091 at stage 0
146 12:51:08.985549 uuid=11602091_1.4.2.3.1 testdef=None
147 12:51:08.985638 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 12:51:08.985722 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
149 12:51:08.986236 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 12:51:08.986500 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
152 12:51:08.987131 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 12:51:08.987382 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
155 12:51:08.988082 runner path: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/0/tests/0_dmesg test_uuid 11602091_1.4.2.3.1
156 12:51:08.988251 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 12:51:08.988521 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
159 12:51:08.988594 Using /lava-11602091 at stage 1
160 12:51:08.988886 uuid=11602091_1.4.2.3.5 testdef=None
161 12:51:08.989029 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 12:51:08.989114 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
163 12:51:08.989571 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 12:51:08.989831 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
166 12:51:08.990537 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 12:51:08.990764 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
169 12:51:08.991372 runner path: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/1/tests/1_bootrr test_uuid 11602091_1.4.2.3.5
170 12:51:08.991518 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 12:51:08.991724 Creating lava-test-runner.conf files
173 12:51:08.991787 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/0 for stage 0
174 12:51:08.991874 - 0_dmesg
175 12:51:08.991951 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11602091/lava-overlay-j1kkza8m/lava-11602091/1 for stage 1
176 12:51:08.992040 - 1_bootrr
177 12:51:08.992131 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 12:51:08.992215 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
179 12:51:09.000437 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 12:51:09.000546 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
181 12:51:09.000633 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 12:51:09.000717 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 12:51:09.000802 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
184 12:51:09.242279 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 12:51:09.242635 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
186 12:51:09.242752 extracting modules file /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11602091/extract-overlay-ramdisk-pedcyte4/ramdisk
187 12:51:09.264034 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 12:51:09.264190 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
189 12:51:09.264290 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11602091/compress-overlay-3t_c7kbd/overlay-1.4.2.4.tar.gz to ramdisk
190 12:51:09.264366 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11602091/compress-overlay-3t_c7kbd/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11602091/extract-overlay-ramdisk-pedcyte4/ramdisk
191 12:51:09.278461 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 12:51:09.278661 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
193 12:51:09.278799 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 12:51:09.278941 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
195 12:51:09.279076 Building ramdisk /var/lib/lava/dispatcher/tmp/11602091/extract-overlay-ramdisk-pedcyte4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11602091/extract-overlay-ramdisk-pedcyte4/ramdisk
196 12:51:09.421343 >> 53982 blocks
197 12:51:10.320078 rename /var/lib/lava/dispatcher/tmp/11602091/extract-overlay-ramdisk-pedcyte4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/ramdisk/ramdisk.cpio.gz
198 12:51:10.320518 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 12:51:10.320642 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 12:51:10.320746 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 12:51:10.320840 No mkimage arch provided, not using FIT.
202 12:51:10.320955 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 12:51:10.321056 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 12:51:10.321175 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
205 12:51:10.321270 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 12:51:10.321356 No LXC device requested
207 12:51:10.321439 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 12:51:10.321527 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 12:51:10.321607 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 12:51:10.321685 Checking files for TFTP limit of 4294967296 bytes.
211 12:51:10.322237 end: 1 tftp-deploy (duration 00:00:02) [common]
212 12:51:10.322416 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 12:51:10.322529 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 12:51:10.322649 substitutions:
215 12:51:10.322717 - {DTB}: None
216 12:51:10.322818 - {INITRD}: 11602091/tftp-deploy-5liexiwc/ramdisk/ramdisk.cpio.gz
217 12:51:10.322878 - {KERNEL}: 11602091/tftp-deploy-5liexiwc/kernel/bzImage
218 12:51:10.322937 - {LAVA_MAC}: None
219 12:51:10.322995 - {PRESEED_CONFIG}: None
220 12:51:10.323051 - {PRESEED_LOCAL}: None
221 12:51:10.323108 - {RAMDISK}: 11602091/tftp-deploy-5liexiwc/ramdisk/ramdisk.cpio.gz
222 12:51:10.323164 - {ROOT_PART}: None
223 12:51:10.323219 - {ROOT}: None
224 12:51:10.323312 - {SERVER_IP}: 192.168.201.1
225 12:51:10.323367 - {TEE}: None
226 12:51:10.323423 Parsed boot commands:
227 12:51:10.323477 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 12:51:10.323649 Parsed boot commands: tftpboot 192.168.201.1 11602091/tftp-deploy-5liexiwc/kernel/bzImage 11602091/tftp-deploy-5liexiwc/kernel/cmdline 11602091/tftp-deploy-5liexiwc/ramdisk/ramdisk.cpio.gz
229 12:51:10.323753 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 12:51:10.323856 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 12:51:10.323948 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 12:51:10.324035 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 12:51:10.324108 Not connected, no need to disconnect.
234 12:51:10.324183 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 12:51:10.324293 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 12:51:10.324378 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-1'
237 12:51:10.328150 Setting prompt string to ['lava-test: # ']
238 12:51:10.328606 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 12:51:10.328716 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 12:51:10.328818 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 12:51:10.328924 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 12:51:10.329164 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-1' '--port=1' '--command=reboot'
243 12:51:15.461352 >> Command sent successfully.
244 12:51:15.463734 Returned 0 in 5 seconds
245 12:51:15.564147 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 12:51:15.564475 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 12:51:15.564573 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 12:51:15.564662 Setting prompt string to 'Starting depthcharge on Voema...'
250 12:51:15.564730 Changing prompt to 'Starting depthcharge on Voema...'
251 12:51:15.564798 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
252 12:51:15.565069 [Enter `^Ec?' for help]
253 12:51:17.168416
254 12:51:17.168565
255 12:51:17.177792 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
256 12:51:17.181196 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
257 12:51:17.187883 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
258 12:51:17.191016 CPU: AES supported, TXT NOT supported, VT supported
259 12:51:17.197575 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
260 12:51:17.201104 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
261 12:51:17.208017 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
262 12:51:17.211154 VBOOT: Loading verstage.
263 12:51:17.214350 FMAP: Found "FLASH" version 1.1 at 0x1804000.
264 12:51:17.221285 FMAP: base = 0x0 size = 0x2000000 #areas = 32
265 12:51:17.224290 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
266 12:51:17.234858 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
267 12:51:17.241455 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
268 12:51:17.241546
269 12:51:17.241616
270 12:51:17.254759 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
271 12:51:17.268625 Probing TPM: . done!
272 12:51:17.271855 TPM ready after 0 ms
273 12:51:17.275764 Connected to device vid:did:rid of 1ae0:0028:00
274 12:51:17.286620 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
275 12:51:17.293161 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
276 12:51:17.296643 Initialized TPM device CR50 revision 0
277 12:51:17.347202 tlcl_send_startup: Startup return code is 0
278 12:51:17.347355 TPM: setup succeeded
279 12:51:17.363179 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
280 12:51:17.376734 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
281 12:51:17.389376 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
282 12:51:17.399540 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
283 12:51:17.403298 Chrome EC: UHEPI supported
284 12:51:17.406676 Phase 1
285 12:51:17.410009 FMAP: area GBB found @ 1805000 (458752 bytes)
286 12:51:17.416396 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
287 12:51:17.427006 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
288 12:51:17.433341 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
289 12:51:17.439958 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
290 12:51:17.443458 Recovery requested (1009000e)
291 12:51:17.446859 TPM: Extending digest for VBOOT: boot mode into PCR 0
292 12:51:17.458003 tlcl_extend: response is 0
293 12:51:17.464932 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
294 12:51:17.474816 tlcl_extend: response is 0
295 12:51:17.481223 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
296 12:51:17.488000 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
297 12:51:17.494469 BS: verstage times (exec / console): total (unknown) / 142 ms
298 12:51:17.494556
299 12:51:17.494623
300 12:51:17.507796 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
301 12:51:17.511179 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
302 12:51:17.518664 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
303 12:51:17.521894 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
304 12:51:17.525121 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
305 12:51:17.531841 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
306 12:51:17.535297 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
307 12:51:17.538453 TCO_STS: 0000 0000
308 12:51:17.542005 GEN_PMCON: d0015038 00002200
309 12:51:17.542091 GBLRST_CAUSE: 00000000 00000000
310 12:51:17.545118 HPR_CAUSE0: 00000000
311 12:51:17.548462 prev_sleep_state 5
312 12:51:17.551899 Boot Count incremented to 26149
313 12:51:17.558723 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
314 12:51:17.565111 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
315 12:51:17.572073 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
316 12:51:17.578421 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
317 12:51:17.582246 Chrome EC: UHEPI supported
318 12:51:17.588739 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
319 12:51:17.601567 Probing TPM: done!
320 12:51:17.609590 Connected to device vid:did:rid of 1ae0:0028:00
321 12:51:17.616700 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
322 12:51:17.626466 Initialized TPM device CR50 revision 0
323 12:51:17.636570 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
324 12:51:17.643399 MRC: Hash idx 0x100b comparison successful.
325 12:51:17.646499 MRC cache found, size faa8
326 12:51:17.646585 bootmode is set to: 2
327 12:51:17.649758 SPD index = 0
328 12:51:17.656467 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
329 12:51:17.659939 SPD: module type is LPDDR4X
330 12:51:17.666791 SPD: module part number is MT53E512M64D4NW-046
331 12:51:17.670108 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
332 12:51:17.676509 SPD: device width 16 bits, bus width 16 bits
333 12:51:17.679915 SPD: module size is 1024 MB (per channel)
334 12:51:18.114488 CBMEM:
335 12:51:18.117966 IMD: root @ 0x76fff000 254 entries.
336 12:51:18.121157 IMD: root @ 0x76ffec00 62 entries.
337 12:51:18.124552 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
338 12:51:18.131418 FMAP: area RW_VPD found @ f35000 (8192 bytes)
339 12:51:18.134630 External stage cache:
340 12:51:18.137904 IMD: root @ 0x7b3ff000 254 entries.
341 12:51:18.140948 IMD: root @ 0x7b3fec00 62 entries.
342 12:51:18.156430 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
343 12:51:18.162998 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
344 12:51:18.169315 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
345 12:51:18.184134 MRC: 'RECOVERY_MRC_CACHE' does not need update.
346 12:51:18.187768 cse_lite: Skip switching to RW in the recovery path
347 12:51:18.191632 8 DIMMs found
348 12:51:18.191720 SMM Memory Map
349 12:51:18.194899 SMRAM : 0x7b000000 0x800000
350 12:51:18.198337 Subregion 0: 0x7b000000 0x200000
351 12:51:18.202014 Subregion 1: 0x7b200000 0x200000
352 12:51:18.205223 Subregion 2: 0x7b400000 0x400000
353 12:51:18.208380 top_of_ram = 0x77000000
354 12:51:18.211697 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
355 12:51:18.218685 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
356 12:51:18.224898 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
357 12:51:18.228396 MTRR Range: Start=ff000000 End=0 (Size 1000000)
358 12:51:18.235313 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
359 12:51:18.242019 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
360 12:51:18.253406 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
361 12:51:18.256490 Processing 211 relocs. Offset value of 0x74c0b000
362 12:51:18.266327 BS: romstage times (exec / console): total (unknown) / 277 ms
363 12:51:18.272328
364 12:51:18.272412
365 12:51:18.282401 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
366 12:51:18.286381 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
367 12:51:18.295735 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
368 12:51:18.302570 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
369 12:51:18.308978 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
370 12:51:18.315530 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
371 12:51:18.362360 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
372 12:51:18.369117 Processing 5008 relocs. Offset value of 0x75d98000
373 12:51:18.372603 BS: postcar times (exec / console): total (unknown) / 59 ms
374 12:51:18.375559
375 12:51:18.375643
376 12:51:18.386578 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
377 12:51:18.386666 Normal boot
378 12:51:18.389870 FW_CONFIG value is 0x804c02
379 12:51:18.393116 PCI: 00:07.0 disabled by fw_config
380 12:51:18.396590 PCI: 00:07.1 disabled by fw_config
381 12:51:18.399965 PCI: 00:0d.2 disabled by fw_config
382 12:51:18.403079 PCI: 00:1c.7 disabled by fw_config
383 12:51:18.409820 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
384 12:51:18.416572 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
385 12:51:18.419692 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
386 12:51:18.423217 GENERIC: 0.0 disabled by fw_config
387 12:51:18.426392 GENERIC: 1.0 disabled by fw_config
388 12:51:18.433118 fw_config match found: DB_USB=USB3_ACTIVE
389 12:51:18.436531 fw_config match found: DB_USB=USB3_ACTIVE
390 12:51:18.439857 fw_config match found: DB_USB=USB3_ACTIVE
391 12:51:18.443085 fw_config match found: DB_USB=USB3_ACTIVE
392 12:51:18.450204 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
393 12:51:18.456401 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
394 12:51:18.463153 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
395 12:51:18.473325 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
396 12:51:18.476467 microcode: sig=0x806c1 pf=0x80 revision=0x86
397 12:51:18.479676 microcode: Update skipped, already up-to-date
398 12:51:18.486312 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
399 12:51:18.516269 Detected 4 core, 8 thread CPU.
400 12:51:18.519674 Setting up SMI for CPU
401 12:51:18.522809 IED base = 0x7b400000
402 12:51:18.522895 IED size = 0x00400000
403 12:51:18.526190 Will perform SMM setup.
404 12:51:18.532842 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
405 12:51:18.539397 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
406 12:51:18.546166 Processing 16 relocs. Offset value of 0x00030000
407 12:51:18.549480 Attempting to start 7 APs
408 12:51:18.552694 Waiting for 10ms after sending INIT.
409 12:51:18.568039 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
410 12:51:18.568126 done.
411 12:51:18.571316 AP: slot 6 apic_id 2.
412 12:51:18.574672 AP: slot 2 apic_id 3.
413 12:51:18.577917 Waiting for 2nd SIPI to complete...done.
414 12:51:18.581335 AP: slot 4 apic_id 5.
415 12:51:18.581421 AP: slot 5 apic_id 4.
416 12:51:18.584585 AP: slot 7 apic_id 6.
417 12:51:18.588024 AP: slot 3 apic_id 7.
418 12:51:18.594899 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
419 12:51:18.601348 Processing 13 relocs. Offset value of 0x00038000
420 12:51:18.601434 Unable to locate Global NVS
421 12:51:18.611629 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
422 12:51:18.615192 Installing permanent SMM handler to 0x7b000000
423 12:51:18.624725 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
424 12:51:18.628338 Processing 794 relocs. Offset value of 0x7b010000
425 12:51:18.634748 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
426 12:51:18.642022 Processing 13 relocs. Offset value of 0x7b008000
427 12:51:18.648163 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
428 12:51:18.651846 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
429 12:51:18.658508 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
430 12:51:18.664958 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
431 12:51:18.671808 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
432 12:51:18.678420 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
433 12:51:18.681404 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
434 12:51:18.684946 Unable to locate Global NVS
435 12:51:18.691541 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
436 12:51:18.696118 Clearing SMI status registers
437 12:51:18.699359 SMI_STS: PM1
438 12:51:18.699444 PM1_STS: PWRBTN
439 12:51:18.709453 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
440 12:51:18.709542 In relocation handler: CPU 0
441 12:51:18.716157 New SMBASE=0x7b000000 IEDBASE=0x7b400000
442 12:51:18.719221 Writing SMRR. base = 0x7b000006, mask=0xff800c00
443 12:51:18.722594 Relocation complete.
444 12:51:18.729347 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
445 12:51:18.732699 In relocation handler: CPU 1
446 12:51:18.735928 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
447 12:51:18.739547 Relocation complete.
448 12:51:18.745894 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
449 12:51:18.749256 In relocation handler: CPU 7
450 12:51:18.752819 New SMBASE=0x7affe400 IEDBASE=0x7b400000
451 12:51:18.759228 Writing SMRR. base = 0x7b000006, mask=0xff800c00
452 12:51:18.759315 Relocation complete.
453 12:51:18.765786 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
454 12:51:18.769230 In relocation handler: CPU 3
455 12:51:18.772603 New SMBASE=0x7afff400 IEDBASE=0x7b400000
456 12:51:18.776080 Relocation complete.
457 12:51:18.782839 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
458 12:51:18.785911 In relocation handler: CPU 4
459 12:51:18.789676 New SMBASE=0x7afff000 IEDBASE=0x7b400000
460 12:51:18.792677 Relocation complete.
461 12:51:18.799527 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
462 12:51:18.802727 In relocation handler: CPU 5
463 12:51:18.805966 New SMBASE=0x7affec00 IEDBASE=0x7b400000
464 12:51:18.812568 Writing SMRR. base = 0x7b000006, mask=0xff800c00
465 12:51:18.812656 Relocation complete.
466 12:51:18.822835 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
467 12:51:18.822922 In relocation handler: CPU 2
468 12:51:18.829495 New SMBASE=0x7afff800 IEDBASE=0x7b400000
469 12:51:18.829585 Relocation complete.
470 12:51:18.839478 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
471 12:51:18.839564 In relocation handler: CPU 6
472 12:51:18.846183 New SMBASE=0x7affe800 IEDBASE=0x7b400000
473 12:51:18.850035 Writing SMRR. base = 0x7b000006, mask=0xff800c00
474 12:51:18.853590 Relocation complete.
475 12:51:18.853676 Initializing CPU #0
476 12:51:18.857183 CPU: vendor Intel device 806c1
477 12:51:18.861150 CPU: family 06, model 8c, stepping 01
478 12:51:18.863812 Clearing out pending MCEs
479 12:51:18.867261 Setting up local APIC...
480 12:51:18.867347 apic_id: 0x00 done.
481 12:51:18.870660 Turbo is available but hidden
482 12:51:18.874148 Turbo is available and visible
483 12:51:18.880854 microcode: Update skipped, already up-to-date
484 12:51:18.880946 CPU #0 initialized
485 12:51:18.883914 Initializing CPU #6
486 12:51:18.887575 Initializing CPU #2
487 12:51:18.887661 CPU: vendor Intel device 806c1
488 12:51:18.894309 CPU: family 06, model 8c, stepping 01
489 12:51:18.897261 CPU: vendor Intel device 806c1
490 12:51:18.900808 CPU: family 06, model 8c, stepping 01
491 12:51:18.903813 Clearing out pending MCEs
492 12:51:18.903898 Clearing out pending MCEs
493 12:51:18.907540 Setting up local APIC...
494 12:51:18.910519 Initializing CPU #5
495 12:51:18.910606 Initializing CPU #4
496 12:51:18.913957 CPU: vendor Intel device 806c1
497 12:51:18.917374 CPU: family 06, model 8c, stepping 01
498 12:51:18.920726 CPU: vendor Intel device 806c1
499 12:51:18.923959 CPU: family 06, model 8c, stepping 01
500 12:51:18.927261 Clearing out pending MCEs
501 12:51:18.930775 Clearing out pending MCEs
502 12:51:18.934203 Setting up local APIC...
503 12:51:18.934289 Initializing CPU #3
504 12:51:18.937630 Initializing CPU #7
505 12:51:18.940669 CPU: vendor Intel device 806c1
506 12:51:18.944112 CPU: family 06, model 8c, stepping 01
507 12:51:18.947214 CPU: vendor Intel device 806c1
508 12:51:18.950866 CPU: family 06, model 8c, stepping 01
509 12:51:18.954305 Clearing out pending MCEs
510 12:51:18.957370 Clearing out pending MCEs
511 12:51:18.960679 Setting up local APIC...
512 12:51:18.960764 apic_id: 0x04 done.
513 12:51:18.964035 Setting up local APIC...
514 12:51:18.967241 apic_id: 0x02 done.
515 12:51:18.967326 Setting up local APIC...
516 12:51:18.970520 apic_id: 0x06 done.
517 12:51:18.974068 Setting up local APIC...
518 12:51:18.977446 microcode: Update skipped, already up-to-date
519 12:51:18.980332 apic_id: 0x05 done.
520 12:51:18.980417 CPU #5 initialized
521 12:51:18.987269 microcode: Update skipped, already up-to-date
522 12:51:18.990749 microcode: Update skipped, already up-to-date
523 12:51:18.993911 apic_id: 0x03 done.
524 12:51:18.993996 Initializing CPU #1
525 12:51:19.001387 microcode: Update skipped, already up-to-date
526 12:51:19.001472 apic_id: 0x07 done.
527 12:51:19.003957 CPU #7 initialized
528 12:51:19.007562 CPU #4 initialized
529 12:51:19.007648 CPU #6 initialized
530 12:51:19.013984 microcode: Update skipped, already up-to-date
531 12:51:19.017670 microcode: Update skipped, already up-to-date
532 12:51:19.017755 CPU #2 initialized
533 12:51:19.020468 CPU #3 initialized
534 12:51:19.023905 CPU: vendor Intel device 806c1
535 12:51:19.027458 CPU: family 06, model 8c, stepping 01
536 12:51:19.030752 Clearing out pending MCEs
537 12:51:19.033991 Setting up local APIC...
538 12:51:19.034076 apic_id: 0x01 done.
539 12:51:19.040563 microcode: Update skipped, already up-to-date
540 12:51:19.040649 CPU #1 initialized
541 12:51:19.047617 bsp_do_flight_plan done after 464 msecs.
542 12:51:19.050820 CPU: frequency set to 4000 MHz
543 12:51:19.050906 Enabling SMIs.
544 12:51:19.057248 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 348 / 317 ms
545 12:51:19.073312 SATAXPCIE1 indicates PCIe NVMe is present
546 12:51:19.076668 Probing TPM: done!
547 12:51:19.080452 Connected to device vid:did:rid of 1ae0:0028:00
548 12:51:19.090990 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
549 12:51:19.093705 Initialized TPM device CR50 revision 0
550 12:51:19.097314 Enabling S0i3.4
551 12:51:19.103861 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
552 12:51:19.107210 Found a VBT of 8704 bytes after decompression
553 12:51:19.114081 cse_lite: CSE RO boot. HybridStorageMode disabled
554 12:51:19.120751 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
555 12:51:19.196618 FSPS returned 0
556 12:51:19.199673 Executing Phase 1 of FspMultiPhaseSiInit
557 12:51:19.209609 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
558 12:51:19.212770 port C0 DISC req: usage 1 usb3 1 usb2 5
559 12:51:19.216428 Raw Buffer output 0 00000511
560 12:51:19.219733 Raw Buffer output 1 00000000
561 12:51:19.223235 pmc_send_ipc_cmd succeeded
562 12:51:19.229989 port C1 DISC req: usage 1 usb3 2 usb2 3
563 12:51:19.230078 Raw Buffer output 0 00000321
564 12:51:19.232984 Raw Buffer output 1 00000000
565 12:51:19.237106 pmc_send_ipc_cmd succeeded
566 12:51:19.242749 Detected 4 core, 8 thread CPU.
567 12:51:19.246046 Detected 4 core, 8 thread CPU.
568 12:51:19.480169 Display FSP Version Info HOB
569 12:51:19.483809 Reference Code - CPU = a.0.4c.31
570 12:51:19.486787 uCode Version = 0.0.0.86
571 12:51:19.490086 TXT ACM version = ff.ff.ff.ffff
572 12:51:19.493620 Reference Code - ME = a.0.4c.31
573 12:51:19.496828 MEBx version = 0.0.0.0
574 12:51:19.500062 ME Firmware Version = Consumer SKU
575 12:51:19.503432 Reference Code - PCH = a.0.4c.31
576 12:51:19.506723 PCH-CRID Status = Disabled
577 12:51:19.509972 PCH-CRID Original Value = ff.ff.ff.ffff
578 12:51:19.513334 PCH-CRID New Value = ff.ff.ff.ffff
579 12:51:19.516553 OPROM - RST - RAID = ff.ff.ff.ffff
580 12:51:19.519920 PCH Hsio Version = 4.0.0.0
581 12:51:19.523447 Reference Code - SA - System Agent = a.0.4c.31
582 12:51:19.526489 Reference Code - MRC = 2.0.0.1
583 12:51:19.529984 SA - PCIe Version = a.0.4c.31
584 12:51:19.533736 SA-CRID Status = Disabled
585 12:51:19.537253 SA-CRID Original Value = 0.0.0.1
586 12:51:19.540119 SA-CRID New Value = 0.0.0.1
587 12:51:19.543658 OPROM - VBIOS = ff.ff.ff.ffff
588 12:51:19.547043 IO Manageability Engine FW Version = 11.1.4.0
589 12:51:19.549966 PHY Build Version = 0.0.0.e0
590 12:51:19.553206 Thunderbolt(TM) FW Version = 0.0.0.0
591 12:51:19.559888 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
592 12:51:19.563429 ITSS IRQ Polarities Before:
593 12:51:19.563514 IPC0: 0xffffffff
594 12:51:19.567001 IPC1: 0xffffffff
595 12:51:19.567087 IPC2: 0xffffffff
596 12:51:19.570111 IPC3: 0xffffffff
597 12:51:19.573626 ITSS IRQ Polarities After:
598 12:51:19.573711 IPC0: 0xffffffff
599 12:51:19.576609 IPC1: 0xffffffff
600 12:51:19.576693 IPC2: 0xffffffff
601 12:51:19.580356 IPC3: 0xffffffff
602 12:51:19.583397 Found PCIe Root Port #9 at PCI: 00:1d.0.
603 12:51:19.596617 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
604 12:51:19.606819 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
605 12:51:19.620102 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
606 12:51:19.626544 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
607 12:51:19.626663 Enumerating buses...
608 12:51:19.633419 Show all devs... Before device enumeration.
609 12:51:19.633507 Root Device: enabled 1
610 12:51:19.636434 DOMAIN: 0000: enabled 1
611 12:51:19.639828 CPU_CLUSTER: 0: enabled 1
612 12:51:19.643363 PCI: 00:00.0: enabled 1
613 12:51:19.643448 PCI: 00:02.0: enabled 1
614 12:51:19.646511 PCI: 00:04.0: enabled 1
615 12:51:19.650025 PCI: 00:05.0: enabled 1
616 12:51:19.653613 PCI: 00:06.0: enabled 0
617 12:51:19.653698 PCI: 00:07.0: enabled 0
618 12:51:19.656603 PCI: 00:07.1: enabled 0
619 12:51:19.659909 PCI: 00:07.2: enabled 0
620 12:51:19.659995 PCI: 00:07.3: enabled 0
621 12:51:19.663245 PCI: 00:08.0: enabled 1
622 12:51:19.666735 PCI: 00:09.0: enabled 0
623 12:51:19.670023 PCI: 00:0a.0: enabled 0
624 12:51:19.670109 PCI: 00:0d.0: enabled 1
625 12:51:19.673438 PCI: 00:0d.1: enabled 0
626 12:51:19.676773 PCI: 00:0d.2: enabled 0
627 12:51:19.680117 PCI: 00:0d.3: enabled 0
628 12:51:19.680204 PCI: 00:0e.0: enabled 0
629 12:51:19.683188 PCI: 00:10.2: enabled 1
630 12:51:19.686955 PCI: 00:10.6: enabled 0
631 12:51:19.689858 PCI: 00:10.7: enabled 0
632 12:51:19.689980 PCI: 00:12.0: enabled 0
633 12:51:19.693585 PCI: 00:12.6: enabled 0
634 12:51:19.696694 PCI: 00:13.0: enabled 0
635 12:51:19.696810 PCI: 00:14.0: enabled 1
636 12:51:19.700135 PCI: 00:14.1: enabled 0
637 12:51:19.703146 PCI: 00:14.2: enabled 1
638 12:51:19.706439 PCI: 00:14.3: enabled 1
639 12:51:19.706562 PCI: 00:15.0: enabled 1
640 12:51:19.709982 PCI: 00:15.1: enabled 1
641 12:51:19.713430 PCI: 00:15.2: enabled 1
642 12:51:19.716808 PCI: 00:15.3: enabled 1
643 12:51:19.716896 PCI: 00:16.0: enabled 1
644 12:51:19.720152 PCI: 00:16.1: enabled 0
645 12:51:19.723171 PCI: 00:16.2: enabled 0
646 12:51:19.726487 PCI: 00:16.3: enabled 0
647 12:51:19.726580 PCI: 00:16.4: enabled 0
648 12:51:19.729964 PCI: 00:16.5: enabled 0
649 12:51:19.733261 PCI: 00:17.0: enabled 1
650 12:51:19.733351 PCI: 00:19.0: enabled 0
651 12:51:19.736705 PCI: 00:19.1: enabled 1
652 12:51:19.739791 PCI: 00:19.2: enabled 0
653 12:51:19.743195 PCI: 00:1c.0: enabled 1
654 12:51:19.743282 PCI: 00:1c.1: enabled 0
655 12:51:19.746587 PCI: 00:1c.2: enabled 0
656 12:51:19.749724 PCI: 00:1c.3: enabled 0
657 12:51:19.753219 PCI: 00:1c.4: enabled 0
658 12:51:19.753305 PCI: 00:1c.5: enabled 0
659 12:51:19.756631 PCI: 00:1c.6: enabled 1
660 12:51:19.760019 PCI: 00:1c.7: enabled 0
661 12:51:19.763129 PCI: 00:1d.0: enabled 1
662 12:51:19.763240 PCI: 00:1d.1: enabled 0
663 12:51:19.766939 PCI: 00:1d.2: enabled 1
664 12:51:19.769686 PCI: 00:1d.3: enabled 0
665 12:51:19.769772 PCI: 00:1e.0: enabled 1
666 12:51:19.773084 PCI: 00:1e.1: enabled 0
667 12:51:19.776586 PCI: 00:1e.2: enabled 1
668 12:51:19.780077 PCI: 00:1e.3: enabled 1
669 12:51:19.780162 PCI: 00:1f.0: enabled 1
670 12:51:19.783123 PCI: 00:1f.1: enabled 0
671 12:51:19.786661 PCI: 00:1f.2: enabled 1
672 12:51:19.789655 PCI: 00:1f.3: enabled 1
673 12:51:19.789741 PCI: 00:1f.4: enabled 0
674 12:51:19.793346 PCI: 00:1f.5: enabled 1
675 12:51:19.796892 PCI: 00:1f.6: enabled 0
676 12:51:19.799884 PCI: 00:1f.7: enabled 0
677 12:51:19.799969 APIC: 00: enabled 1
678 12:51:19.803320 GENERIC: 0.0: enabled 1
679 12:51:19.806634 GENERIC: 0.0: enabled 1
680 12:51:19.806721 GENERIC: 1.0: enabled 1
681 12:51:19.810113 GENERIC: 0.0: enabled 1
682 12:51:19.812967 GENERIC: 1.0: enabled 1
683 12:51:19.816683 USB0 port 0: enabled 1
684 12:51:19.816769 GENERIC: 0.0: enabled 1
685 12:51:19.819658 USB0 port 0: enabled 1
686 12:51:19.822918 GENERIC: 0.0: enabled 1
687 12:51:19.823003 I2C: 00:1a: enabled 1
688 12:51:19.826399 I2C: 00:31: enabled 1
689 12:51:19.830061 I2C: 00:32: enabled 1
690 12:51:19.830150 I2C: 00:10: enabled 1
691 12:51:19.833163 I2C: 00:15: enabled 1
692 12:51:19.836541 GENERIC: 0.0: enabled 0
693 12:51:19.839884 GENERIC: 1.0: enabled 0
694 12:51:19.839971 GENERIC: 0.0: enabled 1
695 12:51:19.843320 SPI: 00: enabled 1
696 12:51:19.843407 SPI: 00: enabled 1
697 12:51:19.846896 PNP: 0c09.0: enabled 1
698 12:51:19.849771 GENERIC: 0.0: enabled 1
699 12:51:19.852938 USB3 port 0: enabled 1
700 12:51:19.853038 USB3 port 1: enabled 1
701 12:51:19.856303 USB3 port 2: enabled 0
702 12:51:19.859722 USB3 port 3: enabled 0
703 12:51:19.859807 USB2 port 0: enabled 0
704 12:51:19.863248 USB2 port 1: enabled 1
705 12:51:19.866817 USB2 port 2: enabled 1
706 12:51:19.869788 USB2 port 3: enabled 0
707 12:51:19.869872 USB2 port 4: enabled 1
708 12:51:19.872972 USB2 port 5: enabled 0
709 12:51:19.876333 USB2 port 6: enabled 0
710 12:51:19.876417 USB2 port 7: enabled 0
711 12:51:19.880050 USB2 port 8: enabled 0
712 12:51:19.883259 USB2 port 9: enabled 0
713 12:51:19.886280 USB3 port 0: enabled 0
714 12:51:19.886365 USB3 port 1: enabled 1
715 12:51:19.889577 USB3 port 2: enabled 0
716 12:51:19.892807 USB3 port 3: enabled 0
717 12:51:19.892892 GENERIC: 0.0: enabled 1
718 12:51:19.896394 GENERIC: 1.0: enabled 1
719 12:51:19.899721 APIC: 01: enabled 1
720 12:51:19.899807 APIC: 03: enabled 1
721 12:51:19.903190 APIC: 07: enabled 1
722 12:51:19.906327 APIC: 05: enabled 1
723 12:51:19.906415 APIC: 04: enabled 1
724 12:51:19.909869 APIC: 02: enabled 1
725 12:51:19.909959 APIC: 06: enabled 1
726 12:51:19.913061 Compare with tree...
727 12:51:19.916021 Root Device: enabled 1
728 12:51:19.919491 DOMAIN: 0000: enabled 1
729 12:51:19.919605 PCI: 00:00.0: enabled 1
730 12:51:19.922934 PCI: 00:02.0: enabled 1
731 12:51:19.926399 PCI: 00:04.0: enabled 1
732 12:51:19.929741 GENERIC: 0.0: enabled 1
733 12:51:19.932748 PCI: 00:05.0: enabled 1
734 12:51:19.932840 PCI: 00:06.0: enabled 0
735 12:51:19.935952 PCI: 00:07.0: enabled 0
736 12:51:19.939463 GENERIC: 0.0: enabled 1
737 12:51:19.942981 PCI: 00:07.1: enabled 0
738 12:51:19.946073 GENERIC: 1.0: enabled 1
739 12:51:19.946166 PCI: 00:07.2: enabled 0
740 12:51:19.949477 GENERIC: 0.0: enabled 1
741 12:51:19.952609 PCI: 00:07.3: enabled 0
742 12:51:19.956132 GENERIC: 1.0: enabled 1
743 12:51:19.959546 PCI: 00:08.0: enabled 1
744 12:51:19.959677 PCI: 00:09.0: enabled 0
745 12:51:19.962751 PCI: 00:0a.0: enabled 0
746 12:51:19.966153 PCI: 00:0d.0: enabled 1
747 12:51:19.969304 USB0 port 0: enabled 1
748 12:51:19.972856 USB3 port 0: enabled 1
749 12:51:19.972954 USB3 port 1: enabled 1
750 12:51:19.976147 USB3 port 2: enabled 0
751 12:51:19.979381 USB3 port 3: enabled 0
752 12:51:19.982654 PCI: 00:0d.1: enabled 0
753 12:51:19.985868 PCI: 00:0d.2: enabled 0
754 12:51:19.985955 GENERIC: 0.0: enabled 1
755 12:51:19.989178 PCI: 00:0d.3: enabled 0
756 12:51:19.992620 PCI: 00:0e.0: enabled 0
757 12:51:19.995974 PCI: 00:10.2: enabled 1
758 12:51:19.999408 PCI: 00:10.6: enabled 0
759 12:51:19.999497 PCI: 00:10.7: enabled 0
760 12:51:20.002582 PCI: 00:12.0: enabled 0
761 12:51:20.005834 PCI: 00:12.6: enabled 0
762 12:51:20.009117 PCI: 00:13.0: enabled 0
763 12:51:20.012520 PCI: 00:14.0: enabled 1
764 12:51:20.012611 USB0 port 0: enabled 1
765 12:51:20.015903 USB2 port 0: enabled 0
766 12:51:20.019158 USB2 port 1: enabled 1
767 12:51:20.022831 USB2 port 2: enabled 1
768 12:51:20.025841 USB2 port 3: enabled 0
769 12:51:20.029094 USB2 port 4: enabled 1
770 12:51:20.029182 USB2 port 5: enabled 0
771 12:51:20.032904 USB2 port 6: enabled 0
772 12:51:20.036008 USB2 port 7: enabled 0
773 12:51:20.039143 USB2 port 8: enabled 0
774 12:51:20.042628 USB2 port 9: enabled 0
775 12:51:20.042717 USB3 port 0: enabled 0
776 12:51:20.045967 USB3 port 1: enabled 1
777 12:51:20.049200 USB3 port 2: enabled 0
778 12:51:20.052370 USB3 port 3: enabled 0
779 12:51:20.056063 PCI: 00:14.1: enabled 0
780 12:51:20.056150 PCI: 00:14.2: enabled 1
781 12:51:20.059158 PCI: 00:14.3: enabled 1
782 12:51:20.062662 GENERIC: 0.0: enabled 1
783 12:51:20.066017 PCI: 00:15.0: enabled 1
784 12:51:20.069153 I2C: 00:1a: enabled 1
785 12:51:20.069240 I2C: 00:31: enabled 1
786 12:51:20.072623 I2C: 00:32: enabled 1
787 12:51:20.075687 PCI: 00:15.1: enabled 1
788 12:51:20.079165 I2C: 00:10: enabled 1
789 12:51:20.082586 PCI: 00:15.2: enabled 1
790 12:51:20.082675 PCI: 00:15.3: enabled 1
791 12:51:20.085553 PCI: 00:16.0: enabled 1
792 12:51:20.089303 PCI: 00:16.1: enabled 0
793 12:51:20.093159 PCI: 00:16.2: enabled 0
794 12:51:20.093249 PCI: 00:16.3: enabled 0
795 12:51:20.097272 PCI: 00:16.4: enabled 0
796 12:51:20.100361 PCI: 00:16.5: enabled 0
797 12:51:20.100447 PCI: 00:17.0: enabled 1
798 12:51:20.103715 PCI: 00:19.0: enabled 0
799 12:51:20.107025 PCI: 00:19.1: enabled 1
800 12:51:20.110341 I2C: 00:15: enabled 1
801 12:51:20.113652 PCI: 00:19.2: enabled 0
802 12:51:20.113739 PCI: 00:1d.0: enabled 1
803 12:51:20.116945 GENERIC: 0.0: enabled 1
804 12:51:20.120279 PCI: 00:1e.0: enabled 1
805 12:51:20.123767 PCI: 00:1e.1: enabled 0
806 12:51:20.126868 PCI: 00:1e.2: enabled 1
807 12:51:20.127019 SPI: 00: enabled 1
808 12:51:20.130078 PCI: 00:1e.3: enabled 1
809 12:51:20.133694 SPI: 00: enabled 1
810 12:51:20.136740 PCI: 00:1f.0: enabled 1
811 12:51:20.136827 PNP: 0c09.0: enabled 1
812 12:51:20.188400 PCI: 00:1f.1: enabled 0
813 12:51:20.188572 PCI: 00:1f.2: enabled 1
814 12:51:20.188852 GENERIC: 0.0: enabled 1
815 12:51:20.188923 GENERIC: 0.0: enabled 1
816 12:51:20.189054 GENERIC: 1.0: enabled 1
817 12:51:20.189140 PCI: 00:1f.3: enabled 1
818 12:51:20.189213 PCI: 00:1f.4: enabled 0
819 12:51:20.189284 PCI: 00:1f.5: enabled 1
820 12:51:20.189345 PCI: 00:1f.6: enabled 0
821 12:51:20.190016 PCI: 00:1f.7: enabled 0
822 12:51:20.190148 CPU_CLUSTER: 0: enabled 1
823 12:51:20.190442 APIC: 00: enabled 1
824 12:51:20.190591 APIC: 01: enabled 1
825 12:51:20.190673 APIC: 03: enabled 1
826 12:51:20.190765 APIC: 07: enabled 1
827 12:51:20.190843 APIC: 05: enabled 1
828 12:51:20.190903 APIC: 04: enabled 1
829 12:51:20.190971 APIC: 02: enabled 1
830 12:51:20.191030 APIC: 06: enabled 1
831 12:51:20.191086 Root Device scanning...
832 12:51:20.222266 scan_static_bus for Root Device
833 12:51:20.222445 DOMAIN: 0000 enabled
834 12:51:20.222709 CPU_CLUSTER: 0 enabled
835 12:51:20.222780 DOMAIN: 0000 scanning...
836 12:51:20.222895 PCI: pci_scan_bus for bus 00
837 12:51:20.222959 PCI: 00:00.0 [8086/0000] ops
838 12:51:20.223031 PCI: 00:00.0 [8086/9a12] enabled
839 12:51:20.223095 PCI: 00:02.0 [8086/0000] bus ops
840 12:51:20.223442 PCI: 00:02.0 [8086/9a40] enabled
841 12:51:20.223528 PCI: 00:04.0 [8086/0000] bus ops
842 12:51:20.226257 PCI: 00:04.0 [8086/9a03] enabled
843 12:51:20.226344 PCI: 00:05.0 [8086/9a19] enabled
844 12:51:20.229283 PCI: 00:07.0 [0000/0000] hidden
845 12:51:20.232894 PCI: 00:08.0 [8086/9a11] enabled
846 12:51:20.236338 PCI: 00:0a.0 [8086/9a0d] disabled
847 12:51:20.239439 PCI: 00:0d.0 [8086/0000] bus ops
848 12:51:20.242800 PCI: 00:0d.0 [8086/9a13] enabled
849 12:51:20.246128 PCI: 00:14.0 [8086/0000] bus ops
850 12:51:20.249634 PCI: 00:14.0 [8086/a0ed] enabled
851 12:51:20.252919 PCI: 00:14.2 [8086/a0ef] enabled
852 12:51:20.256303 PCI: 00:14.3 [8086/0000] bus ops
853 12:51:20.259545 PCI: 00:14.3 [8086/a0f0] enabled
854 12:51:20.262835 PCI: 00:15.0 [8086/0000] bus ops
855 12:51:20.266213 PCI: 00:15.0 [8086/a0e8] enabled
856 12:51:20.269796 PCI: 00:15.1 [8086/0000] bus ops
857 12:51:20.273186 PCI: 00:15.1 [8086/a0e9] enabled
858 12:51:20.276486 PCI: 00:15.2 [8086/0000] bus ops
859 12:51:20.279458 PCI: 00:15.2 [8086/a0ea] enabled
860 12:51:20.283168 PCI: 00:15.3 [8086/0000] bus ops
861 12:51:20.286200 PCI: 00:15.3 [8086/a0eb] enabled
862 12:51:20.289646 PCI: 00:16.0 [8086/0000] ops
863 12:51:20.292823 PCI: 00:16.0 [8086/a0e0] enabled
864 12:51:20.299668 PCI: Static device PCI: 00:17.0 not found, disabling it.
865 12:51:20.303125 PCI: 00:19.0 [8086/0000] bus ops
866 12:51:20.306231 PCI: 00:19.0 [8086/a0c5] disabled
867 12:51:20.309533 PCI: 00:19.1 [8086/0000] bus ops
868 12:51:20.313396 PCI: 00:19.1 [8086/a0c6] enabled
869 12:51:20.316199 PCI: 00:1d.0 [8086/0000] bus ops
870 12:51:20.319445 PCI: 00:1d.0 [8086/a0b0] enabled
871 12:51:20.323051 PCI: 00:1e.0 [8086/0000] ops
872 12:51:20.326136 PCI: 00:1e.0 [8086/a0a8] enabled
873 12:51:20.329609 PCI: 00:1e.2 [8086/0000] bus ops
874 12:51:20.332801 PCI: 00:1e.2 [8086/a0aa] enabled
875 12:51:20.336234 PCI: 00:1e.3 [8086/0000] bus ops
876 12:51:20.339625 PCI: 00:1e.3 [8086/a0ab] enabled
877 12:51:20.342776 PCI: 00:1f.0 [8086/0000] bus ops
878 12:51:20.346090 PCI: 00:1f.0 [8086/a087] enabled
879 12:51:20.346190 RTC Init
880 12:51:20.349706 Set power on after power failure.
881 12:51:20.352674 Disabling Deep S3
882 12:51:20.352773 Disabling Deep S3
883 12:51:20.356159 Disabling Deep S4
884 12:51:20.356248 Disabling Deep S4
885 12:51:20.359521 Disabling Deep S5
886 12:51:20.359610 Disabling Deep S5
887 12:51:20.362809 PCI: 00:1f.2 [0000/0000] hidden
888 12:51:20.366110 PCI: 00:1f.3 [8086/0000] bus ops
889 12:51:20.369452 PCI: 00:1f.3 [8086/a0c8] enabled
890 12:51:20.372799 PCI: 00:1f.5 [8086/0000] bus ops
891 12:51:20.376171 PCI: 00:1f.5 [8086/a0a4] enabled
892 12:51:20.379564 PCI: Leftover static devices:
893 12:51:20.383255 PCI: 00:10.2
894 12:51:20.383338 PCI: 00:10.6
895 12:51:20.383403 PCI: 00:10.7
896 12:51:20.386168 PCI: 00:06.0
897 12:51:20.386252 PCI: 00:07.1
898 12:51:20.389756 PCI: 00:07.2
899 12:51:20.389841 PCI: 00:07.3
900 12:51:20.392818 PCI: 00:09.0
901 12:51:20.392902 PCI: 00:0d.1
902 12:51:20.393012 PCI: 00:0d.2
903 12:51:20.396336 PCI: 00:0d.3
904 12:51:20.396429 PCI: 00:0e.0
905 12:51:20.399625 PCI: 00:12.0
906 12:51:20.399710 PCI: 00:12.6
907 12:51:20.399808 PCI: 00:13.0
908 12:51:20.403344 PCI: 00:14.1
909 12:51:20.403428 PCI: 00:16.1
910 12:51:20.406259 PCI: 00:16.2
911 12:51:20.406343 PCI: 00:16.3
912 12:51:20.406409 PCI: 00:16.4
913 12:51:20.409514 PCI: 00:16.5
914 12:51:20.409600 PCI: 00:17.0
915 12:51:20.413467 PCI: 00:19.2
916 12:51:20.413555 PCI: 00:1e.1
917 12:51:20.413622 PCI: 00:1f.1
918 12:51:20.416635 PCI: 00:1f.4
919 12:51:20.416719 PCI: 00:1f.6
920 12:51:20.419766 PCI: 00:1f.7
921 12:51:20.423110 PCI: Check your devicetree.cb.
922 12:51:20.423199 PCI: 00:02.0 scanning...
923 12:51:20.429408 scan_generic_bus for PCI: 00:02.0
924 12:51:20.433291 scan_generic_bus for PCI: 00:02.0 done
925 12:51:20.436627 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
926 12:51:20.439773 PCI: 00:04.0 scanning...
927 12:51:20.442969 scan_generic_bus for PCI: 00:04.0
928 12:51:20.446534 GENERIC: 0.0 enabled
929 12:51:20.450128 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
930 12:51:20.456492 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
931 12:51:20.459669 PCI: 00:0d.0 scanning...
932 12:51:20.463143 scan_static_bus for PCI: 00:0d.0
933 12:51:20.463230 USB0 port 0 enabled
934 12:51:20.467115 USB0 port 0 scanning...
935 12:51:20.469817 scan_static_bus for USB0 port 0
936 12:51:20.472915 USB3 port 0 enabled
937 12:51:20.473040 USB3 port 1 enabled
938 12:51:20.476600 USB3 port 2 disabled
939 12:51:20.479644 USB3 port 3 disabled
940 12:51:20.479733 USB3 port 0 scanning...
941 12:51:20.483425 scan_static_bus for USB3 port 0
942 12:51:20.486377 scan_static_bus for USB3 port 0 done
943 12:51:20.493306 scan_bus: bus USB3 port 0 finished in 6 msecs
944 12:51:20.496342 USB3 port 1 scanning...
945 12:51:20.499910 scan_static_bus for USB3 port 1
946 12:51:20.503079 scan_static_bus for USB3 port 1 done
947 12:51:20.506358 scan_bus: bus USB3 port 1 finished in 6 msecs
948 12:51:20.509512 scan_static_bus for USB0 port 0 done
949 12:51:20.516221 scan_bus: bus USB0 port 0 finished in 43 msecs
950 12:51:20.519648 scan_static_bus for PCI: 00:0d.0 done
951 12:51:20.522856 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
952 12:51:20.526317 PCI: 00:14.0 scanning...
953 12:51:20.529799 scan_static_bus for PCI: 00:14.0
954 12:51:20.532700 USB0 port 0 enabled
955 12:51:20.532792 USB0 port 0 scanning...
956 12:51:20.536279 scan_static_bus for USB0 port 0
957 12:51:20.539938 USB2 port 0 disabled
958 12:51:20.543155 USB2 port 1 enabled
959 12:51:20.543246 USB2 port 2 enabled
960 12:51:20.546362 USB2 port 3 disabled
961 12:51:20.549475 USB2 port 4 enabled
962 12:51:20.549567 USB2 port 5 disabled
963 12:51:20.552892 USB2 port 6 disabled
964 12:51:20.556216 USB2 port 7 disabled
965 12:51:20.556316 USB2 port 8 disabled
966 12:51:20.559608 USB2 port 9 disabled
967 12:51:20.559703 USB3 port 0 disabled
968 12:51:20.562833 USB3 port 1 enabled
969 12:51:20.566858 USB3 port 2 disabled
970 12:51:20.566961 USB3 port 3 disabled
971 12:51:20.569651 USB2 port 1 scanning...
972 12:51:20.572901 scan_static_bus for USB2 port 1
973 12:51:20.576038 scan_static_bus for USB2 port 1 done
974 12:51:20.582734 scan_bus: bus USB2 port 1 finished in 6 msecs
975 12:51:20.582870 USB2 port 2 scanning...
976 12:51:20.586259 scan_static_bus for USB2 port 2
977 12:51:20.592856 scan_static_bus for USB2 port 2 done
978 12:51:20.596019 scan_bus: bus USB2 port 2 finished in 6 msecs
979 12:51:20.599434 USB2 port 4 scanning...
980 12:51:20.602588 scan_static_bus for USB2 port 4
981 12:51:20.606321 scan_static_bus for USB2 port 4 done
982 12:51:20.609477 scan_bus: bus USB2 port 4 finished in 6 msecs
983 12:51:20.613117 USB3 port 1 scanning...
984 12:51:20.616186 scan_static_bus for USB3 port 1
985 12:51:20.619722 scan_static_bus for USB3 port 1 done
986 12:51:20.622933 scan_bus: bus USB3 port 1 finished in 6 msecs
987 12:51:20.629415 scan_static_bus for USB0 port 0 done
988 12:51:20.633283 scan_bus: bus USB0 port 0 finished in 93 msecs
989 12:51:20.636323 scan_static_bus for PCI: 00:14.0 done
990 12:51:20.643146 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
991 12:51:20.643282 PCI: 00:14.3 scanning...
992 12:51:20.646321 scan_static_bus for PCI: 00:14.3
993 12:51:20.649485 GENERIC: 0.0 enabled
994 12:51:20.652652 scan_static_bus for PCI: 00:14.3 done
995 12:51:20.659504 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
996 12:51:20.659605 PCI: 00:15.0 scanning...
997 12:51:20.662614 scan_static_bus for PCI: 00:15.0
998 12:51:20.665974 I2C: 00:1a enabled
999 12:51:20.670160 I2C: 00:31 enabled
1000 12:51:20.670247 I2C: 00:32 enabled
1001 12:51:20.673666 scan_static_bus for PCI: 00:15.0 done
1002 12:51:20.680366 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1003 12:51:20.680454 PCI: 00:15.1 scanning...
1004 12:51:20.683469 scan_static_bus for PCI: 00:15.1
1005 12:51:20.687029 I2C: 00:10 enabled
1006 12:51:20.690493 scan_static_bus for PCI: 00:15.1 done
1007 12:51:20.693744 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1008 12:51:20.696866 PCI: 00:15.2 scanning...
1009 12:51:20.700380 scan_static_bus for PCI: 00:15.2
1010 12:51:20.703415 scan_static_bus for PCI: 00:15.2 done
1011 12:51:20.710135 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1012 12:51:20.713467 PCI: 00:15.3 scanning...
1013 12:51:20.717211 scan_static_bus for PCI: 00:15.3
1014 12:51:20.720757 scan_static_bus for PCI: 00:15.3 done
1015 12:51:20.723776 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1016 12:51:20.727148 PCI: 00:19.1 scanning...
1017 12:51:20.730274 scan_static_bus for PCI: 00:19.1
1018 12:51:20.733960 I2C: 00:15 enabled
1019 12:51:20.737072 scan_static_bus for PCI: 00:19.1 done
1020 12:51:20.740173 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1021 12:51:20.743578 PCI: 00:1d.0 scanning...
1022 12:51:20.746901 do_pci_scan_bridge for PCI: 00:1d.0
1023 12:51:20.750435 PCI: pci_scan_bus for bus 01
1024 12:51:20.753616 PCI: 01:00.0 [1c5c/174a] enabled
1025 12:51:20.757067 GENERIC: 0.0 enabled
1026 12:51:20.760473 Enabling Common Clock Configuration
1027 12:51:20.763903 L1 Sub-State supported from root port 29
1028 12:51:20.767075 L1 Sub-State Support = 0xf
1029 12:51:20.770144 CommonModeRestoreTime = 0x28
1030 12:51:20.773483 Power On Value = 0x16, Power On Scale = 0x0
1031 12:51:20.776895 ASPM: Enabled L1
1032 12:51:20.780297 PCIe: Max_Payload_Size adjusted to 128
1033 12:51:20.783457 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1034 12:51:20.787278 PCI: 00:1e.2 scanning...
1035 12:51:20.790723 scan_generic_bus for PCI: 00:1e.2
1036 12:51:20.793821 SPI: 00 enabled
1037 12:51:20.796890 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1038 12:51:20.803726 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1039 12:51:20.806833 PCI: 00:1e.3 scanning...
1040 12:51:20.810056 scan_generic_bus for PCI: 00:1e.3
1041 12:51:20.810143 SPI: 00 enabled
1042 12:51:20.816902 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1043 12:51:20.823583 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1044 12:51:20.823673 PCI: 00:1f.0 scanning...
1045 12:51:20.826927 scan_static_bus for PCI: 00:1f.0
1046 12:51:20.830216 PNP: 0c09.0 enabled
1047 12:51:20.833448 PNP: 0c09.0 scanning...
1048 12:51:20.836904 scan_static_bus for PNP: 0c09.0
1049 12:51:20.840196 scan_static_bus for PNP: 0c09.0 done
1050 12:51:20.843361 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1051 12:51:20.846975 scan_static_bus for PCI: 00:1f.0 done
1052 12:51:20.853399 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1053 12:51:20.856568 PCI: 00:1f.2 scanning...
1054 12:51:20.860155 scan_static_bus for PCI: 00:1f.2
1055 12:51:20.860245 GENERIC: 0.0 enabled
1056 12:51:20.863325 GENERIC: 0.0 scanning...
1057 12:51:20.866837 scan_static_bus for GENERIC: 0.0
1058 12:51:20.869996 GENERIC: 0.0 enabled
1059 12:51:20.870083 GENERIC: 1.0 enabled
1060 12:51:20.877085 scan_static_bus for GENERIC: 0.0 done
1061 12:51:20.880345 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1062 12:51:20.883568 scan_static_bus for PCI: 00:1f.2 done
1063 12:51:20.890095 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1064 12:51:20.890186 PCI: 00:1f.3 scanning...
1065 12:51:20.893390 scan_static_bus for PCI: 00:1f.3
1066 12:51:20.900031 scan_static_bus for PCI: 00:1f.3 done
1067 12:51:20.903524 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1068 12:51:20.906936 PCI: 00:1f.5 scanning...
1069 12:51:20.910126 scan_generic_bus for PCI: 00:1f.5
1070 12:51:20.913704 scan_generic_bus for PCI: 00:1f.5 done
1071 12:51:20.917098 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1072 12:51:20.923710 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1073 12:51:20.927146 scan_static_bus for Root Device done
1074 12:51:20.930343 scan_bus: bus Root Device finished in 737 msecs
1075 12:51:20.933802 done
1076 12:51:20.936965 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1077 12:51:20.940420 Chrome EC: UHEPI supported
1078 12:51:20.947022 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1079 12:51:20.953936 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1080 12:51:20.957102 SPI flash protection: WPSW=0 SRP0=0
1081 12:51:20.963855 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1082 12:51:20.967120 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1083 12:51:20.970466 found VGA at PCI: 00:02.0
1084 12:51:20.973904 Setting up VGA for PCI: 00:02.0
1085 12:51:20.980402 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1086 12:51:20.983858 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1087 12:51:20.987273 Allocating resources...
1088 12:51:20.987358 Reading resources...
1089 12:51:20.993878 Root Device read_resources bus 0 link: 0
1090 12:51:20.997136 DOMAIN: 0000 read_resources bus 0 link: 0
1091 12:51:21.003464 PCI: 00:04.0 read_resources bus 1 link: 0
1092 12:51:21.007332 PCI: 00:04.0 read_resources bus 1 link: 0 done
1093 12:51:21.013701 PCI: 00:0d.0 read_resources bus 0 link: 0
1094 12:51:21.017243 USB0 port 0 read_resources bus 0 link: 0
1095 12:51:21.020468 USB0 port 0 read_resources bus 0 link: 0 done
1096 12:51:21.027423 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1097 12:51:21.030891 PCI: 00:14.0 read_resources bus 0 link: 0
1098 12:51:21.037454 USB0 port 0 read_resources bus 0 link: 0
1099 12:51:21.040648 USB0 port 0 read_resources bus 0 link: 0 done
1100 12:51:21.047331 PCI: 00:14.0 read_resources bus 0 link: 0 done
1101 12:51:21.050615 PCI: 00:14.3 read_resources bus 0 link: 0
1102 12:51:21.057190 PCI: 00:14.3 read_resources bus 0 link: 0 done
1103 12:51:21.060547 PCI: 00:15.0 read_resources bus 0 link: 0
1104 12:51:21.067134 PCI: 00:15.0 read_resources bus 0 link: 0 done
1105 12:51:21.070522 PCI: 00:15.1 read_resources bus 0 link: 0
1106 12:51:21.077135 PCI: 00:15.1 read_resources bus 0 link: 0 done
1107 12:51:21.080671 PCI: 00:19.1 read_resources bus 0 link: 0
1108 12:51:21.087642 PCI: 00:19.1 read_resources bus 0 link: 0 done
1109 12:51:21.090983 PCI: 00:1d.0 read_resources bus 1 link: 0
1110 12:51:21.097515 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1111 12:51:21.100910 PCI: 00:1e.2 read_resources bus 2 link: 0
1112 12:51:21.107502 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1113 12:51:21.110971 PCI: 00:1e.3 read_resources bus 3 link: 0
1114 12:51:21.117577 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1115 12:51:21.120625 PCI: 00:1f.0 read_resources bus 0 link: 0
1116 12:51:21.127486 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1117 12:51:21.131432 PCI: 00:1f.2 read_resources bus 0 link: 0
1118 12:51:21.134114 GENERIC: 0.0 read_resources bus 0 link: 0
1119 12:51:21.140882 GENERIC: 0.0 read_resources bus 0 link: 0 done
1120 12:51:21.144541 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1121 12:51:21.151403 DOMAIN: 0000 read_resources bus 0 link: 0 done
1122 12:51:21.155093 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1123 12:51:21.161802 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1124 12:51:21.165309 Root Device read_resources bus 0 link: 0 done
1125 12:51:21.168341 Done reading resources.
1126 12:51:21.174917 Show resources in subtree (Root Device)...After reading.
1127 12:51:21.178123 Root Device child on link 0 DOMAIN: 0000
1128 12:51:21.181364 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1129 12:51:21.191809 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1130 12:51:21.201587 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1131 12:51:21.204771 PCI: 00:00.0
1132 12:51:21.211580 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1133 12:51:21.221804 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1134 12:51:21.231564 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1135 12:51:21.241881 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1136 12:51:21.251681 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1137 12:51:21.258172 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1138 12:51:21.268458 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1139 12:51:21.278729 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1140 12:51:21.288547 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1141 12:51:21.298162 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1142 12:51:21.308208 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1143 12:51:21.314744 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1144 12:51:21.324888 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1145 12:51:21.334949 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1146 12:51:21.344683 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1147 12:51:21.354762 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1148 12:51:21.364808 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1149 12:51:21.371668 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1150 12:51:21.381658 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1151 12:51:21.391668 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1152 12:51:21.394776 PCI: 00:02.0
1153 12:51:21.404953 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 12:51:21.414960 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1155 12:51:21.421448 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1156 12:51:21.428076 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1157 12:51:21.438336 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1158 12:51:21.438428 GENERIC: 0.0
1159 12:51:21.441489 PCI: 00:05.0
1160 12:51:21.451335 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1161 12:51:21.454782 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1162 12:51:21.457912 GENERIC: 0.0
1163 12:51:21.458011 PCI: 00:08.0
1164 12:51:21.468334 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1165 12:51:21.471557 PCI: 00:0a.0
1166 12:51:21.474688 PCI: 00:0d.0 child on link 0 USB0 port 0
1167 12:51:21.484714 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 12:51:21.488073 USB0 port 0 child on link 0 USB3 port 0
1169 12:51:21.491514 USB3 port 0
1170 12:51:21.491598 USB3 port 1
1171 12:51:21.494726 USB3 port 2
1172 12:51:21.494810 USB3 port 3
1173 12:51:21.501572 PCI: 00:14.0 child on link 0 USB0 port 0
1174 12:51:21.511536 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1175 12:51:21.515205 USB0 port 0 child on link 0 USB2 port 0
1176 12:51:21.518373 USB2 port 0
1177 12:51:21.518478 USB2 port 1
1178 12:51:21.521807 USB2 port 2
1179 12:51:21.521922 USB2 port 3
1180 12:51:21.525076 USB2 port 4
1181 12:51:21.525183 USB2 port 5
1182 12:51:21.528034 USB2 port 6
1183 12:51:21.528137 USB2 port 7
1184 12:51:21.531420 USB2 port 8
1185 12:51:21.531524 USB2 port 9
1186 12:51:21.534785 USB3 port 0
1187 12:51:21.534884 USB3 port 1
1188 12:51:21.538258 USB3 port 2
1189 12:51:21.538383 USB3 port 3
1190 12:51:21.541718 PCI: 00:14.2
1191 12:51:21.551396 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1192 12:51:21.561665 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1193 12:51:21.564825 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1194 12:51:21.574863 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1195 12:51:21.577970 GENERIC: 0.0
1196 12:51:21.581211 PCI: 00:15.0 child on link 0 I2C: 00:1a
1197 12:51:21.591409 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1198 12:51:21.594816 I2C: 00:1a
1199 12:51:21.594901 I2C: 00:31
1200 12:51:21.594986 I2C: 00:32
1201 12:51:21.601238 PCI: 00:15.1 child on link 0 I2C: 00:10
1202 12:51:21.611206 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 12:51:21.611293 I2C: 00:10
1204 12:51:21.614505 PCI: 00:15.2
1205 12:51:21.624414 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 12:51:21.624501 PCI: 00:15.3
1207 12:51:21.634486 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1208 12:51:21.638168 PCI: 00:16.0
1209 12:51:21.647717 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1210 12:51:21.647815 PCI: 00:19.0
1211 12:51:21.654558 PCI: 00:19.1 child on link 0 I2C: 00:15
1212 12:51:21.664580 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1213 12:51:21.664665 I2C: 00:15
1214 12:51:21.667843 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1215 12:51:21.677837 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1216 12:51:21.687535 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1217 12:51:21.697428 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1218 12:51:21.697514 GENERIC: 0.0
1219 12:51:21.700841 PCI: 01:00.0
1220 12:51:21.711035 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1221 12:51:21.720892 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1222 12:51:21.727546 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1223 12:51:21.730472 PCI: 00:1e.0
1224 12:51:21.740829 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1225 12:51:21.743998 PCI: 00:1e.2 child on link 0 SPI: 00
1226 12:51:21.753871 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1227 12:51:21.757268 SPI: 00
1228 12:51:21.760806 PCI: 00:1e.3 child on link 0 SPI: 00
1229 12:51:21.770777 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 12:51:21.770863 SPI: 00
1231 12:51:21.777509 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1232 12:51:21.783741 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1233 12:51:21.787222 PNP: 0c09.0
1234 12:51:21.793764 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1235 12:51:21.800504 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1236 12:51:21.810400 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1237 12:51:21.817283 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1238 12:51:21.823629 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1239 12:51:21.823729 GENERIC: 0.0
1240 12:51:21.826954 GENERIC: 1.0
1241 12:51:21.827071 PCI: 00:1f.3
1242 12:51:21.836881 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1243 12:51:21.847260 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1244 12:51:21.850949 PCI: 00:1f.5
1245 12:51:21.860309 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1246 12:51:21.864226 CPU_CLUSTER: 0 child on link 0 APIC: 00
1247 12:51:21.864320 APIC: 00
1248 12:51:21.867037 APIC: 01
1249 12:51:21.867125 APIC: 03
1250 12:51:21.867210 APIC: 07
1251 12:51:21.870375 APIC: 05
1252 12:51:21.870464 APIC: 04
1253 12:51:21.873791 APIC: 02
1254 12:51:21.873874 APIC: 06
1255 12:51:21.880526 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1256 12:51:21.887141 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1257 12:51:21.893909 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1258 12:51:21.900561 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1259 12:51:21.903737 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1260 12:51:21.907167 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1261 12:51:21.910367 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1262 12:51:21.920642 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1263 12:51:21.927002 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1264 12:51:21.933802 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1265 12:51:21.940502 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1266 12:51:21.947097 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1267 12:51:21.953531 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1268 12:51:21.963645 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1269 12:51:21.970250 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1270 12:51:21.973735 DOMAIN: 0000: Resource ranges:
1271 12:51:21.977336 * Base: 1000, Size: 800, Tag: 100
1272 12:51:21.980241 * Base: 1900, Size: e700, Tag: 100
1273 12:51:21.986978 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1274 12:51:21.993549 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1275 12:51:22.000356 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1276 12:51:22.007024 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1277 12:51:22.014074 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1278 12:51:22.023427 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1279 12:51:22.030276 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1280 12:51:22.036794 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1281 12:51:22.046748 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1282 12:51:22.053193 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1283 12:51:22.060253 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1284 12:51:22.070491 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1285 12:51:22.076903 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1286 12:51:22.083342 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1287 12:51:22.093159 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1288 12:51:22.099895 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1289 12:51:22.106630 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1290 12:51:22.116651 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1291 12:51:22.123137 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1292 12:51:22.129987 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1293 12:51:22.140183 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1294 12:51:22.147097 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1295 12:51:22.153398 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1296 12:51:22.160371 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1297 12:51:22.169941 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1298 12:51:22.173312 DOMAIN: 0000: Resource ranges:
1299 12:51:22.176556 * Base: 7fc00000, Size: 40400000, Tag: 200
1300 12:51:22.179908 * Base: d0000000, Size: 28000000, Tag: 200
1301 12:51:22.186465 * Base: fa000000, Size: 1000000, Tag: 200
1302 12:51:22.189660 * Base: fb001000, Size: 2fff000, Tag: 200
1303 12:51:22.193370 * Base: fe010000, Size: 2e000, Tag: 200
1304 12:51:22.199836 * Base: fe03f000, Size: d41000, Tag: 200
1305 12:51:22.203034 * Base: fed88000, Size: 8000, Tag: 200
1306 12:51:22.206216 * Base: fed93000, Size: d000, Tag: 200
1307 12:51:22.210146 * Base: feda2000, Size: 1e000, Tag: 200
1308 12:51:22.213267 * Base: fede0000, Size: 1220000, Tag: 200
1309 12:51:22.220002 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1310 12:51:22.226464 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1311 12:51:22.232792 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1312 12:51:22.239917 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1313 12:51:22.246305 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1314 12:51:22.253160 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1315 12:51:22.259687 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1316 12:51:22.266159 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1317 12:51:22.272802 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1318 12:51:22.279542 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1319 12:51:22.286486 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1320 12:51:22.292891 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1321 12:51:22.299438 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1322 12:51:22.306323 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1323 12:51:22.312792 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1324 12:51:22.319627 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1325 12:51:22.326459 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1326 12:51:22.332789 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1327 12:51:22.339539 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1328 12:51:22.346271 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1329 12:51:22.353127 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1330 12:51:22.359729 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1331 12:51:22.366360 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1332 12:51:22.372894 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1333 12:51:22.379525 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1334 12:51:22.382952 PCI: 00:1d.0: Resource ranges:
1335 12:51:22.389517 * Base: 7fc00000, Size: 100000, Tag: 200
1336 12:51:22.396524 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1337 12:51:22.402827 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1338 12:51:22.409809 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1339 12:51:22.416359 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1340 12:51:22.422729 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1341 12:51:22.429483 Root Device assign_resources, bus 0 link: 0
1342 12:51:22.432885 DOMAIN: 0000 assign_resources, bus 0 link: 0
1343 12:51:22.442980 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1344 12:51:22.449530 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1345 12:51:22.456148 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1346 12:51:22.466549 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1347 12:51:22.469893 PCI: 00:04.0 assign_resources, bus 1 link: 0
1348 12:51:22.476572 PCI: 00:04.0 assign_resources, bus 1 link: 0
1349 12:51:22.483092 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1350 12:51:22.493055 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1351 12:51:22.499848 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1352 12:51:22.503149 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1353 12:51:22.509648 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1354 12:51:22.516503 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1355 12:51:22.522978 PCI: 00:14.0 assign_resources, bus 0 link: 0
1356 12:51:22.526323 PCI: 00:14.0 assign_resources, bus 0 link: 0
1357 12:51:22.536614 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1358 12:51:22.542981 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1359 12:51:22.549494 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1360 12:51:22.556311 PCI: 00:14.3 assign_resources, bus 0 link: 0
1361 12:51:22.559545 PCI: 00:14.3 assign_resources, bus 0 link: 0
1362 12:51:22.569564 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1363 12:51:22.572940 PCI: 00:15.0 assign_resources, bus 0 link: 0
1364 12:51:22.576030 PCI: 00:15.0 assign_resources, bus 0 link: 0
1365 12:51:22.586592 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1366 12:51:22.590044 PCI: 00:15.1 assign_resources, bus 0 link: 0
1367 12:51:22.596539 PCI: 00:15.1 assign_resources, bus 0 link: 0
1368 12:51:22.603479 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1369 12:51:22.613241 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1370 12:51:22.619643 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1371 12:51:22.629594 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1372 12:51:22.633482 PCI: 00:19.1 assign_resources, bus 0 link: 0
1373 12:51:22.636641 PCI: 00:19.1 assign_resources, bus 0 link: 0
1374 12:51:22.646342 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1375 12:51:22.656570 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1376 12:51:22.662978 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1377 12:51:22.669969 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1378 12:51:22.676271 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1379 12:51:22.686422 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1380 12:51:22.693065 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1381 12:51:22.696249 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1382 12:51:22.706453 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1383 12:51:22.709762 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1384 12:51:22.716746 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1385 12:51:22.723335 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1386 12:51:22.726544 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1387 12:51:22.733558 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1388 12:51:22.736990 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1389 12:51:22.743495 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1390 12:51:22.747338 LPC: Trying to open IO window from 800 size 1ff
1391 12:51:22.756834 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1392 12:51:22.763283 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1393 12:51:22.773344 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1394 12:51:22.776529 DOMAIN: 0000 assign_resources, bus 0 link: 0
1395 12:51:22.779804 Root Device assign_resources, bus 0 link: 0
1396 12:51:22.783510 Done setting resources.
1397 12:51:22.789867 Show resources in subtree (Root Device)...After assigning values.
1398 12:51:22.793545 Root Device child on link 0 DOMAIN: 0000
1399 12:51:22.800389 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1400 12:51:22.806467 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1401 12:51:22.816552 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1402 12:51:22.819628 PCI: 00:00.0
1403 12:51:22.829897 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1404 12:51:22.840159 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1405 12:51:22.846716 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1406 12:51:22.856598 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1407 12:51:22.866946 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1408 12:51:22.876685 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1409 12:51:22.886478 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1410 12:51:22.896570 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1411 12:51:22.903346 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1412 12:51:22.913397 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1413 12:51:22.923163 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1414 12:51:22.933206 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1415 12:51:22.943293 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1416 12:51:22.949682 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1417 12:51:22.959604 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1418 12:51:22.969823 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1419 12:51:22.979609 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1420 12:51:22.989720 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1421 12:51:22.996740 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1422 12:51:23.006578 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1423 12:51:23.010077 PCI: 00:02.0
1424 12:51:23.019817 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1425 12:51:23.029689 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1426 12:51:23.039832 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1427 12:51:23.043243 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1428 12:51:23.056352 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1429 12:51:23.056482 GENERIC: 0.0
1430 12:51:23.059620 PCI: 00:05.0
1431 12:51:23.069455 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1432 12:51:23.073129 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1433 12:51:23.076488 GENERIC: 0.0
1434 12:51:23.076572 PCI: 00:08.0
1435 12:51:23.086628 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1436 12:51:23.090039 PCI: 00:0a.0
1437 12:51:23.093471 PCI: 00:0d.0 child on link 0 USB0 port 0
1438 12:51:23.103494 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1439 12:51:23.109876 USB0 port 0 child on link 0 USB3 port 0
1440 12:51:23.109991 USB3 port 0
1441 12:51:23.113304 USB3 port 1
1442 12:51:23.113387 USB3 port 2
1443 12:51:23.116689 USB3 port 3
1444 12:51:23.120096 PCI: 00:14.0 child on link 0 USB0 port 0
1445 12:51:23.129934 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1446 12:51:23.133132 USB0 port 0 child on link 0 USB2 port 0
1447 12:51:23.136501 USB2 port 0
1448 12:51:23.136583 USB2 port 1
1449 12:51:23.139840 USB2 port 2
1450 12:51:23.143319 USB2 port 3
1451 12:51:23.143435 USB2 port 4
1452 12:51:23.146532 USB2 port 5
1453 12:51:23.146660 USB2 port 6
1454 12:51:23.149663 USB2 port 7
1455 12:51:23.149745 USB2 port 8
1456 12:51:23.153193 USB2 port 9
1457 12:51:23.153275 USB3 port 0
1458 12:51:23.156434 USB3 port 1
1459 12:51:23.156517 USB3 port 2
1460 12:51:23.159665 USB3 port 3
1461 12:51:23.159778 PCI: 00:14.2
1462 12:51:23.169793 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1463 12:51:23.182817 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1464 12:51:23.186379 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1465 12:51:23.196273 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1466 12:51:23.199773 GENERIC: 0.0
1467 12:51:23.203163 PCI: 00:15.0 child on link 0 I2C: 00:1a
1468 12:51:23.212969 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1469 12:51:23.213055 I2C: 00:1a
1470 12:51:23.216267 I2C: 00:31
1471 12:51:23.216350 I2C: 00:32
1472 12:51:23.222843 PCI: 00:15.1 child on link 0 I2C: 00:10
1473 12:51:23.232740 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1474 12:51:23.232860 I2C: 00:10
1475 12:51:23.236161 PCI: 00:15.2
1476 12:51:23.246486 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1477 12:51:23.246571 PCI: 00:15.3
1478 12:51:23.256001 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1479 12:51:23.259823 PCI: 00:16.0
1480 12:51:23.269530 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1481 12:51:23.272780 PCI: 00:19.0
1482 12:51:23.276601 PCI: 00:19.1 child on link 0 I2C: 00:15
1483 12:51:23.286468 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1484 12:51:23.286554 I2C: 00:15
1485 12:51:23.292822 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1486 12:51:23.302981 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1487 12:51:23.312796 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1488 12:51:23.322921 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1489 12:51:23.326021 GENERIC: 0.0
1490 12:51:23.326106 PCI: 01:00.0
1491 12:51:23.336248 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1492 12:51:23.349337 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1493 12:51:23.359089 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1494 12:51:23.359178 PCI: 00:1e.0
1495 12:51:23.372839 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1496 12:51:23.375819 PCI: 00:1e.2 child on link 0 SPI: 00
1497 12:51:23.386291 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1498 12:51:23.386377 SPI: 00
1499 12:51:23.389097 PCI: 00:1e.3 child on link 0 SPI: 00
1500 12:51:23.402409 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1501 12:51:23.402512 SPI: 00
1502 12:51:23.405955 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1503 12:51:23.415890 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1504 12:51:23.416005 PNP: 0c09.0
1505 12:51:23.425984 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1506 12:51:23.429293 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1507 12:51:23.439128 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1508 12:51:23.449136 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1509 12:51:23.452369 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1510 12:51:23.456024 GENERIC: 0.0
1511 12:51:23.456107 GENERIC: 1.0
1512 12:51:23.459384 PCI: 00:1f.3
1513 12:51:23.469072 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1514 12:51:23.479185 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1515 12:51:23.482549 PCI: 00:1f.5
1516 12:51:23.492443 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1517 12:51:23.496160 CPU_CLUSTER: 0 child on link 0 APIC: 00
1518 12:51:23.496245 APIC: 00
1519 12:51:23.499548 APIC: 01
1520 12:51:23.499631 APIC: 03
1521 12:51:23.502698 APIC: 07
1522 12:51:23.502782 APIC: 05
1523 12:51:23.502846 APIC: 04
1524 12:51:23.506089 APIC: 02
1525 12:51:23.506173 APIC: 06
1526 12:51:23.509105 Done allocating resources.
1527 12:51:23.516020 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1528 12:51:23.522527 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1529 12:51:23.526084 Configure GPIOs for I2S audio on UP4.
1530 12:51:23.532746 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1531 12:51:23.536072 Enabling resources...
1532 12:51:23.539072 PCI: 00:00.0 subsystem <- 8086/9a12
1533 12:51:23.539175 PCI: 00:00.0 cmd <- 06
1534 12:51:23.545970 PCI: 00:02.0 subsystem <- 8086/9a40
1535 12:51:23.546054 PCI: 00:02.0 cmd <- 03
1536 12:51:23.550057 PCI: 00:04.0 subsystem <- 8086/9a03
1537 12:51:23.552659 PCI: 00:04.0 cmd <- 02
1538 12:51:23.555929 PCI: 00:05.0 subsystem <- 8086/9a19
1539 12:51:23.559334 PCI: 00:05.0 cmd <- 02
1540 12:51:23.562890 PCI: 00:08.0 subsystem <- 8086/9a11
1541 12:51:23.565951 PCI: 00:08.0 cmd <- 06
1542 12:51:23.569326 PCI: 00:0d.0 subsystem <- 8086/9a13
1543 12:51:23.572975 PCI: 00:0d.0 cmd <- 02
1544 12:51:23.576072 PCI: 00:14.0 subsystem <- 8086/a0ed
1545 12:51:23.579388 PCI: 00:14.0 cmd <- 02
1546 12:51:23.582668 PCI: 00:14.2 subsystem <- 8086/a0ef
1547 12:51:23.582767 PCI: 00:14.2 cmd <- 02
1548 12:51:23.589556 PCI: 00:14.3 subsystem <- 8086/a0f0
1549 12:51:23.589642 PCI: 00:14.3 cmd <- 02
1550 12:51:23.592882 PCI: 00:15.0 subsystem <- 8086/a0e8
1551 12:51:23.596407 PCI: 00:15.0 cmd <- 02
1552 12:51:23.599569 PCI: 00:15.1 subsystem <- 8086/a0e9
1553 12:51:23.602824 PCI: 00:15.1 cmd <- 02
1554 12:51:23.606079 PCI: 00:15.2 subsystem <- 8086/a0ea
1555 12:51:23.609918 PCI: 00:15.2 cmd <- 02
1556 12:51:23.612727 PCI: 00:15.3 subsystem <- 8086/a0eb
1557 12:51:23.616250 PCI: 00:15.3 cmd <- 02
1558 12:51:23.619555 PCI: 00:16.0 subsystem <- 8086/a0e0
1559 12:51:23.622759 PCI: 00:16.0 cmd <- 02
1560 12:51:23.626258 PCI: 00:19.1 subsystem <- 8086/a0c6
1561 12:51:23.626342 PCI: 00:19.1 cmd <- 02
1562 12:51:23.630217 PCI: 00:1d.0 bridge ctrl <- 0013
1563 12:51:23.636311 PCI: 00:1d.0 subsystem <- 8086/a0b0
1564 12:51:23.636396 PCI: 00:1d.0 cmd <- 06
1565 12:51:23.639414 PCI: 00:1e.0 subsystem <- 8086/a0a8
1566 12:51:23.643113 PCI: 00:1e.0 cmd <- 06
1567 12:51:23.646144 PCI: 00:1e.2 subsystem <- 8086/a0aa
1568 12:51:23.649541 PCI: 00:1e.2 cmd <- 06
1569 12:51:23.653021 PCI: 00:1e.3 subsystem <- 8086/a0ab
1570 12:51:23.656272 PCI: 00:1e.3 cmd <- 02
1571 12:51:23.659645 PCI: 00:1f.0 subsystem <- 8086/a087
1572 12:51:23.662941 PCI: 00:1f.0 cmd <- 407
1573 12:51:23.666495 PCI: 00:1f.3 subsystem <- 8086/a0c8
1574 12:51:23.669853 PCI: 00:1f.3 cmd <- 02
1575 12:51:23.673051 PCI: 00:1f.5 subsystem <- 8086/a0a4
1576 12:51:23.673135 PCI: 00:1f.5 cmd <- 406
1577 12:51:23.678978 PCI: 01:00.0 cmd <- 02
1578 12:51:23.683603 done.
1579 12:51:23.686760 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1580 12:51:23.690115 Initializing devices...
1581 12:51:23.693469 Root Device init
1582 12:51:23.696726 Chrome EC: Set SMI mask to 0x0000000000000000
1583 12:51:23.703624 Chrome EC: clear events_b mask to 0x0000000000000000
1584 12:51:23.710203 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1585 12:51:23.713672 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1586 12:51:23.720854 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1587 12:51:23.727077 Chrome EC: Set WAKE mask to 0x0000000000000000
1588 12:51:23.730444 fw_config match found: DB_USB=USB3_ACTIVE
1589 12:51:23.737197 Configure Right Type-C port orientation for retimer
1590 12:51:23.740469 Root Device init finished in 44 msecs
1591 12:51:23.743817 PCI: 00:00.0 init
1592 12:51:23.747272 CPU TDP = 9 Watts
1593 12:51:23.747369 CPU PL1 = 9 Watts
1594 12:51:23.750706 CPU PL2 = 40 Watts
1595 12:51:23.753997 CPU PL4 = 83 Watts
1596 12:51:23.757401 PCI: 00:00.0 init finished in 8 msecs
1597 12:51:23.757516 PCI: 00:02.0 init
1598 12:51:23.760940 GMA: Found VBT in CBFS
1599 12:51:23.764049 GMA: Found valid VBT in CBFS
1600 12:51:23.770746 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1601 12:51:23.777370 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1602 12:51:23.780751 PCI: 00:02.0 init finished in 18 msecs
1603 12:51:23.784093 PCI: 00:05.0 init
1604 12:51:23.787527 PCI: 00:05.0 init finished in 0 msecs
1605 12:51:23.790744 PCI: 00:08.0 init
1606 12:51:23.793892 PCI: 00:08.0 init finished in 0 msecs
1607 12:51:23.797388 PCI: 00:14.0 init
1608 12:51:23.800662 PCI: 00:14.0 init finished in 0 msecs
1609 12:51:23.800783 PCI: 00:14.2 init
1610 12:51:23.807264 PCI: 00:14.2 init finished in 0 msecs
1611 12:51:23.807372 PCI: 00:15.0 init
1612 12:51:23.810722 I2C bus 0 version 0x3230302a
1613 12:51:23.814082 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1614 12:51:23.820498 PCI: 00:15.0 init finished in 6 msecs
1615 12:51:23.820613 PCI: 00:15.1 init
1616 12:51:23.823924 I2C bus 1 version 0x3230302a
1617 12:51:23.827307 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1618 12:51:23.830575 PCI: 00:15.1 init finished in 6 msecs
1619 12:51:23.833973 PCI: 00:15.2 init
1620 12:51:23.837514 I2C bus 2 version 0x3230302a
1621 12:51:23.840618 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1622 12:51:23.844004 PCI: 00:15.2 init finished in 6 msecs
1623 12:51:23.847544 PCI: 00:15.3 init
1624 12:51:23.851108 I2C bus 3 version 0x3230302a
1625 12:51:23.854501 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1626 12:51:23.857751 PCI: 00:15.3 init finished in 6 msecs
1627 12:51:23.860500 PCI: 00:16.0 init
1628 12:51:23.864132 PCI: 00:16.0 init finished in 0 msecs
1629 12:51:23.864217 PCI: 00:19.1 init
1630 12:51:23.867430 I2C bus 5 version 0x3230302a
1631 12:51:23.870711 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1632 12:51:23.877476 PCI: 00:19.1 init finished in 6 msecs
1633 12:51:23.877560 PCI: 00:1d.0 init
1634 12:51:23.880963 Initializing PCH PCIe bridge.
1635 12:51:23.884009 PCI: 00:1d.0 init finished in 3 msecs
1636 12:51:23.888179 PCI: 00:1f.0 init
1637 12:51:23.891094 IOAPIC: Initializing IOAPIC at 0xfec00000
1638 12:51:23.898027 IOAPIC: Bootstrap Processor Local APIC = 0x00
1639 12:51:23.898111 IOAPIC: ID = 0x02
1640 12:51:23.901572 IOAPIC: Dumping registers
1641 12:51:23.904651 reg 0x0000: 0x02000000
1642 12:51:23.907848 reg 0x0001: 0x00770020
1643 12:51:23.907932 reg 0x0002: 0x00000000
1644 12:51:23.914781 PCI: 00:1f.0 init finished in 21 msecs
1645 12:51:23.914865 PCI: 00:1f.2 init
1646 12:51:23.917977 Disabling ACPI via APMC.
1647 12:51:23.921526 APMC done.
1648 12:51:23.924582 PCI: 00:1f.2 init finished in 5 msecs
1649 12:51:23.936207 PCI: 01:00.0 init
1650 12:51:23.939634 PCI: 01:00.0 init finished in 0 msecs
1651 12:51:23.943093 PNP: 0c09.0 init
1652 12:51:23.949764 Google Chrome EC uptime: 8.427 seconds
1653 12:51:23.952869 Google Chrome AP resets since EC boot: 1
1654 12:51:23.956251 Google Chrome most recent AP reset causes:
1655 12:51:23.959680 0.349: 32775 shutdown: entering G3
1656 12:51:23.966737 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1657 12:51:23.969879 PNP: 0c09.0 init finished in 23 msecs
1658 12:51:23.975953 Devices initialized
1659 12:51:23.979208 Show all devs... After init.
1660 12:51:23.982470 Root Device: enabled 1
1661 12:51:23.982602 DOMAIN: 0000: enabled 1
1662 12:51:23.985805 CPU_CLUSTER: 0: enabled 1
1663 12:51:23.989155 PCI: 00:00.0: enabled 1
1664 12:51:23.992410 PCI: 00:02.0: enabled 1
1665 12:51:23.992531 PCI: 00:04.0: enabled 1
1666 12:51:23.996136 PCI: 00:05.0: enabled 1
1667 12:51:23.999482 PCI: 00:06.0: enabled 0
1668 12:51:24.002449 PCI: 00:07.0: enabled 0
1669 12:51:24.002585 PCI: 00:07.1: enabled 0
1670 12:51:24.006132 PCI: 00:07.2: enabled 0
1671 12:51:24.009190 PCI: 00:07.3: enabled 0
1672 12:51:24.012435 PCI: 00:08.0: enabled 1
1673 12:51:24.012527 PCI: 00:09.0: enabled 0
1674 12:51:24.015727 PCI: 00:0a.0: enabled 0
1675 12:51:24.019273 PCI: 00:0d.0: enabled 1
1676 12:51:24.019390 PCI: 00:0d.1: enabled 0
1677 12:51:24.022352 PCI: 00:0d.2: enabled 0
1678 12:51:24.025815 PCI: 00:0d.3: enabled 0
1679 12:51:24.029096 PCI: 00:0e.0: enabled 0
1680 12:51:24.029210 PCI: 00:10.2: enabled 1
1681 12:51:24.032638 PCI: 00:10.6: enabled 0
1682 12:51:24.035713 PCI: 00:10.7: enabled 0
1683 12:51:24.039221 PCI: 00:12.0: enabled 0
1684 12:51:24.039307 PCI: 00:12.6: enabled 0
1685 12:51:24.042620 PCI: 00:13.0: enabled 0
1686 12:51:24.046018 PCI: 00:14.0: enabled 1
1687 12:51:24.049124 PCI: 00:14.1: enabled 0
1688 12:51:24.049209 PCI: 00:14.2: enabled 1
1689 12:51:24.052503 PCI: 00:14.3: enabled 1
1690 12:51:24.055947 PCI: 00:15.0: enabled 1
1691 12:51:24.056032 PCI: 00:15.1: enabled 1
1692 12:51:24.059085 PCI: 00:15.2: enabled 1
1693 12:51:24.062521 PCI: 00:15.3: enabled 1
1694 12:51:24.066129 PCI: 00:16.0: enabled 1
1695 12:51:24.066220 PCI: 00:16.1: enabled 0
1696 12:51:24.069451 PCI: 00:16.2: enabled 0
1697 12:51:24.072637 PCI: 00:16.3: enabled 0
1698 12:51:24.075975 PCI: 00:16.4: enabled 0
1699 12:51:24.076061 PCI: 00:16.5: enabled 0
1700 12:51:24.079134 PCI: 00:17.0: enabled 0
1701 12:51:24.082726 PCI: 00:19.0: enabled 0
1702 12:51:24.086095 PCI: 00:19.1: enabled 1
1703 12:51:24.086182 PCI: 00:19.2: enabled 0
1704 12:51:24.089148 PCI: 00:1c.0: enabled 1
1705 12:51:24.092793 PCI: 00:1c.1: enabled 0
1706 12:51:24.092877 PCI: 00:1c.2: enabled 0
1707 12:51:24.095874 PCI: 00:1c.3: enabled 0
1708 12:51:24.099423 PCI: 00:1c.4: enabled 0
1709 12:51:24.102302 PCI: 00:1c.5: enabled 0
1710 12:51:24.102412 PCI: 00:1c.6: enabled 1
1711 12:51:24.105804 PCI: 00:1c.7: enabled 0
1712 12:51:24.109223 PCI: 00:1d.0: enabled 1
1713 12:51:24.112627 PCI: 00:1d.1: enabled 0
1714 12:51:24.112715 PCI: 00:1d.2: enabled 1
1715 12:51:24.115692 PCI: 00:1d.3: enabled 0
1716 12:51:24.118938 PCI: 00:1e.0: enabled 1
1717 12:51:24.122500 PCI: 00:1e.1: enabled 0
1718 12:51:24.122587 PCI: 00:1e.2: enabled 1
1719 12:51:24.125925 PCI: 00:1e.3: enabled 1
1720 12:51:24.129105 PCI: 00:1f.0: enabled 1
1721 12:51:24.129190 PCI: 00:1f.1: enabled 0
1722 12:51:24.132373 PCI: 00:1f.2: enabled 1
1723 12:51:24.135837 PCI: 00:1f.3: enabled 1
1724 12:51:24.139142 PCI: 00:1f.4: enabled 0
1725 12:51:24.139228 PCI: 00:1f.5: enabled 1
1726 12:51:24.142245 PCI: 00:1f.6: enabled 0
1727 12:51:24.145747 PCI: 00:1f.7: enabled 0
1728 12:51:24.145832 APIC: 00: enabled 1
1729 12:51:24.149247 GENERIC: 0.0: enabled 1
1730 12:51:24.152217 GENERIC: 0.0: enabled 1
1731 12:51:24.155909 GENERIC: 1.0: enabled 1
1732 12:51:24.155995 GENERIC: 0.0: enabled 1
1733 12:51:24.159128 GENERIC: 1.0: enabled 1
1734 12:51:24.162323 USB0 port 0: enabled 1
1735 12:51:24.166110 GENERIC: 0.0: enabled 1
1736 12:51:24.166197 USB0 port 0: enabled 1
1737 12:51:24.169186 GENERIC: 0.0: enabled 1
1738 12:51:24.172492 I2C: 00:1a: enabled 1
1739 12:51:24.172578 I2C: 00:31: enabled 1
1740 12:51:24.175791 I2C: 00:32: enabled 1
1741 12:51:24.179022 I2C: 00:10: enabled 1
1742 12:51:24.179107 I2C: 00:15: enabled 1
1743 12:51:24.182616 GENERIC: 0.0: enabled 0
1744 12:51:24.186251 GENERIC: 1.0: enabled 0
1745 12:51:24.188845 GENERIC: 0.0: enabled 1
1746 12:51:24.188937 SPI: 00: enabled 1
1747 12:51:24.192423 SPI: 00: enabled 1
1748 12:51:24.192510 PNP: 0c09.0: enabled 1
1749 12:51:24.195694 GENERIC: 0.0: enabled 1
1750 12:51:24.198981 USB3 port 0: enabled 1
1751 12:51:24.202408 USB3 port 1: enabled 1
1752 12:51:24.202492 USB3 port 2: enabled 0
1753 12:51:24.205749 USB3 port 3: enabled 0
1754 12:51:24.209193 USB2 port 0: enabled 0
1755 12:51:24.209278 USB2 port 1: enabled 1
1756 12:51:24.212199 USB2 port 2: enabled 1
1757 12:51:24.215577 USB2 port 3: enabled 0
1758 12:51:24.219059 USB2 port 4: enabled 1
1759 12:51:24.219148 USB2 port 5: enabled 0
1760 12:51:24.222700 USB2 port 6: enabled 0
1761 12:51:24.225606 USB2 port 7: enabled 0
1762 12:51:24.225691 USB2 port 8: enabled 0
1763 12:51:24.229046 USB2 port 9: enabled 0
1764 12:51:24.232379 USB3 port 0: enabled 0
1765 12:51:24.232465 USB3 port 1: enabled 1
1766 12:51:24.235795 USB3 port 2: enabled 0
1767 12:51:24.238838 USB3 port 3: enabled 0
1768 12:51:24.242320 GENERIC: 0.0: enabled 1
1769 12:51:24.242406 GENERIC: 1.0: enabled 1
1770 12:51:24.245879 APIC: 01: enabled 1
1771 12:51:24.249230 APIC: 03: enabled 1
1772 12:51:24.249316 APIC: 07: enabled 1
1773 12:51:24.252463 APIC: 05: enabled 1
1774 12:51:24.252548 APIC: 04: enabled 1
1775 12:51:24.255888 APIC: 02: enabled 1
1776 12:51:24.258893 APIC: 06: enabled 1
1777 12:51:24.258982 PCI: 01:00.0: enabled 1
1778 12:51:24.265655 BS: BS_DEV_INIT run times (exec / console): 32 / 540 ms
1779 12:51:24.269140 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1780 12:51:24.275649 ELOG: NV offset 0xf30000 size 0x1000
1781 12:51:24.282130 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1782 12:51:24.289276 ELOG: Event(17) added with size 13 at 2023-09-23 12:51:00 UTC
1783 12:51:24.295627 ELOG: Event(92) added with size 9 at 2023-09-23 12:51:00 UTC
1784 12:51:24.302207 ELOG: Event(93) added with size 9 at 2023-09-23 12:51:00 UTC
1785 12:51:24.308832 ELOG: Event(9E) added with size 10 at 2023-09-23 12:51:00 UTC
1786 12:51:24.315686 ELOG: Event(9F) added with size 14 at 2023-09-23 12:51:00 UTC
1787 12:51:24.319130 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1788 12:51:24.326103 ELOG: Event(A1) added with size 10 at 2023-09-23 12:51:00 UTC
1789 12:51:24.332457 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1790 12:51:24.339316 ELOG: Event(A0) added with size 9 at 2023-09-23 12:51:00 UTC
1791 12:51:24.345626 elog_add_boot_reason: Logged dev mode boot
1792 12:51:24.349296 BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms
1793 12:51:24.352521 Finalize devices...
1794 12:51:24.352606 Devices finalized
1795 12:51:24.359204 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1796 12:51:24.365582 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1797 12:51:24.369089 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1798 12:51:24.375519 ME: HFSTS1 : 0x80030055
1799 12:51:24.378828 ME: HFSTS2 : 0x30280116
1800 12:51:24.385796 ME: HFSTS3 : 0x00000050
1801 12:51:24.389075 ME: HFSTS4 : 0x00004000
1802 12:51:24.392073 ME: HFSTS5 : 0x00000000
1803 12:51:24.399023 ME: HFSTS6 : 0x00400006
1804 12:51:24.402165 ME: Manufacturing Mode : YES
1805 12:51:24.405797 ME: SPI Protection Mode Enabled : NO
1806 12:51:24.409055 ME: FW Partition Table : OK
1807 12:51:24.412036 ME: Bringup Loader Failure : NO
1808 12:51:24.415533 ME: Firmware Init Complete : NO
1809 12:51:24.419053 ME: Boot Options Present : NO
1810 12:51:24.422392 ME: Update In Progress : NO
1811 12:51:24.428916 ME: D0i3 Support : YES
1812 12:51:24.432086 ME: Low Power State Enabled : NO
1813 12:51:24.435408 ME: CPU Replaced : YES
1814 12:51:24.438857 ME: CPU Replacement Valid : YES
1815 12:51:24.442288 ME: Current Working State : 5
1816 12:51:24.445358 ME: Current Operation State : 1
1817 12:51:24.448835 ME: Current Operation Mode : 3
1818 12:51:24.452013 ME: Error Code : 0
1819 12:51:24.455417 ME: Enhanced Debug Mode : NO
1820 12:51:24.462347 ME: CPU Debug Disabled : YES
1821 12:51:24.465648 ME: TXT Support : NO
1822 12:51:24.469078 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1823 12:51:24.478960 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1824 12:51:24.482312 CBFS: 'fallback/slic' not found.
1825 12:51:24.485611 ACPI: Writing ACPI tables at 76b01000.
1826 12:51:24.485695 ACPI: * FACS
1827 12:51:24.488866 ACPI: * DSDT
1828 12:51:24.492290 Ramoops buffer: 0x100000@0x76a00000.
1829 12:51:24.495616 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1830 12:51:24.502401 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1831 12:51:24.506143 Google Chrome EC: version:
1832 12:51:24.509201 ro: voema_v2.0.7540-147f8d37d1
1833 12:51:24.512229 rw: voema_v2.0.7540-147f8d37d1
1834 12:51:24.512313 running image: 2
1835 12:51:24.519129 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1836 12:51:24.524129 ACPI: * FADT
1837 12:51:24.524214 SCI is IRQ9
1838 12:51:24.527218 ACPI: added table 1/32, length now 40
1839 12:51:24.530688 ACPI: * SSDT
1840 12:51:24.534108 Found 1 CPU(s) with 8 core(s) each.
1841 12:51:24.540871 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1842 12:51:24.544143 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1843 12:51:24.547175 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1844 12:51:24.550716 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1845 12:51:24.557342 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1846 12:51:24.564197 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1847 12:51:24.567347 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1848 12:51:24.574007 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1849 12:51:24.580695 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1850 12:51:24.583851 \_SB.PCI0.RP09: Added StorageD3Enable property
1851 12:51:24.587144 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1852 12:51:24.594003 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1853 12:51:24.600653 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1854 12:51:24.603971 PS2K: Passing 80 keymaps to kernel
1855 12:51:24.610623 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1856 12:51:24.617559 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1857 12:51:24.620766 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1858 12:51:24.627482 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1859 12:51:24.633989 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1860 12:51:24.640695 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1861 12:51:24.647437 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1862 12:51:24.654210 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1863 12:51:24.657697 ACPI: added table 2/32, length now 44
1864 12:51:24.660499 ACPI: * MCFG
1865 12:51:24.663852 ACPI: added table 3/32, length now 48
1866 12:51:24.667086 ACPI: * TPM2
1867 12:51:24.670606 TPM2 log created at 0x769f0000
1868 12:51:24.673961 ACPI: added table 4/32, length now 52
1869 12:51:24.674046 ACPI: * MADT
1870 12:51:24.677332 SCI is IRQ9
1871 12:51:24.680521 ACPI: added table 5/32, length now 56
1872 12:51:24.680605 current = 76b09850
1873 12:51:24.684102 ACPI: * DMAR
1874 12:51:24.687165 ACPI: added table 6/32, length now 60
1875 12:51:24.690524 ACPI: added table 7/32, length now 64
1876 12:51:24.693963 ACPI: * HPET
1877 12:51:24.697145 ACPI: added table 8/32, length now 68
1878 12:51:24.697228 ACPI: done.
1879 12:51:24.700546 ACPI tables: 35216 bytes.
1880 12:51:24.703826 smbios_write_tables: 769ef000
1881 12:51:24.707080 EC returned error result code 3
1882 12:51:24.710566 Couldn't obtain OEM name from CBI
1883 12:51:24.713792 Create SMBIOS type 16
1884 12:51:24.713874 Create SMBIOS type 17
1885 12:51:24.717284 GENERIC: 0.0 (WIFI Device)
1886 12:51:24.720410 SMBIOS tables: 1750 bytes.
1887 12:51:24.723790 Writing table forward entry at 0x00000500
1888 12:51:24.730282 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1889 12:51:24.733491 Writing coreboot table at 0x76b25000
1890 12:51:24.740251 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1891 12:51:24.743735 1. 0000000000001000-000000000009ffff: RAM
1892 12:51:24.750249 2. 00000000000a0000-00000000000fffff: RESERVED
1893 12:51:24.753778 3. 0000000000100000-00000000769eefff: RAM
1894 12:51:24.760105 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1895 12:51:24.763364 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1896 12:51:24.770439 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1897 12:51:24.776774 7. 0000000077000000-000000007fbfffff: RESERVED
1898 12:51:24.780273 8. 00000000c0000000-00000000cfffffff: RESERVED
1899 12:51:24.783537 9. 00000000f8000000-00000000f9ffffff: RESERVED
1900 12:51:24.790230 10. 00000000fb000000-00000000fb000fff: RESERVED
1901 12:51:24.793328 11. 00000000fe000000-00000000fe00ffff: RESERVED
1902 12:51:24.799871 12. 00000000fed80000-00000000fed87fff: RESERVED
1903 12:51:24.803175 13. 00000000fed90000-00000000fed92fff: RESERVED
1904 12:51:24.810318 14. 00000000feda0000-00000000feda1fff: RESERVED
1905 12:51:24.813320 15. 00000000fedc0000-00000000feddffff: RESERVED
1906 12:51:24.816700 16. 0000000100000000-00000002803fffff: RAM
1907 12:51:24.819878 Passing 4 GPIOs to payload:
1908 12:51:24.826679 NAME | PORT | POLARITY | VALUE
1909 12:51:24.829742 lid | undefined | high | high
1910 12:51:24.836828 power | undefined | high | low
1911 12:51:24.843099 oprom | undefined | high | low
1912 12:51:24.846813 EC in RW | 0x000000e5 | high | high
1913 12:51:24.853274 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum c822
1914 12:51:24.856590 coreboot table: 1576 bytes.
1915 12:51:24.860157 IMD ROOT 0. 0x76fff000 0x00001000
1916 12:51:24.863007 IMD SMALL 1. 0x76ffe000 0x00001000
1917 12:51:24.866463 FSP MEMORY 2. 0x76c4e000 0x003b0000
1918 12:51:24.873204 VPD 3. 0x76c4d000 0x00000367
1919 12:51:24.876402 RO MCACHE 4. 0x76c4c000 0x00000fdc
1920 12:51:24.879685 CONSOLE 5. 0x76c2c000 0x00020000
1921 12:51:24.883058 FMAP 6. 0x76c2b000 0x00000578
1922 12:51:24.886358 TIME STAMP 7. 0x76c2a000 0x00000910
1923 12:51:24.889696 VBOOT WORK 8. 0x76c16000 0x00014000
1924 12:51:24.893166 ROMSTG STCK 9. 0x76c15000 0x00001000
1925 12:51:24.896128 AFTER CAR 10. 0x76c0a000 0x0000b000
1926 12:51:24.899465 RAMSTAGE 11. 0x76b97000 0x00073000
1927 12:51:24.906257 REFCODE 12. 0x76b42000 0x00055000
1928 12:51:24.909751 SMM BACKUP 13. 0x76b32000 0x00010000
1929 12:51:24.913169 4f444749 14. 0x76b30000 0x00002000
1930 12:51:24.916213 EXT VBT15. 0x76b2d000 0x0000219f
1931 12:51:24.919873 COREBOOT 16. 0x76b25000 0x00008000
1932 12:51:24.923213 ACPI 17. 0x76b01000 0x00024000
1933 12:51:24.926230 ACPI GNVS 18. 0x76b00000 0x00001000
1934 12:51:24.929806 RAMOOPS 19. 0x76a00000 0x00100000
1935 12:51:24.933133 TPM2 TCGLOG20. 0x769f0000 0x00010000
1936 12:51:24.939549 SMBIOS 21. 0x769ef000 0x00000800
1937 12:51:24.939634 IMD small region:
1938 12:51:24.943002 IMD ROOT 0. 0x76ffec00 0x00000400
1939 12:51:24.946118 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1940 12:51:24.953104 POWER STATE 2. 0x76ffeb80 0x00000044
1941 12:51:24.956548 ROMSTAGE 3. 0x76ffeb60 0x00000004
1942 12:51:24.959639 MEM INFO 4. 0x76ffe980 0x000001e0
1943 12:51:24.966194 BS: BS_WRITE_TABLES run times (exec / console): 5 / 484 ms
1944 12:51:24.969503 MTRR: Physical address space:
1945 12:51:24.976105 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1946 12:51:24.979529 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1947 12:51:24.986012 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1948 12:51:24.992612 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1949 12:51:24.999581 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1950 12:51:25.006265 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1951 12:51:25.012586 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1952 12:51:25.015938 MTRR: Fixed MSR 0x250 0x0606060606060606
1953 12:51:25.019380 MTRR: Fixed MSR 0x258 0x0606060606060606
1954 12:51:25.025806 MTRR: Fixed MSR 0x259 0x0000000000000000
1955 12:51:25.029487 MTRR: Fixed MSR 0x268 0x0606060606060606
1956 12:51:25.032731 MTRR: Fixed MSR 0x269 0x0606060606060606
1957 12:51:25.036165 MTRR: Fixed MSR 0x26a 0x0606060606060606
1958 12:51:25.039597 MTRR: Fixed MSR 0x26b 0x0606060606060606
1959 12:51:25.046096 MTRR: Fixed MSR 0x26c 0x0606060606060606
1960 12:51:25.049635 MTRR: Fixed MSR 0x26d 0x0606060606060606
1961 12:51:25.052918 MTRR: Fixed MSR 0x26e 0x0606060606060606
1962 12:51:25.055965 MTRR: Fixed MSR 0x26f 0x0606060606060606
1963 12:51:25.060223 call enable_fixed_mtrr()
1964 12:51:25.063750 CPU physical address size: 39 bits
1965 12:51:25.070448 MTRR: default type WB/UC MTRR counts: 6/6.
1966 12:51:25.073482 MTRR: UC selected as default type.
1967 12:51:25.080196 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1968 12:51:25.083725 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1969 12:51:25.090326 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1970 12:51:25.097294 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1971 12:51:25.103604 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1972 12:51:25.110491 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1973 12:51:25.110576
1974 12:51:25.114212 MTRR check
1975 12:51:25.114297 Fixed MTRRs : Enabled
1976 12:51:25.116847 Variable MTRRs: Enabled
1977 12:51:25.116938
1978 12:51:25.120585 MTRR: Fixed MSR 0x250 0x0606060606060606
1979 12:51:25.126985 MTRR: Fixed MSR 0x258 0x0606060606060606
1980 12:51:25.130634 MTRR: Fixed MSR 0x259 0x0000000000000000
1981 12:51:25.134617 MTRR: Fixed MSR 0x268 0x0606060606060606
1982 12:51:25.137244 MTRR: Fixed MSR 0x269 0x0606060606060606
1983 12:51:25.143869 MTRR: Fixed MSR 0x26a 0x0606060606060606
1984 12:51:25.147196 MTRR: Fixed MSR 0x26b 0x0606060606060606
1985 12:51:25.150676 MTRR: Fixed MSR 0x26c 0x0606060606060606
1986 12:51:25.153990 MTRR: Fixed MSR 0x26d 0x0606060606060606
1987 12:51:25.157217 MTRR: Fixed MSR 0x26e 0x0606060606060606
1988 12:51:25.163729 MTRR: Fixed MSR 0x26f 0x0606060606060606
1989 12:51:25.170535 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
1990 12:51:25.174102 call enable_fixed_mtrr()
1991 12:51:25.178565 Checking cr50 for pending updates
1992 12:51:25.178650 CPU physical address size: 39 bits
1993 12:51:25.182215 MTRR: Fixed MSR 0x250 0x0606060606060606
1994 12:51:25.188747 MTRR: Fixed MSR 0x250 0x0606060606060606
1995 12:51:25.192256 MTRR: Fixed MSR 0x258 0x0606060606060606
1996 12:51:25.195486 MTRR: Fixed MSR 0x259 0x0000000000000000
1997 12:51:25.199526 MTRR: Fixed MSR 0x268 0x0606060606060606
1998 12:51:25.205514 MTRR: Fixed MSR 0x269 0x0606060606060606
1999 12:51:25.208632 MTRR: Fixed MSR 0x26a 0x0606060606060606
2000 12:51:25.212176 MTRR: Fixed MSR 0x26b 0x0606060606060606
2001 12:51:25.215317 MTRR: Fixed MSR 0x26c 0x0606060606060606
2002 12:51:25.218801 MTRR: Fixed MSR 0x26d 0x0606060606060606
2003 12:51:25.225415 MTRR: Fixed MSR 0x26e 0x0606060606060606
2004 12:51:25.228792 MTRR: Fixed MSR 0x26f 0x0606060606060606
2005 12:51:25.232281 MTRR: Fixed MSR 0x258 0x0606060606060606
2006 12:51:25.235338 call enable_fixed_mtrr()
2007 12:51:25.238894 MTRR: Fixed MSR 0x259 0x0000000000000000
2008 12:51:25.245407 MTRR: Fixed MSR 0x268 0x0606060606060606
2009 12:51:25.248690 MTRR: Fixed MSR 0x269 0x0606060606060606
2010 12:51:25.252309 MTRR: Fixed MSR 0x26a 0x0606060606060606
2011 12:51:25.255333 MTRR: Fixed MSR 0x26b 0x0606060606060606
2012 12:51:25.261915 MTRR: Fixed MSR 0x26c 0x0606060606060606
2013 12:51:25.265465 MTRR: Fixed MSR 0x26d 0x0606060606060606
2014 12:51:25.268504 MTRR: Fixed MSR 0x26e 0x0606060606060606
2015 12:51:25.271885 MTRR: Fixed MSR 0x26f 0x0606060606060606
2016 12:51:25.275862 CPU physical address size: 39 bits
2017 12:51:25.283589 call enable_fixed_mtrr()
2018 12:51:25.283673 Reading cr50 TPM mode
2019 12:51:25.287179 MTRR: Fixed MSR 0x250 0x0606060606060606
2020 12:51:25.290631 MTRR: Fixed MSR 0x250 0x0606060606060606
2021 12:51:25.297123 MTRR: Fixed MSR 0x258 0x0606060606060606
2022 12:51:25.300456 MTRR: Fixed MSR 0x259 0x0000000000000000
2023 12:51:25.303864 MTRR: Fixed MSR 0x268 0x0606060606060606
2024 12:51:25.307178 MTRR: Fixed MSR 0x269 0x0606060606060606
2025 12:51:25.310426 MTRR: Fixed MSR 0x26a 0x0606060606060606
2026 12:51:25.317154 MTRR: Fixed MSR 0x26b 0x0606060606060606
2027 12:51:25.320609 MTRR: Fixed MSR 0x26c 0x0606060606060606
2028 12:51:25.323976 MTRR: Fixed MSR 0x26d 0x0606060606060606
2029 12:51:25.327063 MTRR: Fixed MSR 0x26e 0x0606060606060606
2030 12:51:25.333601 MTRR: Fixed MSR 0x26f 0x0606060606060606
2031 12:51:25.336851 MTRR: Fixed MSR 0x258 0x0606060606060606
2032 12:51:25.340662 call enable_fixed_mtrr()
2033 12:51:25.343886 MTRR: Fixed MSR 0x259 0x0000000000000000
2034 12:51:25.347076 MTRR: Fixed MSR 0x268 0x0606060606060606
2035 12:51:25.353446 MTRR: Fixed MSR 0x269 0x0606060606060606
2036 12:51:25.356720 MTRR: Fixed MSR 0x26a 0x0606060606060606
2037 12:51:25.360063 MTRR: Fixed MSR 0x26b 0x0606060606060606
2038 12:51:25.363344 MTRR: Fixed MSR 0x26c 0x0606060606060606
2039 12:51:25.370164 MTRR: Fixed MSR 0x26d 0x0606060606060606
2040 12:51:25.373503 MTRR: Fixed MSR 0x26e 0x0606060606060606
2041 12:51:25.376807 MTRR: Fixed MSR 0x26f 0x0606060606060606
2042 12:51:25.380135 CPU physical address size: 39 bits
2043 12:51:25.386570 call enable_fixed_mtrr()
2044 12:51:25.390140 CPU physical address size: 39 bits
2045 12:51:25.393366 MTRR: Fixed MSR 0x250 0x0606060606060606
2046 12:51:25.396519 MTRR: Fixed MSR 0x250 0x0606060606060606
2047 12:51:25.399894 MTRR: Fixed MSR 0x258 0x0606060606060606
2048 12:51:25.406722 MTRR: Fixed MSR 0x259 0x0000000000000000
2049 12:51:25.409828 MTRR: Fixed MSR 0x268 0x0606060606060606
2050 12:51:25.413238 MTRR: Fixed MSR 0x269 0x0606060606060606
2051 12:51:25.416447 MTRR: Fixed MSR 0x26a 0x0606060606060606
2052 12:51:25.423206 MTRR: Fixed MSR 0x26b 0x0606060606060606
2053 12:51:25.426550 MTRR: Fixed MSR 0x26c 0x0606060606060606
2054 12:51:25.429896 MTRR: Fixed MSR 0x26d 0x0606060606060606
2055 12:51:25.432996 MTRR: Fixed MSR 0x26e 0x0606060606060606
2056 12:51:25.436191 MTRR: Fixed MSR 0x26f 0x0606060606060606
2057 12:51:25.443221 MTRR: Fixed MSR 0x258 0x0606060606060606
2058 12:51:25.446195 call enable_fixed_mtrr()
2059 12:51:25.449650 MTRR: Fixed MSR 0x259 0x0000000000000000
2060 12:51:25.453049 MTRR: Fixed MSR 0x268 0x0606060606060606
2061 12:51:25.457095 MTRR: Fixed MSR 0x269 0x0606060606060606
2062 12:51:25.463074 MTRR: Fixed MSR 0x26a 0x0606060606060606
2063 12:51:25.466787 MTRR: Fixed MSR 0x26b 0x0606060606060606
2064 12:51:25.469463 MTRR: Fixed MSR 0x26c 0x0606060606060606
2065 12:51:25.472975 MTRR: Fixed MSR 0x26d 0x0606060606060606
2066 12:51:25.479647 MTRR: Fixed MSR 0x26e 0x0606060606060606
2067 12:51:25.482816 MTRR: Fixed MSR 0x26f 0x0606060606060606
2068 12:51:25.486242 CPU physical address size: 39 bits
2069 12:51:25.490033 call enable_fixed_mtrr()
2070 12:51:25.494093 CPU physical address size: 39 bits
2071 12:51:25.496888 CPU physical address size: 39 bits
2072 12:51:25.503710 BS: BS_PAYLOAD_LOAD entry times (exec / console): 112 / 6 ms
2073 12:51:25.510379 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2074 12:51:25.516714 Checking segment from ROM address 0xffc02b38
2075 12:51:25.520766 Checking segment from ROM address 0xffc02b54
2076 12:51:25.523512 Loading segment from ROM address 0xffc02b38
2077 12:51:25.526840 code (compression=0)
2078 12:51:25.537071 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2079 12:51:25.544018 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2080 12:51:25.546924 it's not compressed!
2081 12:51:25.685448 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2082 12:51:25.692266 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2083 12:51:25.699062 Loading segment from ROM address 0xffc02b54
2084 12:51:25.699147 Entry Point 0x30000000
2085 12:51:25.702474 Loaded segments
2086 12:51:25.708661 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2087 12:51:25.751799 Finalizing chipset.
2088 12:51:25.754943 Finalizing SMM.
2089 12:51:25.755036 APMC done.
2090 12:51:25.761833 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2091 12:51:25.765174 mp_park_aps done after 0 msecs.
2092 12:51:25.768769 Jumping to boot code at 0x30000000(0x76b25000)
2093 12:51:25.778310 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2094 12:51:25.778395
2095 12:51:25.778461
2096 12:51:25.778521
2097 12:51:25.781713 Starting depthcharge on Voema...
2098 12:51:25.781796
2099 12:51:25.782133 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2100 12:51:25.782234 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2101 12:51:25.782315 Setting prompt string to ['volteer:']
2102 12:51:25.782393 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2103 12:51:25.791787 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2104 12:51:25.791872
2105 12:51:25.798066 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2106 12:51:25.798151
2107 12:51:25.801623 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2108 12:51:25.805941
2109 12:51:25.806024 Failed to find eMMC card reader
2110 12:51:25.806091
2111 12:51:25.809216 Wipe memory regions:
2112 12:51:25.809299
2113 12:51:25.812361 [0x00000000001000, 0x000000000a0000)
2114 12:51:25.812444
2115 12:51:25.815902 [0x00000000100000, 0x00000030000000)
2116 12:51:25.843317
2117 12:51:25.846960 [0x00000032662db0, 0x000000769ef000)
2118 12:51:25.882923
2119 12:51:25.886099 [0x00000100000000, 0x00000280400000)
2120 12:51:26.087620
2121 12:51:26.091292 ec_init: CrosEC protocol v3 supported (256, 256)
2122 12:51:26.091407
2123 12:51:26.098027 update_port_state: port C0 state: usb enable 1 mux conn 0
2124 12:51:26.098141
2125 12:51:26.104364 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2126 12:51:26.108935
2127 12:51:26.112306 pmc_check_ipc_sts: STS_BUSY done after 1611 us
2128 12:51:26.112415
2129 12:51:26.115773 send_conn_disc_msg: pmc_send_cmd succeeded
2130 12:51:26.547900
2131 12:51:26.548074 R8152: Initializing
2132 12:51:26.548175
2133 12:51:26.551401 Version 6 (ocp_data = 5c30)
2134 12:51:26.551512
2135 12:51:26.555041 R8152: Done initializing
2136 12:51:26.555156
2137 12:51:26.557816 Adding net device
2138 12:51:26.859284
2139 12:51:26.862804 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2140 12:51:26.862920
2141 12:51:26.863017
2142 12:51:26.863109
2143 12:51:26.866327 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2145 12:51:26.966718 volteer: tftpboot 192.168.201.1 11602091/tftp-deploy-5liexiwc/kernel/bzImage 11602091/tftp-deploy-5liexiwc/kernel/cmdline 11602091/tftp-deploy-5liexiwc/ramdisk/ramdisk.cpio.gz
2146 12:51:26.966949 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2147 12:51:26.967094 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2148 12:51:26.970969 tftpboot 192.168.201.1 11602091/tftp-deploy-5liexiwc/kernel/bzImploy-5liexiwc/kernel/cmdline 11602091/tftp-deploy-5liexiwc/ramdisk/ramdisk.cpio.gz
2149 12:51:26.971087
2150 12:51:26.971184 Waiting for link
2151 12:51:27.176330
2152 12:51:27.176505 done.
2153 12:51:27.176611
2154 12:51:27.176732 MAC: 00:24:32:30:78:74
2155 12:51:27.176853
2156 12:51:27.179476 Sending DHCP discover... done.
2157 12:51:27.179585
2158 12:51:27.182811 Waiting for reply... done.
2159 12:51:27.182920
2160 12:51:27.186219 Sending DHCP request... done.
2161 12:51:27.186363
2162 12:51:27.240695 Waiting for reply... done.
2163 12:51:27.240885
2164 12:51:27.241000 My ip is 192.168.201.14
2165 12:51:27.241102
2166 12:51:27.243906 The DHCP server ip is 192.168.201.1
2167 12:51:27.247322
2168 12:51:27.250644 TFTP server IP predefined by user: 192.168.201.1
2169 12:51:27.250770
2170 12:51:27.257366 Bootfile predefined by user: 11602091/tftp-deploy-5liexiwc/kernel/bzImage
2171 12:51:27.257494
2172 12:51:27.260583 Sending tftp read request... done.
2173 12:51:27.260696
2174 12:51:27.264154 Waiting for the transfer...
2175 12:51:27.264264
2176 12:51:27.824413 00000000 ################################################################
2177 12:51:27.824593
2178 12:51:28.380121 00080000 ################################################################
2179 12:51:28.380292
2180 12:51:28.905209 00100000 ################################################################
2181 12:51:28.905351
2182 12:51:29.436410 00180000 ################################################################
2183 12:51:29.436556
2184 12:51:29.956053 00200000 ################################################################
2185 12:51:29.956203
2186 12:51:30.469281 00280000 ################################################################
2187 12:51:30.469449
2188 12:51:30.982752 00300000 ################################################################
2189 12:51:30.982896
2190 12:51:31.495609 00380000 ################################################################
2191 12:51:31.495756
2192 12:51:32.010582 00400000 ################################################################
2193 12:51:32.010740
2194 12:51:32.538769 00480000 ################################################################
2195 12:51:32.538946
2196 12:51:33.055582 00500000 ################################################################
2197 12:51:33.055734
2198 12:51:33.583806 00580000 ################################################################
2199 12:51:33.583954
2200 12:51:34.095728 00600000 ################################################################
2201 12:51:34.095864
2202 12:51:34.604591 00680000 ################################################################
2203 12:51:34.604787
2204 12:51:35.111576 00700000 ################################################################
2205 12:51:35.111738
2206 12:51:35.624334 00780000 ################################################################
2207 12:51:35.624499
2208 12:51:36.155932 00800000 ################################################################
2209 12:51:36.156066
2210 12:51:36.675218 00880000 ################################################################
2211 12:51:36.675358
2212 12:51:37.190556 00900000 ################################################################
2213 12:51:37.190697
2214 12:51:37.734671 00980000 ################################################################
2215 12:51:37.734800
2216 12:51:38.288624 00a00000 ################################################################
2217 12:51:38.288760
2218 12:51:38.771891 00a80000 ######################################################### done.
2219 12:51:38.772032
2220 12:51:38.775201 The bootfile was 11473408 bytes long.
2221 12:51:38.775285
2222 12:51:38.778446 Sending tftp read request... done.
2223 12:51:38.778521
2224 12:51:38.781822 Waiting for the transfer...
2225 12:51:38.781900
2226 12:51:39.319763 00000000 ################################################################
2227 12:51:39.319905
2228 12:51:39.841485 00080000 ################################################################
2229 12:51:39.841632
2230 12:51:40.345074 00100000 ################################################################
2231 12:51:40.345209
2232 12:51:40.853896 00180000 ################################################################
2233 12:51:40.854033
2234 12:51:41.366662 00200000 ################################################################
2235 12:51:41.366806
2236 12:51:41.869358 00280000 ################################################################
2237 12:51:41.869508
2238 12:51:42.380668 00300000 ################################################################
2239 12:51:42.380825
2240 12:51:42.874348 00380000 ################################################################
2241 12:51:42.874514
2242 12:51:43.375612 00400000 ################################################################
2243 12:51:43.375750
2244 12:51:43.877345 00480000 ################################################################
2245 12:51:43.877518
2246 12:51:44.379982 00500000 ################################################################
2247 12:51:44.380154
2248 12:51:44.893750 00580000 ################################################################
2249 12:51:44.893912
2250 12:51:45.397664 00600000 ################################################################
2251 12:51:45.397799
2252 12:51:45.902551 00680000 ################################################################
2253 12:51:45.902693
2254 12:51:46.407255 00700000 ################################################################
2255 12:51:46.407418
2256 12:51:46.912761 00780000 ################################################################
2257 12:51:46.912923
2258 12:51:47.421505 00800000 ################################################################
2259 12:51:47.421661
2260 12:51:47.710475 00880000 ##################################### done.
2261 12:51:47.710628
2262 12:51:47.713509 Sending tftp read request... done.
2263 12:51:47.713593
2264 12:51:47.716837 Waiting for the transfer...
2265 12:51:47.716921
2266 12:51:47.717030 00000000 # done.
2267 12:51:47.717095
2268 12:51:47.727100 Command line loaded dynamically from TFTP file: 11602091/tftp-deploy-5liexiwc/kernel/cmdline
2269 12:51:47.727186
2270 12:51:47.743676 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2271 12:51:47.747267
2272 12:51:47.750816 Shutting down all USB controllers.
2273 12:51:47.750916
2274 12:51:47.750996 Removing current net device
2275 12:51:47.751058
2276 12:51:47.754049 Finalizing coreboot
2277 12:51:47.754132
2278 12:51:47.760615 Exiting depthcharge with code 4 at timestamp: 30633032
2279 12:51:47.760732
2280 12:51:47.760826
2281 12:51:47.760916 Starting kernel ...
2282 12:51:47.761019
2283 12:51:47.761079
2284 12:51:47.761454 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
2285 12:51:47.761549 start: 2.2.5 auto-login-action (timeout 00:04:23) [common]
2286 12:51:47.761624 Setting prompt string to ['Linux version [0-9]']
2287 12:51:47.761691 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2288 12:51:47.761759 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2290 12:56:10.762738 end: 2.2.5 auto-login-action (duration 00:04:23) [common]
2292 12:56:10.763830 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 263 seconds'
2294 12:56:10.764701 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2297 12:56:10.766145 end: 2 depthcharge-action (duration 00:05:00) [common]
2299 12:56:10.766865 Cleaning after the job
2300 12:56:10.766951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/ramdisk
2301 12:56:10.768094 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/kernel
2302 12:56:10.769400 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11602091/tftp-deploy-5liexiwc/modules
2303 12:56:10.769926 start: 5.1 power-off (timeout 00:00:30) [common]
2304 12:56:10.770081 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-1' '--port=1' '--command=off'
2305 12:56:10.854394 >> Command sent successfully.
2306 12:56:10.865235 Returned 0 in 0 seconds
2307 12:56:10.966609 end: 5.1 power-off (duration 00:00:00) [common]
2309 12:56:10.968141 start: 5.2 read-feedback (timeout 00:10:00) [common]
2310 12:56:10.969421 Listened to connection for namespace 'common' for up to 1s
2311 12:56:11.969364 Finalising connection for namespace 'common'
2312 12:56:11.970038 Disconnecting from shell: Finalise
2313 12:56:11.970460
2314 12:56:12.071598 end: 5.2 read-feedback (duration 00:00:01) [common]
2315 12:56:12.072218 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11602091
2316 12:56:12.089571 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11602091
2317 12:56:12.089697 JobError: Your job cannot terminate cleanly.