Boot log: asus-C436FA-Flip-hatch
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 01:48:31.918694 lava-dispatcher, installed at version: 2023.08
2 01:48:31.918931 start: 0 validate
3 01:48:31.919062 Start time: 2023-10-11 01:48:31.919054+00:00 (UTC)
4 01:48:31.919182 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:48:31.919314 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 01:48:32.184781 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:48:32.185757 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.295-cip103-95-ge42cfc8bb88b7%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 01:48:32.441422 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:48:32.442169 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.295-cip103-95-ge42cfc8bb88b7%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 01:48:35.635535 validate duration: 3.72
12 01:48:35.635821 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 01:48:35.635925 start: 1.1 download-retry (timeout 00:10:00) [common]
14 01:48:35.636025 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 01:48:35.636150 Not decompressing ramdisk as can be used compressed.
16 01:48:35.636233 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 01:48:35.636317 saving as /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/ramdisk/rootfs.cpio.gz
18 01:48:35.636393 total size: 8418130 (8 MB)
19 01:48:36.262610 progress 0 % (0 MB)
20 01:48:36.276011 progress 5 % (0 MB)
21 01:48:36.289193 progress 10 % (0 MB)
22 01:48:36.299411 progress 15 % (1 MB)
23 01:48:36.305708 progress 20 % (1 MB)
24 01:48:36.310573 progress 25 % (2 MB)
25 01:48:36.314774 progress 30 % (2 MB)
26 01:48:36.318185 progress 35 % (2 MB)
27 01:48:36.321542 progress 40 % (3 MB)
28 01:48:36.324696 progress 45 % (3 MB)
29 01:48:36.327595 progress 50 % (4 MB)
30 01:48:36.330346 progress 55 % (4 MB)
31 01:48:36.332941 progress 60 % (4 MB)
32 01:48:36.335180 progress 65 % (5 MB)
33 01:48:36.337463 progress 70 % (5 MB)
34 01:48:36.339786 progress 75 % (6 MB)
35 01:48:36.342028 progress 80 % (6 MB)
36 01:48:36.344219 progress 85 % (6 MB)
37 01:48:36.346413 progress 90 % (7 MB)
38 01:48:36.348618 progress 95 % (7 MB)
39 01:48:36.350752 progress 100 % (8 MB)
40 01:48:36.350980 8 MB downloaded in 0.71 s (11.23 MB/s)
41 01:48:36.351147 end: 1.1.1 http-download (duration 00:00:01) [common]
43 01:48:36.351394 end: 1.1 download-retry (duration 00:00:01) [common]
44 01:48:36.351482 start: 1.2 download-retry (timeout 00:09:59) [common]
45 01:48:36.351564 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 01:48:36.351701 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.295-cip103-95-ge42cfc8bb88b7/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 01:48:36.351769 saving as /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/kernel/bzImage
48 01:48:36.351831 total size: 11473408 (10 MB)
49 01:48:36.351892 No compression specified
50 01:48:36.353071 progress 0 % (0 MB)
51 01:48:36.356113 progress 5 % (0 MB)
52 01:48:36.359195 progress 10 % (1 MB)
53 01:48:36.362047 progress 15 % (1 MB)
54 01:48:36.365108 progress 20 % (2 MB)
55 01:48:36.368033 progress 25 % (2 MB)
56 01:48:36.371099 progress 30 % (3 MB)
57 01:48:36.373996 progress 35 % (3 MB)
58 01:48:36.377100 progress 40 % (4 MB)
59 01:48:36.380115 progress 45 % (4 MB)
60 01:48:36.383299 progress 50 % (5 MB)
61 01:48:36.386345 progress 55 % (6 MB)
62 01:48:36.389479 progress 60 % (6 MB)
63 01:48:36.392451 progress 65 % (7 MB)
64 01:48:36.395499 progress 70 % (7 MB)
65 01:48:36.398407 progress 75 % (8 MB)
66 01:48:36.401397 progress 80 % (8 MB)
67 01:48:36.404399 progress 85 % (9 MB)
68 01:48:36.407505 progress 90 % (9 MB)
69 01:48:36.410374 progress 95 % (10 MB)
70 01:48:36.413495 progress 100 % (10 MB)
71 01:48:36.413620 10 MB downloaded in 0.06 s (177.10 MB/s)
72 01:48:36.413774 end: 1.2.1 http-download (duration 00:00:00) [common]
74 01:48:36.414002 end: 1.2 download-retry (duration 00:00:00) [common]
75 01:48:36.414086 start: 1.3 download-retry (timeout 00:09:59) [common]
76 01:48:36.414168 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 01:48:36.414311 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.295-cip103-95-ge42cfc8bb88b7/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 01:48:36.414378 saving as /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/modules/modules.tar
79 01:48:36.414442 total size: 484192 (0 MB)
80 01:48:36.414503 Using unxz to decompress xz
81 01:48:36.418801 progress 6 % (0 MB)
82 01:48:36.419214 progress 13 % (0 MB)
83 01:48:36.419460 progress 20 % (0 MB)
84 01:48:36.421059 progress 27 % (0 MB)
85 01:48:36.423104 progress 33 % (0 MB)
86 01:48:36.424981 progress 40 % (0 MB)
87 01:48:36.426948 progress 47 % (0 MB)
88 01:48:36.428838 progress 54 % (0 MB)
89 01:48:36.430848 progress 60 % (0 MB)
90 01:48:36.432860 progress 67 % (0 MB)
91 01:48:36.434886 progress 74 % (0 MB)
92 01:48:36.436930 progress 81 % (0 MB)
93 01:48:36.438871 progress 87 % (0 MB)
94 01:48:36.440803 progress 94 % (0 MB)
95 01:48:36.443233 progress 100 % (0 MB)
96 01:48:36.449751 0 MB downloaded in 0.04 s (13.08 MB/s)
97 01:48:36.450036 end: 1.3.1 http-download (duration 00:00:00) [common]
99 01:48:36.450308 end: 1.3 download-retry (duration 00:00:00) [common]
100 01:48:36.450400 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
101 01:48:36.450493 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
102 01:48:36.450617 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 01:48:36.450702 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
104 01:48:36.450927 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a
105 01:48:36.451064 makedir: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin
106 01:48:36.451169 makedir: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/tests
107 01:48:36.451268 makedir: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/results
108 01:48:36.451386 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-add-keys
109 01:48:36.451536 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-add-sources
110 01:48:36.451668 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-background-process-start
111 01:48:36.451802 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-background-process-stop
112 01:48:36.451929 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-common-functions
113 01:48:36.452054 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-echo-ipv4
114 01:48:36.452180 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-install-packages
115 01:48:36.452318 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-installed-packages
116 01:48:36.452444 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-os-build
117 01:48:36.452569 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-probe-channel
118 01:48:36.452694 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-probe-ip
119 01:48:36.452817 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-target-ip
120 01:48:36.452942 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-target-mac
121 01:48:36.453066 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-target-storage
122 01:48:36.453195 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-case
123 01:48:36.453320 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-event
124 01:48:36.453444 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-feedback
125 01:48:36.453569 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-raise
126 01:48:36.453694 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-reference
127 01:48:36.453820 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-runner
128 01:48:36.453944 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-set
129 01:48:36.454068 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-test-shell
130 01:48:36.454196 Updating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-install-packages (oe)
131 01:48:36.454351 Updating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/bin/lava-installed-packages (oe)
132 01:48:36.454474 Creating /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/environment
133 01:48:36.454577 LAVA metadata
134 01:48:36.454656 - LAVA_JOB_ID=11733014
135 01:48:36.454720 - LAVA_DISPATCHER_IP=192.168.201.1
136 01:48:36.454823 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
137 01:48:36.454890 skipped lava-vland-overlay
138 01:48:36.454966 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 01:48:36.455044 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
140 01:48:36.455106 skipped lava-multinode-overlay
141 01:48:36.455180 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 01:48:36.455258 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
143 01:48:36.455330 Loading test definitions
144 01:48:36.455421 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
145 01:48:36.455497 Using /lava-11733014 at stage 0
146 01:48:36.455819 uuid=11733014_1.4.2.3.1 testdef=None
147 01:48:36.455906 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 01:48:36.455992 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
149 01:48:36.456585 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 01:48:36.456803 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
152 01:48:36.457449 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 01:48:36.457673 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
155 01:48:36.458288 runner path: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/0/tests/0_dmesg test_uuid 11733014_1.4.2.3.1
156 01:48:36.458443 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 01:48:36.458710 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
159 01:48:36.458781 Using /lava-11733014 at stage 1
160 01:48:36.459074 uuid=11733014_1.4.2.3.5 testdef=None
161 01:48:36.459160 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 01:48:36.459242 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
163 01:48:36.459707 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 01:48:36.459918 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
166 01:48:36.460559 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 01:48:36.460782 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
169 01:48:36.461407 runner path: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/1/tests/1_bootrr test_uuid 11733014_1.4.2.3.5
170 01:48:36.461559 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 01:48:36.461761 Creating lava-test-runner.conf files
173 01:48:36.461822 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/0 for stage 0
174 01:48:36.461911 - 0_dmesg
175 01:48:36.461989 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11733014/lava-overlay-sucm6l6a/lava-11733014/1 for stage 1
176 01:48:36.462079 - 1_bootrr
177 01:48:36.462172 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 01:48:36.462255 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
179 01:48:36.470740 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 01:48:36.470850 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
181 01:48:36.470936 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 01:48:36.471023 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 01:48:36.471106 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
184 01:48:36.725368 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 01:48:36.725760 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
186 01:48:36.725881 extracting modules file /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11733014/extract-overlay-ramdisk-_z9pi1na/ramdisk
187 01:48:36.747227 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 01:48:36.747387 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
189 01:48:36.747490 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11733014/compress-overlay-5g15tk4a/overlay-1.4.2.4.tar.gz to ramdisk
190 01:48:36.747559 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11733014/compress-overlay-5g15tk4a/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11733014/extract-overlay-ramdisk-_z9pi1na/ramdisk
191 01:48:36.755863 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 01:48:36.755972 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
193 01:48:36.756060 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 01:48:36.756147 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
195 01:48:36.756224 Building ramdisk /var/lib/lava/dispatcher/tmp/11733014/extract-overlay-ramdisk-_z9pi1na/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11733014/extract-overlay-ramdisk-_z9pi1na/ramdisk
196 01:48:36.905006 >> 53982 blocks
197 01:48:37.793960 rename /var/lib/lava/dispatcher/tmp/11733014/extract-overlay-ramdisk-_z9pi1na/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/ramdisk/ramdisk.cpio.gz
198 01:48:37.794427 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 01:48:37.794584 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 01:48:37.794702 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 01:48:37.794802 No mkimage arch provided, not using FIT.
202 01:48:37.794894 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 01:48:37.794977 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 01:48:37.795079 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
205 01:48:37.795168 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 01:48:37.795247 No LXC device requested
207 01:48:37.795321 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 01:48:37.795404 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 01:48:37.795481 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 01:48:37.795555 Checking files for TFTP limit of 4294967296 bytes.
211 01:48:37.795960 end: 1 tftp-deploy (duration 00:00:02) [common]
212 01:48:37.796065 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 01:48:37.796161 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 01:48:37.796280 substitutions:
215 01:48:37.796344 - {DTB}: None
216 01:48:37.796404 - {INITRD}: 11733014/tftp-deploy-n_ivmho2/ramdisk/ramdisk.cpio.gz
217 01:48:37.796461 - {KERNEL}: 11733014/tftp-deploy-n_ivmho2/kernel/bzImage
218 01:48:37.796517 - {LAVA_MAC}: None
219 01:48:37.796572 - {PRESEED_CONFIG}: None
220 01:48:37.796625 - {PRESEED_LOCAL}: None
221 01:48:37.796678 - {RAMDISK}: 11733014/tftp-deploy-n_ivmho2/ramdisk/ramdisk.cpio.gz
222 01:48:37.796732 - {ROOT_PART}: None
223 01:48:37.796784 - {ROOT}: None
224 01:48:37.796837 - {SERVER_IP}: 192.168.201.1
225 01:48:37.796889 - {TEE}: None
226 01:48:37.796943 Parsed boot commands:
227 01:48:37.796995 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 01:48:37.797177 Parsed boot commands: tftpboot 192.168.201.1 11733014/tftp-deploy-n_ivmho2/kernel/bzImage 11733014/tftp-deploy-n_ivmho2/kernel/cmdline 11733014/tftp-deploy-n_ivmho2/ramdisk/ramdisk.cpio.gz
229 01:48:37.797266 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 01:48:37.797353 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 01:48:37.797445 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 01:48:37.797531 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 01:48:37.797600 Not connected, no need to disconnect.
234 01:48:37.797672 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 01:48:37.797752 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 01:48:37.797817 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-C436FA-Flip-hatch-cbg-0'
237 01:48:37.801818 Setting prompt string to ['lava-test: # ']
238 01:48:37.802179 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 01:48:37.802283 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 01:48:37.802374 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 01:48:37.802460 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 01:48:37.802690 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=reboot'
243 01:48:42.954037 >> Command sent successfully.
244 01:48:42.965619 Returned 0 in 5 seconds
245 01:48:43.066942 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 01:48:43.068549 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 01:48:43.069121 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 01:48:43.069588 Setting prompt string to 'Starting depthcharge on Helios...'
250 01:48:43.069960 Changing prompt to 'Starting depthcharge on Helios...'
251 01:48:43.070344 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
252 01:48:43.072063 [Enter `^Ec?' for help]
253 01:48:43.677146
254 01:48:43.677912
255 01:48:43.687507 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
256 01:48:43.691077 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
257 01:48:43.697307 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
258 01:48:43.701055 CPU: AES supported, TXT NOT supported, VT supported
259 01:48:43.707723 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
260 01:48:43.710881 PCH: device id 0284 (rev 00) is Cometlake-U Premium
261 01:48:43.717736 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
262 01:48:43.720762 VBOOT: Loading verstage.
263 01:48:43.724031 FMAP: Found "FLASH" version 1.1 at 0xc04000.
264 01:48:43.730619 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
265 01:48:43.734115 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
266 01:48:43.737316 CBFS @ c08000 size 3f8000
267 01:48:43.744165 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
268 01:48:43.747659 CBFS: Locating 'fallback/verstage'
269 01:48:43.750875 CBFS: Found @ offset 10fb80 size 1072c
270 01:48:43.751344
271 01:48:43.754220
272 01:48:43.764258 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
273 01:48:43.778409 Probing TPM: . done!
274 01:48:43.781866 TPM ready after 0 ms
275 01:48:43.785451 Connected to device vid:did:rid of 1ae0:0028:00
276 01:48:43.795484 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
277 01:48:43.798992 Initialized TPM device CR50 revision 0
278 01:48:43.845609 tlcl_send_startup: Startup return code is 0
279 01:48:43.846199 TPM: setup succeeded
280 01:48:43.858617 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
281 01:48:43.862108 Chrome EC: UHEPI supported
282 01:48:43.865807 Phase 1
283 01:48:43.868975 FMAP: area GBB found @ c05000 (12288 bytes)
284 01:48:43.875768 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
285 01:48:43.876338 Phase 2
286 01:48:43.878894 Phase 3
287 01:48:43.882509 FMAP: area GBB found @ c05000 (12288 bytes)
288 01:48:43.888984 VB2:vb2_report_dev_firmware() This is developer signed firmware
289 01:48:43.895443 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
290 01:48:43.898977 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
291 01:48:43.905757 VB2:vb2_verify_keyblock() Checking keyblock signature...
292 01:48:43.921433 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
293 01:48:43.924051 FMAP: area VBLOCK_A found @ 400000 (65536 bytes)
294 01:48:43.930969 VB2:vb2_verify_fw_preamble() Verifying preamble.
295 01:48:43.934982 Phase 4
296 01:48:43.938293 FMAP: area FW_MAIN_A found @ 410000 (3506112 bytes)
297 01:48:43.945004 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
298 01:48:44.124541 VB2:vb2_rsa_verify_digest() Digest check failed!
299 01:48:44.131095 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
300 01:48:44.131704 Saving nvdata
301 01:48:44.134612 Reboot requested (10020007)
302 01:48:44.137828 board_reset() called!
303 01:48:44.138465 full_reset() called!
304 01:48:48.644368
305 01:48:48.644902
306 01:48:48.654411 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
307 01:48:48.657837 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
308 01:48:48.664290 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
309 01:48:48.668377 CPU: AES supported, TXT NOT supported, VT supported
310 01:48:48.674331 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
311 01:48:48.677680 PCH: device id 0284 (rev 00) is Cometlake-U Premium
312 01:48:48.684528 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
313 01:48:48.687446 VBOOT: Loading verstage.
314 01:48:48.691049 FMAP: Found "FLASH" version 1.1 at 0xc04000.
315 01:48:48.697846 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
316 01:48:48.701219 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
317 01:48:48.704430 CBFS @ c08000 size 3f8000
318 01:48:48.711166 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
319 01:48:48.714607 CBFS: Locating 'fallback/verstage'
320 01:48:48.717581 CBFS: Found @ offset 10fb80 size 1072c
321 01:48:48.721419
322 01:48:48.721981
323 01:48:48.731014 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
324 01:48:48.745473 Probing TPM: . done!
325 01:48:48.749229 TPM ready after 0 ms
326 01:48:48.752156 Connected to device vid:did:rid of 1ae0:0028:00
327 01:48:48.762493 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
328 01:48:48.765775 Initialized TPM device CR50 revision 0
329 01:48:48.814166 tlcl_send_startup: Startup return code is 0
330 01:48:48.814744 TPM: setup succeeded
331 01:48:48.826650 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
332 01:48:48.830311 Chrome EC: UHEPI supported
333 01:48:48.834410 Phase 1
334 01:48:48.836879 FMAP: area GBB found @ c05000 (12288 bytes)
335 01:48:48.843864 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
336 01:48:48.850473 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
337 01:48:48.853687 Recovery requested (1009000e)
338 01:48:48.854149 Saving nvdata
339 01:48:48.865502 tlcl_extend: response is 0
340 01:48:48.874102 tlcl_extend: response is 0
341 01:48:48.881492 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
342 01:48:48.884263 CBFS @ c08000 size 3f8000
343 01:48:48.891141 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
344 01:48:48.894327 CBFS: Locating 'fallback/romstage'
345 01:48:48.898304 CBFS: Found @ offset 80 size 145fc
346 01:48:48.900881 Accumulated console time in verstage 98 ms
347 01:48:48.901360
348 01:48:48.901725
349 01:48:48.914039 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
350 01:48:48.921104 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
351 01:48:48.923952 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
352 01:48:48.927378 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
353 01:48:48.933993 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
354 01:48:48.937615 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
355 01:48:48.940622 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
356 01:48:48.944269 TCO_STS: 0000 0000
357 01:48:48.947527 GEN_PMCON: e0015238 00000200
358 01:48:48.950578 GBLRST_CAUSE: 00000000 00000000
359 01:48:48.951071 prev_sleep_state 5
360 01:48:48.953830 Boot Count incremented to 71507
361 01:48:48.961041 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
362 01:48:48.964837 CBFS @ c08000 size 3f8000
363 01:48:48.970954 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
364 01:48:48.971774 CBFS: Locating 'fspm.bin'
365 01:48:48.977716 CBFS: Found @ offset 5ffc0 size 71000
366 01:48:48.980732 Chrome EC: UHEPI supported
367 01:48:48.987963 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
368 01:48:48.990731 Probing TPM: done!
369 01:48:48.997637 Connected to device vid:did:rid of 1ae0:0028:00
370 01:48:49.007428 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
371 01:48:49.013476 Initialized TPM device CR50 revision 0
372 01:48:49.023007 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
373 01:48:49.029215 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
374 01:48:49.032397 MRC cache found, size 1948
375 01:48:49.035836 bootmode is set to: 2
376 01:48:49.039115 PRMRR disabled by config.
377 01:48:49.042478 SPD INDEX = 1
378 01:48:49.045862 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
379 01:48:49.049106 CBFS @ c08000 size 3f8000
380 01:48:49.055495 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
381 01:48:49.056202 CBFS: Locating 'spd.bin'
382 01:48:49.059413 CBFS: Found @ offset 5fb80 size 400
383 01:48:49.062069 SPD: module type is LPDDR3
384 01:48:49.065959 SPD: module part is
385 01:48:49.072083 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
386 01:48:49.075642 SPD: device width 4 bits, bus width 8 bits
387 01:48:49.078857 SPD: module size is 4096 MB (per channel)
388 01:48:49.082456 memory slot: 0 configuration done.
389 01:48:49.085502 memory slot: 2 configuration done.
390 01:48:49.136311 CBMEM:
391 01:48:49.139734 IMD: root @ 99fff000 254 entries.
392 01:48:49.143469 IMD: root @ 99ffec00 62 entries.
393 01:48:49.146281 External stage cache:
394 01:48:49.149791 IMD: root @ 9abff000 254 entries.
395 01:48:49.153353 IMD: root @ 9abfec00 62 entries.
396 01:48:49.159703 Chrome EC: clear events_b mask to 0x0000000020004000
397 01:48:49.172426 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
398 01:48:49.185770 tlcl_write: response is 0
399 01:48:49.195154 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
400 01:48:49.201822 MRC: TPM MRC hash updated successfully.
401 01:48:49.202365 2 DIMMs found
402 01:48:49.204937 SMM Memory Map
403 01:48:49.208118 SMRAM : 0x9a000000 0x1000000
404 01:48:49.212090 Subregion 0: 0x9a000000 0xa00000
405 01:48:49.215424 Subregion 1: 0x9aa00000 0x200000
406 01:48:49.218072 Subregion 2: 0x9ac00000 0x400000
407 01:48:49.221582 top_of_ram = 0x9a000000
408 01:48:49.224854 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
409 01:48:49.231502 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
410 01:48:49.234611 MTRR Range: Start=ff000000 End=0 (Size 1000000)
411 01:48:49.241499 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
412 01:48:49.244854 CBFS @ c08000 size 3f8000
413 01:48:49.248074 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
414 01:48:49.252077 CBFS: Locating 'fallback/postcar'
415 01:48:49.257963 CBFS: Found @ offset 107000 size 4b44
416 01:48:49.261027 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
417 01:48:49.273862 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
418 01:48:49.277095 Processing 180 relocs. Offset value of 0x97c0c000
419 01:48:49.285945 Accumulated console time in romstage 286 ms
420 01:48:49.286484
421 01:48:49.286949
422 01:48:49.296127 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
423 01:48:49.302232 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
424 01:48:49.305842 CBFS @ c08000 size 3f8000
425 01:48:49.308719 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
426 01:48:49.315293 CBFS: Locating 'fallback/ramstage'
427 01:48:49.319401 CBFS: Found @ offset 43380 size 1b9e8
428 01:48:49.325200 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
429 01:48:49.357726 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
430 01:48:49.360872 Processing 3976 relocs. Offset value of 0x98db0000
431 01:48:49.367979 Accumulated console time in postcar 52 ms
432 01:48:49.368697
433 01:48:49.369270
434 01:48:49.377267 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
435 01:48:49.383759 FMAP: area RO_VPD found @ c00000 (16384 bytes)
436 01:48:49.387061 WARNING: RO_VPD is uninitialized or empty.
437 01:48:49.390428 FMAP: area RW_VPD found @ af8000 (8192 bytes)
438 01:48:49.397515 FMAP: area RW_VPD found @ af8000 (8192 bytes)
439 01:48:49.398175 Normal boot.
440 01:48:49.404399 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
441 01:48:49.406954 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
442 01:48:49.410335 CBFS @ c08000 size 3f8000
443 01:48:49.417421 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
444 01:48:49.420186 CBFS: Locating 'cpu_microcode_blob.bin'
445 01:48:49.423695 CBFS: Found @ offset 14700 size 2ec00
446 01:48:49.426703 microcode: sig=0x806ec pf=0x4 revision=0xc9
447 01:48:49.430282 Skip microcode update
448 01:48:49.437165 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
449 01:48:49.437733 CBFS @ c08000 size 3f8000
450 01:48:49.443660 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
451 01:48:49.446685 CBFS: Locating 'fsps.bin'
452 01:48:49.450019 CBFS: Found @ offset d1fc0 size 35000
453 01:48:49.475575 Detected 4 core, 8 thread CPU.
454 01:48:49.478876 Setting up SMI for CPU
455 01:48:49.482426 IED base = 0x9ac00000
456 01:48:49.483049 IED size = 0x00400000
457 01:48:49.485930 Will perform SMM setup.
458 01:48:49.492172 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
459 01:48:49.498669 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
460 01:48:49.502049 Processing 16 relocs. Offset value of 0x00030000
461 01:48:49.505760 Attempting to start 7 APs
462 01:48:49.508996 Waiting for 10ms after sending INIT.
463 01:48:49.525183 Waiting for 1st SIPI to complete...AP: slot 2 apic_id 1.
464 01:48:49.525731 done.
465 01:48:49.528615 AP: slot 1 apic_id 2.
466 01:48:49.532731 AP: slot 4 apic_id 3.
467 01:48:49.533202 AP: slot 6 apic_id 5.
468 01:48:49.535232 AP: slot 5 apic_id 4.
469 01:48:49.538980 AP: slot 3 apic_id 7.
470 01:48:49.539548 AP: slot 7 apic_id 6.
471 01:48:49.545517 Waiting for 2nd SIPI to complete...done.
472 01:48:49.551825 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
473 01:48:49.555389 Processing 13 relocs. Offset value of 0x00038000
474 01:48:49.561805 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
475 01:48:49.568354 Installing SMM handler to 0x9a000000
476 01:48:49.575590 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
477 01:48:49.578512 Processing 658 relocs. Offset value of 0x9a010000
478 01:48:49.588487 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
479 01:48:49.591675 Processing 13 relocs. Offset value of 0x9a008000
480 01:48:49.598182 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
481 01:48:49.604937 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
482 01:48:49.607855 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
483 01:48:49.614632 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
484 01:48:49.621762 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
485 01:48:49.628368 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
486 01:48:49.631614 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
487 01:48:49.638342 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
488 01:48:49.641184 Clearing SMI status registers
489 01:48:49.644869 SMI_STS: PM1
490 01:48:49.645411 PM1_STS: PWRBTN
491 01:48:49.647972 TCO_STS: SECOND_TO
492 01:48:49.651292 New SMBASE 0x9a000000
493 01:48:49.654777 In relocation handler: CPU 0
494 01:48:49.657887 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
495 01:48:49.661092 Writing SMRR. base = 0x9a000006, mask=0xff000800
496 01:48:49.664351 Relocation complete.
497 01:48:49.668053 New SMBASE 0x99fff800
498 01:48:49.668529 In relocation handler: CPU 2
499 01:48:49.674420 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
500 01:48:49.677839 Writing SMRR. base = 0x9a000006, mask=0xff000800
501 01:48:49.681306 Relocation complete.
502 01:48:49.684448 New SMBASE 0x99fff400
503 01:48:49.684924 In relocation handler: CPU 3
504 01:48:49.690984 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
505 01:48:49.694972 Writing SMRR. base = 0x9a000006, mask=0xff000800
506 01:48:49.697869 Relocation complete.
507 01:48:49.698410 New SMBASE 0x99ffe400
508 01:48:49.700954 In relocation handler: CPU 7
509 01:48:49.708229 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
510 01:48:49.710980 Writing SMRR. base = 0x9a000006, mask=0xff000800
511 01:48:49.714387 Relocation complete.
512 01:48:49.714973 New SMBASE 0x99ffec00
513 01:48:49.718216 In relocation handler: CPU 5
514 01:48:49.720900 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
515 01:48:49.727816 Writing SMRR. base = 0x9a000006, mask=0xff000800
516 01:48:49.730990 Relocation complete.
517 01:48:49.731672 New SMBASE 0x99ffe800
518 01:48:49.734620 In relocation handler: CPU 6
519 01:48:49.738298 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
520 01:48:49.744117 Writing SMRR. base = 0x9a000006, mask=0xff000800
521 01:48:49.747791 Relocation complete.
522 01:48:49.748330 New SMBASE 0x99fff000
523 01:48:49.750940 In relocation handler: CPU 4
524 01:48:49.754211 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
525 01:48:49.760523 Writing SMRR. base = 0x9a000006, mask=0xff000800
526 01:48:49.761125 Relocation complete.
527 01:48:49.764111 New SMBASE 0x99fffc00
528 01:48:49.767490 In relocation handler: CPU 1
529 01:48:49.770723 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
530 01:48:49.777437 Writing SMRR. base = 0x9a000006, mask=0xff000800
531 01:48:49.777987 Relocation complete.
532 01:48:49.780693 Initializing CPU #0
533 01:48:49.784486 CPU: vendor Intel device 806ec
534 01:48:49.787725 CPU: family 06, model 8e, stepping 0c
535 01:48:49.790974 Clearing out pending MCEs
536 01:48:49.794062 Setting up local APIC...
537 01:48:49.794574 apic_id: 0x00 done.
538 01:48:49.797228 Turbo is available but hidden
539 01:48:49.800816 Turbo is available and visible
540 01:48:49.804218 VMX status: enabled
541 01:48:49.807653 IA32_FEATURE_CONTROL status: locked
542 01:48:49.810738 Skip microcode update
543 01:48:49.811212 CPU #0 initialized
544 01:48:49.813863 Initializing CPU #2
545 01:48:49.814332 Initializing CPU #4
546 01:48:49.817285 Initializing CPU #1
547 01:48:49.820695 CPU: vendor Intel device 806ec
548 01:48:49.824295 CPU: family 06, model 8e, stepping 0c
549 01:48:49.827399 CPU: vendor Intel device 806ec
550 01:48:49.831132 CPU: family 06, model 8e, stepping 0c
551 01:48:49.833890 Clearing out pending MCEs
552 01:48:49.837045 Clearing out pending MCEs
553 01:48:49.840526 Setting up local APIC...
554 01:48:49.841193 Initializing CPU #5
555 01:48:49.843833 Initializing CPU #6
556 01:48:49.847476 CPU: vendor Intel device 806ec
557 01:48:49.850337 CPU: family 06, model 8e, stepping 0c
558 01:48:49.854034 CPU: vendor Intel device 806ec
559 01:48:49.857070 CPU: family 06, model 8e, stepping 0c
560 01:48:49.860613 Clearing out pending MCEs
561 01:48:49.863464 Clearing out pending MCEs
562 01:48:49.863933 Setting up local APIC...
563 01:48:49.867149 CPU: vendor Intel device 806ec
564 01:48:49.870772 CPU: family 06, model 8e, stepping 0c
565 01:48:49.874220 Clearing out pending MCEs
566 01:48:49.876787 Setting up local APIC...
567 01:48:49.880018 Setting up local APIC...
568 01:48:49.883705 Setting up local APIC...
569 01:48:49.884207 Initializing CPU #3
570 01:48:49.886839 Initializing CPU #7
571 01:48:49.890555 CPU: vendor Intel device 806ec
572 01:48:49.893498 CPU: family 06, model 8e, stepping 0c
573 01:48:49.896860 CPU: vendor Intel device 806ec
574 01:48:49.900442 CPU: family 06, model 8e, stepping 0c
575 01:48:49.903185 Clearing out pending MCEs
576 01:48:49.907079 Clearing out pending MCEs
577 01:48:49.907643 Setting up local APIC...
578 01:48:49.909784 apic_id: 0x04 done.
579 01:48:49.913583 apic_id: 0x05 done.
580 01:48:49.914053 VMX status: enabled
581 01:48:49.917001 VMX status: enabled
582 01:48:49.919898 IA32_FEATURE_CONTROL status: locked
583 01:48:49.923154 IA32_FEATURE_CONTROL status: locked
584 01:48:49.926930 Skip microcode update
585 01:48:49.927497 Skip microcode update
586 01:48:49.929704 CPU #5 initialized
587 01:48:49.933333 CPU #6 initialized
588 01:48:49.933861 apic_id: 0x07 done.
589 01:48:49.936596 Setting up local APIC...
590 01:48:49.940165 apic_id: 0x01 done.
591 01:48:49.940633 apic_id: 0x03 done.
592 01:48:49.943241 apic_id: 0x02 done.
593 01:48:49.943706 VMX status: enabled
594 01:48:49.946370 VMX status: enabled
595 01:48:49.950011 IA32_FEATURE_CONTROL status: locked
596 01:48:49.953621 IA32_FEATURE_CONTROL status: locked
597 01:48:49.956527 Skip microcode update
598 01:48:49.959920 Skip microcode update
599 01:48:49.960398 CPU #4 initialized
600 01:48:49.963219 CPU #1 initialized
601 01:48:49.963683 VMX status: enabled
602 01:48:49.966731 apic_id: 0x06 done.
603 01:48:49.970175 VMX status: enabled
604 01:48:49.970783 VMX status: enabled
605 01:48:49.972876 IA32_FEATURE_CONTROL status: locked
606 01:48:49.976082 IA32_FEATURE_CONTROL status: locked
607 01:48:49.979410 Skip microcode update
608 01:48:49.983047 Skip microcode update
609 01:48:49.983510 CPU #3 initialized
610 01:48:49.986239 CPU #7 initialized
611 01:48:49.989653 IA32_FEATURE_CONTROL status: locked
612 01:48:49.993005 Skip microcode update
613 01:48:49.993470 CPU #2 initialized
614 01:48:49.999509 bsp_do_flight_plan done after 452 msecs.
615 01:48:50.002905 CPU: frequency set to 4200 MHz
616 01:48:50.003374 Enabling SMIs.
617 01:48:50.003739 Locking SMM.
618 01:48:50.019384 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
619 01:48:50.022582 CBFS @ c08000 size 3f8000
620 01:48:50.029177 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
621 01:48:50.029644 CBFS: Locating 'vbt.bin'
622 01:48:50.032370 CBFS: Found @ offset 5f5c0 size 499
623 01:48:50.040056 Found a VBT of 4608 bytes after decompression
624 01:48:50.224056 Display FSP Version Info HOB
625 01:48:50.227349 Reference Code - CPU = 9.0.1e.30
626 01:48:50.230616 uCode Version = 0.0.0.ca
627 01:48:50.233854 TXT ACM version = ff.ff.ff.ffff
628 01:48:50.236904 Display FSP Version Info HOB
629 01:48:50.240493 Reference Code - ME = 9.0.1e.30
630 01:48:50.243885 MEBx version = 0.0.0.0
631 01:48:50.247193 ME Firmware Version = Consumer SKU
632 01:48:50.250173 Display FSP Version Info HOB
633 01:48:50.253571 Reference Code - CML PCH = 9.0.1e.30
634 01:48:50.256876 PCH-CRID Status = Disabled
635 01:48:50.260653 PCH-CRID Original Value = ff.ff.ff.ffff
636 01:48:50.263641 PCH-CRID New Value = ff.ff.ff.ffff
637 01:48:50.266715 OPROM - RST - RAID = ff.ff.ff.ffff
638 01:48:50.270452 ChipsetInit Base Version = ff.ff.ff.ffff
639 01:48:50.273669 ChipsetInit Oem Version = ff.ff.ff.ffff
640 01:48:50.277173 Display FSP Version Info HOB
641 01:48:50.283555 Reference Code - SA - System Agent = 9.0.1e.30
642 01:48:50.286821 Reference Code - MRC = 0.7.1.6c
643 01:48:50.287287 SA - PCIe Version = 9.0.1e.30
644 01:48:50.290036 SA-CRID Status = Disabled
645 01:48:50.293531 SA-CRID Original Value = 0.0.0.c
646 01:48:50.297045 SA-CRID New Value = 0.0.0.c
647 01:48:50.299999 OPROM - VBIOS = ff.ff.ff.ffff
648 01:48:50.300468 RTC Init
649 01:48:50.307198 Set power on after power failure.
650 01:48:50.307664 Disabling Deep S3
651 01:48:50.310814 Disabling Deep S3
652 01:48:50.311279 Disabling Deep S4
653 01:48:50.313468 Disabling Deep S4
654 01:48:50.314015 Disabling Deep S5
655 01:48:50.316652 Disabling Deep S5
656 01:48:50.323601 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 195 exit 1
657 01:48:50.324066 Enumerating buses...
658 01:48:50.330602 Show all devs... Before device enumeration.
659 01:48:50.331069 Root Device: enabled 1
660 01:48:50.333421 CPU_CLUSTER: 0: enabled 1
661 01:48:50.336879 DOMAIN: 0000: enabled 1
662 01:48:50.337339 APIC: 00: enabled 1
663 01:48:50.340394 PCI: 00:00.0: enabled 1
664 01:48:50.343309 PCI: 00:02.0: enabled 1
665 01:48:50.346583 PCI: 00:04.0: enabled 0
666 01:48:50.347116 PCI: 00:05.0: enabled 0
667 01:48:50.350802 PCI: 00:12.0: enabled 1
668 01:48:50.353260 PCI: 00:12.5: enabled 0
669 01:48:50.356619 PCI: 00:12.6: enabled 0
670 01:48:50.357086 PCI: 00:14.0: enabled 1
671 01:48:50.359861 PCI: 00:14.1: enabled 0
672 01:48:50.363635 PCI: 00:14.3: enabled 1
673 01:48:50.366644 PCI: 00:14.5: enabled 0
674 01:48:50.367107 PCI: 00:15.0: enabled 1
675 01:48:50.370659 PCI: 00:15.1: enabled 1
676 01:48:50.374592 PCI: 00:15.2: enabled 0
677 01:48:50.375173 PCI: 00:15.3: enabled 0
678 01:48:50.376835 PCI: 00:16.0: enabled 1
679 01:48:50.379812 PCI: 00:16.1: enabled 0
680 01:48:50.383514 PCI: 00:16.2: enabled 0
681 01:48:50.383979 PCI: 00:16.3: enabled 0
682 01:48:50.386933 PCI: 00:16.4: enabled 0
683 01:48:50.390199 PCI: 00:16.5: enabled 0
684 01:48:50.393971 PCI: 00:17.0: enabled 1
685 01:48:50.394430 PCI: 00:19.0: enabled 1
686 01:48:50.396914 PCI: 00:19.1: enabled 0
687 01:48:50.400232 PCI: 00:19.2: enabled 0
688 01:48:50.403148 PCI: 00:1a.0: enabled 0
689 01:48:50.403609 PCI: 00:1c.0: enabled 0
690 01:48:50.406877 PCI: 00:1c.1: enabled 0
691 01:48:50.410800 PCI: 00:1c.2: enabled 0
692 01:48:50.411370 PCI: 00:1c.3: enabled 0
693 01:48:50.413245 PCI: 00:1c.4: enabled 0
694 01:48:50.416992 PCI: 00:1c.5: enabled 0
695 01:48:50.419944 PCI: 00:1c.6: enabled 0
696 01:48:50.420423 PCI: 00:1c.7: enabled 0
697 01:48:50.423574 PCI: 00:1d.0: enabled 1
698 01:48:50.427119 PCI: 00:1d.1: enabled 0
699 01:48:50.430278 PCI: 00:1d.2: enabled 0
700 01:48:50.431018 PCI: 00:1d.3: enabled 0
701 01:48:50.432993 PCI: 00:1d.4: enabled 0
702 01:48:50.436635 PCI: 00:1d.5: enabled 1
703 01:48:50.439893 PCI: 00:1e.0: enabled 1
704 01:48:50.440359 PCI: 00:1e.1: enabled 0
705 01:48:50.443209 PCI: 00:1e.2: enabled 1
706 01:48:50.446480 PCI: 00:1e.3: enabled 1
707 01:48:50.447006 PCI: 00:1f.0: enabled 1
708 01:48:50.449691 PCI: 00:1f.1: enabled 1
709 01:48:50.453201 PCI: 00:1f.2: enabled 1
710 01:48:50.456187 PCI: 00:1f.3: enabled 1
711 01:48:50.456654 PCI: 00:1f.4: enabled 1
712 01:48:50.459719 PCI: 00:1f.5: enabled 1
713 01:48:50.463098 PCI: 00:1f.6: enabled 0
714 01:48:50.466419 USB0 port 0: enabled 1
715 01:48:50.466934 I2C: 00:15: enabled 1
716 01:48:50.469586 I2C: 00:5d: enabled 1
717 01:48:50.473448 GENERIC: 0.0: enabled 1
718 01:48:50.474108 I2C: 00:1a: enabled 1
719 01:48:50.476404 I2C: 00:38: enabled 1
720 01:48:50.479666 I2C: 00:39: enabled 1
721 01:48:50.480171 I2C: 00:3a: enabled 1
722 01:48:50.483200 I2C: 00:3b: enabled 1
723 01:48:50.486291 PCI: 00:00.0: enabled 1
724 01:48:50.486798 SPI: 00: enabled 1
725 01:48:50.489305 SPI: 01: enabled 1
726 01:48:50.492924 PNP: 0c09.0: enabled 1
727 01:48:50.493487 USB2 port 0: enabled 1
728 01:48:50.495962 USB2 port 1: enabled 1
729 01:48:50.499572 USB2 port 2: enabled 0
730 01:48:50.500042 USB2 port 3: enabled 0
731 01:48:50.502620 USB2 port 5: enabled 0
732 01:48:50.506435 USB2 port 6: enabled 1
733 01:48:50.509331 USB2 port 9: enabled 1
734 01:48:50.509887 USB3 port 0: enabled 1
735 01:48:50.513094 USB3 port 1: enabled 1
736 01:48:50.516106 USB3 port 2: enabled 1
737 01:48:50.516578 USB3 port 3: enabled 1
738 01:48:50.519310 USB3 port 4: enabled 0
739 01:48:50.522517 APIC: 02: enabled 1
740 01:48:50.523015 APIC: 01: enabled 1
741 01:48:50.526323 APIC: 07: enabled 1
742 01:48:50.529612 APIC: 03: enabled 1
743 01:48:50.530179 APIC: 04: enabled 1
744 01:48:50.532612 APIC: 05: enabled 1
745 01:48:50.533082 APIC: 06: enabled 1
746 01:48:50.535932 Compare with tree...
747 01:48:50.539296 Root Device: enabled 1
748 01:48:50.542860 CPU_CLUSTER: 0: enabled 1
749 01:48:50.543400 APIC: 00: enabled 1
750 01:48:50.546045 APIC: 02: enabled 1
751 01:48:50.549405 APIC: 01: enabled 1
752 01:48:50.549944 APIC: 07: enabled 1
753 01:48:50.552872 APIC: 03: enabled 1
754 01:48:50.556056 APIC: 04: enabled 1
755 01:48:50.556522 APIC: 05: enabled 1
756 01:48:50.559289 APIC: 06: enabled 1
757 01:48:50.562281 DOMAIN: 0000: enabled 1
758 01:48:50.565640 PCI: 00:00.0: enabled 1
759 01:48:50.566081 PCI: 00:02.0: enabled 1
760 01:48:50.569128 PCI: 00:04.0: enabled 0
761 01:48:50.572216 PCI: 00:05.0: enabled 0
762 01:48:50.575560 PCI: 00:12.0: enabled 1
763 01:48:50.579030 PCI: 00:12.5: enabled 0
764 01:48:50.579496 PCI: 00:12.6: enabled 0
765 01:48:50.582364 PCI: 00:14.0: enabled 1
766 01:48:50.585395 USB0 port 0: enabled 1
767 01:48:50.588919 USB2 port 0: enabled 1
768 01:48:50.592385 USB2 port 1: enabled 1
769 01:48:50.592955 USB2 port 2: enabled 0
770 01:48:50.595693 USB2 port 3: enabled 0
771 01:48:50.598648 USB2 port 5: enabled 0
772 01:48:50.602069 USB2 port 6: enabled 1
773 01:48:50.605792 USB2 port 9: enabled 1
774 01:48:50.606323 USB3 port 0: enabled 1
775 01:48:50.608726 USB3 port 1: enabled 1
776 01:48:50.612115 USB3 port 2: enabled 1
777 01:48:50.615473 USB3 port 3: enabled 1
778 01:48:50.618644 USB3 port 4: enabled 0
779 01:48:50.622746 PCI: 00:14.1: enabled 0
780 01:48:50.623313 PCI: 00:14.3: enabled 1
781 01:48:50.625798 PCI: 00:14.5: enabled 0
782 01:48:50.628820 PCI: 00:15.0: enabled 1
783 01:48:50.632049 I2C: 00:15: enabled 1
784 01:48:50.632514 PCI: 00:15.1: enabled 1
785 01:48:50.635676 I2C: 00:5d: enabled 1
786 01:48:50.638890 GENERIC: 0.0: enabled 1
787 01:48:50.642160 PCI: 00:15.2: enabled 0
788 01:48:50.645321 PCI: 00:15.3: enabled 0
789 01:48:50.645786 PCI: 00:16.0: enabled 1
790 01:48:50.648756 PCI: 00:16.1: enabled 0
791 01:48:50.652026 PCI: 00:16.2: enabled 0
792 01:48:50.655265 PCI: 00:16.3: enabled 0
793 01:48:50.658650 PCI: 00:16.4: enabled 0
794 01:48:50.659209 PCI: 00:16.5: enabled 0
795 01:48:50.662010 PCI: 00:17.0: enabled 1
796 01:48:50.665426 PCI: 00:19.0: enabled 1
797 01:48:50.668686 I2C: 00:1a: enabled 1
798 01:48:50.669232 I2C: 00:38: enabled 1
799 01:48:50.672574 I2C: 00:39: enabled 1
800 01:48:50.675546 I2C: 00:3a: enabled 1
801 01:48:50.678587 I2C: 00:3b: enabled 1
802 01:48:50.682475 PCI: 00:19.1: enabled 0
803 01:48:50.682989 PCI: 00:19.2: enabled 0
804 01:48:50.685227 PCI: 00:1a.0: enabled 0
805 01:48:50.688591 PCI: 00:1c.0: enabled 0
806 01:48:50.691892 PCI: 00:1c.1: enabled 0
807 01:48:50.692363 PCI: 00:1c.2: enabled 0
808 01:48:50.695161 PCI: 00:1c.3: enabled 0
809 01:48:50.698617 PCI: 00:1c.4: enabled 0
810 01:48:50.701713 PCI: 00:1c.5: enabled 0
811 01:48:50.705400 PCI: 00:1c.6: enabled 0
812 01:48:50.705885 PCI: 00:1c.7: enabled 0
813 01:48:50.708337 PCI: 00:1d.0: enabled 1
814 01:48:50.711747 PCI: 00:1d.1: enabled 0
815 01:48:50.715334 PCI: 00:1d.2: enabled 0
816 01:48:50.718517 PCI: 00:1d.3: enabled 0
817 01:48:50.719021 PCI: 00:1d.4: enabled 0
818 01:48:50.721862 PCI: 00:1d.5: enabled 1
819 01:48:50.725154 PCI: 00:00.0: enabled 1
820 01:48:50.728653 PCI: 00:1e.0: enabled 1
821 01:48:50.731936 PCI: 00:1e.1: enabled 0
822 01:48:50.732415 PCI: 00:1e.2: enabled 1
823 01:48:50.734952 SPI: 00: enabled 1
824 01:48:50.738415 PCI: 00:1e.3: enabled 1
825 01:48:50.741766 SPI: 01: enabled 1
826 01:48:50.742308 PCI: 00:1f.0: enabled 1
827 01:48:50.745350 PNP: 0c09.0: enabled 1
828 01:48:50.748415 PCI: 00:1f.1: enabled 1
829 01:48:50.751448 PCI: 00:1f.2: enabled 1
830 01:48:50.754956 PCI: 00:1f.3: enabled 1
831 01:48:50.755504 PCI: 00:1f.4: enabled 1
832 01:48:50.758231 PCI: 00:1f.5: enabled 1
833 01:48:50.761548 PCI: 00:1f.6: enabled 0
834 01:48:50.764567 Root Device scanning...
835 01:48:50.768129 scan_static_bus for Root Device
836 01:48:50.768602 CPU_CLUSTER: 0 enabled
837 01:48:50.772080 DOMAIN: 0000 enabled
838 01:48:50.775239 DOMAIN: 0000 scanning...
839 01:48:50.778267 PCI: pci_scan_bus for bus 00
840 01:48:50.782256 PCI: 00:00.0 [8086/0000] ops
841 01:48:50.784391 PCI: 00:00.0 [8086/9b61] enabled
842 01:48:50.787952 PCI: 00:02.0 [8086/0000] bus ops
843 01:48:50.791445 PCI: 00:02.0 [8086/9b41] enabled
844 01:48:50.794764 PCI: 00:04.0 [8086/1903] disabled
845 01:48:50.798205 PCI: 00:08.0 [8086/1911] enabled
846 01:48:50.801699 PCI: 00:12.0 [8086/02f9] enabled
847 01:48:50.804677 PCI: 00:14.0 [8086/0000] bus ops
848 01:48:50.808520 PCI: 00:14.0 [8086/02ed] enabled
849 01:48:50.811504 PCI: 00:14.2 [8086/02ef] enabled
850 01:48:50.814852 PCI: 00:14.3 [8086/02f0] enabled
851 01:48:50.817941 PCI: 00:15.0 [8086/0000] bus ops
852 01:48:50.821581 PCI: 00:15.0 [8086/02e8] enabled
853 01:48:50.824721 PCI: 00:15.1 [8086/0000] bus ops
854 01:48:50.827816 PCI: 00:15.1 [8086/02e9] enabled
855 01:48:50.830928 PCI: 00:16.0 [8086/0000] ops
856 01:48:50.834665 PCI: 00:16.0 [8086/02e0] enabled
857 01:48:50.838130 PCI: 00:17.0 [8086/0000] ops
858 01:48:50.841359 PCI: 00:17.0 [8086/02d3] enabled
859 01:48:50.844613 PCI: 00:19.0 [8086/0000] bus ops
860 01:48:50.848085 PCI: 00:19.0 [8086/02c5] enabled
861 01:48:50.850961 PCI: 00:1d.0 [8086/0000] bus ops
862 01:48:50.854568 PCI: 00:1d.0 [8086/02b0] enabled
863 01:48:50.858230 PCI: Static device PCI: 00:1d.5 not found, disabling it.
864 01:48:50.861310 PCI: 00:1e.0 [8086/0000] ops
865 01:48:50.864149 PCI: 00:1e.0 [8086/02a8] enabled
866 01:48:50.867634 PCI: 00:1e.2 [8086/0000] bus ops
867 01:48:50.870950 PCI: 00:1e.2 [8086/02aa] enabled
868 01:48:50.874604 PCI: 00:1e.3 [8086/0000] bus ops
869 01:48:50.877851 PCI: 00:1e.3 [8086/02ab] enabled
870 01:48:50.881018 PCI: 00:1f.0 [8086/0000] bus ops
871 01:48:50.884469 PCI: 00:1f.0 [8086/0284] enabled
872 01:48:50.891051 PCI: Static device PCI: 00:1f.1 not found, disabling it.
873 01:48:50.898061 PCI: Static device PCI: 00:1f.2 not found, disabling it.
874 01:48:50.901184 PCI: 00:1f.3 [8086/0000] bus ops
875 01:48:50.904400 PCI: 00:1f.3 [8086/02c8] enabled
876 01:48:50.907619 PCI: 00:1f.4 [8086/0000] bus ops
877 01:48:50.911227 PCI: 00:1f.4 [8086/02a3] enabled
878 01:48:50.914174 PCI: 00:1f.5 [8086/0000] bus ops
879 01:48:50.917501 PCI: 00:1f.5 [8086/02a4] enabled
880 01:48:50.918093 PCI: Leftover static devices:
881 01:48:50.921167 PCI: 00:05.0
882 01:48:50.921730 PCI: 00:12.5
883 01:48:50.924289 PCI: 00:12.6
884 01:48:50.924859 PCI: 00:14.1
885 01:48:50.927424 PCI: 00:14.5
886 01:48:50.928045 PCI: 00:15.2
887 01:48:50.928427 PCI: 00:15.3
888 01:48:50.930686 PCI: 00:16.1
889 01:48:50.931153 PCI: 00:16.2
890 01:48:50.933959 PCI: 00:16.3
891 01:48:50.934423 PCI: 00:16.4
892 01:48:50.934843 PCI: 00:16.5
893 01:48:50.937738 PCI: 00:19.1
894 01:48:50.938201 PCI: 00:19.2
895 01:48:50.941407 PCI: 00:1a.0
896 01:48:50.942023 PCI: 00:1c.0
897 01:48:50.942397 PCI: 00:1c.1
898 01:48:50.943867 PCI: 00:1c.2
899 01:48:50.944332 PCI: 00:1c.3
900 01:48:50.947017 PCI: 00:1c.4
901 01:48:50.947482 PCI: 00:1c.5
902 01:48:50.951147 PCI: 00:1c.6
903 01:48:50.951712 PCI: 00:1c.7
904 01:48:50.952085 PCI: 00:1d.1
905 01:48:50.954406 PCI: 00:1d.2
906 01:48:50.955019 PCI: 00:1d.3
907 01:48:50.957282 PCI: 00:1d.4
908 01:48:50.957847 PCI: 00:1d.5
909 01:48:50.958216 PCI: 00:1e.1
910 01:48:50.960562 PCI: 00:1f.1
911 01:48:50.961127 PCI: 00:1f.2
912 01:48:50.963837 PCI: 00:1f.6
913 01:48:50.967572 PCI: Check your devicetree.cb.
914 01:48:50.968038 PCI: 00:02.0 scanning...
915 01:48:50.971024 scan_generic_bus for PCI: 00:02.0
916 01:48:50.977662 scan_generic_bus for PCI: 00:02.0 done
917 01:48:50.981129 scan_bus: scanning of bus PCI: 00:02.0 took 10196 usecs
918 01:48:50.983694 PCI: 00:14.0 scanning...
919 01:48:50.987331 scan_static_bus for PCI: 00:14.0
920 01:48:50.990973 USB0 port 0 enabled
921 01:48:50.991538 USB0 port 0 scanning...
922 01:48:50.994257 scan_static_bus for USB0 port 0
923 01:48:50.997908 USB2 port 0 enabled
924 01:48:51.001127 USB2 port 1 enabled
925 01:48:51.001689 USB2 port 2 disabled
926 01:48:51.004273 USB2 port 3 disabled
927 01:48:51.007177 USB2 port 5 disabled
928 01:48:51.007641 USB2 port 6 enabled
929 01:48:51.010764 USB2 port 9 enabled
930 01:48:51.013942 USB3 port 0 enabled
931 01:48:51.014406 USB3 port 1 enabled
932 01:48:51.017236 USB3 port 2 enabled
933 01:48:51.017795 USB3 port 3 enabled
934 01:48:51.020786 USB3 port 4 disabled
935 01:48:51.023956 USB2 port 0 scanning...
936 01:48:51.027326 scan_static_bus for USB2 port 0
937 01:48:51.030582 scan_static_bus for USB2 port 0 done
938 01:48:51.037096 scan_bus: scanning of bus USB2 port 0 took 9690 usecs
939 01:48:51.037635 USB2 port 1 scanning...
940 01:48:51.040811 scan_static_bus for USB2 port 1
941 01:48:51.043765 scan_static_bus for USB2 port 1 done
942 01:48:51.050580 scan_bus: scanning of bus USB2 port 1 took 9700 usecs
943 01:48:51.054078 USB2 port 6 scanning...
944 01:48:51.056948 scan_static_bus for USB2 port 6
945 01:48:51.060466 scan_static_bus for USB2 port 6 done
946 01:48:51.067007 scan_bus: scanning of bus USB2 port 6 took 9707 usecs
947 01:48:51.067655 USB2 port 9 scanning...
948 01:48:51.070325 scan_static_bus for USB2 port 9
949 01:48:51.073774 scan_static_bus for USB2 port 9 done
950 01:48:51.080457 scan_bus: scanning of bus USB2 port 9 took 9692 usecs
951 01:48:51.083663 USB3 port 0 scanning...
952 01:48:51.087051 scan_static_bus for USB3 port 0
953 01:48:51.090318 scan_static_bus for USB3 port 0 done
954 01:48:51.096602 scan_bus: scanning of bus USB3 port 0 took 9700 usecs
955 01:48:51.097069 USB3 port 1 scanning...
956 01:48:51.100637 scan_static_bus for USB3 port 1
957 01:48:51.106579 scan_static_bus for USB3 port 1 done
958 01:48:51.110062 scan_bus: scanning of bus USB3 port 1 took 9709 usecs
959 01:48:51.113883 USB3 port 2 scanning...
960 01:48:51.116587 scan_static_bus for USB3 port 2
961 01:48:51.119966 scan_static_bus for USB3 port 2 done
962 01:48:51.126819 scan_bus: scanning of bus USB3 port 2 took 9710 usecs
963 01:48:51.127286 USB3 port 3 scanning...
964 01:48:51.130297 scan_static_bus for USB3 port 3
965 01:48:51.136586 scan_static_bus for USB3 port 3 done
966 01:48:51.140560 scan_bus: scanning of bus USB3 port 3 took 9698 usecs
967 01:48:51.143106 scan_static_bus for USB0 port 0 done
968 01:48:51.150727 scan_bus: scanning of bus USB0 port 0 took 155440 usecs
969 01:48:51.153107 scan_static_bus for PCI: 00:14.0 done
970 01:48:51.159897 scan_bus: scanning of bus PCI: 00:14.0 took 173104 usecs
971 01:48:51.162861 PCI: 00:15.0 scanning...
972 01:48:51.166429 scan_generic_bus for PCI: 00:15.0
973 01:48:51.169899 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
974 01:48:51.173313 scan_generic_bus for PCI: 00:15.0 done
975 01:48:51.179427 scan_bus: scanning of bus PCI: 00:15.0 took 14310 usecs
976 01:48:51.183115 PCI: 00:15.1 scanning...
977 01:48:51.186351 scan_generic_bus for PCI: 00:15.1
978 01:48:51.189553 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
979 01:48:51.193182 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
980 01:48:51.197061 scan_generic_bus for PCI: 00:15.1 done
981 01:48:51.202824 scan_bus: scanning of bus PCI: 00:15.1 took 18615 usecs
982 01:48:51.207000 PCI: 00:19.0 scanning...
983 01:48:51.209343 scan_generic_bus for PCI: 00:19.0
984 01:48:51.212784 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
985 01:48:51.216312 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
986 01:48:51.223003 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
987 01:48:51.226370 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
988 01:48:51.229444 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
989 01:48:51.233024 scan_generic_bus for PCI: 00:19.0 done
990 01:48:51.239525 scan_bus: scanning of bus PCI: 00:19.0 took 30755 usecs
991 01:48:51.242768 PCI: 00:1d.0 scanning...
992 01:48:51.246173 do_pci_scan_bridge for PCI: 00:1d.0
993 01:48:51.249631 PCI: pci_scan_bus for bus 01
994 01:48:51.252824 PCI: 01:00.0 [1c5c/1327] enabled
995 01:48:51.256624 Enabling Common Clock Configuration
996 01:48:51.259484 L1 Sub-State supported from root port 29
997 01:48:51.262359 L1 Sub-State Support = 0xf
998 01:48:51.266238 CommonModeRestoreTime = 0x28
999 01:48:51.268854 Power On Value = 0x16, Power On Scale = 0x0
1000 01:48:51.272847 ASPM: Enabled L1
1001 01:48:51.279206 scan_bus: scanning of bus PCI: 00:1d.0 took 32790 usecs
1002 01:48:51.279680 PCI: 00:1e.2 scanning...
1003 01:48:51.282506 scan_generic_bus for PCI: 00:1e.2
1004 01:48:51.289305 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1005 01:48:51.292246 scan_generic_bus for PCI: 00:1e.2 done
1006 01:48:51.295695 scan_bus: scanning of bus PCI: 00:1e.2 took 13999 usecs
1007 01:48:51.299138 PCI: 00:1e.3 scanning...
1008 01:48:51.302137 scan_generic_bus for PCI: 00:1e.3
1009 01:48:51.306445 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1010 01:48:51.312097 scan_generic_bus for PCI: 00:1e.3 done
1011 01:48:51.315910 scan_bus: scanning of bus PCI: 00:1e.3 took 14007 usecs
1012 01:48:51.319304 PCI: 00:1f.0 scanning...
1013 01:48:51.322061 scan_static_bus for PCI: 00:1f.0
1014 01:48:51.325613 PNP: 0c09.0 enabled
1015 01:48:51.328928 scan_static_bus for PCI: 00:1f.0 done
1016 01:48:51.335561 scan_bus: scanning of bus PCI: 00:1f.0 took 12049 usecs
1017 01:48:51.336130 PCI: 00:1f.3 scanning...
1018 01:48:51.342499 scan_bus: scanning of bus PCI: 00:1f.3 took 2860 usecs
1019 01:48:51.345884 PCI: 00:1f.4 scanning...
1020 01:48:51.349038 scan_generic_bus for PCI: 00:1f.4
1021 01:48:51.352232 scan_generic_bus for PCI: 00:1f.4 done
1022 01:48:51.359310 scan_bus: scanning of bus PCI: 00:1f.4 took 10179 usecs
1023 01:48:51.361928 PCI: 00:1f.5 scanning...
1024 01:48:51.365233 scan_generic_bus for PCI: 00:1f.5
1025 01:48:51.368271 scan_generic_bus for PCI: 00:1f.5 done
1026 01:48:51.372685 scan_bus: scanning of bus PCI: 00:1f.5 took 10188 usecs
1027 01:48:51.378919 scan_bus: scanning of bus DOMAIN: 0000 took 605213 usecs
1028 01:48:51.381797 scan_static_bus for Root Device done
1029 01:48:51.388720 scan_bus: scanning of bus Root Device took 625092 usecs
1030 01:48:51.389181 done
1031 01:48:51.392556 Chrome EC: UHEPI supported
1032 01:48:51.398888 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1033 01:48:51.405969 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1034 01:48:51.411954 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1035 01:48:51.418442 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1036 01:48:51.421646 SPI flash protection: WPSW=0 SRP0=0
1037 01:48:51.425709 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1038 01:48:51.431781 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 10 exit 2
1039 01:48:51.435484 found VGA at PCI: 00:02.0
1040 01:48:51.438712 Setting up VGA for PCI: 00:02.0
1041 01:48:51.441941 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1042 01:48:51.448792 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1043 01:48:51.449360 Allocating resources...
1044 01:48:51.451574 Reading resources...
1045 01:48:51.455477 Root Device read_resources bus 0 link: 0
1046 01:48:51.461815 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1047 01:48:51.464828 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1048 01:48:51.471434 DOMAIN: 0000 read_resources bus 0 link: 0
1049 01:48:51.474984 PCI: 00:14.0 read_resources bus 0 link: 0
1050 01:48:51.481619 USB0 port 0 read_resources bus 0 link: 0
1051 01:48:51.488694 USB0 port 0 read_resources bus 0 link: 0 done
1052 01:48:51.491909 PCI: 00:14.0 read_resources bus 0 link: 0 done
1053 01:48:51.499095 PCI: 00:15.0 read_resources bus 1 link: 0
1054 01:48:51.502587 PCI: 00:15.0 read_resources bus 1 link: 0 done
1055 01:48:51.509450 PCI: 00:15.1 read_resources bus 2 link: 0
1056 01:48:51.512743 PCI: 00:15.1 read_resources bus 2 link: 0 done
1057 01:48:51.520121 PCI: 00:19.0 read_resources bus 3 link: 0
1058 01:48:51.526408 PCI: 00:19.0 read_resources bus 3 link: 0 done
1059 01:48:51.529809 PCI: 00:1d.0 read_resources bus 1 link: 0
1060 01:48:51.536343 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1061 01:48:51.540284 PCI: 00:1e.2 read_resources bus 4 link: 0
1062 01:48:51.546920 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1063 01:48:51.550893 PCI: 00:1e.3 read_resources bus 5 link: 0
1064 01:48:51.556786 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1065 01:48:51.560285 PCI: 00:1f.0 read_resources bus 0 link: 0
1066 01:48:51.566924 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1067 01:48:51.573226 DOMAIN: 0000 read_resources bus 0 link: 0 done
1068 01:48:51.576693 Root Device read_resources bus 0 link: 0 done
1069 01:48:51.579915 Done reading resources.
1070 01:48:51.583188 Show resources in subtree (Root Device)...After reading.
1071 01:48:51.589945 Root Device child on link 0 CPU_CLUSTER: 0
1072 01:48:51.593709 CPU_CLUSTER: 0 child on link 0 APIC: 00
1073 01:48:51.594268 APIC: 00
1074 01:48:51.596653 APIC: 02
1075 01:48:51.597205 APIC: 01
1076 01:48:51.600298 APIC: 07
1077 01:48:51.600852 APIC: 03
1078 01:48:51.601214 APIC: 04
1079 01:48:51.603216 APIC: 05
1080 01:48:51.603721 APIC: 06
1081 01:48:51.606474 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1082 01:48:51.616055 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1083 01:48:51.666973 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1084 01:48:51.667521 PCI: 00:00.0
1085 01:48:51.667953 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1086 01:48:51.668816 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1087 01:48:51.669599 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1088 01:48:51.670047 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1089 01:48:51.716043 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1090 01:48:51.716747 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1091 01:48:51.717307 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1092 01:48:51.717787 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1093 01:48:51.718267 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1094 01:48:51.727924 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1095 01:48:51.731583 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1096 01:48:51.741731 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1097 01:48:51.751570 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1098 01:48:51.761563 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1099 01:48:51.768011 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1100 01:48:51.777835 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1101 01:48:51.781365 PCI: 00:02.0
1102 01:48:51.790908 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1103 01:48:51.801141 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1104 01:48:51.807904 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1105 01:48:51.810911 PCI: 00:04.0
1106 01:48:51.811145 PCI: 00:08.0
1107 01:48:51.820613 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1108 01:48:51.824122 PCI: 00:12.0
1109 01:48:51.834422 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1110 01:48:51.837837 PCI: 00:14.0 child on link 0 USB0 port 0
1111 01:48:51.847068 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1112 01:48:51.851128 USB0 port 0 child on link 0 USB2 port 0
1113 01:48:51.854076 USB2 port 0
1114 01:48:51.856840 USB2 port 1
1115 01:48:51.856925 USB2 port 2
1116 01:48:51.860169 USB2 port 3
1117 01:48:51.860253 USB2 port 5
1118 01:48:51.863604 USB2 port 6
1119 01:48:51.863690 USB2 port 9
1120 01:48:51.867253 USB3 port 0
1121 01:48:51.867337 USB3 port 1
1122 01:48:51.870278 USB3 port 2
1123 01:48:51.870358 USB3 port 3
1124 01:48:51.873707 USB3 port 4
1125 01:48:51.873789 PCI: 00:14.2
1126 01:48:51.883594 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1127 01:48:51.893282 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1128 01:48:51.896658 PCI: 00:14.3
1129 01:48:51.906566 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1130 01:48:51.910155 PCI: 00:15.0 child on link 0 I2C: 01:15
1131 01:48:51.919938 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1132 01:48:51.923427 I2C: 01:15
1133 01:48:51.926814 PCI: 00:15.1 child on link 0 I2C: 02:5d
1134 01:48:51.936509 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1135 01:48:51.936608 I2C: 02:5d
1136 01:48:51.940071 GENERIC: 0.0
1137 01:48:51.940156 PCI: 00:16.0
1138 01:48:51.949928 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1139 01:48:51.953227 PCI: 00:17.0
1140 01:48:51.963250 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1141 01:48:51.969941 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1142 01:48:51.980138 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1143 01:48:51.986481 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1144 01:48:51.996272 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1145 01:48:52.002742 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1146 01:48:52.009556 PCI: 00:19.0 child on link 0 I2C: 03:1a
1147 01:48:52.020060 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1148 01:48:52.020156 I2C: 03:1a
1149 01:48:52.022806 I2C: 03:38
1150 01:48:52.022887 I2C: 03:39
1151 01:48:52.026073 I2C: 03:3a
1152 01:48:52.026152 I2C: 03:3b
1153 01:48:52.029694 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1154 01:48:52.039865 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1155 01:48:52.049483 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1156 01:48:52.059721 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1157 01:48:52.059881 PCI: 01:00.0
1158 01:48:52.069348 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1159 01:48:52.074082 PCI: 00:1e.0
1160 01:48:52.082900 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1161 01:48:52.092948 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1162 01:48:52.095998 PCI: 00:1e.2 child on link 0 SPI: 00
1163 01:48:52.106868 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1164 01:48:52.109695 SPI: 00
1165 01:48:52.112782 PCI: 00:1e.3 child on link 0 SPI: 01
1166 01:48:52.122912 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1167 01:48:52.123469 SPI: 01
1168 01:48:52.129327 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1169 01:48:52.136190 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1170 01:48:52.145970 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1171 01:48:52.146428 PNP: 0c09.0
1172 01:48:52.155605 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1173 01:48:52.159053 PCI: 00:1f.3
1174 01:48:52.168695 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1175 01:48:52.179079 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1176 01:48:52.179621 PCI: 00:1f.4
1177 01:48:52.188857 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1178 01:48:52.199407 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1179 01:48:52.199831 PCI: 00:1f.5
1180 01:48:52.209394 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1181 01:48:52.215703 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1182 01:48:52.222814 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1183 01:48:52.228921 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1184 01:48:52.231989 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1185 01:48:52.235781 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1186 01:48:52.239290 PCI: 00:17.0 18 * [0x60 - 0x67] io
1187 01:48:52.242008 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1188 01:48:52.249980 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1189 01:48:52.255362 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1190 01:48:52.265076 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1191 01:48:52.271863 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1192 01:48:52.278272 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1193 01:48:52.282280 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1194 01:48:52.291577 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1195 01:48:52.295005 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1196 01:48:52.301833 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1197 01:48:52.305091 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1198 01:48:52.311304 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1199 01:48:52.315278 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1200 01:48:52.321920 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1201 01:48:52.325238 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1202 01:48:52.328557 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1203 01:48:52.335231 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1204 01:48:52.338991 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1205 01:48:52.344897 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1206 01:48:52.348522 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1207 01:48:52.355451 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1208 01:48:52.358184 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1209 01:48:52.364990 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1210 01:48:52.368235 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1211 01:48:52.374739 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1212 01:48:52.378254 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1213 01:48:52.385025 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1214 01:48:52.388122 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1215 01:48:52.394731 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1216 01:48:52.398256 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1217 01:48:52.401389 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1218 01:48:52.411180 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1219 01:48:52.414409 avoid_fixed_resources: DOMAIN: 0000
1220 01:48:52.421044 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1221 01:48:52.428007 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1222 01:48:52.434912 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1223 01:48:52.440810 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1224 01:48:52.450860 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1225 01:48:52.458208 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1226 01:48:52.464062 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1227 01:48:52.473930 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1228 01:48:52.481175 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1229 01:48:52.487437 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1230 01:48:52.493947 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1231 01:48:52.504034 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1232 01:48:52.504584 Setting resources...
1233 01:48:52.510869 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1234 01:48:52.513976 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1235 01:48:52.520699 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1236 01:48:52.523888 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1237 01:48:52.527097 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1238 01:48:52.534092 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1239 01:48:52.540149 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1240 01:48:52.547313 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1241 01:48:52.553800 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1242 01:48:52.561579 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1243 01:48:52.564236 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1244 01:48:52.566996 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1245 01:48:52.573674 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1246 01:48:52.577151 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1247 01:48:52.583353 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1248 01:48:52.587063 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1249 01:48:52.593904 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1250 01:48:52.596820 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1251 01:48:52.603738 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1252 01:48:52.607818 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1253 01:48:52.613566 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1254 01:48:52.616813 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1255 01:48:52.623742 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1256 01:48:52.626582 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1257 01:48:52.630439 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1258 01:48:52.636824 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1259 01:48:52.639931 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1260 01:48:52.646863 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1261 01:48:52.650219 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1262 01:48:52.656979 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1263 01:48:52.659726 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1264 01:48:52.666741 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1265 01:48:52.673927 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1266 01:48:52.679925 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1267 01:48:52.686479 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1268 01:48:52.696487 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1269 01:48:52.699917 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1270 01:48:52.706143 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1271 01:48:52.712855 Root Device assign_resources, bus 0 link: 0
1272 01:48:52.716181 DOMAIN: 0000 assign_resources, bus 0 link: 0
1273 01:48:52.725914 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1274 01:48:52.732705 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1275 01:48:52.742788 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1276 01:48:52.749484 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1277 01:48:52.759160 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1278 01:48:52.765852 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1279 01:48:52.768932 PCI: 00:14.0 assign_resources, bus 0 link: 0
1280 01:48:52.776026 PCI: 00:14.0 assign_resources, bus 0 link: 0
1281 01:48:52.782462 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1282 01:48:52.792288 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1283 01:48:52.799171 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1284 01:48:52.808882 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1285 01:48:52.812927 PCI: 00:15.0 assign_resources, bus 1 link: 0
1286 01:48:52.818690 PCI: 00:15.0 assign_resources, bus 1 link: 0
1287 01:48:52.825355 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1288 01:48:52.828942 PCI: 00:15.1 assign_resources, bus 2 link: 0
1289 01:48:52.835615 PCI: 00:15.1 assign_resources, bus 2 link: 0
1290 01:48:52.842045 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1291 01:48:52.852164 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1292 01:48:52.858473 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1293 01:48:52.865262 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1294 01:48:52.875218 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1295 01:48:52.882101 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1296 01:48:52.888511 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1297 01:48:52.898435 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1298 01:48:52.901744 PCI: 00:19.0 assign_resources, bus 3 link: 0
1299 01:48:52.908374 PCI: 00:19.0 assign_resources, bus 3 link: 0
1300 01:48:52.914946 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1301 01:48:52.924929 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1302 01:48:52.934791 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1303 01:48:52.938945 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1304 01:48:52.944961 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1305 01:48:52.951462 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1306 01:48:52.957890 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1307 01:48:52.968099 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1308 01:48:52.971444 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1309 01:48:52.977883 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1310 01:48:52.984441 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1311 01:48:52.988106 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1312 01:48:52.994897 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1313 01:48:52.998438 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1314 01:48:53.005110 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1315 01:48:53.008019 LPC: Trying to open IO window from 800 size 1ff
1316 01:48:53.018086 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1317 01:48:53.025133 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1318 01:48:53.034245 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1319 01:48:53.041634 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1320 01:48:53.048772 DOMAIN: 0000 assign_resources, bus 0 link: 0
1321 01:48:53.051076 Root Device assign_resources, bus 0 link: 0
1322 01:48:53.054451 Done setting resources.
1323 01:48:53.061204 Show resources in subtree (Root Device)...After assigning values.
1324 01:48:53.064284 Root Device child on link 0 CPU_CLUSTER: 0
1325 01:48:53.067901 CPU_CLUSTER: 0 child on link 0 APIC: 00
1326 01:48:53.071381 APIC: 00
1327 01:48:53.071793 APIC: 02
1328 01:48:53.072117 APIC: 01
1329 01:48:53.074336 APIC: 07
1330 01:48:53.074798 APIC: 03
1331 01:48:53.077573 APIC: 04
1332 01:48:53.077994 APIC: 05
1333 01:48:53.078319 APIC: 06
1334 01:48:53.084223 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1335 01:48:53.093721 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1336 01:48:53.103550 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1337 01:48:53.103683 PCI: 00:00.0
1338 01:48:53.113354 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1339 01:48:53.124064 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1340 01:48:53.133102 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1341 01:48:53.143412 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1342 01:48:53.153385 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1343 01:48:53.163052 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1344 01:48:53.169494 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1345 01:48:53.179556 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1346 01:48:53.189437 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1347 01:48:53.199163 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1348 01:48:53.209448 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1349 01:48:53.216026 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1350 01:48:53.225566 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1351 01:48:53.236292 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1352 01:48:53.245390 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1353 01:48:53.255262 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1354 01:48:53.255388 PCI: 00:02.0
1355 01:48:53.268514 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1356 01:48:53.279059 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1357 01:48:53.288676 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1358 01:48:53.288764 PCI: 00:04.0
1359 01:48:53.291994 PCI: 00:08.0
1360 01:48:53.302241 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1361 01:48:53.302327 PCI: 00:12.0
1362 01:48:53.311941 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1363 01:48:53.318257 PCI: 00:14.0 child on link 0 USB0 port 0
1364 01:48:53.328066 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1365 01:48:53.331469 USB0 port 0 child on link 0 USB2 port 0
1366 01:48:53.334835 USB2 port 0
1367 01:48:53.334943 USB2 port 1
1368 01:48:53.337910 USB2 port 2
1369 01:48:53.337991 USB2 port 3
1370 01:48:53.341418 USB2 port 5
1371 01:48:53.341500 USB2 port 6
1372 01:48:53.344614 USB2 port 9
1373 01:48:53.344695 USB3 port 0
1374 01:48:53.348140 USB3 port 1
1375 01:48:53.348220 USB3 port 2
1376 01:48:53.352223 USB3 port 3
1377 01:48:53.352304 USB3 port 4
1378 01:48:53.354925 PCI: 00:14.2
1379 01:48:53.365324 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1380 01:48:53.374462 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1381 01:48:53.377672 PCI: 00:14.3
1382 01:48:53.387769 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1383 01:48:53.391044 PCI: 00:15.0 child on link 0 I2C: 01:15
1384 01:48:53.401000 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1385 01:48:53.404163 I2C: 01:15
1386 01:48:53.407483 PCI: 00:15.1 child on link 0 I2C: 02:5d
1387 01:48:53.417791 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1388 01:48:53.421163 I2C: 02:5d
1389 01:48:53.421244 GENERIC: 0.0
1390 01:48:53.424023 PCI: 00:16.0
1391 01:48:53.434455 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1392 01:48:53.434597 PCI: 00:17.0
1393 01:48:53.443881 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1394 01:48:53.454108 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1395 01:48:53.463664 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1396 01:48:53.473666 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1397 01:48:53.483451 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1398 01:48:53.493690 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1399 01:48:53.497308 PCI: 00:19.0 child on link 0 I2C: 03:1a
1400 01:48:53.506725 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1401 01:48:53.510054 I2C: 03:1a
1402 01:48:53.510129 I2C: 03:38
1403 01:48:53.513433 I2C: 03:39
1404 01:48:53.513506 I2C: 03:3a
1405 01:48:53.516795 I2C: 03:3b
1406 01:48:53.520375 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1407 01:48:53.530360 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1408 01:48:53.539776 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1409 01:48:53.550313 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1410 01:48:53.550412 PCI: 01:00.0
1411 01:48:53.562921 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1412 01:48:53.563001 PCI: 00:1e.0
1413 01:48:53.572956 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1414 01:48:53.585902 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1415 01:48:53.589975 PCI: 00:1e.2 child on link 0 SPI: 00
1416 01:48:53.599559 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1417 01:48:53.599645 SPI: 00
1418 01:48:53.603133 PCI: 00:1e.3 child on link 0 SPI: 01
1419 01:48:53.616151 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1420 01:48:53.616240 SPI: 01
1421 01:48:53.619587 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1422 01:48:53.629238 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1423 01:48:53.638808 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1424 01:48:53.638884 PNP: 0c09.0
1425 01:48:53.648783 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1426 01:48:53.648860 PCI: 00:1f.3
1427 01:48:53.658758 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1428 01:48:53.672109 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1429 01:48:53.672192 PCI: 00:1f.4
1430 01:48:53.681932 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1431 01:48:53.692045 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1432 01:48:53.692124 PCI: 00:1f.5
1433 01:48:53.701630 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1434 01:48:53.705707 Done allocating resources.
1435 01:48:53.711532 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1436 01:48:53.715081 Enabling resources...
1437 01:48:53.718677 PCI: 00:00.0 subsystem <- 8086/9b61
1438 01:48:53.721269 PCI: 00:00.0 cmd <- 06
1439 01:48:53.724845 PCI: 00:02.0 subsystem <- 8086/9b41
1440 01:48:53.728530 PCI: 00:02.0 cmd <- 03
1441 01:48:53.731261 PCI: 00:08.0 cmd <- 06
1442 01:48:53.734850 PCI: 00:12.0 subsystem <- 8086/02f9
1443 01:48:53.734930 PCI: 00:12.0 cmd <- 02
1444 01:48:53.741925 PCI: 00:14.0 subsystem <- 8086/02ed
1445 01:48:53.742004 PCI: 00:14.0 cmd <- 02
1446 01:48:53.745133 PCI: 00:14.2 cmd <- 02
1447 01:48:53.748438 PCI: 00:14.3 subsystem <- 8086/02f0
1448 01:48:53.751546 PCI: 00:14.3 cmd <- 02
1449 01:48:53.754610 PCI: 00:15.0 subsystem <- 8086/02e8
1450 01:48:53.758396 PCI: 00:15.0 cmd <- 02
1451 01:48:53.761359 PCI: 00:15.1 subsystem <- 8086/02e9
1452 01:48:53.764900 PCI: 00:15.1 cmd <- 02
1453 01:48:53.768284 PCI: 00:16.0 subsystem <- 8086/02e0
1454 01:48:53.771712 PCI: 00:16.0 cmd <- 02
1455 01:48:53.774999 PCI: 00:17.0 subsystem <- 8086/02d3
1456 01:48:53.777890 PCI: 00:17.0 cmd <- 03
1457 01:48:53.781240 PCI: 00:19.0 subsystem <- 8086/02c5
1458 01:48:53.781323 PCI: 00:19.0 cmd <- 02
1459 01:48:53.784745 PCI: 00:1d.0 bridge ctrl <- 0013
1460 01:48:53.791240 PCI: 00:1d.0 subsystem <- 8086/02b0
1461 01:48:53.791321 PCI: 00:1d.0 cmd <- 06
1462 01:48:53.794337 PCI: 00:1e.0 subsystem <- 8086/02a8
1463 01:48:53.797722 PCI: 00:1e.0 cmd <- 06
1464 01:48:53.801238 PCI: 00:1e.2 subsystem <- 8086/02aa
1465 01:48:53.804216 PCI: 00:1e.2 cmd <- 06
1466 01:48:53.807774 PCI: 00:1e.3 subsystem <- 8086/02ab
1467 01:48:53.810892 PCI: 00:1e.3 cmd <- 02
1468 01:48:53.814475 PCI: 00:1f.0 subsystem <- 8086/0284
1469 01:48:53.817764 PCI: 00:1f.0 cmd <- 407
1470 01:48:53.820939 PCI: 00:1f.3 subsystem <- 8086/02c8
1471 01:48:53.824187 PCI: 00:1f.3 cmd <- 02
1472 01:48:53.827501 PCI: 00:1f.4 subsystem <- 8086/02a3
1473 01:48:53.830935 PCI: 00:1f.4 cmd <- 03
1474 01:48:53.834424 PCI: 00:1f.5 subsystem <- 8086/02a4
1475 01:48:53.837705 PCI: 00:1f.5 cmd <- 406
1476 01:48:53.845005 PCI: 01:00.0 cmd <- 02
1477 01:48:53.850581 done.
1478 01:48:53.863380 ME: Version: 14.0.39.1367
1479 01:48:53.869639 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 12
1480 01:48:53.873012 Initializing devices...
1481 01:48:53.873107 Root Device init ...
1482 01:48:53.879478 Chrome EC: Set SMI mask to 0x0000000000000000
1483 01:48:53.883024 Chrome EC: clear events_b mask to 0x0000000000000000
1484 01:48:53.889704 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1485 01:48:53.896541 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1486 01:48:53.903369 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1487 01:48:53.906018 Chrome EC: Set WAKE mask to 0x0000000000000000
1488 01:48:53.909623 Root Device init finished in 35167 usecs
1489 01:48:53.913920 CPU_CLUSTER: 0 init ...
1490 01:48:53.919798 CPU_CLUSTER: 0 init finished in 2448 usecs
1491 01:48:53.923628 PCI: 00:00.0 init ...
1492 01:48:53.927304 CPU TDP: 15 Watts
1493 01:48:53.930751 CPU PL2 = 64 Watts
1494 01:48:53.934264 PCI: 00:00.0 init finished in 7071 usecs
1495 01:48:53.937101 PCI: 00:02.0 init ...
1496 01:48:53.940476 PCI: 00:02.0 init finished in 2253 usecs
1497 01:48:53.943640 PCI: 00:08.0 init ...
1498 01:48:53.947157 PCI: 00:08.0 init finished in 2251 usecs
1499 01:48:53.950447 PCI: 00:12.0 init ...
1500 01:48:53.953623 PCI: 00:12.0 init finished in 2251 usecs
1501 01:48:53.956969 PCI: 00:14.0 init ...
1502 01:48:53.960711 PCI: 00:14.0 init finished in 2252 usecs
1503 01:48:53.963461 PCI: 00:14.2 init ...
1504 01:48:53.967073 PCI: 00:14.2 init finished in 2253 usecs
1505 01:48:53.970250 PCI: 00:14.3 init ...
1506 01:48:53.973528 PCI: 00:14.3 init finished in 2270 usecs
1507 01:48:53.976904 PCI: 00:15.0 init ...
1508 01:48:53.980103 DW I2C bus 0 at 0xd121f000 (400 KHz)
1509 01:48:53.983624 PCI: 00:15.0 init finished in 5972 usecs
1510 01:48:53.986864 PCI: 00:15.1 init ...
1511 01:48:53.990153 DW I2C bus 1 at 0xd1220000 (400 KHz)
1512 01:48:53.996908 PCI: 00:15.1 init finished in 5969 usecs
1513 01:48:53.996995 PCI: 00:16.0 init ...
1514 01:48:54.003032 PCI: 00:16.0 init finished in 2245 usecs
1515 01:48:54.006633 PCI: 00:19.0 init ...
1516 01:48:54.009568 DW I2C bus 4 at 0xd1222000 (400 KHz)
1517 01:48:54.013113 PCI: 00:19.0 init finished in 5976 usecs
1518 01:48:54.016356 PCI: 00:1d.0 init ...
1519 01:48:54.019659 Initializing PCH PCIe bridge.
1520 01:48:54.022720 PCI: 00:1d.0 init finished in 5285 usecs
1521 01:48:54.026197 PCI: 00:1f.0 init ...
1522 01:48:54.029483 IOAPIC: Initializing IOAPIC at 0xfec00000
1523 01:48:54.036170 IOAPIC: Bootstrap Processor Local APIC = 0x00
1524 01:48:54.036252 IOAPIC: ID = 0x02
1525 01:48:54.039336 IOAPIC: Dumping registers
1526 01:48:54.042991 reg 0x0000: 0x02000000
1527 01:48:54.046053 reg 0x0001: 0x00770020
1528 01:48:54.046132 reg 0x0002: 0x00000000
1529 01:48:54.053522 PCI: 00:1f.0 init finished in 23545 usecs
1530 01:48:54.056053 PCI: 00:1f.4 init ...
1531 01:48:54.060169 PCI: 00:1f.4 init finished in 2261 usecs
1532 01:48:54.069721 PCI: 01:00.0 init ...
1533 01:48:54.073302 PCI: 01:00.0 init finished in 2244 usecs
1534 01:48:54.078104 PNP: 0c09.0 init ...
1535 01:48:54.081591 Google Chrome EC uptime: 11.092 seconds
1536 01:48:54.087362 Google Chrome AP resets since EC boot: 0
1537 01:48:54.090774 Google Chrome most recent AP reset causes:
1538 01:48:54.097761 Google Chrome EC reset flags at last EC boot: reset-pin
1539 01:48:54.100761 PNP: 0c09.0 init finished in 20604 usecs
1540 01:48:54.103823 Devices initialized
1541 01:48:54.107328 Show all devs... After init.
1542 01:48:54.107409 Root Device: enabled 1
1543 01:48:54.110678 CPU_CLUSTER: 0: enabled 1
1544 01:48:54.113797 DOMAIN: 0000: enabled 1
1545 01:48:54.113877 APIC: 00: enabled 1
1546 01:48:54.117216 PCI: 00:00.0: enabled 1
1547 01:48:54.120319 PCI: 00:02.0: enabled 1
1548 01:48:54.123913 PCI: 00:04.0: enabled 0
1549 01:48:54.123992 PCI: 00:05.0: enabled 0
1550 01:48:54.126987 PCI: 00:12.0: enabled 1
1551 01:48:54.131054 PCI: 00:12.5: enabled 0
1552 01:48:54.133995 PCI: 00:12.6: enabled 0
1553 01:48:54.134075 PCI: 00:14.0: enabled 1
1554 01:48:54.137532 PCI: 00:14.1: enabled 0
1555 01:48:54.140112 PCI: 00:14.3: enabled 1
1556 01:48:54.140191 PCI: 00:14.5: enabled 0
1557 01:48:54.143760 PCI: 00:15.0: enabled 1
1558 01:48:54.146901 PCI: 00:15.1: enabled 1
1559 01:48:54.150092 PCI: 00:15.2: enabled 0
1560 01:48:54.150171 PCI: 00:15.3: enabled 0
1561 01:48:54.153195 PCI: 00:16.0: enabled 1
1562 01:48:54.156627 PCI: 00:16.1: enabled 0
1563 01:48:54.160135 PCI: 00:16.2: enabled 0
1564 01:48:54.160215 PCI: 00:16.3: enabled 0
1565 01:48:54.163470 PCI: 00:16.4: enabled 0
1566 01:48:54.166876 PCI: 00:16.5: enabled 0
1567 01:48:54.169969 PCI: 00:17.0: enabled 1
1568 01:48:54.170048 PCI: 00:19.0: enabled 1
1569 01:48:54.173310 PCI: 00:19.1: enabled 0
1570 01:48:54.176512 PCI: 00:19.2: enabled 0
1571 01:48:54.180187 PCI: 00:1a.0: enabled 0
1572 01:48:54.180268 PCI: 00:1c.0: enabled 0
1573 01:48:54.183281 PCI: 00:1c.1: enabled 0
1574 01:48:54.186708 PCI: 00:1c.2: enabled 0
1575 01:48:54.186788 PCI: 00:1c.3: enabled 0
1576 01:48:54.190187 PCI: 00:1c.4: enabled 0
1577 01:48:54.193320 PCI: 00:1c.5: enabled 0
1578 01:48:54.196733 PCI: 00:1c.6: enabled 0
1579 01:48:54.196813 PCI: 00:1c.7: enabled 0
1580 01:48:54.199579 PCI: 00:1d.0: enabled 1
1581 01:48:54.202894 PCI: 00:1d.1: enabled 0
1582 01:48:54.206306 PCI: 00:1d.2: enabled 0
1583 01:48:54.206385 PCI: 00:1d.3: enabled 0
1584 01:48:54.210041 PCI: 00:1d.4: enabled 0
1585 01:48:54.213023 PCI: 00:1d.5: enabled 0
1586 01:48:54.216894 PCI: 00:1e.0: enabled 1
1587 01:48:54.216973 PCI: 00:1e.1: enabled 0
1588 01:48:54.219559 PCI: 00:1e.2: enabled 1
1589 01:48:54.223583 PCI: 00:1e.3: enabled 1
1590 01:48:54.223663 PCI: 00:1f.0: enabled 1
1591 01:48:54.226202 PCI: 00:1f.1: enabled 0
1592 01:48:54.229338 PCI: 00:1f.2: enabled 0
1593 01:48:54.232684 PCI: 00:1f.3: enabled 1
1594 01:48:54.232776 PCI: 00:1f.4: enabled 1
1595 01:48:54.236159 PCI: 00:1f.5: enabled 1
1596 01:48:54.239470 PCI: 00:1f.6: enabled 0
1597 01:48:54.242826 USB0 port 0: enabled 1
1598 01:48:54.242906 I2C: 01:15: enabled 1
1599 01:48:54.245992 I2C: 02:5d: enabled 1
1600 01:48:54.249434 GENERIC: 0.0: enabled 1
1601 01:48:54.249513 I2C: 03:1a: enabled 1
1602 01:48:54.252859 I2C: 03:38: enabled 1
1603 01:48:54.256081 I2C: 03:39: enabled 1
1604 01:48:54.256160 I2C: 03:3a: enabled 1
1605 01:48:54.259849 I2C: 03:3b: enabled 1
1606 01:48:54.262701 PCI: 00:00.0: enabled 1
1607 01:48:54.262786 SPI: 00: enabled 1
1608 01:48:54.265814 SPI: 01: enabled 1
1609 01:48:54.269054 PNP: 0c09.0: enabled 1
1610 01:48:54.269172 USB2 port 0: enabled 1
1611 01:48:54.272386 USB2 port 1: enabled 1
1612 01:48:54.275918 USB2 port 2: enabled 0
1613 01:48:54.279115 USB2 port 3: enabled 0
1614 01:48:54.279250 USB2 port 5: enabled 0
1615 01:48:54.282500 USB2 port 6: enabled 1
1616 01:48:54.285693 USB2 port 9: enabled 1
1617 01:48:54.285774 USB3 port 0: enabled 1
1618 01:48:54.288868 USB3 port 1: enabled 1
1619 01:48:54.292550 USB3 port 2: enabled 1
1620 01:48:54.292631 USB3 port 3: enabled 1
1621 01:48:54.295601 USB3 port 4: enabled 0
1622 01:48:54.299126 APIC: 02: enabled 1
1623 01:48:54.299209 APIC: 01: enabled 1
1624 01:48:54.302214 APIC: 07: enabled 1
1625 01:48:54.305776 APIC: 03: enabled 1
1626 01:48:54.305859 APIC: 04: enabled 1
1627 01:48:54.309149 APIC: 05: enabled 1
1628 01:48:54.312006 APIC: 06: enabled 1
1629 01:48:54.312087 PCI: 00:08.0: enabled 1
1630 01:48:54.315213 PCI: 00:14.2: enabled 1
1631 01:48:54.318456 PCI: 01:00.0: enabled 1
1632 01:48:54.322188 Disabling ACPI via APMC:
1633 01:48:54.325337 done.
1634 01:48:54.328591 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1635 01:48:54.332152 ELOG: NV offset 0xaf0000 size 0x4000
1636 01:48:54.339683 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1637 01:48:54.346143 ELOG: Event(17) added with size 13 at 2023-10-11 01:48:54 UTC
1638 01:48:54.352753 ELOG: Event(92) added with size 9 at 2023-10-11 01:48:54 UTC
1639 01:48:54.360716 ELOG: Event(93) added with size 9 at 2023-10-11 01:48:54 UTC
1640 01:48:54.366857 ELOG: Event(9A) added with size 9 at 2023-10-11 01:48:54 UTC
1641 01:48:54.372572 ELOG: Event(9E) added with size 10 at 2023-10-11 01:48:54 UTC
1642 01:48:54.378981 ELOG: Event(9F) added with size 14 at 2023-10-11 01:48:54 UTC
1643 01:48:54.382193 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1644 01:48:54.389870 ELOG: Event(A1) added with size 10 at 2023-10-11 01:48:54 UTC
1645 01:48:54.399609 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1646 01:48:54.406396 ELOG: Event(A0) added with size 9 at 2023-10-11 01:48:54 UTC
1647 01:48:54.409507 elog_add_boot_reason: Logged dev mode boot
1648 01:48:54.409590 Finalize devices...
1649 01:48:54.413134 PCI: 00:17.0 final
1650 01:48:54.416547 Devices finalized
1651 01:48:54.420265 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1652 01:48:54.426477 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1653 01:48:54.429686 ME: HFSTS1 : 0x90000245
1654 01:48:54.433286 ME: HFSTS2 : 0x3B850126
1655 01:48:54.439331 ME: HFSTS3 : 0x00000020
1656 01:48:54.442452 ME: HFSTS4 : 0x00004800
1657 01:48:54.445688 ME: HFSTS5 : 0x00000000
1658 01:48:54.449030 ME: HFSTS6 : 0x40400006
1659 01:48:54.452640 ME: Manufacturing Mode : NO
1660 01:48:54.455805 ME: FW Partition Table : OK
1661 01:48:54.459161 ME: Bringup Loader Failure : NO
1662 01:48:54.462739 ME: Firmware Init Complete : YES
1663 01:48:54.465763 ME: Boot Options Present : NO
1664 01:48:54.469144 ME: Update In Progress : NO
1665 01:48:54.472331 ME: D0i3 Support : YES
1666 01:48:54.476107 ME: Low Power State Enabled : NO
1667 01:48:54.478911 ME: CPU Replaced : NO
1668 01:48:54.482518 ME: CPU Replacement Valid : YES
1669 01:48:54.485576 ME: Current Working State : 5
1670 01:48:54.489001 ME: Current Operation State : 1
1671 01:48:54.492304 ME: Current Operation Mode : 0
1672 01:48:54.495520 ME: Error Code : 0
1673 01:48:54.499038 ME: CPU Debug Disabled : YES
1674 01:48:54.502581 ME: TXT Support : NO
1675 01:48:54.508978 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1676 01:48:54.515053 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1677 01:48:54.515134 CBFS @ c08000 size 3f8000
1678 01:48:54.522174 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1679 01:48:54.524986 CBFS: Locating 'fallback/dsdt.aml'
1680 01:48:54.528425 CBFS: Found @ offset 10bb80 size 3fa5
1681 01:48:54.535430 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1682 01:48:54.538549 CBFS @ c08000 size 3f8000
1683 01:48:54.545224 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1684 01:48:54.545304 CBFS: Locating 'fallback/slic'
1685 01:48:54.550072 CBFS: 'fallback/slic' not found.
1686 01:48:54.556700 ACPI: Writing ACPI tables at 99b3e000.
1687 01:48:54.556781 ACPI: * FACS
1688 01:48:54.560070 ACPI: * DSDT
1689 01:48:54.563545 Ramoops buffer: 0x100000@0x99a3d000.
1690 01:48:54.566992 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1691 01:48:54.573352 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1692 01:48:54.576490 Google Chrome EC: version:
1693 01:48:54.579922 ro: helios_v2.0.2659-56403530b
1694 01:48:54.583141 rw: helios_v2.0.2849-c41de27e7d
1695 01:48:54.583222 running image: 1
1696 01:48:54.588335 ACPI: * FADT
1697 01:48:54.588416 SCI is IRQ9
1698 01:48:54.594355 ACPI: added table 1/32, length now 40
1699 01:48:54.594463 ACPI: * SSDT
1700 01:48:54.597465 Found 1 CPU(s) with 8 core(s) each.
1701 01:48:54.601317 Error: Could not locate 'wifi_sar' in VPD.
1702 01:48:54.607768 Checking CBFS for default SAR values
1703 01:48:54.611203 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1704 01:48:54.614768 CBFS @ c08000 size 3f8000
1705 01:48:54.620821 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1706 01:48:54.624177 CBFS: Locating 'wifi_sar_defaults.hex'
1707 01:48:54.627350 CBFS: Found @ offset 5fac0 size 77
1708 01:48:54.630757 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1709 01:48:54.637604 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1710 01:48:54.640638 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1711 01:48:54.647483 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1712 01:48:54.650745 failed to find key in VPD: dsm_calib_r0_0
1713 01:48:54.660327 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1714 01:48:54.663863 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1715 01:48:54.667311 failed to find key in VPD: dsm_calib_r0_1
1716 01:48:54.677255 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1717 01:48:54.683911 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1718 01:48:54.686829 failed to find key in VPD: dsm_calib_r0_2
1719 01:48:54.696856 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1720 01:48:54.700248 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1721 01:48:54.707260 failed to find key in VPD: dsm_calib_r0_3
1722 01:48:54.713483 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1723 01:48:54.720161 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1724 01:48:54.723606 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1725 01:48:54.726614 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1726 01:48:54.730330 EC returned error result code 1
1727 01:48:54.734351 EC returned error result code 1
1728 01:48:54.738275 EC returned error result code 1
1729 01:48:54.744610 PS2K: Bad resp from EC. Vivaldi disabled!
1730 01:48:54.748097 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1731 01:48:54.755170 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1732 01:48:54.761458 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1733 01:48:54.765133 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1734 01:48:54.770860 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1735 01:48:54.777773 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1736 01:48:54.784344 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1737 01:48:54.788305 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1738 01:48:54.794432 ACPI: added table 2/32, length now 44
1739 01:48:54.794538 ACPI: * MCFG
1740 01:48:54.798110 ACPI: added table 3/32, length now 48
1741 01:48:54.801033 ACPI: * TPM2
1742 01:48:54.804131 TPM2 log created at 99a2d000
1743 01:48:54.807747 ACPI: added table 4/32, length now 52
1744 01:48:54.807856 ACPI: * MADT
1745 01:48:54.810819 SCI is IRQ9
1746 01:48:54.814174 ACPI: added table 5/32, length now 56
1747 01:48:54.814255 current = 99b43ac0
1748 01:48:54.817278 ACPI: * DMAR
1749 01:48:54.821020 ACPI: added table 6/32, length now 60
1750 01:48:54.824303 ACPI: * IGD OpRegion
1751 01:48:54.824384 GMA: Found VBT in CBFS
1752 01:48:54.827413 GMA: Found valid VBT in CBFS
1753 01:48:54.830461 ACPI: added table 7/32, length now 64
1754 01:48:54.834194 ACPI: * HPET
1755 01:48:54.837135 ACPI: added table 8/32, length now 68
1756 01:48:54.840486 ACPI: done.
1757 01:48:54.840566 ACPI tables: 31744 bytes.
1758 01:48:54.844498 smbios_write_tables: 99a2c000
1759 01:48:54.847906 EC returned error result code 3
1760 01:48:54.851787 Couldn't obtain OEM name from CBI
1761 01:48:54.854188 Create SMBIOS type 17
1762 01:48:54.857754 PCI: 00:00.0 (Intel Cannonlake)
1763 01:48:54.860735 PCI: 00:14.3 (Intel WiFi)
1764 01:48:54.863957 SMBIOS tables: 939 bytes.
1765 01:48:54.867320 Writing table forward entry at 0x00000500
1766 01:48:54.874325 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1767 01:48:54.877665 Writing coreboot table at 0x99b62000
1768 01:48:54.883873 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1769 01:48:54.887303 1. 0000000000001000-000000000009ffff: RAM
1770 01:48:54.890988 2. 00000000000a0000-00000000000fffff: RESERVED
1771 01:48:54.897382 3. 0000000000100000-0000000099a2bfff: RAM
1772 01:48:54.903852 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1773 01:48:54.906888 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1774 01:48:54.913458 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1775 01:48:54.917132 7. 000000009a000000-000000009f7fffff: RESERVED
1776 01:48:54.923419 8. 00000000e0000000-00000000efffffff: RESERVED
1777 01:48:54.926975 9. 00000000fc000000-00000000fc000fff: RESERVED
1778 01:48:54.933912 10. 00000000fe000000-00000000fe00ffff: RESERVED
1779 01:48:54.936967 11. 00000000fed10000-00000000fed17fff: RESERVED
1780 01:48:54.940790 12. 00000000fed80000-00000000fed83fff: RESERVED
1781 01:48:54.947193 13. 00000000fed90000-00000000fed91fff: RESERVED
1782 01:48:54.950112 14. 00000000feda0000-00000000feda1fff: RESERVED
1783 01:48:54.956717 15. 0000000100000000-000000045e7fffff: RAM
1784 01:48:54.960084 Graphics framebuffer located at 0xc0000000
1785 01:48:54.963945 Passing 5 GPIOs to payload:
1786 01:48:54.966377 NAME | PORT | POLARITY | VALUE
1787 01:48:54.972980 write protect | undefined | high | low
1788 01:48:54.979485 lid | undefined | high | high
1789 01:48:54.982946 power | undefined | high | low
1790 01:48:54.990558 oprom | undefined | high | low
1791 01:48:54.992942 EC in RW | 0x000000cb | high | low
1792 01:48:54.996314 Board ID: 4
1793 01:48:54.999474 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1794 01:48:55.002933 CBFS @ c08000 size 3f8000
1795 01:48:55.009419 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1796 01:48:55.016813 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6baa
1797 01:48:55.016895 coreboot table: 1492 bytes.
1798 01:48:55.019243 IMD ROOT 0. 99fff000 00001000
1799 01:48:55.022785 IMD SMALL 1. 99ffe000 00001000
1800 01:48:55.025915 FSP MEMORY 2. 99c4e000 003b0000
1801 01:48:55.029358 CONSOLE 3. 99c2e000 00020000
1802 01:48:55.032723 FMAP 4. 99c2d000 0000054e
1803 01:48:55.035986 TIME STAMP 5. 99c2c000 00000910
1804 01:48:55.039551 VBOOT WORK 6. 99c18000 00014000
1805 01:48:55.042554 MRC DATA 7. 99c16000 00001958
1806 01:48:55.046100 ROMSTG STCK 8. 99c15000 00001000
1807 01:48:55.049663 AFTER CAR 9. 99c0b000 0000a000
1808 01:48:55.052453 RAMSTAGE 10. 99baf000 0005c000
1809 01:48:55.056228 REFCODE 11. 99b7a000 00035000
1810 01:48:55.059556 SMM BACKUP 12. 99b6a000 00010000
1811 01:48:55.062435 COREBOOT 13. 99b62000 00008000
1812 01:48:55.066267 ACPI 14. 99b3e000 00024000
1813 01:48:55.069541 ACPI GNVS 15. 99b3d000 00001000
1814 01:48:55.072621 RAMOOPS 16. 99a3d000 00100000
1815 01:48:55.076558 TPM2 TCGLOG17. 99a2d000 00010000
1816 01:48:55.079426 SMBIOS 18. 99a2c000 00000800
1817 01:48:55.082525 IMD small region:
1818 01:48:55.085900 IMD ROOT 0. 99ffec00 00000400
1819 01:48:55.089396 FSP RUNTIME 1. 99ffebe0 00000004
1820 01:48:55.092734 EC HOSTEVENT 2. 99ffebc0 00000008
1821 01:48:55.095787 POWER STATE 3. 99ffeb80 00000040
1822 01:48:55.098986 ROMSTAGE 4. 99ffeb60 00000004
1823 01:48:55.102338 MEM INFO 5. 99ffe9a0 000001b9
1824 01:48:55.108991 VPD 6. 99ffe920 0000006c
1825 01:48:55.109074 MTRR: Physical address space:
1826 01:48:55.115388 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1827 01:48:55.122056 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1828 01:48:55.128971 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1829 01:48:55.135431 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1830 01:48:55.142192 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1831 01:48:55.148898 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1832 01:48:55.155472 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1833 01:48:55.158964 MTRR: Fixed MSR 0x250 0x0606060606060606
1834 01:48:55.162066 MTRR: Fixed MSR 0x258 0x0606060606060606
1835 01:48:55.165642 MTRR: Fixed MSR 0x259 0x0000000000000000
1836 01:48:55.171833 MTRR: Fixed MSR 0x268 0x0606060606060606
1837 01:48:55.175598 MTRR: Fixed MSR 0x269 0x0606060606060606
1838 01:48:55.178754 MTRR: Fixed MSR 0x26a 0x0606060606060606
1839 01:48:55.182353 MTRR: Fixed MSR 0x26b 0x0606060606060606
1840 01:48:55.188264 MTRR: Fixed MSR 0x26c 0x0606060606060606
1841 01:48:55.191743 MTRR: Fixed MSR 0x26d 0x0606060606060606
1842 01:48:55.195376 MTRR: Fixed MSR 0x26e 0x0606060606060606
1843 01:48:55.198271 MTRR: Fixed MSR 0x26f 0x0606060606060606
1844 01:48:55.202235 call enable_fixed_mtrr()
1845 01:48:55.205140 CPU physical address size: 39 bits
1846 01:48:55.211566 MTRR: default type WB/UC MTRR counts: 6/8.
1847 01:48:55.215210 MTRR: WB selected as default type.
1848 01:48:55.222420 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1849 01:48:55.224746 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1850 01:48:55.231416 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1851 01:48:55.238032 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1852 01:48:55.244661 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1853 01:48:55.251980 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1854 01:48:55.254798 MTRR: Fixed MSR 0x250 0x0606060606060606
1855 01:48:55.261222 MTRR: Fixed MSR 0x258 0x0606060606060606
1856 01:48:55.264400 MTRR: Fixed MSR 0x259 0x0000000000000000
1857 01:48:55.268158 MTRR: Fixed MSR 0x268 0x0606060606060606
1858 01:48:55.271339 MTRR: Fixed MSR 0x269 0x0606060606060606
1859 01:48:55.277874 MTRR: Fixed MSR 0x26a 0x0606060606060606
1860 01:48:55.281620 MTRR: Fixed MSR 0x26b 0x0606060606060606
1861 01:48:55.284251 MTRR: Fixed MSR 0x26c 0x0606060606060606
1862 01:48:55.287620 MTRR: Fixed MSR 0x26d 0x0606060606060606
1863 01:48:55.294304 MTRR: Fixed MSR 0x26e 0x0606060606060606
1864 01:48:55.297419 MTRR: Fixed MSR 0x26f 0x0606060606060606
1865 01:48:55.297503
1866 01:48:55.297586 MTRR check
1867 01:48:55.300980 Fixed MTRRs : Enabled
1868 01:48:55.304065 Variable MTRRs: Enabled
1869 01:48:55.304147
1870 01:48:55.307679 call enable_fixed_mtrr()
1871 01:48:55.311210 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1872 01:48:55.314128 CPU physical address size: 39 bits
1873 01:48:55.321384 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1874 01:48:55.324744 MTRR: Fixed MSR 0x250 0x0606060606060606
1875 01:48:55.328071 MTRR: Fixed MSR 0x250 0x0606060606060606
1876 01:48:55.334469 MTRR: Fixed MSR 0x258 0x0606060606060606
1877 01:48:55.337879 MTRR: Fixed MSR 0x259 0x0000000000000000
1878 01:48:55.341042 MTRR: Fixed MSR 0x268 0x0606060606060606
1879 01:48:55.344559 MTRR: Fixed MSR 0x269 0x0606060606060606
1880 01:48:55.350808 MTRR: Fixed MSR 0x26a 0x0606060606060606
1881 01:48:55.354593 MTRR: Fixed MSR 0x26b 0x0606060606060606
1882 01:48:55.357968 MTRR: Fixed MSR 0x26c 0x0606060606060606
1883 01:48:55.361136 MTRR: Fixed MSR 0x26d 0x0606060606060606
1884 01:48:55.365068 MTRR: Fixed MSR 0x26e 0x0606060606060606
1885 01:48:55.371144 MTRR: Fixed MSR 0x26f 0x0606060606060606
1886 01:48:55.374228 MTRR: Fixed MSR 0x258 0x0606060606060606
1887 01:48:55.377253 call enable_fixed_mtrr()
1888 01:48:55.381155 MTRR: Fixed MSR 0x259 0x0000000000000000
1889 01:48:55.384407 MTRR: Fixed MSR 0x268 0x0606060606060606
1890 01:48:55.390776 MTRR: Fixed MSR 0x269 0x0606060606060606
1891 01:48:55.394006 MTRR: Fixed MSR 0x26a 0x0606060606060606
1892 01:48:55.397810 MTRR: Fixed MSR 0x26b 0x0606060606060606
1893 01:48:55.400614 MTRR: Fixed MSR 0x26c 0x0606060606060606
1894 01:48:55.404422 MTRR: Fixed MSR 0x26d 0x0606060606060606
1895 01:48:55.410274 MTRR: Fixed MSR 0x26e 0x0606060606060606
1896 01:48:55.413726 MTRR: Fixed MSR 0x26f 0x0606060606060606
1897 01:48:55.417138 CPU physical address size: 39 bits
1898 01:48:55.420895 call enable_fixed_mtrr()
1899 01:48:55.423559 CBFS @ c08000 size 3f8000
1900 01:48:55.426987 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1901 01:48:55.434372 CBFS: Locating 'fallback/payload'
1902 01:48:55.436822 MTRR: Fixed MSR 0x250 0x0606060606060606
1903 01:48:55.440240 MTRR: Fixed MSR 0x258 0x0606060606060606
1904 01:48:55.443595 MTRR: Fixed MSR 0x259 0x0000000000000000
1905 01:48:55.446720 MTRR: Fixed MSR 0x268 0x0606060606060606
1906 01:48:55.453471 MTRR: Fixed MSR 0x269 0x0606060606060606
1907 01:48:55.456802 MTRR: Fixed MSR 0x26a 0x0606060606060606
1908 01:48:55.460408 MTRR: Fixed MSR 0x26b 0x0606060606060606
1909 01:48:55.463399 MTRR: Fixed MSR 0x26c 0x0606060606060606
1910 01:48:55.469843 MTRR: Fixed MSR 0x26d 0x0606060606060606
1911 01:48:55.473528 MTRR: Fixed MSR 0x26e 0x0606060606060606
1912 01:48:55.476802 MTRR: Fixed MSR 0x26f 0x0606060606060606
1913 01:48:55.480000 MTRR: Fixed MSR 0x250 0x0606060606060606
1914 01:48:55.486524 MTRR: Fixed MSR 0x258 0x0606060606060606
1915 01:48:55.489801 MTRR: Fixed MSR 0x259 0x0000000000000000
1916 01:48:55.493594 MTRR: Fixed MSR 0x268 0x0606060606060606
1917 01:48:55.496568 MTRR: Fixed MSR 0x269 0x0606060606060606
1918 01:48:55.503534 MTRR: Fixed MSR 0x26a 0x0606060606060606
1919 01:48:55.506147 MTRR: Fixed MSR 0x26b 0x0606060606060606
1920 01:48:55.509518 MTRR: Fixed MSR 0x26c 0x0606060606060606
1921 01:48:55.512744 MTRR: Fixed MSR 0x26d 0x0606060606060606
1922 01:48:55.519909 MTRR: Fixed MSR 0x26e 0x0606060606060606
1923 01:48:55.522780 MTRR: Fixed MSR 0x26f 0x0606060606060606
1924 01:48:55.526518 call enable_fixed_mtrr()
1925 01:48:55.526635 call enable_fixed_mtrr()
1926 01:48:55.532617 CPU physical address size: 39 bits
1927 01:48:55.535872 CPU physical address size: 39 bits
1928 01:48:55.539393 CBFS: Found @ offset 1c96c0 size 3f798
1929 01:48:55.542400 MTRR: Fixed MSR 0x250 0x0606060606060606
1930 01:48:55.545682 MTRR: Fixed MSR 0x250 0x0606060606060606
1931 01:48:55.552598 MTRR: Fixed MSR 0x258 0x0606060606060606
1932 01:48:55.555856 MTRR: Fixed MSR 0x259 0x0000000000000000
1933 01:48:55.559409 MTRR: Fixed MSR 0x268 0x0606060606060606
1934 01:48:55.562817 MTRR: Fixed MSR 0x269 0x0606060606060606
1935 01:48:55.569030 MTRR: Fixed MSR 0x26a 0x0606060606060606
1936 01:48:55.572573 MTRR: Fixed MSR 0x26b 0x0606060606060606
1937 01:48:55.575778 MTRR: Fixed MSR 0x26c 0x0606060606060606
1938 01:48:55.579208 MTRR: Fixed MSR 0x26d 0x0606060606060606
1939 01:48:55.582451 MTRR: Fixed MSR 0x26e 0x0606060606060606
1940 01:48:55.589005 MTRR: Fixed MSR 0x26f 0x0606060606060606
1941 01:48:55.591932 MTRR: Fixed MSR 0x258 0x0606060606060606
1942 01:48:55.595345 call enable_fixed_mtrr()
1943 01:48:55.598757 MTRR: Fixed MSR 0x259 0x0000000000000000
1944 01:48:55.601817 MTRR: Fixed MSR 0x268 0x0606060606060606
1945 01:48:55.608517 MTRR: Fixed MSR 0x269 0x0606060606060606
1946 01:48:55.612655 MTRR: Fixed MSR 0x26a 0x0606060606060606
1947 01:48:55.615216 MTRR: Fixed MSR 0x26b 0x0606060606060606
1948 01:48:55.619034 MTRR: Fixed MSR 0x26c 0x0606060606060606
1949 01:48:55.625324 MTRR: Fixed MSR 0x26d 0x0606060606060606
1950 01:48:55.628674 MTRR: Fixed MSR 0x26e 0x0606060606060606
1951 01:48:55.632202 MTRR: Fixed MSR 0x26f 0x0606060606060606
1952 01:48:55.635186 CPU physical address size: 39 bits
1953 01:48:55.638158 call enable_fixed_mtrr()
1954 01:48:55.641837 Checking segment from ROM address 0xffdd16f8
1955 01:48:55.645005 CPU physical address size: 39 bits
1956 01:48:55.648845 CPU physical address size: 39 bits
1957 01:48:55.655582 Checking segment from ROM address 0xffdd1714
1958 01:48:55.658478 Loading segment from ROM address 0xffdd16f8
1959 01:48:55.662013 code (compression=0)
1960 01:48:55.668220 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1961 01:48:55.678311 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1962 01:48:55.681305 it's not compressed!
1963 01:48:55.772392 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1964 01:48:55.779076 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1965 01:48:55.785748 Loading segment from ROM address 0xffdd1714
1966 01:48:55.785831 Entry Point 0x30000000
1967 01:48:55.789114 Loaded segments
1968 01:48:55.794541 Finalizing chipset.
1969 01:48:55.798375 Finalizing SMM.
1970 01:48:55.801477 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1971 01:48:55.804809 mp_park_aps done after 0 msecs.
1972 01:48:55.811401 Jumping to boot code at 30000000(99b62000)
1973 01:48:55.817909 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1974 01:48:55.817991
1975 01:48:55.818054
1976 01:48:55.818116
1977 01:48:55.820992 Starting depthcharge on Helios...
1978 01:48:55.821072
1979 01:48:55.821420 end: 2.2.3 depthcharge-start (duration 00:00:13) [common]
1980 01:48:55.821520 start: 2.2.4 bootloader-commands (timeout 00:04:42) [common]
1981 01:48:55.821605 Setting prompt string to ['hatch:']
1982 01:48:55.821681 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:42)
1983 01:48:55.831001 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1984 01:48:55.831086
1985 01:48:55.837719 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1986 01:48:55.837800
1987 01:48:55.844316 board_setup: Info: eMMC controller not present; skipping
1988 01:48:55.844421
1989 01:48:55.847355 New NVMe Controller 0x30053ac0 @ 00:1d:00
1990 01:48:55.847436
1991 01:48:55.854031 board_setup: Info: SDHCI controller not present; skipping
1992 01:48:55.854123
1993 01:48:55.860986 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
1994 01:48:55.861070
1995 01:48:55.861134 Wipe memory regions:
1996 01:48:55.861192
1997 01:48:55.864258 [0x00000000001000, 0x000000000a0000)
1998 01:48:55.864340
1999 01:48:55.867153 [0x00000000100000, 0x00000030000000)
2000 01:48:55.933837
2001 01:48:55.936882 [0x00000030657430, 0x00000099a2c000)
2002 01:48:56.074139
2003 01:48:56.077284 [0x00000100000000, 0x0000045e800000)
2004 01:48:57.459876
2005 01:48:57.460022 R8152: Initializing
2006 01:48:57.460090
2007 01:48:57.462960 Version 9 (ocp_data = 6010)
2008 01:48:57.467601
2009 01:48:57.467676 R8152: Done initializing
2010 01:48:57.467737
2011 01:48:57.470553 Adding net device
2012 01:48:58.079983
2013 01:48:58.080133 R8152: Initializing
2014 01:48:58.080202
2015 01:48:58.083332 Version 6 (ocp_data = 5c30)
2016 01:48:58.083406
2017 01:48:58.086939 R8152: Done initializing
2018 01:48:58.087019
2019 01:48:58.090009 net_add_device: Attemp to include the same device
2020 01:48:58.093177
2021 01:48:58.100470 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2022 01:48:58.100572
2023 01:48:58.100664
2024 01:48:58.100753
2025 01:48:58.101062 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2027 01:48:58.201450 hatch: tftpboot 192.168.201.1 11733014/tftp-deploy-n_ivmho2/kernel/bzImage 11733014/tftp-deploy-n_ivmho2/kernel/cmdline 11733014/tftp-deploy-n_ivmho2/ramdisk/ramdisk.cpio.gz
2028 01:48:58.201625 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2029 01:48:58.201714 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:40)
2030 01:48:58.206269 tftpboot 192.168.201.1 11733014/tftp-deploy-n_ivmho2/kernel/bzIloy-n_ivmho2/kernel/cmdline 11733014/tftp-deploy-n_ivmho2/ramdisk/ramdisk.cpio.gz
2031 01:48:58.206380
2032 01:48:58.206472 Waiting for link
2033 01:48:58.407913
2034 01:48:58.408062 done.
2035 01:48:58.408162
2036 01:48:58.408251 MAC: 00:24:32:50:1a:5f
2037 01:48:58.408338
2038 01:48:58.409814 Sending DHCP discover... done.
2039 01:48:58.409898
2040 01:48:58.413180 Waiting for reply... done.
2041 01:48:58.413279
2042 01:48:58.416494 Sending DHCP request... done.
2043 01:48:58.416577
2044 01:48:58.419868 Waiting for reply... done.
2045 01:48:58.423618
2046 01:48:58.423700 My ip is 192.168.201.21
2047 01:48:58.423784
2048 01:48:58.427051 The DHCP server ip is 192.168.201.1
2049 01:48:58.427134
2050 01:48:58.433455 TFTP server IP predefined by user: 192.168.201.1
2051 01:48:58.433538
2052 01:48:58.439620 Bootfile predefined by user: 11733014/tftp-deploy-n_ivmho2/kernel/bzImage
2053 01:48:58.439704
2054 01:48:58.443001 Sending tftp read request... done.
2055 01:48:58.443084
2056 01:48:58.446254 Waiting for the transfer...
2057 01:48:58.446338
2058 01:48:59.008074 00000000 ################################################################
2059 01:48:59.008222
2060 01:48:59.542510 00080000 ################################################################
2061 01:48:59.542691
2062 01:49:00.084942 00100000 ################################################################
2063 01:49:00.085091
2064 01:49:00.621312 00180000 ################################################################
2065 01:49:00.621453
2066 01:49:01.163675 00200000 ################################################################
2067 01:49:01.163825
2068 01:49:01.694992 00280000 ################################################################
2069 01:49:01.695147
2070 01:49:02.238488 00300000 ################################################################
2071 01:49:02.238688
2072 01:49:02.773717 00380000 ################################################################
2073 01:49:02.773903
2074 01:49:03.315409 00400000 ################################################################
2075 01:49:03.315550
2076 01:49:03.907796 00480000 ################################################################
2077 01:49:03.907930
2078 01:49:04.516840 00500000 ################################################################
2079 01:49:04.516977
2080 01:49:05.127515 00580000 ################################################################
2081 01:49:05.127650
2082 01:49:05.696538 00600000 ################################################################
2083 01:49:05.696676
2084 01:49:06.240596 00680000 ################################################################
2085 01:49:06.240726
2086 01:49:06.785454 00700000 ################################################################
2087 01:49:06.785598
2088 01:49:07.334095 00780000 ################################################################
2089 01:49:07.334254
2090 01:49:07.904622 00800000 ################################################################
2091 01:49:07.904751
2092 01:49:08.473268 00880000 ################################################################
2093 01:49:08.473401
2094 01:49:09.023369 00900000 ################################################################
2095 01:49:09.023501
2096 01:49:09.568912 00980000 ################################################################
2097 01:49:09.569058
2098 01:49:10.129474 00a00000 ################################################################
2099 01:49:10.129622
2100 01:49:10.598017 00a80000 ######################################################### done.
2101 01:49:10.598149
2102 01:49:10.601303 The bootfile was 11473408 bytes long.
2103 01:49:10.601386
2104 01:49:10.604724 Sending tftp read request... done.
2105 01:49:10.604807
2106 01:49:10.607793 Waiting for the transfer...
2107 01:49:10.607876
2108 01:49:11.176395 00000000 ################################################################
2109 01:49:11.176545
2110 01:49:11.727758 00080000 ################################################################
2111 01:49:11.727892
2112 01:49:12.293033 00100000 ################################################################
2113 01:49:12.293235
2114 01:49:12.925333 00180000 ################################################################
2115 01:49:12.925481
2116 01:49:13.471123 00200000 ################################################################
2117 01:49:13.471257
2118 01:49:14.042459 00280000 ################################################################
2119 01:49:14.042648
2120 01:49:14.583375 00300000 ################################################################
2121 01:49:14.583510
2122 01:49:15.161933 00380000 ################################################################
2123 01:49:15.162067
2124 01:49:15.734565 00400000 ################################################################
2125 01:49:15.734710
2126 01:49:16.426900 00480000 ################################################################
2127 01:49:16.427471
2128 01:49:17.136946 00500000 ################################################################
2129 01:49:17.137481
2130 01:49:17.828488 00580000 ################################################################
2131 01:49:17.828979
2132 01:49:18.480846 00600000 ################################################################
2133 01:49:18.481330
2134 01:49:19.184599 00680000 ################################################################
2135 01:49:19.185168
2136 01:49:19.891289 00700000 ################################################################
2137 01:49:19.891860
2138 01:49:20.615377 00780000 ################################################################
2139 01:49:20.615912
2140 01:49:21.309794 00800000 ################################################################
2141 01:49:21.310291
2142 01:49:21.715595 00880000 ##################################### done.
2143 01:49:21.716206
2144 01:49:21.718838 Sending tftp read request... done.
2145 01:49:21.719389
2146 01:49:21.722027 Waiting for the transfer...
2147 01:49:21.722632
2148 01:49:21.723039 00000000 # done.
2149 01:49:21.723445
2150 01:49:21.732222 Command line loaded dynamically from TFTP file: 11733014/tftp-deploy-n_ivmho2/kernel/cmdline
2151 01:49:21.732740
2152 01:49:21.751987 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2153 01:49:21.752431
2154 01:49:21.759278 ec_init(0): CrosEC protocol v3 supported (256, 256)
2155 01:49:21.763759
2156 01:49:21.767081 Shutting down all USB controllers.
2157 01:49:21.767497
2158 01:49:21.767822 Removing current net device
2159 01:49:21.774661
2160 01:49:21.775078 Finalizing coreboot
2161 01:49:21.775496
2162 01:49:21.781354 Exiting depthcharge with code 4 at timestamp: 33339826
2163 01:49:21.781816
2164 01:49:21.782147
2165 01:49:21.782454 Starting kernel ...
2166 01:49:21.782807
2167 01:49:21.783102
2168 01:49:21.784339 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
2169 01:49:21.784806 start: 2.2.5 auto-login-action (timeout 00:04:16) [common]
2170 01:49:21.785165 Setting prompt string to ['Linux version [0-9]']
2171 01:49:21.785493 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2172 01:49:21.785825 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2174 01:53:37.785010 end: 2.2.5 auto-login-action (duration 00:04:16) [common]
2176 01:53:37.785215 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 256 seconds'
2178 01:53:37.785371 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2181 01:53:37.785623 end: 2 depthcharge-action (duration 00:05:00) [common]
2183 01:53:37.785896 Cleaning after the job
2184 01:53:37.785984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/ramdisk
2185 01:53:37.787507 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/kernel
2186 01:53:37.789221 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11733014/tftp-deploy-n_ivmho2/modules
2187 01:53:37.790023 start: 5.1 power-off (timeout 00:00:30) [common]
2188 01:53:37.790192 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=off'
2189 01:53:37.868300 >> Command sent successfully.
2190 01:53:37.872863 Returned 0 in 0 seconds
2191 01:53:37.973896 end: 5.1 power-off (duration 00:00:00) [common]
2193 01:53:37.975553 start: 5.2 read-feedback (timeout 00:10:00) [common]
2194 01:53:37.976862 Listened to connection for namespace 'common' for up to 1s
2196 01:53:37.978215 Listened to connection for namespace 'common' for up to 1s
2197 01:53:38.977619 Finalising connection for namespace 'common'
2198 01:53:38.978298 Disconnecting from shell: Finalise
2199 01:53:38.978754
2200 01:53:39.079787 end: 5.2 read-feedback (duration 00:00:01) [common]
2201 01:53:39.080378 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11733014
2202 01:53:39.117965 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11733014
2203 01:53:39.118165 JobError: Your job cannot terminate cleanly.