Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 01:48:44.761950 lava-dispatcher, installed at version: 2023.08
2 01:48:44.762160 start: 0 validate
3 01:48:44.762295 Start time: 2023-10-11 01:48:44.762287+00:00 (UTC)
4 01:48:44.762418 Using caching service: 'http://localhost/cache/?uri=%s'
5 01:48:44.762553 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 01:48:45.015641 Using caching service: 'http://localhost/cache/?uri=%s'
7 01:48:45.015821 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.295-cip103-95-ge42cfc8bb88b7%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 01:48:45.269240 Using caching service: 'http://localhost/cache/?uri=%s'
9 01:48:45.269430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-4.19.y-cip-rc%2Fv4.19.295-cip103-95-ge42cfc8bb88b7%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 01:48:45.522663 validate duration: 0.76
12 01:48:45.523063 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 01:48:45.523231 start: 1.1 download-retry (timeout 00:10:00) [common]
14 01:48:45.523372 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 01:48:45.523550 Not decompressing ramdisk as can be used compressed.
16 01:48:45.523644 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 01:48:45.523719 saving as /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/ramdisk/rootfs.cpio.gz
18 01:48:45.523826 total size: 8418130 (8 MB)
19 01:48:45.525286 progress 0 % (0 MB)
20 01:48:45.527748 progress 5 % (0 MB)
21 01:48:45.530078 progress 10 % (0 MB)
22 01:48:45.532398 progress 15 % (1 MB)
23 01:48:45.534714 progress 20 % (1 MB)
24 01:48:45.537021 progress 25 % (2 MB)
25 01:48:45.539395 progress 30 % (2 MB)
26 01:48:45.541681 progress 35 % (2 MB)
27 01:48:45.544120 progress 40 % (3 MB)
28 01:48:45.546470 progress 45 % (3 MB)
29 01:48:45.548831 progress 50 % (4 MB)
30 01:48:45.551133 progress 55 % (4 MB)
31 01:48:45.553511 progress 60 % (4 MB)
32 01:48:45.555722 progress 65 % (5 MB)
33 01:48:45.558025 progress 70 % (5 MB)
34 01:48:45.560340 progress 75 % (6 MB)
35 01:48:45.562620 progress 80 % (6 MB)
36 01:48:45.564894 progress 85 % (6 MB)
37 01:48:45.567168 progress 90 % (7 MB)
38 01:48:45.569426 progress 95 % (7 MB)
39 01:48:45.571586 progress 100 % (8 MB)
40 01:48:45.571824 8 MB downloaded in 0.05 s (167.26 MB/s)
41 01:48:45.571984 end: 1.1.1 http-download (duration 00:00:00) [common]
43 01:48:45.572247 end: 1.1 download-retry (duration 00:00:00) [common]
44 01:48:45.572351 start: 1.2 download-retry (timeout 00:10:00) [common]
45 01:48:45.572435 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 01:48:45.572591 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.295-cip103-95-ge42cfc8bb88b7/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 01:48:45.572670 saving as /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/kernel/bzImage
48 01:48:45.572735 total size: 11473408 (10 MB)
49 01:48:45.572797 No compression specified
50 01:48:45.574075 progress 0 % (0 MB)
51 01:48:45.577200 progress 5 % (0 MB)
52 01:48:45.580407 progress 10 % (1 MB)
53 01:48:45.583431 progress 15 % (1 MB)
54 01:48:45.586623 progress 20 % (2 MB)
55 01:48:45.589747 progress 25 % (2 MB)
56 01:48:45.592938 progress 30 % (3 MB)
57 01:48:45.596303 progress 35 % (3 MB)
58 01:48:45.599622 progress 40 % (4 MB)
59 01:48:45.602828 progress 45 % (4 MB)
60 01:48:45.606313 progress 50 % (5 MB)
61 01:48:45.609614 progress 55 % (6 MB)
62 01:48:45.612812 progress 60 % (6 MB)
63 01:48:45.615772 progress 65 % (7 MB)
64 01:48:45.618866 progress 70 % (7 MB)
65 01:48:45.621963 progress 75 % (8 MB)
66 01:48:45.625109 progress 80 % (8 MB)
67 01:48:45.628164 progress 85 % (9 MB)
68 01:48:45.631294 progress 90 % (9 MB)
69 01:48:45.634323 progress 95 % (10 MB)
70 01:48:45.637542 progress 100 % (10 MB)
71 01:48:45.637675 10 MB downloaded in 0.06 s (168.53 MB/s)
72 01:48:45.637820 end: 1.2.1 http-download (duration 00:00:00) [common]
74 01:48:45.638073 end: 1.2 download-retry (duration 00:00:00) [common]
75 01:48:45.638160 start: 1.3 download-retry (timeout 00:10:00) [common]
76 01:48:45.638252 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 01:48:45.638393 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-4.19.y-cip-rc/v4.19.295-cip103-95-ge42cfc8bb88b7/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 01:48:45.638465 saving as /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/modules/modules.tar
79 01:48:45.638529 total size: 484192 (0 MB)
80 01:48:45.638591 Using unxz to decompress xz
81 01:48:45.642807 progress 6 % (0 MB)
82 01:48:45.643224 progress 13 % (0 MB)
83 01:48:45.643502 progress 20 % (0 MB)
84 01:48:45.645105 progress 27 % (0 MB)
85 01:48:45.647135 progress 33 % (0 MB)
86 01:48:45.649081 progress 40 % (0 MB)
87 01:48:45.651036 progress 47 % (0 MB)
88 01:48:45.652975 progress 54 % (0 MB)
89 01:48:45.654936 progress 60 % (0 MB)
90 01:48:45.657011 progress 67 % (0 MB)
91 01:48:45.659063 progress 74 % (0 MB)
92 01:48:45.661152 progress 81 % (0 MB)
93 01:48:45.663097 progress 87 % (0 MB)
94 01:48:45.665025 progress 94 % (0 MB)
95 01:48:45.667533 progress 100 % (0 MB)
96 01:48:45.674078 0 MB downloaded in 0.04 s (12.99 MB/s)
97 01:48:45.674391 end: 1.3.1 http-download (duration 00:00:00) [common]
99 01:48:45.674794 end: 1.3 download-retry (duration 00:00:00) [common]
100 01:48:45.674917 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
101 01:48:45.675041 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
102 01:48:45.675153 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
103 01:48:45.675300 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
104 01:48:45.675633 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb
105 01:48:45.675804 makedir: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin
106 01:48:45.675938 makedir: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/tests
107 01:48:45.676056 makedir: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/results
108 01:48:45.676199 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-add-keys
109 01:48:45.676354 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-add-sources
110 01:48:45.676487 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-background-process-start
111 01:48:45.676616 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-background-process-stop
112 01:48:45.676740 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-common-functions
113 01:48:45.676865 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-echo-ipv4
114 01:48:45.676989 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-install-packages
115 01:48:45.677115 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-installed-packages
116 01:48:45.677258 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-os-build
117 01:48:45.677386 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-probe-channel
118 01:48:45.677570 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-probe-ip
119 01:48:45.677757 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-target-ip
120 01:48:45.677947 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-target-mac
121 01:48:45.678135 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-target-storage
122 01:48:45.678305 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-case
123 01:48:45.678466 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-event
124 01:48:45.678625 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-feedback
125 01:48:45.678781 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-raise
126 01:48:45.678938 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-reference
127 01:48:45.679097 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-runner
128 01:48:45.679254 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-set
129 01:48:45.679448 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-test-shell
130 01:48:45.679580 Updating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-install-packages (oe)
131 01:48:45.679734 Updating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/bin/lava-installed-packages (oe)
132 01:48:45.679857 Creating /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/environment
133 01:48:45.679957 LAVA metadata
134 01:48:45.680030 - LAVA_JOB_ID=11733068
135 01:48:45.680095 - LAVA_DISPATCHER_IP=192.168.201.1
136 01:48:45.680200 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
137 01:48:45.680282 skipped lava-vland-overlay
138 01:48:45.680399 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
139 01:48:45.680491 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
140 01:48:45.680555 skipped lava-multinode-overlay
141 01:48:45.680635 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
142 01:48:45.680717 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
143 01:48:45.680790 Loading test definitions
144 01:48:45.680886 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
145 01:48:45.680971 Using /lava-11733068 at stage 0
146 01:48:45.681298 uuid=11733068_1.4.2.3.1 testdef=None
147 01:48:45.681404 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
148 01:48:45.681494 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
149 01:48:45.682120 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
151 01:48:45.682381 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
152 01:48:45.683032 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
154 01:48:45.683294 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
155 01:48:45.684080 runner path: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/0/tests/0_dmesg test_uuid 11733068_1.4.2.3.1
156 01:48:45.684273 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
158 01:48:45.684597 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
159 01:48:45.684672 Using /lava-11733068 at stage 1
160 01:48:45.685169 uuid=11733068_1.4.2.3.5 testdef=None
161 01:48:45.685312 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
162 01:48:45.685427 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
163 01:48:45.686073 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
165 01:48:45.686422 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
166 01:48:45.687360 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
168 01:48:45.687761 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
169 01:48:45.688657 runner path: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/1/tests/1_bootrr test_uuid 11733068_1.4.2.3.5
170 01:48:45.688858 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
172 01:48:45.689241 Creating lava-test-runner.conf files
173 01:48:45.689354 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/0 for stage 0
174 01:48:45.689530 - 0_dmesg
175 01:48:45.689617 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11733068/lava-overlay-57ov9srb/lava-11733068/1 for stage 1
176 01:48:45.689748 - 1_bootrr
177 01:48:45.689870 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
178 01:48:45.689962 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
179 01:48:45.699606 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
180 01:48:45.699755 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
181 01:48:45.699843 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
182 01:48:45.699954 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
183 01:48:45.700041 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
184 01:48:45.958465 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
185 01:48:45.958872 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
186 01:48:45.958986 extracting modules file /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11733068/extract-overlay-ramdisk-zojj1fa_/ramdisk
187 01:48:45.981105 end: 1.4.4 extract-modules (duration 00:00:00) [common]
188 01:48:45.981273 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
189 01:48:45.981375 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11733068/compress-overlay-erg67oto/overlay-1.4.2.4.tar.gz to ramdisk
190 01:48:45.981447 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11733068/compress-overlay-erg67oto/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11733068/extract-overlay-ramdisk-zojj1fa_/ramdisk
191 01:48:45.990191 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
192 01:48:45.990304 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
193 01:48:45.990394 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
194 01:48:45.990482 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
195 01:48:45.990564 Building ramdisk /var/lib/lava/dispatcher/tmp/11733068/extract-overlay-ramdisk-zojj1fa_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11733068/extract-overlay-ramdisk-zojj1fa_/ramdisk
196 01:48:46.137670 >> 53982 blocks
197 01:48:47.075280 rename /var/lib/lava/dispatcher/tmp/11733068/extract-overlay-ramdisk-zojj1fa_/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/ramdisk/ramdisk.cpio.gz
198 01:48:47.075876 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
199 01:48:47.076039 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
200 01:48:47.076175 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
201 01:48:47.076314 No mkimage arch provided, not using FIT.
202 01:48:47.076445 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
203 01:48:47.076568 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
204 01:48:47.076715 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
205 01:48:47.076843 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
206 01:48:47.076969 No LXC device requested
207 01:48:47.077088 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
208 01:48:47.077219 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
209 01:48:47.077335 end: 1.6 deploy-device-env (duration 00:00:00) [common]
210 01:48:47.077450 Checking files for TFTP limit of 4294967296 bytes.
211 01:48:47.078007 end: 1 tftp-deploy (duration 00:00:02) [common]
212 01:48:47.078148 start: 2 depthcharge-action (timeout 00:05:00) [common]
213 01:48:47.078272 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
214 01:48:47.078453 substitutions:
215 01:48:47.078553 - {DTB}: None
216 01:48:47.078648 - {INITRD}: 11733068/tftp-deploy-ncixsgin/ramdisk/ramdisk.cpio.gz
217 01:48:47.078734 - {KERNEL}: 11733068/tftp-deploy-ncixsgin/kernel/bzImage
218 01:48:47.078819 - {LAVA_MAC}: None
219 01:48:47.078904 - {PRESEED_CONFIG}: None
220 01:48:47.078992 - {PRESEED_LOCAL}: None
221 01:48:47.079093 - {RAMDISK}: 11733068/tftp-deploy-ncixsgin/ramdisk/ramdisk.cpio.gz
222 01:48:47.079186 - {ROOT_PART}: None
223 01:48:47.079273 - {ROOT}: None
224 01:48:47.079360 - {SERVER_IP}: 192.168.201.1
225 01:48:47.079485 - {TEE}: None
226 01:48:47.079572 Parsed boot commands:
227 01:48:47.079669 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
228 01:48:47.079912 Parsed boot commands: tftpboot 192.168.201.1 11733068/tftp-deploy-ncixsgin/kernel/bzImage 11733068/tftp-deploy-ncixsgin/kernel/cmdline 11733068/tftp-deploy-ncixsgin/ramdisk/ramdisk.cpio.gz
229 01:48:47.080035 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
230 01:48:47.080156 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
231 01:48:47.080291 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
232 01:48:47.080420 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
233 01:48:47.080532 Not connected, no need to disconnect.
234 01:48:47.080643 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
235 01:48:47.080767 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
236 01:48:47.080868 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-3'
237 01:48:47.085212 Setting prompt string to ['lava-test: # ']
238 01:48:47.085715 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
239 01:48:47.085857 end: 2.2.1 reset-connection (duration 00:00:00) [common]
240 01:48:47.085999 start: 2.2.2 reset-device (timeout 00:05:00) [common]
241 01:48:47.086152 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
242 01:48:47.086481 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=reboot'
243 01:48:52.221879 >> Command sent successfully.
244 01:48:52.224267 Returned 0 in 5 seconds
245 01:48:52.324682 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
247 01:48:52.325124 end: 2.2.2 reset-device (duration 00:00:05) [common]
248 01:48:52.325265 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
249 01:48:52.325392 Setting prompt string to 'Starting depthcharge on Voema...'
250 01:48:52.325498 Changing prompt to 'Starting depthcharge on Voema...'
251 01:48:52.325598 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
252 01:48:52.325965 [Enter `^Ec?' for help]
253 01:48:53.958282
254 01:48:53.958432
255 01:48:53.968344 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
256 01:48:53.971702 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
257 01:48:53.978109 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
258 01:48:53.981660 CPU: AES supported, TXT NOT supported, VT supported
259 01:48:53.988059 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
260 01:48:53.991581 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
261 01:48:53.998288 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
262 01:48:54.001234 VBOOT: Loading verstage.
263 01:48:54.004964 FMAP: Found "FLASH" version 1.1 at 0x1804000.
264 01:48:54.011524 FMAP: base = 0x0 size = 0x2000000 #areas = 32
265 01:48:54.014679 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
266 01:48:54.025050 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
267 01:48:54.031470 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
268 01:48:54.031559
269 01:48:54.031646
270 01:48:54.044917 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
271 01:48:54.058518 Probing TPM: . done!
272 01:48:54.061852 TPM ready after 0 ms
273 01:48:54.065260 Connected to device vid:did:rid of 1ae0:0028:00
274 01:48:54.076457 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
275 01:48:54.083391 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
276 01:48:54.086495 Initialized TPM device CR50 revision 0
277 01:48:54.137089 tlcl_send_startup: Startup return code is 0
278 01:48:54.137199 TPM: setup succeeded
279 01:48:54.151404 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
280 01:48:54.165620 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
281 01:48:54.178434 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
282 01:48:54.188020 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
283 01:48:54.191526 Chrome EC: UHEPI supported
284 01:48:54.195234 Phase 1
285 01:48:54.198549 FMAP: area GBB found @ 1805000 (458752 bytes)
286 01:48:54.205062 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
287 01:48:54.215267 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
288 01:48:54.221962 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
289 01:48:54.228296 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
290 01:48:54.231575 Recovery requested (1009000e)
291 01:48:54.235270 TPM: Extending digest for VBOOT: boot mode into PCR 0
292 01:48:54.246506 tlcl_extend: response is 0
293 01:48:54.253021 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
294 01:48:54.262977 tlcl_extend: response is 0
295 01:48:54.269808 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
296 01:48:54.276203 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
297 01:48:54.282986 BS: verstage times (exec / console): total (unknown) / 142 ms
298 01:48:54.283091
299 01:48:54.283194
300 01:48:54.296164 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
301 01:48:54.302667 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
302 01:48:54.306165 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
303 01:48:54.309977 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
304 01:48:54.315967 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
305 01:48:54.319562 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
306 01:48:54.322892 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
307 01:48:54.326171 TCO_STS: 0000 0000
308 01:48:54.329453 GEN_PMCON: d0015038 00002200
309 01:48:54.332494 GBLRST_CAUSE: 00000000 00000000
310 01:48:54.332583 HPR_CAUSE0: 00000000
311 01:48:54.335731 prev_sleep_state 5
312 01:48:54.339588 Boot Count incremented to 24212
313 01:48:54.345979 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
314 01:48:54.352528 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
315 01:48:54.362492 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
316 01:48:54.368981 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
317 01:48:54.372596 Chrome EC: UHEPI supported
318 01:48:54.378801 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
319 01:48:54.389894 Probing TPM: done!
320 01:48:54.397005 Connected to device vid:did:rid of 1ae0:0028:00
321 01:48:54.404800 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
322 01:48:54.414413 Initialized TPM device CR50 revision 0
323 01:48:54.425218 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
324 01:48:54.431661 MRC: Hash idx 0x100b comparison successful.
325 01:48:54.434942 MRC cache found, size faa8
326 01:48:54.435029 bootmode is set to: 2
327 01:48:54.438169 SPD index = 0
328 01:48:54.445370 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
329 01:48:54.448542 SPD: module type is LPDDR4X
330 01:48:54.451939 SPD: module part number is MT53E512M64D4NW-046
331 01:48:54.458065 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
332 01:48:54.465100 SPD: device width 16 bits, bus width 16 bits
333 01:48:54.467899 SPD: module size is 1024 MB (per channel)
334 01:48:54.900697 CBMEM:
335 01:48:54.904174 IMD: root @ 0x76fff000 254 entries.
336 01:48:54.907616 IMD: root @ 0x76ffec00 62 entries.
337 01:48:54.911185 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
338 01:48:54.917444 FMAP: area RW_VPD found @ f35000 (8192 bytes)
339 01:48:54.921146 External stage cache:
340 01:48:54.924391 IMD: root @ 0x7b3ff000 254 entries.
341 01:48:54.927347 IMD: root @ 0x7b3fec00 62 entries.
342 01:48:54.942759 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
343 01:48:54.949595 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
344 01:48:54.955976 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
345 01:48:54.970316 MRC: 'RECOVERY_MRC_CACHE' does not need update.
346 01:48:54.977482 cse_lite: Skip switching to RW in the recovery path
347 01:48:54.977574 8 DIMMs found
348 01:48:54.977645 SMM Memory Map
349 01:48:54.981093 SMRAM : 0x7b000000 0x800000
350 01:48:54.984855 Subregion 0: 0x7b000000 0x200000
351 01:48:54.987863 Subregion 1: 0x7b200000 0x200000
352 01:48:54.991324 Subregion 2: 0x7b400000 0x400000
353 01:48:54.994773 top_of_ram = 0x77000000
354 01:48:55.001239 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
355 01:48:55.004618 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
356 01:48:55.011002 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
357 01:48:55.015010 MTRR Range: Start=ff000000 End=0 (Size 1000000)
358 01:48:55.021281 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
359 01:48:55.027885 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
360 01:48:55.039630 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
361 01:48:55.046338 Processing 211 relocs. Offset value of 0x74c0b000
362 01:48:55.052797 BS: romstage times (exec / console): total (unknown) / 277 ms
363 01:48:55.059040
364 01:48:55.059155
365 01:48:55.068814 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
366 01:48:55.071859 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
367 01:48:55.082162 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
368 01:48:55.088666 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
369 01:48:55.095263 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
370 01:48:55.102109 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
371 01:48:55.148816 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
372 01:48:55.155698 Processing 5008 relocs. Offset value of 0x75d98000
373 01:48:55.158613 BS: postcar times (exec / console): total (unknown) / 59 ms
374 01:48:55.161929
375 01:48:55.162016
376 01:48:55.172326 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
377 01:48:55.172423 Normal boot
378 01:48:55.175631 FW_CONFIG value is 0x804c02
379 01:48:55.178927 PCI: 00:07.0 disabled by fw_config
380 01:48:55.182297 PCI: 00:07.1 disabled by fw_config
381 01:48:55.185881 PCI: 00:0d.2 disabled by fw_config
382 01:48:55.188944 PCI: 00:1c.7 disabled by fw_config
383 01:48:55.195694 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
384 01:48:55.202126 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
385 01:48:55.205625 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
386 01:48:55.208676 GENERIC: 0.0 disabled by fw_config
387 01:48:55.212105 GENERIC: 1.0 disabled by fw_config
388 01:48:55.218716 fw_config match found: DB_USB=USB3_ACTIVE
389 01:48:55.222268 fw_config match found: DB_USB=USB3_ACTIVE
390 01:48:55.225900 fw_config match found: DB_USB=USB3_ACTIVE
391 01:48:55.228726 fw_config match found: DB_USB=USB3_ACTIVE
392 01:48:55.235320 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
393 01:48:55.242344 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
394 01:48:55.251837 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
395 01:48:55.258645 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
396 01:48:55.262050 microcode: sig=0x806c1 pf=0x80 revision=0x86
397 01:48:55.268726 microcode: Update skipped, already up-to-date
398 01:48:55.275247 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
399 01:48:55.302484 Detected 4 core, 8 thread CPU.
400 01:48:55.305492 Setting up SMI for CPU
401 01:48:55.309051 IED base = 0x7b400000
402 01:48:55.309143 IED size = 0x00400000
403 01:48:55.312594 Will perform SMM setup.
404 01:48:55.319198 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
405 01:48:55.325946 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
406 01:48:55.332185 Processing 16 relocs. Offset value of 0x00030000
407 01:48:55.335651 Attempting to start 7 APs
408 01:48:55.338973 Waiting for 10ms after sending INIT.
409 01:48:55.354237 Waiting for 1st SIPI to complete...done.
410 01:48:55.354345 AP: slot 5 apic_id 4.
411 01:48:55.357934 AP: slot 1 apic_id 1.
412 01:48:55.360975 AP: slot 7 apic_id 6.
413 01:48:55.361084 AP: slot 3 apic_id 7.
414 01:48:55.364448 AP: slot 4 apic_id 5.
415 01:48:55.368040 Waiting for 2nd SIPI to complete...done.
416 01:48:55.370778 AP: slot 6 apic_id 2.
417 01:48:55.374210 AP: slot 2 apic_id 3.
418 01:48:55.380862 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
419 01:48:55.387480 Processing 13 relocs. Offset value of 0x00038000
420 01:48:55.387575 Unable to locate Global NVS
421 01:48:55.397982 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
422 01:48:55.400929 Installing permanent SMM handler to 0x7b000000
423 01:48:55.411011 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
424 01:48:55.414123 Processing 794 relocs. Offset value of 0x7b010000
425 01:48:55.424356 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
426 01:48:55.427449 Processing 13 relocs. Offset value of 0x7b008000
427 01:48:55.434588 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
428 01:48:55.440875 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
429 01:48:55.443955 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
430 01:48:55.450659 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
431 01:48:55.457186 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
432 01:48:55.463927 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
433 01:48:55.470921 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
434 01:48:55.471017 Unable to locate Global NVS
435 01:48:55.480395 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
436 01:48:55.483836 Clearing SMI status registers
437 01:48:55.483920 SMI_STS: PM1
438 01:48:55.487296 PM1_STS: PWRBTN
439 01:48:55.495289 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
440 01:48:55.497262 In relocation handler: CPU 0
441 01:48:55.500496 New SMBASE=0x7b000000 IEDBASE=0x7b400000
442 01:48:55.507335 Writing SMRR. base = 0x7b000006, mask=0xff800c00
443 01:48:55.507462 Relocation complete.
444 01:48:55.517457 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
445 01:48:55.517541 In relocation handler: CPU 1
446 01:48:55.524004 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
447 01:48:55.524096 Relocation complete.
448 01:48:55.530447 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
449 01:48:55.533981 In relocation handler: CPU 6
450 01:48:55.540380 New SMBASE=0x7affe800 IEDBASE=0x7b400000
451 01:48:55.543739 Writing SMRR. base = 0x7b000006, mask=0xff800c00
452 01:48:55.546944 Relocation complete.
453 01:48:55.553973 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
454 01:48:55.557242 In relocation handler: CPU 2
455 01:48:55.560513 New SMBASE=0x7afff800 IEDBASE=0x7b400000
456 01:48:55.563398 Relocation complete.
457 01:48:55.570059 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
458 01:48:55.573548 In relocation handler: CPU 7
459 01:48:55.577133 New SMBASE=0x7affe400 IEDBASE=0x7b400000
460 01:48:55.580308 Writing SMRR. base = 0x7b000006, mask=0xff800c00
461 01:48:55.583549 Relocation complete.
462 01:48:55.590556 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
463 01:48:55.593777 In relocation handler: CPU 3
464 01:48:55.597339 New SMBASE=0x7afff400 IEDBASE=0x7b400000
465 01:48:55.600679 Relocation complete.
466 01:48:55.606960 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
467 01:48:55.610219 In relocation handler: CPU 4
468 01:48:55.613701 New SMBASE=0x7afff000 IEDBASE=0x7b400000
469 01:48:55.617368 Relocation complete.
470 01:48:55.623890 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
471 01:48:55.627435 In relocation handler: CPU 5
472 01:48:55.630373 New SMBASE=0x7affec00 IEDBASE=0x7b400000
473 01:48:55.637388 Writing SMRR. base = 0x7b000006, mask=0xff800c00
474 01:48:55.637475 Relocation complete.
475 01:48:55.641027 Initializing CPU #0
476 01:48:55.644543 CPU: vendor Intel device 806c1
477 01:48:55.648384 CPU: family 06, model 8c, stepping 01
478 01:48:55.648481 Clearing out pending MCEs
479 01:48:55.651998 Setting up local APIC...
480 01:48:55.655243 apic_id: 0x00 done.
481 01:48:55.658773 Turbo is available but hidden
482 01:48:55.662247 Turbo is available and visible
483 01:48:55.665129 microcode: Update skipped, already up-to-date
484 01:48:55.668553 CPU #0 initialized
485 01:48:55.668665 Initializing CPU #2
486 01:48:55.672113 Initializing CPU #6
487 01:48:55.675156 Initializing CPU #4
488 01:48:55.678789 CPU: vendor Intel device 806c1
489 01:48:55.682131 CPU: family 06, model 8c, stepping 01
490 01:48:55.685320 CPU: vendor Intel device 806c1
491 01:48:55.688634 CPU: family 06, model 8c, stepping 01
492 01:48:55.691879 Clearing out pending MCEs
493 01:48:55.695329 CPU: vendor Intel device 806c1
494 01:48:55.698461 CPU: family 06, model 8c, stepping 01
495 01:48:55.698546 Initializing CPU #1
496 01:48:55.701819 Initializing CPU #7
497 01:48:55.705403 Initializing CPU #3
498 01:48:55.705488 Setting up local APIC...
499 01:48:55.708366 CPU: vendor Intel device 806c1
500 01:48:55.711741 CPU: family 06, model 8c, stepping 01
501 01:48:55.715090 Initializing CPU #5
502 01:48:55.718351 Clearing out pending MCEs
503 01:48:55.721674 CPU: vendor Intel device 806c1
504 01:48:55.724974 CPU: family 06, model 8c, stepping 01
505 01:48:55.728534 Setting up local APIC...
506 01:48:55.728619 Clearing out pending MCEs
507 01:48:55.731983 apic_id: 0x02 done.
508 01:48:55.734841 Setting up local APIC...
509 01:48:55.738313 microcode: Update skipped, already up-to-date
510 01:48:55.741803 apic_id: 0x03 done.
511 01:48:55.744893 CPU #6 initialized
512 01:48:55.748286 microcode: Update skipped, already up-to-date
513 01:48:55.751745 apic_id: 0x05 done.
514 01:48:55.751831 Clearing out pending MCEs
515 01:48:55.755204 Clearing out pending MCEs
516 01:48:55.761894 microcode: Update skipped, already up-to-date
517 01:48:55.761981 Setting up local APIC...
518 01:48:55.764852 Setting up local APIC...
519 01:48:55.768129 CPU #2 initialized
520 01:48:55.768214 apic_id: 0x07 done.
521 01:48:55.771718 CPU: vendor Intel device 806c1
522 01:48:55.774502 CPU: family 06, model 8c, stepping 01
523 01:48:55.781766 microcode: Update skipped, already up-to-date
524 01:48:55.784700 Clearing out pending MCEs
525 01:48:55.784785 apic_id: 0x04 done.
526 01:48:55.788035 CPU #4 initialized
527 01:48:55.791635 microcode: Update skipped, already up-to-date
528 01:48:55.795060 Setting up local APIC...
529 01:48:55.795145 CPU #5 initialized
530 01:48:55.798325 CPU #3 initialized
531 01:48:55.801565 apic_id: 0x06 done.
532 01:48:55.804652 CPU: vendor Intel device 806c1
533 01:48:55.808253 CPU: family 06, model 8c, stepping 01
534 01:48:55.811283 Clearing out pending MCEs
535 01:48:55.814840 microcode: Update skipped, already up-to-date
536 01:48:55.817818 Setting up local APIC...
537 01:48:55.817903 CPU #7 initialized
538 01:48:55.821423 apic_id: 0x01 done.
539 01:48:55.824691 microcode: Update skipped, already up-to-date
540 01:48:55.828157 CPU #1 initialized
541 01:48:55.831374 bsp_do_flight_plan done after 459 msecs.
542 01:48:55.834418 CPU: frequency set to 4000 MHz
543 01:48:55.838253 Enabling SMIs.
544 01:48:55.844706 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
545 01:48:55.859515 SATAXPCIE1 indicates PCIe NVMe is present
546 01:48:55.862574 Probing TPM: done!
547 01:48:55.865987 Connected to device vid:did:rid of 1ae0:0028:00
548 01:48:55.876882 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
549 01:48:55.879863 Initialized TPM device CR50 revision 0
550 01:48:55.883350 Enabling S0i3.4
551 01:48:55.889924 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
552 01:48:55.893228 Found a VBT of 8704 bytes after decompression
553 01:48:55.899746 cse_lite: CSE RO boot. HybridStorageMode disabled
554 01:48:55.906509 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
555 01:48:55.982885 FSPS returned 0
556 01:48:55.985816 Executing Phase 1 of FspMultiPhaseSiInit
557 01:48:55.996048 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
558 01:48:55.999762 port C0 DISC req: usage 1 usb3 1 usb2 5
559 01:48:56.002836 Raw Buffer output 0 00000511
560 01:48:56.005976 Raw Buffer output 1 00000000
561 01:48:56.009999 pmc_send_ipc_cmd succeeded
562 01:48:56.016755 port C1 DISC req: usage 1 usb3 2 usb2 3
563 01:48:56.016843 Raw Buffer output 0 00000321
564 01:48:56.019577 Raw Buffer output 1 00000000
565 01:48:56.023899 pmc_send_ipc_cmd succeeded
566 01:48:56.029054 Detected 4 core, 8 thread CPU.
567 01:48:56.032611 Detected 4 core, 8 thread CPU.
568 01:48:56.266980 Display FSP Version Info HOB
569 01:48:56.269883 Reference Code - CPU = a.0.4c.31
570 01:48:56.273294 uCode Version = 0.0.0.86
571 01:48:56.276824 TXT ACM version = ff.ff.ff.ffff
572 01:48:56.280301 Reference Code - ME = a.0.4c.31
573 01:48:56.283238 MEBx version = 0.0.0.0
574 01:48:56.286849 ME Firmware Version = Consumer SKU
575 01:48:56.289764 Reference Code - PCH = a.0.4c.31
576 01:48:56.293379 PCH-CRID Status = Disabled
577 01:48:56.297116 PCH-CRID Original Value = ff.ff.ff.ffff
578 01:48:56.300170 PCH-CRID New Value = ff.ff.ff.ffff
579 01:48:56.303250 OPROM - RST - RAID = ff.ff.ff.ffff
580 01:48:56.306685 PCH Hsio Version = 4.0.0.0
581 01:48:56.309614 Reference Code - SA - System Agent = a.0.4c.31
582 01:48:56.313070 Reference Code - MRC = 2.0.0.1
583 01:48:56.316386 SA - PCIe Version = a.0.4c.31
584 01:48:56.319656 SA-CRID Status = Disabled
585 01:48:56.323293 SA-CRID Original Value = 0.0.0.1
586 01:48:56.326251 SA-CRID New Value = 0.0.0.1
587 01:48:56.329560 OPROM - VBIOS = ff.ff.ff.ffff
588 01:48:56.333320 IO Manageability Engine FW Version = 11.1.4.0
589 01:48:56.336322 PHY Build Version = 0.0.0.e0
590 01:48:56.339998 Thunderbolt(TM) FW Version = 0.0.0.0
591 01:48:56.346640 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
592 01:48:56.349685 ITSS IRQ Polarities Before:
593 01:48:56.350085 IPC0: 0xffffffff
594 01:48:56.353069 IPC1: 0xffffffff
595 01:48:56.353468 IPC2: 0xffffffff
596 01:48:56.356271 IPC3: 0xffffffff
597 01:48:56.359783 ITSS IRQ Polarities After:
598 01:48:56.360225 IPC0: 0xffffffff
599 01:48:56.363446 IPC1: 0xffffffff
600 01:48:56.363848 IPC2: 0xffffffff
601 01:48:56.366289 IPC3: 0xffffffff
602 01:48:56.369482 Found PCIe Root Port #9 at PCI: 00:1d.0.
603 01:48:56.382772 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
604 01:48:56.393171 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
605 01:48:56.406380 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
606 01:48:56.413223 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
607 01:48:56.413662 Enumerating buses...
608 01:48:56.419326 Show all devs... Before device enumeration.
609 01:48:56.419816 Root Device: enabled 1
610 01:48:56.422639 DOMAIN: 0000: enabled 1
611 01:48:56.426456 CPU_CLUSTER: 0: enabled 1
612 01:48:56.429328 PCI: 00:00.0: enabled 1
613 01:48:56.429798 PCI: 00:02.0: enabled 1
614 01:48:56.433035 PCI: 00:04.0: enabled 1
615 01:48:56.436092 PCI: 00:05.0: enabled 1
616 01:48:56.439769 PCI: 00:06.0: enabled 0
617 01:48:56.440202 PCI: 00:07.0: enabled 0
618 01:48:56.442717 PCI: 00:07.1: enabled 0
619 01:48:56.446420 PCI: 00:07.2: enabled 0
620 01:48:56.449526 PCI: 00:07.3: enabled 0
621 01:48:56.449959 PCI: 00:08.0: enabled 1
622 01:48:56.452915 PCI: 00:09.0: enabled 0
623 01:48:56.456398 PCI: 00:0a.0: enabled 0
624 01:48:56.459479 PCI: 00:0d.0: enabled 1
625 01:48:56.459920 PCI: 00:0d.1: enabled 0
626 01:48:56.462543 PCI: 00:0d.2: enabled 0
627 01:48:56.466186 PCI: 00:0d.3: enabled 0
628 01:48:56.469549 PCI: 00:0e.0: enabled 0
629 01:48:56.469951 PCI: 00:10.2: enabled 1
630 01:48:56.472913 PCI: 00:10.6: enabled 0
631 01:48:56.475888 PCI: 00:10.7: enabled 0
632 01:48:56.476259 PCI: 00:12.0: enabled 0
633 01:48:56.479134 PCI: 00:12.6: enabled 0
634 01:48:56.482977 PCI: 00:13.0: enabled 0
635 01:48:56.485963 PCI: 00:14.0: enabled 1
636 01:48:56.486352 PCI: 00:14.1: enabled 0
637 01:48:56.489741 PCI: 00:14.2: enabled 1
638 01:48:56.492742 PCI: 00:14.3: enabled 1
639 01:48:56.495887 PCI: 00:15.0: enabled 1
640 01:48:56.496291 PCI: 00:15.1: enabled 1
641 01:48:56.499434 PCI: 00:15.2: enabled 1
642 01:48:56.502681 PCI: 00:15.3: enabled 1
643 01:48:56.506537 PCI: 00:16.0: enabled 1
644 01:48:56.507042 PCI: 00:16.1: enabled 0
645 01:48:56.509343 PCI: 00:16.2: enabled 0
646 01:48:56.513063 PCI: 00:16.3: enabled 0
647 01:48:56.513463 PCI: 00:16.4: enabled 0
648 01:48:56.516040 PCI: 00:16.5: enabled 0
649 01:48:56.519574 PCI: 00:17.0: enabled 1
650 01:48:56.522726 PCI: 00:19.0: enabled 0
651 01:48:56.523125 PCI: 00:19.1: enabled 1
652 01:48:56.526225 PCI: 00:19.2: enabled 0
653 01:48:56.529103 PCI: 00:1c.0: enabled 1
654 01:48:56.532808 PCI: 00:1c.1: enabled 0
655 01:48:56.533209 PCI: 00:1c.2: enabled 0
656 01:48:56.536286 PCI: 00:1c.3: enabled 0
657 01:48:56.539244 PCI: 00:1c.4: enabled 0
658 01:48:56.543015 PCI: 00:1c.5: enabled 0
659 01:48:56.543446 PCI: 00:1c.6: enabled 1
660 01:48:56.546079 PCI: 00:1c.7: enabled 0
661 01:48:56.549205 PCI: 00:1d.0: enabled 1
662 01:48:56.552843 PCI: 00:1d.1: enabled 0
663 01:48:56.553319 PCI: 00:1d.2: enabled 1
664 01:48:56.555981 PCI: 00:1d.3: enabled 0
665 01:48:56.559042 PCI: 00:1e.0: enabled 1
666 01:48:56.559481 PCI: 00:1e.1: enabled 0
667 01:48:56.562793 PCI: 00:1e.2: enabled 1
668 01:48:56.565914 PCI: 00:1e.3: enabled 1
669 01:48:56.569284 PCI: 00:1f.0: enabled 1
670 01:48:56.569775 PCI: 00:1f.1: enabled 0
671 01:48:56.572694 PCI: 00:1f.2: enabled 1
672 01:48:56.575821 PCI: 00:1f.3: enabled 1
673 01:48:56.579240 PCI: 00:1f.4: enabled 0
674 01:48:56.579773 PCI: 00:1f.5: enabled 1
675 01:48:56.582480 PCI: 00:1f.6: enabled 0
676 01:48:56.585472 PCI: 00:1f.7: enabled 0
677 01:48:56.585874 APIC: 00: enabled 1
678 01:48:56.588772 GENERIC: 0.0: enabled 1
679 01:48:56.592138 GENERIC: 0.0: enabled 1
680 01:48:56.595644 GENERIC: 1.0: enabled 1
681 01:48:56.596043 GENERIC: 0.0: enabled 1
682 01:48:56.599500 GENERIC: 1.0: enabled 1
683 01:48:56.602539 USB0 port 0: enabled 1
684 01:48:56.605613 GENERIC: 0.0: enabled 1
685 01:48:56.606089 USB0 port 0: enabled 1
686 01:48:56.609160 GENERIC: 0.0: enabled 1
687 01:48:56.612228 I2C: 00:1a: enabled 1
688 01:48:56.612763 I2C: 00:31: enabled 1
689 01:48:56.615689 I2C: 00:32: enabled 1
690 01:48:56.618849 I2C: 00:10: enabled 1
691 01:48:56.619010 I2C: 00:15: enabled 1
692 01:48:56.621814 GENERIC: 0.0: enabled 0
693 01:48:56.625758 GENERIC: 1.0: enabled 0
694 01:48:56.628811 GENERIC: 0.0: enabled 1
695 01:48:56.628895 SPI: 00: enabled 1
696 01:48:56.632037 SPI: 00: enabled 1
697 01:48:56.632122 PNP: 0c09.0: enabled 1
698 01:48:56.635143 GENERIC: 0.0: enabled 1
699 01:48:56.638589 USB3 port 0: enabled 1
700 01:48:56.641814 USB3 port 1: enabled 1
701 01:48:56.641889 USB3 port 2: enabled 0
702 01:48:56.645182 USB3 port 3: enabled 0
703 01:48:56.648994 USB2 port 0: enabled 0
704 01:48:56.649108 USB2 port 1: enabled 1
705 01:48:56.652092 USB2 port 2: enabled 1
706 01:48:56.655178 USB2 port 3: enabled 0
707 01:48:56.659036 USB2 port 4: enabled 1
708 01:48:56.659136 USB2 port 5: enabled 0
709 01:48:56.662057 USB2 port 6: enabled 0
710 01:48:56.665254 USB2 port 7: enabled 0
711 01:48:56.665344 USB2 port 8: enabled 0
712 01:48:56.668454 USB2 port 9: enabled 0
713 01:48:56.671670 USB3 port 0: enabled 0
714 01:48:56.671765 USB3 port 1: enabled 1
715 01:48:56.675271 USB3 port 2: enabled 0
716 01:48:56.678304 USB3 port 3: enabled 0
717 01:48:56.681534 GENERIC: 0.0: enabled 1
718 01:48:56.681618 GENERIC: 1.0: enabled 1
719 01:48:56.685136 APIC: 01: enabled 1
720 01:48:56.688632 APIC: 03: enabled 1
721 01:48:56.688717 APIC: 07: enabled 1
722 01:48:56.691700 APIC: 05: enabled 1
723 01:48:56.691783 APIC: 04: enabled 1
724 01:48:56.695258 APIC: 02: enabled 1
725 01:48:56.698576 APIC: 06: enabled 1
726 01:48:56.698674 Compare with tree...
727 01:48:56.701920 Root Device: enabled 1
728 01:48:56.705361 DOMAIN: 0000: enabled 1
729 01:48:56.708700 PCI: 00:00.0: enabled 1
730 01:48:56.708806 PCI: 00:02.0: enabled 1
731 01:48:56.711877 PCI: 00:04.0: enabled 1
732 01:48:56.714878 GENERIC: 0.0: enabled 1
733 01:48:56.718364 PCI: 00:05.0: enabled 1
734 01:48:56.721865 PCI: 00:06.0: enabled 0
735 01:48:56.721950 PCI: 00:07.0: enabled 0
736 01:48:56.725295 GENERIC: 0.0: enabled 1
737 01:48:56.728316 PCI: 00:07.1: enabled 0
738 01:48:56.731897 GENERIC: 1.0: enabled 1
739 01:48:56.735032 PCI: 00:07.2: enabled 0
740 01:48:56.735117 GENERIC: 0.0: enabled 1
741 01:48:56.738255 PCI: 00:07.3: enabled 0
742 01:48:56.741904 GENERIC: 1.0: enabled 1
743 01:48:56.744858 PCI: 00:08.0: enabled 1
744 01:48:56.748338 PCI: 00:09.0: enabled 0
745 01:48:56.748421 PCI: 00:0a.0: enabled 0
746 01:48:56.751856 PCI: 00:0d.0: enabled 1
747 01:48:56.754776 USB0 port 0: enabled 1
748 01:48:56.758484 USB3 port 0: enabled 1
749 01:48:56.761406 USB3 port 1: enabled 1
750 01:48:56.761491 USB3 port 2: enabled 0
751 01:48:56.765241 USB3 port 3: enabled 0
752 01:48:56.768304 PCI: 00:0d.1: enabled 0
753 01:48:56.771372 PCI: 00:0d.2: enabled 0
754 01:48:56.775193 GENERIC: 0.0: enabled 1
755 01:48:56.778301 PCI: 00:0d.3: enabled 0
756 01:48:56.778384 PCI: 00:0e.0: enabled 0
757 01:48:56.781491 PCI: 00:10.2: enabled 1
758 01:48:56.785095 PCI: 00:10.6: enabled 0
759 01:48:56.788200 PCI: 00:10.7: enabled 0
760 01:48:56.788284 PCI: 00:12.0: enabled 0
761 01:48:56.791443 PCI: 00:12.6: enabled 0
762 01:48:56.794986 PCI: 00:13.0: enabled 0
763 01:48:56.798158 PCI: 00:14.0: enabled 1
764 01:48:56.801493 USB0 port 0: enabled 1
765 01:48:56.801606 USB2 port 0: enabled 0
766 01:48:56.804973 USB2 port 1: enabled 1
767 01:48:56.807941 USB2 port 2: enabled 1
768 01:48:56.811284 USB2 port 3: enabled 0
769 01:48:56.814546 USB2 port 4: enabled 1
770 01:48:56.817929 USB2 port 5: enabled 0
771 01:48:56.818012 USB2 port 6: enabled 0
772 01:48:56.821102 USB2 port 7: enabled 0
773 01:48:56.824679 USB2 port 8: enabled 0
774 01:48:56.828112 USB2 port 9: enabled 0
775 01:48:56.831228 USB3 port 0: enabled 0
776 01:48:56.834554 USB3 port 1: enabled 1
777 01:48:56.834697 USB3 port 2: enabled 0
778 01:48:56.838044 USB3 port 3: enabled 0
779 01:48:56.841514 PCI: 00:14.1: enabled 0
780 01:48:56.844363 PCI: 00:14.2: enabled 1
781 01:48:56.847709 PCI: 00:14.3: enabled 1
782 01:48:56.847794 GENERIC: 0.0: enabled 1
783 01:48:56.851418 PCI: 00:15.0: enabled 1
784 01:48:56.854429 I2C: 00:1a: enabled 1
785 01:48:56.857920 I2C: 00:31: enabled 1
786 01:48:56.858009 I2C: 00:32: enabled 1
787 01:48:56.861278 PCI: 00:15.1: enabled 1
788 01:48:56.864555 I2C: 00:10: enabled 1
789 01:48:56.867719 PCI: 00:15.2: enabled 1
790 01:48:56.871000 PCI: 00:15.3: enabled 1
791 01:48:56.871084 PCI: 00:16.0: enabled 1
792 01:48:56.874708 PCI: 00:16.1: enabled 0
793 01:48:56.877854 PCI: 00:16.2: enabled 0
794 01:48:56.880938 PCI: 00:16.3: enabled 0
795 01:48:56.884698 PCI: 00:16.4: enabled 0
796 01:48:56.884782 PCI: 00:16.5: enabled 0
797 01:48:56.888742 PCI: 00:17.0: enabled 1
798 01:48:56.892206 PCI: 00:19.0: enabled 0
799 01:48:56.892291 PCI: 00:19.1: enabled 1
800 01:48:56.895371 I2C: 00:15: enabled 1
801 01:48:56.899280 PCI: 00:19.2: enabled 0
802 01:48:56.902233 PCI: 00:1d.0: enabled 1
803 01:48:56.906098 GENERIC: 0.0: enabled 1
804 01:48:56.906182 PCI: 00:1e.0: enabled 1
805 01:48:56.909242 PCI: 00:1e.1: enabled 0
806 01:48:56.912207 PCI: 00:1e.2: enabled 1
807 01:48:56.915390 SPI: 00: enabled 1
808 01:48:56.915482 PCI: 00:1e.3: enabled 1
809 01:48:56.918992 SPI: 00: enabled 1
810 01:48:56.922184 PCI: 00:1f.0: enabled 1
811 01:48:56.967669 PNP: 0c09.0: enabled 1
812 01:48:56.968150 PCI: 00:1f.1: enabled 0
813 01:48:56.968515 PCI: 00:1f.2: enabled 1
814 01:48:56.969314 GENERIC: 0.0: enabled 1
815 01:48:56.969770 GENERIC: 0.0: enabled 1
816 01:48:56.970089 GENERIC: 1.0: enabled 1
817 01:48:56.970399 PCI: 00:1f.3: enabled 1
818 01:48:56.970698 PCI: 00:1f.4: enabled 0
819 01:48:56.970968 PCI: 00:1f.5: enabled 1
820 01:48:56.971424 PCI: 00:1f.6: enabled 0
821 01:48:56.971805 PCI: 00:1f.7: enabled 0
822 01:48:56.972313 CPU_CLUSTER: 0: enabled 1
823 01:48:56.972642 APIC: 00: enabled 1
824 01:48:56.972916 APIC: 01: enabled 1
825 01:48:56.973211 APIC: 03: enabled 1
826 01:48:56.973492 APIC: 07: enabled 1
827 01:48:56.973967 APIC: 05: enabled 1
828 01:48:56.974436 APIC: 04: enabled 1
829 01:48:56.974937 APIC: 02: enabled 1
830 01:48:56.975514 APIC: 06: enabled 1
831 01:48:56.975948 Root Device scanning...
832 01:48:56.979220 scan_static_bus for Root Device
833 01:48:56.982415 DOMAIN: 0000 enabled
834 01:48:56.985942 CPU_CLUSTER: 0 enabled
835 01:48:56.986366 DOMAIN: 0000 scanning...
836 01:48:56.988961 PCI: pci_scan_bus for bus 00
837 01:48:56.992195 PCI: 00:00.0 [8086/0000] ops
838 01:48:56.995901 PCI: 00:00.0 [8086/9a12] enabled
839 01:48:56.998731 PCI: 00:02.0 [8086/0000] bus ops
840 01:48:57.002646 PCI: 00:02.0 [8086/9a40] enabled
841 01:48:57.005666 PCI: 00:04.0 [8086/0000] bus ops
842 01:48:57.008718 PCI: 00:04.0 [8086/9a03] enabled
843 01:48:57.012557 PCI: 00:05.0 [8086/9a19] enabled
844 01:48:57.015655 PCI: 00:07.0 [0000/0000] hidden
845 01:48:57.019496 PCI: 00:08.0 [8086/9a11] enabled
846 01:48:57.022319 PCI: 00:0a.0 [8086/9a0d] disabled
847 01:48:57.025557 PCI: 00:0d.0 [8086/0000] bus ops
848 01:48:57.028964 PCI: 00:0d.0 [8086/9a13] enabled
849 01:48:57.032110 PCI: 00:14.0 [8086/0000] bus ops
850 01:48:57.035721 PCI: 00:14.0 [8086/a0ed] enabled
851 01:48:57.039269 PCI: 00:14.2 [8086/a0ef] enabled
852 01:48:57.042556 PCI: 00:14.3 [8086/0000] bus ops
853 01:48:57.045410 PCI: 00:14.3 [8086/a0f0] enabled
854 01:48:57.049001 PCI: 00:15.0 [8086/0000] bus ops
855 01:48:57.052438 PCI: 00:15.0 [8086/a0e8] enabled
856 01:48:57.055357 PCI: 00:15.1 [8086/0000] bus ops
857 01:48:57.059204 PCI: 00:15.1 [8086/a0e9] enabled
858 01:48:57.062017 PCI: 00:15.2 [8086/0000] bus ops
859 01:48:57.065448 PCI: 00:15.2 [8086/a0ea] enabled
860 01:48:57.069077 PCI: 00:15.3 [8086/0000] bus ops
861 01:48:57.072493 PCI: 00:15.3 [8086/a0eb] enabled
862 01:48:57.075482 PCI: 00:16.0 [8086/0000] ops
863 01:48:57.078778 PCI: 00:16.0 [8086/a0e0] enabled
864 01:48:57.085477 PCI: Static device PCI: 00:17.0 not found, disabling it.
865 01:48:57.088807 PCI: 00:19.0 [8086/0000] bus ops
866 01:48:57.092342 PCI: 00:19.0 [8086/a0c5] disabled
867 01:48:57.095832 PCI: 00:19.1 [8086/0000] bus ops
868 01:48:57.099028 PCI: 00:19.1 [8086/a0c6] enabled
869 01:48:57.102529 PCI: 00:1d.0 [8086/0000] bus ops
870 01:48:57.105731 PCI: 00:1d.0 [8086/a0b0] enabled
871 01:48:57.108726 PCI: 00:1e.0 [8086/0000] ops
872 01:48:57.112526 PCI: 00:1e.0 [8086/a0a8] enabled
873 01:48:57.115564 PCI: 00:1e.2 [8086/0000] bus ops
874 01:48:57.118861 PCI: 00:1e.2 [8086/a0aa] enabled
875 01:48:57.122503 PCI: 00:1e.3 [8086/0000] bus ops
876 01:48:57.125604 PCI: 00:1e.3 [8086/a0ab] enabled
877 01:48:57.128837 PCI: 00:1f.0 [8086/0000] bus ops
878 01:48:57.132318 PCI: 00:1f.0 [8086/a087] enabled
879 01:48:57.132761 RTC Init
880 01:48:57.135472 Set power on after power failure.
881 01:48:57.139084 Disabling Deep S3
882 01:48:57.139593 Disabling Deep S3
883 01:48:57.142254 Disabling Deep S4
884 01:48:57.142727 Disabling Deep S4
885 01:48:57.145889 Disabling Deep S5
886 01:48:57.148762 Disabling Deep S5
887 01:48:57.152118 PCI: 00:1f.2 [0000/0000] hidden
888 01:48:57.155564 PCI: 00:1f.3 [8086/0000] bus ops
889 01:48:57.159083 PCI: 00:1f.3 [8086/a0c8] enabled
890 01:48:57.162120 PCI: 00:1f.5 [8086/0000] bus ops
891 01:48:57.165185 PCI: 00:1f.5 [8086/a0a4] enabled
892 01:48:57.168736 PCI: Leftover static devices:
893 01:48:57.169328 PCI: 00:10.2
894 01:48:57.169687 PCI: 00:10.6
895 01:48:57.172525 PCI: 00:10.7
896 01:48:57.173016 PCI: 00:06.0
897 01:48:57.175496 PCI: 00:07.1
898 01:48:57.175961 PCI: 00:07.2
899 01:48:57.176295 PCI: 00:07.3
900 01:48:57.179034 PCI: 00:09.0
901 01:48:57.179539 PCI: 00:0d.1
902 01:48:57.182401 PCI: 00:0d.2
903 01:48:57.182978 PCI: 00:0d.3
904 01:48:57.183320 PCI: 00:0e.0
905 01:48:57.185419 PCI: 00:12.0
906 01:48:57.185887 PCI: 00:12.6
907 01:48:57.189098 PCI: 00:13.0
908 01:48:57.189519 PCI: 00:14.1
909 01:48:57.191912 PCI: 00:16.1
910 01:48:57.192334 PCI: 00:16.2
911 01:48:57.192859 PCI: 00:16.3
912 01:48:57.195661 PCI: 00:16.4
913 01:48:57.196153 PCI: 00:16.5
914 01:48:57.199071 PCI: 00:17.0
915 01:48:57.199536 PCI: 00:19.2
916 01:48:57.199879 PCI: 00:1e.1
917 01:48:57.202321 PCI: 00:1f.1
918 01:48:57.202768 PCI: 00:1f.4
919 01:48:57.205864 PCI: 00:1f.6
920 01:48:57.206406 PCI: 00:1f.7
921 01:48:57.208800 PCI: Check your devicetree.cb.
922 01:48:57.212134 PCI: 00:02.0 scanning...
923 01:48:57.215831 scan_generic_bus for PCI: 00:02.0
924 01:48:57.218856 scan_generic_bus for PCI: 00:02.0 done
925 01:48:57.222716 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
926 01:48:57.225834 PCI: 00:04.0 scanning...
927 01:48:57.229025 scan_generic_bus for PCI: 00:04.0
928 01:48:57.232366 GENERIC: 0.0 enabled
929 01:48:57.238896 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
930 01:48:57.241920 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
931 01:48:57.245714 PCI: 00:0d.0 scanning...
932 01:48:57.249057 scan_static_bus for PCI: 00:0d.0
933 01:48:57.251915 USB0 port 0 enabled
934 01:48:57.252343 USB0 port 0 scanning...
935 01:48:57.255503 scan_static_bus for USB0 port 0
936 01:48:57.258962 USB3 port 0 enabled
937 01:48:57.262208 USB3 port 1 enabled
938 01:48:57.262770 USB3 port 2 disabled
939 01:48:57.265469 USB3 port 3 disabled
940 01:48:57.268546 USB3 port 0 scanning...
941 01:48:57.272096 scan_static_bus for USB3 port 0
942 01:48:57.274976 scan_static_bus for USB3 port 0 done
943 01:48:57.278664 scan_bus: bus USB3 port 0 finished in 6 msecs
944 01:48:57.282325 USB3 port 1 scanning...
945 01:48:57.285661 scan_static_bus for USB3 port 1
946 01:48:57.288427 scan_static_bus for USB3 port 1 done
947 01:48:57.295305 scan_bus: bus USB3 port 1 finished in 6 msecs
948 01:48:57.298267 scan_static_bus for USB0 port 0 done
949 01:48:57.301787 scan_bus: bus USB0 port 0 finished in 43 msecs
950 01:48:57.305336 scan_static_bus for PCI: 00:0d.0 done
951 01:48:57.311953 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
952 01:48:57.312386 PCI: 00:14.0 scanning...
953 01:48:57.315206 scan_static_bus for PCI: 00:14.0
954 01:48:57.318133 USB0 port 0 enabled
955 01:48:57.321469 USB0 port 0 scanning...
956 01:48:57.325544 scan_static_bus for USB0 port 0
957 01:48:57.328270 USB2 port 0 disabled
958 01:48:57.328786 USB2 port 1 enabled
959 01:48:57.331289 USB2 port 2 enabled
960 01:48:57.331753 USB2 port 3 disabled
961 01:48:57.334987 USB2 port 4 enabled
962 01:48:57.338162 USB2 port 5 disabled
963 01:48:57.338720 USB2 port 6 disabled
964 01:48:57.341578 USB2 port 7 disabled
965 01:48:57.345260 USB2 port 8 disabled
966 01:48:57.345810 USB2 port 9 disabled
967 01:48:57.348104 USB3 port 0 disabled
968 01:48:57.351243 USB3 port 1 enabled
969 01:48:57.351784 USB3 port 2 disabled
970 01:48:57.355009 USB3 port 3 disabled
971 01:48:57.358201 USB2 port 1 scanning...
972 01:48:57.361279 scan_static_bus for USB2 port 1
973 01:48:57.364709 scan_static_bus for USB2 port 1 done
974 01:48:57.368152 scan_bus: bus USB2 port 1 finished in 6 msecs
975 01:48:57.371488 USB2 port 2 scanning...
976 01:48:57.374576 scan_static_bus for USB2 port 2
977 01:48:57.378110 scan_static_bus for USB2 port 2 done
978 01:48:57.381666 scan_bus: bus USB2 port 2 finished in 6 msecs
979 01:48:57.384770 USB2 port 4 scanning...
980 01:48:57.387961 scan_static_bus for USB2 port 4
981 01:48:57.391707 scan_static_bus for USB2 port 4 done
982 01:48:57.397699 scan_bus: bus USB2 port 4 finished in 6 msecs
983 01:48:57.398269 USB3 port 1 scanning...
984 01:48:57.401205 scan_static_bus for USB3 port 1
985 01:48:57.408243 scan_static_bus for USB3 port 1 done
986 01:48:57.411085 scan_bus: bus USB3 port 1 finished in 6 msecs
987 01:48:57.414800 scan_static_bus for USB0 port 0 done
988 01:48:57.417955 scan_bus: bus USB0 port 0 finished in 93 msecs
989 01:48:57.424578 scan_static_bus for PCI: 00:14.0 done
990 01:48:57.427693 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
991 01:48:57.430892 PCI: 00:14.3 scanning...
992 01:48:57.434396 scan_static_bus for PCI: 00:14.3
993 01:48:57.437579 GENERIC: 0.0 enabled
994 01:48:57.441190 scan_static_bus for PCI: 00:14.3 done
995 01:48:57.444540 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
996 01:48:57.447539 PCI: 00:15.0 scanning...
997 01:48:57.451275 scan_static_bus for PCI: 00:15.0
998 01:48:57.454293 I2C: 00:1a enabled
999 01:48:57.454761 I2C: 00:31 enabled
1000 01:48:57.457810 I2C: 00:32 enabled
1001 01:48:57.460809 scan_static_bus for PCI: 00:15.0 done
1002 01:48:57.464717 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1003 01:48:57.468537 PCI: 00:15.1 scanning...
1004 01:48:57.471467 scan_static_bus for PCI: 00:15.1
1005 01:48:57.475176 I2C: 00:10 enabled
1006 01:48:57.478270 scan_static_bus for PCI: 00:15.1 done
1007 01:48:57.481521 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1008 01:48:57.484590 PCI: 00:15.2 scanning...
1009 01:48:57.488082 scan_static_bus for PCI: 00:15.2
1010 01:48:57.491260 scan_static_bus for PCI: 00:15.2 done
1011 01:48:57.498385 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1012 01:48:57.498856 PCI: 00:15.3 scanning...
1013 01:48:57.501326 scan_static_bus for PCI: 00:15.3
1014 01:48:57.508385 scan_static_bus for PCI: 00:15.3 done
1015 01:48:57.511251 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1016 01:48:57.514637 PCI: 00:19.1 scanning...
1017 01:48:57.518222 scan_static_bus for PCI: 00:19.1
1018 01:48:57.518755 I2C: 00:15 enabled
1019 01:48:57.524578 scan_static_bus for PCI: 00:19.1 done
1020 01:48:57.528183 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1021 01:48:57.531340 PCI: 00:1d.0 scanning...
1022 01:48:57.534963 do_pci_scan_bridge for PCI: 00:1d.0
1023 01:48:57.538075 PCI: pci_scan_bus for bus 01
1024 01:48:57.541009 PCI: 01:00.0 [1c5c/174a] enabled
1025 01:48:57.541491 GENERIC: 0.0 enabled
1026 01:48:57.547726 Enabling Common Clock Configuration
1027 01:48:57.551498 L1 Sub-State supported from root port 29
1028 01:48:57.554854 L1 Sub-State Support = 0xf
1029 01:48:57.557785 CommonModeRestoreTime = 0x28
1030 01:48:57.561551 Power On Value = 0x16, Power On Scale = 0x0
1031 01:48:57.562049 ASPM: Enabled L1
1032 01:48:57.567918 PCIe: Max_Payload_Size adjusted to 128
1033 01:48:57.571624 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1034 01:48:57.574615 PCI: 00:1e.2 scanning...
1035 01:48:57.578325 scan_generic_bus for PCI: 00:1e.2
1036 01:48:57.578812 SPI: 00 enabled
1037 01:48:57.584689 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1038 01:48:57.591661 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1039 01:48:57.592158 PCI: 00:1e.3 scanning...
1040 01:48:57.594489 scan_generic_bus for PCI: 00:1e.3
1041 01:48:57.598149 SPI: 00 enabled
1042 01:48:57.604585 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1043 01:48:57.607713 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1044 01:48:57.611314 PCI: 00:1f.0 scanning...
1045 01:48:57.614620 scan_static_bus for PCI: 00:1f.0
1046 01:48:57.617931 PNP: 0c09.0 enabled
1047 01:48:57.618383 PNP: 0c09.0 scanning...
1048 01:48:57.621295 scan_static_bus for PNP: 0c09.0
1049 01:48:57.627831 scan_static_bus for PNP: 0c09.0 done
1050 01:48:57.631289 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1051 01:48:57.634490 scan_static_bus for PCI: 00:1f.0 done
1052 01:48:57.641344 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1053 01:48:57.641895 PCI: 00:1f.2 scanning...
1054 01:48:57.644399 scan_static_bus for PCI: 00:1f.2
1055 01:48:57.648057 GENERIC: 0.0 enabled
1056 01:48:57.651169 GENERIC: 0.0 scanning...
1057 01:48:57.654132 scan_static_bus for GENERIC: 0.0
1058 01:48:57.654552 GENERIC: 0.0 enabled
1059 01:48:57.657914 GENERIC: 1.0 enabled
1060 01:48:57.661429 scan_static_bus for GENERIC: 0.0 done
1061 01:48:57.667850 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1062 01:48:57.670920 scan_static_bus for PCI: 00:1f.2 done
1063 01:48:57.674104 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1064 01:48:57.677739 PCI: 00:1f.3 scanning...
1065 01:48:57.680827 scan_static_bus for PCI: 00:1f.3
1066 01:48:57.684434 scan_static_bus for PCI: 00:1f.3 done
1067 01:48:57.691058 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1068 01:48:57.691648 PCI: 00:1f.5 scanning...
1069 01:48:57.698044 scan_generic_bus for PCI: 00:1f.5
1070 01:48:57.701124 scan_generic_bus for PCI: 00:1f.5 done
1071 01:48:57.704746 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1072 01:48:57.711091 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1073 01:48:57.714801 scan_static_bus for Root Device done
1074 01:48:57.717844 scan_bus: bus Root Device finished in 736 msecs
1075 01:48:57.718265 done
1076 01:48:57.724377 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1077 01:48:57.728079 Chrome EC: UHEPI supported
1078 01:48:57.734585 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1079 01:48:57.741164 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1080 01:48:57.744509 SPI flash protection: WPSW=0 SRP0=0
1081 01:48:57.750973 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1082 01:48:57.754831 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1083 01:48:57.757776 found VGA at PCI: 00:02.0
1084 01:48:57.760810 Setting up VGA for PCI: 00:02.0
1085 01:48:57.767903 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1086 01:48:57.770825 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1087 01:48:57.774409 Allocating resources...
1088 01:48:57.777762 Reading resources...
1089 01:48:57.781075 Root Device read_resources bus 0 link: 0
1090 01:48:57.784328 DOMAIN: 0000 read_resources bus 0 link: 0
1091 01:48:57.791161 PCI: 00:04.0 read_resources bus 1 link: 0
1092 01:48:57.794076 PCI: 00:04.0 read_resources bus 1 link: 0 done
1093 01:48:57.800767 PCI: 00:0d.0 read_resources bus 0 link: 0
1094 01:48:57.803734 USB0 port 0 read_resources bus 0 link: 0
1095 01:48:57.810323 USB0 port 0 read_resources bus 0 link: 0 done
1096 01:48:57.814102 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1097 01:48:57.817121 PCI: 00:14.0 read_resources bus 0 link: 0
1098 01:48:57.824049 USB0 port 0 read_resources bus 0 link: 0
1099 01:48:57.827114 USB0 port 0 read_resources bus 0 link: 0 done
1100 01:48:57.833910 PCI: 00:14.0 read_resources bus 0 link: 0 done
1101 01:48:57.837155 PCI: 00:14.3 read_resources bus 0 link: 0
1102 01:48:57.843937 PCI: 00:14.3 read_resources bus 0 link: 0 done
1103 01:48:57.847649 PCI: 00:15.0 read_resources bus 0 link: 0
1104 01:48:57.854263 PCI: 00:15.0 read_resources bus 0 link: 0 done
1105 01:48:57.857350 PCI: 00:15.1 read_resources bus 0 link: 0
1106 01:48:57.864004 PCI: 00:15.1 read_resources bus 0 link: 0 done
1107 01:48:57.867253 PCI: 00:19.1 read_resources bus 0 link: 0
1108 01:48:57.874647 PCI: 00:19.1 read_resources bus 0 link: 0 done
1109 01:48:57.877729 PCI: 00:1d.0 read_resources bus 1 link: 0
1110 01:48:57.884251 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1111 01:48:57.887381 PCI: 00:1e.2 read_resources bus 2 link: 0
1112 01:48:57.894350 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1113 01:48:57.897485 PCI: 00:1e.3 read_resources bus 3 link: 0
1114 01:48:57.904578 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1115 01:48:57.907670 PCI: 00:1f.0 read_resources bus 0 link: 0
1116 01:48:57.914498 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1117 01:48:57.917793 PCI: 00:1f.2 read_resources bus 0 link: 0
1118 01:48:57.920812 GENERIC: 0.0 read_resources bus 0 link: 0
1119 01:48:57.928229 GENERIC: 0.0 read_resources bus 0 link: 0 done
1120 01:48:57.931315 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1121 01:48:57.938592 DOMAIN: 0000 read_resources bus 0 link: 0 done
1122 01:48:57.941665 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1123 01:48:57.948884 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1124 01:48:57.951874 Root Device read_resources bus 0 link: 0 done
1125 01:48:57.954923 Done reading resources.
1126 01:48:57.962021 Show resources in subtree (Root Device)...After reading.
1127 01:48:57.964899 Root Device child on link 0 DOMAIN: 0000
1128 01:48:57.968828 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1129 01:48:57.978433 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1130 01:48:57.988581 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1131 01:48:57.991562 PCI: 00:00.0
1132 01:48:58.001597 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1133 01:48:58.008256 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1134 01:48:58.018080 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1135 01:48:58.028216 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1136 01:48:58.038401 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1137 01:48:58.048293 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1138 01:48:58.054549 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1139 01:48:58.064966 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1140 01:48:58.074697 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1141 01:48:58.084375 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1142 01:48:58.094464 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1143 01:48:58.104466 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1144 01:48:58.111108 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1145 01:48:58.120984 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1146 01:48:58.131346 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1147 01:48:58.141043 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1148 01:48:58.151257 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1149 01:48:58.160684 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1150 01:48:58.167344 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1151 01:48:58.177356 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1152 01:48:58.180957 PCI: 00:02.0
1153 01:48:58.190554 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 01:48:58.200638 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1155 01:48:58.210667 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1156 01:48:58.214233 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1157 01:48:58.224074 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1158 01:48:58.227113 GENERIC: 0.0
1159 01:48:58.227196 PCI: 00:05.0
1160 01:48:58.237146 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1161 01:48:58.243882 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1162 01:48:58.243966 GENERIC: 0.0
1163 01:48:58.247396 PCI: 00:08.0
1164 01:48:58.257095 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1165 01:48:58.257267 PCI: 00:0a.0
1166 01:48:58.260693 PCI: 00:0d.0 child on link 0 USB0 port 0
1167 01:48:58.270398 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 01:48:58.277070 USB0 port 0 child on link 0 USB3 port 0
1169 01:48:58.277154 USB3 port 0
1170 01:48:58.280782 USB3 port 1
1171 01:48:58.280881 USB3 port 2
1172 01:48:58.283769 USB3 port 3
1173 01:48:58.286866 PCI: 00:14.0 child on link 0 USB0 port 0
1174 01:48:58.297319 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1175 01:48:58.300670 USB0 port 0 child on link 0 USB2 port 0
1176 01:48:58.304066 USB2 port 0
1177 01:48:58.306923 USB2 port 1
1178 01:48:58.307005 USB2 port 2
1179 01:48:58.310344 USB2 port 3
1180 01:48:58.310426 USB2 port 4
1181 01:48:58.314035 USB2 port 5
1182 01:48:58.314117 USB2 port 6
1183 01:48:58.317101 USB2 port 7
1184 01:48:58.317184 USB2 port 8
1185 01:48:58.320669 USB2 port 9
1186 01:48:58.320752 USB3 port 0
1187 01:48:58.323746 USB3 port 1
1188 01:48:58.323828 USB3 port 2
1189 01:48:58.326940 USB3 port 3
1190 01:48:58.327022 PCI: 00:14.2
1191 01:48:58.337218 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1192 01:48:58.347018 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1193 01:48:58.353869 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1194 01:48:58.363566 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1195 01:48:58.363650 GENERIC: 0.0
1196 01:48:58.369970 PCI: 00:15.0 child on link 0 I2C: 00:1a
1197 01:48:58.380406 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1198 01:48:58.380491 I2C: 00:1a
1199 01:48:58.383543 I2C: 00:31
1200 01:48:58.383626 I2C: 00:32
1201 01:48:58.387002 PCI: 00:15.1 child on link 0 I2C: 00:10
1202 01:48:58.397218 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 01:48:58.400152 I2C: 00:10
1204 01:48:58.400235 PCI: 00:15.2
1205 01:48:58.410189 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 01:48:58.413424 PCI: 00:15.3
1207 01:48:58.423481 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1208 01:48:58.423565 PCI: 00:16.0
1209 01:48:58.433447 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1210 01:48:58.436351 PCI: 00:19.0
1211 01:48:58.439928 PCI: 00:19.1 child on link 0 I2C: 00:15
1212 01:48:58.449782 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1213 01:48:58.453380 I2C: 00:15
1214 01:48:58.456517 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1215 01:48:58.466350 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1216 01:48:58.473143 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1217 01:48:58.483173 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1218 01:48:58.486609 GENERIC: 0.0
1219 01:48:58.486723 PCI: 01:00.0
1220 01:48:58.496119 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1221 01:48:58.505603 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1222 01:48:58.516003 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1223 01:48:58.516090 PCI: 00:1e.0
1224 01:48:58.529025 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1225 01:48:58.532368 PCI: 00:1e.2 child on link 0 SPI: 00
1226 01:48:58.542527 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1227 01:48:58.542612 SPI: 00
1228 01:48:58.549229 PCI: 00:1e.3 child on link 0 SPI: 00
1229 01:48:58.558817 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 01:48:58.558902 SPI: 00
1231 01:48:58.562307 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1232 01:48:58.572227 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1233 01:48:58.572311 PNP: 0c09.0
1234 01:48:58.582543 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1235 01:48:58.585564 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1236 01:48:58.595512 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1237 01:48:58.605456 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1238 01:48:58.608740 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1239 01:48:58.612088 GENERIC: 0.0
1240 01:48:58.615230 GENERIC: 1.0
1241 01:48:58.615313 PCI: 00:1f.3
1242 01:48:58.625220 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1243 01:48:58.634856 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1244 01:48:58.638470 PCI: 00:1f.5
1245 01:48:58.644958 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1246 01:48:58.651619 CPU_CLUSTER: 0 child on link 0 APIC: 00
1247 01:48:58.651720 APIC: 00
1248 01:48:58.655253 APIC: 01
1249 01:48:58.655336 APIC: 03
1250 01:48:58.655440 APIC: 07
1251 01:48:58.658174 APIC: 05
1252 01:48:58.658256 APIC: 04
1253 01:48:58.658322 APIC: 02
1254 01:48:58.661879 APIC: 06
1255 01:48:58.668137 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1256 01:48:58.674984 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1257 01:48:58.681738 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1258 01:48:58.688262 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1259 01:48:58.691323 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1260 01:48:58.695104 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1261 01:48:58.698248 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1262 01:48:58.708049 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1263 01:48:58.715216 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1264 01:48:58.721404 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1265 01:48:58.728037 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1266 01:48:58.734898 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1267 01:48:58.740965 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1268 01:48:58.751258 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1269 01:48:58.757615 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1270 01:48:58.761186 DOMAIN: 0000: Resource ranges:
1271 01:48:58.764488 * Base: 1000, Size: 800, Tag: 100
1272 01:48:58.767824 * Base: 1900, Size: e700, Tag: 100
1273 01:48:58.774381 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1274 01:48:58.781125 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1275 01:48:58.787733 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1276 01:48:58.794414 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1277 01:48:58.801185 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1278 01:48:58.811119 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1279 01:48:58.817527 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1280 01:48:58.824127 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1281 01:48:58.833895 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1282 01:48:58.841075 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1283 01:48:58.847604 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1284 01:48:58.857300 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1285 01:48:58.864018 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1286 01:48:58.870553 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1287 01:48:58.880488 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1288 01:48:58.887287 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1289 01:48:58.893757 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1290 01:48:58.903695 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1291 01:48:58.910514 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1292 01:48:58.917398 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1293 01:48:58.927050 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1294 01:48:58.933848 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1295 01:48:58.940353 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1296 01:48:58.950097 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1297 01:48:58.956618 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1298 01:48:58.960171 DOMAIN: 0000: Resource ranges:
1299 01:48:58.963658 * Base: 7fc00000, Size: 40400000, Tag: 200
1300 01:48:58.969894 * Base: d0000000, Size: 28000000, Tag: 200
1301 01:48:58.973464 * Base: fa000000, Size: 1000000, Tag: 200
1302 01:48:58.976623 * Base: fb001000, Size: 2fff000, Tag: 200
1303 01:48:58.980452 * Base: fe010000, Size: 2e000, Tag: 200
1304 01:48:58.986539 * Base: fe03f000, Size: d41000, Tag: 200
1305 01:48:58.990190 * Base: fed88000, Size: 8000, Tag: 200
1306 01:48:58.993072 * Base: fed93000, Size: d000, Tag: 200
1307 01:48:58.996462 * Base: feda2000, Size: 1e000, Tag: 200
1308 01:48:59.003015 * Base: fede0000, Size: 1220000, Tag: 200
1309 01:48:59.006668 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1310 01:48:59.012960 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1311 01:48:59.020014 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1312 01:48:59.026496 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1313 01:48:59.033181 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1314 01:48:59.039878 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1315 01:48:59.046475 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1316 01:48:59.053114 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1317 01:48:59.059892 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1318 01:48:59.066306 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1319 01:48:59.072976 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1320 01:48:59.079284 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1321 01:48:59.086062 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1322 01:48:59.092799 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1323 01:48:59.099432 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1324 01:48:59.106273 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1325 01:48:59.112395 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1326 01:48:59.119296 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1327 01:48:59.125916 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1328 01:48:59.132643 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1329 01:48:59.139270 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1330 01:48:59.145608 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1331 01:48:59.152639 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1332 01:48:59.159246 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1333 01:48:59.169016 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1334 01:48:59.172598 PCI: 00:1d.0: Resource ranges:
1335 01:48:59.175916 * Base: 7fc00000, Size: 100000, Tag: 200
1336 01:48:59.182025 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1337 01:48:59.188770 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1338 01:48:59.195446 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1339 01:48:59.205257 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1340 01:48:59.212562 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1341 01:48:59.215631 Root Device assign_resources, bus 0 link: 0
1342 01:48:59.218618 DOMAIN: 0000 assign_resources, bus 0 link: 0
1343 01:48:59.229079 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1344 01:48:59.236335 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1345 01:48:59.245877 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1346 01:48:59.252443 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1347 01:48:59.259028 PCI: 00:04.0 assign_resources, bus 1 link: 0
1348 01:48:59.262434 PCI: 00:04.0 assign_resources, bus 1 link: 0
1349 01:48:59.269351 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1350 01:48:59.279374 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1351 01:48:59.285902 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1352 01:48:59.292431 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1353 01:48:59.296063 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1354 01:48:59.305917 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1355 01:48:59.308946 PCI: 00:14.0 assign_resources, bus 0 link: 0
1356 01:48:59.312738 PCI: 00:14.0 assign_resources, bus 0 link: 0
1357 01:48:59.322574 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1358 01:48:59.328985 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1359 01:48:59.339048 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1360 01:48:59.342175 PCI: 00:14.3 assign_resources, bus 0 link: 0
1361 01:48:59.349009 PCI: 00:14.3 assign_resources, bus 0 link: 0
1362 01:48:59.355637 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1363 01:48:59.358805 PCI: 00:15.0 assign_resources, bus 0 link: 0
1364 01:48:59.365453 PCI: 00:15.0 assign_resources, bus 0 link: 0
1365 01:48:59.372128 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1366 01:48:59.378820 PCI: 00:15.1 assign_resources, bus 0 link: 0
1367 01:48:59.382030 PCI: 00:15.1 assign_resources, bus 0 link: 0
1368 01:48:59.392501 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1369 01:48:59.399121 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1370 01:48:59.408683 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1371 01:48:59.415310 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1372 01:48:59.419048 PCI: 00:19.1 assign_resources, bus 0 link: 0
1373 01:48:59.425343 PCI: 00:19.1 assign_resources, bus 0 link: 0
1374 01:48:59.432102 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1375 01:48:59.441885 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1376 01:48:59.451844 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1377 01:48:59.455367 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1378 01:48:59.465208 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1379 01:48:59.471799 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1380 01:48:59.481407 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1381 01:48:59.485121 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1382 01:48:59.494998 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1383 01:48:59.498653 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1384 01:48:59.501598 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1385 01:48:59.511576 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1386 01:48:59.514861 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1387 01:48:59.521867 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1388 01:48:59.524798 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1389 01:48:59.531773 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1390 01:48:59.534808 LPC: Trying to open IO window from 800 size 1ff
1391 01:48:59.544717 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1392 01:48:59.551399 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1393 01:48:59.558416 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1394 01:48:59.564446 DOMAIN: 0000 assign_resources, bus 0 link: 0
1395 01:48:59.568092 Root Device assign_resources, bus 0 link: 0
1396 01:48:59.571658 Done setting resources.
1397 01:48:59.577872 Show resources in subtree (Root Device)...After assigning values.
1398 01:48:59.580941 Root Device child on link 0 DOMAIN: 0000
1399 01:48:59.587700 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1400 01:48:59.594853 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1401 01:48:59.604160 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1402 01:48:59.607672 PCI: 00:00.0
1403 01:48:59.617337 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1404 01:48:59.627696 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1405 01:48:59.634265 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1406 01:48:59.644133 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1407 01:48:59.654070 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1408 01:48:59.664104 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1409 01:48:59.673848 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1410 01:48:59.684042 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1411 01:48:59.690592 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1412 01:48:59.700229 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1413 01:48:59.710037 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1414 01:48:59.719869 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1415 01:48:59.729973 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1416 01:48:59.736519 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1417 01:48:59.746625 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1418 01:48:59.756748 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1419 01:48:59.766527 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1420 01:48:59.776444 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1421 01:48:59.785969 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1422 01:48:59.795859 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1423 01:48:59.795943 PCI: 00:02.0
1424 01:48:59.806159 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1425 01:48:59.818951 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1426 01:48:59.825756 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1427 01:48:59.832280 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1428 01:48:59.842476 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1429 01:48:59.845933 GENERIC: 0.0
1430 01:48:59.846017 PCI: 00:05.0
1431 01:48:59.856071 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1432 01:48:59.862040 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1433 01:48:59.862123 GENERIC: 0.0
1434 01:48:59.865676 PCI: 00:08.0
1435 01:48:59.875544 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1436 01:48:59.875628 PCI: 00:0a.0
1437 01:48:59.882277 PCI: 00:0d.0 child on link 0 USB0 port 0
1438 01:48:59.892112 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1439 01:48:59.895851 USB0 port 0 child on link 0 USB3 port 0
1440 01:48:59.898711 USB3 port 0
1441 01:48:59.898793 USB3 port 1
1442 01:48:59.902048 USB3 port 2
1443 01:48:59.902130 USB3 port 3
1444 01:48:59.908839 PCI: 00:14.0 child on link 0 USB0 port 0
1445 01:48:59.918218 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1446 01:48:59.921741 USB0 port 0 child on link 0 USB2 port 0
1447 01:48:59.925189 USB2 port 0
1448 01:48:59.925272 USB2 port 1
1449 01:48:59.928222 USB2 port 2
1450 01:48:59.928304 USB2 port 3
1451 01:48:59.931746 USB2 port 4
1452 01:48:59.931828 USB2 port 5
1453 01:48:59.935361 USB2 port 6
1454 01:48:59.935489 USB2 port 7
1455 01:48:59.938795 USB2 port 8
1456 01:48:59.938880 USB2 port 9
1457 01:48:59.941550 USB3 port 0
1458 01:48:59.941633 USB3 port 1
1459 01:48:59.945140 USB3 port 2
1460 01:48:59.948062 USB3 port 3
1461 01:48:59.948145 PCI: 00:14.2
1462 01:48:59.958421 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1463 01:48:59.968468 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1464 01:48:59.974725 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1465 01:48:59.984732 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1466 01:48:59.984815 GENERIC: 0.0
1467 01:48:59.991316 PCI: 00:15.0 child on link 0 I2C: 00:1a
1468 01:49:00.001021 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1469 01:49:00.001119 I2C: 00:1a
1470 01:49:00.004775 I2C: 00:31
1471 01:49:00.004859 I2C: 00:32
1472 01:49:00.008038 PCI: 00:15.1 child on link 0 I2C: 00:10
1473 01:49:00.021220 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1474 01:49:00.021306 I2C: 00:10
1475 01:49:00.024628 PCI: 00:15.2
1476 01:49:00.034673 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1477 01:49:00.034758 PCI: 00:15.3
1478 01:49:00.044361 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1479 01:49:00.047516 PCI: 00:16.0
1480 01:49:00.057639 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1481 01:49:00.057725 PCI: 00:19.0
1482 01:49:00.064268 PCI: 00:19.1 child on link 0 I2C: 00:15
1483 01:49:00.074197 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1484 01:49:00.074283 I2C: 00:15
1485 01:49:00.080367 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1486 01:49:00.087030 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1487 01:49:00.100646 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1488 01:49:00.110543 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1489 01:49:00.113469 GENERIC: 0.0
1490 01:49:00.113561 PCI: 01:00.0
1491 01:49:00.123350 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1492 01:49:00.137328 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1493 01:49:00.146882 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1494 01:49:00.146970 PCI: 00:1e.0
1495 01:49:00.159983 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1496 01:49:00.163263 PCI: 00:1e.2 child on link 0 SPI: 00
1497 01:49:00.173300 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1498 01:49:00.173399 SPI: 00
1499 01:49:00.176497 PCI: 00:1e.3 child on link 0 SPI: 00
1500 01:49:00.190019 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1501 01:49:00.190105 SPI: 00
1502 01:49:00.193260 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1503 01:49:00.203225 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1504 01:49:00.203310 PNP: 0c09.0
1505 01:49:00.212964 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1506 01:49:00.216703 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1507 01:49:00.226382 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1508 01:49:00.236329 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1509 01:49:00.239350 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1510 01:49:00.242986 GENERIC: 0.0
1511 01:49:00.245986 GENERIC: 1.0
1512 01:49:00.246095 PCI: 00:1f.3
1513 01:49:00.256113 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1514 01:49:00.266322 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1515 01:49:00.269722 PCI: 00:1f.5
1516 01:49:00.279307 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1517 01:49:00.282321 CPU_CLUSTER: 0 child on link 0 APIC: 00
1518 01:49:00.285816 APIC: 00
1519 01:49:00.285898 APIC: 01
1520 01:49:00.285963 APIC: 03
1521 01:49:00.289124 APIC: 07
1522 01:49:00.289206 APIC: 05
1523 01:49:00.292312 APIC: 04
1524 01:49:00.292395 APIC: 02
1525 01:49:00.292459 APIC: 06
1526 01:49:00.295655 Done allocating resources.
1527 01:49:00.302299 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1528 01:49:00.309126 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1529 01:49:00.312216 Configure GPIOs for I2S audio on UP4.
1530 01:49:00.319106 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1531 01:49:00.322069 Enabling resources...
1532 01:49:00.325821 PCI: 00:00.0 subsystem <- 8086/9a12
1533 01:49:00.328931 PCI: 00:00.0 cmd <- 06
1534 01:49:00.332396 PCI: 00:02.0 subsystem <- 8086/9a40
1535 01:49:00.335670 PCI: 00:02.0 cmd <- 03
1536 01:49:00.338718 PCI: 00:04.0 subsystem <- 8086/9a03
1537 01:49:00.338796 PCI: 00:04.0 cmd <- 02
1538 01:49:00.345888 PCI: 00:05.0 subsystem <- 8086/9a19
1539 01:49:00.345987 PCI: 00:05.0 cmd <- 02
1540 01:49:00.348826 PCI: 00:08.0 subsystem <- 8086/9a11
1541 01:49:00.352657 PCI: 00:08.0 cmd <- 06
1542 01:49:00.355783 PCI: 00:0d.0 subsystem <- 8086/9a13
1543 01:49:00.359382 PCI: 00:0d.0 cmd <- 02
1544 01:49:00.362431 PCI: 00:14.0 subsystem <- 8086/a0ed
1545 01:49:00.365933 PCI: 00:14.0 cmd <- 02
1546 01:49:00.369143 PCI: 00:14.2 subsystem <- 8086/a0ef
1547 01:49:00.372270 PCI: 00:14.2 cmd <- 02
1548 01:49:00.375758 PCI: 00:14.3 subsystem <- 8086/a0f0
1549 01:49:00.379122 PCI: 00:14.3 cmd <- 02
1550 01:49:00.382421 PCI: 00:15.0 subsystem <- 8086/a0e8
1551 01:49:00.382551 PCI: 00:15.0 cmd <- 02
1552 01:49:00.389470 PCI: 00:15.1 subsystem <- 8086/a0e9
1553 01:49:00.389553 PCI: 00:15.1 cmd <- 02
1554 01:49:00.392356 PCI: 00:15.2 subsystem <- 8086/a0ea
1555 01:49:00.395919 PCI: 00:15.2 cmd <- 02
1556 01:49:00.399378 PCI: 00:15.3 subsystem <- 8086/a0eb
1557 01:49:00.402445 PCI: 00:15.3 cmd <- 02
1558 01:49:00.405980 PCI: 00:16.0 subsystem <- 8086/a0e0
1559 01:49:00.409166 PCI: 00:16.0 cmd <- 02
1560 01:49:00.412748 PCI: 00:19.1 subsystem <- 8086/a0c6
1561 01:49:00.415614 PCI: 00:19.1 cmd <- 02
1562 01:49:00.418860 PCI: 00:1d.0 bridge ctrl <- 0013
1563 01:49:00.422356 PCI: 00:1d.0 subsystem <- 8086/a0b0
1564 01:49:00.425618 PCI: 00:1d.0 cmd <- 06
1565 01:49:00.429291 PCI: 00:1e.0 subsystem <- 8086/a0a8
1566 01:49:00.429404 PCI: 00:1e.0 cmd <- 06
1567 01:49:00.436128 PCI: 00:1e.2 subsystem <- 8086/a0aa
1568 01:49:00.436211 PCI: 00:1e.2 cmd <- 06
1569 01:49:00.439350 PCI: 00:1e.3 subsystem <- 8086/a0ab
1570 01:49:00.442476 PCI: 00:1e.3 cmd <- 02
1571 01:49:00.445812 PCI: 00:1f.0 subsystem <- 8086/a087
1572 01:49:00.449071 PCI: 00:1f.0 cmd <- 407
1573 01:49:00.452644 PCI: 00:1f.3 subsystem <- 8086/a0c8
1574 01:49:00.455722 PCI: 00:1f.3 cmd <- 02
1575 01:49:00.459199 PCI: 00:1f.5 subsystem <- 8086/a0a4
1576 01:49:00.462847 PCI: 00:1f.5 cmd <- 406
1577 01:49:00.466365 PCI: 01:00.0 cmd <- 02
1578 01:49:00.471283 done.
1579 01:49:00.474267 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1580 01:49:00.477848 Initializing devices...
1581 01:49:00.480974 Root Device init
1582 01:49:00.483909 Chrome EC: Set SMI mask to 0x0000000000000000
1583 01:49:00.490696 Chrome EC: clear events_b mask to 0x0000000000000000
1584 01:49:00.497507 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1585 01:49:00.500622 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1586 01:49:00.507500 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1587 01:49:00.513853 Chrome EC: Set WAKE mask to 0x0000000000000000
1588 01:49:00.517205 fw_config match found: DB_USB=USB3_ACTIVE
1589 01:49:00.523899 Configure Right Type-C port orientation for retimer
1590 01:49:00.527346 Root Device init finished in 42 msecs
1591 01:49:00.530779 PCI: 00:00.0 init
1592 01:49:00.530862 CPU TDP = 9 Watts
1593 01:49:00.534039 CPU PL1 = 9 Watts
1594 01:49:00.537147 CPU PL2 = 40 Watts
1595 01:49:00.537244 CPU PL4 = 83 Watts
1596 01:49:00.540353 PCI: 00:00.0 init finished in 8 msecs
1597 01:49:00.544008 PCI: 00:02.0 init
1598 01:49:00.547128 GMA: Found VBT in CBFS
1599 01:49:00.550194 GMA: Found valid VBT in CBFS
1600 01:49:00.553926 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1601 01:49:00.563753 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1602 01:49:00.567292 PCI: 00:02.0 init finished in 18 msecs
1603 01:49:00.570430 PCI: 00:05.0 init
1604 01:49:00.573478 PCI: 00:05.0 init finished in 0 msecs
1605 01:49:00.573568 PCI: 00:08.0 init
1606 01:49:00.580015 PCI: 00:08.0 init finished in 0 msecs
1607 01:49:00.580100 PCI: 00:14.0 init
1608 01:49:00.586766 PCI: 00:14.0 init finished in 0 msecs
1609 01:49:00.586850 PCI: 00:14.2 init
1610 01:49:00.590449 PCI: 00:14.2 init finished in 0 msecs
1611 01:49:00.593849 PCI: 00:15.0 init
1612 01:49:00.597085 I2C bus 0 version 0x3230302a
1613 01:49:00.600763 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1614 01:49:00.603758 PCI: 00:15.0 init finished in 6 msecs
1615 01:49:00.606998 PCI: 00:15.1 init
1616 01:49:00.610646 I2C bus 1 version 0x3230302a
1617 01:49:00.613605 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1618 01:49:00.617164 PCI: 00:15.1 init finished in 6 msecs
1619 01:49:00.620737 PCI: 00:15.2 init
1620 01:49:00.623954 I2C bus 2 version 0x3230302a
1621 01:49:00.627163 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1622 01:49:00.630327 PCI: 00:15.2 init finished in 6 msecs
1623 01:49:00.630410 PCI: 00:15.3 init
1624 01:49:00.633843 I2C bus 3 version 0x3230302a
1625 01:49:00.636965 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1626 01:49:00.643626 PCI: 00:15.3 init finished in 6 msecs
1627 01:49:00.643710 PCI: 00:16.0 init
1628 01:49:00.647143 PCI: 00:16.0 init finished in 0 msecs
1629 01:49:00.650946 PCI: 00:19.1 init
1630 01:49:00.653996 I2C bus 5 version 0x3230302a
1631 01:49:00.657100 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1632 01:49:00.660613 PCI: 00:19.1 init finished in 6 msecs
1633 01:49:00.663861 PCI: 00:1d.0 init
1634 01:49:00.667522 Initializing PCH PCIe bridge.
1635 01:49:00.670481 PCI: 00:1d.0 init finished in 3 msecs
1636 01:49:00.673994 PCI: 00:1f.0 init
1637 01:49:00.677696 IOAPIC: Initializing IOAPIC at 0xfec00000
1638 01:49:00.680661 IOAPIC: Bootstrap Processor Local APIC = 0x00
1639 01:49:00.684117 IOAPIC: ID = 0x02
1640 01:49:00.687100 IOAPIC: Dumping registers
1641 01:49:00.690621 reg 0x0000: 0x02000000
1642 01:49:00.690704 reg 0x0001: 0x00770020
1643 01:49:00.693814 reg 0x0002: 0x00000000
1644 01:49:00.697466 PCI: 00:1f.0 init finished in 21 msecs
1645 01:49:00.700849 PCI: 00:1f.2 init
1646 01:49:00.704150 Disabling ACPI via APMC.
1647 01:49:00.707113 APMC done.
1648 01:49:00.710897 PCI: 00:1f.2 init finished in 5 msecs
1649 01:49:00.722497 PCI: 01:00.0 init
1650 01:49:00.725393 PCI: 01:00.0 init finished in 0 msecs
1651 01:49:00.729028 PNP: 0c09.0 init
1652 01:49:00.732262 Google Chrome EC uptime: 8.439 seconds
1653 01:49:00.739130 Google Chrome AP resets since EC boot: 1
1654 01:49:00.742275 Google Chrome most recent AP reset causes:
1655 01:49:00.745871 0.379: 32775 shutdown: entering G3
1656 01:49:00.752249 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1657 01:49:00.755608 PNP: 0c09.0 init finished in 22 msecs
1658 01:49:00.760932 Devices initialized
1659 01:49:00.764455 Show all devs... After init.
1660 01:49:00.767623 Root Device: enabled 1
1661 01:49:00.767707 DOMAIN: 0000: enabled 1
1662 01:49:00.771257 CPU_CLUSTER: 0: enabled 1
1663 01:49:00.774275 PCI: 00:00.0: enabled 1
1664 01:49:00.777946 PCI: 00:02.0: enabled 1
1665 01:49:00.778028 PCI: 00:04.0: enabled 1
1666 01:49:00.781057 PCI: 00:05.0: enabled 1
1667 01:49:00.784233 PCI: 00:06.0: enabled 0
1668 01:49:00.787806 PCI: 00:07.0: enabled 0
1669 01:49:00.787889 PCI: 00:07.1: enabled 0
1670 01:49:00.791133 PCI: 00:07.2: enabled 0
1671 01:49:00.794483 PCI: 00:07.3: enabled 0
1672 01:49:00.797540 PCI: 00:08.0: enabled 1
1673 01:49:00.797623 PCI: 00:09.0: enabled 0
1674 01:49:00.800951 PCI: 00:0a.0: enabled 0
1675 01:49:00.804226 PCI: 00:0d.0: enabled 1
1676 01:49:00.807874 PCI: 00:0d.1: enabled 0
1677 01:49:00.807957 PCI: 00:0d.2: enabled 0
1678 01:49:00.811282 PCI: 00:0d.3: enabled 0
1679 01:49:00.814085 PCI: 00:0e.0: enabled 0
1680 01:49:00.814168 PCI: 00:10.2: enabled 1
1681 01:49:00.817239 PCI: 00:10.6: enabled 0
1682 01:49:00.821204 PCI: 00:10.7: enabled 0
1683 01:49:00.824078 PCI: 00:12.0: enabled 0
1684 01:49:00.824188 PCI: 00:12.6: enabled 0
1685 01:49:00.827787 PCI: 00:13.0: enabled 0
1686 01:49:00.830901 PCI: 00:14.0: enabled 1
1687 01:49:00.833957 PCI: 00:14.1: enabled 0
1688 01:49:00.834040 PCI: 00:14.2: enabled 1
1689 01:49:00.837385 PCI: 00:14.3: enabled 1
1690 01:49:00.840691 PCI: 00:15.0: enabled 1
1691 01:49:00.844283 PCI: 00:15.1: enabled 1
1692 01:49:00.844366 PCI: 00:15.2: enabled 1
1693 01:49:00.847322 PCI: 00:15.3: enabled 1
1694 01:49:00.850990 PCI: 00:16.0: enabled 1
1695 01:49:00.851072 PCI: 00:16.1: enabled 0
1696 01:49:00.854127 PCI: 00:16.2: enabled 0
1697 01:49:00.857054 PCI: 00:16.3: enabled 0
1698 01:49:00.860646 PCI: 00:16.4: enabled 0
1699 01:49:00.860738 PCI: 00:16.5: enabled 0
1700 01:49:00.864042 PCI: 00:17.0: enabled 0
1701 01:49:00.867326 PCI: 00:19.0: enabled 0
1702 01:49:00.870768 PCI: 00:19.1: enabled 1
1703 01:49:00.870851 PCI: 00:19.2: enabled 0
1704 01:49:00.874009 PCI: 00:1c.0: enabled 1
1705 01:49:00.877504 PCI: 00:1c.1: enabled 0
1706 01:49:00.880626 PCI: 00:1c.2: enabled 0
1707 01:49:00.880710 PCI: 00:1c.3: enabled 0
1708 01:49:00.884387 PCI: 00:1c.4: enabled 0
1709 01:49:00.887360 PCI: 00:1c.5: enabled 0
1710 01:49:00.887488 PCI: 00:1c.6: enabled 1
1711 01:49:00.891092 PCI: 00:1c.7: enabled 0
1712 01:49:00.894261 PCI: 00:1d.0: enabled 1
1713 01:49:00.897262 PCI: 00:1d.1: enabled 0
1714 01:49:00.897345 PCI: 00:1d.2: enabled 1
1715 01:49:00.901085 PCI: 00:1d.3: enabled 0
1716 01:49:00.903965 PCI: 00:1e.0: enabled 1
1717 01:49:00.907368 PCI: 00:1e.1: enabled 0
1718 01:49:00.907490 PCI: 00:1e.2: enabled 1
1719 01:49:00.910563 PCI: 00:1e.3: enabled 1
1720 01:49:00.913619 PCI: 00:1f.0: enabled 1
1721 01:49:00.917065 PCI: 00:1f.1: enabled 0
1722 01:49:00.917147 PCI: 00:1f.2: enabled 1
1723 01:49:00.920453 PCI: 00:1f.3: enabled 1
1724 01:49:00.923925 PCI: 00:1f.4: enabled 0
1725 01:49:00.926896 PCI: 00:1f.5: enabled 1
1726 01:49:00.926979 PCI: 00:1f.6: enabled 0
1727 01:49:00.930237 PCI: 00:1f.7: enabled 0
1728 01:49:00.934012 APIC: 00: enabled 1
1729 01:49:00.934096 GENERIC: 0.0: enabled 1
1730 01:49:00.937030 GENERIC: 0.0: enabled 1
1731 01:49:00.940223 GENERIC: 1.0: enabled 1
1732 01:49:00.943738 GENERIC: 0.0: enabled 1
1733 01:49:00.943821 GENERIC: 1.0: enabled 1
1734 01:49:00.946651 USB0 port 0: enabled 1
1735 01:49:00.950370 GENERIC: 0.0: enabled 1
1736 01:49:00.950453 USB0 port 0: enabled 1
1737 01:49:00.953458 GENERIC: 0.0: enabled 1
1738 01:49:00.957112 I2C: 00:1a: enabled 1
1739 01:49:00.960284 I2C: 00:31: enabled 1
1740 01:49:00.960367 I2C: 00:32: enabled 1
1741 01:49:00.963287 I2C: 00:10: enabled 1
1742 01:49:00.966995 I2C: 00:15: enabled 1
1743 01:49:00.967078 GENERIC: 0.0: enabled 0
1744 01:49:00.970061 GENERIC: 1.0: enabled 0
1745 01:49:00.973211 GENERIC: 0.0: enabled 1
1746 01:49:00.973293 SPI: 00: enabled 1
1747 01:49:00.976483 SPI: 00: enabled 1
1748 01:49:00.980109 PNP: 0c09.0: enabled 1
1749 01:49:00.980192 GENERIC: 0.0: enabled 1
1750 01:49:00.983311 USB3 port 0: enabled 1
1751 01:49:00.986879 USB3 port 1: enabled 1
1752 01:49:00.990204 USB3 port 2: enabled 0
1753 01:49:00.990359 USB3 port 3: enabled 0
1754 01:49:00.993655 USB2 port 0: enabled 0
1755 01:49:00.996742 USB2 port 1: enabled 1
1756 01:49:00.996842 USB2 port 2: enabled 1
1757 01:49:00.999747 USB2 port 3: enabled 0
1758 01:49:01.002945 USB2 port 4: enabled 1
1759 01:49:01.006538 USB2 port 5: enabled 0
1760 01:49:01.006650 USB2 port 6: enabled 0
1761 01:49:01.009852 USB2 port 7: enabled 0
1762 01:49:01.012950 USB2 port 8: enabled 0
1763 01:49:01.013032 USB2 port 9: enabled 0
1764 01:49:01.016670 USB3 port 0: enabled 0
1765 01:49:01.020095 USB3 port 1: enabled 1
1766 01:49:01.020178 USB3 port 2: enabled 0
1767 01:49:01.023102 USB3 port 3: enabled 0
1768 01:49:01.026603 GENERIC: 0.0: enabled 1
1769 01:49:01.029823 GENERIC: 1.0: enabled 1
1770 01:49:01.029906 APIC: 01: enabled 1
1771 01:49:01.033122 APIC: 03: enabled 1
1772 01:49:01.033205 APIC: 07: enabled 1
1773 01:49:01.036182 APIC: 05: enabled 1
1774 01:49:01.039617 APIC: 04: enabled 1
1775 01:49:01.039700 APIC: 02: enabled 1
1776 01:49:01.043088 APIC: 06: enabled 1
1777 01:49:01.046511 PCI: 01:00.0: enabled 1
1778 01:49:01.049554 BS: BS_DEV_INIT run times (exec / console): 30 / 540 ms
1779 01:49:01.056533 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1780 01:49:01.059290 ELOG: NV offset 0xf30000 size 0x1000
1781 01:49:01.066211 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1782 01:49:01.072961 ELOG: Event(17) added with size 13 at 2023-10-11 01:49:00 UTC
1783 01:49:01.079746 ELOG: Event(92) added with size 9 at 2023-10-11 01:49:00 UTC
1784 01:49:01.086503 ELOG: Event(93) added with size 9 at 2023-10-11 01:49:00 UTC
1785 01:49:01.093102 ELOG: Event(9E) added with size 10 at 2023-10-11 01:49:00 UTC
1786 01:49:01.099631 ELOG: Event(9F) added with size 14 at 2023-10-11 01:49:00 UTC
1787 01:49:01.102830 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1788 01:49:01.109642 ELOG: Event(A1) added with size 10 at 2023-10-11 01:49:00 UTC
1789 01:49:01.116396 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1790 01:49:01.122980 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1791 01:49:01.126576 Finalize devices...
1792 01:49:01.126661 Devices finalized
1793 01:49:01.132705 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1794 01:49:01.136532 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1795 01:49:01.143057 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1796 01:49:01.149750 ME: HFSTS1 : 0x80030055
1797 01:49:01.153072 ME: HFSTS2 : 0x30280116
1798 01:49:01.156445 ME: HFSTS3 : 0x00000050
1799 01:49:01.162799 ME: HFSTS4 : 0x00004000
1800 01:49:01.166085 ME: HFSTS5 : 0x00000000
1801 01:49:01.169570 ME: HFSTS6 : 0x00400006
1802 01:49:01.172800 ME: Manufacturing Mode : YES
1803 01:49:01.179868 ME: SPI Protection Mode Enabled : NO
1804 01:49:01.182838 ME: FW Partition Table : OK
1805 01:49:01.185961 ME: Bringup Loader Failure : NO
1806 01:49:01.189618 ME: Firmware Init Complete : NO
1807 01:49:01.192784 ME: Boot Options Present : NO
1808 01:49:01.195950 ME: Update In Progress : NO
1809 01:49:01.198996 ME: D0i3 Support : YES
1810 01:49:01.203008 ME: Low Power State Enabled : NO
1811 01:49:01.209336 ME: CPU Replaced : YES
1812 01:49:01.212694 ME: CPU Replacement Valid : YES
1813 01:49:01.216012 ME: Current Working State : 5
1814 01:49:01.219254 ME: Current Operation State : 1
1815 01:49:01.222784 ME: Current Operation Mode : 3
1816 01:49:01.225761 ME: Error Code : 0
1817 01:49:01.229540 ME: Enhanced Debug Mode : NO
1818 01:49:01.232471 ME: CPU Debug Disabled : YES
1819 01:49:01.235616 ME: TXT Support : NO
1820 01:49:01.242530 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1821 01:49:01.252841 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1822 01:49:01.255993 CBFS: 'fallback/slic' not found.
1823 01:49:01.259081 ACPI: Writing ACPI tables at 76b01000.
1824 01:49:01.259190 ACPI: * FACS
1825 01:49:01.262779 ACPI: * DSDT
1826 01:49:01.265930 Ramoops buffer: 0x100000@0x76a00000.
1827 01:49:01.268922 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1828 01:49:01.275705 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1829 01:49:01.278987 Google Chrome EC: version:
1830 01:49:01.282509 ro: voema_v2.0.7540-147f8d37d1
1831 01:49:01.285445 rw: voema_v2.0.7540-147f8d37d1
1832 01:49:01.288953 running image: 2
1833 01:49:01.292078 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1834 01:49:01.298071 ACPI: * FADT
1835 01:49:01.298184 SCI is IRQ9
1836 01:49:01.304242 ACPI: added table 1/32, length now 40
1837 01:49:01.304326 ACPI: * SSDT
1838 01:49:01.307801 Found 1 CPU(s) with 8 core(s) each.
1839 01:49:01.314557 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1840 01:49:01.317652 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1841 01:49:01.321118 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1842 01:49:01.324388 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1843 01:49:01.331070 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1844 01:49:01.337524 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1845 01:49:01.341046 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1846 01:49:01.347148 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1847 01:49:01.353871 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1848 01:49:01.357500 \_SB.PCI0.RP09: Added StorageD3Enable property
1849 01:49:01.363645 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1850 01:49:01.367296 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1851 01:49:01.373534 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1852 01:49:01.377321 PS2K: Passing 80 keymaps to kernel
1853 01:49:01.383521 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1854 01:49:01.390477 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1855 01:49:01.397245 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1856 01:49:01.403415 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1857 01:49:01.409911 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1858 01:49:01.416969 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1859 01:49:01.423544 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1860 01:49:01.430381 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1861 01:49:01.433508 ACPI: added table 2/32, length now 44
1862 01:49:01.433593 ACPI: * MCFG
1863 01:49:01.439829 ACPI: added table 3/32, length now 48
1864 01:49:01.439913 ACPI: * TPM2
1865 01:49:01.443650 TPM2 log created at 0x769f0000
1866 01:49:01.446794 ACPI: added table 4/32, length now 52
1867 01:49:01.450100 ACPI: * MADT
1868 01:49:01.450183 SCI is IRQ9
1869 01:49:01.453403 ACPI: added table 5/32, length now 56
1870 01:49:01.456823 current = 76b09850
1871 01:49:01.456908 ACPI: * DMAR
1872 01:49:01.459828 ACPI: added table 6/32, length now 60
1873 01:49:01.466386 ACPI: added table 7/32, length now 64
1874 01:49:01.466470 ACPI: * HPET
1875 01:49:01.470109 ACPI: added table 8/32, length now 68
1876 01:49:01.473343 ACPI: done.
1877 01:49:01.473425 ACPI tables: 35216 bytes.
1878 01:49:01.476251 smbios_write_tables: 769ef000
1879 01:49:01.479939 EC returned error result code 3
1880 01:49:01.483292 Couldn't obtain OEM name from CBI
1881 01:49:01.486965 Create SMBIOS type 16
1882 01:49:01.490041 Create SMBIOS type 17
1883 01:49:01.493593 GENERIC: 0.0 (WIFI Device)
1884 01:49:01.493675 SMBIOS tables: 1750 bytes.
1885 01:49:01.500443 Writing table forward entry at 0x00000500
1886 01:49:01.507102 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1887 01:49:01.509961 Writing coreboot table at 0x76b25000
1888 01:49:01.517111 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1889 01:49:01.519972 1. 0000000000001000-000000000009ffff: RAM
1890 01:49:01.523364 2. 00000000000a0000-00000000000fffff: RESERVED
1891 01:49:01.529656 3. 0000000000100000-00000000769eefff: RAM
1892 01:49:01.533215 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1893 01:49:01.539637 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1894 01:49:01.546743 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1895 01:49:01.549753 7. 0000000077000000-000000007fbfffff: RESERVED
1896 01:49:01.553395 8. 00000000c0000000-00000000cfffffff: RESERVED
1897 01:49:01.559631 9. 00000000f8000000-00000000f9ffffff: RESERVED
1898 01:49:01.562963 10. 00000000fb000000-00000000fb000fff: RESERVED
1899 01:49:01.569572 11. 00000000fe000000-00000000fe00ffff: RESERVED
1900 01:49:01.573170 12. 00000000fed80000-00000000fed87fff: RESERVED
1901 01:49:01.579893 13. 00000000fed90000-00000000fed92fff: RESERVED
1902 01:49:01.583046 14. 00000000feda0000-00000000feda1fff: RESERVED
1903 01:49:01.589942 15. 00000000fedc0000-00000000feddffff: RESERVED
1904 01:49:01.592963 16. 0000000100000000-00000002803fffff: RAM
1905 01:49:01.596729 Passing 4 GPIOs to payload:
1906 01:49:01.599776 NAME | PORT | POLARITY | VALUE
1907 01:49:01.606490 lid | undefined | high | high
1908 01:49:01.609521 power | undefined | high | low
1909 01:49:01.616636 oprom | undefined | high | low
1910 01:49:01.623158 EC in RW | 0x000000e5 | high | high
1911 01:49:01.629474 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum dfd3
1912 01:49:01.629579 coreboot table: 1576 bytes.
1913 01:49:01.636287 IMD ROOT 0. 0x76fff000 0x00001000
1914 01:49:01.639842 IMD SMALL 1. 0x76ffe000 0x00001000
1915 01:49:01.642788 FSP MEMORY 2. 0x76c4e000 0x003b0000
1916 01:49:01.646092 VPD 3. 0x76c4d000 0x00000367
1917 01:49:01.649938 RO MCACHE 4. 0x76c4c000 0x00000fdc
1918 01:49:01.652800 CONSOLE 5. 0x76c2c000 0x00020000
1919 01:49:01.656103 FMAP 6. 0x76c2b000 0x00000578
1920 01:49:01.659597 TIME STAMP 7. 0x76c2a000 0x00000910
1921 01:49:01.662839 VBOOT WORK 8. 0x76c16000 0x00014000
1922 01:49:01.669404 ROMSTG STCK 9. 0x76c15000 0x00001000
1923 01:49:01.672820 AFTER CAR 10. 0x76c0a000 0x0000b000
1924 01:49:01.676498 RAMSTAGE 11. 0x76b97000 0x00073000
1925 01:49:01.679942 REFCODE 12. 0x76b42000 0x00055000
1926 01:49:01.682741 SMM BACKUP 13. 0x76b32000 0x00010000
1927 01:49:01.686551 4f444749 14. 0x76b30000 0x00002000
1928 01:49:01.689609 EXT VBT15. 0x76b2d000 0x0000219f
1929 01:49:01.692815 COREBOOT 16. 0x76b25000 0x00008000
1930 01:49:01.696209 ACPI 17. 0x76b01000 0x00024000
1931 01:49:01.702966 ACPI GNVS 18. 0x76b00000 0x00001000
1932 01:49:01.706214 RAMOOPS 19. 0x76a00000 0x00100000
1933 01:49:01.709354 TPM2 TCGLOG20. 0x769f0000 0x00010000
1934 01:49:01.713136 SMBIOS 21. 0x769ef000 0x00000800
1935 01:49:01.713209 IMD small region:
1936 01:49:01.719372 IMD ROOT 0. 0x76ffec00 0x00000400
1937 01:49:01.722757 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1938 01:49:01.726413 POWER STATE 2. 0x76ffeb80 0x00000044
1939 01:49:01.729457 ROMSTAGE 3. 0x76ffeb60 0x00000004
1940 01:49:01.732746 MEM INFO 4. 0x76ffe980 0x000001e0
1941 01:49:01.739542 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1942 01:49:01.742699 MTRR: Physical address space:
1943 01:49:01.749620 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1944 01:49:01.756441 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1945 01:49:01.762872 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1946 01:49:01.769621 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1947 01:49:01.772532 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1948 01:49:01.779151 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1949 01:49:01.786112 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1950 01:49:01.789543 MTRR: Fixed MSR 0x250 0x0606060606060606
1951 01:49:01.796125 MTRR: Fixed MSR 0x258 0x0606060606060606
1952 01:49:01.799150 MTRR: Fixed MSR 0x259 0x0000000000000000
1953 01:49:01.802688 MTRR: Fixed MSR 0x268 0x0606060606060606
1954 01:49:01.805792 MTRR: Fixed MSR 0x269 0x0606060606060606
1955 01:49:01.812755 MTRR: Fixed MSR 0x26a 0x0606060606060606
1956 01:49:01.815658 MTRR: Fixed MSR 0x26b 0x0606060606060606
1957 01:49:01.819511 MTRR: Fixed MSR 0x26c 0x0606060606060606
1958 01:49:01.822630 MTRR: Fixed MSR 0x26d 0x0606060606060606
1959 01:49:01.829007 MTRR: Fixed MSR 0x26e 0x0606060606060606
1960 01:49:01.832233 MTRR: Fixed MSR 0x26f 0x0606060606060606
1961 01:49:01.835952 call enable_fixed_mtrr()
1962 01:49:01.838926 CPU physical address size: 39 bits
1963 01:49:01.842578 MTRR: default type WB/UC MTRR counts: 6/6.
1964 01:49:01.845833 MTRR: UC selected as default type.
1965 01:49:01.852555 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1966 01:49:01.858683 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1967 01:49:01.865558 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1968 01:49:01.872270 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1969 01:49:01.878936 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1970 01:49:01.885746 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1971 01:49:01.889122 MTRR: Fixed MSR 0x250 0x0606060606060606
1972 01:49:01.895685 MTRR: Fixed MSR 0x258 0x0606060606060606
1973 01:49:01.898733 MTRR: Fixed MSR 0x259 0x0000000000000000
1974 01:49:01.902412 MTRR: Fixed MSR 0x268 0x0606060606060606
1975 01:49:01.905404 MTRR: Fixed MSR 0x269 0x0606060606060606
1976 01:49:01.908590 MTRR: Fixed MSR 0x26a 0x0606060606060606
1977 01:49:01.915305 MTRR: Fixed MSR 0x26b 0x0606060606060606
1978 01:49:01.918566 MTRR: Fixed MSR 0x26c 0x0606060606060606
1979 01:49:01.922304 MTRR: Fixed MSR 0x26d 0x0606060606060606
1980 01:49:01.925131 MTRR: Fixed MSR 0x26e 0x0606060606060606
1981 01:49:01.931694 MTRR: Fixed MSR 0x26f 0x0606060606060606
1982 01:49:01.931780
1983 01:49:01.931846 MTRR check
1984 01:49:01.935178 call enable_fixed_mtrr()
1985 01:49:01.938524 Fixed MTRRs : Enabled
1986 01:49:01.942282 Variable MTRRs: Enabled
1987 01:49:01.942366
1988 01:49:01.945305 CPU physical address size: 39 bits
1989 01:49:01.952309 BS: BS_WRITE_TABLES exit times (exec / console): 50 / 151 ms
1990 01:49:01.955310 MTRR: Fixed MSR 0x250 0x0606060606060606
1991 01:49:01.958451 MTRR: Fixed MSR 0x250 0x0606060606060606
1992 01:49:01.965073 MTRR: Fixed MSR 0x258 0x0606060606060606
1993 01:49:01.968842 MTRR: Fixed MSR 0x259 0x0000000000000000
1994 01:49:01.971749 MTRR: Fixed MSR 0x268 0x0606060606060606
1995 01:49:01.974853 MTRR: Fixed MSR 0x269 0x0606060606060606
1996 01:49:01.981857 MTRR: Fixed MSR 0x26a 0x0606060606060606
1997 01:49:01.984949 MTRR: Fixed MSR 0x26b 0x0606060606060606
1998 01:49:01.988506 MTRR: Fixed MSR 0x26c 0x0606060606060606
1999 01:49:01.991442 MTRR: Fixed MSR 0x26d 0x0606060606060606
2000 01:49:01.994999 MTRR: Fixed MSR 0x26e 0x0606060606060606
2001 01:49:02.001536 MTRR: Fixed MSR 0x26f 0x0606060606060606
2002 01:49:02.005130 MTRR: Fixed MSR 0x258 0x0606060606060606
2003 01:49:02.008270 call enable_fixed_mtrr()
2004 01:49:02.011807 MTRR: Fixed MSR 0x259 0x0000000000000000
2005 01:49:02.018197 MTRR: Fixed MSR 0x268 0x0606060606060606
2006 01:49:02.021191 MTRR: Fixed MSR 0x269 0x0606060606060606
2007 01:49:02.024780 MTRR: Fixed MSR 0x26a 0x0606060606060606
2008 01:49:02.028211 MTRR: Fixed MSR 0x26b 0x0606060606060606
2009 01:49:02.031769 MTRR: Fixed MSR 0x26c 0x0606060606060606
2010 01:49:02.037852 MTRR: Fixed MSR 0x26d 0x0606060606060606
2011 01:49:02.041467 MTRR: Fixed MSR 0x26e 0x0606060606060606
2012 01:49:02.044444 MTRR: Fixed MSR 0x26f 0x0606060606060606
2013 01:49:02.048094 CPU physical address size: 39 bits
2014 01:49:02.054966 call enable_fixed_mtrr()
2015 01:49:02.058103 MTRR: Fixed MSR 0x250 0x0606060606060606
2016 01:49:02.061862 MTRR: Fixed MSR 0x250 0x0606060606060606
2017 01:49:02.065055 MTRR: Fixed MSR 0x258 0x0606060606060606
2018 01:49:02.071126 MTRR: Fixed MSR 0x259 0x0000000000000000
2019 01:49:02.074954 MTRR: Fixed MSR 0x268 0x0606060606060606
2020 01:49:02.078251 MTRR: Fixed MSR 0x269 0x0606060606060606
2021 01:49:02.081445 MTRR: Fixed MSR 0x26a 0x0606060606060606
2022 01:49:02.084639 MTRR: Fixed MSR 0x26b 0x0606060606060606
2023 01:49:02.090962 MTRR: Fixed MSR 0x26c 0x0606060606060606
2024 01:49:02.094811 MTRR: Fixed MSR 0x26d 0x0606060606060606
2025 01:49:02.097927 MTRR: Fixed MSR 0x26e 0x0606060606060606
2026 01:49:02.100871 MTRR: Fixed MSR 0x26f 0x0606060606060606
2027 01:49:02.109006 MTRR: Fixed MSR 0x258 0x0606060606060606
2028 01:49:02.112379 MTRR: Fixed MSR 0x259 0x0000000000000000
2029 01:49:02.115610 MTRR: Fixed MSR 0x268 0x0606060606060606
2030 01:49:02.118653 MTRR: Fixed MSR 0x269 0x0606060606060606
2031 01:49:02.125853 MTRR: Fixed MSR 0x26a 0x0606060606060606
2032 01:49:02.128773 MTRR: Fixed MSR 0x26b 0x0606060606060606
2033 01:49:02.131844 MTRR: Fixed MSR 0x26c 0x0606060606060606
2034 01:49:02.135344 MTRR: Fixed MSR 0x26d 0x0606060606060606
2035 01:49:02.141990 MTRR: Fixed MSR 0x26e 0x0606060606060606
2036 01:49:02.145168 MTRR: Fixed MSR 0x26f 0x0606060606060606
2037 01:49:02.148273 call enable_fixed_mtrr()
2038 01:49:02.151918 call enable_fixed_mtrr()
2039 01:49:02.155024 MTRR: Fixed MSR 0x250 0x0606060606060606
2040 01:49:02.158211 MTRR: Fixed MSR 0x250 0x0606060606060606
2041 01:49:02.161730 MTRR: Fixed MSR 0x258 0x0606060606060606
2042 01:49:02.168659 MTRR: Fixed MSR 0x259 0x0000000000000000
2043 01:49:02.171810 MTRR: Fixed MSR 0x268 0x0606060606060606
2044 01:49:02.174903 MTRR: Fixed MSR 0x269 0x0606060606060606
2045 01:49:02.178006 MTRR: Fixed MSR 0x26a 0x0606060606060606
2046 01:49:02.184887 MTRR: Fixed MSR 0x26b 0x0606060606060606
2047 01:49:02.188587 MTRR: Fixed MSR 0x26c 0x0606060606060606
2048 01:49:02.191730 MTRR: Fixed MSR 0x26d 0x0606060606060606
2049 01:49:02.194792 MTRR: Fixed MSR 0x26e 0x0606060606060606
2050 01:49:02.201324 MTRR: Fixed MSR 0x26f 0x0606060606060606
2051 01:49:02.204519 MTRR: Fixed MSR 0x258 0x0606060606060606
2052 01:49:02.208095 MTRR: Fixed MSR 0x259 0x0000000000000000
2053 01:49:02.214558 MTRR: Fixed MSR 0x268 0x0606060606060606
2054 01:49:02.218080 MTRR: Fixed MSR 0x269 0x0606060606060606
2055 01:49:02.221349 MTRR: Fixed MSR 0x26a 0x0606060606060606
2056 01:49:02.224514 MTRR: Fixed MSR 0x26b 0x0606060606060606
2057 01:49:02.231335 MTRR: Fixed MSR 0x26c 0x0606060606060606
2058 01:49:02.234417 MTRR: Fixed MSR 0x26d 0x0606060606060606
2059 01:49:02.238000 MTRR: Fixed MSR 0x26e 0x0606060606060606
2060 01:49:02.240883 MTRR: Fixed MSR 0x26f 0x0606060606060606
2061 01:49:02.244875 call enable_fixed_mtrr()
2062 01:49:02.247834 call enable_fixed_mtrr()
2063 01:49:02.251671 CPU physical address size: 39 bits
2064 01:49:02.254697 CPU physical address size: 39 bits
2065 01:49:02.258304 CPU physical address size: 39 bits
2066 01:49:02.264592 CPU physical address size: 39 bits
2067 01:49:02.268028 CPU physical address size: 39 bits
2068 01:49:02.271259 Checking cr50 for pending updates
2069 01:49:02.278070 Reading cr50 TPM mode
2070 01:49:02.288029 BS: BS_PAYLOAD_LOAD entry times (exec / console): 325 / 6 ms
2071 01:49:02.298353 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2072 01:49:02.301460 Checking segment from ROM address 0xffc02b38
2073 01:49:02.304589 Checking segment from ROM address 0xffc02b54
2074 01:49:02.311613 Loading segment from ROM address 0xffc02b38
2075 01:49:02.311699 code (compression=0)
2076 01:49:02.321510 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2077 01:49:02.331250 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2078 01:49:02.331373 it's not compressed!
2079 01:49:02.470723 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2080 01:49:02.477698 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2081 01:49:02.484442 Loading segment from ROM address 0xffc02b54
2082 01:49:02.484547 Entry Point 0x30000000
2083 01:49:02.487674 Loaded segments
2084 01:49:02.494055 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2085 01:49:02.536896 Finalizing chipset.
2086 01:49:02.540620 Finalizing SMM.
2087 01:49:02.540713 APMC done.
2088 01:49:02.547099 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2089 01:49:02.550336 mp_park_aps done after 0 msecs.
2090 01:49:02.553491 Jumping to boot code at 0x30000000(0x76b25000)
2091 01:49:02.564081 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2092 01:49:02.564191
2093 01:49:02.564289
2094 01:49:02.564378
2095 01:49:02.567198 Starting depthcharge on Voema...
2096 01:49:02.567299
2097 01:49:02.567740 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2098 01:49:02.567872 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2099 01:49:02.567982 Setting prompt string to ['volteer:']
2100 01:49:02.568088 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2101 01:49:02.576960 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2102 01:49:02.577074
2103 01:49:02.583470 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2104 01:49:02.583575
2105 01:49:02.587120 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2106 01:49:02.590377
2107 01:49:02.593670 Failed to find eMMC card reader
2108 01:49:02.593774
2109 01:49:02.593867 Wipe memory regions:
2110 01:49:02.593959
2111 01:49:02.599886 [0x00000000001000, 0x000000000a0000)
2112 01:49:02.599989
2113 01:49:02.603277 [0x00000000100000, 0x00000030000000)
2114 01:49:02.628456
2115 01:49:02.632119 [0x00000032662db0, 0x000000769ef000)
2116 01:49:02.668072
2117 01:49:02.670782 [0x00000100000000, 0x00000280400000)
2118 01:49:02.871752
2119 01:49:02.874980 ec_init: CrosEC protocol v3 supported (256, 256)
2120 01:49:02.875096
2121 01:49:02.881870 update_port_state: port C0 state: usb enable 1 mux conn 0
2122 01:49:02.881979
2123 01:49:02.888306 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2124 01:49:02.893066
2125 01:49:02.896144 pmc_check_ipc_sts: STS_BUSY done after 1562 us
2126 01:49:02.896253
2127 01:49:02.899778 send_conn_disc_msg: pmc_send_cmd succeeded
2128 01:49:03.333200
2129 01:49:03.333340 R8152: Initializing
2130 01:49:03.333439
2131 01:49:03.336523 Version 6 (ocp_data = 5c30)
2132 01:49:03.336598
2133 01:49:03.339800 R8152: Done initializing
2134 01:49:03.339902
2135 01:49:03.343192 Adding net device
2136 01:49:03.644713
2137 01:49:03.648248 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2138 01:49:03.648334
2139 01:49:03.648400
2140 01:49:03.648465
2141 01:49:03.651727 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2143 01:49:03.752130 volteer: tftpboot 192.168.201.1 11733068/tftp-deploy-ncixsgin/kernel/bzImage 11733068/tftp-deploy-ncixsgin/kernel/cmdline 11733068/tftp-deploy-ncixsgin/ramdisk/ramdisk.cpio.gz
2144 01:49:03.752282 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2145 01:49:03.752390 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2146 01:49:03.756194 tftpboot 192.168.201.1 11733068/tftp-deploy-ncixsgin/kernel/bzIploy-ncixsgin/kernel/cmdline 11733068/tftp-deploy-ncixsgin/ramdisk/ramdisk.cpio.gz
2147 01:49:03.756286
2148 01:49:03.756353 Waiting for link
2149 01:49:03.961097
2150 01:49:03.961232 done.
2151 01:49:03.961300
2152 01:49:03.961363 MAC: 00:24:32:30:7c:e4
2153 01:49:03.961426
2154 01:49:03.964231 Sending DHCP discover... done.
2155 01:49:03.964318
2156 01:49:03.967889 Waiting for reply... done.
2157 01:49:03.968001
2158 01:49:03.971150 Sending DHCP request... done.
2159 01:49:03.971252
2160 01:49:03.974105 Waiting for reply... done.
2161 01:49:03.974190
2162 01:49:03.977806 My ip is 192.168.201.23
2163 01:49:03.977917
2164 01:49:03.980862 The DHCP server ip is 192.168.201.1
2165 01:49:03.980939
2166 01:49:03.987473 TFTP server IP predefined by user: 192.168.201.1
2167 01:49:03.987561
2168 01:49:03.994255 Bootfile predefined by user: 11733068/tftp-deploy-ncixsgin/kernel/bzImage
2169 01:49:03.994342
2170 01:49:03.997490 Sending tftp read request... done.
2171 01:49:03.997576
2172 01:49:04.000579 Waiting for the transfer...
2173 01:49:04.000668
2174 01:49:04.525016 00000000 ################################################################
2175 01:49:04.525182
2176 01:49:05.036463 00080000 ################################################################
2177 01:49:05.036602
2178 01:49:05.556432 00100000 ################################################################
2179 01:49:05.556574
2180 01:49:06.081155 00180000 ################################################################
2181 01:49:06.081313
2182 01:49:06.612460 00200000 ################################################################
2183 01:49:06.612636
2184 01:49:07.134533 00280000 ################################################################
2185 01:49:07.134673
2186 01:49:07.654353 00300000 ################################################################
2187 01:49:07.654518
2188 01:49:08.175777 00380000 ################################################################
2189 01:49:08.175910
2190 01:49:08.692547 00400000 ################################################################
2191 01:49:08.692684
2192 01:49:09.207468 00480000 ################################################################
2193 01:49:09.207607
2194 01:49:09.744205 00500000 ################################################################
2195 01:49:09.744370
2196 01:49:10.298505 00580000 ################################################################
2197 01:49:10.298638
2198 01:49:10.829891 00600000 ################################################################
2199 01:49:10.830069
2200 01:49:11.347312 00680000 ################################################################
2201 01:49:11.347460
2202 01:49:11.858756 00700000 ################################################################
2203 01:49:11.858891
2204 01:49:12.380384 00780000 ################################################################
2205 01:49:12.380546
2206 01:49:12.895743 00800000 ################################################################
2207 01:49:12.895882
2208 01:49:13.414994 00880000 ################################################################
2209 01:49:13.415164
2210 01:49:13.922531 00900000 ################################################################
2211 01:49:13.922666
2212 01:49:14.439391 00980000 ################################################################
2213 01:49:14.439544
2214 01:49:14.958483 00a00000 ################################################################
2215 01:49:14.958632
2216 01:49:15.414158 00a80000 ######################################################### done.
2217 01:49:15.414344
2218 01:49:15.417884 The bootfile was 11473408 bytes long.
2219 01:49:15.418031
2220 01:49:15.421003 Sending tftp read request... done.
2221 01:49:15.421088
2222 01:49:15.424125 Waiting for the transfer...
2223 01:49:15.424213
2224 01:49:15.940513 00000000 ################################################################
2225 01:49:15.940653
2226 01:49:16.464221 00080000 ################################################################
2227 01:49:16.464366
2228 01:49:16.980924 00100000 ################################################################
2229 01:49:16.981097
2230 01:49:17.495502 00180000 ################################################################
2231 01:49:17.495646
2232 01:49:18.013604 00200000 ################################################################
2233 01:49:18.013743
2234 01:49:18.523923 00280000 ################################################################
2235 01:49:18.524071
2236 01:49:19.036615 00300000 ################################################################
2237 01:49:19.036777
2238 01:49:19.549455 00380000 ################################################################
2239 01:49:19.549626
2240 01:49:20.061340 00400000 ################################################################
2241 01:49:20.061513
2242 01:49:20.576904 00480000 ################################################################
2243 01:49:20.577082
2244 01:49:21.107370 00500000 ################################################################
2245 01:49:21.107525
2246 01:49:21.652285 00580000 ################################################################
2247 01:49:21.652458
2248 01:49:22.194844 00600000 ################################################################
2249 01:49:22.195008
2250 01:49:22.718664 00680000 ################################################################
2251 01:49:22.718819
2252 01:49:23.248545 00700000 ################################################################
2253 01:49:23.248731
2254 01:49:23.763680 00780000 ################################################################
2255 01:49:23.763837
2256 01:49:24.277752 00800000 ################################################################
2257 01:49:24.277950
2258 01:49:24.576233 00880000 ###################################### done.
2259 01:49:24.579352
2260 01:49:24.582573 Sending tftp read request... done.
2261 01:49:24.582656
2262 01:49:24.582768 Waiting for the transfer...
2263 01:49:24.582869
2264 01:49:24.586315 00000000 # done.
2265 01:49:24.586434
2266 01:49:24.596222 Command line loaded dynamically from TFTP file: 11733068/tftp-deploy-ncixsgin/kernel/cmdline
2267 01:49:24.596336
2268 01:49:24.609225 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2269 01:49:24.616077
2270 01:49:24.619375 Shutting down all USB controllers.
2271 01:49:24.619482
2272 01:49:24.619549 Removing current net device
2273 01:49:24.619611
2274 01:49:24.622984 Finalizing coreboot
2275 01:49:24.623069
2276 01:49:24.629386 Exiting depthcharge with code 4 at timestamp: 30711514
2277 01:49:24.629470
2278 01:49:24.629536
2279 01:49:24.629598 Starting kernel ...
2280 01:49:24.629657
2281 01:49:24.629715
2282 01:49:24.630094 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
2283 01:49:24.630194 start: 2.2.5 auto-login-action (timeout 00:04:22) [common]
2284 01:49:24.630269 Setting prompt string to ['Linux version [0-9]']
2285 01:49:24.630337 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2286 01:49:24.630405 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2288 01:53:46.630434 end: 2.2.5 auto-login-action (duration 00:04:22) [common]
2290 01:53:46.630637 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 262 seconds'
2292 01:53:46.630798 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2295 01:53:46.631053 end: 2 depthcharge-action (duration 00:05:00) [common]
2297 01:53:46.631271 Cleaning after the job
2298 01:53:46.631362 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/ramdisk
2299 01:53:46.632716 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/kernel
2300 01:53:46.634554 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11733068/tftp-deploy-ncixsgin/modules
2301 01:53:46.635194 start: 5.1 power-off (timeout 00:00:30) [common]
2302 01:53:46.635483 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=off'
2303 01:53:46.711783 >> Command sent successfully.
2304 01:53:46.714412 Returned 0 in 0 seconds
2305 01:53:46.814781 end: 5.1 power-off (duration 00:00:00) [common]
2307 01:53:46.815221 start: 5.2 read-feedback (timeout 00:10:00) [common]
2308 01:53:46.815541 Listened to connection for namespace 'common' for up to 1s
2309 01:53:47.816452 Finalising connection for namespace 'common'
2310 01:53:47.816654 Disconnecting from shell: Finalise
2311 01:53:47.816759
2312 01:53:47.917153 end: 5.2 read-feedback (duration 00:00:01) [common]
2313 01:53:47.917320 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11733068
2314 01:53:47.935686 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11733068
2315 01:53:47.935869 JobError: Your job cannot terminate cleanly.