[Enter `^Ec?' for help] coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)... CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz CPU: ID 806c1, Tigerlake B0, ucode: 00000086 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU IGD: device id 9a40 (rev 01) is Tigerlake Y GT2 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0x1804000. FMAP: base = 0x0 size = 0x2000000 #areas = 32 FMAP: area COREBOOT found @ 1875000 (7909376 bytes) CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)... Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: area GBB found @ 1805000 (458752 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 FMAP: area COREBOOT found @ 1875000 (7909376 bytes) CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638 BS: verstage times (exec / console): total (unknown) / 142 ms coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)... VB2:vb2api_ec_sync() In recovery mode, skipping EC sync pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000 TCO_STS: 0000 0000 GEN_PMCON: d0015038 00002200 GBLRST_CAUSE: 00000000 00000000 HPR_CAUSE0: 00000000 prev_sleep_state 5 Boot Count incremented to 16688 FMAP: area COREBOOT found @ 1875000 (7909376 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c Chrome EC: UHEPI supported FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6 Initialized TPM device CR50 revision 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 MRC: Hash idx 0x100b comparison successful. MRC cache found, size faa8 bootmode is set to: 2 SPD index = 0 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c SPD: module type is LPDDR4X SPD: module part number is MT53E512M64D4NW-046 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 16 bits SPD: module size is 1024 MB (per channel) CBMEM: IMD: root @ 0x76fff000 254 entries. IMD: root @ 0x76ffec00 62 entries. FMAP: area RO_VPD found @ 1800000 (16384 bytes) FMAP: area RW_VPD found @ f35000 (8192 bytes) External stage cache: IMD: root @ 0x7b3ff000 254 entries. IMD: root @ 0x7b3fec00 62 entries. FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes) MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'. SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 MRC: 'RECOVERY_MRC_CACHE' does not need update. cse_lite: Skip switching to RW in the recovery path 8 DIMMs found SMM Memory Map SMRAM : 0x7b000000 0x800000 Subregion 0: 0x7b000000 0x200000 Subregion 1: 0x7b200000 0x200000 Subregion 2: 0x7b400000 0x400000 top_of_ram = 0x77000000 MTRR Range: Start=76000000 End=77000000 (Size 1000000) MTRR Range: Start=7b000000 End=7b800000 (Size 800000) MTRR Range: Start=f9000000 End=fa000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes) Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500 Processing 211 relocs. Offset value of 0x74c0b000 BS: romstage times (exec / console): total (unknown) / 277 ms coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)... FMAP: area COREBOOT found @ 1875000 (7909376 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes) Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270 Processing 5008 relocs. Offset value of 0x75d98000 BS: postcar times (exec / console): total (unknown) / 59 ms coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)... Normal boot FW_CONFIG value is 0x804c02 PCI: 00:07.0 disabled by fw_config PCI: 00:07.1 disabled by fw_config PCI: 00:0d.2 disabled by fw_config PCI: 00:1c.7 disabled by fw_config fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4 GENERIC: 0.0 disabled by fw_config GENERIC: 1.0 disabled by fw_config fw_config match found: DB_USB=USB3_ACTIVE fw_config match found: DB_USB=USB3_ACTIVE fw_config match found: DB_USB=USB3_ACTIVE fw_config match found: DB_USB=USB3_ACTIVE FMAP: area COREBOOT found @ 1875000 (7909376 bytes) MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c microcode: sig=0x806c1 pf=0x80 revision=0x86 microcode: Update skipped, already up-to-date CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c Detected 4 core, 8 thread CPU. Setting up SMI for CPU IED base = 0x7b400000 IED size = 0x00400000 Will perform SMM setup. CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 7 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1. AP: slot 7 apic_id 3. AP: slot 3 apic_id 2. AP: slot 5 apic_id 4. AP: slot 4 apic_id 5. AP: slot 6 apic_id 7. AP: slot 2 apic_id 6. done. Waiting for 2nd SIPI to complete...done. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 Unable to locate Global NVS SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000) Installing permanent SMM handler to 0x7b000000 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908 Processing 794 relocs. Offset value of 0x7b010000 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x7b008000 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd Unable to locate Global NVS SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000) Clearing SMI status registers SMI_STS: PM1 PM1_STS: PWRBTN smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0 In relocation handler: CPU 0 New SMBASE=0x7b000000 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1 In relocation handler: CPU 1 New SMBASE=0x7afffc00 IEDBASE=0x7b400000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3 In relocation handler: CPU 3 New SMBASE=0x7afff400 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7 In relocation handler: CPU 7 New SMBASE=0x7affe400 IEDBASE=0x7b400000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4 In relocation handler: CPU 4 New SMBASE=0x7afff000 IEDBASE=0x7b400000 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5 In relocation handler: CPU 5 New SMBASE=0x7affec00 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2 In relocation handler: CPU 2 New SMBASE=0x7afff800 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800c00 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6 In relocation handler: CPU 6 New SMBASE=0x7affe800 IEDBASE=0x7b400000 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is available and visible microcode: Update skipped, already up-to-date CPU #0 initialized Initializing CPU #7 Initializing CPU #3 CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... Initializing CPU #2 Initializing CPU #6 CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 Clearing out pending MCEs Clearing out pending MCEs Setting up local APIC... Initializing CPU #1 apic_id: 0x06 done. Setting up local APIC... Initializing CPU #5 CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 apic_id: 0x07 done. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date CPU #2 initialized CPU #6 initialized CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 Clearing out pending MCEs Setting up local APIC... Setting up local APIC... apic_id: 0x02 done. apic_id: 0x03 done. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date CPU #3 initialized CPU #7 initialized apic_id: 0x01 done. Initializing CPU #4 Clearing out pending MCEs CPU: vendor Intel device 806c1 CPU: family 06, model 8c, stepping 01 microcode: Update skipped, already up-to-date Clearing out pending MCEs Setting up local APIC... Setting up local APIC... CPU #1 initialized apic_id: 0x05 done. apic_id: 0x04 done. microcode: Update skipped, already up-to-date microcode: Update skipped, already up-to-date CPU #4 initialized CPU #5 initialized bsp_do_flight_plan done after 454 msecs. CPU: frequency set to 4000 MHz Enabling SMIs. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms SATAXPCIE1 indicates PCIe NVMe is present Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6 Initialized TPM device CR50 revision 0 Enabling S0i3.4 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc Found a VBT of 8704 bytes after decompression cse_lite: CSE RO boot. HybridStorageMode disabled WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called FSPS returned 0 Executing Phase 1 of FspMultiPhaseSiInit FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called port C0 DISC req: usage 1 usb3 1 usb2 5 Raw Buffer output 0 00000511 Raw Buffer output 1 00000000 pmc_send_ipc_cmd succeeded port C1 DISC req: usage 1 usb3 2 usb2 3 Raw Buffer output 0 00000321 Raw Buffer output 1 00000000 pmc_send_ipc_cmd succeeded Detected 4 core, 8 thread CPU. Detected 4 core, 8 thread CPU. Display FSP Version Info HOB Reference Code - CPU = a.0.4c.31 uCode Version = 0.0.0.86 TXT ACM version = ff.ff.ff.ffff Reference Code - ME = a.0.4c.31 MEBx version = 0.0.0.0 ME Firmware Version = Consumer SKU Reference Code - PCH = a.0.4c.31 PCH-CRID Status = Disabled PCH-CRID Original Value = ff.ff.ff.ffff PCH-CRID New Value = ff.ff.ff.ffff OPROM - RST - RAID = ff.ff.ff.ffff PCH Hsio Version = 4.0.0.0 Reference Code - SA - System Agent = a.0.4c.31 Reference Code - MRC = 2.0.0.1 SA - PCIe Version = a.0.4c.31 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.1 SA-CRID New Value = 0.0.0.1 OPROM - VBIOS = ff.ff.ff.ffff IO Manageability Engine FW Version = 11.1.4.0 PHY Build Version = 0.0.0.e0 Thunderbolt(TM) FW Version = 0.0.0.0 System Agent Manageability Engine FW Version = ff.ff.ff.ffff ITSS IRQ Polarities Before: IPC0: 0xffffffff IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0xffffffff ITSS IRQ Polarities After: IPC0: 0xffffffff IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0xffffffff Found PCIe Root Port #9 at PCI: 00:1d.0. pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing. pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing. pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing. BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 DOMAIN: 0000: enabled 1 CPU_CLUSTER: 0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 PCI: 00:07.1: enabled 0 PCI: 00:07.2: enabled 0 PCI: 00:07.3: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0d.0: enabled 1 PCI: 00:0d.1: enabled 0 PCI: 00:0d.2: enabled 0 PCI: 00:0d.3: enabled 0 PCI: 00:0e.0: enabled 0 PCI: 00:10.2: enabled 1 PCI: 00:10.6: enabled 0 PCI: 00:10.7: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:13.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:19.0: enabled 0 PCI: 00:19.1: enabled 1 PCI: 00:19.2: enabled 0 PCI: 00:1c.0: enabled 1 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 1 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 0 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 0 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 PCI: 00:1e.3: enabled 1 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 PCI: 00:1f.7: enabled 0 APIC: 00: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:31: enabled 1 I2C: 00:32: enabled 1 I2C: 00:10: enabled 1 I2C: 00:15: enabled 1 GENERIC: 0.0: enabled 0 GENERIC: 1.0: enabled 0 GENERIC: 0.0: enabled 1 SPI: 00: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 GENERIC: 0.0: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 0 USB3 port 3: enabled 0 USB2 port 0: enabled 0 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 0 USB2 port 4: enabled 1 USB2 port 5: enabled 0 USB2 port 6: enabled 0 USB2 port 7: enabled 0 USB2 port 8: enabled 0 USB2 port 9: enabled 0 USB3 port 0: enabled 0 USB3 port 1: enabled 1 USB3 port 2: enabled 0 USB3 port 3: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 APIC: 01: enabled 1 APIC: 06: enabled 1 APIC: 02: enabled 1 APIC: 05: enabled 1 APIC: 04: enabled 1 APIC: 07: enabled 1 APIC: 03: enabled 1 Compare with tree... Root Device: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:06.0: enabled 0 PCI: 00:07.0: enabled 0 GENERIC: 0.0: enabled 1 PCI: 00:07.1: enabled 0 GENERIC: 1.0: enabled 1 PCI: 00:07.2: enabled 0 GENERIC: 0.0: enabled 1 PCI: 00:07.3: enabled 0 GENERIC: 1.0: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:0a.0: enabled 0 PCI: 00:0d.0: enabled 1 USB0 port 0: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 0 USB3 port 3: enabled 0 PCI: 00:0d.1: enabled 0 PCI: 00:0d.2: enabled 0 GENERIC: 0.0: enabled 1 PCI: 00:0d.3: enabled 0 PCI: 00:0e.0: enabled 0 PCI: 00:10.2: enabled 1 PCI: 00:10.6: enabled 0 PCI: 00:10.7: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:13.0: enabled 0 PCI: 00:14.0: enabled 1 USB0 port 0: enabled 1 USB2 port 0: enabled 0 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 0 USB2 port 4: enabled 1 USB2 port 5: enabled 0 USB2 port 6: enabled 0 USB2 port 7: enabled 0 USB2 port 8: enabled 0 USB2 port 9: enabled 0 USB3 port 0: enabled 0 USB3 port 1: enabled 1 USB3 port 2: enabled 0 USB3 port 3: enabled 0 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 1 PCI: 00:14.3: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:15.0: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:31: enabled 1 I2C: 00:32: enabled 1 PCI: 00:15.1: enabled 1 I2C: 00:10: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:19.0: enabled 0 PCI: 00:19.1: enabled 1 I2C: 00:15: enabled 1 PCI: 00:19.2: enabled 0 PCI: 00:1d.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 SPI: 00: enabled 1 PCI: 00:1e.3: enabled 1 SPI: 00: enabled 1 PCI: 00:1f.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 GENERIC: 1.0: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 PCI: 00:1f.7: enabled 0 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: 01: enabled 1 APIC: 06: enabled 1 APIC: 02: enabled 1 APIC: 05: enabled 1 APIC: 04: enabled 1 APIC: 07: enabled 1 APIC: 03: enabled 1 Root Device scanning... scan_static_bus for Root Device DOMAIN: 0000 enabled CPU_CLUSTER: 0 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/9a12] enabled PCI: 00:02.0 [8086/0000] bus ops PCI: 00:02.0 [8086/9a40] enabled PCI: 00:04.0 [8086/0000] bus ops PCI: 00:04.0 [8086/9a03] enabled PCI: 00:05.0 [8086/9a19] enabled PCI: 00:07.0 [0000/0000] hidden PCI: 00:08.0 [8086/9a11] enabled PCI: 00:0a.0 [8086/9a0d] disabled PCI: 00:0d.0 [8086/0000] bus ops PCI: 00:0d.0 [8086/9a13] enabled PCI: 00:14.0 [8086/0000] bus ops PCI: 00:14.0 [8086/a0ed] enabled PCI: 00:14.2 [8086/a0ef] enabled PCI: 00:14.3 [8086/0000] bus ops PCI: 00:14.3 [8086/a0f0] enabled PCI: 00:15.0 [8086/0000] bus ops PCI: 00:15.0 [8086/a0e8] enabled PCI: 00:15.1 [8086/0000] bus ops PCI: 00:15.1 [8086/a0e9] enabled PCI: 00:15.2 [8086/0000] bus ops PCI: 00:15.2 [8086/a0ea] enabled PCI: 00:15.3 [8086/0000] bus ops PCI: 00:15.3 [8086/a0eb] enabled PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/a0e0] enabled PCI: Static device PCI: 00:17.0 not found, disabling it. PCI: 00:19.0 [8086/0000] bus ops PCI: 00:19.0 [8086/a0c5] disabled PCI: 00:19.1 [8086/0000] bus ops PCI: 00:19.1 [8086/a0c6] enabled PCI: 00:1d.0 [8086/0000] bus ops PCI: 00:1d.0 [8086/a0b0] enabled PCI: 00:1e.0 [8086/0000] ops PCI: 00:1e.0 [8086/a0a8] enabled PCI: 00:1e.2 [8086/0000] bus ops PCI: 00:1e.2 [8086/a0aa] enabled PCI: 00:1e.3 [8086/0000] bus ops PCI: 00:1e.3 [8086/a0ab] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/a087] enabled RTC Init Set power on after power failure. Disabling Deep S3 Disabling Deep S3 Disabling Deep S4 Disabling Deep S4 Disabling Deep S5 Disabling Deep S5 PCI: 00:1f.2 [0000/0000] hidden PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/a0c8] enabled PCI: 00:1f.5 [8086/0000] bus ops PCI: 00:1f.5 [8086/a0a4] enabled PCI: Leftover static devices: PCI: 00:10.2 PCI: 00:10.6 PCI: 00:10.7 PCI: 00:06.0 PCI: 00:07.1 PCI: 00:07.2 PCI: 00:07.3 PCI: 00:09.0 PCI: 00:0d.1 PCI: 00:0d.2 PCI: 00:0d.3 PCI: 00:0e.0 PCI: 00:12.0 PCI: 00:12.6 PCI: 00:13.0 PCI: 00:14.1 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:16.4 PCI: 00:16.5 PCI: 00:17.0 PCI: 00:19.2 PCI: 00:1e.1 PCI: 00:1f.1 PCI: 00:1f.4 PCI: 00:1f.6 PCI: 00:1f.7 PCI: Check your devicetree.cb. PCI: 00:02.0 scanning... scan_generic_bus for PCI: 00:02.0 scan_generic_bus for PCI: 00:02.0 done scan_bus: bus PCI: 00:02.0 finished in 7 msecs PCI: 00:04.0 scanning... scan_generic_bus for PCI: 00:04.0 GENERIC: 0.0 enabled bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done scan_bus: bus PCI: 00:04.0 finished in 11 msecs PCI: 00:0d.0 scanning... scan_static_bus for PCI: 00:0d.0 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB3 port 0 enabled USB3 port 1 enabled USB3 port 2 disabled USB3 port 3 disabled USB3 port 0 scanning... scan_static_bus for USB3 port 0 scan_static_bus for USB3 port 0 done scan_bus: bus USB3 port 0 finished in 6 msecs USB3 port 1 scanning... scan_static_bus for USB3 port 1 scan_static_bus for USB3 port 1 done scan_bus: bus USB3 port 1 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 43 msecs scan_static_bus for PCI: 00:0d.0 done scan_bus: bus PCI: 00:0d.0 finished in 60 msecs PCI: 00:14.0 scanning... scan_static_bus for PCI: 00:14.0 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB2 port 0 disabled USB2 port 1 enabled USB2 port 2 enabled USB2 port 3 disabled USB2 port 4 enabled USB2 port 5 disabled USB2 port 6 disabled USB2 port 7 disabled USB2 port 8 disabled USB2 port 9 disabled USB3 port 0 disabled USB3 port 1 enabled USB3 port 2 disabled USB3 port 3 disabled USB2 port 1 scanning... scan_static_bus for USB2 port 1 scan_static_bus for USB2 port 1 done scan_bus: bus USB2 port 1 finished in 6 msecs USB2 port 2 scanning... scan_static_bus for USB2 port 2 scan_static_bus for USB2 port 2 done scan_bus: bus USB2 port 2 finished in 6 msecs USB2 port 4 scanning... scan_static_bus for USB2 port 4 scan_static_bus for USB2 port 4 done scan_bus: bus USB2 port 4 finished in 6 msecs USB3 port 1 scanning... scan_static_bus for USB3 port 1 scan_static_bus for USB3 port 1 done scan_bus: bus USB3 port 1 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 93 msecs scan_static_bus for PCI: 00:14.0 done scan_bus: bus PCI: 00:14.0 finished in 110 msecs PCI: 00:14.3 scanning... scan_static_bus for PCI: 00:14.3 GENERIC: 0.0 enabled scan_static_bus for PCI: 00:14.3 done scan_bus: bus PCI: 00:14.3 finished in 9 msecs PCI: 00:15.0 scanning... scan_static_bus for PCI: 00:15.0 I2C: 00:1a enabled I2C: 00:31 enabled I2C: 00:32 enabled scan_static_bus for PCI: 00:15.0 done scan_bus: bus PCI: 00:15.0 finished in 13 msecs PCI: 00:15.1 scanning... scan_static_bus for PCI: 00:15.1 I2C: 00:10 enabled scan_static_bus for PCI: 00:15.1 done scan_bus: bus PCI: 00:15.1 finished in 9 msecs PCI: 00:15.2 scanning... scan_static_bus for PCI: 00:15.2 scan_static_bus for PCI: 00:15.2 done scan_bus: bus PCI: 00:15.2 finished in 7 msecs PCI: 00:15.3 scanning... scan_static_bus for PCI: 00:15.3 scan_static_bus for PCI: 00:15.3 done scan_bus: bus PCI: 00:15.3 finished in 7 msecs PCI: 00:19.1 scanning... scan_static_bus for PCI: 00:19.1 I2C: 00:15 enabled scan_static_bus for PCI: 00:19.1 done scan_bus: bus PCI: 00:19.1 finished in 9 msecs PCI: 00:1d.0 scanning... do_pci_scan_bridge for PCI: 00:1d.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [1c5c/174a] enabled GENERIC: 0.0 enabled Enabling Common Clock Configuration L1 Sub-State supported from root port 29 L1 Sub-State Support = 0xf CommonModeRestoreTime = 0x28 Power On Value = 0x16, Power On Scale = 0x0 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs PCI: 00:1e.2 scanning... scan_generic_bus for PCI: 00:1e.2 SPI: 00 enabled bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done scan_bus: bus PCI: 00:1e.2 finished in 11 msecs PCI: 00:1e.3 scanning... scan_generic_bus for PCI: 00:1e.3 SPI: 00 enabled bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done scan_bus: bus PCI: 00:1e.3 finished in 11 msecs PCI: 00:1f.0 scanning... scan_static_bus for PCI: 00:1f.0 PNP: 0c09.0 enabled PNP: 0c09.0 scanning... scan_static_bus for PNP: 0c09.0 scan_static_bus for PNP: 0c09.0 done scan_bus: bus PNP: 0c09.0 finished in 6 msecs scan_static_bus for PCI: 00:1f.0 done scan_bus: bus PCI: 00:1f.0 finished in 23 msecs PCI: 00:1f.2 scanning... scan_static_bus for PCI: 00:1f.2 GENERIC: 0.0 enabled GENERIC: 0.0 scanning... scan_static_bus for GENERIC: 0.0 GENERIC: 0.0 enabled GENERIC: 1.0 enabled scan_static_bus for GENERIC: 0.0 done scan_bus: bus GENERIC: 0.0 finished in 11 msecs scan_static_bus for PCI: 00:1f.2 done scan_bus: bus PCI: 00:1f.2 finished in 28 msecs PCI: 00:1f.3 scanning... scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done scan_bus: bus PCI: 00:1f.3 finished in 7 msecs PCI: 00:1f.5 scanning... scan_generic_bus for PCI: 00:1f.5 scan_generic_bus for PCI: 00:1f.5 done scan_bus: bus PCI: 00:1f.5 finished in 7 msecs scan_bus: bus DOMAIN: 0000 finished in 717 msecs scan_static_bus for Root Device done scan_bus: bus Root Device finished in 737 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms Chrome EC: UHEPI supported FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x2000000 SPI flash protection: WPSW=0 SRP0=0 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 done PCI: 00:0d.0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 00:0d.0 read_resources bus 0 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:15.0 read_resources bus 0 link: 0 PCI: 00:15.0 read_resources bus 0 link: 0 done PCI: 00:15.1 read_resources bus 0 link: 0 PCI: 00:15.1 read_resources bus 0 link: 0 done PCI: 00:19.1 read_resources bus 0 link: 0 PCI: 00:19.1 read_resources bus 0 link: 0 done PCI: 00:1d.0 read_resources bus 1 link: 0 PCI: 00:1d.0 read_resources bus 1 link: 0 done PCI: 00:1e.2 read_resources bus 2 link: 0 PCI: 00:1e.2 read_resources bus 2 link: 0 done PCI: 00:1e.3 read_resources bus 3 link: 0 PCI: 00:1e.3 read_resources bus 3 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI: 00:1f.2 read_resources bus 0 link: 0 GENERIC: 0.0 read_resources bus 0 link: 0 GENERIC: 0.0 read_resources bus 0 link: 0 done PCI: 00:1f.2 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 DOMAIN: 0000 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:05.0 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:07.0 child on link 0 GENERIC: 0.0 GENERIC: 0.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:0a.0 PCI: 00:0d.0 child on link 0 USB0 port 0 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB3 port 0 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 4 USB2 port 5 USB2 port 6 USB2 port 7 USB2 port 8 USB2 port 9 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 00:14.3 child on link 0 GENERIC: 0.0 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:15.0 child on link 0 I2C: 00:1a PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:1a I2C: 00:31 I2C: 00:32 PCI: 00:15.1 child on link 0 I2C: 00:10 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:10 PCI: 00:15.2 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.3 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:19.0 PCI: 00:19.1 child on link 0 I2C: 00:15 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:15 PCI: 00:1d.0 child on link 0 GENERIC: 0.0 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 GENERIC: 0.0 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:1e.0 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:1e.2 child on link 0 SPI: 00 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 SPI: 00 PCI: 00:1e.3 child on link 0 SPI: 00 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.2 child on link 0 GENERIC: 0.0 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1 GENERIC: 0.0 child on link 0 GENERIC: 0.0 GENERIC: 0.0 GENERIC: 1.0 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20 PCI: 00:1f.5 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 01 APIC: 06 APIC: 02 APIC: 05 APIC: 04 APIC: 07 APIC: 03 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x3fff] mem PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed) update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 800, Tag: 100 * Base: 1900, Size: e700, Tag: 100 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed) update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed) update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed) update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed) update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed) update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed) update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed) update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed) update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed) update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed) update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed) update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed) update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed) update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed) update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed) update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed) update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed) update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed) update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed) update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 7fc00000, Size: 40400000, Tag: 200 * Base: d0000000, Size: 28000000, Tag: 200 * Base: fa000000, Size: 1000000, Tag: 200 * Base: fb001000, Size: 2fff000, Tag: 200 * Base: fe010000, Size: 2e000, Tag: 200 * Base: fe03f000, Size: d41000, Tag: 200 * Base: fed88000, Size: 8000, Tag: 200 * Base: fed93000, Size: d000, Tag: 200 * Base: feda2000, Size: 1e000, Tag: 200 * Base: fede0000, Size: 1220000, Tag: 200 * Base: 280400000, Size: 7d7fc00000, Tag: 100200 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff PCI: 00:1d.0: Resource ranges: * Base: 7fc00000, Size: 100000, Tag: 200 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assi