[Enter `^Ec?' for help] � coreboot-7d042db9 Mon Oct 22 20:40:09 UTC 2018 bootblock starting... Exception handlers installed. Configuring PLL at ff760030 with NF = 99, NR = 2 and NO = 2 (VCO = 1188000KHz, output = 594000KHz) Configuring PLL at ff760020 with NF = 32, NR = 1 and NO = 2 (VCO = 768000KHz, output = 384000KHz) Translation table is @ ff700000 Mapping address range [0x00000000:0x00000000) as uncached Creating new subtable @ff720800 for [0xff700000:0xff800000) Mapping address range [0xff700000:0xff718000) as writethrough I2C bus 0: 386718Hz (divh = 9, divl = 13) Configuring PLL at ff760000 with NF = 75, NR = 1 and NO = 1 (VCO = 1800000KHz, output = 1800000KHz) I2C bus 1: 386718Hz (divh = 9, divl = 13) Manufacturer: c8 SF: Detected GD25Q32(B) with sector size 0x1000, total 0x400000 VBOOT: Loading verstage. CBFS @ 20000 size e0000 CBFS: 'Master Header Locator' located CBFS at [20000:100000) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 16d00 size 7797 coreboot-7d042db9 Mon Oct 22 20:40:09 UTC 2018 verstage starting... Exception handlers installed. out: cmd=0x17: 03 c3 17 00 01 00 14 00 00 00 00 00 00 00 00 00 6b f7 70 ff 9c 7e 71 ff c4 7f 71 ff in-header: 03 5d 00 00 10 00 00 00 in-data: 70 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20 tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms I2C TPM 1:20 (chip type slb9645tt device-id 0x1A) TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded TPM: tlcl_read(0x1007, 10) TPM: command 0xcf returned 0x0 out: cmd=0xd: 03 f0 0d 00 00 00 00 00 in-header: 03 fc 01 00 00 00 00 00 in-data: handle_proto3_response: EC response with error code: 1 Chrome EC: UHEPI not supported out: cmd=0x87: 03 89 87 00 00 00 04 00 79 00 71 ff in-header: 03 19 00 00 04 00 00 00 in-data: 80 20 40 00 Phase 1 Manufacturer: c8 SF: Detected GD25Q32(B) with sector size 0x1000, total 0x400000 FMAP: Found "FLASH" version 1.1 at 100000. FMAP: base = 0 size = 400000 #areas = 21 FMAP: area GBB found @ 101000 (978688 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ 101000 (978688 bytes) VB2:vb2_report_dev_firmware() This is developer signed firmware FMAP: area VBLOCK_A found @ 200000 (8192 bytes) FMAP: area VBLOCK_A found @ 200000 (8192 bytes) VB2:vb2_verify_keyblock() Checking key block signature... VB2:vb2_load_fw_keyblock() Ignoring FW key rollback due to GBB flag FMAP: area VBLOCK_A found @ 200000 (8192 bytes) FMAP: area VBLOCK_A found @ 200000 (8192 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. VB2:vb2_load_fw_preamble() Ignoring FW rollback due to GBB flag Phase 4 FMAP: area FW_MAIN_A found @ 202000 (483072 bytes) Initialized RK3288 HW crypto for 221376 byte SHA256 VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2 TPM: command 0x14 returned 0x0 TPM: command 0x14 returned 0x0 TPM: Set global lock TPM: tlcl_write(0x0, 0) TPM: command 0xcd returned 0x0 Slot A is selected CBFS: 'VBOOT' located CBFS at [202000:2380c0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 0 size 5438 coreboot-7d042db9 Mon Oct 22 20:40:09 UTC 2018 romstage starting... Exception handlers installed. RAM Config: 5. Starting SDRAM initialization... Configuring PLL at ff760010 with NF = 500, NR = 9 and NO = 2 (VCO = 1333333KHz, output = 666666KHz)