[Enter `^Ec?' for help] � coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 bootblock starting (log level: 8)... CPU: Intel(R) Celeron(R) CPU 5205U @ 1.90GHz CPU: ID a0660, Cometlake-U A0 (6+2), ucode: 000000c9 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 9b71 (rev 00) is CometLake-U (2+2) PCH: device id 0285 (rev 00) is Cometlake-U Base IGD: device id 9baa (rev 04) is CometLake ULT GT2 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0xc04000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 32 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 10c240 size 1152c coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 verstage starting (log level: 8)... Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: area GBB found @ c05000 (12288 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 1607c BS: verstage times (exec / console): total (unknown) / 119 ms coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 romstage starting (log level: 8)... VB2:vb2api_ec_sync() In recovery mode, skipping EC sync pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 TCO_STS: 0000 0000 GEN_PMCON: e0015038 00000200 GBLRST_CAUSE: 00000000 00000000 prev_sleep_state 5 Boot Count incremented to 21160 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 66fc0 size 71000 Chrome EC: UHEPI supported FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66 Initialized TPM device CR50 revision 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE MRC cache found, size 1948 bootmode is set to: 2 PRMRR disabled by config. FMAP: area RW_SPD_CACHE found @ aff000 (4096 bytes) SPD_CACHE: cache found, size 0x1000 No memory dimm at address 50 SPD_CACHE: DIMM0 is not present SPD_CACHE: DIMM1 is the same SPD @ 0x52 SPD: module type is DDR4 SPD: module part number is HMA851S6CJR6N-VK SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) memory slot: 2 configuration done. CBMEM: IMD: root @ 0x99fff000 254 entries. IMD: root @ 0x99ffec00 62 entries. FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ af8000 (8192 bytes) External stage cache: IMD: root @ 0x9abff000 254 entries. IMD: root @ 0x9abfec00 62 entries. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 tlcl_write: response is 0 MRC: TPM MRC hash updated successfully. 1 DIMMs found SMM Memory Map SMRAM : 0x9a000000 0x1000000 Subregion 0: 0x9a000000 0xa00000 Subregion 1: 0x9aa00000 0x200000 Subregion 2: 0x9ac00000 0x400000 top_of_ram = 0x9a000000 MTRR Range: Start=99000000 End=9a000000 (Size 1000000) MTRR Range: Start=9a000000 End=9b000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 1076c0 size 4b28 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes) Loading module at 0x99c0c000 with entry 0x99c0c000. filesize: 0x4818 memsize: 0x8af8 Processing 173 relocs. Offset value of 0x97c0c000 BS: romstage times (exec / console): total (unknown) / 267 ms coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 postcar starting (log level: 8)... FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 44e00 size 1e0ef Decompressing stage fallback/ramstage @ 0x99ba4fc0 (415200 bytes) Loading module at 0x99ba5000 with entry 0x99ba5000. filesize: 0x46598 memsize: 0x655a0 Processing 4604 relocs. Offset value of 0x98da5000 BS: postcar times (exec / console): total (unknown) / 43 ms coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 ramstage starting (log level: 8)... Normal boot cse_lite: Skip switching to RW in the recovery path BS: BS_PRE_DEVICE entry times (exec / console): 0 / 5 ms FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 16180 size 2ec00 microcode: sig=0xa0660 pf=0x80 revision=0xc9 Skip microcode update FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fsps.bin' CBFS: Found @ offset d8fc0 size 2e69d Detected 2 core, 2 thread CPU. Setting up SMI for CPU IED base = 0x9ac00000 IED size = 0x00400000 Will perform SMM setup. CPU: Intel(R) Celeron(R) CPU 5205U @ 1.90GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. AP: slot 1 apic_id 2. Waiting for 2nd SIPI to complete...done. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 0x00038000. Will call 0x99bc2760(0x00000000) Installing SMM handler to 0x9a000000 Loading module at 0x9a010000 with entry 0x9a010a30. filesize: 0x7bc8 memsize: 0xcc90 Processing 617 relocs. Offset value of 0x9a010000 Loading module at 0x9a008000 with entry 0x9a008000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x9a008000 SMM Module: placing jmp sequence at 0x9a007c00 rel16 0x03fd SMM Module: stub loaded at 0x9a008000. Will call 0x9a010a30(0x00000000) Clearing SMI status registers SMI_STS: PM1 PM1_STS: PWRBTN New SMBASE 0x9a000000 In relocation handler: CPU 0 New SMBASE=0x9a000000 IEDBASE=0x9ac00000 Writing SMRR. base = 0x9a000006, mask=0xff000800 Relocation complete. New SMBASE 0x99fffc00 In relocation handler: CPU 1 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000 Writing SMRR. base = 0x9a000006, mask=0xff000800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device a0660 CPU: family 06, model a6, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is unavailable VMX status: enabled IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device a0660 CPU: family 06, model a6, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x02 done. VMX status: enabled IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #1 initialized bsp_do_flight_plan done after 160 msecs. Enabling SMIs. Locking SMM. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 89 / 199 ms Waiting for DisplayPort DisplayPort not ready after 3000ms. Abort. FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 66a80 size 49e Found