Boot log: acer-cbv514-1h-34uz-brya
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Kernel Warnings: 0
1 07:06:28.869146 lava-dispatcher, installed at version: 2024.03
2 07:06:28.869359 start: 0 validate
3 07:06:28.869467 Start time: 2024-06-24 07:06:28.869460+00:00 (UTC)
4 07:06:28.869601 Using caching service: 'http://localhost/cache/?uri=%s'
5 07:06:28.869736 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Fx86%2Frootfs.cpio.gz exists
6 07:06:29.123348 Using caching service: 'http://localhost/cache/?uri=%s'
7 07:06:29.124119 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-5.10.y-cip-rc%2Fv5.10.218-cip49-1-g6e4566075fbe7%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fkernel%2FbzImage exists
8 07:06:34.134182 Using caching service: 'http://localhost/cache/?uri=%s'
9 07:06:34.134357 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-iwamatsu-linux-5.10.y-cip-rc%2Fv5.10.218-cip49-1-g6e4566075fbe7%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fmodules.tar.xz exists
10 07:06:36.139043 validate duration: 7.27
12 07:06:36.139292 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 07:06:36.139398 start: 1.1 download-retry (timeout 00:10:00) [common]
14 07:06:36.139486 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 07:06:36.139627 Not decompressing ramdisk as can be used compressed.
16 07:06:36.139712 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/x86/rootfs.cpio.gz
17 07:06:36.139780 saving as /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/ramdisk/rootfs.cpio.gz
18 07:06:36.139842 total size: 8417901 (8 MB)
19 07:06:36.140878 progress 0 % (0 MB)
20 07:06:36.143180 progress 5 % (0 MB)
21 07:06:36.145384 progress 10 % (0 MB)
22 07:06:36.147585 progress 15 % (1 MB)
23 07:06:36.149830 progress 20 % (1 MB)
24 07:06:36.152028 progress 25 % (2 MB)
25 07:06:36.154276 progress 30 % (2 MB)
26 07:06:36.156363 progress 35 % (2 MB)
27 07:06:36.158548 progress 40 % (3 MB)
28 07:06:36.160739 progress 45 % (3 MB)
29 07:06:36.163073 progress 50 % (4 MB)
30 07:06:36.165274 progress 55 % (4 MB)
31 07:06:36.167440 progress 60 % (4 MB)
32 07:06:36.169489 progress 65 % (5 MB)
33 07:06:36.171674 progress 70 % (5 MB)
34 07:06:36.173919 progress 75 % (6 MB)
35 07:06:36.176056 progress 80 % (6 MB)
36 07:06:36.178271 progress 85 % (6 MB)
37 07:06:36.180433 progress 90 % (7 MB)
38 07:06:36.182657 progress 95 % (7 MB)
39 07:06:36.184657 progress 100 % (8 MB)
40 07:06:36.184887 8 MB downloaded in 0.05 s (178.26 MB/s)
41 07:06:36.185085 end: 1.1.1 http-download (duration 00:00:00) [common]
43 07:06:36.185304 end: 1.1 download-retry (duration 00:00:00) [common]
44 07:06:36.185389 start: 1.2 download-retry (timeout 00:10:00) [common]
45 07:06:36.185469 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 07:06:36.185602 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-5.10.y-cip-rc/v5.10.218-cip49-1-g6e4566075fbe7/x86_64/x86_64_defconfig+x86-board/gcc-10/kernel/bzImage
47 07:06:36.185664 saving as /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/kernel/bzImage
48 07:06:36.185717 total size: 19684992 (18 MB)
49 07:06:36.185772 No compression specified
50 07:06:36.186807 progress 0 % (0 MB)
51 07:06:36.191877 progress 5 % (0 MB)
52 07:06:36.196959 progress 10 % (1 MB)
53 07:06:36.201984 progress 15 % (2 MB)
54 07:06:36.206937 progress 20 % (3 MB)
55 07:06:36.211915 progress 25 % (4 MB)
56 07:06:36.216868 progress 30 % (5 MB)
57 07:06:36.221855 progress 35 % (6 MB)
58 07:06:36.226855 progress 40 % (7 MB)
59 07:06:36.231821 progress 45 % (8 MB)
60 07:06:36.236782 progress 50 % (9 MB)
61 07:06:36.241819 progress 55 % (10 MB)
62 07:06:36.246841 progress 60 % (11 MB)
63 07:06:36.251798 progress 65 % (12 MB)
64 07:06:36.256793 progress 70 % (13 MB)
65 07:06:36.261775 progress 75 % (14 MB)
66 07:06:36.266792 progress 80 % (15 MB)
67 07:06:36.271686 progress 85 % (15 MB)
68 07:06:36.276584 progress 90 % (16 MB)
69 07:06:36.281505 progress 95 % (17 MB)
70 07:06:36.286417 progress 100 % (18 MB)
71 07:06:36.286618 18 MB downloaded in 0.10 s (186.06 MB/s)
72 07:06:36.286765 end: 1.2.1 http-download (duration 00:00:00) [common]
74 07:06:36.286972 end: 1.2 download-retry (duration 00:00:00) [common]
75 07:06:36.287054 start: 1.3 download-retry (timeout 00:10:00) [common]
76 07:06:36.287130 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 07:06:36.287260 downloading http://storage.kernelci.org/cip-gitlab/ci-iwamatsu-linux-5.10.y-cip-rc/v5.10.218-cip49-1-g6e4566075fbe7/x86_64/x86_64_defconfig+x86-board/gcc-10/modules.tar.xz
78 07:06:36.287322 saving as /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/modules/modules.tar
79 07:06:36.287375 total size: 1635364 (1 MB)
80 07:06:36.287430 Using unxz to decompress xz
81 07:06:36.288827 progress 2 % (0 MB)
82 07:06:36.291059 progress 8 % (0 MB)
83 07:06:36.296859 progress 14 % (0 MB)
84 07:06:36.302634 progress 20 % (0 MB)
85 07:06:36.308252 progress 26 % (0 MB)
86 07:06:36.313945 progress 32 % (0 MB)
87 07:06:36.319707 progress 38 % (0 MB)
88 07:06:36.325547 progress 44 % (0 MB)
89 07:06:36.330813 progress 50 % (0 MB)
90 07:06:36.337509 progress 56 % (0 MB)
91 07:06:36.343469 progress 62 % (0 MB)
92 07:06:36.349055 progress 68 % (1 MB)
93 07:06:36.354629 progress 74 % (1 MB)
94 07:06:36.359799 progress 80 % (1 MB)
95 07:06:36.366586 progress 86 % (1 MB)
96 07:06:36.372579 progress 92 % (1 MB)
97 07:06:36.378525 progress 98 % (1 MB)
98 07:06:36.386893 1 MB downloaded in 0.10 s (15.67 MB/s)
99 07:06:36.387051 end: 1.3.1 http-download (duration 00:00:00) [common]
101 07:06:36.387264 end: 1.3 download-retry (duration 00:00:00) [common]
102 07:06:36.387343 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
103 07:06:36.387421 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
104 07:06:36.387492 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
105 07:06:36.387563 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
106 07:06:36.387711 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_
107 07:06:36.387823 makedir: /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin
108 07:06:36.387913 makedir: /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/tests
109 07:06:36.387997 makedir: /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/results
110 07:06:36.388090 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-add-keys
111 07:06:36.388217 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-add-sources
112 07:06:36.388331 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-background-process-start
113 07:06:36.388442 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-background-process-stop
114 07:06:36.388562 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-common-functions
115 07:06:36.388675 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-echo-ipv4
116 07:06:36.388784 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-install-packages
117 07:06:36.388892 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-installed-packages
118 07:06:36.388998 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-os-build
119 07:06:36.389152 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-probe-channel
120 07:06:36.389260 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-probe-ip
121 07:06:36.389368 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-target-ip
122 07:06:36.389475 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-target-mac
123 07:06:36.389582 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-target-storage
124 07:06:36.389693 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-case
125 07:06:36.389801 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-event
126 07:06:36.389909 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-feedback
127 07:06:36.390017 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-raise
128 07:06:36.390128 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-reference
129 07:06:36.390241 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-runner
130 07:06:36.390354 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-set
131 07:06:36.390463 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-test-shell
132 07:06:36.390573 Updating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-install-packages (oe)
133 07:06:36.390711 Updating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/bin/lava-installed-packages (oe)
134 07:06:36.390819 Creating /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/environment
135 07:06:36.390903 LAVA metadata
136 07:06:36.390967 - LAVA_JOB_ID=14531168
137 07:06:36.391023 - LAVA_DISPATCHER_IP=192.168.201.1
138 07:06:36.391111 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
139 07:06:36.391167 skipped lava-vland-overlay
140 07:06:36.391231 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
141 07:06:36.391301 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
142 07:06:36.391357 skipped lava-multinode-overlay
143 07:06:36.391421 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
144 07:06:36.391490 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
145 07:06:36.391550 Loading test definitions
146 07:06:36.391622 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
147 07:06:36.391693 Using /lava-14531168 at stage 0
148 07:06:36.391982 uuid=14531168_1.4.2.3.1 testdef=None
149 07:06:36.392074 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
150 07:06:36.392155 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
151 07:06:36.392620 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
153 07:06:36.392815 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
154 07:06:36.393445 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
156 07:06:36.393653 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
157 07:06:36.394251 runner path: /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/0/tests/0_dmesg test_uuid 14531168_1.4.2.3.1
158 07:06:36.394396 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
160 07:06:36.394596 Creating lava-test-runner.conf files
161 07:06:36.394680 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14531168/lava-overlay-s4w9si7_/lava-14531168/0 for stage 0
162 07:06:36.394786 - 0_dmesg
163 07:06:36.394904 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
164 07:06:36.395006 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
165 07:06:36.401239 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
166 07:06:36.401348 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
167 07:06:36.401431 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
168 07:06:36.401509 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
169 07:06:36.401585 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
170 07:06:36.641583 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
171 07:06:36.641717 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
172 07:06:36.641797 extracting modules file /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14531168/extract-overlay-ramdisk-ba4il8fk/ramdisk
173 07:06:36.685221 end: 1.4.4 extract-modules (duration 00:00:00) [common]
174 07:06:36.685350 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
175 07:06:36.685432 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14531168/compress-overlay-3pnnavx3/overlay-1.4.2.4.tar.gz to ramdisk
176 07:06:36.685493 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14531168/compress-overlay-3pnnavx3/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14531168/extract-overlay-ramdisk-ba4il8fk/ramdisk
177 07:06:36.692581 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
178 07:06:36.692709 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
179 07:06:36.692816 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
180 07:06:36.692920 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
181 07:06:36.693023 Building ramdisk /var/lib/lava/dispatcher/tmp/14531168/extract-overlay-ramdisk-ba4il8fk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14531168/extract-overlay-ramdisk-ba4il8fk/ramdisk
182 07:06:36.852226 >> 67295 blocks
183 07:06:37.969896 rename /var/lib/lava/dispatcher/tmp/14531168/extract-overlay-ramdisk-ba4il8fk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/ramdisk/ramdisk.cpio.gz
184 07:06:37.970082 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
185 07:06:37.970207 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
186 07:06:37.970289 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
187 07:06:37.970357 No mkimage arch provided, not using FIT.
188 07:06:37.970428 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
189 07:06:37.970498 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
190 07:06:37.970571 end: 1.4 prepare-tftp-overlay (duration 00:00:02) [common]
191 07:06:37.970643 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
192 07:06:37.970701 No LXC device requested
193 07:06:37.970765 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
194 07:06:37.970835 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
195 07:06:37.970903 end: 1.6 deploy-device-env (duration 00:00:00) [common]
196 07:06:37.970963 Checking files for TFTP limit of 4294967296 bytes.
197 07:06:37.971239 end: 1 tftp-deploy (duration 00:00:02) [common]
198 07:06:37.971324 start: 2 depthcharge-action (timeout 00:05:00) [common]
199 07:06:37.971401 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
200 07:06:37.971485 substitutions:
201 07:06:37.971544 - {DTB}: None
202 07:06:37.971598 - {INITRD}: 14531168/tftp-deploy-puyn5imd/ramdisk/ramdisk.cpio.gz
203 07:06:37.971650 - {KERNEL}: 14531168/tftp-deploy-puyn5imd/kernel/bzImage
204 07:06:37.971700 - {LAVA_MAC}: None
205 07:06:37.971750 - {PRESEED_CONFIG}: None
206 07:06:37.971799 - {PRESEED_LOCAL}: None
207 07:06:37.971848 - {RAMDISK}: 14531168/tftp-deploy-puyn5imd/ramdisk/ramdisk.cpio.gz
208 07:06:37.971905 - {ROOT_PART}: None
209 07:06:37.971955 - {ROOT}: None
210 07:06:37.972007 - {SERVER_IP}: 192.168.201.1
211 07:06:37.972063 - {TEE}: None
212 07:06:37.972111 Parsed boot commands:
213 07:06:37.972158 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
214 07:06:37.972291 Parsed boot commands: tftpboot 192.168.201.1 14531168/tftp-deploy-puyn5imd/kernel/bzImage 14531168/tftp-deploy-puyn5imd/kernel/cmdline 14531168/tftp-deploy-puyn5imd/ramdisk/ramdisk.cpio.gz
215 07:06:37.972370 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
216 07:06:37.972443 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
217 07:06:37.972516 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
218 07:06:37.972586 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
219 07:06:37.972648 Not connected, no need to disconnect.
220 07:06:37.972744 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
221 07:06:37.972853 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
222 07:06:37.972945 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh acer-cbv514-1h-34uz-brya-cbg-4'
223 07:06:37.976390 Setting prompt string to ['lava-test: # ']
224 07:06:37.976690 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
225 07:06:37.976781 end: 2.2.1 reset-connection (duration 00:00:00) [common]
226 07:06:37.976869 start: 2.2.2 reset-device (timeout 00:05:00) [common]
227 07:06:37.976979 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
228 07:06:37.977201 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'acer-cbv514-1h-34uz-brya-cbg-4']
229 07:06:51.622262 Returned 0 in 13 seconds
230 07:06:51.722772 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
232 07:06:51.723156 end: 2.2.2 reset-device (duration 00:00:14) [common]
233 07:06:51.723292 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
234 07:06:51.723415 Setting prompt string to 'Starting depthcharge on Volmar...'
235 07:06:51.723515 Changing prompt to 'Starting depthcharge on Volmar...'
236 07:06:51.723621 depthcharge-start: Wait for prompt Starting depthcharge on Volmar... (timeout 00:05:00)
237 07:06:51.724150 [Enter `^Ec?' for help]
238 07:06:51.724257
239 07:06:51.724356
240 07:06:51.724451 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 bootblock starting (log level: 8)...
241 07:06:51.724539 CPU: 12th Gen Intel(R) Core(TM) i3-1215U
242 07:06:51.724626 CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423
243 07:06:51.724718 CPU: AES supported, TXT NOT supported, VT supported
244 07:06:51.724804 Cache: Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384
245 07:06:51.724894 Cache size = 10 MiB
246 07:06:51.724978 MCH: device id 4609 (rev 04) is Alderlake-P
247 07:06:51.725072 PCH: device id 5182 (rev 01) is Raptorlake-P SKU
248 07:06:51.725157 IGD: device id 46b3 (rev 0c) is Alderlake P GT2
249 07:06:51.725244 VBOOT: Loading verstage.
250 07:06:51.725327 FMAP: Found "FLASH" version 1.1 at 0x1804000.
251 07:06:51.725413 FMAP: base = 0x0 size = 0x2000000 #areas = 37
252 07:06:51.725499 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
253 07:06:51.725582 CBFS: mcache @0xfef85600 built for 72 files, used 0xfd8 of 0x2000 bytes
254 07:06:51.725670 CBFS: Found 'fallback/verstage' @0x18a540 size 0x16ae8 in mcache @0xfef85954
255 07:06:51.725754
256 07:06:51.725842
257 07:06:51.725926 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 verstage starting (log level: 8)...
258 07:06:51.726010 Probing TPM I2C: I2C bus 1 version 0x3230302a
259 07:06:51.726090 DW I2C bus 1 at 0xfe022000 (400 KHz)
260 07:06:51.726176 I2C TX abort detected (00000001)
261 07:06:51.726257 cr50_i2c_read: Address write failed
262 07:06:51.726342 .done! DID_VID 0x00281ae0
263 07:06:51.726429 TPM ready after 0 ms
264 07:06:51.726510 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
265 07:06:51.726589 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
266 07:06:51.726675 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
267 07:06:51.726761 tlcl_send_startup: Startup return code is 0
268 07:06:51.726848 TPM: setup succeeded
269 07:06:51.726933 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
270 07:06:51.727017 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
271 07:06:51.727097 Chrome EC: UHEPI supported
272 07:06:51.727183 Reading cr50 boot mode
273 07:06:51.727267 Cr50 says boot_mode is VERIFIED_RW(0x00).
274 07:06:51.727349 Phase 1
275 07:06:51.727434 FMAP: area GBB found @ 1805000 (458752 bytes)
276 07:06:51.727523 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
277 07:06:51.727604 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
278 07:06:51.727691 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
279 07:06:51.727777 VB2:vb2_check_recovery() Recovery was requested manually
280 07:06:51.727858 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
281 07:06:51.727945 Recovery requested (1009000e)
282 07:06:51.728030 TPM: Extending digest for `VBOOT: boot mode` into PCR 0
283 07:06:51.728111 tlcl_extend: response is 0
284 07:06:51.728194 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured
285 07:06:51.728276 TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1
286 07:06:51.728361 tlcl_extend: response is 0
287 07:06:51.728445 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured
288 07:06:51.728531 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
289 07:06:51.728612 CBFS: Found 'fallback/romstage' @0x80 size 0x1d810 in mcache @0xfef8562c
290 07:06:51.728697 BS: verstage times (exec / console): total (unknown) / 156 ms
291 07:06:51.728782
292 07:06:51.728861
293 07:06:51.728950 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 romstage starting (log level: 8)...
294 07:06:51.729034 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
295 07:06:51.729088 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
296 07:06:51.729143 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
297 07:06:51.729196 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
298 07:06:51.729276 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
299 07:06:51.729356 gpe0_sts[3]: 00000000 gpe0_en[3]: 00080000
300 07:06:51.729435 TCO_STS: 0000 0000
301 07:06:51.729489 GEN_PMCON: d0015038 00002200
302 07:06:51.729540 GBLRST_CAUSE: 00000000 00000000
303 07:06:51.729591 HPR_CAUSE0: 00000000
304 07:06:51.729644 prev_sleep_state 5
305 07:06:51.729694 Abort disabling TXT, as CPU is not TXT capable.
306 07:06:51.729744 cse_lite: Skip switching to RW in the recovery path
307 07:06:51.729798 Boot Count incremented to 12102
308 07:06:51.729883 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
309 07:06:51.729966 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
310 07:06:51.730037 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
311 07:06:51.730090 CBFS: Found 'fspm.bin' @0x7dfc0 size 0xc0000 in mcache @0xfef8589c
312 07:06:51.730147 Chrome EC: UHEPI supported
313 07:06:51.730227 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
314 07:06:51.730311 Probing TPM I2C: done! DID_VID 0x00281ae0
315 07:06:51.730395 Locality already claimed
316 07:06:51.730477 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
317 07:06:51.730564 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
318 07:06:51.730646 MRC: Hash idx 0x100b comparison successful.
319 07:06:51.730726 MRC cache found, size f6c8
320 07:06:51.730804 bootmode is set to: 2
321 07:06:51.730888 EC returned error result code 3
322 07:06:51.730969 FW_CONFIG value from CBI is 0x131
323 07:06:51.731051 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED
324 07:06:51.731105 SPD index = 0
325 07:06:51.731163 CBFS: Found 'spd.bin' @0x78480 size 0x400 in mcache @0xfef857c8
326 07:06:51.731215 SPD: module type is LPDDR4X
327 07:06:51.731264 SPD: module part number is K4U6E3S4AB-MGCL
328 07:06:51.731314 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
329 07:06:51.731565 SPD: device width 16 bits, bus width 16 bits
330 07:06:51.731652 SPD: module size is 1024 MB (per channel)
331 07:06:51.731707 CBMEM:
332 07:06:51.731758 IMD: root @ 0x76fff000 254 entries.
333 07:06:51.731808 IMD: root @ 0x76ffec00 62 entries.
334 07:06:51.731859 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
335 07:06:51.731917 RO_VPD is uninitialized or empty.
336 07:06:51.731967 FMAP: area RW_VPD found @ f29000 (8192 bytes)
337 07:06:51.732054 External stage cache:
338 07:06:51.732135 IMD: root @ 0x7bbff000 254 entries.
339 07:06:51.732210 IMD: root @ 0x7bbfec00 62 entries.
340 07:06:51.732263 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
341 07:06:51.732315 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
342 07:06:51.732365 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
343 07:06:51.732423 MRC: 'RECOVERY_MRC_CACHE' does not need update.
344 07:06:51.732482 8 DIMMs found
345 07:06:51.732569 SMM Memory Map
346 07:06:51.732652 SMRAM : 0x7b800000 0x800000
347 07:06:51.732740 Subregion 0: 0x7b800000 0x200000
348 07:06:51.732819 Subregion 1: 0x7ba00000 0x200000
349 07:06:51.732906 Subregion 2: 0x7bc00000 0x400000
350 07:06:51.732986 top_of_ram = 0x77000000
351 07:06:51.733058 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
352 07:06:51.733110 MTRR Range: Start=7b800000 End=7c000000 (Size 800000)
353 07:06:51.733168 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
354 07:06:51.733219 MTRR Range: Start=ff000000 End=0 (Size 1000000)
355 07:06:51.733269 Normal boot
356 07:06:51.733320 CBFS: Found 'fallback/postcar' @0x185000 size 0x54dc in mcache @0xfef85910
357 07:06:51.733370 Loading module at 0x76aba000 with entry 0x76aba031. filesize: 0x50e8 memsize: 0xa4a0
358 07:06:51.733428 Processing 237 relocs. Offset value of 0x74aba000
359 07:06:51.733494 BS: romstage times (exec / console): total (unknown) / 280 ms
360 07:06:51.733568
361 07:06:51.733649
362 07:06:51.733734 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 postcar starting (log level: 8)...
363 07:06:51.733818 Normal boot
364 07:06:51.733898 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
365 07:06:51.733952 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
366 07:06:51.734003 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
367 07:06:51.734087 CBFS: Found 'fallback/ramstage' @0x52e00 size 0x24b33 in mcache @0x76add10c
368 07:06:51.734183 Loading module at 0x76a30000 with entry 0x76a30000. filesize: 0x51f70 memsize: 0x880d0
369 07:06:51.734266 Processing 5931 relocs. Offset value of 0x72a30000
370 07:06:51.734350 BS: postcar times (exec / console): total (unknown) / 51 ms
371 07:06:51.734433
372 07:06:51.734516
373 07:06:51.734570 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 ramstage starting (log level: 8)...
374 07:06:51.734621 Reserving BERT start 76a1f000, size 10000
375 07:06:51.734688 Normal boot
376 07:06:51.734771 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
377 07:06:51.734853 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
378 07:06:51.734938 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
379 07:06:51.735025 FMAP: area RW_VPD found @ f29000 (8192 bytes)
380 07:06:51.735105 Google Chrome EC: version:
381 07:06:51.735189 ro: volmar_v2.0.14126-e605144e9c
382 07:06:51.735246 rw: volmar_v0.0.55-22d1557
383 07:06:51.735325 running image: 1
384 07:06:51.735408 ACPI _SWS is PM1 Index 8 GPE Index -1
385 07:06:51.735494 BS: BS_PRE_DEVICE entry times (exec / console): 0 / 4 ms
386 07:06:51.735576 EC returned error result code 3
387 07:06:51.735660 FW_CONFIG value from CBI is 0x131
388 07:06:51.735747 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED
389 07:06:51.735829 PCI: 00:1c.2 disabled by fw_config
390 07:06:51.735916 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
391 07:06:51.735997 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
392 07:06:51.736076 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
393 07:06:51.736158 fw_config match found: FPMCU_MASK=FPMCU_ENABLED
394 07:06:51.736237 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
395 07:06:51.736318 CBFS: Found 'cpu_microcode_blob.bin' @0x1d940 size 0x35400 in mcache @0x76add0ac
396 07:06:51.736399 microcode: sig=0x906a4 pf=0x80 revision=0x423
397 07:06:51.736481 microcode: Update skipped, already up-to-date
398 07:06:51.736565 CBFS: Found 'fsps.bin' @0x13e000 size 0x46fb3 in mcache @0x76add2dc
399 07:06:51.736647 Detected 6 core, 8 thread CPU.
400 07:06:51.736732 Setting up SMI for CPU
401 07:06:51.736811 IED base = 0x7bc00000
402 07:06:51.736894 IED size = 0x00400000
403 07:06:51.736974 Will perform SMM setup.
404 07:06:51.737061 CPU: 12th Gen Intel(R) Core(TM) i3-1215U.
405 07:06:51.737150 LAPIC 0x0 in XAPIC mode.
406 07:06:51.737232 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
407 07:06:51.737317 Processing 18 relocs. Offset value of 0x00030000
408 07:06:51.737399 Attempting to start 7 APs
409 07:06:51.737482 Waiting for 10ms after sending INIT.
410 07:06:51.737563 Waiting for SIPI to complete...
411 07:06:51.737647 LAPIC 0x1 in XAPIC mode.
412 07:06:51.737730 done.
413 07:06:51.737809 LAPIC 0x8 in XAPIC mode.
414 07:06:51.737889 LAPIC 0x16 in XAPIC mode.
415 07:06:51.737969 LAPIC 0x12 in XAPIC mode.
416 07:06:51.738047 LAPIC 0x14 in XAPIC mode.
417 07:06:51.738125 AP: slot 2 apic_id 16, MCU rev: 0x00000423
418 07:06:51.738207 AP: slot 4 apic_id 12, MCU rev: 0x00000423
419 07:06:51.738286 LAPIC 0x9 in XAPIC mode.
420 07:06:51.738367 AP: slot 1 apic_id 14, MCU rev: 0x00000423
421 07:06:51.738450 LAPIC 0x10 in XAPIC mode.
422 07:06:51.738534 AP: slot 7 apic_id 9, MCU rev: 0x00000423
423 07:06:51.738616 AP: slot 6 apic_id 8, MCU rev: 0x00000423
424 07:06:51.738698 AP: slot 3 apic_id 10, MCU rev: 0x00000423
425 07:06:51.738971 AP: slot 5 apic_id 1, MCU rev: 0x00000423
426 07:06:51.739059 Waiting for SIPI to complete...
427 07:06:51.739146 done.
428 07:06:51.739227 smm_setup_relocation_handler: enter
429 07:06:51.739306 smm_setup_relocation_handler: exit
430 07:06:51.739387 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x208 memsize: 0x208
431 07:06:51.739470 Processing 11 relocs. Offset value of 0x00038000
432 07:06:51.739554 smm_module_setup_stub: stack_top = 0x7b804000
433 07:06:51.739636 smm_module_setup_stub: per cpu stack_size = 0x800
434 07:06:51.739722 smm_module_setup_stub: runtime.start32_offset = 0x4c
435 07:06:51.739802 smm_module_setup_stub: runtime.smm_size = 0x10000
436 07:06:51.739881 SMM Module: stub loaded at 38000. Will call 0x76a53094
437 07:06:51.739939 Installing permanent SMM handler to 0x7b800000
438 07:06:51.739990 smm_load_module: total_smm_space_needed e468, available -> 200000
439 07:06:51.740041 Loading module at 0x7b9f6000 with entry 0x7b9f6d5f. filesize: 0x4348 memsize: 0x9468
440 07:06:51.740092 Processing 255 relocs. Offset value of 0x7b9f6000
441 07:06:51.740146 smm_load_module: smram_start: 0x7b800000
442 07:06:51.740197 smm_load_module: smram_end: 7ba00000
443 07:06:51.740247 smm_load_module: handler start 0x7b9f6d5f
444 07:06:51.740299 smm_load_module: handler_size 98d0
445 07:06:51.740385 smm_load_module: fxsave_area 0x7b9ff000
446 07:06:51.740467 smm_load_module: fxsave_size 1000
447 07:06:51.740551 smm_load_module: CONFIG_MSEG_SIZE 0x0
448 07:06:51.740631 smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
449 07:06:51.740715 smm_load_module: handler_mod_params.smbase = 0x7b800000
450 07:06:51.740797 smm_load_module: per_cpu_save_state_size = 0x400
451 07:06:51.740878 smm_load_module: num_cpus = 0x8
452 07:06:51.740964 smm_load_module: cbmemc = 0x76ade000, cbmemc_size = 0x20000
453 07:06:51.741064 smm_load_module: total_save_state_size = 0x2000
454 07:06:51.741151 smm_load_module: cpu0 entry: 7b9e6000
455 07:06:51.741232 smm_create_map: cpus allowed in one segment 30
456 07:06:51.741297 smm_create_map: min # of segments needed 1
457 07:06:51.741349 CPU 0x0
458 07:06:51.741406 smbase 7b9e6000 entry 7b9ee000
459 07:06:51.741457 ss_start 7b9f5c00 code_end 7b9ee208
460 07:06:51.741523 CPU 0x1
461 07:06:51.741603 smbase 7b9e5c00 entry 7b9edc00
462 07:06:51.741691 ss_start 7b9f5800 code_end 7b9ede08
463 07:06:51.741776 CPU 0x2
464 07:06:51.741856 smbase 7b9e5800 entry 7b9ed800
465 07:06:51.741928 ss_start 7b9f5400 code_end 7b9eda08
466 07:06:51.741981 CPU 0x3
467 07:06:51.742031 smbase 7b9e5400 entry 7b9ed400
468 07:06:51.742081 ss_start 7b9f5000 code_end 7b9ed608
469 07:06:51.742134 CPU 0x4
470 07:06:51.742217 smbase 7b9e5000 entry 7b9ed000
471 07:06:51.742298 ss_start 7b9f4c00 code_end 7b9ed208
472 07:06:51.742381 CPU 0x5
473 07:06:51.742466 smbase 7b9e4c00 entry 7b9ecc00
474 07:06:51.742545 ss_start 7b9f4800 code_end 7b9ece08
475 07:06:51.742629 CPU 0x6
476 07:06:51.742712 smbase 7b9e4800 entry 7b9ec800
477 07:06:51.742793 ss_start 7b9f4400 code_end 7b9eca08
478 07:06:51.742872 CPU 0x7
479 07:06:51.742954 smbase 7b9e4400 entry 7b9ec400
480 07:06:51.743033 ss_start 7b9f4000 code_end 7b9ec608
481 07:06:51.743113 Loading module at 0x7b9ee000 with entry 0x7b9ee000. filesize: 0x208 memsize: 0x208
482 07:06:51.743199 Processing 11 relocs. Offset value of 0x7b9ee000
483 07:06:51.743279 smm_place_entry_code: smbase 7b9e4400, stack_top 7b804000
484 07:06:51.743358 SMM Module: placing smm entry code at 7b9edc00, cpu # 0x1
485 07:06:51.743441 smm_place_entry_code: copying from 7b9ee000 to 7b9edc00 0x208 bytes
486 07:06:51.743527 SMM Module: placing smm entry code at 7b9ed800, cpu # 0x2
487 07:06:51.743607 smm_place_entry_code: copying from 7b9ee000 to 7b9ed800 0x208 bytes
488 07:06:51.743695 SMM Module: placing smm entry code at 7b9ed400, cpu # 0x3
489 07:06:51.743776 smm_place_entry_code: copying from 7b9ee000 to 7b9ed400 0x208 bytes
490 07:06:51.743859 SMM Module: placing smm entry code at 7b9ed000, cpu # 0x4
491 07:06:51.743944 smm_place_entry_code: copying from 7b9ee000 to 7b9ed000 0x208 bytes
492 07:06:51.744029 SMM Module: placing smm entry code at 7b9ecc00, cpu # 0x5
493 07:06:51.744112 smm_place_entry_code: copying from 7b9ee000 to 7b9ecc00 0x208 bytes
494 07:06:51.744197 SMM Module: placing smm entry code at 7b9ec800, cpu # 0x6
495 07:06:51.744284 smm_place_entry_code: copying from 7b9ee000 to 7b9ec800 0x208 bytes
496 07:06:51.744363 SMM Module: placing smm entry code at 7b9ec400, cpu # 0x7
497 07:06:51.744447 smm_place_entry_code: copying from 7b9ee000 to 7b9ec400 0x208 bytes
498 07:06:51.744526 smm_module_setup_stub: stack_top = 0x7b804000
499 07:06:51.744605 smm_module_setup_stub: per cpu stack_size = 0x800
500 07:06:51.744688 smm_module_setup_stub: runtime.start32_offset = 0x4c
501 07:06:51.744773 smm_module_setup_stub: runtime.smm_size = 0x200000
502 07:06:51.744853 SMM Module: stub loaded at 7b9ee000. Will call 0x7b9f6d5f
503 07:06:51.744937 Clearing SMI status registers
504 07:06:51.745024 SMI_STS: PM1
505 07:06:51.745107 PM1_STS: PWRBTN
506 07:06:51.745194 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e6000, cpu = 0
507 07:06:51.745256 In relocation handler: CPU 0
508 07:06:51.745308 New SMBASE=0x7b9e6000 IEDBASE=0x7bc00000
509 07:06:51.745363 Writing SMRR. base = 0x7b800006, mask=0xff800c00
510 07:06:51.745450 Relocation complete.
511 07:06:51.745534 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4c00, cpu = 5
512 07:06:51.745619 In relocation handler: CPU 5
513 07:06:51.745703 New SMBASE=0x7b9e4c00 IEDBASE=0x7bc00000
514 07:06:51.745789 Relocation complete.
515 07:06:51.746079 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5400, cpu = 3
516 07:06:51.746172 In relocation handler: CPU 3
517 07:06:51.746262 New SMBASE=0x7b9e5400 IEDBASE=0x7bc00000
518 07:06:51.746347 Writing SMRR. base = 0x7b800006, mask=0xff800c00
519 07:06:51.746429 Relocation complete.
520 07:06:51.746510 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5000, cpu = 4
521 07:06:51.746589 In relocation handler: CPU 4
522 07:06:51.746677 New SMBASE=0x7b9e5000 IEDBASE=0x7bc00000
523 07:06:51.746758 Writing SMRR. base = 0x7b800006, mask=0xff800c00
524 07:06:51.746840 Relocation complete.
525 07:06:51.746925 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5c00, cpu = 1
526 07:06:51.747010 In relocation handler: CPU 1
527 07:06:51.747092 New SMBASE=0x7b9e5c00 IEDBASE=0x7bc00000
528 07:06:51.747176 Writing SMRR. base = 0x7b800006, mask=0xff800c00
529 07:06:51.747254 Relocation complete.
530 07:06:51.747338 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5800, cpu = 2
531 07:06:51.747422 In relocation handler: CPU 2
532 07:06:51.747504 New SMBASE=0x7b9e5800 IEDBASE=0x7bc00000
533 07:06:51.747591 Writing SMRR. base = 0x7b800006, mask=0xff800c00
534 07:06:51.747674 Relocation complete.
535 07:06:51.747760 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4400, cpu = 7
536 07:06:51.747840 In relocation handler: CPU 7
537 07:06:51.747922 New SMBASE=0x7b9e4400 IEDBASE=0x7bc00000
538 07:06:51.748006 Relocation complete.
539 07:06:51.748090 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4800, cpu = 6
540 07:06:51.748176 In relocation handler: CPU 6
541 07:06:51.748257 New SMBASE=0x7b9e4800 IEDBASE=0x7bc00000
542 07:06:51.748341 Writing SMRR. base = 0x7b800006, mask=0xff800c00
543 07:06:51.748427 Relocation complete.
544 07:06:51.748506 Initializing CPU #0
545 07:06:51.748584 CPU: vendor Intel device 906a4
546 07:06:51.748670 CPU: family 06, model 9a, stepping 04
547 07:06:51.748750 Clearing out pending MCEs
548 07:06:51.748833 cpu: energy policy set to 7
549 07:06:51.748921 Turbo is available but hidden
550 07:06:51.749002 Turbo is available and visible
551 07:06:51.749097 microcode: Update skipped, already up-to-date
552 07:06:51.749180 CPU #0 initialized
553 07:06:51.749259 Initializing CPU #5
554 07:06:51.749337 Initializing CPU #1
555 07:06:51.749418 Initializing CPU #4
556 07:06:51.749495 Initializing CPU #3
557 07:06:51.749573 CPU: vendor Intel device 906a4
558 07:06:51.749653 CPU: family 06, model 9a, stepping 04
559 07:06:51.749732 Initializing CPU #2
560 07:06:51.749810 CPU: vendor Intel device 906a4
561 07:06:51.749894 CPU: family 06, model 9a, stepping 04
562 07:06:51.749974 Clearing out pending MCEs
563 07:06:51.750057 Clearing out pending MCEs
564 07:06:51.750143 CPU: vendor Intel device 906a4
565 07:06:51.750224 CPU: family 06, model 9a, stepping 04
566 07:06:51.750292 CPU: vendor Intel device 906a4
567 07:06:51.750344 CPU: family 06, model 9a, stepping 04
568 07:06:51.750426 cpu: energy policy set to 7
569 07:06:51.750505 CPU: vendor Intel device 906a4
570 07:06:51.750585 CPU: family 06, model 9a, stepping 04
571 07:06:51.750668 Clearing out pending MCEs
572 07:06:51.750752 Clearing out pending MCEs
573 07:06:51.750833 microcode: Update skipped, already up-to-date
574 07:06:51.750914 CPU #3 initialized
575 07:06:51.750976 cpu: energy policy set to 7
576 07:06:51.751057 cpu: energy policy set to 7
577 07:06:51.751138 cpu: energy policy set to 7
578 07:06:51.751223 microcode: Update skipped, already up-to-date
579 07:06:51.751302 CPU #4 initialized
580 07:06:51.751362 microcode: Update skipped, already up-to-date
581 07:06:51.751419 CPU #1 initialized
582 07:06:51.751470 microcode: Update skipped, already up-to-date
583 07:06:51.751520 CPU #2 initialized
584 07:06:51.751568 Initializing CPU #7
585 07:06:51.751618 Initializing CPU #6
586 07:06:51.751700 Clearing out pending MCEs
587 07:06:51.751779 CPU: vendor Intel device 906a4
588 07:06:51.751862 CPU: family 06, model 9a, stepping 04
589 07:06:51.751946 CPU: vendor Intel device 906a4
590 07:06:51.752030 CPU: family 06, model 9a, stepping 04
591 07:06:51.752088 cpu: energy policy set to 7
592 07:06:51.752146 Clearing out pending MCEs
593 07:06:51.752230 Clearing out pending MCEs
594 07:06:51.752309 cpu: energy policy set to 7
595 07:06:51.752377 cpu: energy policy set to 7
596 07:06:51.752434 microcode: Update skipped, already up-to-date
597 07:06:51.752485 CPU #6 initialized
598 07:06:51.752535 microcode: Update skipped, already up-to-date
599 07:06:51.752585 CPU #7 initialized
600 07:06:51.752639 microcode: Update skipped, already up-to-date
601 07:06:51.752690 CPU #5 initialized
602 07:06:51.752740 bsp_do_flight_plan done after 688 msecs.
603 07:06:51.752789 CPU: frequency set to 4400 MHz
604 07:06:51.752865 Enabling SMIs.
605 07:06:51.752949 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 379 / 520 ms
606 07:06:51.753039 Probing TPM I2C: done! DID_VID 0x00281ae0
607 07:06:51.753095 Locality already claimed
608 07:06:51.753150 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
609 07:06:51.753201 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
610 07:06:51.753252 Enabling GPIO PM b/c CR50 has long IRQ pulse support
611 07:06:51.753302 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
612 07:06:51.753353 CBFS: Found 'vbt.bin' @0x7d8c0 size 0x4e9 in mcache @0x76add214
613 07:06:51.753410 Found a VBT of 9216 bytes after decompression
614 07:06:51.753462 PCI 1.0, PIN A, using IRQ #16
615 07:06:51.753513 PCI 2.0, PIN A, using IRQ #17
616 07:06:51.753598 PCI 4.0, PIN A, using IRQ #18
617 07:06:51.753681 PCI 5.0, PIN A, using IRQ #16
618 07:06:51.753762 PCI 6.0, PIN A, using IRQ #16
619 07:06:51.753845 PCI 6.2, PIN C, using IRQ #18
620 07:06:51.753930 PCI 7.0, PIN A, using IRQ #19
621 07:06:51.754015 PCI 7.1, PIN B, using IRQ #20
622 07:06:51.754100 PCI 7.2, PIN C, using IRQ #21
623 07:06:51.754187 PCI 7.3, PIN D, using IRQ #22
624 07:06:51.754272 PCI 8.0, PIN A, using IRQ #23
625 07:06:51.754351 PCI D.0, PIN A, using IRQ #17
626 07:06:51.754430 PCI D.1, PIN B, using IRQ #19
627 07:06:51.754483 PCI 10.0, PIN A, using IRQ #24
628 07:06:51.754534 PCI 10.1, PIN B, using IRQ #25
629 07:06:51.754584 PCI 10.6, PIN C, using IRQ #20
630 07:06:51.754633 PCI 10.7, PIN D, using IRQ #21
631 07:06:51.754892 PCI 11.0, PIN A, using IRQ #26
632 07:06:51.754980 PCI 11.1, PIN B, using IRQ #27
633 07:06:51.755062 PCI 11.2, PIN C, using IRQ #28
634 07:06:51.755147 PCI 11.3, PIN D, using IRQ #29
635 07:06:51.755207 PCI 12.0, PIN A, using IRQ #30
636 07:06:51.755260 PCI 12.6, PIN B, using IRQ #31
637 07:06:51.755345 PCI 12.7, PIN C, using IRQ #22
638 07:06:51.755427 PCI 13.0, PIN A, using IRQ #32
639 07:06:51.755498 PCI 13.1, PIN B, using IRQ #33
640 07:06:51.755550 PCI 13.2, PIN C, using IRQ #34
641 07:06:51.755600 PCI 13.3, PIN D, using IRQ #35
642 07:06:51.755658 PCI 14.0, PIN B, using IRQ #23
643 07:06:51.755737 PCI 14.1, PIN A, using IRQ #36
644 07:06:51.755815 PCI 14.3, PIN C, using IRQ #17
645 07:06:51.755894 PCI 15.0, PIN A, using IRQ #37
646 07:06:51.755973 PCI 15.1, PIN B, using IRQ #38
647 07:06:51.756056 PCI 15.2, PIN C, using IRQ #39
648 07:06:51.756138 PCI 15.3, PIN D, using IRQ #40
649 07:06:51.756222 PCI 16.0, PIN A, using IRQ #18
650 07:06:51.756307 PCI 16.1, PIN B, using IRQ #19
651 07:06:51.756386 PCI 16.2, PIN C, using IRQ #20
652 07:06:51.756466 PCI 16.3, PIN D, using IRQ #21
653 07:06:51.756543 PCI 16.4, PIN A, using IRQ #18
654 07:06:51.756621 PCI 16.5, PIN B, using IRQ #19
655 07:06:51.756702 PCI 17.0, PIN A, using IRQ #22
656 07:06:51.756784 PCI 19.0, PIN A, using IRQ #41
657 07:06:51.756862 PCI 19.1, PIN B, using IRQ #42
658 07:06:51.756946 PCI 19.2, PIN C, using IRQ #43
659 07:06:51.757044 PCI 1C.0, PIN A, using IRQ #16
660 07:06:51.757128 PCI 1C.1, PIN B, using IRQ #17
661 07:06:51.757211 PCI 1C.2, PIN C, using IRQ #18
662 07:06:51.757294 PCI 1C.3, PIN D, using IRQ #19
663 07:06:51.757378 PCI 1C.4, PIN A, using IRQ #16
664 07:06:51.757461 PCI 1C.5, PIN B, using IRQ #17
665 07:06:51.757529 PCI 1C.6, PIN C, using IRQ #18
666 07:06:51.757580 PCI 1C.7, PIN D, using IRQ #19
667 07:06:51.757630 PCI 1D.0, PIN A, using IRQ #16
668 07:06:51.757711 PCI 1D.1, PIN B, using IRQ #17
669 07:06:51.757789 PCI 1D.2, PIN C, using IRQ #18
670 07:06:51.757867 PCI 1D.3, PIN D, using IRQ #19
671 07:06:51.757954 PCI 1E.0, PIN A, using IRQ #23
672 07:06:51.758024 PCI 1E.1, PIN B, using IRQ #20
673 07:06:51.758104 PCI 1E.2, PIN C, using IRQ #44
674 07:06:51.758189 PCI 1E.3, PIN D, using IRQ #45
675 07:06:51.758277 PCI 1F.3, PIN B, using IRQ #22
676 07:06:51.758366 PCI 1F.4, PIN C, using IRQ #23
677 07:06:51.758450 PCI 1F.6, PIN D, using IRQ #20
678 07:06:51.758520 PCI 1F.7, PIN A, using IRQ #21
679 07:06:51.758573 IRQ: Using dynamically assigned PCI IO-APIC IRQs
680 07:06:51.758644 WEAK: src/soc/intel/alderlake/fsp_params.c/mainboard_silicon_init_params called
681 07:06:51.758726 FSPS returned 0
682 07:06:51.758811 Executing Phase 1 of FspMultiPhaseSiInit
683 07:06:51.758896 FSP MultiPhaseSiInit src/soc/intel/alderlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
684 07:06:51.758981 port C0 DISC req: usage 1 usb3 1 usb2 1
685 07:06:51.759043 Raw Buffer output 0 00000111
686 07:06:51.759094 Raw Buffer output 1 00000000
687 07:06:51.759177 pmc_send_ipc_cmd succeeded
688 07:06:51.759256 port C1 DISC req: usage 1 usb3 3 usb2 3
689 07:06:51.759334 Raw Buffer output 0 00000331
690 07:06:51.759391 Raw Buffer output 1 00000000
691 07:06:51.759471 pmc_send_ipc_cmd succeeded
692 07:06:51.759549 Detected 6 core, 8 thread CPU.
693 07:06:51.759627 Detected 6 core, 8 thread CPU.
694 07:06:51.759708 Detected 6 core, 8 thread CPU.
695 07:06:51.759787 Detected 6 core, 8 thread CPU.
696 07:06:51.759865 Detected 6 core, 8 thread CPU.
697 07:06:51.759949 Detected 6 core, 8 thread CPU.
698 07:06:51.760040 Detected 6 core, 8 thread CPU.
699 07:06:51.760125 Detected 6 core, 8 thread CPU.
700 07:06:51.760207 Detected 6 core, 8 thread CPU.
701 07:06:51.760290 Detected 6 core, 8 thread CPU.
702 07:06:51.760369 Detected 6 core, 8 thread CPU.
703 07:06:51.760452 Detected 6 core, 8 thread CPU.
704 07:06:51.760536 Detected 6 core, 8 thread CPU.
705 07:06:51.760615 Detected 6 core, 8 thread CPU.
706 07:06:51.760701 Detected 6 core, 8 thread CPU.
707 07:06:51.760780 Detected 6 core, 8 thread CPU.
708 07:06:51.760862 Detected 6 core, 8 thread CPU.
709 07:06:51.760950 Detected 6 core, 8 thread CPU.
710 07:06:51.761036 Detected 6 core, 8 thread CPU.
711 07:06:51.761118 Detected 6 core, 8 thread CPU.
712 07:06:51.761205 Detected 6 core, 8 thread CPU.
713 07:06:51.761284 Detected 6 core, 8 thread CPU.
714 07:06:51.761361 Detected 6 core, 8 thread CPU.
715 07:06:51.761445 Detected 6 core, 8 thread CPU.
716 07:06:51.761523 Detected 6 core, 8 thread CPU.
717 07:06:51.761602 Detected 6 core, 8 thread CPU.
718 07:06:51.761686 Detected 6 core, 8 thread CPU.
719 07:06:51.761766 Detected 6 core, 8 thread CPU.
720 07:06:51.761847 Detected 6 core, 8 thread CPU.
721 07:06:51.761931 Detected 6 core, 8 thread CPU.
722 07:06:51.762010 Detected 6 core, 8 thread CPU.
723 07:06:51.762100 Detected 6 core, 8 thread CPU.
724 07:06:51.762183 Detected 6 core, 8 thread CPU.
725 07:06:51.762267 Detected 6 core, 8 thread CPU.
726 07:06:51.762347 Detected 6 core, 8 thread CPU.
727 07:06:51.762431 Detected 6 core, 8 thread CPU.
728 07:06:51.762512 Detected 6 core, 8 thread CPU.
729 07:06:51.762589 Detected 6 core, 8 thread CPU.
730 07:06:51.762664 Detected 6 core, 8 thread CPU.
731 07:06:51.762717 Detected 6 core, 8 thread CPU.
732 07:06:51.762767 Detected 6 core, 8 thread CPU.
733 07:06:51.762816 Detected 6 core, 8 thread CPU.
734 07:06:51.762866 Display FSP Version Info HOB
735 07:06:51.762928 Reference Code - CPU = c.0.65.70
736 07:06:51.763011 uCode Version = 0.0.4.23
737 07:06:51.763090 TXT ACM version = ff.ff.ff.ffff
738 07:06:51.763177 Reference Code - ME = c.0.65.70
739 07:06:51.763256 MEBx version = 0.0.0.0
740 07:06:51.763338 ME Firmware Version = Consumer SKU
741 07:06:51.763423 Reference Code - PCH = c.0.65.70
742 07:06:51.763502 PCH-CRID Status = Disabled
743 07:06:51.763586 PCH-CRID Original Value = ff.ff.ff.ffff
744 07:06:51.763645 PCH-CRID New Value = ff.ff.ff.ffff
745 07:06:51.763698 OPROM - RST - RAID = ff.ff.ff.ffff
746 07:06:51.763749 PCH Hsio Version = 4.0.0.0
747 07:06:51.763798 Reference Code - SA - System Agent = c.0.65.70
748 07:06:51.763848 Reference Code - MRC = 0.0.3.80
749 07:06:51.763905 SA - PCIe Version = c.0.65.70
750 07:06:51.763956 SA-CRID Status = Disabled
751 07:06:51.764005 SA-CRID Original Value = 0.0.0.4
752 07:06:51.764055 SA-CRID New Value = 0.0.0.4
753 07:06:51.764137 OPROM - VBIOS = ff.ff.ff.ffff
754 07:06:51.764424 IO Manageability Engine FW Version = 24.0.4.0
755 07:06:51.764518 PHY Build Version = 0.0.0.2016
756 07:06:51.764599 Thunderbolt(TM) FW Version = 0.0.0.0
757 07:06:51.764682 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
758 07:06:51.764770 BS: BS_DEV_INIT_CHIPS run times (exec / console): 463 / 507 ms
759 07:06:51.764851 Enumerating buses...
760 07:06:51.764939 Show all devs... Before device enumeration.
761 07:06:51.765027 Root Device: enabled 1
762 07:06:51.765112 CPU_CLUSTER: 0: enabled 1
763 07:06:51.765199 DOMAIN: 0000: enabled 1
764 07:06:51.765280 GPIO: 0: enabled 1
765 07:06:51.765361 PCI: 00:00.0: enabled 1
766 07:06:51.765449 PCI: 00:01.0: enabled 0
767 07:06:51.765527 PCI: 00:01.1: enabled 0
768 07:06:51.765605 PCI: 00:02.0: enabled 1
769 07:06:51.765686 PCI: 00:04.0: enabled 1
770 07:06:51.765764 PCI: 00:05.0: enabled 0
771 07:06:51.765847 PCI: 00:06.0: enabled 1
772 07:06:51.765930 PCI: 00:06.2: enabled 0
773 07:06:51.766014 PCI: 00:07.0: enabled 0
774 07:06:51.766097 PCI: 00:07.1: enabled 0
775 07:06:51.766186 PCI: 00:07.2: enabled 0
776 07:06:51.766266 PCI: 00:07.3: enabled 0
777 07:06:51.766348 PCI: 00:08.0: enabled 0
778 07:06:51.766430 PCI: 00:09.0: enabled 0
779 07:06:51.766513 PCI: 00:0a.0: enabled 1
780 07:06:51.766594 PCI: 00:0d.0: enabled 1
781 07:06:51.766679 PCI: 00:0d.1: enabled 0
782 07:06:51.766764 PCI: 00:0d.2: enabled 0
783 07:06:51.766842 PCI: 00:0d.3: enabled 0
784 07:06:51.766923 PCI: 00:0e.0: enabled 0
785 07:06:51.767001 PCI: 00:10.0: enabled 0
786 07:06:51.767078 PCI: 00:10.1: enabled 0
787 07:06:51.767158 PCI: 00:10.6: enabled 0
788 07:06:51.767240 PCI: 00:10.7: enabled 0
789 07:06:51.767319 PCI: 00:12.0: enabled 0
790 07:06:51.767403 PCI: 00:12.6: enabled 0
791 07:06:51.767487 PCI: 00:12.7: enabled 0
792 07:06:51.767567 PCI: 00:13.0: enabled 0
793 07:06:51.767651 PCI: 00:14.0: enabled 1
794 07:06:51.767731 PCI: 00:14.1: enabled 0
795 07:06:51.767814 PCI: 00:14.2: enabled 1
796 07:06:51.767895 PCI: 00:14.3: enabled 1
797 07:06:51.767975 PCI: 00:15.0: enabled 1
798 07:06:51.768054 PCI: 00:15.1: enabled 1
799 07:06:51.768132 PCI: 00:15.2: enabled 0
800 07:06:51.768218 PCI: 00:15.3: enabled 1
801 07:06:51.768296 PCI: 00:16.0: enabled 1
802 07:06:51.768379 PCI: 00:16.1: enabled 0
803 07:06:51.768461 PCI: 00:16.2: enabled 0
804 07:06:51.768539 PCI: 00:16.3: enabled 0
805 07:06:51.768616 PCI: 00:16.4: enabled 0
806 07:06:51.768697 PCI: 00:16.5: enabled 0
807 07:06:51.768775 PCI: 00:17.0: enabled 1
808 07:06:51.768852 PCI: 00:19.0: enabled 0
809 07:06:51.768936 PCI: 00:19.1: enabled 1
810 07:06:51.769020 PCI: 00:19.2: enabled 0
811 07:06:51.769112 PCI: 00:1a.0: enabled 0
812 07:06:51.769195 PCI: 00:1c.0: enabled 0
813 07:06:51.769275 PCI: 00:1c.1: enabled 0
814 07:06:51.769358 PCI: 00:1c.2: enabled 0
815 07:06:51.769441 PCI: 00:1c.3: enabled 0
816 07:06:51.769526 PCI: 00:1c.4: enabled 0
817 07:06:51.769605 PCI: 00:1c.5: enabled 0
818 07:06:51.769683 PCI: 00:1c.6: enabled 0
819 07:06:51.769737 PCI: 00:1c.7: enabled 0
820 07:06:51.769787 PCI: 00:1d.0: enabled 0
821 07:06:51.769836 PCI: 00:1d.1: enabled 0
822 07:06:51.769890 PCI: 00:1d.2: enabled 0
823 07:06:51.769969 PCI: 00:1d.3: enabled 0
824 07:06:51.770052 PCI: 00:1e.0: enabled 1
825 07:06:51.770133 PCI: 00:1e.1: enabled 0
826 07:06:51.770214 PCI: 00:1e.2: enabled 0
827 07:06:51.770267 PCI: 00:1e.3: enabled 1
828 07:06:51.770317 PCI: 00:1f.0: enabled 1
829 07:06:51.770366 PCI: 00:1f.1: enabled 0
830 07:06:51.770423 PCI: 00:1f.2: enabled 1
831 07:06:51.770474 PCI: 00:1f.3: enabled 1
832 07:06:51.770523 PCI: 00:1f.4: enabled 0
833 07:06:51.770573 PCI: 00:1f.5: enabled 1
834 07:06:51.770622 PCI: 00:1f.6: enabled 0
835 07:06:51.770678 PCI: 00:1f.7: enabled 0
836 07:06:51.770728 GENERIC: 0.0: enabled 1
837 07:06:51.770778 GENERIC: 0.0: enabled 1
838 07:06:51.770827 GENERIC: 1.0: enabled 1
839 07:06:51.770901 GENERIC: 0.0: enabled 1
840 07:06:51.770980 GENERIC: 1.0: enabled 1
841 07:06:51.771061 USB0 port 0: enabled 1
842 07:06:51.771116 USB0 port 0: enabled 1
843 07:06:51.771173 GENERIC: 0.0: enabled 1
844 07:06:51.771224 I2C: 00:1a: enabled 1
845 07:06:51.771273 I2C: 00:31: enabled 1
846 07:06:51.771322 I2C: 00:32: enabled 1
847 07:06:51.771370 I2C: 00:50: enabled 1
848 07:06:51.771426 I2C: 00:10: enabled 1
849 07:06:51.771476 I2C: 00:15: enabled 1
850 07:06:51.771525 I2C: 00:2c: enabled 1
851 07:06:51.771574 GENERIC: 0.0: enabled 1
852 07:06:51.771626 SPI: 00: enabled 1
853 07:06:51.771711 PNP: 0c09.0: enabled 1
854 07:06:51.771790 GENERIC: 0.0: enabled 1
855 07:06:51.771873 USB3 port 0: enabled 1
856 07:06:51.771955 USB3 port 1: enabled 0
857 07:06:51.772036 USB3 port 2: enabled 1
858 07:06:51.772100 USB3 port 3: enabled 0
859 07:06:51.772172 USB2 port 0: enabled 1
860 07:06:51.772252 USB2 port 1: enabled 0
861 07:06:51.772336 USB2 port 2: enabled 1
862 07:06:51.772421 USB2 port 3: enabled 0
863 07:06:51.772502 USB2 port 4: enabled 0
864 07:06:51.772569 USB2 port 5: enabled 1
865 07:06:51.772620 USB2 port 6: enabled 0
866 07:06:51.772678 USB2 port 7: enabled 0
867 07:06:51.772728 USB2 port 8: enabled 1
868 07:06:51.772776 USB2 port 9: enabled 1
869 07:06:51.772826 USB3 port 0: enabled 1
870 07:06:51.772878 USB3 port 1: enabled 0
871 07:06:51.772964 USB3 port 2: enabled 0
872 07:06:51.773058 USB3 port 3: enabled 0
873 07:06:51.773114 GENERIC: 0.0: enabled 1
874 07:06:51.773188 GENERIC: 1.0: enabled 1
875 07:06:51.773266 APIC: 00: enabled 1
876 07:06:51.773344 APIC: 14: enabled 1
877 07:06:51.773425 APIC: 16: enabled 1
878 07:06:51.773502 APIC: 10: enabled 1
879 07:06:51.773585 APIC: 12: enabled 1
880 07:06:51.773669 APIC: 01: enabled 1
881 07:06:51.773751 APIC: 08: enabled 1
882 07:06:51.773836 APIC: 09: enabled 1
883 07:06:51.773919 Compare with tree...
884 07:06:51.774001 Root Device: enabled 1
885 07:06:51.774085 CPU_CLUSTER: 0: enabled 1
886 07:06:51.774177 APIC: 00: enabled 1
887 07:06:51.774268 APIC: 14: enabled 1
888 07:06:51.774349 APIC: 16: enabled 1
889 07:06:51.774431 APIC: 10: enabled 1
890 07:06:51.774510 APIC: 12: enabled 1
891 07:06:51.774588 APIC: 01: enabled 1
892 07:06:51.774664 APIC: 08: enabled 1
893 07:06:51.774716 APIC: 09: enabled 1
894 07:06:51.774766 DOMAIN: 0000: enabled 1
895 07:06:51.774816 GPIO: 0: enabled 1
896 07:06:51.774866 PCI: 00:00.0: enabled 1
897 07:06:51.774923 PCI: 00:01.0: enabled 0
898 07:06:51.774973 PCI: 00:01.1: enabled 0
899 07:06:51.775022 PCI: 00:02.0: enabled 1
900 07:06:51.775071 PCI: 00:04.0: enabled 1
901 07:06:51.775120 GENERIC: 0.0: enabled 1
902 07:06:51.775176 PCI: 00:05.0: enabled 0
903 07:06:51.775226 PCI: 00:06.0: enabled 1
904 07:06:51.775276 PCI: 00:06.2: enabled 0
905 07:06:51.775325 PCI: 00:08.0: enabled 0
906 07:06:51.775375 PCI: 00:09.0: enabled 0
907 07:06:51.775429 PCI: 00:0a.0: enabled 1
908 07:06:51.775479 PCI: 00:0d.0: enabled 1
909 07:06:51.775528 USB0 port 0: enabled 1
910 07:06:51.775576 USB3 port 0: enabled 1
911 07:06:51.775625 USB3 port 1: enabled 0
912 07:06:51.775680 USB3 port 2: enabled 1
913 07:06:51.775730 USB3 port 3: enabled 0
914 07:06:51.775793 PCI: 00:0d.1: enabled 0
915 07:06:51.776050 PCI: 00:0d.2: enabled 0
916 07:06:51.776110 PCI: 00:0d.3: enabled 0
917 07:06:51.776168 PCI: 00:0e.0: enabled 0
918 07:06:51.776218 PCI: 00:10.0: enabled 0
919 07:06:51.776268 PCI: 00:10.1: enabled 0
920 07:06:51.776318 PCI: 00:10.6: enabled 0
921 07:06:51.776367 PCI: 00:10.7: enabled 0
922 07:06:51.776424 PCI: 00:12.0: enabled 0
923 07:06:51.776474 PCI: 00:12.6: enabled 0
924 07:06:51.776523 PCI: 00:12.7: enabled 0
925 07:06:51.776573 PCI: 00:13.0: enabled 0
926 07:06:51.776622 PCI: 00:14.0: enabled 1
927 07:06:51.776678 USB0 port 0: enabled 1
928 07:06:51.776728 USB2 port 0: enabled 1
929 07:06:51.776777 USB2 port 1: enabled 0
930 07:06:51.776826 USB2 port 2: enabled 1
931 07:06:51.776876 USB2 port 3: enabled 0
932 07:06:51.776956 USB2 port 4: enabled 0
933 07:06:51.777039 USB2 port 5: enabled 1
934 07:06:51.777092 USB2 port 6: enabled 0
935 07:06:51.777145 USB2 port 7: enabled 0
936 07:06:51.777196 USB2 port 8: enabled 1
937 07:06:51.777246 USB2 port 9: enabled 1
938 07:06:51.777296 USB3 port 0: enabled 1
939 07:06:51.777346 USB3 port 1: enabled 0
940 07:06:51.777395 USB3 port 2: enabled 0
941 07:06:51.777448 USB3 port 3: enabled 0
942 07:06:51.777499 PCI: 00:14.1: enabled 0
943 07:06:51.777547 PCI: 00:14.2: enabled 1
944 07:06:51.777596 PCI: 00:14.3: enabled 1
945 07:06:51.777645 GENERIC: 0.0: enabled 1
946 07:06:51.777701 PCI: 00:15.0: enabled 1
947 07:06:51.777751 I2C: 00:1a: enabled 1
948 07:06:51.777801 I2C: 00:31: enabled 1
949 07:06:51.777850 I2C: 00:32: enabled 1
950 07:06:51.777900 PCI: 00:15.1: enabled 1
951 07:06:51.777957 I2C: 00:50: enabled 1
952 07:06:51.778007 PCI: 00:15.2: enabled 0
953 07:06:51.778056 PCI: 00:15.3: enabled 1
954 07:06:51.778106 I2C: 00:10: enabled 1
955 07:06:51.778155 PCI: 00:16.0: enabled 1
956 07:06:51.778210 PCI: 00:16.1: enabled 0
957 07:06:51.778260 PCI: 00:16.2: enabled 0
958 07:06:51.778310 PCI: 00:16.3: enabled 0
959 07:06:51.778359 PCI: 00:16.4: enabled 0
960 07:06:51.778411 PCI: 00:16.5: enabled 0
961 07:06:51.778462 PCI: 00:17.0: enabled 1
962 07:06:51.778511 PCI: 00:19.0: enabled 0
963 07:06:51.778559 PCI: 00:19.1: enabled 1
964 07:06:51.778609 I2C: 00:15: enabled 1
965 07:06:51.778662 I2C: 00:2c: enabled 1
966 07:06:51.778713 PCI: 00:19.2: enabled 0
967 07:06:51.778763 PCI: 00:1a.0: enabled 0
968 07:06:51.778811 PCI: 00:1e.0: enabled 1
969 07:06:51.778860 PCI: 00:1e.1: enabled 0
970 07:06:51.778916 PCI: 00:1e.2: enabled 0
971 07:06:51.778967 PCI: 00:1e.3: enabled 1
972 07:06:51.779016 SPI: 00: enabled 1
973 07:06:51.779065 PCI: 00:1f.0: enabled 1
974 07:06:51.779114 PNP: 0c09.0: enabled 1
975 07:06:51.779185 PCI: 00:1f.1: enabled 0
976 07:06:51.779263 PCI: 00:1f.2: enabled 1
977 07:06:51.779341 GENERIC: 0.0: enabled 1
978 07:06:51.779424 GENERIC: 0.0: enabled 1
979 07:06:51.779503 GENERIC: 1.0: enabled 1
980 07:06:51.779580 PCI: 00:1f.3: enabled 1
981 07:06:51.779657 PCI: 00:1f.4: enabled 0
982 07:06:51.779738 PCI: 00:1f.5: enabled 1
983 07:06:51.779816 PCI: 00:1f.6: enabled 0
984 07:06:51.779893 PCI: 00:1f.7: enabled 0
985 07:06:51.779972 Root Device scanning...
986 07:06:51.780052 scan_static_bus for Root Device
987 07:06:51.780129 CPU_CLUSTER: 0 enabled
988 07:06:51.780208 DOMAIN: 0000 enabled
989 07:06:51.780288 DOMAIN: 0000 scanning...
990 07:06:51.780365 PCI: pci_scan_bus for bus 00
991 07:06:51.780443 PCI: 00:00.0 [8086/0000] ops
992 07:06:51.780524 PCI: 00:00.0 [8086/4609] enabled
993 07:06:51.780601 PCI: 00:02.0 [8086/0000] bus ops
994 07:06:51.780679 PCI: 00:02.0 [8086/46b3] enabled
995 07:06:51.780759 PCI: 00:04.0 [8086/0000] bus ops
996 07:06:51.780837 PCI: 00:04.0 [8086/461d] enabled
997 07:06:51.780915 PCI: 00:06.0 [8086/0000] bus ops
998 07:06:51.780996 PCI: 00:06.0 [8086/464d] enabled
999 07:06:51.781082 PCI: 00:08.0 [8086/464f] disabled
1000 07:06:51.781161 PCI: 00:0a.0 [8086/467d] enabled
1001 07:06:51.781240 PCI: 00:0d.0 [8086/0000] bus ops
1002 07:06:51.781319 PCI: 00:0d.0 [8086/461e] enabled
1003 07:06:51.781396 PCI: 00:14.0 [8086/0000] bus ops
1004 07:06:51.781474 PCI: 00:14.0 [8086/51ed] enabled
1005 07:06:51.781555 PCI: 00:14.2 [8086/51ef] enabled
1006 07:06:51.781633 PCI: 00:14.3 [8086/0000] bus ops
1007 07:06:51.781710 PCI: 00:14.3 [8086/51f0] enabled
1008 07:06:51.781787 PCI: 00:15.0 [8086/0000] bus ops
1009 07:06:51.781868 PCI: 00:15.0 [8086/51e8] enabled
1010 07:06:51.781947 PCI: 00:15.1 [8086/0000] bus ops
1011 07:06:51.782025 PCI: 00:15.1 [8086/51e9] enabled
1012 07:06:51.782107 PCI: 00:15.2 [8086/0000] bus ops
1013 07:06:51.782185 PCI: 00:15.2 [8086/51ea] disabled
1014 07:06:51.782263 PCI: 00:15.3 [8086/0000] bus ops
1015 07:06:51.782345 PCI: 00:15.3 [8086/51eb] enabled
1016 07:06:51.782423 PCI: 00:16.0 [8086/0000] ops
1017 07:06:51.782502 PCI: 00:16.0 [8086/51e0] enabled
1018 07:06:51.782580 PCI: Static device PCI: 00:17.0 not found, disabling it.
1019 07:06:51.782662 PCI: 00:19.0 [8086/0000] bus ops
1020 07:06:51.782740 PCI: 00:19.0 [8086/51c5] disabled
1021 07:06:51.782818 PCI: 00:19.1 [8086/0000] bus ops
1022 07:06:51.782900 PCI: 00:19.1 [8086/51c6] enabled
1023 07:06:51.782979 PCI: 00:1e.0 [8086/0000] ops
1024 07:06:51.783057 PCI: 00:1e.0 [8086/51a8] enabled
1025 07:06:51.783135 PCI: 00:1e.3 [8086/0000] bus ops
1026 07:06:51.783216 PCI: 00:1e.3 [8086/51ab] enabled
1027 07:06:51.783294 PCI: 00:1f.0 [8086/0000] bus ops
1028 07:06:51.783371 PCI: 00:1f.0 [8086/5182] enabled
1029 07:06:51.783451 RTC Init
1030 07:06:51.783529 Set power on after power failure.
1031 07:06:51.783607 Disabling Deep S3
1032 07:06:51.783688 Disabling Deep S3
1033 07:06:51.783766 Disabling Deep S4
1034 07:06:51.783843 Disabling Deep S4
1035 07:06:51.783923 Disabling Deep S5
1036 07:06:51.784001 Disabling Deep S5
1037 07:06:51.784078 PCI: 00:1f.2 [0000/0000] hidden
1038 07:06:51.784158 PCI: 00:1f.3 [8086/0000] bus ops
1039 07:06:51.784237 PCI: 00:1f.3 [8086/51c8] enabled
1040 07:06:51.784315 PCI: 00:1f.5 [8086/0000] bus ops
1041 07:06:51.784395 PCI: 00:1f.5 [8086/51a4] enabled
1042 07:06:51.784473 GPIO: 0 enabled
1043 07:06:51.784551 PCI: Leftover static devices:
1044 07:06:51.784632 PCI: 00:01.0
1045 07:06:51.784714 PCI: 00:01.1
1046 07:06:51.784792 PCI: 00:05.0
1047 07:06:51.784868 PCI: 00:06.2
1048 07:06:51.784949 PCI: 00:09.0
1049 07:06:51.785031 PCI: 00:0d.1
1050 07:06:51.785108 PCI: 00:0d.2
1051 07:06:51.785174 PCI: 00:0d.3
1052 07:06:51.785225 PCI: 00:0e.0
1053 07:06:51.785275 PCI: 00:10.0
1054 07:06:51.785325 PCI: 00:10.1
1055 07:06:51.785374 PCI: 00:10.6
1056 07:06:51.785429 PCI: 00:10.7
1057 07:06:51.785478 PCI: 00:12.0
1058 07:06:51.785527 PCI: 00:12.6
1059 07:06:51.785576 PCI: 00:12.7
1060 07:06:51.785624 PCI: 00:13.0
1061 07:06:51.785678 PCI: 00:14.1
1062 07:06:51.785727 PCI: 00:16.1
1063 07:06:51.785776 PCI: 00:16.2
1064 07:06:51.785825 PCI: 00:16.3
1065 07:06:51.785874 PCI: 00:16.4
1066 07:06:51.785928 PCI: 00:16.5
1067 07:06:51.785977 PCI: 00:17.0
1068 07:06:51.786025 PCI: 00:19.2
1069 07:06:51.786271 PCI: 00:1a.0
1070 07:06:51.786327 PCI: 00:1e.1
1071 07:06:51.786376 PCI: 00:1e.2
1072 07:06:51.786432 PCI: 00:1f.1
1073 07:06:51.786481 PCI: 00:1f.4
1074 07:06:51.786529 PCI: 00:1f.6
1075 07:06:51.786577 PCI: 00:1f.7
1076 07:06:51.786627 PCI: Check your devicetree.cb.
1077 07:06:51.786681 PCI: 00:02.0 scanning...
1078 07:06:51.786731 scan_generic_bus for PCI: 00:02.0
1079 07:06:51.786780 scan_generic_bus for PCI: 00:02.0 done
1080 07:06:51.786829 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
1081 07:06:51.786880 PCI: 00:04.0 scanning...
1082 07:06:51.786935 scan_generic_bus for PCI: 00:04.0
1083 07:06:51.786985 GENERIC: 0.0 enabled
1084 07:06:51.787034 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
1085 07:06:51.787084 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
1086 07:06:51.787137 PCI: 00:06.0 scanning...
1087 07:06:51.787189 do_pci_scan_bridge for PCI: 00:06.0
1088 07:06:51.787238 PCI: pci_scan_bus for bus 01
1089 07:06:51.787287 PCI: 01:00.0 [15b7/5009] enabled
1090 07:06:51.787337 Enabling Common Clock Configuration
1091 07:06:51.787389 L1 Sub-State supported from root port 6
1092 07:06:51.787441 L1 Sub-State Support = 0x5
1093 07:06:51.787491 CommonModeRestoreTime = 0x6e
1094 07:06:51.787540 Power On Value = 0x5, Power On Scale = 0x2
1095 07:06:51.787590 ASPM: Enabled L1
1096 07:06:51.787644 PCIe: Max_Payload_Size adjusted to 256
1097 07:06:51.787694 PCI: 01:00.0: Enabled LTR
1098 07:06:51.787743 PCI: 01:00.0: Programmed LTR max latencies
1099 07:06:51.787792 scan_bus: bus PCI: 00:06.0 finished in 40 msecs
1100 07:06:51.787842 PCI: 00:0d.0 scanning...
1101 07:06:51.787896 scan_static_bus for PCI: 00:0d.0
1102 07:06:51.787947 USB0 port 0 enabled
1103 07:06:51.787996 USB0 port 0 scanning...
1104 07:06:51.788046 scan_static_bus for USB0 port 0
1105 07:06:51.788095 USB3 port 0 enabled
1106 07:06:51.788148 USB3 port 1 disabled
1107 07:06:51.788198 USB3 port 2 enabled
1108 07:06:51.788247 USB3 port 3 disabled
1109 07:06:51.788296 USB3 port 0 scanning...
1110 07:06:51.788345 scan_static_bus for USB3 port 0
1111 07:06:51.788399 scan_static_bus for USB3 port 0 done
1112 07:06:51.788450 scan_bus: bus USB3 port 0 finished in 6 msecs
1113 07:06:51.788499 USB3 port 2 scanning...
1114 07:06:51.788549 scan_static_bus for USB3 port 2
1115 07:06:51.788598 scan_static_bus for USB3 port 2 done
1116 07:06:51.788651 scan_bus: bus USB3 port 2 finished in 6 msecs
1117 07:06:51.788701 scan_static_bus for USB0 port 0 done
1118 07:06:51.788751 scan_bus: bus USB0 port 0 finished in 43 msecs
1119 07:06:51.788801 scan_static_bus for PCI: 00:0d.0 done
1120 07:06:51.788851 scan_bus: bus PCI: 00:0d.0 finished in 59 msecs
1121 07:06:51.788905 PCI: 00:14.0 scanning...
1122 07:06:51.788956 scan_static_bus for PCI: 00:14.0
1123 07:06:51.789005 USB0 port 0 enabled
1124 07:06:51.789069 USB0 port 0 scanning...
1125 07:06:51.789118 scan_static_bus for USB0 port 0
1126 07:06:51.789175 USB2 port 0 enabled
1127 07:06:51.789224 USB2 port 1 disabled
1128 07:06:51.789273 USB2 port 2 enabled
1129 07:06:51.789323 USB2 port 3 disabled
1130 07:06:51.789372 USB2 port 4 disabled
1131 07:06:51.789426 USB2 port 5 enabled
1132 07:06:51.789476 USB2 port 6 disabled
1133 07:06:51.789524 USB2 port 7 disabled
1134 07:06:51.789573 USB2 port 8 enabled
1135 07:06:51.789622 USB2 port 9 enabled
1136 07:06:51.789677 USB3 port 0 enabled
1137 07:06:51.789727 USB3 port 1 disabled
1138 07:06:51.789776 USB3 port 2 disabled
1139 07:06:51.789825 USB3 port 3 disabled
1140 07:06:51.789875 USB2 port 0 scanning...
1141 07:06:51.789930 scan_static_bus for USB2 port 0
1142 07:06:51.789980 scan_static_bus for USB2 port 0 done
1143 07:06:51.790029 scan_bus: bus USB2 port 0 finished in 6 msecs
1144 07:06:51.790079 USB2 port 2 scanning...
1145 07:06:51.790128 scan_static_bus for USB2 port 2
1146 07:06:51.790182 scan_static_bus for USB2 port 2 done
1147 07:06:51.790261 scan_bus: bus USB2 port 2 finished in 6 msecs
1148 07:06:51.790341 USB2 port 5 scanning...
1149 07:06:51.790427 scan_static_bus for USB2 port 5
1150 07:06:51.790485 scan_static_bus for USB2 port 5 done
1151 07:06:51.790566 scan_bus: bus USB2 port 5 finished in 6 msecs
1152 07:06:51.790647 USB2 port 8 scanning...
1153 07:06:51.790724 scan_static_bus for USB2 port 8
1154 07:06:51.790777 scan_static_bus for USB2 port 8 done
1155 07:06:51.790827 scan_bus: bus USB2 port 8 finished in 6 msecs
1156 07:06:51.790877 USB2 port 9 scanning...
1157 07:06:51.790932 scan_static_bus for USB2 port 9
1158 07:06:51.790981 scan_static_bus for USB2 port 9 done
1159 07:06:51.791031 scan_bus: bus USB2 port 9 finished in 6 msecs
1160 07:06:51.791080 USB3 port 0 scanning...
1161 07:06:51.791146 scan_static_bus for USB3 port 0
1162 07:06:51.791226 scan_static_bus for USB3 port 0 done
1163 07:06:51.791310 scan_bus: bus USB3 port 0 finished in 6 msecs
1164 07:06:51.791368 scan_static_bus for USB0 port 0 done
1165 07:06:51.791426 scan_bus: bus USB0 port 0 finished in 120 msecs
1166 07:06:51.791477 scan_static_bus for PCI: 00:14.0 done
1167 07:06:51.791526 scan_bus: bus PCI: 00:14.0 finished in 136 msecs
1168 07:06:51.791575 PCI: 00:14.3 scanning...
1169 07:06:51.791625 scan_static_bus for PCI: 00:14.3
1170 07:06:51.791680 GENERIC: 0.0 enabled
1171 07:06:51.791730 scan_static_bus for PCI: 00:14.3 done
1172 07:06:51.791780 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1173 07:06:51.791865 PCI: 00:15.0 scanning...
1174 07:06:51.791947 scan_static_bus for PCI: 00:15.0
1175 07:06:51.792031 I2C: 00:1a enabled
1176 07:06:51.792110 I2C: 00:31 enabled
1177 07:06:51.792192 I2C: 00:32 enabled
1178 07:06:51.792245 scan_static_bus for PCI: 00:15.0 done
1179 07:06:51.792296 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1180 07:06:51.792345 PCI: 00:15.1 scanning...
1181 07:06:51.792408 scan_static_bus for PCI: 00:15.1
1182 07:06:51.792493 I2C: 00:50 enabled
1183 07:06:51.792573 scan_static_bus for PCI: 00:15.1 done
1184 07:06:51.792660 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1185 07:06:51.792740 PCI: 00:15.3 scanning...
1186 07:06:51.792821 scan_static_bus for PCI: 00:15.3
1187 07:06:51.792903 I2C: 00:10 enabled
1188 07:06:51.792982 scan_static_bus for PCI: 00:15.3 done
1189 07:06:51.793053 scan_bus: bus PCI: 00:15.3 finished in 9 msecs
1190 07:06:51.793110 PCI: 00:19.1 scanning...
1191 07:06:51.793195 scan_static_bus for PCI: 00:19.1
1192 07:06:51.793275 I2C: 00:15 enabled
1193 07:06:51.793358 I2C: 00:2c enabled
1194 07:06:51.793440 scan_static_bus for PCI: 00:19.1 done
1195 07:06:51.793517 scan_bus: bus PCI: 00:19.1 finished in 11 msecs
1196 07:06:51.793570 PCI: 00:1e.3 scanning...
1197 07:06:51.793619 scan_generic_bus for PCI: 00:1e.3
1198 07:06:51.793676 SPI: 00 enabled
1199 07:06:51.793928 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1200 07:06:51.794019 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1201 07:06:51.794099 PCI: 00:1f.0 scanning...
1202 07:06:51.794185 scan_static_bus for PCI: 00:1f.0
1203 07:06:51.794266 PNP: 0c09.0 enabled
1204 07:06:51.794347 PNP: 0c09.0 scanning...
1205 07:06:51.794420 scan_static_bus for PNP: 0c09.0
1206 07:06:51.794473 scan_static_bus for PNP: 0c09.0 done
1207 07:06:51.794524 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1208 07:06:51.794575 scan_static_bus for PCI: 00:1f.0 done
1209 07:06:51.794625 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1210 07:06:51.794682 PCI: 00:1f.2 scanning...
1211 07:06:51.794731 scan_static_bus for PCI: 00:1f.2
1212 07:06:51.794781 GENERIC: 0.0 enabled
1213 07:06:51.794831 GENERIC: 0.0 scanning...
1214 07:06:51.794880 scan_static_bus for GENERIC: 0.0
1215 07:06:51.794934 GENERIC: 0.0 enabled
1216 07:06:51.794984 GENERIC: 1.0 enabled
1217 07:06:51.795033 scan_static_bus for GENERIC: 0.0 done
1218 07:06:51.795083 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1219 07:06:51.795134 scan_static_bus for PCI: 00:1f.2 done
1220 07:06:51.795187 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1221 07:06:51.795238 PCI: 00:1f.3 scanning...
1222 07:06:51.795309 scan_static_bus for PCI: 00:1f.3
1223 07:06:51.795391 scan_static_bus for PCI: 00:1f.3 done
1224 07:06:51.795474 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1225 07:06:51.795529 PCI: 00:1f.5 scanning...
1226 07:06:51.795579 scan_generic_bus for PCI: 00:1f.5
1227 07:06:51.795628 scan_generic_bus for PCI: 00:1f.5 done
1228 07:06:51.795684 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1229 07:06:51.795733 scan_bus: bus DOMAIN: 0000 finished in 710 msecs
1230 07:06:51.795782 scan_static_bus for Root Device done
1231 07:06:51.795831 scan_bus: bus Root Device finished in 729 msecs
1232 07:06:51.795880 done
1233 07:06:51.795934 BS: BS_DEV_ENUMERATE run times (exec / console): 4 / 1297 ms
1234 07:06:51.795984 Chrome EC: UHEPI supported
1235 07:06:51.796057 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (131072 bytes)
1236 07:06:51.796138 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1237 07:06:51.796223 SPI flash protection: WPSW=0 SRP0=0
1238 07:06:51.796303 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1239 07:06:51.796372 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1240 07:06:51.796428 found VGA at PCI: 00:02.0
1241 07:06:51.796478 Setting up VGA for PCI: 00:02.0
1242 07:06:51.796526 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1243 07:06:51.796575 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1244 07:06:51.796624 Allocating resources...
1245 07:06:51.796678 Reading resources...
1246 07:06:51.796727 Root Device read_resources bus 0 link: 0
1247 07:06:51.796779 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1248 07:06:51.796862 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1249 07:06:51.796945 DOMAIN: 0000 read_resources bus 0 link: 0
1250 07:06:51.797038 SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x20000
1251 07:06:51.797119 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x1000
1252 07:06:51.797196 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x1000
1253 07:06:51.797249 SA MMIO resource: REGBAR -> base = 0xfb000000, size = 0x1000
1254 07:06:51.797298 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x4000
1255 07:06:51.797347 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x80000
1256 07:06:51.797404 SA MMIO resource: TPM -> base = 0xfed40000, size = 0x10000
1257 07:06:51.797460 SA MMIO resource: LT_SECURITY -> base = 0xfed50000, size = 0x20000
1258 07:06:51.797544 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x100000
1259 07:06:51.797624 SA MMIO resource: PCH_RESERVED -> base = 0xfc800000, size = 0x2000000
1260 07:06:51.797696 SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x1000
1261 07:06:51.797760 SA MMIO resource: IPUVTBAR -> base = 0xfed92000, size = 0x1000
1262 07:06:51.797841 SA MMIO resource: TBT0BAR -> base = 0xfed84000, size = 0x1000
1263 07:06:51.797928 SA MMIO resource: TBT1BAR -> base = 0xfed85000, size = 0x1000
1264 07:06:51.798014 SA MMIO resource: TBT2BAR -> base = 0xfed86000, size = 0x1000
1265 07:06:51.798093 SA MMIO resource: TBT3BAR -> base = 0xfed87000, size = 0x1000
1266 07:06:51.798166 SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x1000
1267 07:06:51.798218 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000
1268 07:06:51.798269 SA MMIO resource: DSM -> base = 0x7c800000, size = 0x3c00000
1269 07:06:51.798318 SA MMIO resource: TSEG -> base = 0x7b800000, size = 0x800000
1270 07:06:51.798367 SA MMIO resource: GSM -> base = 0x7c000000, size = 0x800000
1271 07:06:51.798422 PCI: 00:04.0 read_resources bus 1 link: 0
1272 07:06:51.798472 PCI: 00:04.0 read_resources bus 1 link: 0 done
1273 07:06:51.798521 PCI: 00:06.0 read_resources bus 1 link: 0
1274 07:06:51.798570 PCI: 00:06.0 read_resources bus 1 link: 0 done
1275 07:06:51.798652 PCI: 00:0d.0 read_resources bus 0 link: 0
1276 07:06:51.798731 USB0 port 0 read_resources bus 0 link: 0
1277 07:06:51.798808 USB0 port 0 read_resources bus 0 link: 0 done
1278 07:06:51.798861 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1279 07:06:51.798918 PCI: 00:14.0 read_resources bus 0 link: 0
1280 07:06:51.798968 USB0 port 0 read_resources bus 0 link: 0
1281 07:06:51.799017 USB0 port 0 read_resources bus 0 link: 0 done
1282 07:06:51.799066 PCI: 00:14.0 read_resources bus 0 link: 0 done
1283 07:06:51.799114 PCI: 00:14.3 read_resources bus 0 link: 0
1284 07:06:51.799170 PCI: 00:14.3 read_resources bus 0 link: 0 done
1285 07:06:51.799222 PCI: 00:15.0 read_resources bus 0 link: 0
1286 07:06:51.799306 PCI: 00:15.0 read_resources bus 0 link: 0 done
1287 07:06:51.799385 PCI: 00:15.1 read_resources bus 0 link: 0
1288 07:06:51.799664 PCI: 00:15.1 read_resources bus 0 link: 0 done
1289 07:06:51.799725 PCI: 00:15.3 read_resources bus 0 link: 0
1290 07:06:51.799777 PCI: 00:15.3 read_resources bus 0 link: 0 done
1291 07:06:51.799856 PCI: 00:19.1 read_resources bus 0 link: 0
1292 07:06:51.799938 PCI: 00:19.1 read_resources bus 0 link: 0 done
1293 07:06:51.800020 PCI: 00:1e.3 read_resources bus 2 link: 0
1294 07:06:51.800101 PCI: 00:1e.3 read_resources bus 2 link: 0 done
1295 07:06:51.800187 PCI: 00:1f.0 read_resources bus 0 link: 0
1296 07:06:51.800242 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1297 07:06:51.800292 PCI: 00:1f.2 read_resources bus 0 link: 0
1298 07:06:51.800341 GENERIC: 0.0 read_resources bus 0 link: 0
1299 07:06:51.800395 GENERIC: 0.0 read_resources bus 0 link: 0 done
1300 07:06:51.800478 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1301 07:06:51.800556 DOMAIN: 0000 read_resources bus 0 link: 0 done
1302 07:06:51.800641 Root Device read_resources bus 0 link: 0 done
1303 07:06:51.800721 Done reading resources.
1304 07:06:51.800799 Show resources in subtree (Root Device)...After reading.
1305 07:06:51.800877 Root Device child on link 0 CPU_CLUSTER: 0
1306 07:06:51.800959 CPU_CLUSTER: 0 child on link 0 APIC: 00
1307 07:06:51.801059 APIC: 00
1308 07:06:51.801141 APIC: 14
1309 07:06:51.801223 APIC: 16
1310 07:06:51.801301 APIC: 10
1311 07:06:51.801384 APIC: 12
1312 07:06:51.801465 APIC: 01
1313 07:06:51.801542 APIC: 08
1314 07:06:51.801622 APIC: 09
1315 07:06:51.801705 DOMAIN: 0000 child on link 0 GPIO: 0
1316 07:06:51.801786 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1317 07:06:51.801875 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1318 07:06:51.801958 GPIO: 0
1319 07:06:51.802044 PCI: 00:00.0
1320 07:06:51.802125 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0
1321 07:06:51.802212 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1
1322 07:06:51.802293 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1323 07:06:51.802374 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1324 07:06:51.802456 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4
1325 07:06:51.802535 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5
1326 07:06:51.802616 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1327 07:06:51.802703 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
1328 07:06:51.802784 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8
1329 07:06:51.802870 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9
1330 07:06:51.802954 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1331 07:06:51.803035 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1332 07:06:51.803114 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1333 07:06:51.803197 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d
1334 07:06:51.803277 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e
1335 07:06:51.803356 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f
1336 07:06:51.803439 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10
1337 07:06:51.803523 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11
1338 07:06:51.803604 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12
1339 07:06:51.803690 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13
1340 07:06:51.803771 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14
1341 07:06:51.803858 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15
1342 07:06:51.803943 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16
1343 07:06:51.804026 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17
1344 07:06:51.804108 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18
1345 07:06:51.804196 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19
1346 07:06:51.804279 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a
1347 07:06:51.804359 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b
1348 07:06:51.804441 PCI: 00:02.0
1349 07:06:51.804525 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1350 07:06:51.804803 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1351 07:06:51.804891 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1352 07:06:51.804971 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1353 07:06:51.805059 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1354 07:06:51.805111 GENERIC: 0.0
1355 07:06:51.805200 PCI: 00:06.0 child on link 0 PCI: 01:00.0
1356 07:06:51.805282 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1357 07:06:51.805355 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1358 07:06:51.805414 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1359 07:06:51.805465 PCI: 01:00.0
1360 07:06:51.805514 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1361 07:06:51.805565 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1362 07:06:51.805615 PCI: 00:08.0
1363 07:06:51.805670 PCI: 00:0a.0
1364 07:06:51.805720 PCI: 00:0a.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
1365 07:06:51.805770 PCI: 00:0d.0 child on link 0 USB0 port 0
1366 07:06:51.805819 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1367 07:06:51.805868 USB0 port 0 child on link 0 USB3 port 0
1368 07:06:51.805926 USB3 port 0
1369 07:06:51.806010 USB3 port 1
1370 07:06:51.806087 USB3 port 2
1371 07:06:51.806171 USB3 port 3
1372 07:06:51.806250 PCI: 00:14.0 child on link 0 USB0 port 0
1373 07:06:51.806333 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1374 07:06:51.806392 USB0 port 0 child on link 0 USB2 port 0
1375 07:06:51.806445 USB2 port 0
1376 07:06:51.806517 USB2 port 1
1377 07:06:51.806595 USB2 port 2
1378 07:06:51.806679 USB2 port 3
1379 07:06:51.806734 USB2 port 4
1380 07:06:51.806783 USB2 port 5
1381 07:06:51.806832 USB2 port 6
1382 07:06:51.806880 USB2 port 7
1383 07:06:51.806934 USB2 port 8
1384 07:06:51.806983 USB2 port 9
1385 07:06:51.807031 USB3 port 0
1386 07:06:51.807080 USB3 port 1
1387 07:06:51.807128 USB3 port 2
1388 07:06:51.807182 USB3 port 3
1389 07:06:51.807231 PCI: 00:14.2
1390 07:06:51.807280 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1391 07:06:51.807334 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1392 07:06:51.807424 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1393 07:06:51.807504 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1394 07:06:51.807574 GENERIC: 0.0
1395 07:06:51.807624 PCI: 00:15.0 child on link 0 I2C: 00:1a
1396 07:06:51.807679 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1397 07:06:51.807729 I2C: 00:1a
1398 07:06:51.807778 I2C: 00:31
1399 07:06:51.807825 I2C: 00:32
1400 07:06:51.807874 PCI: 00:15.1 child on link 0 I2C: 00:50
1401 07:06:51.807929 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1402 07:06:51.807980 I2C: 00:50
1403 07:06:51.808058 PCI: 00:15.2
1404 07:06:51.808143 PCI: 00:15.3 child on link 0 I2C: 00:10
1405 07:06:51.808225 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1406 07:06:51.808309 I2C: 00:10
1407 07:06:51.808391 PCI: 00:16.0
1408 07:06:51.808474 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1409 07:06:51.808558 PCI: 00:19.0
1410 07:06:51.808639 PCI: 00:19.1 child on link 0 I2C: 00:15
1411 07:06:51.808725 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1412 07:06:51.808804 I2C: 00:15
1413 07:06:51.808885 I2C: 00:2c
1414 07:06:51.808963 PCI: 00:1e.0
1415 07:06:51.809052 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1416 07:06:51.809137 PCI: 00:1e.3 child on link 0 SPI: 00
1417 07:06:51.809219 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1418 07:06:51.809285 SPI: 00
1419 07:06:51.809336 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1420 07:06:51.809391 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1421 07:06:51.809442 PNP: 0c09.0
1422 07:06:51.809491 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1423 07:06:51.809541 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1424 07:06:51.809590 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1425 07:06:51.809648 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1426 07:06:51.809699 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1427 07:06:51.809749 GENERIC: 0.0
1428 07:06:51.809798 GENERIC: 1.0
1429 07:06:51.809848 PCI: 00:1f.3
1430 07:06:51.809930 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1431 07:06:51.810013 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1432 07:06:51.810096 PCI: 00:1f.5
1433 07:06:51.810374 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1434 07:06:51.810460 === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1435 07:06:51.810550 PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff
1436 07:06:51.810633 PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1437 07:06:51.810715 PCI: 00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1438 07:06:51.810795 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1439 07:06:51.810881 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1440 07:06:51.810964 PCI: 00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1441 07:06:51.811048 PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1442 07:06:51.811132 PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1443 07:06:51.811214 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1444 07:06:51.811303 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1445 07:06:51.811386 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1446 07:06:51.811466 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1447 07:06:51.811545 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1448 07:06:51.811626 DOMAIN: 0000: Resource ranges:
1449 07:06:51.811704 * Base: 1000, Size: 800, Tag: 100
1450 07:06:51.811786 * Base: 1900, Size: e700, Tag: 100
1451 07:06:51.811868 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1452 07:06:51.811954 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1453 07:06:51.812036 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1454 07:06:51.812119 update_constraints: PCI: 00:00.0 00 base fedc0000 limit feddffff mem (fixed)
1455 07:06:51.812207 update_constraints: PCI: 00:00.0 01 base feda0000 limit feda0fff mem (fixed)
1456 07:06:51.812287 update_constraints: PCI: 00:00.0 02 base feda1000 limit feda1fff mem (fixed)
1457 07:06:51.812371 update_constraints: PCI: 00:00.0 03 base fb000000 limit fb000fff mem (fixed)
1458 07:06:51.812455 update_constraints: PCI: 00:00.0 04 base fed80000 limit fed83fff mem (fixed)
1459 07:06:51.812537 update_constraints: PCI: 00:00.0 05 base feb00000 limit feb7ffff mem (fixed)
1460 07:06:51.812624 update_constraints: PCI: 00:00.0 06 base fed40000 limit fed4ffff mem (fixed)
1461 07:06:51.812679 update_constraints: PCI: 00:00.0 07 base fed50000 limit fed6ffff mem (fixed)
1462 07:06:51.812729 update_constraints: PCI: 00:00.0 08 base fec00000 limit fecfffff mem (fixed)
1463 07:06:51.812779 update_constraints: PCI: 00:00.0 09 base fc800000 limit fe7fffff mem (fixed)
1464 07:06:51.812851 update_constraints: PCI: 00:00.0 0a base fed90000 limit fed90fff mem (fixed)
1465 07:06:51.812930 update_constraints: PCI: 00:00.0 0b base fed92000 limit fed92fff mem (fixed)
1466 07:06:51.813009 update_constraints: PCI: 00:00.0 0c base fed84000 limit fed84fff mem (fixed)
1467 07:06:51.813078 update_constraints: PCI: 00:00.0 0d base fed85000 limit fed85fff mem (fixed)
1468 07:06:51.813130 update_constraints: PCI: 00:00.0 0e base fed86000 limit fed86fff mem (fixed)
1469 07:06:51.813180 update_constraints: PCI: 00:00.0 0f base fed87000 limit fed87fff mem (fixed)
1470 07:06:51.813229 update_constraints: PCI: 00:00.0 10 base fed91000 limit fed91fff mem (fixed)
1471 07:06:51.813278 update_constraints: PCI: 00:00.0 11 base c0000000 limit cfffffff mem (fixed)
1472 07:06:51.813359 update_constraints: PCI: 00:00.0 12 base 7c800000 limit 803fffff mem (fixed)
1473 07:06:51.813440 update_constraints: PCI: 00:00.0 13 base 7b800000 limit 7bffffff mem (fixed)
1474 07:06:51.813524 update_constraints: PCI: 00:00.0 14 base 7c000000 limit 7c7fffff mem (fixed)
1475 07:06:51.813609 update_constraints: PCI: 00:00.0 15 base 00000000 limit 0009ffff mem (fixed)
1476 07:06:51.813704 update_constraints: PCI: 00:00.0 16 base 000c0000 limit 76ffffff mem (fixed)
1477 07:06:51.813795 update_constraints: PCI: 00:00.0 17 base 77000000 limit 803fffff mem (fixed)
1478 07:06:51.813881 update_constraints: PCI: 00:00.0 18 base 100000000 limit 27fbfffff mem (fixed)
1479 07:06:51.813950 update_constraints: PCI: 00:00.0 19 base 000a0000 limit 000bffff mem (fixed)
1480 07:06:51.814001 update_constraints: PCI: 00:00.0 1a base 000c0000 limit 000fffff mem (fixed)
1481 07:06:51.814050 update_constraints: PCI: 00:00.0 1b base f8000000 limit f9ffffff mem (fixed)
1482 07:06:51.814101 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1483 07:06:51.814157 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1484 07:06:51.814207 DOMAIN: 0000: Resource ranges:
1485 07:06:51.814256 * Base: 80400000, Size: 3fc00000, Tag: 200
1486 07:06:51.814324 * Base: d0000000, Size: 28000000, Tag: 200
1487 07:06:51.814407 * Base: fa000000, Size: 1000000, Tag: 200
1488 07:06:51.814491 * Base: fb001000, Size: 17ff000, Tag: 200
1489 07:06:51.814573 * Base: fe800000, Size: 300000, Tag: 200
1490 07:06:51.814656 * Base: feb80000, Size: 80000, Tag: 200
1491 07:06:51.814720 * Base: fed00000, Size: 40000, Tag: 200
1492 07:06:51.814770 * Base: fed70000, Size: 10000, Tag: 200
1493 07:06:51.815024 * Base: fed88000, Size: 8000, Tag: 200
1494 07:06:51.815087 * Base: fed93000, Size: d000, Tag: 200
1495 07:06:51.815139 * Base: feda2000, Size: 1e000, Tag: 200
1496 07:06:51.815189 * Base: fede0000, Size: 1220000, Tag: 200
1497 07:06:51.815238 * Base: 27fc00000, Size: 7d80400000, Tag: 100200
1498 07:06:51.815287 PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
1499 07:06:51.815341 PCI: 00:02.0 10 * [0x81000000 - 0x81ffffff] limit: 81ffffff mem
1500 07:06:51.815393 PCI: 00:06.0 20 * [0x80400000 - 0x804fffff] limit: 804fffff mem
1501 07:06:51.815443 PCI: 00:1f.3 20 * [0x80500000 - 0x805fffff] limit: 805fffff mem
1502 07:06:51.815493 PCI: 00:04.0 10 * [0x80600000 - 0x8061ffff] limit: 8061ffff mem
1503 07:06:51.815574 PCI: 00:0d.0 10 * [0x80620000 - 0x8062ffff] limit: 8062ffff mem
1504 07:06:51.815655 PCI: 00:14.0 10 * [0x80630000 - 0x8063ffff] limit: 8063ffff mem
1505 07:06:51.815732 PCI: 00:0a.0 10 * [0x80640000 - 0x80647fff] limit: 80647fff mem
1506 07:06:51.815784 PCI: 00:14.2 10 * [0x80648000 - 0x8064bfff] limit: 8064bfff mem
1507 07:06:51.815840 PCI: 00:14.3 10 * [0x8064c000 - 0x8064ffff] limit: 8064ffff mem
1508 07:06:51.815890 PCI: 00:1f.3 10 * [0x80650000 - 0x80653fff] limit: 80653fff mem
1509 07:06:51.815940 PCI: 00:14.2 18 * [0x80654000 - 0x80654fff] limit: 80654fff mem
1510 07:06:51.815990 PCI: 00:15.0 10 * [0x80655000 - 0x80655fff] limit: 80655fff mem
1511 07:06:51.816039 PCI: 00:15.1 10 * [0x80656000 - 0x80656fff] limit: 80656fff mem
1512 07:06:51.816107 PCI: 00:15.3 10 * [0x80657000 - 0x80657fff] limit: 80657fff mem
1513 07:06:51.816193 PCI: 00:16.0 10 * [0x80658000 - 0x80658fff] limit: 80658fff mem
1514 07:06:51.816274 PCI: 00:19.1 10 * [0x80659000 - 0x80659fff] limit: 80659fff mem
1515 07:06:51.816359 PCI: 00:1e.3 10 * [0x8065a000 - 0x8065afff] limit: 8065afff mem
1516 07:06:51.816446 PCI: 00:1f.5 10 * [0x8065b000 - 0x8065bfff] limit: 8065bfff mem
1517 07:06:51.816526 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1518 07:06:51.816612 PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff
1519 07:06:51.816691 PCI: 00:06.0: Resource ranges:
1520 07:06:51.816769 * Base: 80400000, Size: 100000, Tag: 200
1521 07:06:51.816855 PCI: 01:00.0 10 * [0x80400000 - 0x80403fff] limit: 80403fff mem
1522 07:06:51.816935 PCI: 01:00.0 20 * [0x80404000 - 0x804040ff] limit: 804040ff mem
1523 07:06:51.817026 PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff done
1524 07:06:51.817112 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1525 07:06:51.817197 Root Device assign_resources, bus 0 link: 0
1526 07:06:51.817283 DOMAIN: 0000 assign_resources, bus 0 link: 0
1527 07:06:51.817367 PCI: 00:02.0 10 <- [0x0081000000 - 0x0081ffffff] size 0x01000000 gran 0x18 mem64
1528 07:06:51.817450 PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
1529 07:06:51.817536 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1530 07:06:51.817620 PCI: 00:04.0 10 <- [0x0080600000 - 0x008061ffff] size 0x00020000 gran 0x11 mem64
1531 07:06:51.817699 PCI: 00:04.0 assign_resources, bus 1 link: 0
1532 07:06:51.817780 PCI: 00:04.0 assign_resources, bus 1 link: 0 done
1533 07:06:51.817860 PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1534 07:06:51.817939 PCI: 00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1535 07:06:51.818021 PCI: 00:06.0 20 <- [0x0080400000 - 0x00804fffff] size 0x00100000 gran 0x14 bus 01 mem
1536 07:06:51.818100 PCI: 00:06.0 assign_resources, bus 1 link: 0
1537 07:06:51.818183 PCI: 01:00.0 10 <- [0x0080400000 - 0x0080403fff] size 0x00004000 gran 0x0e mem64
1538 07:06:51.818265 PCI: 01:00.0 20 <- [0x0080404000 - 0x00804040ff] size 0x00000100 gran 0x08 mem64
1539 07:06:51.818350 PCI: 00:06.0 assign_resources, bus 1 link: 0 done
1540 07:06:51.818432 PCI: 00:0a.0 10 <- [0x0080640000 - 0x0080647fff] size 0x00008000 gran 0x0f mem64
1541 07:06:51.818514 PCI: 00:0d.0 10 <- [0x0080620000 - 0x008062ffff] size 0x00010000 gran 0x10 mem64
1542 07:06:51.818600 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1543 07:06:51.818680 PCI: 00:0d.0 assign_resources, bus 0 link: 0 done
1544 07:06:51.818765 PCI: 00:14.0 10 <- [0x0080630000 - 0x008063ffff] size 0x00010000 gran 0x10 mem64
1545 07:06:51.818846 PCI: 00:14.0 assign_resources, bus 0 link: 0
1546 07:06:51.818925 PCI: 00:14.0 assign_resources, bus 0 link: 0 done
1547 07:06:51.819004 PCI: 00:14.2 10 <- [0x0080648000 - 0x008064bfff] size 0x00004000 gran 0x0e mem64
1548 07:06:51.819087 PCI: 00:14.2 18 <- [0x0080654000 - 0x0080654fff] size 0x00001000 gran 0x0c mem64
1549 07:06:51.819166 PCI: 00:14.3 10 <- [0x008064c000 - 0x008064ffff] size 0x00004000 gran 0x0e mem64
1550 07:06:51.819244 PCI: 00:14.3 assign_resources, bus 0 link: 0
1551 07:06:51.819326 PCI: 00:14.3 assign_resources, bus 0 link: 0 done
1552 07:06:51.819411 PCI: 00:15.0 10 <- [0x0080655000 - 0x0080655fff] size 0x00001000 gran 0x0c mem64
1553 07:06:51.819489 PCI: 00:15.0 assign_resources, bus 0 link: 0
1554 07:06:51.819572 PCI: 00:15.0 assign_resources, bus 0 link: 0 done
1555 07:06:51.819851 PCI: 00:15.1 10 <- [0x0080656000 - 0x0080656fff] size 0x00001000 gran 0x0c mem64
1556 07:06:51.819956 PCI: 00:15.1 assign_resources, bus 0 link: 0
1557 07:06:51.820054 PCI: 00:15.1 assign_resources, bus 0 link: 0 done
1558 07:06:51.820140 PCI: 00:15.3 10 <- [0x0080657000 - 0x0080657fff] size 0x00001000 gran 0x0c mem64
1559 07:06:51.820222 PCI: 00:15.3 assign_resources, bus 0 link: 0
1560 07:06:51.820314 PCI: 00:15.3 assign_resources, bus 0 link: 0 done
1561 07:06:51.820396 PCI: 00:16.0 10 <- [0x0080658000 - 0x0080658fff] size 0x00001000 gran 0x0c mem64
1562 07:06:51.820476 PCI: 00:19.1 10 <- [0x0080659000 - 0x0080659fff] size 0x00001000 gran 0x0c mem64
1563 07:06:51.820569 PCI: 00:19.1 assign_resources, bus 0 link: 0
1564 07:06:51.820653 PCI: 00:19.1 assign_resources, bus 0 link: 0 done
1565 07:06:51.820737 PCI: 00:1e.3 10 <- [0x008065a000 - 0x008065afff] size 0x00001000 gran 0x0c mem64
1566 07:06:51.820827 PCI: 00:1e.3 assign_resources, bus 2 link: 0
1567 07:06:51.820905 PCI: 00:1e.3 assign_resources, bus 2 link: 0 done
1568 07:06:51.820983 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1569 07:06:51.821080 PCI: 00:1f.0 assign_resources, bus 0 link: 0 done
1570 07:06:51.821158 LPC: Trying to open IO window from 800 size 1ff
1571 07:06:51.821237 PCI: 00:1f.3 10 <- [0x0080650000 - 0x0080653fff] size 0x00004000 gran 0x0e mem64
1572 07:06:51.821335 PCI: 00:1f.3 20 <- [0x0080500000 - 0x00805fffff] size 0x00100000 gran 0x14 mem64
1573 07:06:51.821416 PCI: 00:1f.5 10 <- [0x008065b000 - 0x008065bfff] size 0x00001000 gran 0x0c mem
1574 07:06:51.821503 DOMAIN: 0000 assign_resources, bus 0 link: 0 done
1575 07:06:51.821598 Root Device assign_resources, bus 0 link: 0 done
1576 07:06:51.821677 Done setting resources.
1577 07:06:51.821759 Show resources in subtree (Root Device)...After assigning values.
1578 07:06:51.821851 Root Device child on link 0 CPU_CLUSTER: 0
1579 07:06:51.821929 CPU_CLUSTER: 0 child on link 0 APIC: 00
1580 07:06:51.822006 APIC: 00
1581 07:06:51.822093 APIC: 14
1582 07:06:51.822170 APIC: 16
1583 07:06:51.822246 APIC: 10
1584 07:06:51.822323 APIC: 12
1585 07:06:51.822409 APIC: 01
1586 07:06:51.822486 APIC: 08
1587 07:06:51.822568 APIC: 09
1588 07:06:51.822657 DOMAIN: 0000 child on link 0 GPIO: 0
1589 07:06:51.822737 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1590 07:06:51.822816 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1591 07:06:51.822888 GPIO: 0
1592 07:06:51.822938 PCI: 00:00.0
1593 07:06:51.822987 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0
1594 07:06:51.823037 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1
1595 07:06:51.823086 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1596 07:06:51.823173 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1597 07:06:51.823259 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4
1598 07:06:51.823339 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5
1599 07:06:51.823429 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1600 07:06:51.823509 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
1601 07:06:51.823588 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8
1602 07:06:51.823678 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9
1603 07:06:51.823758 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1604 07:06:51.823848 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1605 07:06:51.823941 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1606 07:06:51.824021 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d
1607 07:06:51.824102 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e
1608 07:06:51.824167 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f
1609 07:06:51.824217 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10
1610 07:06:51.824266 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11
1611 07:06:51.824316 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12
1612 07:06:51.824396 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13
1613 07:06:51.824481 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14
1614 07:06:51.824561 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15
1615 07:06:51.824641 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16
1616 07:06:51.824935 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17
1617 07:06:51.825026 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18
1618 07:06:51.825082 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19
1619 07:06:51.825139 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a
1620 07:06:51.825215 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b
1621 07:06:51.825266 PCI: 00:02.0
1622 07:06:51.825316 PCI: 00:02.0 resource base 81000000 size 1000000 align 24 gran 24 limit 81ffffff flags 60000201 index 10
1623 07:06:51.825365 PCI: 00:02.0 resource base 90000000 size 10000000 align 28 gran 28 limit 9fffffff flags 60001201 index 18
1624 07:06:51.825427 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1625 07:06:51.825510 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1626 07:06:51.825589 PCI: 00:04.0 resource base 80600000 size 20000 align 17 gran 17 limit 8061ffff flags 60000201 index 10
1627 07:06:51.825666 GENERIC: 0.0
1628 07:06:51.825754 PCI: 00:06.0 child on link 0 PCI: 01:00.0
1629 07:06:51.825834 PCI: 00:06.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1630 07:06:51.825915 PCI: 00:06.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1631 07:06:51.826006 PCI: 00:06.0 resource base 80400000 size 100000 align 20 gran 20 limit 804fffff flags 60080202 index 20
1632 07:06:51.826085 PCI: 01:00.0
1633 07:06:51.826164 PCI: 01:00.0 resource base 80400000 size 4000 align 14 gran 14 limit 80403fff flags 60000201 index 10
1634 07:06:51.826252 PCI: 01:00.0 resource base 80404000 size 100 align 12 gran 8 limit 804040ff flags 60000201 index 20
1635 07:06:51.826355 PCI: 00:08.0
1636 07:06:51.826434 PCI: 00:0a.0
1637 07:06:51.826512 PCI: 00:0a.0 resource base 80640000 size 8000 align 15 gran 15 limit 80647fff flags 60000201 index 10
1638 07:06:51.826610 PCI: 00:0d.0 child on link 0 USB0 port 0
1639 07:06:51.826691 PCI: 00:0d.0 resource base 80620000 size 10000 align 16 gran 16 limit 8062ffff flags 60000201 index 10
1640 07:06:51.826773 USB0 port 0 child on link 0 USB3 port 0
1641 07:06:51.826850 USB3 port 0
1642 07:06:51.826941 USB3 port 1
1643 07:06:51.827022 USB3 port 2
1644 07:06:51.827102 USB3 port 3
1645 07:06:51.827187 PCI: 00:14.0 child on link 0 USB0 port 0
1646 07:06:51.827267 PCI: 00:14.0 resource base 80630000 size 10000 align 16 gran 16 limit 8063ffff flags 60000201 index 10
1647 07:06:51.827361 USB0 port 0 child on link 0 USB2 port 0
1648 07:06:51.827449 USB2 port 0
1649 07:06:51.827527 USB2 port 1
1650 07:06:51.827613 USB2 port 2
1651 07:06:51.827702 USB2 port 3
1652 07:06:51.827783 USB2 port 4
1653 07:06:51.827862 USB2 port 5
1654 07:06:51.827950 USB2 port 6
1655 07:06:51.828029 USB2 port 7
1656 07:06:51.828086 USB2 port 8
1657 07:06:51.828175 USB2 port 9
1658 07:06:51.828258 USB3 port 0
1659 07:06:51.828334 USB3 port 1
1660 07:06:51.828420 USB3 port 2
1661 07:06:51.828498 USB3 port 3
1662 07:06:51.828574 PCI: 00:14.2
1663 07:06:51.828652 PCI: 00:14.2 resource base 80648000 size 4000 align 14 gran 14 limit 8064bfff flags 60000201 index 10
1664 07:06:51.828745 PCI: 00:14.2 resource base 80654000 size 1000 align 12 gran 12 limit 80654fff flags 60000201 index 18
1665 07:06:51.828827 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1666 07:06:51.828906 PCI: 00:14.3 resource base 8064c000 size 4000 align 14 gran 14 limit 8064ffff flags 60000201 index 10
1667 07:06:51.828994 GENERIC: 0.0
1668 07:06:51.829080 PCI: 00:15.0 child on link 0 I2C: 00:1a
1669 07:06:51.829160 PCI: 00:15.0 resource base 80655000 size 1000 align 12 gran 12 limit 80655fff flags 60000201 index 10
1670 07:06:51.829247 I2C: 00:1a
1671 07:06:51.829325 I2C: 00:31
1672 07:06:51.829403 I2C: 00:32
1673 07:06:51.829498 PCI: 00:15.1 child on link 0 I2C: 00:50
1674 07:06:51.829578 PCI: 00:15.1 resource base 80656000 size 1000 align 12 gran 12 limit 80656fff flags 60000201 index 10
1675 07:06:51.829655 I2C: 00:50
1676 07:06:51.829732 PCI: 00:15.2
1677 07:06:51.829784 PCI: 00:15.3 child on link 0 I2C: 00:10
1678 07:06:51.829833 PCI: 00:15.3 resource base 80657000 size 1000 align 12 gran 12 limit 80657fff flags 60000201 index 10
1679 07:06:51.829882 I2C: 00:10
1680 07:06:51.829930 PCI: 00:16.0
1681 07:06:51.830025 PCI: 00:16.0 resource base 80658000 size 1000 align 12 gran 12 limit 80658fff flags 60000201 index 10
1682 07:06:51.830111 PCI: 00:19.0
1683 07:06:51.830198 PCI: 00:19.1 child on link 0 I2C: 00:15
1684 07:06:51.830289 PCI: 00:19.1 resource base 80659000 size 1000 align 12 gran 12 limit 80659fff flags 60000201 index 10
1685 07:06:51.830366 I2C: 00:15
1686 07:06:51.830447 I2C: 00:2c
1687 07:06:51.830529 PCI: 00:1e.0
1688 07:06:51.830610 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1689 07:06:51.830694 PCI: 00:1e.3 child on link 0 SPI: 00
1690 07:06:51.830784 PCI: 00:1e.3 resource base 8065a000 size 1000 align 12 gran 12 limit 8065afff flags 60000201 index 10
1691 07:06:51.830862 SPI: 00
1692 07:06:51.830944 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1693 07:06:51.831029 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1694 07:06:51.831106 PNP: 0c09.0
1695 07:06:51.831374 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1696 07:06:51.831464 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1697 07:06:51.831561 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1698 07:06:51.831658 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1699 07:06:51.831744 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1700 07:06:51.831821 GENERIC: 0.0
1701 07:06:51.831906 GENERIC: 1.0
1702 07:06:51.831983 PCI: 00:1f.3
1703 07:06:51.832052 PCI: 00:1f.3 resource base 80650000 size 4000 align 14 gran 14 limit 80653fff flags 60000201 index 10
1704 07:06:51.832115 PCI: 00:1f.3 resource base 80500000 size 100000 align 20 gran 20 limit 805fffff flags 60000201 index 20
1705 07:06:51.832168 PCI: 00:1f.5
1706 07:06:51.832217 PCI: 00:1f.5 resource base 8065b000 size 1000 align 12 gran 12 limit 8065bfff flags 60000200 index 10
1707 07:06:51.832267 Done allocating resources.
1708 07:06:51.832316 BS: BS_DEV_RESOURCES run times (exec / console): 2 / 2717 ms
1709 07:06:51.832365 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
1710 07:06:51.832414 Configure audio over I2S with MAX98373 NAU88L25B.
1711 07:06:51.832495 Enabling BT offload
1712 07:06:51.832581 BS: BS_DEV_ENABLE entry times (exec / console): 5 / 12 ms
1713 07:06:51.832659 Enabling resources...
1714 07:06:51.832740 PCI: 00:00.0 subsystem <- 8086/4609
1715 07:06:51.832817 PCI: 00:00.0 cmd <- 06
1716 07:06:51.832894 PCI: 00:02.0 subsystem <- 8086/46b3
1717 07:06:51.832976 PCI: 00:02.0 cmd <- 03
1718 07:06:51.833066 PCI: 00:04.0 subsystem <- 8086/461d
1719 07:06:51.833143 PCI: 00:04.0 cmd <- 02
1720 07:06:51.833220 PCI: 00:06.0 bridge ctrl <- 0013
1721 07:06:51.833299 PCI: 00:06.0 subsystem <- 8086/464d
1722 07:06:51.833376 PCI: 00:06.0 cmd <- 106
1723 07:06:51.833453 PCI: 00:0a.0 subsystem <- 8086/467d
1724 07:06:51.833529 PCI: 00:0a.0 cmd <- 02
1725 07:06:51.833614 PCI: 00:0d.0 subsystem <- 8086/461e
1726 07:06:51.833695 PCI: 00:0d.0 cmd <- 02
1727 07:06:51.833773 PCI: 00:14.0 subsystem <- 8086/51ed
1728 07:06:51.833847 PCI: 00:14.0 cmd <- 02
1729 07:06:51.833897 PCI: 00:14.2 subsystem <- 8086/51ef
1730 07:06:51.833945 PCI: 00:14.2 cmd <- 02
1731 07:06:51.833994 PCI: 00:14.3 subsystem <- 8086/51f0
1732 07:06:51.834054 PCI: 00:14.3 cmd <- 02
1733 07:06:51.963762 PCI: 00:15.0 subsystem <- 8086/51e8
1734 07:06:51.963896 PCI: 00:15.0 cmd <- 02
1735 07:06:51.963991 PCI: 00:15.1 subsystem <- 8086/51e9
1736 07:06:51.964078 PCI: 00:15.1 cmd <- 06
1737 07:06:51.964159 PCI: 00:15.3 subsystem <- 8086/51eb
1738 07:06:51.964242 PCI: 00:15.3 cmd <- 02
1739 07:06:51.964326 PCI: 00:16.0 subsystem <- 8086/51e0
1740 07:06:51.964408 PCI: 00:16.0 cmd <- 02
1741 07:06:51.964489 PCI: 00:19.1 subsystem <- 8086/51c6
1742 07:06:51.964571 PCI: 00:19.1 cmd <- 02
1743 07:06:51.964650 PCI: 00:1e.0 subsystem <- 8086/51a8
1744 07:06:51.964731 PCI: 00:1e.0 cmd <- 06
1745 07:06:51.964808 PCI: 00:1e.3 subsystem <- 8086/51ab
1746 07:06:51.964889 PCI: 00:1e.3 cmd <- 02
1747 07:06:51.964967 PCI: 00:1f.0 subsystem <- 8086/5182
1748 07:06:51.965046 PCI: 00:1f.0 cmd <- 407
1749 07:06:51.965103 PCI: 00:1f.3 subsystem <- 8086/51c8
1750 07:06:51.965160 PCI: 00:1f.3 cmd <- 02
1751 07:06:51.965210 PCI: 00:1f.5 subsystem <- 8086/51a4
1752 07:06:51.965260 PCI: 00:1f.5 cmd <- 406
1753 07:06:51.965310 PCI: 01:00.0 cmd <- 02
1754 07:06:51.965358 done.
1755 07:06:51.965414 BS: BS_DEV_ENABLE run times (exec / console): 1 / 122 ms
1756 07:06:51.965466 ME: Version: Unavailable
1757 07:06:51.965515 BS: BS_DEV_ENABLE exit times (exec / console): 0 / 3 ms
1758 07:06:51.965565 Initializing devices...
1759 07:06:51.965614 Root Device init
1760 07:06:51.965668 mainboard: EC init
1761 07:06:51.965718 Chrome EC: Set SMI mask to 0x0000000000000000
1762 07:06:51.965768 Chrome EC: clear events_b mask to 0x0000000000000000
1763 07:06:51.965817 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1764 07:06:51.965866 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
1765 07:06:51.965922 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001808101e
1766 07:06:51.965972 Chrome EC: Set WAKE mask to 0x0000000000000000
1767 07:06:51.966021 Root Device init finished in 35 msecs
1768 07:06:51.966070 PCI: 00:00.0 init
1769 07:06:51.966119 CPU TDP = 15 Watts
1770 07:06:51.966175 CPU PL1 = 15 Watts
1771 07:06:51.966230 CPU PL2 = 55 Watts
1772 07:06:51.966301 CPU PL4 = 123 Watts
1773 07:06:51.966351 PCI: 00:00.0 init finished in 8 msecs
1774 07:06:51.966400 PCI: 00:02.0 init
1775 07:06:51.966456 GMA: Found VBT in CBFS
1776 07:06:51.966505 GMA: Found valid VBT in CBFS
1777 07:06:51.966554 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1778 07:06:51.966604 x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000
1779 07:06:51.966653 PCI: 00:02.0 init finished in 18 msecs
1780 07:06:51.966702 PCI: 00:06.0 init
1781 07:06:51.966781 Initializing PCH PCIe bridge.
1782 07:06:51.966859 PCI: 00:06.0 init finished in 3 msecs
1783 07:06:51.966936 PCI: 00:0a.0 init
1784 07:06:51.967013 PCI: 00:0a.0 init finished in 0 msecs
1785 07:06:51.967090 PCI: 00:14.0 init
1786 07:06:51.967167 PCI: 00:14.0 init finished in 0 msecs
1787 07:06:51.967243 PCI: 00:14.2 init
1788 07:06:51.967321 PCI: 00:14.2 init finished in 0 msecs
1789 07:06:51.967398 PCI: 00:15.0 init
1790 07:06:51.967475 I2C bus 0 version 0x3230302a
1791 07:06:51.967552 DW I2C bus 0 at 0x80655000 (400 KHz)
1792 07:06:51.967630 PCI: 00:15.0 init finished in 6 msecs
1793 07:06:51.967707 PCI: 00:15.1 init
1794 07:06:51.967784 I2C bus 1 version 0x3230302a
1795 07:06:51.967861 DW I2C bus 1 at 0x80656000 (400 KHz)
1796 07:06:51.967929 PCI: 00:15.1 init finished in 6 msecs
1797 07:06:51.967979 PCI: 00:15.3 init
1798 07:06:51.968030 I2C bus 3 version 0x3230302a
1799 07:06:51.968079 DW I2C bus 3 at 0x80657000 (400 KHz)
1800 07:06:51.968128 PCI: 00:15.3 init finished in 6 msecs
1801 07:06:51.968204 PCI: 00:16.0 init
1802 07:06:51.968282 PCI: 00:16.0 init finished in 0 msecs
1803 07:06:51.968358 PCI: 00:19.1 init
1804 07:06:51.968439 I2C bus 5 version 0x3230302a
1805 07:06:51.968516 DW I2C bus 5 at 0x80659000 (400 KHz)
1806 07:06:51.968594 PCI: 00:19.1 init finished in 6 msecs
1807 07:06:51.968675 PCI: 00:1f.0 init
1808 07:06:51.968960 IOAPIC: Initializing IOAPIC at 0xfec00000
1809 07:06:51.969065 IOAPIC: ID = 0x02
1810 07:06:51.969164 IOAPIC: Dumping registers
1811 07:06:51.969262 reg 0x0000: 0x02000000
1812 07:06:51.969359 reg 0x0001: 0x00770020
1813 07:06:51.969445 reg 0x0002: 0x00000000
1814 07:06:51.969542 IOAPIC: 120 interrupts
1815 07:06:51.969640 IOAPIC: Clearing IOAPIC at 0xfec00000
1816 07:06:51.969738 IOAPIC: vector 0x00 value 0x00000000 0x00010000
1817 07:06:51.969836 IOAPIC: vector 0x01 value 0x00000000 0x00010000
1818 07:06:51.969935 IOAPIC: vector 0x02 value 0x00000000 0x00010000
1819 07:06:51.970032 IOAPIC: vector 0x03 value 0x00000000 0x00010000
1820 07:06:51.970121 IOAPIC: vector 0x04 value 0x00000000 0x00010000
1821 07:06:51.970207 IOAPIC: vector 0x05 value 0x00000000 0x00010000
1822 07:06:51.970286 IOAPIC: vector 0x06 value 0x00000000 0x00010000
1823 07:06:51.970368 IOAPIC: vector 0x07 value 0x00000000 0x00010000
1824 07:06:51.970451 IOAPIC: vector 0x08 value 0x00000000 0x00010000
1825 07:06:51.970530 IOAPIC: vector 0x09 value 0x00000000 0x00010000
1826 07:06:51.970608 IOAPIC: vector 0x0a value 0x00000000 0x00010000
1827 07:06:51.970689 IOAPIC: vector 0x0b value 0x00000000 0x00010000
1828 07:06:51.970774 IOAPIC: vector 0x0c value 0x00000000 0x00010000
1829 07:06:51.970854 IOAPIC: vector 0x0d value 0x00000000 0x00010000
1830 07:06:51.970936 IOAPIC: vector 0x0e value 0x00000000 0x00010000
1831 07:06:51.971014 IOAPIC: vector 0x0f value 0x00000000 0x00010000
1832 07:06:51.971092 IOAPIC: vector 0x10 value 0x00000000 0x00010000
1833 07:06:51.971173 IOAPIC: vector 0x11 value 0x00000000 0x00010000
1834 07:06:51.971255 IOAPIC: vector 0x12 value 0x00000000 0x00010000
1835 07:06:51.971335 IOAPIC: vector 0x13 value 0x00000000 0x00010000
1836 07:06:51.971426 IOAPIC: vector 0x14 value 0x00000000 0x00010000
1837 07:06:51.971508 IOAPIC: vector 0x15 value 0x00000000 0x00010000
1838 07:06:51.971592 IOAPIC: vector 0x16 value 0x00000000 0x00010000
1839 07:06:51.971676 IOAPIC: vector 0x17 value 0x00000000 0x00010000
1840 07:06:51.971759 IOAPIC: vector 0x18 value 0x00000000 0x00010000
1841 07:06:51.971840 IOAPIC: vector 0x19 value 0x00000000 0x00010000
1842 07:06:51.971925 IOAPIC: vector 0x1a value 0x00000000 0x00010000
1843 07:06:51.972009 IOAPIC: vector 0x1b value 0x00000000 0x00010000
1844 07:06:51.972089 IOAPIC: vector 0x1c value 0x00000000 0x00010000
1845 07:06:51.972179 IOAPIC: vector 0x1d value 0x00000000 0x00010000
1846 07:06:51.972264 IOAPIC: vector 0x1e value 0x00000000 0x00010000
1847 07:06:51.972346 IOAPIC: vector 0x1f value 0x00000000 0x00010000
1848 07:06:51.972434 IOAPIC: vector 0x20 value 0x00000000 0x00010000
1849 07:06:51.972513 IOAPIC: vector 0x21 value 0x00000000 0x00010000
1850 07:06:51.972591 IOAPIC: vector 0x22 value 0x00000000 0x00010000
1851 07:06:51.972673 IOAPIC: vector 0x23 value 0x00000000 0x00010000
1852 07:06:51.972752 IOAPIC: vector 0x24 value 0x00000000 0x00010000
1853 07:06:51.972835 IOAPIC: vector 0x25 value 0x00000000 0x00010000
1854 07:06:51.972919 IOAPIC: vector 0x26 value 0x00000000 0x00010000
1855 07:06:51.973004 IOAPIC: vector 0x27 value 0x00000000 0x00010000
1856 07:06:51.973095 IOAPIC: vector 0x28 value 0x00000000 0x00010000
1857 07:06:51.973179 IOAPIC: vector 0x29 value 0x00000000 0x00010000
1858 07:06:51.973261 IOAPIC: vector 0x2a value 0x00000000 0x00010000
1859 07:06:51.973342 IOAPIC: vector 0x2b value 0x00000000 0x00010000
1860 07:06:51.973424 IOAPIC: vector 0x2c value 0x00000000 0x00010000
1861 07:06:51.973502 IOAPIC: vector 0x2d value 0x00000000 0x00010000
1862 07:06:51.973581 IOAPIC: vector 0x2e value 0x00000000 0x00010000
1863 07:06:51.973667 IOAPIC: vector 0x2f value 0x00000000 0x00010000
1864 07:06:51.973748 IOAPIC: vector 0x30 value 0x00000000 0x00010000
1865 07:06:51.973829 IOAPIC: vector 0x31 value 0x00000000 0x00010000
1866 07:06:51.973921 IOAPIC: vector 0x32 value 0x00000000 0x00010000
1867 07:06:51.974002 IOAPIC: vector 0x33 value 0x00000000 0x00010000
1868 07:06:51.974083 IOAPIC: vector 0x34 value 0x00000000 0x00010000
1869 07:06:51.974172 IOAPIC: vector 0x35 value 0x00000000 0x00010000
1870 07:06:51.974255 IOAPIC: vector 0x36 value 0x00000000 0x00010000
1871 07:06:51.974344 IOAPIC: vector 0x37 value 0x00000000 0x00010000
1872 07:06:51.974429 IOAPIC: vector 0x38 value 0x00000000 0x00010000
1873 07:06:51.974508 IOAPIC: vector 0x39 value 0x00000000 0x00010000
1874 07:06:51.974587 IOAPIC: vector 0x3a value 0x00000000 0x00010000
1875 07:06:51.974669 IOAPIC: vector 0x3b value 0x00000000 0x00010000
1876 07:06:51.974747 IOAPIC: vector 0x3c value 0x00000000 0x00010000
1877 07:06:51.974825 IOAPIC: vector 0x3d value 0x00000000 0x00010000
1878 07:06:51.974906 IOAPIC: vector 0x3e value 0x00000000 0x00010000
1879 07:06:51.974985 IOAPIC: vector 0x3f value 0x00000000 0x00010000
1880 07:06:51.975064 IOAPIC: vector 0x40 value 0x00000000 0x00010000
1881 07:06:51.975143 IOAPIC: vector 0x41 value 0x00000000 0x00010000
1882 07:06:51.975197 IOAPIC: vector 0x42 value 0x00000000 0x00010000
1883 07:06:51.975247 IOAPIC: vector 0x43 value 0x00000000 0x00010000
1884 07:06:51.975297 IOAPIC: vector 0x44 value 0x00000000 0x00010000
1885 07:06:51.975346 IOAPIC: vector 0x45 value 0x00000000 0x00010000
1886 07:06:51.975399 IOAPIC: vector 0x46 value 0x00000000 0x00010000
1887 07:06:51.975449 IOAPIC: vector 0x47 value 0x00000000 0x00010000
1888 07:06:51.975499 IOAPIC: vector 0x48 value 0x00000000 0x00010000
1889 07:06:51.975548 IOAPIC: vector 0x49 value 0x00000000 0x00010000
1890 07:06:51.975598 IOAPIC: vector 0x4a value 0x00000000 0x00010000
1891 07:06:51.975663 IOAPIC: vector 0x4b value 0x00000000 0x00010000
1892 07:06:51.975745 IOAPIC: vector 0x4c value 0x00000000 0x00010000
1893 07:06:51.975825 IOAPIC: vector 0x4d value 0x00000000 0x00010000
1894 07:06:51.975910 IOAPIC: vector 0x4e value 0x00000000 0x00010000
1895 07:06:51.976170 IOAPIC: vector 0x4f value 0x00000000 0x00010000
1896 07:06:51.976284 IOAPIC: vector 0x50 value 0x00000000 0x00010000
1897 07:06:51.976373 IOAPIC: vector 0x51 value 0x00000000 0x00010000
1898 07:06:51.976466 IOAPIC: vector 0x52 value 0x00000000 0x00010000
1899 07:06:51.976550 IOAPIC: vector 0x53 value 0x00000000 0x00010000
1900 07:06:51.976634 IOAPIC: vector 0x54 value 0x00000000 0x00010000
1901 07:06:51.976713 IOAPIC: vector 0x55 value 0x00000000 0x00010000
1902 07:06:51.976792 IOAPIC: vector 0x56 value 0x00000000 0x00010000
1903 07:06:51.976877 IOAPIC: vector 0x57 value 0x00000000 0x00010000
1904 07:06:51.976957 IOAPIC: vector 0x58 value 0x00000000 0x00010000
1905 07:06:51.977043 IOAPIC: vector 0x59 value 0x00000000 0x00010000
1906 07:06:51.977126 IOAPIC: vector 0x5a value 0x00000000 0x00010000
1907 07:06:51.977205 IOAPIC: vector 0x5b value 0x00000000 0x00010000
1908 07:06:51.977283 IOAPIC: vector 0x5c value 0x00000000 0x00010000
1909 07:06:51.977361 IOAPIC: vector 0x5d value 0x00000000 0x00010000
1910 07:06:51.977442 IOAPIC: vector 0x5e value 0x00000000 0x00010000
1911 07:06:51.977520 IOAPIC: vector 0x5f value 0x00000000 0x00010000
1912 07:06:51.977602 IOAPIC: vector 0x60 value 0x00000000 0x00010000
1913 07:06:51.977683 IOAPIC: vector 0x61 value 0x00000000 0x00010000
1914 07:06:51.977761 IOAPIC: vector 0x62 value 0x00000000 0x00010000
1915 07:06:51.977839 IOAPIC: vector 0x63 value 0x00000000 0x00010000
1916 07:06:51.977934 IOAPIC: vector 0x64 value 0x00000000 0x00010000
1917 07:06:51.978013 IOAPIC: vector 0x65 value 0x00000000 0x00010000
1918 07:06:51.978091 IOAPIC: vector 0x66 value 0x00000000 0x00010000
1919 07:06:51.978172 IOAPIC: vector 0x67 value 0x00000000 0x00010000
1920 07:06:51.978276 IOAPIC: vector 0x68 value 0x00000000 0x00010000
1921 07:06:51.978367 IOAPIC: vector 0x69 value 0x00000000 0x00010000
1922 07:06:51.978455 IOAPIC: vector 0x6a value 0x00000000 0x00010000
1923 07:06:51.978546 IOAPIC: vector 0x6b value 0x00000000 0x00010000
1924 07:06:51.978625 IOAPIC: vector 0x6c value 0x00000000 0x00010000
1925 07:06:51.978703 IOAPIC: vector 0x6d value 0x00000000 0x00010000
1926 07:06:51.978791 IOAPIC: vector 0x6e value 0x00000000 0x00010000
1927 07:06:51.978871 IOAPIC: vector 0x6f value 0x00000000 0x00010000
1928 07:06:51.978952 IOAPIC: vector 0x70 value 0x00000000 0x00010000
1929 07:06:51.979036 IOAPIC: vector 0x71 value 0x00000000 0x00010000
1930 07:06:51.979125 IOAPIC: vector 0x72 value 0x00000000 0x00010000
1931 07:06:51.979209 IOAPIC: vector 0x73 value 0x00000000 0x00010000
1932 07:06:51.979293 IOAPIC: vector 0x74 value 0x00000000 0x00010000
1933 07:06:51.979381 IOAPIC: vector 0x75 value 0x00000000 0x00010000
1934 07:06:51.979460 IOAPIC: vector 0x76 value 0x00000000 0x00010000
1935 07:06:51.979544 IOAPIC: vector 0x77 value 0x00000000 0x00010000
1936 07:06:51.979627 IOAPIC: Bootstrap Processor Local APIC = 0x00
1937 07:06:51.979707 IOAPIC: vector 0x00 value 0x00000000 0x00000700
1938 07:06:51.979793 PCI: 00:1f.0 init finished in 607 msecs
1939 07:06:51.979876 PCI: 00:1f.2 init
1940 07:06:51.979959 apm_control: Disabling ACPI.
1941 07:06:51.980044 APMC done.
1942 07:06:51.980127 PCI: 00:1f.2 init finished in 6 msecs
1943 07:06:51.980205 PCI: 00:1f.3 init
1944 07:06:51.980289 PCI: 00:1f.3 init finished in 0 msecs
1945 07:06:51.980372 PCI: 01:00.0 init
1946 07:06:51.980449 PCI: 01:00.0 init finished in 0 msecs
1947 07:06:51.980533 PNP: 0c09.0 init
1948 07:06:51.980620 Google Chrome EC uptime: 10.938 seconds
1949 07:06:51.980702 Google Chrome AP resets since EC boot: 0
1950 07:06:51.980788 Google Chrome most recent AP reset causes:
1951 07:06:51.980877 Google Chrome EC reset flags at last EC boot: reset-pin | hard
1952 07:06:51.980967 PNP: 0c09.0 init finished in 19 msecs
1953 07:06:51.981072 GENERIC: 0.0 init
1954 07:06:51.981158 GENERIC: 0.0 init finished in 0 msecs
1955 07:06:51.981245 GENERIC: 1.0 init
1956 07:06:51.981335 GENERIC: 1.0 init finished in 0 msecs
1957 07:06:51.981421 Devices initialized
1958 07:06:51.981507 Show all devs... After init.
1959 07:06:51.981595 Root Device: enabled 1
1960 07:06:51.981680 CPU_CLUSTER: 0: enabled 1
1961 07:06:51.981765 DOMAIN: 0000: enabled 1
1962 07:06:51.981853 GPIO: 0: enabled 1
1963 07:06:51.981939 PCI: 00:00.0: enabled 1
1964 07:06:51.982024 PCI: 00:01.0: enabled 0
1965 07:06:51.982113 PCI: 00:01.1: enabled 0
1966 07:06:51.982203 PCI: 00:02.0: enabled 1
1967 07:06:51.982289 PCI: 00:04.0: enabled 1
1968 07:06:51.982382 PCI: 00:05.0: enabled 0
1969 07:06:51.982467 PCI: 00:06.0: enabled 1
1970 07:06:51.982554 PCI: 00:06.2: enabled 0
1971 07:06:51.982639 PCI: 00:07.0: enabled 0
1972 07:06:51.982724 PCI: 00:07.1: enabled 0
1973 07:06:51.982811 PCI: 00:07.2: enabled 0
1974 07:06:51.982895 PCI: 00:07.3: enabled 0
1975 07:06:51.982980 PCI: 00:08.0: enabled 0
1976 07:06:51.983068 PCI: 00:09.0: enabled 0
1977 07:06:51.983154 PCI: 00:0a.0: enabled 1
1978 07:06:51.983239 PCI: 00:0d.0: enabled 1
1979 07:06:51.983327 PCI: 00:0d.1: enabled 0
1980 07:06:51.983415 PCI: 00:0d.2: enabled 0
1981 07:06:51.983500 PCI: 00:0d.3: enabled 0
1982 07:06:51.983590 PCI: 00:0e.0: enabled 0
1983 07:06:51.983677 PCI: 00:10.0: enabled 0
1984 07:06:51.983762 PCI: 00:10.1: enabled 0
1985 07:06:51.983850 PCI: 00:10.6: enabled 0
1986 07:06:51.983935 PCI: 00:10.7: enabled 0
1987 07:06:51.984023 PCI: 00:12.0: enabled 0
1988 07:06:51.984109 PCI: 00:12.6: enabled 0
1989 07:06:51.984196 PCI: 00:12.7: enabled 0
1990 07:06:51.984282 PCI: 00:13.0: enabled 0
1991 07:06:51.984370 PCI: 00:14.0: enabled 1
1992 07:06:51.984458 PCI: 00:14.1: enabled 0
1993 07:06:51.984543 PCI: 00:14.2: enabled 1
1994 07:06:51.984627 PCI: 00:14.3: enabled 1
1995 07:06:51.984715 PCI: 00:15.0: enabled 1
1996 07:06:51.984803 PCI: 00:15.1: enabled 1
1997 07:06:51.984888 PCI: 00:15.2: enabled 0
1998 07:06:51.984972 PCI: 00:15.3: enabled 1
1999 07:06:51.985068 PCI: 00:16.0: enabled 1
2000 07:06:51.985154 PCI: 00:16.1: enabled 0
2001 07:06:51.985239 PCI: 00:16.2: enabled 0
2002 07:06:51.985327 PCI: 00:16.3: enabled 0
2003 07:06:51.985412 PCI: 00:16.4: enabled 0
2004 07:06:51.985496 PCI: 00:16.5: enabled 0
2005 07:06:51.985584 PCI: 00:17.0: enabled 0
2006 07:06:51.985669 PCI: 00:19.0: enabled 0
2007 07:06:51.985757 PCI: 00:19.1: enabled 1
2008 07:06:51.985842 PCI: 00:19.2: enabled 0
2009 07:06:51.985930 PCI: 00:1a.0: enabled 0
2010 07:06:51.986020 PCI: 00:1c.0: enabled 0
2011 07:06:51.986110 PCI: 00:1c.1: enabled 0
2012 07:06:51.986395 PCI: 00:1c.2: enabled 0
2013 07:06:51.986482 PCI: 00:1c.3: enabled 0
2014 07:06:51.986569 PCI: 00:1c.4: enabled 0
2015 07:06:51.986654 PCI: 00:1c.5: enabled 0
2016 07:06:51.986739 PCI: 00:1c.6: enabled 0
2017 07:06:51.986827 PCI: 00:1c.7: enabled 0
2018 07:06:51.986913 PCI: 00:1d.0: enabled 0
2019 07:06:51.986998 PCI: 00:1d.1: enabled 0
2020 07:06:51.987088 PCI: 00:1d.2: enabled 0
2021 07:06:51.987177 PCI: 00:1d.3: enabled 0
2022 07:06:51.987262 PCI: 00:1e.0: enabled 1
2023 07:06:51.987347 PCI: 00:1e.1: enabled 0
2024 07:06:51.987435 PCI: 00:1e.2: enabled 0
2025 07:06:51.987520 PCI: 00:1e.3: enabled 1
2026 07:06:51.987605 PCI: 00:1f.0: enabled 1
2027 07:06:51.987693 PCI: 00:1f.1: enabled 0
2028 07:06:51.987778 PCI: 00:1f.2: enabled 1
2029 07:06:51.987863 PCI: 00:1f.3: enabled 1
2030 07:06:51.987951 PCI: 00:1f.4: enabled 0
2031 07:06:51.988043 PCI: 00:1f.5: enabled 1
2032 07:06:51.988127 PCI: 00:1f.6: enabled 0
2033 07:06:51.988213 PCI: 00:1f.7: enabled 0
2034 07:06:51.988303 GENERIC: 0.0: enabled 1
2035 07:06:51.988388 GENERIC: 0.0: enabled 1
2036 07:06:51.988473 GENERIC: 1.0: enabled 1
2037 07:06:51.988561 GENERIC: 0.0: enabled 1
2038 07:06:51.988647 GENERIC: 1.0: enabled 1
2039 07:06:51.988731 USB0 port 0: enabled 1
2040 07:06:51.988816 USB0 port 0: enabled 1
2041 07:06:51.988904 GENERIC: 0.0: enabled 1
2042 07:06:51.988993 I2C: 00:1a: enabled 1
2043 07:06:51.989086 I2C: 00:31: enabled 1
2044 07:06:51.989175 I2C: 00:32: enabled 1
2045 07:06:51.989262 I2C: 00:50: enabled 1
2046 07:06:51.989348 I2C: 00:10: enabled 1
2047 07:06:51.989434 I2C: 00:15: enabled 1
2048 07:06:51.989526 I2C: 00:2c: enabled 1
2049 07:06:51.989612 GENERIC: 0.0: enabled 1
2050 07:06:51.989698 SPI: 00: enabled 1
2051 07:06:51.989786 PNP: 0c09.0: enabled 1
2052 07:06:51.989871 GENERIC: 0.0: enabled 1
2053 07:06:51.989956 USB3 port 0: enabled 1
2054 07:06:51.990041 USB3 port 1: enabled 0
2055 07:06:51.990133 USB3 port 2: enabled 1
2056 07:06:51.990218 USB3 port 3: enabled 0
2057 07:06:51.990305 USB2 port 0: enabled 1
2058 07:06:51.990395 USB2 port 1: enabled 0
2059 07:06:51.990480 USB2 port 2: enabled 1
2060 07:06:51.990565 USB2 port 3: enabled 0
2061 07:06:51.990653 USB2 port 4: enabled 0
2062 07:06:51.990738 USB2 port 5: enabled 1
2063 07:06:51.990825 USB2 port 6: enabled 0
2064 07:06:51.990911 USB2 port 7: enabled 0
2065 07:06:51.990999 USB2 port 8: enabled 1
2066 07:06:51.991083 USB2 port 9: enabled 1
2067 07:06:51.991168 USB3 port 0: enabled 1
2068 07:06:51.991256 USB3 port 1: enabled 0
2069 07:06:51.991340 USB3 port 2: enabled 0
2070 07:06:51.991431 USB3 port 3: enabled 0
2071 07:06:51.991522 GENERIC: 0.0: enabled 1
2072 07:06:51.991603 GENERIC: 1.0: enabled 1
2073 07:06:51.991680 APIC: 00: enabled 1
2074 07:06:51.991757 APIC: 14: enabled 1
2075 07:06:51.991837 APIC: 16: enabled 1
2076 07:06:51.991914 APIC: 10: enabled 1
2077 07:06:51.991995 APIC: 12: enabled 1
2078 07:06:51.992079 APIC: 01: enabled 1
2079 07:06:51.992166 APIC: 08: enabled 1
2080 07:06:51.992245 APIC: 09: enabled 1
2081 07:06:51.992326 PCI: 01:00.0: enabled 1
2082 07:06:51.992412 BS: BS_DEV_INIT run times (exec / console): 8 / 1126 ms
2083 07:06:51.992496 FMAP: area RW_ELOG found @ f20000 (16384 bytes)
2084 07:06:51.992584 ELOG: NV offset 0xf20000 size 0x4000
2085 07:06:51.992677 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
2086 07:06:51.992762 ELOG: Event(17) added with size 13 at 2024-06-24 07:06:50 UTC
2087 07:06:51.992850 ELOG: Event(92) added with size 9 at 2024-06-24 07:06:50 UTC
2088 07:06:51.992939 ELOG: Event(93) added with size 9 at 2024-06-24 07:06:50 UTC
2089 07:06:51.993030 ELOG: Event(9E) added with size 10 at 2024-06-24 07:06:50 UTC
2090 07:06:51.993119 ELOG: Event(9F) added with size 14 at 2024-06-24 07:06:50 UTC
2091 07:06:51.993209 BS: BS_DEV_INIT exit times (exec / console): 4 / 45 ms
2092 07:06:51.993295 ELOG: Event(A1) added with size 10 at 2024-06-24 07:06:50 UTC
2093 07:06:51.993384 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
2094 07:06:51.993470 ELOG: Event(A0) added with size 9 at 2024-06-24 07:06:51 UTC
2095 07:06:51.993555 elog_add_boot_reason: Logged dev mode boot
2096 07:06:51.993643 BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms
2097 07:06:51.993729 Finalize devices...
2098 07:06:51.993816 PCI: 00:16.0 final
2099 07:06:51.993908 PCI: 00:1f.2 final
2100 07:06:51.993993 GENERIC: 0.0 final
2101 07:06:51.994082 added type-c port0 info to cbmem: usb2:1 usb3:1 sbu:0 data:0
2102 07:06:51.994168 GENERIC: 1.0 final
2103 07:06:51.994254 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
2104 07:06:51.994342 Devices finalized
2105 07:06:51.994427 BS: BS_POST_DEVICE run times (exec / console): 0 / 24 ms
2106 07:06:51.994512 FMAP: area RW_NVRAM found @ f2b000 (24576 bytes)
2107 07:06:51.994608 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
2108 07:06:51.994695 ME: HFSTS1 : 0x80030045
2109 07:06:51.994781 ME: HFSTS2 : 0x30280116
2110 07:06:51.994870 ME: HFSTS3 : 0x00000050
2111 07:06:51.994960 ME: HFSTS4 : 0x00004000
2112 07:06:51.995045 ME: HFSTS5 : 0x00000000
2113 07:06:51.995134 ME: HFSTS6 : 0x40400006
2114 07:06:51.995219 ME: Manufacturing Mode : YES
2115 07:06:51.995305 ME: SPI Protection Mode Enabled : YES
2116 07:06:51.995391 ME: FPFs Committed : YES
2117 07:06:51.995479 ME: Manufacturing Vars Locked : NO
2118 07:06:51.995568 ME: FW Partition Table : OK
2119 07:06:51.995657 ME: Bringup Loader Failure : NO
2120 07:06:51.995740 ME: Firmware Init Complete : NO
2121 07:06:51.995818 ME: Boot Options Present : NO
2122 07:06:51.995895 ME: Update In Progress : NO
2123 07:06:51.995978 ME: D0i3 Support : YES
2124 07:06:51.996057 ME: Low Power State Enabled : NO
2125 07:06:51.996134 ME: CPU Replaced : YES
2126 07:06:51.996213 ME: CPU Replacement Valid : YES
2127 07:06:51.996293 ME: Current Working State : 5
2128 07:06:51.996377 ME: Current Operation State : 1
2129 07:06:51.996458 ME: Current Operation Mode : 3
2130 07:06:51.996539 ME: Error Code : 0
2131 07:06:51.996618 ME: Enhanced Debug Mode : NO
2132 07:06:51.996696 ME: CPU Debug Disabled : YES
2133 07:06:51.996773 ME: TXT Support : NO
2134 07:06:51.996854 ME: WP for RO is enabled : YES
2135 07:06:51.997134 ME: RO write protection scope - Start=0x1000, End=0x15AFFF
2136 07:06:51.997220 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 111 ms
2137 07:06:51.997299 ELOG: Event(91) added with size 10 at 2024-06-24 07:06:51 UTC
2138 07:06:51.997382 Chrome EC: clear events_b mask to 0x0000000020004000
2139 07:06:51.997460 Ramoops buffer: 0x100000@0x7689a000.
2140 07:06:51.997544 BS: BS_WRITE_TABLES entry times (exec / console): 1 / 15 ms
2141 07:06:51.997623 CBFS: Found 'fallback/dsdt.aml' @0x788c0 size 0x4fd1 in mcache @0x76add1e8
2142 07:06:51.997704 CBFS: 'fallback/slic' not found.
2143 07:06:51.997782 ACPI: Writing ACPI tables at 7686e000.
2144 07:06:51.997860 ACPI: * FACS
2145 07:06:51.997940 ACPI: * DSDT
2146 07:06:51.998018 PCI space above 4GB MMIO is at 0x27fc00000, len = 0x7d80400000
2147 07:06:51.998096 ACPI: * FADT
2148 07:06:51.998175 SCI is IRQ9
2149 07:06:51.998257 ACPI: added table 1/32, length now 40
2150 07:06:51.998345 ACPI: * SSDT
2151 07:06:51.998435 Found 1 CPU(s) with 6/8 physical/logical core(s) each.
2152 07:06:51.998534 \_SB.PCI0.PEPD: Intel Power Engine Plug-in
2153 07:06:51.998624 \_SB.PCI0.PMC: Intel Alderlake at PCI: 00:1f.2
2154 07:06:51.998703 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
2155 07:06:51.998790 CBFS: Found 'wifi_sar_0.hex' @0x3b1c40 size 0xe6 in mcache @0x76addf40
2156 07:06:51.998869 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
2157 07:06:51.998952 \_SB.PCI0.I2C0.NAU8: Nuvoton NAU8825 Codec address 01ah irq 0
2158 07:06:51.999048 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
2159 07:06:51.999128 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
2160 07:06:51.999206 \_SB.PCI0.I2C1.TPMI: I2C TPM at I2C: 00:50
2161 07:06:51.999284 \_SB.PCI0.I2C3.H010: ELAN Touchscreen at I2C: 00:10
2162 07:06:51.999365 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
2163 07:06:51.999454 \_SB.PCI0.I2C5.H02C: Synaptics Touchpad at I2C: 00:2c
2164 07:06:51.999535 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
2165 07:06:51.999616 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
2166 07:06:51.999695 PS2K: Passing 80 keymaps to kernel
2167 07:06:51.999784 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
2168 07:06:51.999865 \_SB.PCI0.TXHC.RHUB.SS03: USB3 Type-C Port C1 (DB) at USB3 port 2
2169 07:06:51.999953 \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-C Port C0 (MLB) at USB2 port 0
2170 07:06:52.000032 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
2171 07:06:52.000110 \_SB.PCI0.XHCI.RHUB.HS06: USB2 Camera at USB2 port 5
2172 07:06:52.000205 \_SB.PCI0.XHCI.RHUB.HS09: USB2 Type-A Port A0 (DB) at USB2 port 8
2173 07:06:52.000296 \_SB.PCI0.XHCI.RHUB.HS10: USB2 Bluetooth at USB2 port 9
2174 07:06:52.000395 \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-A Port A0 (DB) at USB3 port 0
2175 07:06:52.000483 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
2176 07:06:52.000562 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
2177 07:06:52.000640 ACPI: added table 2/32, length now 44
2178 07:06:52.000720 ACPI: * MCFG
2179 07:06:52.000798 ACPI: added table 3/32, length now 48
2180 07:06:52.000874 ACPI: * TPM2
2181 07:06:52.000951 TPM2 log created at 0x7685e000
2182 07:06:52.001054 ACPI: added table 4/32, length now 52
2183 07:06:52.001136 ACPI: * LPIT
2184 07:06:52.001214 ACPI: added table 5/32, length now 56
2185 07:06:52.001294 ACPI: * MADT
2186 07:06:52.001371 SCI is IRQ9
2187 07:06:52.001450 ACPI: added table 6/32, length now 60
2188 07:06:52.001534 cmd_reg from pmc_make_ipc_cmd 1052838
2189 07:06:52.001618 CL PMC desc table: numb of regions is 0x2 at addr 0xfe0121bc
2190 07:06:52.001697 CL PMC desc table: region 0x0 has size 0x280 at offset 0x2200
2191 07:06:52.001776 CL PMC desc table: region 0x1 has size 0x80 at offset 0x3e00
2192 07:06:52.001857 PMC CrashLog size in discovery mode: 0xC00
2193 07:06:52.001936 cpu crashlog bar addr: 0x80640000
2194 07:06:52.002013 cpu discovery table offset: 0x6030
2195 07:06:52.002091 cpu_crashlog_discovery_table buffer count: 0x3
2196 07:06:52.002174 cpu_crashlog_discovery_table buffer: 0x0 size: 0x700 offset: 0x0
2197 07:06:52.002239 cpu_crashlog_discovery_table buffer: 0x1 size: 0x2b0 offset: 0x4000
2198 07:06:52.002328 cpu_crashlog_discovery_table buffer: 0x2 size: 0x370 offset: 0x5000
2199 07:06:52.002411 PMC crashLog size in discovery mode : 0xC00
2200 07:06:52.002490 Invalid data 0x0 at offset 0x2200 from addr 0xfe010000 of PMC SRAM.
2201 07:06:52.002569 discover mode PMC crashlog size adjusted to: 0x200
2202 07:06:52.002647 Invalid data 0x0 at offset 0x3e00 from addr 0xfe010000 of PMC SRAM.
2203 07:06:52.002728 discover mode PMC crashlog size adjusted to: 0x0
2204 07:06:52.002806 m_cpu_crashLog_size : 0x3480 bytes
2205 07:06:52.002893 CPU crashLog present.
2206 07:06:52.002973 CPU crash data size: 0x3480 bytes in 0x3 region(s).
2207 07:06:52.003060 Invalid data 0x0 at offset 0x0 from addr 0x80640000 of telemetry SRAM.
2208 07:06:52.003139 current = 76877550
2209 07:06:52.003221 ACPI: * DMAR
2210 07:06:52.003301 ACPI: added table 7/32, length now 64
2211 07:06:52.003384 ACPI: added table 8/32, length now 68
2212 07:06:52.003464 ACPI: * HPET
2213 07:06:52.003541 ACPI: added table 9/32, length now 72
2214 07:06:52.003621 ACPI: done.
2215 07:06:52.003699 ACPI tables: 38528 bytes.
2216 07:06:52.003776 smbios_write_tables: 76858000
2217 07:06:52.003853 EC returned error result code 3
2218 07:06:52.003934 Couldn't obtain OEM name from CBI
2219 07:06:52.004011 Create SMBIOS type 16
2220 07:06:52.004088 Create SMBIOS type 17
2221 07:06:52.004167 Create SMBIOS type 20
2222 07:06:52.004245 GENERIC: 0.0 (WIFI Device)
2223 07:06:52.004327 SMBIOS tables: 2156 bytes.
2224 07:06:52.004407 Writing table forward entry at 0x00000500
2225 07:06:52.004504 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 6955
2226 07:06:52.004587 Writing coreboot table at 0x76892000
2227 07:06:52.004666 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
2228 07:06:52.004945 1. 0000000000001000-000000000009ffff: RAM
2229 07:06:52.005047 2. 00000000000a0000-00000000000fffff: RESERVED
2230 07:06:52.005102 3. 0000000000100000-0000000076857fff: RAM
2231 07:06:52.005158 4. 0000000076858000-0000000076a2ffff: CONFIGURATION TABLES
2232 07:06:52.005207 5. 0000000076a30000-0000000076ab8fff: RAMSTAGE
2233 07:06:52.005258 6. 0000000076ab9000-0000000076ffffff: CONFIGURATION TABLES
2234 07:06:52.005311 7. 0000000077000000-00000000803fffff: RESERVED
2235 07:06:52.005365 8. 00000000c0000000-00000000cfffffff: RESERVED
2236 07:06:52.005415 9. 00000000f8000000-00000000f9ffffff: RESERVED
2237 07:06:52.005463 10. 00000000fb000000-00000000fb000fff: RESERVED
2238 07:06:52.005531 11. 00000000fc800000-00000000fe7fffff: RESERVED
2239 07:06:52.005608 12. 00000000feb00000-00000000feb7ffff: RESERVED
2240 07:06:52.005693 13. 00000000fec00000-00000000fecfffff: RESERVED
2241 07:06:52.005773 14. 00000000fed40000-00000000fed6ffff: RESERVED
2242 07:06:52.005858 15. 00000000fed80000-00000000fed87fff: RESERVED
2243 07:06:52.005940 16. 00000000fed90000-00000000fed92fff: RESERVED
2244 07:06:52.006024 17. 00000000feda0000-00000000feda1fff: RESERVED
2245 07:06:52.006107 18. 00000000fedc0000-00000000feddffff: RESERVED
2246 07:06:52.006191 19. 0000000100000000-000000027fbfffff: RAM
2247 07:06:52.006271 Passing 4 GPIOs to payload:
2248 07:06:52.006362 NAME | PORT | POLARITY | VALUE
2249 07:06:52.006446 lid | undefined | high | high
2250 07:06:52.006524 power | undefined | high | low
2251 07:06:52.006606 oprom | undefined | high | low
2252 07:06:52.006683 EC in RW | 0x00000151 | high | low
2253 07:06:52.006763 Board ID: 3
2254 07:06:52.006839 FW config: 0x131
2255 07:06:52.006917 Wrote coreboot table at: 0x76892000, 0x6cc bytes, checksum 7a07
2256 07:06:52.006994 coreboot table: 1764 bytes.
2257 07:06:52.007074 IMD ROOT 0. 0x76fff000 0x00001000
2258 07:06:52.007155 IMD SMALL 1. 0x76ffe000 0x00001000
2259 07:06:52.007232 FSP MEMORY 2. 0x76afe000 0x00500000
2260 07:06:52.007316 CONSOLE 3. 0x76ade000 0x00020000
2261 07:06:52.007393 RO MCACHE 4. 0x76add000 0x00000fd8
2262 07:06:52.007470 FMAP 5. 0x76adc000 0x0000064a
2263 07:06:52.007547 TIME STAMP 6. 0x76adb000 0x00000910
2264 07:06:52.007627 VBOOT WORK 7. 0x76ac7000 0x00014000
2265 07:06:52.007705 MEM INFO 8. 0x76ac6000 0x000003b8
2266 07:06:52.007783 ROMSTG STCK 9. 0x76ac5000 0x00001000
2267 07:06:52.007859 AFTER CAR 10. 0x76ab9000 0x0000c000
2268 07:06:52.007939 RAMSTAGE 11. 0x76a2f000 0x0008a000
2269 07:06:52.008016 ACPI BERT 12. 0x76a1f000 0x00010000
2270 07:06:52.008083 CHROMEOS NVS13. 0x76a1e000 0x00000f00
2271 07:06:52.008134 REFCODE 14. 0x769af000 0x0006f000
2272 07:06:52.008215 SMM BACKUP 15. 0x7699f000 0x00010000
2273 07:06:52.008296 IGD OPREGION16. 0x7699a000 0x00004203
2274 07:06:52.008373 RAMOOPS 17. 0x7689a000 0x00100000
2275 07:06:52.008457 COREBOOT 18. 0x76892000 0x00008000
2276 07:06:52.008534 ACPI 19. 0x7686e000 0x00024000
2277 07:06:52.008616 TPM2 TCGLOG20. 0x7685e000 0x00010000
2278 07:06:52.008693 PMC CRASHLOG21. 0x7685d000 0x00000c00
2279 07:06:52.008773 CPU CRASHLOG22. 0x76859000 0x00003480
2280 07:06:52.008850 SMBIOS 23. 0x76858000 0x00001000
2281 07:06:52.008926 IMD small region:
2282 07:06:52.009002 IMD ROOT 0. 0x76ffec00 0x00000400
2283 07:06:52.009070 FSP RUNTIME 1. 0x76ffebe0 0x00000004
2284 07:06:52.009120 VPD 2. 0x76ffeb60 0x0000006c
2285 07:06:52.009169 POWER STATE 3. 0x76ffeb00 0x00000044
2286 07:06:52.009232 ROMSTAGE 4. 0x76ffeae0 0x00000004
2287 07:06:52.009290 ACPI GNVS 5. 0x76ffea80 0x00000048
2288 07:06:52.009340 TYPE_C INFO 6. 0x76ffea60 0x0000000c
2289 07:06:52.009388 BS: BS_WRITE_TABLES run times (exec / console): 9 / 624 ms
2290 07:06:52.009437 MTRR: Physical address space:
2291 07:06:52.009485 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
2292 07:06:52.009536 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
2293 07:06:52.009589 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
2294 07:06:52.009639 0x0000000077000000 - 0x0000000090000000 size 0x19000000 type 0
2295 07:06:52.009689 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1
2296 07:06:52.009738 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0
2297 07:06:52.009787 0x0000000100000000 - 0x000000027fc00000 size 0x17fc00000 type 6
2298 07:06:52.009836 MTRR: Fixed MSR 0x250 0x0606060606060606
2299 07:06:52.009887 MTRR: Fixed MSR 0x258 0x0606060606060606
2300 07:06:52.009944 MTRR: Fixed MSR 0x259 0x0000000000000000
2301 07:06:52.010002 MTRR: Fixed MSR 0x268 0x0606060606060606
2302 07:06:52.010052 MTRR: Fixed MSR 0x269 0x0606060606060606
2303 07:06:52.010100 MTRR: Fixed MSR 0x26a 0x0606060606060606
2304 07:06:52.010148 MTRR: Fixed MSR 0x26b 0x0606060606060606
2305 07:06:52.010198 MTRR: Fixed MSR 0x26c 0x0606060606060606
2306 07:06:52.010246 MTRR: Fixed MSR 0x26d 0x0606060606060606
2307 07:06:52.010293 MTRR: Fixed MSR 0x26e 0x0606060606060606
2308 07:06:52.010341 MTRR: Fixed MSR 0x26f 0x0606060606060606
2309 07:06:52.010388 call enable_fixed_mtrr()
2310 07:06:52.010445 CPU physical address size: 39 bits
2311 07:06:52.010498 MTRR: default type WB/UC MTRR counts: 6/6.
2312 07:06:52.010553 MTRR: UC selected as default type.
2313 07:06:52.010610 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
2314 07:06:52.010660 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
2315 07:06:52.010739 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
2316 07:06:52.010820 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 1
2317 07:06:52.010898 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
2318 07:06:52.011171 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
2319 07:06:52.011247 MTRR: Fixed MSR 0x250 0x0606060606060606
2320 07:06:52.011325 MTRR: Fixed MSR 0x258 0x0606060606060606
2321 07:06:52.011405 MTRR: Fixed MSR 0x259 0x0000000000000000
2322 07:06:52.011482 MTRR: Fixed MSR 0x268 0x0606060606060606
2323 07:06:52.011559 MTRR: Fixed MSR 0x269 0x0606060606060606
2324 07:06:52.011639 MTRR: Fixed MSR 0x26a 0x0606060606060606
2325 07:06:52.011716 MTRR: Fixed MSR 0x26b 0x0606060606060606
2326 07:06:52.011792 MTRR: Fixed MSR 0x26c 0x0606060606060606
2327 07:06:52.011848 MTRR: Fixed MSR 0x26d 0x0606060606060606
2328 07:06:52.011933 MTRR: Fixed MSR 0x26e 0x0606060606060606
2329 07:06:52.012010 MTRR: Fixed MSR 0x26f 0x0606060606060606
2330 07:06:52.012088 MTRR: Fixed MSR 0x250 0x0606060606060606
2331 07:06:52.012143 call enable_fixed_mtrr()
2332 07:06:52.012196 MTRR: Fixed MSR 0x250 0x0606060606060606
2333 07:06:52.012245 MTRR: Fixed MSR 0x258 0x0606060606060606
2334 07:06:52.012300 MTRR: Fixed MSR 0x259 0x0000000000000000
2335 07:06:52.012347 MTRR: Fixed MSR 0x268 0x0606060606060606
2336 07:06:52.012399 MTRR: Fixed MSR 0x269 0x0606060606060606
2337 07:06:52.012453 MTRR: Fixed MSR 0x258 0x0606060606060606
2338 07:06:52.012506 MTRR: Fixed MSR 0x259 0x0000000000000000
2339 07:06:52.012553 MTRR: Fixed MSR 0x268 0x0606060606060606
2340 07:06:52.012601 MTRR: Fixed MSR 0x269 0x0606060606060606
2341 07:06:52.012649 MTRR: Fixed MSR 0x26a 0x0606060606060606
2342 07:06:52.012696 MTRR: Fixed MSR 0x26b 0x0606060606060606
2343 07:06:52.012747 MTRR: Fixed MSR 0x26c 0x0606060606060606
2344 07:06:52.012795 MTRR: Fixed MSR 0x26d 0x0606060606060606
2345 07:06:52.012842 MTRR: Fixed MSR 0x26e 0x0606060606060606
2346 07:06:52.012890 MTRR: Fixed MSR 0x26f 0x0606060606060606
2347 07:06:52.012969 MTRR: Fixed MSR 0x250 0x0606060606060606
2348 07:06:52.013049 call enable_fixed_mtrr()
2349 07:06:52.013100 MTRR: Fixed MSR 0x250 0x0606060606060606
2350 07:06:52.013149 MTRR: Fixed MSR 0x258 0x0606060606060606
2351 07:06:52.013198 MTRR: Fixed MSR 0x259 0x0000000000000000
2352 07:06:52.013246 MTRR: Fixed MSR 0x268 0x0606060606060606
2353 07:06:52.013297 MTRR: Fixed MSR 0x269 0x0606060606060606
2354 07:06:52.013345 MTRR: Fixed MSR 0x250 0x0606060606060606
2355 07:06:52.013393 CPU physical address size: 39 bits
2356 07:06:52.013444 MTRR: Fixed MSR 0x250 0x0606060606060606
2357 07:06:52.013497 MTRR: Fixed MSR 0x26a 0x0606060606060606
2358 07:06:52.013561 MTRR: Fixed MSR 0x258 0x0606060606060606
2359 07:06:52.013618 MTRR: Fixed MSR 0x26b 0x0606060606060606
2360 07:06:52.013666 MTRR: Fixed MSR 0x26c 0x0606060606060606
2361 07:06:52.013713 MTRR: Fixed MSR 0x26d 0x0606060606060606
2362 07:06:52.013760 MTRR: Fixed MSR 0x26e 0x0606060606060606
2363 07:06:52.013822 MTRR: Fixed MSR 0x26f 0x0606060606060606
2364 07:06:52.013871 MTRR: Fixed MSR 0x26a 0x0606060606060606
2365 07:06:52.013920 call enable_fixed_mtrr()
2366 07:06:52.013977 MTRR: Fixed MSR 0x26b 0x0606060606060606
2367 07:06:52.014027 MTRR: Fixed MSR 0x26c 0x0606060606060606
2368 07:06:52.014082 MTRR: Fixed MSR 0x26d 0x0606060606060606
2369 07:06:52.014130 MTRR: Fixed MSR 0x26e 0x0606060606060606
2370 07:06:52.014186 MTRR: Fixed MSR 0x26f 0x0606060606060606
2371 07:06:52.014234 CPU physical address size: 39 bits
2372 07:06:52.014283 CPU physical address size: 39 bits
2373 07:06:52.014341 MTRR: Fixed MSR 0x259 0x0000000000000000
2374 07:06:52.014392 call enable_fixed_mtrr()
2375 07:06:52.014447 MTRR: Fixed MSR 0x268 0x0606060606060606
2376 07:06:52.014503 MTRR: Fixed MSR 0x269 0x0606060606060606
2377 07:06:52.014557 MTRR: Fixed MSR 0x26a 0x0606060606060606
2378 07:06:52.014614 MTRR: Fixed MSR 0x26b 0x0606060606060606
2379 07:06:52.014670 MTRR: Fixed MSR 0x26c 0x0606060606060606
2380 07:06:52.014773 MTRR: Fixed MSR 0x26d 0x0606060606060606
2381 07:06:52.014856 MTRR: Fixed MSR 0x26e 0x0606060606060606
2382 07:06:52.014938 MTRR: Fixed MSR 0x26f 0x0606060606060606
2383 07:06:52.015016 MTRR: Fixed MSR 0x258 0x0606060606060606
2384 07:06:52.015102 call enable_fixed_mtrr()
2385 07:06:52.015185 CPU physical address size: 39 bits
2386 07:06:52.015268 MTRR: Fixed MSR 0x258 0x0606060606060606
2387 07:06:52.015345 CPU physical address size: 39 bits
2388 07:06:52.015424 MTRR: Fixed MSR 0x259 0x0000000000000000
2389 07:06:52.015502 MTRR: Fixed MSR 0x259 0x0000000000000000
2390 07:06:52.015578 MTRR: Fixed MSR 0x268 0x0606060606060606
2391 07:06:52.015658 MTRR: Fixed MSR 0x269 0x0606060606060606
2392 07:06:52.015735 MTRR: Fixed MSR 0x268 0x0606060606060606
2393 07:06:52.015815 MTRR: Fixed MSR 0x269 0x0606060606060606
2394 07:06:52.015892 MTRR: Fixed MSR 0x26a 0x0606060606060606
2395 07:06:52.015944 MTRR: Fixed MSR 0x26b 0x0606060606060606
2396 07:06:52.016032 MTRR: Fixed MSR 0x26c 0x0606060606060606
2397 07:06:52.016110 MTRR: Fixed MSR 0x26d 0x0606060606060606
2398 07:06:52.016191 MTRR: Fixed MSR 0x26e 0x0606060606060606
2399 07:06:52.016272 MTRR: Fixed MSR 0x26f 0x0606060606060606
2400 07:06:52.016349 MTRR: Fixed MSR 0x26a 0x0606060606060606
2401 07:06:52.016430 call enable_fixed_mtrr()
2402 07:06:52.016511 MTRR: Fixed MSR 0x26b 0x0606060606060606
2403 07:06:52.016593 MTRR: Fixed MSR 0x26c 0x0606060606060606
2404 07:06:52.016670 MTRR: Fixed MSR 0x26d 0x0606060606060606
2405 07:06:52.016750 MTRR: Fixed MSR 0x26e 0x0606060606060606
2406 07:06:52.016827 MTRR: Fixed MSR 0x26f 0x0606060606060606
2407 07:06:52.016903 CPU physical address size: 39 bits
2408 07:06:52.016983 call enable_fixed_mtrr()
2409 07:06:52.017068 CPU physical address size: 39 bits
2410 07:06:52.017144
2411 07:06:52.017228 MTRR check
2412 07:06:52.017305 Fixed MTRRs : Enabled
2413 07:06:52.017382 Variable MTRRs: Enabled
2414 07:06:52.017461
2415 07:06:52.017538 BS: BS_WRITE_TABLES exit times (exec / console): 253 / 150 ms
2416 07:06:52.017616 CBFS: Found 'fallback/payload' @0x3b1d80 size 0x25902 in mcache @0x76addf68
2417 07:06:52.017696 Checking segment from ROM address 0xffc26dac
2418 07:06:52.017773 Checking segment from ROM address 0xffc26dc8
2419 07:06:52.017853 Loading segment from ROM address 0xffc26dac
2420 07:06:52.017938 code (compression=1)
2421 07:06:52.018208 New segment dstaddr 0x30000000 memsize 0x2668e60 srcaddr 0xffc26de4 filesize 0x258ca
2422 07:06:52.018291 Loading Segment: addr: 0x30000000 memsz: 0x0000000002668e60 filesz: 0x00000000000258ca
2423 07:06:52.018368 using LZMA
2424 07:06:52.018449 [ 0x30000000, 30051214, 0x32668e60) <- ffc26de4
2425 07:06:52.018533 Clearing Segment: addr: 0x0000000030051214 memsz: 0x0000000002617c4c
2426 07:06:52.018615 Loading segment from ROM address 0xffc26dc8
2427 07:06:52.018701 Entry Point 0x30000000
2428 07:06:52.018778 Loaded segments
2429 07:06:52.018856 BS: BS_PAYLOAD_LOAD run times (exec / console): 86 / 62 ms
2430 07:06:52.018942 BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
2431 07:06:52.019020 Finalizing chipset.
2432 07:06:52.019098 apm_control: Finalizing SMM.
2433 07:06:52.019177 APMC done.
2434 07:06:52.019254 HECI: CSE device 16.0 is hidden
2435 07:06:52.019330 HECI: CSE device 16.1 is disabled
2436 07:06:52.019407 HECI: CSE device 16.2 is disabled
2437 07:06:52.019487 HECI: CSE device 16.3 is disabled
2438 07:06:52.019564 HECI: CSE device 16.4 is disabled
2439 07:06:52.019655 HECI: CSE device 16.5 is disabled
2440 07:06:52.022273 HECI: CSE device 16.0 is hidden
2441 07:06:52.029387 CSE is disabled, cannot send End-of-Post (EOP) message
2442 07:06:52.031853 BS: BS_PAYLOAD_BOOT entry times (exec / console): 0 / 35 ms
2443 07:06:52.035596 mp_park_aps done after 0 msecs.
2444 07:06:52.042153 Jumping to boot code at 0x30000000(0x76892000)
2445 07:06:52.051926 CPU0: stack: 0x76a9a000 - 0x76a9b000, lowest used address 0x76a9a3dc, stack used: 3108 bytes
2446 07:06:52.055617
2447 07:06:52.055715
2448 07:06:52.055800
2449 07:06:52.058968 Starting depthcharge on Volmar...
2450 07:06:52.059032
2451 07:06:52.059348 end: 2.2.3 depthcharge-start (duration 00:00:00) [common]
2452 07:06:52.059465 start: 2.2.4 bootloader-commands (timeout 00:04:46) [common]
2453 07:06:52.059564 Setting prompt string to ['brya:']
2454 07:06:52.059664 bootloader-commands: Wait for prompt ['brya:'] (timeout 00:04:46)
2455 07:06:52.065674 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2456 07:06:52.065743
2457 07:06:52.072692 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2458 07:06:52.072787
2459 07:06:52.078941 Looking for NVMe Controller 0x300653c0 @ 00:06:00
2460 07:06:52.079033
2461 07:06:52.082424 configure_storage: Failed to remap 1C:2
2462 07:06:52.082490
2463 07:06:52.085489 Wipe memory regions:
2464 07:06:52.085551
2465 07:06:52.088975 [0x00000000001000, 0x000000000a0000)
2466 07:06:52.089069
2467 07:06:52.092248 [0x00000000100000, 0x00000030000000)
2468 07:06:52.194701
2469 07:06:52.197957 [0x00000032668e60, 0x00000076858000)
2470 07:06:52.342727
2471 07:06:52.345268 [0x00000100000000, 0x0000027fc00000)
2472 07:06:53.155462
2473 07:06:53.158749 ec_init: CrosEC protocol v3 supported (256, 256)
2474 07:06:53.769110
2475 07:06:53.769224 R8152: Initializing
2476 07:06:53.769293
2477 07:06:53.772575 Version 9 (ocp_data = 6010)
2478 07:06:53.772669
2479 07:06:53.775667 R8152: Done initializing
2480 07:06:53.775762
2481 07:06:53.778754 Adding net device
2482 07:06:54.079809
2483 07:06:54.083047 [firmware-brya-14505.B-collabora] Feb 7 2023 16:06:26
2484 07:06:54.083157
2485 07:06:54.083246
2486 07:06:54.083553 Setting prompt string to ['brya:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2488 07:06:54.183873 brya: tftpboot 192.168.201.1 14531168/tftp-deploy-puyn5imd/kernel/bzImage 14531168/tftp-deploy-puyn5imd/kernel/cmdline 14531168/tftp-deploy-puyn5imd/ramdisk/ramdisk.cpio.gz
2489 07:06:54.184070 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2490 07:06:54.184151 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:44)
2491 07:06:54.188461 tftpboot 192.168.201.1 14531168/tftp-deploy-puyn5imd/kernel/bzIploy-puyn5imd/kernel/cmdline 14531168/tftp-deploy-puyn5imd/ramdisk/ramdisk.cpio.gz
2492 07:06:54.188541
2493 07:06:54.188602 Waiting for link
2494 07:06:54.392199
2495 07:06:54.392315 done.
2496 07:06:54.392378
2497 07:06:54.392434 MAC: 00:e0:4c:68:01:22
2498 07:06:54.392492
2499 07:06:54.395753 Sending DHCP discover... done.
2500 07:06:54.395845
2501 07:06:54.398931 Waiting for reply... done.
2502 07:06:54.399022
2503 07:06:54.402867 Sending DHCP request... done.
2504 07:06:54.402964
2505 07:06:54.408977 Waiting for reply... done.
2506 07:06:54.409078
2507 07:06:54.409139 My ip is 192.168.201.15
2508 07:06:54.409194
2509 07:06:54.412798 The DHCP server ip is 192.168.201.1
2510 07:06:54.412900
2511 07:06:54.418742 TFTP server IP predefined by user: 192.168.201.1
2512 07:06:54.418817
2513 07:06:54.425797 Bootfile predefined by user: 14531168/tftp-deploy-puyn5imd/kernel/bzImage
2514 07:06:54.425892
2515 07:06:54.428894 Sending tftp read request... done.
2516 07:06:54.428986
2517 07:06:54.431992 Waiting for the transfer...
2518 07:06:54.432059
2519 07:06:54.683764 00000000 ################################################################
2520 07:06:54.683913
2521 07:06:54.932917 00080000 ################################################################
2522 07:06:54.933040
2523 07:06:55.185073 00100000 ################################################################
2524 07:06:55.185196
2525 07:06:55.473719 00180000 ################################################################
2526 07:06:55.473843
2527 07:06:55.732724 00200000 ################################################################
2528 07:06:55.732862
2529 07:06:55.967034 00280000 ################################################################
2530 07:06:55.967186
2531 07:06:56.209605 00300000 ################################################################
2532 07:06:56.209754
2533 07:06:56.475733 00380000 ################################################################
2534 07:06:56.475876
2535 07:06:56.738008 00400000 ################################################################
2536 07:06:56.738168
2537 07:06:56.986338 00480000 ################################################################
2538 07:06:56.986451
2539 07:06:57.235436 00500000 ################################################################
2540 07:06:57.235550
2541 07:06:57.492843 00580000 ################################################################
2542 07:06:57.492969
2543 07:06:57.738438 00600000 ################################################################
2544 07:06:57.738564
2545 07:06:57.986716 00680000 ################################################################
2546 07:06:57.986833
2547 07:06:58.230375 00700000 ################################################################
2548 07:06:58.230501
2549 07:06:58.479965 00780000 ################################################################
2550 07:06:58.480095
2551 07:06:58.728001 00800000 ################################################################
2552 07:06:58.728136
2553 07:06:58.979116 00880000 ################################################################
2554 07:06:58.979239
2555 07:06:59.234226 00900000 ################################################################
2556 07:06:59.234337
2557 07:06:59.494813 00980000 ################################################################
2558 07:06:59.494928
2559 07:06:59.753114 00a00000 ################################################################
2560 07:06:59.753253
2561 07:07:00.008127 00a80000 ################################################################
2562 07:07:00.008278
2563 07:07:00.268186 00b00000 ################################################################
2564 07:07:00.268352
2565 07:07:00.528337 00b80000 ################################################################
2566 07:07:00.528483
2567 07:07:00.787760 00c00000 ################################################################
2568 07:07:00.787876
2569 07:07:01.067258 00c80000 ################################################################
2570 07:07:01.067449
2571 07:07:01.313454 00d00000 ################################################################
2572 07:07:01.313571
2573 07:07:01.558733 00d80000 ################################################################
2574 07:07:01.558849
2575 07:07:01.804775 00e00000 ################################################################
2576 07:07:01.804907
2577 07:07:02.050157 00e80000 ################################################################
2578 07:07:02.050304
2579 07:07:02.297895 00f00000 ################################################################
2580 07:07:02.298010
2581 07:07:02.549213 00f80000 ################################################################
2582 07:07:02.549376
2583 07:07:02.793944 01000000 ################################################################
2584 07:07:02.794052
2585 07:07:03.043190 01080000 ################################################################
2586 07:07:03.043304
2587 07:07:03.287805 01100000 ################################################################
2588 07:07:03.287943
2589 07:07:03.537513 01180000 ################################################################
2590 07:07:03.537632
2591 07:07:03.794283 01200000 ################################################################
2592 07:07:03.794400
2593 07:07:03.935219 01280000 ################################### done.
2594 07:07:03.935340
2595 07:07:03.938494 The bootfile was 19684992 bytes long.
2596 07:07:03.938574
2597 07:07:03.941716 Sending tftp read request... done.
2598 07:07:03.941796
2599 07:07:03.944824 Waiting for the transfer...
2600 07:07:03.944902
2601 07:07:04.209053 00000000 ################################################################
2602 07:07:04.209192
2603 07:07:04.478434 00080000 ################################################################
2604 07:07:04.478562
2605 07:07:04.741313 00100000 ################################################################
2606 07:07:04.741453
2607 07:07:05.002359 00180000 ################################################################
2608 07:07:05.002494
2609 07:07:05.255686 00200000 ################################################################
2610 07:07:05.255807
2611 07:07:05.505170 00280000 ################################################################
2612 07:07:05.505327
2613 07:07:05.754369 00300000 ################################################################
2614 07:07:05.754485
2615 07:07:06.014904 00380000 ################################################################
2616 07:07:06.015016
2617 07:07:06.269922 00400000 ################################################################
2618 07:07:06.270086
2619 07:07:06.542792 00480000 ################################################################
2620 07:07:06.542921
2621 07:07:06.848199 00500000 ################################################################
2622 07:07:06.848329
2623 07:07:07.144716 00580000 ################################################################
2624 07:07:07.144842
2625 07:07:07.451683 00600000 ################################################################
2626 07:07:07.451817
2627 07:07:07.747991 00680000 ################################################################
2628 07:07:07.748139
2629 07:07:08.009919 00700000 ################################################################
2630 07:07:08.010085
2631 07:07:08.266727 00780000 ################################################################
2632 07:07:08.266854
2633 07:07:08.534328 00800000 ################################################################
2634 07:07:08.534456
2635 07:07:08.797606 00880000 ################################################################
2636 07:07:08.797722
2637 07:07:09.065992 00900000 ################################################################
2638 07:07:09.066111
2639 07:07:09.338241 00980000 ################################################################
2640 07:07:09.338385
2641 07:07:09.573706 00a00000 ####################################################### done.
2642 07:07:09.573828
2643 07:07:09.576988 Sending tftp read request... done.
2644 07:07:09.577108
2645 07:07:09.580450 Waiting for the transfer...
2646 07:07:09.580523
2647 07:07:09.580587 00000000 # done.
2648 07:07:09.580643
2649 07:07:09.590598 Command line loaded dynamically from TFTP file: 14531168/tftp-deploy-puyn5imd/kernel/cmdline
2650 07:07:09.590675
2651 07:07:09.607187 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2652 07:07:09.613184
2653 07:07:09.616437 Shutting down all USB controllers.
2654 07:07:09.616515
2655 07:07:09.616572 Removing current net device
2656 07:07:09.616634
2657 07:07:09.620323 Finalizing coreboot
2658 07:07:09.620404
2659 07:07:09.626728 Exiting depthcharge with code 4 at timestamp: 27429579
2660 07:07:09.626813
2661 07:07:09.626879
2662 07:07:09.626934 Starting kernel ...
2663 07:07:09.626988
2664 07:07:09.627048
2665 07:07:09.627473 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
2666 07:07:09.627583 start: 2.2.5 auto-login-action (timeout 00:04:28) [common]
2667 07:07:09.627655 Setting prompt string to ['Linux version [0-9]']
2668 07:07:09.627719 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2669 07:07:09.627789 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2671 07:11:37.628593 end: 2.2.5 auto-login-action (duration 00:04:28) [common]
2673 07:11:37.629585 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 268 seconds'
2675 07:11:37.630380 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2678 07:11:37.631611 end: 2 depthcharge-action (duration 00:05:00) [common]
2680 07:11:37.632618 Cleaning after the job
2681 07:11:37.633322 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/ramdisk
2682 07:11:37.639162 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/kernel
2683 07:11:37.648941 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14531168/tftp-deploy-puyn5imd/modules
2684 07:11:37.654916 start: 4.1 power-off (timeout 00:00:30) [common]
2685 07:11:37.655614 Calling: ['pduclient', '--daemon=localhost', '--hostname=acer-cbv514-1h-34uz-brya-cbg-4', '--port=1', '--command=off']
2686 07:11:38.584067 >> Command sent successfully.
2687 07:11:38.597534 Returned 0 in 0 seconds
2688 07:11:38.698935 end: 4.1 power-off (duration 00:00:01) [common]
2690 07:11:38.700382 start: 4.2 read-feedback (timeout 00:09:59) [common]
2691 07:11:38.701626 Listened to connection for namespace 'common' for up to 1s
2693 07:11:38.702930 Listened to connection for namespace 'common' for up to 1s
2694 07:11:39.701417 Finalising connection for namespace 'common'
2695 07:11:39.702075 Disconnecting from shell: Finalise
2696 07:11:39.702466
2697 07:11:39.803654 end: 4.2 read-feedback (duration 00:00:01) [common]
2698 07:11:39.804260 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14531168
2699 07:11:39.824961 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14531168
2700 07:11:39.825167 JobError: Your job cannot terminate cleanly.