Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 17:38:34.626180 lava-dispatcher, installed at version: 2023.08
2 17:38:34.626336 start: 0 validate
3 17:38:34.626442 Start time: 2023-10-20 17:38:34.626435+00:00 (UTC)
4 17:38:34.626550 Validating that http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz exists
5 17:38:34.887026 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip78-rt45-338-gf468de833aa13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage exists
6 17:38:35.018753 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip78-rt45-338-gf468de833aa13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz exists
7 17:38:35.152919 validate duration: 0.53
9 17:38:35.153364 start: 1 tftp-deploy (timeout 00:10:00) [common]
10 17:38:35.153491 start: 1.1 download-retry (timeout 00:10:00) [common]
11 17:38:35.153604 start: 1.1.1 http-download (timeout 00:10:00) [common]
12 17:38:35.153758 Not decompressing ramdisk as can be used compressed.
13 17:38:35.153872 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
14 17:38:35.153946 saving as /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/ramdisk/rootfs.cpio.gz
15 17:38:35.154015 total size: 8418130 (8 MB)
16 17:38:35.414830 progress 0 % (0 MB)
17 17:38:36.484621 progress 5 % (0 MB)
18 17:38:37.479105 progress 10 % (0 MB)
19 17:38:38.577464 progress 15 % (1 MB)
20 17:38:39.521015 progress 20 % (1 MB)
21 17:38:40.430752 progress 25 % (2 MB)
22 17:38:41.303927 progress 30 % (2 MB)
23 17:38:42.198213 progress 35 % (2 MB)
24 17:38:43.014961 progress 40 % (3 MB)
25 17:38:43.819190 progress 45 % (3 MB)
26 17:38:44.650587 progress 50 % (4 MB)
27 17:38:45.646598 progress 55 % (4 MB)
28 17:38:46.469619 progress 60 % (4 MB)
29 17:38:47.180518 progress 65 % (5 MB)
30 17:38:48.000487 progress 70 % (5 MB)
31 17:38:48.806926 progress 75 % (6 MB)
32 17:38:49.535339 progress 80 % (6 MB)
33 17:38:50.247123 progress 85 % (6 MB)
34 17:38:50.913772 progress 90 % (7 MB)
35 17:38:51.524420 progress 95 % (7 MB)
36 17:38:52.034767 progress 100 % (8 MB)
37 17:38:52.035051 8 MB downloaded in 16.88 s (0.48 MB/s)
38 17:38:52.035256 end: 1.1.1 http-download (duration 00:00:17) [common]
40 17:38:52.035499 end: 1.1 download-retry (duration 00:00:17) [common]
41 17:38:52.035579 start: 1.2 download-retry (timeout 00:09:43) [common]
42 17:38:52.035655 start: 1.2.1 http-download (timeout 00:09:43) [common]
43 17:38:52.035800 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip78-rt45-338-gf468de833aa13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
44 17:38:52.035873 saving as /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/kernel/bzImage
45 17:38:52.035942 total size: 8507280 (8 MB)
46 17:38:52.036009 No compression specified
47 17:38:52.165550 progress 0 % (0 MB)
48 17:38:52.551709 progress 5 % (0 MB)
49 17:38:53.060828 progress 10 % (0 MB)
50 17:38:53.358771 progress 15 % (1 MB)
51 17:38:53.705876 progress 20 % (1 MB)
52 17:38:53.998804 progress 25 % (2 MB)
53 17:38:54.341042 progress 30 % (2 MB)
54 17:38:54.596874 progress 35 % (2 MB)
55 17:38:54.766537 progress 40 % (3 MB)
56 17:38:54.986264 progress 45 % (3 MB)
57 17:38:55.240763 progress 50 % (4 MB)
58 17:38:55.372554 progress 55 % (4 MB)
59 17:38:55.623586 progress 60 % (4 MB)
60 17:38:55.754999 progress 65 % (5 MB)
61 17:38:55.885887 progress 70 % (5 MB)
62 17:38:56.088489 progress 75 % (6 MB)
63 17:38:56.262669 progress 80 % (6 MB)
64 17:38:56.393769 progress 85 % (6 MB)
65 17:38:56.523904 progress 90 % (7 MB)
66 17:38:56.652520 progress 95 % (7 MB)
67 17:38:56.779329 progress 100 % (8 MB)
68 17:38:56.780172 8 MB downloaded in 4.74 s (1.71 MB/s)
69 17:38:56.780711 end: 1.2.1 http-download (duration 00:00:05) [common]
71 17:38:56.781030 end: 1.2 download-retry (duration 00:00:05) [common]
72 17:38:56.781104 start: 1.3 download-retry (timeout 00:09:38) [common]
73 17:38:56.781182 start: 1.3.1 http-download (timeout 00:09:38) [common]
74 17:38:56.781319 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip78-rt45-338-gf468de833aa13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
75 17:38:56.781385 saving as /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/modules/modules.tar
76 17:38:56.781440 total size: 253900 (0 MB)
77 17:38:56.781494 Using unxz to decompress xz
78 17:38:56.913713 progress 12 % (0 MB)
79 17:38:56.915264 progress 25 % (0 MB)
80 17:38:56.916336 progress 38 % (0 MB)
81 17:38:56.918700 progress 51 % (0 MB)
82 17:38:56.920982 progress 64 % (0 MB)
83 17:38:56.922655 progress 77 % (0 MB)
84 17:38:56.925400 progress 90 % (0 MB)
85 17:38:56.928570 progress 100 % (0 MB)
86 17:38:56.935247 0 MB downloaded in 0.15 s (1.57 MB/s)
87 17:38:56.935462 end: 1.3.1 http-download (duration 00:00:00) [common]
89 17:38:56.935717 end: 1.3 download-retry (duration 00:00:00) [common]
90 17:38:56.935816 start: 1.4 prepare-tftp-overlay (timeout 00:09:38) [common]
91 17:38:56.935918 start: 1.4.1 extract-nfsrootfs (timeout 00:09:38) [common]
92 17:38:56.935993 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
93 17:38:56.936078 start: 1.4.2 lava-overlay (timeout 00:09:38) [common]
94 17:38:56.936280 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5
95 17:38:56.936395 makedir: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin
96 17:38:56.936486 makedir: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/tests
97 17:38:56.936568 makedir: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/results
98 17:38:56.936677 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-add-keys
99 17:38:56.936792 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-add-sources
100 17:38:56.936890 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-background-process-start
101 17:38:56.936999 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-background-process-stop
102 17:38:56.937106 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-common-functions
103 17:38:56.937219 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-echo-ipv4
104 17:38:56.937327 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-install-packages
105 17:38:56.937432 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-installed-packages
106 17:38:56.937526 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-os-build
107 17:38:56.937619 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-probe-channel
108 17:38:56.937709 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-probe-ip
109 17:38:56.937800 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-target-ip
110 17:38:56.937919 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-target-mac
111 17:38:56.938018 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-target-storage
112 17:38:56.938112 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-case
113 17:38:56.938205 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-event
114 17:38:56.938296 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-feedback
115 17:38:56.938385 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-raise
116 17:38:56.938476 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-reference
117 17:38:56.938567 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-runner
118 17:38:56.938678 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-set
119 17:38:56.938780 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-test-shell
120 17:38:56.938882 Updating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-install-packages (oe)
121 17:38:56.939014 Updating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/bin/lava-installed-packages (oe)
122 17:38:56.939134 Creating /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/environment
123 17:38:56.939333 LAVA metadata
124 17:38:56.939432 - LAVA_JOB_ID=11831827
125 17:38:56.939498 - LAVA_DISPATCHER_IP=10.108.97.116
126 17:38:56.939590 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:38) [common]
127 17:38:56.939650 skipped lava-vland-overlay
128 17:38:56.939717 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
129 17:38:56.939796 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:38) [common]
130 17:38:56.939853 skipped lava-multinode-overlay
131 17:38:56.939913 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
132 17:38:56.939981 start: 1.4.2.3 test-definition (timeout 00:09:38) [common]
133 17:38:56.940044 Loading test definitions
134 17:38:56.940121 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:38) [common]
135 17:38:56.940186 Using /lava-11831827 at stage 0
136 17:38:56.940453 uuid=11831827_1.4.2.3.1 testdef=None
137 17:38:56.940531 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
138 17:38:56.940605 start: 1.4.2.3.2 test-overlay (timeout 00:09:38) [common]
139 17:38:56.941041 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
141 17:38:56.941237 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:38) [common]
142 17:38:56.941769 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
144 17:38:56.941954 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:38) [common]
145 17:38:56.942440 runner path: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/0/tests/0_dmesg test_uuid 11831827_1.4.2.3.1
146 17:38:56.942558 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
148 17:38:56.942749 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:38) [common]
149 17:38:56.942803 Using /lava-11831827 at stage 1
150 17:38:56.943022 uuid=11831827_1.4.2.3.5 testdef=None
151 17:38:56.943088 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
152 17:38:56.943149 start: 1.4.2.3.6 test-overlay (timeout 00:09:38) [common]
153 17:38:56.943500 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
155 17:38:56.943669 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:38) [common]
156 17:38:56.944270 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
158 17:38:56.944441 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:38) [common]
159 17:38:56.944975 runner path: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/1/tests/1_bootrr test_uuid 11831827_1.4.2.3.5
160 17:38:56.945085 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
162 17:38:56.945241 Creating lava-test-runner.conf files
163 17:38:56.945286 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/0 for stage 0
164 17:38:56.945351 - 0_dmesg
165 17:38:56.945412 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11831827/lava-overlay-zh8cshy5/lava-11831827/1 for stage 1
166 17:38:56.945480 - 1_bootrr
167 17:38:56.945553 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
168 17:38:56.945619 start: 1.4.2.4 compress-overlay (timeout 00:09:38) [common]
169 17:38:56.952104 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
170 17:38:56.952200 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
171 17:38:56.952275 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
172 17:38:56.952346 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
173 17:38:56.952414 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
174 17:38:57.118177 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
175 17:38:57.118476 start: 1.4.4 extract-modules (timeout 00:09:38) [common]
176 17:38:57.118596 extracting modules file /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11831827/extract-overlay-ramdisk-f39nxa1a/ramdisk
177 17:38:57.127435 end: 1.4.4 extract-modules (duration 00:00:00) [common]
178 17:38:57.127531 start: 1.4.5 apply-overlay-tftp (timeout 00:09:38) [common]
179 17:38:57.127604 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11831827/compress-overlay-ot1u7451/overlay-1.4.2.4.tar.gz to ramdisk
180 17:38:57.127662 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11831827/compress-overlay-ot1u7451/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11831827/extract-overlay-ramdisk-f39nxa1a/ramdisk
181 17:38:57.133864 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
182 17:38:57.133970 start: 1.4.6 configure-preseed-file (timeout 00:09:38) [common]
183 17:38:57.134045 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
184 17:38:57.134112 start: 1.4.7 compress-ramdisk (timeout 00:09:38) [common]
185 17:38:57.134172 Building ramdisk /var/lib/lava/dispatcher/tmp/11831827/extract-overlay-ramdisk-f39nxa1a/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11831827/extract-overlay-ramdisk-f39nxa1a/ramdisk
186 17:38:57.191722 >> 49827 blocks
187 17:38:57.924716 rename /var/lib/lava/dispatcher/tmp/11831827/extract-overlay-ramdisk-f39nxa1a/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/ramdisk/ramdisk.cpio.gz
188 17:38:57.925054 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
189 17:38:57.925159 start: 1.4.8 prepare-kernel (timeout 00:09:37) [common]
190 17:38:57.925245 start: 1.4.8.1 prepare-fit (timeout 00:09:37) [common]
191 17:38:57.925325 No mkimage arch provided, not using FIT.
192 17:38:57.925400 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
193 17:38:57.925469 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
194 17:38:57.925552 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
195 17:38:57.925627 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:37) [common]
196 17:38:57.925690 No LXC device requested
197 17:38:57.925754 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
198 17:38:57.925824 start: 1.6 deploy-device-env (timeout 00:09:37) [common]
199 17:38:57.925890 end: 1.6 deploy-device-env (duration 00:00:00) [common]
200 17:38:57.925952 Checking files for TFTP limit of 4294967296 bytes.
201 17:38:57.926276 end: 1 tftp-deploy (duration 00:00:23) [common]
202 17:38:57.926351 start: 2 depthcharge-action (timeout 00:05:00) [common]
203 17:38:57.926418 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
204 17:38:57.926969 substitutions:
205 17:38:57.927026 - {DTB}: None
206 17:38:57.927084 - {INITRD}: 11831827/tftp-deploy-z718qvo2/ramdisk/ramdisk.cpio.gz
207 17:38:57.927129 - {KERNEL}: 11831827/tftp-deploy-z718qvo2/kernel/bzImage
208 17:38:57.927172 - {LAVA_MAC}: None
209 17:38:57.927216 - {PRESEED_CONFIG}: None
210 17:38:57.927259 - {PRESEED_LOCAL}: None
211 17:38:57.927303 - {RAMDISK}: 11831827/tftp-deploy-z718qvo2/ramdisk/ramdisk.cpio.gz
212 17:38:57.927346 - {ROOT_PART}: None
213 17:38:57.927389 - {ROOT}: None
214 17:38:57.927432 - {SERVER_IP}: 10.108.97.116
215 17:38:57.927476 - {TEE}: None
216 17:38:57.927518 Parsed boot commands:
217 17:38:57.927561 - tftpboot 10.108.97.116 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
218 17:38:57.928115 Parsed boot commands: tftpboot 10.108.97.116 11831827/tftp-deploy-z718qvo2/kernel/bzImage 11831827/tftp-deploy-z718qvo2/kernel/cmdline 11831827/tftp-deploy-z718qvo2/ramdisk/ramdisk.cpio.gz
219 17:38:57.928198 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
220 17:38:57.928267 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
221 17:38:57.928334 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
222 17:38:57.928399 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
223 17:38:57.928452 Not connected, no need to disconnect.
224 17:38:57.928507 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
225 17:38:57.928655 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
226 17:38:57.928705 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-16'
227 17:38:57.931623 Setting prompt string to ['lava-test: # ']
228 17:38:57.931904 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
229 17:38:57.932000 end: 2.2.1 reset-connection (duration 00:00:00) [common]
230 17:38:57.932087 start: 2.2.2 reset-device (timeout 00:05:00) [common]
231 17:38:57.932182 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
232 17:38:57.932331 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-16' '--port=1' '--command=reboot'
233 17:39:03.076338 >> Command sent successfully.
234 17:39:03.084572 Returned 0 in 5 seconds
235 17:39:03.185549 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
237 17:39:03.186592 end: 2.2.2 reset-device (duration 00:00:05) [common]
238 17:39:03.186955 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
239 17:39:03.187261 Setting prompt string to 'Starting depthcharge on Voema...'
240 17:39:03.187492 Changing prompt to 'Starting depthcharge on Voema...'
241 17:39:03.187724 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
242 17:39:03.188544 [Enter `^Ec?' for help]
243 17:39:04.739958
244 17:39:04.740445
245 17:39:04.749828 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
246 17:39:04.753031 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz
247 17:39:04.759829 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
248 17:39:04.763282 CPU: AES supported, TXT NOT supported, VT supported
249 17:39:04.769462 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
250 17:39:04.776149 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
251 17:39:04.779664 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
252 17:39:04.782774 VBOOT: Loading verstage.
253 17:39:04.786366 FMAP: Found "FLASH" version 1.1 at 0x1804000.
254 17:39:04.793547 FMAP: base = 0x0 size = 0x2000000 #areas = 32
255 17:39:04.796539 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
256 17:39:04.804440 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
257 17:39:04.811375 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
258 17:39:04.815328
259 17:39:04.815408
260 17:39:04.825558 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
261 17:39:04.840181 Probing TPM: . done!
262 17:39:04.843521 TPM ready after 0 ms
263 17:39:04.847382 Connected to device vid:did:rid of 1ae0:0028:00
264 17:39:04.858337 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
265 17:39:04.864696 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
266 17:39:04.868501 Initialized TPM device CR50 revision 0
267 17:39:04.917071 tlcl_send_startup: Startup return code is 0
268 17:39:04.917224 TPM: setup succeeded
269 17:39:04.931059 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
270 17:39:04.945219 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
271 17:39:04.958237 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
272 17:39:04.967892 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
273 17:39:04.971905 Chrome EC: UHEPI supported
274 17:39:04.975349 Phase 1
275 17:39:04.978492 FMAP: area GBB found @ 1805000 (458752 bytes)
276 17:39:04.988231 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
277 17:39:04.995368 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
278 17:39:05.001552 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
279 17:39:05.008427 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
280 17:39:05.011481 Recovery requested (1009000e)
281 17:39:05.014636 TPM: Extending digest for VBOOT: boot mode into PCR 0
282 17:39:05.026378 tlcl_extend: response is 0
283 17:39:05.032977 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
284 17:39:05.043102 tlcl_extend: response is 0
285 17:39:05.049160 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
286 17:39:05.055740 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
287 17:39:05.062378 BS: verstage times (exec / console): total (unknown) / 142 ms
288 17:39:05.062739
289 17:39:05.062993
290 17:39:05.076099 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
291 17:39:05.082154 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
292 17:39:05.085803 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
293 17:39:05.088823 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
294 17:39:05.095503 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
295 17:39:05.098961 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
296 17:39:05.102263 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
297 17:39:05.105669 TCO_STS: 0000 0000
298 17:39:05.108942 GEN_PMCON: d0015038 00002200
299 17:39:05.112360 GBLRST_CAUSE: 00000000 00000000
300 17:39:05.115354 HPR_CAUSE0: 00000000
301 17:39:05.115739 prev_sleep_state 5
302 17:39:05.118966 Boot Count incremented to 3909
303 17:39:05.125769 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
304 17:39:05.132061 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
305 17:39:05.143553 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
306 17:39:05.148701 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
307 17:39:05.152357 Chrome EC: UHEPI supported
308 17:39:05.158545 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
309 17:39:05.169186 Probing TPM: done!
310 17:39:05.175955 Connected to device vid:did:rid of 1ae0:0028:00
311 17:39:05.186536 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
312 17:39:05.189463 Initialized TPM device CR50 revision 0
313 17:39:05.204210 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
314 17:39:05.211015 MRC: Hash idx 0x100b comparison successful.
315 17:39:05.214439 MRC cache found, size faa8
316 17:39:05.214823 bootmode is set to: 2
317 17:39:05.217759 SPD index = 2
318 17:39:05.224660 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
319 17:39:05.228170 SPD: module type is LPDDR4X
320 17:39:05.231273 SPD: module part number is MT53D1G64D4NW-046
321 17:39:05.237767 SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
322 17:39:05.240959 SPD: device width 16 bits, bus width 16 bits
323 17:39:05.247185 SPD: module size is 2048 MB (per channel)
324 17:39:05.677488 CBMEM:
325 17:39:05.680984 IMD: root @ 0x76fff000 254 entries.
326 17:39:05.684374 IMD: root @ 0x76ffec00 62 entries.
327 17:39:05.687378 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
328 17:39:05.694089 FMAP: area RW_VPD found @ f35000 (8192 bytes)
329 17:39:05.697364 External stage cache:
330 17:39:05.700575 IMD: root @ 0x7b3ff000 254 entries.
331 17:39:05.703715 IMD: root @ 0x7b3fec00 62 entries.
332 17:39:05.718740 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
333 17:39:05.725222 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
334 17:39:05.731618 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
335 17:39:05.745648 MRC: 'RECOVERY_MRC_CACHE' does not need update.
336 17:39:05.752294 cse_lite: Skip switching to RW in the recovery path
337 17:39:05.752375 8 DIMMs found
338 17:39:05.752433 SMM Memory Map
339 17:39:05.758994 SMRAM : 0x7b000000 0x800000
340 17:39:05.762592 Subregion 0: 0x7b000000 0x200000
341 17:39:05.765497 Subregion 1: 0x7b200000 0x200000
342 17:39:05.769009 Subregion 2: 0x7b400000 0x400000
343 17:39:05.769089 top_of_ram = 0x77000000
344 17:39:05.775489 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
345 17:39:05.782033 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
346 17:39:05.785330 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
347 17:39:05.792565 MTRR Range: Start=ff000000 End=0 (Size 1000000)
348 17:39:05.798923 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
349 17:39:05.805538 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
350 17:39:05.815705 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
351 17:39:05.822330 Processing 211 relocs. Offset value of 0x74c0b000
352 17:39:05.829161 BS: romstage times (exec / console): total (unknown) / 276 ms
353 17:39:05.834943
354 17:39:05.835323
355 17:39:05.844513 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
356 17:39:05.847573 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
357 17:39:05.857476 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
358 17:39:05.864422 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
359 17:39:05.871187 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
360 17:39:05.877473 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
361 17:39:05.921173 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
362 17:39:05.927713 Processing 5008 relocs. Offset value of 0x75d98000
363 17:39:05.931070 BS: postcar times (exec / console): total (unknown) / 59 ms
364 17:39:05.934691
365 17:39:05.934772
366 17:39:05.944322 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
367 17:39:05.944404 Normal boot
368 17:39:05.947587 FW_CONFIG value is 0x804c02
369 17:39:05.951564 PCI: 00:07.0 disabled by fw_config
370 17:39:05.954594 PCI: 00:07.1 disabled by fw_config
371 17:39:05.960814 PCI: 00:0d.2 disabled by fw_config
372 17:39:05.963954 PCI: 00:1c.7 disabled by fw_config
373 17:39:05.967410 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
374 17:39:05.974160 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
375 17:39:05.980917 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
376 17:39:05.983952 GENERIC: 0.0 disabled by fw_config
377 17:39:05.987547 GENERIC: 1.0 disabled by fw_config
378 17:39:05.991133 fw_config match found: DB_USB=USB3_ACTIVE
379 17:39:05.994085 fw_config match found: DB_USB=USB3_ACTIVE
380 17:39:05.997274 fw_config match found: DB_USB=USB3_ACTIVE
381 17:39:06.003837 fw_config match found: DB_USB=USB3_ACTIVE
382 17:39:06.007344 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
383 17:39:06.017027 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
384 17:39:06.023746 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
385 17:39:06.031278 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
386 17:39:06.034157 microcode: sig=0x806c1 pf=0x80 revision=0x86
387 17:39:06.040805 microcode: Update skipped, already up-to-date
388 17:39:06.047303 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
389 17:39:06.075143 Detected 4 core, 8 thread CPU.
390 17:39:06.078467 Setting up SMI for CPU
391 17:39:06.081791 IED base = 0x7b400000
392 17:39:06.082167 IED size = 0x00400000
393 17:39:06.085119 Will perform SMM setup.
394 17:39:06.091533 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz.
395 17:39:06.098122 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
396 17:39:06.104704 Processing 16 relocs. Offset value of 0x00030000
397 17:39:06.107990 Attempting to start 7 APs
398 17:39:06.111225 Waiting for 10ms after sending INIT.
399 17:39:06.126804 Waiting for 1st SIPI to complete...AP: slot 2 apic_id 1.
400 17:39:06.130019 AP: slot 5 apic_id 6.
401 17:39:06.133442 AP: slot 4 apic_id 7.
402 17:39:06.133520 done.
403 17:39:06.133576 AP: slot 7 apic_id 4.
404 17:39:06.136811 AP: slot 1 apic_id 5.
405 17:39:06.140333 AP: slot 3 apic_id 2.
406 17:39:06.140411 AP: slot 6 apic_id 3.
407 17:39:06.146961 Waiting for 2nd SIPI to complete...done.
408 17:39:06.153148 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
409 17:39:06.160088 Processing 13 relocs. Offset value of 0x00038000
410 17:39:06.163559 Unable to locate Global NVS
411 17:39:06.169801 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
412 17:39:06.173487 Installing permanent SMM handler to 0x7b000000
413 17:39:06.183243 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
414 17:39:06.186517 Processing 794 relocs. Offset value of 0x7b010000
415 17:39:06.196384 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
416 17:39:06.199608 Processing 13 relocs. Offset value of 0x7b008000
417 17:39:06.206248 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
418 17:39:06.213028 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
419 17:39:06.216332 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
420 17:39:06.223576 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
421 17:39:06.230093 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
422 17:39:06.236973 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
423 17:39:06.243279 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
424 17:39:06.243723 Unable to locate Global NVS
425 17:39:06.253448 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
426 17:39:06.256575 Clearing SMI status registers
427 17:39:06.256892 SMI_STS: PM1
428 17:39:06.259974 PM1_STS: PWRBTN
429 17:39:06.266110 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
430 17:39:06.269755 In relocation handler: CPU 0
431 17:39:06.273063 New SMBASE=0x7b000000 IEDBASE=0x7b400000
432 17:39:06.280405 Writing SMRR. base = 0x7b000006, mask=0xff800c00
433 17:39:06.280865 Relocation complete.
434 17:39:06.290095 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
435 17:39:06.290572 In relocation handler: CPU 2
436 17:39:06.296529 New SMBASE=0x7afff800 IEDBASE=0x7b400000
437 17:39:06.296883 Relocation complete.
438 17:39:06.306833 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
439 17:39:06.307300 In relocation handler: CPU 7
440 17:39:06.312541 New SMBASE=0x7affe400 IEDBASE=0x7b400000
441 17:39:06.316153 Writing SMRR. base = 0x7b000006, mask=0xff800c00
442 17:39:06.319364 Relocation complete.
443 17:39:06.326002 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
444 17:39:06.329294 In relocation handler: CPU 1
445 17:39:06.332748 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
446 17:39:06.335985 Relocation complete.
447 17:39:06.342977 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
448 17:39:06.346372 In relocation handler: CPU 4
449 17:39:06.349199 New SMBASE=0x7afff000 IEDBASE=0x7b400000
450 17:39:06.352658 Relocation complete.
451 17:39:06.359470 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
452 17:39:06.362756 In relocation handler: CPU 5
453 17:39:06.365751 New SMBASE=0x7affec00 IEDBASE=0x7b400000
454 17:39:06.372175 Writing SMRR. base = 0x7b000006, mask=0xff800c00
455 17:39:06.372538 Relocation complete.
456 17:39:06.379158 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
457 17:39:06.382446 In relocation handler: CPU 3
458 17:39:06.389409 New SMBASE=0x7afff400 IEDBASE=0x7b400000
459 17:39:06.392604 Writing SMRR. base = 0x7b000006, mask=0xff800c00
460 17:39:06.395730 Relocation complete.
461 17:39:06.402328 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
462 17:39:06.405622 In relocation handler: CPU 6
463 17:39:06.408689 New SMBASE=0x7affe800 IEDBASE=0x7b400000
464 17:39:06.412406 Relocation complete.
465 17:39:06.412765 Initializing CPU #0
466 17:39:06.415569 CPU: vendor Intel device 806c1
467 17:39:06.419122 CPU: family 06, model 8c, stepping 01
468 17:39:06.422536 Clearing out pending MCEs
469 17:39:06.425507 Setting up local APIC...
470 17:39:06.428578 apic_id: 0x00 done.
471 17:39:06.432104 Turbo is available but hidden
472 17:39:06.435474 Turbo is available and visible
473 17:39:06.438630 microcode: Update skipped, already up-to-date
474 17:39:06.441854 CPU #0 initialized
475 17:39:06.442214 Initializing CPU #2
476 17:39:06.445209 Initializing CPU #6
477 17:39:06.445602 Initializing CPU #1
478 17:39:06.448495 Initializing CPU #7
479 17:39:06.451743 CPU: vendor Intel device 806c1
480 17:39:06.455837 CPU: family 06, model 8c, stepping 01
481 17:39:06.458337 CPU: vendor Intel device 806c1
482 17:39:06.461896 CPU: family 06, model 8c, stepping 01
483 17:39:06.465228 Clearing out pending MCEs
484 17:39:06.468546 Clearing out pending MCEs
485 17:39:06.472141 Setting up local APIC...
486 17:39:06.472639 Initializing CPU #5
487 17:39:06.475311 Initializing CPU #4
488 17:39:06.478722 CPU: vendor Intel device 806c1
489 17:39:06.482222 CPU: family 06, model 8c, stepping 01
490 17:39:06.485079 Setting up local APIC...
491 17:39:06.488319 CPU: vendor Intel device 806c1
492 17:39:06.492459 CPU: family 06, model 8c, stepping 01
493 17:39:06.492918 Clearing out pending MCEs
494 17:39:06.496128 CPU: vendor Intel device 806c1
495 17:39:06.498979 CPU: family 06, model 8c, stepping 01
496 17:39:06.502426 Setting up local APIC...
497 17:39:06.506323 Clearing out pending MCEs
498 17:39:06.509356 apic_id: 0x06 done.
499 17:39:06.509811 Setting up local APIC...
500 17:39:06.512584 Initializing CPU #3
501 17:39:06.515637 CPU: vendor Intel device 806c1
502 17:39:06.518974 CPU: family 06, model 8c, stepping 01
503 17:39:06.522347 CPU: vendor Intel device 806c1
504 17:39:06.525508 CPU: family 06, model 8c, stepping 01
505 17:39:06.532460 microcode: Update skipped, already up-to-date
506 17:39:06.532925 apic_id: 0x07 done.
507 17:39:06.535598 CPU #5 initialized
508 17:39:06.539336 microcode: Update skipped, already up-to-date
509 17:39:06.542562 apic_id: 0x05 done.
510 17:39:06.543021 apic_id: 0x04 done.
511 17:39:06.548940 microcode: Update skipped, already up-to-date
512 17:39:06.552412 microcode: Update skipped, already up-to-date
513 17:39:06.555458 CPU #1 initialized
514 17:39:06.555830 CPU #7 initialized
515 17:39:06.558304 Clearing out pending MCEs
516 17:39:06.561933 CPU #4 initialized
517 17:39:06.565048 Clearing out pending MCEs
518 17:39:06.565123 Setting up local APIC...
519 17:39:06.569550 Clearing out pending MCEs
520 17:39:06.572107 Setting up local APIC...
521 17:39:06.575443 apic_id: 0x02 done.
522 17:39:06.575926 apic_id: 0x03 done.
523 17:39:06.582257 microcode: Update skipped, already up-to-date
524 17:39:06.585309 microcode: Update skipped, already up-to-date
525 17:39:06.588636 CPU #3 initialized
526 17:39:06.588990 CPU #6 initialized
527 17:39:06.591766 Setting up local APIC...
528 17:39:06.595228 apic_id: 0x01 done.
529 17:39:06.598573 microcode: Update skipped, already up-to-date
530 17:39:06.602450 CPU #2 initialized
531 17:39:06.605434 bsp_do_flight_plan done after 454 msecs.
532 17:39:06.608828 CPU: frequency set to 4400 MHz
533 17:39:06.609189 Enabling SMIs.
534 17:39:06.615158 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
535 17:39:06.632514 SATAXPCIE1 indicates PCIe NVMe is present
536 17:39:06.635951 Probing TPM: done!
537 17:39:06.639043 Connected to device vid:did:rid of 1ae0:0028:00
538 17:39:06.649601 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
539 17:39:06.652966 Initialized TPM device CR50 revision 0
540 17:39:06.656535 Enabling S0i3.4
541 17:39:06.662482 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
542 17:39:06.666051 Found a VBT of 8704 bytes after decompression
543 17:39:06.672364 cse_lite: CSE RO boot. HybridStorageMode disabled
544 17:39:06.678956 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
545 17:39:06.754036 FSPS returned 0
546 17:39:06.757388 Executing Phase 1 of FspMultiPhaseSiInit
547 17:39:06.767182 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
548 17:39:06.770088 port C0 DISC req: usage 1 usb3 1 usb2 5
549 17:39:06.773450 Raw Buffer output 0 00000511
550 17:39:06.776856 Raw Buffer output 1 00000000
551 17:39:06.780690 pmc_send_ipc_cmd succeeded
552 17:39:06.787686 port C1 DISC req: usage 1 usb3 2 usb2 3
553 17:39:06.788213 Raw Buffer output 0 00000321
554 17:39:06.790927 Raw Buffer output 1 00000000
555 17:39:06.794735 pmc_send_ipc_cmd succeeded
556 17:39:06.800285 Detected 4 core, 8 thread CPU.
557 17:39:06.803123 Detected 4 core, 8 thread CPU.
558 17:39:07.003453 Display FSP Version Info HOB
559 17:39:07.006805 Reference Code - CPU = a.0.4c.31
560 17:39:07.010739 uCode Version = 0.0.0.86
561 17:39:07.013599 TXT ACM version = ff.ff.ff.ffff
562 17:39:07.016597 Reference Code - ME = a.0.4c.31
563 17:39:07.020150 MEBx version = 0.0.0.0
564 17:39:07.023355 ME Firmware Version = Consumer SKU
565 17:39:07.026699 Reference Code - PCH = a.0.4c.31
566 17:39:07.029837 PCH-CRID Status = Disabled
567 17:39:07.032941 PCH-CRID Original Value = ff.ff.ff.ffff
568 17:39:07.036813 PCH-CRID New Value = ff.ff.ff.ffff
569 17:39:07.039913 OPROM - RST - RAID = ff.ff.ff.ffff
570 17:39:07.043329 PCH Hsio Version = 4.0.0.0
571 17:39:07.046426 Reference Code - SA - System Agent = a.0.4c.31
572 17:39:07.049750 Reference Code - MRC = 2.0.0.1
573 17:39:07.053017 SA - PCIe Version = a.0.4c.31
574 17:39:07.056481 SA-CRID Status = Disabled
575 17:39:07.059888 SA-CRID Original Value = 0.0.0.1
576 17:39:07.063104 SA-CRID New Value = 0.0.0.1
577 17:39:07.066545 OPROM - VBIOS = ff.ff.ff.ffff
578 17:39:07.069892 IO Manageability Engine FW Version = 11.1.4.0
579 17:39:07.073870 PHY Build Version = 0.0.0.e0
580 17:39:07.078268 Thunderbolt(TM) FW Version = 0.0.0.0
581 17:39:07.084171 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
582 17:39:07.084633 ITSS IRQ Polarities Before:
583 17:39:07.087231 IPC0: 0xffffffff
584 17:39:07.090944 IPC1: 0xffffffff
585 17:39:07.091398 IPC2: 0xffffffff
586 17:39:07.094070 IPC3: 0xffffffff
587 17:39:07.094538 ITSS IRQ Polarities After:
588 17:39:07.097182 IPC0: 0xffffffff
589 17:39:07.097533 IPC1: 0xffffffff
590 17:39:07.100509 IPC2: 0xffffffff
591 17:39:07.103652 IPC3: 0xffffffff
592 17:39:07.106715 Found PCIe Root Port #9 at PCI: 00:1d.0.
593 17:39:07.117295 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
594 17:39:07.130437 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
595 17:39:07.143431 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
596 17:39:07.150079 BS: BS_DEV_INIT_CHIPS run times (exec / console): 290 / 236 ms
597 17:39:07.150523 Enumerating buses...
598 17:39:07.156470 Show all devs... Before device enumeration.
599 17:39:07.156911 Root Device: enabled 1
600 17:39:07.159789 DOMAIN: 0000: enabled 1
601 17:39:07.163339 CPU_CLUSTER: 0: enabled 1
602 17:39:07.166590 PCI: 00:00.0: enabled 1
603 17:39:07.167090 PCI: 00:02.0: enabled 1
604 17:39:07.169933 PCI: 00:04.0: enabled 1
605 17:39:07.172959 PCI: 00:05.0: enabled 1
606 17:39:07.176276 PCI: 00:06.0: enabled 0
607 17:39:07.176647 PCI: 00:07.0: enabled 0
608 17:39:07.181037 PCI: 00:07.1: enabled 0
609 17:39:07.183345 PCI: 00:07.2: enabled 0
610 17:39:07.186590 PCI: 00:07.3: enabled 0
611 17:39:07.187054 PCI: 00:08.0: enabled 1
612 17:39:07.189303 PCI: 00:09.0: enabled 0
613 17:39:07.193268 PCI: 00:0a.0: enabled 0
614 17:39:07.196210 PCI: 00:0d.0: enabled 1
615 17:39:07.196559 PCI: 00:0d.1: enabled 0
616 17:39:07.199872 PCI: 00:0d.2: enabled 0
617 17:39:07.202966 PCI: 00:0d.3: enabled 0
618 17:39:07.203411 PCI: 00:0e.0: enabled 0
619 17:39:07.206409 PCI: 00:10.2: enabled 1
620 17:39:07.209940 PCI: 00:10.6: enabled 0
621 17:39:07.212648 PCI: 00:10.7: enabled 0
622 17:39:07.213008 PCI: 00:12.0: enabled 0
623 17:39:07.216013 PCI: 00:12.6: enabled 0
624 17:39:07.219288 PCI: 00:13.0: enabled 0
625 17:39:07.222763 PCI: 00:14.0: enabled 1
626 17:39:07.223230 PCI: 00:14.1: enabled 0
627 17:39:07.226175 PCI: 00:14.2: enabled 1
628 17:39:07.229456 PCI: 00:14.3: enabled 1
629 17:39:07.232995 PCI: 00:15.0: enabled 1
630 17:39:07.233488 PCI: 00:15.1: enabled 1
631 17:39:07.235969 PCI: 00:15.2: enabled 1
632 17:39:07.239475 PCI: 00:15.3: enabled 1
633 17:39:07.242476 PCI: 00:16.0: enabled 1
634 17:39:07.242843 PCI: 00:16.1: enabled 0
635 17:39:07.246017 PCI: 00:16.2: enabled 0
636 17:39:07.249122 PCI: 00:16.3: enabled 0
637 17:39:07.249486 PCI: 00:16.4: enabled 0
638 17:39:07.252445 PCI: 00:16.5: enabled 0
639 17:39:07.255748 PCI: 00:17.0: enabled 1
640 17:39:07.259228 PCI: 00:19.0: enabled 0
641 17:39:07.259697 PCI: 00:19.1: enabled 1
642 17:39:07.262975 PCI: 00:19.2: enabled 0
643 17:39:07.265985 PCI: 00:1c.0: enabled 1
644 17:39:07.269309 PCI: 00:1c.1: enabled 0
645 17:39:07.269795 PCI: 00:1c.2: enabled 0
646 17:39:07.272358 PCI: 00:1c.3: enabled 0
647 17:39:07.275802 PCI: 00:1c.4: enabled 0
648 17:39:07.278817 PCI: 00:1c.5: enabled 0
649 17:39:07.279199 PCI: 00:1c.6: enabled 1
650 17:39:07.282322 PCI: 00:1c.7: enabled 0
651 17:39:07.285437 PCI: 00:1d.0: enabled 1
652 17:39:07.288631 PCI: 00:1d.1: enabled 0
653 17:39:07.288979 PCI: 00:1d.2: enabled 1
654 17:39:07.291817 PCI: 00:1d.3: enabled 0
655 17:39:07.295434 PCI: 00:1e.0: enabled 1
656 17:39:07.298847 PCI: 00:1e.1: enabled 0
657 17:39:07.299332 PCI: 00:1e.2: enabled 1
658 17:39:07.302164 PCI: 00:1e.3: enabled 1
659 17:39:07.305602 PCI: 00:1f.0: enabled 1
660 17:39:07.306094 PCI: 00:1f.1: enabled 0
661 17:39:07.308946 PCI: 00:1f.2: enabled 1
662 17:39:07.312236 PCI: 00:1f.3: enabled 1
663 17:39:07.315272 PCI: 00:1f.4: enabled 0
664 17:39:07.315664 PCI: 00:1f.5: enabled 1
665 17:39:07.318410 PCI: 00:1f.6: enabled 0
666 17:39:07.321660 PCI: 00:1f.7: enabled 0
667 17:39:07.325564 APIC: 00: enabled 1
668 17:39:07.326031 GENERIC: 0.0: enabled 1
669 17:39:07.328461 GENERIC: 0.0: enabled 1
670 17:39:07.331951 GENERIC: 1.0: enabled 1
671 17:39:07.335187 GENERIC: 0.0: enabled 1
672 17:39:07.335579 GENERIC: 1.0: enabled 1
673 17:39:07.338530 USB0 port 0: enabled 1
674 17:39:07.341849 GENERIC: 0.0: enabled 1
675 17:39:07.342344 USB0 port 0: enabled 1
676 17:39:07.345636 GENERIC: 0.0: enabled 1
677 17:39:07.348408 I2C: 00:1a: enabled 1
678 17:39:07.348898 I2C: 00:31: enabled 1
679 17:39:07.351610 I2C: 00:32: enabled 1
680 17:39:07.354854 I2C: 00:10: enabled 1
681 17:39:07.358402 I2C: 00:15: enabled 1
682 17:39:07.358795 GENERIC: 0.0: enabled 0
683 17:39:07.361383 GENERIC: 1.0: enabled 0
684 17:39:07.364689 GENERIC: 0.0: enabled 1
685 17:39:07.365040 SPI: 00: enabled 1
686 17:39:07.368001 SPI: 00: enabled 1
687 17:39:07.371801 PNP: 0c09.0: enabled 1
688 17:39:07.372273 GENERIC: 0.0: enabled 1
689 17:39:07.374807 USB3 port 0: enabled 1
690 17:39:07.378173 USB3 port 1: enabled 1
691 17:39:07.381555 USB3 port 2: enabled 0
692 17:39:07.382017 USB3 port 3: enabled 0
693 17:39:07.384743 USB2 port 0: enabled 0
694 17:39:07.388538 USB2 port 1: enabled 1
695 17:39:07.388985 USB2 port 2: enabled 1
696 17:39:07.391011 USB2 port 3: enabled 0
697 17:39:07.394627 USB2 port 4: enabled 1
698 17:39:07.394977 USB2 port 5: enabled 0
699 17:39:07.397897 USB2 port 6: enabled 0
700 17:39:07.400930 USB2 port 7: enabled 0
701 17:39:07.404438 USB2 port 8: enabled 0
702 17:39:07.404788 USB2 port 9: enabled 0
703 17:39:07.407614 USB3 port 0: enabled 0
704 17:39:07.411125 USB3 port 1: enabled 1
705 17:39:07.411589 USB3 port 2: enabled 0
706 17:39:07.414427 USB3 port 3: enabled 0
707 17:39:07.417723 GENERIC: 0.0: enabled 1
708 17:39:07.420939 GENERIC: 1.0: enabled 1
709 17:39:07.421342 APIC: 05: enabled 1
710 17:39:07.424125 APIC: 01: enabled 1
711 17:39:07.427313 APIC: 02: enabled 1
712 17:39:07.427663 APIC: 07: enabled 1
713 17:39:07.430501 APIC: 06: enabled 1
714 17:39:07.430582 APIC: 03: enabled 1
715 17:39:07.433728 APIC: 04: enabled 1
716 17:39:07.437140 Compare with tree...
717 17:39:07.437214 Root Device: enabled 1
718 17:39:07.440844 DOMAIN: 0000: enabled 1
719 17:39:07.444489 PCI: 00:00.0: enabled 1
720 17:39:07.447245 PCI: 00:02.0: enabled 1
721 17:39:07.447616 PCI: 00:04.0: enabled 1
722 17:39:07.450682 GENERIC: 0.0: enabled 1
723 17:39:07.454117 PCI: 00:05.0: enabled 1
724 17:39:07.457934 PCI: 00:06.0: enabled 0
725 17:39:07.460277 PCI: 00:07.0: enabled 0
726 17:39:07.463573 GENERIC: 0.0: enabled 1
727 17:39:07.463950 PCI: 00:07.1: enabled 0
728 17:39:07.466742 GENERIC: 1.0: enabled 1
729 17:39:07.470630 PCI: 00:07.2: enabled 0
730 17:39:07.473503 GENERIC: 0.0: enabled 1
731 17:39:07.477166 PCI: 00:07.3: enabled 0
732 17:39:07.477275 GENERIC: 1.0: enabled 1
733 17:39:07.480293 PCI: 00:08.0: enabled 1
734 17:39:07.483406 PCI: 00:09.0: enabled 0
735 17:39:07.487009 PCI: 00:0a.0: enabled 0
736 17:39:07.489949 PCI: 00:0d.0: enabled 1
737 17:39:07.490032 USB0 port 0: enabled 1
738 17:39:07.493506 USB3 port 0: enabled 1
739 17:39:07.496709 USB3 port 1: enabled 1
740 17:39:07.499693 USB3 port 2: enabled 0
741 17:39:07.503261 USB3 port 3: enabled 0
742 17:39:07.503351 PCI: 00:0d.1: enabled 0
743 17:39:07.506649 PCI: 00:0d.2: enabled 0
744 17:39:07.509765 GENERIC: 0.0: enabled 1
745 17:39:07.513134 PCI: 00:0d.3: enabled 0
746 17:39:07.516356 PCI: 00:0e.0: enabled 0
747 17:39:07.519739 PCI: 00:10.2: enabled 1
748 17:39:07.519843 PCI: 00:10.6: enabled 0
749 17:39:07.523258 PCI: 00:10.7: enabled 0
750 17:39:07.526466 PCI: 00:12.0: enabled 0
751 17:39:07.529981 PCI: 00:12.6: enabled 0
752 17:39:07.530061 PCI: 00:13.0: enabled 0
753 17:39:07.533013 PCI: 00:14.0: enabled 1
754 17:39:07.536796 USB0 port 0: enabled 1
755 17:39:07.539707 USB2 port 0: enabled 0
756 17:39:07.543081 USB2 port 1: enabled 1
757 17:39:07.546576 USB2 port 2: enabled 1
758 17:39:07.546653 USB2 port 3: enabled 0
759 17:39:07.549396 USB2 port 4: enabled 1
760 17:39:07.552896 USB2 port 5: enabled 0
761 17:39:07.556199 USB2 port 6: enabled 0
762 17:39:07.559403 USB2 port 7: enabled 0
763 17:39:07.562988 USB2 port 8: enabled 0
764 17:39:07.563065 USB2 port 9: enabled 0
765 17:39:07.566047 USB3 port 0: enabled 0
766 17:39:07.569581 USB3 port 1: enabled 1
767 17:39:07.572793 USB3 port 2: enabled 0
768 17:39:07.576130 USB3 port 3: enabled 0
769 17:39:07.576210 PCI: 00:14.1: enabled 0
770 17:39:07.579412 PCI: 00:14.2: enabled 1
771 17:39:07.582746 PCI: 00:14.3: enabled 1
772 17:39:07.585862 GENERIC: 0.0: enabled 1
773 17:39:07.589883 PCI: 00:15.0: enabled 1
774 17:39:07.589989 I2C: 00:1a: enabled 1
775 17:39:07.592878 I2C: 00:31: enabled 1
776 17:39:07.595958 I2C: 00:32: enabled 1
777 17:39:07.599237 PCI: 00:15.1: enabled 1
778 17:39:07.602587 I2C: 00:10: enabled 1
779 17:39:07.602681 PCI: 00:15.2: enabled 1
780 17:39:07.606008 PCI: 00:15.3: enabled 1
781 17:39:07.609018 PCI: 00:16.0: enabled 1
782 17:39:07.612403 PCI: 00:16.1: enabled 0
783 17:39:07.612528 PCI: 00:16.2: enabled 0
784 17:39:07.616127 PCI: 00:16.3: enabled 0
785 17:39:07.619849 PCI: 00:16.4: enabled 0
786 17:39:07.622574 PCI: 00:16.5: enabled 0
787 17:39:07.625734 PCI: 00:17.0: enabled 1
788 17:39:07.625848 PCI: 00:19.0: enabled 0
789 17:39:07.629266 PCI: 00:19.1: enabled 1
790 17:39:07.632363 I2C: 00:15: enabled 1
791 17:39:07.636326 PCI: 00:19.2: enabled 0
792 17:39:07.639103 PCI: 00:1d.0: enabled 1
793 17:39:07.639253 GENERIC: 0.0: enabled 1
794 17:39:07.642416 PCI: 00:1e.0: enabled 1
795 17:39:07.646070 PCI: 00:1e.1: enabled 0
796 17:39:07.649216 PCI: 00:1e.2: enabled 1
797 17:39:07.652613 SPI: 00: enabled 1
798 17:39:07.652740 PCI: 00:1e.3: enabled 1
799 17:39:07.655985 SPI: 00: enabled 1
800 17:39:07.659918 PCI: 00:1f.0: enabled 1
801 17:39:07.662711 PNP: 0c09.0: enabled 1
802 17:39:07.663173 PCI: 00:1f.1: enabled 0
803 17:39:07.666144 PCI: 00:1f.2: enabled 1
804 17:39:07.669067 GENERIC: 0.0: enabled 1
805 17:39:07.672297 GENERIC: 0.0: enabled 1
806 17:39:07.675581 GENERIC: 1.0: enabled 1
807 17:39:07.675961 PCI: 00:1f.3: enabled 1
808 17:39:07.678937 PCI: 00:1f.4: enabled 0
809 17:39:07.682113 PCI: 00:1f.5: enabled 1
810 17:39:07.685993 PCI: 00:1f.6: enabled 0
811 17:39:07.688906 PCI: 00:1f.7: enabled 0
812 17:39:07.691949 CPU_CLUSTER: 0: enabled 1
813 17:39:07.692312 APIC: 00: enabled 1
814 17:39:07.695812 APIC: 05: enabled 1
815 17:39:07.731013 APIC: 01: enabled 1
816 17:39:07.731563 APIC: 02: enabled 1
817 17:39:07.731912 APIC: 07: enabled 1
818 17:39:07.732143 APIC: 06: enabled 1
819 17:39:07.732359 APIC: 03: enabled 1
820 17:39:07.732571 APIC: 04: enabled 1
821 17:39:07.733072 Root Device scanning...
822 17:39:07.733319 scan_static_bus for Root Device
823 17:39:07.733533 DOMAIN: 0000 enabled
824 17:39:07.733742 CPU_CLUSTER: 0 enabled
825 17:39:07.733947 DOMAIN: 0000 scanning...
826 17:39:07.734152 PCI: pci_scan_bus for bus 00
827 17:39:07.734356 PCI: 00:00.0 [8086/0000] ops
828 17:39:07.743561 PCI: 00:00.0 [8086/9a12] enabled
829 17:39:07.744046 PCI: 00:02.0 [8086/0000] bus ops
830 17:39:07.744307 PCI: 00:02.0 [8086/9a40] enabled
831 17:39:07.744530 PCI: 00:04.0 [8086/0000] bus ops
832 17:39:07.746009 PCI: 00:04.0 [8086/9a03] enabled
833 17:39:07.749697 PCI: 00:05.0 [8086/9a19] enabled
834 17:39:07.752971 PCI: 00:07.0 [0000/0000] hidden
835 17:39:07.756137 PCI: 00:08.0 [8086/9a11] enabled
836 17:39:07.758916 PCI: 00:0a.0 [8086/9a0d] disabled
837 17:39:07.762528 PCI: 00:0d.0 [8086/0000] bus ops
838 17:39:07.766256 PCI: 00:0d.0 [8086/9a13] enabled
839 17:39:07.769696 PCI: 00:14.0 [8086/0000] bus ops
840 17:39:07.772867 PCI: 00:14.0 [8086/a0ed] enabled
841 17:39:07.776181 PCI: 00:14.2 [8086/a0ef] enabled
842 17:39:07.779265 PCI: 00:14.3 [8086/0000] bus ops
843 17:39:07.782790 PCI: 00:14.3 [8086/a0f0] enabled
844 17:39:07.786341 PCI: 00:15.0 [8086/0000] bus ops
845 17:39:07.789076 PCI: 00:15.0 [8086/a0e8] enabled
846 17:39:07.792316 PCI: 00:15.1 [8086/0000] bus ops
847 17:39:07.795494 PCI: 00:15.1 [8086/a0e9] enabled
848 17:39:07.798835 PCI: 00:15.2 [8086/0000] bus ops
849 17:39:07.802284 PCI: 00:15.2 [8086/a0ea] enabled
850 17:39:07.805889 PCI: 00:15.3 [8086/0000] bus ops
851 17:39:07.809076 PCI: 00:15.3 [8086/a0eb] enabled
852 17:39:07.812437 PCI: 00:16.0 [8086/0000] ops
853 17:39:07.816369 PCI: 00:16.0 [8086/a0e0] enabled
854 17:39:07.822757 PCI: Static device PCI: 00:17.0 not found, disabling it.
855 17:39:07.825936 PCI: 00:19.0 [8086/0000] bus ops
856 17:39:07.828970 PCI: 00:19.0 [8086/a0c5] disabled
857 17:39:07.832044 PCI: 00:19.1 [8086/0000] bus ops
858 17:39:07.835656 PCI: 00:19.1 [8086/a0c6] enabled
859 17:39:07.838932 PCI: 00:1d.0 [8086/0000] bus ops
860 17:39:07.841921 PCI: 00:1d.0 [8086/a0b0] enabled
861 17:39:07.845425 PCI: 00:1e.0 [8086/0000] ops
862 17:39:07.848975 PCI: 00:1e.0 [8086/a0a8] enabled
863 17:39:07.851629 PCI: 00:1e.2 [8086/0000] bus ops
864 17:39:07.855299 PCI: 00:1e.2 [8086/a0aa] enabled
865 17:39:07.858558 PCI: 00:1e.3 [8086/0000] bus ops
866 17:39:07.861890 PCI: 00:1e.3 [8086/a0ab] enabled
867 17:39:07.865260 PCI: 00:1f.0 [8086/0000] bus ops
868 17:39:07.868191 PCI: 00:1f.0 [8086/a087] enabled
869 17:39:07.868338 RTC Init
870 17:39:07.871789 Set power on after power failure.
871 17:39:07.875615 Disabling Deep S3
872 17:39:07.875762 Disabling Deep S3
873 17:39:07.878573 Disabling Deep S4
874 17:39:07.878732 Disabling Deep S4
875 17:39:07.881895 Disabling Deep S5
876 17:39:07.882065 Disabling Deep S5
877 17:39:07.884915 PCI: 00:1f.2 [0000/0000] hidden
878 17:39:07.888112 PCI: 00:1f.3 [8086/0000] bus ops
879 17:39:07.891592 PCI: 00:1f.3 [8086/a0c8] enabled
880 17:39:07.895070 PCI: 00:1f.5 [8086/0000] bus ops
881 17:39:07.898139 PCI: 00:1f.5 [8086/a0a4] enabled
882 17:39:07.901493 PCI: Leftover static devices:
883 17:39:07.904727 PCI: 00:10.2
884 17:39:07.904941 PCI: 00:10.6
885 17:39:07.908089 PCI: 00:10.7
886 17:39:07.908176 PCI: 00:06.0
887 17:39:07.908228 PCI: 00:07.1
888 17:39:07.912085 PCI: 00:07.2
889 17:39:07.912506 PCI: 00:07.3
890 17:39:07.915456 PCI: 00:09.0
891 17:39:07.915968 PCI: 00:0d.1
892 17:39:07.916262 PCI: 00:0d.2
893 17:39:07.918409 PCI: 00:0d.3
894 17:39:07.918941 PCI: 00:0e.0
895 17:39:07.921989 PCI: 00:12.0
896 17:39:07.922517 PCI: 00:12.6
897 17:39:07.925406 PCI: 00:13.0
898 17:39:07.925925 PCI: 00:14.1
899 17:39:07.926216 PCI: 00:16.1
900 17:39:07.928564 PCI: 00:16.2
901 17:39:07.928944 PCI: 00:16.3
902 17:39:07.931674 PCI: 00:16.4
903 17:39:07.932204 PCI: 00:16.5
904 17:39:07.932517 PCI: 00:17.0
905 17:39:07.935033 PCI: 00:19.2
906 17:39:07.935413 PCI: 00:1e.1
907 17:39:07.938168 PCI: 00:1f.1
908 17:39:07.938552 PCI: 00:1f.4
909 17:39:07.938822 PCI: 00:1f.6
910 17:39:07.941430 PCI: 00:1f.7
911 17:39:07.945224 PCI: Check your devicetree.cb.
912 17:39:07.948090 PCI: 00:02.0 scanning...
913 17:39:07.951554 scan_generic_bus for PCI: 00:02.0
914 17:39:07.954423 scan_generic_bus for PCI: 00:02.0 done
915 17:39:07.957939 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
916 17:39:07.961475 PCI: 00:04.0 scanning...
917 17:39:07.964943 scan_generic_bus for PCI: 00:04.0
918 17:39:07.968208 GENERIC: 0.0 enabled
919 17:39:07.975236 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
920 17:39:07.977952 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
921 17:39:07.981335 PCI: 00:0d.0 scanning...
922 17:39:07.984434 scan_static_bus for PCI: 00:0d.0
923 17:39:07.987690 USB0 port 0 enabled
924 17:39:07.987790 USB0 port 0 scanning...
925 17:39:07.991218 scan_static_bus for USB0 port 0
926 17:39:07.994665 USB3 port 0 enabled
927 17:39:07.997980 USB3 port 1 enabled
928 17:39:07.998464 USB3 port 2 disabled
929 17:39:08.001066 USB3 port 3 disabled
930 17:39:08.004316 USB3 port 0 scanning...
931 17:39:08.007581 scan_static_bus for USB3 port 0
932 17:39:08.010699 scan_static_bus for USB3 port 0 done
933 17:39:08.014308 scan_bus: bus USB3 port 0 finished in 6 msecs
934 17:39:08.017487 USB3 port 1 scanning...
935 17:39:08.020699 scan_static_bus for USB3 port 1
936 17:39:08.024114 scan_static_bus for USB3 port 1 done
937 17:39:08.027393 scan_bus: bus USB3 port 1 finished in 6 msecs
938 17:39:08.034237 scan_static_bus for USB0 port 0 done
939 17:39:08.037800 scan_bus: bus USB0 port 0 finished in 43 msecs
940 17:39:08.040871 scan_static_bus for PCI: 00:0d.0 done
941 17:39:08.047332 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
942 17:39:08.047435 PCI: 00:14.0 scanning...
943 17:39:08.050170 scan_static_bus for PCI: 00:14.0
944 17:39:08.054601 USB0 port 0 enabled
945 17:39:08.057275 USB0 port 0 scanning...
946 17:39:08.060408 scan_static_bus for USB0 port 0
947 17:39:08.060495 USB2 port 0 disabled
948 17:39:08.063892 USB2 port 1 enabled
949 17:39:08.066913 USB2 port 2 enabled
950 17:39:08.066986 USB2 port 3 disabled
951 17:39:08.070984 USB2 port 4 enabled
952 17:39:08.073948 USB2 port 5 disabled
953 17:39:08.074313 USB2 port 6 disabled
954 17:39:08.077535 USB2 port 7 disabled
955 17:39:08.080545 USB2 port 8 disabled
956 17:39:08.080903 USB2 port 9 disabled
957 17:39:08.083724 USB3 port 0 disabled
958 17:39:08.083808 USB3 port 1 enabled
959 17:39:08.087079 USB3 port 2 disabled
960 17:39:08.090302 USB3 port 3 disabled
961 17:39:08.093700 USB2 port 1 scanning...
962 17:39:08.097030 scan_static_bus for USB2 port 1
963 17:39:08.100497 scan_static_bus for USB2 port 1 done
964 17:39:08.103949 scan_bus: bus USB2 port 1 finished in 6 msecs
965 17:39:08.107116 USB2 port 2 scanning...
966 17:39:08.110638 scan_static_bus for USB2 port 2
967 17:39:08.114111 scan_static_bus for USB2 port 2 done
968 17:39:08.117023 scan_bus: bus USB2 port 2 finished in 6 msecs
969 17:39:08.120035 USB2 port 4 scanning...
970 17:39:08.123166 scan_static_bus for USB2 port 4
971 17:39:08.126982 scan_static_bus for USB2 port 4 done
972 17:39:08.133245 scan_bus: bus USB2 port 4 finished in 6 msecs
973 17:39:08.133319 USB3 port 1 scanning...
974 17:39:08.136590 scan_static_bus for USB3 port 1
975 17:39:08.143302 scan_static_bus for USB3 port 1 done
976 17:39:08.146920 scan_bus: bus USB3 port 1 finished in 6 msecs
977 17:39:08.150296 scan_static_bus for USB0 port 0 done
978 17:39:08.153236 scan_bus: bus USB0 port 0 finished in 93 msecs
979 17:39:08.159610 scan_static_bus for PCI: 00:14.0 done
980 17:39:08.162845 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
981 17:39:08.166575 PCI: 00:14.3 scanning...
982 17:39:08.169603 scan_static_bus for PCI: 00:14.3
983 17:39:08.173665 GENERIC: 0.0 enabled
984 17:39:08.176485 scan_static_bus for PCI: 00:14.3 done
985 17:39:08.179944 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
986 17:39:08.183040 PCI: 00:15.0 scanning...
987 17:39:08.186495 scan_static_bus for PCI: 00:15.0
988 17:39:08.189600 I2C: 00:1a enabled
989 17:39:08.189958 I2C: 00:31 enabled
990 17:39:08.192637 I2C: 00:32 enabled
991 17:39:08.196444 scan_static_bus for PCI: 00:15.0 done
992 17:39:08.199267 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
993 17:39:08.202593 PCI: 00:15.1 scanning...
994 17:39:08.206228 scan_static_bus for PCI: 00:15.1
995 17:39:08.210234 I2C: 00:10 enabled
996 17:39:08.213310 scan_static_bus for PCI: 00:15.1 done
997 17:39:08.216066 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
998 17:39:08.219995 PCI: 00:15.2 scanning...
999 17:39:08.223120 scan_static_bus for PCI: 00:15.2
1000 17:39:08.226375 scan_static_bus for PCI: 00:15.2 done
1001 17:39:08.233371 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1002 17:39:08.236052 PCI: 00:15.3 scanning...
1003 17:39:08.239264 scan_static_bus for PCI: 00:15.3
1004 17:39:08.243003 scan_static_bus for PCI: 00:15.3 done
1005 17:39:08.246036 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1006 17:39:08.249246 PCI: 00:19.1 scanning...
1007 17:39:08.253067 scan_static_bus for PCI: 00:19.1
1008 17:39:08.256076 I2C: 00:15 enabled
1009 17:39:08.259658 scan_static_bus for PCI: 00:19.1 done
1010 17:39:08.262686 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1011 17:39:08.266649 PCI: 00:1d.0 scanning...
1012 17:39:08.268746 do_pci_scan_bridge for PCI: 00:1d.0
1013 17:39:08.272828 PCI: pci_scan_bus for bus 01
1014 17:39:08.275931 PCI: 01:00.0 [15b7/5009] enabled
1015 17:39:08.279201 GENERIC: 0.0 enabled
1016 17:39:08.282524 Enabling Common Clock Configuration
1017 17:39:08.285572 L1 Sub-State supported from root port 29
1018 17:39:08.288888 L1 Sub-State Support = 0x5
1019 17:39:08.292606 CommonModeRestoreTime = 0x28
1020 17:39:08.295319 Power On Value = 0x16, Power On Scale = 0x0
1021 17:39:08.299030 ASPM: Enabled L1
1022 17:39:08.302026 PCIe: Max_Payload_Size adjusted to 128
1023 17:39:08.305296 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1024 17:39:08.308705 PCI: 00:1e.2 scanning...
1025 17:39:08.312498 scan_generic_bus for PCI: 00:1e.2
1026 17:39:08.316431 SPI: 00 enabled
1027 17:39:08.319299 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1028 17:39:08.326386 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1029 17:39:08.326833 PCI: 00:1e.3 scanning...
1030 17:39:08.333372 scan_generic_bus for PCI: 00:1e.3
1031 17:39:08.333805 SPI: 00 enabled
1032 17:39:08.339800 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1033 17:39:08.343467 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1034 17:39:08.346305 PCI: 00:1f.0 scanning...
1035 17:39:08.349865 scan_static_bus for PCI: 00:1f.0
1036 17:39:08.353106 PNP: 0c09.0 enabled
1037 17:39:08.353454 PNP: 0c09.0 scanning...
1038 17:39:08.356890 scan_static_bus for PNP: 0c09.0
1039 17:39:08.363432 scan_static_bus for PNP: 0c09.0 done
1040 17:39:08.366506 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1041 17:39:08.369740 scan_static_bus for PCI: 00:1f.0 done
1042 17:39:08.376320 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1043 17:39:08.376777 PCI: 00:1f.2 scanning...
1044 17:39:08.379507 scan_static_bus for PCI: 00:1f.2
1045 17:39:08.382962 GENERIC: 0.0 enabled
1046 17:39:08.386248 GENERIC: 0.0 scanning...
1047 17:39:08.389597 scan_static_bus for GENERIC: 0.0
1048 17:39:08.392914 GENERIC: 0.0 enabled
1049 17:39:08.393251 GENERIC: 1.0 enabled
1050 17:39:08.396015 scan_static_bus for GENERIC: 0.0 done
1051 17:39:08.402855 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1052 17:39:08.406021 scan_static_bus for PCI: 00:1f.2 done
1053 17:39:08.409638 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1054 17:39:08.412863 PCI: 00:1f.3 scanning...
1055 17:39:08.416154 scan_static_bus for PCI: 00:1f.3
1056 17:39:08.419212 scan_static_bus for PCI: 00:1f.3 done
1057 17:39:08.425908 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1058 17:39:08.429493 PCI: 00:1f.5 scanning...
1059 17:39:08.432986 scan_generic_bus for PCI: 00:1f.5
1060 17:39:08.435972 scan_generic_bus for PCI: 00:1f.5 done
1061 17:39:08.439141 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1062 17:39:08.445929 scan_bus: bus DOMAIN: 0000 finished in 716 msecs
1063 17:39:08.449299 scan_static_bus for Root Device done
1064 17:39:08.452206 scan_bus: bus Root Device finished in 735 msecs
1065 17:39:08.455485 done
1066 17:39:08.458837 BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 1295 ms
1067 17:39:08.462072 Chrome EC: UHEPI supported
1068 17:39:08.469808 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1069 17:39:08.476318 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1070 17:39:08.479806 SPI flash protection: WPSW=1 SRP0=0
1071 17:39:08.486308 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1072 17:39:08.489592 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1073 17:39:08.492435 found VGA at PCI: 00:02.0
1074 17:39:08.495950 Setting up VGA for PCI: 00:02.0
1075 17:39:08.503139 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1076 17:39:08.506247 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1077 17:39:08.509770 Allocating resources...
1078 17:39:08.512751 Reading resources...
1079 17:39:08.515960 Root Device read_resources bus 0 link: 0
1080 17:39:08.519181 DOMAIN: 0000 read_resources bus 0 link: 0
1081 17:39:08.525745 PCI: 00:04.0 read_resources bus 1 link: 0
1082 17:39:08.529177 PCI: 00:04.0 read_resources bus 1 link: 0 done
1083 17:39:08.536212 PCI: 00:0d.0 read_resources bus 0 link: 0
1084 17:39:08.539020 USB0 port 0 read_resources bus 0 link: 0
1085 17:39:08.546243 USB0 port 0 read_resources bus 0 link: 0 done
1086 17:39:08.549140 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1087 17:39:08.555614 PCI: 00:14.0 read_resources bus 0 link: 0
1088 17:39:08.559168 USB0 port 0 read_resources bus 0 link: 0
1089 17:39:08.565337 USB0 port 0 read_resources bus 0 link: 0 done
1090 17:39:08.568867 PCI: 00:14.0 read_resources bus 0 link: 0 done
1091 17:39:08.575581 PCI: 00:14.3 read_resources bus 0 link: 0
1092 17:39:08.579534 PCI: 00:14.3 read_resources bus 0 link: 0 done
1093 17:39:08.582297 PCI: 00:15.0 read_resources bus 0 link: 0
1094 17:39:08.590117 PCI: 00:15.0 read_resources bus 0 link: 0 done
1095 17:39:08.593192 PCI: 00:15.1 read_resources bus 0 link: 0
1096 17:39:08.599248 PCI: 00:15.1 read_resources bus 0 link: 0 done
1097 17:39:08.602428 PCI: 00:19.1 read_resources bus 0 link: 0
1098 17:39:08.609866 PCI: 00:19.1 read_resources bus 0 link: 0 done
1099 17:39:08.613530 PCI: 00:1d.0 read_resources bus 1 link: 0
1100 17:39:08.619840 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1101 17:39:08.623191 PCI: 00:1e.2 read_resources bus 2 link: 0
1102 17:39:08.629927 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1103 17:39:08.632909 PCI: 00:1e.3 read_resources bus 3 link: 0
1104 17:39:08.639394 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1105 17:39:08.643020 PCI: 00:1f.0 read_resources bus 0 link: 0
1106 17:39:08.649439 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1107 17:39:08.652990 PCI: 00:1f.2 read_resources bus 0 link: 0
1108 17:39:08.656633 GENERIC: 0.0 read_resources bus 0 link: 0
1109 17:39:08.663302 GENERIC: 0.0 read_resources bus 0 link: 0 done
1110 17:39:08.666455 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1111 17:39:08.673575 DOMAIN: 0000 read_resources bus 0 link: 0 done
1112 17:39:08.677099 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1113 17:39:08.683736 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1114 17:39:08.687231 Root Device read_resources bus 0 link: 0 done
1115 17:39:08.690615 Done reading resources.
1116 17:39:08.696986 Show resources in subtree (Root Device)...After reading.
1117 17:39:08.700239 Root Device child on link 0 DOMAIN: 0000
1118 17:39:08.703182 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1119 17:39:08.714030 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1120 17:39:08.724132 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1121 17:39:08.727254 PCI: 00:00.0
1122 17:39:08.736965 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1123 17:39:08.743459 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1124 17:39:08.753554 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1125 17:39:08.763367 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1126 17:39:08.773597 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1127 17:39:08.783043 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1128 17:39:08.793517 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1129 17:39:08.799785 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1130 17:39:08.810030 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1131 17:39:08.819457 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1132 17:39:08.829943 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1133 17:39:08.839479 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1134 17:39:08.846130 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1135 17:39:08.856219 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1136 17:39:08.866683 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1137 17:39:08.876360 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1138 17:39:08.885905 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1139 17:39:08.896795 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1140 17:39:08.905652 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1141 17:39:08.912885 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1142 17:39:08.915668 PCI: 00:02.0
1143 17:39:08.925650 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1144 17:39:08.935923 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1145 17:39:08.945789 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1146 17:39:08.948773 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1147 17:39:08.958932 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1148 17:39:08.962763 GENERIC: 0.0
1149 17:39:08.962847 PCI: 00:05.0
1150 17:39:08.971923 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1151 17:39:08.978764 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1152 17:39:08.979128 GENERIC: 0.0
1153 17:39:08.982162 PCI: 00:08.0
1154 17:39:08.991748 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1155 17:39:08.991839 PCI: 00:0a.0
1156 17:39:08.995299 PCI: 00:0d.0 child on link 0 USB0 port 0
1157 17:39:09.005421 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1158 17:39:09.011708 USB0 port 0 child on link 0 USB3 port 0
1159 17:39:09.012114 USB3 port 0
1160 17:39:09.015266 USB3 port 1
1161 17:39:09.015624 USB3 port 2
1162 17:39:09.018515 USB3 port 3
1163 17:39:09.022037 PCI: 00:14.0 child on link 0 USB0 port 0
1164 17:39:09.031629 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1165 17:39:09.038342 USB0 port 0 child on link 0 USB2 port 0
1166 17:39:09.038701 USB2 port 0
1167 17:39:09.041723 USB2 port 1
1168 17:39:09.042077 USB2 port 2
1169 17:39:09.044806 USB2 port 3
1170 17:39:09.045156 USB2 port 4
1171 17:39:09.048225 USB2 port 5
1172 17:39:09.048666 USB2 port 6
1173 17:39:09.051625 USB2 port 7
1174 17:39:09.052085 USB2 port 8
1175 17:39:09.055070 USB2 port 9
1176 17:39:09.055422 USB3 port 0
1177 17:39:09.058362 USB3 port 1
1178 17:39:09.061552 USB3 port 2
1179 17:39:09.062027 USB3 port 3
1180 17:39:09.064861 PCI: 00:14.2
1181 17:39:09.075292 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1182 17:39:09.084704 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1183 17:39:09.088392 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1184 17:39:09.097976 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1185 17:39:09.098408 GENERIC: 0.0
1186 17:39:09.104581 PCI: 00:15.0 child on link 0 I2C: 00:1a
1187 17:39:09.114869 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1188 17:39:09.115318 I2C: 00:1a
1189 17:39:09.118077 I2C: 00:31
1190 17:39:09.118429 I2C: 00:32
1191 17:39:09.121126 PCI: 00:15.1 child on link 0 I2C: 00:10
1192 17:39:09.131412 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1193 17:39:09.134722 I2C: 00:10
1194 17:39:09.135171 PCI: 00:15.2
1195 17:39:09.144327 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1196 17:39:09.147678 PCI: 00:15.3
1197 17:39:09.158144 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1198 17:39:09.158591 PCI: 00:16.0
1199 17:39:09.167803 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1200 17:39:09.171133 PCI: 00:19.0
1201 17:39:09.174261 PCI: 00:19.1 child on link 0 I2C: 00:15
1202 17:39:09.184401 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 17:39:09.187530 I2C: 00:15
1204 17:39:09.191090 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1205 17:39:09.200739 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1206 17:39:09.210784 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1207 17:39:09.217254 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1208 17:39:09.220569 GENERIC: 0.0
1209 17:39:09.220647 PCI: 01:00.0
1210 17:39:09.231065 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1211 17:39:09.241025 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1212 17:39:09.244103 PCI: 00:1e.0
1213 17:39:09.253775 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1214 17:39:09.260349 PCI: 00:1e.2 child on link 0 SPI: 00
1215 17:39:09.270447 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1216 17:39:09.270892 SPI: 00
1217 17:39:09.274055 PCI: 00:1e.3 child on link 0 SPI: 00
1218 17:39:09.283636 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1219 17:39:09.286580 SPI: 00
1220 17:39:09.290223 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1221 17:39:09.297316 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1222 17:39:09.300142 PNP: 0c09.0
1223 17:39:09.310232 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1224 17:39:09.313784 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1225 17:39:09.323482 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1226 17:39:09.333260 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1227 17:39:09.336868 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1228 17:39:09.341303 GENERIC: 0.0
1229 17:39:09.341791 GENERIC: 1.0
1230 17:39:09.343662 PCI: 00:1f.3
1231 17:39:09.353178 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1232 17:39:09.363101 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1233 17:39:09.363181 PCI: 00:1f.5
1234 17:39:09.373308 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1235 17:39:09.376691 CPU_CLUSTER: 0 child on link 0 APIC: 00
1236 17:39:09.379728 APIC: 00
1237 17:39:09.380104 APIC: 05
1238 17:39:09.380358 APIC: 01
1239 17:39:09.383377 APIC: 02
1240 17:39:09.383731 APIC: 07
1241 17:39:09.386405 APIC: 06
1242 17:39:09.386756 APIC: 03
1243 17:39:09.387000 APIC: 04
1244 17:39:09.396197 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1245 17:39:09.399377 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1246 17:39:09.406014 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1247 17:39:09.412963 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1248 17:39:09.416717 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1249 17:39:09.422890 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1250 17:39:09.429207 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1251 17:39:09.435720 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1252 17:39:09.442920 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1253 17:39:09.449248 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1254 17:39:09.456077 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1255 17:39:09.465923 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1256 17:39:09.472347 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1257 17:39:09.478992 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1258 17:39:09.482217 DOMAIN: 0000: Resource ranges:
1259 17:39:09.486144 * Base: 1000, Size: 800, Tag: 100
1260 17:39:09.489128 * Base: 1900, Size: e700, Tag: 100
1261 17:39:09.495823 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1262 17:39:09.502178 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1263 17:39:09.508447 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1264 17:39:09.515353 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1265 17:39:09.525180 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1266 17:39:09.532145 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1267 17:39:09.538846 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1268 17:39:09.548468 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1269 17:39:09.554971 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1270 17:39:09.561983 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1271 17:39:09.571983 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1272 17:39:09.578161 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1273 17:39:09.584736 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1274 17:39:09.595173 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1275 17:39:09.601728 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1276 17:39:09.608427 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1277 17:39:09.617949 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1278 17:39:09.624583 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1279 17:39:09.632091 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1280 17:39:09.641724 update_constraints: PCI: 00:00.0 10 base 100000000 limit 4803fffff mem (fixed)
1281 17:39:09.647746 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1282 17:39:09.654267 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1283 17:39:09.664347 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1284 17:39:09.671216 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1285 17:39:09.677815 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1286 17:39:09.680921 DOMAIN: 0000: Resource ranges:
1287 17:39:09.687608 * Base: 7fc00000, Size: 40400000, Tag: 200
1288 17:39:09.690687 * Base: d0000000, Size: 28000000, Tag: 200
1289 17:39:09.693874 * Base: fa000000, Size: 1000000, Tag: 200
1290 17:39:09.697363 * Base: fb001000, Size: 2fff000, Tag: 200
1291 17:39:09.705071 * Base: fe010000, Size: 2e000, Tag: 200
1292 17:39:09.707278 * Base: fe03f000, Size: d41000, Tag: 200
1293 17:39:09.710996 * Base: fed88000, Size: 8000, Tag: 200
1294 17:39:09.714231 * Base: fed93000, Size: d000, Tag: 200
1295 17:39:09.721190 * Base: feda2000, Size: 1e000, Tag: 200
1296 17:39:09.723545 * Base: fede0000, Size: 1220000, Tag: 200
1297 17:39:09.727482 * Base: 480400000, Size: 7b7fc00000, Tag: 100200
1298 17:39:09.733722 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1299 17:39:09.740722 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1300 17:39:09.748257 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1301 17:39:09.754042 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1302 17:39:09.760548 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1303 17:39:09.767186 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1304 17:39:09.773830 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1305 17:39:09.780633 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1306 17:39:09.787413 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1307 17:39:09.793776 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1308 17:39:09.800097 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1309 17:39:09.806663 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1310 17:39:09.814127 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1311 17:39:09.820472 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1312 17:39:09.827040 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1313 17:39:09.833775 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1314 17:39:09.840416 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1315 17:39:09.847224 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1316 17:39:09.853544 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1317 17:39:09.860054 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1318 17:39:09.866790 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1319 17:39:09.873301 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1320 17:39:09.883534 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1321 17:39:09.890308 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1322 17:39:09.893517 PCI: 00:1d.0: Resource ranges:
1323 17:39:09.896401 * Base: 7fc00000, Size: 100000, Tag: 200
1324 17:39:09.903710 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1325 17:39:09.909677 PCI: 01:00.0 20 * [0x7fc04000 - 0x7fc040ff] limit: 7fc040ff mem
1326 17:39:09.919897 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1327 17:39:09.926382 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1328 17:39:09.930321 Root Device assign_resources, bus 0 link: 0
1329 17:39:09.936259 DOMAIN: 0000 assign_resources, bus 0 link: 0
1330 17:39:09.943034 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1331 17:39:09.952896 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1332 17:39:09.959694 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1333 17:39:09.969326 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1334 17:39:09.972907 PCI: 00:04.0 assign_resources, bus 1 link: 0
1335 17:39:09.979275 PCI: 00:04.0 assign_resources, bus 1 link: 0
1336 17:39:09.986140 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1337 17:39:09.995912 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1338 17:39:10.002285 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1339 17:39:10.005642 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1340 17:39:10.012022 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1341 17:39:10.018435 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1342 17:39:10.025774 PCI: 00:14.0 assign_resources, bus 0 link: 0
1343 17:39:10.028849 PCI: 00:14.0 assign_resources, bus 0 link: 0
1344 17:39:10.039055 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1345 17:39:10.045432 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1346 17:39:10.055005 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1347 17:39:10.058416 PCI: 00:14.3 assign_resources, bus 0 link: 0
1348 17:39:10.061590 PCI: 00:14.3 assign_resources, bus 0 link: 0
1349 17:39:10.072043 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1350 17:39:10.075245 PCI: 00:15.0 assign_resources, bus 0 link: 0
1351 17:39:10.081655 PCI: 00:15.0 assign_resources, bus 0 link: 0
1352 17:39:10.088327 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1353 17:39:10.091209 PCI: 00:15.1 assign_resources, bus 0 link: 0
1354 17:39:10.098453 PCI: 00:15.1 assign_resources, bus 0 link: 0
1355 17:39:10.104890 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1356 17:39:10.114833 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1357 17:39:10.121121 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1358 17:39:10.130982 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1359 17:39:10.134765 PCI: 00:19.1 assign_resources, bus 0 link: 0
1360 17:39:10.141230 PCI: 00:19.1 assign_resources, bus 0 link: 0
1361 17:39:10.147902 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1362 17:39:10.157631 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1363 17:39:10.167246 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1364 17:39:10.172125 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1365 17:39:10.180716 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1366 17:39:10.187500 PCI: 01:00.0 20 <- [0x007fc04000 - 0x007fc040ff] size 0x00000100 gran 0x08 mem64
1367 17:39:10.194175 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1368 17:39:10.200381 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1369 17:39:10.204034 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1370 17:39:10.210421 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1371 17:39:10.217400 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1372 17:39:10.224165 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1373 17:39:10.227313 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1374 17:39:10.233348 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1375 17:39:10.236799 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1376 17:39:10.243383 LPC: Trying to open IO window from 800 size 1ff
1377 17:39:10.250287 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1378 17:39:10.260257 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1379 17:39:10.267045 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1380 17:39:10.270124 DOMAIN: 0000 assign_resources, bus 0 link: 0
1381 17:39:10.276583 Root Device assign_resources, bus 0 link: 0
1382 17:39:10.279729 Done setting resources.
1383 17:39:10.286796 Show resources in subtree (Root Device)...After assigning values.
1384 17:39:10.289986 Root Device child on link 0 DOMAIN: 0000
1385 17:39:10.293798 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1386 17:39:10.303294 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1387 17:39:10.313062 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1388 17:39:10.313149 PCI: 00:00.0
1389 17:39:10.323498 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1390 17:39:10.333604 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1391 17:39:10.342863 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1392 17:39:10.352548 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1393 17:39:10.362931 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1394 17:39:10.369954 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1395 17:39:10.379420 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1396 17:39:10.389546 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1397 17:39:10.399153 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1398 17:39:10.409040 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1399 17:39:10.419648 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1400 17:39:10.425974 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1401 17:39:10.435696 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1402 17:39:10.446501 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1403 17:39:10.455355 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1404 17:39:10.465453 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1405 17:39:10.475449 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1406 17:39:10.482362 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1407 17:39:10.492280 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1408 17:39:10.501967 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1409 17:39:10.505354 PCI: 00:02.0
1410 17:39:10.515282 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1411 17:39:10.525002 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1412 17:39:10.535501 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1413 17:39:10.538562 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1414 17:39:10.548501 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1415 17:39:10.551824 GENERIC: 0.0
1416 17:39:10.552316 PCI: 00:05.0
1417 17:39:10.565779 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1418 17:39:10.568039 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1419 17:39:10.571740 GENERIC: 0.0
1420 17:39:10.571839 PCI: 00:08.0
1421 17:39:10.581788 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1422 17:39:10.585108 PCI: 00:0a.0
1423 17:39:10.587971 PCI: 00:0d.0 child on link 0 USB0 port 0
1424 17:39:10.597955 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1425 17:39:10.601603 USB0 port 0 child on link 0 USB3 port 0
1426 17:39:10.604241 USB3 port 0
1427 17:39:10.607572 USB3 port 1
1428 17:39:10.607647 USB3 port 2
1429 17:39:10.611190 USB3 port 3
1430 17:39:10.615362 PCI: 00:14.0 child on link 0 USB0 port 0
1431 17:39:10.624730 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1432 17:39:10.628055 USB0 port 0 child on link 0 USB2 port 0
1433 17:39:10.631724 USB2 port 0
1434 17:39:10.632275 USB2 port 1
1435 17:39:10.634908 USB2 port 2
1436 17:39:10.637971 USB2 port 3
1437 17:39:10.638435 USB2 port 4
1438 17:39:10.641701 USB2 port 5
1439 17:39:10.642073 USB2 port 6
1440 17:39:10.644313 USB2 port 7
1441 17:39:10.644809 USB2 port 8
1442 17:39:10.647806 USB2 port 9
1443 17:39:10.648281 USB3 port 0
1444 17:39:10.651414 USB3 port 1
1445 17:39:10.651964 USB3 port 2
1446 17:39:10.654788 USB3 port 3
1447 17:39:10.655281 PCI: 00:14.2
1448 17:39:10.664529 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1449 17:39:10.678077 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1450 17:39:10.680990 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1451 17:39:10.691030 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1452 17:39:10.694466 GENERIC: 0.0
1453 17:39:10.697665 PCI: 00:15.0 child on link 0 I2C: 00:1a
1454 17:39:10.707514 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1455 17:39:10.708020 I2C: 00:1a
1456 17:39:10.710614 I2C: 00:31
1457 17:39:10.711103 I2C: 00:32
1458 17:39:10.716891 PCI: 00:15.1 child on link 0 I2C: 00:10
1459 17:39:10.727179 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1460 17:39:10.727574 I2C: 00:10
1461 17:39:10.730594 PCI: 00:15.2
1462 17:39:10.740607 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1463 17:39:10.741041 PCI: 00:15.3
1464 17:39:10.754024 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1465 17:39:10.754371 PCI: 00:16.0
1466 17:39:10.764167 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1467 17:39:10.767013 PCI: 00:19.0
1468 17:39:10.771235 PCI: 00:19.1 child on link 0 I2C: 00:15
1469 17:39:10.780462 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1470 17:39:10.783629 I2C: 00:15
1471 17:39:10.786943 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1472 17:39:10.797343 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1473 17:39:10.806971 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1474 17:39:10.816877 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1475 17:39:10.820228 GENERIC: 0.0
1476 17:39:10.820304 PCI: 01:00.0
1477 17:39:10.833503 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1478 17:39:10.843502 PCI: 01:00.0 resource base 7fc04000 size 100 align 12 gran 8 limit 7fc040ff flags 60000201 index 20
1479 17:39:10.844012 PCI: 00:1e.0
1480 17:39:10.856562 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1481 17:39:10.859851 PCI: 00:1e.2 child on link 0 SPI: 00
1482 17:39:10.869524 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1483 17:39:10.869602 SPI: 00
1484 17:39:10.873412 PCI: 00:1e.3 child on link 0 SPI: 00
1485 17:39:10.886431 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1486 17:39:10.887006 SPI: 00
1487 17:39:10.889789 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1488 17:39:10.899602 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1489 17:39:10.900078 PNP: 0c09.0
1490 17:39:10.910032 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1491 17:39:10.913389 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1492 17:39:10.923181 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1493 17:39:10.932607 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1494 17:39:10.935637 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1495 17:39:10.939205 GENERIC: 0.0
1496 17:39:10.943439 GENERIC: 1.0
1497 17:39:10.943951 PCI: 00:1f.3
1498 17:39:10.952873 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1499 17:39:10.962830 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1500 17:39:10.965553 PCI: 00:1f.5
1501 17:39:10.975832 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1502 17:39:10.979048 CPU_CLUSTER: 0 child on link 0 APIC: 00
1503 17:39:10.982623 APIC: 00
1504 17:39:10.982964 APIC: 05
1505 17:39:10.983204 APIC: 01
1506 17:39:10.985883 APIC: 02
1507 17:39:10.986349 APIC: 07
1508 17:39:10.989169 APIC: 06
1509 17:39:10.989623 APIC: 03
1510 17:39:10.989948 APIC: 04
1511 17:39:10.992672 Done allocating resources.
1512 17:39:10.999008 BS: BS_DEV_RESOURCES run times (exec / console): 26 / 2475 ms
1513 17:39:11.005581 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1514 17:39:11.008598 Configure GPIOs for I2S audio on UP4.
1515 17:39:11.015378 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1516 17:39:11.018368 Enabling resources...
1517 17:39:11.021557 PCI: 00:00.0 subsystem <- 8086/9a12
1518 17:39:11.025104 PCI: 00:00.0 cmd <- 06
1519 17:39:11.028789 PCI: 00:02.0 subsystem <- 8086/9a40
1520 17:39:11.031487 PCI: 00:02.0 cmd <- 03
1521 17:39:11.034751 PCI: 00:04.0 subsystem <- 8086/9a03
1522 17:39:11.034830 PCI: 00:04.0 cmd <- 02
1523 17:39:11.041545 PCI: 00:05.0 subsystem <- 8086/9a19
1524 17:39:11.041624 PCI: 00:05.0 cmd <- 02
1525 17:39:11.044975 PCI: 00:08.0 subsystem <- 8086/9a11
1526 17:39:11.048226 PCI: 00:08.0 cmd <- 06
1527 17:39:11.051387 PCI: 00:0d.0 subsystem <- 8086/9a13
1528 17:39:11.055469 PCI: 00:0d.0 cmd <- 02
1529 17:39:11.058401 PCI: 00:14.0 subsystem <- 8086/a0ed
1530 17:39:11.061883 PCI: 00:14.0 cmd <- 02
1531 17:39:11.065210 PCI: 00:14.2 subsystem <- 8086/a0ef
1532 17:39:11.068271 PCI: 00:14.2 cmd <- 02
1533 17:39:11.071405 PCI: 00:14.3 subsystem <- 8086/a0f0
1534 17:39:11.074602 PCI: 00:14.3 cmd <- 02
1535 17:39:11.078211 PCI: 00:15.0 subsystem <- 8086/a0e8
1536 17:39:11.081297 PCI: 00:15.0 cmd <- 02
1537 17:39:11.084561 PCI: 00:15.1 subsystem <- 8086/a0e9
1538 17:39:11.084647 PCI: 00:15.1 cmd <- 02
1539 17:39:11.091389 PCI: 00:15.2 subsystem <- 8086/a0ea
1540 17:39:11.091467 PCI: 00:15.2 cmd <- 02
1541 17:39:11.094734 PCI: 00:15.3 subsystem <- 8086/a0eb
1542 17:39:11.097832 PCI: 00:15.3 cmd <- 02
1543 17:39:11.101211 PCI: 00:16.0 subsystem <- 8086/a0e0
1544 17:39:11.104436 PCI: 00:16.0 cmd <- 02
1545 17:39:11.107474 PCI: 00:19.1 subsystem <- 8086/a0c6
1546 17:39:11.110867 PCI: 00:19.1 cmd <- 02
1547 17:39:11.114252 PCI: 00:1d.0 bridge ctrl <- 0013
1548 17:39:11.117687 PCI: 00:1d.0 subsystem <- 8086/a0b0
1549 17:39:11.120854 PCI: 00:1d.0 cmd <- 06
1550 17:39:11.125121 PCI: 00:1e.0 subsystem <- 8086/a0a8
1551 17:39:11.127682 PCI: 00:1e.0 cmd <- 06
1552 17:39:11.131165 PCI: 00:1e.2 subsystem <- 8086/a0aa
1553 17:39:11.134309 PCI: 00:1e.2 cmd <- 06
1554 17:39:11.138083 PCI: 00:1e.3 subsystem <- 8086/a0ab
1555 17:39:11.138539 PCI: 00:1e.3 cmd <- 02
1556 17:39:11.145078 PCI: 00:1f.0 subsystem <- 8086/a087
1557 17:39:11.145516 PCI: 00:1f.0 cmd <- 407
1558 17:39:11.147804 PCI: 00:1f.3 subsystem <- 8086/a0c8
1559 17:39:11.150962 PCI: 00:1f.3 cmd <- 02
1560 17:39:11.154201 PCI: 00:1f.5 subsystem <- 8086/a0a4
1561 17:39:11.157421 PCI: 00:1f.5 cmd <- 406
1562 17:39:11.162257 PCI: 01:00.0 cmd <- 02
1563 17:39:11.167304 done.
1564 17:39:11.170345 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1565 17:39:11.173693 Initializing devices...
1566 17:39:11.176980 Root Device init
1567 17:39:11.180155 Chrome EC: Set SMI mask to 0x0000000000000000
1568 17:39:11.186658 Chrome EC: clear events_b mask to 0x0000000000000000
1569 17:39:11.193004 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1570 17:39:11.196556 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1571 17:39:11.203643 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1572 17:39:11.209706 Chrome EC: Set WAKE mask to 0x0000000000000000
1573 17:39:11.213117 fw_config match found: DB_USB=USB3_ACTIVE
1574 17:39:11.220110 Configure Right Type-C port orientation for retimer
1575 17:39:11.222767 Root Device init finished in 42 msecs
1576 17:39:11.225923 PCI: 00:00.0 init
1577 17:39:11.229480 CPU TDP = 9 Watts
1578 17:39:11.229552 CPU PL1 = 9 Watts
1579 17:39:11.233063 CPU PL2 = 40 Watts
1580 17:39:11.233136 CPU PL4 = 83 Watts
1581 17:39:11.236001 PCI: 00:00.0 init finished in 8 msecs
1582 17:39:11.240308 PCI: 00:02.0 init
1583 17:39:11.243284 GMA: Found VBT in CBFS
1584 17:39:11.246831 GMA: Found valid VBT in CBFS
1585 17:39:11.250230 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1586 17:39:11.259516 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1587 17:39:11.262897 PCI: 00:02.0 init finished in 18 msecs
1588 17:39:11.266228 PCI: 00:05.0 init
1589 17:39:11.270044 PCI: 00:05.0 init finished in 0 msecs
1590 17:39:11.270498 PCI: 00:08.0 init
1591 17:39:11.276555 PCI: 00:08.0 init finished in 0 msecs
1592 17:39:11.277010 PCI: 00:14.0 init
1593 17:39:11.283257 PCI: 00:14.0 init finished in 0 msecs
1594 17:39:11.283746 PCI: 00:14.2 init
1595 17:39:11.286061 PCI: 00:14.2 init finished in 0 msecs
1596 17:39:11.290110 PCI: 00:15.0 init
1597 17:39:11.293925 I2C bus 0 version 0x3230302a
1598 17:39:11.296715 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1599 17:39:11.299720 PCI: 00:15.0 init finished in 6 msecs
1600 17:39:11.303278 PCI: 00:15.1 init
1601 17:39:11.306917 I2C bus 1 version 0x3230302a
1602 17:39:11.309711 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1603 17:39:11.313242 PCI: 00:15.1 init finished in 6 msecs
1604 17:39:11.316341 PCI: 00:15.2 init
1605 17:39:11.320115 I2C bus 2 version 0x3230302a
1606 17:39:11.322868 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1607 17:39:11.325937 PCI: 00:15.2 init finished in 6 msecs
1608 17:39:11.326053 PCI: 00:15.3 init
1609 17:39:11.329767 I2C bus 3 version 0x3230302a
1610 17:39:11.332937 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1611 17:39:11.339572 PCI: 00:15.3 init finished in 6 msecs
1612 17:39:11.339647 PCI: 00:16.0 init
1613 17:39:11.343182 PCI: 00:16.0 init finished in 0 msecs
1614 17:39:11.346905 PCI: 00:19.1 init
1615 17:39:11.350155 I2C bus 5 version 0x3230302a
1616 17:39:11.353212 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1617 17:39:11.356768 PCI: 00:19.1 init finished in 6 msecs
1618 17:39:11.360142 PCI: 00:1d.0 init
1619 17:39:11.363211 Initializing PCH PCIe bridge.
1620 17:39:11.366689 PCI: 00:1d.0 init finished in 3 msecs
1621 17:39:11.369645 PCI: 00:1f.0 init
1622 17:39:11.372977 IOAPIC: Initializing IOAPIC at 0xfec00000
1623 17:39:11.379780 IOAPIC: Bootstrap Processor Local APIC = 0x00
1624 17:39:11.380256 IOAPIC: ID = 0x02
1625 17:39:11.383334 IOAPIC: Dumping registers
1626 17:39:11.386541 reg 0x0000: 0x02000000
1627 17:39:11.389454 reg 0x0001: 0x00770020
1628 17:39:11.389810 reg 0x0002: 0x00000000
1629 17:39:11.396271 PCI: 00:1f.0 init finished in 21 msecs
1630 17:39:11.396731 PCI: 00:1f.2 init
1631 17:39:11.399191 Disabling ACPI via APMC.
1632 17:39:11.402577 APMC done.
1633 17:39:11.406072 PCI: 00:1f.2 init finished in 5 msecs
1634 17:39:11.417725 PCI: 01:00.0 init
1635 17:39:11.421555 PCI: 01:00.0 init finished in 0 msecs
1636 17:39:11.424204 PNP: 0c09.0 init
1637 17:39:11.427725 Google Chrome EC uptime: 8.294 seconds
1638 17:39:11.434234 Google Chrome AP resets since EC boot: 1
1639 17:39:11.437451 Google Chrome most recent AP reset causes:
1640 17:39:11.440533 0.455: 32775 shutdown: entering G3
1641 17:39:11.447130 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1642 17:39:11.450726 PNP: 0c09.0 init finished in 22 msecs
1643 17:39:11.456121 Devices initialized
1644 17:39:11.459386 Show all devs... After init.
1645 17:39:11.462911 Root Device: enabled 1
1646 17:39:11.463369 DOMAIN: 0000: enabled 1
1647 17:39:11.465992 CPU_CLUSTER: 0: enabled 1
1648 17:39:11.469788 PCI: 00:00.0: enabled 1
1649 17:39:11.472825 PCI: 00:02.0: enabled 1
1650 17:39:11.473167 PCI: 00:04.0: enabled 1
1651 17:39:11.475914 PCI: 00:05.0: enabled 1
1652 17:39:11.479731 PCI: 00:06.0: enabled 0
1653 17:39:11.483148 PCI: 00:07.0: enabled 0
1654 17:39:11.483632 PCI: 00:07.1: enabled 0
1655 17:39:11.486223 PCI: 00:07.2: enabled 0
1656 17:39:11.489513 PCI: 00:07.3: enabled 0
1657 17:39:11.492928 PCI: 00:08.0: enabled 1
1658 17:39:11.493410 PCI: 00:09.0: enabled 0
1659 17:39:11.496456 PCI: 00:0a.0: enabled 0
1660 17:39:11.499550 PCI: 00:0d.0: enabled 1
1661 17:39:11.503155 PCI: 00:0d.1: enabled 0
1662 17:39:11.503544 PCI: 00:0d.2: enabled 0
1663 17:39:11.506236 PCI: 00:0d.3: enabled 0
1664 17:39:11.509295 PCI: 00:0e.0: enabled 0
1665 17:39:11.509670 PCI: 00:10.2: enabled 1
1666 17:39:11.512978 PCI: 00:10.6: enabled 0
1667 17:39:11.515793 PCI: 00:10.7: enabled 0
1668 17:39:11.519182 PCI: 00:12.0: enabled 0
1669 17:39:11.519526 PCI: 00:12.6: enabled 0
1670 17:39:11.522566 PCI: 00:13.0: enabled 0
1671 17:39:11.526156 PCI: 00:14.0: enabled 1
1672 17:39:11.529185 PCI: 00:14.1: enabled 0
1673 17:39:11.529527 PCI: 00:14.2: enabled 1
1674 17:39:11.532363 PCI: 00:14.3: enabled 1
1675 17:39:11.536087 PCI: 00:15.0: enabled 1
1676 17:39:11.539338 PCI: 00:15.1: enabled 1
1677 17:39:11.539683 PCI: 00:15.2: enabled 1
1678 17:39:11.542332 PCI: 00:15.3: enabled 1
1679 17:39:11.545685 PCI: 00:16.0: enabled 1
1680 17:39:11.546025 PCI: 00:16.1: enabled 0
1681 17:39:11.549015 PCI: 00:16.2: enabled 0
1682 17:39:11.552359 PCI: 00:16.3: enabled 0
1683 17:39:11.556204 PCI: 00:16.4: enabled 0
1684 17:39:11.556657 PCI: 00:16.5: enabled 0
1685 17:39:11.559054 PCI: 00:17.0: enabled 0
1686 17:39:11.562585 PCI: 00:19.0: enabled 0
1687 17:39:11.566046 PCI: 00:19.1: enabled 1
1688 17:39:11.566399 PCI: 00:19.2: enabled 0
1689 17:39:11.569083 PCI: 00:1c.0: enabled 1
1690 17:39:11.572662 PCI: 00:1c.1: enabled 0
1691 17:39:11.576174 PCI: 00:1c.2: enabled 0
1692 17:39:11.576635 PCI: 00:1c.3: enabled 0
1693 17:39:11.579125 PCI: 00:1c.4: enabled 0
1694 17:39:11.582260 PCI: 00:1c.5: enabled 0
1695 17:39:11.585633 PCI: 00:1c.6: enabled 1
1696 17:39:11.585993 PCI: 00:1c.7: enabled 0
1697 17:39:11.588867 PCI: 00:1d.0: enabled 1
1698 17:39:11.592058 PCI: 00:1d.1: enabled 0
1699 17:39:11.592131 PCI: 00:1d.2: enabled 1
1700 17:39:11.595550 PCI: 00:1d.3: enabled 0
1701 17:39:11.599172 PCI: 00:1e.0: enabled 1
1702 17:39:11.601860 PCI: 00:1e.1: enabled 0
1703 17:39:11.601933 PCI: 00:1e.2: enabled 1
1704 17:39:11.605581 PCI: 00:1e.3: enabled 1
1705 17:39:11.608515 PCI: 00:1f.0: enabled 1
1706 17:39:11.612110 PCI: 00:1f.1: enabled 0
1707 17:39:11.612532 PCI: 00:1f.2: enabled 1
1708 17:39:11.615276 PCI: 00:1f.3: enabled 1
1709 17:39:11.618810 PCI: 00:1f.4: enabled 0
1710 17:39:11.621812 PCI: 00:1f.5: enabled 1
1711 17:39:11.621873 PCI: 00:1f.6: enabled 0
1712 17:39:11.625540 PCI: 00:1f.7: enabled 0
1713 17:39:11.628581 APIC: 00: enabled 1
1714 17:39:11.628895 GENERIC: 0.0: enabled 1
1715 17:39:11.632115 GENERIC: 0.0: enabled 1
1716 17:39:11.636019 GENERIC: 1.0: enabled 1
1717 17:39:11.639083 GENERIC: 0.0: enabled 1
1718 17:39:11.639471 GENERIC: 1.0: enabled 1
1719 17:39:11.642228 USB0 port 0: enabled 1
1720 17:39:11.645633 GENERIC: 0.0: enabled 1
1721 17:39:11.646097 USB0 port 0: enabled 1
1722 17:39:11.648583 GENERIC: 0.0: enabled 1
1723 17:39:11.652028 I2C: 00:1a: enabled 1
1724 17:39:11.655280 I2C: 00:31: enabled 1
1725 17:39:11.655636 I2C: 00:32: enabled 1
1726 17:39:11.658550 I2C: 00:10: enabled 1
1727 17:39:11.661730 I2C: 00:15: enabled 1
1728 17:39:11.662114 GENERIC: 0.0: enabled 0
1729 17:39:11.665304 GENERIC: 1.0: enabled 0
1730 17:39:11.668558 GENERIC: 0.0: enabled 1
1731 17:39:11.668629 SPI: 00: enabled 1
1732 17:39:11.671635 SPI: 00: enabled 1
1733 17:39:11.675588 PNP: 0c09.0: enabled 1
1734 17:39:11.676229 GENERIC: 0.0: enabled 1
1735 17:39:11.678978 USB3 port 0: enabled 1
1736 17:39:11.681882 USB3 port 1: enabled 1
1737 17:39:11.685381 USB3 port 2: enabled 0
1738 17:39:11.685910 USB3 port 3: enabled 0
1739 17:39:11.688757 USB2 port 0: enabled 0
1740 17:39:11.691734 USB2 port 1: enabled 1
1741 17:39:11.692191 USB2 port 2: enabled 1
1742 17:39:11.694758 USB2 port 3: enabled 0
1743 17:39:11.698397 USB2 port 4: enabled 1
1744 17:39:11.698669 USB2 port 5: enabled 0
1745 17:39:11.701678 USB2 port 6: enabled 0
1746 17:39:11.704881 USB2 port 7: enabled 0
1747 17:39:11.708428 USB2 port 8: enabled 0
1748 17:39:11.708779 USB2 port 9: enabled 0
1749 17:39:11.711537 USB3 port 0: enabled 0
1750 17:39:11.715172 USB3 port 1: enabled 1
1751 17:39:11.715636 USB3 port 2: enabled 0
1752 17:39:11.719102 USB3 port 3: enabled 0
1753 17:39:11.721838 GENERIC: 0.0: enabled 1
1754 17:39:11.725372 GENERIC: 1.0: enabled 1
1755 17:39:11.725840 APIC: 05: enabled 1
1756 17:39:11.728085 APIC: 01: enabled 1
1757 17:39:11.728403 APIC: 02: enabled 1
1758 17:39:11.731495 APIC: 07: enabled 1
1759 17:39:11.734945 APIC: 06: enabled 1
1760 17:39:11.735296 APIC: 03: enabled 1
1761 17:39:11.738156 APIC: 04: enabled 1
1762 17:39:11.741355 PCI: 01:00.0: enabled 1
1763 17:39:11.745484 BS: BS_DEV_INIT run times (exec / console): 29 / 540 ms
1764 17:39:11.751397 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1765 17:39:11.754757 ELOG: NV offset 0xf30000 size 0x1000
1766 17:39:11.761356 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1767 17:39:11.767746 ELOG: Event(17) added with size 13 at 2023-10-20 17:39:11 UTC
1768 17:39:11.774910 ELOG: Event(92) added with size 9 at 2023-10-20 17:39:11 UTC
1769 17:39:11.781594 ELOG: Event(93) added with size 9 at 2023-10-20 17:39:11 UTC
1770 17:39:11.787644 ELOG: Event(9E) added with size 10 at 2023-10-20 17:39:11 UTC
1771 17:39:11.794525 ELOG: Event(9F) added with size 14 at 2023-10-20 17:39:11 UTC
1772 17:39:11.800899 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1773 17:39:11.807527 ELOG: Event(A1) added with size 10 at 2023-10-20 17:39:11 UTC
1774 17:39:11.810431 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1775 17:39:11.817554 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1776 17:39:11.820760 Finalize devices...
1777 17:39:11.821104 Devices finalized
1778 17:39:11.827168 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1779 17:39:11.833842 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1780 17:39:11.837432 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1781 17:39:11.844258 ME: HFSTS1 : 0x80030055
1782 17:39:11.847255 ME: HFSTS2 : 0x30280116
1783 17:39:11.850727 ME: HFSTS3 : 0x00000050
1784 17:39:11.857750 ME: HFSTS4 : 0x00004000
1785 17:39:11.860468 ME: HFSTS5 : 0x00000000
1786 17:39:11.867204 ME: HFSTS6 : 0x40400006
1787 17:39:11.870743 ME: Manufacturing Mode : YES
1788 17:39:11.873882 ME: SPI Protection Mode Enabled : NO
1789 17:39:11.877173 ME: FW Partition Table : OK
1790 17:39:11.880115 ME: Bringup Loader Failure : NO
1791 17:39:11.883421 ME: Firmware Init Complete : NO
1792 17:39:11.886986 ME: Boot Options Present : NO
1793 17:39:11.890421 ME: Update In Progress : NO
1794 17:39:11.896867 ME: D0i3 Support : YES
1795 17:39:11.900241 ME: Low Power State Enabled : NO
1796 17:39:11.903353 ME: CPU Replaced : YES
1797 17:39:11.906628 ME: CPU Replacement Valid : YES
1798 17:39:11.910129 ME: Current Working State : 5
1799 17:39:11.913200 ME: Current Operation State : 1
1800 17:39:11.916718 ME: Current Operation Mode : 3
1801 17:39:11.919914 ME: Error Code : 0
1802 17:39:11.923321 ME: Enhanced Debug Mode : NO
1803 17:39:11.930075 ME: CPU Debug Disabled : YES
1804 17:39:11.933527 ME: TXT Support : NO
1805 17:39:11.940597 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1806 17:39:11.946807 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1807 17:39:11.949972 CBFS: 'fallback/slic' not found.
1808 17:39:11.953224 ACPI: Writing ACPI tables at 76b01000.
1809 17:39:11.955994 ACPI: * FACS
1810 17:39:11.956068 ACPI: * DSDT
1811 17:39:11.959680 Ramoops buffer: 0x100000@0x76a00000.
1812 17:39:11.966364 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1813 17:39:11.970005 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1814 17:39:11.973495 Google Chrome EC: version:
1815 17:39:11.976409 ro: voema_v2.0.10114-a447f03e46
1816 17:39:11.980084 rw: voema_v2.0.10114-a447f03e46
1817 17:39:11.982721 running image: 2
1818 17:39:11.989467 PCI space above 4GB MMIO is at 0x480400000, len = 0x7b7fc00000
1819 17:39:11.993088 ACPI: * FADT
1820 17:39:11.993557 SCI is IRQ9
1821 17:39:11.996132 ACPI: added table 1/32, length now 40
1822 17:39:11.999563 ACPI: * SSDT
1823 17:39:12.002903 Found 1 CPU(s) with 8 core(s) each.
1824 17:39:12.006491 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1825 17:39:12.009507 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1826 17:39:12.016247 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1827 17:39:12.019354 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1828 17:39:12.025935 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1829 17:39:12.029302 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1830 17:39:12.036290 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1831 17:39:12.042939 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1832 17:39:12.049295 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1833 17:39:12.052649 \_SB.PCI0.RP09: Added StorageD3Enable property
1834 17:39:12.055648 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1835 17:39:12.062477 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1836 17:39:12.069444 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1837 17:39:12.072749 PS2K: Passing 80 keymaps to kernel
1838 17:39:12.079416 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1839 17:39:12.085885 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1840 17:39:12.092076 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1841 17:39:12.098854 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1842 17:39:12.105673 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1843 17:39:12.112273 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1844 17:39:12.119426 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1845 17:39:12.125404 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1846 17:39:12.128481 ACPI: added table 2/32, length now 44
1847 17:39:12.128827 ACPI: * MCFG
1848 17:39:12.131994 ACPI: added table 3/32, length now 48
1849 17:39:12.135292 ACPI: * TPM2
1850 17:39:12.139025 TPM2 log created at 0x769f0000
1851 17:39:12.141883 ACPI: added table 4/32, length now 52
1852 17:39:12.142236 ACPI: * MADT
1853 17:39:12.145427 SCI is IRQ9
1854 17:39:12.148701 ACPI: added table 5/32, length now 56
1855 17:39:12.152368 current = 76b09850
1856 17:39:12.152827 ACPI: * DMAR
1857 17:39:12.155750 ACPI: added table 6/32, length now 60
1858 17:39:12.159090 ACPI: added table 7/32, length now 64
1859 17:39:12.161808 ACPI: * HPET
1860 17:39:12.165071 ACPI: added table 8/32, length now 68
1861 17:39:12.165445 ACPI: done.
1862 17:39:12.168588 ACPI tables: 35216 bytes.
1863 17:39:12.171558 smbios_write_tables: 769ef000
1864 17:39:12.174945 EC returned error result code 3
1865 17:39:12.182394 Couldn't obtain OEM name from CBI
1866 17:39:12.182748 Create SMBIOS type 16
1867 17:39:12.185866 Create SMBIOS type 17
1868 17:39:12.189295 GENERIC: 0.0 (WIFI Device)
1869 17:39:12.189745 SMBIOS tables: 1734 bytes.
1870 17:39:12.195674 Writing table forward entry at 0x00000500
1871 17:39:12.202225 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1872 17:39:12.205658 Writing coreboot table at 0x76b25000
1873 17:39:12.212095 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1874 17:39:12.215530 1. 0000000000001000-000000000009ffff: RAM
1875 17:39:12.218736 2. 00000000000a0000-00000000000fffff: RESERVED
1876 17:39:12.225552 3. 0000000000100000-00000000769eefff: RAM
1877 17:39:12.228703 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1878 17:39:12.235192 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1879 17:39:12.241907 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1880 17:39:12.245205 7. 0000000077000000-000000007fbfffff: RESERVED
1881 17:39:12.251824 8. 00000000c0000000-00000000cfffffff: RESERVED
1882 17:39:12.255106 9. 00000000f8000000-00000000f9ffffff: RESERVED
1883 17:39:12.258246 10. 00000000fb000000-00000000fb000fff: RESERVED
1884 17:39:12.264978 11. 00000000fe000000-00000000fe00ffff: RESERVED
1885 17:39:12.268265 12. 00000000fed80000-00000000fed87fff: RESERVED
1886 17:39:12.274737 13. 00000000fed90000-00000000fed92fff: RESERVED
1887 17:39:12.278111 14. 00000000feda0000-00000000feda1fff: RESERVED
1888 17:39:12.285194 15. 00000000fedc0000-00000000feddffff: RESERVED
1889 17:39:12.288485 16. 0000000100000000-00000004803fffff: RAM
1890 17:39:12.291825 Passing 4 GPIOs to payload:
1891 17:39:12.295463 NAME | PORT | POLARITY | VALUE
1892 17:39:12.301684 lid | undefined | high | high
1893 17:39:12.308150 power | undefined | high | low
1894 17:39:12.311065 oprom | undefined | high | low
1895 17:39:12.318571 EC in RW | 0x000000e5 | high | high
1896 17:39:12.324354 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 1314
1897 17:39:12.327733 coreboot table: 1576 bytes.
1898 17:39:12.331318 IMD ROOT 0. 0x76fff000 0x00001000
1899 17:39:12.334483 IMD SMALL 1. 0x76ffe000 0x00001000
1900 17:39:12.338374 FSP MEMORY 2. 0x76c4e000 0x003b0000
1901 17:39:12.341007 VPD 3. 0x76c4d000 0x00000367
1902 17:39:12.344049 RO MCACHE 4. 0x76c4c000 0x00000fdc
1903 17:39:12.347528 CONSOLE 5. 0x76c2c000 0x00020000
1904 17:39:12.354423 FMAP 6. 0x76c2b000 0x00000578
1905 17:39:12.357450 TIME STAMP 7. 0x76c2a000 0x00000910
1906 17:39:12.360820 VBOOT WORK 8. 0x76c16000 0x00014000
1907 17:39:12.364148 ROMSTG STCK 9. 0x76c15000 0x00001000
1908 17:39:12.367126 AFTER CAR 10. 0x76c0a000 0x0000b000
1909 17:39:12.370474 RAMSTAGE 11. 0x76b97000 0x00073000
1910 17:39:12.373552 REFCODE 12. 0x76b42000 0x00055000
1911 17:39:12.380648 SMM BACKUP 13. 0x76b32000 0x00010000
1912 17:39:12.383364 4f444749 14. 0x76b30000 0x00002000
1913 17:39:12.386476 EXT VBT15. 0x76b2d000 0x0000219f
1914 17:39:12.389892 COREBOOT 16. 0x76b25000 0x00008000
1915 17:39:12.393229 ACPI 17. 0x76b01000 0x00024000
1916 17:39:12.397000 ACPI GNVS 18. 0x76b00000 0x00001000
1917 17:39:12.400307 RAMOOPS 19. 0x76a00000 0x00100000
1918 17:39:12.403445 TPM2 TCGLOG20. 0x769f0000 0x00010000
1919 17:39:12.407098 SMBIOS 21. 0x769ef000 0x00000800
1920 17:39:12.409890 IMD small region:
1921 17:39:12.413217 IMD ROOT 0. 0x76ffec00 0x00000400
1922 17:39:12.416178 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1923 17:39:12.422791 POWER STATE 2. 0x76ffeb80 0x00000044
1924 17:39:12.426092 ROMSTAGE 3. 0x76ffeb60 0x00000004
1925 17:39:12.429630 MEM INFO 4. 0x76ffe980 0x000001e0
1926 17:39:12.436164 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1927 17:39:12.440181 MTRR: Physical address space:
1928 17:39:12.446828 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1929 17:39:12.449940 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1930 17:39:12.456387 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1931 17:39:12.463292 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1932 17:39:12.469205 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1933 17:39:12.475881 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1934 17:39:12.482646 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
1935 17:39:12.486240 MTRR: Fixed MSR 0x250 0x0606060606060606
1936 17:39:12.489361 MTRR: Fixed MSR 0x258 0x0606060606060606
1937 17:39:12.495392 MTRR: Fixed MSR 0x259 0x0000000000000000
1938 17:39:12.499081 MTRR: Fixed MSR 0x268 0x0606060606060606
1939 17:39:12.503109 MTRR: Fixed MSR 0x269 0x0606060606060606
1940 17:39:12.505821 MTRR: Fixed MSR 0x26a 0x0606060606060606
1941 17:39:12.512186 MTRR: Fixed MSR 0x26b 0x0606060606060606
1942 17:39:12.515845 MTRR: Fixed MSR 0x26c 0x0606060606060606
1943 17:39:12.519229 MTRR: Fixed MSR 0x26d 0x0606060606060606
1944 17:39:12.522435 MTRR: Fixed MSR 0x26e 0x0606060606060606
1945 17:39:12.525819 MTRR: Fixed MSR 0x26f 0x0606060606060606
1946 17:39:12.531344 call enable_fixed_mtrr()
1947 17:39:12.534239 CPU physical address size: 39 bits
1948 17:39:12.540776 MTRR: default type WB/UC MTRR counts: 6/7.
1949 17:39:12.544254 MTRR: WB selected as default type.
1950 17:39:12.551107 MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1951 17:39:12.554524 MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1952 17:39:12.561305 MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1953 17:39:12.567518 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
1954 17:39:12.574273 MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1955 17:39:12.581336 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
1956 17:39:12.588298 MTRR: Fixed MSR 0x250 0x0606060606060606
1957 17:39:12.591414 MTRR: Fixed MSR 0x258 0x0606060606060606
1958 17:39:12.594485 MTRR: Fixed MSR 0x259 0x0000000000000000
1959 17:39:12.597824 MTRR: Fixed MSR 0x268 0x0606060606060606
1960 17:39:12.604294 MTRR: Fixed MSR 0x269 0x0606060606060606
1961 17:39:12.607601 MTRR: Fixed MSR 0x26a 0x0606060606060606
1962 17:39:12.610552 MTRR: Fixed MSR 0x26b 0x0606060606060606
1963 17:39:12.614000 MTRR: Fixed MSR 0x26c 0x0606060606060606
1964 17:39:12.620654 MTRR: Fixed MSR 0x26d 0x0606060606060606
1965 17:39:12.624701 MTRR: Fixed MSR 0x26e 0x0606060606060606
1966 17:39:12.627574 MTRR: Fixed MSR 0x26f 0x0606060606060606
1967 17:39:12.627656
1968 17:39:12.632246 MTRR check
1969 17:39:12.635145 call enable_fixed_mtrr()
1970 17:39:12.635491 Fixed MTRRs : Enabled
1971 17:39:12.638398 Variable MTRRs: Enabled
1972 17:39:12.638472
1973 17:39:12.641713 MTRR: Fixed MSR 0x250 0x0606060606060606
1974 17:39:12.648221 MTRR: Fixed MSR 0x250 0x0606060606060606
1975 17:39:12.651567 MTRR: Fixed MSR 0x258 0x0606060606060606
1976 17:39:12.654589 MTRR: Fixed MSR 0x259 0x0000000000000000
1977 17:39:12.658327 MTRR: Fixed MSR 0x268 0x0606060606060606
1978 17:39:12.664560 MTRR: Fixed MSR 0x269 0x0606060606060606
1979 17:39:12.668185 MTRR: Fixed MSR 0x26a 0x0606060606060606
1980 17:39:12.671062 MTRR: Fixed MSR 0x26b 0x0606060606060606
1981 17:39:12.674279 MTRR: Fixed MSR 0x26c 0x0606060606060606
1982 17:39:12.680965 MTRR: Fixed MSR 0x26d 0x0606060606060606
1983 17:39:12.684374 MTRR: Fixed MSR 0x26e 0x0606060606060606
1984 17:39:12.687096 MTRR: Fixed MSR 0x26f 0x0606060606060606
1985 17:39:12.695366 MTRR: Fixed MSR 0x258 0x0606060606060606
1986 17:39:12.698778 MTRR: Fixed MSR 0x259 0x0000000000000000
1987 17:39:12.702025 MTRR: Fixed MSR 0x268 0x0606060606060606
1988 17:39:12.704860 MTRR: Fixed MSR 0x269 0x0606060606060606
1989 17:39:12.711045 MTRR: Fixed MSR 0x26a 0x0606060606060606
1990 17:39:12.714591 MTRR: Fixed MSR 0x26b 0x0606060606060606
1991 17:39:12.718113 MTRR: Fixed MSR 0x26c 0x0606060606060606
1992 17:39:12.721536 MTRR: Fixed MSR 0x26d 0x0606060606060606
1993 17:39:12.728023 MTRR: Fixed MSR 0x26e 0x0606060606060606
1994 17:39:12.731491 MTRR: Fixed MSR 0x26f 0x0606060606060606
1995 17:39:12.734986 call enable_fixed_mtrr()
1996 17:39:12.738079 call enable_fixed_mtrr()
1997 17:39:12.741714 MTRR: Fixed MSR 0x250 0x0606060606060606
1998 17:39:12.744895 MTRR: Fixed MSR 0x250 0x0606060606060606
1999 17:39:12.751121 MTRR: Fixed MSR 0x258 0x0606060606060606
2000 17:39:12.754851 MTRR: Fixed MSR 0x259 0x0000000000000000
2001 17:39:12.757831 MTRR: Fixed MSR 0x268 0x0606060606060606
2002 17:39:12.761276 MTRR: Fixed MSR 0x269 0x0606060606060606
2003 17:39:12.768418 MTRR: Fixed MSR 0x26a 0x0606060606060606
2004 17:39:12.771273 MTRR: Fixed MSR 0x26b 0x0606060606060606
2005 17:39:12.774330 MTRR: Fixed MSR 0x26c 0x0606060606060606
2006 17:39:12.778217 MTRR: Fixed MSR 0x26d 0x0606060606060606
2007 17:39:12.781345 MTRR: Fixed MSR 0x26e 0x0606060606060606
2008 17:39:12.787494 MTRR: Fixed MSR 0x26f 0x0606060606060606
2009 17:39:12.791448 MTRR: Fixed MSR 0x258 0x0606060606060606
2010 17:39:12.794762 call enable_fixed_mtrr()
2011 17:39:12.798227 MTRR: Fixed MSR 0x259 0x0000000000000000
2012 17:39:12.804628 MTRR: Fixed MSR 0x268 0x0606060606060606
2013 17:39:12.807599 MTRR: Fixed MSR 0x269 0x0606060606060606
2014 17:39:12.810996 MTRR: Fixed MSR 0x26a 0x0606060606060606
2015 17:39:12.814573 MTRR: Fixed MSR 0x26b 0x0606060606060606
2016 17:39:12.821105 MTRR: Fixed MSR 0x26c 0x0606060606060606
2017 17:39:12.824550 MTRR: Fixed MSR 0x26d 0x0606060606060606
2018 17:39:12.827484 MTRR: Fixed MSR 0x26e 0x0606060606060606
2019 17:39:12.830644 MTRR: Fixed MSR 0x26f 0x0606060606060606
2020 17:39:12.835853 CPU physical address size: 39 bits
2021 17:39:12.842303 call enable_fixed_mtrr()
2022 17:39:12.845388 CPU physical address size: 39 bits
2023 17:39:12.853108 BS: BS_WRITE_TABLES exit times (exec / console): 52 / 151 ms
2024 17:39:12.855835 MTRR: Fixed MSR 0x250 0x0606060606060606
2025 17:39:12.862208 MTRR: Fixed MSR 0x250 0x0606060606060606
2026 17:39:12.865485 Checking cr50 for pending updates
2027 17:39:12.869978 CPU physical address size: 39 bits
2028 17:39:12.873210 CPU physical address size: 39 bits
2029 17:39:12.876755 CPU physical address size: 39 bits
2030 17:39:12.879800 Reading cr50 TPM mode
2031 17:39:12.883493 MTRR: Fixed MSR 0x258 0x0606060606060606
2032 17:39:12.887072 MTRR: Fixed MSR 0x258 0x0606060606060606
2033 17:39:12.893397 MTRR: Fixed MSR 0x259 0x0000000000000000
2034 17:39:12.897020 MTRR: Fixed MSR 0x268 0x0606060606060606
2035 17:39:12.900069 MTRR: Fixed MSR 0x269 0x0606060606060606
2036 17:39:12.903120 MTRR: Fixed MSR 0x26a 0x0606060606060606
2037 17:39:12.909643 MTRR: Fixed MSR 0x26b 0x0606060606060606
2038 17:39:12.912811 MTRR: Fixed MSR 0x26c 0x0606060606060606
2039 17:39:12.915971 MTRR: Fixed MSR 0x26d 0x0606060606060606
2040 17:39:12.919956 MTRR: Fixed MSR 0x26e 0x0606060606060606
2041 17:39:12.926408 MTRR: Fixed MSR 0x26f 0x0606060606060606
2042 17:39:12.929593 MTRR: Fixed MSR 0x259 0x0000000000000000
2043 17:39:12.936112 MTRR: Fixed MSR 0x268 0x0606060606060606
2044 17:39:12.939079 MTRR: Fixed MSR 0x269 0x0606060606060606
2045 17:39:12.943019 MTRR: Fixed MSR 0x26a 0x0606060606060606
2046 17:39:12.946310 MTRR: Fixed MSR 0x26b 0x0606060606060606
2047 17:39:12.952871 MTRR: Fixed MSR 0x26c 0x0606060606060606
2048 17:39:12.957020 MTRR: Fixed MSR 0x26d 0x0606060606060606
2049 17:39:12.959465 MTRR: Fixed MSR 0x26e 0x0606060606060606
2050 17:39:12.963213 MTRR: Fixed MSR 0x26f 0x0606060606060606
2051 17:39:12.967304 call enable_fixed_mtrr()
2052 17:39:12.970412 call enable_fixed_mtrr()
2053 17:39:12.977193 BS: BS_PAYLOAD_LOAD entry times (exec / console): 25 / 6 ms
2054 17:39:12.980157 CPU physical address size: 39 bits
2055 17:39:12.983740 CPU physical address size: 39 bits
2056 17:39:12.994263 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2057 17:39:12.997120 Checking segment from ROM address 0xffc02b38
2058 17:39:13.000385 Checking segment from ROM address 0xffc02b54
2059 17:39:13.007151 Loading segment from ROM address 0xffc02b38
2060 17:39:13.007246 code (compression=0)
2061 17:39:13.016865 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2062 17:39:13.026776 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2063 17:39:13.027250 it's not compressed!
2064 17:39:13.168250 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2065 17:39:13.175147 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2066 17:39:13.181659 Loading segment from ROM address 0xffc02b54
2067 17:39:13.184376 Entry Point 0x30000000
2068 17:39:13.184724 Loaded segments
2069 17:39:13.190851 BS: BS_PAYLOAD_LOAD run times (exec / console): 145 / 63 ms
2070 17:39:13.236320 Finalizing chipset.
2071 17:39:13.239942 Finalizing SMM.
2072 17:39:13.240465 APMC done.
2073 17:39:13.246260 BS: BS_PAYLOAD_LOAD exit times (exec / console): 44 / 5 ms
2074 17:39:13.249538 mp_park_aps done after 0 msecs.
2075 17:39:13.252784 Jumping to boot code at 0x30000000(0x76b25000)
2076 17:39:13.262805 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2077 17:39:13.263418
2078 17:39:13.263847
2079 17:39:13.264230
2080 17:39:13.266133 Starting depthcharge on Voema...
2081 17:39:13.267066 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2082 17:39:13.267533 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2083 17:39:13.267944 Setting prompt string to ['volteer:']
2084 17:39:13.268337 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2085 17:39:13.269468
2086 17:39:13.276112 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2087 17:39:13.276533
2088 17:39:13.282450 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2089 17:39:13.282801
2090 17:39:13.288953 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2091 17:39:13.289309
2092 17:39:13.292422 Failed to find eMMC card reader
2093 17:39:13.292832
2094 17:39:13.293212 Wipe memory regions:
2095 17:39:13.295700
2096 17:39:13.298854 [0x00000000001000, 0x000000000a0000)
2097 17:39:13.299203
2098 17:39:13.302238 [0x00000000100000, 0x00000030000000)
2099 17:39:13.338110
2100 17:39:13.340990 [0x00000032662db0, 0x000000769ef000)
2101 17:39:13.391174
2102 17:39:13.394442 [0x00000100000000, 0x00000480400000)
2103 17:39:14.026139
2104 17:39:14.029406 ec_init: CrosEC protocol v3 supported (256, 256)
2105 17:39:14.460366
2106 17:39:14.460830 R8152: Initializing
2107 17:39:14.461095
2108 17:39:14.463740 Version 9 (ocp_data = 6010)
2109 17:39:14.464139
2110 17:39:14.467366 R8152: Done initializing
2111 17:39:14.467709
2112 17:39:14.470486 Adding net device
2113 17:39:14.771428
2114 17:39:14.775625 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2115 17:39:14.776140
2116 17:39:14.776414
2117 17:39:14.776651
2118 17:39:14.778770 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2120 17:39:14.879994 volteer: tftpboot 10.108.97.116 11831827/tftp-deploy-z718qvo2/kernel/bzImage 11831827/tftp-deploy-z718qvo2/kernel/cmdline 11831827/tftp-deploy-z718qvo2/ramdisk/ramdisk.cpio.gz
2121 17:39:14.880535 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2122 17:39:14.880862 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2123 17:39:14.885217 tftpboot 10.108.97.116 11831827/tftp-deploy-z718qvo2/kernel/bzIploy-z718qvo2/kernel/cmdline 11831827/tftp-deploy-z718qvo2/ramdisk/ramdisk.cpio.gz
2124 17:39:14.885575
2125 17:39:14.885818 Waiting for link
2126 17:39:15.088573
2127 17:39:15.089044 done.
2128 17:39:15.089318
2129 17:39:15.089556 MAC: 00:e0:4c:68:05:b8
2130 17:39:15.089786
2131 17:39:15.091829 Sending DHCP discover... done.
2132 17:39:15.092205
2133 17:39:15.095121 Waiting for reply... done.
2134 17:39:15.095462
2135 17:39:15.098386 Sending DHCP request... done.
2136 17:39:15.098542
2137 17:39:15.102359 Waiting for reply... done.
2138 17:39:15.102816
2139 17:39:15.105031 My ip is 192.168.201.11
2140 17:39:15.105375
2141 17:39:15.108996 The DHCP server ip is 192.168.201.1
2142 17:39:15.109453
2143 17:39:15.111840 TFTP server IP predefined by user: 10.108.97.116
2144 17:39:15.112185
2145 17:39:15.119214 Bootfile predefined by user: 11831827/tftp-deploy-z718qvo2/kernel/bzImage
2146 17:39:15.119670
2147 17:39:15.121687 Sending tftp read request... done.
2148 17:39:15.122064
2149 17:39:15.130183 Waiting for the transfer...
2150 17:39:15.130648
2151 17:39:15.354384 00000000 ################################################################
2152 17:39:15.354541
2153 17:39:15.576749 00080000 ################################################################
2154 17:39:15.576911
2155 17:39:15.801439 00100000 ################################################################
2156 17:39:15.801590
2157 17:39:16.026290 00180000 ################################################################
2158 17:39:16.026435
2159 17:39:16.250073 00200000 ################################################################
2160 17:39:16.250221
2161 17:39:16.473424 00280000 ################################################################
2162 17:39:16.473576
2163 17:39:16.696152 00300000 ################################################################
2164 17:39:16.696298
2165 17:39:16.919959 00380000 ################################################################
2166 17:39:16.920112
2167 17:39:17.143193 00400000 ################################################################
2168 17:39:17.143342
2169 17:39:17.365961 00480000 ################################################################
2170 17:39:17.366137
2171 17:39:17.587834 00500000 ################################################################
2172 17:39:17.587991
2173 17:39:17.811409 00580000 ################################################################
2174 17:39:17.811556
2175 17:39:18.035226 00600000 ################################################################
2176 17:39:18.035368
2177 17:39:18.258029 00680000 ################################################################
2178 17:39:18.258170
2179 17:39:18.482356 00700000 ################################################################
2180 17:39:18.482498
2181 17:39:18.705605 00780000 ################################################################
2182 17:39:18.705744
2183 17:39:18.755992 00800000 ############### done.
2184 17:39:18.756085
2185 17:39:18.759127 The bootfile was 8507280 bytes long.
2186 17:39:18.759183
2187 17:39:18.762321 Sending tftp read request... done.
2188 17:39:18.762382
2189 17:39:18.766318 Waiting for the transfer...
2190 17:39:18.766377
2191 17:39:18.990514 00000000 ################################################################
2192 17:39:18.990672
2193 17:39:19.214468 00080000 ################################################################
2194 17:39:19.214608
2195 17:39:19.437359 00100000 ################################################################
2196 17:39:19.437506
2197 17:39:19.660599 00180000 ################################################################
2198 17:39:19.660756
2199 17:39:19.884293 00200000 ################################################################
2200 17:39:19.884441
2201 17:39:20.108913 00280000 ################################################################
2202 17:39:20.109068
2203 17:39:20.331514 00300000 ################################################################
2204 17:39:20.331668
2205 17:39:20.557114 00380000 ################################################################
2206 17:39:20.557257
2207 17:39:20.780018 00400000 ################################################################
2208 17:39:20.780162
2209 17:39:21.002988 00480000 ################################################################
2210 17:39:21.003134
2211 17:39:21.226657 00500000 ################################################################
2212 17:39:21.226800
2213 17:39:21.450517 00580000 ################################################################
2214 17:39:21.450661
2215 17:39:21.673223 00600000 ################################################################
2216 17:39:21.673363
2217 17:39:21.898965 00680000 ################################################################
2218 17:39:21.899133
2219 17:39:22.123134 00700000 ################################################################
2220 17:39:22.123280
2221 17:39:22.346168 00780000 ################################################################
2222 17:39:22.346316
2223 17:39:22.534357 00800000 ####################################################### done.
2224 17:39:22.534510
2225 17:39:22.537742 Sending tftp read request... done.
2226 17:39:22.537835
2227 17:39:22.540834 Waiting for the transfer...
2228 17:39:22.540898
2229 17:39:22.540949 00000000 # done.
2230 17:39:22.544328
2231 17:39:22.551070 Command line loaded dynamically from TFTP file: 11831827/tftp-deploy-z718qvo2/kernel/cmdline
2232 17:39:22.551500
2233 17:39:22.567587 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=10.108.97.116
2234 17:39:22.573065
2235 17:39:22.575702 Shutting down all USB controllers.
2236 17:39:22.576077
2237 17:39:22.576318 Removing current net device
2238 17:39:22.576532
2239 17:39:22.579527 Finalizing coreboot
2240 17:39:22.580010
2241 17:39:22.586435 Exiting depthcharge with code 4 at timestamp: 17872905
2242 17:39:22.586889
2243 17:39:22.587143
2244 17:39:22.587361 Starting kernel ...
2245 17:39:22.587570
2246 17:39:22.587810
2247 17:39:22.588691 end: 2.2.4 bootloader-commands (duration 00:00:09) [common]
2248 17:39:22.589048 start: 2.2.5 auto-login-action (timeout 00:04:35) [common]
2249 17:39:22.589312 Setting prompt string to ['Linux version [0-9]']
2250 17:39:22.589553 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2251 17:39:22.589793 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2253 17:43:57.589830 end: 2.2.5 auto-login-action (duration 00:04:35) [common]
2255 17:43:57.590635 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 275 seconds'
2257 17:43:57.591229 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2260 17:43:57.592316 end: 2 depthcharge-action (duration 00:05:00) [common]
2262 17:43:57.593144 Cleaning after the job
2263 17:43:57.593477 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/ramdisk
2264 17:43:57.594967 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/kernel
2265 17:43:57.595796 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831827/tftp-deploy-z718qvo2/modules
2266 17:43:57.596050 start: 5.1 power-off (timeout 00:00:30) [common]
2267 17:43:57.596181 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-16' '--port=1' '--command=off'
2268 17:43:57.682475 >> Command sent successfully.
2269 17:43:57.685121 Returned 0 in 0 seconds
2270 17:43:57.785771 end: 5.1 power-off (duration 00:00:00) [common]
2272 17:43:57.786993 start: 5.2 read-feedback (timeout 00:10:00) [common]
2273 17:43:57.787829 Listened to connection for namespace 'common' for up to 1s
2274 17:43:58.787810 Finalising connection for namespace 'common'
2275 17:43:58.787951 Disconnecting from shell: Finalise
2276 17:43:58.788016
2277 17:43:58.888572 end: 5.2 read-feedback (duration 00:00:01) [common]
2278 17:43:58.889091 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11831827
2279 17:43:58.902014 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11831827
2280 17:43:58.902173 JobError: Your job cannot terminate cleanly.