Boot log: asus-C436FA-Flip-hatch
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 17:48:21.574284 lava-dispatcher, installed at version: 2023.08
2 17:48:21.574504 start: 0 validate
3 17:48:21.574647 Start time: 2023-10-20 17:48:21.574639+00:00 (UTC)
4 17:48:21.574772 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:48:21.574904 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Famd64%2Finitrd.cpio.gz exists
6 17:48:21.846339 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:48:21.847049 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4.302-cip78-rt45-338-gf468de833aa13%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 17:48:25.747442 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:48:25.747620 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 17:48:31.424841 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:48:31.425588 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv4.4.302-cip78-rt45-338-gf468de833aa13%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 17:48:31.704209 validate duration: 10.13
14 17:48:31.705438 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:48:31.705941 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:48:31.706377 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:48:31.707007 Not decompressing ramdisk as can be used compressed.
18 17:48:31.707444 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/amd64/initrd.cpio.gz
19 17:48:31.707782 saving as /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/ramdisk/initrd.cpio.gz
20 17:48:31.708111 total size: 5432480 (5 MB)
21 17:48:33.835063 progress 0 % (0 MB)
22 17:48:33.848130 progress 5 % (0 MB)
23 17:48:33.856152 progress 10 % (0 MB)
24 17:48:33.861027 progress 15 % (0 MB)
25 17:48:33.864605 progress 20 % (1 MB)
26 17:48:33.867321 progress 25 % (1 MB)
27 17:48:33.869945 progress 30 % (1 MB)
28 17:48:33.872441 progress 35 % (1 MB)
29 17:48:33.874669 progress 40 % (2 MB)
30 17:48:33.876644 progress 45 % (2 MB)
31 17:48:33.878604 progress 50 % (2 MB)
32 17:48:33.880676 progress 55 % (2 MB)
33 17:48:33.882402 progress 60 % (3 MB)
34 17:48:33.884134 progress 65 % (3 MB)
35 17:48:33.885962 progress 70 % (3 MB)
36 17:48:33.887593 progress 75 % (3 MB)
37 17:48:33.889191 progress 80 % (4 MB)
38 17:48:33.890707 progress 85 % (4 MB)
39 17:48:33.892344 progress 90 % (4 MB)
40 17:48:33.893785 progress 95 % (4 MB)
41 17:48:33.895246 progress 100 % (5 MB)
42 17:48:33.895457 5 MB downloaded in 2.19 s (2.37 MB/s)
43 17:48:33.895606 end: 1.1.1 http-download (duration 00:00:02) [common]
45 17:48:33.895845 end: 1.1 download-retry (duration 00:00:02) [common]
46 17:48:33.895932 start: 1.2 download-retry (timeout 00:09:58) [common]
47 17:48:33.896019 start: 1.2.1 http-download (timeout 00:09:58) [common]
48 17:48:33.896165 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip78-rt45-338-gf468de833aa13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 17:48:33.896234 saving as /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/kernel/bzImage
50 17:48:33.896294 total size: 8507280 (8 MB)
51 17:48:33.896354 No compression specified
52 17:48:33.897487 progress 0 % (0 MB)
53 17:48:33.899700 progress 5 % (0 MB)
54 17:48:33.902036 progress 10 % (0 MB)
55 17:48:33.904341 progress 15 % (1 MB)
56 17:48:33.906642 progress 20 % (1 MB)
57 17:48:33.909011 progress 25 % (2 MB)
58 17:48:33.911324 progress 30 % (2 MB)
59 17:48:33.913573 progress 35 % (2 MB)
60 17:48:33.915872 progress 40 % (3 MB)
61 17:48:33.918144 progress 45 % (3 MB)
62 17:48:33.920444 progress 50 % (4 MB)
63 17:48:33.922701 progress 55 % (4 MB)
64 17:48:33.924902 progress 60 % (4 MB)
65 17:48:33.927519 progress 65 % (5 MB)
66 17:48:33.930814 progress 70 % (5 MB)
67 17:48:33.934089 progress 75 % (6 MB)
68 17:48:33.937420 progress 80 % (6 MB)
69 17:48:33.940527 progress 85 % (6 MB)
70 17:48:33.943943 progress 90 % (7 MB)
71 17:48:33.946435 progress 95 % (7 MB)
72 17:48:33.948695 progress 100 % (8 MB)
73 17:48:33.948885 8 MB downloaded in 0.05 s (154.28 MB/s)
74 17:48:33.949029 end: 1.2.1 http-download (duration 00:00:00) [common]
76 17:48:33.949255 end: 1.2 download-retry (duration 00:00:00) [common]
77 17:48:33.949342 start: 1.3 download-retry (timeout 00:09:58) [common]
78 17:48:33.949426 start: 1.3.1 http-download (timeout 00:09:58) [common]
79 17:48:33.949565 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/amd64/full.rootfs.tar.xz
80 17:48:33.949634 saving as /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/nfsrootfs/full.rootfs.tar
81 17:48:33.949700 total size: 207157356 (197 MB)
82 17:48:33.949763 Using unxz to decompress xz
83 17:48:33.953740 progress 0 % (0 MB)
84 17:48:34.501097 progress 5 % (9 MB)
85 17:48:35.025368 progress 10 % (19 MB)
86 17:48:35.628332 progress 15 % (29 MB)
87 17:48:35.989527 progress 20 % (39 MB)
88 17:48:36.347477 progress 25 % (49 MB)
89 17:48:36.949090 progress 30 % (59 MB)
90 17:48:37.495438 progress 35 % (69 MB)
91 17:48:38.104972 progress 40 % (79 MB)
92 17:48:39.262650 progress 45 % (88 MB)
93 17:48:39.845588 progress 50 % (98 MB)
94 17:48:40.481434 progress 55 % (108 MB)
95 17:48:41.167620 progress 60 % (118 MB)
96 17:48:41.305009 progress 65 % (128 MB)
97 17:48:41.443478 progress 70 % (138 MB)
98 17:48:41.536844 progress 75 % (148 MB)
99 17:48:41.606799 progress 80 % (158 MB)
100 17:48:41.676411 progress 85 % (167 MB)
101 17:48:41.775422 progress 90 % (177 MB)
102 17:48:42.046005 progress 95 % (187 MB)
103 17:48:42.632692 progress 100 % (197 MB)
104 17:48:42.638981 197 MB downloaded in 8.69 s (22.74 MB/s)
105 17:48:42.639241 end: 1.3.1 http-download (duration 00:00:09) [common]
107 17:48:42.639504 end: 1.3 download-retry (duration 00:00:09) [common]
108 17:48:42.639595 start: 1.4 download-retry (timeout 00:09:49) [common]
109 17:48:42.639685 start: 1.4.1 http-download (timeout 00:09:49) [common]
110 17:48:42.639845 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v4.4.302-cip78-rt45-338-gf468de833aa13/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 17:48:42.639918 saving as /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/modules/modules.tar
112 17:48:42.639979 total size: 253900 (0 MB)
113 17:48:42.640044 Using unxz to decompress xz
114 17:48:42.910387 progress 12 % (0 MB)
115 17:48:42.912685 progress 25 % (0 MB)
116 17:48:42.914035 progress 38 % (0 MB)
117 17:48:42.919183 progress 51 % (0 MB)
118 17:48:42.921161 progress 64 % (0 MB)
119 17:48:42.923119 progress 77 % (0 MB)
120 17:48:42.924998 progress 90 % (0 MB)
121 17:48:42.926791 progress 100 % (0 MB)
122 17:48:42.932509 0 MB downloaded in 0.29 s (0.83 MB/s)
123 17:48:42.932751 end: 1.4.1 http-download (duration 00:00:00) [common]
125 17:48:42.933025 end: 1.4 download-retry (duration 00:00:00) [common]
126 17:48:42.933134 start: 1.5 prepare-tftp-overlay (timeout 00:09:49) [common]
127 17:48:42.933232 start: 1.5.1 extract-nfsrootfs (timeout 00:09:49) [common]
128 17:48:49.428384 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/11831830/extract-nfsrootfs-rh37j3mc
129 17:48:49.428585 end: 1.5.1 extract-nfsrootfs (duration 00:00:06) [common]
130 17:48:49.428683 start: 1.5.2 lava-overlay (timeout 00:09:42) [common]
131 17:48:49.428853 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm
132 17:48:49.428989 makedir: /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin
133 17:48:49.429094 makedir: /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/tests
134 17:48:49.429197 makedir: /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/results
135 17:48:49.429297 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-add-keys
136 17:48:49.429439 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-add-sources
137 17:48:49.429568 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-background-process-start
138 17:48:49.429695 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-background-process-stop
139 17:48:49.429822 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-common-functions
140 17:48:49.429945 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-echo-ipv4
141 17:48:49.430072 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-install-packages
142 17:48:49.430196 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-installed-packages
143 17:48:49.430318 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-os-build
144 17:48:49.430443 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-probe-channel
145 17:48:49.430731 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-probe-ip
146 17:48:49.430860 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-target-ip
147 17:48:49.430985 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-target-mac
148 17:48:49.431110 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-target-storage
149 17:48:49.431236 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-case
150 17:48:49.431363 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-event
151 17:48:49.431486 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-feedback
152 17:48:49.431610 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-raise
153 17:48:49.431734 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-reference
154 17:48:49.431858 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-runner
155 17:48:49.431981 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-set
156 17:48:49.432106 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-test-shell
157 17:48:49.432236 Updating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-add-keys (debian)
158 17:48:49.450755 Updating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-add-sources (debian)
159 17:48:49.450921 Updating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-install-packages (debian)
160 17:48:49.451068 Updating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-installed-packages (debian)
161 17:48:49.451211 Updating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/bin/lava-os-build (debian)
162 17:48:49.451334 Creating /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/environment
163 17:48:49.451433 LAVA metadata
164 17:48:49.451506 - LAVA_JOB_ID=11831830
165 17:48:49.451571 - LAVA_DISPATCHER_IP=192.168.201.1
166 17:48:49.451675 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:42) [common]
167 17:48:49.451743 skipped lava-vland-overlay
168 17:48:49.451819 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
169 17:48:49.451898 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:42) [common]
170 17:48:49.451959 skipped lava-multinode-overlay
171 17:48:49.452032 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
172 17:48:49.452110 start: 1.5.2.3 test-definition (timeout 00:09:42) [common]
173 17:48:49.452183 Loading test definitions
174 17:48:49.452273 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:42) [common]
175 17:48:49.452346 Using /lava-11831830 at stage 0
176 17:48:49.452647 uuid=11831830_1.5.2.3.1 testdef=None
177 17:48:49.452736 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
178 17:48:49.452822 start: 1.5.2.3.2 test-overlay (timeout 00:09:42) [common]
179 17:48:49.453277 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
181 17:48:49.453492 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:42) [common]
182 17:48:49.454033 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
184 17:48:49.454258 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:42) [common]
185 17:48:52.118844 runner path: /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/0/tests/0_timesync-off test_uuid 11831830_1.5.2.3.1
186 17:48:52.120052 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:03) [common]
188 17:48:52.121311 start: 1.5.2.3.5 git-repo-action (timeout 00:09:40) [common]
189 17:48:52.121688 Using /lava-11831830 at stage 0
190 17:48:52.121998 Fetching tests from https://github.com/kernelci/test-definitions.git
191 17:48:52.122080 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/0/tests/1_kselftest-rtc'
192 17:49:11.543341 Running '/usr/bin/git checkout kernelci.org
193 17:49:11.893993 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
194 17:49:11.897563 uuid=11831830_1.5.2.3.5 testdef=None
195 17:49:11.898341 end: 1.5.2.3.5 git-repo-action (duration 00:00:20) [common]
197 17:49:11.899674 start: 1.5.2.3.6 test-overlay (timeout 00:09:20) [common]
198 17:49:11.903487 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
200 17:49:11.904759 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:20) [common]
201 17:49:11.913944 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
203 17:49:11.915302 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:20) [common]
204 17:49:11.924711 runner path: /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/0/tests/1_kselftest-rtc test_uuid 11831830_1.5.2.3.5
205 17:49:11.925190 BOARD='asus-C436FA-Flip-hatch'
206 17:49:11.925524 BRANCH='cip-gitlab'
207 17:49:11.925835 SKIPFILE='/dev/null'
208 17:49:11.926132 SKIP_INSTALL='True'
209 17:49:11.926419 TESTPROG_URL='None'
210 17:49:11.926744 TST_CASENAME=''
211 17:49:11.927030 TST_CMDFILES='rtc'
212 17:49:11.927769 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
214 17:49:11.928808 Creating lava-test-runner.conf files
215 17:49:11.929137 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11831830/lava-overlay-t7n7onbm/lava-11831830/0 for stage 0
216 17:49:11.929610 - 0_timesync-off
217 17:49:11.929956 - 1_kselftest-rtc
218 17:49:11.930464 end: 1.5.2.3 test-definition (duration 00:00:22) [common]
219 17:49:11.930939 start: 1.5.2.4 compress-overlay (timeout 00:09:20) [common]
220 17:49:24.062471 end: 1.5.2.4 compress-overlay (duration 00:00:12) [common]
221 17:49:24.062638 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:08) [common]
222 17:49:24.062766 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
223 17:49:24.062867 end: 1.5.2 lava-overlay (duration 00:00:35) [common]
224 17:49:24.062957 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:08) [common]
225 17:49:25.778360 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
226 17:49:25.778813 start: 1.5.4 extract-modules (timeout 00:09:06) [common]
227 17:49:25.778936 extracting modules file /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11831830/extract-nfsrootfs-rh37j3mc
228 17:49:25.792797 extracting modules file /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11831830/extract-overlay-ramdisk-ksd56ldl/ramdisk
229 17:49:25.806608 end: 1.5.4 extract-modules (duration 00:00:00) [common]
230 17:49:25.806739 start: 1.5.5 apply-overlay-tftp (timeout 00:09:06) [common]
231 17:49:25.806833 [common] Applying overlay to NFS
232 17:49:25.806901 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11831830/compress-overlay-uw3uz74n/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11831830/extract-nfsrootfs-rh37j3mc
233 17:49:26.732755 end: 1.5.5 apply-overlay-tftp (duration 00:00:01) [common]
234 17:49:26.732929 start: 1.5.6 configure-preseed-file (timeout 00:09:05) [common]
235 17:49:26.733021 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
236 17:49:26.733111 start: 1.5.7 compress-ramdisk (timeout 00:09:05) [common]
237 17:49:26.733196 Building ramdisk /var/lib/lava/dispatcher/tmp/11831830/extract-overlay-ramdisk-ksd56ldl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11831830/extract-overlay-ramdisk-ksd56ldl/ramdisk
238 17:49:27.467038 >> 26198 blocks
239 17:49:28.004517 rename /var/lib/lava/dispatcher/tmp/11831830/extract-overlay-ramdisk-ksd56ldl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/ramdisk/ramdisk.cpio.gz
240 17:49:28.004969 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
241 17:49:28.005093 start: 1.5.8 prepare-kernel (timeout 00:09:04) [common]
242 17:49:28.005195 start: 1.5.8.1 prepare-fit (timeout 00:09:04) [common]
243 17:49:28.005296 No mkimage arch provided, not using FIT.
244 17:49:28.005383 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
245 17:49:28.005466 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
246 17:49:28.005569 end: 1.5 prepare-tftp-overlay (duration 00:00:45) [common]
247 17:49:28.005659 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:04) [common]
248 17:49:28.005735 No LXC device requested
249 17:49:28.005816 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
250 17:49:28.005898 start: 1.7 deploy-device-env (timeout 00:09:04) [common]
251 17:49:28.005976 end: 1.7 deploy-device-env (duration 00:00:00) [common]
252 17:49:28.006051 Checking files for TFTP limit of 4294967296 bytes.
253 17:49:28.006456 end: 1 tftp-deploy (duration 00:00:56) [common]
254 17:49:28.006609 start: 2 depthcharge-action (timeout 00:05:00) [common]
255 17:49:28.006701 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
256 17:49:28.006823 substitutions:
257 17:49:28.006894 - {DTB}: None
258 17:49:28.006955 - {INITRD}: 11831830/tftp-deploy-e4kzmb5l/ramdisk/ramdisk.cpio.gz
259 17:49:28.007014 - {KERNEL}: 11831830/tftp-deploy-e4kzmb5l/kernel/bzImage
260 17:49:28.007071 - {LAVA_MAC}: None
261 17:49:28.007126 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/11831830/extract-nfsrootfs-rh37j3mc
262 17:49:28.007186 - {NFS_SERVER_IP}: 192.168.201.1
263 17:49:28.007241 - {PRESEED_CONFIG}: None
264 17:49:28.007295 - {PRESEED_LOCAL}: None
265 17:49:28.007348 - {RAMDISK}: 11831830/tftp-deploy-e4kzmb5l/ramdisk/ramdisk.cpio.gz
266 17:49:28.007402 - {ROOT_PART}: None
267 17:49:28.007455 - {ROOT}: None
268 17:49:28.007508 - {SERVER_IP}: 192.168.201.1
269 17:49:28.007560 - {TEE}: None
270 17:49:28.007612 Parsed boot commands:
271 17:49:28.007664 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
272 17:49:28.007838 Parsed boot commands: tftpboot 192.168.201.1 11831830/tftp-deploy-e4kzmb5l/kernel/bzImage 11831830/tftp-deploy-e4kzmb5l/kernel/cmdline 11831830/tftp-deploy-e4kzmb5l/ramdisk/ramdisk.cpio.gz
273 17:49:28.007926 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
274 17:49:28.008010 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
275 17:49:28.008098 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
276 17:49:28.008179 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
277 17:49:28.008248 Not connected, no need to disconnect.
278 17:49:28.008320 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
279 17:49:28.008400 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
280 17:49:28.008464 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-C436FA-Flip-hatch-cbg-0'
281 17:49:28.012349 Setting prompt string to ['lava-test: # ']
282 17:49:28.012721 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
283 17:49:28.012831 end: 2.2.1 reset-connection (duration 00:00:00) [common]
284 17:49:28.012927 start: 2.2.2 reset-device (timeout 00:05:00) [common]
285 17:49:28.013014 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
286 17:49:28.013205 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=reboot'
287 17:49:34.985670 >> Command sent successfully.
288 17:49:34.996243 Returned 0 in 6 seconds
289 17:49:35.097436 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
291 17:49:35.098874 end: 2.2.2 reset-device (duration 00:00:07) [common]
292 17:49:35.099401 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
293 17:49:35.099851 Setting prompt string to 'Starting depthcharge on Helios...'
294 17:49:35.100204 Changing prompt to 'Starting depthcharge on Helios...'
295 17:49:35.100545 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
296 17:49:35.101732 [Enter `^Ec?' for help]
297 17:49:35.709129
298 17:49:35.709656
299 17:49:35.719246 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
300 17:49:35.722322 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
301 17:49:35.728983 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
302 17:49:35.732520 CPU: AES supported, TXT NOT supported, VT supported
303 17:49:35.738929 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
304 17:49:35.742395 PCH: device id 0284 (rev 00) is Cometlake-U Premium
305 17:49:35.748939 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
306 17:49:35.752578 VBOOT: Loading verstage.
307 17:49:35.755665 FMAP: Found "FLASH" version 1.1 at 0xc04000.
308 17:49:35.762361 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
309 17:49:35.765270 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
310 17:49:35.769071 CBFS @ c08000 size 3f8000
311 17:49:35.775535 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
312 17:49:35.779075 CBFS: Locating 'fallback/verstage'
313 17:49:35.782401 CBFS: Found @ offset 10fb80 size 1072c
314 17:49:35.785705
315 17:49:35.786183
316 17:49:35.796144 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
317 17:49:35.810496 Probing TPM: . done!
318 17:49:35.813509 TPM ready after 0 ms
319 17:49:35.816484 Connected to device vid:did:rid of 1ae0:0028:00
320 17:49:35.827437 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
321 17:49:35.830871 Initialized TPM device CR50 revision 0
322 17:49:35.877974 tlcl_send_startup: Startup return code is 0
323 17:49:35.878506 TPM: setup succeeded
324 17:49:35.890771 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
325 17:49:35.894234 Chrome EC: UHEPI supported
326 17:49:35.897846 Phase 1
327 17:49:35.900897 FMAP: area GBB found @ c05000 (12288 bytes)
328 17:49:35.908046 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
329 17:49:35.908586 Phase 2
330 17:49:35.910993 Phase 3
331 17:49:35.914610 FMAP: area GBB found @ c05000 (12288 bytes)
332 17:49:35.921218 VB2:vb2_report_dev_firmware() This is developer signed firmware
333 17:49:35.927564 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
334 17:49:35.931213 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
335 17:49:35.937505 VB2:vb2_verify_keyblock() Checking keyblock signature...
336 17:49:35.953408 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
337 17:49:35.956423 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
338 17:49:35.962506 VB2:vb2_verify_fw_preamble() Verifying preamble.
339 17:49:35.966966 Phase 4
340 17:49:35.970695 FMAP: area FW_MAIN_B found @ 778000 (3506112 bytes)
341 17:49:35.977089 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
342 17:49:36.156445 VB2:vb2_rsa_verify_digest() Digest check failed!
343 17:49:36.163110 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
344 17:49:36.163531 Saving nvdata
345 17:49:36.166843 Reboot requested (10020007)
346 17:49:36.169974 board_reset() called!
347 17:49:36.170494 full_reset() called!
348 17:49:40.676210
349 17:49:40.676730
350 17:49:40.686199 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
351 17:49:40.689544 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
352 17:49:40.696257 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
353 17:49:40.699370 CPU: AES supported, TXT NOT supported, VT supported
354 17:49:40.705806 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
355 17:49:40.709146 PCH: device id 0284 (rev 00) is Cometlake-U Premium
356 17:49:40.715918 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
357 17:49:40.719479 VBOOT: Loading verstage.
358 17:49:40.722630 FMAP: Found "FLASH" version 1.1 at 0xc04000.
359 17:49:40.729345 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
360 17:49:40.732946 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
361 17:49:40.736382 CBFS @ c08000 size 3f8000
362 17:49:40.743062 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
363 17:49:40.745817 CBFS: Locating 'fallback/verstage'
364 17:49:40.749210 CBFS: Found @ offset 10fb80 size 1072c
365 17:49:40.752870
366 17:49:40.753388
367 17:49:40.762705 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
368 17:49:40.777409 Probing TPM: . done!
369 17:49:40.780460 TPM ready after 0 ms
370 17:49:40.783734 Connected to device vid:did:rid of 1ae0:0028:00
371 17:49:40.794073 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
372 17:49:40.798013 Initialized TPM device CR50 revision 0
373 17:49:40.845103 tlcl_send_startup: Startup return code is 0
374 17:49:40.845760 TPM: setup succeeded
375 17:49:40.857596 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
376 17:49:40.861035 Chrome EC: UHEPI supported
377 17:49:40.864432 Phase 1
378 17:49:40.867967 FMAP: area GBB found @ c05000 (12288 bytes)
379 17:49:40.874381 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
380 17:49:40.881517 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
381 17:49:40.884960 Recovery requested (1009000e)
382 17:49:40.890628 Saving nvdata
383 17:49:40.896395 tlcl_extend: response is 0
384 17:49:40.905338 tlcl_extend: response is 0
385 17:49:40.912281 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
386 17:49:40.915630 CBFS @ c08000 size 3f8000
387 17:49:40.922079 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
388 17:49:40.925195 CBFS: Locating 'fallback/romstage'
389 17:49:40.928616 CBFS: Found @ offset 80 size 145fc
390 17:49:40.931635 Accumulated console time in verstage 99 ms
391 17:49:40.932068
392 17:49:40.932398
393 17:49:40.945193 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
394 17:49:40.951760 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
395 17:49:40.955061 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
396 17:49:40.958510 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
397 17:49:40.965152 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
398 17:49:40.968158 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
399 17:49:40.971542 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
400 17:49:40.974759 TCO_STS: 0000 0000
401 17:49:40.978385 GEN_PMCON: e0015238 00000200
402 17:49:40.981601 GBLRST_CAUSE: 00000000 00000000
403 17:49:40.982187 prev_sleep_state 5
404 17:49:40.984770 Boot Count incremented to 71968
405 17:49:40.991757 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
406 17:49:40.995013 CBFS @ c08000 size 3f8000
407 17:49:41.001941 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
408 17:49:41.002364 CBFS: Locating 'fspm.bin'
409 17:49:41.005299 CBFS: Found @ offset 5ffc0 size 71000
410 17:49:41.009100 Chrome EC: UHEPI supported
411 17:49:41.016615 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
412 17:49:41.021923 Probing TPM: done!
413 17:49:41.028571 Connected to device vid:did:rid of 1ae0:0028:00
414 17:49:41.038389 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
415 17:49:41.044751 Initialized TPM device CR50 revision 0
416 17:49:41.053332 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
417 17:49:41.060147 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
418 17:49:41.063267 MRC cache found, size 1948
419 17:49:41.066740 bootmode is set to: 2
420 17:49:41.069934 PRMRR disabled by config.
421 17:49:41.070368 SPD INDEX = 1
422 17:49:41.076706 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
423 17:49:41.079650 CBFS @ c08000 size 3f8000
424 17:49:41.086660 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
425 17:49:41.087187 CBFS: Locating 'spd.bin'
426 17:49:41.089609 CBFS: Found @ offset 5fb80 size 400
427 17:49:41.093452 SPD: module type is LPDDR3
428 17:49:41.096650 SPD: module part is
429 17:49:41.103334 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
430 17:49:41.107035 SPD: device width 4 bits, bus width 8 bits
431 17:49:41.109930 SPD: module size is 4096 MB (per channel)
432 17:49:41.113529 memory slot: 0 configuration done.
433 17:49:41.117025 memory slot: 2 configuration done.
434 17:49:41.167489 CBMEM:
435 17:49:41.171037 IMD: root @ 99fff000 254 entries.
436 17:49:41.173847 IMD: root @ 99ffec00 62 entries.
437 17:49:41.177689 External stage cache:
438 17:49:41.180424 IMD: root @ 9abff000 254 entries.
439 17:49:41.183758 IMD: root @ 9abfec00 62 entries.
440 17:49:41.187223 Chrome EC: clear events_b mask to 0x0000000020004000
441 17:49:41.203747 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
442 17:49:41.217251 tlcl_write: response is 0
443 17:49:41.226252 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
444 17:49:41.232522 MRC: TPM MRC hash updated successfully.
445 17:49:41.233054 2 DIMMs found
446 17:49:41.236183 SMM Memory Map
447 17:49:41.239146 SMRAM : 0x9a000000 0x1000000
448 17:49:41.243074 Subregion 0: 0x9a000000 0xa00000
449 17:49:41.245658 Subregion 1: 0x9aa00000 0x200000
450 17:49:41.248738 Subregion 2: 0x9ac00000 0x400000
451 17:49:41.252470 top_of_ram = 0x9a000000
452 17:49:41.255912 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
453 17:49:41.262464 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
454 17:49:41.265779 MTRR Range: Start=ff000000 End=0 (Size 1000000)
455 17:49:41.272142 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
456 17:49:41.275711 CBFS @ c08000 size 3f8000
457 17:49:41.279370 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
458 17:49:41.282418 CBFS: Locating 'fallback/postcar'
459 17:49:41.285806 CBFS: Found @ offset 107000 size 4b44
460 17:49:41.291935 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
461 17:49:41.305303 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
462 17:49:41.308147 Processing 180 relocs. Offset value of 0x97c0c000
463 17:49:41.316426 Accumulated console time in romstage 286 ms
464 17:49:41.316942
465 17:49:41.317280
466 17:49:41.326915 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
467 17:49:41.333214 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
468 17:49:41.336443 CBFS @ c08000 size 3f8000
469 17:49:41.339955 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
470 17:49:41.346124 CBFS: Locating 'fallback/ramstage'
471 17:49:41.349803 CBFS: Found @ offset 43380 size 1b9e8
472 17:49:41.356027 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
473 17:49:41.388435 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
474 17:49:41.391246 Processing 3976 relocs. Offset value of 0x98db0000
475 17:49:41.398128 Accumulated console time in postcar 52 ms
476 17:49:41.398716
477 17:49:41.399064
478 17:49:41.408042 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
479 17:49:41.415169 FMAP: area RO_VPD found @ c00000 (16384 bytes)
480 17:49:41.418037 WARNING: RO_VPD is uninitialized or empty.
481 17:49:41.421946 FMAP: area RW_VPD found @ af8000 (8192 bytes)
482 17:49:41.428060 FMAP: area RW_VPD found @ af8000 (8192 bytes)
483 17:49:41.428491 Normal boot.
484 17:49:41.434762 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
485 17:49:41.438250 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
486 17:49:41.441755 CBFS @ c08000 size 3f8000
487 17:49:41.448137 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
488 17:49:41.451518 CBFS: Locating 'cpu_microcode_blob.bin'
489 17:49:41.454701 CBFS: Found @ offset 14700 size 2ec00
490 17:49:41.458113 microcode: sig=0x806ec pf=0x4 revision=0xc9
491 17:49:41.461104 Skip microcode update
492 17:49:41.468461 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
493 17:49:41.469018 CBFS @ c08000 size 3f8000
494 17:49:41.474738 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
495 17:49:41.477704 CBFS: Locating 'fsps.bin'
496 17:49:41.481220 CBFS: Found @ offset d1fc0 size 35000
497 17:49:41.506437 Detected 4 core, 8 thread CPU.
498 17:49:41.509704 Setting up SMI for CPU
499 17:49:41.513359 IED base = 0x9ac00000
500 17:49:41.513888 IED size = 0x00400000
501 17:49:41.516817 Will perform SMM setup.
502 17:49:41.523360 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
503 17:49:41.529852 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
504 17:49:41.532809 Processing 16 relocs. Offset value of 0x00030000
505 17:49:41.537078 Attempting to start 7 APs
506 17:49:41.540017 Waiting for 10ms after sending INIT.
507 17:49:41.556714 Waiting for 1st SIPI to complete...done.
508 17:49:41.557241 AP: slot 1 apic_id 1.
509 17:49:41.562801 Waiting for 2nd SIPI to complete...done.
510 17:49:41.563329 AP: slot 6 apic_id 3.
511 17:49:41.566468 AP: slot 7 apic_id 2.
512 17:49:41.569404 AP: slot 2 apic_id 5.
513 17:49:41.569827 AP: slot 3 apic_id 4.
514 17:49:41.572512 AP: slot 5 apic_id 6.
515 17:49:41.576112 AP: slot 4 apic_id 7.
516 17:49:41.582711 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
517 17:49:41.589465 Processing 13 relocs. Offset value of 0x00038000
518 17:49:41.596410 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
519 17:49:41.599205 Installing SMM handler to 0x9a000000
520 17:49:41.605780 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
521 17:49:41.612244 Processing 658 relocs. Offset value of 0x9a010000
522 17:49:41.619009 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
523 17:49:41.622425 Processing 13 relocs. Offset value of 0x9a008000
524 17:49:41.629307 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
525 17:49:41.635969 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
526 17:49:41.642971 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
527 17:49:41.645764 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
528 17:49:41.652388 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
529 17:49:41.658582 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
530 17:49:41.665333 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
531 17:49:41.668825 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
532 17:49:41.672154 Clearing SMI status registers
533 17:49:41.676034 SMI_STS: PM1
534 17:49:41.676575 PM1_STS: PWRBTN
535 17:49:41.679233 TCO_STS: SECOND_TO
536 17:49:41.682442 New SMBASE 0x9a000000
537 17:49:41.685782 In relocation handler: CPU 0
538 17:49:41.688863 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
539 17:49:41.692390 Writing SMRR. base = 0x9a000006, mask=0xff000800
540 17:49:41.695365 Relocation complete.
541 17:49:41.699037 New SMBASE 0x99fffc00
542 17:49:41.699572 In relocation handler: CPU 1
543 17:49:41.705972 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
544 17:49:41.709073 Writing SMRR. base = 0x9a000006, mask=0xff000800
545 17:49:41.712622 Relocation complete.
546 17:49:41.715952 New SMBASE 0x99fff000
547 17:49:41.716481 In relocation handler: CPU 4
548 17:49:41.722916 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
549 17:49:41.725647 Writing SMRR. base = 0x9a000006, mask=0xff000800
550 17:49:41.729339 Relocation complete.
551 17:49:41.729863 New SMBASE 0x99ffec00
552 17:49:41.732422 In relocation handler: CPU 5
553 17:49:41.739360 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
554 17:49:41.742495 Writing SMRR. base = 0x9a000006, mask=0xff000800
555 17:49:41.745670 Relocation complete.
556 17:49:41.746200 New SMBASE 0x99ffe800
557 17:49:41.749060 In relocation handler: CPU 6
558 17:49:41.755186 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
559 17:49:41.758601 Writing SMRR. base = 0x9a000006, mask=0xff000800
560 17:49:41.762247 Relocation complete.
561 17:49:41.762836 New SMBASE 0x99ffe400
562 17:49:41.765396 In relocation handler: CPU 7
563 17:49:41.769185 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
564 17:49:41.775120 Writing SMRR. base = 0x9a000006, mask=0xff000800
565 17:49:41.779009 Relocation complete.
566 17:49:41.779537 New SMBASE 0x99fff400
567 17:49:41.781778 In relocation handler: CPU 3
568 17:49:41.785397 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
569 17:49:41.791763 Writing SMRR. base = 0x9a000006, mask=0xff000800
570 17:49:41.795196 Relocation complete.
571 17:49:41.795616 New SMBASE 0x99fff800
572 17:49:41.798487 In relocation handler: CPU 2
573 17:49:41.802065 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
574 17:49:41.808800 Writing SMRR. base = 0x9a000006, mask=0xff000800
575 17:49:41.809284 Relocation complete.
576 17:49:41.811514 Initializing CPU #0
577 17:49:41.815018 CPU: vendor Intel device 806ec
578 17:49:41.818836 CPU: family 06, model 8e, stepping 0c
579 17:49:41.821850 Clearing out pending MCEs
580 17:49:41.825311 Setting up local APIC...
581 17:49:41.825853 apic_id: 0x00 done.
582 17:49:41.828346 Turbo is available but hidden
583 17:49:41.831493 Turbo is available and visible
584 17:49:41.835418 VMX status: enabled
585 17:49:41.838482 IA32_FEATURE_CONTROL status: locked
586 17:49:41.841842 Skip microcode update
587 17:49:41.842362 CPU #0 initialized
588 17:49:41.845014 Initializing CPU #1
589 17:49:41.848824 Initializing CPU #5
590 17:49:41.849477 Initializing CPU #4
591 17:49:41.851427 CPU: vendor Intel device 806ec
592 17:49:41.855339 CPU: family 06, model 8e, stepping 0c
593 17:49:41.858406 CPU: vendor Intel device 806ec
594 17:49:41.861912 CPU: family 06, model 8e, stepping 0c
595 17:49:41.865106 Clearing out pending MCEs
596 17:49:41.868267 Clearing out pending MCEs
597 17:49:41.871616 Setting up local APIC...
598 17:49:41.872140 Initializing CPU #6
599 17:49:41.875072 Initializing CPU #7
600 17:49:41.878443 CPU: vendor Intel device 806ec
601 17:49:41.881431 CPU: family 06, model 8e, stepping 0c
602 17:49:41.884938 CPU: vendor Intel device 806ec
603 17:49:41.888676 CPU: family 06, model 8e, stepping 0c
604 17:49:41.891582 Clearing out pending MCEs
605 17:49:41.895054 Clearing out pending MCEs
606 17:49:41.895644 Setting up local APIC...
607 17:49:41.898346 CPU: vendor Intel device 806ec
608 17:49:41.905201 CPU: family 06, model 8e, stepping 0c
609 17:49:41.905731 Clearing out pending MCEs
610 17:49:41.908123 Setting up local APIC...
611 17:49:41.911227 Setting up local APIC...
612 17:49:41.911653 apic_id: 0x03 done.
613 17:49:41.914628 apic_id: 0x02 done.
614 17:49:41.918176 VMX status: enabled
615 17:49:41.918744 VMX status: enabled
616 17:49:41.921402 IA32_FEATURE_CONTROL status: locked
617 17:49:41.928093 IA32_FEATURE_CONTROL status: locked
618 17:49:41.928623 Skip microcode update
619 17:49:41.931204 Skip microcode update
620 17:49:41.931627 CPU #6 initialized
621 17:49:41.934501 CPU #7 initialized
622 17:49:41.938327 Initializing CPU #3
623 17:49:41.938893 Initializing CPU #2
624 17:49:41.941252 CPU: vendor Intel device 806ec
625 17:49:41.944893 CPU: family 06, model 8e, stepping 0c
626 17:49:41.947800 CPU: vendor Intel device 806ec
627 17:49:41.951407 CPU: family 06, model 8e, stepping 0c
628 17:49:41.954616 Clearing out pending MCEs
629 17:49:41.958205 Clearing out pending MCEs
630 17:49:41.961327 Setting up local APIC...
631 17:49:41.961749 apic_id: 0x07 done.
632 17:49:41.964568 Setting up local APIC...
633 17:49:41.968042 apic_id: 0x01 done.
634 17:49:41.970854 apic_id: 0x04 done.
635 17:49:41.971279 Setting up local APIC...
636 17:49:41.974389 apic_id: 0x06 done.
637 17:49:41.977734 VMX status: enabled
638 17:49:41.978264 VMX status: enabled
639 17:49:41.980884 IA32_FEATURE_CONTROL status: locked
640 17:49:41.984360 IA32_FEATURE_CONTROL status: locked
641 17:49:41.987914 Skip microcode update
642 17:49:41.990728 Skip microcode update
643 17:49:41.991151 apic_id: 0x05 done.
644 17:49:41.994205 VMX status: enabled
645 17:49:41.997458 VMX status: enabled
646 17:49:42.001163 IA32_FEATURE_CONTROL status: locked
647 17:49:42.004033 IA32_FEATURE_CONTROL status: locked
648 17:49:42.004459 Skip microcode update
649 17:49:42.007113 CPU #5 initialized
650 17:49:42.010553 CPU #4 initialized
651 17:49:42.010999 CPU #3 initialized
652 17:49:42.014364 Skip microcode update
653 17:49:42.014834 VMX status: enabled
654 17:49:42.017153 CPU #2 initialized
655 17:49:42.020407 IA32_FEATURE_CONTROL status: locked
656 17:49:42.023799 Skip microcode update
657 17:49:42.024285 CPU #1 initialized
658 17:49:42.030636 bsp_do_flight_plan done after 466 msecs.
659 17:49:42.034052 CPU: frequency set to 4200 MHz
660 17:49:42.034490 Enabling SMIs.
661 17:49:42.037104 Locking SMM.
662 17:49:42.050229 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
663 17:49:42.053928 CBFS @ c08000 size 3f8000
664 17:49:42.060527 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
665 17:49:42.061149 CBFS: Locating 'vbt.bin'
666 17:49:42.063768 CBFS: Found @ offset 5f5c0 size 499
667 17:49:42.070511 Found a VBT of 4608 bytes after decompression
668 17:49:42.255774 Display FSP Version Info HOB
669 17:49:42.259397 Reference Code - CPU = 9.0.1e.30
670 17:49:42.262360 uCode Version = 0.0.0.ca
671 17:49:42.265652 TXT ACM version = ff.ff.ff.ffff
672 17:49:42.269058 Display FSP Version Info HOB
673 17:49:42.272211 Reference Code - ME = 9.0.1e.30
674 17:49:42.275186 MEBx version = 0.0.0.0
675 17:49:42.278596 ME Firmware Version = Consumer SKU
676 17:49:42.282475 Display FSP Version Info HOB
677 17:49:42.285380 Reference Code - CML PCH = 9.0.1e.30
678 17:49:42.288980 PCH-CRID Status = Disabled
679 17:49:42.292503 PCH-CRID Original Value = ff.ff.ff.ffff
680 17:49:42.295238 PCH-CRID New Value = ff.ff.ff.ffff
681 17:49:42.298463 OPROM - RST - RAID = ff.ff.ff.ffff
682 17:49:42.301959 ChipsetInit Base Version = ff.ff.ff.ffff
683 17:49:42.305607 ChipsetInit Oem Version = ff.ff.ff.ffff
684 17:49:42.308697 Display FSP Version Info HOB
685 17:49:42.315221 Reference Code - SA - System Agent = 9.0.1e.30
686 17:49:42.318423 Reference Code - MRC = 0.7.1.6c
687 17:49:42.322138 SA - PCIe Version = 9.0.1e.30
688 17:49:42.322703 SA-CRID Status = Disabled
689 17:49:42.325365 SA-CRID Original Value = 0.0.0.c
690 17:49:42.328425 SA-CRID New Value = 0.0.0.c
691 17:49:42.331991 OPROM - VBIOS = ff.ff.ff.ffff
692 17:49:42.334983 RTC Init
693 17:49:42.338610 Set power on after power failure.
694 17:49:42.339135 Disabling Deep S3
695 17:49:42.341871 Disabling Deep S3
696 17:49:42.342433 Disabling Deep S4
697 17:49:42.345254 Disabling Deep S4
698 17:49:42.348025 Disabling Deep S5
699 17:49:42.348447 Disabling Deep S5
700 17:49:42.354719 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 196 exit 1
701 17:49:42.355239 Enumerating buses...
702 17:49:42.361624 Show all devs... Before device enumeration.
703 17:49:42.364958 Root Device: enabled 1
704 17:49:42.365487 CPU_CLUSTER: 0: enabled 1
705 17:49:42.368519 DOMAIN: 0000: enabled 1
706 17:49:42.371394 APIC: 00: enabled 1
707 17:49:42.371921 PCI: 00:00.0: enabled 1
708 17:49:42.374324 PCI: 00:02.0: enabled 1
709 17:49:42.377697 PCI: 00:04.0: enabled 0
710 17:49:42.381876 PCI: 00:05.0: enabled 0
711 17:49:42.382438 PCI: 00:12.0: enabled 1
712 17:49:42.384675 PCI: 00:12.5: enabled 0
713 17:49:42.388220 PCI: 00:12.6: enabled 0
714 17:49:42.391271 PCI: 00:14.0: enabled 1
715 17:49:42.391692 PCI: 00:14.1: enabled 0
716 17:49:42.394586 PCI: 00:14.3: enabled 1
717 17:49:42.398096 PCI: 00:14.5: enabled 0
718 17:49:42.398679 PCI: 00:15.0: enabled 1
719 17:49:42.401424 PCI: 00:15.1: enabled 1
720 17:49:42.405094 PCI: 00:15.2: enabled 0
721 17:49:42.407829 PCI: 00:15.3: enabled 0
722 17:49:42.408250 PCI: 00:16.0: enabled 1
723 17:49:42.411297 PCI: 00:16.1: enabled 0
724 17:49:42.414569 PCI: 00:16.2: enabled 0
725 17:49:42.418162 PCI: 00:16.3: enabled 0
726 17:49:42.418738 PCI: 00:16.4: enabled 0
727 17:49:42.421253 PCI: 00:16.5: enabled 0
728 17:49:42.424526 PCI: 00:17.0: enabled 1
729 17:49:42.428079 PCI: 00:19.0: enabled 1
730 17:49:42.428607 PCI: 00:19.1: enabled 0
731 17:49:42.431296 PCI: 00:19.2: enabled 0
732 17:49:42.434797 PCI: 00:1a.0: enabled 0
733 17:49:42.435319 PCI: 00:1c.0: enabled 0
734 17:49:42.437781 PCI: 00:1c.1: enabled 0
735 17:49:42.441246 PCI: 00:1c.2: enabled 0
736 17:49:42.444971 PCI: 00:1c.3: enabled 0
737 17:49:42.445503 PCI: 00:1c.4: enabled 0
738 17:49:42.447591 PCI: 00:1c.5: enabled 0
739 17:49:42.451219 PCI: 00:1c.6: enabled 0
740 17:49:42.454621 PCI: 00:1c.7: enabled 0
741 17:49:42.455158 PCI: 00:1d.0: enabled 1
742 17:49:42.457642 PCI: 00:1d.1: enabled 0
743 17:49:42.460993 PCI: 00:1d.2: enabled 0
744 17:49:42.464305 PCI: 00:1d.3: enabled 0
745 17:49:42.464834 PCI: 00:1d.4: enabled 0
746 17:49:42.467762 PCI: 00:1d.5: enabled 1
747 17:49:42.471223 PCI: 00:1e.0: enabled 1
748 17:49:42.471758 PCI: 00:1e.1: enabled 0
749 17:49:42.474064 PCI: 00:1e.2: enabled 1
750 17:49:42.477120 PCI: 00:1e.3: enabled 1
751 17:49:42.481317 PCI: 00:1f.0: enabled 1
752 17:49:42.481847 PCI: 00:1f.1: enabled 1
753 17:49:42.483950 PCI: 00:1f.2: enabled 1
754 17:49:42.487271 PCI: 00:1f.3: enabled 1
755 17:49:42.490872 PCI: 00:1f.4: enabled 1
756 17:49:42.491396 PCI: 00:1f.5: enabled 1
757 17:49:42.494296 PCI: 00:1f.6: enabled 0
758 17:49:42.497667 USB0 port 0: enabled 1
759 17:49:42.498196 I2C: 00:15: enabled 1
760 17:49:42.500962 I2C: 00:5d: enabled 1
761 17:49:42.504217 GENERIC: 0.0: enabled 1
762 17:49:42.507705 I2C: 00:1a: enabled 1
763 17:49:42.508128 I2C: 00:38: enabled 1
764 17:49:42.510712 I2C: 00:39: enabled 1
765 17:49:42.514472 I2C: 00:3a: enabled 1
766 17:49:42.515040 I2C: 00:3b: enabled 1
767 17:49:42.517595 PCI: 00:00.0: enabled 1
768 17:49:42.521302 SPI: 00: enabled 1
769 17:49:42.521826 SPI: 01: enabled 1
770 17:49:42.524118 PNP: 0c09.0: enabled 1
771 17:49:42.527435 USB2 port 0: enabled 1
772 17:49:42.527860 USB2 port 1: enabled 1
773 17:49:42.530427 USB2 port 2: enabled 0
774 17:49:42.534105 USB2 port 3: enabled 0
775 17:49:42.534669 USB2 port 5: enabled 0
776 17:49:42.537767 USB2 port 6: enabled 1
777 17:49:42.540694 USB2 port 9: enabled 1
778 17:49:42.541226 USB3 port 0: enabled 1
779 17:49:42.543798 USB3 port 1: enabled 1
780 17:49:42.548158 USB3 port 2: enabled 1
781 17:49:42.551114 USB3 port 3: enabled 1
782 17:49:42.551646 USB3 port 4: enabled 0
783 17:49:42.554464 APIC: 01: enabled 1
784 17:49:42.557370 APIC: 05: enabled 1
785 17:49:42.557910 APIC: 04: enabled 1
786 17:49:42.560154 APIC: 07: enabled 1
787 17:49:42.560577 APIC: 06: enabled 1
788 17:49:42.563721 APIC: 03: enabled 1
789 17:49:42.567067 APIC: 02: enabled 1
790 17:49:42.567745 Compare with tree...
791 17:49:42.570654 Root Device: enabled 1
792 17:49:42.573596 CPU_CLUSTER: 0: enabled 1
793 17:49:42.574019 APIC: 00: enabled 1
794 17:49:42.576919 APIC: 01: enabled 1
795 17:49:42.580672 APIC: 05: enabled 1
796 17:49:42.581095 APIC: 04: enabled 1
797 17:49:42.583499 APIC: 07: enabled 1
798 17:49:42.586823 APIC: 06: enabled 1
799 17:49:42.590259 APIC: 03: enabled 1
800 17:49:42.590723 APIC: 02: enabled 1
801 17:49:42.593821 DOMAIN: 0000: enabled 1
802 17:49:42.597273 PCI: 00:00.0: enabled 1
803 17:49:42.600392 PCI: 00:02.0: enabled 1
804 17:49:42.600925 PCI: 00:04.0: enabled 0
805 17:49:42.603272 PCI: 00:05.0: enabled 0
806 17:49:42.607027 PCI: 00:12.0: enabled 1
807 17:49:42.610079 PCI: 00:12.5: enabled 0
808 17:49:42.613729 PCI: 00:12.6: enabled 0
809 17:49:42.614258 PCI: 00:14.0: enabled 1
810 17:49:42.617285 USB0 port 0: enabled 1
811 17:49:42.620264 USB2 port 0: enabled 1
812 17:49:42.623341 USB2 port 1: enabled 1
813 17:49:42.626763 USB2 port 2: enabled 0
814 17:49:42.627295 USB2 port 3: enabled 0
815 17:49:42.630261 USB2 port 5: enabled 0
816 17:49:42.633431 USB2 port 6: enabled 1
817 17:49:42.636845 USB2 port 9: enabled 1
818 17:49:42.640367 USB3 port 0: enabled 1
819 17:49:42.640895 USB3 port 1: enabled 1
820 17:49:42.643498 USB3 port 2: enabled 1
821 17:49:42.646867 USB3 port 3: enabled 1
822 17:49:42.649656 USB3 port 4: enabled 0
823 17:49:42.653744 PCI: 00:14.1: enabled 0
824 17:49:42.656739 PCI: 00:14.3: enabled 1
825 17:49:42.657298 PCI: 00:14.5: enabled 0
826 17:49:42.659935 PCI: 00:15.0: enabled 1
827 17:49:42.663198 I2C: 00:15: enabled 1
828 17:49:42.666932 PCI: 00:15.1: enabled 1
829 17:49:42.667484 I2C: 00:5d: enabled 1
830 17:49:42.669703 GENERIC: 0.0: enabled 1
831 17:49:42.673138 PCI: 00:15.2: enabled 0
832 17:49:42.676413 PCI: 00:15.3: enabled 0
833 17:49:42.679816 PCI: 00:16.0: enabled 1
834 17:49:42.680266 PCI: 00:16.1: enabled 0
835 17:49:42.682632 PCI: 00:16.2: enabled 0
836 17:49:42.686261 PCI: 00:16.3: enabled 0
837 17:49:42.689667 PCI: 00:16.4: enabled 0
838 17:49:42.692775 PCI: 00:16.5: enabled 0
839 17:49:42.693194 PCI: 00:17.0: enabled 1
840 17:49:42.696134 PCI: 00:19.0: enabled 1
841 17:49:42.699190 I2C: 00:1a: enabled 1
842 17:49:42.702730 I2C: 00:38: enabled 1
843 17:49:42.706233 I2C: 00:39: enabled 1
844 17:49:42.706694 I2C: 00:3a: enabled 1
845 17:49:42.709690 I2C: 00:3b: enabled 1
846 17:49:42.713297 PCI: 00:19.1: enabled 0
847 17:49:42.716311 PCI: 00:19.2: enabled 0
848 17:49:42.716845 PCI: 00:1a.0: enabled 0
849 17:49:42.719599 PCI: 00:1c.0: enabled 0
850 17:49:42.722643 PCI: 00:1c.1: enabled 0
851 17:49:42.726269 PCI: 00:1c.2: enabled 0
852 17:49:42.729234 PCI: 00:1c.3: enabled 0
853 17:49:42.729655 PCI: 00:1c.4: enabled 0
854 17:49:42.732585 PCI: 00:1c.5: enabled 0
855 17:49:42.735948 PCI: 00:1c.6: enabled 0
856 17:49:42.739480 PCI: 00:1c.7: enabled 0
857 17:49:42.742657 PCI: 00:1d.0: enabled 1
858 17:49:42.743204 PCI: 00:1d.1: enabled 0
859 17:49:42.745959 PCI: 00:1d.2: enabled 0
860 17:49:42.748905 PCI: 00:1d.3: enabled 0
861 17:49:42.752730 PCI: 00:1d.4: enabled 0
862 17:49:42.756019 PCI: 00:1d.5: enabled 1
863 17:49:42.756549 PCI: 00:00.0: enabled 1
864 17:49:42.759485 PCI: 00:1e.0: enabled 1
865 17:49:42.762706 PCI: 00:1e.1: enabled 0
866 17:49:42.766209 PCI: 00:1e.2: enabled 1
867 17:49:42.766796 SPI: 00: enabled 1
868 17:49:42.769237 PCI: 00:1e.3: enabled 1
869 17:49:42.772297 SPI: 01: enabled 1
870 17:49:42.775739 PCI: 00:1f.0: enabled 1
871 17:49:42.776199 PNP: 0c09.0: enabled 1
872 17:49:42.778843 PCI: 00:1f.1: enabled 1
873 17:49:42.782114 PCI: 00:1f.2: enabled 1
874 17:49:42.785791 PCI: 00:1f.3: enabled 1
875 17:49:42.788997 PCI: 00:1f.4: enabled 1
876 17:49:42.789522 PCI: 00:1f.5: enabled 1
877 17:49:42.791938 PCI: 00:1f.6: enabled 0
878 17:49:42.795467 Root Device scanning...
879 17:49:42.798760 scan_static_bus for Root Device
880 17:49:42.802118 CPU_CLUSTER: 0 enabled
881 17:49:42.802675 DOMAIN: 0000 enabled
882 17:49:42.805955 DOMAIN: 0000 scanning...
883 17:49:42.808804 PCI: pci_scan_bus for bus 00
884 17:49:42.812105 PCI: 00:00.0 [8086/0000] ops
885 17:49:42.815770 PCI: 00:00.0 [8086/9b61] enabled
886 17:49:42.818719 PCI: 00:02.0 [8086/0000] bus ops
887 17:49:42.822018 PCI: 00:02.0 [8086/9b41] enabled
888 17:49:42.825698 PCI: 00:04.0 [8086/1903] disabled
889 17:49:42.828470 PCI: 00:08.0 [8086/1911] enabled
890 17:49:42.832230 PCI: 00:12.0 [8086/02f9] enabled
891 17:49:42.835362 PCI: 00:14.0 [8086/0000] bus ops
892 17:49:42.838798 PCI: 00:14.0 [8086/02ed] enabled
893 17:49:42.842002 PCI: 00:14.2 [8086/02ef] enabled
894 17:49:42.845349 PCI: 00:14.3 [8086/02f0] enabled
895 17:49:42.848287 PCI: 00:15.0 [8086/0000] bus ops
896 17:49:42.851999 PCI: 00:15.0 [8086/02e8] enabled
897 17:49:42.855568 PCI: 00:15.1 [8086/0000] bus ops
898 17:49:42.858697 PCI: 00:15.1 [8086/02e9] enabled
899 17:49:42.862228 PCI: 00:16.0 [8086/0000] ops
900 17:49:42.865088 PCI: 00:16.0 [8086/02e0] enabled
901 17:49:42.868506 PCI: 00:17.0 [8086/0000] ops
902 17:49:42.871910 PCI: 00:17.0 [8086/02d3] enabled
903 17:49:42.875420 PCI: 00:19.0 [8086/0000] bus ops
904 17:49:42.878192 PCI: 00:19.0 [8086/02c5] enabled
905 17:49:42.881667 PCI: 00:1d.0 [8086/0000] bus ops
906 17:49:42.885533 PCI: 00:1d.0 [8086/02b0] enabled
907 17:49:42.891597 PCI: Static device PCI: 00:1d.5 not found, disabling it.
908 17:49:42.892145 PCI: 00:1e.0 [8086/0000] ops
909 17:49:42.894883 PCI: 00:1e.0 [8086/02a8] enabled
910 17:49:42.898775 PCI: 00:1e.2 [8086/0000] bus ops
911 17:49:42.901899 PCI: 00:1e.2 [8086/02aa] enabled
912 17:49:42.905260 PCI: 00:1e.3 [8086/0000] bus ops
913 17:49:42.908081 PCI: 00:1e.3 [8086/02ab] enabled
914 17:49:42.911520 PCI: 00:1f.0 [8086/0000] bus ops
915 17:49:42.914857 PCI: 00:1f.0 [8086/0284] enabled
916 17:49:42.921608 PCI: Static device PCI: 00:1f.1 not found, disabling it.
917 17:49:42.928204 PCI: Static device PCI: 00:1f.2 not found, disabling it.
918 17:49:42.931739 PCI: 00:1f.3 [8086/0000] bus ops
919 17:49:42.934998 PCI: 00:1f.3 [8086/02c8] enabled
920 17:49:42.938270 PCI: 00:1f.4 [8086/0000] bus ops
921 17:49:42.941503 PCI: 00:1f.4 [8086/02a3] enabled
922 17:49:42.944780 PCI: 00:1f.5 [8086/0000] bus ops
923 17:49:42.948435 PCI: 00:1f.5 [8086/02a4] enabled
924 17:49:42.951689 PCI: Leftover static devices:
925 17:49:42.952108 PCI: 00:05.0
926 17:49:42.955197 PCI: 00:12.5
927 17:49:42.955723 PCI: 00:12.6
928 17:49:42.956060 PCI: 00:14.1
929 17:49:42.958617 PCI: 00:14.5
930 17:49:42.959144 PCI: 00:15.2
931 17:49:42.961524 PCI: 00:15.3
932 17:49:42.962054 PCI: 00:16.1
933 17:49:42.962393 PCI: 00:16.2
934 17:49:42.965386 PCI: 00:16.3
935 17:49:42.965913 PCI: 00:16.4
936 17:49:42.967977 PCI: 00:16.5
937 17:49:42.968398 PCI: 00:19.1
938 17:49:42.968733 PCI: 00:19.2
939 17:49:42.971598 PCI: 00:1a.0
940 17:49:42.972124 PCI: 00:1c.0
941 17:49:42.974924 PCI: 00:1c.1
942 17:49:42.975459 PCI: 00:1c.2
943 17:49:42.978421 PCI: 00:1c.3
944 17:49:42.979020 PCI: 00:1c.4
945 17:49:42.979383 PCI: 00:1c.5
946 17:49:42.981177 PCI: 00:1c.6
947 17:49:42.981594 PCI: 00:1c.7
948 17:49:42.984535 PCI: 00:1d.1
949 17:49:42.984954 PCI: 00:1d.2
950 17:49:42.985288 PCI: 00:1d.3
951 17:49:42.988107 PCI: 00:1d.4
952 17:49:42.988531 PCI: 00:1d.5
953 17:49:42.991297 PCI: 00:1e.1
954 17:49:42.991717 PCI: 00:1f.1
955 17:49:42.992047 PCI: 00:1f.2
956 17:49:42.994380 PCI: 00:1f.6
957 17:49:42.998499 PCI: Check your devicetree.cb.
958 17:49:43.001124 PCI: 00:02.0 scanning...
959 17:49:43.004866 scan_generic_bus for PCI: 00:02.0
960 17:49:43.008033 scan_generic_bus for PCI: 00:02.0 done
961 17:49:43.014593 scan_bus: scanning of bus PCI: 00:02.0 took 10182 usecs
962 17:49:43.015022 PCI: 00:14.0 scanning...
963 17:49:43.018554 scan_static_bus for PCI: 00:14.0
964 17:49:43.021447 USB0 port 0 enabled
965 17:49:43.024759 USB0 port 0 scanning...
966 17:49:43.028042 scan_static_bus for USB0 port 0
967 17:49:43.028588 USB2 port 0 enabled
968 17:49:43.031087 USB2 port 1 enabled
969 17:49:43.034460 USB2 port 2 disabled
970 17:49:43.035021 USB2 port 3 disabled
971 17:49:43.038173 USB2 port 5 disabled
972 17:49:43.040940 USB2 port 6 enabled
973 17:49:43.041378 USB2 port 9 enabled
974 17:49:43.044283 USB3 port 0 enabled
975 17:49:43.044813 USB3 port 1 enabled
976 17:49:43.047683 USB3 port 2 enabled
977 17:49:43.050957 USB3 port 3 enabled
978 17:49:43.051392 USB3 port 4 disabled
979 17:49:43.054607 USB2 port 0 scanning...
980 17:49:43.058221 scan_static_bus for USB2 port 0
981 17:49:43.060747 scan_static_bus for USB2 port 0 done
982 17:49:43.067438 scan_bus: scanning of bus USB2 port 0 took 9692 usecs
983 17:49:43.071066 USB2 port 1 scanning...
984 17:49:43.074322 scan_static_bus for USB2 port 1
985 17:49:43.077713 scan_static_bus for USB2 port 1 done
986 17:49:43.080595 scan_bus: scanning of bus USB2 port 1 took 9694 usecs
987 17:49:43.084395 USB2 port 6 scanning...
988 17:49:43.087683 scan_static_bus for USB2 port 6
989 17:49:43.090763 scan_static_bus for USB2 port 6 done
990 17:49:43.097693 scan_bus: scanning of bus USB2 port 6 took 9703 usecs
991 17:49:43.101004 USB2 port 9 scanning...
992 17:49:43.104203 scan_static_bus for USB2 port 9
993 17:49:43.107535 scan_static_bus for USB2 port 9 done
994 17:49:43.110959 scan_bus: scanning of bus USB2 port 9 took 9702 usecs
995 17:49:43.114165 USB3 port 0 scanning...
996 17:49:43.117231 scan_static_bus for USB3 port 0
997 17:49:43.120901 scan_static_bus for USB3 port 0 done
998 17:49:43.127432 scan_bus: scanning of bus USB3 port 0 took 9703 usecs
999 17:49:43.130731 USB3 port 1 scanning...
1000 17:49:43.133939 scan_static_bus for USB3 port 1
1001 17:49:43.137181 scan_static_bus for USB3 port 1 done
1002 17:49:43.140287 scan_bus: scanning of bus USB3 port 1 took 9700 usecs
1003 17:49:43.144049 USB3 port 2 scanning...
1004 17:49:43.147039 scan_static_bus for USB3 port 2
1005 17:49:43.150571 scan_static_bus for USB3 port 2 done
1006 17:49:43.156956 scan_bus: scanning of bus USB3 port 2 took 9704 usecs
1007 17:49:43.160194 USB3 port 3 scanning...
1008 17:49:43.163526 scan_static_bus for USB3 port 3
1009 17:49:43.167244 scan_static_bus for USB3 port 3 done
1010 17:49:43.173530 scan_bus: scanning of bus USB3 port 3 took 9704 usecs
1011 17:49:43.176879 scan_static_bus for USB0 port 0 done
1012 17:49:43.179882 scan_bus: scanning of bus USB0 port 0 took 155350 usecs
1013 17:49:43.183702 scan_static_bus for PCI: 00:14.0 done
1014 17:49:43.190634 scan_bus: scanning of bus PCI: 00:14.0 took 172967 usecs
1015 17:49:43.193331 PCI: 00:15.0 scanning...
1016 17:49:43.196621 scan_generic_bus for PCI: 00:15.0
1017 17:49:43.200211 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
1018 17:49:43.203611 scan_generic_bus for PCI: 00:15.0 done
1019 17:49:43.209905 scan_bus: scanning of bus PCI: 00:15.0 took 14314 usecs
1020 17:49:43.213254 PCI: 00:15.1 scanning...
1021 17:49:43.216813 scan_generic_bus for PCI: 00:15.1
1022 17:49:43.220214 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
1023 17:49:43.223396 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
1024 17:49:43.229777 scan_generic_bus for PCI: 00:15.1 done
1025 17:49:43.233446 scan_bus: scanning of bus PCI: 00:15.1 took 18589 usecs
1026 17:49:43.236678 PCI: 00:19.0 scanning...
1027 17:49:43.240118 scan_generic_bus for PCI: 00:19.0
1028 17:49:43.243608 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
1029 17:49:43.250155 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
1030 17:49:43.253747 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
1031 17:49:43.256834 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
1032 17:49:43.259811 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
1033 17:49:43.266746 scan_generic_bus for PCI: 00:19.0 done
1034 17:49:43.269815 scan_bus: scanning of bus PCI: 00:19.0 took 30735 usecs
1035 17:49:43.273453 PCI: 00:1d.0 scanning...
1036 17:49:43.276141 do_pci_scan_bridge for PCI: 00:1d.0
1037 17:49:43.279873 PCI: pci_scan_bus for bus 01
1038 17:49:43.282993 PCI: 01:00.0 [1c5c/1327] enabled
1039 17:49:43.286517 Enabling Common Clock Configuration
1040 17:49:43.289857 L1 Sub-State supported from root port 29
1041 17:49:43.293759 L1 Sub-State Support = 0xf
1042 17:49:43.296836 CommonModeRestoreTime = 0x28
1043 17:49:43.300184 Power On Value = 0x16, Power On Scale = 0x0
1044 17:49:43.303441 ASPM: Enabled L1
1045 17:49:43.310431 scan_bus: scanning of bus PCI: 00:1d.0 took 32777 usecs
1046 17:49:43.310995 PCI: 00:1e.2 scanning...
1047 17:49:43.316353 scan_generic_bus for PCI: 00:1e.2
1048 17:49:43.320247 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1049 17:49:43.323431 scan_generic_bus for PCI: 00:1e.2 done
1050 17:49:43.330096 scan_bus: scanning of bus PCI: 00:1e.2 took 13993 usecs
1051 17:49:43.330710 PCI: 00:1e.3 scanning...
1052 17:49:43.333249 scan_generic_bus for PCI: 00:1e.3
1053 17:49:43.339858 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1054 17:49:43.343405 scan_generic_bus for PCI: 00:1e.3 done
1055 17:49:43.346483 scan_bus: scanning of bus PCI: 00:1e.3 took 13987 usecs
1056 17:49:43.349655 PCI: 00:1f.0 scanning...
1057 17:49:43.352932 scan_static_bus for PCI: 00:1f.0
1058 17:49:43.356736 PNP: 0c09.0 enabled
1059 17:49:43.359577 scan_static_bus for PCI: 00:1f.0 done
1060 17:49:43.366586 scan_bus: scanning of bus PCI: 00:1f.0 took 12036 usecs
1061 17:49:43.367094 PCI: 00:1f.3 scanning...
1062 17:49:43.373676 scan_bus: scanning of bus PCI: 00:1f.3 took 2858 usecs
1063 17:49:43.376480 PCI: 00:1f.4 scanning...
1064 17:49:43.379703 scan_generic_bus for PCI: 00:1f.4
1065 17:49:43.383148 scan_generic_bus for PCI: 00:1f.4 done
1066 17:49:43.389848 scan_bus: scanning of bus PCI: 00:1f.4 took 10191 usecs
1067 17:49:43.393180 PCI: 00:1f.5 scanning...
1068 17:49:43.396091 scan_generic_bus for PCI: 00:1f.5
1069 17:49:43.399886 scan_generic_bus for PCI: 00:1f.5 done
1070 17:49:43.406413 scan_bus: scanning of bus PCI: 00:1f.5 took 10184 usecs
1071 17:49:43.409918 scan_bus: scanning of bus DOMAIN: 0000 took 604801 usecs
1072 17:49:43.412721 scan_static_bus for Root Device done
1073 17:49:43.419397 scan_bus: scanning of bus Root Device took 624677 usecs
1074 17:49:43.419899 done
1075 17:49:43.422816 Chrome EC: UHEPI supported
1076 17:49:43.429956 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1077 17:49:43.436566 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1078 17:49:43.442840 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1079 17:49:43.449340 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1080 17:49:43.452801 SPI flash protection: WPSW=0 SRP0=0
1081 17:49:43.455935 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1082 17:49:43.462458 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 9 exit 2
1083 17:49:43.466103 found VGA at PCI: 00:02.0
1084 17:49:43.469088 Setting up VGA for PCI: 00:02.0
1085 17:49:43.472823 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1086 17:49:43.479005 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1087 17:49:43.482386 Allocating resources...
1088 17:49:43.483059 Reading resources...
1089 17:49:43.488909 Root Device read_resources bus 0 link: 0
1090 17:49:43.492380 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1091 17:49:43.495522 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1092 17:49:43.502572 DOMAIN: 0000 read_resources bus 0 link: 0
1093 17:49:43.509318 PCI: 00:14.0 read_resources bus 0 link: 0
1094 17:49:43.512158 USB0 port 0 read_resources bus 0 link: 0
1095 17:49:43.519765 USB0 port 0 read_resources bus 0 link: 0 done
1096 17:49:43.523326 PCI: 00:14.0 read_resources bus 0 link: 0 done
1097 17:49:43.530619 PCI: 00:15.0 read_resources bus 1 link: 0
1098 17:49:43.533507 PCI: 00:15.0 read_resources bus 1 link: 0 done
1099 17:49:43.540762 PCI: 00:15.1 read_resources bus 2 link: 0
1100 17:49:43.543510 PCI: 00:15.1 read_resources bus 2 link: 0 done
1101 17:49:43.550990 PCI: 00:19.0 read_resources bus 3 link: 0
1102 17:49:43.558400 PCI: 00:19.0 read_resources bus 3 link: 0 done
1103 17:49:43.561114 PCI: 00:1d.0 read_resources bus 1 link: 0
1104 17:49:43.567878 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1105 17:49:43.571183 PCI: 00:1e.2 read_resources bus 4 link: 0
1106 17:49:43.577993 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1107 17:49:43.581353 PCI: 00:1e.3 read_resources bus 5 link: 0
1108 17:49:43.587834 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1109 17:49:43.590864 PCI: 00:1f.0 read_resources bus 0 link: 0
1110 17:49:43.598119 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1111 17:49:43.604584 DOMAIN: 0000 read_resources bus 0 link: 0 done
1112 17:49:43.607457 Root Device read_resources bus 0 link: 0 done
1113 17:49:43.611259 Done reading resources.
1114 17:49:43.614201 Show resources in subtree (Root Device)...After reading.
1115 17:49:43.621545 Root Device child on link 0 CPU_CLUSTER: 0
1116 17:49:43.624353 CPU_CLUSTER: 0 child on link 0 APIC: 00
1117 17:49:43.624769 APIC: 00
1118 17:49:43.627835 APIC: 01
1119 17:49:43.628343 APIC: 05
1120 17:49:43.631030 APIC: 04
1121 17:49:43.631447 APIC: 07
1122 17:49:43.631780 APIC: 06
1123 17:49:43.634715 APIC: 03
1124 17:49:43.635258 APIC: 02
1125 17:49:43.637851 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1126 17:49:43.648117 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1127 17:49:43.697648 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1128 17:49:43.698324 PCI: 00:00.0
1129 17:49:43.699089 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1130 17:49:43.699441 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1131 17:49:43.699757 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1132 17:49:43.700206 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1133 17:49:43.705445 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1134 17:49:43.715111 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1135 17:49:43.725460 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1136 17:49:43.734693 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1137 17:49:43.744689 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1138 17:49:43.751248 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1139 17:49:43.761376 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1140 17:49:43.771146 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1141 17:49:43.781186 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1142 17:49:43.790843 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1143 17:49:43.801395 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1144 17:49:43.811099 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1145 17:49:43.811520 PCI: 00:02.0
1146 17:49:43.820895 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1147 17:49:43.831021 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1148 17:49:43.840732 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1149 17:49:43.841223 PCI: 00:04.0
1150 17:49:43.844396 PCI: 00:08.0
1151 17:49:43.854452 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1152 17:49:43.855010 PCI: 00:12.0
1153 17:49:43.863961 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1154 17:49:43.870721 PCI: 00:14.0 child on link 0 USB0 port 0
1155 17:49:43.880537 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1156 17:49:43.884027 USB0 port 0 child on link 0 USB2 port 0
1157 17:49:43.884546 USB2 port 0
1158 17:49:43.887228 USB2 port 1
1159 17:49:43.887668 USB2 port 2
1160 17:49:43.890703 USB2 port 3
1161 17:49:43.893788 USB2 port 5
1162 17:49:43.894224 USB2 port 6
1163 17:49:43.897599 USB2 port 9
1164 17:49:43.898098 USB3 port 0
1165 17:49:43.900734 USB3 port 1
1166 17:49:43.901237 USB3 port 2
1167 17:49:43.903872 USB3 port 3
1168 17:49:43.904381 USB3 port 4
1169 17:49:43.907589 PCI: 00:14.2
1170 17:49:43.917225 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1171 17:49:43.927208 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1172 17:49:43.927717 PCI: 00:14.3
1173 17:49:43.937450 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1174 17:49:43.940259 PCI: 00:15.0 child on link 0 I2C: 01:15
1175 17:49:43.950287 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1176 17:49:43.953817 I2C: 01:15
1177 17:49:43.957351 PCI: 00:15.1 child on link 0 I2C: 02:5d
1178 17:49:43.967169 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1179 17:49:43.970681 I2C: 02:5d
1180 17:49:43.971187 GENERIC: 0.0
1181 17:49:43.973742 PCI: 00:16.0
1182 17:49:43.983670 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1183 17:49:43.984182 PCI: 00:17.0
1184 17:49:43.993763 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1185 17:49:44.003411 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1186 17:49:44.010292 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1187 17:49:44.020236 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1188 17:49:44.026871 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1189 17:49:44.036817 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1190 17:49:44.040015 PCI: 00:19.0 child on link 0 I2C: 03:1a
1191 17:49:44.050155 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1192 17:49:44.053483 I2C: 03:1a
1193 17:49:44.053985 I2C: 03:38
1194 17:49:44.056496 I2C: 03:39
1195 17:49:44.056998 I2C: 03:3a
1196 17:49:44.059769 I2C: 03:3b
1197 17:49:44.063214 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1198 17:49:44.070106 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1199 17:49:44.079372 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1200 17:49:44.089499 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1201 17:49:44.093091 PCI: 01:00.0
1202 17:49:44.102446 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1203 17:49:44.103020 PCI: 00:1e.0
1204 17:49:44.116134 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1205 17:49:44.126128 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1206 17:49:44.129100 PCI: 00:1e.2 child on link 0 SPI: 00
1207 17:49:44.139232 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1208 17:49:44.139745 SPI: 00
1209 17:49:44.142156 PCI: 00:1e.3 child on link 0 SPI: 01
1210 17:49:44.152377 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1211 17:49:44.155617 SPI: 01
1212 17:49:44.158638 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1213 17:49:44.168949 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1214 17:49:44.175408 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1215 17:49:44.178623 PNP: 0c09.0
1216 17:49:44.189076 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1217 17:49:44.189582 PCI: 00:1f.3
1218 17:49:44.198443 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1219 17:49:44.208296 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1220 17:49:44.211508 PCI: 00:1f.4
1221 17:49:44.218850 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1222 17:49:44.228410 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1223 17:49:44.231999 PCI: 00:1f.5
1224 17:49:44.241706 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1225 17:49:44.244782 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1226 17:49:44.251572 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1227 17:49:44.258250 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1228 17:49:44.261572 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1229 17:49:44.268030 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1230 17:49:44.271583 PCI: 00:17.0 18 * [0x60 - 0x67] io
1231 17:49:44.274423 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1232 17:49:44.281290 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1233 17:49:44.288084 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1234 17:49:44.294765 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1235 17:49:44.304713 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1236 17:49:44.311347 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1237 17:49:44.314454 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1238 17:49:44.321736 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1239 17:49:44.328501 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1240 17:49:44.331600 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1241 17:49:44.338295 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1242 17:49:44.341394 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1243 17:49:44.347716 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1244 17:49:44.351037 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1245 17:49:44.354679 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1246 17:49:44.361227 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1247 17:49:44.365086 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1248 17:49:44.371329 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1249 17:49:44.374610 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1250 17:49:44.380960 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1251 17:49:44.384664 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1252 17:49:44.391157 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1253 17:49:44.394393 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1254 17:49:44.401063 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1255 17:49:44.404604 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1256 17:49:44.410870 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1257 17:49:44.413883 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1258 17:49:44.420819 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1259 17:49:44.424014 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1260 17:49:44.427820 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1261 17:49:44.434804 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1262 17:49:44.444375 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1263 17:49:44.448065 avoid_fixed_resources: DOMAIN: 0000
1264 17:49:44.450569 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1265 17:49:44.457341 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1266 17:49:44.464005 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1267 17:49:44.474265 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1268 17:49:44.480887 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1269 17:49:44.487112 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1270 17:49:44.496869 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1271 17:49:44.503657 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1272 17:49:44.510163 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1273 17:49:44.520508 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1274 17:49:44.527122 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1275 17:49:44.533762 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1276 17:49:44.536888 Setting resources...
1277 17:49:44.543988 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1278 17:49:44.547243 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1279 17:49:44.550584 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1280 17:49:44.553471 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1281 17:49:44.556860 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1282 17:49:44.562954 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1283 17:49:44.570068 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1284 17:49:44.576607 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1285 17:49:44.583361 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1286 17:49:44.590117 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1287 17:49:44.593227 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1288 17:49:44.599975 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1289 17:49:44.603551 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1290 17:49:44.610402 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1291 17:49:44.613316 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1292 17:49:44.620021 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1293 17:49:44.623529 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1294 17:49:44.629955 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1295 17:49:44.633313 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1296 17:49:44.640037 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1297 17:49:44.643142 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1298 17:49:44.646985 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1299 17:49:44.653016 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1300 17:49:44.656368 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1301 17:49:44.663238 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1302 17:49:44.666273 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1303 17:49:44.672672 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1304 17:49:44.676507 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1305 17:49:44.682891 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1306 17:49:44.686090 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1307 17:49:44.692794 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1308 17:49:44.696044 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1309 17:49:44.703017 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1310 17:49:44.712345 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1311 17:49:44.719255 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1312 17:49:44.726003 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1313 17:49:44.732618 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1314 17:49:44.739442 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1315 17:49:44.742668 Root Device assign_resources, bus 0 link: 0
1316 17:49:44.749224 DOMAIN: 0000 assign_resources, bus 0 link: 0
1317 17:49:44.756089 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1318 17:49:44.765365 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1319 17:49:44.772291 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1320 17:49:44.781939 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1321 17:49:44.788455 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1322 17:49:44.798572 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1323 17:49:44.801945 PCI: 00:14.0 assign_resources, bus 0 link: 0
1324 17:49:44.805357 PCI: 00:14.0 assign_resources, bus 0 link: 0
1325 17:49:44.815699 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1326 17:49:44.821857 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1327 17:49:44.832181 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1328 17:49:44.838677 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1329 17:49:44.844998 PCI: 00:15.0 assign_resources, bus 1 link: 0
1330 17:49:44.848319 PCI: 00:15.0 assign_resources, bus 1 link: 0
1331 17:49:44.858485 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1332 17:49:44.861636 PCI: 00:15.1 assign_resources, bus 2 link: 0
1333 17:49:44.864877 PCI: 00:15.1 assign_resources, bus 2 link: 0
1334 17:49:44.875452 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1335 17:49:44.881645 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1336 17:49:44.891128 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1337 17:49:44.898129 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1338 17:49:44.904592 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1339 17:49:44.914731 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1340 17:49:44.921083 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1341 17:49:44.927685 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1342 17:49:44.934618 PCI: 00:19.0 assign_resources, bus 3 link: 0
1343 17:49:44.937879 PCI: 00:19.0 assign_resources, bus 3 link: 0
1344 17:49:44.947907 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1345 17:49:44.957852 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1346 17:49:44.964377 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1347 17:49:44.967830 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1348 17:49:44.977545 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1349 17:49:44.980889 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1350 17:49:44.990765 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1351 17:49:44.997630 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1352 17:49:45.004009 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1353 17:49:45.007415 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1354 17:49:45.016931 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1355 17:49:45.020861 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1356 17:49:45.023851 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1357 17:49:45.030714 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1358 17:49:45.034043 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1359 17:49:45.040762 LPC: Trying to open IO window from 800 size 1ff
1360 17:49:45.047431 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1361 17:49:45.057136 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1362 17:49:45.063850 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1363 17:49:45.073443 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1364 17:49:45.076953 DOMAIN: 0000 assign_resources, bus 0 link: 0
1365 17:49:45.083778 Root Device assign_resources, bus 0 link: 0
1366 17:49:45.084295 Done setting resources.
1367 17:49:45.089988 Show resources in subtree (Root Device)...After assigning values.
1368 17:49:45.096717 Root Device child on link 0 CPU_CLUSTER: 0
1369 17:49:45.420671 CPU_CLUSTER: 0 child on link 0 APIC: 00
1370 17:49:45.421184 APIC: 00
1371 17:49:45.421864 APIC: 01
1372 17:49:45.422193 APIC: 05
1373 17:49:45.422490 APIC: 04
1374 17:49:45.422817 APIC: 07
1375 17:49:45.423098 APIC: 06
1376 17:49:45.423376 APIC: 03
1377 17:49:45.423647 APIC: 02
1378 17:49:45.423917 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1379 17:49:45.424191 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1380 17:49:45.424469 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1381 17:49:45.424744 PCI: 00:00.0
1382 17:49:45.425013 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1383 17:49:45.425288 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1384 17:49:45.425562 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1385 17:49:45.425833 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1386 17:49:45.426104 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1387 17:49:45.426375 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1388 17:49:45.426671 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1389 17:49:45.426945 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1390 17:49:45.427217 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1391 17:49:45.427486 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1392 17:49:45.427757 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1393 17:49:45.428025 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1394 17:49:45.428297 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1395 17:49:45.428568 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1396 17:49:45.428841 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1397 17:49:45.429220 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1398 17:49:45.429503 PCI: 00:02.0
1399 17:49:45.429774 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1400 17:49:45.430049 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1401 17:49:45.430323 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1402 17:49:45.430620 PCI: 00:04.0
1403 17:49:45.430890 PCI: 00:08.0
1404 17:49:45.431158 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1405 17:49:45.431429 PCI: 00:12.0
1406 17:49:45.431694 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1407 17:49:45.431965 PCI: 00:14.0 child on link 0 USB0 port 0
1408 17:49:45.432231 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1409 17:49:45.432502 USB0 port 0 child on link 0 USB2 port 0
1410 17:49:45.432771 USB2 port 0
1411 17:49:45.433037 USB2 port 1
1412 17:49:45.433299 USB2 port 2
1413 17:49:45.433564 USB2 port 3
1414 17:49:45.433828 USB2 port 5
1415 17:49:45.434090 USB2 port 6
1416 17:49:45.434353 USB2 port 9
1417 17:49:45.434637 USB3 port 0
1418 17:49:45.434905 USB3 port 1
1419 17:49:45.435168 USB3 port 2
1420 17:49:45.435433 USB3 port 3
1421 17:49:45.435696 USB3 port 4
1422 17:49:45.435959 PCI: 00:14.2
1423 17:49:45.436225 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1424 17:49:45.436499 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1425 17:49:45.436769 PCI: 00:14.3
1426 17:49:45.437037 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1427 17:49:45.437371 PCI: 00:15.0 child on link 0 I2C: 01:15
1428 17:49:45.437655 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1429 17:49:45.437926 I2C: 01:15
1430 17:49:45.440459 PCI: 00:15.1 child on link 0 I2C: 02:5d
1431 17:49:45.450371 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1432 17:49:45.450960 I2C: 02:5d
1433 17:49:45.453299 GENERIC: 0.0
1434 17:49:45.453701 PCI: 00:16.0
1435 17:49:45.463020 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1436 17:49:45.466644 PCI: 00:17.0
1437 17:49:45.476724 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1438 17:49:45.486441 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1439 17:49:45.496480 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1440 17:49:45.506627 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1441 17:49:45.513129 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1442 17:49:45.522983 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1443 17:49:45.529673 PCI: 00:19.0 child on link 0 I2C: 03:1a
1444 17:49:45.539081 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1445 17:49:45.539590 I2C: 03:1a
1446 17:49:45.542593 I2C: 03:38
1447 17:49:45.543009 I2C: 03:39
1448 17:49:45.545593 I2C: 03:3a
1449 17:49:45.546007 I2C: 03:3b
1450 17:49:45.552742 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1451 17:49:45.558971 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1452 17:49:45.568783 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1453 17:49:45.581824 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1454 17:49:45.581985 PCI: 01:00.0
1455 17:49:45.591577 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1456 17:49:45.595025 PCI: 00:1e.0
1457 17:49:45.605244 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1458 17:49:45.614834 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1459 17:49:45.618162 PCI: 00:1e.2 child on link 0 SPI: 00
1460 17:49:45.631705 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1461 17:49:45.631870 SPI: 00
1462 17:49:45.635304 PCI: 00:1e.3 child on link 0 SPI: 01
1463 17:49:45.644666 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1464 17:49:45.648417 SPI: 01
1465 17:49:45.651350 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1466 17:49:45.661736 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1467 17:49:45.667922 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1468 17:49:45.671370 PNP: 0c09.0
1469 17:49:45.677438 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1470 17:49:45.680902 PCI: 00:1f.3
1471 17:49:45.691006 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1472 17:49:45.701304 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1473 17:49:45.704379 PCI: 00:1f.4
1474 17:49:45.714484 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1475 17:49:45.724629 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1476 17:49:45.725155 PCI: 00:1f.5
1477 17:49:45.734132 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1478 17:49:45.737703 Done allocating resources.
1479 17:49:45.744296 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1480 17:49:45.747277 Enabling resources...
1481 17:49:45.751149 PCI: 00:00.0 subsystem <- 8086/9b61
1482 17:49:45.753995 PCI: 00:00.0 cmd <- 06
1483 17:49:45.757700 PCI: 00:02.0 subsystem <- 8086/9b41
1484 17:49:45.758218 PCI: 00:02.0 cmd <- 03
1485 17:49:45.761209 PCI: 00:08.0 cmd <- 06
1486 17:49:45.764265 PCI: 00:12.0 subsystem <- 8086/02f9
1487 17:49:45.767750 PCI: 00:12.0 cmd <- 02
1488 17:49:45.770993 PCI: 00:14.0 subsystem <- 8086/02ed
1489 17:49:45.774053 PCI: 00:14.0 cmd <- 02
1490 17:49:45.777610 PCI: 00:14.2 cmd <- 02
1491 17:49:45.780951 PCI: 00:14.3 subsystem <- 8086/02f0
1492 17:49:45.784448 PCI: 00:14.3 cmd <- 02
1493 17:49:45.787251 PCI: 00:15.0 subsystem <- 8086/02e8
1494 17:49:45.790812 PCI: 00:15.0 cmd <- 02
1495 17:49:45.793675 PCI: 00:15.1 subsystem <- 8086/02e9
1496 17:49:45.794095 PCI: 00:15.1 cmd <- 02
1497 17:49:45.800841 PCI: 00:16.0 subsystem <- 8086/02e0
1498 17:49:45.801255 PCI: 00:16.0 cmd <- 02
1499 17:49:45.804298 PCI: 00:17.0 subsystem <- 8086/02d3
1500 17:49:45.807129 PCI: 00:17.0 cmd <- 03
1501 17:49:45.810903 PCI: 00:19.0 subsystem <- 8086/02c5
1502 17:49:45.813988 PCI: 00:19.0 cmd <- 02
1503 17:49:45.817604 PCI: 00:1d.0 bridge ctrl <- 0013
1504 17:49:45.820770 PCI: 00:1d.0 subsystem <- 8086/02b0
1505 17:49:45.824124 PCI: 00:1d.0 cmd <- 06
1506 17:49:45.827298 PCI: 00:1e.0 subsystem <- 8086/02a8
1507 17:49:45.830900 PCI: 00:1e.0 cmd <- 06
1508 17:49:45.833808 PCI: 00:1e.2 subsystem <- 8086/02aa
1509 17:49:45.837242 PCI: 00:1e.2 cmd <- 06
1510 17:49:45.840277 PCI: 00:1e.3 subsystem <- 8086/02ab
1511 17:49:45.843985 PCI: 00:1e.3 cmd <- 02
1512 17:49:45.846970 PCI: 00:1f.0 subsystem <- 8086/0284
1513 17:49:45.850943 PCI: 00:1f.0 cmd <- 407
1514 17:49:45.853866 PCI: 00:1f.3 subsystem <- 8086/02c8
1515 17:49:45.854582 PCI: 00:1f.3 cmd <- 02
1516 17:49:45.860956 PCI: 00:1f.4 subsystem <- 8086/02a3
1517 17:49:45.861473 PCI: 00:1f.4 cmd <- 03
1518 17:49:45.864570 PCI: 00:1f.5 subsystem <- 8086/02a4
1519 17:49:45.867450 PCI: 00:1f.5 cmd <- 406
1520 17:49:45.876913 PCI: 01:00.0 cmd <- 02
1521 17:49:45.882415 done.
1522 17:49:45.895329 ME: Version: 14.0.39.1367
1523 17:49:45.901917 BS: BS_DEV_ENABLE times (ms): entry 0 run 18 exit 12
1524 17:49:45.904979 Initializing devices...
1525 17:49:45.905394 Root Device init ...
1526 17:49:45.911902 Chrome EC: Set SMI mask to 0x0000000000000000
1527 17:49:45.915088 Chrome EC: clear events_b mask to 0x0000000000000000
1528 17:49:45.922092 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1529 17:49:45.928260 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1530 17:49:45.935233 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1531 17:49:45.938152 Chrome EC: Set WAKE mask to 0x0000000000000000
1532 17:49:45.942020 Root Device init finished in 35192 usecs
1533 17:49:45.945089 CPU_CLUSTER: 0 init ...
1534 17:49:45.951679 CPU_CLUSTER: 0 init finished in 2449 usecs
1535 17:49:45.956490 PCI: 00:00.0 init ...
1536 17:49:45.959495 CPU TDP: 15 Watts
1537 17:49:45.963065 CPU PL2 = 64 Watts
1538 17:49:45.965994 PCI: 00:00.0 init finished in 7083 usecs
1539 17:49:45.969794 PCI: 00:02.0 init ...
1540 17:49:45.972743 PCI: 00:02.0 init finished in 2247 usecs
1541 17:49:45.976189 PCI: 00:08.0 init ...
1542 17:49:45.979465 PCI: 00:08.0 init finished in 2254 usecs
1543 17:49:45.982689 PCI: 00:12.0 init ...
1544 17:49:45.986071 PCI: 00:12.0 init finished in 2253 usecs
1545 17:49:45.989131 PCI: 00:14.0 init ...
1546 17:49:45.992417 PCI: 00:14.0 init finished in 2254 usecs
1547 17:49:45.995911 PCI: 00:14.2 init ...
1548 17:49:45.998889 PCI: 00:14.2 init finished in 2252 usecs
1549 17:49:46.002596 PCI: 00:14.3 init ...
1550 17:49:46.005704 PCI: 00:14.3 init finished in 2272 usecs
1551 17:49:46.009070 PCI: 00:15.0 init ...
1552 17:49:46.012237 DW I2C bus 0 at 0xd121f000 (400 KHz)
1553 17:49:46.015810 PCI: 00:15.0 init finished in 5982 usecs
1554 17:49:46.019183 PCI: 00:15.1 init ...
1555 17:49:46.022296 DW I2C bus 1 at 0xd1220000 (400 KHz)
1556 17:49:46.028858 PCI: 00:15.1 init finished in 5980 usecs
1557 17:49:46.029381 PCI: 00:16.0 init ...
1558 17:49:46.035286 PCI: 00:16.0 init finished in 2253 usecs
1559 17:49:46.035703 PCI: 00:19.0 init ...
1560 17:49:46.041928 DW I2C bus 4 at 0xd1222000 (400 KHz)
1561 17:49:46.045595 PCI: 00:19.0 init finished in 5980 usecs
1562 17:49:46.048990 PCI: 00:1d.0 init ...
1563 17:49:46.051953 Initializing PCH PCIe bridge.
1564 17:49:46.055100 PCI: 00:1d.0 init finished in 5288 usecs
1565 17:49:46.058701 PCI: 00:1f.0 init ...
1566 17:49:46.061994 IOAPIC: Initializing IOAPIC at 0xfec00000
1567 17:49:46.068473 IOAPIC: Bootstrap Processor Local APIC = 0x00
1568 17:49:46.069011 IOAPIC: ID = 0x02
1569 17:49:46.071854 IOAPIC: Dumping registers
1570 17:49:46.075432 reg 0x0000: 0x02000000
1571 17:49:46.078335 reg 0x0001: 0x00770020
1572 17:49:46.078790 reg 0x0002: 0x00000000
1573 17:49:46.085124 PCI: 00:1f.0 init finished in 23558 usecs
1574 17:49:46.088519 PCI: 00:1f.4 init ...
1575 17:49:46.091398 PCI: 00:1f.4 init finished in 2263 usecs
1576 17:49:46.102715 PCI: 01:00.0 init ...
1577 17:49:46.105663 PCI: 01:00.0 init finished in 2255 usecs
1578 17:49:46.110093 PNP: 0c09.0 init ...
1579 17:49:46.113108 Google Chrome EC uptime: 11.097 seconds
1580 17:49:46.119632 Google Chrome AP resets since EC boot: 0
1581 17:49:46.123161 Google Chrome most recent AP reset causes:
1582 17:49:46.129557 Google Chrome EC reset flags at last EC boot: reset-pin
1583 17:49:46.133374 PNP: 0c09.0 init finished in 20586 usecs
1584 17:49:46.136163 Devices initialized
1585 17:49:46.139742 Show all devs... After init.
1586 17:49:46.140263 Root Device: enabled 1
1587 17:49:46.142862 CPU_CLUSTER: 0: enabled 1
1588 17:49:46.146415 DOMAIN: 0000: enabled 1
1589 17:49:46.146965 APIC: 00: enabled 1
1590 17:49:46.149630 PCI: 00:00.0: enabled 1
1591 17:49:46.153054 PCI: 00:02.0: enabled 1
1592 17:49:46.156036 PCI: 00:04.0: enabled 0
1593 17:49:46.156449 PCI: 00:05.0: enabled 0
1594 17:49:46.159180 PCI: 00:12.0: enabled 1
1595 17:49:46.162677 PCI: 00:12.5: enabled 0
1596 17:49:46.166421 PCI: 00:12.6: enabled 0
1597 17:49:46.166995 PCI: 00:14.0: enabled 1
1598 17:49:46.169611 PCI: 00:14.1: enabled 0
1599 17:49:46.172598 PCI: 00:14.3: enabled 1
1600 17:49:46.173111 PCI: 00:14.5: enabled 0
1601 17:49:46.176139 PCI: 00:15.0: enabled 1
1602 17:49:46.179307 PCI: 00:15.1: enabled 1
1603 17:49:46.182444 PCI: 00:15.2: enabled 0
1604 17:49:46.182888 PCI: 00:15.3: enabled 0
1605 17:49:46.185877 PCI: 00:16.0: enabled 1
1606 17:49:46.189056 PCI: 00:16.1: enabled 0
1607 17:49:46.192469 PCI: 00:16.2: enabled 0
1608 17:49:46.192986 PCI: 00:16.3: enabled 0
1609 17:49:46.195462 PCI: 00:16.4: enabled 0
1610 17:49:46.198505 PCI: 00:16.5: enabled 0
1611 17:49:46.202494 PCI: 00:17.0: enabled 1
1612 17:49:46.203058 PCI: 00:19.0: enabled 1
1613 17:49:46.205381 PCI: 00:19.1: enabled 0
1614 17:49:46.208629 PCI: 00:19.2: enabled 0
1615 17:49:46.212283 PCI: 00:1a.0: enabled 0
1616 17:49:46.212801 PCI: 00:1c.0: enabled 0
1617 17:49:46.215053 PCI: 00:1c.1: enabled 0
1618 17:49:46.218628 PCI: 00:1c.2: enabled 0
1619 17:49:46.222168 PCI: 00:1c.3: enabled 0
1620 17:49:46.222731 PCI: 00:1c.4: enabled 0
1621 17:49:46.225368 PCI: 00:1c.5: enabled 0
1622 17:49:46.228475 PCI: 00:1c.6: enabled 0
1623 17:49:46.228886 PCI: 00:1c.7: enabled 0
1624 17:49:46.231987 PCI: 00:1d.0: enabled 1
1625 17:49:46.234903 PCI: 00:1d.1: enabled 0
1626 17:49:46.238632 PCI: 00:1d.2: enabled 0
1627 17:49:46.239140 PCI: 00:1d.3: enabled 0
1628 17:49:46.242255 PCI: 00:1d.4: enabled 0
1629 17:49:46.245330 PCI: 00:1d.5: enabled 0
1630 17:49:46.249032 PCI: 00:1e.0: enabled 1
1631 17:49:46.249541 PCI: 00:1e.1: enabled 0
1632 17:49:46.251877 PCI: 00:1e.2: enabled 1
1633 17:49:46.255456 PCI: 00:1e.3: enabled 1
1634 17:49:46.258358 PCI: 00:1f.0: enabled 1
1635 17:49:46.258900 PCI: 00:1f.1: enabled 0
1636 17:49:46.261336 PCI: 00:1f.2: enabled 0
1637 17:49:46.265063 PCI: 00:1f.3: enabled 1
1638 17:49:46.265473 PCI: 00:1f.4: enabled 1
1639 17:49:46.268128 PCI: 00:1f.5: enabled 1
1640 17:49:46.272242 PCI: 00:1f.6: enabled 0
1641 17:49:46.274887 USB0 port 0: enabled 1
1642 17:49:46.275297 I2C: 01:15: enabled 1
1643 17:49:46.278336 I2C: 02:5d: enabled 1
1644 17:49:46.281774 GENERIC: 0.0: enabled 1
1645 17:49:46.282294 I2C: 03:1a: enabled 1
1646 17:49:46.284902 I2C: 03:38: enabled 1
1647 17:49:46.288389 I2C: 03:39: enabled 1
1648 17:49:46.288902 I2C: 03:3a: enabled 1
1649 17:49:46.291856 I2C: 03:3b: enabled 1
1650 17:49:46.294825 PCI: 00:00.0: enabled 1
1651 17:49:46.295343 SPI: 00: enabled 1
1652 17:49:46.298139 SPI: 01: enabled 1
1653 17:49:46.301418 PNP: 0c09.0: enabled 1
1654 17:49:46.301970 USB2 port 0: enabled 1
1655 17:49:46.304897 USB2 port 1: enabled 1
1656 17:49:46.307778 USB2 port 2: enabled 0
1657 17:49:46.311320 USB2 port 3: enabled 0
1658 17:49:46.311734 USB2 port 5: enabled 0
1659 17:49:46.314599 USB2 port 6: enabled 1
1660 17:49:46.317819 USB2 port 9: enabled 1
1661 17:49:46.318251 USB3 port 0: enabled 1
1662 17:49:46.321323 USB3 port 1: enabled 1
1663 17:49:46.324595 USB3 port 2: enabled 1
1664 17:49:46.328332 USB3 port 3: enabled 1
1665 17:49:46.328840 USB3 port 4: enabled 0
1666 17:49:46.331171 APIC: 01: enabled 1
1667 17:49:46.331660 APIC: 05: enabled 1
1668 17:49:46.334416 APIC: 04: enabled 1
1669 17:49:46.337576 APIC: 07: enabled 1
1670 17:49:46.337993 APIC: 06: enabled 1
1671 17:49:46.341216 APIC: 03: enabled 1
1672 17:49:46.344626 APIC: 02: enabled 1
1673 17:49:46.345136 PCI: 00:08.0: enabled 1
1674 17:49:46.348001 PCI: 00:14.2: enabled 1
1675 17:49:46.351190 PCI: 01:00.0: enabled 1
1676 17:49:46.354860 Disabling ACPI via APMC:
1677 17:49:46.357828 done.
1678 17:49:46.361253 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1679 17:49:46.364847 ELOG: NV offset 0xaf0000 size 0x4000
1680 17:49:46.371200 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1681 17:49:46.378683 ELOG: Event(17) added with size 13 at 2023-10-20 17:49:46 UTC
1682 17:49:46.384792 ELOG: Event(92) added with size 9 at 2023-10-20 17:49:46 UTC
1683 17:49:46.391688 ELOG: Event(93) added with size 9 at 2023-10-20 17:49:46 UTC
1684 17:49:46.397891 ELOG: Event(9A) added with size 9 at 2023-10-20 17:49:46 UTC
1685 17:49:46.404521 ELOG: Event(9E) added with size 10 at 2023-10-20 17:49:46 UTC
1686 17:49:46.410869 ELOG: Event(9F) added with size 14 at 2023-10-20 17:49:46 UTC
1687 17:49:46.414339 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1688 17:49:46.422210 ELOG: Event(A1) added with size 10 at 2023-10-20 17:49:46 UTC
1689 17:49:46.431838 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1690 17:49:46.438621 ELOG: Event(A0) added with size 9 at 2023-10-20 17:49:46 UTC
1691 17:49:46.441886 elog_add_boot_reason: Logged dev mode boot
1692 17:49:46.445432 Finalize devices...
1693 17:49:46.445848 PCI: 00:17.0 final
1694 17:49:46.448503 Devices finalized
1695 17:49:46.451865 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1696 17:49:46.458497 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
1697 17:49:46.462042 ME: HFSTS1 : 0x90000245
1698 17:49:48.717864 ME: HFSTS2 : 0x3B850126
1699 17:49:48.719027 ME: HFSTS3 : 0x00000020
1700 17:49:48.719394 ME: HFSTS4 : 0x00004800
1701 17:49:48.719710 ME: HFSTS5 : 0x00000000
1702 17:49:48.720006 ME: HFSTS6 : 0x40400006
1703 17:49:48.720288 ME: Manufacturing Mode : NO
1704 17:49:48.720567 ME: FW Partition Table : OK
1705 17:49:48.720843 ME: Bringup Loader Failure : NO
1706 17:49:48.721117 ME: Firmware Init Complete : YES
1707 17:49:48.721392 ME: Boot Options Present : NO
1708 17:49:48.721831 ME: Update In Progress : NO
1709 17:49:48.722257 ME: D0i3 Support : YES
1710 17:49:48.722710 ME: Low Power State Enabled : NO
1711 17:49:48.722999 ME: CPU Replaced : NO
1712 17:49:48.723270 ME: CPU Replacement Valid : YES
1713 17:49:48.723539 ME: Current Working State : 5
1714 17:49:48.723865 ME: Current Operation State : 1
1715 17:49:48.724325 ME: Current Operation Mode : 0
1716 17:49:48.724788 ME: Error Code : 0
1717 17:49:48.725236 ME: CPU Debug Disabled : YES
1718 17:49:48.725684 ME: TXT Support : NO
1719 17:49:48.727633 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1720 17:49:48.728094 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1721 17:49:48.728539 CBFS @ c08000 size 3f8000
1722 17:49:48.728970 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1723 17:49:48.729391 CBFS: Locating 'fallback/dsdt.aml'
1724 17:49:48.729806 CBFS: Found @ offset 10bb80 size 3fa5
1725 17:49:48.730211 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1726 17:49:48.730638 CBFS @ c08000 size 3f8000
1727 17:49:48.731037 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1728 17:49:48.731426 CBFS: Locating 'fallback/slic'
1729 17:49:48.731810 CBFS: 'fallback/slic' not found.
1730 17:49:48.732189 ACPI: Writing ACPI tables at 99b3e000.
1731 17:49:48.732561 ACPI: * FACS
1732 17:49:48.732932 ACPI: * DSDT
1733 17:49:48.733300 Ramoops buffer: 0x100000@0x99a3d000.
1734 17:49:48.733675 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1735 17:49:48.734311 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1736 17:49:48.734872 Google Chrome EC: version:
1737 17:49:48.735373 ro: helios_v2.0.2659-56403530b
1738 17:49:48.735864 rw: helios_v2.0.2849-c41de27e7d
1739 17:49:48.736348 running image: 1
1740 17:49:48.736820 ACPI: * FADT
1741 17:49:48.737287 SCI is IRQ9
1742 17:49:48.737755 ACPI: added table 1/32, length now 40
1743 17:49:48.738129 ACPI: * SSDT
1744 17:49:48.738628 Found 1 CPU(s) with 8 core(s) each.
1745 17:49:48.739014 Error: Could not locate 'wifi_sar' in VPD.
1746 17:49:48.739392 Checking CBFS for default SAR values
1747 17:49:48.739878 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1748 17:49:48.740258 CBFS @ c08000 size 3f8000
1749 17:49:48.740721 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1750 17:49:48.741186 CBFS: Locating 'wifi_sar_defaults.hex'
1751 17:49:48.741653 CBFS: Found @ offset 5fac0 size 77
1752 17:49:48.742026 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1753 17:49:48.742479 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1754 17:49:48.742774 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1755 17:49:48.743054 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1756 17:49:48.743321 failed to find key in VPD: dsm_calib_r0_0
1757 17:49:48.743588 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1758 17:49:48.743920 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1759 17:49:48.744250 failed to find key in VPD: dsm_calib_r0_1
1760 17:49:48.744581 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1761 17:49:48.744923 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1762 17:49:48.745254 failed to find key in VPD: dsm_calib_r0_2
1763 17:49:48.745583 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1764 17:49:48.745848 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1765 17:49:48.746112 failed to find key in VPD: dsm_calib_r0_3
1766 17:49:48.746440 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1767 17:49:48.746736 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1768 17:49:48.747024 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1769 17:49:48.747293 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1770 17:49:48.747585 EC returned error result code 1
1771 17:49:48.747834 EC returned error result code 1
1772 17:49:48.748082 EC returned error result code 1
1773 17:49:48.748331 PS2K: Bad resp from EC. Vivaldi disabled!
1774 17:49:48.748578 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1775 17:49:48.748836 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1776 17:49:48.749087 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1777 17:49:48.749336 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1778 17:49:48.749586 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1779 17:49:48.749786 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1780 17:49:48.749988 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1781 17:49:48.750236 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1782 17:49:48.750484 ACPI: added table 2/32, length now 44
1783 17:49:48.750704 ACPI: * MCFG
1784 17:49:48.750923 ACPI: added table 3/32, length now 48
1785 17:49:48.751173 ACPI: * TPM2
1786 17:49:48.751422 TPM2 log created at 99a2d000
1787 17:49:48.751670 ACPI: added table 4/32, length now 52
1788 17:49:48.751915 ACPI: * MADT
1789 17:49:48.752162 SCI is IRQ9
1790 17:49:48.752407 ACPI: added table 5/32, length now 56
1791 17:49:48.752621 current = 99b43ac0
1792 17:49:48.752822 ACPI: * DMAR
1793 17:49:48.753020 ACPI: added table 6/32, length now 60
1794 17:49:48.753217 ACPI: * IGD OpRegion
1795 17:49:48.753415 GMA: Found VBT in CBFS
1796 17:49:48.753612 GMA: Found valid VBT in CBFS
1797 17:49:48.753770 ACPI: added table 7/32, length now 64
1798 17:49:48.753928 ACPI: * HPET
1799 17:49:48.754124 ACPI: added table 8/32, length now 68
1800 17:49:48.754320 ACPI: done.
1801 17:49:48.754822 ACPI tables: 31744 bytes.
1802 17:49:48.755025 smbios_write_tables: 99a2c000
1803 17:49:48.755236 EC returned error result code 3
1804 17:49:48.755440 Couldn't obtain OEM name from CBI
1805 17:49:48.755642 Create SMBIOS type 17
1806 17:49:48.755842 PCI: 00:00.0 (Intel Cannonlake)
1807 17:49:48.756042 PCI: 00:14.3 (Intel WiFi)
1808 17:49:48.756241 SMBIOS tables: 939 bytes.
1809 17:49:48.756440 Writing table forward entry at 0x00000500
1810 17:49:48.756638 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1811 17:49:48.756837 Writing coreboot table at 0x99b62000
1812 17:49:48.757037 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1813 17:49:48.757236 1. 0000000000001000-000000000009ffff: RAM
1814 17:49:48.757438 2. 00000000000a0000-00000000000fffff: RESERVED
1815 17:49:48.757605 3. 0000000000100000-0000000099a2bfff: RAM
1816 17:49:48.757772 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1817 17:49:48.757907 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1818 17:49:48.758074 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1819 17:49:48.758241 7. 000000009a000000-000000009f7fffff: RESERVED
1820 17:49:48.758407 8. 00000000e0000000-00000000efffffff: RESERVED
1821 17:49:48.758594 9. 00000000fc000000-00000000fc000fff: RESERVED
1822 17:49:48.758765 10. 00000000fe000000-00000000fe00ffff: RESERVED
1823 17:49:48.758938 11. 00000000fed10000-00000000fed17fff: RESERVED
1824 17:49:48.759112 12. 00000000fed80000-00000000fed83fff: RESERVED
1825 17:49:48.759284 13. 00000000fed90000-00000000fed91fff: RESERVED
1826 17:49:48.759456 14. 00000000feda0000-00000000feda1fff: RESERVED
1827 17:49:48.759627 15. 0000000100000000-000000045e7fffff: RAM
1828 17:49:48.759797 Graphics framebuffer located at 0xc0000000
1829 17:49:48.759962 Passing 5 GPIOs to payload:
1830 17:49:48.760132 NAME | PORT | POLARITY | VALUE
1831 17:49:48.760300 write protect | undefined | high | low
1832 17:49:48.760465 lid | undefined | high | high
1833 17:49:48.760631 power | undefined | high | low
1834 17:49:48.760797 oprom | undefined | high | low
1835 17:49:48.760963 EC in RW | 0x000000cb | high | low
1836 17:49:48.761128 Board ID: 4
1837 17:49:48.761293 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1838 17:49:48.761459 CBFS @ c08000 size 3f8000
1839 17:49:48.761623 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1840 17:49:48.761790 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6baa
1841 17:49:48.761956 coreboot table: 1492 bytes.
1842 17:49:48.762121 IMD ROOT 0. 99fff000 00001000
1843 17:49:48.762286 IMD SMALL 1. 99ffe000 00001000
1844 17:49:48.762456 FSP MEMORY 2. 99c4e000 003b0000
1845 17:49:48.762594 CONSOLE 3. 99c2e000 00020000
1846 17:49:48.762710 FMAP 4. 99c2d000 0000054e
1847 17:49:48.762854 TIME STAMP 5. 99c2c000 00000910
1848 17:49:48.762997 VBOOT WORK 6. 99c18000 00014000
1849 17:49:48.763139 MRC DATA 7. 99c16000 00001958
1850 17:49:48.763280 ROMSTG STCK 8. 99c15000 00001000
1851 17:49:48.763422 AFTER CAR 9. 99c0b000 0000a000
1852 17:49:48.763563 RAMSTAGE 10. 99baf000 0005c000
1853 17:49:48.763703 REFCODE 11. 99b7a000 00035000
1854 17:49:48.763845 SMM BACKUP 12. 99b6a000 00010000
1855 17:49:48.763986 COREBOOT 13. 99b62000 00008000
1856 17:49:48.764127 ACPI 14. 99b3e000 00024000
1857 17:49:48.764268 ACPI GNVS 15. 99b3d000 00001000
1858 17:49:48.764408 RAMOOPS 16. 99a3d000 00100000
1859 17:49:48.764549 TPM2 TCGLOG17. 99a2d000 00010000
1860 17:49:48.764691 SMBIOS 18. 99a2c000 00000800
1861 17:49:48.764832 IMD small region:
1862 17:49:48.764973 IMD ROOT 0. 99ffec00 00000400
1863 17:49:48.765114 FSP RUNTIME 1. 99ffebe0 00000004
1864 17:49:48.765255 EC HOSTEVENT 2. 99ffebc0 00000008
1865 17:49:48.765396 POWER STATE 3. 99ffeb80 00000040
1866 17:49:48.765538 ROMSTAGE 4. 99ffeb60 00000004
1867 17:49:48.765679 MEM INFO 5. 99ffe9a0 000001b9
1868 17:49:48.765820 VPD 6. 99ffe920 0000006c
1869 17:49:48.765960 MTRR: Physical address space:
1870 17:49:48.766101 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1871 17:49:48.766255 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1872 17:49:48.766403 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1873 17:49:48.766558 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1874 17:49:48.766708 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1875 17:49:48.766855 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1876 17:49:48.767003 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1877 17:49:48.767150 MTRR: Fixed MSR 0x250 0x0606060606060606
1878 17:49:48.767293 MTRR: Fixed MSR 0x258 0x0606060606060606
1879 17:49:48.767447 MTRR: Fixed MSR 0x259 0x0000000000000000
1880 17:49:48.767573 MTRR: Fixed MSR 0x268 0x0606060606060606
1881 17:49:48.767697 MTRR: Fixed MSR 0x269 0x0606060606060606
1882 17:49:48.767821 MTRR: Fixed MSR 0x26a 0x0606060606060606
1883 17:49:48.767945 MTRR: Fixed MSR 0x26b 0x0606060606060606
1884 17:49:48.768068 MTRR: Fixed MSR 0x26c 0x0606060606060606
1885 17:49:48.768192 MTRR: Fixed MSR 0x26d 0x0606060606060606
1886 17:49:48.768316 MTRR: Fixed MSR 0x26e 0x0606060606060606
1887 17:49:48.768440 MTRR: Fixed MSR 0x26f 0x0606060606060606
1888 17:49:48.768563 call enable_fixed_mtrr()
1889 17:49:48.768687 CPU physical address size: 39 bits
1890 17:49:48.768811 MTRR: default type WB/UC MTRR counts: 6/8.
1891 17:49:48.768934 MTRR: WB selected as default type.
1892 17:49:48.769058 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1893 17:49:48.769182 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1894 17:49:48.769306 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1895 17:49:48.769431 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1896 17:49:48.769774 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1897 17:49:48.769901 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1898 17:49:48.770029 MTRR: Fixed MSR 0x250 0x0606060606060606
1899 17:49:48.770156 MTRR: Fixed MSR 0x258 0x0606060606060606
1900 17:49:48.770282 MTRR: Fixed MSR 0x259 0x0000000000000000
1901 17:49:48.770407 MTRR: Fixed MSR 0x268 0x0606060606060606
1902 17:49:48.770541 MTRR: Fixed MSR 0x269 0x0606060606060606
1903 17:49:48.770668 MTRR: Fixed MSR 0x26a 0x0606060606060606
1904 17:49:48.770793 MTRR: Fixed MSR 0x26b 0x0606060606060606
1905 17:49:48.770918 MTRR: Fixed MSR 0x26c 0x0606060606060606
1906 17:49:48.771043 MTRR: Fixed MSR 0x26d 0x0606060606060606
1907 17:49:48.771142 MTRR: Fixed MSR 0x26e 0x0606060606060606
1908 17:49:48.771266 MTRR: Fixed MSR 0x26f 0x0606060606060606
1909 17:49:48.771391 MTRR: Fixed MSR 0x250 0x0606060606060606
1910 17:49:48.771515 MTRR: Fixed MSR 0x258 0x0606060606060606
1911 17:49:48.771640 MTRR: Fixed MSR 0x259 0x0000000000000000
1912 17:49:48.771764 MTRR: Fixed MSR 0x268 0x0606060606060606
1913 17:49:48.771888 MTRR: Fixed MSR 0x269 0x0606060606060606
1914 17:49:48.772022 MTRR: Fixed MSR 0x26a 0x0606060606060606
1915 17:49:48.772124 MTRR: Fixed MSR 0x26b 0x0606060606060606
1916 17:49:48.772224 MTRR: Fixed MSR 0x26c 0x0606060606060606
1917 17:49:48.772324 MTRR: Fixed MSR 0x26d 0x0606060606060606
1918 17:49:48.772455 MTRR: Fixed MSR 0x26e 0x0606060606060606
1919 17:49:48.772566 MTRR: Fixed MSR 0x26f 0x0606060606060606
1920 17:49:48.772676 call enable_fixed_mtrr()
1921 17:49:48.772787 MTRR: Fixed MSR 0x250 0x0606060606060606
1922 17:49:48.772897 MTRR: Fixed MSR 0x250 0x0606060606060606
1923 17:49:48.773007 MTRR: Fixed MSR 0x258 0x0606060606060606
1924 17:49:48.773117 MTRR: Fixed MSR 0x259 0x0000000000000000
1925 17:49:48.773227 MTRR: Fixed MSR 0x268 0x0606060606060606
1926 17:49:48.773338 MTRR: Fixed MSR 0x269 0x0606060606060606
1927 17:49:48.773448 MTRR: Fixed MSR 0x26a 0x0606060606060606
1928 17:49:48.773557 MTRR: Fixed MSR 0x26b 0x0606060606060606
1929 17:49:48.773666 MTRR: Fixed MSR 0x26c 0x0606060606060606
1930 17:49:48.773775 MTRR: Fixed MSR 0x26d 0x0606060606060606
1931 17:49:48.773885 MTRR: Fixed MSR 0x26e 0x0606060606060606
1932 17:49:48.774003 MTRR: Fixed MSR 0x26f 0x0606060606060606
1933 17:49:48.774113 MTRR: Fixed MSR 0x258 0x0606060606060606
1934 17:49:48.774223 call enable_fixed_mtrr()
1935 17:49:48.774334 MTRR: Fixed MSR 0x259 0x0000000000000000
1936 17:49:48.774444 MTRR: Fixed MSR 0x268 0x0606060606060606
1937 17:49:48.774559 MTRR: Fixed MSR 0x269 0x0606060606060606
1938 17:49:48.774650 MTRR: Fixed MSR 0x26a 0x0606060606060606
1939 17:49:48.774761 MTRR: Fixed MSR 0x26b 0x0606060606060606
1940 17:49:48.774849 MTRR: Fixed MSR 0x26c 0x0606060606060606
1941 17:49:48.774938 MTRR: Fixed MSR 0x26d 0x0606060606060606
1942 17:49:48.775047 MTRR: Fixed MSR 0x26e 0x0606060606060606
1943 17:49:48.775158 MTRR: Fixed MSR 0x26f 0x0606060606060606
1944 17:49:48.775268 CPU physical address size: 39 bits
1945 17:49:48.775378 call enable_fixed_mtrr()
1946 17:49:48.775488
1947 17:49:48.775598 MTRR check
1948 17:49:48.775709 MTRR: Fixed MSR 0x250 0x0606060606060606
1949 17:49:48.775819 Fixed MTRRs : MTRR: Fixed MSR 0x258 0x0606060606060606
1950 17:49:48.775938 MTRR: Fixed MSR 0x259 0x0000000000000000
1951 17:49:48.776027 MTRR: Fixed MSR 0x268 0x0606060606060606
1952 17:49:48.776138 MTRR: Fixed MSR 0x269 0x0606060606060606
1953 17:49:48.776226 MTRR: Fixed MSR 0x26a 0x0606060606060606
1954 17:49:48.776336 MTRR: Fixed MSR 0x26b 0x0606060606060606
1955 17:49:48.776424 MTRR: Fixed MSR 0x26c 0x0606060606060606
1956 17:49:48.776534 MTRR: Fixed MSR 0x26d 0x0606060606060606
1957 17:49:48.776644 MTRR: Fixed MSR 0x26e 0x0606060606060606
1958 17:49:48.776732 MTRR: Fixed MSR 0x26f 0x0606060606060606
1959 17:49:48.776842 Enabled
1960 17:49:48.776952 Variable MTRRs: Enabled
1961 17:49:48.777062
1962 17:49:48.777172 call enable_fixed_mtrr()
1963 17:49:48.777282 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1964 17:49:48.777393 CPU physical address size: 39 bits
1965 17:49:48.777508 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1966 17:49:48.777608 MTRR: Fixed MSR 0x250 0x0606060606060606
1967 17:49:48.777708 MTRR: Fixed MSR 0x258 0x0606060606060606
1968 17:49:48.777808 MTRR: Fixed MSR 0x259 0x0000000000000000
1969 17:49:48.777909 MTRR: Fixed MSR 0x268 0x0606060606060606
1970 17:49:48.778013 MTRR: Fixed MSR 0x269 0x0606060606060606
1971 17:49:48.778113 MTRR: Fixed MSR 0x26a 0x0606060606060606
1972 17:49:48.778213 MTRR: Fixed MSR 0x26b 0x0606060606060606
1973 17:49:48.778315 MTRR: Fixed MSR 0x26c 0x0606060606060606
1974 17:49:48.778416 MTRR: Fixed MSR 0x26d 0x0606060606060606
1975 17:49:48.778516 MTRR: Fixed MSR 0x26e 0x0606060606060606
1976 17:49:48.778621 MTRR: Fixed MSR 0x26f 0x0606060606060606
1977 17:49:48.778722 MTRR: Fixed MSR 0x250 0x0606060606060606
1978 17:49:48.778821 call enable_fixed_mtrr()
1979 17:49:48.778920 MTRR: Fixed MSR 0x258 0x0606060606060606
1980 17:49:48.779019 MTRR: Fixed MSR 0x259 0x0000000000000000
1981 17:49:48.779119 MTRR: Fixed MSR 0x268 0x0606060606060606
1982 17:49:48.779218 MTRR: Fixed MSR 0x269 0x0606060606060606
1983 17:49:48.779317 MTRR: Fixed MSR 0x26a 0x0606060606060606
1984 17:49:48.779416 MTRR: Fixed MSR 0x26b 0x0606060606060606
1985 17:49:48.779515 MTRR: Fixed MSR 0x26c 0x0606060606060606
1986 17:49:48.779614 MTRR: Fixed MSR 0x26d 0x0606060606060606
1987 17:49:48.779713 MTRR: Fixed MSR 0x26e 0x0606060606060606
1988 17:49:48.779813 MTRR: Fixed MSR 0x26f 0x0606060606060606
1989 17:49:48.779913 CPU physical address size: 39 bits
1990 17:49:48.780026 call enable_fixed_mtrr()
1991 17:49:48.780128 CBFS @ c08000 size 3f8000
1992 17:49:48.780229 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1993 17:49:48.780329 CBFS: Locating 'fallback/payload'
1994 17:49:48.780430 CPU physical address size: 39 bits
1995 17:49:48.780530 CPU physical address size: 39 bits
1996 17:49:48.780629 CBFS: Found @ offset 1c96c0 size 3f798
1997 17:49:48.780729 call enable_fixed_mtrr()
1998 17:49:48.780829 CPU physical address size: 39 bits
1999 17:49:48.781127 CPU physical address size: 39 bits
2000 17:49:48.781229 Checking segment from ROM address 0xffdd16f8
2001 17:49:48.781331 Checking segment from ROM address 0xffdd1714
2002 17:49:48.781434 Loading segment from ROM address 0xffdd16f8
2003 17:49:48.781535 code (compression=0)
2004 17:49:48.781636 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
2005 17:49:48.781738 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
2006 17:49:48.781839 it's not compressed!
2007 17:49:48.781941 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
2008 17:49:48.782044 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
2009 17:49:48.782146 Loading segment from ROM address 0xffdd1714
2010 17:49:48.782246 Entry Point 0x30000000
2011 17:49:48.782346 Loaded segments
2012 17:49:48.782457 Finalizing chipset.
2013 17:49:48.782557 Finalizing SMM.
2014 17:49:48.782650 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
2015 17:49:48.782743 mp_park_aps done after 0 msecs.
2016 17:49:48.782834 Jumping to boot code at 30000000(99b62000)
2017 17:49:48.782926 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
2018 17:49:48.783018
2019 17:49:48.783108
2020 17:49:48.783199
2021 17:49:48.783289 Starting depthcharge on Helios...
2022 17:49:48.783380
2023 17:49:48.783470 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2024 17:49:48.783562
2025 17:49:48.783653 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2026 17:49:48.783744
2027 17:49:48.783834 board_setup: Info: eMMC controller not present; skipping
2028 17:49:48.783929
2029 17:49:48.784020 New NVMe Controller 0x30053ac0 @ 00:1d:00
2030 17:49:48.784112
2031 17:49:48.784204 board_setup: Info: SDHCI controller not present; skipping
2032 17:49:48.784295
2033 17:49:48.784386 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2034 17:49:48.784480
2035 17:49:48.784571 Wipe memory regions:
2036 17:49:48.784662
2037 17:49:48.784752 [0x00000000001000, 0x000000000a0000)
2038 17:49:48.784843
2039 17:49:48.784933 [0x00000000100000, 0x00000030000000)
2040 17:49:48.785024
2041 17:49:48.785115 [0x00000030657430, 0x00000099a2c000)
2042 17:49:48.785205
2043 17:49:48.785294 [0x00000100000000, 0x0000045e800000)
2044 17:49:48.785699 end: 2.2.3 depthcharge-start (duration 00:00:14) [common]
2045 17:49:48.785831 start: 2.2.4 bootloader-commands (timeout 00:04:39) [common]
2046 17:49:48.785948 Setting prompt string to ['hatch:']
2047 17:49:48.786073 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:39)
2048 17:49:49.492606
2049 17:49:49.493113 R8152: Initializing
2050 17:49:49.493563
2051 17:49:49.496157 Version 9 (ocp_data = 6010)
2052 17:49:49.500126
2053 17:49:49.500544 R8152: Done initializing
2054 17:49:49.500973
2055 17:49:49.503148 Adding net device
2056 17:49:50.112766
2057 17:49:50.113308 R8152: Initializing
2058 17:49:50.113820
2059 17:49:50.115865 Version 6 (ocp_data = 5c30)
2060 17:49:50.116387
2061 17:49:50.119355 R8152: Done initializing
2062 17:49:50.119851
2063 17:49:50.122469 net_add_device: Attemp to include the same device
2064 17:49:50.125782
2065 17:49:50.133192 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2066 17:49:50.133754
2067 17:49:50.134260
2068 17:49:50.134863
2069 17:49:50.135733 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2071 17:49:50.236980 hatch: tftpboot 192.168.201.1 11831830/tftp-deploy-e4kzmb5l/kernel/bzImage 11831830/tftp-deploy-e4kzmb5l/kernel/cmdline 11831830/tftp-deploy-e4kzmb5l/ramdisk/ramdisk.cpio.gz
2072 17:49:50.237579 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2073 17:49:50.238023 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:38)
2074 17:49:50.242193 tftpboot 192.168.201.1 11831830/tftp-deploy-e4kzmb5l/kernel/bzImloy-e4kzmb5l/kernel/cmdline 11831830/tftp-deploy-e4kzmb5l/ramdisk/ramdisk.cpio.gz
2075 17:49:50.242737
2076 17:49:50.243121 Waiting for link
2077 17:49:50.443122
2078 17:49:50.443660 done.
2079 17:49:50.444101
2080 17:49:50.444511 MAC: 00:24:32:50:1a:5f
2081 17:49:50.444920
2082 17:49:50.446408 Sending DHCP discover... done.
2083 17:49:50.446860
2084 17:49:50.450270 Waiting for reply... done.
2085 17:49:50.450886
2086 17:49:50.453227 Sending DHCP request... done.
2087 17:49:50.453643
2088 17:49:53.870282 Waiting for reply... done.
2089 17:49:53.870835
2090 17:49:53.871171 My ip is 192.168.201.21
2091 17:49:53.871482
2092 17:49:53.872113 The DHCP server ip is 192.168.201.1
2093 17:49:53.872445
2094 17:49:53.872737 TFTP server IP predefined by user: 192.168.201.1
2095 17:49:53.873029
2096 17:49:53.873313 Bootfile predefined by user: 11831830/tftp-deploy-e4kzmb5l/kernel/bzImage
2097 17:49:53.873594
2098 17:49:53.873870 Sending tftp read request... done.
2099 17:49:53.874146
2100 17:49:53.874418 Waiting for the transfer...
2101 17:49:53.874728
2102 17:49:53.875003 00000000 ################################################################
2103 17:49:53.875286
2104 17:49:53.875562 00080000 ################################################################
2105 17:49:53.875635
2106 17:49:54.184855 00100000 ################################################################
2107 17:49:54.185431
2108 17:49:54.885655 00180000 ################################################################
2109 17:49:54.886294
2110 17:49:55.588658 00200000 ################################################################
2111 17:49:55.589186
2112 17:49:56.263352 00280000 ################################################################
2113 17:49:56.263876
2114 17:49:56.937009 00300000 ################################################################
2115 17:49:56.937547
2116 17:49:59.725406 00380000 ################################################################
2117 17:49:59.725950
2118 17:49:59.726297 00400000 ################################################################
2119 17:49:59.726688
2120 17:49:59.727019 00480000 ################################################################
2121 17:49:59.727375
2122 17:49:59.727865 00500000 ################################################################
2123 17:49:59.728211
2124 17:50:00.337595 00580000 ################################################################
2125 17:50:00.338100
2126 17:50:01.064770 00600000 ################################################################
2127 17:50:01.065302
2128 17:50:01.757410 00680000 ################################################################
2129 17:50:01.757952
2130 17:50:02.463073 00700000 ################################################################
2131 17:50:02.463621
2132 17:50:03.180610 00780000 ################################################################
2133 17:50:03.181141
2134 17:50:03.338176 00800000 ############### done.
2135 17:50:03.338707
2136 17:50:03.341576 The bootfile was 8507280 bytes long.
2137 17:50:03.341997
2138 17:50:03.344740 Sending tftp read request... done.
2139 17:50:03.345157
2140 17:50:03.348027 Waiting for the transfer...
2141 17:50:03.348441
2142 17:50:04.012478 00000000 ################################################################
2143 17:50:04.012983
2144 17:50:04.708077 00080000 ################################################################
2145 17:50:04.708579
2146 17:50:05.344927 00100000 ################################################################
2147 17:50:05.345072
2148 17:50:05.963637 00180000 ################################################################
2149 17:50:05.963783
2150 17:50:06.546439 00200000 ################################################################
2151 17:50:06.546603
2152 17:50:07.158656 00280000 ################################################################
2153 17:50:07.159157
2154 17:50:07.833487 00300000 ################################################################
2155 17:50:07.833983
2156 17:50:08.511719 00380000 ################################################################
2157 17:50:08.512221
2158 17:50:09.182073 00400000 ################################################################
2159 17:50:09.182613
2160 17:50:10.389758 00480000 ################################################################
2161 17:50:10.390623
2162 17:50:10.504818 00500000 ################################################################ done.
2163 17:50:10.504965
2164 17:50:10.508211 Sending tftp read request... done.
2165 17:50:10.508306
2166 17:50:10.511387 Waiting for the transfer...
2167 17:50:10.511509
2168 17:50:10.511580 00000000 # done.
2169 17:50:10.511646
2170 17:50:10.521437 Command line loaded dynamically from TFTP file: 11831830/tftp-deploy-e4kzmb5l/kernel/cmdline
2171 17:50:10.521598
2172 17:50:10.551333 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/11831830/extract-nfsrootfs-rh37j3mc,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2173 17:50:10.551532
2174 17:50:10.554605 ec_init(0): CrosEC protocol v3 supported (256, 256)
2175 17:50:10.560542
2176 17:50:10.564068 Shutting down all USB controllers.
2177 17:50:10.564262
2178 17:50:10.564399 Removing current net device
2179 17:50:10.571687
2180 17:50:10.571842 Finalizing coreboot
2181 17:50:10.571918
2182 17:50:10.578410 Exiting depthcharge with code 4 at timestamp: 30087093
2183 17:50:10.578572
2184 17:50:10.578682
2185 17:50:10.578784 Starting kernel ...
2186 17:50:10.578886
2187 17:50:10.578979
2188 17:50:10.579579 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
2189 17:50:10.579693 start: 2.2.5 auto-login-action (timeout 00:04:17) [common]
2190 17:50:10.579778 Setting prompt string to ['Linux version [0-9]']
2191 17:50:10.579856 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2192 17:50:10.579934 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2194 17:54:27.580620 end: 2.2.5 auto-login-action (duration 00:04:17) [common]
2196 17:54:27.581718 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 257 seconds'
2198 17:54:27.582583 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2201 17:54:27.584008 end: 2 depthcharge-action (duration 00:05:00) [common]
2203 17:54:27.585170 Cleaning after the job
2204 17:54:27.585656 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/ramdisk
2205 17:54:27.590307 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/kernel
2206 17:54:27.597627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/nfsrootfs
2207 17:54:27.711359 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11831830/tftp-deploy-e4kzmb5l/modules
2208 17:54:27.711813 start: 4.1 power-off (timeout 00:00:30) [common]
2209 17:54:27.711975 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=off'
2210 17:54:27.784040 >> Command sent successfully.
2211 17:54:27.788061 Returned 0 in 0 seconds
2212 17:54:27.889024 end: 4.1 power-off (duration 00:00:00) [common]
2214 17:54:27.890605 start: 4.2 read-feedback (timeout 00:10:00) [common]
2215 17:54:27.891948 Listened to connection for namespace 'common' for up to 1s
2217 17:54:27.893555 Listened to connection for namespace 'common' for up to 1s
2218 17:54:28.892566 Finalising connection for namespace 'common'
2219 17:54:28.893256 Disconnecting from shell: Finalise
2220 17:54:28.893681
2221 17:54:28.994936 end: 4.2 read-feedback (duration 00:00:01) [common]
2222 17:54:28.995549 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11831830
2223 17:54:29.547339 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11831830
2224 17:54:29.547529 JobError: Your job cannot terminate cleanly.