Boot log: asus-C436FA-Flip-hatch
- Errors: 2
- Boot result: FAIL
- Kernel Errors: 0
- Warnings: 0
- Kernel Warnings: 0
1 12:44:08.869125 lava-dispatcher, installed at version: 2023.01
2 12:44:08.869320 start: 0 validate
3 12:44:08.869448 Start time: 2023-03-22 12:44:08.869442+00:00 (UTC)
4 12:44:08.869572 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:44:08.869732 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230317.0%2Famd64%2Finitrd.cpio.gz exists
6 12:44:09.163110 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:44:09.163310 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv5.10.175-cip29-rt12%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:44:26.209585 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:44:26.210278 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230317.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 12:44:26.214195 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:44:26.214814 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv5.10.175-cip29-rt12%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:44:27.226886 validate duration: 18.36
14 12:44:27.228319 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:44:27.228930 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:44:27.229036 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:44:27.229138 Not decompressing ramdisk as can be used compressed.
18 12:44:27.229230 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230317.0/amd64/initrd.cpio.gz
19 12:44:27.229338 saving as /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/ramdisk/initrd.cpio.gz
20 12:44:27.229437 total size: 5432123 (5MB)
21 12:44:27.518390 progress 0% (0MB)
22 12:44:27.520243 progress 5% (0MB)
23 12:44:27.521812 progress 10% (0MB)
24 12:44:27.523440 progress 15% (0MB)
25 12:44:27.525203 progress 20% (1MB)
26 12:44:27.526727 progress 25% (1MB)
27 12:44:27.528243 progress 30% (1MB)
28 12:44:27.529884 progress 35% (1MB)
29 12:44:27.531383 progress 40% (2MB)
30 12:44:27.532968 progress 45% (2MB)
31 12:44:27.534620 progress 50% (2MB)
32 12:44:27.536255 progress 55% (2MB)
33 12:44:27.537712 progress 60% (3MB)
34 12:44:27.539262 progress 65% (3MB)
35 12:44:27.540909 progress 70% (3MB)
36 12:44:27.542390 progress 75% (3MB)
37 12:44:27.543880 progress 80% (4MB)
38 12:44:27.545449 progress 85% (4MB)
39 12:44:27.547123 progress 90% (4MB)
40 12:44:27.548664 progress 95% (4MB)
41 12:44:27.550101 progress 100% (5MB)
42 12:44:27.550332 5MB downloaded in 0.32s (16.14MB/s)
43 12:44:27.550579 end: 1.1.1 http-download (duration 00:00:00) [common]
45 12:44:27.550886 end: 1.1 download-retry (duration 00:00:00) [common]
46 12:44:27.551002 start: 1.2 download-retry (timeout 00:10:00) [common]
47 12:44:27.551154 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 12:44:27.551297 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v5.10.175-cip29-rt12/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 12:44:27.551383 saving as /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/kernel/bzImage
50 12:44:27.551473 total size: 11646080 (11MB)
51 12:44:27.551560 No compression specified
52 12:44:27.552521 progress 0% (0MB)
53 12:44:27.555762 progress 5% (0MB)
54 12:44:27.559011 progress 10% (1MB)
55 12:44:27.562262 progress 15% (1MB)
56 12:44:27.565529 progress 20% (2MB)
57 12:44:27.568568 progress 25% (2MB)
58 12:44:27.571774 progress 30% (3MB)
59 12:44:27.574999 progress 35% (3MB)
60 12:44:27.578309 progress 40% (4MB)
61 12:44:27.581392 progress 45% (5MB)
62 12:44:27.584622 progress 50% (5MB)
63 12:44:27.587858 progress 55% (6MB)
64 12:44:27.591151 progress 60% (6MB)
65 12:44:27.594418 progress 65% (7MB)
66 12:44:27.597430 progress 70% (7MB)
67 12:44:27.600633 progress 75% (8MB)
68 12:44:27.603820 progress 80% (8MB)
69 12:44:27.606993 progress 85% (9MB)
70 12:44:27.610031 progress 90% (10MB)
71 12:44:27.613209 progress 95% (10MB)
72 12:44:27.616434 progress 100% (11MB)
73 12:44:27.616629 11MB downloaded in 0.07s (170.47MB/s)
74 12:44:27.616798 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:44:27.617064 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:44:27.617164 start: 1.3 download-retry (timeout 00:10:00) [common]
78 12:44:27.617262 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 12:44:27.617391 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230317.0/amd64/full.rootfs.tar.xz
80 12:44:27.617482 saving as /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/nfsrootfs/full.rootfs.tar
81 12:44:27.617593 total size: 133351768 (127MB)
82 12:44:27.617674 Using unxz to decompress xz
83 12:44:27.621126 progress 0% (0MB)
84 12:44:28.027712 progress 5% (6MB)
85 12:44:28.443113 progress 10% (12MB)
86 12:44:28.771020 progress 15% (19MB)
87 12:44:28.994605 progress 20% (25MB)
88 12:44:29.303153 progress 25% (31MB)
89 12:44:29.709327 progress 30% (38MB)
90 12:44:30.123044 progress 35% (44MB)
91 12:44:30.579479 progress 40% (50MB)
92 12:44:31.013859 progress 45% (57MB)
93 12:44:31.422637 progress 50% (63MB)
94 12:44:31.850878 progress 55% (69MB)
95 12:44:32.279130 progress 60% (76MB)
96 12:44:32.704629 progress 65% (82MB)
97 12:44:33.127265 progress 70% (89MB)
98 12:44:33.554464 progress 75% (95MB)
99 12:44:34.069857 progress 80% (101MB)
100 12:44:34.577632 progress 85% (108MB)
101 12:44:34.901202 progress 90% (114MB)
102 12:44:35.304890 progress 95% (120MB)
103 12:44:35.759534 progress 100% (127MB)
104 12:44:35.766255 127MB downloaded in 8.15s (15.61MB/s)
105 12:44:35.766616 end: 1.3.1 http-download (duration 00:00:08) [common]
107 12:44:35.766919 end: 1.3 download-retry (duration 00:00:08) [common]
108 12:44:35.767028 start: 1.4 download-retry (timeout 00:09:51) [common]
109 12:44:35.767144 start: 1.4.1 http-download (timeout 00:09:51) [common]
110 12:44:35.767280 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v5.10.175-cip29-rt12/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 12:44:35.767365 saving as /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/modules/modules.tar
112 12:44:35.767437 total size: 497788 (0MB)
113 12:44:35.767508 Using unxz to decompress xz
114 12:44:35.770914 progress 6% (0MB)
115 12:44:35.771360 progress 13% (0MB)
116 12:44:35.771771 progress 19% (0MB)
117 12:44:35.773282 progress 26% (0MB)
118 12:44:35.775550 progress 32% (0MB)
119 12:44:35.777936 progress 39% (0MB)
120 12:44:35.780058 progress 46% (0MB)
121 12:44:35.782278 progress 52% (0MB)
122 12:44:35.784940 progress 59% (0MB)
123 12:44:35.787212 progress 65% (0MB)
124 12:44:35.789578 progress 72% (0MB)
125 12:44:35.791784 progress 78% (0MB)
126 12:44:35.794028 progress 85% (0MB)
127 12:44:35.796495 progress 92% (0MB)
128 12:44:35.798709 progress 98% (0MB)
129 12:44:35.806488 0MB downloaded in 0.04s (12.16MB/s)
130 12:44:35.806808 end: 1.4.1 http-download (duration 00:00:00) [common]
132 12:44:35.807133 end: 1.4 download-retry (duration 00:00:00) [common]
133 12:44:35.807245 start: 1.5 prepare-tftp-overlay (timeout 00:09:51) [common]
134 12:44:35.807354 start: 1.5.1 extract-nfsrootfs (timeout 00:09:51) [common]
135 12:44:37.208058 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/9729676/extract-nfsrootfs-9ty6xpyx
136 12:44:37.208303 end: 1.5.1 extract-nfsrootfs (duration 00:00:01) [common]
137 12:44:37.208437 start: 1.5.2 lava-overlay (timeout 00:09:50) [common]
138 12:44:37.208594 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9
139 12:44:37.208721 makedir: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin
140 12:44:37.208820 makedir: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/tests
141 12:44:37.208919 makedir: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/results
142 12:44:37.209032 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-add-keys
143 12:44:37.209178 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-add-sources
144 12:44:37.209311 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-background-process-start
145 12:44:37.209438 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-background-process-stop
146 12:44:37.209563 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-common-functions
147 12:44:37.209687 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-echo-ipv4
148 12:44:37.209814 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-install-packages
149 12:44:37.209942 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-installed-packages
150 12:44:37.210064 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-os-build
151 12:44:37.210187 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-probe-channel
152 12:44:37.210309 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-probe-ip
153 12:44:37.210430 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-target-ip
154 12:44:37.210552 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-target-mac
155 12:44:37.210672 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-target-storage
156 12:44:37.210799 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-case
157 12:44:37.210921 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-event
158 12:44:37.211062 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-feedback
159 12:44:37.211204 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-raise
160 12:44:37.211328 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-reference
161 12:44:37.211450 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-runner
162 12:44:37.211574 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-set
163 12:44:37.211697 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-test-shell
164 12:44:37.211845 Updating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-install-packages (oe)
165 12:44:37.211974 Updating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/bin/lava-installed-packages (oe)
166 12:44:37.212084 Creating /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/environment
167 12:44:37.212181 LAVA metadata
168 12:44:37.212261 - LAVA_JOB_ID=9729676
169 12:44:37.212335 - LAVA_DISPATCHER_IP=192.168.201.1
170 12:44:37.212463 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:50) [common]
171 12:44:37.212537 skipped lava-vland-overlay
172 12:44:37.212623 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
173 12:44:37.212715 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
174 12:44:37.212785 skipped lava-multinode-overlay
175 12:44:37.212866 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
176 12:44:37.212955 start: 1.5.2.3 test-definition (timeout 00:09:50) [common]
177 12:44:37.213038 Loading test definitions
178 12:44:37.213140 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:50) [common]
179 12:44:37.213217 Using /lava-9729676 at stage 0
180 12:44:37.213500 uuid=9729676_1.5.2.3.1 testdef=None
181 12:44:37.213600 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
182 12:44:37.213699 start: 1.5.2.3.2 test-overlay (timeout 00:09:50) [common]
183 12:44:37.214230 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
185 12:44:37.214489 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:50) [common]
186 12:44:37.215133 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
188 12:44:37.215402 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
189 12:44:37.216025 runner path: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/0/tests/0_dmesg test_uuid 9729676_1.5.2.3.1
190 12:44:37.216197 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
192 12:44:37.216462 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:50) [common]
193 12:44:37.216546 Using /lava-9729676 at stage 1
194 12:44:37.216828 uuid=9729676_1.5.2.3.5 testdef=None
195 12:44:37.216929 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
196 12:44:37.217026 start: 1.5.2.3.6 test-overlay (timeout 00:09:50) [common]
197 12:44:37.217528 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
199 12:44:37.217795 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:50) [common]
200 12:44:37.218511 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
202 12:44:37.218780 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
203 12:44:37.219433 runner path: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/1/tests/1_bootrr test_uuid 9729676_1.5.2.3.5
204 12:44:37.219603 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
206 12:44:37.219841 Creating lava-test-runner.conf files
207 12:44:37.219913 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/0 for stage 0
208 12:44:37.220008 - 0_dmesg
209 12:44:37.220093 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9729676/lava-overlay-ysuiiqw9/lava-9729676/1 for stage 1
210 12:44:37.220186 - 1_bootrr
211 12:44:37.220290 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
212 12:44:37.220388 start: 1.5.2.4 compress-overlay (timeout 00:09:50) [common]
213 12:44:37.226885 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
214 12:44:37.227063 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
215 12:44:37.227188 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
216 12:44:37.227292 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
217 12:44:37.227389 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
218 12:44:37.343130 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
219 12:44:37.343587 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
220 12:44:37.343885 extracting modules file /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9729676/extract-nfsrootfs-9ty6xpyx
221 12:44:37.358269 extracting modules file /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9729676/extract-overlay-ramdisk-uykvy4fv/ramdisk
222 12:44:37.372500 end: 1.5.4 extract-modules (duration 00:00:00) [common]
223 12:44:37.372698 start: 1.5.5 apply-overlay-tftp (timeout 00:09:50) [common]
224 12:44:37.372815 [common] Applying overlay to NFS
225 12:44:37.372898 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9729676/compress-overlay-a28fvhlm/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9729676/extract-nfsrootfs-9ty6xpyx
226 12:44:37.377467 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
227 12:44:37.377644 start: 1.5.6 configure-preseed-file (timeout 00:09:50) [common]
228 12:44:37.377759 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
229 12:44:37.377863 start: 1.5.7 compress-ramdisk (timeout 00:09:50) [common]
230 12:44:37.377960 Building ramdisk /var/lib/lava/dispatcher/tmp/9729676/extract-overlay-ramdisk-uykvy4fv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9729676/extract-overlay-ramdisk-uykvy4fv/ramdisk
231 12:44:37.423858 >> 30091 blocks
232 12:44:38.030787 rename /var/lib/lava/dispatcher/tmp/9729676/extract-overlay-ramdisk-uykvy4fv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/ramdisk/ramdisk.cpio.gz
233 12:44:38.031250 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
234 12:44:38.031391 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
235 12:44:38.031502 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
236 12:44:38.031607 No mkimage arch provided, not using FIT.
237 12:44:38.031711 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
238 12:44:38.031812 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
239 12:44:38.031929 end: 1.5 prepare-tftp-overlay (duration 00:00:02) [common]
240 12:44:38.032035 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:49) [common]
241 12:44:38.032122 No LXC device requested
242 12:44:38.032216 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
243 12:44:38.032319 start: 1.7 deploy-device-env (timeout 00:09:49) [common]
244 12:44:38.032415 end: 1.7 deploy-device-env (duration 00:00:00) [common]
245 12:44:38.032493 Checking files for TFTP limit of 4294967296 bytes.
246 12:44:38.032927 end: 1 tftp-deploy (duration 00:00:11) [common]
247 12:44:38.033047 start: 2 depthcharge-action (timeout 00:05:00) [common]
248 12:44:38.033153 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
249 12:44:38.033298 substitutions:
250 12:44:38.033375 - {DTB}: None
251 12:44:38.033450 - {INITRD}: 9729676/tftp-deploy-618pfdcj/ramdisk/ramdisk.cpio.gz
252 12:44:38.033519 - {KERNEL}: 9729676/tftp-deploy-618pfdcj/kernel/bzImage
253 12:44:38.033585 - {LAVA_MAC}: None
254 12:44:38.033651 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/9729676/extract-nfsrootfs-9ty6xpyx
255 12:44:38.033717 - {NFS_SERVER_IP}: 192.168.201.1
256 12:44:38.033781 - {PRESEED_CONFIG}: None
257 12:44:38.033845 - {PRESEED_LOCAL}: None
258 12:44:38.033909 - {RAMDISK}: 9729676/tftp-deploy-618pfdcj/ramdisk/ramdisk.cpio.gz
259 12:44:38.033973 - {ROOT_PART}: None
260 12:44:38.034036 - {ROOT}: None
261 12:44:38.034100 - {SERVER_IP}: 192.168.201.1
262 12:44:38.034162 - {TEE}: None
263 12:44:38.034225 Parsed boot commands:
264 12:44:38.034286 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
265 12:44:38.034458 Parsed boot commands: tftpboot 192.168.201.1 9729676/tftp-deploy-618pfdcj/kernel/bzImage 9729676/tftp-deploy-618pfdcj/kernel/cmdline 9729676/tftp-deploy-618pfdcj/ramdisk/ramdisk.cpio.gz
266 12:44:38.034563 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
267 12:44:38.034663 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
268 12:44:38.034798 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
269 12:44:38.034923 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
270 12:44:38.035004 Not connected, no need to disconnect.
271 12:44:38.035103 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
272 12:44:38.035202 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
273 12:44:38.035280 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-C436FA-Flip-hatch-cbg-4'
274 12:44:38.038583 Setting prompt string to ['lava-test: # ']
275 12:44:38.039034 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
276 12:44:38.039228 end: 2.2.1 reset-connection (duration 00:00:00) [common]
277 12:44:38.039398 start: 2.2.2 reset-device (timeout 00:05:00) [common]
278 12:44:38.039552 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
279 12:44:38.039853 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=reboot'
280 12:44:43.184495 >> Command sent successfully.
281 12:44:43.190447 Returned 0 in 5 seconds
282 12:44:43.291507 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
284 12:44:43.292830 end: 2.2.2 reset-device (duration 00:00:05) [common]
285 12:44:43.293304 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
286 12:44:43.293714 Setting prompt string to 'Starting depthcharge on Helios...'
287 12:44:43.294042 Changing prompt to 'Starting depthcharge on Helios...'
288 12:44:43.294373 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
289 12:44:43.295510 [Enter `^Ec?' for help]
290 12:44:43.909361
291 12:44:43.909852
292 12:44:43.919701 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
293 12:44:43.922995 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
294 12:44:43.929616 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
295 12:44:43.932667 CPU: AES supported, TXT NOT supported, VT supported
296 12:44:43.940028 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
297 12:44:43.943056 PCH: device id 0284 (rev 00) is Cometlake-U Premium
298 12:44:43.949410 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
299 12:44:43.952892 VBOOT: Loading verstage.
300 12:44:43.955863 FMAP: Found "FLASH" version 1.1 at 0xc04000.
301 12:44:43.962886 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
302 12:44:43.965899 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
303 12:44:43.969284 CBFS @ c08000 size 3f8000
304 12:44:43.975669 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
305 12:44:43.979042 CBFS: Locating 'fallback/verstage'
306 12:44:43.982652 CBFS: Found @ offset 10fb80 size 1072c
307 12:44:43.985907
308 12:44:43.986288
309 12:44:43.995556 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
310 12:44:44.010337 Probing TPM: . done!
311 12:44:44.013388 TPM ready after 0 ms
312 12:44:44.016555 Connected to device vid:did:rid of 1ae0:0028:00
313 12:44:44.027047 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
314 12:44:44.030918 Initialized TPM device CR50 revision 0
315 12:44:44.074561 tlcl_send_startup: Startup return code is 0
316 12:44:44.075207 TPM: setup succeeded
317 12:44:44.087136 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
318 12:44:44.091059 Chrome EC: UHEPI supported
319 12:44:44.094651 Phase 1
320 12:44:44.097718 FMAP: area GBB found @ c05000 (12288 bytes)
321 12:44:44.103488 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
322 12:44:44.107194 Phase 2
323 12:44:44.107601 Phase 3
324 12:44:44.110231 FMAP: area GBB found @ c05000 (12288 bytes)
325 12:44:44.117088 VB2:vb2_report_dev_firmware() This is developer signed firmware
326 12:44:44.123546 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
327 12:44:44.126908 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
328 12:44:44.134295 VB2:vb2_verify_keyblock() Checking keyblock signature...
329 12:44:44.149597 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
330 12:44:44.152508 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
331 12:44:44.159795 VB2:vb2_verify_fw_preamble() Verifying preamble.
332 12:44:44.163479 Phase 4
333 12:44:44.167010 FMAP: area FW_MAIN_B found @ 778000 (3506112 bytes)
334 12:44:44.173356 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
335 12:44:44.353201 VB2:vb2_rsa_verify_digest() Digest check failed!
336 12:44:44.359398 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
337 12:44:44.359950 Saving nvdata
338 12:44:44.362583 Reboot requested (10020007)
339 12:44:44.365772 board_reset() called!
340 12:44:44.366234 full_reset() called!
341 12:44:48.875469
342 12:44:48.875631
343 12:44:48.885857 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
344 12:44:48.889086 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
345 12:44:48.896011 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
346 12:44:48.899205 CPU: AES supported, TXT NOT supported, VT supported
347 12:44:48.905890 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
348 12:44:48.909239 PCH: device id 0284 (rev 00) is Cometlake-U Premium
349 12:44:48.915407 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
350 12:44:48.919050 VBOOT: Loading verstage.
351 12:44:48.921926 FMAP: Found "FLASH" version 1.1 at 0xc04000.
352 12:44:48.928758 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
353 12:44:48.932387 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
354 12:44:48.935966 CBFS @ c08000 size 3f8000
355 12:44:48.942032 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
356 12:44:48.945792 CBFS: Locating 'fallback/verstage'
357 12:44:48.949186 CBFS: Found @ offset 10fb80 size 1072c
358 12:44:48.952351
359 12:44:48.952485
360 12:44:48.962556 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
361 12:44:48.976948 Probing TPM: . done!
362 12:44:48.980167 TPM ready after 0 ms
363 12:44:48.983409 Connected to device vid:did:rid of 1ae0:0028:00
364 12:44:48.993795 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
365 12:44:48.997702 Initialized TPM device CR50 revision 0
366 12:44:49.041255 tlcl_send_startup: Startup return code is 0
367 12:44:49.041708 TPM: setup succeeded
368 12:44:49.053518 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
369 12:44:49.057509 Chrome EC: UHEPI supported
370 12:44:49.060709 Phase 1
371 12:44:49.063874 FMAP: area GBB found @ c05000 (12288 bytes)
372 12:44:49.070443 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
373 12:44:49.077198 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
374 12:44:49.080404 Recovery requested (1009000e)
375 12:44:49.086223 Saving nvdata
376 12:44:49.092510 tlcl_extend: response is 0
377 12:44:49.101048 tlcl_extend: response is 0
378 12:44:49.108146 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
379 12:44:49.111591 CBFS @ c08000 size 3f8000
380 12:44:49.118012 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
381 12:44:49.121245 CBFS: Locating 'fallback/romstage'
382 12:44:49.124434 CBFS: Found @ offset 80 size 145fc
383 12:44:49.128217 Accumulated console time in verstage 98 ms
384 12:44:49.128676
385 12:44:49.129005
386 12:44:49.141013 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
387 12:44:49.148098 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
388 12:44:49.150935 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
389 12:44:49.154561 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
390 12:44:49.160968 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
391 12:44:49.164033 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
392 12:44:49.167847 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
393 12:44:49.171211 TCO_STS: 0000 0000
394 12:44:49.174215 GEN_PMCON: e0015238 00000200
395 12:44:49.177428 GBLRST_CAUSE: 00000000 00000000
396 12:44:49.177870 prev_sleep_state 5
397 12:44:49.180834 Boot Count incremented to 48650
398 12:44:49.187755 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
399 12:44:49.191703 CBFS @ c08000 size 3f8000
400 12:44:49.197337 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
401 12:44:49.197855 CBFS: Locating 'fspm.bin'
402 12:44:49.204449 CBFS: Found @ offset 5ffc0 size 71000
403 12:44:49.207673 Chrome EC: UHEPI supported
404 12:44:49.214271 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
405 12:44:49.218156 Probing TPM: done!
406 12:44:49.224494 Connected to device vid:did:rid of 1ae0:0028:00
407 12:44:49.234265 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
408 12:44:49.240972 Initialized TPM device CR50 revision 0
409 12:44:49.249730 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
410 12:44:49.256285 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
411 12:44:49.259394 MRC cache found, size 1948
412 12:44:49.262788 bootmode is set to: 2
413 12:44:49.265678 PRMRR disabled by config.
414 12:44:49.269312 SPD INDEX = 1
415 12:44:49.272310 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
416 12:44:49.276226 CBFS @ c08000 size 3f8000
417 12:44:49.282723 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
418 12:44:49.283177 CBFS: Locating 'spd.bin'
419 12:44:49.285879 CBFS: Found @ offset 5fb80 size 400
420 12:44:49.288906 SPD: module type is LPDDR3
421 12:44:49.292687 SPD: module part is
422 12:44:49.298820 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
423 12:44:49.302799 SPD: device width 4 bits, bus width 8 bits
424 12:44:49.305327 SPD: module size is 4096 MB (per channel)
425 12:44:49.309514 memory slot: 0 configuration done.
426 12:44:49.312404 memory slot: 2 configuration done.
427 12:44:49.363979 CBMEM:
428 12:44:49.367199 IMD: root @ 99fff000 254 entries.
429 12:44:49.369904 IMD: root @ 99ffec00 62 entries.
430 12:44:49.373449 External stage cache:
431 12:44:49.376900 IMD: root @ 9abff000 254 entries.
432 12:44:49.379883 IMD: root @ 9abfec00 62 entries.
433 12:44:49.383451 Chrome EC: clear events_b mask to 0x0000000020004000
434 12:44:49.399257 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
435 12:44:49.412288 tlcl_write: response is 0
436 12:44:49.421420 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
437 12:44:49.428119 MRC: TPM MRC hash updated successfully.
438 12:44:49.428631 2 DIMMs found
439 12:44:49.431880 SMM Memory Map
440 12:44:49.434620 SMRAM : 0x9a000000 0x1000000
441 12:44:49.438480 Subregion 0: 0x9a000000 0xa00000
442 12:44:49.441689 Subregion 1: 0x9aa00000 0x200000
443 12:44:49.444891 Subregion 2: 0x9ac00000 0x400000
444 12:44:49.448092 top_of_ram = 0x9a000000
445 12:44:49.451153 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
446 12:44:49.457932 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
447 12:44:49.461155 MTRR Range: Start=ff000000 End=0 (Size 1000000)
448 12:44:49.468052 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
449 12:44:49.470974 CBFS @ c08000 size 3f8000
450 12:44:49.474554 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
451 12:44:49.477659 CBFS: Locating 'fallback/postcar'
452 12:44:49.484406 CBFS: Found @ offset 107000 size 4b44
453 12:44:49.490947 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
454 12:44:49.500495 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
455 12:44:49.503591 Processing 180 relocs. Offset value of 0x97c0c000
456 12:44:49.511638 Accumulated console time in romstage 286 ms
457 12:44:49.512056
458 12:44:49.512390
459 12:44:49.522008 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
460 12:44:49.528463 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
461 12:44:49.531488 CBFS @ c08000 size 3f8000
462 12:44:49.534711 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
463 12:44:49.541253 CBFS: Locating 'fallback/ramstage'
464 12:44:49.545342 CBFS: Found @ offset 43380 size 1b9e8
465 12:44:49.551335 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
466 12:44:49.583624 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
467 12:44:49.586976 Processing 3976 relocs. Offset value of 0x98db0000
468 12:44:49.593809 Accumulated console time in postcar 52 ms
469 12:44:49.594264
470 12:44:49.594623
471 12:44:49.603361 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
472 12:44:49.610131 FMAP: area RO_VPD found @ c00000 (16384 bytes)
473 12:44:49.613689 WARNING: RO_VPD is uninitialized or empty.
474 12:44:49.617109 FMAP: area RW_VPD found @ af8000 (8192 bytes)
475 12:44:49.623426 FMAP: area RW_VPD found @ af8000 (8192 bytes)
476 12:44:49.623960 Normal boot.
477 12:44:49.629680 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
478 12:44:49.633590 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
479 12:44:49.636765 CBFS @ c08000 size 3f8000
480 12:44:49.642700 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
481 12:44:49.646542 CBFS: Locating 'cpu_microcode_blob.bin'
482 12:44:49.650465 CBFS: Found @ offset 14700 size 2ec00
483 12:44:49.653286 microcode: sig=0x806ec pf=0x4 revision=0xc9
484 12:44:49.656608 Skip microcode update
485 12:44:49.662827 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
486 12:44:49.663308 CBFS @ c08000 size 3f8000
487 12:44:49.669366 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
488 12:44:49.673250 CBFS: Locating 'fsps.bin'
489 12:44:49.676424 CBFS: Found @ offset d1fc0 size 35000
490 12:44:49.701604 Detected 4 core, 8 thread CPU.
491 12:44:49.704631 Setting up SMI for CPU
492 12:44:49.708568 IED base = 0x9ac00000
493 12:44:49.709113 IED size = 0x00400000
494 12:44:49.711193 Will perform SMM setup.
495 12:44:49.717757 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
496 12:44:49.724512 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
497 12:44:49.727933 Processing 16 relocs. Offset value of 0x00030000
498 12:44:49.731850 Attempting to start 7 APs
499 12:44:49.735020 Waiting for 10ms after sending INIT.
500 12:44:49.751369 Waiting for 1st SIPI to complete...AP: slot 3 apic_id 1.
501 12:44:49.751891 done.
502 12:44:49.754900 AP: slot 6 apic_id 2.
503 12:44:49.758103 AP: slot 4 apic_id 3.
504 12:44:49.761243 Waiting for 2nd SIPI to complete...done.
505 12:44:49.764362 AP: slot 1 apic_id 5.
506 12:44:49.764806 AP: slot 2 apic_id 4.
507 12:44:49.767598 AP: slot 5 apic_id 7.
508 12:44:49.771553 AP: slot 7 apic_id 6.
509 12:44:49.777778 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
510 12:44:49.784253 Processing 13 relocs. Offset value of 0x00038000
511 12:44:49.787314 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
512 12:44:49.794476 Installing SMM handler to 0x9a000000
513 12:44:49.801034 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
514 12:44:49.807329 Processing 658 relocs. Offset value of 0x9a010000
515 12:44:49.814000 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
516 12:44:49.816940 Processing 13 relocs. Offset value of 0x9a008000
517 12:44:49.823906 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
518 12:44:49.830284 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
519 12:44:49.833625 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
520 12:44:49.840650 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
521 12:44:49.847071 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
522 12:44:49.853549 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
523 12:44:49.856715 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
524 12:44:49.863296 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
525 12:44:49.867193 Clearing SMI status registers
526 12:44:49.870401 SMI_STS: PM1
527 12:44:49.870503 PM1_STS: PWRBTN
528 12:44:49.873729 TCO_STS: SECOND_TO
529 12:44:49.876838 New SMBASE 0x9a000000
530 12:44:49.880269 In relocation handler: CPU 0
531 12:44:49.883471 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
532 12:44:49.886701 Writing SMRR. base = 0x9a000006, mask=0xff000800
533 12:44:49.890660 Relocation complete.
534 12:44:49.893862 New SMBASE 0x99fff400
535 12:44:49.893964 In relocation handler: CPU 3
536 12:44:49.900216 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
537 12:44:49.903801 Writing SMRR. base = 0x9a000006, mask=0xff000800
538 12:44:49.906845 Relocation complete.
539 12:44:49.910218 New SMBASE 0x99ffe800
540 12:44:49.910320 In relocation handler: CPU 6
541 12:44:49.916797 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
542 12:44:49.920093 Writing SMRR. base = 0x9a000006, mask=0xff000800
543 12:44:49.923631 Relocation complete.
544 12:44:49.923731 New SMBASE 0x99fff000
545 12:44:49.926688 In relocation handler: CPU 4
546 12:44:49.933406 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
547 12:44:49.936800 Writing SMRR. base = 0x9a000006, mask=0xff000800
548 12:44:49.940013 Relocation complete.
549 12:44:49.940112 New SMBASE 0x99ffec00
550 12:44:49.943093 In relocation handler: CPU 5
551 12:44:49.950257 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
552 12:44:49.953466 Writing SMRR. base = 0x9a000006, mask=0xff000800
553 12:44:49.956639 Relocation complete.
554 12:44:49.956738 New SMBASE 0x99ffe400
555 12:44:49.960096 In relocation handler: CPU 7
556 12:44:49.963428 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
557 12:44:49.969698 Writing SMRR. base = 0x9a000006, mask=0xff000800
558 12:44:49.972959 Relocation complete.
559 12:44:49.973059 New SMBASE 0x99fffc00
560 12:44:49.976062 In relocation handler: CPU 1
561 12:44:49.979986 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
562 12:44:49.986417 Writing SMRR. base = 0x9a000006, mask=0xff000800
563 12:44:49.989544 Relocation complete.
564 12:44:49.989644 New SMBASE 0x99fff800
565 12:44:49.992794 In relocation handler: CPU 2
566 12:44:49.995997 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
567 12:44:50.002983 Writing SMRR. base = 0x9a000006, mask=0xff000800
568 12:44:50.003092 Relocation complete.
569 12:44:50.006123 Initializing CPU #0
570 12:44:50.009341 CPU: vendor Intel device 806ec
571 12:44:50.012592 CPU: family 06, model 8e, stepping 0c
572 12:44:50.016166 Clearing out pending MCEs
573 12:44:50.019230 Setting up local APIC...
574 12:44:50.019333 apic_id: 0x00 done.
575 12:44:50.022448 Turbo is available but hidden
576 12:44:50.025987 Turbo is available and visible
577 12:44:50.029143 VMX status: enabled
578 12:44:50.032851 IA32_FEATURE_CONTROL status: locked
579 12:44:50.035755 Skip microcode update
580 12:44:50.035858 CPU #0 initialized
581 12:44:50.039394 Initializing CPU #3
582 12:44:50.042283 Initializing CPU #4
583 12:44:50.042383 Initializing CPU #6
584 12:44:50.046050 CPU: vendor Intel device 806ec
585 12:44:50.049059 CPU: family 06, model 8e, stepping 0c
586 12:44:50.052898 CPU: vendor Intel device 806ec
587 12:44:50.056115 CPU: family 06, model 8e, stepping 0c
588 12:44:50.059167 Clearing out pending MCEs
589 12:44:50.062447 Clearing out pending MCEs
590 12:44:50.065518 Setting up local APIC...
591 12:44:50.069269 CPU: vendor Intel device 806ec
592 12:44:50.072488 CPU: family 06, model 8e, stepping 0c
593 12:44:50.075640 Clearing out pending MCEs
594 12:44:50.075745 Initializing CPU #1
595 12:44:50.078879 Initializing CPU #2
596 12:44:50.081984 CPU: vendor Intel device 806ec
597 12:44:50.085763 CPU: family 06, model 8e, stepping 0c
598 12:44:50.089047 CPU: vendor Intel device 806ec
599 12:44:50.092205 CPU: family 06, model 8e, stepping 0c
600 12:44:50.095375 Clearing out pending MCEs
601 12:44:50.098615 Clearing out pending MCEs
602 12:44:50.098714 Setting up local APIC...
603 12:44:50.101869 Setting up local APIC...
604 12:44:50.105238 Initializing CPU #7
605 12:44:50.105336 Initializing CPU #5
606 12:44:50.108369 CPU: vendor Intel device 806ec
607 12:44:50.112221 CPU: family 06, model 8e, stepping 0c
608 12:44:50.114926 CPU: vendor Intel device 806ec
609 12:44:50.122077 CPU: family 06, model 8e, stepping 0c
610 12:44:50.122179 Clearing out pending MCEs
611 12:44:50.125021 Clearing out pending MCEs
612 12:44:50.128559 Setting up local APIC...
613 12:44:50.132142 apic_id: 0x03 done.
614 12:44:50.132254 Setting up local APIC...
615 12:44:50.135313 apic_id: 0x05 done.
616 12:44:50.138265 Setting up local APIC...
617 12:44:50.138396 apic_id: 0x02 done.
618 12:44:50.141942 VMX status: enabled
619 12:44:50.144965 VMX status: enabled
620 12:44:50.148589 IA32_FEATURE_CONTROL status: locked
621 12:44:50.151582 IA32_FEATURE_CONTROL status: locked
622 12:44:50.151681 Skip microcode update
623 12:44:50.155056 Skip microcode update
624 12:44:50.158207 CPU #4 initialized
625 12:44:50.158334 CPU #6 initialized
626 12:44:50.161409 VMX status: enabled
627 12:44:50.165154 apic_id: 0x04 done.
628 12:44:50.168472 IA32_FEATURE_CONTROL status: locked
629 12:44:50.168581 VMX status: enabled
630 12:44:50.171604 Skip microcode update
631 12:44:50.174862 IA32_FEATURE_CONTROL status: locked
632 12:44:50.178098 CPU #1 initialized
633 12:44:50.178196 Skip microcode update
634 12:44:50.181858 Setting up local APIC...
635 12:44:50.185017 CPU #2 initialized
636 12:44:50.185114 apic_id: 0x06 done.
637 12:44:50.188124 apic_id: 0x07 done.
638 12:44:50.191258 VMX status: enabled
639 12:44:50.191361 VMX status: enabled
640 12:44:50.194962 IA32_FEATURE_CONTROL status: locked
641 12:44:50.198297 IA32_FEATURE_CONTROL status: locked
642 12:44:50.201433 Skip microcode update
643 12:44:50.204798 Skip microcode update
644 12:44:50.204895 CPU #7 initialized
645 12:44:50.208052 CPU #5 initialized
646 12:44:50.211138 apic_id: 0x01 done.
647 12:44:50.211235 VMX status: enabled
648 12:44:50.214435 IA32_FEATURE_CONTROL status: locked
649 12:44:50.217717 Skip microcode update
650 12:44:50.221605 CPU #3 initialized
651 12:44:50.224744 bsp_do_flight_plan done after 461 msecs.
652 12:44:50.227773 CPU: frequency set to 4200 MHz
653 12:44:50.227870 Enabling SMIs.
654 12:44:50.231433 Locking SMM.
655 12:44:50.244919 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
656 12:44:50.248613 CBFS @ c08000 size 3f8000
657 12:44:50.254801 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
658 12:44:50.254901 CBFS: Locating 'vbt.bin'
659 12:44:50.261356 CBFS: Found @ offset 5f5c0 size 499
660 12:44:50.264537 Found a VBT of 4608 bytes after decompression
661 12:44:50.446515 Display FSP Version Info HOB
662 12:44:50.449581 Reference Code - CPU = 9.0.1e.30
663 12:44:50.453072 uCode Version = 0.0.0.ca
664 12:44:50.456152 TXT ACM version = ff.ff.ff.ffff
665 12:44:50.459686 Display FSP Version Info HOB
666 12:44:50.462774 Reference Code - ME = 9.0.1e.30
667 12:44:50.465901 MEBx version = 0.0.0.0
668 12:44:50.469587 ME Firmware Version = Consumer SKU
669 12:44:50.472679 Display FSP Version Info HOB
670 12:44:50.476280 Reference Code - CML PCH = 9.0.1e.30
671 12:44:50.479046 PCH-CRID Status = Disabled
672 12:44:50.482710 PCH-CRID Original Value = ff.ff.ff.ffff
673 12:44:50.485738 PCH-CRID New Value = ff.ff.ff.ffff
674 12:44:50.488974 OPROM - RST - RAID = ff.ff.ff.ffff
675 12:44:50.492972 ChipsetInit Base Version = ff.ff.ff.ffff
676 12:44:50.496065 ChipsetInit Oem Version = ff.ff.ff.ffff
677 12:44:50.499078 Display FSP Version Info HOB
678 12:44:50.506148 Reference Code - SA - System Agent = 9.0.1e.30
679 12:44:50.509311 Reference Code - MRC = 0.7.1.6c
680 12:44:50.509409 SA - PCIe Version = 9.0.1e.30
681 12:44:50.512553 SA-CRID Status = Disabled
682 12:44:50.515700 SA-CRID Original Value = 0.0.0.c
683 12:44:50.518974 SA-CRID New Value = 0.0.0.c
684 12:44:50.522205 OPROM - VBIOS = ff.ff.ff.ffff
685 12:44:50.525390 RTC Init
686 12:44:50.528658 Set power on after power failure.
687 12:44:50.528756 Disabling Deep S3
688 12:44:50.532505 Disabling Deep S3
689 12:44:50.532603 Disabling Deep S4
690 12:44:50.535693 Disabling Deep S4
691 12:44:50.538790 Disabling Deep S5
692 12:44:50.538898 Disabling Deep S5
693 12:44:50.545799 BS: BS_DEV_INIT_CHIPS times (ms): entry 36 run 192 exit 1
694 12:44:50.545898 Enumerating buses...
695 12:44:50.552198 Show all devs... Before device enumeration.
696 12:44:50.555089 Root Device: enabled 1
697 12:44:50.555189 CPU_CLUSTER: 0: enabled 1
698 12:44:50.558272 DOMAIN: 0000: enabled 1
699 12:44:50.561959 APIC: 00: enabled 1
700 12:44:50.562057 PCI: 00:00.0: enabled 1
701 12:44:50.565626 PCI: 00:02.0: enabled 1
702 12:44:50.568544 PCI: 00:04.0: enabled 0
703 12:44:50.571621 PCI: 00:05.0: enabled 0
704 12:44:50.571717 PCI: 00:12.0: enabled 1
705 12:44:50.575029 PCI: 00:12.5: enabled 0
706 12:44:50.578293 PCI: 00:12.6: enabled 0
707 12:44:50.582153 PCI: 00:14.0: enabled 1
708 12:44:50.582251 PCI: 00:14.1: enabled 0
709 12:44:50.585104 PCI: 00:14.3: enabled 1
710 12:44:50.588899 PCI: 00:14.5: enabled 0
711 12:44:50.589006 PCI: 00:15.0: enabled 1
712 12:44:50.591901 PCI: 00:15.1: enabled 1
713 12:44:50.595189 PCI: 00:15.2: enabled 0
714 12:44:50.598515 PCI: 00:15.3: enabled 0
715 12:44:50.598615 PCI: 00:16.0: enabled 1
716 12:44:50.601628 PCI: 00:16.1: enabled 0
717 12:44:50.605261 PCI: 00:16.2: enabled 0
718 12:44:50.608595 PCI: 00:16.3: enabled 0
719 12:44:50.608708 PCI: 00:16.4: enabled 0
720 12:44:50.611789 PCI: 00:16.5: enabled 0
721 12:44:50.615026 PCI: 00:17.0: enabled 1
722 12:44:50.618194 PCI: 00:19.0: enabled 1
723 12:44:50.618293 PCI: 00:19.1: enabled 0
724 12:44:50.621507 PCI: 00:19.2: enabled 0
725 12:44:50.625282 PCI: 00:1a.0: enabled 0
726 12:44:50.627964 PCI: 00:1c.0: enabled 0
727 12:44:50.628064 PCI: 00:1c.1: enabled 0
728 12:44:50.631966 PCI: 00:1c.2: enabled 0
729 12:44:50.635048 PCI: 00:1c.3: enabled 0
730 12:44:50.635165 PCI: 00:1c.4: enabled 0
731 12:44:50.638258 PCI: 00:1c.5: enabled 0
732 12:44:50.641612 PCI: 00:1c.6: enabled 0
733 12:44:50.644780 PCI: 00:1c.7: enabled 0
734 12:44:50.644880 PCI: 00:1d.0: enabled 1
735 12:44:50.648137 PCI: 00:1d.1: enabled 0
736 12:44:50.651292 PCI: 00:1d.2: enabled 0
737 12:44:50.654539 PCI: 00:1d.3: enabled 0
738 12:44:50.654639 PCI: 00:1d.4: enabled 0
739 12:44:50.658342 PCI: 00:1d.5: enabled 1
740 12:44:50.661580 PCI: 00:1e.0: enabled 1
741 12:44:50.664795 PCI: 00:1e.1: enabled 0
742 12:44:50.664896 PCI: 00:1e.2: enabled 1
743 12:44:50.667961 PCI: 00:1e.3: enabled 1
744 12:44:50.671627 PCI: 00:1f.0: enabled 1
745 12:44:50.671731 PCI: 00:1f.1: enabled 1
746 12:44:50.674609 PCI: 00:1f.2: enabled 1
747 12:44:50.678258 PCI: 00:1f.3: enabled 1
748 12:44:50.681259 PCI: 00:1f.4: enabled 1
749 12:44:50.681359 PCI: 00:1f.5: enabled 1
750 12:44:50.684675 PCI: 00:1f.6: enabled 0
751 12:44:50.687838 USB0 port 0: enabled 1
752 12:44:50.691494 I2C: 00:15: enabled 1
753 12:44:50.691600 I2C: 00:5d: enabled 1
754 12:44:50.694489 GENERIC: 0.0: enabled 1
755 12:44:50.698218 I2C: 00:1a: enabled 1
756 12:44:50.698320 I2C: 00:38: enabled 1
757 12:44:50.701436 I2C: 00:39: enabled 1
758 12:44:50.704595 I2C: 00:3a: enabled 1
759 12:44:50.704696 I2C: 00:3b: enabled 1
760 12:44:50.707700 PCI: 00:00.0: enabled 1
761 12:44:50.710949 SPI: 00: enabled 1
762 12:44:50.711050 SPI: 01: enabled 1
763 12:44:50.714138 PNP: 0c09.0: enabled 1
764 12:44:50.717980 USB2 port 0: enabled 1
765 12:44:50.718081 USB2 port 1: enabled 1
766 12:44:50.721327 USB2 port 2: enabled 0
767 12:44:50.724397 USB2 port 3: enabled 0
768 12:44:50.724498 USB2 port 5: enabled 0
769 12:44:50.727586 USB2 port 6: enabled 1
770 12:44:50.730910 USB2 port 9: enabled 1
771 12:44:50.734031 USB3 port 0: enabled 1
772 12:44:50.734132 USB3 port 1: enabled 1
773 12:44:50.737355 USB3 port 2: enabled 1
774 12:44:50.740993 USB3 port 3: enabled 1
775 12:44:50.741094 USB3 port 4: enabled 0
776 12:44:50.744100 APIC: 05: enabled 1
777 12:44:50.747286 APIC: 04: enabled 1
778 12:44:50.747387 APIC: 01: enabled 1
779 12:44:50.751026 APIC: 03: enabled 1
780 12:44:50.751145 APIC: 07: enabled 1
781 12:44:50.754390 APIC: 02: enabled 1
782 12:44:50.757425 APIC: 06: enabled 1
783 12:44:50.757522 Compare with tree...
784 12:44:50.760762 Root Device: enabled 1
785 12:44:50.763965 CPU_CLUSTER: 0: enabled 1
786 12:44:50.767093 APIC: 00: enabled 1
787 12:44:50.767198 APIC: 05: enabled 1
788 12:44:50.770837 APIC: 04: enabled 1
789 12:44:50.773813 APIC: 01: enabled 1
790 12:44:50.773914 APIC: 03: enabled 1
791 12:44:50.777462 APIC: 07: enabled 1
792 12:44:50.780648 APIC: 02: enabled 1
793 12:44:50.780766 APIC: 06: enabled 1
794 12:44:50.784195 DOMAIN: 0000: enabled 1
795 12:44:50.787233 PCI: 00:00.0: enabled 1
796 12:44:50.790781 PCI: 00:02.0: enabled 1
797 12:44:50.790901 PCI: 00:04.0: enabled 0
798 12:44:50.794050 PCI: 00:05.0: enabled 0
799 12:44:50.797490 PCI: 00:12.0: enabled 1
800 12:44:50.800487 PCI: 00:12.5: enabled 0
801 12:44:50.804014 PCI: 00:12.6: enabled 0
802 12:44:50.804132 PCI: 00:14.0: enabled 1
803 12:44:50.807422 USB0 port 0: enabled 1
804 12:44:50.810376 USB2 port 0: enabled 1
805 12:44:50.813616 USB2 port 1: enabled 1
806 12:44:50.817340 USB2 port 2: enabled 0
807 12:44:50.817454 USB2 port 3: enabled 0
808 12:44:50.820505 USB2 port 5: enabled 0
809 12:44:50.823781 USB2 port 6: enabled 1
810 12:44:50.826991 USB2 port 9: enabled 1
811 12:44:50.830178 USB3 port 0: enabled 1
812 12:44:50.833324 USB3 port 1: enabled 1
813 12:44:50.833442 USB3 port 2: enabled 1
814 12:44:50.837227 USB3 port 3: enabled 1
815 12:44:50.840312 USB3 port 4: enabled 0
816 12:44:50.843472 PCI: 00:14.1: enabled 0
817 12:44:50.847261 PCI: 00:14.3: enabled 1
818 12:44:50.847438 PCI: 00:14.5: enabled 0
819 12:44:50.850554 PCI: 00:15.0: enabled 1
820 12:44:50.853659 I2C: 00:15: enabled 1
821 12:44:50.856916 PCI: 00:15.1: enabled 1
822 12:44:50.860037 I2C: 00:5d: enabled 1
823 12:44:50.860171 GENERIC: 0.0: enabled 1
824 12:44:50.863212 PCI: 00:15.2: enabled 0
825 12:44:50.867038 PCI: 00:15.3: enabled 0
826 12:44:50.870344 PCI: 00:16.0: enabled 1
827 12:44:50.873600 PCI: 00:16.1: enabled 0
828 12:44:50.873726 PCI: 00:16.2: enabled 0
829 12:44:50.876722 PCI: 00:16.3: enabled 0
830 12:44:50.879871 PCI: 00:16.4: enabled 0
831 12:44:50.883406 PCI: 00:16.5: enabled 0
832 12:44:50.883556 PCI: 00:17.0: enabled 1
833 12:44:50.886891 PCI: 00:19.0: enabled 1
834 12:44:50.889934 I2C: 00:1a: enabled 1
835 12:44:50.893600 I2C: 00:38: enabled 1
836 12:44:50.896419 I2C: 00:39: enabled 1
837 12:44:50.896576 I2C: 00:3a: enabled 1
838 12:44:50.900085 I2C: 00:3b: enabled 1
839 12:44:50.903190 PCI: 00:19.1: enabled 0
840 12:44:50.906695 PCI: 00:19.2: enabled 0
841 12:44:50.906851 PCI: 00:1a.0: enabled 0
842 12:44:50.909809 PCI: 00:1c.0: enabled 0
843 12:44:50.913330 PCI: 00:1c.1: enabled 0
844 12:44:50.916257 PCI: 00:1c.2: enabled 0
845 12:44:50.920005 PCI: 00:1c.3: enabled 0
846 12:44:50.920119 PCI: 00:1c.4: enabled 0
847 12:44:50.923125 PCI: 00:1c.5: enabled 0
848 12:44:50.926335 PCI: 00:1c.6: enabled 0
849 12:44:50.929610 PCI: 00:1c.7: enabled 0
850 12:44:50.933415 PCI: 00:1d.0: enabled 1
851 12:44:50.933518 PCI: 00:1d.1: enabled 0
852 12:44:50.936621 PCI: 00:1d.2: enabled 0
853 12:44:50.939829 PCI: 00:1d.3: enabled 0
854 12:44:50.943051 PCI: 00:1d.4: enabled 0
855 12:44:50.946404 PCI: 00:1d.5: enabled 1
856 12:44:50.946505 PCI: 00:00.0: enabled 1
857 12:44:50.949567 PCI: 00:1e.0: enabled 1
858 12:44:50.952854 PCI: 00:1e.1: enabled 0
859 12:44:50.956142 PCI: 00:1e.2: enabled 1
860 12:44:50.956243 SPI: 00: enabled 1
861 12:44:50.959996 PCI: 00:1e.3: enabled 1
862 12:44:50.963098 SPI: 01: enabled 1
863 12:44:50.966394 PCI: 00:1f.0: enabled 1
864 12:44:50.969667 PNP: 0c09.0: enabled 1
865 12:44:50.969767 PCI: 00:1f.1: enabled 1
866 12:44:50.972969 PCI: 00:1f.2: enabled 1
867 12:44:50.976187 PCI: 00:1f.3: enabled 1
868 12:44:50.979195 PCI: 00:1f.4: enabled 1
869 12:44:50.979293 PCI: 00:1f.5: enabled 1
870 12:44:50.983057 PCI: 00:1f.6: enabled 0
871 12:44:50.986174 Root Device scanning...
872 12:44:50.989256 scan_static_bus for Root Device
873 12:44:50.992821 CPU_CLUSTER: 0 enabled
874 12:44:50.992940 DOMAIN: 0000 enabled
875 12:44:50.996416 DOMAIN: 0000 scanning...
876 12:44:50.999432 PCI: pci_scan_bus for bus 00
877 12:44:51.002882 PCI: 00:00.0 [8086/0000] ops
878 12:44:51.005870 PCI: 00:00.0 [8086/9b61] enabled
879 12:44:51.009449 PCI: 00:02.0 [8086/0000] bus ops
880 12:44:51.012512 PCI: 00:02.0 [8086/9b41] enabled
881 12:44:51.015956 PCI: 00:04.0 [8086/1903] disabled
882 12:44:51.019574 PCI: 00:08.0 [8086/1911] enabled
883 12:44:51.022664 PCI: 00:12.0 [8086/02f9] enabled
884 12:44:51.025617 PCI: 00:14.0 [8086/0000] bus ops
885 12:44:51.029191 PCI: 00:14.0 [8086/02ed] enabled
886 12:44:51.032837 PCI: 00:14.2 [8086/02ef] enabled
887 12:44:51.036167 PCI: 00:14.3 [8086/02f0] enabled
888 12:44:51.039457 PCI: 00:15.0 [8086/0000] bus ops
889 12:44:51.042486 PCI: 00:15.0 [8086/02e8] enabled
890 12:44:51.045664 PCI: 00:15.1 [8086/0000] bus ops
891 12:44:51.049046 PCI: 00:15.1 [8086/02e9] enabled
892 12:44:51.052235 PCI: 00:16.0 [8086/0000] ops
893 12:44:51.055498 PCI: 00:16.0 [8086/02e0] enabled
894 12:44:51.059263 PCI: 00:17.0 [8086/0000] ops
895 12:44:51.062596 PCI: 00:17.0 [8086/02d3] enabled
896 12:44:51.065653 PCI: 00:19.0 [8086/0000] bus ops
897 12:44:51.068953 PCI: 00:19.0 [8086/02c5] enabled
898 12:44:51.072222 PCI: 00:1d.0 [8086/0000] bus ops
899 12:44:51.075602 PCI: 00:1d.0 [8086/02b0] enabled
900 12:44:51.081992 PCI: Static device PCI: 00:1d.5 not found, disabling it.
901 12:44:51.085848 PCI: 00:1e.0 [8086/0000] ops
902 12:44:51.088958 PCI: 00:1e.0 [8086/02a8] enabled
903 12:44:51.092277 PCI: 00:1e.2 [8086/0000] bus ops
904 12:44:51.095301 PCI: 00:1e.2 [8086/02aa] enabled
905 12:44:51.098972 PCI: 00:1e.3 [8086/0000] bus ops
906 12:44:51.102074 PCI: 00:1e.3 [8086/02ab] enabled
907 12:44:51.105693 PCI: 00:1f.0 [8086/0000] bus ops
908 12:44:51.108635 PCI: 00:1f.0 [8086/0284] enabled
909 12:44:51.112154 PCI: Static device PCI: 00:1f.1 not found, disabling it.
910 12:44:51.118369 PCI: Static device PCI: 00:1f.2 not found, disabling it.
911 12:44:51.122016 PCI: 00:1f.3 [8086/0000] bus ops
912 12:44:51.125462 PCI: 00:1f.3 [8086/02c8] enabled
913 12:44:51.128588 PCI: 00:1f.4 [8086/0000] bus ops
914 12:44:51.131728 PCI: 00:1f.4 [8086/02a3] enabled
915 12:44:51.135384 PCI: 00:1f.5 [8086/0000] bus ops
916 12:44:51.138242 PCI: 00:1f.5 [8086/02a4] enabled
917 12:44:51.142008 PCI: Leftover static devices:
918 12:44:51.142109 PCI: 00:05.0
919 12:44:51.145188 PCI: 00:12.5
920 12:44:51.145288 PCI: 00:12.6
921 12:44:51.148428 PCI: 00:14.1
922 12:44:51.148527 PCI: 00:14.5
923 12:44:51.148607 PCI: 00:15.2
924 12:44:51.151649 PCI: 00:15.3
925 12:44:51.151749 PCI: 00:16.1
926 12:44:51.155380 PCI: 00:16.2
927 12:44:51.155479 PCI: 00:16.3
928 12:44:51.155559 PCI: 00:16.4
929 12:44:51.158638 PCI: 00:16.5
930 12:44:51.158738 PCI: 00:19.1
931 12:44:51.161719 PCI: 00:19.2
932 12:44:51.161819 PCI: 00:1a.0
933 12:44:51.161897 PCI: 00:1c.0
934 12:44:51.164997 PCI: 00:1c.1
935 12:44:51.165096 PCI: 00:1c.2
936 12:44:51.168172 PCI: 00:1c.3
937 12:44:51.168272 PCI: 00:1c.4
938 12:44:51.171979 PCI: 00:1c.5
939 12:44:51.172079 PCI: 00:1c.6
940 12:44:51.172158 PCI: 00:1c.7
941 12:44:51.175101 PCI: 00:1d.1
942 12:44:51.175201 PCI: 00:1d.2
943 12:44:51.178459 PCI: 00:1d.3
944 12:44:51.178558 PCI: 00:1d.4
945 12:44:51.178638 PCI: 00:1d.5
946 12:44:51.181569 PCI: 00:1e.1
947 12:44:51.181669 PCI: 00:1f.1
948 12:44:51.184853 PCI: 00:1f.2
949 12:44:51.184953 PCI: 00:1f.6
950 12:44:51.187907 PCI: Check your devicetree.cb.
951 12:44:51.191915 PCI: 00:02.0 scanning...
952 12:44:51.194583 scan_generic_bus for PCI: 00:02.0
953 12:44:51.198472 scan_generic_bus for PCI: 00:02.0 done
954 12:44:51.204699 scan_bus: scanning of bus PCI: 00:02.0 took 10188 usecs
955 12:44:51.208217 PCI: 00:14.0 scanning...
956 12:44:51.210998 scan_static_bus for PCI: 00:14.0
957 12:44:51.211098 USB0 port 0 enabled
958 12:44:51.214806 USB0 port 0 scanning...
959 12:44:51.217794 scan_static_bus for USB0 port 0
960 12:44:51.221487 USB2 port 0 enabled
961 12:44:51.221579 USB2 port 1 enabled
962 12:44:51.224433 USB2 port 2 disabled
963 12:44:51.228178 USB2 port 3 disabled
964 12:44:51.228270 USB2 port 5 disabled
965 12:44:51.231204 USB2 port 6 enabled
966 12:44:51.231296 USB2 port 9 enabled
967 12:44:51.234845 USB3 port 0 enabled
968 12:44:51.237972 USB3 port 1 enabled
969 12:44:51.238065 USB3 port 2 enabled
970 12:44:51.240964 USB3 port 3 enabled
971 12:44:51.244411 USB3 port 4 disabled
972 12:44:51.244502 USB2 port 0 scanning...
973 12:44:51.247612 scan_static_bus for USB2 port 0
974 12:44:51.251502 scan_static_bus for USB2 port 0 done
975 12:44:51.257799 scan_bus: scanning of bus USB2 port 0 took 9698 usecs
976 12:44:51.261088 USB2 port 1 scanning...
977 12:44:51.264223 scan_static_bus for USB2 port 1
978 12:44:51.267565 scan_static_bus for USB2 port 1 done
979 12:44:51.274039 scan_bus: scanning of bus USB2 port 1 took 9706 usecs
980 12:44:51.274142 USB2 port 6 scanning...
981 12:44:51.277240 scan_static_bus for USB2 port 6
982 12:44:51.284294 scan_static_bus for USB2 port 6 done
983 12:44:51.287522 scan_bus: scanning of bus USB2 port 6 took 9711 usecs
984 12:44:51.290616 USB2 port 9 scanning...
985 12:44:51.293840 scan_static_bus for USB2 port 9
986 12:44:51.297705 scan_static_bus for USB2 port 9 done
987 12:44:51.304267 scan_bus: scanning of bus USB2 port 9 took 9699 usecs
988 12:44:51.304377 USB3 port 0 scanning...
989 12:44:51.307224 scan_static_bus for USB3 port 0
990 12:44:51.314062 scan_static_bus for USB3 port 0 done
991 12:44:51.317802 scan_bus: scanning of bus USB3 port 0 took 9708 usecs
992 12:44:51.320651 USB3 port 1 scanning...
993 12:44:51.324131 scan_static_bus for USB3 port 1
994 12:44:51.327077 scan_static_bus for USB3 port 1 done
995 12:44:51.334113 scan_bus: scanning of bus USB3 port 1 took 9706 usecs
996 12:44:51.334213 USB3 port 2 scanning...
997 12:44:51.337188 scan_static_bus for USB3 port 2
998 12:44:51.344008 scan_static_bus for USB3 port 2 done
999 12:44:51.347096 scan_bus: scanning of bus USB3 port 2 took 9691 usecs
1000 12:44:51.350621 USB3 port 3 scanning...
1001 12:44:51.354129 scan_static_bus for USB3 port 3
1002 12:44:51.357110 scan_static_bus for USB3 port 3 done
1003 12:44:51.364239 scan_bus: scanning of bus USB3 port 3 took 9707 usecs
1004 12:44:51.367380 scan_static_bus for USB0 port 0 done
1005 12:44:51.374004 scan_bus: scanning of bus USB0 port 0 took 155387 usecs
1006 12:44:51.377104 scan_static_bus for PCI: 00:14.0 done
1007 12:44:51.380368 scan_bus: scanning of bus PCI: 00:14.0 took 173024 usecs
1008 12:44:51.383679 PCI: 00:15.0 scanning...
1009 12:44:51.387519 scan_generic_bus for PCI: 00:15.0
1010 12:44:51.390139 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
1011 12:44:51.397219 scan_generic_bus for PCI: 00:15.0 done
1012 12:44:51.400281 scan_bus: scanning of bus PCI: 00:15.0 took 14304 usecs
1013 12:44:51.403529 PCI: 00:15.1 scanning...
1014 12:44:51.407189 scan_generic_bus for PCI: 00:15.1
1015 12:44:51.410412 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
1016 12:44:51.417336 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
1017 12:44:51.420593 scan_generic_bus for PCI: 00:15.1 done
1018 12:44:51.427103 scan_bus: scanning of bus PCI: 00:15.1 took 18605 usecs
1019 12:44:51.427203 PCI: 00:19.0 scanning...
1020 12:44:51.430081 scan_generic_bus for PCI: 00:19.0
1021 12:44:51.436707 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
1022 12:44:51.440407 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
1023 12:44:51.443362 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
1024 12:44:51.447209 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
1025 12:44:51.453374 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
1026 12:44:51.456437 scan_generic_bus for PCI: 00:19.0 done
1027 12:44:51.459979 scan_bus: scanning of bus PCI: 00:19.0 took 30729 usecs
1028 12:44:51.463106 PCI: 00:1d.0 scanning...
1029 12:44:51.466626 do_pci_scan_bridge for PCI: 00:1d.0
1030 12:44:51.470042 PCI: pci_scan_bus for bus 01
1031 12:44:51.473255 PCI: 01:00.0 [1c5c/1327] enabled
1032 12:44:51.476633 Enabling Common Clock Configuration
1033 12:44:51.483092 L1 Sub-State supported from root port 29
1034 12:44:51.486534 L1 Sub-State Support = 0xf
1035 12:44:51.486633 CommonModeRestoreTime = 0x28
1036 12:44:51.493556 Power On Value = 0x16, Power On Scale = 0x0
1037 12:44:51.493657 ASPM: Enabled L1
1038 12:44:51.499992 scan_bus: scanning of bus PCI: 00:1d.0 took 32798 usecs
1039 12:44:51.503217 PCI: 00:1e.2 scanning...
1040 12:44:51.506454 scan_generic_bus for PCI: 00:1e.2
1041 12:44:51.509705 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
1042 12:44:51.512854 scan_generic_bus for PCI: 00:1e.2 done
1043 12:44:51.519958 scan_bus: scanning of bus PCI: 00:1e.2 took 14006 usecs
1044 12:44:51.523005 PCI: 00:1e.3 scanning...
1045 12:44:51.526356 scan_generic_bus for PCI: 00:1e.3
1046 12:44:51.529500 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1047 12:44:51.532684 scan_generic_bus for PCI: 00:1e.3 done
1048 12:44:51.539897 scan_bus: scanning of bus PCI: 00:1e.3 took 14006 usecs
1049 12:44:51.542724 PCI: 00:1f.0 scanning...
1050 12:44:51.545871 scan_static_bus for PCI: 00:1f.0
1051 12:44:51.545989 PNP: 0c09.0 enabled
1052 12:44:51.549504 scan_static_bus for PCI: 00:1f.0 done
1053 12:44:51.556130 scan_bus: scanning of bus PCI: 00:1f.0 took 12060 usecs
1054 12:44:51.559208 PCI: 00:1f.3 scanning...
1055 12:44:51.565874 scan_bus: scanning of bus PCI: 00:1f.3 took 2860 usecs
1056 12:44:51.565978 PCI: 00:1f.4 scanning...
1057 12:44:51.569454 scan_generic_bus for PCI: 00:1f.4
1058 12:44:51.576084 scan_generic_bus for PCI: 00:1f.4 done
1059 12:44:51.579288 scan_bus: scanning of bus PCI: 00:1f.4 took 10198 usecs
1060 12:44:51.582584 PCI: 00:1f.5 scanning...
1061 12:44:51.585747 scan_generic_bus for PCI: 00:1f.5
1062 12:44:51.588885 scan_generic_bus for PCI: 00:1f.5 done
1063 12:44:51.595937 scan_bus: scanning of bus PCI: 00:1f.5 took 10180 usecs
1064 12:44:51.602452 scan_bus: scanning of bus DOMAIN: 0000 took 605130 usecs
1065 12:44:51.605598 scan_static_bus for Root Device done
1066 12:44:51.612223 scan_bus: scanning of bus Root Device took 624984 usecs
1067 12:44:51.612323 done
1068 12:44:51.615453 Chrome EC: UHEPI supported
1069 12:44:51.622472 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1070 12:44:51.625563 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1071 12:44:51.632072 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1072 12:44:51.639021 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1073 12:44:51.642690 SPI flash protection: WPSW=0 SRP0=0
1074 12:44:51.649194 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1075 12:44:51.652228 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 9 exit 2
1076 12:44:51.655389 found VGA at PCI: 00:02.0
1077 12:44:51.658799 Setting up VGA for PCI: 00:02.0
1078 12:44:51.665328 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1079 12:44:51.668789 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1080 12:44:51.672243 Allocating resources...
1081 12:44:51.675334 Reading resources...
1082 12:44:51.679003 Root Device read_resources bus 0 link: 0
1083 12:44:51.682083 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1084 12:44:51.689118 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1085 12:44:51.692287 DOMAIN: 0000 read_resources bus 0 link: 0
1086 12:44:51.699179 PCI: 00:14.0 read_resources bus 0 link: 0
1087 12:44:51.702328 USB0 port 0 read_resources bus 0 link: 0
1088 12:44:51.710642 USB0 port 0 read_resources bus 0 link: 0 done
1089 12:44:51.713924 PCI: 00:14.0 read_resources bus 0 link: 0 done
1090 12:44:51.721541 PCI: 00:15.0 read_resources bus 1 link: 0
1091 12:44:51.724774 PCI: 00:15.0 read_resources bus 1 link: 0 done
1092 12:44:51.731693 PCI: 00:15.1 read_resources bus 2 link: 0
1093 12:44:51.734927 PCI: 00:15.1 read_resources bus 2 link: 0 done
1094 12:44:51.742082 PCI: 00:19.0 read_resources bus 3 link: 0
1095 12:44:51.748968 PCI: 00:19.0 read_resources bus 3 link: 0 done
1096 12:44:51.752148 PCI: 00:1d.0 read_resources bus 1 link: 0
1097 12:44:51.758731 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1098 12:44:51.762508 PCI: 00:1e.2 read_resources bus 4 link: 0
1099 12:44:51.768581 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1100 12:44:51.772155 PCI: 00:1e.3 read_resources bus 5 link: 0
1101 12:44:51.778807 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1102 12:44:51.782165 PCI: 00:1f.0 read_resources bus 0 link: 0
1103 12:44:51.788436 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1104 12:44:51.795452 DOMAIN: 0000 read_resources bus 0 link: 0 done
1105 12:44:51.798711 Root Device read_resources bus 0 link: 0 done
1106 12:44:51.801865 Done reading resources.
1107 12:44:51.808215 Show resources in subtree (Root Device)...After reading.
1108 12:44:51.811445 Root Device child on link 0 CPU_CLUSTER: 0
1109 12:44:51.814663 CPU_CLUSTER: 0 child on link 0 APIC: 00
1110 12:44:51.817937 APIC: 00
1111 12:44:51.818025 APIC: 05
1112 12:44:51.818100 APIC: 04
1113 12:44:51.821884 APIC: 01
1114 12:44:51.821970 APIC: 03
1115 12:44:51.822043 APIC: 07
1116 12:44:51.824496 APIC: 02
1117 12:44:51.824581 APIC: 06
1118 12:44:51.831700 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1119 12:44:51.838072 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1120 12:44:51.894141 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1121 12:44:51.894267 PCI: 00:00.0
1122 12:44:51.895362 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1123 12:44:51.895657 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1124 12:44:51.895928 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1125 12:44:51.896195 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1126 12:44:51.944151 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1127 12:44:51.944454 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1128 12:44:51.944728 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1129 12:44:51.944810 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1130 12:44:51.945069 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1131 12:44:51.945334 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1132 12:44:51.951395 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1133 12:44:51.961808 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1134 12:44:51.971734 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1135 12:44:51.981456 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1136 12:44:51.990862 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1137 12:44:52.001004 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1138 12:44:52.001108 PCI: 00:02.0
1139 12:44:52.010875 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1140 12:44:52.024256 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1141 12:44:52.030711 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1142 12:44:52.033844 PCI: 00:04.0
1143 12:44:52.033944 PCI: 00:08.0
1144 12:44:52.043961 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1145 12:44:52.047109 PCI: 00:12.0
1146 12:44:52.057245 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1147 12:44:52.060474 PCI: 00:14.0 child on link 0 USB0 port 0
1148 12:44:52.070227 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1149 12:44:52.073483 USB0 port 0 child on link 0 USB2 port 0
1150 12:44:52.076675 USB2 port 0
1151 12:44:52.076773 USB2 port 1
1152 12:44:52.080030 USB2 port 2
1153 12:44:52.080128 USB2 port 3
1154 12:44:52.083513 USB2 port 5
1155 12:44:52.087173 USB2 port 6
1156 12:44:52.087271 USB2 port 9
1157 12:44:52.090361 USB3 port 0
1158 12:44:52.090465 USB3 port 1
1159 12:44:52.093158 USB3 port 2
1160 12:44:52.093293 USB3 port 3
1161 12:44:52.096809 USB3 port 4
1162 12:44:52.096908 PCI: 00:14.2
1163 12:44:52.106714 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1164 12:44:52.117072 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1165 12:44:52.120217 PCI: 00:14.3
1166 12:44:52.129842 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1167 12:44:52.133072 PCI: 00:15.0 child on link 0 I2C: 01:15
1168 12:44:52.143370 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1169 12:44:52.143464 I2C: 01:15
1170 12:44:52.149834 PCI: 00:15.1 child on link 0 I2C: 02:5d
1171 12:44:52.160004 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1172 12:44:52.160097 I2C: 02:5d
1173 12:44:52.163300 GENERIC: 0.0
1174 12:44:52.163391 PCI: 00:16.0
1175 12:44:52.173013 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1176 12:44:52.176331 PCI: 00:17.0
1177 12:44:52.182714 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1178 12:44:52.192582 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1179 12:44:52.202492 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1180 12:44:52.209315 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1181 12:44:52.219511 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1182 12:44:52.225852 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1183 12:44:52.232138 PCI: 00:19.0 child on link 0 I2C: 03:1a
1184 12:44:52.242450 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1185 12:44:52.242553 I2C: 03:1a
1186 12:44:52.245752 I2C: 03:38
1187 12:44:52.245852 I2C: 03:39
1188 12:44:52.248971 I2C: 03:3a
1189 12:44:52.249070 I2C: 03:3b
1190 12:44:52.252039 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1191 12:44:52.262249 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1192 12:44:52.272493 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1193 12:44:52.282017 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1194 12:44:52.282118 PCI: 01:00.0
1195 12:44:52.292039 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1196 12:44:52.295311 PCI: 00:1e.0
1197 12:44:52.305381 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1198 12:44:52.315131 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1199 12:44:52.318199 PCI: 00:1e.2 child on link 0 SPI: 00
1200 12:44:52.328449 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1201 12:44:52.331573 SPI: 00
1202 12:44:52.334904 PCI: 00:1e.3 child on link 0 SPI: 01
1203 12:44:52.345014 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1204 12:44:52.345115 SPI: 01
1205 12:44:52.351341 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1206 12:44:52.358278 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1207 12:44:52.367823 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1208 12:44:52.371055 PNP: 0c09.0
1209 12:44:52.378056 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1210 12:44:52.381254 PCI: 00:1f.3
1211 12:44:52.391497 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1212 12:44:52.401104 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1213 12:44:52.401203 PCI: 00:1f.4
1214 12:44:52.410960 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1215 12:44:52.421263 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1216 12:44:52.421367 PCI: 00:1f.5
1217 12:44:52.431070 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1218 12:44:52.437597 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1219 12:44:52.443940 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1220 12:44:52.450411 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1221 12:44:52.453734 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1222 12:44:52.457522 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1223 12:44:52.460804 PCI: 00:17.0 18 * [0x60 - 0x67] io
1224 12:44:52.463837 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1225 12:44:52.470343 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1226 12:44:52.477356 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1227 12:44:52.486940 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1228 12:44:52.493879 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1229 12:44:52.503568 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1230 12:44:52.506821 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1231 12:44:52.513729 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1232 12:44:52.516690 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1233 12:44:52.523266 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1234 12:44:52.526884 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1235 12:44:52.533489 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1236 12:44:52.536517 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1237 12:44:52.543709 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1238 12:44:52.546822 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1239 12:44:52.553128 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1240 12:44:52.556883 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1241 12:44:52.563068 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1242 12:44:52.566328 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1243 12:44:52.572735 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1244 12:44:52.576609 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1245 12:44:52.583042 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1246 12:44:52.586210 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1247 12:44:52.589464 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1248 12:44:52.596366 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1249 12:44:52.599503 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1250 12:44:52.606017 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1251 12:44:52.609123 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1252 12:44:52.615838 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1253 12:44:52.619576 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1254 12:44:52.626330 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1255 12:44:52.632487 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1256 12:44:52.636288 avoid_fixed_resources: DOMAIN: 0000
1257 12:44:52.642392 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1258 12:44:52.649242 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1259 12:44:52.655918 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1260 12:44:52.665401 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1261 12:44:52.672382 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1262 12:44:52.678566 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1263 12:44:52.688769 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1264 12:44:52.695356 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1265 12:44:52.702215 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1266 12:44:52.711715 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1267 12:44:52.718813 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1268 12:44:52.725276 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1269 12:44:52.728436 Setting resources...
1270 12:44:52.735028 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1271 12:44:52.738460 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1272 12:44:52.741537 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1273 12:44:52.745195 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1274 12:44:52.748293 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1275 12:44:52.754675 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1276 12:44:52.761376 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1277 12:44:52.768086 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1278 12:44:52.774729 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1279 12:44:52.781063 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1280 12:44:52.784876 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1281 12:44:52.791283 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1282 12:44:52.794578 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1283 12:44:52.801105 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1284 12:44:52.804399 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1285 12:44:52.811270 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1286 12:44:52.814477 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1287 12:44:52.820895 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1288 12:44:52.824214 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1289 12:44:52.831187 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1290 12:44:52.834269 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1291 12:44:52.840656 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1292 12:44:52.844137 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1293 12:44:52.850677 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1294 12:44:52.854354 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1295 12:44:52.857331 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1296 12:44:52.864057 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1297 12:44:52.867611 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1298 12:44:52.874114 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1299 12:44:52.877059 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1300 12:44:52.884113 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1301 12:44:52.887191 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1302 12:44:52.896877 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1303 12:44:52.903910 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1304 12:44:52.910415 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1305 12:44:52.917249 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1306 12:44:52.923616 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1307 12:44:52.929974 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1308 12:44:52.933796 Root Device assign_resources, bus 0 link: 0
1309 12:44:52.939957 DOMAIN: 0000 assign_resources, bus 0 link: 0
1310 12:44:52.946557 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1311 12:44:52.956548 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1312 12:44:52.963232 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1313 12:44:52.972927 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1314 12:44:52.979774 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1315 12:44:52.989892 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1316 12:44:52.993251 PCI: 00:14.0 assign_resources, bus 0 link: 0
1317 12:44:52.996349 PCI: 00:14.0 assign_resources, bus 0 link: 0
1318 12:44:53.006670 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1319 12:44:53.013110 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1320 12:44:53.022875 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1321 12:44:53.029842 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1322 12:44:53.036418 PCI: 00:15.0 assign_resources, bus 1 link: 0
1323 12:44:53.039485 PCI: 00:15.0 assign_resources, bus 1 link: 0
1324 12:44:53.049789 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1325 12:44:53.052897 PCI: 00:15.1 assign_resources, bus 2 link: 0
1326 12:44:53.056131 PCI: 00:15.1 assign_resources, bus 2 link: 0
1327 12:44:53.065962 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1328 12:44:53.072870 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1329 12:44:53.082426 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1330 12:44:53.089678 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1331 12:44:53.095620 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1332 12:44:53.105473 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1333 12:44:53.112539 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1334 12:44:53.122108 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1335 12:44:53.125761 PCI: 00:19.0 assign_resources, bus 3 link: 0
1336 12:44:53.128934 PCI: 00:19.0 assign_resources, bus 3 link: 0
1337 12:44:53.138597 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1338 12:44:53.148716 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1339 12:44:53.155194 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1340 12:44:53.161618 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1341 12:44:53.168603 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1342 12:44:53.175345 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1343 12:44:53.181453 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1344 12:44:53.191352 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1345 12:44:53.194828 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1346 12:44:53.198356 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1347 12:44:53.207720 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1348 12:44:53.211303 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1349 12:44:53.218253 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1350 12:44:53.221408 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1351 12:44:53.227798 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1352 12:44:53.230967 LPC: Trying to open IO window from 800 size 1ff
1353 12:44:53.240820 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1354 12:44:53.247892 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1355 12:44:53.257616 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1356 12:44:53.264232 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1357 12:44:53.267294 DOMAIN: 0000 assign_resources, bus 0 link: 0
1358 12:44:53.274152 Root Device assign_resources, bus 0 link: 0
1359 12:44:53.277869 Done setting resources.
1360 12:44:53.284194 Show resources in subtree (Root Device)...After assigning values.
1361 12:44:53.287311 Root Device child on link 0 CPU_CLUSTER: 0
1362 12:44:53.290801 CPU_CLUSTER: 0 child on link 0 APIC: 00
1363 12:44:53.290897 APIC: 00
1364 12:44:53.294386 APIC: 05
1365 12:44:53.294481 APIC: 04
1366 12:44:53.297787 APIC: 01
1367 12:44:53.297882 APIC: 03
1368 12:44:53.297957 APIC: 07
1369 12:44:53.300751 APIC: 02
1370 12:44:53.300847 APIC: 06
1371 12:44:53.307743 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1372 12:44:53.314257 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1373 12:44:53.327401 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1374 12:44:53.327504 PCI: 00:00.0
1375 12:44:53.336935 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1376 12:44:53.347112 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1377 12:44:53.356666 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1378 12:44:53.366942 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1379 12:44:53.376961 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1380 12:44:53.383096 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1381 12:44:53.393308 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1382 12:44:53.403298 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1383 12:44:53.413084 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1384 12:44:53.423034 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1385 12:44:53.429483 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1386 12:44:53.439498 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1387 12:44:53.449675 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1388 12:44:53.459556 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1389 12:44:53.469363 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1390 12:44:53.478955 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1391 12:44:53.479055 PCI: 00:02.0
1392 12:44:53.489204 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1393 12:44:53.502064 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1394 12:44:53.509083 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1395 12:44:53.512012 PCI: 00:04.0
1396 12:44:53.512109 PCI: 00:08.0
1397 12:44:53.525427 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1398 12:44:53.525527 PCI: 00:12.0
1399 12:44:53.535226 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1400 12:44:53.542144 PCI: 00:14.0 child on link 0 USB0 port 0
1401 12:44:53.552103 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1402 12:44:53.555196 USB0 port 0 child on link 0 USB2 port 0
1403 12:44:53.558388 USB2 port 0
1404 12:44:53.558485 USB2 port 1
1405 12:44:53.561687 USB2 port 2
1406 12:44:53.561785 USB2 port 3
1407 12:44:53.564898 USB2 port 5
1408 12:44:53.564995 USB2 port 6
1409 12:44:53.568182 USB2 port 9
1410 12:44:53.568279 USB3 port 0
1411 12:44:53.571326 USB3 port 1
1412 12:44:53.571423 USB3 port 2
1413 12:44:53.575101 USB3 port 3
1414 12:44:53.575199 USB3 port 4
1415 12:44:53.578391 PCI: 00:14.2
1416 12:44:53.588251 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1417 12:44:53.598056 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1418 12:44:53.601297 PCI: 00:14.3
1419 12:44:53.611655 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1420 12:44:53.614783 PCI: 00:15.0 child on link 0 I2C: 01:15
1421 12:44:53.624609 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1422 12:44:53.628038 I2C: 01:15
1423 12:44:53.630950 PCI: 00:15.1 child on link 0 I2C: 02:5d
1424 12:44:53.641086 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1425 12:44:53.641188 I2C: 02:5d
1426 12:44:53.644501 GENERIC: 0.0
1427 12:44:53.647529 PCI: 00:16.0
1428 12:44:53.657618 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1429 12:44:53.657719 PCI: 00:17.0
1430 12:44:53.667490 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1431 12:44:53.677222 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1432 12:44:53.687377 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1433 12:44:53.697503 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1434 12:44:53.707089 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1435 12:44:53.716732 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1436 12:44:53.720571 PCI: 00:19.0 child on link 0 I2C: 03:1a
1437 12:44:53.730022 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1438 12:44:53.733726 I2C: 03:1a
1439 12:44:53.733826 I2C: 03:38
1440 12:44:53.733923 I2C: 03:39
1441 12:44:53.736766 I2C: 03:3a
1442 12:44:53.736866 I2C: 03:3b
1443 12:44:53.743241 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1444 12:44:53.753489 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1445 12:44:53.763229 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1446 12:44:53.773337 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1447 12:44:53.773438 PCI: 01:00.0
1448 12:44:53.782916 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1449 12:44:53.786906 PCI: 00:1e.0
1450 12:44:53.796253 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1451 12:44:53.806454 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1452 12:44:53.812901 PCI: 00:1e.2 child on link 0 SPI: 00
1453 12:44:53.822525 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1454 12:44:53.822625 SPI: 00
1455 12:44:53.826381 PCI: 00:1e.3 child on link 0 SPI: 01
1456 12:44:53.836123 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1457 12:44:53.838995 SPI: 01
1458 12:44:53.842584 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1459 12:44:53.852723 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1460 12:44:53.862550 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1461 12:44:53.862652 PNP: 0c09.0
1462 12:44:53.872684 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1463 12:44:53.872787 PCI: 00:1f.3
1464 12:44:53.882541 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1465 12:44:53.892157 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1466 12:44:53.895292 PCI: 00:1f.4
1467 12:44:53.905466 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1468 12:44:53.915170 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1469 12:44:53.915278 PCI: 00:1f.5
1470 12:44:53.925688 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1471 12:44:53.928887 Done allocating resources.
1472 12:44:53.934865 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1473 12:44:53.938063 Enabling resources...
1474 12:44:53.941769 PCI: 00:00.0 subsystem <- 8086/9b61
1475 12:44:53.944854 PCI: 00:00.0 cmd <- 06
1476 12:44:53.948388 PCI: 00:02.0 subsystem <- 8086/9b41
1477 12:44:53.951277 PCI: 00:02.0 cmd <- 03
1478 12:44:53.954988 PCI: 00:08.0 cmd <- 06
1479 12:44:53.958081 PCI: 00:12.0 subsystem <- 8086/02f9
1480 12:44:53.958174 PCI: 00:12.0 cmd <- 02
1481 12:44:53.964665 PCI: 00:14.0 subsystem <- 8086/02ed
1482 12:44:53.964760 PCI: 00:14.0 cmd <- 02
1483 12:44:53.968378 PCI: 00:14.2 cmd <- 02
1484 12:44:53.971307 PCI: 00:14.3 subsystem <- 8086/02f0
1485 12:44:53.974723 PCI: 00:14.3 cmd <- 02
1486 12:44:53.978364 PCI: 00:15.0 subsystem <- 8086/02e8
1487 12:44:53.981416 PCI: 00:15.0 cmd <- 02
1488 12:44:53.984642 PCI: 00:15.1 subsystem <- 8086/02e9
1489 12:44:53.987938 PCI: 00:15.1 cmd <- 02
1490 12:44:53.991133 PCI: 00:16.0 subsystem <- 8086/02e0
1491 12:44:53.994957 PCI: 00:16.0 cmd <- 02
1492 12:44:53.998212 PCI: 00:17.0 subsystem <- 8086/02d3
1493 12:44:54.001264 PCI: 00:17.0 cmd <- 03
1494 12:44:54.004424 PCI: 00:19.0 subsystem <- 8086/02c5
1495 12:44:54.004524 PCI: 00:19.0 cmd <- 02
1496 12:44:54.008281 PCI: 00:1d.0 bridge ctrl <- 0013
1497 12:44:54.014767 PCI: 00:1d.0 subsystem <- 8086/02b0
1498 12:44:54.014867 PCI: 00:1d.0 cmd <- 06
1499 12:44:54.017964 PCI: 00:1e.0 subsystem <- 8086/02a8
1500 12:44:54.021171 PCI: 00:1e.0 cmd <- 06
1501 12:44:54.024435 PCI: 00:1e.2 subsystem <- 8086/02aa
1502 12:44:54.028168 PCI: 00:1e.2 cmd <- 06
1503 12:44:54.031249 PCI: 00:1e.3 subsystem <- 8086/02ab
1504 12:44:54.034440 PCI: 00:1e.3 cmd <- 02
1505 12:44:54.037577 PCI: 00:1f.0 subsystem <- 8086/0284
1506 12:44:54.040880 PCI: 00:1f.0 cmd <- 407
1507 12:44:54.044546 PCI: 00:1f.3 subsystem <- 8086/02c8
1508 12:44:54.047736 PCI: 00:1f.3 cmd <- 02
1509 12:44:54.050834 PCI: 00:1f.4 subsystem <- 8086/02a3
1510 12:44:54.054412 PCI: 00:1f.4 cmd <- 03
1511 12:44:54.057609 PCI: 00:1f.5 subsystem <- 8086/02a4
1512 12:44:54.060995 PCI: 00:1f.5 cmd <- 406
1513 12:44:54.068836 PCI: 01:00.0 cmd <- 02
1514 12:44:54.073563 done.
1515 12:44:54.086577 ME: Version: 14.0.39.1367
1516 12:44:54.093459 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 12
1517 12:44:54.096674 Initializing devices...
1518 12:44:54.096774 Root Device init ...
1519 12:44:54.103119 Chrome EC: Set SMI mask to 0x0000000000000000
1520 12:44:54.106301 Chrome EC: clear events_b mask to 0x0000000000000000
1521 12:44:54.113167 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1522 12:44:54.119680 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1523 12:44:54.126764 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1524 12:44:54.129880 Chrome EC: Set WAKE mask to 0x0000000000000000
1525 12:44:54.133112 Root Device init finished in 35177 usecs
1526 12:44:54.136822 CPU_CLUSTER: 0 init ...
1527 12:44:54.143302 CPU_CLUSTER: 0 init finished in 2447 usecs
1528 12:44:54.147653 PCI: 00:00.0 init ...
1529 12:44:54.150964 CPU TDP: 15 Watts
1530 12:44:54.154031 CPU PL2 = 64 Watts
1531 12:44:54.157163 PCI: 00:00.0 init finished in 7082 usecs
1532 12:44:54.160921 PCI: 00:02.0 init ...
1533 12:44:54.164117 PCI: 00:02.0 init finished in 2244 usecs
1534 12:44:54.166937 PCI: 00:08.0 init ...
1535 12:44:54.170547 PCI: 00:08.0 init finished in 2251 usecs
1536 12:44:54.173695 PCI: 00:12.0 init ...
1537 12:44:54.176825 PCI: 00:12.0 init finished in 2253 usecs
1538 12:44:54.180458 PCI: 00:14.0 init ...
1539 12:44:54.183874 PCI: 00:14.0 init finished in 2253 usecs
1540 12:44:54.186868 PCI: 00:14.2 init ...
1541 12:44:54.190381 PCI: 00:14.2 init finished in 2252 usecs
1542 12:44:54.193903 PCI: 00:14.3 init ...
1543 12:44:54.197182 PCI: 00:14.3 init finished in 2272 usecs
1544 12:44:54.200320 PCI: 00:15.0 init ...
1545 12:44:54.203520 DW I2C bus 0 at 0xd121f000 (400 KHz)
1546 12:44:54.206770 PCI: 00:15.0 init finished in 5970 usecs
1547 12:44:54.210628 PCI: 00:15.1 init ...
1548 12:44:54.213647 DW I2C bus 1 at 0xd1220000 (400 KHz)
1549 12:44:54.220065 PCI: 00:15.1 init finished in 5977 usecs
1550 12:44:54.220163 PCI: 00:16.0 init ...
1551 12:44:54.227051 PCI: 00:16.0 init finished in 2252 usecs
1552 12:44:54.229712 PCI: 00:19.0 init ...
1553 12:44:54.232945 DW I2C bus 4 at 0xd1222000 (400 KHz)
1554 12:44:54.236775 PCI: 00:19.0 init finished in 5976 usecs
1555 12:44:54.239947 PCI: 00:1d.0 init ...
1556 12:44:54.243296 Initializing PCH PCIe bridge.
1557 12:44:54.246427 PCI: 00:1d.0 init finished in 5285 usecs
1558 12:44:54.249575 PCI: 00:1f.0 init ...
1559 12:44:54.253349 IOAPIC: Initializing IOAPIC at 0xfec00000
1560 12:44:54.259746 IOAPIC: Bootstrap Processor Local APIC = 0x00
1561 12:44:54.259835 IOAPIC: ID = 0x02
1562 12:44:54.262875 IOAPIC: Dumping registers
1563 12:44:54.266181 reg 0x0000: 0x02000000
1564 12:44:54.269295 reg 0x0001: 0x00770020
1565 12:44:54.269382 reg 0x0002: 0x00000000
1566 12:44:54.276461 PCI: 00:1f.0 init finished in 23551 usecs
1567 12:44:54.279413 PCI: 00:1f.4 init ...
1568 12:44:54.282368 PCI: 00:1f.4 init finished in 2261 usecs
1569 12:44:54.293789 PCI: 01:00.0 init ...
1570 12:44:54.296819 PCI: 01:00.0 init finished in 2252 usecs
1571 12:44:54.301112 PNP: 0c09.0 init ...
1572 12:44:54.304643 Google Chrome EC uptime: 11.059 seconds
1573 12:44:54.311036 Google Chrome AP resets since EC boot: 0
1574 12:44:54.314224 Google Chrome most recent AP reset causes:
1575 12:44:54.321058 Google Chrome EC reset flags at last EC boot: reset-pin
1576 12:44:54.324287 PNP: 0c09.0 init finished in 20567 usecs
1577 12:44:54.327561 Devices initialized
1578 12:44:54.327659 Show all devs... After init.
1579 12:44:54.330764 Root Device: enabled 1
1580 12:44:54.334737 CPU_CLUSTER: 0: enabled 1
1581 12:44:54.337982 DOMAIN: 0000: enabled 1
1582 12:44:54.338084 APIC: 00: enabled 1
1583 12:44:54.341111 PCI: 00:00.0: enabled 1
1584 12:44:54.344338 PCI: 00:02.0: enabled 1
1585 12:44:54.347441 PCI: 00:04.0: enabled 0
1586 12:44:54.347539 PCI: 00:05.0: enabled 0
1587 12:44:54.350653 PCI: 00:12.0: enabled 1
1588 12:44:54.354443 PCI: 00:12.5: enabled 0
1589 12:44:54.354540 PCI: 00:12.6: enabled 0
1590 12:44:54.357681 PCI: 00:14.0: enabled 1
1591 12:44:54.360866 PCI: 00:14.1: enabled 0
1592 12:44:54.363931 PCI: 00:14.3: enabled 1
1593 12:44:54.364029 PCI: 00:14.5: enabled 0
1594 12:44:54.367303 PCI: 00:15.0: enabled 1
1595 12:44:54.371110 PCI: 00:15.1: enabled 1
1596 12:44:54.374223 PCI: 00:15.2: enabled 0
1597 12:44:54.374320 PCI: 00:15.3: enabled 0
1598 12:44:54.377535 PCI: 00:16.0: enabled 1
1599 12:44:54.380847 PCI: 00:16.1: enabled 0
1600 12:44:54.384031 PCI: 00:16.2: enabled 0
1601 12:44:54.384129 PCI: 00:16.3: enabled 0
1602 12:44:54.387111 PCI: 00:16.4: enabled 0
1603 12:44:54.390763 PCI: 00:16.5: enabled 0
1604 12:44:54.393964 PCI: 00:17.0: enabled 1
1605 12:44:54.394063 PCI: 00:19.0: enabled 1
1606 12:44:54.396975 PCI: 00:19.1: enabled 0
1607 12:44:54.400623 PCI: 00:19.2: enabled 0
1608 12:44:54.400710 PCI: 00:1a.0: enabled 0
1609 12:44:54.403626 PCI: 00:1c.0: enabled 0
1610 12:44:54.407184 PCI: 00:1c.1: enabled 0
1611 12:44:54.410097 PCI: 00:1c.2: enabled 0
1612 12:44:54.410188 PCI: 00:1c.3: enabled 0
1613 12:44:54.413801 PCI: 00:1c.4: enabled 0
1614 12:44:54.416945 PCI: 00:1c.5: enabled 0
1615 12:44:54.420675 PCI: 00:1c.6: enabled 0
1616 12:44:54.420764 PCI: 00:1c.7: enabled 0
1617 12:44:54.423662 PCI: 00:1d.0: enabled 1
1618 12:44:54.426774 PCI: 00:1d.1: enabled 0
1619 12:44:54.430044 PCI: 00:1d.2: enabled 0
1620 12:44:54.430131 PCI: 00:1d.3: enabled 0
1621 12:44:54.433934 PCI: 00:1d.4: enabled 0
1622 12:44:54.437289 PCI: 00:1d.5: enabled 0
1623 12:44:54.437378 PCI: 00:1e.0: enabled 1
1624 12:44:54.440500 PCI: 00:1e.1: enabled 0
1625 12:44:54.443867 PCI: 00:1e.2: enabled 1
1626 12:44:54.446942 PCI: 00:1e.3: enabled 1
1627 12:44:54.447027 PCI: 00:1f.0: enabled 1
1628 12:44:54.450063 PCI: 00:1f.1: enabled 0
1629 12:44:54.453401 PCI: 00:1f.2: enabled 0
1630 12:44:54.456576 PCI: 00:1f.3: enabled 1
1631 12:44:54.456663 PCI: 00:1f.4: enabled 1
1632 12:44:54.459697 PCI: 00:1f.5: enabled 1
1633 12:44:54.462971 PCI: 00:1f.6: enabled 0
1634 12:44:54.466751 USB0 port 0: enabled 1
1635 12:44:54.466834 I2C: 01:15: enabled 1
1636 12:44:54.469951 I2C: 02:5d: enabled 1
1637 12:44:54.473021 GENERIC: 0.0: enabled 1
1638 12:44:54.473104 I2C: 03:1a: enabled 1
1639 12:44:54.476239 I2C: 03:38: enabled 1
1640 12:44:54.479529 I2C: 03:39: enabled 1
1641 12:44:54.479613 I2C: 03:3a: enabled 1
1642 12:44:54.482803 I2C: 03:3b: enabled 1
1643 12:44:54.486690 PCI: 00:00.0: enabled 1
1644 12:44:54.486771 SPI: 00: enabled 1
1645 12:44:54.489721 SPI: 01: enabled 1
1646 12:44:54.492798 PNP: 0c09.0: enabled 1
1647 12:44:54.492882 USB2 port 0: enabled 1
1648 12:44:54.496377 USB2 port 1: enabled 1
1649 12:44:54.499380 USB2 port 2: enabled 0
1650 12:44:54.499474 USB2 port 3: enabled 0
1651 12:44:54.503111 USB2 port 5: enabled 0
1652 12:44:54.506078 USB2 port 6: enabled 1
1653 12:44:54.509213 USB2 port 9: enabled 1
1654 12:44:54.509300 USB3 port 0: enabled 1
1655 12:44:54.512737 USB3 port 1: enabled 1
1656 12:44:54.515926 USB3 port 2: enabled 1
1657 12:44:54.516013 USB3 port 3: enabled 1
1658 12:44:54.519912 USB3 port 4: enabled 0
1659 12:44:54.522960 APIC: 05: enabled 1
1660 12:44:54.523046 APIC: 04: enabled 1
1661 12:44:54.526088 APIC: 01: enabled 1
1662 12:44:54.529675 APIC: 03: enabled 1
1663 12:44:54.529774 APIC: 07: enabled 1
1664 12:44:54.533085 APIC: 02: enabled 1
1665 12:44:54.533184 APIC: 06: enabled 1
1666 12:44:54.536206 PCI: 00:08.0: enabled 1
1667 12:44:54.539429 PCI: 00:14.2: enabled 1
1668 12:44:54.542571 PCI: 01:00.0: enabled 1
1669 12:44:54.545834 Disabling ACPI via APMC:
1670 12:44:54.545933 done.
1671 12:44:54.552955 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1672 12:44:54.556211 ELOG: NV offset 0xaf0000 size 0x4000
1673 12:44:54.562641 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1674 12:44:54.569612 ELOG: Event(17) added with size 13 at 2023-03-22 12:44:53 UTC
1675 12:44:54.575896 ELOG: Event(92) added with size 9 at 2023-03-22 12:44:53 UTC
1676 12:44:54.582363 ELOG: Event(93) added with size 9 at 2023-03-22 12:44:53 UTC
1677 12:44:54.589556 ELOG: Event(9A) added with size 9 at 2023-03-22 12:44:53 UTC
1678 12:44:54.595882 ELOG: Event(9E) added with size 10 at 2023-03-22 12:44:53 UTC
1679 12:44:54.602437 ELOG: Event(9F) added with size 14 at 2023-03-22 12:44:53 UTC
1680 12:44:54.606002 BS: BS_DEV_INIT times (ms): entry 0 run 27 exit 6
1681 12:44:54.613421 ELOG: Event(A1) added with size 10 at 2023-03-22 12:44:53 UTC
1682 12:44:54.623051 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1683 12:44:54.629908 ELOG: Event(A0) added with size 9 at 2023-03-22 12:44:53 UTC
1684 12:44:54.633208 elog_add_boot_reason: Logged dev mode boot
1685 12:44:54.636357 Finalize devices...
1686 12:44:54.636459 PCI: 00:17.0 final
1687 12:44:54.639487 Devices finalized
1688 12:44:54.642654 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1689 12:44:54.649098 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1690 12:44:54.652916 ME: HFSTS1 : 0x90000245
1691 12:44:54.656134 ME: HFSTS2 : 0x3B850126
1692 12:44:54.662588 ME: HFSTS3 : 0x00000020
1693 12:44:54.665720 ME: HFSTS4 : 0x00004800
1694 12:44:54.668925 ME: HFSTS5 : 0x00000000
1695 12:44:54.672807 ME: HFSTS6 : 0x40400006
1696 12:44:54.676077 ME: Manufacturing Mode : NO
1697 12:44:54.679047 ME: FW Partition Table : OK
1698 12:44:54.682181 ME: Bringup Loader Failure : NO
1699 12:44:54.685437 ME: Firmware Init Complete : YES
1700 12:44:54.689291 ME: Boot Options Present : NO
1701 12:44:54.692520 ME: Update In Progress : NO
1702 12:44:54.695680 ME: D0i3 Support : YES
1703 12:44:54.698822 ME: Low Power State Enabled : NO
1704 12:44:54.702001 ME: CPU Replaced : NO
1705 12:44:54.705360 ME: CPU Replacement Valid : YES
1706 12:44:54.708954 ME: Current Working State : 5
1707 12:44:54.711991 ME: Current Operation State : 1
1708 12:44:54.715665 ME: Current Operation Mode : 0
1709 12:44:54.718800 ME: Error Code : 0
1710 12:44:54.722325 ME: CPU Debug Disabled : YES
1711 12:44:54.725409 ME: TXT Support : NO
1712 12:44:54.732034 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1713 12:44:54.738802 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1714 12:44:54.738903 CBFS @ c08000 size 3f8000
1715 12:44:54.745152 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1716 12:44:54.748345 CBFS: Locating 'fallback/dsdt.aml'
1717 12:44:54.751762 CBFS: Found @ offset 10bb80 size 3fa5
1718 12:44:54.758504 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1719 12:44:54.761793 CBFS @ c08000 size 3f8000
1720 12:44:54.768182 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1721 12:44:54.768276 CBFS: Locating 'fallback/slic'
1722 12:44:54.773318 CBFS: 'fallback/slic' not found.
1723 12:44:54.780302 ACPI: Writing ACPI tables at 99b3e000.
1724 12:44:54.780395 ACPI: * FACS
1725 12:44:54.783386 ACPI: * DSDT
1726 12:44:54.786693 Ramoops buffer: 0x100000@0x99a3d000.
1727 12:44:54.790152 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1728 12:44:54.796576 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1729 12:44:54.799804 Google Chrome EC: version:
1730 12:44:54.803648 ro: helios_v2.0.2659-56403530b
1731 12:44:54.806853 rw: helios_v2.0.2849-c41de27e7d
1732 12:44:54.806940 running image: 1
1733 12:44:54.810599 ACPI: * FADT
1734 12:44:54.810690 SCI is IRQ9
1735 12:44:54.817256 ACPI: added table 1/32, length now 40
1736 12:44:54.817354 ACPI: * SSDT
1737 12:44:54.820977 Found 1 CPU(s) with 8 core(s) each.
1738 12:44:54.824004 Error: Could not locate 'wifi_sar' in VPD.
1739 12:44:54.830699 Checking CBFS for default SAR values
1740 12:44:54.833691 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1741 12:44:54.837329 CBFS @ c08000 size 3f8000
1742 12:44:54.843976 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1743 12:44:54.846985 CBFS: Locating 'wifi_sar_defaults.hex'
1744 12:44:54.850635 CBFS: Found @ offset 5fac0 size 77
1745 12:44:54.854370 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1746 12:44:54.860290 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1747 12:44:54.864003 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1748 12:44:54.870418 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1749 12:44:54.873585 failed to find key in VPD: dsm_calib_r0_0
1750 12:44:54.883785 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1751 12:44:54.887001 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1752 12:44:54.890266 failed to find key in VPD: dsm_calib_r0_1
1753 12:44:54.900148 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1754 12:44:54.906714 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1755 12:44:54.909846 failed to find key in VPD: dsm_calib_r0_2
1756 12:44:54.919829 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1757 12:44:54.922878 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1758 12:44:54.929619 failed to find key in VPD: dsm_calib_r0_3
1759 12:44:54.936465 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1760 12:44:54.942935 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1761 12:44:54.946123 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1762 12:44:54.953082 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1763 12:44:54.956604 EC returned error result code 1
1764 12:44:54.960289 EC returned error result code 1
1765 12:44:54.963530 EC returned error result code 1
1766 12:44:54.966749 PS2K: Bad resp from EC. Vivaldi disabled!
1767 12:44:54.973835 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1768 12:44:54.980344 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1769 12:44:54.983468 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1770 12:44:54.990390 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1771 12:44:54.993609 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1772 12:44:55.000062 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1773 12:44:55.006614 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1774 12:44:55.013009 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1775 12:44:55.016225 ACPI: added table 2/32, length now 44
1776 12:44:55.016326 ACPI: * MCFG
1777 12:44:55.023216 ACPI: added table 3/32, length now 48
1778 12:44:55.023318 ACPI: * TPM2
1779 12:44:55.026191 TPM2 log created at 99a2d000
1780 12:44:55.029767 ACPI: added table 4/32, length now 52
1781 12:44:55.032898 ACPI: * MADT
1782 12:44:55.032998 SCI is IRQ9
1783 12:44:55.036499 ACPI: added table 5/32, length now 56
1784 12:44:55.039612 current = 99b43ac0
1785 12:44:55.039712 ACPI: * DMAR
1786 12:44:55.043096 ACPI: added table 6/32, length now 60
1787 12:44:55.046197 ACPI: * IGD OpRegion
1788 12:44:55.049854 GMA: Found VBT in CBFS
1789 12:44:55.052780 GMA: Found valid VBT in CBFS
1790 12:44:55.056468 ACPI: added table 7/32, length now 64
1791 12:44:55.056570 ACPI: * HPET
1792 12:44:55.059551 ACPI: added table 8/32, length now 68
1793 12:44:55.063161 ACPI: done.
1794 12:44:55.066282 ACPI tables: 31744 bytes.
1795 12:44:55.069984 smbios_write_tables: 99a2c000
1796 12:44:55.073028 EC returned error result code 3
1797 12:44:55.076271 Couldn't obtain OEM name from CBI
1798 12:44:55.079643 Create SMBIOS type 17
1799 12:44:55.082864 PCI: 00:00.0 (Intel Cannonlake)
1800 12:44:55.082958 PCI: 00:14.3 (Intel WiFi)
1801 12:44:55.085998 SMBIOS tables: 939 bytes.
1802 12:44:55.089191 Writing table forward entry at 0x00000500
1803 12:44:55.095714 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1804 12:44:55.099006 Writing coreboot table at 0x99b62000
1805 12:44:55.105575 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1806 12:44:55.108835 1. 0000000000001000-000000000009ffff: RAM
1807 12:44:55.116034 2. 00000000000a0000-00000000000fffff: RESERVED
1808 12:44:55.119107 3. 0000000000100000-0000000099a2bfff: RAM
1809 12:44:55.125657 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1810 12:44:55.128863 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1811 12:44:55.135653 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1812 12:44:55.141861 7. 000000009a000000-000000009f7fffff: RESERVED
1813 12:44:55.145602 8. 00000000e0000000-00000000efffffff: RESERVED
1814 12:44:55.151795 9. 00000000fc000000-00000000fc000fff: RESERVED
1815 12:44:55.155437 10. 00000000fe000000-00000000fe00ffff: RESERVED
1816 12:44:55.158467 11. 00000000fed10000-00000000fed17fff: RESERVED
1817 12:44:55.165223 12. 00000000fed80000-00000000fed83fff: RESERVED
1818 12:44:55.168718 13. 00000000fed90000-00000000fed91fff: RESERVED
1819 12:44:55.175026 14. 00000000feda0000-00000000feda1fff: RESERVED
1820 12:44:55.178637 15. 0000000100000000-000000045e7fffff: RAM
1821 12:44:55.181814 Graphics framebuffer located at 0xc0000000
1822 12:44:55.185030 Passing 5 GPIOs to payload:
1823 12:44:55.191826 NAME | PORT | POLARITY | VALUE
1824 12:44:55.195130 write protect | undefined | high | low
1825 12:44:55.201733 lid | undefined | high | high
1826 12:44:55.208288 power | undefined | high | low
1827 12:44:55.211538 oprom | undefined | high | low
1828 12:44:55.218066 EC in RW | 0x000000cb | high | low
1829 12:44:55.218164 Board ID: 4
1830 12:44:55.224547 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1831 12:44:55.224645 CBFS @ c08000 size 3f8000
1832 12:44:55.231376 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1833 12:44:55.237816 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6264
1834 12:44:55.241117 coreboot table: 1492 bytes.
1835 12:44:55.244810 IMD ROOT 0. 99fff000 00001000
1836 12:44:55.247761 IMD SMALL 1. 99ffe000 00001000
1837 12:44:55.251337 FSP MEMORY 2. 99c4e000 003b0000
1838 12:44:55.254393 CONSOLE 3. 99c2e000 00020000
1839 12:44:55.258128 FMAP 4. 99c2d000 0000054e
1840 12:44:55.261217 TIME STAMP 5. 99c2c000 00000910
1841 12:44:55.264225 VBOOT WORK 6. 99c18000 00014000
1842 12:44:55.267894 MRC DATA 7. 99c16000 00001958
1843 12:44:55.270980 ROMSTG STCK 8. 99c15000 00001000
1844 12:44:55.274640 AFTER CAR 9. 99c0b000 0000a000
1845 12:44:55.277727 RAMSTAGE 10. 99baf000 0005c000
1846 12:44:55.281271 REFCODE 11. 99b7a000 00035000
1847 12:44:55.285055 SMM BACKUP 12. 99b6a000 00010000
1848 12:44:55.287638 COREBOOT 13. 99b62000 00008000
1849 12:44:55.290684 ACPI 14. 99b3e000 00024000
1850 12:44:55.294471 ACPI GNVS 15. 99b3d000 00001000
1851 12:44:55.297792 RAMOOPS 16. 99a3d000 00100000
1852 12:44:55.301012 TPM2 TCGLOG17. 99a2d000 00010000
1853 12:44:55.304234 SMBIOS 18. 99a2c000 00000800
1854 12:44:55.307643 IMD small region:
1855 12:44:55.310849 IMD ROOT 0. 99ffec00 00000400
1856 12:44:55.314152 FSP RUNTIME 1. 99ffebe0 00000004
1857 12:44:55.317430 EC HOSTEVENT 2. 99ffebc0 00000008
1858 12:44:55.320749 POWER STATE 3. 99ffeb80 00000040
1859 12:44:55.323868 ROMSTAGE 4. 99ffeb60 00000004
1860 12:44:55.327026 MEM INFO 5. 99ffe9a0 000001b9
1861 12:44:55.330318 VPD 6. 99ffe920 0000006c
1862 12:44:55.334225 MTRR: Physical address space:
1863 12:44:55.340633 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1864 12:44:55.347243 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1865 12:44:55.353643 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1866 12:44:55.360370 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1867 12:44:55.363859 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1868 12:44:55.370150 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1869 12:44:55.376777 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1870 12:44:55.380363 MTRR: Fixed MSR 0x250 0x0606060606060606
1871 12:44:55.386491 MTRR: Fixed MSR 0x258 0x0606060606060606
1872 12:44:55.390104 MTRR: Fixed MSR 0x259 0x0000000000000000
1873 12:44:55.393071 MTRR: Fixed MSR 0x268 0x0606060606060606
1874 12:44:55.396702 MTRR: Fixed MSR 0x269 0x0606060606060606
1875 12:44:55.403100 MTRR: Fixed MSR 0x26a 0x0606060606060606
1876 12:44:55.406450 MTRR: Fixed MSR 0x26b 0x0606060606060606
1877 12:44:55.409687 MTRR: Fixed MSR 0x26c 0x0606060606060606
1878 12:44:55.413030 MTRR: Fixed MSR 0x26d 0x0606060606060606
1879 12:44:55.419683 MTRR: Fixed MSR 0x26e 0x0606060606060606
1880 12:44:55.422878 MTRR: Fixed MSR 0x26f 0x0606060606060606
1881 12:44:55.426093 call enable_fixed_mtrr()
1882 12:44:55.429362 CPU physical address size: 39 bits
1883 12:44:55.433185 MTRR: default type WB/UC MTRR counts: 6/8.
1884 12:44:55.436446 MTRR: WB selected as default type.
1885 12:44:55.442783 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1886 12:44:55.449233 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1887 12:44:55.456316 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1888 12:44:55.462858 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1889 12:44:55.469031 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1890 12:44:55.475628 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1891 12:44:55.479305 MTRR: Fixed MSR 0x250 0x0606060606060606
1892 12:44:55.482459 MTRR: Fixed MSR 0x258 0x0606060606060606
1893 12:44:55.489221 MTRR: Fixed MSR 0x259 0x0000000000000000
1894 12:44:55.492047 MTRR: Fixed MSR 0x268 0x0606060606060606
1895 12:44:55.495720 MTRR: Fixed MSR 0x269 0x0606060606060606
1896 12:44:55.498789 MTRR: Fixed MSR 0x26a 0x0606060606060606
1897 12:44:55.505412 MTRR: Fixed MSR 0x26b 0x0606060606060606
1898 12:44:55.508870 MTRR: Fixed MSR 0x26c 0x0606060606060606
1899 12:44:55.512367 MTRR: Fixed MSR 0x26d 0x0606060606060606
1900 12:44:55.515491 MTRR: Fixed MSR 0x26e 0x0606060606060606
1901 12:44:55.518887 MTRR: Fixed MSR 0x26f 0x0606060606060606
1902 12:44:55.522019
1903 12:44:55.522116 MTRR check
1904 12:44:55.525206 call enable_fixed_mtrr()
1905 12:44:55.528517 Fixed MTRRs : Enabled
1906 12:44:55.528616 Variable MTRRs: Enabled
1907 12:44:55.528694
1908 12:44:55.531913 CPU physical address size: 39 bits
1909 12:44:55.538457 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1910 12:44:55.541711 MTRR: Fixed MSR 0x250 0x0606060606060606
1911 12:44:55.548212 MTRR: Fixed MSR 0x250 0x0606060606060606
1912 12:44:55.551350 MTRR: Fixed MSR 0x258 0x0606060606060606
1913 12:44:55.555307 MTRR: Fixed MSR 0x259 0x0000000000000000
1914 12:44:55.558553 MTRR: Fixed MSR 0x268 0x0606060606060606
1915 12:44:55.565066 MTRR: Fixed MSR 0x269 0x0606060606060606
1916 12:44:55.568162 MTRR: Fixed MSR 0x26a 0x0606060606060606
1917 12:44:55.571933 MTRR: Fixed MSR 0x26b 0x0606060606060606
1918 12:44:55.575146 MTRR: Fixed MSR 0x26c 0x0606060606060606
1919 12:44:55.578274 MTRR: Fixed MSR 0x26d 0x0606060606060606
1920 12:44:55.584533 MTRR: Fixed MSR 0x26e 0x0606060606060606
1921 12:44:55.588157 MTRR: Fixed MSR 0x26f 0x0606060606060606
1922 12:44:55.591291 MTRR: Fixed MSR 0x258 0x0606060606060606
1923 12:44:55.594466 call enable_fixed_mtrr()
1924 12:44:55.598185 MTRR: Fixed MSR 0x259 0x0000000000000000
1925 12:44:55.604475 MTRR: Fixed MSR 0x268 0x0606060606060606
1926 12:44:55.608051 MTRR: Fixed MSR 0x269 0x0606060606060606
1927 12:44:55.611106 MTRR: Fixed MSR 0x26a 0x0606060606060606
1928 12:44:55.614943 MTRR: Fixed MSR 0x26b 0x0606060606060606
1929 12:44:55.618023 MTRR: Fixed MSR 0x26c 0x0606060606060606
1930 12:44:55.624545 MTRR: Fixed MSR 0x26d 0x0606060606060606
1931 12:44:55.627746 MTRR: Fixed MSR 0x26e 0x0606060606060606
1932 12:44:55.630902 MTRR: Fixed MSR 0x26f 0x0606060606060606
1933 12:44:55.634123 CPU physical address size: 39 bits
1934 12:44:55.637541 call enable_fixed_mtrr()
1935 12:44:55.640757 MTRR: Fixed MSR 0x250 0x0606060606060606
1936 12:44:55.647164 MTRR: Fixed MSR 0x250 0x0606060606060606
1937 12:44:55.651104 MTRR: Fixed MSR 0x258 0x0606060606060606
1938 12:44:55.654359 MTRR: Fixed MSR 0x259 0x0000000000000000
1939 12:44:55.657664 MTRR: Fixed MSR 0x268 0x0606060606060606
1940 12:44:55.664226 MTRR: Fixed MSR 0x269 0x0606060606060606
1941 12:44:55.667529 MTRR: Fixed MSR 0x26a 0x0606060606060606
1942 12:44:55.670701 MTRR: Fixed MSR 0x26b 0x0606060606060606
1943 12:44:55.673673 MTRR: Fixed MSR 0x26c 0x0606060606060606
1944 12:44:55.680619 MTRR: Fixed MSR 0x26d 0x0606060606060606
1945 12:44:55.683935 MTRR: Fixed MSR 0x26e 0x0606060606060606
1946 12:44:55.686972 MTRR: Fixed MSR 0x26f 0x0606060606060606
1947 12:44:55.690193 MTRR: Fixed MSR 0x258 0x0606060606060606
1948 12:44:55.694017 call enable_fixed_mtrr()
1949 12:44:55.697061 MTRR: Fixed MSR 0x259 0x0000000000000000
1950 12:44:55.703697 MTRR: Fixed MSR 0x268 0x0606060606060606
1951 12:44:55.706906 MTRR: Fixed MSR 0x269 0x0606060606060606
1952 12:44:55.709941 MTRR: Fixed MSR 0x26a 0x0606060606060606
1953 12:44:55.713605 MTRR: Fixed MSR 0x26b 0x0606060606060606
1954 12:44:55.719972 MTRR: Fixed MSR 0x26c 0x0606060606060606
1955 12:44:55.723755 MTRR: Fixed MSR 0x26d 0x0606060606060606
1956 12:44:55.726844 MTRR: Fixed MSR 0x26e 0x0606060606060606
1957 12:44:55.730134 MTRR: Fixed MSR 0x26f 0x0606060606060606
1958 12:44:55.733967 CPU physical address size: 39 bits
1959 12:44:55.737261 call enable_fixed_mtrr()
1960 12:44:55.740510 MTRR: Fixed MSR 0x250 0x0606060606060606
1961 12:44:55.746476 MTRR: Fixed MSR 0x250 0x0606060606060606
1962 12:44:55.749774 MTRR: Fixed MSR 0x258 0x0606060606060606
1963 12:44:55.753164 MTRR: Fixed MSR 0x259 0x0000000000000000
1964 12:44:55.757062 MTRR: Fixed MSR 0x268 0x0606060606060606
1965 12:44:55.763736 MTRR: Fixed MSR 0x269 0x0606060606060606
1966 12:44:55.766973 MTRR: Fixed MSR 0x26a 0x0606060606060606
1967 12:44:55.770225 MTRR: Fixed MSR 0x26b 0x0606060606060606
1968 12:44:55.773655 MTRR: Fixed MSR 0x26c 0x0606060606060606
1969 12:44:55.779655 MTRR: Fixed MSR 0x26d 0x0606060606060606
1970 12:44:55.783104 MTRR: Fixed MSR 0x26e 0x0606060606060606
1971 12:44:55.786272 MTRR: Fixed MSR 0x26f 0x0606060606060606
1972 12:44:55.789556 MTRR: Fixed MSR 0x258 0x0606060606060606
1973 12:44:55.793308 call enable_fixed_mtrr()
1974 12:44:55.796465 MTRR: Fixed MSR 0x259 0x0000000000000000
1975 12:44:55.802852 MTRR: Fixed MSR 0x268 0x0606060606060606
1976 12:44:55.806375 MTRR: Fixed MSR 0x269 0x0606060606060606
1977 12:44:55.809443 MTRR: Fixed MSR 0x26a 0x0606060606060606
1978 12:44:55.813101 MTRR: Fixed MSR 0x26b 0x0606060606060606
1979 12:44:55.819899 MTRR: Fixed MSR 0x26c 0x0606060606060606
1980 12:44:55.822933 MTRR: Fixed MSR 0x26d 0x0606060606060606
1981 12:44:55.826420 MTRR: Fixed MSR 0x26e 0x0606060606060606
1982 12:44:55.829491 MTRR: Fixed MSR 0x26f 0x0606060606060606
1983 12:44:55.833263 CPU physical address size: 39 bits
1984 12:44:55.836579 call enable_fixed_mtrr()
1985 12:44:55.839665 CPU physical address size: 39 bits
1986 12:44:55.842961 CPU physical address size: 39 bits
1987 12:44:55.846121 CPU physical address size: 39 bits
1988 12:44:55.852632 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1989 12:44:55.856017 CBFS @ c08000 size 3f8000
1990 12:44:55.859356 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1991 12:44:55.865903 CBFS: Locating 'fallback/payload'
1992 12:44:55.869238 CBFS: Found @ offset 1c96c0 size 3f798
1993 12:44:55.872485 Checking segment from ROM address 0xffdd16f8
1994 12:44:55.879591 Checking segment from ROM address 0xffdd1714
1995 12:44:55.882787 Loading segment from ROM address 0xffdd16f8
1996 12:44:55.885769 code (compression=0)
1997 12:44:55.892452 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1998 12:44:55.902347 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1999 12:44:55.905504 it's not compressed!
2000 12:44:55.996736 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
2001 12:44:56.003034 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
2002 12:44:56.006336 Loading segment from ROM address 0xffdd1714
2003 12:44:56.009512 Entry Point 0x30000000
2004 12:44:56.012784 Loaded segments
2005 12:44:56.018553 Finalizing chipset.
2006 12:44:56.021707 Finalizing SMM.
2007 12:44:56.025108 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 89 exit 5
2008 12:44:56.028617 mp_park_aps done after 0 msecs.
2009 12:44:56.035280 Jumping to boot code at 30000000(99b62000)
2010 12:44:56.041885 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
2011 12:44:56.041986
2012 12:44:56.042067
2013 12:44:56.042140
2014 12:44:56.045031 Starting depthcharge on Helios...
2015 12:44:56.045133
2016 12:44:56.045491 end: 2.2.3 depthcharge-start (duration 00:00:13) [common]
2017 12:44:56.045607 start: 2.2.4 bootloader-commands (timeout 00:04:42) [common]
2018 12:44:56.045705 Setting prompt string to ['hatch:']
2019 12:44:56.045798 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:42)
2020 12:44:56.054676 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2021 12:44:56.054787
2022 12:44:56.061721 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2023 12:44:56.061824
2024 12:44:56.068354 board_setup: Info: eMMC controller not present; skipping
2025 12:44:56.068454
2026 12:44:56.071601 New NVMe Controller 0x30053ac0 @ 00:1d:00
2027 12:44:56.071701
2028 12:44:56.078113 board_setup: Info: SDHCI controller not present; skipping
2029 12:44:56.078214
2030 12:44:56.084553 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
2031 12:44:56.084652
2032 12:44:56.084730 Wipe memory regions:
2033 12:44:56.084804
2034 12:44:56.087878 [0x00000000001000, 0x000000000a0000)
2035 12:44:56.087977
2036 12:44:56.091001 [0x00000000100000, 0x00000030000000)
2037 12:44:56.157695
2038 12:44:56.160729 [0x00000030657430, 0x00000099a2c000)
2039 12:44:56.307580
2040 12:44:56.310642 [0x00000100000000, 0x0000045e800000)
2041 12:44:57.767767
2042 12:44:57.767940 R8152: Initializing
2043 12:44:57.768023
2044 12:44:57.771032 Version 9 (ocp_data = 6010)
2045 12:44:57.775576
2046 12:44:57.775673 R8152: Done initializing
2047 12:44:57.775751
2048 12:44:57.778847 Adding net device
2049 12:44:58.261593
2050 12:44:58.261756 R8152: Initializing
2051 12:44:58.261837
2052 12:44:58.264589 Version 6 (ocp_data = 5c30)
2053 12:44:58.264686
2054 12:44:58.267910 R8152: Done initializing
2055 12:44:58.268006
2056 12:44:58.271035 net_add_device: Attemp to include the same device
2057 12:44:58.274952
2058 12:44:58.281578 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2059 12:44:58.281679
2060 12:44:58.281793
2061 12:44:58.281874
2062 12:44:58.282163 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2064 12:44:58.382959 hatch: tftpboot 192.168.201.1 9729676/tftp-deploy-618pfdcj/kernel/bzImage 9729676/tftp-deploy-618pfdcj/kernel/cmdline 9729676/tftp-deploy-618pfdcj/ramdisk/ramdisk.cpio.gz
2065 12:44:58.383141 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2066 12:44:58.383240 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:40)
2067 12:44:58.387305 tftpboot 192.168.201.1 9729676/tftp-deploy-618pfdcj/kernel/bzImoy-618pfdcj/kernel/cmdline 9729676/tftp-deploy-618pfdcj/ramdisk/ramdisk.cpio.gz
2068 12:44:58.387406
2069 12:44:58.387482 Waiting for link
2070 12:44:58.588417
2071 12:44:58.588573 done.
2072 12:44:58.588651
2073 12:44:58.588723 MAC: 00:24:32:50:1a:59
2074 12:44:58.588791
2075 12:44:58.591434 Sending DHCP discover... done.
2076 12:44:58.591533
2077 12:44:58.594578 Waiting for reply... done.
2078 12:44:58.594677
2079 12:44:58.597870 Sending DHCP request... done.
2080 12:44:58.597985
2081 12:44:58.601280 Waiting for reply... done.
2082 12:44:58.601371
2083 12:44:58.604343 My ip is 192.168.201.14
2084 12:44:58.604451
2085 12:44:58.607623 The DHCP server ip is 192.168.201.1
2086 12:44:58.607723
2087 12:44:58.610951 TFTP server IP predefined by user: 192.168.201.1
2088 12:44:58.611050
2089 12:44:58.618045 Bootfile predefined by user: 9729676/tftp-deploy-618pfdcj/kernel/bzImage
2090 12:44:58.618144
2091 12:44:58.621301 Sending tftp read request... done.
2092 12:44:58.624560
2093 12:44:58.627783 Waiting for the transfer...
2094 12:44:58.627890
2095 12:44:59.169584 00000000 ################################################################
2096 12:44:59.169738
2097 12:44:59.707857 00080000 ################################################################
2098 12:44:59.708025
2099 12:45:00.258045 00100000 ################################################################
2100 12:45:00.258223
2101 12:45:00.803438 00180000 ################################################################
2102 12:45:00.803608
2103 12:45:01.354904 00200000 ################################################################
2104 12:45:01.355052
2105 12:45:01.904548 00280000 ################################################################
2106 12:45:01.904707
2107 12:45:02.447003 00300000 ################################################################
2108 12:45:02.447164
2109 12:45:02.969721 00380000 ################################################################
2110 12:45:02.969880
2111 12:45:03.500436 00400000 ################################################################
2112 12:45:03.500618
2113 12:45:04.027397 00480000 ################################################################
2114 12:45:04.027552
2115 12:45:04.550801 00500000 ################################################################
2116 12:45:04.550963
2117 12:45:05.070539 00580000 ################################################################
2118 12:45:05.070691
2119 12:45:05.600212 00600000 ################################################################
2120 12:45:05.600365
2121 12:45:06.127519 00680000 ################################################################
2122 12:45:06.127671
2123 12:45:06.653507 00700000 ################################################################
2124 12:45:06.653664
2125 12:45:07.174738 00780000 ################################################################
2126 12:45:07.174901
2127 12:45:07.695810 00800000 ################################################################
2128 12:45:07.695966
2129 12:45:08.213656 00880000 ################################################################
2130 12:45:08.213826
2131 12:45:08.731107 00900000 ################################################################
2132 12:45:08.731279
2133 12:45:09.252806 00980000 ################################################################
2134 12:45:09.252962
2135 12:45:09.785044 00a00000 ################################################################
2136 12:45:09.785216
2137 12:45:10.317398 00a80000 ################################################################
2138 12:45:10.317558
2139 12:45:10.430597 00b00000 ############## done.
2140 12:45:10.430753
2141 12:45:10.433810 The bootfile was 11646080 bytes long.
2142 12:45:10.433906
2143 12:45:10.436976 Sending tftp read request... done.
2144 12:45:10.437085
2145 12:45:10.440530 Waiting for the transfer...
2146 12:45:10.440635
2147 12:45:10.957719 00000000 ################################################################
2148 12:45:10.957918
2149 12:45:11.474935 00080000 ################################################################
2150 12:45:11.475117
2151 12:45:11.992260 00100000 ################################################################
2152 12:45:11.992465
2153 12:45:12.514207 00180000 ################################################################
2154 12:45:12.514418
2155 12:45:13.034126 00200000 ################################################################
2156 12:45:13.034333
2157 12:45:13.567412 00280000 ################################################################
2158 12:45:13.567611
2159 12:45:14.109790 00300000 ################################################################
2160 12:45:14.109959
2161 12:45:14.650402 00380000 ################################################################
2162 12:45:14.650552
2163 12:45:15.184824 00400000 ################################################################
2164 12:45:15.184993
2165 12:45:15.720350 00480000 ################################################################
2166 12:45:15.720513
2167 12:45:16.255415 00500000 ################################################################
2168 12:45:16.255572
2169 12:45:16.661194 00580000 ################################################# done.
2170 12:45:16.661366
2171 12:45:16.664634 Sending tftp read request... done.
2172 12:45:16.664764
2173 12:45:16.668358 Waiting for the transfer...
2174 12:45:16.668503
2175 12:45:16.668609 00000000 # done.
2176 12:45:16.668706
2177 12:45:16.677990 Command line loaded dynamically from TFTP file: 9729676/tftp-deploy-618pfdcj/kernel/cmdline
2178 12:45:16.678155
2179 12:45:16.704333 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/9729676/extract-nfsrootfs-9ty6xpyx,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2180 12:45:16.704491
2181 12:45:16.710874 ec_init(0): CrosEC protocol v3 supported (256, 256)
2182 12:45:16.714955
2183 12:45:16.718247 Shutting down all USB controllers.
2184 12:45:16.718350
2185 12:45:16.718440 Removing current net device
2186 12:45:16.721560
2187 12:45:16.721661 Finalizing coreboot
2188 12:45:16.721742
2189 12:45:16.728135 Exiting depthcharge with code 4 at timestamp: 28025553
2190 12:45:16.728272
2191 12:45:16.728355
2192 12:45:16.728428 Starting kernel ...
2193 12:45:16.728499
2194 12:45:16.728913 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
2195 12:45:16.729036 start: 2.2.5 auto-login-action (timeout 00:04:21) [common]
2196 12:45:16.729134 Setting prompt string to ['Linux version [0-9]']
2197 12:45:16.729217 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2198 12:45:16.729298 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2199 12:45:16.731334
2201 12:49:37.729276 end: 2.2.5 auto-login-action (duration 00:04:21) [common]
2203 12:49:37.729522 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 261 seconds'
2205 12:49:37.729706 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2208 12:49:37.730008 end: 2 depthcharge-action (duration 00:05:00) [common]
2210 12:49:37.730261 Cleaning after the job
2211 12:49:37.730361 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/ramdisk
2212 12:49:37.730937 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/kernel
2213 12:49:37.731838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/nfsrootfs
2214 12:49:37.766207 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9729676/tftp-deploy-618pfdcj/modules
2215 12:49:37.766713 start: 5.1 power-off (timeout 00:00:30) [common]
2216 12:49:37.766902 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-4' '--port=1' '--command=off'
2217 12:49:37.842532 >> Command sent successfully.
2218 12:49:37.845037 Returned 0 in 0 seconds
2219 12:49:37.945836 end: 5.1 power-off (duration 00:00:00) [common]
2221 12:49:37.946193 start: 5.2 read-feedback (timeout 00:10:00) [common]
2222 12:49:37.946462 Listened to connection for namespace 'common' for up to 1s
2224 12:49:37.946885 Listened to connection for namespace 'common' for up to 1s
2225 12:49:38.951159 Finalising connection for namespace 'common'
2226 12:49:38.951340 Disconnecting from shell: Finalise
2227 12:49:38.951435
2228 12:49:39.052166 end: 5.2 read-feedback (duration 00:00:01) [common]
2229 12:49:39.052341 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9729676
2230 12:49:39.156675 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9729676
2231 12:49:39.156871 JobError: Your job cannot terminate cleanly.