[Enter `^Ec?' for help] coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 bootblock starting (log level: 8)... CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz CPU: ID 906c0, Jasperlake A0, ucode: 2400001f CPU: AES supported, TXT NOT supported, VT supported MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1 PCH: device id 4d87 (rev 01) is Jasperlake Super IGD: device id 4e55 (rev 01) is Jasperlake GT4 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0xc04000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 32 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fallback/verstage' @0xfa740 size 0x155ec coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 verstage starting (log level: 8)... Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: area GBB found @ c05000 (12288 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fallback/romstage' @0x80 size 0x1bde4 BS: verstage times (exec / console): total (unknown) / 124 ms coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 romstage starting (log level: 8)... VB2:vb2api_ec_sync() In recovery mode, skipping EC sync pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00080000 gpe0_en[3]: 00010000 TCO_STS: 0000 0001 GEN_PMCON: d0015038 00002200 GBLRST_CAUSE: 00000000 00000000 prev_sleep_state 5 Boot Count incremented to 6745 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fspm.bin' @0x44fc0 size 0x79000 Chrome EC: UHEPI supported FMAP: area RECOVERY_MRC_CACHE found @ bca000 (65536 bytes) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Initialized TPM device CR50 revision 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 MRC: Hash idx 0x100b comparison successful. MRC cache found, size 5458 bootmode is set to: 2 SPD INDEX = 0 CBFS: Found 'spd.bin' @0x40c40 size 0x600 SPD: module type is LPDDR4X SPD: module part number is MT53E512M32D2NP-046 WT:E SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb SPD: device width 16 bits, bus width 32 bits SPD: module size is 4096 MB (per channel) meminit_channels: DRAM half-populated CBMEM: IMD: root @ 0x76fff000 254 entries. IMD: root @ 0x76ffec00 62 entries. FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ bfc000 (8192 bytes) External stage cache: IMD: root @ 0x7b3ff000 254 entries. IMD: root @ 0x7b3fec00 62 entries. FMAP: area RECOVERY_MRC_CACHE found @ bca000 (65536 bytes) MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'. SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 MRC: 'RECOVERY_MRC_CACHE' does not need update. cse_lite: Skip switching to RW in the recovery path 1 DIMMs found SMM Memory Map SMRAM : 0x7b000000 0x800000 Subregion 0: 0x7b000000 0x200000 Subregion 1: 0x7b200000 0x200000 Subregion 2: 0x7b400000 0x400000 top_of_ram = 0x77000000 MTRR Range: Start=76000000 End=77000000 (Size 1000000) MTRR Range: Start=7b000000 End=7b800000 (Size 800000) MTRR Range: Start=ff000000 End=0 (Size 1000000) CBFS: Found 'fallback/postcar' @0xf5940 size 0x4d9c Decompressing stage fallback/postcar @ 0x76c0dfc0 (36304 bytes) Loading module at 0x76c0e000 with entry 0x76c0e000. filesize: 0x4a50 memsize: 0x8d90 Processing 188 relocs. Offset value of 0x74c0e000 BS: romstage times (exec / console): total (unknown) / 255 ms coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 postcar starting (log level: 8)... FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fallback/ramstage' @0x20f80 size 0x1f488 Decompressing stage fallback/ramstage @ 0x76ba7fc0 (413104 bytes) Loading module at 0x76ba8000 with entry 0x76ba8000. filesize: 0x4ec20 memsize: 0x64d70 Processing 4805 relocs. Offset value of 0x75da8000 BS: postcar times (exec / console): total (unknown) / 42 ms coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 ramstage starting (log level: 8)... Normal boot EC returned error result code 3 FW_CONFIG value is 0x204 GENERIC: 0.0 disabled by fw_config fw_config match found: TS_SOURCE=TS_UNPROVISIONED I2C: 00:10 disabled by fw_config I2C: 00:10 disabled by fw_config fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: CAMERA_WFC=CAMERA_UNPROVISIONED I2C: 00:10 disabled by fw_config fw_config match found: CAMERA_VCM=CAMERA_VCM_UNPROVISIONED fw_config match found: AUDIO_CODEC_SOURCE=AUDIO_CODEC_UNPROVISIONED I2C: 00:1a disabled by fw_config I2C: 00:1a disabled by fw_config fw_config match found: AUDIO_AMP=UNPROVISIONED fw_config match found: AUDIO_AMP=UNPROVISIONED GENERIC: 0.0 disabled by fw_config FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'cpu_microcode_blob.bin' @0x1bf00 size 0x5000 microcode: sig=0x906c0 pf=0x1 revision=0x2400001f microcode: Update skipped, already up-to-date CBFS: Found 'fsps.bin' @0xbefc0 size 0x36906 Detected 2 core, 2 thread CPU. Setting up SMI for CPU IED base = 0x7b400000 IED size = 0x00400000 Will perform SMM setup. CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. AP: slot 1 apic_id 2. Waiting for 2nd SIPI to complete...done. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 Unable to locate Global NVS SMM Module: stub loaded at 0x00038000. Will call 0x76bc5fe2(0x00000000) Installing permanent SMM handler to 0x7b000000 Loading module at 0x7b010000 with entry 0x7b010a91. filesize: 0xba48 memsize: 0x10b10 Processing 704 relocs. Offset value of 0x7b010000 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x7b008000 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd Unable to locate Global NVS SMM Module: stub loaded at 0x7b008000. Will call 0x7b010a91(0x00000000) Clearing SMI status registers SMI_STS: PM1 PM1_STS: PWRBTN TCO_STS: INTRD_DET GPE0 STD STS: smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0 In relocation handler: CPU 0 New SMBASE=0x7b000000 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1 In relocation handler: CPU 1 New SMBASE=0x7afffc00 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 906c0 CPU: family 06, model 9c, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is available and visible microcode: Update skipped, already up-to-date CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device 906c0 CPU: family 06, model 9c, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x02 done. microcode: Update skipped, already up-to-date CPU #1 initialized bsp_do_flight_plan done after 175 msecs. CPU: frequency set to 2800 MHz Enabling SMIs. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 86 / 289 ms Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_B:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Initialized TPM device CR50 revision 0 CBFS: Found 'vbt.bin' @0x445c0 size 0x4bc Found a VBT of 7680 bytes after decompression WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called Detected 2 core, 2 thread CPU. Detected 2 core, 2 thread CPU. Display FSP Version Info HOB Reference Code - CPU = 8.7.22.30 uCode Version = 24.0.0.1f TXT ACM version = ff.ff.ff.ffff Reference Code - ME = 8.7.22.30 MEBx version = 0.0.0.0 ME Firmware Version = Consumer SKU Reference Code - PCH = 8.7.22.30 PCH-CRID Status = Disabled PCH-CRID Original Value = ff.ff.ff.ffff PCH-CRID New Value = ff.ff.ff.ffff OPROM - RST - RAID = ff.ff.ff.ffff PCH Hsio Version = 4.0.0.0 Reference Code - SA - System Agent = 8.7.22.30 Reference Code - MRC = 0.0.4.68 SA - PCIe Version = 8.7.22.30 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.0 SA-CRID New Value = 0.0.0.0 OPROM - VBIOS = ff.ff.ff.ffff IO Manageability Engine FW Version = ff.ff.ff.ffff PHY Build Version = ff.ff.ff.ffff Thunderbolt(TM) FW Version = ff.ff.ff.ffff System Agent Manageability Engine F