Boot log: mt8192-asurada-spherion-r0

    1 16:42:56.739066  lava-dispatcher, installed at version: 2023.03
    2 16:42:56.739306  start: 0 validate
    3 16:42:56.739449  Start time: 2023-06-03 16:42:56.739442+00:00 (UTC)
    4 16:42:56.739584  Using caching service: 'http://localhost/cache/?uri=%s'
    5 16:42:56.739719  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
    6 16:42:57.031701  Using caching service: 'http://localhost/cache/?uri=%s'
    7 16:42:57.031944  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 16:42:57.333043  Using caching service: 'http://localhost/cache/?uri=%s'
    9 16:42:57.333241  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 16:43:18.577370  Using caching service: 'http://localhost/cache/?uri=%s'
   11 16:43:18.577597  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 16:43:19.144466  validate duration: 22.41
   14 16:43:19.144770  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 16:43:19.144880  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 16:43:19.144984  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 16:43:19.145114  Not decompressing ramdisk as can be used compressed.
   18 16:43:19.145229  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
   19 16:43:19.145330  saving as /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/ramdisk/rootfs.cpio.gz
   20 16:43:19.145431  total size: 34405874 (32MB)
   21 16:43:21.751992  progress   0% (0MB)
   22 16:43:21.760896  progress   5% (1MB)
   23 16:43:21.769599  progress  10% (3MB)
   24 16:43:21.778482  progress  15% (4MB)
   25 16:43:21.787256  progress  20% (6MB)
   26 16:43:21.796073  progress  25% (8MB)
   27 16:43:21.804652  progress  30% (9MB)
   28 16:43:21.813505  progress  35% (11MB)
   29 16:43:21.822284  progress  40% (13MB)
   30 16:43:21.831211  progress  45% (14MB)
   31 16:43:21.839975  progress  50% (16MB)
   32 16:43:21.848878  progress  55% (18MB)
   33 16:43:21.857530  progress  60% (19MB)
   34 16:43:21.866380  progress  65% (21MB)
   35 16:43:21.875118  progress  70% (22MB)
   36 16:43:21.884102  progress  75% (24MB)
   37 16:43:21.892755  progress  80% (26MB)
   38 16:43:21.901487  progress  85% (27MB)
   39 16:43:21.910098  progress  90% (29MB)
   40 16:43:21.918810  progress  95% (31MB)
   41 16:43:21.927403  progress 100% (32MB)
   42 16:43:21.927685  32MB downloaded in 2.78s (11.79MB/s)
   43 16:43:21.927857  end: 1.1.1 http-download (duration 00:00:03) [common]
   45 16:43:21.928205  end: 1.1 download-retry (duration 00:00:03) [common]
   46 16:43:21.928308  start: 1.2 download-retry (timeout 00:09:57) [common]
   47 16:43:21.928420  start: 1.2.1 http-download (timeout 00:09:57) [common]
   48 16:43:21.928561  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 16:43:21.928639  saving as /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/kernel/Image
   50 16:43:21.928721  total size: 45746688 (43MB)
   51 16:43:21.928831  No compression specified
   52 16:43:22.221638  progress   0% (0MB)
   53 16:43:22.233304  progress   5% (2MB)
   54 16:43:22.244816  progress  10% (4MB)
   55 16:43:22.256683  progress  15% (6MB)
   56 16:43:22.268483  progress  20% (8MB)
   57 16:43:22.280210  progress  25% (10MB)
   58 16:43:22.291856  progress  30% (13MB)
   59 16:43:22.303488  progress  35% (15MB)
   60 16:43:22.315062  progress  40% (17MB)
   61 16:43:22.326613  progress  45% (19MB)
   62 16:43:22.338218  progress  50% (21MB)
   63 16:43:22.349950  progress  55% (24MB)
   64 16:43:22.361671  progress  60% (26MB)
   65 16:43:22.373333  progress  65% (28MB)
   66 16:43:22.385221  progress  70% (30MB)
   67 16:43:22.396989  progress  75% (32MB)
   68 16:43:22.408438  progress  80% (34MB)
   69 16:43:22.420155  progress  85% (37MB)
   70 16:43:22.431898  progress  90% (39MB)
   71 16:43:22.443419  progress  95% (41MB)
   72 16:43:22.454874  progress 100% (43MB)
   73 16:43:22.455038  43MB downloaded in 0.53s (82.89MB/s)
   74 16:43:22.455208  end: 1.2.1 http-download (duration 00:00:01) [common]
   76 16:43:22.455469  end: 1.2 download-retry (duration 00:00:01) [common]
   77 16:43:22.455604  start: 1.3 download-retry (timeout 00:09:57) [common]
   78 16:43:22.455732  start: 1.3.1 http-download (timeout 00:09:57) [common]
   79 16:43:22.455903  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 16:43:22.456044  saving as /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/dtb/mt8192-asurada-spherion-r0.dtb
   81 16:43:22.456146  total size: 46924 (0MB)
   82 16:43:22.456245  No compression specified
   83 16:43:22.457950  progress  69% (0MB)
   84 16:43:22.458253  progress 100% (0MB)
   85 16:43:22.458443  0MB downloaded in 0.00s (19.50MB/s)
   86 16:43:22.458606  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 16:43:22.458857  end: 1.3 download-retry (duration 00:00:00) [common]
   89 16:43:22.458958  start: 1.4 download-retry (timeout 00:09:57) [common]
   90 16:43:22.459057  start: 1.4.1 http-download (timeout 00:09:57) [common]
   91 16:43:22.459182  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 16:43:22.459258  saving as /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/modules/modules.tar
   93 16:43:22.459357  total size: 8545664 (8MB)
   94 16:43:22.459456  Using unxz to decompress xz
   95 16:43:22.463495  progress   0% (0MB)
   96 16:43:22.485050  progress   5% (0MB)
   97 16:43:22.509675  progress  10% (0MB)
   98 16:43:22.535563  progress  15% (1MB)
   99 16:43:22.560259  progress  20% (1MB)
  100 16:43:22.585701  progress  25% (2MB)
  101 16:43:22.610376  progress  30% (2MB)
  102 16:43:22.635254  progress  35% (2MB)
  103 16:43:22.659751  progress  40% (3MB)
  104 16:43:22.684762  progress  45% (3MB)
  105 16:43:22.708552  progress  50% (4MB)
  106 16:43:22.731286  progress  55% (4MB)
  107 16:43:22.755887  progress  60% (4MB)
  108 16:43:22.780999  progress  65% (5MB)
  109 16:43:22.806332  progress  70% (5MB)
  110 16:43:22.832890  progress  75% (6MB)
  111 16:43:22.861949  progress  80% (6MB)
  112 16:43:22.884545  progress  85% (6MB)
  113 16:43:22.909129  progress  90% (7MB)
  114 16:43:22.932057  progress  95% (7MB)
  115 16:43:22.955326  progress 100% (8MB)
  116 16:43:22.961127  8MB downloaded in 0.50s (16.24MB/s)
  117 16:43:22.961400  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 16:43:22.961668  end: 1.4 download-retry (duration 00:00:01) [common]
  120 16:43:22.961764  start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
  121 16:43:22.961862  start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
  122 16:43:22.961945  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 16:43:22.962033  start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
  124 16:43:22.962252  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz
  125 16:43:22.962378  makedir: /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin
  126 16:43:22.962479  makedir: /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/tests
  127 16:43:22.962575  makedir: /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/results
  128 16:43:22.962694  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-add-keys
  129 16:43:22.962833  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-add-sources
  130 16:43:22.962961  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-background-process-start
  131 16:43:22.963085  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-background-process-stop
  132 16:43:22.963205  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-common-functions
  133 16:43:22.963324  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-echo-ipv4
  134 16:43:22.963443  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-install-packages
  135 16:43:22.963562  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-installed-packages
  136 16:43:22.963682  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-os-build
  137 16:43:22.963800  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-probe-channel
  138 16:43:22.963921  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-probe-ip
  139 16:43:22.964046  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-target-ip
  140 16:43:22.964166  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-target-mac
  141 16:43:22.964284  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-target-storage
  142 16:43:22.964407  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-case
  143 16:43:22.964526  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-event
  144 16:43:22.964644  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-feedback
  145 16:43:22.964762  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-raise
  146 16:43:22.964883  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-reference
  147 16:43:22.965001  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-runner
  148 16:43:22.965119  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-set
  149 16:43:22.965240  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-test-shell
  150 16:43:22.965362  Updating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-install-packages (oe)
  151 16:43:22.965508  Updating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/bin/lava-installed-packages (oe)
  152 16:43:22.965632  Creating /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/environment
  153 16:43:22.965735  LAVA metadata
  154 16:43:22.965811  - LAVA_JOB_ID=10576290
  155 16:43:22.965877  - LAVA_DISPATCHER_IP=192.168.201.1
  156 16:43:22.965980  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
  157 16:43:22.966051  skipped lava-vland-overlay
  158 16:43:22.966128  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 16:43:22.966212  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
  160 16:43:22.966276  skipped lava-multinode-overlay
  161 16:43:22.966350  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 16:43:22.966431  start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
  163 16:43:22.966510  Loading test definitions
  164 16:43:22.966602  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
  165 16:43:22.966680  Using /lava-10576290 at stage 0
  166 16:43:22.966961  uuid=10576290_1.5.2.3.1 testdef=None
  167 16:43:22.967047  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 16:43:22.967131  start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
  169 16:43:22.967628  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 16:43:22.967847  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
  172 16:43:22.968481  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 16:43:22.968712  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
  175 16:43:22.969292  runner path: /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/0/tests/0_cros-ec test_uuid 10576290_1.5.2.3.1
  176 16:43:22.969441  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 16:43:22.969646  Creating lava-test-runner.conf files
  179 16:43:22.969709  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576290/lava-overlay-mm_yi0zz/lava-10576290/0 for stage 0
  180 16:43:22.969795  - 0_cros-ec
  181 16:43:22.969890  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 16:43:22.969977  start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
  183 16:43:22.976464  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 16:43:22.976569  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
  185 16:43:22.976657  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 16:43:22.976741  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 16:43:22.976828  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
  188 16:43:23.938660  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 16:43:23.939032  start: 1.5.4 extract-modules (timeout 00:09:55) [common]
  190 16:43:23.939145  extracting modules file /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576290/extract-overlay-ramdisk-mdwiaerh/ramdisk
  191 16:43:24.150456  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 16:43:24.150615  start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
  193 16:43:24.150710  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576290/compress-overlay-0_okw8wh/overlay-1.5.2.4.tar.gz to ramdisk
  194 16:43:24.150784  [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576290/compress-overlay-0_okw8wh/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576290/extract-overlay-ramdisk-mdwiaerh/ramdisk
  195 16:43:24.158257  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 16:43:24.158377  start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
  197 16:43:24.158471  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 16:43:24.158560  start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
  199 16:43:24.158641  Building ramdisk /var/lib/lava/dispatcher/tmp/10576290/extract-overlay-ramdisk-mdwiaerh/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576290/extract-overlay-ramdisk-mdwiaerh/ramdisk
  200 16:43:24.814220  >> 269468 blocks

  201 16:43:29.481664  rename /var/lib/lava/dispatcher/tmp/10576290/extract-overlay-ramdisk-mdwiaerh/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/ramdisk/ramdisk.cpio.gz
  202 16:43:29.482101  end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
  203 16:43:29.482231  start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
  204 16:43:29.482335  start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
  205 16:43:29.482440  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/kernel/Image'
  206 16:43:41.068597  Returned 0 in 11 seconds
  207 16:43:41.169249  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/kernel/image.itb
  208 16:43:41.833526  output: FIT description: Kernel Image image with one or more FDT blobs
  209 16:43:41.833904  output: Created:         Sat Jun  3 17:43:41 2023
  210 16:43:41.833990  output:  Image 0 (kernel-1)
  211 16:43:41.834060  output:   Description:  
  212 16:43:41.834124  output:   Created:      Sat Jun  3 17:43:41 2023
  213 16:43:41.834187  output:   Type:         Kernel Image
  214 16:43:41.834249  output:   Compression:  lzma compressed
  215 16:43:41.834312  output:   Data Size:    10083474 Bytes = 9847.14 KiB = 9.62 MiB
  216 16:43:41.834372  output:   Architecture: AArch64
  217 16:43:41.834432  output:   OS:           Linux
  218 16:43:41.834493  output:   Load Address: 0x00000000
  219 16:43:41.834552  output:   Entry Point:  0x00000000
  220 16:43:41.834611  output:   Hash algo:    crc32
  221 16:43:41.834668  output:   Hash value:   b48eba69
  222 16:43:41.834724  output:  Image 1 (fdt-1)
  223 16:43:41.834780  output:   Description:  mt8192-asurada-spherion-r0
  224 16:43:41.834835  output:   Created:      Sat Jun  3 17:43:41 2023
  225 16:43:41.834891  output:   Type:         Flat Device Tree
  226 16:43:41.834946  output:   Compression:  uncompressed
  227 16:43:41.835001  output:   Data Size:    46924 Bytes = 45.82 KiB = 0.04 MiB
  228 16:43:41.835057  output:   Architecture: AArch64
  229 16:43:41.835112  output:   Hash algo:    crc32
  230 16:43:41.835167  output:   Hash value:   1df858fa
  231 16:43:41.835222  output:  Image 2 (ramdisk-1)
  232 16:43:41.835276  output:   Description:  unavailable
  233 16:43:41.835336  output:   Created:      Sat Jun  3 17:43:41 2023
  234 16:43:41.835392  output:   Type:         RAMDisk Image
  235 16:43:41.835447  output:   Compression:  Unknown Compression
  236 16:43:41.835502  output:   Data Size:    47372215 Bytes = 46261.93 KiB = 45.18 MiB
  237 16:43:41.835557  output:   Architecture: AArch64
  238 16:43:41.835612  output:   OS:           Linux
  239 16:43:41.835667  output:   Load Address: unavailable
  240 16:43:41.835722  output:   Entry Point:  unavailable
  241 16:43:41.835780  output:   Hash algo:    crc32
  242 16:43:41.835835  output:   Hash value:   3d21f616
  243 16:43:41.835890  output:  Default Configuration: 'conf-1'
  244 16:43:41.835945  output:  Configuration 0 (conf-1)
  245 16:43:41.836040  output:   Description:  mt8192-asurada-spherion-r0
  246 16:43:41.836124  output:   Kernel:       kernel-1
  247 16:43:41.836183  output:   Init Ramdisk: ramdisk-1
  248 16:43:41.836238  output:   FDT:          fdt-1
  249 16:43:41.836293  output:   Loadables:    kernel-1
  250 16:43:41.836348  output: 
  251 16:43:41.836543  end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
  252 16:43:41.836643  end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
  253 16:43:41.836749  end: 1.5 prepare-tftp-overlay (duration 00:00:19) [common]
  254 16:43:41.836842  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
  255 16:43:41.836926  No LXC device requested
  256 16:43:41.837008  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 16:43:41.837099  start: 1.7 deploy-device-env (timeout 00:09:37) [common]
  258 16:43:41.837180  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 16:43:41.837254  Checking files for TFTP limit of 4294967296 bytes.
  260 16:43:41.837762  end: 1 tftp-deploy (duration 00:00:23) [common]
  261 16:43:41.837869  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 16:43:41.837961  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 16:43:41.838083  substitutions:
  264 16:43:41.838151  - {DTB}: 10576290/tftp-deploy-q_z35kvn/dtb/mt8192-asurada-spherion-r0.dtb
  265 16:43:41.838219  - {INITRD}: 10576290/tftp-deploy-q_z35kvn/ramdisk/ramdisk.cpio.gz
  266 16:43:41.838288  - {KERNEL}: 10576290/tftp-deploy-q_z35kvn/kernel/Image
  267 16:43:41.838357  - {LAVA_MAC}: None
  268 16:43:41.838423  - {PRESEED_CONFIG}: None
  269 16:43:41.838488  - {PRESEED_LOCAL}: None
  270 16:43:41.838552  - {RAMDISK}: 10576290/tftp-deploy-q_z35kvn/ramdisk/ramdisk.cpio.gz
  271 16:43:41.838618  - {ROOT_PART}: None
  272 16:43:41.838682  - {ROOT}: None
  273 16:43:41.838746  - {SERVER_IP}: 192.168.201.1
  274 16:43:41.838809  - {TEE}: None
  275 16:43:41.838873  Parsed boot commands:
  276 16:43:41.838936  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 16:43:41.839114  Parsed boot commands: tftpboot 192.168.201.1 10576290/tftp-deploy-q_z35kvn/kernel/image.itb 10576290/tftp-deploy-q_z35kvn/kernel/cmdline 
  278 16:43:41.839208  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 16:43:41.839298  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 16:43:41.839393  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 16:43:41.839484  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 16:43:41.839558  Not connected, no need to disconnect.
  283 16:43:41.839635  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 16:43:41.839719  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 16:43:41.839786  [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
  286 16:43:41.843204  Setting prompt string to ['lava-test: # ']
  287 16:43:41.843610  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 16:43:41.843754  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 16:43:41.843886  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 16:43:41.844022  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 16:43:41.844229  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
  292 16:43:46.979624  >> Command sent successfully.

  293 16:43:46.982090  Returned 0 in 5 seconds
  294 16:43:47.082511  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 16:43:47.083088  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 16:43:47.083190  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 16:43:47.083278  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 16:43:47.083346  Changing prompt to 'Starting depthcharge on Spherion...'
  300 16:43:47.083415  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 16:43:47.083663  [Enter `^Ec?' for help]

  302 16:43:47.256938  

  303 16:43:47.257098  

  304 16:43:47.257166  F0: 102B 0000

  305 16:43:47.257228  

  306 16:43:47.257287  F3: 1001 0000 [0200]

  307 16:43:47.260619  

  308 16:43:47.260703  F3: 1001 0000

  309 16:43:47.260770  

  310 16:43:47.260831  F7: 102D 0000

  311 16:43:47.260891  

  312 16:43:47.263522  F1: 0000 0000

  313 16:43:47.263606  

  314 16:43:47.263673  V0: 0000 0000 [0001]

  315 16:43:47.263735  

  316 16:43:47.267177  00: 0007 8000

  317 16:43:47.267262  

  318 16:43:47.267329  01: 0000 0000

  319 16:43:47.267394  

  320 16:43:47.269926  BP: 0C00 0209 [0000]

  321 16:43:47.270011  

  322 16:43:47.270079  G0: 1182 0000

  323 16:43:47.270141  

  324 16:43:47.273722  EC: 0000 0021 [4000]

  325 16:43:47.273809  

  326 16:43:47.273880  S7: 0000 0000 [0000]

  327 16:43:47.273948  

  328 16:43:47.277258  CC: 0000 0000 [0001]

  329 16:43:47.277345  

  330 16:43:47.277413  T0: 0000 0040 [010F]

  331 16:43:47.277476  

  332 16:43:47.277535  Jump to BL

  333 16:43:47.280737  

  334 16:43:47.303598  

  335 16:43:47.303720  

  336 16:43:47.303788  

  337 16:43:47.310713  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 16:43:47.317689  ARM64: Exception handlers installed.

  339 16:43:47.317809  ARM64: Testing exception

  340 16:43:47.321269  ARM64: Done test exception

  341 16:43:47.327965  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 16:43:47.337938  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 16:43:47.344397  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 16:43:47.354998  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 16:43:47.361593  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 16:43:47.371608  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 16:43:47.381668  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 16:43:47.388622  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 16:43:47.406570  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 16:43:47.410083  WDT: Last reset was cold boot

  351 16:43:47.413570  SPI1(PAD0) initialized at 2873684 Hz

  352 16:43:47.416779  SPI5(PAD0) initialized at 992727 Hz

  353 16:43:47.420223  VBOOT: Loading verstage.

  354 16:43:47.427290  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 16:43:47.430084  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 16:43:47.433425  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 16:43:47.437085  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 16:43:47.443911  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 16:43:47.450568  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 16:43:47.462086  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  361 16:43:47.462182  

  362 16:43:47.462251  

  363 16:43:47.472155  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 16:43:47.475141  ARM64: Exception handlers installed.

  365 16:43:47.478666  ARM64: Testing exception

  366 16:43:47.478751  ARM64: Done test exception

  367 16:43:47.485334  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 16:43:47.488279  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 16:43:47.504245  Probing TPM: . done!

  370 16:43:47.504336  TPM ready after 0 ms

  371 16:43:47.511217  Connected to device vid:did:rid of 1ae0:0028:00

  372 16:43:47.517740  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

  373 16:43:47.576592  Initialized TPM device CR50 revision 0

  374 16:43:47.588344  tlcl_send_startup: Startup return code is 0

  375 16:43:47.588530  TPM: setup succeeded

  376 16:43:47.599570  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 16:43:47.608321  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 16:43:47.621163  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 16:43:47.630955  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 16:43:47.633625  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 16:43:47.638168  in-header: 03 07 00 00 08 00 00 00 

  382 16:43:47.641620  in-data: aa e4 47 04 13 02 00 00 

  383 16:43:47.645233  Chrome EC: UHEPI supported

  384 16:43:47.652431  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 16:43:47.656308  in-header: 03 ad 00 00 08 00 00 00 

  386 16:43:47.660142  in-data: 00 20 20 08 00 00 00 00 

  387 16:43:47.660234  Phase 1

  388 16:43:47.663617  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 16:43:47.671034  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 16:43:47.674520  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 16:43:47.678159  Recovery requested (1009000e)

  392 16:43:47.688022  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 16:43:47.693755  tlcl_extend: response is 0

  394 16:43:47.704907  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 16:43:47.708932  tlcl_extend: response is 0

  396 16:43:47.715768  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 16:43:47.735614  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  398 16:43:47.742001  BS: bootblock times (exec / console): total (unknown) / 148 ms

  399 16:43:47.742121  

  400 16:43:47.742189  

  401 16:43:47.752996  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 16:43:47.756686  ARM64: Exception handlers installed.

  403 16:43:47.756791  ARM64: Testing exception

  404 16:43:47.759569  ARM64: Done test exception

  405 16:43:47.780550  pmic_efuse_setting: Set efuses in 11 msecs

  406 16:43:47.784213  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 16:43:47.791008  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 16:43:47.794476  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 16:43:47.801582  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 16:43:47.805116  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 16:43:47.808574  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 16:43:47.815673  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 16:43:47.819521  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 16:43:47.823368  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 16:43:47.827005  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 16:43:47.834083  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 16:43:47.837876  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 16:43:47.841803  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 16:43:47.845385  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 16:43:47.852864  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 16:43:47.860268  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 16:43:47.864242  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 16:43:47.871517  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 16:43:47.875096  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 16:43:47.882001  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 16:43:47.885601  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 16:43:47.893191  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 16:43:47.896767  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 16:43:47.904262  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 16:43:47.907848  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 16:43:47.914850  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 16:43:47.922340  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 16:43:47.925910  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 16:43:47.929716  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 16:43:47.933369  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 16:43:47.940561  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 16:43:47.944348  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 16:43:47.951514  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 16:43:47.955267  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 16:43:47.958792  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 16:43:47.966199  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 16:43:47.970056  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 16:43:47.973422  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 16:43:47.981099  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 16:43:47.984587  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 16:43:47.988225  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 16:43:47.992266  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 16:43:47.999410  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 16:43:48.003233  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 16:43:48.007222  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 16:43:48.010779  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 16:43:48.014297  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 16:43:48.018042  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 16:43:48.025091  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 16:43:48.028501  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 16:43:48.032244  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 16:43:48.035890  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 16:43:48.042927  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 16:43:48.054052  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 16:43:48.057603  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 16:43:48.065086  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 16:43:48.072367  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 16:43:48.079924  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 16:43:48.083496  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 16:43:48.086396  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 16:43:48.094510  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0

  467 16:43:48.097990  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 16:43:48.105269  [RTC]rtc_osc_init,62: osc32con val = 0xde6f

  469 16:43:48.108619  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 16:43:48.117933  [RTC]rtc_get_frequency_meter,154: input=15, output=791

  471 16:43:48.127673  [RTC]rtc_get_frequency_meter,154: input=23, output=980

  472 16:43:48.137324  [RTC]rtc_get_frequency_meter,154: input=19, output=886

  473 16:43:48.146704  [RTC]rtc_get_frequency_meter,154: input=17, output=838

  474 16:43:48.156996  [RTC]rtc_get_frequency_meter,154: input=16, output=814

  475 16:43:48.166169  [RTC]rtc_get_frequency_meter,154: input=15, output=790

  476 16:43:48.176107  [RTC]rtc_get_frequency_meter,154: input=16, output=814

  477 16:43:48.179470  [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16

  478 16:43:48.186292  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f

  479 16:43:48.190405  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  480 16:43:48.194116  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  481 16:43:48.198009  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  482 16:43:48.201427  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  483 16:43:48.204861  ADC[4]: Raw value=901328 ID=7

  484 16:43:48.209066  ADC[3]: Raw value=213336 ID=1

  485 16:43:48.209153  RAM Code: 0x71

  486 16:43:48.212774  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  487 16:43:48.219694  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  488 16:43:48.227497  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  489 16:43:48.234446  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  490 16:43:48.238407  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  491 16:43:48.241667  in-header: 03 07 00 00 08 00 00 00 

  492 16:43:48.245228  in-data: aa e4 47 04 13 02 00 00 

  493 16:43:48.245679  Chrome EC: UHEPI supported

  494 16:43:48.252482  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  495 16:43:48.256238  in-header: 03 ed 00 00 08 00 00 00 

  496 16:43:48.260071  in-data: 80 20 60 08 00 00 00 00 

  497 16:43:48.263905  MRC: failed to locate region type 0.

  498 16:43:48.267459  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  499 16:43:48.270963  DRAM-K: Running full calibration

  500 16:43:48.278744  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  501 16:43:48.279194  header.status = 0x0

  502 16:43:48.282664  header.version = 0x6 (expected: 0x6)

  503 16:43:48.286435  header.size = 0xd00 (expected: 0xd00)

  504 16:43:48.289783  header.flags = 0x0

  505 16:43:48.293426  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  506 16:43:48.313139  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  507 16:43:48.320552  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  508 16:43:48.324737  dram_init: ddr_geometry: 2

  509 16:43:48.325101  [EMI] MDL number = 2

  510 16:43:48.328270  [EMI] Get MDL freq = 0

  511 16:43:48.328633  dram_init: ddr_type: 0

  512 16:43:48.331814  is_discrete_lpddr4: 1

  513 16:43:48.332236  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  514 16:43:48.336034  

  515 16:43:48.336509  

  516 16:43:48.336812  [Bian_co] ETT version 0.0.0.1

  517 16:43:48.343062   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  518 16:43:48.343607  

  519 16:43:48.346379  dramc_set_vcore_voltage set vcore to 650000

  520 16:43:48.346879  Read voltage for 800, 4

  521 16:43:48.347330  Vio18 = 0

  522 16:43:48.350139  Vcore = 650000

  523 16:43:48.350542  Vdram = 0

  524 16:43:48.350861  Vddq = 0

  525 16:43:48.354090  Vmddr = 0

  526 16:43:48.354595  dram_init: config_dvfs: 1

  527 16:43:48.361817  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  528 16:43:48.364384  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  529 16:43:48.368317  [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10

  530 16:43:48.371278  freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10

  531 16:43:48.378246  [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9

  532 16:43:48.381290  freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9

  533 16:43:48.381725  MEM_TYPE=3, freq_sel=18

  534 16:43:48.384761  sv_algorithm_assistance_LP4_1600 

  535 16:43:48.391264  ============ PULL DRAM RESETB DOWN ============

  536 16:43:48.394913  ========== PULL DRAM RESETB DOWN end =========

  537 16:43:48.397871  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  538 16:43:48.401497  =================================== 

  539 16:43:48.404270  LPDDR4 DRAM CONFIGURATION

  540 16:43:48.407617  =================================== 

  541 16:43:48.411462  EX_ROW_EN[0]    = 0x0

  542 16:43:48.412086  EX_ROW_EN[1]    = 0x0

  543 16:43:48.414280  LP4Y_EN      = 0x0

  544 16:43:48.414885  WORK_FSP     = 0x0

  545 16:43:48.417626  WL           = 0x2

  546 16:43:48.418043  RL           = 0x2

  547 16:43:48.421022  BL           = 0x2

  548 16:43:48.421564  RPST         = 0x0

  549 16:43:48.424499  RD_PRE       = 0x0

  550 16:43:48.424902  WR_PRE       = 0x1

  551 16:43:48.427318  WR_PST       = 0x0

  552 16:43:48.427866  DBI_WR       = 0x0

  553 16:43:48.430929  DBI_RD       = 0x0

  554 16:43:48.431530  OTF          = 0x1

  555 16:43:48.434375  =================================== 

  556 16:43:48.437829  =================================== 

  557 16:43:48.440852  ANA top config

  558 16:43:48.444425  =================================== 

  559 16:43:48.444922  DLL_ASYNC_EN            =  0

  560 16:43:48.447901  ALL_SLAVE_EN            =  1

  561 16:43:48.450746  NEW_RANK_MODE           =  1

  562 16:43:48.454173  DLL_IDLE_MODE           =  1

  563 16:43:48.457832  LP45_APHY_COMB_EN       =  1

  564 16:43:48.458234  TX_ODT_DIS              =  1

  565 16:43:48.460625  NEW_8X_MODE             =  1

  566 16:43:48.464601  =================================== 

  567 16:43:48.467666  =================================== 

  568 16:43:48.470472  data_rate                  = 1600

  569 16:43:48.473967  CKR                        = 1

  570 16:43:48.477633  DQ_P2S_RATIO               = 8

  571 16:43:48.480905  =================================== 

  572 16:43:48.483627  CA_P2S_RATIO               = 8

  573 16:43:48.484092  DQ_CA_OPEN                 = 0

  574 16:43:48.487146  DQ_SEMI_OPEN               = 0

  575 16:43:48.490617  CA_SEMI_OPEN               = 0

  576 16:43:48.494244  CA_FULL_RATE               = 0

  577 16:43:48.497992  DQ_CKDIV4_EN               = 1

  578 16:43:48.500880  CA_CKDIV4_EN               = 1

  579 16:43:48.501328  CA_PREDIV_EN               = 0

  580 16:43:48.504290  PH8_DLY                    = 0

  581 16:43:48.507451  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  582 16:43:48.510979  DQ_AAMCK_DIV               = 4

  583 16:43:48.514409  CA_AAMCK_DIV               = 4

  584 16:43:48.514830  CA_ADMCK_DIV               = 4

  585 16:43:48.517429  DQ_TRACK_CA_EN             = 0

  586 16:43:48.520418  CA_PICK                    = 800

  587 16:43:48.524389  CA_MCKIO                   = 800

  588 16:43:48.527109  MCKIO_SEMI                 = 0

  589 16:43:48.530887  PLL_FREQ                   = 3068

  590 16:43:48.534500  DQ_UI_PI_RATIO             = 32

  591 16:43:48.535243  CA_UI_PI_RATIO             = 0

  592 16:43:48.538595  =================================== 

  593 16:43:48.542028  =================================== 

  594 16:43:48.546071  memory_type:LPDDR4         

  595 16:43:48.546573  GP_NUM     : 10       

  596 16:43:48.549646  SRAM_EN    : 1       

  597 16:43:48.550052  MD32_EN    : 0       

  598 16:43:48.553208  =================================== 

  599 16:43:48.557297  [ANA_INIT] >>>>>>>>>>>>>> 

  600 16:43:48.560731  <<<<<< [CONFIGURE PHASE]: ANA_TX

  601 16:43:48.564817  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  602 16:43:48.565253  =================================== 

  603 16:43:48.567913  data_rate = 1600,PCW = 0X7600

  604 16:43:48.571445  =================================== 

  605 16:43:48.575028  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  606 16:43:48.581120  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  607 16:43:48.587937  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  608 16:43:48.591747  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  609 16:43:48.595115  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  610 16:43:48.598062  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  611 16:43:48.601496  [ANA_INIT] flow start 

  612 16:43:48.601907  [ANA_INIT] PLL >>>>>>>> 

  613 16:43:48.604986  [ANA_INIT] PLL <<<<<<<< 

  614 16:43:48.607999  [ANA_INIT] MIDPI >>>>>>>> 

  615 16:43:48.608527  [ANA_INIT] MIDPI <<<<<<<< 

  616 16:43:48.611697  [ANA_INIT] DLL >>>>>>>> 

  617 16:43:48.615245  [ANA_INIT] flow end 

  618 16:43:48.618055  ============ LP4 DIFF to SE enter ============

  619 16:43:48.621452  ============ LP4 DIFF to SE exit  ============

  620 16:43:48.625165  [ANA_INIT] <<<<<<<<<<<<< 

  621 16:43:48.628166  [Flow] Enable top DCM control >>>>> 

  622 16:43:48.631684  [Flow] Enable top DCM control <<<<< 

  623 16:43:48.634645  Enable DLL master slave shuffle 

  624 16:43:48.637908  ============================================================== 

  625 16:43:48.641824  Gating Mode config

  626 16:43:48.644861  ============================================================== 

  627 16:43:48.648362  Config description: 

  628 16:43:48.658094  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  629 16:43:48.665077  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  630 16:43:48.667911  SELPH_MODE            0: By rank         1: By Phase 

  631 16:43:48.674962  ============================================================== 

  632 16:43:48.678441  GAT_TRACK_EN                 =  1

  633 16:43:48.681783  RX_GATING_MODE               =  2

  634 16:43:48.684741  RX_GATING_TRACK_MODE         =  2

  635 16:43:48.688461  SELPH_MODE                   =  1

  636 16:43:48.691622  PICG_EARLY_EN                =  1

  637 16:43:48.692049  VALID_LAT_VALUE              =  1

  638 16:43:48.698360  ============================================================== 

  639 16:43:48.701690  Enter into Gating configuration >>>> 

  640 16:43:48.705163  Exit from Gating configuration <<<< 

  641 16:43:48.708417  Enter into  DVFS_PRE_config >>>>> 

  642 16:43:48.718586  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  643 16:43:48.721733  Exit from  DVFS_PRE_config <<<<< 

  644 16:43:48.724644  Enter into PICG configuration >>>> 

  645 16:43:48.728335  Exit from PICG configuration <<<< 

  646 16:43:48.731836  [RX_INPUT] configuration >>>>> 

  647 16:43:48.735037  [RX_INPUT] configuration <<<<< 

  648 16:43:48.738263  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  649 16:43:48.744520  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  650 16:43:48.752096  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  651 16:43:48.759020  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  652 16:43:48.761866  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  653 16:43:48.768863  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  654 16:43:48.771901  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  655 16:43:48.779133  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  656 16:43:48.781840  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  657 16:43:48.785151  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  658 16:43:48.788525  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  659 16:43:48.795163  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  660 16:43:48.798360  =================================== 

  661 16:43:48.798446  LPDDR4 DRAM CONFIGURATION

  662 16:43:48.801602  =================================== 

  663 16:43:48.804898  EX_ROW_EN[0]    = 0x0

  664 16:43:48.808534  EX_ROW_EN[1]    = 0x0

  665 16:43:48.808620  LP4Y_EN      = 0x0

  666 16:43:48.811593  WORK_FSP     = 0x0

  667 16:43:48.811678  WL           = 0x2

  668 16:43:48.814945  RL           = 0x2

  669 16:43:48.815030  BL           = 0x2

  670 16:43:48.818390  RPST         = 0x0

  671 16:43:48.818474  RD_PRE       = 0x0

  672 16:43:48.821982  WR_PRE       = 0x1

  673 16:43:48.822067  WR_PST       = 0x0

  674 16:43:48.824882  DBI_WR       = 0x0

  675 16:43:48.824967  DBI_RD       = 0x0

  676 16:43:48.828585  OTF          = 0x1

  677 16:43:48.831952  =================================== 

  678 16:43:48.834968  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  679 16:43:48.838300  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  680 16:43:48.845668  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  681 16:43:48.848727  =================================== 

  682 16:43:48.848813  LPDDR4 DRAM CONFIGURATION

  683 16:43:48.851709  =================================== 

  684 16:43:48.855201  EX_ROW_EN[0]    = 0x10

  685 16:43:48.855287  EX_ROW_EN[1]    = 0x0

  686 16:43:48.858725  LP4Y_EN      = 0x0

  687 16:43:48.858815  WORK_FSP     = 0x0

  688 16:43:48.862029  WL           = 0x2

  689 16:43:48.862127  RL           = 0x2

  690 16:43:48.865482  BL           = 0x2

  691 16:43:48.868486  RPST         = 0x0

  692 16:43:48.868584  RD_PRE       = 0x0

  693 16:43:48.871966  WR_PRE       = 0x1

  694 16:43:48.872065  WR_PST       = 0x0

  695 16:43:48.875044  DBI_WR       = 0x0

  696 16:43:48.875141  DBI_RD       = 0x0

  697 16:43:48.878414  OTF          = 0x1

  698 16:43:48.881998  =================================== 

  699 16:43:48.884990  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  700 16:43:48.890508  nWR fixed to 40

  701 16:43:48.893994  [ModeRegInit_LP4] CH0 RK0

  702 16:43:48.894085  [ModeRegInit_LP4] CH0 RK1

  703 16:43:48.897671  [ModeRegInit_LP4] CH1 RK0

  704 16:43:48.900651  [ModeRegInit_LP4] CH1 RK1

  705 16:43:48.901016  match AC timing 13

  706 16:43:48.907494  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  707 16:43:48.910889  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  708 16:43:48.914228  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  709 16:43:48.920807  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  710 16:43:48.924349  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  711 16:43:48.924694  [EMI DOE] emi_dcm 0

  712 16:43:48.930690  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  713 16:43:48.931159  ==

  714 16:43:48.934073  Dram Type= 6, Freq= 0, CH_0, rank 0

  715 16:43:48.937672  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  716 16:43:48.938005  ==

  717 16:43:48.944185  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  718 16:43:48.947626  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  719 16:43:48.958362  [CA 0] Center 37 (6~68) winsize 63

  720 16:43:48.961348  [CA 1] Center 37 (6~68) winsize 63

  721 16:43:48.964868  [CA 2] Center 35 (5~66) winsize 62

  722 16:43:48.968419  [CA 3] Center 34 (4~65) winsize 62

  723 16:43:48.971437  [CA 4] Center 34 (4~65) winsize 62

  724 16:43:48.974835  [CA 5] Center 33 (3~64) winsize 62

  725 16:43:48.975165  

  726 16:43:48.978398  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  727 16:43:48.978727  

  728 16:43:48.981807  [CATrainingPosCal] consider 1 rank data

  729 16:43:48.984756  u2DelayCellTimex100 = 270/100 ps

  730 16:43:48.988252  CA0 delay=37 (6~68),Diff = 4 PI (28 cell)

  731 16:43:48.991541  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  732 16:43:48.998144  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  733 16:43:49.001629  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  734 16:43:49.004881  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

  735 16:43:49.008286  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  736 16:43:49.008395  

  737 16:43:49.011119  CA PerBit enable=1, Macro0, CA PI delay=33

  738 16:43:49.011226  

  739 16:43:49.014508  [CBTSetCACLKResult] CA Dly = 33

  740 16:43:49.014616  CS Dly: 5 (0~36)

  741 16:43:49.014713  ==

  742 16:43:49.017966  Dram Type= 6, Freq= 0, CH_0, rank 1

  743 16:43:49.025455  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  744 16:43:49.025798  ==

  745 16:43:49.028496  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  746 16:43:49.035289  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  747 16:43:49.044652  [CA 0] Center 37 (6~68) winsize 63

  748 16:43:49.047570  [CA 1] Center 37 (6~68) winsize 63

  749 16:43:49.051111  [CA 2] Center 35 (4~66) winsize 63

  750 16:43:49.054581  [CA 3] Center 35 (4~66) winsize 63

  751 16:43:49.058075  [CA 4] Center 33 (3~64) winsize 62

  752 16:43:49.061369  [CA 5] Center 33 (3~64) winsize 62

  753 16:43:49.061624  

  754 16:43:49.064784  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  755 16:43:49.064984  

  756 16:43:49.067680  [CATrainingPosCal] consider 2 rank data

  757 16:43:49.071338  u2DelayCellTimex100 = 270/100 ps

  758 16:43:49.074727  CA0 delay=37 (6~68),Diff = 4 PI (28 cell)

  759 16:43:49.077679  CA1 delay=37 (6~68),Diff = 4 PI (28 cell)

  760 16:43:49.084611  CA2 delay=35 (5~66),Diff = 2 PI (14 cell)

  761 16:43:49.087899  CA3 delay=34 (4~65),Diff = 1 PI (7 cell)

  762 16:43:49.091392  CA4 delay=34 (4~64),Diff = 1 PI (7 cell)

  763 16:43:49.094843  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

  764 16:43:49.095180  

  765 16:43:49.098144  CA PerBit enable=1, Macro0, CA PI delay=33

  766 16:43:49.098394  

  767 16:43:49.101687  [CBTSetCACLKResult] CA Dly = 33

  768 16:43:49.101885  CS Dly: 6 (0~38)

  769 16:43:49.102068  

  770 16:43:49.104648  ----->DramcWriteLeveling(PI) begin...

  771 16:43:49.107650  ==

  772 16:43:49.107848  Dram Type= 6, Freq= 0, CH_0, rank 0

  773 16:43:49.114984  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  774 16:43:49.115070  ==

  775 16:43:49.119072  Write leveling (Byte 0): 30 => 30

  776 16:43:49.119474  Write leveling (Byte 1): 30 => 30

  777 16:43:49.122898  DramcWriteLeveling(PI) end<-----

  778 16:43:49.123319  

  779 16:43:49.123641  ==

  780 16:43:49.126523  Dram Type= 6, Freq= 0, CH_0, rank 0

  781 16:43:49.130427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  782 16:43:49.130831  ==

  783 16:43:49.133417  [Gating] SW mode calibration

  784 16:43:49.140892  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  785 16:43:49.147704  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  786 16:43:49.150694   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  787 16:43:49.154534   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  788 16:43:49.157422   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  789 16:43:49.164175   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

  790 16:43:49.167163   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 16:43:49.170861   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 16:43:49.177620   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 16:43:49.180941   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 16:43:49.184296   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 16:43:49.190789   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 16:43:49.194436   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 16:43:49.197674   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 16:43:49.204374   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 16:43:49.207207   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 16:43:49.210668   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 16:43:49.217578   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 16:43:49.221151   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 16:43:49.224218   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  804 16:43:49.231236   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

  805 16:43:49.234261   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  806 16:43:49.237281   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 16:43:49.240634   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 16:43:49.247875   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 16:43:49.251319   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 16:43:49.254205   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 16:43:49.261319   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 16:43:49.264686   0  9  8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)

  813 16:43:49.267874   0  9 12 | B1->B0 | 2929 3131 | 0 0 | (0 0) (0 0)

  814 16:43:49.274373   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  815 16:43:49.278061   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  816 16:43:49.281066   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  817 16:43:49.287727   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 16:43:49.291283   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 16:43:49.294267   0 10  4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

  820 16:43:49.301435   0 10  8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 0)

  821 16:43:49.304519   0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)

  822 16:43:49.308096   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  823 16:43:49.311456   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  824 16:43:49.318201   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  825 16:43:49.322002   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 16:43:49.325008   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 16:43:49.331568   0 11  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  828 16:43:49.334865   0 11  8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)

  829 16:43:49.338266   0 11 12 | B1->B0 | 3737 3f3f | 1 0 | (0 0) (0 0)

  830 16:43:49.344639   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  831 16:43:49.347893   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  832 16:43:49.351258   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  833 16:43:49.357753   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 16:43:49.361678   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 16:43:49.364845   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  836 16:43:49.371566   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  837 16:43:49.375207   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  838 16:43:49.377979   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 16:43:49.384505   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 16:43:49.388264   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 16:43:49.391139   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 16:43:49.394600   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 16:43:49.401493   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 16:43:49.404958   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 16:43:49.408368   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 16:43:49.414639   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 16:43:49.418147   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 16:43:49.421439   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 16:43:49.428132   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 16:43:49.431308   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 16:43:49.434787   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 16:43:49.441564   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  853 16:43:49.444496   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  854 16:43:49.447920  Total UI for P1: 0, mck2ui 16

  855 16:43:49.451461  best dqsien dly found for B0: ( 0, 14,  8)

  856 16:43:49.454666  Total UI for P1: 0, mck2ui 16

  857 16:43:49.458102  best dqsien dly found for B1: ( 0, 14, 10)

  858 16:43:49.461579  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

  859 16:43:49.464521  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

  860 16:43:49.464633  

  861 16:43:49.468208  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

  862 16:43:49.471136  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

  863 16:43:49.474523  [Gating] SW calibration Done

  864 16:43:49.474604  ==

  865 16:43:49.477806  Dram Type= 6, Freq= 0, CH_0, rank 0

  866 16:43:49.481385  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  867 16:43:49.484665  ==

  868 16:43:49.484748  RX Vref Scan: 0

  869 16:43:49.484815  

  870 16:43:49.488063  RX Vref 0 -> 0, step: 1

  871 16:43:49.488152  

  872 16:43:49.491235  RX Delay -130 -> 252, step: 16

  873 16:43:49.495015  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  874 16:43:49.497969  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

  875 16:43:49.501706  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  876 16:43:49.504755  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  877 16:43:49.508169  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

  878 16:43:49.514142  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

  879 16:43:49.517511  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

  880 16:43:49.521486  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

  881 16:43:49.524738  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

  882 16:43:49.528140  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  883 16:43:49.534817  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  884 16:43:49.537888  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

  885 16:43:49.541351  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

  886 16:43:49.544517  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

  887 16:43:49.551455  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

  888 16:43:49.554482  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  889 16:43:49.554620  ==

  890 16:43:49.558021  Dram Type= 6, Freq= 0, CH_0, rank 0

  891 16:43:49.561445  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  892 16:43:49.561625  ==

  893 16:43:49.561766  DQS Delay:

  894 16:43:49.564887  DQS0 = 0, DQS1 = 0

  895 16:43:49.565063  DQM Delay:

  896 16:43:49.567757  DQM0 = 85, DQM1 = 78

  897 16:43:49.567931  DQ Delay:

  898 16:43:49.571353  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85

  899 16:43:49.574790  DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93

  900 16:43:49.577677  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69

  901 16:43:49.581120  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

  902 16:43:49.581296  

  903 16:43:49.581436  

  904 16:43:49.581566  ==

  905 16:43:49.584577  Dram Type= 6, Freq= 0, CH_0, rank 0

  906 16:43:49.587619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  907 16:43:49.591446  ==

  908 16:43:49.591622  

  909 16:43:49.591762  

  910 16:43:49.591893  	TX Vref Scan disable

  911 16:43:49.595142   == TX Byte 0 ==

  912 16:43:49.597866  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  913 16:43:49.601140  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  914 16:43:49.604630   == TX Byte 1 ==

  915 16:43:49.608258  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  916 16:43:49.611327  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  917 16:43:49.611513  ==

  918 16:43:49.614764  Dram Type= 6, Freq= 0, CH_0, rank 0

  919 16:43:49.620976  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  920 16:43:49.621108  ==

  921 16:43:49.633388  TX Vref=22, minBit 0, minWin=27, winSum=442

  922 16:43:49.636651  TX Vref=24, minBit 5, minWin=27, winSum=442

  923 16:43:49.639412  TX Vref=26, minBit 5, minWin=27, winSum=447

  924 16:43:49.642893  TX Vref=28, minBit 12, minWin=27, winSum=451

  925 16:43:49.646711  TX Vref=30, minBit 9, minWin=27, winSum=451

  926 16:43:49.649440  TX Vref=32, minBit 1, minWin=28, winSum=451

  927 16:43:49.656478  [TxChooseVref] Worse bit 1, Min win 28, Win sum 451, Final Vref 32

  928 16:43:49.656578  

  929 16:43:49.660091  Final TX Range 1 Vref 32

  930 16:43:49.660176  

  931 16:43:49.660242  ==

  932 16:43:49.663527  Dram Type= 6, Freq= 0, CH_0, rank 0

  933 16:43:49.666681  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  934 16:43:49.666828  ==

  935 16:43:49.666961  

  936 16:43:49.667077  

  937 16:43:49.670052  	TX Vref Scan disable

  938 16:43:49.673041   == TX Byte 0 ==

  939 16:43:49.676556  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  940 16:43:49.680094  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  941 16:43:49.683529   == TX Byte 1 ==

  942 16:43:49.686575  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  943 16:43:49.690002  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  944 16:43:49.690127  

  945 16:43:49.693785  [DATLAT]

  946 16:43:49.693889  Freq=800, CH0 RK0

  947 16:43:49.693972  

  948 16:43:49.696715  DATLAT Default: 0xa

  949 16:43:49.696827  0, 0xFFFF, sum = 0

  950 16:43:49.700309  1, 0xFFFF, sum = 0

  951 16:43:49.700451  2, 0xFFFF, sum = 0

  952 16:43:49.703645  3, 0xFFFF, sum = 0

  953 16:43:49.703809  4, 0xFFFF, sum = 0

  954 16:43:49.707024  5, 0xFFFF, sum = 0

  955 16:43:49.707205  6, 0xFFFF, sum = 0

  956 16:43:49.709975  7, 0xFFFF, sum = 0

  957 16:43:49.710192  8, 0xFFFF, sum = 0

  958 16:43:49.713542  9, 0x0, sum = 1

  959 16:43:49.713627  10, 0x0, sum = 2

  960 16:43:49.717206  11, 0x0, sum = 3

  961 16:43:49.717291  12, 0x0, sum = 4

  962 16:43:49.720152  best_step = 10

  963 16:43:49.720235  

  964 16:43:49.720301  ==

  965 16:43:49.723746  Dram Type= 6, Freq= 0, CH_0, rank 0

  966 16:43:49.726533  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  967 16:43:49.726627  ==

  968 16:43:49.730054  RX Vref Scan: 1

  969 16:43:49.730139  

  970 16:43:49.730205  Set Vref Range= 32 -> 127

  971 16:43:49.730269  

  972 16:43:49.733566  RX Vref 32 -> 127, step: 1

  973 16:43:49.733639  

  974 16:43:49.736928  RX Delay -95 -> 252, step: 8

  975 16:43:49.737017  

  976 16:43:49.740402  Set Vref, RX VrefLevel [Byte0]: 32

  977 16:43:49.743223                           [Byte1]: 32

  978 16:43:49.743307  

  979 16:43:49.747078  Set Vref, RX VrefLevel [Byte0]: 33

  980 16:43:49.750494                           [Byte1]: 33

  981 16:43:49.750581  

  982 16:43:49.753967  Set Vref, RX VrefLevel [Byte0]: 34

  983 16:43:49.757310                           [Byte1]: 34

  984 16:43:49.760937  

  985 16:43:49.761058  Set Vref, RX VrefLevel [Byte0]: 35

  986 16:43:49.764556                           [Byte1]: 35

  987 16:43:49.768561  

  988 16:43:49.768694  Set Vref, RX VrefLevel [Byte0]: 36

  989 16:43:49.772099                           [Byte1]: 36

  990 16:43:49.776091  

  991 16:43:49.776169  Set Vref, RX VrefLevel [Byte0]: 37

  992 16:43:49.779470                           [Byte1]: 37

  993 16:43:49.784278  

  994 16:43:49.784358  Set Vref, RX VrefLevel [Byte0]: 38

  995 16:43:49.787711                           [Byte1]: 38

  996 16:43:49.791719  

  997 16:43:49.791827  Set Vref, RX VrefLevel [Byte0]: 39

  998 16:43:49.794766                           [Byte1]: 39

  999 16:43:49.799292  

 1000 16:43:49.799407  Set Vref, RX VrefLevel [Byte0]: 40

 1001 16:43:49.802855                           [Byte1]: 40

 1002 16:43:49.806976  

 1003 16:43:49.807086  Set Vref, RX VrefLevel [Byte0]: 41

 1004 16:43:49.809851                           [Byte1]: 41

 1005 16:43:49.814430  

 1006 16:43:49.814562  Set Vref, RX VrefLevel [Byte0]: 42

 1007 16:43:49.817494                           [Byte1]: 42

 1008 16:43:49.821456  

 1009 16:43:49.821551  Set Vref, RX VrefLevel [Byte0]: 43

 1010 16:43:49.825182                           [Byte1]: 43

 1011 16:43:49.829190  

 1012 16:43:49.829274  Set Vref, RX VrefLevel [Byte0]: 44

 1013 16:43:49.832461                           [Byte1]: 44

 1014 16:43:49.837306  

 1015 16:43:49.837441  Set Vref, RX VrefLevel [Byte0]: 45

 1016 16:43:49.840359                           [Byte1]: 45

 1017 16:43:49.844906  

 1018 16:43:49.845011  Set Vref, RX VrefLevel [Byte0]: 46

 1019 16:43:49.851021                           [Byte1]: 46

 1020 16:43:49.851119  

 1021 16:43:49.854552  Set Vref, RX VrefLevel [Byte0]: 47

 1022 16:43:49.857486                           [Byte1]: 47

 1023 16:43:49.857571  

 1024 16:43:49.861206  Set Vref, RX VrefLevel [Byte0]: 48

 1025 16:43:49.864281                           [Byte1]: 48

 1026 16:43:49.864364  

 1027 16:43:49.867596  Set Vref, RX VrefLevel [Byte0]: 49

 1028 16:43:49.871373                           [Byte1]: 49

 1029 16:43:49.874621  

 1030 16:43:49.874765  Set Vref, RX VrefLevel [Byte0]: 50

 1031 16:43:49.878573                           [Byte1]: 50

 1032 16:43:49.882596  

 1033 16:43:49.882695  Set Vref, RX VrefLevel [Byte0]: 51

 1034 16:43:49.885727                           [Byte1]: 51

 1035 16:43:49.889859  

 1036 16:43:49.889961  Set Vref, RX VrefLevel [Byte0]: 52

 1037 16:43:49.893228                           [Byte1]: 52

 1038 16:43:49.897431  

 1039 16:43:49.897554  Set Vref, RX VrefLevel [Byte0]: 53

 1040 16:43:49.901035                           [Byte1]: 53

 1041 16:43:49.905053  

 1042 16:43:49.905190  Set Vref, RX VrefLevel [Byte0]: 54

 1043 16:43:49.908727                           [Byte1]: 54

 1044 16:43:49.912732  

 1045 16:43:49.912890  Set Vref, RX VrefLevel [Byte0]: 55

 1046 16:43:49.916245                           [Byte1]: 55

 1047 16:43:49.920407  

 1048 16:43:49.920606  Set Vref, RX VrefLevel [Byte0]: 56

 1049 16:43:49.923933                           [Byte1]: 56

 1050 16:43:49.928093  

 1051 16:43:49.928596  Set Vref, RX VrefLevel [Byte0]: 57

 1052 16:43:49.931576                           [Byte1]: 57

 1053 16:43:49.935521  

 1054 16:43:49.935629  Set Vref, RX VrefLevel [Byte0]: 58

 1055 16:43:49.938820                           [Byte1]: 58

 1056 16:43:49.943460  

 1057 16:43:49.943543  Set Vref, RX VrefLevel [Byte0]: 59

 1058 16:43:49.946286                           [Byte1]: 59

 1059 16:43:49.950666  

 1060 16:43:49.950774  Set Vref, RX VrefLevel [Byte0]: 60

 1061 16:43:49.954349                           [Byte1]: 60

 1062 16:43:49.958137  

 1063 16:43:49.958219  Set Vref, RX VrefLevel [Byte0]: 61

 1064 16:43:49.961606                           [Byte1]: 61

 1065 16:43:49.966065  

 1066 16:43:49.966176  Set Vref, RX VrefLevel [Byte0]: 62

 1067 16:43:49.969446                           [Byte1]: 62

 1068 16:43:49.974138  

 1069 16:43:49.974270  Set Vref, RX VrefLevel [Byte0]: 63

 1070 16:43:49.977009                           [Byte1]: 63

 1071 16:43:49.980960  

 1072 16:43:49.981034  Set Vref, RX VrefLevel [Byte0]: 64

 1073 16:43:49.984907                           [Byte1]: 64

 1074 16:43:49.988869  

 1075 16:43:49.988957  Set Vref, RX VrefLevel [Byte0]: 65

 1076 16:43:49.992511                           [Byte1]: 65

 1077 16:43:49.996370  

 1078 16:43:49.996464  Set Vref, RX VrefLevel [Byte0]: 66

 1079 16:43:49.999999                           [Byte1]: 66

 1080 16:43:50.004338  

 1081 16:43:50.004452  Set Vref, RX VrefLevel [Byte0]: 67

 1082 16:43:50.007139                           [Byte1]: 67

 1083 16:43:50.011885  

 1084 16:43:50.012046  Set Vref, RX VrefLevel [Byte0]: 68

 1085 16:43:50.014830                           [Byte1]: 68

 1086 16:43:50.019481  

 1087 16:43:50.019672  Set Vref, RX VrefLevel [Byte0]: 69

 1088 16:43:50.022473                           [Byte1]: 69

 1089 16:43:50.027106  

 1090 16:43:50.027241  Set Vref, RX VrefLevel [Byte0]: 70

 1091 16:43:50.029942                           [Byte1]: 70

 1092 16:43:50.034774  

 1093 16:43:50.034914  Set Vref, RX VrefLevel [Byte0]: 71

 1094 16:43:50.037474                           [Byte1]: 71

 1095 16:43:50.042117  

 1096 16:43:50.042274  Set Vref, RX VrefLevel [Byte0]: 72

 1097 16:43:50.044993                           [Byte1]: 72

 1098 16:43:50.049491  

 1099 16:43:50.049626  Set Vref, RX VrefLevel [Byte0]: 73

 1100 16:43:50.052899                           [Byte1]: 73

 1101 16:43:50.057153  

 1102 16:43:50.057289  Set Vref, RX VrefLevel [Byte0]: 74

 1103 16:43:50.060408                           [Byte1]: 74

 1104 16:43:50.064867  

 1105 16:43:50.065020  Set Vref, RX VrefLevel [Byte0]: 75

 1106 16:43:50.068247                           [Byte1]: 75

 1107 16:43:50.072227  

 1108 16:43:50.072428  Final RX Vref Byte 0 = 63 to rank0

 1109 16:43:50.075790  Final RX Vref Byte 1 = 58 to rank0

 1110 16:43:50.079377  Final RX Vref Byte 0 = 63 to rank1

 1111 16:43:50.083347  Final RX Vref Byte 1 = 58 to rank1==

 1112 16:43:50.085947  Dram Type= 6, Freq= 0, CH_0, rank 0

 1113 16:43:50.092648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1114 16:43:50.093079  ==

 1115 16:43:50.093463  DQS Delay:

 1116 16:43:50.093806  DQS0 = 0, DQS1 = 0

 1117 16:43:50.096215  DQM Delay:

 1118 16:43:50.096697  DQM0 = 87, DQM1 = 79

 1119 16:43:50.099732  DQ Delay:

 1120 16:43:50.102448  DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84

 1121 16:43:50.102887  DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96

 1122 16:43:50.105881  DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76

 1123 16:43:50.109640  DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88

 1124 16:43:50.112622  

 1125 16:43:50.113044  

 1126 16:43:50.119601  [DQSOSCAuto] RK0, (LSB)MR18= 0x2d13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 398 ps

 1127 16:43:50.122998  CH0 RK0: MR19=606, MR18=2D13

 1128 16:43:50.129065  CH0_RK0: MR19=0x606, MR18=0x2D13, DQSOSC=398, MR23=63, INC=93, DEC=62

 1129 16:43:50.129366  

 1130 16:43:50.132628  ----->DramcWriteLeveling(PI) begin...

 1131 16:43:50.132932  ==

 1132 16:43:50.136129  Dram Type= 6, Freq= 0, CH_0, rank 1

 1133 16:43:50.139630  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1134 16:43:50.140017  ==

 1135 16:43:50.142562  Write leveling (Byte 0): 31 => 31

 1136 16:43:50.146095  Write leveling (Byte 1): 28 => 28

 1137 16:43:50.149515  DramcWriteLeveling(PI) end<-----

 1138 16:43:50.149826  

 1139 16:43:50.150087  ==

 1140 16:43:50.153240  Dram Type= 6, Freq= 0, CH_0, rank 1

 1141 16:43:50.156357  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1142 16:43:50.156673  ==

 1143 16:43:50.159242  [Gating] SW mode calibration

 1144 16:43:50.166261  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1145 16:43:50.172822  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1146 16:43:50.175990   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1147 16:43:50.179640   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1148 16:43:50.185872   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1149 16:43:50.189386   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1150 16:43:50.192870   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1151 16:43:50.236543   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1152 16:43:50.237259   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1153 16:43:50.238199   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1154 16:43:50.238745   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1155 16:43:50.239280   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1156 16:43:50.239881   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1157 16:43:50.240325   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1158 16:43:50.240726   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1159 16:43:50.241109   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1160 16:43:50.241444   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1161 16:43:50.241895   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 16:43:50.245535   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 16:43:50.251748   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)

 1164 16:43:50.255484   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)

 1165 16:43:50.258591   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 16:43:50.265257   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 16:43:50.268862   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 16:43:50.272067   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 16:43:50.278909   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 16:43:50.282234   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 16:43:50.285180   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 16:43:50.291923   0  9  8 | B1->B0 | 2323 3030 | 0 1 | (1 1) (1 1)

 1173 16:43:50.295609   0  9 12 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)

 1174 16:43:50.298381   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1175 16:43:50.301969   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1176 16:43:50.308447   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1177 16:43:50.311850   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1178 16:43:50.314835   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1179 16:43:50.321872   0 10  4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 1180 16:43:50.325382   0 10  8 | B1->B0 | 2f2f 2525 | 1 0 | (1 0) (0 0)

 1181 16:43:50.328656   0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)

 1182 16:43:50.335081   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1183 16:43:50.338378   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1184 16:43:50.342211   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1185 16:43:50.348280   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1186 16:43:50.351719   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1187 16:43:50.354715   0 11  4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

 1188 16:43:50.362263   0 11  8 | B1->B0 | 2828 3d3d | 0 0 | (0 0) (0 0)

 1189 16:43:50.365730   0 11 12 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)

 1190 16:43:50.369015   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1191 16:43:50.373054   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1192 16:43:50.379845   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1193 16:43:50.383328   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1194 16:43:50.386642   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1195 16:43:50.390745   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1196 16:43:50.394157   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 1197 16:43:50.400636   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1198 16:43:50.404750   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1199 16:43:50.407484   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1200 16:43:50.414031   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1201 16:43:50.417461   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1202 16:43:50.420703   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1203 16:43:50.427374   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1204 16:43:50.430964   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1205 16:43:50.434180   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1206 16:43:50.441177   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1207 16:43:50.444370   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1208 16:43:50.448069   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 16:43:50.454133   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 16:43:50.457643   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 16:43:50.461094   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1212 16:43:50.467424   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1213 16:43:50.467893  Total UI for P1: 0, mck2ui 16

 1214 16:43:50.471285  best dqsien dly found for B0: ( 0, 14,  4)

 1215 16:43:50.477591   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1216 16:43:50.481003  Total UI for P1: 0, mck2ui 16

 1217 16:43:50.484278  best dqsien dly found for B1: ( 0, 14,  8)

 1218 16:43:50.487523  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1219 16:43:50.490782  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1220 16:43:50.491231  

 1221 16:43:50.494131  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1222 16:43:50.497453  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1223 16:43:50.501048  [Gating] SW calibration Done

 1224 16:43:50.501477  ==

 1225 16:43:50.504435  Dram Type= 6, Freq= 0, CH_0, rank 1

 1226 16:43:50.507850  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1227 16:43:50.508458  ==

 1228 16:43:50.511013  RX Vref Scan: 0

 1229 16:43:50.511444  

 1230 16:43:50.511788  RX Vref 0 -> 0, step: 1

 1231 16:43:50.512238  

 1232 16:43:50.514529  RX Delay -130 -> 252, step: 16

 1233 16:43:50.520878  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1234 16:43:50.524310  iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240

 1235 16:43:50.527901  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1236 16:43:50.531450  iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256

 1237 16:43:50.534312  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1238 16:43:50.537879  iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240

 1239 16:43:50.544294  iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256

 1240 16:43:50.547305  iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240

 1241 16:43:50.550913  iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224

 1242 16:43:50.554633  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

 1243 16:43:50.557629  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1244 16:43:50.564027  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1245 16:43:50.567346  iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240

 1246 16:43:50.570988  iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256

 1247 16:43:50.574425  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1248 16:43:50.580781  iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256

 1249 16:43:50.581208  ==

 1250 16:43:50.584280  Dram Type= 6, Freq= 0, CH_0, rank 1

 1251 16:43:50.587409  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1252 16:43:50.587838  ==

 1253 16:43:50.588263  DQS Delay:

 1254 16:43:50.590734  DQS0 = 0, DQS1 = 0

 1255 16:43:50.591159  DQM Delay:

 1256 16:43:50.594269  DQM0 = 83, DQM1 = 72

 1257 16:43:50.594694  DQ Delay:

 1258 16:43:50.597389  DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77

 1259 16:43:50.601010  DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85

 1260 16:43:50.604463  DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69

 1261 16:43:50.607292  DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77

 1262 16:43:50.607847  

 1263 16:43:50.608387  

 1264 16:43:50.608845  ==

 1265 16:43:50.610786  Dram Type= 6, Freq= 0, CH_0, rank 1

 1266 16:43:50.614291  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1267 16:43:50.614787  ==

 1268 16:43:50.615135  

 1269 16:43:50.615453  

 1270 16:43:50.617786  	TX Vref Scan disable

 1271 16:43:50.620857   == TX Byte 0 ==

 1272 16:43:50.624120  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

 1273 16:43:50.627450  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

 1274 16:43:50.630999   == TX Byte 1 ==

 1275 16:43:50.634630  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1276 16:43:50.637689  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1277 16:43:50.638113  ==

 1278 16:43:50.641156  Dram Type= 6, Freq= 0, CH_0, rank 1

 1279 16:43:50.643947  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1280 16:43:50.647489  ==

 1281 16:43:50.659116  TX Vref=22, minBit 0, minWin=27, winSum=444

 1282 16:43:50.662756  TX Vref=24, minBit 12, minWin=27, winSum=448

 1283 16:43:50.666054  TX Vref=26, minBit 9, minWin=27, winSum=451

 1284 16:43:50.669037  TX Vref=28, minBit 3, minWin=27, winSum=454

 1285 16:43:50.672436  TX Vref=30, minBit 2, minWin=28, winSum=457

 1286 16:43:50.679443  TX Vref=32, minBit 12, minWin=27, winSum=456

 1287 16:43:50.682754  [TxChooseVref] Worse bit 2, Min win 28, Win sum 457, Final Vref 30

 1288 16:43:50.683306  

 1289 16:43:50.685877  Final TX Range 1 Vref 30

 1290 16:43:50.686297  

 1291 16:43:50.686678  ==

 1292 16:43:50.689603  Dram Type= 6, Freq= 0, CH_0, rank 1

 1293 16:43:50.692481  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1294 16:43:50.692948  ==

 1295 16:43:50.696038  

 1296 16:43:50.696628  

 1297 16:43:50.697008  	TX Vref Scan disable

 1298 16:43:50.699293   == TX Byte 0 ==

 1299 16:43:50.702672  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

 1300 16:43:50.709370  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

 1301 16:43:50.710014   == TX Byte 1 ==

 1302 16:43:50.712238  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1303 16:43:50.719165  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1304 16:43:50.719475  

 1305 16:43:50.719709  [DATLAT]

 1306 16:43:50.720045  Freq=800, CH0 RK1

 1307 16:43:50.720314  

 1308 16:43:50.722754  DATLAT Default: 0xa

 1309 16:43:50.723108  0, 0xFFFF, sum = 0

 1310 16:43:50.726182  1, 0xFFFF, sum = 0

 1311 16:43:50.726538  2, 0xFFFF, sum = 0

 1312 16:43:50.729104  3, 0xFFFF, sum = 0

 1313 16:43:50.729483  4, 0xFFFF, sum = 0

 1314 16:43:50.732428  5, 0xFFFF, sum = 0

 1315 16:43:50.736084  6, 0xFFFF, sum = 0

 1316 16:43:50.736442  7, 0xFFFF, sum = 0

 1317 16:43:50.739489  8, 0xFFFF, sum = 0

 1318 16:43:50.740027  9, 0x0, sum = 1

 1319 16:43:50.740396  10, 0x0, sum = 2

 1320 16:43:50.742419  11, 0x0, sum = 3

 1321 16:43:50.742760  12, 0x0, sum = 4

 1322 16:43:50.745972  best_step = 10

 1323 16:43:50.746293  

 1324 16:43:50.746581  ==

 1325 16:43:50.749530  Dram Type= 6, Freq= 0, CH_0, rank 1

 1326 16:43:50.752807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1327 16:43:50.753131  ==

 1328 16:43:50.755952  RX Vref Scan: 0

 1329 16:43:50.756323  

 1330 16:43:50.756640  RX Vref 0 -> 0, step: 1

 1331 16:43:50.756902  

 1332 16:43:50.758759  RX Delay -95 -> 252, step: 8

 1333 16:43:50.766257  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1334 16:43:50.769241  iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224

 1335 16:43:50.772790  iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232

 1336 16:43:50.776432  iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232

 1337 16:43:50.779626  iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224

 1338 16:43:50.785681  iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232

 1339 16:43:50.789260  iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224

 1340 16:43:50.792734  iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224

 1341 16:43:50.796017  iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216

 1342 16:43:50.799283  iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216

 1343 16:43:50.806131  iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224

 1344 16:43:50.809812  iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216

 1345 16:43:50.812504  iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216

 1346 16:43:50.815882  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1347 16:43:50.819371  iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224

 1348 16:43:50.825888  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 1349 16:43:50.826280  ==

 1350 16:43:50.829524  Dram Type= 6, Freq= 0, CH_0, rank 1

 1351 16:43:50.832386  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1352 16:43:50.832752  ==

 1353 16:43:50.833128  DQS Delay:

 1354 16:43:50.836107  DQS0 = 0, DQS1 = 0

 1355 16:43:50.836494  DQM Delay:

 1356 16:43:50.839202  DQM0 = 87, DQM1 = 78

 1357 16:43:50.839605  DQ Delay:

 1358 16:43:50.842669  DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84

 1359 16:43:50.846211  DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96

 1360 16:43:50.849140  DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68

 1361 16:43:50.852623  DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88

 1362 16:43:50.852997  

 1363 16:43:50.853347  

 1364 16:43:50.859093  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps

 1365 16:43:50.862637  CH0 RK1: MR19=606, MR18=2D16

 1366 16:43:50.869031  CH0_RK1: MR19=0x606, MR18=0x2D16, DQSOSC=398, MR23=63, INC=93, DEC=62

 1367 16:43:50.872470  [RxdqsGatingPostProcess] freq 800

 1368 16:43:50.879592  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1369 16:43:50.882647  Pre-setting of DQS Precalculation

 1370 16:43:50.886132  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1371 16:43:50.886551  ==

 1372 16:43:50.889582  Dram Type= 6, Freq= 0, CH_1, rank 0

 1373 16:43:50.893001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1374 16:43:50.893467  ==

 1375 16:43:50.899205  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1376 16:43:50.905905  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1377 16:43:50.914575  [CA 0] Center 36 (6~66) winsize 61

 1378 16:43:50.917869  [CA 1] Center 36 (6~66) winsize 61

 1379 16:43:50.920978  [CA 2] Center 34 (4~64) winsize 61

 1380 16:43:50.924421  [CA 3] Center 33 (3~64) winsize 62

 1381 16:43:50.927723  [CA 4] Center 34 (4~65) winsize 62

 1382 16:43:50.930740  [CA 5] Center 33 (3~64) winsize 62

 1383 16:43:50.931234  

 1384 16:43:50.934160  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1385 16:43:50.934718  

 1386 16:43:50.938128  [CATrainingPosCal] consider 1 rank data

 1387 16:43:50.940902  u2DelayCellTimex100 = 270/100 ps

 1388 16:43:50.944519  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1389 16:43:50.947442  CA1 delay=36 (6~66),Diff = 3 PI (21 cell)

 1390 16:43:50.954572  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1391 16:43:50.957520  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1392 16:43:50.961245  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1393 16:43:50.964239  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1394 16:43:50.964663  

 1395 16:43:50.967769  CA PerBit enable=1, Macro0, CA PI delay=33

 1396 16:43:50.968302  

 1397 16:43:50.971122  [CBTSetCACLKResult] CA Dly = 33

 1398 16:43:50.971994  CS Dly: 4 (0~35)

 1399 16:43:50.972512  ==

 1400 16:43:50.974559  Dram Type= 6, Freq= 0, CH_1, rank 1

 1401 16:43:50.981079  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1402 16:43:50.981506  ==

 1403 16:43:50.984610  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1404 16:43:50.990979  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1405 16:43:51.000327  [CA 0] Center 36 (6~66) winsize 61

 1406 16:43:51.003762  [CA 1] Center 36 (6~66) winsize 61

 1407 16:43:51.007761  [CA 2] Center 34 (4~64) winsize 61

 1408 16:43:51.010441  [CA 3] Center 33 (3~64) winsize 62

 1409 16:43:51.013541  [CA 4] Center 34 (4~65) winsize 62

 1410 16:43:51.016979  [CA 5] Center 33 (3~64) winsize 62

 1411 16:43:51.017487  

 1412 16:43:51.020444  [CmdBusTrainingLP45] Vref(ca) range 1: 30

 1413 16:43:51.020867  

 1414 16:43:51.023322  [CATrainingPosCal] consider 2 rank data

 1415 16:43:51.026888  u2DelayCellTimex100 = 270/100 ps

 1416 16:43:51.030926  CA0 delay=36 (6~66),Diff = 3 PI (21 cell)

 1417 16:43:51.034570  CA1 delay=36 (6~66),Diff = 3 PI (21 cell)

 1418 16:43:51.037903  CA2 delay=34 (4~64),Diff = 1 PI (7 cell)

 1419 16:43:51.041545  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 1420 16:43:51.044827  CA4 delay=34 (4~65),Diff = 1 PI (7 cell)

 1421 16:43:51.049089  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 1422 16:43:51.049514  

 1423 16:43:51.052588  CA PerBit enable=1, Macro0, CA PI delay=33

 1424 16:43:51.053038  

 1425 16:43:51.056093  [CBTSetCACLKResult] CA Dly = 33

 1426 16:43:51.060074  CS Dly: 5 (0~37)

 1427 16:43:51.060514  

 1428 16:43:51.060859  ----->DramcWriteLeveling(PI) begin...

 1429 16:43:51.064354  ==

 1430 16:43:51.064781  Dram Type= 6, Freq= 0, CH_1, rank 0

 1431 16:43:51.070901  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1432 16:43:51.071331  ==

 1433 16:43:51.074465  Write leveling (Byte 0): 26 => 26

 1434 16:43:51.075035  Write leveling (Byte 1): 29 => 29

 1435 16:43:51.077785  DramcWriteLeveling(PI) end<-----

 1436 16:43:51.078286  

 1437 16:43:51.080967  ==

 1438 16:43:51.081392  Dram Type= 6, Freq= 0, CH_1, rank 0

 1439 16:43:51.087662  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1440 16:43:51.088129  ==

 1441 16:43:51.090707  [Gating] SW mode calibration

 1442 16:43:51.097544  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1443 16:43:51.100892  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1444 16:43:51.107328   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1445 16:43:51.110414   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1446 16:43:51.114041   0  6  8 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)

 1447 16:43:51.120919   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1448 16:43:51.124401   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1449 16:43:51.127051   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1450 16:43:51.133952   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1451 16:43:51.137525   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1452 16:43:51.140616   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1453 16:43:51.143913   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1454 16:43:51.150497   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1455 16:43:51.154042   0  7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1456 16:43:51.156988   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1457 16:43:51.164239   0  7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1458 16:43:51.167205   0  7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1459 16:43:51.170565   0  7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1460 16:43:51.176917   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 16:43:51.180350   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1462 16:43:51.183614   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1463 16:43:51.190281   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 16:43:51.193759   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1465 16:43:51.197044   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 16:43:51.204195   0  8 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1467 16:43:51.207103   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 16:43:51.210742   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 16:43:51.217039   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 16:43:51.220477   0  9  8 | B1->B0 | 2525 2626 | 0 0 | (0 0) (0 0)

 1471 16:43:51.224018   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1472 16:43:51.230333   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1473 16:43:51.233719   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1474 16:43:51.237121   0  9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1475 16:43:51.240460   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1476 16:43:51.247097   0 10  0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 1477 16:43:51.250403   0 10  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1478 16:43:51.253869   0 10  8 | B1->B0 | 2a2a 2f2f | 0 1 | (0 0) (1 0)

 1479 16:43:51.261155   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 1480 16:43:51.263993   0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1481 16:43:51.267600   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1482 16:43:51.273894   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1483 16:43:51.277559   0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1484 16:43:51.280242   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1485 16:43:51.287173   0 11  4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)

 1486 16:43:51.290809   0 11  8 | B1->B0 | 3131 3131 | 0 0 | (0 0) (0 0)

 1487 16:43:51.293620   0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 1488 16:43:51.300662   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1489 16:43:51.304192   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1490 16:43:51.306978   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1491 16:43:51.313817   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1492 16:43:51.317192   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1493 16:43:51.320616   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1494 16:43:51.327132   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1495 16:43:51.330790   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1496 16:43:51.334104   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1497 16:43:51.337340   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1498 16:43:51.344049   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1499 16:43:51.347369   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1500 16:43:51.350180   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1501 16:43:51.357355   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1502 16:43:51.360773   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1503 16:43:51.364020   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1504 16:43:51.370626   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1505 16:43:51.374070   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1506 16:43:51.377028   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 16:43:51.383945   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 16:43:51.387448   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 16:43:51.390349   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1510 16:43:51.397358   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1511 16:43:51.397800  Total UI for P1: 0, mck2ui 16

 1512 16:43:51.404375  best dqsien dly found for B0: ( 0, 14,  4)

 1513 16:43:51.407642   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1514 16:43:51.410655  Total UI for P1: 0, mck2ui 16

 1515 16:43:51.413565  best dqsien dly found for B1: ( 0, 14,  8)

 1516 16:43:51.416896  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1517 16:43:51.420470  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1518 16:43:51.420555  

 1519 16:43:51.423735  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1520 16:43:51.427256  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1521 16:43:51.430075  [Gating] SW calibration Done

 1522 16:43:51.430160  ==

 1523 16:43:51.433621  Dram Type= 6, Freq= 0, CH_1, rank 0

 1524 16:43:51.436946  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1525 16:43:51.437032  ==

 1526 16:43:51.440460  RX Vref Scan: 0

 1527 16:43:51.440545  

 1528 16:43:51.443984  RX Vref 0 -> 0, step: 1

 1529 16:43:51.444085  

 1530 16:43:51.444172  RX Delay -130 -> 252, step: 16

 1531 16:43:51.450477  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

 1532 16:43:51.453881  iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224

 1533 16:43:51.456865  iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240

 1534 16:43:51.460234  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1535 16:43:51.463623  iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240

 1536 16:43:51.470073  iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240

 1537 16:43:51.473854  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1538 16:43:51.476705  iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224

 1539 16:43:51.480327  iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256

 1540 16:43:51.483944  iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224

 1541 16:43:51.490133  iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240

 1542 16:43:51.493743  iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240

 1543 16:43:51.497138  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1544 16:43:51.500001  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1545 16:43:51.503568  iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240

 1546 16:43:51.510545  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1547 16:43:51.510628  ==

 1548 16:43:51.513464  Dram Type= 6, Freq= 0, CH_1, rank 0

 1549 16:43:51.516990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1550 16:43:51.517074  ==

 1551 16:43:51.517141  DQS Delay:

 1552 16:43:51.520416  DQS0 = 0, DQS1 = 0

 1553 16:43:51.520499  DQM Delay:

 1554 16:43:51.523716  DQM0 = 84, DQM1 = 75

 1555 16:43:51.523799  DQ Delay:

 1556 16:43:51.527238  DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85

 1557 16:43:51.530102  DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77

 1558 16:43:51.533426  DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69

 1559 16:43:51.536898  DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85

 1560 16:43:51.536983  

 1561 16:43:51.537068  

 1562 16:43:51.537149  ==

 1563 16:43:51.540314  Dram Type= 6, Freq= 0, CH_1, rank 0

 1564 16:43:51.543861  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1565 16:43:51.543949  ==

 1566 16:43:51.546868  

 1567 16:43:51.546953  

 1568 16:43:51.547038  	TX Vref Scan disable

 1569 16:43:51.550439   == TX Byte 0 ==

 1570 16:43:51.553873  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1571 16:43:51.557348  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1572 16:43:51.560162   == TX Byte 1 ==

 1573 16:43:51.563740  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1574 16:43:51.567136  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1575 16:43:51.567222  ==

 1576 16:43:51.569974  Dram Type= 6, Freq= 0, CH_1, rank 0

 1577 16:43:51.576942  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1578 16:43:51.577029  ==

 1579 16:43:51.589303  TX Vref=22, minBit 11, minWin=26, winSum=437

 1580 16:43:51.592221  TX Vref=24, minBit 0, minWin=27, winSum=439

 1581 16:43:51.595785  TX Vref=26, minBit 0, minWin=27, winSum=445

 1582 16:43:51.598771  TX Vref=28, minBit 0, minWin=27, winSum=449

 1583 16:43:51.602097  TX Vref=30, minBit 1, minWin=28, winSum=456

 1584 16:43:51.605711  TX Vref=32, minBit 1, minWin=28, winSum=454

 1585 16:43:51.612138  [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 30

 1586 16:43:51.612224  

 1587 16:43:51.615757  Final TX Range 1 Vref 30

 1588 16:43:51.615843  

 1589 16:43:51.615950  ==

 1590 16:43:51.618968  Dram Type= 6, Freq= 0, CH_1, rank 0

 1591 16:43:51.622437  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1592 16:43:51.622523  ==

 1593 16:43:51.622609  

 1594 16:43:51.622690  

 1595 16:43:51.625795  	TX Vref Scan disable

 1596 16:43:51.629200   == TX Byte 0 ==

 1597 16:43:51.632612  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1598 16:43:51.635834  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1599 16:43:51.639114   == TX Byte 1 ==

 1600 16:43:51.642658  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1601 16:43:51.646042  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1602 16:43:51.646129  

 1603 16:43:51.649038  [DATLAT]

 1604 16:43:51.649124  Freq=800, CH1 RK0

 1605 16:43:51.649210  

 1606 16:43:51.652591  DATLAT Default: 0xa

 1607 16:43:51.652677  0, 0xFFFF, sum = 0

 1608 16:43:51.656127  1, 0xFFFF, sum = 0

 1609 16:43:51.656214  2, 0xFFFF, sum = 0

 1610 16:43:51.659456  3, 0xFFFF, sum = 0

 1611 16:43:51.659543  4, 0xFFFF, sum = 0

 1612 16:43:51.662444  5, 0xFFFF, sum = 0

 1613 16:43:51.662524  6, 0xFFFF, sum = 0

 1614 16:43:51.666017  7, 0xFFFF, sum = 0

 1615 16:43:51.666104  8, 0x0, sum = 1

 1616 16:43:51.669473  9, 0x0, sum = 2

 1617 16:43:51.669566  10, 0x0, sum = 3

 1618 16:43:51.672770  11, 0x0, sum = 4

 1619 16:43:51.672857  best_step = 9

 1620 16:43:51.672942  

 1621 16:43:51.673023  ==

 1622 16:43:51.676321  Dram Type= 6, Freq= 0, CH_1, rank 0

 1623 16:43:51.679089  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1624 16:43:51.682572  ==

 1625 16:43:51.682657  RX Vref Scan: 1

 1626 16:43:51.682742  

 1627 16:43:51.686208  Set Vref Range= 32 -> 127

 1628 16:43:51.686293  

 1629 16:43:51.686397  RX Vref 32 -> 127, step: 1

 1630 16:43:51.689723  

 1631 16:43:51.689807  RX Delay -111 -> 252, step: 8

 1632 16:43:51.689911  

 1633 16:43:51.692555  Set Vref, RX VrefLevel [Byte0]: 32

 1634 16:43:51.696173                           [Byte1]: 32

 1635 16:43:51.699716  

 1636 16:43:51.699800  Set Vref, RX VrefLevel [Byte0]: 33

 1637 16:43:51.702850                           [Byte1]: 33

 1638 16:43:51.707254  

 1639 16:43:51.707342  Set Vref, RX VrefLevel [Byte0]: 34

 1640 16:43:51.710915                           [Byte1]: 34

 1641 16:43:51.715287  

 1642 16:43:51.715373  Set Vref, RX VrefLevel [Byte0]: 35

 1643 16:43:51.718654                           [Byte1]: 35

 1644 16:43:51.722932  

 1645 16:43:51.723026  Set Vref, RX VrefLevel [Byte0]: 36

 1646 16:43:51.726473                           [Byte1]: 36

 1647 16:43:51.730198  

 1648 16:43:51.730282  Set Vref, RX VrefLevel [Byte0]: 37

 1649 16:43:51.733681                           [Byte1]: 37

 1650 16:43:51.737925  

 1651 16:43:51.738033  Set Vref, RX VrefLevel [Byte0]: 38

 1652 16:43:51.741224                           [Byte1]: 38

 1653 16:43:51.745923  

 1654 16:43:51.746030  Set Vref, RX VrefLevel [Byte0]: 39

 1655 16:43:51.748784                           [Byte1]: 39

 1656 16:43:51.753354  

 1657 16:43:51.753428  Set Vref, RX VrefLevel [Byte0]: 40

 1658 16:43:51.756445                           [Byte1]: 40

 1659 16:43:51.761261  

 1660 16:43:51.761331  Set Vref, RX VrefLevel [Byte0]: 41

 1661 16:43:51.764563                           [Byte1]: 41

 1662 16:43:51.768613  

 1663 16:43:51.768692  Set Vref, RX VrefLevel [Byte0]: 42

 1664 16:43:51.772149                           [Byte1]: 42

 1665 16:43:51.776387  

 1666 16:43:51.776472  Set Vref, RX VrefLevel [Byte0]: 43

 1667 16:43:51.779853                           [Byte1]: 43

 1668 16:43:51.784016  

 1669 16:43:51.784092  Set Vref, RX VrefLevel [Byte0]: 44

 1670 16:43:51.787036                           [Byte1]: 44

 1671 16:43:51.791699  

 1672 16:43:51.791772  Set Vref, RX VrefLevel [Byte0]: 45

 1673 16:43:51.794634                           [Byte1]: 45

 1674 16:43:51.799473  

 1675 16:43:51.799547  Set Vref, RX VrefLevel [Byte0]: 46

 1676 16:43:51.805476                           [Byte1]: 46

 1677 16:43:51.805564  

 1678 16:43:51.808920  Set Vref, RX VrefLevel [Byte0]: 47

 1679 16:43:51.812348                           [Byte1]: 47

 1680 16:43:51.812431  

 1681 16:43:51.815339  Set Vref, RX VrefLevel [Byte0]: 48

 1682 16:43:51.818896                           [Byte1]: 48

 1683 16:43:51.822172  

 1684 16:43:51.822254  Set Vref, RX VrefLevel [Byte0]: 49

 1685 16:43:51.825571                           [Byte1]: 49

 1686 16:43:51.829769  

 1687 16:43:51.829851  Set Vref, RX VrefLevel [Byte0]: 50

 1688 16:43:51.832985                           [Byte1]: 50

 1689 16:43:51.837399  

 1690 16:43:51.837487  Set Vref, RX VrefLevel [Byte0]: 51

 1691 16:43:51.840825                           [Byte1]: 51

 1692 16:43:51.845348  

 1693 16:43:51.845458  Set Vref, RX VrefLevel [Byte0]: 52

 1694 16:43:51.848763                           [Byte1]: 52

 1695 16:43:51.852723  

 1696 16:43:51.852823  Set Vref, RX VrefLevel [Byte0]: 53

 1697 16:43:51.856074                           [Byte1]: 53

 1698 16:43:51.860203  

 1699 16:43:51.860299  Set Vref, RX VrefLevel [Byte0]: 54

 1700 16:43:51.863670                           [Byte1]: 54

 1701 16:43:51.868367  

 1702 16:43:51.868468  Set Vref, RX VrefLevel [Byte0]: 55

 1703 16:43:51.871169                           [Byte1]: 55

 1704 16:43:51.876150  

 1705 16:43:51.876257  Set Vref, RX VrefLevel [Byte0]: 56

 1706 16:43:51.879227                           [Byte1]: 56

 1707 16:43:51.883138  

 1708 16:43:51.883240  Set Vref, RX VrefLevel [Byte0]: 57

 1709 16:43:51.886520                           [Byte1]: 57

 1710 16:43:51.891285  

 1711 16:43:51.891368  Set Vref, RX VrefLevel [Byte0]: 58

 1712 16:43:51.894227                           [Byte1]: 58

 1713 16:43:51.898864  

 1714 16:43:51.898947  Set Vref, RX VrefLevel [Byte0]: 59

 1715 16:43:51.901755                           [Byte1]: 59

 1716 16:43:51.906618  

 1717 16:43:51.906702  Set Vref, RX VrefLevel [Byte0]: 60

 1718 16:43:51.909546                           [Byte1]: 60

 1719 16:43:51.914042  

 1720 16:43:51.914125  Set Vref, RX VrefLevel [Byte0]: 61

 1721 16:43:51.917591                           [Byte1]: 61

 1722 16:43:51.921766  

 1723 16:43:51.921849  Set Vref, RX VrefLevel [Byte0]: 62

 1724 16:43:51.925194                           [Byte1]: 62

 1725 16:43:51.929366  

 1726 16:43:51.929449  Set Vref, RX VrefLevel [Byte0]: 63

 1727 16:43:51.932750                           [Byte1]: 63

 1728 16:43:51.936780  

 1729 16:43:51.936863  Set Vref, RX VrefLevel [Byte0]: 64

 1730 16:43:51.940126                           [Byte1]: 64

 1731 16:43:51.944522  

 1732 16:43:51.944639  Set Vref, RX VrefLevel [Byte0]: 65

 1733 16:43:51.948029                           [Byte1]: 65

 1734 16:43:51.952143  

 1735 16:43:51.952270  Set Vref, RX VrefLevel [Byte0]: 66

 1736 16:43:51.955453                           [Byte1]: 66

 1737 16:43:51.960106  

 1738 16:43:51.960189  Set Vref, RX VrefLevel [Byte0]: 67

 1739 16:43:51.963092                           [Byte1]: 67

 1740 16:43:51.967654  

 1741 16:43:51.967736  Set Vref, RX VrefLevel [Byte0]: 68

 1742 16:43:51.971157                           [Byte1]: 68

 1743 16:43:51.975202  

 1744 16:43:51.975285  Set Vref, RX VrefLevel [Byte0]: 69

 1745 16:43:51.978623                           [Byte1]: 69

 1746 16:43:51.982944  

 1747 16:43:51.983027  Set Vref, RX VrefLevel [Byte0]: 70

 1748 16:43:51.986315                           [Byte1]: 70

 1749 16:43:51.990569  

 1750 16:43:51.990652  Set Vref, RX VrefLevel [Byte0]: 71

 1751 16:43:51.993716                           [Byte1]: 71

 1752 16:43:51.997793  

 1753 16:43:51.997876  Set Vref, RX VrefLevel [Byte0]: 72

 1754 16:43:52.001344                           [Byte1]: 72

 1755 16:43:52.005620  

 1756 16:43:52.005706  Set Vref, RX VrefLevel [Byte0]: 73

 1757 16:43:52.009269                           [Byte1]: 73

 1758 16:43:52.013393  

 1759 16:43:52.013475  Set Vref, RX VrefLevel [Byte0]: 74

 1760 16:43:52.016953                           [Byte1]: 74

 1761 16:43:52.021278  

 1762 16:43:52.021361  Set Vref, RX VrefLevel [Byte0]: 75

 1763 16:43:52.024671                           [Byte1]: 75

 1764 16:43:52.028681  

 1765 16:43:52.028764  Set Vref, RX VrefLevel [Byte0]: 76

 1766 16:43:52.032254                           [Byte1]: 76

 1767 16:43:52.036363  

 1768 16:43:52.036447  Set Vref, RX VrefLevel [Byte0]: 77

 1769 16:43:52.039366                           [Byte1]: 77

 1770 16:43:52.043926  

 1771 16:43:52.044046  Set Vref, RX VrefLevel [Byte0]: 78

 1772 16:43:52.047277                           [Byte1]: 78

 1773 16:43:52.051910  

 1774 16:43:52.052031  Set Vref, RX VrefLevel [Byte0]: 79

 1775 16:43:52.054616                           [Byte1]: 79

 1776 16:43:52.059351  

 1777 16:43:52.059434  Set Vref, RX VrefLevel [Byte0]: 80

 1778 16:43:52.062736                           [Byte1]: 80

 1779 16:43:52.066944  

 1780 16:43:52.067027  Final RX Vref Byte 0 = 61 to rank0

 1781 16:43:52.070250  Final RX Vref Byte 1 = 59 to rank0

 1782 16:43:52.073675  Final RX Vref Byte 0 = 61 to rank1

 1783 16:43:52.076964  Final RX Vref Byte 1 = 59 to rank1==

 1784 16:43:52.080448  Dram Type= 6, Freq= 0, CH_1, rank 0

 1785 16:43:52.086831  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1786 16:43:52.086915  ==

 1787 16:43:52.086982  DQS Delay:

 1788 16:43:52.087044  DQS0 = 0, DQS1 = 0

 1789 16:43:52.090292  DQM Delay:

 1790 16:43:52.090375  DQM0 = 84, DQM1 = 74

 1791 16:43:52.093618  DQ Delay:

 1792 16:43:52.097065  DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84

 1793 16:43:52.097148  DQ4 =84, DQ5 =92, DQ6 =96, DQ7 =80

 1794 16:43:52.099952  DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72

 1795 16:43:52.103483  DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76

 1796 16:43:52.107091  

 1797 16:43:52.107173  

 1798 16:43:52.113783  [DQSOSCAuto] RK0, (LSB)MR18= 0x26fb, (MSB)MR19= 0x605, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps

 1799 16:43:52.116779  CH1 RK0: MR19=605, MR18=26FB

 1800 16:43:52.123397  CH1_RK0: MR19=0x605, MR18=0x26FB, DQSOSC=400, MR23=63, INC=92, DEC=61

 1801 16:43:52.123496  

 1802 16:43:52.127255  ----->DramcWriteLeveling(PI) begin...

 1803 16:43:52.127339  ==

 1804 16:43:52.130486  Dram Type= 6, Freq= 0, CH_1, rank 1

 1805 16:43:52.133487  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1806 16:43:52.133571  ==

 1807 16:43:52.136916  Write leveling (Byte 0): 29 => 29

 1808 16:43:52.140440  Write leveling (Byte 1): 29 => 29

 1809 16:43:52.143623  DramcWriteLeveling(PI) end<-----

 1810 16:43:52.143721  

 1811 16:43:52.143792  ==

 1812 16:43:52.147173  Dram Type= 6, Freq= 0, CH_1, rank 1

 1813 16:43:52.150329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1814 16:43:52.150405  ==

 1815 16:43:52.153875  [Gating] SW mode calibration

 1816 16:43:52.160656  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1817 16:43:52.167051  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1818 16:43:52.170550   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1819 16:43:52.173453   0  6  4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)

 1820 16:43:52.180350   0  6  8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)

 1821 16:43:52.183799   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1822 16:43:52.187403   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 16:43:52.193606   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 16:43:52.197021   0  6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1825 16:43:52.200608   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 16:43:52.203478   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 16:43:52.210511   0  7  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1828 16:43:52.213508   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1829 16:43:52.217045   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1830 16:43:52.223553   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1831 16:43:52.227003   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1832 16:43:52.230655   0  7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1833 16:43:52.237422   0  7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)

 1834 16:43:52.240535   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1835 16:43:52.243401   0  8  4 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)

 1836 16:43:52.250467   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 16:43:52.253765   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 16:43:52.256690   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1839 16:43:52.263649   0  8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1840 16:43:52.266748   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1841 16:43:52.270180   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1842 16:43:52.276778   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1843 16:43:52.280072   0  9  4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 1844 16:43:52.283500   0  9  8 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)

 1845 16:43:52.290647   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1846 16:43:52.293831   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1847 16:43:52.296569   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1848 16:43:52.303372   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1849 16:43:52.306886   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1850 16:43:52.310479   0 10  0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)

 1851 16:43:52.316915   0 10  4 | B1->B0 | 3232 2f2f | 1 0 | (0 0) (0 1)

 1852 16:43:52.320524   0 10  8 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)

 1853 16:43:52.323495   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1854 16:43:52.327083   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1855 16:43:52.333331   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1856 16:43:52.336850   0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1857 16:43:52.340200   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 16:43:52.346611   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1859 16:43:52.350217   0 11  4 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)

 1860 16:43:52.353587   0 11  8 | B1->B0 | 3e3e 4545 | 0 0 | (0 0) (0 0)

 1861 16:43:52.360575   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1862 16:43:52.363817   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1863 16:43:52.366588   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1864 16:43:52.373792   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1865 16:43:52.377030   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1866 16:43:52.380104   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1867 16:43:52.386569   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 1868 16:43:52.389917   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1869 16:43:52.393380   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1870 16:43:52.400431   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1871 16:43:52.403665   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1872 16:43:52.407014   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1873 16:43:52.413334   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1874 16:43:52.417025   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1875 16:43:52.420033   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1876 16:43:52.423655   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1877 16:43:52.430137   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1878 16:43:52.433649   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1879 16:43:52.436527   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1880 16:43:52.443159   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1881 16:43:52.446484   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1882 16:43:52.450049   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1883 16:43:52.456419   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 1884 16:43:52.459815   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1885 16:43:52.463361  Total UI for P1: 0, mck2ui 16

 1886 16:43:52.466365  best dqsien dly found for B0: ( 0, 14,  4)

 1887 16:43:52.469790  Total UI for P1: 0, mck2ui 16

 1888 16:43:52.472953  best dqsien dly found for B1: ( 0, 14,  6)

 1889 16:43:52.476484  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1890 16:43:52.479960  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1891 16:43:52.480066  

 1892 16:43:52.483459  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1893 16:43:52.486470  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1894 16:43:52.489888  [Gating] SW calibration Done

 1895 16:43:52.489980  ==

 1896 16:43:52.493444  Dram Type= 6, Freq= 0, CH_1, rank 1

 1897 16:43:52.496456  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1898 16:43:52.499896  ==

 1899 16:43:52.500015  RX Vref Scan: 0

 1900 16:43:52.500113  

 1901 16:43:52.503441  RX Vref 0 -> 0, step: 1

 1902 16:43:52.503552  

 1903 16:43:52.506389  RX Delay -130 -> 252, step: 16

 1904 16:43:52.509814  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

 1905 16:43:52.513032  iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240

 1906 16:43:52.516513  iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240

 1907 16:43:52.520206  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

 1908 16:43:52.526672  iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240

 1909 16:43:52.529768  iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224

 1910 16:43:52.533421  iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224

 1911 16:43:52.536470  iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224

 1912 16:43:52.539842  iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240

 1913 16:43:52.546434  iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240

 1914 16:43:52.549866  iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240

 1915 16:43:52.553297  iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240

 1916 16:43:52.556343  iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240

 1917 16:43:52.560105  iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224

 1918 16:43:52.566714  iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240

 1919 16:43:52.569678  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

 1920 16:43:52.569757  ==

 1921 16:43:52.573108  Dram Type= 6, Freq= 0, CH_1, rank 1

 1922 16:43:52.576406  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1923 16:43:52.576482  ==

 1924 16:43:52.576581  DQS Delay:

 1925 16:43:52.580013  DQS0 = 0, DQS1 = 0

 1926 16:43:52.580089  DQM Delay:

 1927 16:43:52.582914  DQM0 = 82, DQM1 = 78

 1928 16:43:52.582996  DQ Delay:

 1929 16:43:52.586501  DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85

 1930 16:43:52.589990  DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77

 1931 16:43:52.593147  DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69

 1932 16:43:52.597041  DQ12 =85, DQ13 =93, DQ14 =85, DQ15 =85

 1933 16:43:52.597146  

 1934 16:43:52.597238  

 1935 16:43:52.597326  ==

 1936 16:43:52.599634  Dram Type= 6, Freq= 0, CH_1, rank 1

 1937 16:43:52.602869  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1938 16:43:52.606366  ==

 1939 16:43:52.606448  

 1940 16:43:52.606512  

 1941 16:43:52.606572  	TX Vref Scan disable

 1942 16:43:52.609871   == TX Byte 0 ==

 1943 16:43:52.613371  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1944 16:43:52.616192  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1945 16:43:52.620069   == TX Byte 1 ==

 1946 16:43:52.623117  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1947 16:43:52.626540  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1948 16:43:52.630008  ==

 1949 16:43:52.630116  Dram Type= 6, Freq= 0, CH_1, rank 1

 1950 16:43:52.636531  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1951 16:43:52.636645  ==

 1952 16:43:52.648687  TX Vref=22, minBit 1, minWin=27, winSum=441

 1953 16:43:52.651986  TX Vref=24, minBit 1, minWin=27, winSum=446

 1954 16:43:52.655257  TX Vref=26, minBit 1, minWin=27, winSum=447

 1955 16:43:52.658331  TX Vref=28, minBit 0, minWin=28, winSum=452

 1956 16:43:52.661755  TX Vref=30, minBit 0, minWin=28, winSum=454

 1957 16:43:52.665221  TX Vref=32, minBit 3, minWin=27, winSum=454

 1958 16:43:52.671653  [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30

 1959 16:43:52.671760  

 1960 16:43:52.675122  Final TX Range 1 Vref 30

 1961 16:43:52.675237  

 1962 16:43:52.675333  ==

 1963 16:43:52.678549  Dram Type= 6, Freq= 0, CH_1, rank 1

 1964 16:43:52.681875  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1965 16:43:52.681958  ==

 1966 16:43:52.682023  

 1967 16:43:52.685363  

 1968 16:43:52.685444  	TX Vref Scan disable

 1969 16:43:52.688400   == TX Byte 0 ==

 1970 16:43:52.692160  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1971 16:43:52.695472  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1972 16:43:52.698569   == TX Byte 1 ==

 1973 16:43:52.702005  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1974 16:43:52.704907  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1975 16:43:52.704993  

 1976 16:43:52.708412  [DATLAT]

 1977 16:43:52.708498  Freq=800, CH1 RK1

 1978 16:43:52.708585  

 1979 16:43:52.711835  DATLAT Default: 0x9

 1980 16:43:52.711921  0, 0xFFFF, sum = 0

 1981 16:43:52.715357  1, 0xFFFF, sum = 0

 1982 16:43:52.715444  2, 0xFFFF, sum = 0

 1983 16:43:52.718707  3, 0xFFFF, sum = 0

 1984 16:43:52.718793  4, 0xFFFF, sum = 0

 1985 16:43:52.722096  5, 0xFFFF, sum = 0

 1986 16:43:52.722185  6, 0xFFFF, sum = 0

 1987 16:43:52.725150  7, 0xFFFF, sum = 0

 1988 16:43:52.725238  8, 0xFFFF, sum = 0

 1989 16:43:52.728625  9, 0x0, sum = 1

 1990 16:43:52.728712  10, 0x0, sum = 2

 1991 16:43:52.731722  11, 0x0, sum = 3

 1992 16:43:52.731809  12, 0x0, sum = 4

 1993 16:43:52.735389  best_step = 10

 1994 16:43:52.735474  

 1995 16:43:52.735560  ==

 1996 16:43:52.738326  Dram Type= 6, Freq= 0, CH_1, rank 1

 1997 16:43:52.741901  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1998 16:43:52.741987  ==

 1999 16:43:52.745330  RX Vref Scan: 0

 2000 16:43:52.745416  

 2001 16:43:52.745503  RX Vref 0 -> 0, step: 1

 2002 16:43:52.745588  

 2003 16:43:52.748676  RX Delay -95 -> 252, step: 8

 2004 16:43:52.755260  iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232

 2005 16:43:52.758588  iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232

 2006 16:43:52.761936  iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232

 2007 16:43:52.765445  iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232

 2008 16:43:52.768664  iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240

 2009 16:43:52.775177  iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224

 2010 16:43:52.778668  iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232

 2011 16:43:52.782050  iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232

 2012 16:43:52.785456  iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240

 2013 16:43:52.789037  iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224

 2014 16:43:52.791841  iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232

 2015 16:43:52.798851  iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232

 2016 16:43:52.801768  iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224

 2017 16:43:52.805379  iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232

 2018 16:43:52.808784  iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240

 2019 16:43:52.815091  iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232

 2020 16:43:52.815171  ==

 2021 16:43:52.818670  Dram Type= 6, Freq= 0, CH_1, rank 1

 2022 16:43:52.822336  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2023 16:43:52.822420  ==

 2024 16:43:52.822486  DQS Delay:

 2025 16:43:52.825147  DQS0 = 0, DQS1 = 0

 2026 16:43:52.825230  DQM Delay:

 2027 16:43:52.828599  DQM0 = 81, DQM1 = 75

 2028 16:43:52.828682  DQ Delay:

 2029 16:43:52.832137  DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76

 2030 16:43:52.835027  DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76

 2031 16:43:52.838764  DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68

 2032 16:43:52.842100  DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84

 2033 16:43:52.842189  

 2034 16:43:52.842269  

 2035 16:43:52.848714  [DQSOSCAuto] RK1, (LSB)MR18= 0x202a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps

 2036 16:43:52.851769  CH1 RK1: MR19=606, MR18=202A

 2037 16:43:52.858584  CH1_RK1: MR19=0x606, MR18=0x202A, DQSOSC=399, MR23=63, INC=92, DEC=61

 2038 16:43:52.861965  [RxdqsGatingPostProcess] freq 800

 2039 16:43:52.868429  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2040 16:43:52.868508  Pre-setting of DQS Precalculation

 2041 16:43:52.875433  [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10

 2042 16:43:52.881884  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2043 16:43:52.888539  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2044 16:43:52.888623  

 2045 16:43:52.888688  

 2046 16:43:52.891933  [Calibration Summary] 1600 Mbps

 2047 16:43:52.895332  CH 0, Rank 0

 2048 16:43:52.895432  SW Impedance     : PASS

 2049 16:43:52.898630  DUTY Scan        : NO K

 2050 16:43:52.901771  ZQ Calibration   : PASS

 2051 16:43:52.901853  Jitter Meter     : NO K

 2052 16:43:52.905237  CBT Training     : PASS

 2053 16:43:52.905309  Write leveling   : PASS

 2054 16:43:52.908769  RX DQS gating    : PASS

 2055 16:43:52.912263  RX DQ/DQS(RDDQC) : PASS

 2056 16:43:52.912361  TX DQ/DQS        : PASS

 2057 16:43:52.915453  RX DATLAT        : PASS

 2058 16:43:52.918386  RX DQ/DQS(Engine): PASS

 2059 16:43:52.918469  TX OE            : NO K

 2060 16:43:52.921946  All Pass.

 2061 16:43:52.922046  

 2062 16:43:52.922208  CH 0, Rank 1

 2063 16:43:52.925494  SW Impedance     : PASS

 2064 16:43:52.925681  DUTY Scan        : NO K

 2065 16:43:52.928335  ZQ Calibration   : PASS

 2066 16:43:52.931735  Jitter Meter     : NO K

 2067 16:43:52.931820  CBT Training     : PASS

 2068 16:43:52.935320  Write leveling   : PASS

 2069 16:43:52.938971  RX DQS gating    : PASS

 2070 16:43:52.939053  RX DQ/DQS(RDDQC) : PASS

 2071 16:43:52.941818  TX DQ/DQS        : PASS

 2072 16:43:52.941901  RX DATLAT        : PASS

 2073 16:43:52.945385  RX DQ/DQS(Engine): PASS

 2074 16:43:52.948841  TX OE            : NO K

 2075 16:43:52.948925  All Pass.

 2076 16:43:52.948993  

 2077 16:43:52.949059  CH 1, Rank 0

 2078 16:43:52.951767  SW Impedance     : PASS

 2079 16:43:52.955438  DUTY Scan        : NO K

 2080 16:43:52.955521  ZQ Calibration   : PASS

 2081 16:43:52.958400  Jitter Meter     : NO K

 2082 16:43:52.962413  CBT Training     : PASS

 2083 16:43:52.962496  Write leveling   : PASS

 2084 16:43:52.965130  RX DQS gating    : PASS

 2085 16:43:52.968682  RX DQ/DQS(RDDQC) : PASS

 2086 16:43:52.968768  TX DQ/DQS        : PASS

 2087 16:43:52.972070  RX DATLAT        : PASS

 2088 16:43:52.975186  RX DQ/DQS(Engine): PASS

 2089 16:43:52.975269  TX OE            : NO K

 2090 16:43:52.975335  All Pass.

 2091 16:43:52.978431  

 2092 16:43:52.978546  CH 1, Rank 1

 2093 16:43:52.981811  SW Impedance     : PASS

 2094 16:43:52.981894  DUTY Scan        : NO K

 2095 16:43:52.985257  ZQ Calibration   : PASS

 2096 16:43:52.988675  Jitter Meter     : NO K

 2097 16:43:52.988757  CBT Training     : PASS

 2098 16:43:52.992211  Write leveling   : PASS

 2099 16:43:52.992294  RX DQS gating    : PASS

 2100 16:43:52.995408  RX DQ/DQS(RDDQC) : PASS

 2101 16:43:52.998326  TX DQ/DQS        : PASS

 2102 16:43:52.998408  RX DATLAT        : PASS

 2103 16:43:53.001881  RX DQ/DQS(Engine): PASS

 2104 16:43:53.005200  TX OE            : NO K

 2105 16:43:53.005341  All Pass.

 2106 16:43:53.005424  

 2107 16:43:53.008959  DramC Write-DBI off

 2108 16:43:53.009046  	PER_BANK_REFRESH: Hybrid Mode

 2109 16:43:53.011844  TX_TRACKING: ON

 2110 16:43:53.015294  [GetDramInforAfterCalByMRR] Vendor 6.

 2111 16:43:53.018695  [GetDramInforAfterCalByMRR] Revision 606.

 2112 16:43:53.021844  [GetDramInforAfterCalByMRR] Revision 2 0.

 2113 16:43:53.021927  MR0 0x3b3b

 2114 16:43:53.025315  MR8 0x5151

 2115 16:43:53.028326  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2116 16:43:53.028417  

 2117 16:43:53.028501  MR0 0x3b3b

 2118 16:43:53.028576  MR8 0x5151

 2119 16:43:53.035179  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2120 16:43:53.035261  

 2121 16:43:53.042099  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2122 16:43:53.045075  [FAST_K] Save calibration result to emmc

 2123 16:43:53.048886  [FAST_K] Save calibration result to emmc

 2124 16:43:53.052267  dram_init: config_dvfs: 1

 2125 16:43:53.055327  dramc_set_vcore_voltage set vcore to 662500

 2126 16:43:53.058780  Read voltage for 1200, 2

 2127 16:43:53.058863  Vio18 = 0

 2128 16:43:53.062370  Vcore = 662500

 2129 16:43:53.062455  Vdram = 0

 2130 16:43:53.062540  Vddq = 0

 2131 16:43:53.062619  Vmddr = 0

 2132 16:43:53.068878  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2133 16:43:53.075287  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2134 16:43:53.075374  MEM_TYPE=3, freq_sel=15

 2135 16:43:53.078735  sv_algorithm_assistance_LP4_1600 

 2136 16:43:53.082137  ============ PULL DRAM RESETB DOWN ============

 2137 16:43:53.088558  ========== PULL DRAM RESETB DOWN end =========

 2138 16:43:53.091974  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2139 16:43:53.095457  =================================== 

 2140 16:43:53.098809  LPDDR4 DRAM CONFIGURATION

 2141 16:43:53.101748  =================================== 

 2142 16:43:53.101831  EX_ROW_EN[0]    = 0x0

 2143 16:43:53.105202  EX_ROW_EN[1]    = 0x0

 2144 16:43:53.105285  LP4Y_EN      = 0x0

 2145 16:43:53.108405  WORK_FSP     = 0x0

 2146 16:43:53.108487  WL           = 0x4

 2147 16:43:53.111857  RL           = 0x4

 2148 16:43:53.111939  BL           = 0x2

 2149 16:43:53.115363  RPST         = 0x0

 2150 16:43:53.118892  RD_PRE       = 0x0

 2151 16:43:53.118976  WR_PRE       = 0x1

 2152 16:43:53.121771  WR_PST       = 0x0

 2153 16:43:53.121853  DBI_WR       = 0x0

 2154 16:43:53.125772  DBI_RD       = 0x0

 2155 16:43:53.125855  OTF          = 0x1

 2156 16:43:53.128369  =================================== 

 2157 16:43:53.132126  =================================== 

 2158 16:43:53.135072  ANA top config

 2159 16:43:53.138456  =================================== 

 2160 16:43:53.138538  DLL_ASYNC_EN            =  0

 2161 16:43:53.141878  ALL_SLAVE_EN            =  0

 2162 16:43:53.145034  NEW_RANK_MODE           =  1

 2163 16:43:53.148822  DLL_IDLE_MODE           =  1

 2164 16:43:53.148920  LP45_APHY_COMB_EN       =  1

 2165 16:43:53.151952  TX_ODT_DIS              =  1

 2166 16:43:53.155029  NEW_8X_MODE             =  1

 2167 16:43:53.158477  =================================== 

 2168 16:43:53.162064  =================================== 

 2169 16:43:53.165031  data_rate                  = 2400

 2170 16:43:53.168314  CKR                        = 1

 2171 16:43:53.168410  DQ_P2S_RATIO               = 8

 2172 16:43:53.171745  =================================== 

 2173 16:43:53.174981  CA_P2S_RATIO               = 8

 2174 16:43:53.178553  DQ_CA_OPEN                 = 0

 2175 16:43:53.182207  DQ_SEMI_OPEN               = 0

 2176 16:43:53.184944  CA_SEMI_OPEN               = 0

 2177 16:43:53.188554  CA_FULL_RATE               = 0

 2178 16:43:53.188679  DQ_CKDIV4_EN               = 0

 2179 16:43:53.191889  CA_CKDIV4_EN               = 0

 2180 16:43:53.194793  CA_PREDIV_EN               = 0

 2181 16:43:53.198761  PH8_DLY                    = 17

 2182 16:43:53.201566  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2183 16:43:53.204913  DQ_AAMCK_DIV               = 4

 2184 16:43:53.205021  CA_AAMCK_DIV               = 4

 2185 16:43:53.208304  CA_ADMCK_DIV               = 4

 2186 16:43:53.211712  DQ_TRACK_CA_EN             = 0

 2187 16:43:53.214893  CA_PICK                    = 1200

 2188 16:43:53.218410  CA_MCKIO                   = 1200

 2189 16:43:53.221906  MCKIO_SEMI                 = 0

 2190 16:43:53.225400  PLL_FREQ                   = 2366

 2191 16:43:53.225495  DQ_UI_PI_RATIO             = 32

 2192 16:43:53.228268  CA_UI_PI_RATIO             = 0

 2193 16:43:53.231625  =================================== 

 2194 16:43:53.235154  =================================== 

 2195 16:43:53.238140  memory_type:LPDDR4         

 2196 16:43:53.241585  GP_NUM     : 10       

 2197 16:43:53.241667  SRAM_EN    : 1       

 2198 16:43:53.244893  MD32_EN    : 0       

 2199 16:43:53.248468  =================================== 

 2200 16:43:53.251375  [ANA_INIT] >>>>>>>>>>>>>> 

 2201 16:43:53.251458  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2202 16:43:53.255039  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2203 16:43:53.258580  =================================== 

 2204 16:43:53.261474  data_rate = 2400,PCW = 0X5b00

 2205 16:43:53.264917  =================================== 

 2206 16:43:53.268492  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2207 16:43:53.274873  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2208 16:43:53.281722  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2209 16:43:53.284604  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2210 16:43:53.288164  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2211 16:43:53.291460  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2212 16:43:53.294931  [ANA_INIT] flow start 

 2213 16:43:53.295017  [ANA_INIT] PLL >>>>>>>> 

 2214 16:43:53.298341  [ANA_INIT] PLL <<<<<<<< 

 2215 16:43:53.301727  [ANA_INIT] MIDPI >>>>>>>> 

 2216 16:43:53.301826  [ANA_INIT] MIDPI <<<<<<<< 

 2217 16:43:53.304790  [ANA_INIT] DLL >>>>>>>> 

 2218 16:43:53.307856  [ANA_INIT] DLL <<<<<<<< 

 2219 16:43:53.307965  [ANA_INIT] flow end 

 2220 16:43:53.315330  ============ LP4 DIFF to SE enter ============

 2221 16:43:53.318260  ============ LP4 DIFF to SE exit  ============

 2222 16:43:53.321786  [ANA_INIT] <<<<<<<<<<<<< 

 2223 16:43:53.324618  [Flow] Enable top DCM control >>>>> 

 2224 16:43:53.328151  [Flow] Enable top DCM control <<<<< 

 2225 16:43:53.328223  Enable DLL master slave shuffle 

 2226 16:43:53.335269  ============================================================== 

 2227 16:43:53.337830  Gating Mode config

 2228 16:43:53.341265  ============================================================== 

 2229 16:43:53.344803  Config description: 

 2230 16:43:53.354668  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2231 16:43:53.361152  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2232 16:43:53.364589  SELPH_MODE            0: By rank         1: By Phase 

 2233 16:43:53.371709  ============================================================== 

 2234 16:43:53.374586  GAT_TRACK_EN                 =  1

 2235 16:43:53.378059  RX_GATING_MODE               =  2

 2236 16:43:53.381526  RX_GATING_TRACK_MODE         =  2

 2237 16:43:53.381602  SELPH_MODE                   =  1

 2238 16:43:53.385072  PICG_EARLY_EN                =  1

 2239 16:43:53.388083  VALID_LAT_VALUE              =  1

 2240 16:43:53.394945  ============================================================== 

 2241 16:43:53.397930  Enter into Gating configuration >>>> 

 2242 16:43:53.401435  Exit from Gating configuration <<<< 

 2243 16:43:53.404489  Enter into  DVFS_PRE_config >>>>> 

 2244 16:43:53.414510  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2245 16:43:53.418056  Exit from  DVFS_PRE_config <<<<< 

 2246 16:43:53.421503  Enter into PICG configuration >>>> 

 2247 16:43:53.425029  Exit from PICG configuration <<<< 

 2248 16:43:53.427865  [RX_INPUT] configuration >>>>> 

 2249 16:43:53.431373  [RX_INPUT] configuration <<<<< 

 2250 16:43:53.434957  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2251 16:43:53.441200  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2252 16:43:53.448131  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2253 16:43:53.454484  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2254 16:43:53.457903  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2255 16:43:53.464346  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2256 16:43:53.467780  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2257 16:43:53.474720  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2258 16:43:53.478215  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2259 16:43:53.481196  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2260 16:43:53.484686  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2261 16:43:53.491266  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2262 16:43:53.494830  =================================== 

 2263 16:43:53.494911  LPDDR4 DRAM CONFIGURATION

 2264 16:43:53.497681  =================================== 

 2265 16:43:53.500946  EX_ROW_EN[0]    = 0x0

 2266 16:43:53.504339  EX_ROW_EN[1]    = 0x0

 2267 16:43:53.504418  LP4Y_EN      = 0x0

 2268 16:43:53.507823  WORK_FSP     = 0x0

 2269 16:43:53.507929  WL           = 0x4

 2270 16:43:53.511209  RL           = 0x4

 2271 16:43:53.511312  BL           = 0x2

 2272 16:43:53.514603  RPST         = 0x0

 2273 16:43:53.514712  RD_PRE       = 0x0

 2274 16:43:53.517832  WR_PRE       = 0x1

 2275 16:43:53.517908  WR_PST       = 0x0

 2276 16:43:53.521279  DBI_WR       = 0x0

 2277 16:43:53.521385  DBI_RD       = 0x0

 2278 16:43:53.525096  OTF          = 0x1

 2279 16:43:53.527935  =================================== 

 2280 16:43:53.531397  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2281 16:43:53.534923  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2282 16:43:53.541465  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2283 16:43:53.544633  =================================== 

 2284 16:43:53.544737  LPDDR4 DRAM CONFIGURATION

 2285 16:43:53.548112  =================================== 

 2286 16:43:53.551534  EX_ROW_EN[0]    = 0x10

 2287 16:43:53.551641  EX_ROW_EN[1]    = 0x0

 2288 16:43:53.554474  LP4Y_EN      = 0x0

 2289 16:43:53.557895  WORK_FSP     = 0x0

 2290 16:43:53.557973  WL           = 0x4

 2291 16:43:53.561358  RL           = 0x4

 2292 16:43:53.561436  BL           = 0x2

 2293 16:43:53.564368  RPST         = 0x0

 2294 16:43:53.564475  RD_PRE       = 0x0

 2295 16:43:53.567978  WR_PRE       = 0x1

 2296 16:43:53.568067  WR_PST       = 0x0

 2297 16:43:53.571564  DBI_WR       = 0x0

 2298 16:43:53.571640  DBI_RD       = 0x0

 2299 16:43:53.574378  OTF          = 0x1

 2300 16:43:53.577826  =================================== 

 2301 16:43:53.584380  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2302 16:43:53.584458  ==

 2303 16:43:53.587873  Dram Type= 6, Freq= 0, CH_0, rank 0

 2304 16:43:53.591236  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2305 16:43:53.591338  ==

 2306 16:43:53.594689  [Duty_Offset_Calibration]

 2307 16:43:53.594800  	B0:2	B1:-1	CA:1

 2308 16:43:53.594898  

 2309 16:43:53.597759  [DutyScan_Calibration_Flow] k_type=0

 2310 16:43:53.607303  

 2311 16:43:53.607413  ==CLK 0==

 2312 16:43:53.610381  Final CLK duty delay cell = -4

 2313 16:43:53.613273  [-4] MAX Duty = 5031%(X100), DQS PI = 4

 2314 16:43:53.616791  [-4] MIN Duty = 4875%(X100), DQS PI = 30

 2315 16:43:53.620130  [-4] AVG Duty = 4953%(X100)

 2316 16:43:53.620205  

 2317 16:43:53.623426  CH0 CLK Duty spec in!! Max-Min= 156%

 2318 16:43:53.626796  [DutyScan_Calibration_Flow] ====Done====

 2319 16:43:53.626867  

 2320 16:43:53.629862  [DutyScan_Calibration_Flow] k_type=1

 2321 16:43:53.644789  

 2322 16:43:53.644873  ==DQS 0 ==

 2323 16:43:53.648294  Final DQS duty delay cell = -4

 2324 16:43:53.651724  [-4] MAX Duty = 5000%(X100), DQS PI = 54

 2325 16:43:53.655317  [-4] MIN Duty = 4876%(X100), DQS PI = 12

 2326 16:43:53.658113  [-4] AVG Duty = 4938%(X100)

 2327 16:43:53.658203  

 2328 16:43:53.658301  ==DQS 1 ==

 2329 16:43:53.661501  Final DQS duty delay cell = -4

 2330 16:43:53.665187  [-4] MAX Duty = 5093%(X100), DQS PI = 6

 2331 16:43:53.668563  [-4] MIN Duty = 5000%(X100), DQS PI = 48

 2332 16:43:53.671637  [-4] AVG Duty = 5046%(X100)

 2333 16:43:53.671711  

 2334 16:43:53.674689  CH0 DQS 0 Duty spec in!! Max-Min= 124%

 2335 16:43:53.674766  

 2336 16:43:53.678009  CH0 DQS 1 Duty spec in!! Max-Min= 93%

 2337 16:43:53.681447  [DutyScan_Calibration_Flow] ====Done====

 2338 16:43:53.681526  

 2339 16:43:53.684996  [DutyScan_Calibration_Flow] k_type=3

 2340 16:43:53.702226  

 2341 16:43:53.702309  ==DQM 0 ==

 2342 16:43:53.705090  Final DQM duty delay cell = 0

 2343 16:43:53.708619  [0] MAX Duty = 5000%(X100), DQS PI = 46

 2344 16:43:53.712205  [0] MIN Duty = 4907%(X100), DQS PI = 0

 2345 16:43:53.712308  [0] AVG Duty = 4953%(X100)

 2346 16:43:53.714968  

 2347 16:43:53.715083  ==DQM 1 ==

 2348 16:43:53.718488  Final DQM duty delay cell = 0

 2349 16:43:53.722002  [0] MAX Duty = 5124%(X100), DQS PI = 60

 2350 16:43:53.725499  [0] MIN Duty = 4969%(X100), DQS PI = 10

 2351 16:43:53.728859  [0] AVG Duty = 5046%(X100)

 2352 16:43:53.728944  

 2353 16:43:53.732233  CH0 DQM 0 Duty spec in!! Max-Min= 93%

 2354 16:43:53.732316  

 2355 16:43:53.735045  CH0 DQM 1 Duty spec in!! Max-Min= 155%

 2356 16:43:53.738389  [DutyScan_Calibration_Flow] ====Done====

 2357 16:43:53.738471  

 2358 16:43:53.741876  [DutyScan_Calibration_Flow] k_type=2

 2359 16:43:53.757513  

 2360 16:43:53.757605  ==DQ 0 ==

 2361 16:43:53.761060  Final DQ duty delay cell = -4

 2362 16:43:53.763892  [-4] MAX Duty = 5062%(X100), DQS PI = 54

 2363 16:43:53.767394  [-4] MIN Duty = 4876%(X100), DQS PI = 20

 2364 16:43:53.770957  [-4] AVG Duty = 4969%(X100)

 2365 16:43:53.771039  

 2366 16:43:53.771105  ==DQ 1 ==

 2367 16:43:53.773883  Final DQ duty delay cell = 0

 2368 16:43:53.777830  [0] MAX Duty = 5062%(X100), DQS PI = 26

 2369 16:43:53.780780  [0] MIN Duty = 4907%(X100), DQS PI = 46

 2370 16:43:53.784130  [0] AVG Duty = 4984%(X100)

 2371 16:43:53.784212  

 2372 16:43:53.787774  CH0 DQ 0 Duty spec in!! Max-Min= 186%

 2373 16:43:53.787857  

 2374 16:43:53.790547  CH0 DQ 1 Duty spec in!! Max-Min= 155%

 2375 16:43:53.794204  [DutyScan_Calibration_Flow] ====Done====

 2376 16:43:53.794286  ==

 2377 16:43:53.797135  Dram Type= 6, Freq= 0, CH_1, rank 0

 2378 16:43:53.800583  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2379 16:43:53.800667  ==

 2380 16:43:53.804110  [Duty_Offset_Calibration]

 2381 16:43:53.804192  	B0:1	B1:1	CA:2

 2382 16:43:53.804256  

 2383 16:43:53.807047  [DutyScan_Calibration_Flow] k_type=0

 2384 16:43:53.817988  

 2385 16:43:53.818072  ==CLK 0==

 2386 16:43:53.821066  Final CLK duty delay cell = 0

 2387 16:43:53.824394  [0] MAX Duty = 5156%(X100), DQS PI = 24

 2388 16:43:53.827852  [0] MIN Duty = 4969%(X100), DQS PI = 38

 2389 16:43:53.827950  [0] AVG Duty = 5062%(X100)

 2390 16:43:53.831292  

 2391 16:43:53.831373  CH1 CLK Duty spec in!! Max-Min= 187%

 2392 16:43:53.838097  [DutyScan_Calibration_Flow] ====Done====

 2393 16:43:53.838181  

 2394 16:43:53.841423  [DutyScan_Calibration_Flow] k_type=1

 2395 16:43:53.857444  

 2396 16:43:53.857539  ==DQS 0 ==

 2397 16:43:53.860909  Final DQS duty delay cell = 0

 2398 16:43:53.863768  [0] MAX Duty = 5031%(X100), DQS PI = 18

 2399 16:43:53.867256  [0] MIN Duty = 4844%(X100), DQS PI = 48

 2400 16:43:53.870863  [0] AVG Duty = 4937%(X100)

 2401 16:43:53.870942  

 2402 16:43:53.871007  ==DQS 1 ==

 2403 16:43:53.874239  Final DQS duty delay cell = 0

 2404 16:43:53.877111  [0] MAX Duty = 5062%(X100), DQS PI = 36

 2405 16:43:53.880750  [0] MIN Duty = 4907%(X100), DQS PI = 14

 2406 16:43:53.884002  [0] AVG Duty = 4984%(X100)

 2407 16:43:53.884111  

 2408 16:43:53.887047  CH1 DQS 0 Duty spec in!! Max-Min= 187%

 2409 16:43:53.887129  

 2410 16:43:53.890520  CH1 DQS 1 Duty spec in!! Max-Min= 155%

 2411 16:43:53.893991  [DutyScan_Calibration_Flow] ====Done====

 2412 16:43:53.894073  

 2413 16:43:53.897017  [DutyScan_Calibration_Flow] k_type=3

 2414 16:43:53.913941  

 2415 16:43:53.914041  ==DQM 0 ==

 2416 16:43:53.917510  Final DQM duty delay cell = 0

 2417 16:43:53.920325  [0] MAX Duty = 5093%(X100), DQS PI = 16

 2418 16:43:53.924090  [0] MIN Duty = 4907%(X100), DQS PI = 48

 2419 16:43:53.924173  [0] AVG Duty = 5000%(X100)

 2420 16:43:53.927410  

 2421 16:43:53.927506  ==DQM 1 ==

 2422 16:43:53.930722  Final DQM duty delay cell = 0

 2423 16:43:53.934215  [0] MAX Duty = 5156%(X100), DQS PI = 0

 2424 16:43:53.937533  [0] MIN Duty = 4938%(X100), DQS PI = 22

 2425 16:43:53.937652  [0] AVG Duty = 5047%(X100)

 2426 16:43:53.940581  

 2427 16:43:53.943936  CH1 DQM 0 Duty spec in!! Max-Min= 186%

 2428 16:43:53.944067  

 2429 16:43:53.947337  CH1 DQM 1 Duty spec in!! Max-Min= 218%

 2430 16:43:53.950738  [DutyScan_Calibration_Flow] ====Done====

 2431 16:43:53.950821  

 2432 16:43:53.953990  [DutyScan_Calibration_Flow] k_type=2

 2433 16:43:53.970504  

 2434 16:43:53.970588  ==DQ 0 ==

 2435 16:43:53.973627  Final DQ duty delay cell = 0

 2436 16:43:53.976889  [0] MAX Duty = 5124%(X100), DQS PI = 20

 2437 16:43:53.980328  [0] MIN Duty = 4969%(X100), DQS PI = 14

 2438 16:43:53.980410  [0] AVG Duty = 5046%(X100)

 2439 16:43:53.983832  

 2440 16:43:53.983913  ==DQ 1 ==

 2441 16:43:53.986803  Final DQ duty delay cell = 0

 2442 16:43:53.990188  [0] MAX Duty = 5124%(X100), DQS PI = 58

 2443 16:43:53.993688  [0] MIN Duty = 5031%(X100), DQS PI = 2

 2444 16:43:53.993770  [0] AVG Duty = 5077%(X100)

 2445 16:43:53.993835  

 2446 16:43:53.997401  CH1 DQ 0 Duty spec in!! Max-Min= 155%

 2447 16:43:53.997483  

 2448 16:43:54.000539  CH1 DQ 1 Duty spec in!! Max-Min= 93%

 2449 16:43:54.007160  [DutyScan_Calibration_Flow] ====Done====

 2450 16:43:54.010200  nWR fixed to 30

 2451 16:43:54.010282  [ModeRegInit_LP4] CH0 RK0

 2452 16:43:54.013765  [ModeRegInit_LP4] CH0 RK1

 2453 16:43:54.016742  [ModeRegInit_LP4] CH1 RK0

 2454 16:43:54.016824  [ModeRegInit_LP4] CH1 RK1

 2455 16:43:54.020141  match AC timing 7

 2456 16:43:54.023608  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2457 16:43:54.026963  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2458 16:43:54.033900  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2459 16:43:54.037319  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2460 16:43:54.043370  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2461 16:43:54.043453  ==

 2462 16:43:54.046837  Dram Type= 6, Freq= 0, CH_0, rank 0

 2463 16:43:54.050318  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2464 16:43:54.050402  ==

 2465 16:43:54.057078  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2466 16:43:54.060045  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2467 16:43:54.070368  [CA 0] Center 40 (10~71) winsize 62

 2468 16:43:54.073866  [CA 1] Center 39 (9~70) winsize 62

 2469 16:43:54.076766  [CA 2] Center 36 (6~67) winsize 62

 2470 16:43:54.080110  [CA 3] Center 35 (5~66) winsize 62

 2471 16:43:54.083468  [CA 4] Center 34 (4~65) winsize 62

 2472 16:43:54.086937  [CA 5] Center 34 (4~64) winsize 61

 2473 16:43:54.087019  

 2474 16:43:54.090433  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2475 16:43:54.090516  

 2476 16:43:54.093924  [CATrainingPosCal] consider 1 rank data

 2477 16:43:54.096810  u2DelayCellTimex100 = 270/100 ps

 2478 16:43:54.100434  CA0 delay=40 (10~71),Diff = 6 PI (28 cell)

 2479 16:43:54.107013  CA1 delay=39 (9~70),Diff = 5 PI (24 cell)

 2480 16:43:54.109981  CA2 delay=36 (6~67),Diff = 2 PI (9 cell)

 2481 16:43:54.113504  CA3 delay=35 (5~66),Diff = 1 PI (4 cell)

 2482 16:43:54.116920  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 2483 16:43:54.120502  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 2484 16:43:54.120585  

 2485 16:43:54.123402  CA PerBit enable=1, Macro0, CA PI delay=34

 2486 16:43:54.123484  

 2487 16:43:54.126788  [CBTSetCACLKResult] CA Dly = 34

 2488 16:43:54.126870  CS Dly: 7 (0~38)

 2489 16:43:54.130379  ==

 2490 16:43:54.133449  Dram Type= 6, Freq= 0, CH_0, rank 1

 2491 16:43:54.136633  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2492 16:43:54.136715  ==

 2493 16:43:54.140175  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2494 16:43:54.146779  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2495 16:43:54.156360  [CA 0] Center 39 (9~70) winsize 62

 2496 16:43:54.159832  [CA 1] Center 39 (9~70) winsize 62

 2497 16:43:54.162690  [CA 2] Center 36 (6~67) winsize 62

 2498 16:43:54.166308  [CA 3] Center 36 (5~67) winsize 63

 2499 16:43:54.169720  [CA 4] Center 34 (4~65) winsize 62

 2500 16:43:54.173113  [CA 5] Center 34 (4~64) winsize 61

 2501 16:43:54.173186  

 2502 16:43:54.176123  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2503 16:43:54.176198  

 2504 16:43:54.179593  [CATrainingPosCal] consider 2 rank data

 2505 16:43:54.183052  u2DelayCellTimex100 = 270/100 ps

 2506 16:43:54.186531  CA0 delay=40 (10~70),Diff = 6 PI (28 cell)

 2507 16:43:54.189715  CA1 delay=39 (9~70),Diff = 5 PI (24 cell)

 2508 16:43:54.195927  CA2 delay=36 (6~67),Diff = 2 PI (9 cell)

 2509 16:43:54.199640  CA3 delay=35 (5~66),Diff = 1 PI (4 cell)

 2510 16:43:54.202577  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 2511 16:43:54.206190  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 2512 16:43:54.206299  

 2513 16:43:54.209317  CA PerBit enable=1, Macro0, CA PI delay=34

 2514 16:43:54.209392  

 2515 16:43:54.212871  [CBTSetCACLKResult] CA Dly = 34

 2516 16:43:54.212943  CS Dly: 8 (0~41)

 2517 16:43:54.213004  

 2518 16:43:54.216325  ----->DramcWriteLeveling(PI) begin...

 2519 16:43:54.219806  ==

 2520 16:43:54.223069  Dram Type= 6, Freq= 0, CH_0, rank 0

 2521 16:43:54.226027  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2522 16:43:54.226112  ==

 2523 16:43:54.229705  Write leveling (Byte 0): 31 => 31

 2524 16:43:54.232753  Write leveling (Byte 1): 29 => 29

 2525 16:43:54.236244  DramcWriteLeveling(PI) end<-----

 2526 16:43:54.236329  

 2527 16:43:54.236395  ==

 2528 16:43:54.239251  Dram Type= 6, Freq= 0, CH_0, rank 0

 2529 16:43:54.243000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2530 16:43:54.243084  ==

 2531 16:43:54.246586  [Gating] SW mode calibration

 2532 16:43:54.252807  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2533 16:43:54.256019  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2534 16:43:54.262472   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2535 16:43:54.266046   0 15  4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)

 2536 16:43:54.269701   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2537 16:43:54.276075   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2538 16:43:54.279294   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2539 16:43:54.282959   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2540 16:43:54.289716   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2541 16:43:54.293043   0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2542 16:43:54.296612   1  0  0 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)

 2543 16:43:54.303172   1  0  4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)

 2544 16:43:54.306212   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2545 16:43:54.309588   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2546 16:43:54.316330   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2547 16:43:54.319602   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2548 16:43:54.323185   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2549 16:43:54.329685   1  0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2550 16:43:54.333020   1  1  0 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)

 2551 16:43:54.335937   1  1  4 | B1->B0 | 3a3a 4444 | 1 0 | (0 0) (0 0)

 2552 16:43:54.343163   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2553 16:43:54.346432   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2554 16:43:54.349789   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2555 16:43:54.353067   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2556 16:43:54.359674   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2557 16:43:54.363027   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2558 16:43:54.366313   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2559 16:43:54.373311   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2560 16:43:54.376344   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2561 16:43:54.379794   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2562 16:43:54.386148   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2563 16:43:54.389603   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2564 16:43:54.393094   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2565 16:43:54.399779   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2566 16:43:54.402744   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2567 16:43:54.406217   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2568 16:43:54.412783   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2569 16:43:54.416225   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2570 16:43:54.419827   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2571 16:43:54.426314   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2572 16:43:54.429430   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2573 16:43:54.433008   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2574 16:43:54.439541   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2575 16:43:54.443157   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2576 16:43:54.445991  Total UI for P1: 0, mck2ui 16

 2577 16:43:54.449716  best dqsien dly found for B0: ( 1,  4,  0)

 2578 16:43:54.452992   1  4  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2579 16:43:54.455959  Total UI for P1: 0, mck2ui 16

 2580 16:43:54.459301  best dqsien dly found for B1: ( 1,  4,  2)

 2581 16:43:54.462814  best DQS0 dly(MCK, UI, PI) = (1, 4, 0)

 2582 16:43:54.465749  best DQS1 dly(MCK, UI, PI) = (1, 4, 2)

 2583 16:43:54.465833  

 2584 16:43:54.469399  best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2585 16:43:54.472735  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)

 2586 16:43:54.475987  [Gating] SW calibration Done

 2587 16:43:54.476086  ==

 2588 16:43:54.479621  Dram Type= 6, Freq= 0, CH_0, rank 0

 2589 16:43:54.485931  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2590 16:43:54.486047  ==

 2591 16:43:54.486146  RX Vref Scan: 0

 2592 16:43:54.486237  

 2593 16:43:54.489195  RX Vref 0 -> 0, step: 1

 2594 16:43:54.489273  

 2595 16:43:54.493018  RX Delay -40 -> 252, step: 8

 2596 16:43:54.496117  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2597 16:43:54.499573  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 2598 16:43:54.502963  iDelay=200, Bit 2, Center 111 (40 ~ 183) 144

 2599 16:43:54.506297  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2600 16:43:54.512844  iDelay=200, Bit 4, Center 115 (40 ~ 191) 152

 2601 16:43:54.515894  iDelay=200, Bit 5, Center 111 (40 ~ 183) 144

 2602 16:43:54.519423  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2603 16:43:54.522698  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2604 16:43:54.526226  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2605 16:43:54.529753  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2606 16:43:54.536274  iDelay=200, Bit 10, Center 107 (40 ~ 175) 136

 2607 16:43:54.539704  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 2608 16:43:54.543132  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2609 16:43:54.546362  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2610 16:43:54.549584  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2611 16:43:54.556650  iDelay=200, Bit 15, Center 115 (48 ~ 183) 136

 2612 16:43:54.556738  ==

 2613 16:43:54.559536  Dram Type= 6, Freq= 0, CH_0, rank 0

 2614 16:43:54.563143  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2615 16:43:54.563251  ==

 2616 16:43:54.563376  DQS Delay:

 2617 16:43:54.566531  DQS0 = 0, DQS1 = 0

 2618 16:43:54.566642  DQM Delay:

 2619 16:43:54.569932  DQM0 = 116, DQM1 = 107

 2620 16:43:54.570035  DQ Delay:

 2621 16:43:54.573226  DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115

 2622 16:43:54.576290  DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123

 2623 16:43:54.579522  DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99

 2624 16:43:54.582698  DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115

 2625 16:43:54.582802  

 2626 16:43:54.582900  

 2627 16:43:54.582993  ==

 2628 16:43:54.586560  Dram Type= 6, Freq= 0, CH_0, rank 0

 2629 16:43:54.593089  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2630 16:43:54.593196  ==

 2631 16:43:54.593289  

 2632 16:43:54.593382  

 2633 16:43:54.593469  	TX Vref Scan disable

 2634 16:43:54.597128   == TX Byte 0 ==

 2635 16:43:54.600006  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2636 16:43:54.603558  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2637 16:43:54.607010   == TX Byte 1 ==

 2638 16:43:54.610037  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2639 16:43:54.613468  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2640 16:43:54.616526  ==

 2641 16:43:54.620148  Dram Type= 6, Freq= 0, CH_0, rank 0

 2642 16:43:54.623114  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2643 16:43:54.623202  ==

 2644 16:43:54.634826  TX Vref=22, minBit 1, minWin=25, winSum=415

 2645 16:43:54.637834  TX Vref=24, minBit 7, minWin=25, winSum=421

 2646 16:43:54.641403  TX Vref=26, minBit 0, minWin=26, winSum=424

 2647 16:43:54.644880  TX Vref=28, minBit 0, minWin=26, winSum=431

 2648 16:43:54.648156  TX Vref=30, minBit 1, minWin=26, winSum=434

 2649 16:43:54.651734  TX Vref=32, minBit 1, minWin=26, winSum=431

 2650 16:43:54.657914  [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30

 2651 16:43:54.658026  

 2652 16:43:54.661465  Final TX Range 1 Vref 30

 2653 16:43:54.661567  

 2654 16:43:54.661662  ==

 2655 16:43:54.665009  Dram Type= 6, Freq= 0, CH_0, rank 0

 2656 16:43:54.667900  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2657 16:43:54.668032  ==

 2658 16:43:54.668097  

 2659 16:43:54.668158  

 2660 16:43:54.671409  	TX Vref Scan disable

 2661 16:43:54.674976   == TX Byte 0 ==

 2662 16:43:54.678484  Update DQ  dly =850 (3 ,2, 18)  DQ  OEN =(2 ,7)

 2663 16:43:54.681719  Update DQM dly =850 (3 ,2, 18)  DQM OEN =(2 ,7)

 2664 16:43:54.684730   == TX Byte 1 ==

 2665 16:43:54.688017  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 2666 16:43:54.691730  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 2667 16:43:54.691845  

 2668 16:43:54.695053  [DATLAT]

 2669 16:43:54.695160  Freq=1200, CH0 RK0

 2670 16:43:54.695271  

 2671 16:43:54.697977  DATLAT Default: 0xd

 2672 16:43:54.698079  0, 0xFFFF, sum = 0

 2673 16:43:54.701618  1, 0xFFFF, sum = 0

 2674 16:43:54.701727  2, 0xFFFF, sum = 0

 2675 16:43:54.704864  3, 0xFFFF, sum = 0

 2676 16:43:54.704970  4, 0xFFFF, sum = 0

 2677 16:43:54.708076  5, 0xFFFF, sum = 0

 2678 16:43:54.708157  6, 0xFFFF, sum = 0

 2679 16:43:54.711461  7, 0xFFFF, sum = 0

 2680 16:43:54.711565  8, 0xFFFF, sum = 0

 2681 16:43:54.714902  9, 0xFFFF, sum = 0

 2682 16:43:54.717832  10, 0xFFFF, sum = 0

 2683 16:43:54.717953  11, 0xFFFF, sum = 0

 2684 16:43:54.721336  12, 0x0, sum = 1

 2685 16:43:54.721442  13, 0x0, sum = 2

 2686 16:43:54.721579  14, 0x0, sum = 3

 2687 16:43:54.724980  15, 0x0, sum = 4

 2688 16:43:54.725103  best_step = 13

 2689 16:43:54.725197  

 2690 16:43:54.725292  ==

 2691 16:43:54.728097  Dram Type= 6, Freq= 0, CH_0, rank 0

 2692 16:43:54.734492  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2693 16:43:54.734597  ==

 2694 16:43:54.734708  RX Vref Scan: 1

 2695 16:43:54.734803  

 2696 16:43:54.738010  Set Vref Range= 32 -> 127

 2697 16:43:54.738117  

 2698 16:43:54.741486  RX Vref 32 -> 127, step: 1

 2699 16:43:54.741588  

 2700 16:43:54.745084  RX Delay -21 -> 252, step: 4

 2701 16:43:54.745188  

 2702 16:43:54.748129  Set Vref, RX VrefLevel [Byte0]: 32

 2703 16:43:54.751971                           [Byte1]: 32

 2704 16:43:54.752099  

 2705 16:43:54.754659  Set Vref, RX VrefLevel [Byte0]: 33

 2706 16:43:54.758261                           [Byte1]: 33

 2707 16:43:54.758369  

 2708 16:43:54.762075  Set Vref, RX VrefLevel [Byte0]: 34

 2709 16:43:54.764671                           [Byte1]: 34

 2710 16:43:54.768900  

 2711 16:43:54.769014  Set Vref, RX VrefLevel [Byte0]: 35

 2712 16:43:54.772244                           [Byte1]: 35

 2713 16:43:54.776516  

 2714 16:43:54.776622  Set Vref, RX VrefLevel [Byte0]: 36

 2715 16:43:54.780076                           [Byte1]: 36

 2716 16:43:54.784705  

 2717 16:43:54.784809  Set Vref, RX VrefLevel [Byte0]: 37

 2718 16:43:54.788052                           [Byte1]: 37

 2719 16:43:54.792545  

 2720 16:43:54.792651  Set Vref, RX VrefLevel [Byte0]: 38

 2721 16:43:54.795987                           [Byte1]: 38

 2722 16:43:54.800268  

 2723 16:43:54.800372  Set Vref, RX VrefLevel [Byte0]: 39

 2724 16:43:54.803888                           [Byte1]: 39

 2725 16:43:54.808230  

 2726 16:43:54.808312  Set Vref, RX VrefLevel [Byte0]: 40

 2727 16:43:54.811845                           [Byte1]: 40

 2728 16:43:54.816107  

 2729 16:43:54.816182  Set Vref, RX VrefLevel [Byte0]: 41

 2730 16:43:54.819986                           [Byte1]: 41

 2731 16:43:54.824250  

 2732 16:43:54.824326  Set Vref, RX VrefLevel [Byte0]: 42

 2733 16:43:54.827625                           [Byte1]: 42

 2734 16:43:54.832299  

 2735 16:43:54.832401  Set Vref, RX VrefLevel [Byte0]: 43

 2736 16:43:54.835421                           [Byte1]: 43

 2737 16:43:54.840493  

 2738 16:43:54.840568  Set Vref, RX VrefLevel [Byte0]: 44

 2739 16:43:54.843420                           [Byte1]: 44

 2740 16:43:54.847958  

 2741 16:43:54.848103  Set Vref, RX VrefLevel [Byte0]: 45

 2742 16:43:54.851440                           [Byte1]: 45

 2743 16:43:54.856024  

 2744 16:43:54.856109  Set Vref, RX VrefLevel [Byte0]: 46

 2745 16:43:54.859369                           [Byte1]: 46

 2746 16:43:54.863724  

 2747 16:43:54.863847  Set Vref, RX VrefLevel [Byte0]: 47

 2748 16:43:54.867305                           [Byte1]: 47

 2749 16:43:54.872208  

 2750 16:43:54.872388  Set Vref, RX VrefLevel [Byte0]: 48

 2751 16:43:54.875029                           [Byte1]: 48

 2752 16:43:54.879901  

 2753 16:43:54.880073  Set Vref, RX VrefLevel [Byte0]: 49

 2754 16:43:54.882840                           [Byte1]: 49

 2755 16:43:54.887601  

 2756 16:43:54.887753  Set Vref, RX VrefLevel [Byte0]: 50

 2757 16:43:54.890952                           [Byte1]: 50

 2758 16:43:54.895588  

 2759 16:43:54.895737  Set Vref, RX VrefLevel [Byte0]: 51

 2760 16:43:54.898791                           [Byte1]: 51

 2761 16:43:54.903338  

 2762 16:43:54.903480  Set Vref, RX VrefLevel [Byte0]: 52

 2763 16:43:54.907195                           [Byte1]: 52

 2764 16:43:54.911533  

 2765 16:43:54.911667  Set Vref, RX VrefLevel [Byte0]: 53

 2766 16:43:54.914726                           [Byte1]: 53

 2767 16:43:54.919200  

 2768 16:43:54.919341  Set Vref, RX VrefLevel [Byte0]: 54

 2769 16:43:54.922757                           [Byte1]: 54

 2770 16:43:54.927405  

 2771 16:43:54.927504  Set Vref, RX VrefLevel [Byte0]: 55

 2772 16:43:54.930838                           [Byte1]: 55

 2773 16:43:54.935513  

 2774 16:43:54.935602  Set Vref, RX VrefLevel [Byte0]: 56

 2775 16:43:54.938468                           [Byte1]: 56

 2776 16:43:54.943356  

 2777 16:43:54.943444  Set Vref, RX VrefLevel [Byte0]: 57

 2778 16:43:54.946639                           [Byte1]: 57

 2779 16:43:54.951466  

 2780 16:43:54.951554  Set Vref, RX VrefLevel [Byte0]: 58

 2781 16:43:54.954371                           [Byte1]: 58

 2782 16:43:54.958998  

 2783 16:43:54.959085  Set Vref, RX VrefLevel [Byte0]: 59

 2784 16:43:54.962547                           [Byte1]: 59

 2785 16:43:54.967161  

 2786 16:43:54.967247  Set Vref, RX VrefLevel [Byte0]: 60

 2787 16:43:54.970157                           [Byte1]: 60

 2788 16:43:54.974816  

 2789 16:43:54.974908  Set Vref, RX VrefLevel [Byte0]: 61

 2790 16:43:54.978356                           [Byte1]: 61

 2791 16:43:54.983052  

 2792 16:43:54.983159  Set Vref, RX VrefLevel [Byte0]: 62

 2793 16:43:54.986017                           [Byte1]: 62

 2794 16:43:54.990739  

 2795 16:43:54.990856  Set Vref, RX VrefLevel [Byte0]: 63

 2796 16:43:54.994281                           [Byte1]: 63

 2797 16:43:54.998788  

 2798 16:43:54.998929  Set Vref, RX VrefLevel [Byte0]: 64

 2799 16:43:55.002253                           [Byte1]: 64

 2800 16:43:55.006803  

 2801 16:43:55.006985  Set Vref, RX VrefLevel [Byte0]: 65

 2802 16:43:55.009972                           [Byte1]: 65

 2803 16:43:55.015251  

 2804 16:43:55.015620  Set Vref, RX VrefLevel [Byte0]: 66

 2805 16:43:55.018069                           [Byte1]: 66

 2806 16:43:55.022412  

 2807 16:43:55.022776  Set Vref, RX VrefLevel [Byte0]: 67

 2808 16:43:55.025882                           [Byte1]: 67

 2809 16:43:55.030393  

 2810 16:43:55.030640  Set Vref, RX VrefLevel [Byte0]: 68

 2811 16:43:55.033449                           [Byte1]: 68

 2812 16:43:55.038153  

 2813 16:43:55.038268  Final RX Vref Byte 0 = 55 to rank0

 2814 16:43:55.041908  Final RX Vref Byte 1 = 51 to rank0

 2815 16:43:55.045114  Final RX Vref Byte 0 = 55 to rank1

 2816 16:43:55.048262  Final RX Vref Byte 1 = 51 to rank1==

 2817 16:43:55.051739  Dram Type= 6, Freq= 0, CH_0, rank 0

 2818 16:43:55.055255  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2819 16:43:55.058966  ==

 2820 16:43:55.059076  DQS Delay:

 2821 16:43:55.059167  DQS0 = 0, DQS1 = 0

 2822 16:43:55.061520  DQM Delay:

 2823 16:43:55.061634  DQM0 = 114, DQM1 = 104

 2824 16:43:55.065131  DQ Delay:

 2825 16:43:55.068801  DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112

 2826 16:43:55.071963  DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122

 2827 16:43:55.074830  DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96

 2828 16:43:55.078311  DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114

 2829 16:43:55.078419  

 2830 16:43:55.078508  

 2831 16:43:55.085381  [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps

 2832 16:43:55.088490  CH0 RK0: MR19=303, MR18=FEED

 2833 16:43:55.095032  CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26

 2834 16:43:55.095186  

 2835 16:43:55.098712  ----->DramcWriteLeveling(PI) begin...

 2836 16:43:55.098823  ==

 2837 16:43:55.101901  Dram Type= 6, Freq= 0, CH_0, rank 1

 2838 16:43:55.105308  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2839 16:43:55.105419  ==

 2840 16:43:55.108748  Write leveling (Byte 0): 33 => 33

 2841 16:43:55.111885  Write leveling (Byte 1): 29 => 29

 2842 16:43:55.115125  DramcWriteLeveling(PI) end<-----

 2843 16:43:55.115238  

 2844 16:43:55.115336  ==

 2845 16:43:55.118515  Dram Type= 6, Freq= 0, CH_0, rank 1

 2846 16:43:55.121742  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2847 16:43:55.124942  ==

 2848 16:43:55.125092  [Gating] SW mode calibration

 2849 16:43:55.135171  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2850 16:43:55.138650  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2851 16:43:55.142205   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2852 16:43:55.149033   0 15  4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)

 2853 16:43:55.152153   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2854 16:43:55.155520   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2855 16:43:55.161902   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2856 16:43:55.165941   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2857 16:43:55.168898   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2858 16:43:55.175301   0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)

 2859 16:43:55.178820   1  0  0 | B1->B0 | 3030 2929 | 0 0 | (0 1) (0 0)

 2860 16:43:55.181923   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 2861 16:43:55.185331   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2862 16:43:55.191842   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2863 16:43:55.195357   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2864 16:43:55.198954   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2865 16:43:55.205076   1  0 24 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)

 2866 16:43:55.208569   1  0 28 | B1->B0 | 2323 4343 | 0 1 | (0 0) (0 0)

 2867 16:43:55.212196   1  1  0 | B1->B0 | 2f2f 4140 | 0 1 | (1 1) (0 0)

 2868 16:43:55.219260   1  1  4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 2869 16:43:55.221979   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2870 16:43:55.225655   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2871 16:43:55.232181   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2872 16:43:55.235698   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2873 16:43:55.238879   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2874 16:43:55.245605   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2875 16:43:55.248573   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2876 16:43:55.252213   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2877 16:43:55.259160   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2878 16:43:55.261960   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2879 16:43:55.265337   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2880 16:43:55.268816   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2881 16:43:55.275771   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2882 16:43:55.279094   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2883 16:43:55.282190   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2884 16:43:55.288604   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2885 16:43:55.292131   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2886 16:43:55.295696   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2887 16:43:55.302112   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2888 16:43:55.305612   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2889 16:43:55.309108   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2890 16:43:55.315575   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2891 16:43:55.318914   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2892 16:43:55.322212  Total UI for P1: 0, mck2ui 16

 2893 16:43:55.325677  best dqsien dly found for B0: ( 1,  3, 26)

 2894 16:43:55.328901   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2895 16:43:55.332269  Total UI for P1: 0, mck2ui 16

 2896 16:43:55.335553  best dqsien dly found for B1: ( 1,  4,  0)

 2897 16:43:55.339080  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2898 16:43:55.342482  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2899 16:43:55.342573  

 2900 16:43:55.345930  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2901 16:43:55.352435  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2902 16:43:55.352527  [Gating] SW calibration Done

 2903 16:43:55.352606  ==

 2904 16:43:55.356021  Dram Type= 6, Freq= 0, CH_0, rank 1

 2905 16:43:55.362492  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2906 16:43:55.362599  ==

 2907 16:43:55.362691  RX Vref Scan: 0

 2908 16:43:55.362782  

 2909 16:43:55.365834  RX Vref 0 -> 0, step: 1

 2910 16:43:55.365959  

 2911 16:43:55.368870  RX Delay -40 -> 252, step: 8

 2912 16:43:55.372106  iDelay=200, Bit 0, Center 115 (40 ~ 191) 152

 2913 16:43:55.375589  iDelay=200, Bit 1, Center 115 (40 ~ 191) 152

 2914 16:43:55.379098  iDelay=200, Bit 2, Center 115 (40 ~ 191) 152

 2915 16:43:55.382644  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 2916 16:43:55.389008  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2917 16:43:55.392507  iDelay=200, Bit 5, Center 107 (32 ~ 183) 152

 2918 16:43:55.395605  iDelay=200, Bit 6, Center 123 (48 ~ 199) 152

 2919 16:43:55.399266  iDelay=200, Bit 7, Center 123 (48 ~ 199) 152

 2920 16:43:55.402750  iDelay=200, Bit 8, Center 95 (24 ~ 167) 144

 2921 16:43:55.409288  iDelay=200, Bit 9, Center 95 (24 ~ 167) 144

 2922 16:43:55.412747  iDelay=200, Bit 10, Center 103 (32 ~ 175) 144

 2923 16:43:55.415738  iDelay=200, Bit 11, Center 99 (32 ~ 167) 136

 2924 16:43:55.419255  iDelay=200, Bit 12, Center 111 (40 ~ 183) 144

 2925 16:43:55.422223  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 2926 16:43:55.429287  iDelay=200, Bit 14, Center 119 (48 ~ 191) 144

 2927 16:43:55.432568  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 2928 16:43:55.432652  ==

 2929 16:43:55.435838  Dram Type= 6, Freq= 0, CH_0, rank 1

 2930 16:43:55.439209  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2931 16:43:55.439292  ==

 2932 16:43:55.442733  DQS Delay:

 2933 16:43:55.442816  DQS0 = 0, DQS1 = 0

 2934 16:43:55.442881  DQM Delay:

 2935 16:43:55.445435  DQM0 = 116, DQM1 = 106

 2936 16:43:55.445517  DQ Delay:

 2937 16:43:55.449080  DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115

 2938 16:43:55.452287  DQ4 =119, DQ5 =107, DQ6 =123, DQ7 =123

 2939 16:43:55.455807  DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99

 2940 16:43:55.458880  DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111

 2941 16:43:55.462319  

 2942 16:43:55.462404  

 2943 16:43:55.462488  ==

 2944 16:43:55.465801  Dram Type= 6, Freq= 0, CH_0, rank 1

 2945 16:43:55.469133  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2946 16:43:55.469220  ==

 2947 16:43:55.469304  

 2948 16:43:55.469384  

 2949 16:43:55.472696  	TX Vref Scan disable

 2950 16:43:55.472783   == TX Byte 0 ==

 2951 16:43:55.478780  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2952 16:43:55.482206  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2953 16:43:55.482292   == TX Byte 1 ==

 2954 16:43:55.489061  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2955 16:43:55.492610  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2956 16:43:55.492696  ==

 2957 16:43:55.495619  Dram Type= 6, Freq= 0, CH_0, rank 1

 2958 16:43:55.499152  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2959 16:43:55.499237  ==

 2960 16:43:55.512216  TX Vref=22, minBit 1, minWin=25, winSum=420

 2961 16:43:55.515070  TX Vref=24, minBit 1, minWin=26, winSum=431

 2962 16:43:55.518408  TX Vref=26, minBit 2, minWin=26, winSum=431

 2963 16:43:55.521806  TX Vref=28, minBit 2, minWin=26, winSum=433

 2964 16:43:55.524884  TX Vref=30, minBit 0, minWin=27, winSum=436

 2965 16:43:55.531769  TX Vref=32, minBit 12, minWin=26, winSum=436

 2966 16:43:55.535224  [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 30

 2967 16:43:55.535310  

 2968 16:43:55.538524  Final TX Range 1 Vref 30

 2969 16:43:55.538609  

 2970 16:43:55.538693  ==

 2971 16:43:55.541731  Dram Type= 6, Freq= 0, CH_0, rank 1

 2972 16:43:55.545040  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2973 16:43:55.545126  ==

 2974 16:43:55.548512  

 2975 16:43:55.548596  

 2976 16:43:55.548680  	TX Vref Scan disable

 2977 16:43:55.551282   == TX Byte 0 ==

 2978 16:43:55.554742  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2979 16:43:55.561856  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2980 16:43:55.561942   == TX Byte 1 ==

 2981 16:43:55.564623  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2982 16:43:55.568261  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2983 16:43:55.571859  

 2984 16:43:55.571945  [DATLAT]

 2985 16:43:55.572053  Freq=1200, CH0 RK1

 2986 16:43:55.572135  

 2987 16:43:55.575300  DATLAT Default: 0xd

 2988 16:43:55.575385  0, 0xFFFF, sum = 0

 2989 16:43:55.578554  1, 0xFFFF, sum = 0

 2990 16:43:55.578703  2, 0xFFFF, sum = 0

 2991 16:43:55.581327  3, 0xFFFF, sum = 0

 2992 16:43:55.584924  4, 0xFFFF, sum = 0

 2993 16:43:55.585011  5, 0xFFFF, sum = 0

 2994 16:43:55.587920  6, 0xFFFF, sum = 0

 2995 16:43:55.588027  7, 0xFFFF, sum = 0

 2996 16:43:55.591808  8, 0xFFFF, sum = 0

 2997 16:43:55.591894  9, 0xFFFF, sum = 0

 2998 16:43:55.595238  10, 0xFFFF, sum = 0

 2999 16:43:55.595363  11, 0xFFFF, sum = 0

 3000 16:43:55.598256  12, 0x0, sum = 1

 3001 16:43:55.598342  13, 0x0, sum = 2

 3002 16:43:55.601886  14, 0x0, sum = 3

 3003 16:43:55.601972  15, 0x0, sum = 4

 3004 16:43:55.602058  best_step = 13

 3005 16:43:55.602138  

 3006 16:43:55.604852  ==

 3007 16:43:55.608449  Dram Type= 6, Freq= 0, CH_0, rank 1

 3008 16:43:55.611990  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3009 16:43:55.612145  ==

 3010 16:43:55.612272  RX Vref Scan: 0

 3011 16:43:55.612403  

 3012 16:43:55.614845  RX Vref 0 -> 0, step: 1

 3013 16:43:55.614947  

 3014 16:43:55.618436  RX Delay -21 -> 252, step: 4

 3015 16:43:55.621537  iDelay=195, Bit 0, Center 114 (43 ~ 186) 144

 3016 16:43:55.628644  iDelay=195, Bit 1, Center 114 (43 ~ 186) 144

 3017 16:43:55.631528  iDelay=195, Bit 2, Center 112 (43 ~ 182) 140

 3018 16:43:55.634971  iDelay=195, Bit 3, Center 114 (43 ~ 186) 144

 3019 16:43:55.638377  iDelay=195, Bit 4, Center 112 (43 ~ 182) 140

 3020 16:43:55.641578  iDelay=195, Bit 5, Center 106 (35 ~ 178) 144

 3021 16:43:55.644945  iDelay=195, Bit 6, Center 122 (51 ~ 194) 144

 3022 16:43:55.651818  iDelay=195, Bit 7, Center 122 (51 ~ 194) 144

 3023 16:43:55.655096  iDelay=195, Bit 8, Center 94 (27 ~ 162) 136

 3024 16:43:55.658369  iDelay=195, Bit 9, Center 92 (23 ~ 162) 140

 3025 16:43:55.662103  iDelay=195, Bit 10, Center 106 (39 ~ 174) 136

 3026 16:43:55.665433  iDelay=195, Bit 11, Center 94 (27 ~ 162) 136

 3027 16:43:55.671766  iDelay=195, Bit 12, Center 110 (43 ~ 178) 136

 3028 16:43:55.675277  iDelay=195, Bit 13, Center 112 (47 ~ 178) 132

 3029 16:43:55.678387  iDelay=195, Bit 14, Center 116 (51 ~ 182) 132

 3030 16:43:55.681774  iDelay=195, Bit 15, Center 114 (47 ~ 182) 136

 3031 16:43:55.681879  ==

 3032 16:43:55.684998  Dram Type= 6, Freq= 0, CH_0, rank 1

 3033 16:43:55.691524  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3034 16:43:55.691610  ==

 3035 16:43:55.691677  DQS Delay:

 3036 16:43:55.691740  DQS0 = 0, DQS1 = 0

 3037 16:43:55.695141  DQM Delay:

 3038 16:43:55.695225  DQM0 = 114, DQM1 = 104

 3039 16:43:55.698793  DQ Delay:

 3040 16:43:55.701727  DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114

 3041 16:43:55.705156  DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122

 3042 16:43:55.708317  DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94

 3043 16:43:55.711778  DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114

 3044 16:43:55.711863  

 3045 16:43:55.711930  

 3046 16:43:55.718288  [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps

 3047 16:43:55.721537  CH0 RK1: MR19=403, MR18=2F2

 3048 16:43:55.728226  CH0_RK1: MR19=0x403, MR18=0x2F2, DQSOSC=409, MR23=63, INC=39, DEC=26

 3049 16:43:55.731778  [RxdqsGatingPostProcess] freq 1200

 3050 16:43:55.738564  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3051 16:43:55.738652  best DQS0 dly(2T, 0.5T) = (0, 12)

 3052 16:43:55.741568  best DQS1 dly(2T, 0.5T) = (0, 12)

 3053 16:43:55.745006  best DQS0 P1 dly(2T, 0.5T) = (1, 0)

 3054 16:43:55.748388  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3055 16:43:55.751664  best DQS0 dly(2T, 0.5T) = (0, 11)

 3056 16:43:55.754969  best DQS1 dly(2T, 0.5T) = (0, 12)

 3057 16:43:55.758194  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3058 16:43:55.761644  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3059 16:43:55.765028  Pre-setting of DQS Precalculation

 3060 16:43:55.768298  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3061 16:43:55.771765  ==

 3062 16:43:55.771853  Dram Type= 6, Freq= 0, CH_1, rank 0

 3063 16:43:55.778791  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3064 16:43:55.778875  ==

 3065 16:43:55.781637  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3066 16:43:55.788012  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3067 16:43:55.797421  [CA 0] Center 38 (8~68) winsize 61

 3068 16:43:55.800816  [CA 1] Center 38 (8~68) winsize 61

 3069 16:43:55.804386  [CA 2] Center 35 (5~65) winsize 61

 3070 16:43:55.807483  [CA 3] Center 33 (3~64) winsize 62

 3071 16:43:55.810499  [CA 4] Center 34 (4~65) winsize 62

 3072 16:43:55.814067  [CA 5] Center 33 (3~64) winsize 62

 3073 16:43:55.814151  

 3074 16:43:55.817576  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3075 16:43:55.817687  

 3076 16:43:55.820596  [CATrainingPosCal] consider 1 rank data

 3077 16:43:55.824056  u2DelayCellTimex100 = 270/100 ps

 3078 16:43:55.827430  CA0 delay=38 (8~68),Diff = 5 PI (24 cell)

 3079 16:43:55.830880  CA1 delay=38 (8~68),Diff = 5 PI (24 cell)

 3080 16:43:55.837394  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3081 16:43:55.840829  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 3082 16:43:55.844317  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 3083 16:43:55.847339  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3084 16:43:55.847423  

 3085 16:43:55.850799  CA PerBit enable=1, Macro0, CA PI delay=33

 3086 16:43:55.850931  

 3087 16:43:55.854294  [CBTSetCACLKResult] CA Dly = 33

 3088 16:43:55.854378  CS Dly: 6 (0~37)

 3089 16:43:55.854445  ==

 3090 16:43:55.857612  Dram Type= 6, Freq= 0, CH_1, rank 1

 3091 16:43:55.864143  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3092 16:43:55.864230  ==

 3093 16:43:55.867441  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3094 16:43:55.874097  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35

 3095 16:43:55.883171  [CA 0] Center 38 (8~68) winsize 61

 3096 16:43:55.885938  [CA 1] Center 38 (8~68) winsize 61

 3097 16:43:55.889395  [CA 2] Center 34 (4~65) winsize 62

 3098 16:43:55.892857  [CA 3] Center 34 (4~65) winsize 62

 3099 16:43:55.896503  [CA 4] Center 34 (4~65) winsize 62

 3100 16:43:55.899543  [CA 5] Center 33 (3~63) winsize 61

 3101 16:43:55.899628  

 3102 16:43:55.902921  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3103 16:43:55.903004  

 3104 16:43:55.906220  [CATrainingPosCal] consider 2 rank data

 3105 16:43:55.909978  u2DelayCellTimex100 = 270/100 ps

 3106 16:43:55.913003  CA0 delay=38 (8~68),Diff = 5 PI (24 cell)

 3107 16:43:55.916484  CA1 delay=38 (8~68),Diff = 5 PI (24 cell)

 3108 16:43:55.923147  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3109 16:43:55.926171  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3110 16:43:55.929714  CA4 delay=34 (4~65),Diff = 1 PI (4 cell)

 3111 16:43:55.932664  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3112 16:43:55.932737  

 3113 16:43:55.936329  CA PerBit enable=1, Macro0, CA PI delay=33

 3114 16:43:55.936413  

 3115 16:43:55.939645  [CBTSetCACLKResult] CA Dly = 33

 3116 16:43:55.939755  CS Dly: 7 (0~40)

 3117 16:43:55.939850  

 3118 16:43:55.943118  ----->DramcWriteLeveling(PI) begin...

 3119 16:43:55.946149  ==

 3120 16:43:55.946233  Dram Type= 6, Freq= 0, CH_1, rank 0

 3121 16:43:55.953207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3122 16:43:55.953321  ==

 3123 16:43:55.956118  Write leveling (Byte 0): 25 => 25

 3124 16:43:55.959626  Write leveling (Byte 1): 30 => 30

 3125 16:43:55.959735  DramcWriteLeveling(PI) end<-----

 3126 16:43:55.962904  

 3127 16:43:55.962987  ==

 3128 16:43:55.966235  Dram Type= 6, Freq= 0, CH_1, rank 0

 3129 16:43:55.969607  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3130 16:43:55.969692  ==

 3131 16:43:55.972716  [Gating] SW mode calibration

 3132 16:43:55.979909  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3133 16:43:55.983057  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3134 16:43:55.989568   0 15  0 | B1->B0 | 2828 2323 | 0 1 | (0 0) (1 1)

 3135 16:43:55.993088   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)

 3136 16:43:55.996427   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3137 16:43:56.003098   0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 3138 16:43:56.006537   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3139 16:43:56.010043   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3140 16:43:56.016978   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3141 16:43:56.019986   0 15 28 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 0)

 3142 16:43:56.023019   1  0  0 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (1 0)

 3143 16:43:56.029569   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3144 16:43:56.033075   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3145 16:43:56.036604   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3146 16:43:56.040015   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3147 16:43:56.046853   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3148 16:43:56.049637   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3149 16:43:56.053375   1  0 28 | B1->B0 | 2626 2424 | 0 0 | (1 1) (1 1)

 3150 16:43:56.059749   1  1  0 | B1->B0 | 4545 3a3a | 0 1 | (0 0) (0 0)

 3151 16:43:56.063254   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3152 16:43:56.066515   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3153 16:43:56.073201   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3154 16:43:56.076518   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3155 16:43:56.079826   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3156 16:43:56.086477   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3157 16:43:56.090268   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3158 16:43:56.093413   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3159 16:43:56.100147   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3160 16:43:56.103652   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3161 16:43:56.106642   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3162 16:43:56.113712   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3163 16:43:56.116450   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3164 16:43:56.119971   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3165 16:43:56.126939   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3166 16:43:56.129948   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3167 16:43:56.133296   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3168 16:43:56.136232   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3169 16:43:56.143222   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3170 16:43:56.146499   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3171 16:43:56.150040   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3172 16:43:56.156599   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3173 16:43:56.160069   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3174 16:43:56.162986   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3175 16:43:56.170040   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3176 16:43:56.173025  Total UI for P1: 0, mck2ui 16

 3177 16:43:56.176352  best dqsien dly found for B0: ( 1,  3, 30)

 3178 16:43:56.176453  Total UI for P1: 0, mck2ui 16

 3179 16:43:56.183013  best dqsien dly found for B1: ( 1,  3, 30)

 3180 16:43:56.186245  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 3181 16:43:56.189801  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 3182 16:43:56.189935  

 3183 16:43:56.193004  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3184 16:43:56.196242  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3185 16:43:56.199750  [Gating] SW calibration Done

 3186 16:43:56.199838  ==

 3187 16:43:56.203195  Dram Type= 6, Freq= 0, CH_1, rank 0

 3188 16:43:56.206619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3189 16:43:56.206705  ==

 3190 16:43:56.209563  RX Vref Scan: 0

 3191 16:43:56.209672  

 3192 16:43:56.209774  RX Vref 0 -> 0, step: 1

 3193 16:43:56.209874  

 3194 16:43:56.213076  RX Delay -40 -> 252, step: 8

 3195 16:43:56.216491  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 3196 16:43:56.222857  iDelay=200, Bit 1, Center 111 (40 ~ 183) 144

 3197 16:43:56.226434  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3198 16:43:56.230087  iDelay=200, Bit 3, Center 115 (40 ~ 191) 152

 3199 16:43:56.232947  iDelay=200, Bit 4, Center 111 (40 ~ 183) 144

 3200 16:43:56.236299  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3201 16:43:56.242768  iDelay=200, Bit 6, Center 127 (64 ~ 191) 128

 3202 16:43:56.246360  iDelay=200, Bit 7, Center 111 (40 ~ 183) 144

 3203 16:43:56.249327  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 3204 16:43:56.253167  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 3205 16:43:56.256264  iDelay=200, Bit 10, Center 111 (40 ~ 183) 144

 3206 16:43:56.263054  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 3207 16:43:56.266365  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 3208 16:43:56.269389  iDelay=200, Bit 13, Center 115 (48 ~ 183) 136

 3209 16:43:56.272951  iDelay=200, Bit 14, Center 111 (40 ~ 183) 144

 3210 16:43:56.276476  iDelay=200, Bit 15, Center 111 (40 ~ 183) 144

 3211 16:43:56.279244  ==

 3212 16:43:56.283312  Dram Type= 6, Freq= 0, CH_1, rank 0

 3213 16:43:56.285983  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3214 16:43:56.286063  ==

 3215 16:43:56.286130  DQS Delay:

 3216 16:43:56.289223  DQS0 = 0, DQS1 = 0

 3217 16:43:56.289307  DQM Delay:

 3218 16:43:56.292500  DQM0 = 116, DQM1 = 109

 3219 16:43:56.292579  DQ Delay:

 3220 16:43:56.295891  DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115

 3221 16:43:56.299533  DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =111

 3222 16:43:56.303131  DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107

 3223 16:43:56.306005  DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111

 3224 16:43:56.306082  

 3225 16:43:56.306157  

 3226 16:43:56.306220  ==

 3227 16:43:56.309441  Dram Type= 6, Freq= 0, CH_1, rank 0

 3228 16:43:56.316425  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3229 16:43:56.316506  ==

 3230 16:43:56.316573  

 3231 16:43:56.316644  

 3232 16:43:56.316703  	TX Vref Scan disable

 3233 16:43:56.319322   == TX Byte 0 ==

 3234 16:43:56.322518  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3235 16:43:56.329459  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3236 16:43:56.329543   == TX Byte 1 ==

 3237 16:43:56.332603  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3238 16:43:56.339451  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3239 16:43:56.339539  ==

 3240 16:43:56.342965  Dram Type= 6, Freq= 0, CH_1, rank 0

 3241 16:43:56.345928  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3242 16:43:56.346027  ==

 3243 16:43:56.357611  TX Vref=22, minBit 3, minWin=24, winSum=413

 3244 16:43:56.361090  TX Vref=24, minBit 1, minWin=25, winSum=414

 3245 16:43:56.364544  TX Vref=26, minBit 15, minWin=25, winSum=423

 3246 16:43:56.367492  TX Vref=28, minBit 0, minWin=26, winSum=426

 3247 16:43:56.371107  TX Vref=30, minBit 1, minWin=26, winSum=428

 3248 16:43:56.377756  TX Vref=32, minBit 3, minWin=26, winSum=429

 3249 16:43:56.380724  [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 32

 3250 16:43:56.380811  

 3251 16:43:56.384038  Final TX Range 1 Vref 32

 3252 16:43:56.384125  

 3253 16:43:56.384192  ==

 3254 16:43:56.387507  Dram Type= 6, Freq= 0, CH_1, rank 0

 3255 16:43:56.391009  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3256 16:43:56.391096  ==

 3257 16:43:56.394316  

 3258 16:43:56.394403  

 3259 16:43:56.394470  	TX Vref Scan disable

 3260 16:43:56.397692   == TX Byte 0 ==

 3261 16:43:56.401045  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3262 16:43:56.404446  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3263 16:43:56.407292   == TX Byte 1 ==

 3264 16:43:56.410776  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3265 16:43:56.414202  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3266 16:43:56.414288  

 3267 16:43:56.417820  [DATLAT]

 3268 16:43:56.417905  Freq=1200, CH1 RK0

 3269 16:43:56.417974  

 3270 16:43:56.420834  DATLAT Default: 0xd

 3271 16:43:56.420918  0, 0xFFFF, sum = 0

 3272 16:43:56.424120  1, 0xFFFF, sum = 0

 3273 16:43:56.424214  2, 0xFFFF, sum = 0

 3274 16:43:56.427816  3, 0xFFFF, sum = 0

 3275 16:43:56.427901  4, 0xFFFF, sum = 0

 3276 16:43:56.430635  5, 0xFFFF, sum = 0

 3277 16:43:56.430722  6, 0xFFFF, sum = 0

 3278 16:43:56.434234  7, 0xFFFF, sum = 0

 3279 16:43:56.437879  8, 0xFFFF, sum = 0

 3280 16:43:56.437978  9, 0xFFFF, sum = 0

 3281 16:43:56.441087  10, 0xFFFF, sum = 0

 3282 16:43:56.441181  11, 0xFFFF, sum = 0

 3283 16:43:56.444041  12, 0x0, sum = 1

 3284 16:43:56.444127  13, 0x0, sum = 2

 3285 16:43:56.444201  14, 0x0, sum = 3

 3286 16:43:56.447751  15, 0x0, sum = 4

 3287 16:43:56.447865  best_step = 13

 3288 16:43:56.447964  

 3289 16:43:56.450942  ==

 3290 16:43:56.451058  Dram Type= 6, Freq= 0, CH_1, rank 0

 3291 16:43:56.457395  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3292 16:43:56.457509  ==

 3293 16:43:56.457603  RX Vref Scan: 1

 3294 16:43:56.457694  

 3295 16:43:56.460886  Set Vref Range= 32 -> 127

 3296 16:43:56.460987  

 3297 16:43:56.464337  RX Vref 32 -> 127, step: 1

 3298 16:43:56.464425  

 3299 16:43:56.467840  RX Delay -13 -> 252, step: 4

 3300 16:43:56.467922  

 3301 16:43:56.470749  Set Vref, RX VrefLevel [Byte0]: 32

 3302 16:43:56.474128                           [Byte1]: 32

 3303 16:43:56.474211  

 3304 16:43:56.477781  Set Vref, RX VrefLevel [Byte0]: 33

 3305 16:43:56.480699                           [Byte1]: 33

 3306 16:43:56.480781  

 3307 16:43:56.484296  Set Vref, RX VrefLevel [Byte0]: 34

 3308 16:43:56.487657                           [Byte1]: 34

 3309 16:43:56.491587  

 3310 16:43:56.491669  Set Vref, RX VrefLevel [Byte0]: 35

 3311 16:43:56.494871                           [Byte1]: 35

 3312 16:43:56.499418  

 3313 16:43:56.499500  Set Vref, RX VrefLevel [Byte0]: 36

 3314 16:43:56.502985                           [Byte1]: 36

 3315 16:43:56.507519  

 3316 16:43:56.507601  Set Vref, RX VrefLevel [Byte0]: 37

 3317 16:43:56.510712                           [Byte1]: 37

 3318 16:43:56.515308  

 3319 16:43:56.515391  Set Vref, RX VrefLevel [Byte0]: 38

 3320 16:43:56.518819                           [Byte1]: 38

 3321 16:43:56.522944  

 3322 16:43:56.523027  Set Vref, RX VrefLevel [Byte0]: 39

 3323 16:43:56.526469                           [Byte1]: 39

 3324 16:43:56.530900  

 3325 16:43:56.530982  Set Vref, RX VrefLevel [Byte0]: 40

 3326 16:43:56.534404                           [Byte1]: 40

 3327 16:43:56.539073  

 3328 16:43:56.539156  Set Vref, RX VrefLevel [Byte0]: 41

 3329 16:43:56.542438                           [Byte1]: 41

 3330 16:43:56.546663  

 3331 16:43:56.546744  Set Vref, RX VrefLevel [Byte0]: 42

 3332 16:43:56.550388                           [Byte1]: 42

 3333 16:43:56.554594  

 3334 16:43:56.554679  Set Vref, RX VrefLevel [Byte0]: 43

 3335 16:43:56.558066                           [Byte1]: 43

 3336 16:43:56.562942  

 3337 16:43:56.563040  Set Vref, RX VrefLevel [Byte0]: 44

 3338 16:43:56.565653                           [Byte1]: 44

 3339 16:43:56.570395  

 3340 16:43:56.570513  Set Vref, RX VrefLevel [Byte0]: 45

 3341 16:43:56.573980                           [Byte1]: 45

 3342 16:43:56.578666  

 3343 16:43:56.578817  Set Vref, RX VrefLevel [Byte0]: 46

 3344 16:43:56.581548                           [Byte1]: 46

 3345 16:43:56.586325  

 3346 16:43:56.586456  Set Vref, RX VrefLevel [Byte0]: 47

 3347 16:43:56.589770                           [Byte1]: 47

 3348 16:43:56.594329  

 3349 16:43:56.594444  Set Vref, RX VrefLevel [Byte0]: 48

 3350 16:43:56.597589                           [Byte1]: 48

 3351 16:43:56.601935  

 3352 16:43:56.602073  Set Vref, RX VrefLevel [Byte0]: 49

 3353 16:43:56.605210                           [Byte1]: 49

 3354 16:43:56.610080  

 3355 16:43:56.610244  Set Vref, RX VrefLevel [Byte0]: 50

 3356 16:43:56.613461                           [Byte1]: 50

 3357 16:43:56.617516  

 3358 16:43:56.620913  Set Vref, RX VrefLevel [Byte0]: 51

 3359 16:43:56.624328                           [Byte1]: 51

 3360 16:43:56.624473  

 3361 16:43:56.627402  Set Vref, RX VrefLevel [Byte0]: 52

 3362 16:43:56.631087                           [Byte1]: 52

 3363 16:43:56.631206  

 3364 16:43:56.633963  Set Vref, RX VrefLevel [Byte0]: 53

 3365 16:43:56.637347                           [Byte1]: 53

 3366 16:43:56.641446  

 3367 16:43:56.641531  Set Vref, RX VrefLevel [Byte0]: 54

 3368 16:43:56.644789                           [Byte1]: 54

 3369 16:43:56.649373  

 3370 16:43:56.649503  Set Vref, RX VrefLevel [Byte0]: 55

 3371 16:43:56.652933                           [Byte1]: 55

 3372 16:43:56.657069  

 3373 16:43:56.657180  Set Vref, RX VrefLevel [Byte0]: 56

 3374 16:43:56.660587                           [Byte1]: 56

 3375 16:43:56.665233  

 3376 16:43:56.665428  Set Vref, RX VrefLevel [Byte0]: 57

 3377 16:43:56.668203                           [Byte1]: 57

 3378 16:43:56.672893  

 3379 16:43:56.673051  Set Vref, RX VrefLevel [Byte0]: 58

 3380 16:43:56.676486                           [Byte1]: 58

 3381 16:43:56.680647  

 3382 16:43:56.680751  Set Vref, RX VrefLevel [Byte0]: 59

 3383 16:43:56.684094                           [Byte1]: 59

 3384 16:43:56.688828  

 3385 16:43:56.688919  Set Vref, RX VrefLevel [Byte0]: 60

 3386 16:43:56.691819                           [Byte1]: 60

 3387 16:43:56.696412  

 3388 16:43:56.696547  Set Vref, RX VrefLevel [Byte0]: 61

 3389 16:43:56.699801                           [Byte1]: 61

 3390 16:43:56.704403  

 3391 16:43:56.704537  Set Vref, RX VrefLevel [Byte0]: 62

 3392 16:43:56.707931                           [Byte1]: 62

 3393 16:43:56.712122  

 3394 16:43:56.712253  Set Vref, RX VrefLevel [Byte0]: 63

 3395 16:43:56.715328                           [Byte1]: 63

 3396 16:43:56.720430  

 3397 16:43:56.720552  Set Vref, RX VrefLevel [Byte0]: 64

 3398 16:43:56.723842                           [Byte1]: 64

 3399 16:43:56.727896  

 3400 16:43:56.728032  Set Vref, RX VrefLevel [Byte0]: 65

 3401 16:43:56.731279                           [Byte1]: 65

 3402 16:43:56.736028  

 3403 16:43:56.736112  Set Vref, RX VrefLevel [Byte0]: 66

 3404 16:43:56.739339                           [Byte1]: 66

 3405 16:43:56.743787  

 3406 16:43:56.743907  Set Vref, RX VrefLevel [Byte0]: 67

 3407 16:43:56.747183                           [Byte1]: 67

 3408 16:43:56.751784  

 3409 16:43:56.751938  Set Vref, RX VrefLevel [Byte0]: 68

 3410 16:43:56.755318                           [Byte1]: 68

 3411 16:43:56.759386  

 3412 16:43:56.759491  Set Vref, RX VrefLevel [Byte0]: 69

 3413 16:43:56.762868                           [Byte1]: 69

 3414 16:43:56.767180  

 3415 16:43:56.767255  Final RX Vref Byte 0 = 59 to rank0

 3416 16:43:56.770507  Final RX Vref Byte 1 = 53 to rank0

 3417 16:43:56.774105  Final RX Vref Byte 0 = 59 to rank1

 3418 16:43:56.777519  Final RX Vref Byte 1 = 53 to rank1==

 3419 16:43:56.780499  Dram Type= 6, Freq= 0, CH_1, rank 0

 3420 16:43:56.787174  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3421 16:43:56.787274  ==

 3422 16:43:56.787362  DQS Delay:

 3423 16:43:56.790745  DQS0 = 0, DQS1 = 0

 3424 16:43:56.790853  DQM Delay:

 3425 16:43:56.790956  DQM0 = 115, DQM1 = 109

 3426 16:43:56.793938  DQ Delay:

 3427 16:43:56.797196  DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112

 3428 16:43:56.800545  DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =112

 3429 16:43:56.803844  DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =104

 3430 16:43:56.807173  DQ12 =116, DQ13 =114, DQ14 =116, DQ15 =114

 3431 16:43:56.807261  

 3432 16:43:56.807328  

 3433 16:43:56.817339  [DQSOSCAuto] RK0, (LSB)MR18= 0xfce1, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps

 3434 16:43:56.817434  CH1 RK0: MR19=303, MR18=FCE1

 3435 16:43:56.824094  CH1_RK0: MR19=0x303, MR18=0xFCE1, DQSOSC=411, MR23=63, INC=38, DEC=25

 3436 16:43:56.824183  

 3437 16:43:56.827555  ----->DramcWriteLeveling(PI) begin...

 3438 16:43:56.827644  ==

 3439 16:43:56.830440  Dram Type= 6, Freq= 0, CH_1, rank 1

 3440 16:43:56.833940  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3441 16:43:56.837017  ==

 3442 16:43:56.840504  Write leveling (Byte 0): 26 => 26

 3443 16:43:56.840591  Write leveling (Byte 1): 27 => 27

 3444 16:43:56.844058  DramcWriteLeveling(PI) end<-----

 3445 16:43:56.844143  

 3446 16:43:56.844210  ==

 3447 16:43:56.847833  Dram Type= 6, Freq= 0, CH_1, rank 1

 3448 16:43:56.853822  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3449 16:43:56.853918  ==

 3450 16:43:56.856698  [Gating] SW mode calibration

 3451 16:43:56.863751  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3452 16:43:56.866687  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3453 16:43:56.873756   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)

 3454 16:43:56.876794   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3455 16:43:56.880365   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3456 16:43:56.886800   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3457 16:43:56.890347   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3458 16:43:56.893843   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3459 16:43:56.900286   0 15 24 | B1->B0 | 3434 2828 | 0 0 | (0 0) (1 0)

 3460 16:43:56.903732   0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 1) (0 0)

 3461 16:43:56.906956   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3462 16:43:56.910303   1  0  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 3463 16:43:56.916725   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3464 16:43:56.920146   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3465 16:43:56.923577   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3466 16:43:56.930238   1  0 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)

 3467 16:43:56.933891   1  0 24 | B1->B0 | 2626 3a3a | 0 0 | (0 0) (0 0)

 3468 16:43:56.936635   1  0 28 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)

 3469 16:43:56.943765   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3470 16:43:56.946820   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3471 16:43:56.950586   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3472 16:43:56.956633   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3473 16:43:56.960418   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3474 16:43:56.963620   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3475 16:43:56.970141   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 3476 16:43:56.973115   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 3477 16:43:56.976790   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3478 16:43:56.983070   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3479 16:43:56.986521   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3480 16:43:56.990075   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3481 16:43:56.996667   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3482 16:43:56.999822   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3483 16:43:57.003305   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3484 16:43:57.009643   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3485 16:43:57.012958   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3486 16:43:57.016415   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3487 16:43:57.023007   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3488 16:43:57.026273   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3489 16:43:57.029531   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3490 16:43:57.036373   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3491 16:43:57.039715   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3492 16:43:57.042533   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 3493 16:43:57.049710   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3494 16:43:57.049838  Total UI for P1: 0, mck2ui 16

 3495 16:43:57.055801  best dqsien dly found for B0: ( 1,  3, 26)

 3496 16:43:57.055952  Total UI for P1: 0, mck2ui 16

 3497 16:43:57.059714  best dqsien dly found for B1: ( 1,  3, 30)

 3498 16:43:57.065858  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3499 16:43:57.069423  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 3500 16:43:57.069544  

 3501 16:43:57.072517  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3502 16:43:57.076045  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 3503 16:43:57.079015  [Gating] SW calibration Done

 3504 16:43:57.079109  ==

 3505 16:43:57.082056  Dram Type= 6, Freq= 0, CH_1, rank 1

 3506 16:43:57.085642  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3507 16:43:57.085751  ==

 3508 16:43:57.088852  RX Vref Scan: 0

 3509 16:43:57.088957  

 3510 16:43:57.089056  RX Vref 0 -> 0, step: 1

 3511 16:43:57.089147  

 3512 16:43:57.092377  RX Delay -40 -> 252, step: 8

 3513 16:43:57.095339  iDelay=192, Bit 0, Center 115 (40 ~ 191) 152

 3514 16:43:57.102005  iDelay=192, Bit 1, Center 111 (40 ~ 183) 144

 3515 16:43:57.105433  iDelay=192, Bit 2, Center 103 (32 ~ 175) 144

 3516 16:43:57.108978  iDelay=192, Bit 3, Center 111 (40 ~ 183) 144

 3517 16:43:57.111912  iDelay=192, Bit 4, Center 111 (40 ~ 183) 144

 3518 16:43:57.115720  iDelay=192, Bit 5, Center 123 (56 ~ 191) 136

 3519 16:43:57.122051  iDelay=192, Bit 6, Center 119 (48 ~ 191) 144

 3520 16:43:57.125148  iDelay=192, Bit 7, Center 107 (40 ~ 175) 136

 3521 16:43:57.128536  iDelay=192, Bit 8, Center 99 (24 ~ 175) 152

 3522 16:43:57.131895  iDelay=192, Bit 9, Center 95 (24 ~ 167) 144

 3523 16:43:57.135382  iDelay=192, Bit 10, Center 111 (40 ~ 183) 144

 3524 16:43:57.142127  iDelay=192, Bit 11, Center 99 (32 ~ 167) 136

 3525 16:43:57.145496  iDelay=192, Bit 12, Center 115 (48 ~ 183) 136

 3526 16:43:57.148709  iDelay=192, Bit 13, Center 119 (48 ~ 191) 144

 3527 16:43:57.151681  iDelay=192, Bit 14, Center 119 (48 ~ 191) 144

 3528 16:43:57.155313  iDelay=192, Bit 15, Center 119 (48 ~ 191) 144

 3529 16:43:57.158273  ==

 3530 16:43:57.161620  Dram Type= 6, Freq= 0, CH_1, rank 1

 3531 16:43:57.164899  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3532 16:43:57.165019  ==

 3533 16:43:57.165116  DQS Delay:

 3534 16:43:57.168365  DQS0 = 0, DQS1 = 0

 3535 16:43:57.168478  DQM Delay:

 3536 16:43:57.172065  DQM0 = 112, DQM1 = 109

 3537 16:43:57.172175  DQ Delay:

 3538 16:43:57.174881  DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111

 3539 16:43:57.178352  DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107

 3540 16:43:57.181560  DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =99

 3541 16:43:57.184862  DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119

 3542 16:43:57.184996  

 3543 16:43:57.185093  

 3544 16:43:57.185189  ==

 3545 16:43:57.188549  Dram Type= 6, Freq= 0, CH_1, rank 1

 3546 16:43:57.194904  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3547 16:43:57.195034  ==

 3548 16:43:57.195106  

 3549 16:43:57.195177  

 3550 16:43:57.195280  	TX Vref Scan disable

 3551 16:43:57.198397   == TX Byte 0 ==

 3552 16:43:57.201561  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3553 16:43:57.208506  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3554 16:43:57.208628   == TX Byte 1 ==

 3555 16:43:57.211466  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3556 16:43:57.217926  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3557 16:43:57.218057  ==

 3558 16:43:57.221878  Dram Type= 6, Freq= 0, CH_1, rank 1

 3559 16:43:57.224694  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3560 16:43:57.224807  ==

 3561 16:43:57.236420  TX Vref=22, minBit 1, minWin=25, winSum=417

 3562 16:43:57.239345  TX Vref=24, minBit 1, minWin=25, winSum=421

 3563 16:43:57.243065  TX Vref=26, minBit 1, minWin=25, winSum=427

 3564 16:43:57.245824  TX Vref=28, minBit 10, minWin=26, winSum=428

 3565 16:43:57.249251  TX Vref=30, minBit 2, minWin=26, winSum=432

 3566 16:43:57.256587  TX Vref=32, minBit 9, minWin=26, winSum=435

 3567 16:43:57.259495  [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 32

 3568 16:43:57.259629  

 3569 16:43:57.262918  Final TX Range 1 Vref 32

 3570 16:43:57.263011  

 3571 16:43:57.263079  ==

 3572 16:43:57.266344  Dram Type= 6, Freq= 0, CH_1, rank 1

 3573 16:43:57.269621  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3574 16:43:57.269720  ==

 3575 16:43:57.273003  

 3576 16:43:57.273122  

 3577 16:43:57.273192  	TX Vref Scan disable

 3578 16:43:57.275701   == TX Byte 0 ==

 3579 16:43:57.279242  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3580 16:43:57.283082  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3581 16:43:57.285890   == TX Byte 1 ==

 3582 16:43:57.289502  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3583 16:43:57.292423  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3584 16:43:57.295864  

 3585 16:43:57.295988  [DATLAT]

 3586 16:43:57.296058  Freq=1200, CH1 RK1

 3587 16:43:57.296127  

 3588 16:43:57.299363  DATLAT Default: 0xd

 3589 16:43:57.299448  0, 0xFFFF, sum = 0

 3590 16:43:57.302425  1, 0xFFFF, sum = 0

 3591 16:43:57.302541  2, 0xFFFF, sum = 0

 3592 16:43:57.306063  3, 0xFFFF, sum = 0

 3593 16:43:57.309004  4, 0xFFFF, sum = 0

 3594 16:43:57.309144  5, 0xFFFF, sum = 0

 3595 16:43:57.312532  6, 0xFFFF, sum = 0

 3596 16:43:57.312637  7, 0xFFFF, sum = 0

 3597 16:43:57.316067  8, 0xFFFF, sum = 0

 3598 16:43:57.316160  9, 0xFFFF, sum = 0

 3599 16:43:57.319076  10, 0xFFFF, sum = 0

 3600 16:43:57.319171  11, 0xFFFF, sum = 0

 3601 16:43:57.322413  12, 0x0, sum = 1

 3602 16:43:57.322508  13, 0x0, sum = 2

 3603 16:43:57.325935  14, 0x0, sum = 3

 3604 16:43:57.326070  15, 0x0, sum = 4

 3605 16:43:57.326174  best_step = 13

 3606 16:43:57.328995  

 3607 16:43:57.329088  ==

 3608 16:43:57.332767  Dram Type= 6, Freq= 0, CH_1, rank 1

 3609 16:43:57.336009  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3610 16:43:57.336129  ==

 3611 16:43:57.336204  RX Vref Scan: 0

 3612 16:43:57.336269  

 3613 16:43:57.339315  RX Vref 0 -> 0, step: 1

 3614 16:43:57.339423  

 3615 16:43:57.342242  RX Delay -21 -> 252, step: 4

 3616 16:43:57.345732  iDelay=191, Bit 0, Center 112 (43 ~ 182) 140

 3617 16:43:57.352085  iDelay=191, Bit 1, Center 108 (43 ~ 174) 132

 3618 16:43:57.355454  iDelay=191, Bit 2, Center 104 (39 ~ 170) 132

 3619 16:43:57.358741  iDelay=191, Bit 3, Center 112 (47 ~ 178) 132

 3620 16:43:57.362302  iDelay=191, Bit 4, Center 116 (51 ~ 182) 132

 3621 16:43:57.365819  iDelay=191, Bit 5, Center 122 (59 ~ 186) 128

 3622 16:43:57.372231  iDelay=191, Bit 6, Center 122 (55 ~ 190) 136

 3623 16:43:57.375635  iDelay=191, Bit 7, Center 110 (47 ~ 174) 128

 3624 16:43:57.379073  iDelay=191, Bit 8, Center 98 (31 ~ 166) 136

 3625 16:43:57.382445  iDelay=191, Bit 9, Center 98 (35 ~ 162) 128

 3626 16:43:57.386129  iDelay=191, Bit 10, Center 110 (43 ~ 178) 136

 3627 16:43:57.392703  iDelay=191, Bit 11, Center 102 (35 ~ 170) 136

 3628 16:43:57.395674  iDelay=191, Bit 12, Center 114 (51 ~ 178) 128

 3629 16:43:57.399231  iDelay=191, Bit 13, Center 118 (55 ~ 182) 128

 3630 16:43:57.402593  iDelay=191, Bit 14, Center 118 (55 ~ 182) 128

 3631 16:43:57.405759  iDelay=191, Bit 15, Center 118 (55 ~ 182) 128

 3632 16:43:57.405894  ==

 3633 16:43:57.409127  Dram Type= 6, Freq= 0, CH_1, rank 1

 3634 16:43:57.415712  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3635 16:43:57.415866  ==

 3636 16:43:57.415978  DQS Delay:

 3637 16:43:57.419132  DQS0 = 0, DQS1 = 0

 3638 16:43:57.419254  DQM Delay:

 3639 16:43:57.422638  DQM0 = 113, DQM1 = 109

 3640 16:43:57.422755  DQ Delay:

 3641 16:43:57.425491  DQ0 =112, DQ1 =108, DQ2 =104, DQ3 =112

 3642 16:43:57.429134  DQ4 =116, DQ5 =122, DQ6 =122, DQ7 =110

 3643 16:43:57.432316  DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102

 3644 16:43:57.435736  DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =118

 3645 16:43:57.435865  

 3646 16:43:57.435973  

 3647 16:43:57.445780  [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 414 ps

 3648 16:43:57.445945  CH1 RK1: MR19=303, MR18=F6FE

 3649 16:43:57.452198  CH1_RK1: MR19=0x303, MR18=0xF6FE, DQSOSC=410, MR23=63, INC=39, DEC=26

 3650 16:43:57.455824  [RxdqsGatingPostProcess] freq 1200

 3651 16:43:57.462215  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3652 16:43:57.465837  best DQS0 dly(2T, 0.5T) = (0, 11)

 3653 16:43:57.469044  best DQS1 dly(2T, 0.5T) = (0, 11)

 3654 16:43:57.472424  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3655 16:43:57.475704  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3656 16:43:57.478632  best DQS0 dly(2T, 0.5T) = (0, 11)

 3657 16:43:57.478772  best DQS1 dly(2T, 0.5T) = (0, 11)

 3658 16:43:57.482319  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3659 16:43:57.485557  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3660 16:43:57.489207  Pre-setting of DQS Precalculation

 3661 16:43:57.495677  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3662 16:43:57.502304  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3663 16:43:57.509054  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3664 16:43:57.509200  

 3665 16:43:57.509279  

 3666 16:43:57.512041  [Calibration Summary] 2400 Mbps

 3667 16:43:57.515522  CH 0, Rank 0

 3668 16:43:57.515632  SW Impedance     : PASS

 3669 16:43:57.518568  DUTY Scan        : NO K

 3670 16:43:57.518672  ZQ Calibration   : PASS

 3671 16:43:57.522153  Jitter Meter     : NO K

 3672 16:43:57.525812  CBT Training     : PASS

 3673 16:43:57.525926  Write leveling   : PASS

 3674 16:43:57.529214  RX DQS gating    : PASS

 3675 16:43:57.531873  RX DQ/DQS(RDDQC) : PASS

 3676 16:43:57.532009  TX DQ/DQS        : PASS

 3677 16:43:57.535370  RX DATLAT        : PASS

 3678 16:43:57.538714  RX DQ/DQS(Engine): PASS

 3679 16:43:57.538867  TX OE            : NO K

 3680 16:43:57.542181  All Pass.

 3681 16:43:57.542335  

 3682 16:43:57.542439  CH 0, Rank 1

 3683 16:43:57.545073  SW Impedance     : PASS

 3684 16:43:57.545204  DUTY Scan        : NO K

 3685 16:43:57.548437  ZQ Calibration   : PASS

 3686 16:43:57.551938  Jitter Meter     : NO K

 3687 16:43:57.552099  CBT Training     : PASS

 3688 16:43:57.555271  Write leveling   : PASS

 3689 16:43:57.558850  RX DQS gating    : PASS

 3690 16:43:57.559010  RX DQ/DQS(RDDQC) : PASS

 3691 16:43:57.561754  TX DQ/DQS        : PASS

 3692 16:43:57.561885  RX DATLAT        : PASS

 3693 16:43:57.565435  RX DQ/DQS(Engine): PASS

 3694 16:43:57.568311  TX OE            : NO K

 3695 16:43:57.568453  All Pass.

 3696 16:43:57.568567  

 3697 16:43:57.568665  CH 1, Rank 0

 3698 16:43:57.572180  SW Impedance     : PASS

 3699 16:43:57.575472  DUTY Scan        : NO K

 3700 16:43:57.575615  ZQ Calibration   : PASS

 3701 16:43:57.578606  Jitter Meter     : NO K

 3702 16:43:57.581762  CBT Training     : PASS

 3703 16:43:57.581934  Write leveling   : PASS

 3704 16:43:57.585225  RX DQS gating    : PASS

 3705 16:43:57.588861  RX DQ/DQS(RDDQC) : PASS

 3706 16:43:57.589008  TX DQ/DQS        : PASS

 3707 16:43:57.591784  RX DATLAT        : PASS

 3708 16:43:57.595336  RX DQ/DQS(Engine): PASS

 3709 16:43:57.595479  TX OE            : NO K

 3710 16:43:57.598317  All Pass.

 3711 16:43:57.598442  

 3712 16:43:57.598555  CH 1, Rank 1

 3713 16:43:57.601819  SW Impedance     : PASS

 3714 16:43:57.601938  DUTY Scan        : NO K

 3715 16:43:57.605411  ZQ Calibration   : PASS

 3716 16:43:57.608391  Jitter Meter     : NO K

 3717 16:43:57.608523  CBT Training     : PASS

 3718 16:43:57.611902  Write leveling   : PASS

 3719 16:43:57.614946  RX DQS gating    : PASS

 3720 16:43:57.615087  RX DQ/DQS(RDDQC) : PASS

 3721 16:43:57.618616  TX DQ/DQS        : PASS

 3722 16:43:57.618771  RX DATLAT        : PASS

 3723 16:43:57.621592  RX DQ/DQS(Engine): PASS

 3724 16:43:57.624927  TX OE            : NO K

 3725 16:43:57.625076  All Pass.

 3726 16:43:57.625189  

 3727 16:43:57.627969  DramC Write-DBI off

 3728 16:43:57.628100  	PER_BANK_REFRESH: Hybrid Mode

 3729 16:43:57.631883  TX_TRACKING: ON

 3730 16:43:57.641615  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3731 16:43:57.645099  [FAST_K] Save calibration result to emmc

 3732 16:43:57.647828  dramc_set_vcore_voltage set vcore to 650000

 3733 16:43:57.651215  Read voltage for 600, 5

 3734 16:43:57.651381  Vio18 = 0

 3735 16:43:57.651494  Vcore = 650000

 3736 16:43:57.651593  Vdram = 0

 3737 16:43:57.654653  Vddq = 0

 3738 16:43:57.654797  Vmddr = 0

 3739 16:43:57.661004  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3740 16:43:57.664625  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3741 16:43:57.668251  MEM_TYPE=3, freq_sel=19

 3742 16:43:57.670934  sv_algorithm_assistance_LP4_1600 

 3743 16:43:57.674376  ============ PULL DRAM RESETB DOWN ============

 3744 16:43:57.677871  ========== PULL DRAM RESETB DOWN end =========

 3745 16:43:57.684589  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3746 16:43:57.688036  =================================== 

 3747 16:43:57.688164  LPDDR4 DRAM CONFIGURATION

 3748 16:43:57.691327  =================================== 

 3749 16:43:57.694333  EX_ROW_EN[0]    = 0x0

 3750 16:43:57.697812  EX_ROW_EN[1]    = 0x0

 3751 16:43:57.697924  LP4Y_EN      = 0x0

 3752 16:43:57.701398  WORK_FSP     = 0x0

 3753 16:43:57.701502  WL           = 0x2

 3754 16:43:57.704409  RL           = 0x2

 3755 16:43:57.704506  BL           = 0x2

 3756 16:43:57.708060  RPST         = 0x0

 3757 16:43:57.708163  RD_PRE       = 0x0

 3758 16:43:57.711017  WR_PRE       = 0x1

 3759 16:43:57.711114  WR_PST       = 0x0

 3760 16:43:57.714372  DBI_WR       = 0x0

 3761 16:43:57.714515  DBI_RD       = 0x0

 3762 16:43:57.718210  OTF          = 0x1

 3763 16:43:57.720856  =================================== 

 3764 16:43:57.724251  =================================== 

 3765 16:43:57.724368  ANA top config

 3766 16:43:57.727760  =================================== 

 3767 16:43:57.731605  DLL_ASYNC_EN            =  0

 3768 16:43:57.734547  ALL_SLAVE_EN            =  1

 3769 16:43:57.734657  NEW_RANK_MODE           =  1

 3770 16:43:57.737446  DLL_IDLE_MODE           =  1

 3771 16:43:57.740873  LP45_APHY_COMB_EN       =  1

 3772 16:43:57.744568  TX_ODT_DIS              =  1

 3773 16:43:57.748011  NEW_8X_MODE             =  1

 3774 16:43:57.751284  =================================== 

 3775 16:43:57.754591  =================================== 

 3776 16:43:57.754748  data_rate                  = 1200

 3777 16:43:57.757877  CKR                        = 1

 3778 16:43:57.761167  DQ_P2S_RATIO               = 8

 3779 16:43:57.764523  =================================== 

 3780 16:43:57.767602  CA_P2S_RATIO               = 8

 3781 16:43:57.771132  DQ_CA_OPEN                 = 0

 3782 16:43:57.774652  DQ_SEMI_OPEN               = 0

 3783 16:43:57.774788  CA_SEMI_OPEN               = 0

 3784 16:43:57.777968  CA_FULL_RATE               = 0

 3785 16:43:57.781183  DQ_CKDIV4_EN               = 1

 3786 16:43:57.784822  CA_CKDIV4_EN               = 1

 3787 16:43:57.787785  CA_PREDIV_EN               = 0

 3788 16:43:57.791055  PH8_DLY                    = 0

 3789 16:43:57.791187  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3790 16:43:57.794471  DQ_AAMCK_DIV               = 4

 3791 16:43:57.797362  CA_AAMCK_DIV               = 4

 3792 16:43:57.800985  CA_ADMCK_DIV               = 4

 3793 16:43:57.803979  DQ_TRACK_CA_EN             = 0

 3794 16:43:57.807493  CA_PICK                    = 600

 3795 16:43:57.807622  CA_MCKIO                   = 600

 3796 16:43:57.811020  MCKIO_SEMI                 = 0

 3797 16:43:57.814095  PLL_FREQ                   = 2288

 3798 16:43:57.817501  DQ_UI_PI_RATIO             = 32

 3799 16:43:57.821081  CA_UI_PI_RATIO             = 0

 3800 16:43:57.824154  =================================== 

 3801 16:43:57.827527  =================================== 

 3802 16:43:57.830968  memory_type:LPDDR4         

 3803 16:43:57.831128  GP_NUM     : 10       

 3804 16:43:57.833982  SRAM_EN    : 1       

 3805 16:43:57.834130  MD32_EN    : 0       

 3806 16:43:57.837723  =================================== 

 3807 16:43:57.840463  [ANA_INIT] >>>>>>>>>>>>>> 

 3808 16:43:57.844005  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3809 16:43:57.847569  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3810 16:43:57.850618  =================================== 

 3811 16:43:57.853769  data_rate = 1200,PCW = 0X5800

 3812 16:43:57.857021  =================================== 

 3813 16:43:57.860365  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3814 16:43:57.867323  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3815 16:43:57.870587  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3816 16:43:57.876930  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3817 16:43:57.880302  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3818 16:43:57.883574  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3819 16:43:57.883698  [ANA_INIT] flow start 

 3820 16:43:57.887023  [ANA_INIT] PLL >>>>>>>> 

 3821 16:43:57.890494  [ANA_INIT] PLL <<<<<<<< 

 3822 16:43:57.890628  [ANA_INIT] MIDPI >>>>>>>> 

 3823 16:43:57.893783  [ANA_INIT] MIDPI <<<<<<<< 

 3824 16:43:57.897101  [ANA_INIT] DLL >>>>>>>> 

 3825 16:43:57.897219  [ANA_INIT] flow end 

 3826 16:43:57.904193  ============ LP4 DIFF to SE enter ============

 3827 16:43:57.907560  ============ LP4 DIFF to SE exit  ============

 3828 16:43:57.910563  [ANA_INIT] <<<<<<<<<<<<< 

 3829 16:43:57.913632  [Flow] Enable top DCM control >>>>> 

 3830 16:43:57.913752  [Flow] Enable top DCM control <<<<< 

 3831 16:43:57.916696  Enable DLL master slave shuffle 

 3832 16:43:57.923751  ============================================================== 

 3833 16:43:57.927249  Gating Mode config

 3834 16:43:57.930035  ============================================================== 

 3835 16:43:57.933737  Config description: 

 3836 16:43:57.943712  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3837 16:43:57.950110  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3838 16:43:57.953782  SELPH_MODE            0: By rank         1: By Phase 

 3839 16:43:57.960240  ============================================================== 

 3840 16:43:57.964199  GAT_TRACK_EN                 =  1

 3841 16:43:57.967124  RX_GATING_MODE               =  2

 3842 16:43:57.970345  RX_GATING_TRACK_MODE         =  2

 3843 16:43:57.970481  SELPH_MODE                   =  1

 3844 16:43:57.973705  PICG_EARLY_EN                =  1

 3845 16:43:57.976971  VALID_LAT_VALUE              =  1

 3846 16:43:57.983208  ============================================================== 

 3847 16:43:57.987000  Enter into Gating configuration >>>> 

 3848 16:43:57.990561  Exit from Gating configuration <<<< 

 3849 16:43:57.993350  Enter into  DVFS_PRE_config >>>>> 

 3850 16:43:58.003567  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3851 16:43:58.007109  Exit from  DVFS_PRE_config <<<<< 

 3852 16:43:58.010153  Enter into PICG configuration >>>> 

 3853 16:43:58.013240  Exit from PICG configuration <<<< 

 3854 16:43:58.016921  [RX_INPUT] configuration >>>>> 

 3855 16:43:58.019667  [RX_INPUT] configuration <<<<< 

 3856 16:43:58.023107  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3857 16:43:58.029941  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3858 16:43:58.036511  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3859 16:43:58.042923  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3860 16:43:58.049751  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3861 16:43:58.053321  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3862 16:43:58.059912  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3863 16:43:58.062974  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3864 16:43:58.066392  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3865 16:43:58.069759  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3866 16:43:58.075911  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3867 16:43:58.079277  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3868 16:43:58.083068  =================================== 

 3869 16:43:58.086348  LPDDR4 DRAM CONFIGURATION

 3870 16:43:58.089749  =================================== 

 3871 16:43:58.089878  EX_ROW_EN[0]    = 0x0

 3872 16:43:58.093029  EX_ROW_EN[1]    = 0x0

 3873 16:43:58.093150  LP4Y_EN      = 0x0

 3874 16:43:58.096232  WORK_FSP     = 0x0

 3875 16:43:58.096347  WL           = 0x2

 3876 16:43:58.099594  RL           = 0x2

 3877 16:43:58.099708  BL           = 0x2

 3878 16:43:58.102949  RPST         = 0x0

 3879 16:43:58.103070  RD_PRE       = 0x0

 3880 16:43:58.106264  WR_PRE       = 0x1

 3881 16:43:58.106388  WR_PST       = 0x0

 3882 16:43:58.109729  DBI_WR       = 0x0

 3883 16:43:58.109845  DBI_RD       = 0x0

 3884 16:43:58.112639  OTF          = 0x1

 3885 16:43:58.116431  =================================== 

 3886 16:43:58.119262  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3887 16:43:58.122786  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3888 16:43:58.129290  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3889 16:43:58.132773  =================================== 

 3890 16:43:58.136200  LPDDR4 DRAM CONFIGURATION

 3891 16:43:58.136341  =================================== 

 3892 16:43:58.139162  EX_ROW_EN[0]    = 0x10

 3893 16:43:58.142724  EX_ROW_EN[1]    = 0x0

 3894 16:43:58.142858  LP4Y_EN      = 0x0

 3895 16:43:58.146312  WORK_FSP     = 0x0

 3896 16:43:58.146411  WL           = 0x2

 3897 16:43:58.149123  RL           = 0x2

 3898 16:43:58.149212  BL           = 0x2

 3899 16:43:58.152681  RPST         = 0x0

 3900 16:43:58.152779  RD_PRE       = 0x0

 3901 16:43:58.155904  WR_PRE       = 0x1

 3902 16:43:58.156018  WR_PST       = 0x0

 3903 16:43:58.159329  DBI_WR       = 0x0

 3904 16:43:58.159422  DBI_RD       = 0x0

 3905 16:43:58.162300  OTF          = 0x1

 3906 16:43:58.165890  =================================== 

 3907 16:43:58.172357  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3908 16:43:58.175801  nWR fixed to 30

 3909 16:43:58.179241  [ModeRegInit_LP4] CH0 RK0

 3910 16:43:58.179338  [ModeRegInit_LP4] CH0 RK1

 3911 16:43:58.182533  [ModeRegInit_LP4] CH1 RK0

 3912 16:43:58.185405  [ModeRegInit_LP4] CH1 RK1

 3913 16:43:58.185498  match AC timing 17

 3914 16:43:58.192536  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3915 16:43:58.195670  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3916 16:43:58.198800  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3917 16:43:58.205920  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3918 16:43:58.209081  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3919 16:43:58.209190  ==

 3920 16:43:58.211979  Dram Type= 6, Freq= 0, CH_0, rank 0

 3921 16:43:58.215435  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3922 16:43:58.215538  ==

 3923 16:43:58.222018  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3924 16:43:58.228925  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3925 16:43:58.232011  [CA 0] Center 36 (6~67) winsize 62

 3926 16:43:58.235377  [CA 1] Center 36 (6~66) winsize 61

 3927 16:43:58.238753  [CA 2] Center 34 (4~65) winsize 62

 3928 16:43:58.242081  [CA 3] Center 34 (4~64) winsize 61

 3929 16:43:58.246082  [CA 4] Center 33 (3~64) winsize 62

 3930 16:43:58.248673  [CA 5] Center 33 (3~64) winsize 62

 3931 16:43:58.248773  

 3932 16:43:58.252150  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3933 16:43:58.252244  

 3934 16:43:58.255806  [CATrainingPosCal] consider 1 rank data

 3935 16:43:58.258692  u2DelayCellTimex100 = 270/100 ps

 3936 16:43:58.262290  CA0 delay=36 (6~67),Diff = 3 PI (28 cell)

 3937 16:43:58.265312  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3938 16:43:58.268766  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3939 16:43:58.272326  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 3940 16:43:58.275744  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3941 16:43:58.278780  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3942 16:43:58.278877  

 3943 16:43:58.285735  CA PerBit enable=1, Macro0, CA PI delay=33

 3944 16:43:58.285863  

 3945 16:43:58.288746  [CBTSetCACLKResult] CA Dly = 33

 3946 16:43:58.288861  CS Dly: 6 (0~37)

 3947 16:43:58.288958  ==

 3948 16:43:58.292035  Dram Type= 6, Freq= 0, CH_0, rank 1

 3949 16:43:58.295389  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3950 16:43:58.295479  ==

 3951 16:43:58.302235  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3952 16:43:58.308761  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3953 16:43:58.311838  [CA 0] Center 36 (6~66) winsize 61

 3954 16:43:58.315256  [CA 1] Center 36 (6~66) winsize 61

 3955 16:43:58.319101  [CA 2] Center 34 (4~65) winsize 62

 3956 16:43:58.321892  [CA 3] Center 34 (4~64) winsize 61

 3957 16:43:58.325358  [CA 4] Center 33 (3~64) winsize 62

 3958 16:43:58.328900  [CA 5] Center 33 (3~64) winsize 62

 3959 16:43:58.329005  

 3960 16:43:58.332324  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3961 16:43:58.332416  

 3962 16:43:58.335541  [CATrainingPosCal] consider 2 rank data

 3963 16:43:58.338873  u2DelayCellTimex100 = 270/100 ps

 3964 16:43:58.342109  CA0 delay=36 (6~66),Diff = 3 PI (28 cell)

 3965 16:43:58.345009  CA1 delay=36 (6~66),Diff = 3 PI (28 cell)

 3966 16:43:58.348574  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 3967 16:43:58.351487  CA3 delay=34 (4~64),Diff = 1 PI (9 cell)

 3968 16:43:58.355020  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 3969 16:43:58.362205  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 3970 16:43:58.362360  

 3971 16:43:58.365439  CA PerBit enable=1, Macro0, CA PI delay=33

 3972 16:43:58.365549  

 3973 16:43:58.368363  [CBTSetCACLKResult] CA Dly = 33

 3974 16:43:58.368442  CS Dly: 5 (0~36)

 3975 16:43:58.368506  

 3976 16:43:58.372015  ----->DramcWriteLeveling(PI) begin...

 3977 16:43:58.372120  ==

 3978 16:43:58.374924  Dram Type= 6, Freq= 0, CH_0, rank 0

 3979 16:43:58.381365  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3980 16:43:58.381501  ==

 3981 16:43:58.384876  Write leveling (Byte 0): 31 => 31

 3982 16:43:58.384965  Write leveling (Byte 1): 30 => 30

 3983 16:43:58.388289  DramcWriteLeveling(PI) end<-----

 3984 16:43:58.388400  

 3985 16:43:58.388493  ==

 3986 16:43:58.391788  Dram Type= 6, Freq= 0, CH_0, rank 0

 3987 16:43:58.398161  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3988 16:43:58.398307  ==

 3989 16:43:58.401843  [Gating] SW mode calibration

 3990 16:43:58.408132  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3991 16:43:58.411318  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3992 16:43:58.417983   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3993 16:43:58.421364   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3994 16:43:58.424821   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3995 16:43:58.431427   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3996 16:43:58.434918   0  9 16 | B1->B0 | 3131 2e2e | 0 0 | (0 0) (0 0)

 3997 16:43:58.437964   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3998 16:43:58.444790   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3999 16:43:58.448243   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4000 16:43:58.452260   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4001 16:43:58.454638   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4002 16:43:58.461213   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4003 16:43:58.464777   0 10 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4004 16:43:58.468062   0 10 16 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)

 4005 16:43:58.474924   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4006 16:43:58.477852   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4007 16:43:58.481388   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4008 16:43:58.488193   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4009 16:43:58.491213   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4010 16:43:58.494611   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4011 16:43:58.500916   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4012 16:43:58.504383   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4013 16:43:58.507848   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4014 16:43:58.514392   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4015 16:43:58.517618   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4016 16:43:58.520976   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4017 16:43:58.527765   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4018 16:43:58.531123   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4019 16:43:58.534326   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4020 16:43:58.540687   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4021 16:43:58.544313   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4022 16:43:58.547743   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4023 16:43:58.554186   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4024 16:43:58.557531   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4025 16:43:58.560947   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4026 16:43:58.567521   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4027 16:43:58.570479   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4028 16:43:58.574004   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4029 16:43:58.577500  Total UI for P1: 0, mck2ui 16

 4030 16:43:58.580499  best dqsien dly found for B0: ( 0, 13, 14)

 4031 16:43:58.587643   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4032 16:43:58.590371   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4033 16:43:58.593980  Total UI for P1: 0, mck2ui 16

 4034 16:43:58.597372  best dqsien dly found for B1: ( 0, 13, 18)

 4035 16:43:58.600448  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4036 16:43:58.603718  best DQS1 dly(MCK, UI, PI) = (0, 13, 18)

 4037 16:43:58.603836  

 4038 16:43:58.607331  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4039 16:43:58.610415  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)

 4040 16:43:58.613810  [Gating] SW calibration Done

 4041 16:43:58.613896  ==

 4042 16:43:58.617741  Dram Type= 6, Freq= 0, CH_0, rank 0

 4043 16:43:58.620531  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4044 16:43:58.623579  ==

 4045 16:43:58.623667  RX Vref Scan: 0

 4046 16:43:58.623738  

 4047 16:43:58.627032  RX Vref 0 -> 0, step: 1

 4048 16:43:58.627143  

 4049 16:43:58.630521  RX Delay -230 -> 252, step: 16

 4050 16:43:58.634102  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4051 16:43:58.637105  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4052 16:43:58.640589  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4053 16:43:58.643715  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4054 16:43:58.650441  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4055 16:43:58.654196  iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336

 4056 16:43:58.657098  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4057 16:43:58.660361  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4058 16:43:58.666751  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4059 16:43:58.670340  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4060 16:43:58.673470  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4061 16:43:58.677482  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4062 16:43:58.683542  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4063 16:43:58.687010  iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336

 4064 16:43:58.690084  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4065 16:43:58.693639  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4066 16:43:58.693740  ==

 4067 16:43:58.696528  Dram Type= 6, Freq= 0, CH_0, rank 0

 4068 16:43:58.703616  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4069 16:43:58.703781  ==

 4070 16:43:58.703882  DQS Delay:

 4071 16:43:58.706630  DQS0 = 0, DQS1 = 0

 4072 16:43:58.706749  DQM Delay:

 4073 16:43:58.706861  DQM0 = 39, DQM1 = 31

 4074 16:43:58.709850  DQ Delay:

 4075 16:43:58.713568  DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33

 4076 16:43:58.716507  DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49

 4077 16:43:58.719863  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4078 16:43:58.723046  DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41

 4079 16:43:58.723172  

 4080 16:43:58.723242  

 4081 16:43:58.723306  ==

 4082 16:43:58.726535  Dram Type= 6, Freq= 0, CH_0, rank 0

 4083 16:43:58.730000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4084 16:43:58.730106  ==

 4085 16:43:58.730192  

 4086 16:43:58.730255  

 4087 16:43:58.733395  	TX Vref Scan disable

 4088 16:43:58.736824   == TX Byte 0 ==

 4089 16:43:58.739751  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4090 16:43:58.743184  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4091 16:43:58.746825   == TX Byte 1 ==

 4092 16:43:58.749762  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4093 16:43:58.753337  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4094 16:43:58.753453  ==

 4095 16:43:58.756819  Dram Type= 6, Freq= 0, CH_0, rank 0

 4096 16:43:58.760414  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4097 16:43:58.760537  ==

 4098 16:43:58.762928  

 4099 16:43:58.763051  

 4100 16:43:58.763144  	TX Vref Scan disable

 4101 16:43:58.766722   == TX Byte 0 ==

 4102 16:43:58.770293  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4103 16:43:58.776917  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4104 16:43:58.777040   == TX Byte 1 ==

 4105 16:43:58.779809  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4106 16:43:58.786888  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4107 16:43:58.787029  

 4108 16:43:58.787100  [DATLAT]

 4109 16:43:58.787162  Freq=600, CH0 RK0

 4110 16:43:58.787222  

 4111 16:43:58.789865  DATLAT Default: 0x9

 4112 16:43:58.789968  0, 0xFFFF, sum = 0

 4113 16:43:58.793456  1, 0xFFFF, sum = 0

 4114 16:43:58.793571  2, 0xFFFF, sum = 0

 4115 16:43:58.796455  3, 0xFFFF, sum = 0

 4116 16:43:58.800052  4, 0xFFFF, sum = 0

 4117 16:43:58.800140  5, 0xFFFF, sum = 0

 4118 16:43:58.803490  6, 0xFFFF, sum = 0

 4119 16:43:58.803607  7, 0xFFFF, sum = 0

 4120 16:43:58.806504  8, 0x0, sum = 1

 4121 16:43:58.806599  9, 0x0, sum = 2

 4122 16:43:58.806668  10, 0x0, sum = 3

 4123 16:43:58.809979  11, 0x0, sum = 4

 4124 16:43:58.810091  best_step = 9

 4125 16:43:58.810182  

 4126 16:43:58.810270  ==

 4127 16:43:58.813423  Dram Type= 6, Freq= 0, CH_0, rank 0

 4128 16:43:58.819648  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4129 16:43:58.819793  ==

 4130 16:43:58.819891  RX Vref Scan: 1

 4131 16:43:58.819987  

 4132 16:43:58.823261  RX Vref 0 -> 0, step: 1

 4133 16:43:58.823357  

 4134 16:43:58.826349  RX Delay -195 -> 252, step: 8

 4135 16:43:58.826440  

 4136 16:43:58.829586  Set Vref, RX VrefLevel [Byte0]: 55

 4137 16:43:58.833373                           [Byte1]: 51

 4138 16:43:58.833506  

 4139 16:43:58.836848  Final RX Vref Byte 0 = 55 to rank0

 4140 16:43:58.840167  Final RX Vref Byte 1 = 51 to rank0

 4141 16:43:58.842921  Final RX Vref Byte 0 = 55 to rank1

 4142 16:43:58.846793  Final RX Vref Byte 1 = 51 to rank1==

 4143 16:43:58.849692  Dram Type= 6, Freq= 0, CH_0, rank 0

 4144 16:43:58.853203  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4145 16:43:58.853335  ==

 4146 16:43:58.856847  DQS Delay:

 4147 16:43:58.856984  DQS0 = 0, DQS1 = 0

 4148 16:43:58.859516  DQM Delay:

 4149 16:43:58.859632  DQM0 = 42, DQM1 = 34

 4150 16:43:58.859729  DQ Delay:

 4151 16:43:58.863321  DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40

 4152 16:43:58.866128  DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48

 4153 16:43:58.869465  DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28

 4154 16:43:58.873428  DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44

 4155 16:43:58.873563  

 4156 16:43:58.873662  

 4157 16:43:58.883156  [DQSOSCAuto] RK0, (LSB)MR18= 0x401e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 397 ps

 4158 16:43:58.886407  CH0 RK0: MR19=808, MR18=401E

 4159 16:43:58.893078  CH0_RK0: MR19=0x808, MR18=0x401E, DQSOSC=397, MR23=63, INC=166, DEC=110

 4160 16:43:58.893241  

 4161 16:43:58.896167  ----->DramcWriteLeveling(PI) begin...

 4162 16:43:58.896300  ==

 4163 16:43:58.899678  Dram Type= 6, Freq= 0, CH_0, rank 1

 4164 16:43:58.902538  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4165 16:43:58.902666  ==

 4166 16:43:58.905807  Write leveling (Byte 0): 32 => 32

 4167 16:43:58.909294  Write leveling (Byte 1): 31 => 31

 4168 16:43:58.912920  DramcWriteLeveling(PI) end<-----

 4169 16:43:58.913067  

 4170 16:43:58.913180  ==

 4171 16:43:58.915882  Dram Type= 6, Freq= 0, CH_0, rank 1

 4172 16:43:58.919564  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4173 16:43:58.919671  ==

 4174 16:43:58.923086  [Gating] SW mode calibration

 4175 16:43:58.929100  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4176 16:43:58.935572  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4177 16:43:58.939099   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4178 16:43:58.942413   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4179 16:43:58.948845   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4180 16:43:58.952298   0  9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 4181 16:43:58.955743   0  9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)

 4182 16:43:58.962302   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4183 16:43:58.965728   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4184 16:43:58.969159   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4185 16:43:58.975932   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4186 16:43:58.979109   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4187 16:43:58.982395   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4188 16:43:58.988829   0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)

 4189 16:43:58.992411   0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)

 4190 16:43:58.995469   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4191 16:43:58.999057   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4192 16:43:59.005770   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4193 16:43:59.008935   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4194 16:43:59.011963   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4195 16:43:59.018814   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4196 16:43:59.022320   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4197 16:43:59.025693   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4198 16:43:59.032357   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4199 16:43:59.035639   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4200 16:43:59.038860   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4201 16:43:59.045610   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4202 16:43:59.049403   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4203 16:43:59.051738   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4204 16:43:59.058898   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4205 16:43:59.062327   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4206 16:43:59.065370   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4207 16:43:59.071726   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4208 16:43:59.075191   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4209 16:43:59.078545   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4210 16:43:59.084951   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4211 16:43:59.088554   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4212 16:43:59.092147   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4213 16:43:59.098406   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4214 16:43:59.098540  Total UI for P1: 0, mck2ui 16

 4215 16:43:59.104971  best dqsien dly found for B0: ( 0, 13, 12)

 4216 16:43:59.108513   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4217 16:43:59.111965  Total UI for P1: 0, mck2ui 16

 4218 16:43:59.114923  best dqsien dly found for B1: ( 0, 13, 16)

 4219 16:43:59.118272  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4220 16:43:59.121883  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4221 16:43:59.122005  

 4222 16:43:59.125108  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4223 16:43:59.128630  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4224 16:43:59.131842  [Gating] SW calibration Done

 4225 16:43:59.131983  ==

 4226 16:43:59.135065  Dram Type= 6, Freq= 0, CH_0, rank 1

 4227 16:43:59.137976  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4228 16:43:59.141792  ==

 4229 16:43:59.141918  RX Vref Scan: 0

 4230 16:43:59.142014  

 4231 16:43:59.144583  RX Vref 0 -> 0, step: 1

 4232 16:43:59.144689  

 4233 16:43:59.148115  RX Delay -230 -> 252, step: 16

 4234 16:43:59.151442  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4235 16:43:59.155060  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4236 16:43:59.158271  iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336

 4237 16:43:59.164667  iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336

 4238 16:43:59.168268  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4239 16:43:59.171623  iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320

 4240 16:43:59.174715  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4241 16:43:59.178128  iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336

 4242 16:43:59.184578  iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336

 4243 16:43:59.188187  iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336

 4244 16:43:59.191384  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4245 16:43:59.194637  iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320

 4246 16:43:59.201114  iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336

 4247 16:43:59.204840  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4248 16:43:59.208263  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4249 16:43:59.211358  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4250 16:43:59.211459  ==

 4251 16:43:59.214272  Dram Type= 6, Freq= 0, CH_0, rank 1

 4252 16:43:59.221081  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4253 16:43:59.221209  ==

 4254 16:43:59.221282  DQS Delay:

 4255 16:43:59.224415  DQS0 = 0, DQS1 = 0

 4256 16:43:59.224537  DQM Delay:

 4257 16:43:59.224647  DQM0 = 39, DQM1 = 32

 4258 16:43:59.228136  DQ Delay:

 4259 16:43:59.231009  DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33

 4260 16:43:59.234202  DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49

 4261 16:43:59.237567  DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25

 4262 16:43:59.240983  DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41

 4263 16:43:59.241121  

 4264 16:43:59.241216  

 4265 16:43:59.241311  ==

 4266 16:43:59.244263  Dram Type= 6, Freq= 0, CH_0, rank 1

 4267 16:43:59.247731  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4268 16:43:59.247856  ==

 4269 16:43:59.247952  

 4270 16:43:59.248051  

 4271 16:43:59.251183  	TX Vref Scan disable

 4272 16:43:59.254517   == TX Byte 0 ==

 4273 16:43:59.257416  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4274 16:43:59.260733  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4275 16:43:59.264223   == TX Byte 1 ==

 4276 16:43:59.267636  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4277 16:43:59.271422  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4278 16:43:59.271529  ==

 4279 16:43:59.274094  Dram Type= 6, Freq= 0, CH_0, rank 1

 4280 16:43:59.277725  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4281 16:43:59.280564  ==

 4282 16:43:59.280660  

 4283 16:43:59.280742  

 4284 16:43:59.280807  	TX Vref Scan disable

 4285 16:43:59.284843   == TX Byte 0 ==

 4286 16:43:59.287726  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4287 16:43:59.294271  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4288 16:43:59.294387   == TX Byte 1 ==

 4289 16:43:59.297701  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4290 16:43:59.304178  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4291 16:43:59.304289  

 4292 16:43:59.304355  [DATLAT]

 4293 16:43:59.304419  Freq=600, CH0 RK1

 4294 16:43:59.304481  

 4295 16:43:59.307820  DATLAT Default: 0x9

 4296 16:43:59.307938  0, 0xFFFF, sum = 0

 4297 16:43:59.311352  1, 0xFFFF, sum = 0

 4298 16:43:59.314345  2, 0xFFFF, sum = 0

 4299 16:43:59.314427  3, 0xFFFF, sum = 0

 4300 16:43:59.317469  4, 0xFFFF, sum = 0

 4301 16:43:59.317584  5, 0xFFFF, sum = 0

 4302 16:43:59.321047  6, 0xFFFF, sum = 0

 4303 16:43:59.321130  7, 0xFFFF, sum = 0

 4304 16:43:59.324461  8, 0x0, sum = 1

 4305 16:43:59.324553  9, 0x0, sum = 2

 4306 16:43:59.324623  10, 0x0, sum = 3

 4307 16:43:59.327758  11, 0x0, sum = 4

 4308 16:43:59.327882  best_step = 9

 4309 16:43:59.327987  

 4310 16:43:59.328077  ==

 4311 16:43:59.330885  Dram Type= 6, Freq= 0, CH_0, rank 1

 4312 16:43:59.337329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4313 16:43:59.337464  ==

 4314 16:43:59.337562  RX Vref Scan: 0

 4315 16:43:59.337651  

 4316 16:43:59.340763  RX Vref 0 -> 0, step: 1

 4317 16:43:59.340863  

 4318 16:43:59.343944  RX Delay -195 -> 252, step: 8

 4319 16:43:59.347373  iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312

 4320 16:43:59.354245  iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312

 4321 16:43:59.357708  iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304

 4322 16:43:59.361131  iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312

 4323 16:43:59.364454  iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304

 4324 16:43:59.370613  iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304

 4325 16:43:59.374107  iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312

 4326 16:43:59.377742  iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312

 4327 16:43:59.380769  iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312

 4328 16:43:59.384323  iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312

 4329 16:43:59.390990  iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312

 4330 16:43:59.394047  iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296

 4331 16:43:59.397636  iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320

 4332 16:43:59.400435  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4333 16:43:59.407881  iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312

 4334 16:43:59.410478  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4335 16:43:59.410596  ==

 4336 16:43:59.414113  Dram Type= 6, Freq= 0, CH_0, rank 1

 4337 16:43:59.417187  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4338 16:43:59.417304  ==

 4339 16:43:59.420683  DQS Delay:

 4340 16:43:59.420788  DQS0 = 0, DQS1 = 0

 4341 16:43:59.420872  DQM Delay:

 4342 16:43:59.424327  DQM0 = 39, DQM1 = 32

 4343 16:43:59.424411  DQ Delay:

 4344 16:43:59.426977  DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40

 4345 16:43:59.430418  DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48

 4346 16:43:59.433776  DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24

 4347 16:43:59.437151  DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40

 4348 16:43:59.437244  

 4349 16:43:59.437310  

 4350 16:43:59.447262  [DQSOSCAuto] RK1, (LSB)MR18= 0x5032, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps

 4351 16:43:59.450635  CH0 RK1: MR19=808, MR18=5032

 4352 16:43:59.454044  CH0_RK1: MR19=0x808, MR18=0x5032, DQSOSC=394, MR23=63, INC=168, DEC=112

 4353 16:43:59.457519  [RxdqsGatingPostProcess] freq 600

 4354 16:43:59.463893  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4355 16:43:59.467306  Pre-setting of DQS Precalculation

 4356 16:43:59.470731  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4357 16:43:59.470828  ==

 4358 16:43:59.473673  Dram Type= 6, Freq= 0, CH_1, rank 0

 4359 16:43:59.480675  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4360 16:43:59.480790  ==

 4361 16:43:59.483658  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4362 16:43:59.490776  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4363 16:43:59.493537  [CA 0] Center 35 (5~66) winsize 62

 4364 16:43:59.497163  [CA 1] Center 35 (5~65) winsize 61

 4365 16:43:59.500634  [CA 2] Center 33 (3~64) winsize 62

 4366 16:43:59.503619  [CA 3] Center 33 (3~64) winsize 62

 4367 16:43:59.506738  [CA 4] Center 33 (3~64) winsize 62

 4368 16:43:59.510274  [CA 5] Center 33 (3~64) winsize 62

 4369 16:43:59.510368  

 4370 16:43:59.513844  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4371 16:43:59.513935  

 4372 16:43:59.516713  [CATrainingPosCal] consider 1 rank data

 4373 16:43:59.520245  u2DelayCellTimex100 = 270/100 ps

 4374 16:43:59.523817  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4375 16:43:59.530225  CA1 delay=35 (5~65),Diff = 2 PI (19 cell)

 4376 16:43:59.533545  CA2 delay=33 (3~64),Diff = 0 PI (0 cell)

 4377 16:43:59.536890  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4378 16:43:59.540333  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 4379 16:43:59.543423  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4380 16:43:59.543524  

 4381 16:43:59.546850  CA PerBit enable=1, Macro0, CA PI delay=33

 4382 16:43:59.546947  

 4383 16:43:59.549721  [CBTSetCACLKResult] CA Dly = 33

 4384 16:43:59.549812  CS Dly: 4 (0~35)

 4385 16:43:59.553512  ==

 4386 16:43:59.556828  Dram Type= 6, Freq= 0, CH_1, rank 1

 4387 16:43:59.559612  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4388 16:43:59.559715  ==

 4389 16:43:59.563177  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4390 16:43:59.570043  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4391 16:43:59.574088  [CA 0] Center 35 (5~66) winsize 62

 4392 16:43:59.576703  [CA 1] Center 36 (6~66) winsize 61

 4393 16:43:59.580148  [CA 2] Center 34 (3~65) winsize 63

 4394 16:43:59.583572  [CA 3] Center 33 (3~64) winsize 62

 4395 16:43:59.587221  [CA 4] Center 34 (3~65) winsize 63

 4396 16:43:59.590214  [CA 5] Center 33 (3~64) winsize 62

 4397 16:43:59.590306  

 4398 16:43:59.593858  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4399 16:43:59.593947  

 4400 16:43:59.596734  [CATrainingPosCal] consider 2 rank data

 4401 16:43:59.600179  u2DelayCellTimex100 = 270/100 ps

 4402 16:43:59.603744  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4403 16:43:59.610211  CA1 delay=35 (6~65),Diff = 2 PI (19 cell)

 4404 16:43:59.613801  CA2 delay=33 (3~64),Diff = 0 PI (0 cell)

 4405 16:43:59.616756  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 4406 16:43:59.620389  CA4 delay=33 (3~64),Diff = 0 PI (0 cell)

 4407 16:43:59.623481  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4408 16:43:59.623576  

 4409 16:43:59.626985  CA PerBit enable=1, Macro0, CA PI delay=33

 4410 16:43:59.627078  

 4411 16:43:59.630413  [CBTSetCACLKResult] CA Dly = 33

 4412 16:43:59.630508  CS Dly: 4 (0~36)

 4413 16:43:59.633368  

 4414 16:43:59.636863  ----->DramcWriteLeveling(PI) begin...

 4415 16:43:59.636958  ==

 4416 16:43:59.640219  Dram Type= 6, Freq= 0, CH_1, rank 0

 4417 16:43:59.644386  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4418 16:43:59.644490  ==

 4419 16:43:59.646809  Write leveling (Byte 0): 29 => 29

 4420 16:43:59.650127  Write leveling (Byte 1): 30 => 30

 4421 16:43:59.653662  DramcWriteLeveling(PI) end<-----

 4422 16:43:59.653801  

 4423 16:43:59.653917  ==

 4424 16:43:59.656778  Dram Type= 6, Freq= 0, CH_1, rank 0

 4425 16:43:59.660052  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4426 16:43:59.660243  ==

 4427 16:43:59.663447  [Gating] SW mode calibration

 4428 16:43:59.669726  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4429 16:43:59.676546  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4430 16:43:59.679931   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4431 16:43:59.683412   0  9  4 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)

 4432 16:43:59.690269   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4433 16:43:59.693258   0  9 12 | B1->B0 | 3232 3232 | 1 0 | (1 1) (0 1)

 4434 16:43:59.697008   0  9 16 | B1->B0 | 2e2e 2525 | 0 0 | (0 0) (0 0)

 4435 16:43:59.699739   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4436 16:43:59.706732   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4437 16:43:59.709749   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4438 16:43:59.712822   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4439 16:43:59.719836   0 10  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4440 16:43:59.722808   0 10  8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4441 16:43:59.726403   0 10 12 | B1->B0 | 2626 2828 | 1 0 | (0 0) (0 0)

 4442 16:43:59.732990   0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)

 4443 16:43:59.736485   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4444 16:43:59.740170   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4445 16:43:59.746637   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4446 16:43:59.749661   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4447 16:43:59.752607   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4448 16:43:59.759392   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4449 16:43:59.762526   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4450 16:43:59.765770   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4451 16:43:59.772870   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4452 16:43:59.776106   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4453 16:43:59.779434   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4454 16:43:59.785918   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4455 16:43:59.789060   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4456 16:43:59.792485   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4457 16:43:59.799012   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4458 16:43:59.802735   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4459 16:43:59.805826   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4460 16:43:59.812193   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4461 16:43:59.815823   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4462 16:43:59.818736   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4463 16:43:59.825276   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4464 16:43:59.829079   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4465 16:43:59.831909   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4466 16:43:59.835450  Total UI for P1: 0, mck2ui 16

 4467 16:43:59.839105  best dqsien dly found for B0: ( 0, 13, 10)

 4468 16:43:59.842646  Total UI for P1: 0, mck2ui 16

 4469 16:43:59.845460  best dqsien dly found for B1: ( 0, 13, 10)

 4470 16:43:59.849050  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4471 16:43:59.851930  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4472 16:43:59.852068  

 4473 16:43:59.858464  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4474 16:43:59.862200  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4475 16:43:59.865312  [Gating] SW calibration Done

 4476 16:43:59.865439  ==

 4477 16:43:59.868547  Dram Type= 6, Freq= 0, CH_1, rank 0

 4478 16:43:59.871961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4479 16:43:59.872064  ==

 4480 16:43:59.872154  RX Vref Scan: 0

 4481 16:43:59.872236  

 4482 16:43:59.875256  RX Vref 0 -> 0, step: 1

 4483 16:43:59.875374  

 4484 16:43:59.878485  RX Delay -230 -> 252, step: 16

 4485 16:43:59.881794  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4486 16:43:59.888369  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4487 16:43:59.891680  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4488 16:43:59.895289  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4489 16:43:59.898307  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4490 16:43:59.901677  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4491 16:43:59.908340  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4492 16:43:59.911418  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4493 16:43:59.915033  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4494 16:43:59.918466  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4495 16:43:59.924963  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4496 16:43:59.928541  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4497 16:43:59.931475  iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336

 4498 16:43:59.935062  iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320

 4499 16:43:59.941835  iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320

 4500 16:43:59.944659  iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320

 4501 16:43:59.944793  ==

 4502 16:43:59.948153  Dram Type= 6, Freq= 0, CH_1, rank 0

 4503 16:43:59.951744  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4504 16:43:59.951875  ==

 4505 16:43:59.951987  DQS Delay:

 4506 16:43:59.954546  DQS0 = 0, DQS1 = 0

 4507 16:43:59.954655  DQM Delay:

 4508 16:43:59.958061  DQM0 = 45, DQM1 = 36

 4509 16:43:59.958190  DQ Delay:

 4510 16:43:59.961612  DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41

 4511 16:43:59.965070  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4512 16:43:59.967855  DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33

 4513 16:43:59.971295  DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41

 4514 16:43:59.971405  

 4515 16:43:59.971483  

 4516 16:43:59.971548  ==

 4517 16:43:59.974947  Dram Type= 6, Freq= 0, CH_1, rank 0

 4518 16:43:59.978210  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4519 16:43:59.981566  ==

 4520 16:43:59.981694  

 4521 16:43:59.981791  

 4522 16:43:59.981882  	TX Vref Scan disable

 4523 16:43:59.984828   == TX Byte 0 ==

 4524 16:43:59.988103  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4525 16:43:59.991485  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4526 16:43:59.994627   == TX Byte 1 ==

 4527 16:43:59.998356  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4528 16:44:00.001598  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4529 16:44:00.004375  ==

 4530 16:44:00.007746  Dram Type= 6, Freq= 0, CH_1, rank 0

 4531 16:44:00.011404  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4532 16:44:00.011526  ==

 4533 16:44:00.011626  

 4534 16:44:00.011717  

 4535 16:44:00.014172  	TX Vref Scan disable

 4536 16:44:00.014251   == TX Byte 0 ==

 4537 16:44:00.021053  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4538 16:44:00.024646  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4539 16:44:00.024750   == TX Byte 1 ==

 4540 16:44:00.031067  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4541 16:44:00.034640  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4542 16:44:00.034746  

 4543 16:44:00.034817  [DATLAT]

 4544 16:44:00.037653  Freq=600, CH1 RK0

 4545 16:44:00.037744  

 4546 16:44:00.037813  DATLAT Default: 0x9

 4547 16:44:00.041234  0, 0xFFFF, sum = 0

 4548 16:44:00.041332  1, 0xFFFF, sum = 0

 4549 16:44:00.044198  2, 0xFFFF, sum = 0

 4550 16:44:00.047568  3, 0xFFFF, sum = 0

 4551 16:44:00.047667  4, 0xFFFF, sum = 0

 4552 16:44:00.051257  5, 0xFFFF, sum = 0

 4553 16:44:00.051356  6, 0xFFFF, sum = 0

 4554 16:44:00.054012  7, 0xFFFF, sum = 0

 4555 16:44:00.054107  8, 0x0, sum = 1

 4556 16:44:00.057750  9, 0x0, sum = 2

 4557 16:44:00.057868  10, 0x0, sum = 3

 4558 16:44:00.057942  11, 0x0, sum = 4

 4559 16:44:00.061195  best_step = 9

 4560 16:44:00.061289  

 4561 16:44:00.061357  ==

 4562 16:44:00.064263  Dram Type= 6, Freq= 0, CH_1, rank 0

 4563 16:44:00.067698  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4564 16:44:00.067831  ==

 4565 16:44:00.071094  RX Vref Scan: 1

 4566 16:44:00.071192  

 4567 16:44:00.071262  RX Vref 0 -> 0, step: 1

 4568 16:44:00.071327  

 4569 16:44:00.074373  RX Delay -179 -> 252, step: 8

 4570 16:44:00.074469  

 4571 16:44:00.077827  Set Vref, RX VrefLevel [Byte0]: 59

 4572 16:44:00.080751                           [Byte1]: 53

 4573 16:44:00.085136  

 4574 16:44:00.085242  Final RX Vref Byte 0 = 59 to rank0

 4575 16:44:00.088557  Final RX Vref Byte 1 = 53 to rank0

 4576 16:44:00.091498  Final RX Vref Byte 0 = 59 to rank1

 4577 16:44:00.094796  Final RX Vref Byte 1 = 53 to rank1==

 4578 16:44:00.098171  Dram Type= 6, Freq= 0, CH_1, rank 0

 4579 16:44:00.105258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4580 16:44:00.105401  ==

 4581 16:44:00.105482  DQS Delay:

 4582 16:44:00.105548  DQS0 = 0, DQS1 = 0

 4583 16:44:00.108371  DQM Delay:

 4584 16:44:00.108453  DQM0 = 40, DQM1 = 34

 4585 16:44:00.111582  DQ Delay:

 4586 16:44:00.114995  DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40

 4587 16:44:00.117931  DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36

 4588 16:44:00.121355  DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28

 4589 16:44:00.124948  DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40

 4590 16:44:00.125061  

 4591 16:44:00.125134  

 4592 16:44:00.131461  [DQSOSCAuto] RK0, (LSB)MR18= 0x4108, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps

 4593 16:44:00.134416  CH1 RK0: MR19=808, MR18=4108

 4594 16:44:00.140951  CH1_RK0: MR19=0x808, MR18=0x4108, DQSOSC=397, MR23=63, INC=166, DEC=110

 4595 16:44:00.141090  

 4596 16:44:00.144475  ----->DramcWriteLeveling(PI) begin...

 4597 16:44:00.144578  ==

 4598 16:44:00.147912  Dram Type= 6, Freq= 0, CH_1, rank 1

 4599 16:44:00.151429  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4600 16:44:00.151539  ==

 4601 16:44:00.154211  Write leveling (Byte 0): 28 => 28

 4602 16:44:00.157871  Write leveling (Byte 1): 31 => 31

 4603 16:44:00.161460  DramcWriteLeveling(PI) end<-----

 4604 16:44:00.161584  

 4605 16:44:00.161654  ==

 4606 16:44:00.165218  Dram Type= 6, Freq= 0, CH_1, rank 1

 4607 16:44:00.167747  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4608 16:44:00.171129  ==

 4609 16:44:00.171236  [Gating] SW mode calibration

 4610 16:44:00.180988  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4611 16:44:00.183826  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4612 16:44:00.187292   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4613 16:44:00.194220   0  9  4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 4614 16:44:00.197569   0  9  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 4615 16:44:00.200395   0  9 12 | B1->B0 | 3232 2f2f | 0 0 | (1 0) (1 1)

 4616 16:44:00.207137   0  9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4617 16:44:00.210533   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4618 16:44:00.214017   0  9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4619 16:44:00.220869   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4620 16:44:00.223826   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4621 16:44:00.227269   0 10  4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 4622 16:44:00.233784   0 10  8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 4623 16:44:00.237522   0 10 12 | B1->B0 | 2f2f 3a3a | 1 0 | (0 0) (0 0)

 4624 16:44:00.240319   0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4625 16:44:00.246927   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4626 16:44:00.250435   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4627 16:44:00.254027   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4628 16:44:00.260408   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4629 16:44:00.263906   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4630 16:44:00.267087   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4631 16:44:00.273189   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4632 16:44:00.276616   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4633 16:44:00.280231   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4634 16:44:00.286480   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4635 16:44:00.289953   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4636 16:44:00.293337   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4637 16:44:00.299712   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4638 16:44:00.303076   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4639 16:44:00.306461   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4640 16:44:00.309855   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4641 16:44:00.316393   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4642 16:44:00.319884   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4643 16:44:00.323328   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4644 16:44:00.329801   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4645 16:44:00.333342   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4646 16:44:00.336418   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4647 16:44:00.343092   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4648 16:44:00.346287  Total UI for P1: 0, mck2ui 16

 4649 16:44:00.349894  best dqsien dly found for B0: ( 0, 13,  8)

 4650 16:44:00.353548   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4651 16:44:00.356346   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4652 16:44:00.359773  Total UI for P1: 0, mck2ui 16

 4653 16:44:00.363367  best dqsien dly found for B1: ( 0, 13, 16)

 4654 16:44:00.366347  best DQS0 dly(MCK, UI, PI) = (0, 13, 8)

 4655 16:44:00.369924  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4656 16:44:00.369998  

 4657 16:44:00.376459  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)

 4658 16:44:00.379898  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4659 16:44:00.382916  [Gating] SW calibration Done

 4660 16:44:00.382998  ==

 4661 16:44:00.386432  Dram Type= 6, Freq= 0, CH_1, rank 1

 4662 16:44:00.389855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4663 16:44:00.389939  ==

 4664 16:44:00.390016  RX Vref Scan: 0

 4665 16:44:00.390079  

 4666 16:44:00.392810  RX Vref 0 -> 0, step: 1

 4667 16:44:00.392881  

 4668 16:44:00.396164  RX Delay -230 -> 252, step: 16

 4669 16:44:00.399846  iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320

 4670 16:44:00.406066  iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336

 4671 16:44:00.409860  iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320

 4672 16:44:00.412942  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4673 16:44:00.416019  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4674 16:44:00.419475  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4675 16:44:00.425934  iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336

 4676 16:44:00.429540  iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336

 4677 16:44:00.432487  iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320

 4678 16:44:00.435887  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4679 16:44:00.442397  iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336

 4680 16:44:00.446001  iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336

 4681 16:44:00.449023  iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320

 4682 16:44:00.452532  iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336

 4683 16:44:00.458943  iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336

 4684 16:44:00.462529  iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336

 4685 16:44:00.462615  ==

 4686 16:44:00.465437  Dram Type= 6, Freq= 0, CH_1, rank 1

 4687 16:44:00.468825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4688 16:44:00.468908  ==

 4689 16:44:00.472484  DQS Delay:

 4690 16:44:00.472569  DQS0 = 0, DQS1 = 0

 4691 16:44:00.472634  DQM Delay:

 4692 16:44:00.475745  DQM0 = 40, DQM1 = 38

 4693 16:44:00.475828  DQ Delay:

 4694 16:44:00.478726  DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41

 4695 16:44:00.482333  DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =33

 4696 16:44:00.485974  DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33

 4697 16:44:00.488777  DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49

 4698 16:44:00.488920  

 4699 16:44:00.488991  

 4700 16:44:00.489052  ==

 4701 16:44:00.492098  Dram Type= 6, Freq= 0, CH_1, rank 1

 4702 16:44:00.495536  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4703 16:44:00.498924  ==

 4704 16:44:00.499007  

 4705 16:44:00.499072  

 4706 16:44:00.499142  	TX Vref Scan disable

 4707 16:44:00.502050   == TX Byte 0 ==

 4708 16:44:00.505397  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4709 16:44:00.512163  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4710 16:44:00.512248   == TX Byte 1 ==

 4711 16:44:00.515571  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4712 16:44:00.522339  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4713 16:44:00.522424  ==

 4714 16:44:00.525242  Dram Type= 6, Freq= 0, CH_1, rank 1

 4715 16:44:00.528594  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4716 16:44:00.528679  ==

 4717 16:44:00.528745  

 4718 16:44:00.528805  

 4719 16:44:00.532063  	TX Vref Scan disable

 4720 16:44:00.535400   == TX Byte 0 ==

 4721 16:44:00.538914  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4722 16:44:00.542000  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4723 16:44:00.545556   == TX Byte 1 ==

 4724 16:44:00.548604  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4725 16:44:00.552109  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4726 16:44:00.552192  

 4727 16:44:00.552257  [DATLAT]

 4728 16:44:00.555100  Freq=600, CH1 RK1

 4729 16:44:00.555182  

 4730 16:44:00.555263  DATLAT Default: 0x9

 4731 16:44:00.558604  0, 0xFFFF, sum = 0

 4732 16:44:00.561900  1, 0xFFFF, sum = 0

 4733 16:44:00.561985  2, 0xFFFF, sum = 0

 4734 16:44:00.565132  3, 0xFFFF, sum = 0

 4735 16:44:00.565216  4, 0xFFFF, sum = 0

 4736 16:44:00.568531  5, 0xFFFF, sum = 0

 4737 16:44:00.568616  6, 0xFFFF, sum = 0

 4738 16:44:00.571873  7, 0xFFFF, sum = 0

 4739 16:44:00.571966  8, 0x0, sum = 1

 4740 16:44:00.574997  9, 0x0, sum = 2

 4741 16:44:00.575082  10, 0x0, sum = 3

 4742 16:44:00.575149  11, 0x0, sum = 4

 4743 16:44:00.578415  best_step = 9

 4744 16:44:00.578511  

 4745 16:44:00.578577  ==

 4746 16:44:00.581881  Dram Type= 6, Freq= 0, CH_1, rank 1

 4747 16:44:00.584855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4748 16:44:00.584939  ==

 4749 16:44:00.588364  RX Vref Scan: 0

 4750 16:44:00.588448  

 4751 16:44:00.588514  RX Vref 0 -> 0, step: 1

 4752 16:44:00.591945  

 4753 16:44:00.592035  RX Delay -179 -> 252, step: 8

 4754 16:44:00.599351  iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304

 4755 16:44:00.602369  iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312

 4756 16:44:00.605891  iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304

 4757 16:44:00.609235  iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312

 4758 16:44:00.615442  iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312

 4759 16:44:00.618907  iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304

 4760 16:44:00.622298  iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304

 4761 16:44:00.625713  iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304

 4762 16:44:00.629131  iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320

 4763 16:44:00.635758  iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320

 4764 16:44:00.638801  iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320

 4765 16:44:00.642244  iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312

 4766 16:44:00.645629  iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312

 4767 16:44:00.652275  iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312

 4768 16:44:00.655421  iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304

 4769 16:44:00.658744  iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312

 4770 16:44:00.658855  ==

 4771 16:44:00.662341  Dram Type= 6, Freq= 0, CH_1, rank 1

 4772 16:44:00.668854  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4773 16:44:00.668966  ==

 4774 16:44:00.669071  DQS Delay:

 4775 16:44:00.669173  DQS0 = 0, DQS1 = 0

 4776 16:44:00.671877  DQM Delay:

 4777 16:44:00.672000  DQM0 = 40, DQM1 = 33

 4778 16:44:00.675598  DQ Delay:

 4779 16:44:00.678768  DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =40

 4780 16:44:00.678872  DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36

 4781 16:44:00.681758  DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24

 4782 16:44:00.688285  DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40

 4783 16:44:00.688372  

 4784 16:44:00.688442  

 4785 16:44:00.695214  [DQSOSCAuto] RK1, (LSB)MR18= 0x3644, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps

 4786 16:44:00.698670  CH1 RK1: MR19=808, MR18=3644

 4787 16:44:00.704796  CH1_RK1: MR19=0x808, MR18=0x3644, DQSOSC=396, MR23=63, INC=167, DEC=111

 4788 16:44:00.708359  [RxdqsGatingPostProcess] freq 600

 4789 16:44:00.711751  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4790 16:44:00.715109  Pre-setting of DQS Precalculation

 4791 16:44:00.721341  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4792 16:44:00.728118  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4793 16:44:00.734916  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4794 16:44:00.735036  

 4795 16:44:00.735133  

 4796 16:44:00.738068  [Calibration Summary] 1200 Mbps

 4797 16:44:00.738155  CH 0, Rank 0

 4798 16:44:00.741480  SW Impedance     : PASS

 4799 16:44:00.745102  DUTY Scan        : NO K

 4800 16:44:00.745188  ZQ Calibration   : PASS

 4801 16:44:00.747946  Jitter Meter     : NO K

 4802 16:44:00.751537  CBT Training     : PASS

 4803 16:44:00.751621  Write leveling   : PASS

 4804 16:44:00.754545  RX DQS gating    : PASS

 4805 16:44:00.758183  RX DQ/DQS(RDDQC) : PASS

 4806 16:44:00.758267  TX DQ/DQS        : PASS

 4807 16:44:00.761181  RX DATLAT        : PASS

 4808 16:44:00.764637  RX DQ/DQS(Engine): PASS

 4809 16:44:00.764723  TX OE            : NO K

 4810 16:44:00.764790  All Pass.

 4811 16:44:00.767723  

 4812 16:44:00.767806  CH 0, Rank 1

 4813 16:44:00.771538  SW Impedance     : PASS

 4814 16:44:00.771622  DUTY Scan        : NO K

 4815 16:44:00.774470  ZQ Calibration   : PASS

 4816 16:44:00.774555  Jitter Meter     : NO K

 4817 16:44:00.777884  CBT Training     : PASS

 4818 16:44:00.781424  Write leveling   : PASS

 4819 16:44:00.781520  RX DQS gating    : PASS

 4820 16:44:00.784333  RX DQ/DQS(RDDQC) : PASS

 4821 16:44:00.787896  TX DQ/DQS        : PASS

 4822 16:44:00.788000  RX DATLAT        : PASS

 4823 16:44:00.791326  RX DQ/DQS(Engine): PASS

 4824 16:44:00.794457  TX OE            : NO K

 4825 16:44:00.794540  All Pass.

 4826 16:44:00.794605  

 4827 16:44:00.794681  CH 1, Rank 0

 4828 16:44:00.798116  SW Impedance     : PASS

 4829 16:44:00.800976  DUTY Scan        : NO K

 4830 16:44:00.801058  ZQ Calibration   : PASS

 4831 16:44:00.804445  Jitter Meter     : NO K

 4832 16:44:00.807624  CBT Training     : PASS

 4833 16:44:00.807736  Write leveling   : PASS

 4834 16:44:00.811080  RX DQS gating    : PASS

 4835 16:44:00.814426  RX DQ/DQS(RDDQC) : PASS

 4836 16:44:00.814524  TX DQ/DQS        : PASS

 4837 16:44:00.817777  RX DATLAT        : PASS

 4838 16:44:00.821322  RX DQ/DQS(Engine): PASS

 4839 16:44:00.821405  TX OE            : NO K

 4840 16:44:00.821501  All Pass.

 4841 16:44:00.821562  

 4842 16:44:00.824265  CH 1, Rank 1

 4843 16:44:00.827912  SW Impedance     : PASS

 4844 16:44:00.828016  DUTY Scan        : NO K

 4845 16:44:00.830569  ZQ Calibration   : PASS

 4846 16:44:00.834434  Jitter Meter     : NO K

 4847 16:44:00.834516  CBT Training     : PASS

 4848 16:44:00.837397  Write leveling   : PASS

 4849 16:44:00.837480  RX DQS gating    : PASS

 4850 16:44:00.840831  RX DQ/DQS(RDDQC) : PASS

 4851 16:44:00.844213  TX DQ/DQS        : PASS

 4852 16:44:00.844296  RX DATLAT        : PASS

 4853 16:44:00.847331  RX DQ/DQS(Engine): PASS

 4854 16:44:00.850866  TX OE            : NO K

 4855 16:44:00.850949  All Pass.

 4856 16:44:00.851014  

 4857 16:44:00.853770  DramC Write-DBI off

 4858 16:44:00.853853  	PER_BANK_REFRESH: Hybrid Mode

 4859 16:44:00.857177  TX_TRACKING: ON

 4860 16:44:00.864564  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4861 16:44:00.870577  [FAST_K] Save calibration result to emmc

 4862 16:44:00.874073  dramc_set_vcore_voltage set vcore to 662500

 4863 16:44:00.874156  Read voltage for 933, 3

 4864 16:44:00.876964  Vio18 = 0

 4865 16:44:00.877046  Vcore = 662500

 4866 16:44:00.877111  Vdram = 0

 4867 16:44:00.880502  Vddq = 0

 4868 16:44:00.880599  Vmddr = 0

 4869 16:44:00.883845  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4870 16:44:00.890392  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4871 16:44:00.894055  MEM_TYPE=3, freq_sel=17

 4872 16:44:00.896955  sv_algorithm_assistance_LP4_1600 

 4873 16:44:00.900765  ============ PULL DRAM RESETB DOWN ============

 4874 16:44:00.903507  ========== PULL DRAM RESETB DOWN end =========

 4875 16:44:00.910191  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4876 16:44:00.913834  =================================== 

 4877 16:44:00.913919  LPDDR4 DRAM CONFIGURATION

 4878 16:44:00.917150  =================================== 

 4879 16:44:00.920189  EX_ROW_EN[0]    = 0x0

 4880 16:44:00.920271  EX_ROW_EN[1]    = 0x0

 4881 16:44:00.923314  LP4Y_EN      = 0x0

 4882 16:44:00.923397  WORK_FSP     = 0x0

 4883 16:44:00.926814  WL           = 0x3

 4884 16:44:00.930340  RL           = 0x3

 4885 16:44:00.930422  BL           = 0x2

 4886 16:44:00.933510  RPST         = 0x0

 4887 16:44:00.933641  RD_PRE       = 0x0

 4888 16:44:00.936687  WR_PRE       = 0x1

 4889 16:44:00.936769  WR_PST       = 0x0

 4890 16:44:00.940101  DBI_WR       = 0x0

 4891 16:44:00.940182  DBI_RD       = 0x0

 4892 16:44:00.943511  OTF          = 0x1

 4893 16:44:00.947011  =================================== 

 4894 16:44:00.950044  =================================== 

 4895 16:44:00.950127  ANA top config

 4896 16:44:00.953457  =================================== 

 4897 16:44:00.956892  DLL_ASYNC_EN            =  0

 4898 16:44:00.959905  ALL_SLAVE_EN            =  1

 4899 16:44:00.960015  NEW_RANK_MODE           =  1

 4900 16:44:00.963467  DLL_IDLE_MODE           =  1

 4901 16:44:00.966536  LP45_APHY_COMB_EN       =  1

 4902 16:44:00.970149  TX_ODT_DIS              =  1

 4903 16:44:00.973480  NEW_8X_MODE             =  1

 4904 16:44:00.973585  =================================== 

 4905 16:44:00.976875  =================================== 

 4906 16:44:00.979890  data_rate                  = 1866

 4907 16:44:00.983293  CKR                        = 1

 4908 16:44:00.986845  DQ_P2S_RATIO               = 8

 4909 16:44:00.989819  =================================== 

 4910 16:44:00.993418  CA_P2S_RATIO               = 8

 4911 16:44:00.996530  DQ_CA_OPEN                 = 0

 4912 16:44:01.000022  DQ_SEMI_OPEN               = 0

 4913 16:44:01.000104  CA_SEMI_OPEN               = 0

 4914 16:44:01.003967  CA_FULL_RATE               = 0

 4915 16:44:01.006632  DQ_CKDIV4_EN               = 1

 4916 16:44:01.010054  CA_CKDIV4_EN               = 1

 4917 16:44:01.013353  CA_PREDIV_EN               = 0

 4918 16:44:01.013430  PH8_DLY                    = 0

 4919 16:44:01.016661  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4920 16:44:01.020050  DQ_AAMCK_DIV               = 4

 4921 16:44:01.023359  CA_AAMCK_DIV               = 4

 4922 16:44:01.026804  CA_ADMCK_DIV               = 4

 4923 16:44:01.030068  DQ_TRACK_CA_EN             = 0

 4924 16:44:01.032960  CA_PICK                    = 933

 4925 16:44:01.033045  CA_MCKIO                   = 933

 4926 16:44:01.036399  MCKIO_SEMI                 = 0

 4927 16:44:01.039871  PLL_FREQ                   = 3732

 4928 16:44:01.043163  DQ_UI_PI_RATIO             = 32

 4929 16:44:01.046660  CA_UI_PI_RATIO             = 0

 4930 16:44:01.050470  =================================== 

 4931 16:44:01.052981  =================================== 

 4932 16:44:01.056453  memory_type:LPDDR4         

 4933 16:44:01.056537  GP_NUM     : 10       

 4934 16:44:01.059970  SRAM_EN    : 1       

 4935 16:44:01.060065  MD32_EN    : 0       

 4936 16:44:01.063697  =================================== 

 4937 16:44:01.066546  [ANA_INIT] >>>>>>>>>>>>>> 

 4938 16:44:01.070013  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4939 16:44:01.073008  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4940 16:44:01.076520  =================================== 

 4941 16:44:01.079493  data_rate = 1866,PCW = 0X8f00

 4942 16:44:01.083003  =================================== 

 4943 16:44:01.086599  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4944 16:44:01.089496  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4945 16:44:01.096069  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4946 16:44:01.099598  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4947 16:44:01.106148  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4948 16:44:01.109759  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4949 16:44:01.109844  [ANA_INIT] flow start 

 4950 16:44:01.113229  [ANA_INIT] PLL >>>>>>>> 

 4951 16:44:01.116209  [ANA_INIT] PLL <<<<<<<< 

 4952 16:44:01.116297  [ANA_INIT] MIDPI >>>>>>>> 

 4953 16:44:01.119151  [ANA_INIT] MIDPI <<<<<<<< 

 4954 16:44:01.122450  [ANA_INIT] DLL >>>>>>>> 

 4955 16:44:01.122528  [ANA_INIT] flow end 

 4956 16:44:01.129443  ============ LP4 DIFF to SE enter ============

 4957 16:44:01.132456  ============ LP4 DIFF to SE exit  ============

 4958 16:44:01.132551  [ANA_INIT] <<<<<<<<<<<<< 

 4959 16:44:01.136245  [Flow] Enable top DCM control >>>>> 

 4960 16:44:01.139536  [Flow] Enable top DCM control <<<<< 

 4961 16:44:01.142598  Enable DLL master slave shuffle 

 4962 16:44:01.149215  ============================================================== 

 4963 16:44:01.153093  Gating Mode config

 4964 16:44:01.155817  ============================================================== 

 4965 16:44:01.159335  Config description: 

 4966 16:44:01.169246  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4967 16:44:01.176345  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4968 16:44:01.179207  SELPH_MODE            0: By rank         1: By Phase 

 4969 16:44:01.185694  ============================================================== 

 4970 16:44:01.189231  GAT_TRACK_EN                 =  1

 4971 16:44:01.192723  RX_GATING_MODE               =  2

 4972 16:44:01.192808  RX_GATING_TRACK_MODE         =  2

 4973 16:44:01.195722  SELPH_MODE                   =  1

 4974 16:44:01.199308  PICG_EARLY_EN                =  1

 4975 16:44:01.202271  VALID_LAT_VALUE              =  1

 4976 16:44:01.208874  ============================================================== 

 4977 16:44:01.212393  Enter into Gating configuration >>>> 

 4978 16:44:01.216436  Exit from Gating configuration <<<< 

 4979 16:44:01.219370  Enter into  DVFS_PRE_config >>>>> 

 4980 16:44:01.229313  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4981 16:44:01.232138  Exit from  DVFS_PRE_config <<<<< 

 4982 16:44:01.235782  Enter into PICG configuration >>>> 

 4983 16:44:01.239342  Exit from PICG configuration <<<< 

 4984 16:44:01.242233  [RX_INPUT] configuration >>>>> 

 4985 16:44:01.245533  [RX_INPUT] configuration <<<<< 

 4986 16:44:01.249343  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4987 16:44:01.255785  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4988 16:44:01.262048  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4989 16:44:01.268949  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4990 16:44:01.272261  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4991 16:44:01.278810  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4992 16:44:01.282331  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4993 16:44:01.288816  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4994 16:44:01.292353  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4995 16:44:01.295799  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4996 16:44:01.298818  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4997 16:44:01.305317  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4998 16:44:01.308840  =================================== 

 4999 16:44:01.308933  LPDDR4 DRAM CONFIGURATION

 5000 16:44:01.312378  =================================== 

 5001 16:44:01.315301  EX_ROW_EN[0]    = 0x0

 5002 16:44:01.318907  EX_ROW_EN[1]    = 0x0

 5003 16:44:01.319007  LP4Y_EN      = 0x0

 5004 16:44:01.321860  WORK_FSP     = 0x0

 5005 16:44:01.321957  WL           = 0x3

 5006 16:44:01.325481  RL           = 0x3

 5007 16:44:01.325567  BL           = 0x2

 5008 16:44:01.329025  RPST         = 0x0

 5009 16:44:01.329134  RD_PRE       = 0x0

 5010 16:44:01.332187  WR_PRE       = 0x1

 5011 16:44:01.332285  WR_PST       = 0x0

 5012 16:44:01.335615  DBI_WR       = 0x0

 5013 16:44:01.335705  DBI_RD       = 0x0

 5014 16:44:01.338748  OTF          = 0x1

 5015 16:44:01.342173  =================================== 

 5016 16:44:01.345487  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5017 16:44:01.348575  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5018 16:44:01.355267  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5019 16:44:01.359078  =================================== 

 5020 16:44:01.359188  LPDDR4 DRAM CONFIGURATION

 5021 16:44:01.361821  =================================== 

 5022 16:44:01.365276  EX_ROW_EN[0]    = 0x10

 5023 16:44:01.368988  EX_ROW_EN[1]    = 0x0

 5024 16:44:01.369073  LP4Y_EN      = 0x0

 5025 16:44:01.372743  WORK_FSP     = 0x0

 5026 16:44:01.372827  WL           = 0x3

 5027 16:44:01.375622  RL           = 0x3

 5028 16:44:01.375708  BL           = 0x2

 5029 16:44:01.378971  RPST         = 0x0

 5030 16:44:01.379055  RD_PRE       = 0x0

 5031 16:44:01.381924  WR_PRE       = 0x1

 5032 16:44:01.382013  WR_PST       = 0x0

 5033 16:44:01.385400  DBI_WR       = 0x0

 5034 16:44:01.385485  DBI_RD       = 0x0

 5035 16:44:01.388407  OTF          = 0x1

 5036 16:44:01.392098  =================================== 

 5037 16:44:01.398458  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5038 16:44:01.401922  nWR fixed to 30

 5039 16:44:01.402008  [ModeRegInit_LP4] CH0 RK0

 5040 16:44:01.405482  [ModeRegInit_LP4] CH0 RK1

 5041 16:44:01.408390  [ModeRegInit_LP4] CH1 RK0

 5042 16:44:01.412070  [ModeRegInit_LP4] CH1 RK1

 5043 16:44:01.412155  match AC timing 9

 5044 16:44:01.414944  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5045 16:44:01.422071  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5046 16:44:01.424909  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5047 16:44:01.431594  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5048 16:44:01.435105  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5049 16:44:01.435191  ==

 5050 16:44:01.438495  Dram Type= 6, Freq= 0, CH_0, rank 0

 5051 16:44:01.441867  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5052 16:44:01.441967  ==

 5053 16:44:01.448184  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5054 16:44:01.455034  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5055 16:44:01.458264  [CA 0] Center 38 (8~69) winsize 62

 5056 16:44:01.461572  [CA 1] Center 38 (7~69) winsize 63

 5057 16:44:01.465332  [CA 2] Center 35 (5~65) winsize 61

 5058 16:44:01.468086  [CA 3] Center 34 (4~65) winsize 62

 5059 16:44:01.471304  [CA 4] Center 34 (4~65) winsize 62

 5060 16:44:01.474655  [CA 5] Center 34 (4~64) winsize 61

 5061 16:44:01.474746  

 5062 16:44:01.478095  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5063 16:44:01.478192  

 5064 16:44:01.481575  [CATrainingPosCal] consider 1 rank data

 5065 16:44:01.485015  u2DelayCellTimex100 = 270/100 ps

 5066 16:44:01.488500  CA0 delay=38 (8~69),Diff = 4 PI (24 cell)

 5067 16:44:01.491281  CA1 delay=38 (7~69),Diff = 4 PI (24 cell)

 5068 16:44:01.494870  CA2 delay=35 (5~65),Diff = 1 PI (6 cell)

 5069 16:44:01.498351  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5070 16:44:01.501757  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 5071 16:44:01.504825  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5072 16:44:01.504906  

 5073 16:44:01.508157  CA PerBit enable=1, Macro0, CA PI delay=34

 5074 16:44:01.508259  

 5075 16:44:01.511689  [CBTSetCACLKResult] CA Dly = 34

 5076 16:44:01.514686  CS Dly: 6 (0~37)

 5077 16:44:01.514770  ==

 5078 16:44:01.517762  Dram Type= 6, Freq= 0, CH_0, rank 1

 5079 16:44:01.521152  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5080 16:44:01.521228  ==

 5081 16:44:01.527741  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5082 16:44:01.535111  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5083 16:44:01.537871  [CA 0] Center 38 (7~69) winsize 63

 5084 16:44:01.541258  [CA 1] Center 38 (7~69) winsize 63

 5085 16:44:01.544549  [CA 2] Center 35 (5~66) winsize 62

 5086 16:44:01.548041  [CA 3] Center 35 (4~66) winsize 63

 5087 16:44:01.551282  [CA 4] Center 33 (3~64) winsize 62

 5088 16:44:01.554642  [CA 5] Center 33 (3~64) winsize 62

 5089 16:44:01.554741  

 5090 16:44:01.558079  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5091 16:44:01.558164  

 5092 16:44:01.561461  [CATrainingPosCal] consider 2 rank data

 5093 16:44:01.564923  u2DelayCellTimex100 = 270/100 ps

 5094 16:44:01.567840  CA0 delay=38 (8~69),Diff = 4 PI (24 cell)

 5095 16:44:01.571232  CA1 delay=38 (7~69),Diff = 4 PI (24 cell)

 5096 16:44:01.574503  CA2 delay=35 (5~65),Diff = 1 PI (6 cell)

 5097 16:44:01.577698  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5098 16:44:01.581140  CA4 delay=34 (4~64),Diff = 0 PI (0 cell)

 5099 16:44:01.584722  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5100 16:44:01.584846  

 5101 16:44:01.591145  CA PerBit enable=1, Macro0, CA PI delay=34

 5102 16:44:01.591236  

 5103 16:44:01.591304  [CBTSetCACLKResult] CA Dly = 34

 5104 16:44:01.594369  CS Dly: 7 (0~39)

 5105 16:44:01.594455  

 5106 16:44:01.597741  ----->DramcWriteLeveling(PI) begin...

 5107 16:44:01.597857  ==

 5108 16:44:01.600905  Dram Type= 6, Freq= 0, CH_0, rank 0

 5109 16:44:01.604138  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5110 16:44:01.604228  ==

 5111 16:44:01.607751  Write leveling (Byte 0): 32 => 32

 5112 16:44:01.611286  Write leveling (Byte 1): 28 => 28

 5113 16:44:01.614224  DramcWriteLeveling(PI) end<-----

 5114 16:44:01.614340  

 5115 16:44:01.614435  ==

 5116 16:44:01.617850  Dram Type= 6, Freq= 0, CH_0, rank 0

 5117 16:44:01.620883  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5118 16:44:01.624397  ==

 5119 16:44:01.624501  [Gating] SW mode calibration

 5120 16:44:01.634257  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5121 16:44:01.637336  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5122 16:44:01.640925   0 14  0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)

 5123 16:44:01.647529   0 14  4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)

 5124 16:44:01.650571   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5125 16:44:01.654184   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5126 16:44:01.660435   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5127 16:44:01.664165   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5128 16:44:01.667417   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5129 16:44:01.673855   0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 5130 16:44:01.677337   0 15  0 | B1->B0 | 3030 2929 | 1 1 | (1 1) (1 0)

 5131 16:44:01.680667   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5132 16:44:01.687396   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5133 16:44:01.690663   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5134 16:44:01.693726   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5135 16:44:01.700721   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5136 16:44:01.703874   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5137 16:44:01.707148   0 15 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 5138 16:44:01.713524   1  0  0 | B1->B0 | 3636 3f3f | 0 0 | (1 1) (0 0)

 5139 16:44:01.717116   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5140 16:44:01.720821   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5141 16:44:01.727298   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5142 16:44:01.730262   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5143 16:44:01.733768   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5144 16:44:01.737366   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5145 16:44:01.743785   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5146 16:44:01.747186   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5147 16:44:01.750961   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5148 16:44:01.757433   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5149 16:44:01.760379   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5150 16:44:01.763897   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5151 16:44:01.770212   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5152 16:44:01.773679   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5153 16:44:01.776784   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5154 16:44:01.783462   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5155 16:44:01.786792   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5156 16:44:01.790177   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5157 16:44:01.797009   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5158 16:44:01.800266   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5159 16:44:01.803479   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5160 16:44:01.810055   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5161 16:44:01.813360   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5162 16:44:01.817201   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5163 16:44:01.823629   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5164 16:44:01.823759  Total UI for P1: 0, mck2ui 16

 5165 16:44:01.830062  best dqsien dly found for B0: ( 1,  2, 30)

 5166 16:44:01.830162  Total UI for P1: 0, mck2ui 16

 5167 16:44:01.836576  best dqsien dly found for B1: ( 1,  3,  0)

 5168 16:44:01.840180  best DQS0 dly(MCK, UI, PI) = (1, 2, 30)

 5169 16:44:01.843259  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5170 16:44:01.843358  

 5171 16:44:01.846772  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5172 16:44:01.849700  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5173 16:44:01.853366  [Gating] SW calibration Done

 5174 16:44:01.853487  ==

 5175 16:44:01.856758  Dram Type= 6, Freq= 0, CH_0, rank 0

 5176 16:44:01.860134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5177 16:44:01.860256  ==

 5178 16:44:01.863596  RX Vref Scan: 0

 5179 16:44:01.863735  

 5180 16:44:01.863844  RX Vref 0 -> 0, step: 1

 5181 16:44:01.863972  

 5182 16:44:01.866623  RX Delay -80 -> 252, step: 8

 5183 16:44:01.870034  iDelay=208, Bit 0, Center 95 (0 ~ 191) 192

 5184 16:44:01.876385  iDelay=208, Bit 1, Center 103 (8 ~ 199) 192

 5185 16:44:01.879817  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5186 16:44:01.883392  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5187 16:44:01.886436  iDelay=208, Bit 4, Center 99 (0 ~ 199) 200

 5188 16:44:01.889797  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5189 16:44:01.893342  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5190 16:44:01.896789  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5191 16:44:01.903025  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5192 16:44:01.906371  iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184

 5193 16:44:01.909706  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5194 16:44:01.913066  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5195 16:44:01.916369  iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200

 5196 16:44:01.922718  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5197 16:44:01.926315  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5198 16:44:01.929717  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5199 16:44:01.929838  ==

 5200 16:44:01.933152  Dram Type= 6, Freq= 0, CH_0, rank 0

 5201 16:44:01.936136  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5202 16:44:01.936257  ==

 5203 16:44:01.939716  DQS Delay:

 5204 16:44:01.939834  DQS0 = 0, DQS1 = 0

 5205 16:44:01.942735  DQM Delay:

 5206 16:44:01.942853  DQM0 = 97, DQM1 = 87

 5207 16:44:01.942966  DQ Delay:

 5208 16:44:01.946241  DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91

 5209 16:44:01.949140  DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103

 5210 16:44:01.953106  DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79

 5211 16:44:01.956167  DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95

 5212 16:44:01.956286  

 5213 16:44:01.959672  

 5214 16:44:01.959788  ==

 5215 16:44:01.962386  Dram Type= 6, Freq= 0, CH_0, rank 0

 5216 16:44:01.965780  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5217 16:44:01.965902  ==

 5218 16:44:01.966014  

 5219 16:44:01.966117  

 5220 16:44:01.969285  	TX Vref Scan disable

 5221 16:44:01.969406   == TX Byte 0 ==

 5222 16:44:01.975605  Update DQ  dly =717 (2 ,6, 13)  DQ  OEN =(2 ,3)

 5223 16:44:01.978944  Update DQM dly =717 (2 ,6, 13)  DQM OEN =(2 ,3)

 5224 16:44:01.979066   == TX Byte 1 ==

 5225 16:44:01.986114  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5226 16:44:01.989115  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5227 16:44:01.989238  ==

 5228 16:44:01.992522  Dram Type= 6, Freq= 0, CH_0, rank 0

 5229 16:44:01.995838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5230 16:44:01.995966  ==

 5231 16:44:01.996079  

 5232 16:44:01.996188  

 5233 16:44:01.998979  	TX Vref Scan disable

 5234 16:44:02.002560   == TX Byte 0 ==

 5235 16:44:02.005612  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5236 16:44:02.008936  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5237 16:44:02.012239   == TX Byte 1 ==

 5238 16:44:02.015487  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5239 16:44:02.019464  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5240 16:44:02.019588  

 5241 16:44:02.022286  [DATLAT]

 5242 16:44:02.022409  Freq=933, CH0 RK0

 5243 16:44:02.022524  

 5244 16:44:02.025452  DATLAT Default: 0xd

 5245 16:44:02.025575  0, 0xFFFF, sum = 0

 5246 16:44:02.028725  1, 0xFFFF, sum = 0

 5247 16:44:02.028850  2, 0xFFFF, sum = 0

 5248 16:44:02.032588  3, 0xFFFF, sum = 0

 5249 16:44:02.032713  4, 0xFFFF, sum = 0

 5250 16:44:02.035534  5, 0xFFFF, sum = 0

 5251 16:44:02.035657  6, 0xFFFF, sum = 0

 5252 16:44:02.039116  7, 0xFFFF, sum = 0

 5253 16:44:02.039241  8, 0xFFFF, sum = 0

 5254 16:44:02.042150  9, 0xFFFF, sum = 0

 5255 16:44:02.042275  10, 0x0, sum = 1

 5256 16:44:02.045599  11, 0x0, sum = 2

 5257 16:44:02.045721  12, 0x0, sum = 3

 5258 16:44:02.048936  13, 0x0, sum = 4

 5259 16:44:02.049058  best_step = 11

 5260 16:44:02.049170  

 5261 16:44:02.049277  ==

 5262 16:44:02.052105  Dram Type= 6, Freq= 0, CH_0, rank 0

 5263 16:44:02.059104  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5264 16:44:02.059229  ==

 5265 16:44:02.059345  RX Vref Scan: 1

 5266 16:44:02.059455  

 5267 16:44:02.062188  RX Vref 0 -> 0, step: 1

 5268 16:44:02.062311  

 5269 16:44:02.066167  RX Delay -61 -> 252, step: 4

 5270 16:44:02.066290  

 5271 16:44:02.068874  Set Vref, RX VrefLevel [Byte0]: 55

 5272 16:44:02.072389                           [Byte1]: 51

 5273 16:44:02.072513  

 5274 16:44:02.075833  Final RX Vref Byte 0 = 55 to rank0

 5275 16:44:02.078885  Final RX Vref Byte 1 = 51 to rank0

 5276 16:44:02.082337  Final RX Vref Byte 0 = 55 to rank1

 5277 16:44:02.085863  Final RX Vref Byte 1 = 51 to rank1==

 5278 16:44:02.088858  Dram Type= 6, Freq= 0, CH_0, rank 0

 5279 16:44:02.092412  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5280 16:44:02.092492  ==

 5281 16:44:02.095763  DQS Delay:

 5282 16:44:02.095876  DQS0 = 0, DQS1 = 0

 5283 16:44:02.095979  DQM Delay:

 5284 16:44:02.099016  DQM0 = 96, DQM1 = 87

 5285 16:44:02.099090  DQ Delay:

 5286 16:44:02.102526  DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =92

 5287 16:44:02.105674  DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =102

 5288 16:44:02.109000  DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80

 5289 16:44:02.111944  DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =98

 5290 16:44:02.112059  

 5291 16:44:02.112164  

 5292 16:44:02.121921  [DQSOSCAuto] RK0, (LSB)MR18= 0x12fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 416 ps

 5293 16:44:02.125344  CH0 RK0: MR19=504, MR18=12FD

 5294 16:44:02.128836  CH0_RK0: MR19=0x504, MR18=0x12FD, DQSOSC=416, MR23=63, INC=62, DEC=41

 5295 16:44:02.128944  

 5296 16:44:02.132277  ----->DramcWriteLeveling(PI) begin...

 5297 16:44:02.135520  ==

 5298 16:44:02.135604  Dram Type= 6, Freq= 0, CH_0, rank 1

 5299 16:44:02.142166  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5300 16:44:02.142250  ==

 5301 16:44:02.145123  Write leveling (Byte 0): 31 => 31

 5302 16:44:02.148453  Write leveling (Byte 1): 28 => 28

 5303 16:44:02.151931  DramcWriteLeveling(PI) end<-----

 5304 16:44:02.152020  

 5305 16:44:02.152085  ==

 5306 16:44:02.155452  Dram Type= 6, Freq= 0, CH_0, rank 1

 5307 16:44:02.158868  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5308 16:44:02.158955  ==

 5309 16:44:02.161873  [Gating] SW mode calibration

 5310 16:44:02.168947  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5311 16:44:02.172229  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5312 16:44:02.178655   0 14  0 | B1->B0 | 2727 3434 | 1 1 | (1 1) (1 1)

 5313 16:44:02.182137   0 14  4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5314 16:44:02.185144   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5315 16:44:02.192173   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5316 16:44:02.195112   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5317 16:44:02.198616   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5318 16:44:02.204878   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 5319 16:44:02.208486   0 14 28 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)

 5320 16:44:02.212098   0 15  0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)

 5321 16:44:02.218125   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5322 16:44:02.221460   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5323 16:44:02.225233   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5324 16:44:02.231446   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5325 16:44:02.234870   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5326 16:44:02.238356   0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 5327 16:44:02.245311   0 15 28 | B1->B0 | 2929 3a3a | 0 1 | (0 0) (0 0)

 5328 16:44:02.248289   1  0  0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 5329 16:44:02.251900   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5330 16:44:02.258219   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5331 16:44:02.261907   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5332 16:44:02.264742   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5333 16:44:02.271844   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5334 16:44:02.275206   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5335 16:44:02.278081   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5336 16:44:02.284928   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5337 16:44:02.288647   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5338 16:44:02.291820   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5339 16:44:02.298407   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5340 16:44:02.301433   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5341 16:44:02.305020   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5342 16:44:02.311343   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5343 16:44:02.314797   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5344 16:44:02.318184   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5345 16:44:02.321463   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5346 16:44:02.327755   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5347 16:44:02.331221   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5348 16:44:02.334637   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5349 16:44:02.341557   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5350 16:44:02.344428   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5351 16:44:02.347815   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5352 16:44:02.354372   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 5353 16:44:02.357886  Total UI for P1: 0, mck2ui 16

 5354 16:44:02.361459  best dqsien dly found for B0: ( 1,  2, 28)

 5355 16:44:02.364915   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5356 16:44:02.367920  Total UI for P1: 0, mck2ui 16

 5357 16:44:02.371193  best dqsien dly found for B1: ( 1,  3,  2)

 5358 16:44:02.374877  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5359 16:44:02.377868  best DQS1 dly(MCK, UI, PI) = (1, 3, 2)

 5360 16:44:02.377951  

 5361 16:44:02.381249  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5362 16:44:02.384616  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)

 5363 16:44:02.387799  [Gating] SW calibration Done

 5364 16:44:02.387882  ==

 5365 16:44:02.391150  Dram Type= 6, Freq= 0, CH_0, rank 1

 5366 16:44:02.394533  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5367 16:44:02.398052  ==

 5368 16:44:02.398136  RX Vref Scan: 0

 5369 16:44:02.398203  

 5370 16:44:02.400991  RX Vref 0 -> 0, step: 1

 5371 16:44:02.401075  

 5372 16:44:02.404490  RX Delay -80 -> 252, step: 8

 5373 16:44:02.407411  iDelay=208, Bit 0, Center 99 (0 ~ 199) 200

 5374 16:44:02.410864  iDelay=208, Bit 1, Center 99 (0 ~ 199) 200

 5375 16:44:02.414273  iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200

 5376 16:44:02.417710  iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200

 5377 16:44:02.421275  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5378 16:44:02.427548  iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192

 5379 16:44:02.431071  iDelay=208, Bit 6, Center 107 (8 ~ 207) 200

 5380 16:44:02.434325  iDelay=208, Bit 7, Center 107 (8 ~ 207) 200

 5381 16:44:02.437494  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5382 16:44:02.440737  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5383 16:44:02.447044  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5384 16:44:02.450462  iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192

 5385 16:44:02.453847  iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192

 5386 16:44:02.457621  iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200

 5387 16:44:02.460448  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5388 16:44:02.463968  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5389 16:44:02.467607  ==

 5390 16:44:02.470685  Dram Type= 6, Freq= 0, CH_0, rank 1

 5391 16:44:02.474001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5392 16:44:02.474084  ==

 5393 16:44:02.474151  DQS Delay:

 5394 16:44:02.477206  DQS0 = 0, DQS1 = 0

 5395 16:44:02.477289  DQM Delay:

 5396 16:44:02.480828  DQM0 = 97, DQM1 = 86

 5397 16:44:02.480911  DQ Delay:

 5398 16:44:02.483818  DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91

 5399 16:44:02.487112  DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107

 5400 16:44:02.490492  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79

 5401 16:44:02.494113  DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =95

 5402 16:44:02.494196  

 5403 16:44:02.494262  

 5404 16:44:02.494322  ==

 5405 16:44:02.497038  Dram Type= 6, Freq= 0, CH_0, rank 1

 5406 16:44:02.500465  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5407 16:44:02.500549  ==

 5408 16:44:02.500615  

 5409 16:44:02.500676  

 5410 16:44:02.503944  	TX Vref Scan disable

 5411 16:44:02.506898   == TX Byte 0 ==

 5412 16:44:02.510531  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5413 16:44:02.513544  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5414 16:44:02.516878   == TX Byte 1 ==

 5415 16:44:02.520235  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5416 16:44:02.523840  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5417 16:44:02.523924  ==

 5418 16:44:02.526833  Dram Type= 6, Freq= 0, CH_0, rank 1

 5419 16:44:02.530258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5420 16:44:02.533789  ==

 5421 16:44:02.533909  

 5422 16:44:02.533976  

 5423 16:44:02.534037  	TX Vref Scan disable

 5424 16:44:02.537723   == TX Byte 0 ==

 5425 16:44:02.541002  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5426 16:44:02.544118  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5427 16:44:02.547521   == TX Byte 1 ==

 5428 16:44:02.550801  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5429 16:44:02.554281  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5430 16:44:02.557810  

 5431 16:44:02.557893  [DATLAT]

 5432 16:44:02.557960  Freq=933, CH0 RK1

 5433 16:44:02.558022  

 5434 16:44:02.560786  DATLAT Default: 0xb

 5435 16:44:02.560895  0, 0xFFFF, sum = 0

 5436 16:44:02.564253  1, 0xFFFF, sum = 0

 5437 16:44:02.564336  2, 0xFFFF, sum = 0

 5438 16:44:02.567424  3, 0xFFFF, sum = 0

 5439 16:44:02.567499  4, 0xFFFF, sum = 0

 5440 16:44:02.570594  5, 0xFFFF, sum = 0

 5441 16:44:02.574189  6, 0xFFFF, sum = 0

 5442 16:44:02.574289  7, 0xFFFF, sum = 0

 5443 16:44:02.577161  8, 0xFFFF, sum = 0

 5444 16:44:02.577234  9, 0xFFFF, sum = 0

 5445 16:44:02.580899  10, 0x0, sum = 1

 5446 16:44:02.580972  11, 0x0, sum = 2

 5447 16:44:02.581039  12, 0x0, sum = 3

 5448 16:44:02.583883  13, 0x0, sum = 4

 5449 16:44:02.583993  best_step = 11

 5450 16:44:02.584075  

 5451 16:44:02.587601  ==

 5452 16:44:02.587694  Dram Type= 6, Freq= 0, CH_0, rank 1

 5453 16:44:02.594090  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5454 16:44:02.594170  ==

 5455 16:44:02.594235  RX Vref Scan: 0

 5456 16:44:02.594298  

 5457 16:44:02.597571  RX Vref 0 -> 0, step: 1

 5458 16:44:02.597644  

 5459 16:44:02.600495  RX Delay -61 -> 252, step: 4

 5460 16:44:02.603852  iDelay=199, Bit 0, Center 98 (7 ~ 190) 184

 5461 16:44:02.610475  iDelay=199, Bit 1, Center 96 (3 ~ 190) 188

 5462 16:44:02.614080  iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188

 5463 16:44:02.617007  iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192

 5464 16:44:02.620405  iDelay=199, Bit 4, Center 96 (7 ~ 186) 180

 5465 16:44:02.623800  iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184

 5466 16:44:02.627329  iDelay=199, Bit 6, Center 104 (11 ~ 198) 188

 5467 16:44:02.633836  iDelay=199, Bit 7, Center 104 (11 ~ 198) 188

 5468 16:44:02.637330  iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176

 5469 16:44:02.640958  iDelay=199, Bit 9, Center 82 (-5 ~ 170) 176

 5470 16:44:02.643601  iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184

 5471 16:44:02.647387  iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172

 5472 16:44:02.650723  iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184

 5473 16:44:02.656994  iDelay=199, Bit 13, Center 94 (7 ~ 182) 176

 5474 16:44:02.660161  iDelay=199, Bit 14, Center 98 (11 ~ 186) 176

 5475 16:44:02.664060  iDelay=199, Bit 15, Center 98 (11 ~ 186) 176

 5476 16:44:02.664168  ==

 5477 16:44:02.666873  Dram Type= 6, Freq= 0, CH_0, rank 1

 5478 16:44:02.670221  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5479 16:44:02.673390  ==

 5480 16:44:02.673474  DQS Delay:

 5481 16:44:02.673557  DQS0 = 0, DQS1 = 0

 5482 16:44:02.676646  DQM Delay:

 5483 16:44:02.676728  DQM0 = 96, DQM1 = 88

 5484 16:44:02.679897  DQ Delay:

 5485 16:44:02.680018  DQ0 =98, DQ1 =96, DQ2 =92, DQ3 =94

 5486 16:44:02.683438  DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104

 5487 16:44:02.686933  DQ8 =82, DQ9 =82, DQ10 =86, DQ11 =80

 5488 16:44:02.689860  DQ12 =90, DQ13 =94, DQ14 =98, DQ15 =98

 5489 16:44:02.693326  

 5490 16:44:02.693414  

 5491 16:44:02.699839  [DQSOSCAuto] RK1, (LSB)MR18= 0x1e0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps

 5492 16:44:02.703059  CH0 RK1: MR19=505, MR18=1E0C

 5493 16:44:02.709891  CH0_RK1: MR19=0x505, MR18=0x1E0C, DQSOSC=412, MR23=63, INC=63, DEC=42

 5494 16:44:02.713468  [RxdqsGatingPostProcess] freq 933

 5495 16:44:02.716537  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5496 16:44:02.719752  best DQS0 dly(2T, 0.5T) = (0, 10)

 5497 16:44:02.722757  best DQS1 dly(2T, 0.5T) = (0, 11)

 5498 16:44:02.726175  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5499 16:44:02.729588  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5500 16:44:02.733227  best DQS0 dly(2T, 0.5T) = (0, 10)

 5501 16:44:02.736226  best DQS1 dly(2T, 0.5T) = (0, 11)

 5502 16:44:02.739927  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5503 16:44:02.743129  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5504 16:44:02.746473  Pre-setting of DQS Precalculation

 5505 16:44:02.749720  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5506 16:44:02.749824  ==

 5507 16:44:02.753179  Dram Type= 6, Freq= 0, CH_1, rank 0

 5508 16:44:02.759838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5509 16:44:02.759989  ==

 5510 16:44:02.763337  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5511 16:44:02.769846  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5512 16:44:02.773028  [CA 0] Center 36 (6~67) winsize 62

 5513 16:44:02.776708  [CA 1] Center 36 (6~67) winsize 62

 5514 16:44:02.779326  [CA 2] Center 33 (3~64) winsize 62

 5515 16:44:02.782953  [CA 3] Center 33 (3~64) winsize 62

 5516 16:44:02.786382  [CA 4] Center 34 (4~64) winsize 61

 5517 16:44:02.789506  [CA 5] Center 33 (3~64) winsize 62

 5518 16:44:02.789591  

 5519 16:44:02.793041  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5520 16:44:02.793127  

 5521 16:44:02.795901  [CATrainingPosCal] consider 1 rank data

 5522 16:44:02.799330  u2DelayCellTimex100 = 270/100 ps

 5523 16:44:02.802957  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5524 16:44:02.805920  CA1 delay=36 (6~67),Diff = 3 PI (18 cell)

 5525 16:44:02.809374  CA2 delay=33 (3~64),Diff = 0 PI (0 cell)

 5526 16:44:02.816134  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5527 16:44:02.819526  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5528 16:44:02.822495  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5529 16:44:02.822581  

 5530 16:44:02.825939  CA PerBit enable=1, Macro0, CA PI delay=33

 5531 16:44:02.826024  

 5532 16:44:02.829429  [CBTSetCACLKResult] CA Dly = 33

 5533 16:44:02.829514  CS Dly: 4 (0~35)

 5534 16:44:02.829582  ==

 5535 16:44:02.832782  Dram Type= 6, Freq= 0, CH_1, rank 1

 5536 16:44:02.839291  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5537 16:44:02.839377  ==

 5538 16:44:02.842333  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5539 16:44:02.849461  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5540 16:44:02.852273  [CA 0] Center 36 (6~67) winsize 62

 5541 16:44:02.855634  [CA 1] Center 37 (7~67) winsize 61

 5542 16:44:02.859414  [CA 2] Center 33 (3~64) winsize 62

 5543 16:44:02.862413  [CA 3] Center 33 (3~64) winsize 62

 5544 16:44:02.865725  [CA 4] Center 33 (3~64) winsize 62

 5545 16:44:02.868983  [CA 5] Center 33 (3~63) winsize 61

 5546 16:44:02.869108  

 5547 16:44:02.872319  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5548 16:44:02.872443  

 5549 16:44:02.875540  [CATrainingPosCal] consider 2 rank data

 5550 16:44:02.879098  u2DelayCellTimex100 = 270/100 ps

 5551 16:44:02.882659  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5552 16:44:02.885940  CA1 delay=37 (7~67),Diff = 4 PI (24 cell)

 5553 16:44:02.892541  CA2 delay=33 (3~64),Diff = 0 PI (0 cell)

 5554 16:44:02.895376  CA3 delay=33 (3~64),Diff = 0 PI (0 cell)

 5555 16:44:02.898824  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5556 16:44:02.902362  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 5557 16:44:02.902477  

 5558 16:44:02.905788  CA PerBit enable=1, Macro0, CA PI delay=33

 5559 16:44:02.905902  

 5560 16:44:02.908823  [CBTSetCACLKResult] CA Dly = 33

 5561 16:44:02.908927  CS Dly: 5 (0~38)

 5562 16:44:02.909019  

 5563 16:44:02.912394  ----->DramcWriteLeveling(PI) begin...

 5564 16:44:02.915292  ==

 5565 16:44:02.918701  Dram Type= 6, Freq= 0, CH_1, rank 0

 5566 16:44:02.922190  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5567 16:44:02.922275  ==

 5568 16:44:02.925700  Write leveling (Byte 0): 25 => 25

 5569 16:44:02.928722  Write leveling (Byte 1): 27 => 27

 5570 16:44:02.932219  DramcWriteLeveling(PI) end<-----

 5571 16:44:02.932301  

 5572 16:44:02.932404  ==

 5573 16:44:02.935573  Dram Type= 6, Freq= 0, CH_1, rank 0

 5574 16:44:02.938991  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5575 16:44:02.939101  ==

 5576 16:44:02.942011  [Gating] SW mode calibration

 5577 16:44:02.948438  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5578 16:44:02.955383  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5579 16:44:02.958514   0 14  0 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)

 5580 16:44:02.961794   0 14  4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5581 16:44:02.968883   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5582 16:44:02.972045   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5583 16:44:02.975730   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5584 16:44:02.978965   0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5585 16:44:02.985400   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5586 16:44:02.988750   0 14 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)

 5587 16:44:02.995140   0 15  0 | B1->B0 | 2828 2929 | 0 0 | (1 0) (0 0)

 5588 16:44:02.998599   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5589 16:44:03.001553   0 15  8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5590 16:44:03.004969   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5591 16:44:03.011446   0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5592 16:44:03.015034   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5593 16:44:03.017981   0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5594 16:44:03.024845   0 15 28 | B1->B0 | 2c2c 2e2e | 1 0 | (0 0) (0 0)

 5595 16:44:03.028420   1  0  0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

 5596 16:44:03.031333   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5597 16:44:03.037720   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5598 16:44:03.041096   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5599 16:44:03.044700   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5600 16:44:03.051091   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5601 16:44:03.054670   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5602 16:44:03.057527   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5603 16:44:03.064579   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5604 16:44:03.067627   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5605 16:44:03.071049   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5606 16:44:03.078054   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5607 16:44:03.081356   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5608 16:44:03.084188   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5609 16:44:03.091198   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5610 16:44:03.094535   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5611 16:44:03.097520   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5612 16:44:03.103945   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5613 16:44:03.107449   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5614 16:44:03.111031   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5615 16:44:03.117146   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5616 16:44:03.120681   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5617 16:44:03.124074   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5618 16:44:03.131002   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5619 16:44:03.134068  Total UI for P1: 0, mck2ui 16

 5620 16:44:03.137386  best dqsien dly found for B0: ( 1,  2, 26)

 5621 16:44:03.137490  Total UI for P1: 0, mck2ui 16

 5622 16:44:03.143824  best dqsien dly found for B1: ( 1,  2, 26)

 5623 16:44:03.147447  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5624 16:44:03.150732  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5625 16:44:03.150839  

 5626 16:44:03.153866  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5627 16:44:03.157559  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5628 16:44:03.161083  [Gating] SW calibration Done

 5629 16:44:03.161233  ==

 5630 16:44:03.163888  Dram Type= 6, Freq= 0, CH_1, rank 0

 5631 16:44:03.166875  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5632 16:44:03.166984  ==

 5633 16:44:03.170406  RX Vref Scan: 0

 5634 16:44:03.170534  

 5635 16:44:03.170663  RX Vref 0 -> 0, step: 1

 5636 16:44:03.170789  

 5637 16:44:03.173758  RX Delay -80 -> 252, step: 8

 5638 16:44:03.177222  iDelay=208, Bit 0, Center 99 (8 ~ 191) 184

 5639 16:44:03.183780  iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200

 5640 16:44:03.187521  iDelay=208, Bit 2, Center 83 (-8 ~ 175) 184

 5641 16:44:03.190196  iDelay=208, Bit 3, Center 95 (0 ~ 191) 192

 5642 16:44:03.193500  iDelay=208, Bit 4, Center 95 (0 ~ 191) 192

 5643 16:44:03.196967  iDelay=208, Bit 5, Center 107 (8 ~ 207) 200

 5644 16:44:03.200483  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5645 16:44:03.206976  iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200

 5646 16:44:03.210542  iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192

 5647 16:44:03.213652  iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192

 5648 16:44:03.216943  iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192

 5649 16:44:03.220267  iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200

 5650 16:44:03.226816  iDelay=208, Bit 12, Center 95 (0 ~ 191) 192

 5651 16:44:03.230329  iDelay=208, Bit 13, Center 95 (0 ~ 191) 192

 5652 16:44:03.233787  iDelay=208, Bit 14, Center 95 (0 ~ 191) 192

 5653 16:44:03.236733  iDelay=208, Bit 15, Center 95 (0 ~ 191) 192

 5654 16:44:03.236843  ==

 5655 16:44:03.240248  Dram Type= 6, Freq= 0, CH_1, rank 0

 5656 16:44:03.243243  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5657 16:44:03.243351  ==

 5658 16:44:03.246730  DQS Delay:

 5659 16:44:03.246850  DQS0 = 0, DQS1 = 0

 5660 16:44:03.250300  DQM Delay:

 5661 16:44:03.250388  DQM0 = 96, DQM1 = 88

 5662 16:44:03.253755  DQ Delay:

 5663 16:44:03.253839  DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95

 5664 16:44:03.256587  DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91

 5665 16:44:03.260102  DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83

 5666 16:44:03.263711  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5667 16:44:03.263828  

 5668 16:44:03.266540  

 5669 16:44:03.266659  ==

 5670 16:44:03.270027  Dram Type= 6, Freq= 0, CH_1, rank 0

 5671 16:44:03.273592  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5672 16:44:03.273677  ==

 5673 16:44:03.273745  

 5674 16:44:03.273808  

 5675 16:44:03.276577  	TX Vref Scan disable

 5676 16:44:03.276662   == TX Byte 0 ==

 5677 16:44:03.283366  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5678 16:44:03.286507  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5679 16:44:03.286631   == TX Byte 1 ==

 5680 16:44:03.292986  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5681 16:44:03.296465  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5682 16:44:03.296578  ==

 5683 16:44:03.299765  Dram Type= 6, Freq= 0, CH_1, rank 0

 5684 16:44:03.303228  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5685 16:44:03.303345  ==

 5686 16:44:03.303446  

 5687 16:44:03.303536  

 5688 16:44:03.306643  	TX Vref Scan disable

 5689 16:44:03.309603   == TX Byte 0 ==

 5690 16:44:03.313200  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5691 16:44:03.316173  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5692 16:44:03.319586   == TX Byte 1 ==

 5693 16:44:03.322916  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5694 16:44:03.326199  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5695 16:44:03.326285  

 5696 16:44:03.329283  [DATLAT]

 5697 16:44:03.329367  Freq=933, CH1 RK0

 5698 16:44:03.329435  

 5699 16:44:03.332815  DATLAT Default: 0xd

 5700 16:44:03.332900  0, 0xFFFF, sum = 0

 5701 16:44:03.336007  1, 0xFFFF, sum = 0

 5702 16:44:03.336094  2, 0xFFFF, sum = 0

 5703 16:44:03.339407  3, 0xFFFF, sum = 0

 5704 16:44:03.339493  4, 0xFFFF, sum = 0

 5705 16:44:03.342938  5, 0xFFFF, sum = 0

 5706 16:44:03.343024  6, 0xFFFF, sum = 0

 5707 16:44:03.345921  7, 0xFFFF, sum = 0

 5708 16:44:03.346006  8, 0xFFFF, sum = 0

 5709 16:44:03.349440  9, 0xFFFF, sum = 0

 5710 16:44:03.349525  10, 0x0, sum = 1

 5711 16:44:03.352810  11, 0x0, sum = 2

 5712 16:44:03.352897  12, 0x0, sum = 3

 5713 16:44:03.356177  13, 0x0, sum = 4

 5714 16:44:03.356266  best_step = 11

 5715 16:44:03.356333  

 5716 16:44:03.356395  ==

 5717 16:44:03.359208  Dram Type= 6, Freq= 0, CH_1, rank 0

 5718 16:44:03.366160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5719 16:44:03.366256  ==

 5720 16:44:03.366327  RX Vref Scan: 1

 5721 16:44:03.366389  

 5722 16:44:03.369597  RX Vref 0 -> 0, step: 1

 5723 16:44:03.369686  

 5724 16:44:03.372662  RX Delay -61 -> 252, step: 4

 5725 16:44:03.372747  

 5726 16:44:03.375748  Set Vref, RX VrefLevel [Byte0]: 59

 5727 16:44:03.379114                           [Byte1]: 53

 5728 16:44:03.379202  

 5729 16:44:03.382544  Final RX Vref Byte 0 = 59 to rank0

 5730 16:44:03.386060  Final RX Vref Byte 1 = 53 to rank0

 5731 16:44:03.389419  Final RX Vref Byte 0 = 59 to rank1

 5732 16:44:03.392728  Final RX Vref Byte 1 = 53 to rank1==

 5733 16:44:03.396078  Dram Type= 6, Freq= 0, CH_1, rank 0

 5734 16:44:03.399309  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5735 16:44:03.399413  ==

 5736 16:44:03.402392  DQS Delay:

 5737 16:44:03.402479  DQS0 = 0, DQS1 = 0

 5738 16:44:03.405982  DQM Delay:

 5739 16:44:03.406110  DQM0 = 98, DQM1 = 90

 5740 16:44:03.406176  DQ Delay:

 5741 16:44:03.409252  DQ0 =102, DQ1 =92, DQ2 =88, DQ3 =98

 5742 16:44:03.412257  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96

 5743 16:44:03.415764  DQ8 =80, DQ9 =80, DQ10 =94, DQ11 =86

 5744 16:44:03.419345  DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96

 5745 16:44:03.419472  

 5746 16:44:03.419552  

 5747 16:44:03.428859  [DQSOSCAuto] RK0, (LSB)MR18= 0x16f2, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps

 5748 16:44:03.432543  CH1 RK0: MR19=504, MR18=16F2

 5749 16:44:03.435628  CH1_RK0: MR19=0x504, MR18=0x16F2, DQSOSC=414, MR23=63, INC=63, DEC=42

 5750 16:44:03.438890  

 5751 16:44:03.442346  ----->DramcWriteLeveling(PI) begin...

 5752 16:44:03.442432  ==

 5753 16:44:03.445918  Dram Type= 6, Freq= 0, CH_1, rank 1

 5754 16:44:03.449405  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5755 16:44:03.449498  ==

 5756 16:44:03.452295  Write leveling (Byte 0): 26 => 26

 5757 16:44:03.455800  Write leveling (Byte 1): 25 => 25

 5758 16:44:03.458748  DramcWriteLeveling(PI) end<-----

 5759 16:44:03.458831  

 5760 16:44:03.458896  ==

 5761 16:44:03.462516  Dram Type= 6, Freq= 0, CH_1, rank 1

 5762 16:44:03.465487  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5763 16:44:03.465591  ==

 5764 16:44:03.469107  [Gating] SW mode calibration

 5765 16:44:03.475688  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5766 16:44:03.482307  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5767 16:44:03.485561   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5768 16:44:03.488905   0 14  4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5769 16:44:03.495796   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5770 16:44:03.498839   0 14 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)

 5771 16:44:03.502228   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5772 16:44:03.508444   0 14 20 | B1->B0 | 3535 3333 | 0 1 | (0 0) (1 1)

 5773 16:44:03.511832   0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (1 0)

 5774 16:44:03.515357   0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)

 5775 16:44:03.521804   0 15  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 5776 16:44:03.525378   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5777 16:44:03.528939   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5778 16:44:03.535051   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5779 16:44:03.538800   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5780 16:44:03.541726   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5781 16:44:03.545205   0 15 24 | B1->B0 | 2626 3636 | 0 0 | (0 0) (1 1)

 5782 16:44:03.552192   0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)

 5783 16:44:03.555139   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5784 16:44:03.558659   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5785 16:44:03.564845   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5786 16:44:03.568337   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5787 16:44:03.571884   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5788 16:44:03.578448   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5789 16:44:03.582075   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5790 16:44:03.584990   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5791 16:44:03.591819   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5792 16:44:03.595303   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5793 16:44:03.598728   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5794 16:44:03.604926   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5795 16:44:03.608223   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5796 16:44:03.611711   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5797 16:44:03.618551   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5798 16:44:03.621596   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5799 16:44:03.624521   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5800 16:44:03.631529   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5801 16:44:03.634942   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5802 16:44:03.638318   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5803 16:44:03.645012   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5804 16:44:03.647810   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5805 16:44:03.651703   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5806 16:44:03.658185   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5807 16:44:03.658270  Total UI for P1: 0, mck2ui 16

 5808 16:44:03.664768  best dqsien dly found for B0: ( 1,  2, 22)

 5809 16:44:03.664859  Total UI for P1: 0, mck2ui 16

 5810 16:44:03.667817  best dqsien dly found for B1: ( 1,  2, 24)

 5811 16:44:03.674744  best DQS0 dly(MCK, UI, PI) = (1, 2, 22)

 5812 16:44:03.678352  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5813 16:44:03.678430  

 5814 16:44:03.681238  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5815 16:44:03.684940  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5816 16:44:03.687820  [Gating] SW calibration Done

 5817 16:44:03.687920  ==

 5818 16:44:03.691652  Dram Type= 6, Freq= 0, CH_1, rank 1

 5819 16:44:03.694894  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5820 16:44:03.694979  ==

 5821 16:44:03.697896  RX Vref Scan: 0

 5822 16:44:03.697979  

 5823 16:44:03.698051  RX Vref 0 -> 0, step: 1

 5824 16:44:03.698114  

 5825 16:44:03.701296  RX Delay -80 -> 252, step: 8

 5826 16:44:03.704877  iDelay=200, Bit 0, Center 95 (0 ~ 191) 192

 5827 16:44:03.708167  iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200

 5828 16:44:03.714826  iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192

 5829 16:44:03.717738  iDelay=200, Bit 3, Center 95 (0 ~ 191) 192

 5830 16:44:03.721615  iDelay=200, Bit 4, Center 95 (0 ~ 191) 192

 5831 16:44:03.724709  iDelay=200, Bit 5, Center 103 (8 ~ 199) 192

 5832 16:44:03.728253  iDelay=200, Bit 6, Center 103 (8 ~ 199) 192

 5833 16:44:03.731253  iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192

 5834 16:44:03.737712  iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192

 5835 16:44:03.741095  iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192

 5836 16:44:03.744519  iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200

 5837 16:44:03.748110  iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184

 5838 16:44:03.751387  iDelay=200, Bit 12, Center 95 (0 ~ 191) 192

 5839 16:44:03.754499  iDelay=200, Bit 13, Center 95 (0 ~ 191) 192

 5840 16:44:03.761478  iDelay=200, Bit 14, Center 95 (0 ~ 191) 192

 5841 16:44:03.764571  iDelay=200, Bit 15, Center 95 (0 ~ 191) 192

 5842 16:44:03.764659  ==

 5843 16:44:03.767822  Dram Type= 6, Freq= 0, CH_1, rank 1

 5844 16:44:03.771352  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5845 16:44:03.771451  ==

 5846 16:44:03.774538  DQS Delay:

 5847 16:44:03.774622  DQS0 = 0, DQS1 = 0

 5848 16:44:03.774689  DQM Delay:

 5849 16:44:03.777972  DQM0 = 94, DQM1 = 89

 5850 16:44:03.778055  DQ Delay:

 5851 16:44:03.781421  DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95

 5852 16:44:03.784552  DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87

 5853 16:44:03.787951  DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83

 5854 16:44:03.790935  DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95

 5855 16:44:03.791046  

 5856 16:44:03.791112  

 5857 16:44:03.791173  ==

 5858 16:44:03.794645  Dram Type= 6, Freq= 0, CH_1, rank 1

 5859 16:44:03.800890  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5860 16:44:03.801015  ==

 5861 16:44:03.801088  

 5862 16:44:03.801150  

 5863 16:44:03.801208  	TX Vref Scan disable

 5864 16:44:03.804765   == TX Byte 0 ==

 5865 16:44:03.808263  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5866 16:44:03.814568  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5867 16:44:03.814683   == TX Byte 1 ==

 5868 16:44:03.817434  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5869 16:44:03.824307  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5870 16:44:03.824433  ==

 5871 16:44:03.827751  Dram Type= 6, Freq= 0, CH_1, rank 1

 5872 16:44:03.830716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5873 16:44:03.830803  ==

 5874 16:44:03.830875  

 5875 16:44:03.830941  

 5876 16:44:03.834186  	TX Vref Scan disable

 5877 16:44:03.834282   == TX Byte 0 ==

 5878 16:44:03.841153  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5879 16:44:03.844356  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5880 16:44:03.844442   == TX Byte 1 ==

 5881 16:44:03.851082  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5882 16:44:03.854038  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5883 16:44:03.854153  

 5884 16:44:03.854233  [DATLAT]

 5885 16:44:03.857538  Freq=933, CH1 RK1

 5886 16:44:03.857647  

 5887 16:44:03.857782  DATLAT Default: 0xb

 5888 16:44:03.860829  0, 0xFFFF, sum = 0

 5889 16:44:03.860942  1, 0xFFFF, sum = 0

 5890 16:44:03.863998  2, 0xFFFF, sum = 0

 5891 16:44:03.867618  3, 0xFFFF, sum = 0

 5892 16:44:03.867734  4, 0xFFFF, sum = 0

 5893 16:44:03.870399  5, 0xFFFF, sum = 0

 5894 16:44:03.870479  6, 0xFFFF, sum = 0

 5895 16:44:03.873929  7, 0xFFFF, sum = 0

 5896 16:44:03.874014  8, 0xFFFF, sum = 0

 5897 16:44:03.877419  9, 0xFFFF, sum = 0

 5898 16:44:03.877531  10, 0x0, sum = 1

 5899 16:44:03.880658  11, 0x0, sum = 2

 5900 16:44:03.880746  12, 0x0, sum = 3

 5901 16:44:03.884241  13, 0x0, sum = 4

 5902 16:44:03.884356  best_step = 11

 5903 16:44:03.884454  

 5904 16:44:03.884520  ==

 5905 16:44:03.887130  Dram Type= 6, Freq= 0, CH_1, rank 1

 5906 16:44:03.890636  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5907 16:44:03.890740  ==

 5908 16:44:03.893563  RX Vref Scan: 0

 5909 16:44:03.893666  

 5910 16:44:03.896952  RX Vref 0 -> 0, step: 1

 5911 16:44:03.897028  

 5912 16:44:03.897094  RX Delay -61 -> 252, step: 4

 5913 16:44:03.905179  iDelay=199, Bit 0, Center 96 (3 ~ 190) 188

 5914 16:44:03.908116  iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184

 5915 16:44:03.911449  iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184

 5916 16:44:03.914790  iDelay=199, Bit 3, Center 94 (3 ~ 186) 184

 5917 16:44:03.918317  iDelay=199, Bit 4, Center 98 (7 ~ 190) 184

 5918 16:44:03.921978  iDelay=199, Bit 5, Center 106 (15 ~ 198) 184

 5919 16:44:03.927920  iDelay=199, Bit 6, Center 104 (11 ~ 198) 188

 5920 16:44:03.931458  iDelay=199, Bit 7, Center 90 (3 ~ 178) 176

 5921 16:44:03.935135  iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188

 5922 16:44:03.938477  iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184

 5923 16:44:03.941445  iDelay=199, Bit 10, Center 90 (-5 ~ 186) 192

 5924 16:44:03.947932  iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184

 5925 16:44:03.951308  iDelay=199, Bit 12, Center 98 (11 ~ 186) 176

 5926 16:44:03.954210  iDelay=199, Bit 13, Center 100 (11 ~ 190) 180

 5927 16:44:03.957795  iDelay=199, Bit 14, Center 100 (11 ~ 190) 180

 5928 16:44:03.960769  iDelay=199, Bit 15, Center 100 (11 ~ 190) 180

 5929 16:44:03.964684  ==

 5930 16:44:03.967644  Dram Type= 6, Freq= 0, CH_1, rank 1

 5931 16:44:03.971143  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5932 16:44:03.971231  ==

 5933 16:44:03.971299  DQS Delay:

 5934 16:44:03.974555  DQS0 = 0, DQS1 = 0

 5935 16:44:03.974659  DQM Delay:

 5936 16:44:03.977470  DQM0 = 95, DQM1 = 91

 5937 16:44:03.977545  DQ Delay:

 5938 16:44:03.980897  DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =94

 5939 16:44:03.984289  DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =90

 5940 16:44:03.987722  DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =82

 5941 16:44:03.990711  DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100

 5942 16:44:03.990810  

 5943 16:44:03.990904  

 5944 16:44:03.997719  [DQSOSCAuto] RK1, (LSB)MR18= 0xd16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps

 5945 16:44:04.000697  CH1 RK1: MR19=505, MR18=D16

 5946 16:44:04.008103  CH1_RK1: MR19=0x505, MR18=0xD16, DQSOSC=414, MR23=63, INC=63, DEC=42

 5947 16:44:04.010945  [RxdqsGatingPostProcess] freq 933

 5948 16:44:04.017761  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5949 16:44:04.020721  best DQS0 dly(2T, 0.5T) = (0, 10)

 5950 16:44:04.020801  best DQS1 dly(2T, 0.5T) = (0, 10)

 5951 16:44:04.024204  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5952 16:44:04.027433  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5953 16:44:04.030966  best DQS0 dly(2T, 0.5T) = (0, 10)

 5954 16:44:04.034420  best DQS1 dly(2T, 0.5T) = (0, 10)

 5955 16:44:04.037329  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5956 16:44:04.040914  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5957 16:44:04.043901  Pre-setting of DQS Precalculation

 5958 16:44:04.050894  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5959 16:44:04.057344  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5960 16:44:04.064236  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5961 16:44:04.064351  

 5962 16:44:04.064447  

 5963 16:44:04.067596  [Calibration Summary] 1866 Mbps

 5964 16:44:04.067710  CH 0, Rank 0

 5965 16:44:04.070539  SW Impedance     : PASS

 5966 16:44:04.070662  DUTY Scan        : NO K

 5967 16:44:04.074175  ZQ Calibration   : PASS

 5968 16:44:04.077296  Jitter Meter     : NO K

 5969 16:44:04.077405  CBT Training     : PASS

 5970 16:44:04.080790  Write leveling   : PASS

 5971 16:44:04.083790  RX DQS gating    : PASS

 5972 16:44:04.083899  RX DQ/DQS(RDDQC) : PASS

 5973 16:44:04.087738  TX DQ/DQS        : PASS

 5974 16:44:04.090617  RX DATLAT        : PASS

 5975 16:44:04.090718  RX DQ/DQS(Engine): PASS

 5976 16:44:04.093561  TX OE            : NO K

 5977 16:44:04.093662  All Pass.

 5978 16:44:04.093752  

 5979 16:44:04.097117  CH 0, Rank 1

 5980 16:44:04.097218  SW Impedance     : PASS

 5981 16:44:04.100673  DUTY Scan        : NO K

 5982 16:44:04.103653  ZQ Calibration   : PASS

 5983 16:44:04.103754  Jitter Meter     : NO K

 5984 16:44:04.107295  CBT Training     : PASS

 5985 16:44:04.110273  Write leveling   : PASS

 5986 16:44:04.110384  RX DQS gating    : PASS

 5987 16:44:04.113838  RX DQ/DQS(RDDQC) : PASS

 5988 16:44:04.117273  TX DQ/DQS        : PASS

 5989 16:44:04.117378  RX DATLAT        : PASS

 5990 16:44:04.120133  RX DQ/DQS(Engine): PASS

 5991 16:44:04.123916  TX OE            : NO K

 5992 16:44:04.124033  All Pass.

 5993 16:44:04.124127  

 5994 16:44:04.124248  CH 1, Rank 0

 5995 16:44:04.127118  SW Impedance     : PASS

 5996 16:44:04.130396  DUTY Scan        : NO K

 5997 16:44:04.130511  ZQ Calibration   : PASS

 5998 16:44:04.133486  Jitter Meter     : NO K

 5999 16:44:04.133579  CBT Training     : PASS

 6000 16:44:04.136914  Write leveling   : PASS

 6001 16:44:04.140285  RX DQS gating    : PASS

 6002 16:44:04.140368  RX DQ/DQS(RDDQC) : PASS

 6003 16:44:04.143679  TX DQ/DQS        : PASS

 6004 16:44:04.146588  RX DATLAT        : PASS

 6005 16:44:04.146663  RX DQ/DQS(Engine): PASS

 6006 16:44:04.150303  TX OE            : NO K

 6007 16:44:04.150377  All Pass.

 6008 16:44:04.150439  

 6009 16:44:04.153603  CH 1, Rank 1

 6010 16:44:04.153677  SW Impedance     : PASS

 6011 16:44:04.156669  DUTY Scan        : NO K

 6012 16:44:04.159977  ZQ Calibration   : PASS

 6013 16:44:04.160052  Jitter Meter     : NO K

 6014 16:44:04.163495  CBT Training     : PASS

 6015 16:44:04.166482  Write leveling   : PASS

 6016 16:44:04.166567  RX DQS gating    : PASS

 6017 16:44:04.169978  RX DQ/DQS(RDDQC) : PASS

 6018 16:44:04.173305  TX DQ/DQS        : PASS

 6019 16:44:04.173394  RX DATLAT        : PASS

 6020 16:44:04.176756  RX DQ/DQS(Engine): PASS

 6021 16:44:04.179660  TX OE            : NO K

 6022 16:44:04.179765  All Pass.

 6023 16:44:04.179878  

 6024 16:44:04.179980  DramC Write-DBI off

 6025 16:44:04.183162  	PER_BANK_REFRESH: Hybrid Mode

 6026 16:44:04.186652  TX_TRACKING: ON

 6027 16:44:04.192923  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6028 16:44:04.196444  [FAST_K] Save calibration result to emmc

 6029 16:44:04.203070  dramc_set_vcore_voltage set vcore to 650000

 6030 16:44:04.203151  Read voltage for 400, 6

 6031 16:44:04.206403  Vio18 = 0

 6032 16:44:04.206480  Vcore = 650000

 6033 16:44:04.206544  Vdram = 0

 6034 16:44:04.206613  Vddq = 0

 6035 16:44:04.210135  Vmddr = 0

 6036 16:44:04.213313  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6037 16:44:04.219788  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6038 16:44:04.223177  MEM_TYPE=3, freq_sel=20

 6039 16:44:04.223282  sv_algorithm_assistance_LP4_800 

 6040 16:44:04.229773  ============ PULL DRAM RESETB DOWN ============

 6041 16:44:04.233029  ========== PULL DRAM RESETB DOWN end =========

 6042 16:44:04.236836  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6043 16:44:04.240105  =================================== 

 6044 16:44:04.243280  LPDDR4 DRAM CONFIGURATION

 6045 16:44:04.246474  =================================== 

 6046 16:44:04.249434  EX_ROW_EN[0]    = 0x0

 6047 16:44:04.249540  EX_ROW_EN[1]    = 0x0

 6048 16:44:04.253188  LP4Y_EN      = 0x0

 6049 16:44:04.253264  WORK_FSP     = 0x0

 6050 16:44:04.256040  WL           = 0x2

 6051 16:44:04.256116  RL           = 0x2

 6052 16:44:04.259539  BL           = 0x2

 6053 16:44:04.259639  RPST         = 0x0

 6054 16:44:04.262990  RD_PRE       = 0x0

 6055 16:44:04.263085  WR_PRE       = 0x1

 6056 16:44:04.266177  WR_PST       = 0x0

 6057 16:44:04.266289  DBI_WR       = 0x0

 6058 16:44:04.269801  DBI_RD       = 0x0

 6059 16:44:04.269883  OTF          = 0x1

 6060 16:44:04.272824  =================================== 

 6061 16:44:04.276046  =================================== 

 6062 16:44:04.279569  ANA top config

 6063 16:44:04.282964  =================================== 

 6064 16:44:04.286477  DLL_ASYNC_EN            =  0

 6065 16:44:04.286623  ALL_SLAVE_EN            =  1

 6066 16:44:04.290105  NEW_RANK_MODE           =  1

 6067 16:44:04.292781  DLL_IDLE_MODE           =  1

 6068 16:44:04.296295  LP45_APHY_COMB_EN       =  1

 6069 16:44:04.296415  TX_ODT_DIS              =  1

 6070 16:44:04.299656  NEW_8X_MODE             =  1

 6071 16:44:04.303239  =================================== 

 6072 16:44:04.306204  =================================== 

 6073 16:44:04.309830  data_rate                  =  800

 6074 16:44:04.313303  CKR                        = 1

 6075 16:44:04.316691  DQ_P2S_RATIO               = 4

 6076 16:44:04.319592  =================================== 

 6077 16:44:04.323239  CA_P2S_RATIO               = 4

 6078 16:44:04.323355  DQ_CA_OPEN                 = 0

 6079 16:44:04.326077  DQ_SEMI_OPEN               = 1

 6080 16:44:04.329575  CA_SEMI_OPEN               = 1

 6081 16:44:04.332957  CA_FULL_RATE               = 0

 6082 16:44:04.336356  DQ_CKDIV4_EN               = 0

 6083 16:44:04.339551  CA_CKDIV4_EN               = 1

 6084 16:44:04.339662  CA_PREDIV_EN               = 0

 6085 16:44:04.342918  PH8_DLY                    = 0

 6086 16:44:04.346267  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6087 16:44:04.349886  DQ_AAMCK_DIV               = 0

 6088 16:44:04.353170  CA_AAMCK_DIV               = 0

 6089 16:44:04.356612  CA_ADMCK_DIV               = 4

 6090 16:44:04.356723  DQ_TRACK_CA_EN             = 0

 6091 16:44:04.359337  CA_PICK                    = 800

 6092 16:44:04.362961  CA_MCKIO                   = 400

 6093 16:44:04.365844  MCKIO_SEMI                 = 400

 6094 16:44:04.369264  PLL_FREQ                   = 3016

 6095 16:44:04.372700  DQ_UI_PI_RATIO             = 32

 6096 16:44:04.375700  CA_UI_PI_RATIO             = 32

 6097 16:44:04.379052  =================================== 

 6098 16:44:04.382359  =================================== 

 6099 16:44:04.382466  memory_type:LPDDR4         

 6100 16:44:04.385807  GP_NUM     : 10       

 6101 16:44:04.389192  SRAM_EN    : 1       

 6102 16:44:04.389268  MD32_EN    : 0       

 6103 16:44:04.392924  =================================== 

 6104 16:44:04.395792  [ANA_INIT] >>>>>>>>>>>>>> 

 6105 16:44:04.399289  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6106 16:44:04.402730  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6107 16:44:04.405806  =================================== 

 6108 16:44:04.409277  data_rate = 800,PCW = 0X7400

 6109 16:44:04.412898  =================================== 

 6110 16:44:04.415680  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6111 16:44:04.419341  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6112 16:44:04.432922  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6113 16:44:04.435718  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6114 16:44:04.439230  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6115 16:44:04.442511  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6116 16:44:04.445703  [ANA_INIT] flow start 

 6117 16:44:04.445775  [ANA_INIT] PLL >>>>>>>> 

 6118 16:44:04.448971  [ANA_INIT] PLL <<<<<<<< 

 6119 16:44:04.452192  [ANA_INIT] MIDPI >>>>>>>> 

 6120 16:44:04.455688  [ANA_INIT] MIDPI <<<<<<<< 

 6121 16:44:04.455757  [ANA_INIT] DLL >>>>>>>> 

 6122 16:44:04.458903  [ANA_INIT] flow end 

 6123 16:44:04.462943  ============ LP4 DIFF to SE enter ============

 6124 16:44:04.465575  ============ LP4 DIFF to SE exit  ============

 6125 16:44:04.469136  [ANA_INIT] <<<<<<<<<<<<< 

 6126 16:44:04.472738  [Flow] Enable top DCM control >>>>> 

 6127 16:44:04.475537  [Flow] Enable top DCM control <<<<< 

 6128 16:44:04.479047  Enable DLL master slave shuffle 

 6129 16:44:04.485479  ============================================================== 

 6130 16:44:04.485566  Gating Mode config

 6131 16:44:04.492617  ============================================================== 

 6132 16:44:04.492703  Config description: 

 6133 16:44:04.502610  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6134 16:44:04.509377  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6135 16:44:04.515901  SELPH_MODE            0: By rank         1: By Phase 

 6136 16:44:04.519295  ============================================================== 

 6137 16:44:04.522838  GAT_TRACK_EN                 =  0

 6138 16:44:04.525795  RX_GATING_MODE               =  2

 6139 16:44:04.529343  RX_GATING_TRACK_MODE         =  2

 6140 16:44:04.532280  SELPH_MODE                   =  1

 6141 16:44:04.535846  PICG_EARLY_EN                =  1

 6142 16:44:04.539433  VALID_LAT_VALUE              =  1

 6143 16:44:04.542331  ============================================================== 

 6144 16:44:04.545845  Enter into Gating configuration >>>> 

 6145 16:44:04.549267  Exit from Gating configuration <<<< 

 6146 16:44:04.552528  Enter into  DVFS_PRE_config >>>>> 

 6147 16:44:04.565714  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6148 16:44:04.569130  Exit from  DVFS_PRE_config <<<<< 

 6149 16:44:04.572155  Enter into PICG configuration >>>> 

 6150 16:44:04.572244  Exit from PICG configuration <<<< 

 6151 16:44:04.575699  [RX_INPUT] configuration >>>>> 

 6152 16:44:04.579204  [RX_INPUT] configuration <<<<< 

 6153 16:44:04.585474  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6154 16:44:04.588909  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6155 16:44:04.595598  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6156 16:44:04.602196  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6157 16:44:04.608541  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6158 16:44:04.615510  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6159 16:44:04.618461  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6160 16:44:04.622050  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6161 16:44:04.625777  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6162 16:44:04.632176  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6163 16:44:04.635646  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6164 16:44:04.638830  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6165 16:44:04.642186  =================================== 

 6166 16:44:04.645151  LPDDR4 DRAM CONFIGURATION

 6167 16:44:04.648746  =================================== 

 6168 16:44:04.651692  EX_ROW_EN[0]    = 0x0

 6169 16:44:04.651784  EX_ROW_EN[1]    = 0x0

 6170 16:44:04.655180  LP4Y_EN      = 0x0

 6171 16:44:04.655259  WORK_FSP     = 0x0

 6172 16:44:04.658517  WL           = 0x2

 6173 16:44:04.658618  RL           = 0x2

 6174 16:44:04.661733  BL           = 0x2

 6175 16:44:04.661838  RPST         = 0x0

 6176 16:44:04.665293  RD_PRE       = 0x0

 6177 16:44:04.665399  WR_PRE       = 0x1

 6178 16:44:04.668524  WR_PST       = 0x0

 6179 16:44:04.668614  DBI_WR       = 0x0

 6180 16:44:04.672049  DBI_RD       = 0x0

 6181 16:44:04.672126  OTF          = 0x1

 6182 16:44:04.675097  =================================== 

 6183 16:44:04.681495  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6184 16:44:04.684794  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6185 16:44:04.688088  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6186 16:44:04.691624  =================================== 

 6187 16:44:04.695058  LPDDR4 DRAM CONFIGURATION

 6188 16:44:04.698489  =================================== 

 6189 16:44:04.701240  EX_ROW_EN[0]    = 0x10

 6190 16:44:04.701315  EX_ROW_EN[1]    = 0x0

 6191 16:44:04.704698  LP4Y_EN      = 0x0

 6192 16:44:04.704770  WORK_FSP     = 0x0

 6193 16:44:04.708286  WL           = 0x2

 6194 16:44:04.708358  RL           = 0x2

 6195 16:44:04.711218  BL           = 0x2

 6196 16:44:04.711293  RPST         = 0x0

 6197 16:44:04.714650  RD_PRE       = 0x0

 6198 16:44:04.714721  WR_PRE       = 0x1

 6199 16:44:04.717911  WR_PST       = 0x0

 6200 16:44:04.717983  DBI_WR       = 0x0

 6201 16:44:04.721623  DBI_RD       = 0x0

 6202 16:44:04.721696  OTF          = 0x1

 6203 16:44:04.724645  =================================== 

 6204 16:44:04.731082  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6205 16:44:04.735717  nWR fixed to 30

 6206 16:44:04.739708  [ModeRegInit_LP4] CH0 RK0

 6207 16:44:04.739784  [ModeRegInit_LP4] CH0 RK1

 6208 16:44:04.742714  [ModeRegInit_LP4] CH1 RK0

 6209 16:44:04.746211  [ModeRegInit_LP4] CH1 RK1

 6210 16:44:04.746319  match AC timing 19

 6211 16:44:04.752858  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6212 16:44:04.755824  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6213 16:44:04.759301  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6214 16:44:04.766067  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6215 16:44:04.769311  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6216 16:44:04.769398  ==

 6217 16:44:04.772577  Dram Type= 6, Freq= 0, CH_0, rank 0

 6218 16:44:04.775912  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6219 16:44:04.776061  ==

 6220 16:44:04.782429  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6221 16:44:04.788835  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6222 16:44:04.792535  [CA 0] Center 36 (8~64) winsize 57

 6223 16:44:04.796131  [CA 1] Center 36 (8~64) winsize 57

 6224 16:44:04.798742  [CA 2] Center 36 (8~64) winsize 57

 6225 16:44:04.801983  [CA 3] Center 36 (8~64) winsize 57

 6226 16:44:04.802089  [CA 4] Center 36 (8~64) winsize 57

 6227 16:44:04.805349  [CA 5] Center 36 (8~64) winsize 57

 6228 16:44:04.805450  

 6229 16:44:04.812478  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6230 16:44:04.812579  

 6231 16:44:04.815444  [CATrainingPosCal] consider 1 rank data

 6232 16:44:04.818866  u2DelayCellTimex100 = 270/100 ps

 6233 16:44:04.822446  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6234 16:44:04.825526  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6235 16:44:04.828716  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6236 16:44:04.832376  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6237 16:44:04.835328  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6238 16:44:04.838978  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6239 16:44:04.839085  

 6240 16:44:04.841927  CA PerBit enable=1, Macro0, CA PI delay=36

 6241 16:44:04.842011  

 6242 16:44:04.845402  [CBTSetCACLKResult] CA Dly = 36

 6243 16:44:04.848986  CS Dly: 1 (0~32)

 6244 16:44:04.849073  ==

 6245 16:44:04.851867  Dram Type= 6, Freq= 0, CH_0, rank 1

 6246 16:44:04.855459  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6247 16:44:04.855544  ==

 6248 16:44:04.861992  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6249 16:44:04.868418  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6250 16:44:04.868551  [CA 0] Center 36 (8~64) winsize 57

 6251 16:44:04.871764  [CA 1] Center 36 (8~64) winsize 57

 6252 16:44:04.875479  [CA 2] Center 36 (8~64) winsize 57

 6253 16:44:04.878785  [CA 3] Center 36 (8~64) winsize 57

 6254 16:44:04.881651  [CA 4] Center 36 (8~64) winsize 57

 6255 16:44:04.884923  [CA 5] Center 36 (8~64) winsize 57

 6256 16:44:04.885008  

 6257 16:44:04.888824  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6258 16:44:04.888913  

 6259 16:44:04.892294  [CATrainingPosCal] consider 2 rank data

 6260 16:44:04.895686  u2DelayCellTimex100 = 270/100 ps

 6261 16:44:04.898365  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6262 16:44:04.905377  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6263 16:44:04.908463  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6264 16:44:04.911556  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6265 16:44:04.915031  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6266 16:44:04.918403  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6267 16:44:04.918532  

 6268 16:44:04.921331  CA PerBit enable=1, Macro0, CA PI delay=36

 6269 16:44:04.921412  

 6270 16:44:04.924897  [CBTSetCACLKResult] CA Dly = 36

 6271 16:44:04.925028  CS Dly: 1 (0~32)

 6272 16:44:04.925128  

 6273 16:44:04.931706  ----->DramcWriteLeveling(PI) begin...

 6274 16:44:04.931827  ==

 6275 16:44:04.935034  Dram Type= 6, Freq= 0, CH_0, rank 0

 6276 16:44:04.938881  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6277 16:44:04.938994  ==

 6278 16:44:04.941825  Write leveling (Byte 0): 40 => 8

 6279 16:44:04.944734  Write leveling (Byte 1): 32 => 0

 6280 16:44:04.948347  DramcWriteLeveling(PI) end<-----

 6281 16:44:04.948466  

 6282 16:44:04.948566  ==

 6283 16:44:04.951335  Dram Type= 6, Freq= 0, CH_0, rank 0

 6284 16:44:04.954739  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6285 16:44:04.954846  ==

 6286 16:44:04.958195  [Gating] SW mode calibration

 6287 16:44:04.964757  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6288 16:44:04.971219  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6289 16:44:04.974651   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6290 16:44:04.978059   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6291 16:44:04.984633   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6292 16:44:04.987541   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6293 16:44:04.990753   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6294 16:44:04.997741   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6295 16:44:05.000956   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6296 16:44:05.004148   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6297 16:44:05.010842   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6298 16:44:05.010956  Total UI for P1: 0, mck2ui 16

 6299 16:44:05.013996  best dqsien dly found for B0: ( 0, 14, 24)

 6300 16:44:05.017820  Total UI for P1: 0, mck2ui 16

 6301 16:44:05.020946  best dqsien dly found for B1: ( 0, 14, 24)

 6302 16:44:05.027598  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6303 16:44:05.030970  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6304 16:44:05.031065  

 6305 16:44:05.033971  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6306 16:44:05.037678  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6307 16:44:05.040502  [Gating] SW calibration Done

 6308 16:44:05.040591  ==

 6309 16:44:05.044031  Dram Type= 6, Freq= 0, CH_0, rank 0

 6310 16:44:05.047494  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6311 16:44:05.047608  ==

 6312 16:44:05.050970  RX Vref Scan: 0

 6313 16:44:05.051076  

 6314 16:44:05.051168  RX Vref 0 -> 0, step: 1

 6315 16:44:05.051257  

 6316 16:44:05.053928  RX Delay -410 -> 252, step: 16

 6317 16:44:05.060557  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6318 16:44:05.064051  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6319 16:44:05.067171  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6320 16:44:05.070516  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6321 16:44:05.076989  iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512

 6322 16:44:05.080448  iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496

 6323 16:44:05.083826  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6324 16:44:05.087348  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6325 16:44:05.093631  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6326 16:44:05.097106  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6327 16:44:05.100736  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6328 16:44:05.103379  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6329 16:44:05.110724  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6330 16:44:05.113548  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6331 16:44:05.116811  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6332 16:44:05.120373  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6333 16:44:05.120502  ==

 6334 16:44:05.123663  Dram Type= 6, Freq= 0, CH_0, rank 0

 6335 16:44:05.130411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6336 16:44:05.130519  ==

 6337 16:44:05.130588  DQS Delay:

 6338 16:44:05.133843  DQS0 = 35, DQS1 = 51

 6339 16:44:05.133956  DQM Delay:

 6340 16:44:05.137235  DQM0 = 6, DQM1 = 10

 6341 16:44:05.137327  DQ Delay:

 6342 16:44:05.140153  DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0

 6343 16:44:05.143779  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6344 16:44:05.143876  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6345 16:44:05.146741  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6346 16:44:05.150122  

 6347 16:44:05.150213  

 6348 16:44:05.150282  ==

 6349 16:44:05.153801  Dram Type= 6, Freq= 0, CH_0, rank 0

 6350 16:44:05.156659  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6351 16:44:05.156752  ==

 6352 16:44:05.156820  

 6353 16:44:05.156885  

 6354 16:44:05.160350  	TX Vref Scan disable

 6355 16:44:05.160474   == TX Byte 0 ==

 6356 16:44:05.163285  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6357 16:44:05.170287  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6358 16:44:05.170418   == TX Byte 1 ==

 6359 16:44:05.173292  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6360 16:44:05.179843  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6361 16:44:05.179929  ==

 6362 16:44:05.183152  Dram Type= 6, Freq= 0, CH_0, rank 0

 6363 16:44:05.186578  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6364 16:44:05.186689  ==

 6365 16:44:05.186784  

 6366 16:44:05.186912  

 6367 16:44:05.190186  	TX Vref Scan disable

 6368 16:44:05.190294   == TX Byte 0 ==

 6369 16:44:05.196768  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6370 16:44:05.199599  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6371 16:44:05.199700   == TX Byte 1 ==

 6372 16:44:05.206419  Update DQ  dly =572 (4 ,1, 28)  DQ  OEN =(3 ,2)

 6373 16:44:05.210124  Update DQM dly =572 (4 ,1, 28)  DQM OEN =(3 ,2)

 6374 16:44:05.210208  

 6375 16:44:05.210273  [DATLAT]

 6376 16:44:05.213456  Freq=400, CH0 RK0

 6377 16:44:05.213540  

 6378 16:44:05.213635  DATLAT Default: 0xf

 6379 16:44:05.216461  0, 0xFFFF, sum = 0

 6380 16:44:05.216546  1, 0xFFFF, sum = 0

 6381 16:44:05.219793  2, 0xFFFF, sum = 0

 6382 16:44:05.219903  3, 0xFFFF, sum = 0

 6383 16:44:05.223250  4, 0xFFFF, sum = 0

 6384 16:44:05.223361  5, 0xFFFF, sum = 0

 6385 16:44:05.226826  6, 0xFFFF, sum = 0

 6386 16:44:05.226937  7, 0xFFFF, sum = 0

 6387 16:44:05.229813  8, 0xFFFF, sum = 0

 6388 16:44:05.229898  9, 0xFFFF, sum = 0

 6389 16:44:05.233064  10, 0xFFFF, sum = 0

 6390 16:44:05.236625  11, 0xFFFF, sum = 0

 6391 16:44:05.236736  12, 0xFFFF, sum = 0

 6392 16:44:05.239970  13, 0x0, sum = 1

 6393 16:44:05.240060  14, 0x0, sum = 2

 6394 16:44:05.240182  15, 0x0, sum = 3

 6395 16:44:05.242866  16, 0x0, sum = 4

 6396 16:44:05.242950  best_step = 14

 6397 16:44:05.243016  

 6398 16:44:05.246491  ==

 6399 16:44:05.246575  Dram Type= 6, Freq= 0, CH_0, rank 0

 6400 16:44:05.252998  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6401 16:44:05.253108  ==

 6402 16:44:05.253176  RX Vref Scan: 1

 6403 16:44:05.253239  

 6404 16:44:05.256576  RX Vref 0 -> 0, step: 1

 6405 16:44:05.256659  

 6406 16:44:05.259565  RX Delay -343 -> 252, step: 8

 6407 16:44:05.259649  

 6408 16:44:05.263143  Set Vref, RX VrefLevel [Byte0]: 55

 6409 16:44:05.266162                           [Byte1]: 51

 6410 16:44:05.269852  

 6411 16:44:05.269937  Final RX Vref Byte 0 = 55 to rank0

 6412 16:44:05.273360  Final RX Vref Byte 1 = 51 to rank0

 6413 16:44:05.276381  Final RX Vref Byte 0 = 55 to rank1

 6414 16:44:05.279913  Final RX Vref Byte 1 = 51 to rank1==

 6415 16:44:05.282930  Dram Type= 6, Freq= 0, CH_0, rank 0

 6416 16:44:05.289999  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6417 16:44:05.290087  ==

 6418 16:44:05.290155  DQS Delay:

 6419 16:44:05.292877  DQS0 = 44, DQS1 = 56

 6420 16:44:05.292992  DQM Delay:

 6421 16:44:05.293086  DQM0 = 11, DQM1 = 11

 6422 16:44:05.296504  DQ Delay:

 6423 16:44:05.299407  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8

 6424 16:44:05.299520  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20

 6425 16:44:05.302880  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8

 6426 16:44:05.306179  DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =20

 6427 16:44:05.306302  

 6428 16:44:05.309653  

 6429 16:44:05.316063  [DQSOSCAuto] RK0, (LSB)MR18= 0x814e, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 393 ps

 6430 16:44:05.319337  CH0 RK0: MR19=C0C, MR18=814E

 6431 16:44:05.326254  CH0_RK0: MR19=0xC0C, MR18=0x814E, DQSOSC=393, MR23=63, INC=382, DEC=254

 6432 16:44:05.326368  ==

 6433 16:44:05.329390  Dram Type= 6, Freq= 0, CH_0, rank 1

 6434 16:44:05.332775  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6435 16:44:05.332860  ==

 6436 16:44:05.335942  [Gating] SW mode calibration

 6437 16:44:05.342763  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6438 16:44:05.349185  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6439 16:44:05.352752   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6440 16:44:05.356289   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6441 16:44:05.362755   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6442 16:44:05.365688   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6443 16:44:05.369345   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6444 16:44:05.375885   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6445 16:44:05.379536   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6446 16:44:05.382575   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6447 16:44:05.386254   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6448 16:44:05.389192  Total UI for P1: 0, mck2ui 16

 6449 16:44:05.392737  best dqsien dly found for B0: ( 0, 14, 24)

 6450 16:44:05.396205  Total UI for P1: 0, mck2ui 16

 6451 16:44:05.399181  best dqsien dly found for B1: ( 0, 14, 24)

 6452 16:44:05.402572  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6453 16:44:05.409177  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6454 16:44:05.409296  

 6455 16:44:05.412562  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6456 16:44:05.415552  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6457 16:44:05.419372  [Gating] SW calibration Done

 6458 16:44:05.419460  ==

 6459 16:44:05.422336  Dram Type= 6, Freq= 0, CH_0, rank 1

 6460 16:44:05.425819  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6461 16:44:05.425920  ==

 6462 16:44:05.429259  RX Vref Scan: 0

 6463 16:44:05.429331  

 6464 16:44:05.429392  RX Vref 0 -> 0, step: 1

 6465 16:44:05.429450  

 6466 16:44:05.432223  RX Delay -410 -> 252, step: 16

 6467 16:44:05.435638  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6468 16:44:05.442424  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6469 16:44:05.445864  iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496

 6470 16:44:05.449286  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6471 16:44:05.452245  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6472 16:44:05.458720  iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480

 6473 16:44:05.462251  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6474 16:44:05.465912  iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496

 6475 16:44:05.468930  iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496

 6476 16:44:05.475476  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6477 16:44:05.478980  iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496

 6478 16:44:05.481941  iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496

 6479 16:44:05.485678  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6480 16:44:05.492374  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6481 16:44:05.495281  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6482 16:44:05.498701  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6483 16:44:05.498787  ==

 6484 16:44:05.502281  Dram Type= 6, Freq= 0, CH_0, rank 1

 6485 16:44:05.508619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6486 16:44:05.508705  ==

 6487 16:44:05.508772  DQS Delay:

 6488 16:44:05.512166  DQS0 = 43, DQS1 = 51

 6489 16:44:05.512250  DQM Delay:

 6490 16:44:05.512317  DQM0 = 11, DQM1 = 10

 6491 16:44:05.515535  DQ Delay:

 6492 16:44:05.518730  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6493 16:44:05.518813  DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24

 6494 16:44:05.521682  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6495 16:44:05.525329  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6496 16:44:05.525413  

 6497 16:44:05.528693  

 6498 16:44:05.528776  ==

 6499 16:44:05.531767  Dram Type= 6, Freq= 0, CH_0, rank 1

 6500 16:44:05.535126  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6501 16:44:05.535212  ==

 6502 16:44:05.535280  

 6503 16:44:05.535342  

 6504 16:44:05.538593  	TX Vref Scan disable

 6505 16:44:05.538677   == TX Byte 0 ==

 6506 16:44:05.541640  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6507 16:44:05.548228  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6508 16:44:05.548313   == TX Byte 1 ==

 6509 16:44:05.551667  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6510 16:44:05.558439  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6511 16:44:05.558539  ==

 6512 16:44:05.561553  Dram Type= 6, Freq= 0, CH_0, rank 1

 6513 16:44:05.565019  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6514 16:44:05.565104  ==

 6515 16:44:05.565171  

 6516 16:44:05.565256  

 6517 16:44:05.568547  	TX Vref Scan disable

 6518 16:44:05.568631   == TX Byte 0 ==

 6519 16:44:05.571601  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6520 16:44:05.578145  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6521 16:44:05.578236   == TX Byte 1 ==

 6522 16:44:05.581708  Update DQ  dly =577 (4 ,2, 1)  DQ  OEN =(3 ,3)

 6523 16:44:05.588180  Update DQM dly =577 (4 ,2, 1)  DQM OEN =(3 ,3)

 6524 16:44:05.588262  

 6525 16:44:05.588325  [DATLAT]

 6526 16:44:05.588385  Freq=400, CH0 RK1

 6527 16:44:05.588443  

 6528 16:44:05.591746  DATLAT Default: 0xe

 6529 16:44:05.594733  0, 0xFFFF, sum = 0

 6530 16:44:05.594806  1, 0xFFFF, sum = 0

 6531 16:44:05.598254  2, 0xFFFF, sum = 0

 6532 16:44:05.598327  3, 0xFFFF, sum = 0

 6533 16:44:05.601539  4, 0xFFFF, sum = 0

 6534 16:44:05.601615  5, 0xFFFF, sum = 0

 6535 16:44:05.605010  6, 0xFFFF, sum = 0

 6536 16:44:05.605084  7, 0xFFFF, sum = 0

 6537 16:44:05.608002  8, 0xFFFF, sum = 0

 6538 16:44:05.608086  9, 0xFFFF, sum = 0

 6539 16:44:05.611545  10, 0xFFFF, sum = 0

 6540 16:44:05.611614  11, 0xFFFF, sum = 0

 6541 16:44:05.614707  12, 0xFFFF, sum = 0

 6542 16:44:05.614779  13, 0x0, sum = 1

 6543 16:44:05.617900  14, 0x0, sum = 2

 6544 16:44:05.617983  15, 0x0, sum = 3

 6545 16:44:05.621355  16, 0x0, sum = 4

 6546 16:44:05.621438  best_step = 14

 6547 16:44:05.621508  

 6548 16:44:05.621573  ==

 6549 16:44:05.624849  Dram Type= 6, Freq= 0, CH_0, rank 1

 6550 16:44:05.631187  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6551 16:44:05.631265  ==

 6552 16:44:05.631329  RX Vref Scan: 0

 6553 16:44:05.631389  

 6554 16:44:05.634484  RX Vref 0 -> 0, step: 1

 6555 16:44:05.634617  

 6556 16:44:05.637950  RX Delay -343 -> 252, step: 8

 6557 16:44:05.644205  iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488

 6558 16:44:05.647741  iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488

 6559 16:44:05.650978  iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480

 6560 16:44:05.654302  iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488

 6561 16:44:05.661072  iDelay=217, Bit 4, Center -40 (-279 ~ 200) 480

 6562 16:44:05.664233  iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480

 6563 16:44:05.667815  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6564 16:44:05.670807  iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488

 6565 16:44:05.677539  iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488

 6566 16:44:05.681036  iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488

 6567 16:44:05.683949  iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488

 6568 16:44:05.687648  iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480

 6569 16:44:05.694269  iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488

 6570 16:44:05.697851  iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480

 6571 16:44:05.700914  iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488

 6572 16:44:05.704152  iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488

 6573 16:44:05.707652  ==

 6574 16:44:05.710528  Dram Type= 6, Freq= 0, CH_0, rank 1

 6575 16:44:05.714196  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6576 16:44:05.714273  ==

 6577 16:44:05.714337  DQS Delay:

 6578 16:44:05.717188  DQS0 = 48, DQS1 = 60

 6579 16:44:05.717262  DQM Delay:

 6580 16:44:05.720609  DQM0 = 11, DQM1 = 14

 6581 16:44:05.720680  DQ Delay:

 6582 16:44:05.724384  DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12

 6583 16:44:05.727506  DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =20

 6584 16:44:05.730436  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4

 6585 16:44:05.733931  DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =24

 6586 16:44:05.734033  

 6587 16:44:05.734128  

 6588 16:44:05.740923  [DQSOSCAuto] RK1, (LSB)MR18= 0x9163, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps

 6589 16:44:05.744345  CH0 RK1: MR19=C0C, MR18=9163

 6590 16:44:05.750393  CH0_RK1: MR19=0xC0C, MR18=0x9163, DQSOSC=391, MR23=63, INC=386, DEC=257

 6591 16:44:05.753818  [RxdqsGatingPostProcess] freq 400

 6592 16:44:05.757187  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6593 16:44:05.760593  best DQS0 dly(2T, 0.5T) = (0, 10)

 6594 16:44:05.763740  best DQS1 dly(2T, 0.5T) = (0, 10)

 6595 16:44:05.767069  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6596 16:44:05.770360  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6597 16:44:05.773918  best DQS0 dly(2T, 0.5T) = (0, 10)

 6598 16:44:05.777516  best DQS1 dly(2T, 0.5T) = (0, 10)

 6599 16:44:05.780481  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6600 16:44:05.784153  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6601 16:44:05.787152  Pre-setting of DQS Precalculation

 6602 16:44:05.790754  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6603 16:44:05.790827  ==

 6604 16:44:05.793748  Dram Type= 6, Freq= 0, CH_1, rank 0

 6605 16:44:05.800435  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6606 16:44:05.800518  ==

 6607 16:44:05.804167  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6608 16:44:05.810651  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6609 16:44:05.813995  [CA 0] Center 36 (8~64) winsize 57

 6610 16:44:05.816929  [CA 1] Center 36 (8~64) winsize 57

 6611 16:44:05.820709  [CA 2] Center 36 (8~64) winsize 57

 6612 16:44:05.824120  [CA 3] Center 36 (8~64) winsize 57

 6613 16:44:05.826990  [CA 4] Center 36 (8~64) winsize 57

 6614 16:44:05.830503  [CA 5] Center 36 (8~64) winsize 57

 6615 16:44:05.830581  

 6616 16:44:05.833423  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6617 16:44:05.833495  

 6618 16:44:05.837026  [CATrainingPosCal] consider 1 rank data

 6619 16:44:05.840443  u2DelayCellTimex100 = 270/100 ps

 6620 16:44:05.843315  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6621 16:44:05.846755  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6622 16:44:05.850200  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6623 16:44:05.853511  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6624 16:44:05.856877  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6625 16:44:05.863534  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6626 16:44:05.863613  

 6627 16:44:05.866662  CA PerBit enable=1, Macro0, CA PI delay=36

 6628 16:44:05.866734  

 6629 16:44:05.869899  [CBTSetCACLKResult] CA Dly = 36

 6630 16:44:05.869980  CS Dly: 1 (0~32)

 6631 16:44:05.870049  ==

 6632 16:44:05.873163  Dram Type= 6, Freq= 0, CH_1, rank 1

 6633 16:44:05.876943  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6634 16:44:05.880337  ==

 6635 16:44:05.883511  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6636 16:44:05.889924  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6637 16:44:05.893527  [CA 0] Center 36 (8~64) winsize 57

 6638 16:44:05.896628  [CA 1] Center 36 (8~64) winsize 57

 6639 16:44:05.899667  [CA 2] Center 36 (8~64) winsize 57

 6640 16:44:05.903276  [CA 3] Center 36 (8~64) winsize 57

 6641 16:44:05.906341  [CA 4] Center 36 (8~64) winsize 57

 6642 16:44:05.909849  [CA 5] Center 36 (8~64) winsize 57

 6643 16:44:05.909932  

 6644 16:44:05.913396  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6645 16:44:05.913480  

 6646 16:44:05.916688  [CATrainingPosCal] consider 2 rank data

 6647 16:44:05.919715  u2DelayCellTimex100 = 270/100 ps

 6648 16:44:05.923291  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6649 16:44:05.926223  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6650 16:44:05.929823  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6651 16:44:05.933291  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6652 16:44:05.936284  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6653 16:44:05.939799  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6654 16:44:05.939881  

 6655 16:44:05.946365  CA PerBit enable=1, Macro0, CA PI delay=36

 6656 16:44:05.946451  

 6657 16:44:05.946561  [CBTSetCACLKResult] CA Dly = 36

 6658 16:44:05.949998  CS Dly: 1 (0~32)

 6659 16:44:05.950081  

 6660 16:44:05.952966  ----->DramcWriteLeveling(PI) begin...

 6661 16:44:05.953049  ==

 6662 16:44:05.956436  Dram Type= 6, Freq= 0, CH_1, rank 0

 6663 16:44:05.959843  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6664 16:44:05.959942  ==

 6665 16:44:05.962784  Write leveling (Byte 0): 40 => 8

 6666 16:44:05.966342  Write leveling (Byte 1): 40 => 8

 6667 16:44:05.969283  DramcWriteLeveling(PI) end<-----

 6668 16:44:05.969388  

 6669 16:44:05.969484  ==

 6670 16:44:05.973223  Dram Type= 6, Freq= 0, CH_1, rank 0

 6671 16:44:05.976408  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6672 16:44:05.976509  ==

 6673 16:44:05.979751  [Gating] SW mode calibration

 6674 16:44:05.986040  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6675 16:44:05.992606  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6676 16:44:05.996207   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 6677 16:44:06.002970   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6678 16:44:06.005937   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6679 16:44:06.009703   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6680 16:44:06.016157   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6681 16:44:06.019207   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6682 16:44:06.022393   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6683 16:44:06.029405   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6684 16:44:06.032492   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6685 16:44:06.035861  Total UI for P1: 0, mck2ui 16

 6686 16:44:06.039415  best dqsien dly found for B0: ( 0, 14, 24)

 6687 16:44:06.042296  Total UI for P1: 0, mck2ui 16

 6688 16:44:06.045742  best dqsien dly found for B1: ( 0, 14, 24)

 6689 16:44:06.049405  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6690 16:44:06.052216  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6691 16:44:06.052299  

 6692 16:44:06.055859  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6693 16:44:06.059379  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6694 16:44:06.062277  [Gating] SW calibration Done

 6695 16:44:06.062360  ==

 6696 16:44:06.065862  Dram Type= 6, Freq= 0, CH_1, rank 0

 6697 16:44:06.068903  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6698 16:44:06.072177  ==

 6699 16:44:06.072261  RX Vref Scan: 0

 6700 16:44:06.072327  

 6701 16:44:06.075475  RX Vref 0 -> 0, step: 1

 6702 16:44:06.075557  

 6703 16:44:06.078898  RX Delay -410 -> 252, step: 16

 6704 16:44:06.082182  iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480

 6705 16:44:06.085609  iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496

 6706 16:44:06.089054  iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496

 6707 16:44:06.095314  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6708 16:44:06.098858  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6709 16:44:06.101939  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6710 16:44:06.105532  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6711 16:44:06.112238  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6712 16:44:06.115615  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6713 16:44:06.118547  iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512

 6714 16:44:06.122145  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6715 16:44:06.128494  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6716 16:44:06.132157  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6717 16:44:06.135073  iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496

 6718 16:44:06.142114  iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496

 6719 16:44:06.145416  iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496

 6720 16:44:06.145500  ==

 6721 16:44:06.148357  Dram Type= 6, Freq= 0, CH_1, rank 0

 6722 16:44:06.151838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6723 16:44:06.151971  ==

 6724 16:44:06.154948  DQS Delay:

 6725 16:44:06.155055  DQS0 = 51, DQS1 = 59

 6726 16:44:06.155148  DQM Delay:

 6727 16:44:06.158342  DQM0 = 19, DQM1 = 16

 6728 16:44:06.158428  DQ Delay:

 6729 16:44:06.161828  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6730 16:44:06.165439  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6731 16:44:06.168954  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16

 6732 16:44:06.171964  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6733 16:44:06.172049  

 6734 16:44:06.172144  

 6735 16:44:06.172204  ==

 6736 16:44:06.175547  Dram Type= 6, Freq= 0, CH_1, rank 0

 6737 16:44:06.178508  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6738 16:44:06.181951  ==

 6739 16:44:06.182034  

 6740 16:44:06.182131  

 6741 16:44:06.182194  	TX Vref Scan disable

 6742 16:44:06.185415   == TX Byte 0 ==

 6743 16:44:06.188774  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6744 16:44:06.192143  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6745 16:44:06.195519   == TX Byte 1 ==

 6746 16:44:06.198578  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6747 16:44:06.202304  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6748 16:44:06.202388  ==

 6749 16:44:06.205164  Dram Type= 6, Freq= 0, CH_1, rank 0

 6750 16:44:06.208291  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6751 16:44:06.211801  ==

 6752 16:44:06.211883  

 6753 16:44:06.211949  

 6754 16:44:06.212048  	TX Vref Scan disable

 6755 16:44:06.215404   == TX Byte 0 ==

 6756 16:44:06.218396  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6757 16:44:06.221996  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6758 16:44:06.225433   == TX Byte 1 ==

 6759 16:44:06.228769  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6760 16:44:06.231486  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6761 16:44:06.231565  

 6762 16:44:06.235384  [DATLAT]

 6763 16:44:06.235468  Freq=400, CH1 RK0

 6764 16:44:06.235534  

 6765 16:44:06.238765  DATLAT Default: 0xf

 6766 16:44:06.238882  0, 0xFFFF, sum = 0

 6767 16:44:06.241805  1, 0xFFFF, sum = 0

 6768 16:44:06.241890  2, 0xFFFF, sum = 0

 6769 16:44:06.245155  3, 0xFFFF, sum = 0

 6770 16:44:06.245271  4, 0xFFFF, sum = 0

 6771 16:44:06.248351  5, 0xFFFF, sum = 0

 6772 16:44:06.248436  6, 0xFFFF, sum = 0

 6773 16:44:06.251763  7, 0xFFFF, sum = 0

 6774 16:44:06.251847  8, 0xFFFF, sum = 0

 6775 16:44:06.255325  9, 0xFFFF, sum = 0

 6776 16:44:06.255409  10, 0xFFFF, sum = 0

 6777 16:44:06.258409  11, 0xFFFF, sum = 0

 6778 16:44:06.258493  12, 0xFFFF, sum = 0

 6779 16:44:06.261498  13, 0x0, sum = 1

 6780 16:44:06.261582  14, 0x0, sum = 2

 6781 16:44:06.265154  15, 0x0, sum = 3

 6782 16:44:06.265238  16, 0x0, sum = 4

 6783 16:44:06.268637  best_step = 14

 6784 16:44:06.268726  

 6785 16:44:06.268791  ==

 6786 16:44:06.271589  Dram Type= 6, Freq= 0, CH_1, rank 0

 6787 16:44:06.275099  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6788 16:44:06.275183  ==

 6789 16:44:06.278166  RX Vref Scan: 1

 6790 16:44:06.278250  

 6791 16:44:06.278315  RX Vref 0 -> 0, step: 1

 6792 16:44:06.278377  

 6793 16:44:06.281660  RX Delay -359 -> 252, step: 8

 6794 16:44:06.281744  

 6795 16:44:06.284999  Set Vref, RX VrefLevel [Byte0]: 59

 6796 16:44:06.288384                           [Byte1]: 53

 6797 16:44:06.292944  

 6798 16:44:06.293029  Final RX Vref Byte 0 = 59 to rank0

 6799 16:44:06.296431  Final RX Vref Byte 1 = 53 to rank0

 6800 16:44:06.299607  Final RX Vref Byte 0 = 59 to rank1

 6801 16:44:06.302743  Final RX Vref Byte 1 = 53 to rank1==

 6802 16:44:06.306395  Dram Type= 6, Freq= 0, CH_1, rank 0

 6803 16:44:06.312852  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6804 16:44:06.312943  ==

 6805 16:44:06.313008  DQS Delay:

 6806 16:44:06.315864  DQS0 = 48, DQS1 = 64

 6807 16:44:06.315984  DQM Delay:

 6808 16:44:06.316063  DQM0 = 12, DQM1 = 16

 6809 16:44:06.319491  DQ Delay:

 6810 16:44:06.323183  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6811 16:44:06.323283  DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12

 6812 16:44:06.326187  DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =16

 6813 16:44:06.329123  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24

 6814 16:44:06.332532  

 6815 16:44:06.332612  

 6816 16:44:06.339213  [DQSOSCAuto] RK0, (LSB)MR18= 0x872f, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps

 6817 16:44:06.342671  CH1 RK0: MR19=C0C, MR18=872F

 6818 16:44:06.349233  CH1_RK0: MR19=0xC0C, MR18=0x872F, DQSOSC=392, MR23=63, INC=384, DEC=256

 6819 16:44:06.349314  ==

 6820 16:44:06.352556  Dram Type= 6, Freq= 0, CH_1, rank 1

 6821 16:44:06.356085  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6822 16:44:06.356165  ==

 6823 16:44:06.359116  [Gating] SW mode calibration

 6824 16:44:06.365586  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6825 16:44:06.372626  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6826 16:44:06.375663   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 6827 16:44:06.379053   0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 6828 16:44:06.385463   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6829 16:44:06.389081   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6830 16:44:06.392265   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6831 16:44:06.398852   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6832 16:44:06.402225   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6833 16:44:06.405581   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6834 16:44:06.412298   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6835 16:44:06.412380  Total UI for P1: 0, mck2ui 16

 6836 16:44:06.418914  best dqsien dly found for B0: ( 0, 14, 24)

 6837 16:44:06.418994  Total UI for P1: 0, mck2ui 16

 6838 16:44:06.421896  best dqsien dly found for B1: ( 0, 14, 24)

 6839 16:44:06.428383  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6840 16:44:06.431936  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6841 16:44:06.432078  

 6842 16:44:06.435382  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6843 16:44:06.438207  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6844 16:44:06.441724  [Gating] SW calibration Done

 6845 16:44:06.441824  ==

 6846 16:44:06.445327  Dram Type= 6, Freq= 0, CH_1, rank 1

 6847 16:44:06.448240  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6848 16:44:06.448316  ==

 6849 16:44:06.451775  RX Vref Scan: 0

 6850 16:44:06.451884  

 6851 16:44:06.452020  RX Vref 0 -> 0, step: 1

 6852 16:44:06.452113  

 6853 16:44:06.455154  RX Delay -410 -> 252, step: 16

 6854 16:44:06.462056  iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496

 6855 16:44:06.465045  iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512

 6856 16:44:06.468548  iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512

 6857 16:44:06.471630  iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496

 6858 16:44:06.478719  iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496

 6859 16:44:06.481918  iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496

 6860 16:44:06.484682  iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496

 6861 16:44:06.487951  iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496

 6862 16:44:06.494718  iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512

 6863 16:44:06.498236  iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496

 6864 16:44:06.501609  iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512

 6865 16:44:06.505126  iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512

 6866 16:44:06.511349  iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496

 6867 16:44:06.514965  iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512

 6868 16:44:06.518050  iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512

 6869 16:44:06.521549  iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512

 6870 16:44:06.524572  ==

 6871 16:44:06.528214  Dram Type= 6, Freq= 0, CH_1, rank 1

 6872 16:44:06.531135  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6873 16:44:06.531241  ==

 6874 16:44:06.531336  DQS Delay:

 6875 16:44:06.534803  DQS0 = 43, DQS1 = 59

 6876 16:44:06.534906  DQM Delay:

 6877 16:44:06.537688  DQM0 = 10, DQM1 = 20

 6878 16:44:06.537807  DQ Delay:

 6879 16:44:06.541264  DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8

 6880 16:44:06.544452  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6881 16:44:06.548081  DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16

 6882 16:44:06.550874  DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32

 6883 16:44:06.550988  

 6884 16:44:06.551082  

 6885 16:44:06.551146  ==

 6886 16:44:06.554554  Dram Type= 6, Freq= 0, CH_1, rank 1

 6887 16:44:06.557427  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6888 16:44:06.557507  ==

 6889 16:44:06.557572  

 6890 16:44:06.557633  

 6891 16:44:06.560945  	TX Vref Scan disable

 6892 16:44:06.561027   == TX Byte 0 ==

 6893 16:44:06.567340  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6894 16:44:06.570902  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6895 16:44:06.571012   == TX Byte 1 ==

 6896 16:44:06.577452  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6897 16:44:06.581115  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6898 16:44:06.581223  ==

 6899 16:44:06.583967  Dram Type= 6, Freq= 0, CH_1, rank 1

 6900 16:44:06.587378  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6901 16:44:06.587460  ==

 6902 16:44:06.587524  

 6903 16:44:06.587593  

 6904 16:44:06.590939  	TX Vref Scan disable

 6905 16:44:06.591039   == TX Byte 0 ==

 6906 16:44:06.597346  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6907 16:44:06.600852  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6908 16:44:06.600931   == TX Byte 1 ==

 6909 16:44:06.607234  Update DQ  dly =581 (4 ,2, 5)  DQ  OEN =(3 ,3)

 6910 16:44:06.610822  Update DQM dly =581 (4 ,2, 5)  DQM OEN =(3 ,3)

 6911 16:44:06.610910  

 6912 16:44:06.610984  [DATLAT]

 6913 16:44:06.614192  Freq=400, CH1 RK1

 6914 16:44:06.614284  

 6915 16:44:06.614351  DATLAT Default: 0xe

 6916 16:44:06.617120  0, 0xFFFF, sum = 0

 6917 16:44:06.617206  1, 0xFFFF, sum = 0

 6918 16:44:06.620708  2, 0xFFFF, sum = 0

 6919 16:44:06.620789  3, 0xFFFF, sum = 0

 6920 16:44:06.624284  4, 0xFFFF, sum = 0

 6921 16:44:06.624369  5, 0xFFFF, sum = 0

 6922 16:44:06.627234  6, 0xFFFF, sum = 0

 6923 16:44:06.627319  7, 0xFFFF, sum = 0

 6924 16:44:06.630726  8, 0xFFFF, sum = 0

 6925 16:44:06.630837  9, 0xFFFF, sum = 0

 6926 16:44:06.633671  10, 0xFFFF, sum = 0

 6927 16:44:06.637149  11, 0xFFFF, sum = 0

 6928 16:44:06.637228  12, 0xFFFF, sum = 0

 6929 16:44:06.640120  13, 0x0, sum = 1

 6930 16:44:06.640197  14, 0x0, sum = 2

 6931 16:44:06.643808  15, 0x0, sum = 3

 6932 16:44:06.643882  16, 0x0, sum = 4

 6933 16:44:06.643944  best_step = 14

 6934 16:44:06.646650  

 6935 16:44:06.646733  ==

 6936 16:44:06.650097  Dram Type= 6, Freq= 0, CH_1, rank 1

 6937 16:44:06.653507  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6938 16:44:06.653654  ==

 6939 16:44:06.653755  RX Vref Scan: 0

 6940 16:44:06.653858  

 6941 16:44:06.656985  RX Vref 0 -> 0, step: 1

 6942 16:44:06.657070  

 6943 16:44:06.659818  RX Delay -359 -> 252, step: 8

 6944 16:44:06.667554  iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488

 6945 16:44:06.670260  iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488

 6946 16:44:06.674103  iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488

 6947 16:44:06.680665  iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496

 6948 16:44:06.684176  iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488

 6949 16:44:06.687357  iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488

 6950 16:44:06.690743  iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488

 6951 16:44:06.697101  iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488

 6952 16:44:06.700543  iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504

 6953 16:44:06.704116  iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496

 6954 16:44:06.707547  iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496

 6955 16:44:06.713805  iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496

 6956 16:44:06.716712  iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480

 6957 16:44:06.720174  iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496

 6958 16:44:06.723715  iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496

 6959 16:44:06.730277  iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496

 6960 16:44:06.730381  ==

 6961 16:44:06.733354  Dram Type= 6, Freq= 0, CH_1, rank 1

 6962 16:44:06.736838  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6963 16:44:06.736918  ==

 6964 16:44:06.736983  DQS Delay:

 6965 16:44:06.740338  DQS0 = 52, DQS1 = 60

 6966 16:44:06.740410  DQM Delay:

 6967 16:44:06.743414  DQM0 = 13, DQM1 = 12

 6968 16:44:06.743484  DQ Delay:

 6969 16:44:06.746944  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6970 16:44:06.749844  DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8

 6971 16:44:06.753117  DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4

 6972 16:44:06.756662  DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20

 6973 16:44:06.756764  

 6974 16:44:06.756854  

 6975 16:44:06.763134  [DQSOSCAuto] RK1, (LSB)MR18= 0x768d, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 394 ps

 6976 16:44:06.766710  CH1 RK1: MR19=C0C, MR18=768D

 6977 16:44:06.772783  CH1_RK1: MR19=0xC0C, MR18=0x768D, DQSOSC=392, MR23=63, INC=384, DEC=256

 6978 16:44:06.776189  [RxdqsGatingPostProcess] freq 400

 6979 16:44:06.782761  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6980 16:44:06.786263  best DQS0 dly(2T, 0.5T) = (0, 10)

 6981 16:44:06.789194  best DQS1 dly(2T, 0.5T) = (0, 10)

 6982 16:44:06.792805  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6983 16:44:06.795796  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6984 16:44:06.799113  best DQS0 dly(2T, 0.5T) = (0, 10)

 6985 16:44:06.799216  best DQS1 dly(2T, 0.5T) = (0, 10)

 6986 16:44:06.802747  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6987 16:44:06.806024  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6988 16:44:06.809078  Pre-setting of DQS Precalculation

 6989 16:44:06.815842  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6990 16:44:06.822690  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6991 16:44:06.829211  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6992 16:44:06.829301  

 6993 16:44:06.829368  

 6994 16:44:06.832236  [Calibration Summary] 800 Mbps

 6995 16:44:06.832346  CH 0, Rank 0

 6996 16:44:06.835530  SW Impedance     : PASS

 6997 16:44:06.839148  DUTY Scan        : NO K

 6998 16:44:06.839232  ZQ Calibration   : PASS

 6999 16:44:06.842650  Jitter Meter     : NO K

 7000 16:44:06.845614  CBT Training     : PASS

 7001 16:44:06.845744  Write leveling   : PASS

 7002 16:44:06.849126  RX DQS gating    : PASS

 7003 16:44:06.852220  RX DQ/DQS(RDDQC) : PASS

 7004 16:44:06.852303  TX DQ/DQS        : PASS

 7005 16:44:06.855750  RX DATLAT        : PASS

 7006 16:44:06.859138  RX DQ/DQS(Engine): PASS

 7007 16:44:06.859221  TX OE            : NO K

 7008 16:44:06.862632  All Pass.

 7009 16:44:06.862721  

 7010 16:44:06.862787  CH 0, Rank 1

 7011 16:44:06.866057  SW Impedance     : PASS

 7012 16:44:06.866156  DUTY Scan        : NO K

 7013 16:44:06.869111  ZQ Calibration   : PASS

 7014 16:44:06.872110  Jitter Meter     : NO K

 7015 16:44:06.872195  CBT Training     : PASS

 7016 16:44:06.875668  Write leveling   : NO K

 7017 16:44:06.875777  RX DQS gating    : PASS

 7018 16:44:06.879126  RX DQ/DQS(RDDQC) : PASS

 7019 16:44:06.882685  TX DQ/DQS        : PASS

 7020 16:44:06.882791  RX DATLAT        : PASS

 7021 16:44:06.885628  RX DQ/DQS(Engine): PASS

 7022 16:44:06.889199  TX OE            : NO K

 7023 16:44:06.889313  All Pass.

 7024 16:44:06.889410  

 7025 16:44:06.889500  CH 1, Rank 0

 7026 16:44:06.892083  SW Impedance     : PASS

 7027 16:44:06.895567  DUTY Scan        : NO K

 7028 16:44:06.895690  ZQ Calibration   : PASS

 7029 16:44:06.898697  Jitter Meter     : NO K

 7030 16:44:06.902210  CBT Training     : PASS

 7031 16:44:06.902326  Write leveling   : PASS

 7032 16:44:06.905637  RX DQS gating    : PASS

 7033 16:44:06.908729  RX DQ/DQS(RDDQC) : PASS

 7034 16:44:06.908812  TX DQ/DQS        : PASS

 7035 16:44:06.911994  RX DATLAT        : PASS

 7036 16:44:06.915481  RX DQ/DQS(Engine): PASS

 7037 16:44:06.915596  TX OE            : NO K

 7038 16:44:06.918801  All Pass.

 7039 16:44:06.918903  

 7040 16:44:06.918986  CH 1, Rank 1

 7041 16:44:06.922170  SW Impedance     : PASS

 7042 16:44:06.922273  DUTY Scan        : NO K

 7043 16:44:06.925598  ZQ Calibration   : PASS

 7044 16:44:06.928684  Jitter Meter     : NO K

 7045 16:44:06.928772  CBT Training     : PASS

 7046 16:44:06.932257  Write leveling   : NO K

 7047 16:44:06.932341  RX DQS gating    : PASS

 7048 16:44:06.935759  RX DQ/DQS(RDDQC) : PASS

 7049 16:44:06.938858  TX DQ/DQS        : PASS

 7050 16:44:06.938950  RX DATLAT        : PASS

 7051 16:44:06.942373  RX DQ/DQS(Engine): PASS

 7052 16:44:06.945252  TX OE            : NO K

 7053 16:44:06.945335  All Pass.

 7054 16:44:06.945401  

 7055 16:44:06.948800  DramC Write-DBI off

 7056 16:44:06.948883  	PER_BANK_REFRESH: Hybrid Mode

 7057 16:44:06.951882  TX_TRACKING: ON

 7058 16:44:06.962078  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7059 16:44:06.965470  [FAST_K] Save calibration result to emmc

 7060 16:44:06.968843  dramc_set_vcore_voltage set vcore to 725000

 7061 16:44:06.968948  Read voltage for 1600, 0

 7062 16:44:06.971877  Vio18 = 0

 7063 16:44:06.971985  Vcore = 725000

 7064 16:44:06.972066  Vdram = 0

 7065 16:44:06.975353  Vddq = 0

 7066 16:44:06.975436  Vmddr = 0

 7067 16:44:06.981904  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7068 16:44:06.985012  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7069 16:44:06.988585  MEM_TYPE=3, freq_sel=13

 7070 16:44:06.991499  sv_algorithm_assistance_LP4_3733 

 7071 16:44:06.995094  ============ PULL DRAM RESETB DOWN ============

 7072 16:44:06.998205  ========== PULL DRAM RESETB DOWN end =========

 7073 16:44:07.004749  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7074 16:44:07.008268  =================================== 

 7075 16:44:07.008363  LPDDR4 DRAM CONFIGURATION

 7076 16:44:07.011308  =================================== 

 7077 16:44:07.014840  EX_ROW_EN[0]    = 0x0

 7078 16:44:07.018261  EX_ROW_EN[1]    = 0x0

 7079 16:44:07.018347  LP4Y_EN      = 0x0

 7080 16:44:07.021728  WORK_FSP     = 0x1

 7081 16:44:07.021815  WL           = 0x5

 7082 16:44:07.024973  RL           = 0x5

 7083 16:44:07.025054  BL           = 0x2

 7084 16:44:07.028228  RPST         = 0x0

 7085 16:44:07.028309  RD_PRE       = 0x0

 7086 16:44:07.031191  WR_PRE       = 0x1

 7087 16:44:07.031272  WR_PST       = 0x1

 7088 16:44:07.034678  DBI_WR       = 0x0

 7089 16:44:07.034751  DBI_RD       = 0x0

 7090 16:44:07.037769  OTF          = 0x1

 7091 16:44:07.041416  =================================== 

 7092 16:44:07.044302  =================================== 

 7093 16:44:07.044412  ANA top config

 7094 16:44:07.047934  =================================== 

 7095 16:44:07.051046  DLL_ASYNC_EN            =  0

 7096 16:44:07.054547  ALL_SLAVE_EN            =  0

 7097 16:44:07.057582  NEW_RANK_MODE           =  1

 7098 16:44:07.057719  DLL_IDLE_MODE           =  1

 7099 16:44:07.061075  LP45_APHY_COMB_EN       =  1

 7100 16:44:07.064412  TX_ODT_DIS              =  0

 7101 16:44:07.068040  NEW_8X_MODE             =  1

 7102 16:44:07.070788  =================================== 

 7103 16:44:07.074211  =================================== 

 7104 16:44:07.077836  data_rate                  = 3200

 7105 16:44:07.077941  CKR                        = 1

 7106 16:44:07.080815  DQ_P2S_RATIO               = 8

 7107 16:44:07.084438  =================================== 

 7108 16:44:07.087318  CA_P2S_RATIO               = 8

 7109 16:44:07.090875  DQ_CA_OPEN                 = 0

 7110 16:44:07.094444  DQ_SEMI_OPEN               = 0

 7111 16:44:07.097465  CA_SEMI_OPEN               = 0

 7112 16:44:07.097564  CA_FULL_RATE               = 0

 7113 16:44:07.101111  DQ_CKDIV4_EN               = 0

 7114 16:44:07.104575  CA_CKDIV4_EN               = 0

 7115 16:44:07.107471  CA_PREDIV_EN               = 0

 7116 16:44:07.110908  PH8_DLY                    = 12

 7117 16:44:07.114247  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7118 16:44:07.114355  DQ_AAMCK_DIV               = 4

 7119 16:44:07.117893  CA_AAMCK_DIV               = 4

 7120 16:44:07.120725  CA_ADMCK_DIV               = 4

 7121 16:44:07.124206  DQ_TRACK_CA_EN             = 0

 7122 16:44:07.127585  CA_PICK                    = 1600

 7123 16:44:07.131044  CA_MCKIO                   = 1600

 7124 16:44:07.131148  MCKIO_SEMI                 = 0

 7125 16:44:07.134465  PLL_FREQ                   = 3068

 7126 16:44:07.137433  DQ_UI_PI_RATIO             = 32

 7127 16:44:07.141075  CA_UI_PI_RATIO             = 0

 7128 16:44:07.144020  =================================== 

 7129 16:44:07.147499  =================================== 

 7130 16:44:07.151142  memory_type:LPDDR4         

 7131 16:44:07.151246  GP_NUM     : 10       

 7132 16:44:07.154058  SRAM_EN    : 1       

 7133 16:44:07.157752  MD32_EN    : 0       

 7134 16:44:07.160714  =================================== 

 7135 16:44:07.160804  [ANA_INIT] >>>>>>>>>>>>>> 

 7136 16:44:07.164408  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7137 16:44:07.167277  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7138 16:44:07.170655  =================================== 

 7139 16:44:07.174032  data_rate = 3200,PCW = 0X7600

 7140 16:44:07.177386  =================================== 

 7141 16:44:07.181018  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7142 16:44:07.187602  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7143 16:44:07.191130  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7144 16:44:07.197573  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7145 16:44:07.200597  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7146 16:44:07.204162  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7147 16:44:07.204264  [ANA_INIT] flow start 

 7148 16:44:07.207113  [ANA_INIT] PLL >>>>>>>> 

 7149 16:44:07.210646  [ANA_INIT] PLL <<<<<<<< 

 7150 16:44:07.210755  [ANA_INIT] MIDPI >>>>>>>> 

 7151 16:44:07.213666  [ANA_INIT] MIDPI <<<<<<<< 

 7152 16:44:07.217135  [ANA_INIT] DLL >>>>>>>> 

 7153 16:44:07.220587  [ANA_INIT] DLL <<<<<<<< 

 7154 16:44:07.220716  [ANA_INIT] flow end 

 7155 16:44:07.223851  ============ LP4 DIFF to SE enter ============

 7156 16:44:07.230752  ============ LP4 DIFF to SE exit  ============

 7157 16:44:07.230882  [ANA_INIT] <<<<<<<<<<<<< 

 7158 16:44:07.234122  [Flow] Enable top DCM control >>>>> 

 7159 16:44:07.236933  [Flow] Enable top DCM control <<<<< 

 7160 16:44:07.240771  Enable DLL master slave shuffle 

 7161 16:44:07.247354  ============================================================== 

 7162 16:44:07.247481  Gating Mode config

 7163 16:44:07.253847  ============================================================== 

 7164 16:44:07.257574  Config description: 

 7165 16:44:07.266983  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7166 16:44:07.273959  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7167 16:44:07.277244  SELPH_MODE            0: By rank         1: By Phase 

 7168 16:44:07.283982  ============================================================== 

 7169 16:44:07.286831  GAT_TRACK_EN                 =  1

 7170 16:44:07.286931  RX_GATING_MODE               =  2

 7171 16:44:07.290568  RX_GATING_TRACK_MODE         =  2

 7172 16:44:07.293438  SELPH_MODE                   =  1

 7173 16:44:07.297038  PICG_EARLY_EN                =  1

 7174 16:44:07.300143  VALID_LAT_VALUE              =  1

 7175 16:44:07.306693  ============================================================== 

 7176 16:44:07.310200  Enter into Gating configuration >>>> 

 7177 16:44:07.313933  Exit from Gating configuration <<<< 

 7178 16:44:07.316827  Enter into  DVFS_PRE_config >>>>> 

 7179 16:44:07.326752  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7180 16:44:07.329764  Exit from  DVFS_PRE_config <<<<< 

 7181 16:44:07.333673  Enter into PICG configuration >>>> 

 7182 16:44:07.336576  Exit from PICG configuration <<<< 

 7183 16:44:07.339864  [RX_INPUT] configuration >>>>> 

 7184 16:44:07.343239  [RX_INPUT] configuration <<<<< 

 7185 16:44:07.346637  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7186 16:44:07.353607  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7187 16:44:07.360208  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7188 16:44:07.363057  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7189 16:44:07.369770  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7190 16:44:07.376796  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7191 16:44:07.380102  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7192 16:44:07.386700  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7193 16:44:07.389646  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7194 16:44:07.393258  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7195 16:44:07.396273  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7196 16:44:07.403259  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7197 16:44:07.406265  =================================== 

 7198 16:44:07.406351  LPDDR4 DRAM CONFIGURATION

 7199 16:44:07.409615  =================================== 

 7200 16:44:07.413250  EX_ROW_EN[0]    = 0x0

 7201 16:44:07.416119  EX_ROW_EN[1]    = 0x0

 7202 16:44:07.416202  LP4Y_EN      = 0x0

 7203 16:44:07.419806  WORK_FSP     = 0x1

 7204 16:44:07.419889  WL           = 0x5

 7205 16:44:07.423136  RL           = 0x5

 7206 16:44:07.423220  BL           = 0x2

 7207 16:44:07.426151  RPST         = 0x0

 7208 16:44:07.426235  RD_PRE       = 0x0

 7209 16:44:07.429824  WR_PRE       = 0x1

 7210 16:44:07.429908  WR_PST       = 0x1

 7211 16:44:07.433246  DBI_WR       = 0x0

 7212 16:44:07.433330  DBI_RD       = 0x0

 7213 16:44:07.436197  OTF          = 0x1

 7214 16:44:07.439489  =================================== 

 7215 16:44:07.442919  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7216 16:44:07.446370  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7217 16:44:07.452641  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7218 16:44:07.455978  =================================== 

 7219 16:44:07.456078  LPDDR4 DRAM CONFIGURATION

 7220 16:44:07.459695  =================================== 

 7221 16:44:07.463152  EX_ROW_EN[0]    = 0x10

 7222 16:44:07.466056  EX_ROW_EN[1]    = 0x0

 7223 16:44:07.466141  LP4Y_EN      = 0x0

 7224 16:44:07.469575  WORK_FSP     = 0x1

 7225 16:44:07.469660  WL           = 0x5

 7226 16:44:07.472684  RL           = 0x5

 7227 16:44:07.472770  BL           = 0x2

 7228 16:44:07.476303  RPST         = 0x0

 7229 16:44:07.476387  RD_PRE       = 0x0

 7230 16:44:07.479195  WR_PRE       = 0x1

 7231 16:44:07.479281  WR_PST       = 0x1

 7232 16:44:07.482595  DBI_WR       = 0x0

 7233 16:44:07.482681  DBI_RD       = 0x0

 7234 16:44:07.485893  OTF          = 0x1

 7235 16:44:07.489096  =================================== 

 7236 16:44:07.495696  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7237 16:44:07.495783  ==

 7238 16:44:07.499201  Dram Type= 6, Freq= 0, CH_0, rank 0

 7239 16:44:07.502108  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7240 16:44:07.502193  ==

 7241 16:44:07.505634  [Duty_Offset_Calibration]

 7242 16:44:07.505752  	B0:2	B1:-1	CA:1

 7243 16:44:07.505820  

 7244 16:44:07.509315  [DutyScan_Calibration_Flow] k_type=0

 7245 16:44:07.518687  

 7246 16:44:07.518774  ==CLK 0==

 7247 16:44:07.522252  Final CLK duty delay cell = -4

 7248 16:44:07.525848  [-4] MAX Duty = 5031%(X100), DQS PI = 22

 7249 16:44:07.528701  [-4] MIN Duty = 4844%(X100), DQS PI = 32

 7250 16:44:07.532387  [-4] AVG Duty = 4937%(X100)

 7251 16:44:07.532487  

 7252 16:44:07.535323  CH0 CLK Duty spec in!! Max-Min= 187%

 7253 16:44:07.538828  [DutyScan_Calibration_Flow] ====Done====

 7254 16:44:07.538925  

 7255 16:44:07.542091  [DutyScan_Calibration_Flow] k_type=1

 7256 16:44:07.558673  

 7257 16:44:07.558823  ==DQS 0 ==

 7258 16:44:07.561762  Final DQS duty delay cell = 0

 7259 16:44:07.564970  [0] MAX Duty = 5125%(X100), DQS PI = 22

 7260 16:44:07.568542  [0] MIN Duty = 5000%(X100), DQS PI = 16

 7261 16:44:07.571595  [0] AVG Duty = 5062%(X100)

 7262 16:44:07.571709  

 7263 16:44:07.571780  ==DQS 1 ==

 7264 16:44:07.575055  Final DQS duty delay cell = -4

 7265 16:44:07.578227  [-4] MAX Duty = 5093%(X100), DQS PI = 0

 7266 16:44:07.581782  [-4] MIN Duty = 5000%(X100), DQS PI = 40

 7267 16:44:07.585214  [-4] AVG Duty = 5046%(X100)

 7268 16:44:07.585322  

 7269 16:44:07.588500  CH0 DQS 0 Duty spec in!! Max-Min= 125%

 7270 16:44:07.588598  

 7271 16:44:07.591809  CH0 DQS 1 Duty spec in!! Max-Min= 93%

 7272 16:44:07.595190  [DutyScan_Calibration_Flow] ====Done====

 7273 16:44:07.595295  

 7274 16:44:07.598253  [DutyScan_Calibration_Flow] k_type=3

 7275 16:44:07.616136  

 7276 16:44:07.616289  ==DQM 0 ==

 7277 16:44:07.619143  Final DQM duty delay cell = 0

 7278 16:44:07.622616  [0] MAX Duty = 5000%(X100), DQS PI = 20

 7279 16:44:07.625711  [0] MIN Duty = 4875%(X100), DQS PI = 6

 7280 16:44:07.629211  [0] AVG Duty = 4937%(X100)

 7281 16:44:07.629302  

 7282 16:44:07.629369  ==DQM 1 ==

 7283 16:44:07.632136  Final DQM duty delay cell = 0

 7284 16:44:07.635645  [0] MAX Duty = 5187%(X100), DQS PI = 58

 7285 16:44:07.639201  [0] MIN Duty = 4969%(X100), DQS PI = 18

 7286 16:44:07.642279  [0] AVG Duty = 5078%(X100)

 7287 16:44:07.642364  

 7288 16:44:07.645760  CH0 DQM 0 Duty spec in!! Max-Min= 125%

 7289 16:44:07.645844  

 7290 16:44:07.649156  CH0 DQM 1 Duty spec in!! Max-Min= 218%

 7291 16:44:07.652069  [DutyScan_Calibration_Flow] ====Done====

 7292 16:44:07.652155  

 7293 16:44:07.655416  [DutyScan_Calibration_Flow] k_type=2

 7294 16:44:07.672232  

 7295 16:44:07.672388  ==DQ 0 ==

 7296 16:44:07.675769  Final DQ duty delay cell = -4

 7297 16:44:07.678861  [-4] MAX Duty = 5031%(X100), DQS PI = 56

 7298 16:44:07.682414  [-4] MIN Duty = 4844%(X100), DQS PI = 14

 7299 16:44:07.685444  [-4] AVG Duty = 4937%(X100)

 7300 16:44:07.685540  

 7301 16:44:07.685606  ==DQ 1 ==

 7302 16:44:07.689121  Final DQ duty delay cell = 0

 7303 16:44:07.692126  [0] MAX Duty = 5000%(X100), DQS PI = 0

 7304 16:44:07.695515  [0] MIN Duty = 4907%(X100), DQS PI = 20

 7305 16:44:07.695617  [0] AVG Duty = 4953%(X100)

 7306 16:44:07.698746  

 7307 16:44:07.702362  CH0 DQ 0 Duty spec in!! Max-Min= 187%

 7308 16:44:07.702446  

 7309 16:44:07.705414  CH0 DQ 1 Duty spec in!! Max-Min= 93%

 7310 16:44:07.708906  [DutyScan_Calibration_Flow] ====Done====

 7311 16:44:07.708998  ==

 7312 16:44:07.712525  Dram Type= 6, Freq= 0, CH_1, rank 0

 7313 16:44:07.715277  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7314 16:44:07.715361  ==

 7315 16:44:07.718923  [Duty_Offset_Calibration]

 7316 16:44:07.719015  	B0:1	B1:1	CA:2

 7317 16:44:07.719081  

 7318 16:44:07.721856  [DutyScan_Calibration_Flow] k_type=0

 7319 16:44:07.732858  

 7320 16:44:07.733000  ==CLK 0==

 7321 16:44:07.736334  Final CLK duty delay cell = 0

 7322 16:44:07.739221  [0] MAX Duty = 5187%(X100), DQS PI = 24

 7323 16:44:07.742772  [0] MIN Duty = 4938%(X100), DQS PI = 50

 7324 16:44:07.745765  [0] AVG Duty = 5062%(X100)

 7325 16:44:07.745860  

 7326 16:44:07.749492  CH1 CLK Duty spec in!! Max-Min= 249%

 7327 16:44:07.752128  [DutyScan_Calibration_Flow] ====Done====

 7328 16:44:07.752218  

 7329 16:44:07.755687  [DutyScan_Calibration_Flow] k_type=1

 7330 16:44:07.772308  

 7331 16:44:07.772454  ==DQS 0 ==

 7332 16:44:07.775674  Final DQS duty delay cell = 0

 7333 16:44:07.779092  [0] MAX Duty = 5094%(X100), DQS PI = 22

 7334 16:44:07.782563  [0] MIN Duty = 4813%(X100), DQS PI = 52

 7335 16:44:07.785698  [0] AVG Duty = 4953%(X100)

 7336 16:44:07.785782  

 7337 16:44:07.785848  ==DQS 1 ==

 7338 16:44:07.789183  Final DQS duty delay cell = 0

 7339 16:44:07.792113  [0] MAX Duty = 5031%(X100), DQS PI = 34

 7340 16:44:07.795404  [0] MIN Duty = 4938%(X100), DQS PI = 12

 7341 16:44:07.798806  [0] AVG Duty = 4984%(X100)

 7342 16:44:07.798890  

 7343 16:44:07.802190  CH1 DQS 0 Duty spec in!! Max-Min= 281%

 7344 16:44:07.802275  

 7345 16:44:07.805334  CH1 DQS 1 Duty spec in!! Max-Min= 93%

 7346 16:44:07.808847  [DutyScan_Calibration_Flow] ====Done====

 7347 16:44:07.808931  

 7348 16:44:07.812260  [DutyScan_Calibration_Flow] k_type=3

 7349 16:44:07.829318  

 7350 16:44:07.829473  ==DQM 0 ==

 7351 16:44:07.832830  Final DQM duty delay cell = 0

 7352 16:44:07.835827  [0] MAX Duty = 5124%(X100), DQS PI = 18

 7353 16:44:07.838946  [0] MIN Duty = 4844%(X100), DQS PI = 52

 7354 16:44:07.842385  [0] AVG Duty = 4984%(X100)

 7355 16:44:07.842470  

 7356 16:44:07.842536  ==DQM 1 ==

 7357 16:44:07.845932  Final DQM duty delay cell = 0

 7358 16:44:07.848962  [0] MAX Duty = 5125%(X100), DQS PI = 8

 7359 16:44:07.852498  [0] MIN Duty = 4875%(X100), DQS PI = 20

 7360 16:44:07.855862  [0] AVG Duty = 5000%(X100)

 7361 16:44:07.855945  

 7362 16:44:07.859060  CH1 DQM 0 Duty spec in!! Max-Min= 280%

 7363 16:44:07.859182  

 7364 16:44:07.862545  CH1 DQM 1 Duty spec in!! Max-Min= 250%

 7365 16:44:07.865698  [DutyScan_Calibration_Flow] ====Done====

 7366 16:44:07.865788  

 7367 16:44:07.869026  [DutyScan_Calibration_Flow] k_type=2

 7368 16:44:07.885911  

 7369 16:44:07.886030  ==DQ 0 ==

 7370 16:44:07.889323  Final DQ duty delay cell = 0

 7371 16:44:07.892951  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7372 16:44:07.896191  [0] MIN Duty = 4907%(X100), DQS PI = 52

 7373 16:44:07.896279  [0] AVG Duty = 5031%(X100)

 7374 16:44:07.899461  

 7375 16:44:07.899548  ==DQ 1 ==

 7376 16:44:07.902351  Final DQ duty delay cell = 0

 7377 16:44:07.906261  [0] MAX Duty = 5124%(X100), DQS PI = 42

 7378 16:44:07.909217  [0] MIN Duty = 5031%(X100), DQS PI = 0

 7379 16:44:07.909308  [0] AVG Duty = 5077%(X100)

 7380 16:44:07.909374  

 7381 16:44:07.916373  CH1 DQ 0 Duty spec in!! Max-Min= 249%

 7382 16:44:07.916457  

 7383 16:44:07.919210  CH1 DQ 1 Duty spec in!! Max-Min= 93%

 7384 16:44:07.922266  [DutyScan_Calibration_Flow] ====Done====

 7385 16:44:07.925651  nWR fixed to 30

 7386 16:44:07.925745  [ModeRegInit_LP4] CH0 RK0

 7387 16:44:07.929289  [ModeRegInit_LP4] CH0 RK1

 7388 16:44:07.932194  [ModeRegInit_LP4] CH1 RK0

 7389 16:44:07.935703  [ModeRegInit_LP4] CH1 RK1

 7390 16:44:07.935787  match AC timing 5

 7391 16:44:07.938693  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7392 16:44:07.945972  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7393 16:44:07.948971  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7394 16:44:07.955425  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7395 16:44:07.958997  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7396 16:44:07.959106  [MiockJmeterHQA]

 7397 16:44:07.959174  

 7398 16:44:07.962358  [DramcMiockJmeter] u1RxGatingPI = 0

 7399 16:44:07.965521  0 : 4252, 4027

 7400 16:44:07.965623  4 : 4253, 4027

 7401 16:44:07.969055  8 : 4252, 4027

 7402 16:44:07.969180  12 : 4257, 4032

 7403 16:44:07.969285  16 : 4363, 4138

 7404 16:44:07.972577  20 : 4252, 4027

 7405 16:44:07.972683  24 : 4252, 4027

 7406 16:44:07.975307  28 : 4252, 4027

 7407 16:44:07.975401  32 : 4255, 4029

 7408 16:44:07.978713  36 : 4252, 4027

 7409 16:44:07.978807  40 : 4252, 4027

 7410 16:44:07.978876  44 : 4365, 4140

 7411 16:44:07.982170  48 : 4253, 4027

 7412 16:44:07.982263  52 : 4255, 4029

 7413 16:44:07.985530  56 : 4250, 4027

 7414 16:44:07.985626  60 : 4363, 4140

 7415 16:44:07.989028  64 : 4250, 4027

 7416 16:44:07.989128  68 : 4361, 4137

 7417 16:44:07.991785  72 : 4252, 4029

 7418 16:44:07.991875  76 : 4250, 4027

 7419 16:44:07.991944  80 : 4250, 4027

 7420 16:44:07.995239  84 : 4252, 4029

 7421 16:44:07.995333  88 : 4361, 4137

 7422 16:44:07.998620  92 : 4250, 4026

 7423 16:44:07.998719  96 : 4360, 3470

 7424 16:44:08.002056  100 : 4249, 0

 7425 16:44:08.002147  104 : 4250, 0

 7426 16:44:08.002216  108 : 4252, 0

 7427 16:44:08.005349  112 : 4250, 0

 7428 16:44:08.005438  116 : 4250, 0

 7429 16:44:08.008760  120 : 4253, 0

 7430 16:44:08.008858  124 : 4360, 0

 7431 16:44:08.008928  128 : 4250, 0

 7432 16:44:08.012233  132 : 4250, 0

 7433 16:44:08.012325  136 : 4250, 0

 7434 16:44:08.015190  140 : 4361, 0

 7435 16:44:08.015279  144 : 4361, 0

 7436 16:44:08.015348  148 : 4250, 0

 7437 16:44:08.018918  152 : 4250, 0

 7438 16:44:08.019006  156 : 4250, 0

 7439 16:44:08.019075  160 : 4253, 0

 7440 16:44:08.021915  164 : 4249, 0

 7441 16:44:08.022004  168 : 4249, 0

 7442 16:44:08.025392  172 : 4252, 0

 7443 16:44:08.025478  176 : 4250, 0

 7444 16:44:08.025547  180 : 4250, 0

 7445 16:44:08.028927  184 : 4252, 0

 7446 16:44:08.029013  188 : 4361, 0

 7447 16:44:08.031843  192 : 4361, 0

 7448 16:44:08.031981  196 : 4363, 0

 7449 16:44:08.032067  200 : 4250, 0

 7450 16:44:08.035548  204 : 4250, 0

 7451 16:44:08.035634  208 : 4250, 0

 7452 16:44:08.038580  212 : 4253, 124

 7453 16:44:08.038666  216 : 4250, 3658

 7454 16:44:08.041609  220 : 4250, 4027

 7455 16:44:08.041696  224 : 4361, 4137

 7456 16:44:08.041764  228 : 4250, 4026

 7457 16:44:08.045216  232 : 4250, 4027

 7458 16:44:08.045303  236 : 4360, 4138

 7459 16:44:08.048790  240 : 4361, 4137

 7460 16:44:08.048878  244 : 4250, 4026

 7461 16:44:08.051719  248 : 4363, 4139

 7462 16:44:08.051808  252 : 4250, 4027

 7463 16:44:08.055264  256 : 4249, 4027

 7464 16:44:08.055353  260 : 4250, 4026

 7465 16:44:08.058316  264 : 4253, 4029

 7466 16:44:08.058405  268 : 4250, 4027

 7467 16:44:08.061832  272 : 4250, 4027

 7468 16:44:08.061920  276 : 4250, 4026

 7469 16:44:08.064800  280 : 4253, 4029

 7470 16:44:08.064897  284 : 4250, 4027

 7471 16:44:08.064974  288 : 4360, 4138

 7472 16:44:08.068336  292 : 4361, 4137

 7473 16:44:08.068428  296 : 4250, 4026

 7474 16:44:08.071339  300 : 4361, 4137

 7475 16:44:08.071431  304 : 4250, 4027

 7476 16:44:08.074823  308 : 4250, 4027

 7477 16:44:08.074916  312 : 4250, 4026

 7478 16:44:08.078286  316 : 4253, 4029

 7479 16:44:08.078378  320 : 4250, 4027

 7480 16:44:08.081704  324 : 4250, 4027

 7481 16:44:08.081792  328 : 4250, 4026

 7482 16:44:08.085117  332 : 4253, 2700

 7483 16:44:08.085206  336 : 4250, 57

 7484 16:44:08.085274  

 7485 16:44:08.087924  	MIOCK jitter meter	ch=0

 7486 16:44:08.088049  

 7487 16:44:08.091371  1T = (336-100) = 236 dly cells

 7488 16:44:08.094814  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps

 7489 16:44:08.094904  ==

 7490 16:44:08.098203  Dram Type= 6, Freq= 0, CH_0, rank 0

 7491 16:44:08.104728  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7492 16:44:08.104835  ==

 7493 16:44:08.108185  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7494 16:44:08.114730  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7495 16:44:08.118187  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7496 16:44:08.124650  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7497 16:44:08.132742  [CA 0] Center 44 (14~75) winsize 62

 7498 16:44:08.135718  [CA 1] Center 43 (13~74) winsize 62

 7499 16:44:08.139209  [CA 2] Center 39 (10~68) winsize 59

 7500 16:44:08.142401  [CA 3] Center 39 (10~68) winsize 59

 7501 16:44:08.145787  [CA 4] Center 37 (7~67) winsize 61

 7502 16:44:08.149466  [CA 5] Center 37 (7~67) winsize 61

 7503 16:44:08.149553  

 7504 16:44:08.152320  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7505 16:44:08.152406  

 7506 16:44:08.155923  [CATrainingPosCal] consider 1 rank data

 7507 16:44:08.158898  u2DelayCellTimex100 = 275/100 ps

 7508 16:44:08.165943  CA0 delay=44 (14~75),Diff = 7 PI (24 cell)

 7509 16:44:08.169548  CA1 delay=43 (13~74),Diff = 6 PI (21 cell)

 7510 16:44:08.172552  CA2 delay=39 (10~68),Diff = 2 PI (7 cell)

 7511 16:44:08.176164  CA3 delay=39 (10~68),Diff = 2 PI (7 cell)

 7512 16:44:08.178984  CA4 delay=37 (7~67),Diff = 0 PI (0 cell)

 7513 16:44:08.182455  CA5 delay=37 (7~67),Diff = 0 PI (0 cell)

 7514 16:44:08.182545  

 7515 16:44:08.185900  CA PerBit enable=1, Macro0, CA PI delay=37

 7516 16:44:08.185986  

 7517 16:44:08.189307  [CBTSetCACLKResult] CA Dly = 37

 7518 16:44:08.192712  CS Dly: 11 (0~42)

 7519 16:44:08.195919  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7520 16:44:08.199334  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7521 16:44:08.199423  ==

 7522 16:44:08.202819  Dram Type= 6, Freq= 0, CH_0, rank 1

 7523 16:44:08.205812  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7524 16:44:08.209227  ==

 7525 16:44:08.212634  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7526 16:44:08.215804  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7527 16:44:08.222128  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7528 16:44:08.228711  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7529 16:44:08.236331  [CA 0] Center 44 (13~75) winsize 63

 7530 16:44:08.239831  [CA 1] Center 44 (14~75) winsize 62

 7531 16:44:08.242837  [CA 2] Center 39 (10~69) winsize 60

 7532 16:44:08.246562  [CA 3] Center 39 (9~69) winsize 61

 7533 16:44:08.249541  [CA 4] Center 37 (7~67) winsize 61

 7534 16:44:08.253120  [CA 5] Center 37 (7~67) winsize 61

 7535 16:44:08.253207  

 7536 16:44:08.256165  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7537 16:44:08.256250  

 7538 16:44:08.259668  [CATrainingPosCal] consider 2 rank data

 7539 16:44:08.263222  u2DelayCellTimex100 = 275/100 ps

 7540 16:44:08.269713  CA0 delay=44 (14~75),Diff = 7 PI (24 cell)

 7541 16:44:08.272607  CA1 delay=44 (14~74),Diff = 7 PI (24 cell)

 7542 16:44:08.276273  CA2 delay=39 (10~68),Diff = 2 PI (7 cell)

 7543 16:44:08.279155  CA3 delay=39 (10~68),Diff = 2 PI (7 cell)

 7544 16:44:08.282728  CA4 delay=37 (7~67),Diff = 0 PI (0 cell)

 7545 16:44:08.286078  CA5 delay=37 (7~67),Diff = 0 PI (0 cell)

 7546 16:44:08.286188  

 7547 16:44:08.289569  CA PerBit enable=1, Macro0, CA PI delay=37

 7548 16:44:08.289658  

 7549 16:44:08.292614  [CBTSetCACLKResult] CA Dly = 37

 7550 16:44:08.295921  CS Dly: 12 (0~44)

 7551 16:44:08.299380  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7552 16:44:08.302921  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7553 16:44:08.303085  

 7554 16:44:08.306092  ----->DramcWriteLeveling(PI) begin...

 7555 16:44:08.306211  ==

 7556 16:44:08.309100  Dram Type= 6, Freq= 0, CH_0, rank 0

 7557 16:44:08.315886  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7558 16:44:08.316071  ==

 7559 16:44:08.319333  Write leveling (Byte 0): 30 => 30

 7560 16:44:08.322691  Write leveling (Byte 1): 28 => 28

 7561 16:44:08.322808  DramcWriteLeveling(PI) end<-----

 7562 16:44:08.322900  

 7563 16:44:08.325731  ==

 7564 16:44:08.329126  Dram Type= 6, Freq= 0, CH_0, rank 0

 7565 16:44:08.332316  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7566 16:44:08.332415  ==

 7567 16:44:08.335889  [Gating] SW mode calibration

 7568 16:44:08.342182  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7569 16:44:08.345782  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7570 16:44:08.352426   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7571 16:44:08.355816   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7572 16:44:08.358744   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7573 16:44:08.365597   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7574 16:44:08.369081   1  4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)

 7575 16:44:08.372647   1  4 20 | B1->B0 | 2626 3434 | 1 0 | (1 1) (0 0)

 7576 16:44:08.378791   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7577 16:44:08.382467   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7578 16:44:08.385519   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7579 16:44:08.392384   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7580 16:44:08.395286   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 7581 16:44:08.398875   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 7582 16:44:08.405612   1  5 16 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)

 7583 16:44:08.408832   1  5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)

 7584 16:44:08.412248   1  5 24 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)

 7585 16:44:08.418605   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7586 16:44:08.422112   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7587 16:44:08.425412   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7588 16:44:08.431702   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7589 16:44:08.435305   1  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7590 16:44:08.438275   1  6 16 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)

 7591 16:44:08.445320   1  6 20 | B1->B0 | 2c2c 4646 | 1 0 | (0 0) (0 0)

 7592 16:44:08.448803   1  6 24 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)

 7593 16:44:08.451728   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7594 16:44:08.455316   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7595 16:44:08.462068   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7596 16:44:08.464912   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7597 16:44:08.468544   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7598 16:44:08.475020   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7599 16:44:08.478673   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 7600 16:44:08.481861   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7601 16:44:08.488357   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7602 16:44:08.491867   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7603 16:44:08.494750   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7604 16:44:08.501810   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7605 16:44:08.505229   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7606 16:44:08.508125   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7607 16:44:08.514740   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7608 16:44:08.518264   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7609 16:44:08.521665   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7610 16:44:08.528480   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7611 16:44:08.531802   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7612 16:44:08.534851   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7613 16:44:08.541800   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7614 16:44:08.544757   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7615 16:44:08.548113   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7616 16:44:08.551498  Total UI for P1: 0, mck2ui 16

 7617 16:44:08.554778  best dqsien dly found for B0: ( 1,  9, 14)

 7618 16:44:08.561412   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7619 16:44:08.565104   1  9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7620 16:44:08.567997  Total UI for P1: 0, mck2ui 16

 7621 16:44:08.571768  best dqsien dly found for B1: ( 1,  9, 22)

 7622 16:44:08.574487  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 7623 16:44:08.578183  best DQS1 dly(MCK, UI, PI) = (1, 9, 22)

 7624 16:44:08.578299  

 7625 16:44:08.581740  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 7626 16:44:08.584742  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)

 7627 16:44:08.588047  [Gating] SW calibration Done

 7628 16:44:08.588141  ==

 7629 16:44:08.591640  Dram Type= 6, Freq= 0, CH_0, rank 0

 7630 16:44:08.594630  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7631 16:44:08.594747  ==

 7632 16:44:08.598284  RX Vref Scan: 0

 7633 16:44:08.598397  

 7634 16:44:08.601212  RX Vref 0 -> 0, step: 1

 7635 16:44:08.601323  

 7636 16:44:08.601421  RX Delay 0 -> 252, step: 8

 7637 16:44:08.608164  iDelay=200, Bit 0, Center 131 (80 ~ 183) 104

 7638 16:44:08.611459  iDelay=200, Bit 1, Center 135 (80 ~ 191) 112

 7639 16:44:08.614957  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 7640 16:44:08.617721  iDelay=200, Bit 3, Center 127 (72 ~ 183) 112

 7641 16:44:08.621032  iDelay=200, Bit 4, Center 135 (80 ~ 191) 112

 7642 16:44:08.628211  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 7643 16:44:08.631161  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 7644 16:44:08.634404  iDelay=200, Bit 7, Center 139 (88 ~ 191) 104

 7645 16:44:08.638086  iDelay=200, Bit 8, Center 111 (56 ~ 167) 112

 7646 16:44:08.641480  iDelay=200, Bit 9, Center 111 (56 ~ 167) 112

 7647 16:44:08.647888  iDelay=200, Bit 10, Center 119 (64 ~ 175) 112

 7648 16:44:08.651431  iDelay=200, Bit 11, Center 115 (64 ~ 167) 104

 7649 16:44:08.655021  iDelay=200, Bit 12, Center 131 (72 ~ 191) 120

 7650 16:44:08.657903  iDelay=200, Bit 13, Center 131 (80 ~ 183) 104

 7651 16:44:08.661440  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 7652 16:44:08.668127  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7653 16:44:08.668262  ==

 7654 16:44:08.671064  Dram Type= 6, Freq= 0, CH_0, rank 0

 7655 16:44:08.674701  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7656 16:44:08.674833  ==

 7657 16:44:08.674934  DQS Delay:

 7658 16:44:08.677661  DQS0 = 0, DQS1 = 0

 7659 16:44:08.677755  DQM Delay:

 7660 16:44:08.681264  DQM0 = 132, DQM1 = 123

 7661 16:44:08.681370  DQ Delay:

 7662 16:44:08.684332  DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127

 7663 16:44:08.687921  DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139

 7664 16:44:08.691298  DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115

 7665 16:44:08.694415  DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135

 7666 16:44:08.697958  

 7667 16:44:08.698071  

 7668 16:44:08.698165  ==

 7669 16:44:08.700821  Dram Type= 6, Freq= 0, CH_0, rank 0

 7670 16:44:08.704486  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7671 16:44:08.704572  ==

 7672 16:44:08.704645  

 7673 16:44:08.704706  

 7674 16:44:08.707653  	TX Vref Scan disable

 7675 16:44:08.707759   == TX Byte 0 ==

 7676 16:44:08.714205  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 7677 16:44:08.717693  Update DQM dly =988 (3 ,6, 28)  DQM OEN =(3 ,3)

 7678 16:44:08.717812   == TX Byte 1 ==

 7679 16:44:08.724427  Update DQ  dly =985 (3 ,6, 25)  DQ  OEN =(3 ,3)

 7680 16:44:08.727758  Update DQM dly =985 (3 ,6, 25)  DQM OEN =(3 ,3)

 7681 16:44:08.727871  ==

 7682 16:44:08.730772  Dram Type= 6, Freq= 0, CH_0, rank 0

 7683 16:44:08.734134  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7684 16:44:08.734243  ==

 7685 16:44:08.749253  

 7686 16:44:08.752148  TX Vref early break, caculate TX vref

 7687 16:44:08.755285  TX Vref=16, minBit 7, minWin=20, winSum=362

 7688 16:44:08.758735  TX Vref=18, minBit 1, minWin=21, winSum=368

 7689 16:44:08.762217  TX Vref=20, minBit 7, minWin=22, winSum=382

 7690 16:44:08.765199  TX Vref=22, minBit 1, minWin=22, winSum=386

 7691 16:44:08.768780  TX Vref=24, minBit 1, minWin=23, winSum=400

 7692 16:44:08.775400  TX Vref=26, minBit 1, minWin=23, winSum=409

 7693 16:44:08.779039  TX Vref=28, minBit 1, minWin=24, winSum=415

 7694 16:44:08.782069  TX Vref=30, minBit 3, minWin=25, winSum=417

 7695 16:44:08.785699  TX Vref=32, minBit 0, minWin=24, winSum=409

 7696 16:44:08.789082  TX Vref=34, minBit 0, minWin=24, winSum=401

 7697 16:44:08.791898  TX Vref=36, minBit 3, minWin=23, winSum=387

 7698 16:44:08.798775  [TxChooseVref] Worse bit 3, Min win 25, Win sum 417, Final Vref 30

 7699 16:44:08.798922  

 7700 16:44:08.801738  Final TX Range 0 Vref 30

 7701 16:44:08.801853  

 7702 16:44:08.801949  ==

 7703 16:44:08.805376  Dram Type= 6, Freq= 0, CH_0, rank 0

 7704 16:44:08.808894  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7705 16:44:08.809030  ==

 7706 16:44:08.809128  

 7707 16:44:08.809226  

 7708 16:44:08.811900  	TX Vref Scan disable

 7709 16:44:08.819120  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 7710 16:44:08.819264   == TX Byte 0 ==

 7711 16:44:08.821951  u2DelayCellOfst[0]=14 cells (4 PI)

 7712 16:44:08.825257  u2DelayCellOfst[1]=21 cells (6 PI)

 7713 16:44:08.828713  u2DelayCellOfst[2]=10 cells (3 PI)

 7714 16:44:08.831506  u2DelayCellOfst[3]=14 cells (4 PI)

 7715 16:44:08.835136  u2DelayCellOfst[4]=10 cells (3 PI)

 7716 16:44:08.838406  u2DelayCellOfst[5]=0 cells (0 PI)

 7717 16:44:08.841873  u2DelayCellOfst[6]=21 cells (6 PI)

 7718 16:44:08.844840  u2DelayCellOfst[7]=21 cells (6 PI)

 7719 16:44:08.848169  Update DQ  dly =985 (3 ,6, 25)  DQ  OEN =(3 ,3)

 7720 16:44:08.851626  Update DQM dly =988 (3 ,6, 28)  DQM OEN =(3 ,3)

 7721 16:44:08.855086   == TX Byte 1 ==

 7722 16:44:08.858159  u2DelayCellOfst[8]=0 cells (0 PI)

 7723 16:44:08.861699  u2DelayCellOfst[9]=0 cells (0 PI)

 7724 16:44:08.864657  u2DelayCellOfst[10]=7 cells (2 PI)

 7725 16:44:08.864765  u2DelayCellOfst[11]=3 cells (1 PI)

 7726 16:44:08.868247  u2DelayCellOfst[12]=14 cells (4 PI)

 7727 16:44:08.871809  u2DelayCellOfst[13]=14 cells (4 PI)

 7728 16:44:08.874790  u2DelayCellOfst[14]=17 cells (5 PI)

 7729 16:44:08.878295  u2DelayCellOfst[15]=14 cells (4 PI)

 7730 16:44:08.884967  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7731 16:44:08.888148  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 7732 16:44:08.888264  DramC Write-DBI on

 7733 16:44:08.888360  ==

 7734 16:44:08.891838  Dram Type= 6, Freq= 0, CH_0, rank 0

 7735 16:44:08.898195  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7736 16:44:08.898305  ==

 7737 16:44:08.898419  

 7738 16:44:08.898529  

 7739 16:44:08.898624  	TX Vref Scan disable

 7740 16:44:08.902181   == TX Byte 0 ==

 7741 16:44:08.905841  Update DQM dly =732 (2 ,6, 28)  DQM OEN =(3 ,3)

 7742 16:44:08.908908   == TX Byte 1 ==

 7743 16:44:08.912378  Update DQM dly =726 (2 ,6, 22)  DQM OEN =(3 ,3)

 7744 16:44:08.915895  DramC Write-DBI off

 7745 16:44:08.916018  

 7746 16:44:08.916085  [DATLAT]

 7747 16:44:08.916156  Freq=1600, CH0 RK0

 7748 16:44:08.916244  

 7749 16:44:08.918732  DATLAT Default: 0xf

 7750 16:44:08.918801  0, 0xFFFF, sum = 0

 7751 16:44:08.922228  1, 0xFFFF, sum = 0

 7752 16:44:08.922324  2, 0xFFFF, sum = 0

 7753 16:44:08.925857  3, 0xFFFF, sum = 0

 7754 16:44:08.929149  4, 0xFFFF, sum = 0

 7755 16:44:08.929237  5, 0xFFFF, sum = 0

 7756 16:44:08.932578  6, 0xFFFF, sum = 0

 7757 16:44:08.932657  7, 0xFFFF, sum = 0

 7758 16:44:08.935915  8, 0xFFFF, sum = 0

 7759 16:44:08.936040  9, 0xFFFF, sum = 0

 7760 16:44:08.939043  10, 0xFFFF, sum = 0

 7761 16:44:08.939148  11, 0xFFFF, sum = 0

 7762 16:44:08.942383  12, 0xFFFF, sum = 0

 7763 16:44:08.942504  13, 0xFFFF, sum = 0

 7764 16:44:08.945777  14, 0x0, sum = 1

 7765 16:44:08.945880  15, 0x0, sum = 2

 7766 16:44:08.949302  16, 0x0, sum = 3

 7767 16:44:08.949418  17, 0x0, sum = 4

 7768 16:44:08.952228  best_step = 15

 7769 16:44:08.952308  

 7770 16:44:08.952374  ==

 7771 16:44:08.955586  Dram Type= 6, Freq= 0, CH_0, rank 0

 7772 16:44:08.959250  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7773 16:44:08.959329  ==

 7774 16:44:08.959393  RX Vref Scan: 1

 7775 16:44:08.962267  

 7776 16:44:08.962368  Set Vref Range= 24 -> 127

 7777 16:44:08.962457  

 7778 16:44:08.965829  RX Vref 24 -> 127, step: 1

 7779 16:44:08.965926  

 7780 16:44:08.969199  RX Delay 11 -> 252, step: 4

 7781 16:44:08.969311  

 7782 16:44:08.972231  Set Vref, RX VrefLevel [Byte0]: 24

 7783 16:44:08.975932                           [Byte1]: 24

 7784 16:44:08.976053  

 7785 16:44:08.978764  Set Vref, RX VrefLevel [Byte0]: 25

 7786 16:44:08.982353                           [Byte1]: 25

 7787 16:44:08.982438  

 7788 16:44:08.985294  Set Vref, RX VrefLevel [Byte0]: 26

 7789 16:44:08.988849                           [Byte1]: 26

 7790 16:44:08.992471  

 7791 16:44:08.992557  Set Vref, RX VrefLevel [Byte0]: 27

 7792 16:44:08.996080                           [Byte1]: 27

 7793 16:44:09.000280  

 7794 16:44:09.000366  Set Vref, RX VrefLevel [Byte0]: 28

 7795 16:44:09.003776                           [Byte1]: 28

 7796 16:44:09.007756  

 7797 16:44:09.007850  Set Vref, RX VrefLevel [Byte0]: 29

 7798 16:44:09.011316                           [Byte1]: 29

 7799 16:44:09.015503  

 7800 16:44:09.015588  Set Vref, RX VrefLevel [Byte0]: 30

 7801 16:44:09.018992                           [Byte1]: 30

 7802 16:44:09.023135  

 7803 16:44:09.023221  Set Vref, RX VrefLevel [Byte0]: 31

 7804 16:44:09.026531                           [Byte1]: 31

 7805 16:44:09.030803  

 7806 16:44:09.030890  Set Vref, RX VrefLevel [Byte0]: 32

 7807 16:44:09.034020                           [Byte1]: 32

 7808 16:44:09.038579  

 7809 16:44:09.038667  Set Vref, RX VrefLevel [Byte0]: 33

 7810 16:44:09.041558                           [Byte1]: 33

 7811 16:44:09.046056  

 7812 16:44:09.046141  Set Vref, RX VrefLevel [Byte0]: 34

 7813 16:44:09.049413                           [Byte1]: 34

 7814 16:44:09.053431  

 7815 16:44:09.053518  Set Vref, RX VrefLevel [Byte0]: 35

 7816 16:44:09.056997                           [Byte1]: 35

 7817 16:44:09.061411  

 7818 16:44:09.061499  Set Vref, RX VrefLevel [Byte0]: 36

 7819 16:44:09.064318                           [Byte1]: 36

 7820 16:44:09.069102  

 7821 16:44:09.069187  Set Vref, RX VrefLevel [Byte0]: 37

 7822 16:44:09.071929                           [Byte1]: 37

 7823 16:44:09.076634  

 7824 16:44:09.076723  Set Vref, RX VrefLevel [Byte0]: 38

 7825 16:44:09.079596                           [Byte1]: 38

 7826 16:44:09.084326  

 7827 16:44:09.084423  Set Vref, RX VrefLevel [Byte0]: 39

 7828 16:44:09.087356                           [Byte1]: 39

 7829 16:44:09.091694  

 7830 16:44:09.091783  Set Vref, RX VrefLevel [Byte0]: 40

 7831 16:44:09.094777                           [Byte1]: 40

 7832 16:44:09.099495  

 7833 16:44:09.099579  Set Vref, RX VrefLevel [Byte0]: 41

 7834 16:44:09.102830                           [Byte1]: 41

 7835 16:44:09.107092  

 7836 16:44:09.107194  Set Vref, RX VrefLevel [Byte0]: 42

 7837 16:44:09.109945                           [Byte1]: 42

 7838 16:44:09.114802  

 7839 16:44:09.114885  Set Vref, RX VrefLevel [Byte0]: 43

 7840 16:44:09.117762                           [Byte1]: 43

 7841 16:44:09.121938  

 7842 16:44:09.122021  Set Vref, RX VrefLevel [Byte0]: 44

 7843 16:44:09.125483                           [Byte1]: 44

 7844 16:44:09.129928  

 7845 16:44:09.130011  Set Vref, RX VrefLevel [Byte0]: 45

 7846 16:44:09.132841                           [Byte1]: 45

 7847 16:44:09.137321  

 7848 16:44:09.137407  Set Vref, RX VrefLevel [Byte0]: 46

 7849 16:44:09.140735                           [Byte1]: 46

 7850 16:44:09.144853  

 7851 16:44:09.144937  Set Vref, RX VrefLevel [Byte0]: 47

 7852 16:44:09.148384                           [Byte1]: 47

 7853 16:44:09.152342  

 7854 16:44:09.152432  Set Vref, RX VrefLevel [Byte0]: 48

 7855 16:44:09.155692                           [Byte1]: 48

 7856 16:44:09.160317  

 7857 16:44:09.160420  Set Vref, RX VrefLevel [Byte0]: 49

 7858 16:44:09.163522                           [Byte1]: 49

 7859 16:44:09.167582  

 7860 16:44:09.167671  Set Vref, RX VrefLevel [Byte0]: 50

 7861 16:44:09.171315                           [Byte1]: 50

 7862 16:44:09.175334  

 7863 16:44:09.175429  Set Vref, RX VrefLevel [Byte0]: 51

 7864 16:44:09.179021                           [Byte1]: 51

 7865 16:44:09.183063  

 7866 16:44:09.183163  Set Vref, RX VrefLevel [Byte0]: 52

 7867 16:44:09.186714                           [Byte1]: 52

 7868 16:44:09.190946  

 7869 16:44:09.191031  Set Vref, RX VrefLevel [Byte0]: 53

 7870 16:44:09.193947                           [Byte1]: 53

 7871 16:44:09.198185  

 7872 16:44:09.198271  Set Vref, RX VrefLevel [Byte0]: 54

 7873 16:44:09.201790                           [Byte1]: 54

 7874 16:44:09.205835  

 7875 16:44:09.205919  Set Vref, RX VrefLevel [Byte0]: 55

 7876 16:44:09.209325                           [Byte1]: 55

 7877 16:44:09.213464  

 7878 16:44:09.213547  Set Vref, RX VrefLevel [Byte0]: 56

 7879 16:44:09.216546                           [Byte1]: 56

 7880 16:44:09.221145  

 7881 16:44:09.221229  Set Vref, RX VrefLevel [Byte0]: 57

 7882 16:44:09.224154                           [Byte1]: 57

 7883 16:44:09.228758  

 7884 16:44:09.228843  Set Vref, RX VrefLevel [Byte0]: 58

 7885 16:44:09.231692                           [Byte1]: 58

 7886 16:44:09.236350  

 7887 16:44:09.236436  Set Vref, RX VrefLevel [Byte0]: 59

 7888 16:44:09.239305                           [Byte1]: 59

 7889 16:44:09.243775  

 7890 16:44:09.243860  Set Vref, RX VrefLevel [Byte0]: 60

 7891 16:44:09.247249                           [Byte1]: 60

 7892 16:44:09.251437  

 7893 16:44:09.251521  Set Vref, RX VrefLevel [Byte0]: 61

 7894 16:44:09.254860                           [Byte1]: 61

 7895 16:44:09.259401  

 7896 16:44:09.259484  Set Vref, RX VrefLevel [Byte0]: 62

 7897 16:44:09.262203                           [Byte1]: 62

 7898 16:44:09.266984  

 7899 16:44:09.267067  Set Vref, RX VrefLevel [Byte0]: 63

 7900 16:44:09.269953                           [Byte1]: 63

 7901 16:44:09.274114  

 7902 16:44:09.274199  Set Vref, RX VrefLevel [Byte0]: 64

 7903 16:44:09.277829                           [Byte1]: 64

 7904 16:44:09.281856  

 7905 16:44:09.281941  Set Vref, RX VrefLevel [Byte0]: 65

 7906 16:44:09.285443                           [Byte1]: 65

 7907 16:44:09.289678  

 7908 16:44:09.292699  Set Vref, RX VrefLevel [Byte0]: 66

 7909 16:44:09.292783                           [Byte1]: 66

 7910 16:44:09.297381  

 7911 16:44:09.297463  Set Vref, RX VrefLevel [Byte0]: 67

 7912 16:44:09.300512                           [Byte1]: 67

 7913 16:44:09.304646  

 7914 16:44:09.304729  Set Vref, RX VrefLevel [Byte0]: 68

 7915 16:44:09.308122                           [Byte1]: 68

 7916 16:44:09.312353  

 7917 16:44:09.312435  Set Vref, RX VrefLevel [Byte0]: 69

 7918 16:44:09.315704                           [Byte1]: 69

 7919 16:44:09.319785  

 7920 16:44:09.319857  Set Vref, RX VrefLevel [Byte0]: 70

 7921 16:44:09.323440                           [Byte1]: 70

 7922 16:44:09.327594  

 7923 16:44:09.327710  Set Vref, RX VrefLevel [Byte0]: 71

 7924 16:44:09.331169                           [Byte1]: 71

 7925 16:44:09.335405  

 7926 16:44:09.335487  Set Vref, RX VrefLevel [Byte0]: 72

 7927 16:44:09.338413                           [Byte1]: 72

 7928 16:44:09.342981  

 7929 16:44:09.343064  Set Vref, RX VrefLevel [Byte0]: 73

 7930 16:44:09.346244                           [Byte1]: 73

 7931 16:44:09.350669  

 7932 16:44:09.350751  Set Vref, RX VrefLevel [Byte0]: 74

 7933 16:44:09.353549                           [Byte1]: 74

 7934 16:44:09.358355  

 7935 16:44:09.358437  Set Vref, RX VrefLevel [Byte0]: 75

 7936 16:44:09.361213                           [Byte1]: 75

 7937 16:44:09.365855  

 7938 16:44:09.365939  Set Vref, RX VrefLevel [Byte0]: 76

 7939 16:44:09.369015                           [Byte1]: 76

 7940 16:44:09.373556  

 7941 16:44:09.373657  Set Vref, RX VrefLevel [Byte0]: 77

 7942 16:44:09.376773                           [Byte1]: 77

 7943 16:44:09.380893  

 7944 16:44:09.380976  Final RX Vref Byte 0 = 56 to rank0

 7945 16:44:09.384352  Final RX Vref Byte 1 = 60 to rank0

 7946 16:44:09.387858  Final RX Vref Byte 0 = 56 to rank1

 7947 16:44:09.390848  Final RX Vref Byte 1 = 60 to rank1==

 7948 16:44:09.394377  Dram Type= 6, Freq= 0, CH_0, rank 0

 7949 16:44:09.400982  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7950 16:44:09.401069  ==

 7951 16:44:09.401136  DQS Delay:

 7952 16:44:09.401197  DQS0 = 0, DQS1 = 0

 7953 16:44:09.404647  DQM Delay:

 7954 16:44:09.404802  DQM0 = 129, DQM1 = 121

 7955 16:44:09.407446  DQ Delay:

 7956 16:44:09.410982  DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126

 7957 16:44:09.414103  DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =138

 7958 16:44:09.417461  DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116

 7959 16:44:09.420905  DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132

 7960 16:44:09.420989  

 7961 16:44:09.421075  

 7962 16:44:09.421150  

 7963 16:44:09.423912  [DramC_TX_OE_Calibration] TA2

 7964 16:44:09.427356  Original DQ_B0 (3 6) =30, OEN = 27

 7965 16:44:09.430939  Original DQ_B1 (3 6) =30, OEN = 27

 7966 16:44:09.434430  24, 0x0, End_B0=24 End_B1=24

 7967 16:44:09.434542  25, 0x0, End_B0=25 End_B1=25

 7968 16:44:09.437540  26, 0x0, End_B0=26 End_B1=26

 7969 16:44:09.440937  27, 0x0, End_B0=27 End_B1=27

 7970 16:44:09.444477  28, 0x0, End_B0=28 End_B1=28

 7971 16:44:09.444614  29, 0x0, End_B0=29 End_B1=29

 7972 16:44:09.447373  30, 0x0, End_B0=30 End_B1=30

 7973 16:44:09.450796  31, 0x4141, End_B0=30 End_B1=30

 7974 16:44:09.453881  Byte0 end_step=30  best_step=27

 7975 16:44:09.457241  Byte1 end_step=30  best_step=27

 7976 16:44:09.460856  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7977 16:44:09.460944  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7978 16:44:09.464310  

 7979 16:44:09.464393  

 7980 16:44:09.470519  [DQSOSCAuto] RK0, (LSB)MR18= 0x1509, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps

 7981 16:44:09.473981  CH0 RK0: MR19=303, MR18=1509

 7982 16:44:09.480445  CH0_RK0: MR19=0x303, MR18=0x1509, DQSOSC=399, MR23=63, INC=23, DEC=15

 7983 16:44:09.480540  

 7984 16:44:09.484068  ----->DramcWriteLeveling(PI) begin...

 7985 16:44:09.484154  ==

 7986 16:44:09.487658  Dram Type= 6, Freq= 0, CH_0, rank 1

 7987 16:44:09.490483  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7988 16:44:09.490570  ==

 7989 16:44:09.494088  Write leveling (Byte 0): 34 => 34

 7990 16:44:09.497158  Write leveling (Byte 1): 28 => 28

 7991 16:44:09.500908  DramcWriteLeveling(PI) end<-----

 7992 16:44:09.500993  

 7993 16:44:09.501060  ==

 7994 16:44:09.504295  Dram Type= 6, Freq= 0, CH_0, rank 1

 7995 16:44:09.507274  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7996 16:44:09.507361  ==

 7997 16:44:09.510808  [Gating] SW mode calibration

 7998 16:44:09.517346  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7999 16:44:09.523770  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8000 16:44:09.527335   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8001 16:44:09.530929   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8002 16:44:09.537239   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8003 16:44:09.540844   1  4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)

 8004 16:44:09.544272   1  4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)

 8005 16:44:09.550629   1  4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)

 8006 16:44:09.554218   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8007 16:44:09.557011   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8008 16:44:09.563853   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8009 16:44:09.566715   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8010 16:44:09.570057   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)

 8011 16:44:09.576913   1  5 12 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)

 8012 16:44:09.580187   1  5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)

 8013 16:44:09.583852   1  5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)

 8014 16:44:09.590218   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8015 16:44:09.593697   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8016 16:44:09.596634   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8017 16:44:09.603436   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8018 16:44:09.607125   1  6  8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)

 8019 16:44:09.609896   1  6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8020 16:44:09.616474   1  6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)

 8021 16:44:09.620057   1  6 20 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)

 8022 16:44:09.622927   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8023 16:44:09.630059   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8024 16:44:09.632960   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8025 16:44:09.636556   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8026 16:44:09.643224   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8027 16:44:09.646654   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8028 16:44:09.649608   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8029 16:44:09.656485   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8030 16:44:09.659928   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8031 16:44:09.662796   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8032 16:44:09.669924   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8033 16:44:09.672899   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8034 16:44:09.676251   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8035 16:44:09.683106   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8036 16:44:09.686374   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8037 16:44:09.689388   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8038 16:44:09.693298   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8039 16:44:09.699524   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8040 16:44:09.703045   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8041 16:44:09.706069   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8042 16:44:09.712747   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8043 16:44:09.716259   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8044 16:44:09.719742   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 8045 16:44:09.722676  Total UI for P1: 0, mck2ui 16

 8046 16:44:09.726320  best dqsien dly found for B0: ( 1,  9,  8)

 8047 16:44:09.732817   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8048 16:44:09.736060   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8049 16:44:09.739533  Total UI for P1: 0, mck2ui 16

 8050 16:44:09.742496  best dqsien dly found for B1: ( 1,  9, 20)

 8051 16:44:09.746008  best DQS0 dly(MCK, UI, PI) = (1, 9, 8)

 8052 16:44:09.749488  best DQS1 dly(MCK, UI, PI) = (1, 9, 20)

 8053 16:44:09.749583  

 8054 16:44:09.753099  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8055 16:44:09.755825  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)

 8056 16:44:09.759308  [Gating] SW calibration Done

 8057 16:44:09.759400  ==

 8058 16:44:09.762736  Dram Type= 6, Freq= 0, CH_0, rank 1

 8059 16:44:09.765625  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8060 16:44:09.768946  ==

 8061 16:44:09.769059  RX Vref Scan: 0

 8062 16:44:09.769156  

 8063 16:44:09.772530  RX Vref 0 -> 0, step: 1

 8064 16:44:09.772637  

 8065 16:44:09.772732  RX Delay 0 -> 252, step: 8

 8066 16:44:09.779641  iDelay=200, Bit 0, Center 131 (72 ~ 191) 120

 8067 16:44:09.782478  iDelay=200, Bit 1, Center 131 (72 ~ 191) 120

 8068 16:44:09.785864  iDelay=200, Bit 2, Center 127 (72 ~ 183) 112

 8069 16:44:09.789183  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8070 16:44:09.792728  iDelay=200, Bit 4, Center 131 (72 ~ 191) 120

 8071 16:44:09.799457  iDelay=200, Bit 5, Center 119 (64 ~ 175) 112

 8072 16:44:09.802924  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8073 16:44:09.805870  iDelay=200, Bit 7, Center 139 (80 ~ 199) 120

 8074 16:44:09.809490  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8075 16:44:09.812491  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8076 16:44:09.819494  iDelay=200, Bit 10, Center 123 (64 ~ 183) 120

 8077 16:44:09.822467  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8078 16:44:09.826052  iDelay=200, Bit 12, Center 131 (80 ~ 183) 104

 8079 16:44:09.829599  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8080 16:44:09.832632  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8081 16:44:09.839213  iDelay=200, Bit 15, Center 131 (72 ~ 191) 120

 8082 16:44:09.839308  ==

 8083 16:44:09.842518  Dram Type= 6, Freq= 0, CH_0, rank 1

 8084 16:44:09.845844  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8085 16:44:09.845952  ==

 8086 16:44:09.846050  DQS Delay:

 8087 16:44:09.849301  DQS0 = 0, DQS1 = 0

 8088 16:44:09.849383  DQM Delay:

 8089 16:44:09.852347  DQM0 = 131, DQM1 = 125

 8090 16:44:09.852427  DQ Delay:

 8091 16:44:09.855832  DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131

 8092 16:44:09.859386  DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139

 8093 16:44:09.862184  DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119

 8094 16:44:09.869139  DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131

 8095 16:44:09.869291  

 8096 16:44:09.869396  

 8097 16:44:09.869495  ==

 8098 16:44:09.872488  Dram Type= 6, Freq= 0, CH_0, rank 1

 8099 16:44:09.875909  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8100 16:44:09.876054  ==

 8101 16:44:09.876164  

 8102 16:44:09.876259  

 8103 16:44:09.878880  	TX Vref Scan disable

 8104 16:44:09.878985   == TX Byte 0 ==

 8105 16:44:09.886010  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 8106 16:44:09.888861  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8107 16:44:09.888978   == TX Byte 1 ==

 8108 16:44:09.895308  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 8109 16:44:09.898922  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8110 16:44:09.899016  ==

 8111 16:44:09.901947  Dram Type= 6, Freq= 0, CH_0, rank 1

 8112 16:44:09.905464  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8113 16:44:09.905579  ==

 8114 16:44:09.920932  

 8115 16:44:09.924320  TX Vref early break, caculate TX vref

 8116 16:44:09.927493  TX Vref=16, minBit 3, minWin=22, winSum=371

 8117 16:44:09.930824  TX Vref=18, minBit 0, minWin=23, winSum=384

 8118 16:44:09.934396  TX Vref=20, minBit 4, minWin=23, winSum=391

 8119 16:44:09.937405  TX Vref=22, minBit 1, minWin=24, winSum=403

 8120 16:44:09.941029  TX Vref=24, minBit 4, minWin=24, winSum=413

 8121 16:44:09.947277  TX Vref=26, minBit 0, minWin=25, winSum=416

 8122 16:44:09.950814  TX Vref=28, minBit 2, minWin=25, winSum=420

 8123 16:44:09.954261  TX Vref=30, minBit 1, minWin=25, winSum=420

 8124 16:44:09.957767  TX Vref=32, minBit 0, minWin=24, winSum=414

 8125 16:44:09.960733  TX Vref=34, minBit 4, minWin=24, winSum=406

 8126 16:44:09.964243  TX Vref=36, minBit 4, minWin=23, winSum=394

 8127 16:44:09.970544  [TxChooseVref] Worse bit 2, Min win 25, Win sum 420, Final Vref 28

 8128 16:44:09.970649  

 8129 16:44:09.974591  Final TX Range 0 Vref 28

 8130 16:44:09.974700  

 8131 16:44:09.974771  ==

 8132 16:44:09.977406  Dram Type= 6, Freq= 0, CH_0, rank 1

 8133 16:44:09.981141  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8134 16:44:09.981240  ==

 8135 16:44:09.981308  

 8136 16:44:09.981371  

 8137 16:44:09.983863  	TX Vref Scan disable

 8138 16:44:09.990976  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8139 16:44:09.991082   == TX Byte 0 ==

 8140 16:44:09.994259  u2DelayCellOfst[0]=14 cells (4 PI)

 8141 16:44:09.997523  u2DelayCellOfst[1]=17 cells (5 PI)

 8142 16:44:10.001047  u2DelayCellOfst[2]=10 cells (3 PI)

 8143 16:44:10.003865  u2DelayCellOfst[3]=10 cells (3 PI)

 8144 16:44:10.007572  u2DelayCellOfst[4]=7 cells (2 PI)

 8145 16:44:10.010921  u2DelayCellOfst[5]=0 cells (0 PI)

 8146 16:44:10.014567  u2DelayCellOfst[6]=17 cells (5 PI)

 8147 16:44:10.017499  u2DelayCellOfst[7]=17 cells (5 PI)

 8148 16:44:10.020861  Update DQ  dly =988 (3 ,6, 28)  DQ  OEN =(3 ,3)

 8149 16:44:10.023881  Update DQM dly =990 (3 ,6, 30)  DQM OEN =(3 ,3)

 8150 16:44:10.027132   == TX Byte 1 ==

 8151 16:44:10.030599  u2DelayCellOfst[8]=0 cells (0 PI)

 8152 16:44:10.030685  u2DelayCellOfst[9]=0 cells (0 PI)

 8153 16:44:10.034247  u2DelayCellOfst[10]=7 cells (2 PI)

 8154 16:44:10.037808  u2DelayCellOfst[11]=0 cells (0 PI)

 8155 16:44:10.040879  u2DelayCellOfst[12]=10 cells (3 PI)

 8156 16:44:10.044459  u2DelayCellOfst[13]=10 cells (3 PI)

 8157 16:44:10.047832  u2DelayCellOfst[14]=14 cells (4 PI)

 8158 16:44:10.050717  u2DelayCellOfst[15]=10 cells (3 PI)

 8159 16:44:10.053914  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8160 16:44:10.060929  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8161 16:44:10.061050  DramC Write-DBI on

 8162 16:44:10.061142  ==

 8163 16:44:10.064309  Dram Type= 6, Freq= 0, CH_0, rank 1

 8164 16:44:10.067341  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8165 16:44:10.070556  ==

 8166 16:44:10.070652  

 8167 16:44:10.070739  

 8168 16:44:10.070821  	TX Vref Scan disable

 8169 16:44:10.074088   == TX Byte 0 ==

 8170 16:44:10.077445  Update DQM dly =734 (2 ,6, 30)  DQM OEN =(3 ,3)

 8171 16:44:10.080787   == TX Byte 1 ==

 8172 16:44:10.084547  Update DQM dly =726 (2 ,6, 22)  DQM OEN =(3 ,3)

 8173 16:44:10.087594  DramC Write-DBI off

 8174 16:44:10.087687  

 8175 16:44:10.087790  [DATLAT]

 8176 16:44:10.087899  Freq=1600, CH0 RK1

 8177 16:44:10.088039  

 8178 16:44:10.090885  DATLAT Default: 0xf

 8179 16:44:10.090982  0, 0xFFFF, sum = 0

 8180 16:44:10.094374  1, 0xFFFF, sum = 0

 8181 16:44:10.097368  2, 0xFFFF, sum = 0

 8182 16:44:10.097459  3, 0xFFFF, sum = 0

 8183 16:44:10.100550  4, 0xFFFF, sum = 0

 8184 16:44:10.100674  5, 0xFFFF, sum = 0

 8185 16:44:10.103997  6, 0xFFFF, sum = 0

 8186 16:44:10.104094  7, 0xFFFF, sum = 0

 8187 16:44:10.107588  8, 0xFFFF, sum = 0

 8188 16:44:10.107722  9, 0xFFFF, sum = 0

 8189 16:44:10.110534  10, 0xFFFF, sum = 0

 8190 16:44:10.110641  11, 0xFFFF, sum = 0

 8191 16:44:10.114025  12, 0xFFFF, sum = 0

 8192 16:44:10.114117  13, 0xFFFF, sum = 0

 8193 16:44:10.117638  14, 0x0, sum = 1

 8194 16:44:10.117729  15, 0x0, sum = 2

 8195 16:44:10.120633  16, 0x0, sum = 3

 8196 16:44:10.120725  17, 0x0, sum = 4

 8197 16:44:10.124096  best_step = 15

 8198 16:44:10.124183  

 8199 16:44:10.124268  ==

 8200 16:44:10.127720  Dram Type= 6, Freq= 0, CH_0, rank 1

 8201 16:44:10.130573  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8202 16:44:10.130685  ==

 8203 16:44:10.134374  RX Vref Scan: 0

 8204 16:44:10.134463  

 8205 16:44:10.134549  RX Vref 0 -> 0, step: 1

 8206 16:44:10.134630  

 8207 16:44:10.137302  RX Delay 11 -> 252, step: 4

 8208 16:44:10.140952  iDelay=191, Bit 0, Center 128 (75 ~ 182) 108

 8209 16:44:10.147540  iDelay=191, Bit 1, Center 130 (75 ~ 186) 112

 8210 16:44:10.150598  iDelay=191, Bit 2, Center 122 (67 ~ 178) 112

 8211 16:44:10.154200  iDelay=191, Bit 3, Center 126 (71 ~ 182) 112

 8212 16:44:10.157639  iDelay=191, Bit 4, Center 126 (75 ~ 178) 104

 8213 16:44:10.161130  iDelay=191, Bit 5, Center 114 (59 ~ 170) 112

 8214 16:44:10.167613  iDelay=191, Bit 6, Center 134 (79 ~ 190) 112

 8215 16:44:10.170508  iDelay=191, Bit 7, Center 136 (83 ~ 190) 108

 8216 16:44:10.173733  iDelay=191, Bit 8, Center 114 (59 ~ 170) 112

 8217 16:44:10.177345  iDelay=191, Bit 9, Center 110 (55 ~ 166) 112

 8218 16:44:10.180759  iDelay=191, Bit 10, Center 122 (67 ~ 178) 112

 8219 16:44:10.187608  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8220 16:44:10.190423  iDelay=191, Bit 12, Center 126 (75 ~ 178) 104

 8221 16:44:10.194065  iDelay=191, Bit 13, Center 128 (75 ~ 182) 108

 8222 16:44:10.197440  iDelay=191, Bit 14, Center 134 (79 ~ 190) 112

 8223 16:44:10.200461  iDelay=191, Bit 15, Center 132 (79 ~ 186) 108

 8224 16:44:10.203991  ==

 8225 16:44:10.207274  Dram Type= 6, Freq= 0, CH_0, rank 1

 8226 16:44:10.210359  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8227 16:44:10.210452  ==

 8228 16:44:10.210518  DQS Delay:

 8229 16:44:10.213819  DQS0 = 0, DQS1 = 0

 8230 16:44:10.213904  DQM Delay:

 8231 16:44:10.217287  DQM0 = 127, DQM1 = 123

 8232 16:44:10.217389  DQ Delay:

 8233 16:44:10.220252  DQ0 =128, DQ1 =130, DQ2 =122, DQ3 =126

 8234 16:44:10.223774  DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =136

 8235 16:44:10.227237  DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =118

 8236 16:44:10.230261  DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132

 8237 16:44:10.230352  

 8238 16:44:10.230417  

 8239 16:44:10.230477  

 8240 16:44:10.233942  [DramC_TX_OE_Calibration] TA2

 8241 16:44:10.236975  Original DQ_B0 (3 6) =30, OEN = 27

 8242 16:44:10.240558  Original DQ_B1 (3 6) =30, OEN = 27

 8243 16:44:10.243482  24, 0x0, End_B0=24 End_B1=24

 8244 16:44:10.247091  25, 0x0, End_B0=25 End_B1=25

 8245 16:44:10.247185  26, 0x0, End_B0=26 End_B1=26

 8246 16:44:10.250608  27, 0x0, End_B0=27 End_B1=27

 8247 16:44:10.253683  28, 0x0, End_B0=28 End_B1=28

 8248 16:44:10.257231  29, 0x0, End_B0=29 End_B1=29

 8249 16:44:10.260191  30, 0x0, End_B0=30 End_B1=30

 8250 16:44:10.260282  31, 0x4141, End_B0=30 End_B1=30

 8251 16:44:10.263791  Byte0 end_step=30  best_step=27

 8252 16:44:10.267303  Byte1 end_step=30  best_step=27

 8253 16:44:10.270410  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8254 16:44:10.273660  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8255 16:44:10.273755  

 8256 16:44:10.273837  

 8257 16:44:10.280138  [DQSOSCAuto] RK1, (LSB)MR18= 0x190c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps

 8258 16:44:10.283560  CH0 RK1: MR19=303, MR18=190C

 8259 16:44:10.290024  CH0_RK1: MR19=0x303, MR18=0x190C, DQSOSC=397, MR23=63, INC=23, DEC=15

 8260 16:44:10.293394  [RxdqsGatingPostProcess] freq 1600

 8261 16:44:10.300262  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8262 16:44:10.300380  best DQS0 dly(2T, 0.5T) = (1, 1)

 8263 16:44:10.303108  best DQS1 dly(2T, 0.5T) = (1, 1)

 8264 16:44:10.306822  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8265 16:44:10.310138  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8266 16:44:10.313680  best DQS0 dly(2T, 0.5T) = (1, 1)

 8267 16:44:10.316729  best DQS1 dly(2T, 0.5T) = (1, 1)

 8268 16:44:10.319845  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8269 16:44:10.323177  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8270 16:44:10.326650  Pre-setting of DQS Precalculation

 8271 16:44:10.330367  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8272 16:44:10.330487  ==

 8273 16:44:10.333207  Dram Type= 6, Freq= 0, CH_1, rank 0

 8274 16:44:10.339778  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8275 16:44:10.339888  ==

 8276 16:44:10.343370  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8277 16:44:10.350029  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8278 16:44:10.353015  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8279 16:44:10.359531  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8280 16:44:10.367565  [CA 0] Center 42 (13~71) winsize 59

 8281 16:44:10.370565  [CA 1] Center 42 (13~71) winsize 59

 8282 16:44:10.373908  [CA 2] Center 37 (9~66) winsize 58

 8283 16:44:10.377740  [CA 3] Center 36 (7~65) winsize 59

 8284 16:44:10.380353  [CA 4] Center 37 (7~67) winsize 61

 8285 16:44:10.383818  [CA 5] Center 36 (7~66) winsize 60

 8286 16:44:10.383933  

 8287 16:44:10.387228  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8288 16:44:10.387303  

 8289 16:44:10.390421  [CATrainingPosCal] consider 1 rank data

 8290 16:44:10.393853  u2DelayCellTimex100 = 275/100 ps

 8291 16:44:10.397503  CA0 delay=42 (13~71),Diff = 6 PI (21 cell)

 8292 16:44:10.403762  CA1 delay=42 (13~71),Diff = 6 PI (21 cell)

 8293 16:44:10.407208  CA2 delay=37 (9~66),Diff = 1 PI (3 cell)

 8294 16:44:10.410137  CA3 delay=36 (7~65),Diff = 0 PI (0 cell)

 8295 16:44:10.413532  CA4 delay=37 (7~67),Diff = 1 PI (3 cell)

 8296 16:44:10.417143  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8297 16:44:10.417239  

 8298 16:44:10.420154  CA PerBit enable=1, Macro0, CA PI delay=36

 8299 16:44:10.420237  

 8300 16:44:10.423827  [CBTSetCACLKResult] CA Dly = 36

 8301 16:44:10.426813  CS Dly: 9 (0~40)

 8302 16:44:10.430803  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8303 16:44:10.433768  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8304 16:44:10.433865  ==

 8305 16:44:10.436812  Dram Type= 6, Freq= 0, CH_1, rank 1

 8306 16:44:10.440365  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8307 16:44:10.443921  ==

 8308 16:44:10.446955  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8309 16:44:10.450569  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8310 16:44:10.457201  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8311 16:44:10.460209  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8312 16:44:10.470523  [CA 0] Center 43 (14~72) winsize 59

 8313 16:44:10.473942  [CA 1] Center 43 (14~72) winsize 59

 8314 16:44:10.476845  [CA 2] Center 38 (9~67) winsize 59

 8315 16:44:10.480280  [CA 3] Center 37 (8~66) winsize 59

 8316 16:44:10.483725  [CA 4] Center 38 (9~68) winsize 60

 8317 16:44:10.487039  [CA 5] Center 37 (8~66) winsize 59

 8318 16:44:10.487156  

 8319 16:44:10.490569  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8320 16:44:10.490656  

 8321 16:44:10.493504  [CATrainingPosCal] consider 2 rank data

 8322 16:44:10.496893  u2DelayCellTimex100 = 275/100 ps

 8323 16:44:10.500349  CA0 delay=42 (14~71),Diff = 6 PI (21 cell)

 8324 16:44:10.506704  CA1 delay=42 (14~71),Diff = 6 PI (21 cell)

 8325 16:44:10.510078  CA2 delay=37 (9~66),Diff = 1 PI (3 cell)

 8326 16:44:10.513505  CA3 delay=36 (8~65),Diff = 0 PI (0 cell)

 8327 16:44:10.516944  CA4 delay=38 (9~67),Diff = 2 PI (7 cell)

 8328 16:44:10.519868  CA5 delay=37 (8~66),Diff = 1 PI (3 cell)

 8329 16:44:10.519972  

 8330 16:44:10.523546  CA PerBit enable=1, Macro0, CA PI delay=36

 8331 16:44:10.523633  

 8332 16:44:10.527051  [CBTSetCACLKResult] CA Dly = 36

 8333 16:44:10.530473  CS Dly: 10 (0~43)

 8334 16:44:10.533353  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8335 16:44:10.536700  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8336 16:44:10.536792  

 8337 16:44:10.540214  ----->DramcWriteLeveling(PI) begin...

 8338 16:44:10.540303  ==

 8339 16:44:10.543389  Dram Type= 6, Freq= 0, CH_1, rank 0

 8340 16:44:10.546914  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8341 16:44:10.549931  ==

 8342 16:44:10.550022  Write leveling (Byte 0): 24 => 24

 8343 16:44:10.553471  Write leveling (Byte 1): 27 => 27

 8344 16:44:10.557027  DramcWriteLeveling(PI) end<-----

 8345 16:44:10.557121  

 8346 16:44:10.557185  ==

 8347 16:44:10.559860  Dram Type= 6, Freq= 0, CH_1, rank 0

 8348 16:44:10.567172  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8349 16:44:10.567278  ==

 8350 16:44:10.570051  [Gating] SW mode calibration

 8351 16:44:10.576528  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8352 16:44:10.580313  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8353 16:44:10.586566   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8354 16:44:10.590104   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8355 16:44:10.593290   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8356 16:44:10.599995   1  4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8357 16:44:10.603317   1  4 16 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)

 8358 16:44:10.606932   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8359 16:44:10.609683   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8360 16:44:10.616592   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8361 16:44:10.620257   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8362 16:44:10.623100   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8363 16:44:10.630220   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8364 16:44:10.633184   1  5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8365 16:44:10.636186   1  5 16 | B1->B0 | 3131 3333 | 0 1 | (0 1) (1 0)

 8366 16:44:10.643035   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8367 16:44:10.646581   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8368 16:44:10.649680   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8369 16:44:10.656174   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8370 16:44:10.659920   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8371 16:44:10.662921   1  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8372 16:44:10.669738   1  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8373 16:44:10.673173   1  6 16 | B1->B0 | 3d3d 2e2e | 0 1 | (0 0) (0 0)

 8374 16:44:10.676131   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8375 16:44:10.682680   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8376 16:44:10.686243   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8377 16:44:10.689267   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8378 16:44:10.696059   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8379 16:44:10.699505   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8380 16:44:10.702972   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8381 16:44:10.709335   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8382 16:44:10.712917   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8383 16:44:10.716110   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8384 16:44:10.723073   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8385 16:44:10.725859   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8386 16:44:10.729339   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8387 16:44:10.735782   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8388 16:44:10.739391   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8389 16:44:10.742880   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8390 16:44:10.749459   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8391 16:44:10.753054   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8392 16:44:10.755829   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8393 16:44:10.762528   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8394 16:44:10.766092   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8395 16:44:10.769087   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8396 16:44:10.772730   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8397 16:44:10.779069   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8398 16:44:10.782676   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8399 16:44:10.786226  Total UI for P1: 0, mck2ui 16

 8400 16:44:10.789160  best dqsien dly found for B0: ( 1,  9, 16)

 8401 16:44:10.792679  Total UI for P1: 0, mck2ui 16

 8402 16:44:10.795951  best dqsien dly found for B1: ( 1,  9, 16)

 8403 16:44:10.798822  best DQS0 dly(MCK, UI, PI) = (1, 9, 16)

 8404 16:44:10.802285  best DQS1 dly(MCK, UI, PI) = (1, 9, 16)

 8405 16:44:10.802383  

 8406 16:44:10.805806  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)

 8407 16:44:10.812672  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)

 8408 16:44:10.812779  [Gating] SW calibration Done

 8409 16:44:10.812851  ==

 8410 16:44:10.816036  Dram Type= 6, Freq= 0, CH_1, rank 0

 8411 16:44:10.822595  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8412 16:44:10.822746  ==

 8413 16:44:10.822836  RX Vref Scan: 0

 8414 16:44:10.822913  

 8415 16:44:10.825675  RX Vref 0 -> 0, step: 1

 8416 16:44:10.825763  

 8417 16:44:10.829109  RX Delay 0 -> 252, step: 8

 8418 16:44:10.832494  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8419 16:44:10.836059  iDelay=208, Bit 1, Center 127 (72 ~ 183) 112

 8420 16:44:10.838830  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8421 16:44:10.842331  iDelay=208, Bit 3, Center 135 (80 ~ 191) 112

 8422 16:44:10.849021  iDelay=208, Bit 4, Center 135 (80 ~ 191) 112

 8423 16:44:10.852766  iDelay=208, Bit 5, Center 147 (88 ~ 207) 120

 8424 16:44:10.855704  iDelay=208, Bit 6, Center 143 (96 ~ 191) 96

 8425 16:44:10.859433  iDelay=208, Bit 7, Center 127 (72 ~ 183) 112

 8426 16:44:10.862148  iDelay=208, Bit 8, Center 111 (56 ~ 167) 112

 8427 16:44:10.869159  iDelay=208, Bit 9, Center 115 (64 ~ 167) 104

 8428 16:44:10.872196  iDelay=208, Bit 10, Center 127 (72 ~ 183) 112

 8429 16:44:10.875733  iDelay=208, Bit 11, Center 123 (72 ~ 175) 104

 8430 16:44:10.878825  iDelay=208, Bit 12, Center 135 (80 ~ 191) 112

 8431 16:44:10.882278  iDelay=208, Bit 13, Center 135 (80 ~ 191) 112

 8432 16:44:10.888740  iDelay=208, Bit 14, Center 135 (80 ~ 191) 112

 8433 16:44:10.892272  iDelay=208, Bit 15, Center 135 (80 ~ 191) 112

 8434 16:44:10.892423  ==

 8435 16:44:10.895238  Dram Type= 6, Freq= 0, CH_1, rank 0

 8436 16:44:10.898708  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8437 16:44:10.898819  ==

 8438 16:44:10.902081  DQS Delay:

 8439 16:44:10.902187  DQS0 = 0, DQS1 = 0

 8440 16:44:10.902280  DQM Delay:

 8441 16:44:10.905469  DQM0 = 134, DQM1 = 127

 8442 16:44:10.905583  DQ Delay:

 8443 16:44:10.908813  DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135

 8444 16:44:10.912393  DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =127

 8445 16:44:10.918620  DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123

 8446 16:44:10.922163  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8447 16:44:10.922290  

 8448 16:44:10.922386  

 8449 16:44:10.922475  ==

 8450 16:44:10.925512  Dram Type= 6, Freq= 0, CH_1, rank 0

 8451 16:44:10.929080  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8452 16:44:10.929172  ==

 8453 16:44:10.929239  

 8454 16:44:10.929301  

 8455 16:44:10.931904  	TX Vref Scan disable

 8456 16:44:10.932042   == TX Byte 0 ==

 8457 16:44:10.939031  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8458 16:44:10.941795  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8459 16:44:10.941894   == TX Byte 1 ==

 8460 16:44:10.948418  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8461 16:44:10.951911  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8462 16:44:10.952048  ==

 8463 16:44:10.955416  Dram Type= 6, Freq= 0, CH_1, rank 0

 8464 16:44:10.958452  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8465 16:44:10.958567  ==

 8466 16:44:10.974104  

 8467 16:44:10.976940  TX Vref early break, caculate TX vref

 8468 16:44:10.980591  TX Vref=16, minBit 8, minWin=21, winSum=365

 8469 16:44:10.983511  TX Vref=18, minBit 5, minWin=22, winSum=376

 8470 16:44:10.987015  TX Vref=20, minBit 8, minWin=22, winSum=385

 8471 16:44:10.990528  TX Vref=22, minBit 8, minWin=23, winSum=392

 8472 16:44:10.993610  TX Vref=24, minBit 5, minWin=24, winSum=406

 8473 16:44:11.000550  TX Vref=26, minBit 5, minWin=24, winSum=412

 8474 16:44:11.003511  TX Vref=28, minBit 1, minWin=25, winSum=421

 8475 16:44:11.006946  TX Vref=30, minBit 9, minWin=25, winSum=420

 8476 16:44:11.009965  TX Vref=32, minBit 0, minWin=25, winSum=413

 8477 16:44:11.013608  TX Vref=34, minBit 1, minWin=24, winSum=400

 8478 16:44:11.016868  TX Vref=36, minBit 1, minWin=23, winSum=390

 8479 16:44:11.023240  [TxChooseVref] Worse bit 1, Min win 25, Win sum 421, Final Vref 28

 8480 16:44:11.023382  

 8481 16:44:11.026649  Final TX Range 0 Vref 28

 8482 16:44:11.026771  

 8483 16:44:11.026875  ==

 8484 16:44:11.029949  Dram Type= 6, Freq= 0, CH_1, rank 0

 8485 16:44:11.033573  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8486 16:44:11.033674  ==

 8487 16:44:11.033744  

 8488 16:44:11.033804  

 8489 16:44:11.036573  	TX Vref Scan disable

 8490 16:44:11.043400  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8491 16:44:11.043511   == TX Byte 0 ==

 8492 16:44:11.046367  u2DelayCellOfst[0]=17 cells (5 PI)

 8493 16:44:11.049965  u2DelayCellOfst[1]=10 cells (3 PI)

 8494 16:44:11.053472  u2DelayCellOfst[2]=0 cells (0 PI)

 8495 16:44:11.056423  u2DelayCellOfst[3]=7 cells (2 PI)

 8496 16:44:11.059916  u2DelayCellOfst[4]=7 cells (2 PI)

 8497 16:44:11.063474  u2DelayCellOfst[5]=21 cells (6 PI)

 8498 16:44:11.066366  u2DelayCellOfst[6]=17 cells (5 PI)

 8499 16:44:11.069851  u2DelayCellOfst[7]=7 cells (2 PI)

 8500 16:44:11.072865  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8501 16:44:11.076423  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8502 16:44:11.080133   == TX Byte 1 ==

 8503 16:44:11.083089  u2DelayCellOfst[8]=0 cells (0 PI)

 8504 16:44:11.083238  u2DelayCellOfst[9]=7 cells (2 PI)

 8505 16:44:11.086517  u2DelayCellOfst[10]=10 cells (3 PI)

 8506 16:44:11.089597  u2DelayCellOfst[11]=7 cells (2 PI)

 8507 16:44:11.093110  u2DelayCellOfst[12]=14 cells (4 PI)

 8508 16:44:11.096602  u2DelayCellOfst[13]=14 cells (4 PI)

 8509 16:44:11.099452  u2DelayCellOfst[14]=17 cells (5 PI)

 8510 16:44:11.103056  u2DelayCellOfst[15]=17 cells (5 PI)

 8511 16:44:11.109526  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8512 16:44:11.112947  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8513 16:44:11.113068  DramC Write-DBI on

 8514 16:44:11.113161  ==

 8515 16:44:11.116337  Dram Type= 6, Freq= 0, CH_1, rank 0

 8516 16:44:11.122719  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8517 16:44:11.122827  ==

 8518 16:44:11.122958  

 8519 16:44:11.123054  

 8520 16:44:11.123118  	TX Vref Scan disable

 8521 16:44:11.126699   == TX Byte 0 ==

 8522 16:44:11.130100  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8523 16:44:11.133577   == TX Byte 1 ==

 8524 16:44:11.136980  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8525 16:44:11.139927  DramC Write-DBI off

 8526 16:44:11.140118  

 8527 16:44:11.140247  [DATLAT]

 8528 16:44:11.140371  Freq=1600, CH1 RK0

 8529 16:44:11.140494  

 8530 16:44:11.143424  DATLAT Default: 0xf

 8531 16:44:11.143526  0, 0xFFFF, sum = 0

 8532 16:44:11.146289  1, 0xFFFF, sum = 0

 8533 16:44:11.149812  2, 0xFFFF, sum = 0

 8534 16:44:11.149942  3, 0xFFFF, sum = 0

 8535 16:44:11.153432  4, 0xFFFF, sum = 0

 8536 16:44:11.153608  5, 0xFFFF, sum = 0

 8537 16:44:11.156515  6, 0xFFFF, sum = 0

 8538 16:44:11.156620  7, 0xFFFF, sum = 0

 8539 16:44:11.159932  8, 0xFFFF, sum = 0

 8540 16:44:11.160061  9, 0xFFFF, sum = 0

 8541 16:44:11.163590  10, 0xFFFF, sum = 0

 8542 16:44:11.163683  11, 0xFFFF, sum = 0

 8543 16:44:11.166471  12, 0xFFFF, sum = 0

 8544 16:44:11.166576  13, 0xFFFF, sum = 0

 8545 16:44:11.170052  14, 0x0, sum = 1

 8546 16:44:11.170152  15, 0x0, sum = 2

 8547 16:44:11.173086  16, 0x0, sum = 3

 8548 16:44:11.173183  17, 0x0, sum = 4

 8549 16:44:11.176594  best_step = 15

 8550 16:44:11.176731  

 8551 16:44:11.176842  ==

 8552 16:44:11.179828  Dram Type= 6, Freq= 0, CH_1, rank 0

 8553 16:44:11.182660  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8554 16:44:11.182762  ==

 8555 16:44:11.186233  RX Vref Scan: 1

 8556 16:44:11.186337  

 8557 16:44:11.186407  Set Vref Range= 24 -> 127

 8558 16:44:11.186471  

 8559 16:44:11.189784  RX Vref 24 -> 127, step: 1

 8560 16:44:11.189873  

 8561 16:44:11.192845  RX Delay 11 -> 252, step: 4

 8562 16:44:11.192933  

 8563 16:44:11.195952  Set Vref, RX VrefLevel [Byte0]: 24

 8564 16:44:11.199341                           [Byte1]: 24

 8565 16:44:11.199437  

 8566 16:44:11.202732  Set Vref, RX VrefLevel [Byte0]: 25

 8567 16:44:11.206292                           [Byte1]: 25

 8568 16:44:11.209725  

 8569 16:44:11.209824  Set Vref, RX VrefLevel [Byte0]: 26

 8570 16:44:11.212920                           [Byte1]: 26

 8571 16:44:11.217106  

 8572 16:44:11.217208  Set Vref, RX VrefLevel [Byte0]: 27

 8573 16:44:11.220654                           [Byte1]: 27

 8574 16:44:11.224605  

 8575 16:44:11.224704  Set Vref, RX VrefLevel [Byte0]: 28

 8576 16:44:11.227917                           [Byte1]: 28

 8577 16:44:11.232622  

 8578 16:44:11.232725  Set Vref, RX VrefLevel [Byte0]: 29

 8579 16:44:11.235566                           [Byte1]: 29

 8580 16:44:11.240165  

 8581 16:44:11.240263  Set Vref, RX VrefLevel [Byte0]: 30

 8582 16:44:11.243292                           [Byte1]: 30

 8583 16:44:11.247914  

 8584 16:44:11.248025  Set Vref, RX VrefLevel [Byte0]: 31

 8585 16:44:11.250613                           [Byte1]: 31

 8586 16:44:11.254973  

 8587 16:44:11.255070  Set Vref, RX VrefLevel [Byte0]: 32

 8588 16:44:11.258459                           [Byte1]: 32

 8589 16:44:11.262790  

 8590 16:44:11.262904  Set Vref, RX VrefLevel [Byte0]: 33

 8591 16:44:11.266379                           [Byte1]: 33

 8592 16:44:11.270428  

 8593 16:44:11.270547  Set Vref, RX VrefLevel [Byte0]: 34

 8594 16:44:11.274161                           [Byte1]: 34

 8595 16:44:11.278139  

 8596 16:44:11.278261  Set Vref, RX VrefLevel [Byte0]: 35

 8597 16:44:11.281232                           [Byte1]: 35

 8598 16:44:11.285862  

 8599 16:44:11.285950  Set Vref, RX VrefLevel [Byte0]: 36

 8600 16:44:11.288946                           [Byte1]: 36

 8601 16:44:11.293047  

 8602 16:44:11.293142  Set Vref, RX VrefLevel [Byte0]: 37

 8603 16:44:11.296545                           [Byte1]: 37

 8604 16:44:11.300755  

 8605 16:44:11.300849  Set Vref, RX VrefLevel [Byte0]: 38

 8606 16:44:11.304173                           [Byte1]: 38

 8607 16:44:11.308403  

 8608 16:44:11.308508  Set Vref, RX VrefLevel [Byte0]: 39

 8609 16:44:11.311922                           [Byte1]: 39

 8610 16:44:11.315941  

 8611 16:44:11.316107  Set Vref, RX VrefLevel [Byte0]: 40

 8612 16:44:11.319551                           [Byte1]: 40

 8613 16:44:11.323643  

 8614 16:44:11.323736  Set Vref, RX VrefLevel [Byte0]: 41

 8615 16:44:11.327231                           [Byte1]: 41

 8616 16:44:11.331160  

 8617 16:44:11.331262  Set Vref, RX VrefLevel [Byte0]: 42

 8618 16:44:11.334620                           [Byte1]: 42

 8619 16:44:11.339127  

 8620 16:44:11.339262  Set Vref, RX VrefLevel [Byte0]: 43

 8621 16:44:11.342209                           [Byte1]: 43

 8622 16:44:11.346742  

 8623 16:44:11.346833  Set Vref, RX VrefLevel [Byte0]: 44

 8624 16:44:11.349680                           [Byte1]: 44

 8625 16:44:11.354299  

 8626 16:44:11.354394  Set Vref, RX VrefLevel [Byte0]: 45

 8627 16:44:11.357592                           [Byte1]: 45

 8628 16:44:11.361725  

 8629 16:44:11.361812  Set Vref, RX VrefLevel [Byte0]: 46

 8630 16:44:11.365246                           [Byte1]: 46

 8631 16:44:11.369359  

 8632 16:44:11.369452  Set Vref, RX VrefLevel [Byte0]: 47

 8633 16:44:11.372899                           [Byte1]: 47

 8634 16:44:11.376945  

 8635 16:44:11.377099  Set Vref, RX VrefLevel [Byte0]: 48

 8636 16:44:11.380614                           [Byte1]: 48

 8637 16:44:11.384896  

 8638 16:44:11.384995  Set Vref, RX VrefLevel [Byte0]: 49

 8639 16:44:11.387720                           [Byte1]: 49

 8640 16:44:11.392480  

 8641 16:44:11.392574  Set Vref, RX VrefLevel [Byte0]: 50

 8642 16:44:11.395393                           [Byte1]: 50

 8643 16:44:11.399752  

 8644 16:44:11.399863  Set Vref, RX VrefLevel [Byte0]: 51

 8645 16:44:11.403225                           [Byte1]: 51

 8646 16:44:11.407311  

 8647 16:44:11.407418  Set Vref, RX VrefLevel [Byte0]: 52

 8648 16:44:11.410642                           [Byte1]: 52

 8649 16:44:11.415493  

 8650 16:44:11.415590  Set Vref, RX VrefLevel [Byte0]: 53

 8651 16:44:11.418442                           [Byte1]: 53

 8652 16:44:11.422548  

 8653 16:44:11.422641  Set Vref, RX VrefLevel [Byte0]: 54

 8654 16:44:11.425982                           [Byte1]: 54

 8655 16:44:11.430377  

 8656 16:44:11.430501  Set Vref, RX VrefLevel [Byte0]: 55

 8657 16:44:11.433761                           [Byte1]: 55

 8658 16:44:11.437936  

 8659 16:44:11.438048  Set Vref, RX VrefLevel [Byte0]: 56

 8660 16:44:11.441222                           [Byte1]: 56

 8661 16:44:11.445314  

 8662 16:44:11.445451  Set Vref, RX VrefLevel [Byte0]: 57

 8663 16:44:11.448842                           [Byte1]: 57

 8664 16:44:11.453452  

 8665 16:44:11.453563  Set Vref, RX VrefLevel [Byte0]: 58

 8666 16:44:11.456338                           [Byte1]: 58

 8667 16:44:11.460803  

 8668 16:44:11.460896  Set Vref, RX VrefLevel [Byte0]: 59

 8669 16:44:11.464280                           [Byte1]: 59

 8670 16:44:11.468394  

 8671 16:44:11.468478  Set Vref, RX VrefLevel [Byte0]: 60

 8672 16:44:11.471915                           [Byte1]: 60

 8673 16:44:11.476175  

 8674 16:44:11.476299  Set Vref, RX VrefLevel [Byte0]: 61

 8675 16:44:11.479061                           [Byte1]: 61

 8676 16:44:11.483788  

 8677 16:44:11.483877  Set Vref, RX VrefLevel [Byte0]: 62

 8678 16:44:11.486856                           [Byte1]: 62

 8679 16:44:11.491045  

 8680 16:44:11.491155  Set Vref, RX VrefLevel [Byte0]: 63

 8681 16:44:11.494497                           [Byte1]: 63

 8682 16:44:11.498740  

 8683 16:44:11.498841  Set Vref, RX VrefLevel [Byte0]: 64

 8684 16:44:11.502204                           [Byte1]: 64

 8685 16:44:11.506368  

 8686 16:44:11.506505  Set Vref, RX VrefLevel [Byte0]: 65

 8687 16:44:11.510077                           [Byte1]: 65

 8688 16:44:11.514087  

 8689 16:44:11.514181  Set Vref, RX VrefLevel [Byte0]: 66

 8690 16:44:11.517464                           [Byte1]: 66

 8691 16:44:11.521633  

 8692 16:44:11.521749  Set Vref, RX VrefLevel [Byte0]: 67

 8693 16:44:11.525011                           [Byte1]: 67

 8694 16:44:11.529059  

 8695 16:44:11.529172  Set Vref, RX VrefLevel [Byte0]: 68

 8696 16:44:11.532353                           [Byte1]: 68

 8697 16:44:11.537023  

 8698 16:44:11.537152  Set Vref, RX VrefLevel [Byte0]: 69

 8699 16:44:11.540580                           [Byte1]: 69

 8700 16:44:11.544477  

 8701 16:44:11.548337  Set Vref, RX VrefLevel [Byte0]: 70

 8702 16:44:11.548463                           [Byte1]: 70

 8703 16:44:11.551936  

 8704 16:44:11.552109  Set Vref, RX VrefLevel [Byte0]: 71

 8705 16:44:11.555468                           [Byte1]: 71

 8706 16:44:11.559772  

 8707 16:44:11.559892  Set Vref, RX VrefLevel [Byte0]: 72

 8708 16:44:11.566596                           [Byte1]: 72

 8709 16:44:11.566772  

 8710 16:44:11.569524  Set Vref, RX VrefLevel [Byte0]: 73

 8711 16:44:11.572651                           [Byte1]: 73

 8712 16:44:11.572842  

 8713 16:44:11.576423  Set Vref, RX VrefLevel [Byte0]: 74

 8714 16:44:11.579471                           [Byte1]: 74

 8715 16:44:11.579601  

 8716 16:44:11.583107  Final RX Vref Byte 0 = 62 to rank0

 8717 16:44:11.585974  Final RX Vref Byte 1 = 54 to rank0

 8718 16:44:11.589590  Final RX Vref Byte 0 = 62 to rank1

 8719 16:44:11.593022  Final RX Vref Byte 1 = 54 to rank1==

 8720 16:44:11.595941  Dram Type= 6, Freq= 0, CH_1, rank 0

 8721 16:44:11.599590  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8722 16:44:11.602782  ==

 8723 16:44:11.602916  DQS Delay:

 8724 16:44:11.603009  DQS0 = 0, DQS1 = 0

 8725 16:44:11.606247  DQM Delay:

 8726 16:44:11.606357  DQM0 = 132, DQM1 = 124

 8727 16:44:11.609259  DQ Delay:

 8728 16:44:11.612919  DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =132

 8729 16:44:11.615855  DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126

 8730 16:44:11.619340  DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120

 8731 16:44:11.622352  DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132

 8732 16:44:11.622469  

 8733 16:44:11.622563  

 8734 16:44:11.622655  

 8735 16:44:11.625902  [DramC_TX_OE_Calibration] TA2

 8736 16:44:11.629416  Original DQ_B0 (3 6) =30, OEN = 27

 8737 16:44:11.632420  Original DQ_B1 (3 6) =30, OEN = 27

 8738 16:44:11.635886  24, 0x0, End_B0=24 End_B1=24

 8739 16:44:11.636054  25, 0x0, End_B0=25 End_B1=25

 8740 16:44:11.638824  26, 0x0, End_B0=26 End_B1=26

 8741 16:44:11.642285  27, 0x0, End_B0=27 End_B1=27

 8742 16:44:11.645747  28, 0x0, End_B0=28 End_B1=28

 8743 16:44:11.649028  29, 0x0, End_B0=29 End_B1=29

 8744 16:44:11.649162  30, 0x0, End_B0=30 End_B1=30

 8745 16:44:11.652499  31, 0x4141, End_B0=30 End_B1=30

 8746 16:44:11.655394  Byte0 end_step=30  best_step=27

 8747 16:44:11.658895  Byte1 end_step=30  best_step=27

 8748 16:44:11.662427  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8749 16:44:11.665450  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8750 16:44:11.665544  

 8751 16:44:11.665610  

 8752 16:44:11.672288  [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps

 8753 16:44:11.675935  CH1 RK0: MR19=302, MR18=14FE

 8754 16:44:11.682365  CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15

 8755 16:44:11.682488  

 8756 16:44:11.685373  ----->DramcWriteLeveling(PI) begin...

 8757 16:44:11.685462  ==

 8758 16:44:11.688829  Dram Type= 6, Freq= 0, CH_1, rank 1

 8759 16:44:11.692369  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8760 16:44:11.692465  ==

 8761 16:44:11.695331  Write leveling (Byte 0): 27 => 27

 8762 16:44:11.699010  Write leveling (Byte 1): 27 => 27

 8763 16:44:11.701998  DramcWriteLeveling(PI) end<-----

 8764 16:44:11.702087  

 8765 16:44:11.702152  ==

 8766 16:44:11.705485  Dram Type= 6, Freq= 0, CH_1, rank 1

 8767 16:44:11.708930  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8768 16:44:11.709029  ==

 8769 16:44:11.711844  [Gating] SW mode calibration

 8770 16:44:11.718575  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8771 16:44:11.725536  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8772 16:44:11.728798   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8773 16:44:11.732156   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8774 16:44:11.738471   1  4  8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 8775 16:44:11.742074   1  4 12 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)

 8776 16:44:11.745528   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8777 16:44:11.752242   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8778 16:44:11.755050   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8779 16:44:11.758593   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8780 16:44:11.765406   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8781 16:44:11.768492   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8782 16:44:11.771917   1  5  8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)

 8783 16:44:11.778451   1  5 12 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)

 8784 16:44:11.782037   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8785 16:44:11.785099   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8786 16:44:11.791472   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8787 16:44:11.795070   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8788 16:44:11.798095   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8789 16:44:11.805362   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 8790 16:44:11.808166   1  6  8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)

 8791 16:44:11.811824   1  6 12 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)

 8792 16:44:11.818327   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8793 16:44:11.821873   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8794 16:44:11.824832   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8795 16:44:11.831877   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8796 16:44:11.834727   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8797 16:44:11.838249   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8798 16:44:11.844559   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8799 16:44:11.848007   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8800 16:44:11.851343   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8801 16:44:11.858220   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8802 16:44:11.861100   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8803 16:44:11.864540   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8804 16:44:11.871265   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8805 16:44:11.874802   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8806 16:44:11.877691   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8807 16:44:11.881123   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8808 16:44:11.888055   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8809 16:44:11.891032   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8810 16:44:11.894481   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8811 16:44:11.901444   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8812 16:44:11.904431   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8813 16:44:11.908100   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8814 16:44:11.914605   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 8815 16:44:11.917647   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 8816 16:44:11.921232  Total UI for P1: 0, mck2ui 16

 8817 16:44:11.924698  best dqsien dly found for B0: ( 1,  9,  6)

 8818 16:44:11.927698   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8819 16:44:11.930883  Total UI for P1: 0, mck2ui 16

 8820 16:44:11.934492  best dqsien dly found for B1: ( 1,  9, 12)

 8821 16:44:11.937892  best DQS0 dly(MCK, UI, PI) = (1, 9, 6)

 8822 16:44:11.940755  best DQS1 dly(MCK, UI, PI) = (1, 9, 12)

 8823 16:44:11.940847  

 8824 16:44:11.947860  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8825 16:44:11.951238  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8826 16:44:11.954119  [Gating] SW calibration Done

 8827 16:44:11.954214  ==

 8828 16:44:11.957511  Dram Type= 6, Freq= 0, CH_1, rank 1

 8829 16:44:11.960897  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8830 16:44:11.960999  ==

 8831 16:44:11.961078  RX Vref Scan: 0

 8832 16:44:11.961152  

 8833 16:44:11.964382  RX Vref 0 -> 0, step: 1

 8834 16:44:11.964471  

 8835 16:44:11.967778  RX Delay 0 -> 252, step: 8

 8836 16:44:11.971088  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8837 16:44:11.974175  iDelay=200, Bit 1, Center 127 (72 ~ 183) 112

 8838 16:44:11.977748  iDelay=200, Bit 2, Center 119 (64 ~ 175) 112

 8839 16:44:11.984157  iDelay=200, Bit 3, Center 131 (72 ~ 191) 120

 8840 16:44:11.987633  iDelay=200, Bit 4, Center 131 (72 ~ 191) 120

 8841 16:44:11.991208  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8842 16:44:11.994306  iDelay=200, Bit 6, Center 139 (80 ~ 199) 120

 8843 16:44:11.997716  iDelay=200, Bit 7, Center 127 (72 ~ 183) 112

 8844 16:44:12.004207  iDelay=200, Bit 8, Center 115 (56 ~ 175) 120

 8845 16:44:12.007204  iDelay=200, Bit 9, Center 115 (56 ~ 175) 120

 8846 16:44:12.010678  iDelay=200, Bit 10, Center 131 (72 ~ 191) 120

 8847 16:44:12.014311  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8848 16:44:12.020869  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8849 16:44:12.023892  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8850 16:44:12.027416  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8851 16:44:12.030511  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8852 16:44:12.030604  ==

 8853 16:44:12.033947  Dram Type= 6, Freq= 0, CH_1, rank 1

 8854 16:44:12.037492  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8855 16:44:12.040978  ==

 8856 16:44:12.041072  DQS Delay:

 8857 16:44:12.041150  DQS0 = 0, DQS1 = 0

 8858 16:44:12.043766  DQM Delay:

 8859 16:44:12.043867  DQM0 = 132, DQM1 = 127

 8860 16:44:12.047293  DQ Delay:

 8861 16:44:12.050831  DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131

 8862 16:44:12.053630  DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127

 8863 16:44:12.057038  DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119

 8864 16:44:12.060577  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8865 16:44:12.060670  

 8866 16:44:12.060737  

 8867 16:44:12.060798  ==

 8868 16:44:12.063771  Dram Type= 6, Freq= 0, CH_1, rank 1

 8869 16:44:12.067198  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8870 16:44:12.067286  ==

 8871 16:44:12.070756  

 8872 16:44:12.070844  

 8873 16:44:12.070912  	TX Vref Scan disable

 8874 16:44:12.073625   == TX Byte 0 ==

 8875 16:44:12.077268  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 8876 16:44:12.080124  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8877 16:44:12.083570   == TX Byte 1 ==

 8878 16:44:12.087051  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8879 16:44:12.090494  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8880 16:44:12.090588  ==

 8881 16:44:12.093569  Dram Type= 6, Freq= 0, CH_1, rank 1

 8882 16:44:12.100617  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8883 16:44:12.100752  ==

 8884 16:44:12.111749  

 8885 16:44:12.114761  TX Vref early break, caculate TX vref

 8886 16:44:12.118352  TX Vref=16, minBit 5, minWin=22, winSum=373

 8887 16:44:12.121519  TX Vref=18, minBit 8, minWin=23, winSum=389

 8888 16:44:12.125076  TX Vref=20, minBit 8, minWin=23, winSum=393

 8889 16:44:12.128044  TX Vref=22, minBit 1, minWin=24, winSum=400

 8890 16:44:12.131575  TX Vref=24, minBit 8, minWin=24, winSum=408

 8891 16:44:12.138258  TX Vref=26, minBit 11, minWin=25, winSum=421

 8892 16:44:12.141574  TX Vref=28, minBit 3, minWin=25, winSum=425

 8893 16:44:12.145007  TX Vref=30, minBit 0, minWin=25, winSum=416

 8894 16:44:12.148626  TX Vref=32, minBit 0, minWin=25, winSum=417

 8895 16:44:12.151467  TX Vref=34, minBit 3, minWin=24, winSum=401

 8896 16:44:12.158370  [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 28

 8897 16:44:12.158485  

 8898 16:44:12.161853  Final TX Range 0 Vref 28

 8899 16:44:12.161942  

 8900 16:44:12.162008  ==

 8901 16:44:12.164856  Dram Type= 6, Freq= 0, CH_1, rank 1

 8902 16:44:12.168123  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8903 16:44:12.168214  ==

 8904 16:44:12.168283  

 8905 16:44:12.168346  

 8906 16:44:12.171517  	TX Vref Scan disable

 8907 16:44:12.177988  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps

 8908 16:44:12.178097   == TX Byte 0 ==

 8909 16:44:12.181338  u2DelayCellOfst[0]=17 cells (5 PI)

 8910 16:44:12.184759  u2DelayCellOfst[1]=10 cells (3 PI)

 8911 16:44:12.188348  u2DelayCellOfst[2]=0 cells (0 PI)

 8912 16:44:12.191806  u2DelayCellOfst[3]=7 cells (2 PI)

 8913 16:44:12.194561  u2DelayCellOfst[4]=7 cells (2 PI)

 8914 16:44:12.198201  u2DelayCellOfst[5]=17 cells (5 PI)

 8915 16:44:12.201171  u2DelayCellOfst[6]=17 cells (5 PI)

 8916 16:44:12.201276  u2DelayCellOfst[7]=7 cells (2 PI)

 8917 16:44:12.208204  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8918 16:44:12.211697  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8919 16:44:12.211796   == TX Byte 1 ==

 8920 16:44:12.214724  u2DelayCellOfst[8]=0 cells (0 PI)

 8921 16:44:12.218270  u2DelayCellOfst[9]=7 cells (2 PI)

 8922 16:44:12.221302  u2DelayCellOfst[10]=14 cells (4 PI)

 8923 16:44:12.224696  u2DelayCellOfst[11]=10 cells (3 PI)

 8924 16:44:12.227792  u2DelayCellOfst[12]=17 cells (5 PI)

 8925 16:44:12.231254  u2DelayCellOfst[13]=17 cells (5 PI)

 8926 16:44:12.234650  u2DelayCellOfst[14]=21 cells (6 PI)

 8927 16:44:12.238319  u2DelayCellOfst[15]=17 cells (5 PI)

 8928 16:44:12.241308  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8929 16:44:12.247707  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8930 16:44:12.247815  DramC Write-DBI on

 8931 16:44:12.247896  ==

 8932 16:44:12.251088  Dram Type= 6, Freq= 0, CH_1, rank 1

 8933 16:44:12.254665  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8934 16:44:12.257707  ==

 8935 16:44:12.257793  

 8936 16:44:12.257864  

 8937 16:44:12.257925  	TX Vref Scan disable

 8938 16:44:12.261162   == TX Byte 0 ==

 8939 16:44:12.264694  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8940 16:44:12.267873   == TX Byte 1 ==

 8941 16:44:12.271335  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8942 16:44:12.274130  DramC Write-DBI off

 8943 16:44:12.274225  

 8944 16:44:12.274366  [DATLAT]

 8945 16:44:12.274480  Freq=1600, CH1 RK1

 8946 16:44:12.274591  

 8947 16:44:12.277653  DATLAT Default: 0xf

 8948 16:44:12.277756  0, 0xFFFF, sum = 0

 8949 16:44:12.281177  1, 0xFFFF, sum = 0

 8950 16:44:12.284643  2, 0xFFFF, sum = 0

 8951 16:44:12.284797  3, 0xFFFF, sum = 0

 8952 16:44:12.287517  4, 0xFFFF, sum = 0

 8953 16:44:12.287651  5, 0xFFFF, sum = 0

 8954 16:44:12.290939  6, 0xFFFF, sum = 0

 8955 16:44:12.291048  7, 0xFFFF, sum = 0

 8956 16:44:12.294474  8, 0xFFFF, sum = 0

 8957 16:44:12.294584  9, 0xFFFF, sum = 0

 8958 16:44:12.297927  10, 0xFFFF, sum = 0

 8959 16:44:12.298048  11, 0xFFFF, sum = 0

 8960 16:44:12.301315  12, 0xFFFF, sum = 0

 8961 16:44:12.301443  13, 0xFFFF, sum = 0

 8962 16:44:12.304381  14, 0x0, sum = 1

 8963 16:44:12.304535  15, 0x0, sum = 2

 8964 16:44:12.307904  16, 0x0, sum = 3

 8965 16:44:12.308029  17, 0x0, sum = 4

 8966 16:44:12.310992  best_step = 15

 8967 16:44:12.311144  

 8968 16:44:12.311245  ==

 8969 16:44:12.314368  Dram Type= 6, Freq= 0, CH_1, rank 1

 8970 16:44:12.317390  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8971 16:44:12.317499  ==

 8972 16:44:12.317600  RX Vref Scan: 0

 8973 16:44:12.320986  

 8974 16:44:12.321087  RX Vref 0 -> 0, step: 1

 8975 16:44:12.321185  

 8976 16:44:12.324971  RX Delay 11 -> 252, step: 4

 8977 16:44:12.327582  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8978 16:44:12.334110  iDelay=191, Bit 1, Center 124 (71 ~ 178) 108

 8979 16:44:12.337677  iDelay=191, Bit 2, Center 118 (67 ~ 170) 104

 8980 16:44:12.340594  iDelay=191, Bit 3, Center 128 (75 ~ 182) 108

 8981 16:44:12.344403  iDelay=191, Bit 4, Center 130 (79 ~ 182) 104

 8982 16:44:12.347308  iDelay=191, Bit 5, Center 142 (95 ~ 190) 96

 8983 16:44:12.354116  iDelay=191, Bit 6, Center 138 (87 ~ 190) 104

 8984 16:44:12.357197  iDelay=191, Bit 7, Center 124 (75 ~ 174) 100

 8985 16:44:12.360768  iDelay=191, Bit 8, Center 114 (59 ~ 170) 112

 8986 16:44:12.364142  iDelay=191, Bit 9, Center 114 (59 ~ 170) 112

 8987 16:44:12.367509  iDelay=191, Bit 10, Center 128 (75 ~ 182) 108

 8988 16:44:12.373985  iDelay=191, Bit 11, Center 116 (63 ~ 170) 108

 8989 16:44:12.377423  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8990 16:44:12.380836  iDelay=191, Bit 13, Center 136 (83 ~ 190) 108

 8991 16:44:12.384202  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8992 16:44:12.387052  iDelay=191, Bit 15, Center 134 (83 ~ 186) 104

 8993 16:44:12.390554  ==

 8994 16:44:12.394009  Dram Type= 6, Freq= 0, CH_1, rank 1

 8995 16:44:12.397614  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8996 16:44:12.397729  ==

 8997 16:44:12.397829  DQS Delay:

 8998 16:44:12.400538  DQS0 = 0, DQS1 = 0

 8999 16:44:12.400645  DQM Delay:

 9000 16:44:12.403903  DQM0 = 129, DQM1 = 126

 9001 16:44:12.404039  DQ Delay:

 9002 16:44:12.407532  DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =128

 9003 16:44:12.410299  DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124

 9004 16:44:12.413851  DQ8 =114, DQ9 =114, DQ10 =128, DQ11 =116

 9005 16:44:12.417372  DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134

 9006 16:44:12.417493  

 9007 16:44:12.417597  

 9008 16:44:12.417687  

 9009 16:44:12.420515  [DramC_TX_OE_Calibration] TA2

 9010 16:44:12.423901  Original DQ_B0 (3 6) =30, OEN = 27

 9011 16:44:12.426858  Original DQ_B1 (3 6) =30, OEN = 27

 9012 16:44:12.430358  24, 0x0, End_B0=24 End_B1=24

 9013 16:44:12.433922  25, 0x0, End_B0=25 End_B1=25

 9014 16:44:12.434061  26, 0x0, End_B0=26 End_B1=26

 9015 16:44:12.436964  27, 0x0, End_B0=27 End_B1=27

 9016 16:44:12.440585  28, 0x0, End_B0=28 End_B1=28

 9017 16:44:12.443460  29, 0x0, End_B0=29 End_B1=29

 9018 16:44:12.447057  30, 0x0, End_B0=30 End_B1=30

 9019 16:44:12.447154  31, 0x4141, End_B0=30 End_B1=30

 9020 16:44:12.450638  Byte0 end_step=30  best_step=27

 9021 16:44:12.454142  Byte1 end_step=30  best_step=27

 9022 16:44:12.456942  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9023 16:44:12.460316  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9024 16:44:12.460405  

 9025 16:44:12.460471  

 9026 16:44:12.466786  [DQSOSCAuto] RK1, (LSB)MR18= 0x1016, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps

 9027 16:44:12.470196  CH1 RK1: MR19=303, MR18=1016

 9028 16:44:12.476883  CH1_RK1: MR19=0x303, MR18=0x1016, DQSOSC=398, MR23=63, INC=23, DEC=15

 9029 16:44:12.480227  [RxdqsGatingPostProcess] freq 1600

 9030 16:44:12.486926  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9031 16:44:12.487047  best DQS0 dly(2T, 0.5T) = (1, 1)

 9032 16:44:12.490330  best DQS1 dly(2T, 0.5T) = (1, 1)

 9033 16:44:12.493773  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9034 16:44:12.497188  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9035 16:44:12.500196  best DQS0 dly(2T, 0.5T) = (1, 1)

 9036 16:44:12.503784  best DQS1 dly(2T, 0.5T) = (1, 1)

 9037 16:44:12.507210  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9038 16:44:12.510174  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9039 16:44:12.513806  Pre-setting of DQS Precalculation

 9040 16:44:12.516807  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9041 16:44:12.523825  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9042 16:44:12.533474  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9043 16:44:12.533635  

 9044 16:44:12.533717  

 9045 16:44:12.536975  [Calibration Summary] 3200 Mbps

 9046 16:44:12.537065  CH 0, Rank 0

 9047 16:44:12.540433  SW Impedance     : PASS

 9048 16:44:12.540530  DUTY Scan        : NO K

 9049 16:44:12.543330  ZQ Calibration   : PASS

 9050 16:44:12.546859  Jitter Meter     : NO K

 9051 16:44:12.546978  CBT Training     : PASS

 9052 16:44:12.550448  Write leveling   : PASS

 9053 16:44:12.550538  RX DQS gating    : PASS

 9054 16:44:12.553386  RX DQ/DQS(RDDQC) : PASS

 9055 16:44:12.556931  TX DQ/DQS        : PASS

 9056 16:44:12.557018  RX DATLAT        : PASS

 9057 16:44:12.560347  RX DQ/DQS(Engine): PASS

 9058 16:44:12.563423  TX OE            : PASS

 9059 16:44:12.563512  All Pass.

 9060 16:44:12.563581  

 9061 16:44:12.563644  CH 0, Rank 1

 9062 16:44:12.566889  SW Impedance     : PASS

 9063 16:44:12.569828  DUTY Scan        : NO K

 9064 16:44:12.569914  ZQ Calibration   : PASS

 9065 16:44:12.573619  Jitter Meter     : NO K

 9066 16:44:12.576698  CBT Training     : PASS

 9067 16:44:12.576779  Write leveling   : PASS

 9068 16:44:12.579876  RX DQS gating    : PASS

 9069 16:44:12.583507  RX DQ/DQS(RDDQC) : PASS

 9070 16:44:12.583607  TX DQ/DQS        : PASS

 9071 16:44:12.586349  RX DATLAT        : PASS

 9072 16:44:12.589823  RX DQ/DQS(Engine): PASS

 9073 16:44:12.589915  TX OE            : PASS

 9074 16:44:12.593308  All Pass.

 9075 16:44:12.593399  

 9076 16:44:12.593466  CH 1, Rank 0

 9077 16:44:12.596633  SW Impedance     : PASS

 9078 16:44:12.596739  DUTY Scan        : NO K

 9079 16:44:12.600193  ZQ Calibration   : PASS

 9080 16:44:12.602903  Jitter Meter     : NO K

 9081 16:44:12.603013  CBT Training     : PASS

 9082 16:44:12.606492  Write leveling   : PASS

 9083 16:44:12.609532  RX DQS gating    : PASS

 9084 16:44:12.609640  RX DQ/DQS(RDDQC) : PASS

 9085 16:44:12.612883  TX DQ/DQS        : PASS

 9086 16:44:12.612962  RX DATLAT        : PASS

 9087 16:44:12.616319  RX DQ/DQS(Engine): PASS

 9088 16:44:12.619786  TX OE            : PASS

 9089 16:44:12.619868  All Pass.

 9090 16:44:12.619932  

 9091 16:44:12.620030  CH 1, Rank 1

 9092 16:44:12.622842  SW Impedance     : PASS

 9093 16:44:12.626176  DUTY Scan        : NO K

 9094 16:44:12.626255  ZQ Calibration   : PASS

 9095 16:44:12.629863  Jitter Meter     : NO K

 9096 16:44:12.632788  CBT Training     : PASS

 9097 16:44:12.632880  Write leveling   : PASS

 9098 16:44:12.636377  RX DQS gating    : PASS

 9099 16:44:12.639704  RX DQ/DQS(RDDQC) : PASS

 9100 16:44:12.639801  TX DQ/DQS        : PASS

 9101 16:44:12.642663  RX DATLAT        : PASS

 9102 16:44:12.645968  RX DQ/DQS(Engine): PASS

 9103 16:44:12.646058  TX OE            : PASS

 9104 16:44:12.649480  All Pass.

 9105 16:44:12.649568  

 9106 16:44:12.649636  DramC Write-DBI on

 9107 16:44:12.653067  	PER_BANK_REFRESH: Hybrid Mode

 9108 16:44:12.653155  TX_TRACKING: ON

 9109 16:44:12.662949  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9110 16:44:12.672967  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9111 16:44:12.679277  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9112 16:44:12.682809  [FAST_K] Save calibration result to emmc

 9113 16:44:12.686132  sync common calibartion params.

 9114 16:44:12.686231  sync cbt_mode0:1, 1:1

 9115 16:44:12.689104  dram_init: ddr_geometry: 2

 9116 16:44:12.692820  dram_init: ddr_geometry: 2

 9117 16:44:12.692913  dram_init: ddr_geometry: 2

 9118 16:44:12.696029  0:dram_rank_size:100000000

 9119 16:44:12.699523  1:dram_rank_size:100000000

 9120 16:44:12.705873  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9121 16:44:12.706000  DFS_SHUFFLE_HW_MODE: ON

 9122 16:44:12.709496  dramc_set_vcore_voltage set vcore to 725000

 9123 16:44:12.712475  Read voltage for 1600, 0

 9124 16:44:12.712582  Vio18 = 0

 9125 16:44:12.715803  Vcore = 725000

 9126 16:44:12.715906  Vdram = 0

 9127 16:44:12.716034  Vddq = 0

 9128 16:44:12.719169  Vmddr = 0

 9129 16:44:12.719281  switch to 3200 Mbps bootup

 9130 16:44:12.722247  [DramcRunTimeConfig]

 9131 16:44:12.722350  PHYPLL

 9132 16:44:12.725746  DPM_CONTROL_AFTERK: ON

 9133 16:44:12.725851  PER_BANK_REFRESH: ON

 9134 16:44:12.729276  REFRESH_OVERHEAD_REDUCTION: ON

 9135 16:44:12.732367  CMD_PICG_NEW_MODE: OFF

 9136 16:44:12.732452  XRTWTW_NEW_MODE: ON

 9137 16:44:12.735724  XRTRTR_NEW_MODE: ON

 9138 16:44:12.735827  TX_TRACKING: ON

 9139 16:44:12.739407  RDSEL_TRACKING: OFF

 9140 16:44:12.742291  DQS Precalculation for DVFS: ON

 9141 16:44:12.742406  RX_TRACKING: OFF

 9142 16:44:12.745830  HW_GATING DBG: ON

 9143 16:44:12.745934  ZQCS_ENABLE_LP4: ON

 9144 16:44:12.748865  RX_PICG_NEW_MODE: ON

 9145 16:44:12.748953  TX_PICG_NEW_MODE: ON

 9146 16:44:12.752452  ENABLE_RX_DCM_DPHY: ON

 9147 16:44:12.755864  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9148 16:44:12.758838  DUMMY_READ_FOR_TRACKING: OFF

 9149 16:44:12.758952  !!! SPM_CONTROL_AFTERK: OFF

 9150 16:44:12.762295  !!! SPM could not control APHY

 9151 16:44:12.765839  IMPEDANCE_TRACKING: ON

 9152 16:44:12.765932  TEMP_SENSOR: ON

 9153 16:44:12.769286  HW_SAVE_FOR_SR: OFF

 9154 16:44:12.772246  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9155 16:44:12.775690  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9156 16:44:12.775801  Read ODT Tracking: ON

 9157 16:44:12.778916  Refresh Rate DeBounce: ON

 9158 16:44:12.782320  DFS_NO_QUEUE_FLUSH: ON

 9159 16:44:12.785689  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9160 16:44:12.785779  ENABLE_DFS_RUNTIME_MRW: OFF

 9161 16:44:12.789147  DDR_RESERVE_NEW_MODE: ON

 9162 16:44:12.791906  MR_CBT_SWITCH_FREQ: ON

 9163 16:44:12.792028  =========================

 9164 16:44:12.812929  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9165 16:44:12.815889  dram_init: ddr_geometry: 2

 9166 16:44:12.834014  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9167 16:44:12.837518  dram_init: dram init end (result: 0)

 9168 16:44:12.844076  DRAM-K: Full calibration passed in 24560 msecs

 9169 16:44:12.847711  MRC: failed to locate region type 0.

 9170 16:44:12.847855  DRAM rank0 size:0x100000000,

 9171 16:44:12.850902  DRAM rank1 size=0x100000000

 9172 16:44:12.860476  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9173 16:44:12.867271  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9174 16:44:12.874040  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9175 16:44:12.880526  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9176 16:44:12.883843  DRAM rank0 size:0x100000000,

 9177 16:44:12.887268  DRAM rank1 size=0x100000000

 9178 16:44:12.887409  CBMEM:

 9179 16:44:12.890790  IMD: root @ 0xfffff000 254 entries.

 9180 16:44:12.893573  IMD: root @ 0xffffec00 62 entries.

 9181 16:44:12.897012  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9182 16:44:12.900559  WARNING: RO_VPD is uninitialized or empty.

 9183 16:44:12.907148  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9184 16:44:12.914301  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9185 16:44:12.926510  read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps

 9186 16:44:12.938346  BS: romstage times (exec / console): total (unknown) / 24067 ms

 9187 16:44:12.938496  

 9188 16:44:12.938566  

 9189 16:44:12.948244  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9190 16:44:12.951803  ARM64: Exception handlers installed.

 9191 16:44:12.954819  ARM64: Testing exception

 9192 16:44:12.958292  ARM64: Done test exception

 9193 16:44:12.958431  Enumerating buses...

 9194 16:44:12.961334  Show all devs... Before device enumeration.

 9195 16:44:12.965092  Root Device: enabled 1

 9196 16:44:12.967939  CPU_CLUSTER: 0: enabled 1

 9197 16:44:12.968067  CPU: 00: enabled 1

 9198 16:44:12.971530  Compare with tree...

 9199 16:44:12.971634  Root Device: enabled 1

 9200 16:44:12.974432   CPU_CLUSTER: 0: enabled 1

 9201 16:44:12.978187    CPU: 00: enabled 1

 9202 16:44:12.978312  Root Device scanning...

 9203 16:44:12.981232  scan_static_bus for Root Device

 9204 16:44:12.984688  CPU_CLUSTER: 0 enabled

 9205 16:44:12.988472  scan_static_bus for Root Device done

 9206 16:44:12.991633  scan_bus: bus Root Device finished in 8 msecs

 9207 16:44:12.991787  done

 9208 16:44:12.998236  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9209 16:44:13.001811  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9210 16:44:13.008553  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9211 16:44:13.011262  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9212 16:44:13.015125  Allocating resources...

 9213 16:44:13.018015  Reading resources...

 9214 16:44:13.021528  Root Device read_resources bus 0 link: 0

 9215 16:44:13.021633  DRAM rank0 size:0x100000000,

 9216 16:44:13.024606  DRAM rank1 size=0x100000000

 9217 16:44:13.028203  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9218 16:44:13.030930  CPU: 00 missing read_resources

 9219 16:44:13.034693  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9220 16:44:13.041132  Root Device read_resources bus 0 link: 0 done

 9221 16:44:13.041249  Done reading resources.

 9222 16:44:13.048120  Show resources in subtree (Root Device)...After reading.

 9223 16:44:13.050933   Root Device child on link 0 CPU_CLUSTER: 0

 9224 16:44:13.054549    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9225 16:44:13.064275    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9226 16:44:13.064400     CPU: 00

 9227 16:44:13.067890  Root Device assign_resources, bus 0 link: 0

 9228 16:44:13.070886  CPU_CLUSTER: 0 missing set_resources

 9229 16:44:13.077382  Root Device assign_resources, bus 0 link: 0 done

 9230 16:44:13.077499  Done setting resources.

 9231 16:44:13.084260  Show resources in subtree (Root Device)...After assigning values.

 9232 16:44:13.087900   Root Device child on link 0 CPU_CLUSTER: 0

 9233 16:44:13.091117    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9234 16:44:13.101090    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9235 16:44:13.101227     CPU: 00

 9236 16:44:13.104591  Done allocating resources.

 9237 16:44:13.107416  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9238 16:44:13.110856  Enabling resources...

 9239 16:44:13.110982  done.

 9240 16:44:13.117648  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9241 16:44:13.117763  Initializing devices...

 9242 16:44:13.120593  Root Device init

 9243 16:44:13.120689  init hardware done!

 9244 16:44:13.123975  0x00000018: ctrlr->caps

 9245 16:44:13.127579  52.000 MHz: ctrlr->f_max

 9246 16:44:13.127681  0.400 MHz: ctrlr->f_min

 9247 16:44:13.130520  0x40ff8080: ctrlr->voltages

 9248 16:44:13.130613  sclk: 390625

 9249 16:44:13.133914  Bus Width = 1

 9250 16:44:13.134005  sclk: 390625

 9251 16:44:13.137480  Bus Width = 1

 9252 16:44:13.137574  Early init status = 3

 9253 16:44:13.143873  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9254 16:44:13.147453  in-header: 03 fc 00 00 01 00 00 00 

 9255 16:44:13.147557  in-data: 00 

 9256 16:44:13.153841  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9257 16:44:13.156905  in-header: 03 fd 00 00 00 00 00 00 

 9258 16:44:13.160478  in-data: 

 9259 16:44:13.164139  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9260 16:44:13.166980  in-header: 03 fc 00 00 01 00 00 00 

 9261 16:44:13.170580  in-data: 00 

 9262 16:44:13.173719  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9263 16:44:13.178920  in-header: 03 fd 00 00 00 00 00 00 

 9264 16:44:13.182313  in-data: 

 9265 16:44:13.185735  [SSUSB] Setting up USB HOST controller...

 9266 16:44:13.188760  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9267 16:44:13.192517  [SSUSB] phy power-on done.

 9268 16:44:13.195288  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9269 16:44:13.202089  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9270 16:44:13.205531  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9271 16:44:13.212006  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9272 16:44:13.218867  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9273 16:44:13.225137  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9274 16:44:13.232040  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9275 16:44:13.238314  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9276 16:44:13.241870  SPM: binary array size = 0x9dc

 9277 16:44:13.245417  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9278 16:44:13.251725  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9279 16:44:13.258365  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9280 16:44:13.265040  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9281 16:44:13.268553  configure_display: Starting display init

 9282 16:44:13.302557  anx7625_power_on_init: Init interface.

 9283 16:44:13.305346  anx7625_disable_pd_protocol: Disabled PD feature.

 9284 16:44:13.308806  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9285 16:44:13.336401  anx7625_start_dp_work: Secure OCM version=00

 9286 16:44:13.339990  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9287 16:44:13.355131  sp_tx_get_edid_block: EDID Block = 1

 9288 16:44:13.457529  Extracted contents:

 9289 16:44:13.460875  header:          00 ff ff ff ff ff ff 00

 9290 16:44:13.463881  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9291 16:44:13.467335  version:         01 04

 9292 16:44:13.470830  basic params:    95 1f 11 78 0a

 9293 16:44:13.473895  chroma info:     76 90 94 55 54 90 27 21 50 54

 9294 16:44:13.477509  established:     00 00 00

 9295 16:44:13.484200  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9296 16:44:13.487037  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9297 16:44:13.493543  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9298 16:44:13.500153  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9299 16:44:13.507062  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9300 16:44:13.510826  extensions:      00

 9301 16:44:13.510926  checksum:        fb

 9302 16:44:13.510993  

 9303 16:44:13.513648  Manufacturer: IVO Model 57d Serial Number 0

 9304 16:44:13.516977  Made week 0 of 2020

 9305 16:44:13.517070  EDID version: 1.4

 9306 16:44:13.520468  Digital display

 9307 16:44:13.523753  6 bits per primary color channel

 9308 16:44:13.523845  DisplayPort interface

 9309 16:44:13.527132  Maximum image size: 31 cm x 17 cm

 9310 16:44:13.530673  Gamma: 220%

 9311 16:44:13.530765  Check DPMS levels

 9312 16:44:13.533938  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9313 16:44:13.537290  First detailed timing is preferred timing

 9314 16:44:13.540510  Established timings supported:

 9315 16:44:13.543775  Standard timings supported:

 9316 16:44:13.543868  Detailed timings

 9317 16:44:13.550476  Hex of detail: 383680a07038204018303c0035ae10000019

 9318 16:44:13.553908  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9319 16:44:13.560469                 0780 0798 07c8 0820 hborder 0

 9320 16:44:13.563398                 0438 043b 0447 0458 vborder 0

 9321 16:44:13.566918                 -hsync -vsync

 9322 16:44:13.567013  Did detailed timing

 9323 16:44:13.570583  Hex of detail: 000000000000000000000000000000000000

 9324 16:44:13.573498  Manufacturer-specified data, tag 0

 9325 16:44:13.580142  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9326 16:44:13.580247  ASCII string: InfoVision

 9327 16:44:13.586840  Hex of detail: 000000fe00523134304e574635205248200a

 9328 16:44:13.590263  ASCII string: R140NWF5 RH 

 9329 16:44:13.590357  Checksum

 9330 16:44:13.590422  Checksum: 0xfb (valid)

 9331 16:44:13.596889  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9332 16:44:13.599852  DSI data_rate: 832800000 bps

 9333 16:44:13.603348  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9334 16:44:13.609692  anx7625_parse_edid: pixelclock(138800).

 9335 16:44:13.613334   hactive(1920), hsync(48), hfp(24), hbp(88)

 9336 16:44:13.616548   vactive(1080), vsync(12), vfp(3), vbp(17)

 9337 16:44:13.619866  anx7625_dsi_config: config dsi.

 9338 16:44:13.626279  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9339 16:44:13.639523  anx7625_dsi_config: success to config DSI

 9340 16:44:13.643007  anx7625_dp_start: MIPI phy setup OK.

 9341 16:44:13.645756  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9342 16:44:13.649023  mtk_ddp_mode_set invalid vrefresh 60

 9343 16:44:13.652873  main_disp_path_setup

 9344 16:44:13.652990  ovl_layer_smi_id_en

 9345 16:44:13.655646  ovl_layer_smi_id_en

 9346 16:44:13.655723  ccorr_config

 9347 16:44:13.655786  aal_config

 9348 16:44:13.658987  gamma_config

 9349 16:44:13.659064  postmask_config

 9350 16:44:13.662486  dither_config

 9351 16:44:13.666049  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9352 16:44:13.672414                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9353 16:44:13.675316  Root Device init finished in 552 msecs

 9354 16:44:13.678933  CPU_CLUSTER: 0 init

 9355 16:44:13.685529  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9356 16:44:13.692573  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9357 16:44:13.692683  APU_MBOX 0x190000b0 = 0x10001

 9358 16:44:13.695492  APU_MBOX 0x190001b0 = 0x10001

 9359 16:44:13.698420  APU_MBOX 0x190005b0 = 0x10001

 9360 16:44:13.702120  APU_MBOX 0x190006b0 = 0x10001

 9361 16:44:13.708573  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9362 16:44:13.718454  read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps

 9363 16:44:13.730951  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9364 16:44:13.737390  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9365 16:44:13.748886  read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps

 9366 16:44:13.758172  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9367 16:44:13.761607  CPU_CLUSTER: 0 init finished in 81 msecs

 9368 16:44:13.764910  Devices initialized

 9369 16:44:13.767892  Show all devs... After init.

 9370 16:44:13.768014  Root Device: enabled 1

 9371 16:44:13.771254  CPU_CLUSTER: 0: enabled 1

 9372 16:44:13.774829  CPU: 00: enabled 1

 9373 16:44:13.777847  BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms

 9374 16:44:13.781301  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9375 16:44:13.784333  ELOG: NV offset 0x57f000 size 0x1000

 9376 16:44:13.790892  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9377 16:44:13.797994  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9378 16:44:13.800941  ELOG: Event(17) added with size 13 at 2023-06-03 16:44:13 UTC

 9379 16:44:13.807908  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9380 16:44:13.811007  in-header: 03 e9 00 00 2c 00 00 00 

 9381 16:44:13.824052  in-data: 76 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9382 16:44:13.827398  ELOG: Event(A1) added with size 10 at 2023-06-03 16:44:13 UTC

 9383 16:44:13.834451  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9384 16:44:13.840891  ELOG: Event(A0) added with size 9 at 2023-06-03 16:44:13 UTC

 9385 16:44:13.843833  elog_add_boot_reason: Logged dev mode boot

 9386 16:44:13.850473  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9387 16:44:13.850614  Finalize devices...

 9388 16:44:13.854002  Devices finalized

 9389 16:44:13.857306  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9390 16:44:13.860634  Writing coreboot table at 0xffe64000

 9391 16:44:13.863991   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9392 16:44:13.870619   1. 0000000040000000-00000000400fffff: RAM

 9393 16:44:13.873886   2. 0000000040100000-000000004032afff: RAMSTAGE

 9394 16:44:13.877545   3. 000000004032b000-00000000545fffff: RAM

 9395 16:44:13.880875   4. 0000000054600000-000000005465ffff: BL31

 9396 16:44:13.883912   5. 0000000054660000-00000000ffe63fff: RAM

 9397 16:44:13.890494   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9398 16:44:13.894005   7. 0000000100000000-000000023fffffff: RAM

 9399 16:44:13.897068  Passing 5 GPIOs to payload:

 9400 16:44:13.900639              NAME |       PORT | POLARITY |     VALUE

 9401 16:44:13.907164          EC in RW | 0x000000aa |      low | undefined

 9402 16:44:13.910927      EC interrupt | 0x00000005 |      low | undefined

 9403 16:44:13.913765     TPM interrupt | 0x000000ab |     high | undefined

 9404 16:44:13.920675    SD card detect | 0x00000011 |     high | undefined

 9405 16:44:13.923571    speaker enable | 0x00000093 |     high | undefined

 9406 16:44:13.927647  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9407 16:44:13.930366  in-header: 03 f9 00 00 02 00 00 00 

 9408 16:44:13.933732  in-data: 02 00 

 9409 16:44:13.937263  ADC[4]: Raw value=900590 ID=7

 9410 16:44:13.937375  ADC[3]: Raw value=212967 ID=1

 9411 16:44:13.940231  RAM Code: 0x71

 9412 16:44:13.943723  ADC[6]: Raw value=74557 ID=0

 9413 16:44:13.943803  ADC[5]: Raw value=211860 ID=1

 9414 16:44:13.946701  SKU Code: 0x1

 9415 16:44:13.953767  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1

 9416 16:44:13.953895  coreboot table: 964 bytes.

 9417 16:44:13.957256  IMD ROOT    0. 0xfffff000 0x00001000

 9418 16:44:13.960525  IMD SMALL   1. 0xffffe000 0x00001000

 9419 16:44:13.963240  RO MCACHE   2. 0xffffc000 0x00001104

 9420 16:44:13.966605  CONSOLE     3. 0xfff7c000 0x00080000

 9421 16:44:13.970056  FMAP        4. 0xfff7b000 0x00000452

 9422 16:44:13.973355  TIME STAMP  5. 0xfff7a000 0x00000910

 9423 16:44:13.977170  VBOOT WORK  6. 0xfff66000 0x00014000

 9424 16:44:13.980027  RAMOOPS     7. 0xffe66000 0x00100000

 9425 16:44:13.983505  COREBOOT    8. 0xffe64000 0x00002000

 9426 16:44:13.986499  IMD small region:

 9427 16:44:13.990053    IMD ROOT    0. 0xffffec00 0x00000400

 9428 16:44:13.993724    VPD         1. 0xffffeba0 0x0000004c

 9429 16:44:13.996739    MMC STATUS  2. 0xffffeb80 0x00000004

 9430 16:44:14.000158  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9431 16:44:14.003087  Probing TPM:  done!

 9432 16:44:14.006794  Connected to device vid:did:rid of 1ae0:0028:00

 9433 16:44:14.017744  Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8

 9434 16:44:14.020813  Initialized TPM device CR50 revision 0

 9435 16:44:14.024743  Checking cr50 for pending updates

 9436 16:44:14.028274  Reading cr50 TPM mode

 9437 16:44:14.037001  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9438 16:44:14.043575  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9439 16:44:14.083835  read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps

 9440 16:44:14.087225  Checking segment from ROM address 0x40100000

 9441 16:44:14.090254  Checking segment from ROM address 0x4010001c

 9442 16:44:14.096805  Loading segment from ROM address 0x40100000

 9443 16:44:14.096971    code (compression=0)

 9444 16:44:14.106694    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9445 16:44:14.113837  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9446 16:44:14.113983  it's not compressed!

 9447 16:44:14.120311  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9448 16:44:14.123341  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9449 16:44:14.143862  Loading segment from ROM address 0x4010001c

 9450 16:44:14.144074    Entry Point 0x80000000

 9451 16:44:14.147355  Loaded segments

 9452 16:44:14.150978  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9453 16:44:14.157379  Jumping to boot code at 0x80000000(0xffe64000)

 9454 16:44:14.164380  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9455 16:44:14.170583  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9456 16:44:14.178650  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9457 16:44:14.181987  Checking segment from ROM address 0x40100000

 9458 16:44:14.185348  Checking segment from ROM address 0x4010001c

 9459 16:44:14.191603  Loading segment from ROM address 0x40100000

 9460 16:44:14.191747    code (compression=1)

 9461 16:44:14.198888    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9462 16:44:14.208604  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9463 16:44:14.208763  using LZMA

 9464 16:44:14.216970  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9465 16:44:14.223537  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9466 16:44:14.226478  Loading segment from ROM address 0x4010001c

 9467 16:44:14.226597    Entry Point 0x54601000

 9468 16:44:14.230040  Loaded segments

 9469 16:44:14.233209  NOTICE:  MT8192 bl31_setup

 9470 16:44:14.240153  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9471 16:44:14.243843  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9472 16:44:14.246780  WARNING: region 0:

 9473 16:44:14.250400  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9474 16:44:14.250522  WARNING: region 1:

 9475 16:44:14.256810  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9476 16:44:14.260300  WARNING: region 2:

 9477 16:44:14.263951  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9478 16:44:14.266834  WARNING: region 3:

 9479 16:44:14.270374  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9480 16:44:14.273745  WARNING: region 4:

 9481 16:44:14.280609  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9482 16:44:14.280825  WARNING: region 5:

 9483 16:44:14.283982  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9484 16:44:14.287372  WARNING: region 6:

 9485 16:44:14.290732  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9486 16:44:14.290860  WARNING: region 7:

 9487 16:44:14.297178  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9488 16:44:14.303760  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9489 16:44:14.307387  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9490 16:44:14.310394  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9491 16:44:14.317225  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9492 16:44:14.320793  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9493 16:44:14.324354  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9494 16:44:14.330350  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9495 16:44:14.333794  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9496 16:44:14.340869  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9497 16:44:14.344155  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9498 16:44:14.347087  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9499 16:44:14.353643  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9500 16:44:14.357155  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9501 16:44:14.360758  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9502 16:44:14.366913  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9503 16:44:14.370355  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9504 16:44:14.373923  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9505 16:44:14.380743  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9506 16:44:14.383753  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9507 16:44:14.390521  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9508 16:44:14.394065  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9509 16:44:14.396959  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9510 16:44:14.403927  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9511 16:44:14.406884  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9512 16:44:14.414120  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9513 16:44:14.417612  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9514 16:44:14.420849  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9515 16:44:14.427372  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9516 16:44:14.430941  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9517 16:44:14.433909  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9518 16:44:14.440649  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9519 16:44:14.443766  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9520 16:44:14.450625  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9521 16:44:14.454238  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9522 16:44:14.457309  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9523 16:44:14.460781  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9524 16:44:14.467301  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9525 16:44:14.470812  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9526 16:44:14.473776  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9527 16:44:14.477248  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9528 16:44:14.480677  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9529 16:44:14.487374  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9530 16:44:14.490743  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9531 16:44:14.494295  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9532 16:44:14.496989  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9533 16:44:14.503723  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9534 16:44:14.507304  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9535 16:44:14.510259  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9536 16:44:14.517480  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9537 16:44:14.520412  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9538 16:44:14.526943  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9539 16:44:14.530601  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9540 16:44:14.533603  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9541 16:44:14.540805  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9542 16:44:14.543589  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9543 16:44:14.550749  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9544 16:44:14.554135  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9545 16:44:14.560943  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9546 16:44:14.563737  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9547 16:44:14.567258  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9548 16:44:14.573756  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9549 16:44:14.576831  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9550 16:44:14.583882  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9551 16:44:14.587207  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9552 16:44:14.593931  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9553 16:44:14.597113  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9554 16:44:14.603723  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9555 16:44:14.607085  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9556 16:44:14.610499  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9557 16:44:14.616959  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9558 16:44:14.620595  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9559 16:44:14.627068  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9560 16:44:14.630686  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9561 16:44:14.633922  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9562 16:44:14.640357  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9563 16:44:14.643912  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9564 16:44:14.650452  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9565 16:44:14.653811  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9566 16:44:14.660186  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9567 16:44:14.663736  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9568 16:44:14.670447  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9569 16:44:14.673885  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9570 16:44:14.676879  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9571 16:44:14.683470  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9572 16:44:14.687477  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9573 16:44:14.693589  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9574 16:44:14.696965  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9575 16:44:14.700464  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9576 16:44:14.707152  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9577 16:44:14.710821  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9578 16:44:14.717069  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9579 16:44:14.720557  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9580 16:44:14.727116  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9581 16:44:14.730698  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9582 16:44:14.737303  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9583 16:44:14.740909  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9584 16:44:14.743822  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9585 16:44:14.747450  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9586 16:44:14.753966  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9587 16:44:14.757344  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9588 16:44:14.760282  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9589 16:44:14.767405  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9590 16:44:14.770350  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9591 16:44:14.773948  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9592 16:44:14.780584  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9593 16:44:14.783545  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9594 16:44:14.790441  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9595 16:44:14.793824  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9596 16:44:14.797273  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9597 16:44:14.803613  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9598 16:44:14.807244  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9599 16:44:14.814158  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9600 16:44:14.816973  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9601 16:44:14.820377  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9602 16:44:14.827337  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9603 16:44:14.830423  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9604 16:44:14.833992  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9605 16:44:14.840661  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9606 16:44:14.843404  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9607 16:44:14.847021  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9608 16:44:14.853769  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9609 16:44:14.857051  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9610 16:44:14.860765  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9611 16:44:14.863667  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9612 16:44:14.870423  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9613 16:44:14.874001  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9614 16:44:14.877192  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9615 16:44:14.883864  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9616 16:44:14.887228  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9617 16:44:14.893784  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9618 16:44:14.897231  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9619 16:44:14.900552  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9620 16:44:14.907303  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9621 16:44:14.910952  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9622 16:44:14.917163  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9623 16:44:14.920645  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9624 16:44:14.924175  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9625 16:44:14.930658  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9626 16:44:14.933684  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9627 16:44:14.937275  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9628 16:44:14.943866  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9629 16:44:14.947388  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9630 16:44:14.953838  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9631 16:44:14.956947  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9632 16:44:14.960453  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9633 16:44:14.966923  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9634 16:44:14.970287  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9635 16:44:14.976991  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9636 16:44:14.980551  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9637 16:44:14.984046  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9638 16:44:14.990519  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9639 16:44:14.993724  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9640 16:44:14.997220  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9641 16:44:15.003873  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9642 16:44:15.007203  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9643 16:44:15.013540  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9644 16:44:15.017067  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9645 16:44:15.020443  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9646 16:44:15.026787  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9647 16:44:15.030417  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9648 16:44:15.036793  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9649 16:44:15.040160  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9650 16:44:15.043801  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9651 16:44:15.050361  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9652 16:44:15.053366  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9653 16:44:15.059948  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9654 16:44:15.063436  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9655 16:44:15.066475  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9656 16:44:15.073461  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9657 16:44:15.077013  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9658 16:44:15.083069  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9659 16:44:15.086481  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9660 16:44:15.090214  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9661 16:44:15.096721  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9662 16:44:15.099787  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9663 16:44:15.103221  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9664 16:44:15.109972  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9665 16:44:15.113294  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9666 16:44:15.119738  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9667 16:44:15.123164  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9668 16:44:15.126671  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9669 16:44:15.133462  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9670 16:44:15.136440  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9671 16:44:15.142941  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9672 16:44:15.146279  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9673 16:44:15.149957  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9674 16:44:15.156412  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9675 16:44:15.160163  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9676 16:44:15.166590  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9677 16:44:15.169658  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9678 16:44:15.173219  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9679 16:44:15.179657  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9680 16:44:15.183231  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9681 16:44:15.189724  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9682 16:44:15.193260  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9683 16:44:15.196280  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9684 16:44:15.202824  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9685 16:44:15.206505  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9686 16:44:15.213298  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9687 16:44:15.216655  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9688 16:44:15.219671  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9689 16:44:15.226410  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9690 16:44:15.229808  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9691 16:44:15.236476  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9692 16:44:15.239471  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9693 16:44:15.246630  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9694 16:44:15.249575  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9695 16:44:15.253137  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9696 16:44:15.259710  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9697 16:44:15.263205  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9698 16:44:15.269774  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9699 16:44:15.272740  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9700 16:44:15.276172  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9701 16:44:15.283065  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9702 16:44:15.286230  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9703 16:44:15.292870  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9704 16:44:15.296432  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9705 16:44:15.302970  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9706 16:44:15.305923  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9707 16:44:15.309511  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9708 16:44:15.315873  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9709 16:44:15.319297  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9710 16:44:15.326268  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9711 16:44:15.329209  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9712 16:44:15.332527  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9713 16:44:15.339232  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9714 16:44:15.342806  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9715 16:44:15.349272  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9716 16:44:15.352352  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9717 16:44:15.355756  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9718 16:44:15.362744  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9719 16:44:15.365827  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9720 16:44:15.369457  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9721 16:44:15.372301  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9722 16:44:15.379006  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9723 16:44:15.382506  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9724 16:44:15.385381  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9725 16:44:15.392387  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9726 16:44:15.395265  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9727 16:44:15.401979  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9728 16:44:15.405535  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9729 16:44:15.409046  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9730 16:44:15.415616  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9731 16:44:15.418923  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9732 16:44:15.422208  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9733 16:44:15.428480  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9734 16:44:15.431918  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9735 16:44:15.438359  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9736 16:44:15.442133  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9737 16:44:15.445024  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9738 16:44:15.451971  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9739 16:44:15.455594  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9740 16:44:15.458475  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9741 16:44:15.465539  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9742 16:44:15.469178  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9743 16:44:15.472098  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9744 16:44:15.478676  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9745 16:44:15.482298  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9746 16:44:15.485330  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9747 16:44:15.491729  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9748 16:44:15.495104  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9749 16:44:15.501698  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9750 16:44:15.505274  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9751 16:44:15.508869  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9752 16:44:15.515361  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9753 16:44:15.518907  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9754 16:44:15.521811  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9755 16:44:15.528537  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9756 16:44:15.531943  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9757 16:44:15.535402  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9758 16:44:15.538205  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9759 16:44:15.545069  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9760 16:44:15.547929  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9761 16:44:15.551634  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9762 16:44:15.554689  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9763 16:44:15.561533  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9764 16:44:15.564987  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9765 16:44:15.568471  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9766 16:44:15.571450  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9767 16:44:15.578197  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9768 16:44:15.581694  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9769 16:44:15.584659  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9770 16:44:15.591160  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9771 16:44:15.594688  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9772 16:44:15.601113  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9773 16:44:15.604729  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9774 16:44:15.608350  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9775 16:44:15.614332  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9776 16:44:15.618005  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9777 16:44:15.624453  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9778 16:44:15.627951  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9779 16:44:15.631238  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9780 16:44:15.637727  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9781 16:44:15.640747  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9782 16:44:15.647613  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9783 16:44:15.650816  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9784 16:44:15.657347  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9785 16:44:15.660700  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9786 16:44:15.664221  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9787 16:44:15.670835  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9788 16:44:15.673767  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9789 16:44:15.680973  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9790 16:44:15.683991  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9791 16:44:15.687660  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9792 16:44:15.694159  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9793 16:44:15.697201  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9794 16:44:15.704336  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9795 16:44:15.707352  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9796 16:44:15.710991  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9797 16:44:15.717560  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9798 16:44:15.720752  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9799 16:44:15.727052  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9800 16:44:15.730492  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9801 16:44:15.734035  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9802 16:44:15.740856  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9803 16:44:15.743674  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9804 16:44:15.750411  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9805 16:44:15.753956  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9806 16:44:15.760605  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9807 16:44:15.763965  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9808 16:44:15.766970  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9809 16:44:15.773550  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9810 16:44:15.777020  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9811 16:44:15.783748  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9812 16:44:15.786704  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9813 16:44:15.790308  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9814 16:44:15.796910  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9815 16:44:15.800424  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9816 16:44:15.807077  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9817 16:44:15.810097  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9818 16:44:15.813667  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9819 16:44:15.820382  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9820 16:44:15.823374  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9821 16:44:15.830504  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9822 16:44:15.833344  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9823 16:44:15.836769  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9824 16:44:15.843528  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9825 16:44:15.847049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9826 16:44:15.853300  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9827 16:44:15.856718  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9828 16:44:15.860123  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9829 16:44:15.866914  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9830 16:44:15.870349  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9831 16:44:15.876490  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9832 16:44:15.880213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9833 16:44:15.883043  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9834 16:44:15.890171  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9835 16:44:15.893077  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9836 16:44:15.900214  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9837 16:44:15.903095  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9838 16:44:15.910117  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9839 16:44:15.913804  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9840 16:44:15.916767  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9841 16:44:15.923298  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9842 16:44:15.926233  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9843 16:44:15.933333  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9844 16:44:15.936257  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9845 16:44:15.943051  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9846 16:44:15.946404  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9847 16:44:15.949868  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9848 16:44:15.956400  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9849 16:44:15.959609  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9850 16:44:15.966060  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9851 16:44:15.970051  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9852 16:44:15.976297  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9853 16:44:15.979716  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9854 16:44:15.982589  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9855 16:44:15.989732  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9856 16:44:15.992756  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9857 16:44:15.999477  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9858 16:44:16.003083  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9859 16:44:16.009947  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9860 16:44:16.013027  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9861 16:44:16.016299  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9862 16:44:16.023024  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9863 16:44:16.025983  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9864 16:44:16.033082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9865 16:44:16.035943  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9866 16:44:16.042997  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9867 16:44:16.045860  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9868 16:44:16.049283  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9869 16:44:16.055632  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9870 16:44:16.059173  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9871 16:44:16.066127  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9872 16:44:16.069053  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9873 16:44:16.075711  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9874 16:44:16.079201  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9875 16:44:16.085543  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9876 16:44:16.089208  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9877 16:44:16.092042  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9878 16:44:16.098667  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9879 16:44:16.102228  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9880 16:44:16.108723  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9881 16:44:16.112447  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9882 16:44:16.118932  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9883 16:44:16.121937  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9884 16:44:16.128927  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9885 16:44:16.131945  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9886 16:44:16.135469  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9887 16:44:16.141816  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9888 16:44:16.145357  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9889 16:44:16.151494  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9890 16:44:16.155069  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9891 16:44:16.158275  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9892 16:44:16.165315  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9893 16:44:16.168854  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9894 16:44:16.175256  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9895 16:44:16.178539  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9896 16:44:16.185170  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9897 16:44:16.188543  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9898 16:44:16.194982  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9899 16:44:16.198540  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9900 16:44:16.205159  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9901 16:44:16.208748  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9902 16:44:16.215194  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9903 16:44:16.218201  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9904 16:44:16.224640  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9905 16:44:16.228394  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9906 16:44:16.234833  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9907 16:44:16.238724  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9908 16:44:16.245121  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9909 16:44:16.248025  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9910 16:44:16.255076  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9911 16:44:16.258018  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9912 16:44:16.264901  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9913 16:44:16.267874  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9914 16:44:16.274755  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9915 16:44:16.278045  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9916 16:44:16.284896  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9917 16:44:16.287659  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9918 16:44:16.294520  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9919 16:44:16.298105  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9920 16:44:16.304686  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9921 16:44:16.307582  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9922 16:44:16.311096  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9923 16:44:16.314690  INFO:    [APUAPC] vio 0

 9924 16:44:16.317704  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9925 16:44:16.324947  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9926 16:44:16.327762  INFO:    [APUAPC] D0_APC_0: 0x400510

 9927 16:44:16.331432  INFO:    [APUAPC] D0_APC_1: 0x0

 9928 16:44:16.335090  INFO:    [APUAPC] D0_APC_2: 0x1540

 9929 16:44:16.335200  INFO:    [APUAPC] D0_APC_3: 0x0

 9930 16:44:16.337983  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9931 16:44:16.344828  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9932 16:44:16.344916  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9933 16:44:16.347757  INFO:    [APUAPC] D1_APC_3: 0x0

 9934 16:44:16.351239  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9935 16:44:16.354706  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9936 16:44:16.358325  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9937 16:44:16.361491  INFO:    [APUAPC] D2_APC_3: 0x0

 9938 16:44:16.364311  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9939 16:44:16.367764  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9940 16:44:16.371148  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9941 16:44:16.374576  INFO:    [APUAPC] D3_APC_3: 0x0

 9942 16:44:16.377955  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9943 16:44:16.381322  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9944 16:44:16.384613  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9945 16:44:16.387483  INFO:    [APUAPC] D4_APC_3: 0x0

 9946 16:44:16.390999  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9947 16:44:16.394421  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9948 16:44:16.397882  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9949 16:44:16.400854  INFO:    [APUAPC] D5_APC_3: 0x0

 9950 16:44:16.404332  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9951 16:44:16.407950  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9952 16:44:16.410911  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9953 16:44:16.414634  INFO:    [APUAPC] D6_APC_3: 0x0

 9954 16:44:16.417714  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9955 16:44:16.421282  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9956 16:44:16.424264  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9957 16:44:16.427331  INFO:    [APUAPC] D7_APC_3: 0x0

 9958 16:44:16.430767  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9959 16:44:16.434417  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9960 16:44:16.437876  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9961 16:44:16.440879  INFO:    [APUAPC] D8_APC_3: 0x0

 9962 16:44:16.443891  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9963 16:44:16.447410  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9964 16:44:16.451012  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9965 16:44:16.453867  INFO:    [APUAPC] D9_APC_3: 0x0

 9966 16:44:16.457476  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9967 16:44:16.460909  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9968 16:44:16.463668  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9969 16:44:16.467115  INFO:    [APUAPC] D10_APC_3: 0x0

 9970 16:44:16.470605  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9971 16:44:16.474071  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9972 16:44:16.477154  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9973 16:44:17.137118  INFO:    [APUAPC] D11_APC_3: 0x0

 9974 16:44:17.138015  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9975 16:44:17.138594  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9976 16:44:17.139089  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9977 16:44:17.139529  INFO:    [APUAPC] D12_APC_3: 0x0

 9978 16:44:17.139948  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9979 16:44:17.140409  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9980 16:44:17.140821  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9981 16:44:17.141224  INFO:    [APUAPC] D13_APC_3: 0x0

 9982 16:44:17.141517  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9983 16:44:17.141606  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9984 16:44:17.141787  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9985 16:44:17.141876  INFO:    [APUAPC] D14_APC_3: 0x0

 9986 16:44:17.141989  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9987 16:44:17.142076  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9988 16:44:17.142162  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9989 16:44:17.142249  INFO:    [APUAPC] D15_APC_3: 0x0

 9990 16:44:17.142334  INFO:    [APUAPC] APC_CON: 0x4

 9991 16:44:17.142418  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9992 16:44:17.142502  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9993 16:44:17.142585  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9994 16:44:17.142668  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9995 16:44:17.142752  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9996 16:44:17.142838  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9997 16:44:17.142922  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9998 16:44:17.143005  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9999 16:44:17.143088  INFO:    [NOCDAPC] D4_APC_0: 0x0

10000 16:44:17.143171  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10001 16:44:17.143254  INFO:    [NOCDAPC] D5_APC_0: 0x0

10002 16:44:17.143337  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10003 16:44:17.143420  INFO:    [NOCDAPC] D6_APC_0: 0x0

10004 16:44:17.143521  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10005 16:44:17.143619  INFO:    [NOCDAPC] D7_APC_0: 0x0

10006 16:44:17.143702  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10007 16:44:17.143832  INFO:    [NOCDAPC] D8_APC_0: 0x0

10008 16:44:17.143917  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10009 16:44:17.144024  INFO:    [NOCDAPC] D9_APC_0: 0x0

10010 16:44:17.144108  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10011 16:44:17.144191  INFO:    [NOCDAPC] D10_APC_0: 0x0

10012 16:44:17.144274  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10013 16:44:17.144357  INFO:    [NOCDAPC] D11_APC_0: 0x0

10014 16:44:17.144440  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10015 16:44:17.144538  INFO:    [NOCDAPC] D12_APC_0: 0x0

10016 16:44:17.144612  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10017 16:44:17.144667  INFO:    [NOCDAPC] D13_APC_0: 0x0

10018 16:44:17.144722  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10019 16:44:17.144776  INFO:    [NOCDAPC] D14_APC_0: 0x0

10020 16:44:17.144831  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10021 16:44:17.144886  INFO:    [NOCDAPC] D15_APC_0: 0x0

10022 16:44:17.144981  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10023 16:44:17.145039  INFO:    [NOCDAPC] APC_CON: 0x4

10024 16:44:17.145114  INFO:    [APUAPC] set_apusys_apc done

10025 16:44:17.145232  INFO:    [DEVAPC] devapc_init done

10026 16:44:17.145292  INFO:    GICv3 without legacy support detected.

10027 16:44:17.145373  INFO:    ARM GICv3 driver initialized in EL3

10028 16:44:17.145457  INFO:    Maximum SPI INTID supported: 639

10029 16:44:17.145541  INFO:    BL31: Initializing runtime services

10030 16:44:17.145625  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10031 16:44:17.145709  INFO:    SPM: enable CPC mode

10032 16:44:17.145824  INFO:    mcdi ready for mcusys-off-idle and system suspend

10033 16:44:17.145942  INFO:    BL31: Preparing for EL3 exit to normal world

10034 16:44:17.146026  INFO:    Entry point address = 0x80000000

10035 16:44:17.146109  INFO:    SPSR = 0x8

10036 16:44:17.146191  

10037 16:44:17.146290  

10038 16:44:17.146374  

10039 16:44:17.146480  Starting depthcharge on Spherion...

10040 16:44:17.146571  

10041 16:44:17.146661  Wipe memory regions:

10042 16:44:17.146751  

10043 16:44:17.146842  	[0x00000040000000, 0x00000054600000)

10044 16:44:17.146932  

10045 16:44:17.147023  	[0x00000054660000, 0x00000080000000)

10046 16:44:17.147114  

10047 16:44:17.147204  	[0x000000821a7280, 0x000000ffe64000)

10048 16:44:17.148080  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10049 16:44:17.148196  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10050 16:44:17.148292  Setting prompt string to ['asurada:']
10051 16:44:17.148382  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10052 16:44:17.822283  

10053 16:44:17.822463  	[0x00000100000000, 0x00000240000000)

10054 16:44:19.711512  

10055 16:44:19.714729  Initializing XHCI USB controller at 0x11200000.

10056 16:44:20.753312  

10057 16:44:20.756202  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10058 16:44:20.756319  

10059 16:44:20.756412  

10060 16:44:20.756501  

10061 16:44:20.756805  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10063 16:44:20.857232  asurada: tftpboot 192.168.201.1 10576290/tftp-deploy-q_z35kvn/kernel/image.itb 10576290/tftp-deploy-q_z35kvn/kernel/cmdline 

10064 16:44:20.857411  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10065 16:44:20.857503  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10066 16:44:20.861807  tftpboot 192.168.201.1 10576290/tftp-deploy-q_z35kvn/kernel/image.ittp-deploy-q_z35kvn/kernel/cmdline 

10067 16:44:20.861899  

10068 16:44:20.861965  Waiting for link

10069 16:44:21.019873  

10070 16:44:21.020034  R8152: Initializing

10071 16:44:21.020106  

10072 16:44:21.023414  Version 6 (ocp_data = 5c30)

10073 16:44:21.023498  

10074 16:44:21.026934  R8152: Done initializing

10075 16:44:21.027018  

10076 16:44:21.027175  Adding net device

10077 16:44:23.057988  

10078 16:44:23.058488  done.

10079 16:44:23.058835  

10080 16:44:23.059153  MAC: 00:24:32:30:78:52

10081 16:44:23.059462  

10082 16:44:23.061117  Sending DHCP discover... done.

10083 16:44:23.061567  

10084 16:44:23.065300  Waiting for reply... done.

10085 16:44:23.065904  

10086 16:44:23.067738  Sending DHCP request... done.

10087 16:44:23.068278  

10088 16:44:23.076523  Waiting for reply... done.

10089 16:44:23.076955  

10090 16:44:23.077355  My ip is 192.168.201.14

10091 16:44:23.077686  

10092 16:44:23.080009  The DHCP server ip is 192.168.201.1

10093 16:44:23.080440  

10094 16:44:23.087087  TFTP server IP predefined by user: 192.168.201.1

10095 16:44:23.087522  

10096 16:44:23.093294  Bootfile predefined by user: 10576290/tftp-deploy-q_z35kvn/kernel/image.itb

10097 16:44:23.093724  

10098 16:44:23.094064  Sending tftp read request... done.

10099 16:44:23.096828  

10100 16:44:23.102345  Waiting for the transfer... 

10101 16:44:23.102844  

10102 16:44:23.693667  00000000 ################################################################

10103 16:44:23.693815  

10104 16:44:24.250023  00080000 ################################################################

10105 16:44:24.250579  

10106 16:44:24.906083  00100000 ################################################################

10107 16:44:24.906746  

10108 16:44:25.477732  00180000 ################################################################

10109 16:44:25.477881  

10110 16:44:26.010028  00200000 ################################################################

10111 16:44:26.010199  

10112 16:44:26.533413  00280000 ################################################################

10113 16:44:26.533569  

10114 16:44:27.057808  00300000 ################################################################

10115 16:44:27.057944  

10116 16:44:27.578552  00380000 ################################################################

10117 16:44:27.578715  

10118 16:44:28.142248  00400000 ################################################################

10119 16:44:28.142409  

10120 16:44:28.670912  00480000 ################################################################

10121 16:44:28.671089  

10122 16:44:29.184795  00500000 ################################################################

10123 16:44:29.184971  

10124 16:44:29.701732  00580000 ################################################################

10125 16:44:29.701878  

10126 16:44:30.226680  00600000 ################################################################

10127 16:44:30.226825  

10128 16:44:30.752327  00680000 ################################################################

10129 16:44:30.752467  

10130 16:44:31.281460  00700000 ################################################################

10131 16:44:31.281601  

10132 16:44:31.810171  00780000 ################################################################

10133 16:44:31.810309  

10134 16:44:32.343004  00800000 ################################################################

10135 16:44:32.343150  

10136 16:44:32.918699  00880000 ################################################################

10137 16:44:32.918849  

10138 16:44:33.457991  00900000 ################################################################

10139 16:44:33.458159  

10140 16:44:33.997425  00980000 ################################################################

10141 16:44:33.997571  

10142 16:44:34.544458  00a00000 ################################################################

10143 16:44:34.544616  

10144 16:44:35.088412  00a80000 ################################################################

10145 16:44:35.088600  

10146 16:44:35.628821  00b00000 ################################################################

10147 16:44:35.628965  

10148 16:44:36.160706  00b80000 ################################################################

10149 16:44:36.160852  

10150 16:44:36.701220  00c00000 ################################################################

10151 16:44:36.701356  

10152 16:44:37.287696  00c80000 ################################################################

10153 16:44:37.287846  

10154 16:44:37.881509  00d00000 ################################################################

10155 16:44:37.881705  

10156 16:44:38.429778  00d80000 ################################################################

10157 16:44:38.429987  

10158 16:44:38.972906  00e00000 ################################################################

10159 16:44:38.973056  

10160 16:44:39.507769  00e80000 ################################################################

10161 16:44:39.507938  

10162 16:44:40.062991  00f00000 ################################################################

10163 16:44:40.063342  

10164 16:44:40.613994  00f80000 ################################################################

10165 16:44:40.614130  

10166 16:44:41.141243  01000000 ################################################################

10167 16:44:41.141405  

10168 16:44:41.670358  01080000 ################################################################

10169 16:44:41.670510  

10170 16:44:42.196435  01100000 ################################################################

10171 16:44:42.196591  

10172 16:44:42.712036  01180000 ################################################################

10173 16:44:42.712177  

10174 16:44:43.309910  01200000 ################################################################

10175 16:44:43.310086  

10176 16:44:43.886289  01280000 ################################################################

10177 16:44:43.886468  

10178 16:44:44.448388  01300000 ################################################################

10179 16:44:44.448553  

10180 16:44:45.010466  01380000 ################################################################

10181 16:44:45.010630  

10182 16:44:45.594308  01400000 ################################################################

10183 16:44:45.594442  

10184 16:44:46.153209  01480000 ################################################################

10185 16:44:46.153341  

10186 16:44:46.821939  01500000 ################################################################

10187 16:44:46.822102  

10188 16:44:47.476827  01580000 ################################################################

10189 16:44:47.476970  

10190 16:44:48.041894  01600000 ################################################################

10191 16:44:48.042032  

10192 16:44:48.595926  01680000 ################################################################

10193 16:44:48.596107  

10194 16:44:49.174279  01700000 ################################################################

10195 16:44:49.174453  

10196 16:44:49.728770  01780000 ################################################################

10197 16:44:49.728953  

10198 16:44:50.267697  01800000 ################################################################

10199 16:44:50.267919  

10200 16:44:50.809422  01880000 ################################################################

10201 16:44:50.809565  

10202 16:44:51.368569  01900000 ################################################################

10203 16:44:51.368707  

10204 16:44:51.892383  01980000 ################################################################

10205 16:44:51.892538  

10206 16:44:52.422563  01a00000 ################################################################

10207 16:44:52.422725  

10208 16:44:52.976121  01a80000 ################################################################

10209 16:44:52.976259  

10210 16:44:53.591411  01b00000 ################################################################

10211 16:44:53.591555  

10212 16:44:54.222064  01b80000 ################################################################

10213 16:44:54.222212  

10214 16:44:54.807115  01c00000 ################################################################

10215 16:44:54.807258  

10216 16:44:55.360705  01c80000 ################################################################

10217 16:44:55.360844  

10218 16:44:55.921405  01d00000 ################################################################

10219 16:44:55.921543  

10220 16:44:56.491720  01d80000 ################################################################

10221 16:44:56.491894  

10222 16:44:57.058206  01e00000 ################################################################

10223 16:44:57.058370  

10224 16:44:57.598826  01e80000 ################################################################

10225 16:44:57.599001  

10226 16:44:58.146207  01f00000 ################################################################

10227 16:44:58.146387  

10228 16:44:58.714952  01f80000 ################################################################

10229 16:44:58.715252  

10230 16:44:59.329724  02000000 ################################################################

10231 16:44:59.329920  

10232 16:44:59.922208  02080000 ################################################################

10233 16:44:59.922731  

10234 16:45:00.541574  02100000 ################################################################

10235 16:45:00.541722  

10236 16:45:01.138733  02180000 ################################################################

10237 16:45:01.138886  

10238 16:45:01.709520  02200000 ################################################################

10239 16:45:01.709653  

10240 16:45:02.317932  02280000 ################################################################

10241 16:45:02.318109  

10242 16:45:02.974762  02300000 ################################################################

10243 16:45:02.974914  

10244 16:45:03.593929  02380000 ################################################################

10245 16:45:03.594082  

10246 16:45:04.169079  02400000 ################################################################

10247 16:45:04.169220  

10248 16:45:04.692718  02480000 ################################################################

10249 16:45:04.692872  

10250 16:45:05.229315  02500000 ################################################################

10251 16:45:05.229483  

10252 16:45:05.783539  02580000 ################################################################

10253 16:45:05.783696  

10254 16:45:06.311084  02600000 ################################################################

10255 16:45:06.311267  

10256 16:45:06.825217  02680000 ################################################################

10257 16:45:06.825384  

10258 16:45:07.348113  02700000 ################################################################

10259 16:45:07.348287  

10260 16:45:07.862618  02780000 ################################################################

10261 16:45:07.862773  

10262 16:45:08.384574  02800000 ################################################################

10263 16:45:08.384773  

10264 16:45:08.995340  02880000 ################################################################

10265 16:45:08.995493  

10266 16:45:09.512171  02900000 ################################################################

10267 16:45:09.512321  

10268 16:45:10.031447  02980000 ################################################################

10269 16:45:10.031604  

10270 16:45:10.560685  02a00000 ################################################################

10271 16:45:10.560835  

10272 16:45:11.091433  02a80000 ################################################################

10273 16:45:11.091618  

10274 16:45:11.624655  02b00000 ################################################################

10275 16:45:11.624892  

10276 16:45:12.148864  02b80000 ################################################################

10277 16:45:12.149016  

10278 16:45:12.709650  02c00000 ################################################################

10279 16:45:12.709806  

10280 16:45:13.230414  02c80000 ################################################################

10281 16:45:13.230568  

10282 16:45:13.762323  02d00000 ################################################################

10283 16:45:13.762467  

10284 16:45:14.337658  02d80000 ################################################################

10285 16:45:14.337822  

10286 16:45:14.889698  02e00000 ################################################################

10287 16:45:14.889865  

10288 16:45:15.448874  02e80000 ################################################################

10289 16:45:15.449022  

10290 16:45:15.985071  02f00000 ################################################################

10291 16:45:15.985231  

10292 16:45:16.509540  02f80000 ################################################################

10293 16:45:16.509682  

10294 16:45:17.050307  03000000 ################################################################

10295 16:45:17.050458  

10296 16:45:17.569758  03080000 ################################################################

10297 16:45:17.569929  

10298 16:45:18.103864  03100000 ################################################################

10299 16:45:18.104085  

10300 16:45:18.628370  03180000 ################################################################

10301 16:45:18.628521  

10302 16:45:19.162243  03200000 ################################################################

10303 16:45:19.162426  

10304 16:45:19.723628  03280000 ################################################################

10305 16:45:19.723790  

10306 16:45:20.274090  03300000 ################################################################

10307 16:45:20.274646  

10308 16:45:20.881741  03380000 ################################################################

10309 16:45:20.881896  

10310 16:45:21.518833  03400000 ################################################################

10311 16:45:21.519406  

10312 16:45:22.064641  03480000 ################################################################

10313 16:45:22.064811  

10314 16:45:22.693987  03500000 ################################################################

10315 16:45:22.694489  

10316 16:45:23.372348  03580000 ################################################################

10317 16:45:23.372540  

10318 16:45:23.925102  03600000 ################################################################

10319 16:45:23.925258  

10320 16:45:24.299734  03680000 ############################################ done.

10321 16:45:24.299907  

10322 16:45:24.303185  The bootfile was 57504646 bytes long.

10323 16:45:24.303304  

10324 16:45:24.306758  Sending tftp read request... done.

10325 16:45:24.306859  

10326 16:45:24.306950  Waiting for the transfer... 

10327 16:45:24.307037  

10328 16:45:24.309711  00000000 # done.

10329 16:45:24.309811  

10330 16:45:24.316825  Command line loaded dynamically from TFTP file: 10576290/tftp-deploy-q_z35kvn/kernel/cmdline

10331 16:45:24.316916  

10332 16:45:24.329922  The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10333 16:45:24.330008  

10334 16:45:24.330075  Loading FIT.

10335 16:45:24.330138  

10336 16:45:24.333374  Image ramdisk-1 has 47372215 bytes.

10337 16:45:24.333457  

10338 16:45:24.336271  Image fdt-1 has 46924 bytes.

10339 16:45:24.336355  

10340 16:45:24.339566  Image kernel-1 has 10083474 bytes.

10341 16:45:24.339649  

10342 16:45:24.346446  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10343 16:45:24.346530  

10344 16:45:24.366362  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10345 16:45:24.366452  

10346 16:45:24.369905  Choosing best match conf-1 for compat google,spherion-rev2.

10347 16:45:24.375225  

10348 16:45:24.400594  Connected to device vid:did:rid of 1ae0:0028:00

10349 16:45:24.415428  

10350 16:45:24.418906  tpm_get_response: command 0x17b, return code 0x0

10351 16:45:24.419018  

10352 16:45:24.422438  ec_init: CrosEC protocol v3 supported (256, 248)

10353 16:45:24.426114  

10354 16:45:24.429179  tpm_cleanup: add release locality here.

10355 16:45:24.429290  

10356 16:45:24.429387  Shutting down all USB controllers.

10357 16:45:24.432887  

10358 16:45:24.432971  Removing current net device

10359 16:45:24.433038  

10360 16:45:24.439592  Exiting depthcharge with code 4 at timestamp: 97132307

10361 16:45:24.439704  

10362 16:45:24.443019  LZMA decompressing kernel-1 to 0x821a6718

10363 16:45:24.443121  

10364 16:45:24.446405  LZMA decompressing kernel-1 to 0x40000000

10365 16:45:25.712440  

10366 16:45:25.712599  jumping to kernel

10367 16:45:25.713026  end: 2.2.4 bootloader-commands (duration 00:01:09) [common]
10368 16:45:25.713133  start: 2.2.5 auto-login-action (timeout 00:03:16) [common]
10369 16:45:25.713212  Setting prompt string to ['Linux version [0-9]']
10370 16:45:25.713282  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10371 16:45:25.713354  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10372 16:45:25.793761  

10373 16:45:25.797078  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10374 16:45:25.800884  start: 2.2.5.1 login-action (timeout 00:03:16) [common]
10375 16:45:25.800979  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10376 16:45:25.801069  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10377 16:45:25.801147  Using line separator: #'\n'#
10378 16:45:25.801210  No login prompt set.
10379 16:45:25.801273  Parsing kernel messages
10380 16:45:25.801331  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10381 16:45:25.801434  [login-action] Waiting for messages, (timeout 00:03:16)
10382 16:45:25.820373  [    0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023

10383 16:45:25.823792  [    0.000000] random: crng init done

10384 16:45:25.827221  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10385 16:45:25.830361  [    0.000000] efi: UEFI not found.

10386 16:45:25.840571  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10387 16:45:25.847264  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10388 16:45:25.856766  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10389 16:45:25.866764  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10390 16:45:25.873270  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10391 16:45:25.877005  [    0.000000] printk: bootconsole [mtk8250] enabled

10392 16:45:25.885906  [    0.000000] NUMA: No NUMA configuration found

10393 16:45:25.892510  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10394 16:45:25.898987  [    0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]

10395 16:45:25.899070  [    0.000000] Zone ranges:

10396 16:45:25.905457  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10397 16:45:25.908566  [    0.000000]   DMA32    empty

10398 16:45:25.915376  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10399 16:45:25.918947  [    0.000000] Movable zone start for each node

10400 16:45:25.921952  [    0.000000] Early memory node ranges

10401 16:45:25.928681  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10402 16:45:25.935091  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10403 16:45:25.941836  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10404 16:45:25.948888  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10405 16:45:25.955611  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10406 16:45:25.961961  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10407 16:45:26.018070  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10408 16:45:26.024551  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10409 16:45:26.031284  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10410 16:45:26.034735  [    0.000000] psci: probing for conduit method from DT.

10411 16:45:26.041014  [    0.000000] psci: PSCIv1.1 detected in firmware.

10412 16:45:26.044350  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10413 16:45:26.051100  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10414 16:45:26.054392  [    0.000000] psci: SMC Calling Convention v1.2

10415 16:45:26.060995  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10416 16:45:26.064700  [    0.000000] Detected VIPT I-cache on CPU0

10417 16:45:26.071046  [    0.000000] CPU features: detected: GIC system register CPU interface

10418 16:45:26.078273  [    0.000000] CPU features: detected: Virtualization Host Extensions

10419 16:45:26.084381  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10420 16:45:26.091136  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10421 16:45:26.097664  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10422 16:45:26.107780  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10423 16:45:26.110651  [    0.000000] alternatives: applying boot alternatives

10424 16:45:26.117643  [    0.000000] Fallback order for Node 0: 0 

10425 16:45:26.123904  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10426 16:45:26.127495  [    0.000000] Policy zone: Normal

10427 16:45:26.137065  [    0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10428 16:45:26.147164  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10429 16:45:26.160135  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10430 16:45:26.169821  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10431 16:45:26.176945  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10432 16:45:26.179867  <6>[    0.000000] software IO TLB: area num 8.

10433 16:45:26.236501  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10434 16:45:26.384971  <6>[    0.000000] Memory: 7926680K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426088K reserved, 32768K cma-reserved)

10435 16:45:26.391830  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10436 16:45:26.398190  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10437 16:45:26.401737  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10438 16:45:26.408490  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10439 16:45:26.414991  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10440 16:45:26.418682  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10441 16:45:26.428494  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10442 16:45:26.434975  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10443 16:45:26.441716  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10444 16:45:26.447972  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10445 16:45:26.451273  <6>[    0.000000] GICv3: 608 SPIs implemented

10446 16:45:26.454480  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10447 16:45:26.461297  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10448 16:45:26.464280  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10449 16:45:26.471540  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10450 16:45:26.484570  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10451 16:45:26.494553  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10452 16:45:26.504564  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10453 16:45:26.511609  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10454 16:45:26.524667  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10455 16:45:26.531634  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10456 16:45:26.537946  <6>[    0.009178] Console: colour dummy device 80x25

10457 16:45:26.548460  <6>[    0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10458 16:45:26.554706  <6>[    0.024349] pid_max: default: 32768 minimum: 301

10459 16:45:26.558002  <6>[    0.029222] LSM: Security Framework initializing

10460 16:45:26.564954  <6>[    0.034160] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10461 16:45:26.575064  <6>[    0.041974] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10462 16:45:26.581311  <6>[    0.051408] cblist_init_generic: Setting adjustable number of callback queues.

10463 16:45:26.587833  <6>[    0.058861] cblist_init_generic: Setting shift to 3 and lim to 1.

10464 16:45:26.594488  <6>[    0.065200] cblist_init_generic: Setting shift to 3 and lim to 1.

10465 16:45:26.601436  <6>[    0.071608] rcu: Hierarchical SRCU implementation.

10466 16:45:26.604574  <6>[    0.076622] rcu: 	Max phase no-delay instances is 1000.

10467 16:45:26.612669  <6>[    0.083646] EFI services will not be available.

10468 16:45:26.615837  <6>[    0.088643] smp: Bringing up secondary CPUs ...

10469 16:45:26.624874  <6>[    0.093723] Detected VIPT I-cache on CPU1

10470 16:45:26.631440  <6>[    0.093795] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10471 16:45:26.638564  <6>[    0.093824] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10472 16:45:26.642015  <6>[    0.094156] Detected VIPT I-cache on CPU2

10473 16:45:26.648342  <6>[    0.094204] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10474 16:45:26.658440  <6>[    0.094220] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10475 16:45:26.661405  <6>[    0.094476] Detected VIPT I-cache on CPU3

10476 16:45:26.668098  <6>[    0.094523] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10477 16:45:26.674456  <6>[    0.094537] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10478 16:45:26.678089  <6>[    0.094845] CPU features: detected: Spectre-v4

10479 16:45:26.684477  <6>[    0.094851] CPU features: detected: Spectre-BHB

10480 16:45:26.688307  <6>[    0.094856] Detected PIPT I-cache on CPU4

10481 16:45:26.694763  <6>[    0.094915] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10482 16:45:26.701408  <6>[    0.094932] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10483 16:45:26.707728  <6>[    0.095229] Detected PIPT I-cache on CPU5

10484 16:45:26.714253  <6>[    0.095291] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10485 16:45:26.720849  <6>[    0.095307] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10486 16:45:26.724595  <6>[    0.095593] Detected PIPT I-cache on CPU6

10487 16:45:26.731167  <6>[    0.095659] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10488 16:45:26.738197  <6>[    0.095675] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10489 16:45:26.744646  <6>[    0.095975] Detected PIPT I-cache on CPU7

10490 16:45:26.751086  <6>[    0.096041] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10491 16:45:26.757958  <6>[    0.096058] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10492 16:45:26.760925  <6>[    0.096105] smp: Brought up 1 node, 8 CPUs

10493 16:45:26.767590  <6>[    0.237386] SMP: Total of 8 processors activated.

10494 16:45:26.770984  <6>[    0.242307] CPU features: detected: 32-bit EL0 Support

10495 16:45:26.781163  <6>[    0.247703] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10496 16:45:26.787460  <6>[    0.256503] CPU features: detected: Common not Private translations

10497 16:45:26.791202  <6>[    0.262978] CPU features: detected: CRC32 instructions

10498 16:45:26.797629  <6>[    0.268330] CPU features: detected: RCpc load-acquire (LDAPR)

10499 16:45:26.804220  <6>[    0.274289] CPU features: detected: LSE atomic instructions

10500 16:45:26.810918  <6>[    0.280070] CPU features: detected: Privileged Access Never

10501 16:45:26.814253  <6>[    0.285886] CPU features: detected: RAS Extension Support

10502 16:45:26.823896  <6>[    0.291495] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10503 16:45:26.827307  <6>[    0.298713] CPU: All CPU(s) started at EL2

10504 16:45:26.833942  <6>[    0.303030] alternatives: applying system-wide alternatives

10505 16:45:26.842736  <6>[    0.313778] devtmpfs: initialized

10506 16:45:26.857813  <6>[    0.322633] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10507 16:45:26.864380  <6>[    0.332596] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)

10508 16:45:26.871395  <6>[    0.340825] pinctrl core: initialized pinctrl subsystem

10509 16:45:26.874946  <6>[    0.347485] DMI not present or invalid.

10510 16:45:26.880988  <6>[    0.351914] NET: Registered PF_NETLINK/PF_ROUTE protocol family

10511 16:45:26.891444  <6>[    0.358806] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations

10512 16:45:26.898056  <6>[    0.366389] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations

10513 16:45:26.907495  <6>[    0.374619] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations

10514 16:45:26.911048  <6>[    0.382869] audit: initializing netlink subsys (disabled)

10515 16:45:26.920954  <5>[    0.388571] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1

10516 16:45:26.927396  <6>[    0.389283] thermal_sys: Registered thermal governor 'step_wise'

10517 16:45:26.934369  <6>[    0.396537] thermal_sys: Registered thermal governor 'power_allocator'

10518 16:45:26.937830  <6>[    0.402794] cpuidle: using governor menu

10519 16:45:26.944059  <6>[    0.413758] NET: Registered PF_QIPCRTR protocol family

10520 16:45:26.951124  <6>[    0.419262] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.

10521 16:45:26.957510  <6>[    0.426367] ASID allocator initialised with 32768 entries

10522 16:45:26.960973  <6>[    0.432934] Serial: AMBA PL011 UART driver

10523 16:45:26.970591  <4>[    0.441599] Trying to register duplicate clock ID: 134

10524 16:45:27.026616  <6>[    0.501151] KASLR enabled

10525 16:45:27.040906  <6>[    0.508896] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages

10526 16:45:27.047298  <6>[    0.515911] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page

10527 16:45:27.054500  <6>[    0.522401] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages

10528 16:45:27.060875  <6>[    0.529406] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page

10529 16:45:27.067584  <6>[    0.535893] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages

10530 16:45:27.074082  <6>[    0.542898] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page

10531 16:45:27.080608  <6>[    0.549386] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages

10532 16:45:27.087386  <6>[    0.556391] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page

10533 16:45:27.090294  <6>[    0.563930] ACPI: Interpreter disabled.

10534 16:45:27.099005  <6>[    0.570321] iommu: Default domain type: Translated 

10535 16:45:27.106072  <6>[    0.575433] iommu: DMA domain TLB invalidation policy: strict mode 

10536 16:45:27.109141  <5>[    0.582090] SCSI subsystem initialized

10537 16:45:27.115598  <6>[    0.586255] usbcore: registered new interface driver usbfs

10538 16:45:27.122665  <6>[    0.591988] usbcore: registered new interface driver hub

10539 16:45:27.125495  <6>[    0.597540] usbcore: registered new device driver usb

10540 16:45:27.132541  <6>[    0.603624] pps_core: LinuxPPS API ver. 1 registered

10541 16:45:27.142304  <6>[    0.608821] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>

10542 16:45:27.145886  <6>[    0.618168] PTP clock support registered

10543 16:45:27.149556  <6>[    0.622411] EDAC MC: Ver: 3.0.0

10544 16:45:27.156790  <6>[    0.627561] FPGA manager framework

10545 16:45:27.160048  <6>[    0.631244] Advanced Linux Sound Architecture Driver Initialized.

10546 16:45:27.163986  <6>[    0.638011] vgaarb: loaded

10547 16:45:27.170633  <6>[    0.641183] clocksource: Switched to clocksource arch_sys_counter

10548 16:45:27.177269  <5>[    0.647622] VFS: Disk quotas dquot_6.6.0

10549 16:45:27.183637  <6>[    0.651808] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10550 16:45:27.187177  <6>[    0.658997] pnp: PnP ACPI: disabled

10551 16:45:27.195040  <6>[    0.665770] NET: Registered PF_INET protocol family

10552 16:45:27.204823  <6>[    0.671369] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10553 16:45:27.216407  <6>[    0.683685] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)

10554 16:45:27.225869  <6>[    0.692501] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)

10555 16:45:27.232867  <6>[    0.700472] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)

10556 16:45:27.239360  <6>[    0.709176] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)

10557 16:45:27.251553  <6>[    0.718916] TCP: Hash tables configured (established 65536 bind 65536)

10558 16:45:27.257792  <6>[    0.725776] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)

10559 16:45:27.265123  <6>[    0.732975] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)

10560 16:45:27.271097  <6>[    0.740680] NET: Registered PF_UNIX/PF_LOCAL protocol family

10561 16:45:27.277834  <6>[    0.746843] RPC: Registered named UNIX socket transport module.

10562 16:45:27.281299  <6>[    0.752999] RPC: Registered udp transport module.

10563 16:45:27.288073  <6>[    0.757934] RPC: Registered tcp transport module.

10564 16:45:27.294511  <6>[    0.762866] RPC: Registered tcp NFSv4.1 backchannel transport module.

10565 16:45:27.297929  <6>[    0.769535] PCI: CLS 0 bytes, default 64

10566 16:45:27.301147  <6>[    0.773883] Unpacking initramfs...

10567 16:45:27.310960  <6>[    0.777995] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available

10568 16:45:27.317859  <6>[    0.786648] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available

10569 16:45:27.325096  <6>[    0.795512] kvm [1]: IPA Size Limit: 40 bits

10570 16:45:27.327929  <6>[    0.800046] kvm [1]: GICv3: no GICV resource entry

10571 16:45:27.334962  <6>[    0.805067] kvm [1]: disabling GICv2 emulation

10572 16:45:27.341060  <6>[    0.809754] kvm [1]: GIC system register CPU interface enabled

10573 16:45:27.344626  <6>[    0.815936] kvm [1]: vgic interrupt IRQ18

10574 16:45:27.351012  <6>[    0.820295] kvm [1]: VHE mode initialized successfully

10575 16:45:27.354762  <5>[    0.826745] Initialise system trusted keyrings

10576 16:45:27.361367  <6>[    0.831558] workingset: timestamp_bits=42 max_order=21 bucket_order=0

10577 16:45:27.370821  <6>[    0.841773] squashfs: version 4.0 (2009/01/31) Phillip Lougher

10578 16:45:27.377549  <5>[    0.848160] NFS: Registering the id_resolver key type

10579 16:45:27.380959  <5>[    0.853458] Key type id_resolver registered

10580 16:45:27.388034  <5>[    0.857872] Key type id_legacy registered

10581 16:45:27.394664  <6>[    0.862152] nfs4filelayout_init: NFSv4 File Layout Driver Registering...

10582 16:45:27.400896  <6>[    0.869072] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...

10583 16:45:27.407452  <6>[    0.876776] 9p: Installing v9fs 9p2000 file system support

10584 16:45:27.443131  <5>[    0.914300] Key type asymmetric registered

10585 16:45:27.447019  <5>[    0.918631] Asymmetric key parser 'x509' registered

10586 16:45:27.457048  <6>[    0.923778] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)

10587 16:45:27.460126  <6>[    0.931392] io scheduler mq-deadline registered

10588 16:45:27.463461  <6>[    0.936152] io scheduler kyber registered

10589 16:45:27.482456  <6>[    0.953085] EINJ: ACPI disabled.

10590 16:45:27.514866  <4>[    0.978890] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10591 16:45:27.524957  <4>[    0.989513] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10592 16:45:27.539270  <6>[    1.010369] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled

10593 16:45:27.547423  <6>[    1.018368] printk: console [ttyS0] disabled

10594 16:45:27.575284  <6>[    1.043014] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2

10595 16:45:27.581807  <6>[    1.052492] printk: console [ttyS0] enabled

10596 16:45:27.585291  <6>[    1.052492] printk: console [ttyS0] enabled

10597 16:45:27.592097  <6>[    1.061386] printk: bootconsole [mtk8250] disabled

10598 16:45:27.594961  <6>[    1.061386] printk: bootconsole [mtk8250] disabled

10599 16:45:27.601815  <6>[    1.072605] SuperH (H)SCI(F) driver initialized

10600 16:45:27.604682  <6>[    1.077864] msm_serial: driver initialized

10601 16:45:27.618977  <6>[    1.086767] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10602 16:45:27.628937  <6>[    1.095313] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10603 16:45:27.635533  <6>[    1.103855] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10604 16:45:27.645724  <6>[    1.112484] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10605 16:45:27.655311  <6>[    1.121190] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10606 16:45:27.661810  <6>[    1.129910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10607 16:45:27.671835  <6>[    1.138451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10608 16:45:27.678736  <6>[    1.147259] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10609 16:45:27.688198  <6>[    1.155802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10610 16:45:27.699935  <6>[    1.171356] loop: module loaded

10611 16:45:27.706883  <6>[    1.177389] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10612 16:45:27.729469  <4>[    1.200785] mtk-pmic-keys: Failed to locate of_node [id: -1]

10613 16:45:27.736663  <6>[    1.207745] megasas: 07.719.03.00-rc1

10614 16:45:27.746168  <6>[    1.217503] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10615 16:45:27.753430  <6>[    1.224565] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10616 16:45:27.769917  <6>[    1.241258] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10617 16:45:27.830998  <6>[    1.295566] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7

10618 16:45:29.332109  <6>[    2.803391] Freeing initrd memory: 46256K

10619 16:45:29.342712  <6>[    2.813745] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10620 16:45:29.353655  <6>[    2.824887] tun: Universal TUN/TAP device driver, 1.6

10621 16:45:29.356586  <6>[    2.830963] thunder_xcv, ver 1.0

10622 16:45:29.360235  <6>[    2.834471] thunder_bgx, ver 1.0

10623 16:45:29.363225  <6>[    2.837969] nicpf, ver 1.0

10624 16:45:29.374060  <6>[    2.841992] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10625 16:45:29.377174  <6>[    2.849468] hns3: Copyright (c) 2017 Huawei Corporation.

10626 16:45:29.383875  <6>[    2.855058] hclge is initializing

10627 16:45:29.387283  <6>[    2.858638] e1000: Intel(R) PRO/1000 Network Driver

10628 16:45:29.393609  <6>[    2.863768] e1000: Copyright (c) 1999-2006 Intel Corporation.

10629 16:45:29.396951  <6>[    2.869784] e1000e: Intel(R) PRO/1000 Network Driver

10630 16:45:29.403484  <6>[    2.875000] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10631 16:45:29.410592  <6>[    2.881193] igb: Intel(R) Gigabit Ethernet Network Driver

10632 16:45:29.417204  <6>[    2.886844] igb: Copyright (c) 2007-2014 Intel Corporation.

10633 16:45:29.423684  <6>[    2.892685] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10634 16:45:29.430159  <6>[    2.899204] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10635 16:45:29.433562  <6>[    2.905667] sky2: driver version 1.30

10636 16:45:29.440178  <6>[    2.910670] VFIO - User Level meta-driver version: 0.3

10637 16:45:29.447832  <6>[    2.918801] usbcore: registered new interface driver usb-storage

10638 16:45:29.453766  <6>[    2.925250] usbcore: registered new device driver onboard-usb-hub

10639 16:45:29.462502  <6>[    2.934263] mt6397-rtc mt6359-rtc: registered as rtc0

10640 16:45:29.472973  <6>[    2.939757] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:45:29 UTC (1685810729)

10641 16:45:29.475788  <6>[    2.949393] i2c_dev: i2c /dev entries driver

10642 16:45:29.492931  <6>[    2.961034] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10643 16:45:29.500251  <6>[    2.971274] sdhci: Secure Digital Host Controller Interface driver

10644 16:45:29.506315  <6>[    2.977710] sdhci: Copyright(c) Pierre Ossman

10645 16:45:29.512866  <6>[    2.983112] Synopsys Designware Multimedia Card Interface Driver

10646 16:45:29.516371  <6>[    2.989810] mmc0: CQHCI version 5.10

10647 16:45:29.522910  <6>[    2.990265] sdhci-pltfm: SDHCI platform and OF driver helper

10648 16:45:29.530672  <6>[    3.002092] ledtrig-cpu: registered to indicate activity on CPUs

10649 16:45:29.541866  <6>[    3.009544] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10650 16:45:29.544614  <6>[    3.016949] usbcore: registered new interface driver usbhid

10651 16:45:29.551162  <6>[    3.022776] usbhid: USB HID core driver

10652 16:45:29.557993  <6>[    3.027033] spi_master spi0: will run message pump with realtime priority

10653 16:45:29.600530  <6>[    3.065471] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10654 16:45:29.619336  <6>[    3.080739] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10655 16:45:29.622884  <6>[    3.094297] mmc0: Command Queue Engine enabled

10656 16:45:29.629505  <6>[    3.099063] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10657 16:45:29.635863  <6>[    3.106001] cros-ec-spi spi0.0: Chrome EC device registered

10658 16:45:29.639329  <6>[    3.106395] mmcblk0: mmc0:0001 DA4128 116 GiB 

10659 16:45:29.648814  <6>[    3.120232]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10660 16:45:29.655960  <6>[    3.127444] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10661 16:45:29.662515  <6>[    3.133374] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10662 16:45:29.669065  <6>[    3.139274] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10663 16:45:29.686437  <6>[    3.154905] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10664 16:45:29.695058  <6>[    3.166337] NET: Registered PF_PACKET protocol family

10665 16:45:29.698436  <6>[    3.171768] 9pnet: Installing 9P2000 support

10666 16:45:29.704911  <5>[    3.176345] Key type dns_resolver registered

10667 16:45:29.708115  <6>[    3.181384] registered taskstats version 1

10668 16:45:29.714990  <5>[    3.185782] Loading compiled-in X.509 certificates

10669 16:45:29.748994  <4>[    3.213935] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10670 16:45:29.758961  <4>[    3.224626] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10671 16:45:29.769026  <3>[    3.237272] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10672 16:45:29.781418  <6>[    3.252651] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10673 16:45:29.787710  <6>[    3.259429] xhci-mtk 11200000.usb: xHCI Host Controller

10674 16:45:29.794866  <6>[    3.264937] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10675 16:45:29.804840  <6>[    3.272794] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10676 16:45:29.811195  <6>[    3.282246] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10677 16:45:29.817999  <6>[    3.288483] xhci-mtk 11200000.usb: xHCI Host Controller

10678 16:45:29.824758  <6>[    3.293998] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10679 16:45:29.831046  <6>[    3.301656] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10680 16:45:29.838146  <6>[    3.309562] hub 1-0:1.0: USB hub found

10681 16:45:29.841773  <6>[    3.313613] hub 1-0:1.0: 1 port detected

10682 16:45:29.851333  <6>[    3.317962] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10683 16:45:29.854453  <6>[    3.326777] hub 2-0:1.0: USB hub found

10684 16:45:29.858120  <6>[    3.330820] hub 2-0:1.0: 1 port detected

10685 16:45:29.866975  <6>[    3.337935] mtk-msdc 11f70000.mmc: Got CD GPIO

10686 16:45:29.883318  <6>[    3.351363] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10687 16:45:29.889926  <6>[    3.359398] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10688 16:45:29.899929  <4>[    3.367481] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10689 16:45:29.909958  <6>[    3.377140] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10690 16:45:29.916354  <6>[    3.385266] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10691 16:45:29.926264  <6>[    3.393290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10692 16:45:29.932834  <6>[    3.401248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10693 16:45:29.939469  <6>[    3.409072] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10694 16:45:29.949036  <6>[    3.416896] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10695 16:45:29.959613  <6>[    3.427650] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10696 16:45:29.969223  <6>[    3.436014] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10697 16:45:29.975859  <6>[    3.444406] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10698 16:45:29.985818  <6>[    3.452756] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10699 16:45:29.992655  <6>[    3.461125] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10700 16:45:30.002400  <6>[    3.469472] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10701 16:45:30.008721  <6>[    3.477841] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10702 16:45:30.019189  <6>[    3.486188] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10703 16:45:30.025707  <6>[    3.494553] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10704 16:45:30.035750  <6>[    3.502897] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10705 16:45:30.042219  <6>[    3.511241] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10706 16:45:30.051902  <6>[    3.519585] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10707 16:45:30.058249  <6>[    3.527928] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10708 16:45:30.068206  <6>[    3.536272] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10709 16:45:30.075287  <6>[    3.544616] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10710 16:45:30.082386  <6>[    3.553550] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10711 16:45:30.089461  <6>[    3.560986] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10712 16:45:30.096618  <6>[    3.568020] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10713 16:45:30.107150  <6>[    3.575122] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10714 16:45:30.113979  <6>[    3.582408] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10715 16:45:30.123842  <6>[    3.589352] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10716 16:45:30.130297  <6>[    3.598494] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10717 16:45:30.140411  <6>[    3.607654] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10718 16:45:30.150217  <6>[    3.616966] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10719 16:45:30.159804  <6>[    3.626443] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10720 16:45:30.169791  <6>[    3.635919] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10721 16:45:30.176789  <6>[    3.645045] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10722 16:45:30.186265  <6>[    3.654518] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10723 16:45:30.196104  <6>[    3.663646] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10724 16:45:30.206329  <6>[    3.672948] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10725 16:45:30.216115  <6>[    3.683113] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10726 16:45:30.226231  <6>[    3.694535] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10727 16:45:30.249255  <6>[    3.717676] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10728 16:45:30.276765  <6>[    3.747977] hub 2-1:1.0: USB hub found

10729 16:45:30.279790  <6>[    3.752382] hub 2-1:1.0: 3 ports detected

10730 16:45:30.401092  <6>[    3.869453] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10731 16:45:30.555447  <6>[    4.027001] hub 1-1:1.0: USB hub found

10732 16:45:30.559098  <6>[    4.031445] hub 1-1:1.0: 4 ports detected

10733 16:45:30.637701  <6>[    4.105691] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10734 16:45:30.881319  <6>[    4.349456] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10735 16:45:31.013708  <6>[    4.485029] hub 1-1.4:1.0: USB hub found

10736 16:45:31.016591  <6>[    4.489672] hub 1-1.4:1.0: 2 ports detected

10737 16:45:31.313433  <6>[    4.781458] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10738 16:45:31.505207  <6>[    4.973455] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10739 16:45:42.501907  <6>[   15.978020] ALSA device list:

10740 16:45:42.508151  <6>[   15.981275]   No soundcards found.

10741 16:45:42.521169  <6>[   15.993716] Freeing unused kernel memory: 8384K

10742 16:45:42.524057  <6>[   15.998647] Run /init as init process

10743 16:45:42.554093  <6>[   16.027231] NET: Registered PF_INET6 protocol family

10744 16:45:42.557636  <6>[   16.033295] Segment Routing with IPv6

10745 16:45:42.564111  <6>[   16.037225] In-situ OAM (IOAM) with IPv6

10746 16:45:42.598683  <30>[   16.051719] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10747 16:45:42.602229  <30>[   16.075465] systemd[1]: Detected architecture arm64.

10748 16:45:42.602317  

10749 16:45:42.608636  Welcome to Debian GNU/Linux 11 (bullseye)!

10750 16:45:42.608721  

10751 16:45:42.624514  <30>[   16.097601] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10752 16:45:42.772037  <30>[   16.241348] systemd[1]: Queued start job for default target Graphical Interface.

10753 16:45:42.809989  <30>[   16.282733] systemd[1]: Created slice system-getty.slice.

10754 16:45:42.816822  [  OK  ] Created slice system-getty.slice.

10755 16:45:42.833571  <30>[   16.306067] systemd[1]: Created slice system-modprobe.slice.

10756 16:45:42.839826  [  OK  ] Created slice system-modprobe.slice.

10757 16:45:42.857965  <30>[   16.330589] systemd[1]: Created slice system-serial\x2dgetty.slice.

10758 16:45:42.868062  [  OK  ] Created slice system-serial\x2dgetty.slice.

10759 16:45:42.881517  <30>[   16.353971] systemd[1]: Created slice User and Session Slice.

10760 16:45:42.887759  [  OK  ] Created slice User and Session Slice.

10761 16:45:42.908925  <30>[   16.378019] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10762 16:45:42.918817  [  OK  ] Started Dispatch Password …ts to Console Directory Watch.

10763 16:45:42.936394  <30>[   16.405617] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10764 16:45:42.942862  [  OK  ] Started Forward Password R…uests to Wall Directory Watch.

10765 16:45:42.963414  <30>[   16.429566] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10766 16:45:42.970490  <30>[   16.441606] systemd[1]: Reached target Local Encrypted Volumes.

10767 16:45:42.976685  [  OK  ] Reached target Local Encrypted Volumes.

10768 16:45:42.993277  <30>[   16.465816] systemd[1]: Reached target Paths.

10769 16:45:42.996812  [  OK  ] Reached target Paths.

10770 16:45:43.012823  <30>[   16.485518] systemd[1]: Reached target Remote File Systems.

10771 16:45:43.019566  [  OK  ] Reached target Remote File Systems.

10772 16:45:43.036690  <30>[   16.509728] systemd[1]: Reached target Slices.

10773 16:45:43.043340  [  OK  ] Reached target Slices.

10774 16:45:43.056357  <30>[   16.529516] systemd[1]: Reached target Swap.

10775 16:45:43.059760  [  OK  ] Reached target Swap.

10776 16:45:43.080107  <30>[   16.549861] systemd[1]: Listening on initctl Compatibility Named Pipe.

10777 16:45:43.086599  [  OK  ] Listening on initctl Compatibility Named Pipe.

10778 16:45:43.093534  <30>[   16.564577] systemd[1]: Listening on Journal Audit Socket.

10779 16:45:43.099631  [  OK  ] Listening on Journal Audit Socket.

10780 16:45:43.112932  <30>[   16.585772] systemd[1]: Listening on Journal Socket (/dev/log).

10781 16:45:43.119291  [  OK  ] Listening on Journal Socket (/dev/log).

10782 16:45:43.137061  <30>[   16.610246] systemd[1]: Listening on Journal Socket.

10783 16:45:43.143938  [  OK  ] Listening on Journal Socket.

10784 16:45:43.160124  <30>[   16.629885] systemd[1]: Listening on Network Service Netlink Socket.

10785 16:45:43.167121  [  OK  ] Listening on Network Service Netlink Socket.

10786 16:45:43.181491  <30>[   16.654228] systemd[1]: Listening on udev Control Socket.

10787 16:45:43.187935  [  OK  ] Listening on udev Control Socket.

10788 16:45:43.204807  <30>[   16.678163] systemd[1]: Listening on udev Kernel Socket.

10789 16:45:43.211599  [  OK  ] Listening on udev Kernel Socket.

10790 16:45:43.248965  <30>[   16.721844] systemd[1]: Mounting Huge Pages File System...

10791 16:45:43.255781           Mounting Huge Pages File System...

10792 16:45:43.270505  <30>[   16.743749] systemd[1]: Mounting POSIX Message Queue File System...

10793 16:45:43.277640           Mounting POSIX Message Queue File System...

10794 16:45:43.294823  <30>[   16.767640] systemd[1]: Mounting Kernel Debug File System...

10795 16:45:43.301005           Mounting Kernel Debug File System...

10796 16:45:43.319823  <30>[   16.789817] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10797 16:45:43.352774  <30>[   16.821994] systemd[1]: Starting Create list of static device nodes for the current kernel...

10798 16:45:43.358894           Starting Create list of st…odes for the current kernel...

10799 16:45:43.378923  <30>[   16.852015] systemd[1]: Starting Load Kernel Module configfs...

10800 16:45:43.385418           Starting Load Kernel Module configfs...

10801 16:45:43.403122  <30>[   16.875997] systemd[1]: Starting Load Kernel Module drm...

10802 16:45:43.409493           Starting Load Kernel Module drm...

10803 16:45:43.427963  <30>[   16.897785] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10804 16:45:43.438442  <30>[   16.911522] systemd[1]: Starting Journal Service...

10805 16:45:43.442026           Starting Journal Service...

10806 16:45:43.458757  <30>[   16.932038] systemd[1]: Starting Load Kernel Modules...

10807 16:45:43.465733           Starting Load Kernel Modules...

10808 16:45:43.486114  <30>[   16.956140] systemd[1]: Starting Remount Root and Kernel File Systems...

10809 16:45:43.492763           Starting Remount Root and Kernel File Systems...

10810 16:45:43.506797  <30>[   16.979839] systemd[1]: Starting Coldplug All udev Devices...

10811 16:45:43.513400           Starting Coldplug All udev Devices...

10812 16:45:43.531013  <30>[   17.004039] systemd[1]: Mounted Huge Pages File System.

10813 16:45:43.537637  [  OK  ] Mounted Huge Pages File System.

10814 16:45:43.553509  <30>[   17.026512] systemd[1]: Started Journal Service.

10815 16:45:43.559893  [  OK  ] Started Journal Service.

10816 16:45:43.573833  [  OK  ] Mounted POSIX Message Queue File System.

10817 16:45:43.589158  [  OK  ] Mounted Kernel Debug File System.

10818 16:45:43.608708  [  OK  ] Finished Create list of st… nodes for the current kernel.

10819 16:45:43.626207  [  OK  ] Finished Load Kernel Module configfs.

10820 16:45:43.646274  [  OK  ] Finished Load Kernel Module drm.

10821 16:45:43.661984  [  OK  ] Finished Load Kernel Modules.

10822 16:45:43.681198  [FAILED] Failed to start Remount Root and Kernel File Systems.

10823 16:45:43.696682  See 'systemctl status systemd-remount-fs.service' for details.

10824 16:45:43.733684           Mounting Kernel Configuration File System...

10825 16:45:43.755255           Starting Flush Journal to Persistent Storage...

10826 16:45:43.773419  <46>[   17.243197] systemd-journald[172]: Received client request to flush runtime journal.

10827 16:45:43.782088           Starting Load/Save Random Seed...

10828 16:45:43.799735           Starting Apply Kernel Variables...

10829 16:45:43.816096           Starting Create System Users...

10830 16:45:43.830961  [  OK  ] Mounted Kernel Configuration File System.

10831 16:45:43.857375  [  OK  ] Finished Flush Journal to Persistent Storage.

10832 16:45:43.869306  [  OK  ] Finished Load/Save Random Seed.

10833 16:45:43.885571  [  OK  ] Finished Apply Kernel Variables.

10834 16:45:43.901751  [  OK  ] Finished Coldplug All udev Devices.

10835 16:45:43.917365  [  OK  ] Finished Create System Users.

10836 16:45:43.965457           Starting Create Static Device Nodes in /dev...

10837 16:45:43.987997  [  OK  ] Finished Create Static Device Nodes in /dev.

10838 16:45:44.001656  [  OK  ] Reached target Local File Systems (Pre).

10839 16:45:44.017003  [  OK  ] Reached target Local File Systems.

10840 16:45:44.060985           Starting Create Volatile Files and Directories...

10841 16:45:44.084610           Starting Rule-based Manage…for Device Events and Files...

10842 16:45:44.102156  [  OK  ] Finished Create Volatile Files and Directories.

10843 16:45:44.121746  [  OK  ] Started Rule-based Manager for Device Events and Files.

10844 16:45:44.182020           Starting Network Service...

10845 16:45:44.207841           Starting Network Time Synchronization...

10846 16:45:44.229181           Starting Update UTMP about System Boot/Shutdown...

10847 16:45:44.267240  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10848 16:45:44.282209  [  OK  ] Started Network Service.

10849 16:45:44.315006  [  OK  ] Found device /dev/ttyS0.

10850 16:45:44.330536  <6>[   17.799623] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10851 16:45:44.336855  [  OK  ] Started Network Time Synchronization.

10852 16:45:44.362832  <6>[   17.832471] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10853 16:45:44.366309  <6>[   17.839390] remoteproc remoteproc0: scp is available

10854 16:45:44.376134  <6>[   17.840411] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10855 16:45:44.386133  <4>[   17.845668] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10856 16:45:44.396032  <6>[   17.854038] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10857 16:45:44.402587  <6>[   17.860800] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10858 16:45:44.408931  <6>[   17.864016] remoteproc remoteproc0: powering up scp

10859 16:45:44.419684  <4>[   17.885643] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10860 16:45:44.423245  <6>[   17.886051] mc: Linux media interface: v0.10

10861 16:45:44.429335  <4>[   17.886891] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10862 16:45:44.435872  <4>[   17.886891] Fallback method does not support PEC.

10863 16:45:44.442565  [  OK  [<3>[   17.895502] remoteproc remoteproc0: request_firmware failed: -2

10864 16:45:44.449073  0m] Created slic<6>[   17.901437] usbcore: registered new interface driver r8152

10865 16:45:44.459014  e syste<3>[   17.928569] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10866 16:45:44.469289  m-systemd\x2dbac<4>[   17.931067] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10867 16:45:44.472181  klight.slice.

10868 16:45:44.475677  <6>[   17.949301] videodev: Linux video capture interface: v2.00

10869 16:45:44.485758  <4>[   17.950195] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10870 16:45:44.492707  [  OK  [<3>[   17.963118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10871 16:45:44.505799  0m] Reached targ<3>[   17.971008] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10872 16:45:44.512341  et Syst<3>[   17.972379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10873 16:45:44.518823  <6>[   17.991020] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10874 16:45:44.528884  <3>[   17.991995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10875 16:45:44.535413  em Time Set.<6>[   17.998868] pci_bus 0000:00: root bus resource [bus 00-ff]

10876 16:45:44.535500  

10877 16:45:44.542666  <3>[   18.007464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10878 16:45:44.552200  <6>[   18.014056] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10879 16:45:44.562743  <6>[   18.014065] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10880 16:45:44.566349  <6>[   18.014141] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10881 16:45:44.576027  <3>[   18.020643] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10882 16:45:44.582753  <3>[   18.022341] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10883 16:45:44.593479  <6>[   18.029470] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10884 16:45:44.599527  <3>[   18.039382] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10885 16:45:44.609540  <3>[   18.041924] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10886 16:45:44.616678  <6>[   18.045540] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10887 16:45:44.619611  <6>[   18.045676] pci 0000:00:00.0: supports D1 D2

10888 16:45:44.629551  <3>[   18.054454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10889 16:45:44.636557  <6>[   18.062457] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10890 16:45:44.646230  <3>[   18.064574] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10891 16:45:44.652861  <6>[   18.067050] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10892 16:45:44.659292  <6>[   18.067388] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10893 16:45:44.665759  <6>[   18.067425] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10894 16:45:44.675951  <6>[   18.067457] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10895 16:45:44.682802  <6>[   18.067482] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10896 16:45:44.686124  <6>[   18.067698] pci 0000:01:00.0: supports D1 D2

10897 16:45:44.692581  <6>[   18.067706] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10898 16:45:44.703486  <4>[   18.071229] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2

10899 16:45:44.710742  <3>[   18.071438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10900 16:45:44.717330  <3>[   18.071638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10901 16:45:44.727585  <3>[   18.071710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10902 16:45:44.734294  <3>[   18.071718] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10903 16:45:44.744496  <3>[   18.071727] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10904 16:45:44.751528  <3>[   18.071828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10905 16:45:44.758104  <3>[   18.071836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10906 16:45:44.767935  <3>[   18.071843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10907 16:45:44.774914  <3>[   18.071852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10908 16:45:44.785089  <3>[   18.071859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10909 16:45:44.792484  <3>[   18.071888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10910 16:45:44.799000  <6>[   18.081383] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10911 16:45:44.805415  <4>[   18.090813] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)

10912 16:45:44.815618  <6>[   18.095076] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10913 16:45:44.825095  <6>[   18.095920] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10914 16:45:44.835095  <6>[   18.109065] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10915 16:45:44.841536  <6>[   18.114468] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10916 16:45:44.848589  <6>[   18.114487] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10917 16:45:44.858018  <6>[   18.123654] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10918 16:45:44.867701  <6>[   18.131513] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10919 16:45:44.871446  <6>[   18.145367] r8152 2-1.3:1.0 eth0: v1.12.13

10920 16:45:44.877681  <6>[   18.152745] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10921 16:45:44.884366  <6>[   18.165259] usbcore: registered new interface driver cdc_ether

10922 16:45:44.891239  <6>[   18.171649] pci 0000:00:00.0: PCI bridge to [bus 01]

10923 16:45:44.897529  <3>[   18.183003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6

10924 16:45:44.907764  <3>[   18.183814] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10925 16:45:44.917690  <3>[   18.186392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10926 16:45:44.924263  <6>[   18.188773] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10927 16:45:44.930558  <6>[   18.189896] usbcore: registered new interface driver r8153_ecm

10928 16:45:44.933974  <6>[   18.189918] Bluetooth: Core ver 2.22

10929 16:45:44.940665  <6>[   18.189989] NET: Registered PF_BLUETOOTH protocol family

10930 16:45:44.947249  <6>[   18.189992] Bluetooth: HCI device and connection manager initialized

10931 16:45:44.950651  <6>[   18.190010] Bluetooth: HCI socket layer initialized

10932 16:45:44.957185  <6>[   18.190015] Bluetooth: L2CAP socket layer initialized

10933 16:45:44.963719  <6>[   18.190026] Bluetooth: SCO socket layer initialized

10934 16:45:44.967253  <6>[   18.204139] r8152 2-1.3:1.0 enx002432307852: renamed from eth0

10935 16:45:44.973943  <6>[   18.205147] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10936 16:45:44.980728  <6>[   18.206656] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10937 16:45:44.990623  <3>[   18.207098] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10938 16:45:45.003745  <6>[   18.207914] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10939 16:45:45.010691  <6>[   18.208125] usbcore: registered new interface driver uvcvideo

10940 16:45:45.017641  <3>[   18.235740] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10941 16:45:45.024262  <6>[   18.239265] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10942 16:45:45.030577  <6>[   18.247039] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10943 16:45:45.037241  <6>[   18.254013] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10944 16:45:45.044019  <6>[   18.254376] usbcore: registered new interface driver btusb

10945 16:45:45.053782  <4>[   18.255064] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10946 16:45:45.060306  <3>[   18.255075] Bluetooth: hci0: Failed to load firmware file (-2)

10947 16:45:45.063785  <3>[   18.255080] Bluetooth: hci0: Failed to set up firmware (-2)

10948 16:45:45.077058  <4>[   18.255084] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10949 16:45:45.080555  <6>[   18.265749] remoteproc remoteproc0: powering up scp

10950 16:45:45.090686  <4>[   18.558692] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2

10951 16:45:45.097561  <5>[   18.563700] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10952 16:45:45.104163  <3>[   18.568557] remoteproc remoteproc0: request_firmware failed: -2

10953 16:45:45.114383  [  OK  [<3>[   18.582724] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!

10954 16:45:45.120746  0m] Reached targ<5>[   18.587541] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10955 16:45:45.130868  et Syst<4>[   18.600181] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10956 16:45:45.137381  em Time Synchron<6>[   18.610122] cfg80211: failed to load regulatory.db

10957 16:45:45.140627  ized.

10958 16:45:45.191743  <6>[   18.661361] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10959 16:45:45.198806  <6>[   18.668915] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10960 16:45:45.205061           Starting Load/Save Screen …of leds:white:kbd_backlight...

10961 16:45:45.222667  <6>[   18.695776] mt7921e 0000:01:00.0: ASIC revision: 79610010

10962 16:45:45.232710           Starting Network Name Resolution...

10963 16:45:45.253474  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10964 16:45:45.332966  <4>[   18.799522] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10965 16:45:45.381115  [  OK  ] Started Network Name Resolution.

10966 16:45:45.453095  <4>[   18.919571] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10967 16:45:45.459399  [  OK  ] Reached target Bluetooth.

10968 16:45:45.473620  [  OK  ] Reached target Network.

10969 16:45:45.496036  [  OK  ] Reached target Host and Network Name Lookups.

10970 16:45:45.508867  [  OK  ] Reached target System Initialization.

10971 16:45:45.527706  [  OK  ] Started Discard unused blocks once a week.

10972 16:45:45.544155  [  OK  ] Started Daily Cleanup of Temporary Directories.

10973 16:45:45.557786  [  OK  ] Reached target Timers.

10974 16:45:45.573880  <4>[   19.040060] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10975 16:45:45.583551  [  OK  ] Listening on D-Bus System Message Bus Socket.

10976 16:45:45.596752  [  OK  ] Reached target Sockets.

10977 16:45:45.613031  [  OK  ] Reached target Basic System.

10978 16:45:45.632465  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10979 16:45:45.665059  [  OK  ] Started D-Bus System Message Bus.

10980 16:45:45.698804  <4>[   19.165404] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10981 16:45:45.709520           Starting User Login Management...

10982 16:45:45.726762           Starting Permit User Sessions...

10983 16:45:45.745362           Starting Load/Save RF Kill Switch Status...

10984 16:45:45.761235  [  OK  ] Started Load/Save RF Kill Switch Status.

10985 16:45:45.778097  [  OK  ] Finished Permit User Sessions.

10986 16:45:45.787810  [  OK  ] Started Getty on tty1.

10987 16:45:45.811046  [  OK  ] Started Serial Getty on ttyS0.

10988 16:45:45.824395  <4>[   19.290594] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10989 16:45:45.830749  [  OK  ] Reached target Login Prompts.

10990 16:45:45.846875  [  OK  ] Started User Login Management.

10991 16:45:45.865722  [  OK  ] Reached target Multi-User System.

10992 16:45:45.880699  [  OK  ] Reached target Graphical Interface.

10993 16:45:45.921026           Starting Update UTMP about System Runlevel Changes...

10994 16:45:45.951352  <4>[   19.417751] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10995 16:45:45.957724  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10996 16:45:45.979127  

10997 16:45:45.979217  

10998 16:45:45.982657  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10999 16:45:45.982740  

11000 16:45:45.985688  debian-bullseye-arm64 login: root (automatic login)

11001 16:45:45.985771  

11002 16:45:45.985836  

11003 16:45:46.001576  Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun  3 16:27:28 UTC 2023 aarch64

11004 16:45:46.001661  

11005 16:45:46.008143  The programs included with the Debian GNU/Linux system are free software;

11006 16:45:46.015244  the exact distribution terms for each program are described in the

11007 16:45:46.018199  individual files in /usr/share/doc/*/copyright.

11008 16:45:46.018281  

11009 16:45:46.024808  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

11010 16:45:46.028355  permitted by applicable law.

11011 16:45:46.028718  Matched prompt #10: / #
11013 16:45:46.028925  Setting prompt string to ['/ #']
11014 16:45:46.029018  end: 2.2.5.1 login-action (duration 00:00:20) [common]
11016 16:45:46.029212  end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11017 16:45:46.029299  start: 2.2.6 expect-shell-connection (timeout 00:02:56) [common]
11018 16:45:46.029371  Setting prompt string to ['/ #']
11019 16:45:46.029431  Forcing a shell prompt, looking for ['/ #']
11021 16:45:46.079645  / # 

11022 16:45:46.079764  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11023 16:45:46.079844  Waiting using forced prompt support (timeout 00:02:30)
11024 16:45:46.079945  <4>[   19.539846] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11025 16:45:46.084792  

11026 16:45:46.085070  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11027 16:45:46.085169  start: 2.2.7 export-device-env (timeout 00:02:56) [common]
11028 16:45:46.085266  end: 2.2.7 export-device-env (duration 00:00:00) [common]
11029 16:45:46.085350  end: 2.2 depthcharge-retry (duration 00:02:04) [common]
11030 16:45:46.085438  end: 2 depthcharge-action (duration 00:02:04) [common]
11031 16:45:46.085528  start: 3 lava-test-retry (timeout 00:05:00) [common]
11032 16:45:46.085614  start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11033 16:45:46.085690  Using namespace: common
11035 16:45:46.186019  / # #

11036 16:45:46.186171  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 16:45:46.228123  #<4>[   19.659824] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11038 16:45:46.228216  

11039 16:45:46.228467  Using /lava-10576290
11041 16:45:46.328914  / # export SHELL=/bin/sh

11042 16:45:46.329618  export SHELL=/bin/sh<4>[   19.779383] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11043 16:45:46.334884  

11045 16:45:46.436150  / # . /lava-10576290/environment

11046 16:45:46.437007  . /lava-10576290/environment<6>[   19.872199] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307852: link becomes ready

11047 16:45:46.437449  <6>[   19.880097] r8152 2-1.3:1.0 enx002432307852: carrier on

11048 16:45:46.437787  <4>[   19.900567] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

11049 16:45:46.442330  

11051 16:45:46.585399  / # /lava-10576290/bin/lava-test-runner /lava-10576290/0

11052 16:45:46.585936  Test shell timeout: 10s (minimum of the action and connection timeout)
11053 16:45:46.587390  <3>[   20.017737] mt7921e 0000:01:00.0: hardware init failed

11054 16:45:46.591483  /lava-10576290/bin/lava-test-runner /la

11055 16:45:46.601802  /lava-10576290/bin/lava-test-runner: 18: .: cannot open /la/../bin/lava-common-functions: No such file

11056 16:46:12.674252  / # <6>[   46.153526] vpu: disabling

11057 16:46:12.677618  <6>[   46.156583] vproc2: disabling

11058 16:46:12.680555  <6>[   46.159863] vproc1: disabling

11059 16:46:12.684158  <6>[   46.163125] vaud18: disabling

11060 16:46:12.690366  <6>[   46.166531] vsram_others: disabling

11061 16:46:12.693955  <6>[   46.170408] va09: disabling

11062 16:46:12.697474  <6>[   46.173512] vsram_md: disabling

11063 16:46:12.700194  <6>[   46.176997] Vgpu: disabling

11065 16:50:46.085858  end: 3.1 lava-test-shell (duration 00:05:00) [common]
11067 16:50:46.086155  lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 300 seconds'
11069 16:50:46.086401  end: 3 lava-test-retry (duration 00:05:00) [common]
11071 16:50:46.086770  Cleaning after the job
11072 16:50:46.086909  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/ramdisk
11073 16:50:46.092264  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/kernel
11074 16:50:46.104805  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/dtb
11075 16:50:46.105051  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576290/tftp-deploy-q_z35kvn/modules
11076 16:50:46.110844  start: 4.1 power-off (timeout 00:00:30) [common]
11077 16:50:46.111193  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11078 16:50:46.187070  >> Command sent successfully.

11079 16:50:46.189611  Returned 0 in 0 seconds
11080 16:50:46.290014  end: 4.1 power-off (duration 00:00:00) [common]
11082 16:50:46.290500  start: 4.2 read-feedback (timeout 00:10:00) [common]
11083 16:50:46.290832  Listened to connection for namespace 'common' for up to 1s
11084 16:50:47.291737  Finalising connection for namespace 'common'
11085 16:50:47.291921  Disconnecting from shell: Finalise
11086 16:50:47.392267  end: 4.2 read-feedback (duration 00:00:01) [common]
11087 16:50:47.392435  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576290
11088 16:50:47.493929  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576290
11089 16:50:47.494118  TestError: A test failed to run, look at the error message.