Boot log: qemu_arm64-virt-gicv3
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 4
1 16:58:00.749336 lava-dispatcher, installed at version: 2023.01
2 16:58:00.749520 start: 0 validate
3 16:58:00.749632 Start time: 2023-06-03 16:58:00.749625+00:00 (UTC)
4 16:58:00.750659 Validating that http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image exists
5 16:58:01.109113 Validating that http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz exists
6 16:58:01.288433 cmd: ['docker', 'pull', 'kernelci/qemu']
7 16:58:01.288687 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
8 16:58:01.447444 >> Using default tag: latest
9 16:58:02.925596 >> latest: Pulling from kernelci/qemu
10 16:58:03.049463 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
11 16:58:03.049718 >> Status: Image is up to date for kernelci/qemu:latest
12 16:58:03.182657 >> docker.io/kernelci/qemu:latest
13 16:58:03.186114 Returned 0 in 1 seconds
14 16:58:03.324822 cmd: ['docker', 'run', '--rm', '--init', 'kernelci/qemu', 'qemu-system-aarch64', '--version']
15 16:58:03.325201 Calling: 'nice' 'docker' 'run' '--rm' '--init' 'kernelci/qemu' 'qemu-system-aarch64' '--version'
16 16:58:09.542036 >> QEMU emulator version 7.2.2 (Debian 1:7.2+dfsg-7~bpo11+1)
17 16:58:09.542408 >> Copyright (c) 2003-2022 Fabrice Bellard and the QEMU Project developers
18 16:58:11.932433 Returned 0 in 8 seconds
19 16:58:12.033555 validate duration: 11.28
21 16:58:12.033991 start: 1 deployimages (timeout 00:03:00) [common]
22 16:58:12.034129 start: 1.1 lava-overlay (timeout 00:03:00) [common]
23 16:58:12.034521 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri
24 16:58:12.034720 makedir: /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin
25 16:58:12.034873 makedir: /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/tests
26 16:58:12.035019 makedir: /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/results
27 16:58:12.035179 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-add-keys
28 16:58:12.035391 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-add-sources
29 16:58:12.035583 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-background-process-start
30 16:58:12.035768 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-background-process-stop
31 16:58:12.035931 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-common-functions
32 16:58:12.036098 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-echo-ipv4
33 16:58:12.036276 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-install-packages
34 16:58:12.036443 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-installed-packages
35 16:58:12.036605 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-os-build
36 16:58:12.036782 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-probe-channel
37 16:58:12.036944 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-probe-ip
38 16:58:12.037115 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-target-ip
39 16:58:12.037285 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-target-mac
40 16:58:12.037444 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-target-storage
41 16:58:12.037606 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-case
42 16:58:12.037944 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-event
43 16:58:12.038134 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-feedback
44 16:58:12.038319 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-raise
45 16:58:12.038485 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-reference
46 16:58:12.038644 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-runner
47 16:58:12.038816 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-set
48 16:58:12.038987 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-test-shell
49 16:58:12.039150 Updating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-install-packages (oe)
50 16:58:12.039370 Updating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/bin/lava-installed-packages (oe)
51 16:58:12.039551 Creating /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/environment
52 16:58:12.039701 LAVA metadata
53 16:58:12.039809 - LAVA_JOB_ID=556569
54 16:58:12.039908 - LAVA_DISPATCHER_IP=172.27.0.2
55 16:58:12.040045 start: 1.1.1 lava-vland-overlay (timeout 00:03:00) [common]
56 16:58:12.040138 skipped lava-vland-overlay
57 16:58:12.040241 end: 1.1.1 lava-vland-overlay (duration 00:00:00) [common]
58 16:58:12.040362 start: 1.1.2 lava-multinode-overlay (timeout 00:03:00) [common]
59 16:58:12.040460 skipped lava-multinode-overlay
60 16:58:12.040563 end: 1.1.2 lava-multinode-overlay (duration 00:00:00) [common]
61 16:58:12.040671 start: 1.1.3 test-definition (timeout 00:03:00) [common]
62 16:58:12.040775 Loading test definitions
63 16:58:12.040898 start: 1.1.3.1 inline-repo-action (timeout 00:03:00) [common]
64 16:58:12.041010 Using /lava-556569 at stage 0
65 16:58:12.041456 uuid=556569_1.1.3.1 testdef=None
66 16:58:12.041577 end: 1.1.3.1 inline-repo-action (duration 00:00:00) [common]
67 16:58:12.041701 start: 1.1.3.2 test-overlay (timeout 00:03:00) [common]
68 16:58:12.042350 end: 1.1.3.2 test-overlay (duration 00:00:00) [common]
70 16:58:12.042706 start: 1.1.3.3 test-install-overlay (timeout 00:03:00) [common]
71 16:58:12.043478 end: 1.1.3.3 test-install-overlay (duration 00:00:00) [common]
73 16:58:12.043829 start: 1.1.3.4 test-runscript-overlay (timeout 00:03:00) [common]
74 16:58:12.044591 runner path: /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/0/tests/0_timesync-off test_uuid 556569_1.1.3.1
75 16:58:12.044787 end: 1.1.3.4 test-runscript-overlay (duration 00:00:00) [common]
77 16:58:12.045131 start: 1.1.3.5 git-repo-action (timeout 00:03:00) [common]
78 16:58:12.045240 Using /lava-556569 at stage 0
79 16:58:12.045386 Fetching tests from https://github.com/kernelci/test-definitions.git
80 16:58:12.045505 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/0/tests/1_kselftest-arm64_qemu'
81 16:58:17.179078 Running '/usr/bin/git checkout kernelci.org
82 16:58:17.303611 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/0/tests/1_kselftest-arm64_qemu/automated/linux/kselftest/kselftest.yaml
83 16:58:17.304758 uuid=556569_1.1.3.5 testdef=None
84 16:58:17.305026 end: 1.1.3.5 git-repo-action (duration 00:00:05) [common]
86 16:58:17.305554 start: 1.1.3.6 test-overlay (timeout 00:02:55) [common]
87 16:58:17.307162 end: 1.1.3.6 test-overlay (duration 00:00:00) [common]
89 16:58:17.307690 start: 1.1.3.7 test-install-overlay (timeout 00:02:55) [common]
90 16:58:17.309859 end: 1.1.3.7 test-install-overlay (duration 00:00:00) [common]
92 16:58:17.310424 start: 1.1.3.8 test-runscript-overlay (timeout 00:02:55) [common]
93 16:58:17.312535 runner path: /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/0/tests/1_kselftest-arm64_qemu test_uuid 556569_1.1.3.5
94 16:58:17.312722 BOARD='qemu_arm64-virt-gicv3'
95 16:58:17.312871 BRANCH='cip-gitlab'
96 16:58:17.313019 SKIPFILE='/dev/null'
97 16:58:17.313169 SKIP_INSTALL='True'
98 16:58:17.313316 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
99 16:58:17.313465 TST_CASENAME=''
100 16:58:17.313610 TST_CMDFILES='arm64'
101 16:58:17.313941 end: 1.1.3.8 test-runscript-overlay (duration 00:00:00) [common]
103 16:58:17.314443 Creating lava-test-runner.conf files
104 16:58:17.314600 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/556569/lava-overlay-ue5oljri/lava-556569/0 for stage 0
105 16:58:17.314821 - 0_timesync-off
106 16:58:17.314977 - 1_kselftest-arm64_qemu
107 16:58:17.315202 end: 1.1.3 test-definition (duration 00:00:05) [common]
108 16:58:17.315401 start: 1.1.4 compress-overlay (timeout 00:02:55) [common]
109 16:58:26.751737 end: 1.1.4 compress-overlay (duration 00:00:09) [common]
110 16:58:26.751926 start: 1.1.5 persistent-nfs-overlay (timeout 00:02:45) [common]
111 16:58:26.752019 end: 1.1.5 persistent-nfs-overlay (duration 00:00:00) [common]
112 16:58:26.752126 end: 1.1 lava-overlay (duration 00:00:15) [common]
113 16:58:26.752219 start: 1.2 apply-overlay-guest (timeout 00:02:45) [common]
114 16:58:26.752299 Overlay: /var/lib/lava/dispatcher/tmp/556569/compress-overlay-31fef7oy/overlay-1.1.4.tar.gz
115 16:58:45.566560 end: 1.2 apply-overlay-guest (duration 00:00:19) [common]
117 16:58:45.567171 start: 1.3 deploy-device-env (timeout 00:02:26) [common]
118 16:58:45.567298 end: 1.3 deploy-device-env (duration 00:00:00) [common]
119 16:58:45.567423 start: 1.4 download-retry (timeout 00:02:26) [common]
120 16:58:45.567553 start: 1.4.1 http-download (timeout 00:02:26) [common]
121 16:58:45.567803 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
122 16:58:45.567906 saving as /var/lib/lava/dispatcher/tmp/556569/deployimages-3mxgxodd/kernel/Image
123 16:58:45.568000 total size: 45746688 (43MB)
124 16:58:45.568087 No compression specified
125 16:58:45.924209 progress 0% (0MB)
126 16:58:46.991468 progress 5% (2MB)
127 16:58:47.172388 progress 10% (4MB)
128 16:58:47.370350 progress 15% (6MB)
129 16:58:47.547660 progress 20% (8MB)
130 16:58:47.903301 progress 25% (10MB)
131 16:58:48.086284 progress 30% (13MB)
132 16:58:48.435701 progress 35% (15MB)
133 16:58:48.615432 progress 40% (17MB)
134 16:58:48.972644 progress 45% (19MB)
135 16:58:49.151587 progress 50% (21MB)
136 16:58:49.503553 progress 55% (24MB)
137 16:58:49.854541 progress 60% (26MB)
138 16:58:50.051994 progress 65% (28MB)
139 16:58:50.407960 progress 70% (30MB)
140 16:58:50.756857 progress 75% (32MB)
141 16:58:50.942384 progress 80% (34MB)
142 16:58:51.291837 progress 85% (37MB)
143 16:58:51.476866 progress 90% (39MB)
144 16:58:51.832479 progress 95% (41MB)
145 16:58:52.179359 progress 100% (43MB)
146 16:58:52.179648 43MB downloaded in 6.61s (6.60MB/s)
147 16:58:52.179873 end: 1.4.1 http-download (duration 00:00:07) [common]
149 16:58:52.180263 end: 1.4 download-retry (duration 00:00:07) [common]
150 16:58:52.180396 start: 1.5 download-retry (timeout 00:02:20) [common]
151 16:58:52.180521 start: 1.5.1 http-download (timeout 00:02:20) [common]
152 16:58:52.180725 Not decompressing ramdisk as can be used compressed.
153 16:58:52.180856 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/rootfs.cpio.gz
154 16:58:52.180948 saving as /var/lib/lava/dispatcher/tmp/556569/deployimages-3mxgxodd/ramdisk/rootfs.cpio.gz
155 16:58:52.181042 total size: 88976554 (84MB)
156 16:58:52.181132 No compression specified
157 16:58:52.359985 progress 0% (0MB)
158 16:58:52.727537 progress 5% (4MB)
159 16:58:53.259434 progress 10% (8MB)
160 16:58:53.790812 progress 15% (12MB)
161 16:58:54.322477 progress 20% (17MB)
162 16:58:54.857795 progress 25% (21MB)
163 16:58:55.393471 progress 30% (25MB)
164 16:58:55.924511 progress 35% (29MB)
165 16:58:56.455581 progress 40% (33MB)
166 16:58:56.986325 progress 45% (38MB)
167 16:58:57.516780 progress 50% (42MB)
168 16:58:58.046905 progress 55% (46MB)
169 16:58:58.425482 progress 60% (50MB)
170 16:58:58.954882 progress 65% (55MB)
171 16:58:59.485139 progress 70% (59MB)
172 16:59:00.015036 progress 75% (63MB)
173 16:59:00.544437 progress 80% (67MB)
174 16:59:01.066146 progress 85% (72MB)
175 16:59:01.593507 progress 90% (76MB)
176 16:59:01.986518 progress 95% (80MB)
177 16:59:02.513818 progress 100% (84MB)
178 16:59:02.514199 84MB downloaded in 10.33s (8.21MB/s)
179 16:59:02.514471 end: 1.5.1 http-download (duration 00:00:10) [common]
181 16:59:02.514982 end: 1.5 download-retry (duration 00:00:10) [common]
182 16:59:02.515145 end: 1 deployimages (duration 00:00:50) [common]
183 16:59:02.515311 start: 2 boot-image-retry (timeout 00:05:00) [common]
184 16:59:02.515477 start: 2.1 boot-qemu-image (timeout 00:05:00) [common]
185 16:59:02.515641 start: 2.1.1 execute-qemu (timeout 00:05:00) [common]
186 16:59:02.516008 Extending command line for qcow2 test overlay
187 16:59:02.516618 Pulling docker image
188 16:59:02.516781 cmd: ['docker', 'pull', 'kernelci/qemu']
189 16:59:02.516916 Calling: 'nice' 'docker' 'pull' 'kernelci/qemu'
190 16:59:02.680919 >> Using default tag: latest
191 16:59:03.978769 >> latest: Pulling from kernelci/qemu
192 16:59:04.027776 >> Digest: sha256:fc85786d1b429cf64a5683fdc5d697be0f1ce54a15ccbe3e596ab02286b2b909
193 16:59:04.028066 >> Status: Image is up to date for kernelci/qemu:latest
194 16:59:04.069358 >> docker.io/kernelci/qemu:latest
195 16:59:04.072078 Returned 0 in 1 seconds
196 16:59:04.209554 Boot command: docker run --network=host --cap-add=NET_ADMIN --interactive --tty --rm --init --name=lava-docker-qemu-556569-2.1.1-6gztugztbn --mount=type=bind,source=/var/lib/lava/dispatcher/tmp,destination=/var/lib/lava/dispatcher/tmp kernelci/qemu qemu-system-aarch64 -cpu max,pauth-impdef=on -machine virt,gic-version=3,mte=on,accel=tcg -nographic -net nic,model=virtio,macaddr=52:54:00:12:34:58 -net user -m 1g -monitor none -kernel /var/lib/lava/dispatcher/tmp/556569/deployimages-3mxgxodd/kernel/Image -append "console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon" -initrd /var/lib/lava/dispatcher/tmp/556569/deployimages-3mxgxodd/ramdisk/rootfs.cpio.gz -drive format=qcow2,file=/var/lib/lava/dispatcher/tmp/556569/apply-overlay-guest-nvbg5fuw/lava-guest.qcow2,media=disk,if=virtio,id=lavatest
197 16:59:04.344957 started a shell command
198 16:59:04.345378 end: 2.1.1 execute-qemu (duration 00:00:02) [common]
199 16:59:04.345490 end: 2.1 boot-qemu-image (duration 00:00:02) [common]
200 16:59:04.345593 start: 2.2 auto-login-action (timeout 00:04:58) [common]
201 16:59:04.345703 Setting prompt string to ['Linux version [0-9]']
202 16:59:04.345780 auto-login-action: Wait for prompt ['Linux version [0-9]'] (timeout 00:05:00)
203 16:59:05.791574 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x000f0510]
204 16:59:05.792161 start: 2.2.1 login-action (timeout 00:04:57) [common]
205 16:59:05.792299 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
206 16:59:05.792433 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
207 16:59:05.792554 Using line separator: #'\n'#
208 16:59:05.792653 No login prompt set.
209 16:59:05.792756 Parsing kernel messages
210 16:59:05.792847 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
211 16:59:05.793020 [login-action] Waiting for messages, (timeout 00:04:57)
212 16:59:05.793951 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
213 16:59:05.794065 [ 0.000000] random: crng init done
214 16:59:05.794156 [ 0.000000] Machine model: linux,dummy-virt
215 16:59:05.794245 [ 0.000000] efi: UEFI not found.
216 16:59:05.794334 [ 0.000000] earlycon: pl11 at MMIO 0x0000000009000000 (options '')
217 16:59:05.794421 [ 0.000000] printk: bootconsole [pl11] enabled
218 16:59:05.797057 [ 0.000000] NUMA: No NUMA configuration found
219 16:59:05.797471 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000007fffffff]
220 16:59:05.798172 [ 0.000000] NUMA: NODE_DATA [mem 0x7fdf3a00-0x7fdf5fff]
221 16:59:05.800241 [ 0.000000] Zone ranges:
222 16:59:05.801045 [ 0.000000] DMA [mem 0x0000000040000000-0x000000007fffffff]
223 16:59:05.801156 [ 0.000000] DMA32 empty
224 16:59:05.801263 [ 0.000000] Normal empty
225 16:59:05.801374 [ 0.000000] Movable zone start for each node
226 16:59:05.801479 [ 0.000000] Early memory node ranges
227 16:59:05.801788 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000007fffffff]
228 16:59:05.802312 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000007fffffff]
229 16:59:05.817187 [ 0.000000] cma: Reserved 32 MiB at 0x000000007cc00000
230 16:59:05.818148 [ 0.000000] psci: probing for conduit method from DT.
231 16:59:05.818655 [ 0.000000] psci: PSCIv1.1 detected in firmware.
232 16:59:05.818783 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
233 16:59:05.818956 [ 0.000000] psci: Trusted OS migration not required
234 16:59:05.819258 [ 0.000000] psci: SMC Calling Convention v1.0
235 16:59:05.821720 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
236 16:59:05.822191 [ 0.000000] pcpu-alloc: s45224 r8192 d32600 u86016 alloc=21*4096
237 16:59:05.822670 [ 0.000000] pcpu-alloc: [0] 0
238 16:59:05.824044 [ 0.000000] Detected PIPT I-cache on CPU0
239 16:59:05.829587 [ 0.000000] CPU features: detected: Address authentication (IMP DEF algorithm)
240 16:59:05.830327 [ 0.000000] CPU features: detected: GIC system register CPU interface
241 16:59:05.830659 [ 0.000000] CPU features: detected: Hardware dirty bit management
242 16:59:05.831007 [ 0.000000] CPU features: detected: Memory Tagging Extension
243 16:59:05.831133 [ 0.000000] CPU features: detected: Asymmetric MTE Tag Check Fault
244 16:59:05.831497 [ 0.000000] CPU features: detected: Spectre-v4
245 16:59:05.835479 [ 0.000000] alternatives: applying boot alternatives
246 16:59:05.838358 [ 0.000000] Fallback order for Node 0: 0
247 16:59:05.838704 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 258048
248 16:59:05.838815 [ 0.000000] Policy zone: DMA
249 16:59:05.839358 [ 0.000000] Kernel command line: console=ttyAMA0,115200 root=/dev/ram0 debug verbose console_msg_format=syslog earlycon
250 16:59:05.841872 <5>[ 0.000000] Unknown kernel command line parameters \"verbose\", will be passed to user space.
251 16:59:05.844757 <6>[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes, linear)
252 16:59:05.845326 <6>[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes, linear)
253 16:59:05.845693 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
254 16:59:05.855236 <6>[ 0.000000] Memory: 862480K/1048576K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 153328K reserved, 32768K cma-reserved)
255 16:59:05.861247 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
256 16:59:05.868415 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
257 16:59:05.868633 <6>[ 0.000000] rcu: RCU event tracing is enabled.
258 16:59:05.868747 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=1.
259 16:59:05.869094 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
260 16:59:05.869220 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
261 16:59:05.869567 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
262 16:59:05.869916 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
263 16:59:05.870959 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
264 16:59:05.877919 <6>[ 0.000000] GICv3: 224 SPIs implemented
265 16:59:05.878282 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
266 16:59:05.879977 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
267 16:59:05.880331 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
268 16:59:05.880942 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000
269 16:59:05.885665 <6>[ 0.000000] ITS [mem 0x08080000-0x0809ffff]
270 16:59:05.886563 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Devices @43030000 (indirect, esz 8, psz 64K, shr 1)
271 16:59:05.886995 <6>[ 0.000000] ITS@0x0000000008080000: allocated 8192 Interrupt Collections @43040000 (flat, esz 8, psz 64K, shr 1)
272 16:59:05.887595 <6>[ 0.000000] GICv3: using LPI property table @0x0000000043050000
273 16:59:05.888297 <6>[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000043060000
274 16:59:05.889564 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
275 16:59:05.898184 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 62.50MHz (virt).
276 16:59:05.898675 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0x1ffffffffffffff max_cycles: 0x1cd42e208c, max_idle_ns: 881590405314 ns
277 16:59:05.899097 <6>[ 0.000076] sched_clock: 57 bits at 63MHz, resolution 16ns, wraps every 4398046511096ns
278 16:59:05.917205 <6>[ 0.015288] Console: colour dummy device 80x25
279 16:59:05.921328 <6>[ 0.021577] Calibrating delay loop (skipped), value calculated using timer frequency.. 125.00 BogoMIPS (lpj=250000)
280 16:59:05.921785 <6>[ 0.022787] pid_max: default: 32768 minimum: 301
281 16:59:05.923187 <6>[ 0.024060] LSM: Security Framework initializing
282 16:59:05.927561 <6>[ 0.028316] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
283 16:59:05.927779 <6>[ 0.028579] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes, linear)
284 16:59:05.960729 <4>[ 0.061650] cacheinfo: Unable to detect cache hierarchy for CPU 0
285 16:59:05.967077 <6>[ 0.067806] cblist_init_generic: Setting adjustable number of callback queues.
286 16:59:05.967345 <6>[ 0.068189] cblist_init_generic: Setting shift to 0 and lim to 1.
287 16:59:05.967983 <6>[ 0.068877] cblist_init_generic: Setting shift to 0 and lim to 1.
288 16:59:05.969748 <6>[ 0.070633] rcu: Hierarchical SRCU implementation.
289 16:59:05.969882 <6>[ 0.070816] rcu: Max phase no-delay instances is 1000.
290 16:59:05.975290 <6>[ 0.076323] Platform MSI: its@8080000 domain created
291 16:59:05.976914 <6>[ 0.077589] PCI/MSI: /intc@8000000/its@8080000 domain created
292 16:59:05.977364 <6>[ 0.078222] fsl-mc MSI: its@8080000 domain created
293 16:59:05.979972 <6>[ 0.080860] EFI services will not be available.
294 16:59:05.981013 <6>[ 0.081898] smp: Bringing up secondary CPUs ...
295 16:59:05.981146 <6>[ 0.082134] smp: Brought up 1 node, 1 CPU
296 16:59:05.981258 <6>[ 0.082281] SMP: Total of 1 processors activated.
297 16:59:05.981597 <6>[ 0.082595] CPU features: detected: Branch Target Identification
298 16:59:05.981731 <6>[ 0.082778] CPU features: detected: 32-bit EL0 Support
299 16:59:05.982078 <6>[ 0.082938] CPU features: detected: 32-bit EL1 Support
300 16:59:05.982189 <6>[ 0.083089] CPU features: detected: ARMv8.4 Translation Table Level
301 16:59:05.982305 <6>[ 0.083283] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
302 16:59:05.982729 <6>[ 0.083557] CPU features: detected: Common not Private translations
303 16:59:05.982926 <6>[ 0.083724] CPU features: detected: CRC32 instructions
304 16:59:05.983125 <6>[ 0.083877] CPU features: detected: E0PD
305 16:59:05.983297 <6>[ 0.084053] CPU features: detected: Generic authentication (IMP DEF algorithm)
306 16:59:05.983485 <6>[ 0.084253] CPU features: detected: RCpc load-acquire (LDAPR)
307 16:59:05.983638 <6>[ 0.084419] CPU features: detected: LSE atomic instructions
308 16:59:05.983768 <6>[ 0.084557] CPU features: detected: Privileged Access Never
309 16:59:05.983986 <6>[ 0.084690] CPU features: detected: RAS Extension Support
310 16:59:05.984202 <6>[ 0.085005] CPU features: detected: Random Number Generator
311 16:59:05.984415 <6>[ 0.085145] CPU features: detected: Speculation barrier (SB)
312 16:59:05.984564 <6>[ 0.085302] CPU features: detected: Stage-2 Force Write-Back
313 16:59:05.984719 <6>[ 0.085469] CPU features: detected: TLB range maintenance instructions
314 16:59:05.984876 <6>[ 0.085696] CPU features: detected: Scalable Matrix Extension
315 16:59:05.985052 <6>[ 0.085862] CPU features: detected: FA64
316 16:59:05.985209 <6>[ 0.085971] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
317 16:59:05.985358 <6>[ 0.086151] CPU features: detected: Scalable Vector Extension
318 16:59:05.996869 <6>[ 0.094880] SVE: maximum available vector length 256 bytes per vector
319 16:59:05.997356 <6>[ 0.098275] SVE: default vector length 64 bytes per vector
320 16:59:05.999277 <6>[ 0.100126] SME: minimum available vector length 16 bytes per vector
321 16:59:05.999478 <6>[ 0.100346] SME: maximum available vector length 256 bytes per vector
322 16:59:05.999618 <6>[ 0.100531] SME: default vector length 32 bytes per vector
323 16:59:05.999989 <6>[ 0.100981] CPU: All CPU(s) started at EL1
324 16:59:06.000402 <6>[ 0.101441] alternatives: applying system-wide alternatives
325 16:59:06.055247 <6>[ 0.156091] devtmpfs: initialized
326 16:59:06.075980 <6>[ 0.176550] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
327 16:59:06.076468 <6>[ 0.177391] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
328 16:59:06.082866 <6>[ 0.183641] pinctrl core: initialized pinctrl subsystem
329 16:59:06.094110 <6>[ 0.195092] DMI not present or invalid.
330 16:59:06.103780 <6>[ 0.204435] NET: Registered PF_NETLINK/PF_ROUTE protocol family
331 16:59:06.115581 <6>[ 0.216348] DMA: preallocated 128 KiB GFP_KERNEL pool for atomic allocations
332 16:59:06.116551 <6>[ 0.217345] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
333 16:59:06.116883 <6>[ 0.217815] DMA: preallocated 128 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
334 16:59:06.117346 <6>[ 0.218337] audit: initializing netlink subsys (disabled)
335 16:59:06.124829 <5>[ 0.225611] audit: type=2000 audit(0.184:1): state=initialized audit_enabled=0 res=1
336 16:59:06.125265 <6>[ 0.226232] thermal_sys: Registered thermal governor 'step_wise'
337 16:59:06.126151 <6>[ 0.226301] thermal_sys: Registered thermal governor 'power_allocator'
338 16:59:06.126265 <6>[ 0.226999] cpuidle: using governor menu
339 16:59:06.127135 <6>[ 0.228063] NET: Registered PF_QIPCRTR protocol family
340 16:59:06.130510 <6>[ 0.231310] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
341 16:59:06.130971 <6>[ 0.231970] ASID allocator initialised with 65536 entries
342 16:59:06.136726 <6>[ 0.237814] Serial: AMBA PL011 UART driver
343 16:59:06.185153 <6>[ 0.285761] 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = 13, base_baud = 0) is a PL011 rev1
344 16:59:06.186803 <6>[ 0.287519] printk: console [ttyAMA0] enabled
345 16:59:06.186997 <6>[ 0.287519] printk: console [ttyAMA0] enabled
346 16:59:06.187182 <6>[ 0.288021] printk: bootconsole [pl11] disabled
347 16:59:06.187316 <6>[ 0.288021] printk: bootconsole [pl11] disabled
348 16:59:06.198304 <6>[ 0.299310] KASLR enabled
349 16:59:06.232877 <6>[ 0.333795] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
350 16:59:06.233398 <6>[ 0.334017] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
351 16:59:06.233510 <6>[ 0.334242] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
352 16:59:06.233601 <6>[ 0.334428] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
353 16:59:06.233716 <6>[ 0.334586] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
354 16:59:06.233804 <6>[ 0.334750] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
355 16:59:06.234056 <6>[ 0.334921] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
356 16:59:06.234174 <6>[ 0.335121] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
357 16:59:06.243645 <6>[ 0.344666] ACPI: Interpreter disabled.
358 16:59:06.251716 <6>[ 0.352680] iommu: Default domain type: Translated
359 16:59:06.252333 <6>[ 0.352918] iommu: DMA domain TLB invalidation policy: strict mode
360 16:59:06.254022 <5>[ 0.354793] SCSI subsystem initialized
361 16:59:06.255061 <7>[ 0.355937] libata version 3.00 loaded.
362 16:59:06.256612 <6>[ 0.357449] usbcore: registered new interface driver usbfs
363 16:59:06.256875 <6>[ 0.357890] usbcore: registered new interface driver hub
364 16:59:06.257312 <6>[ 0.358244] usbcore: registered new device driver usb
365 16:59:06.261514 <6>[ 0.362272] pps_core: LinuxPPS API ver. 1 registered
366 16:59:06.261764 <6>[ 0.362489] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
367 16:59:06.261864 <6>[ 0.362865] PTP clock support registered
368 16:59:06.262578 <6>[ 0.363510] EDAC MC: Ver: 3.0.0
369 16:59:06.268314 <6>[ 0.369387] FPGA manager framework
370 16:59:06.269382 <6>[ 0.370212] Advanced Linux Sound Architecture Driver Initialized.
371 16:59:06.278540 <6>[ 0.379609] vgaarb: loaded
372 16:59:06.282707 <6>[ 0.383495] clocksource: Switched to clocksource arch_sys_counter
373 16:59:06.283861 <5>[ 0.384746] VFS: Disk quotas dquot_6.6.0
374 16:59:06.284237 <6>[ 0.385021] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
375 16:59:06.287313 <6>[ 0.388378] pnp: PnP ACPI: disabled
376 16:59:06.304977 <6>[ 0.405937] NET: Registered PF_INET protocol family
377 16:59:06.307447 <6>[ 0.408271] IP idents hash table entries: 16384 (order: 5, 131072 bytes, linear)
378 16:59:06.312308 <6>[ 0.413154] tcp_listen_portaddr_hash hash table entries: 512 (order: 1, 8192 bytes, linear)
379 16:59:06.312492 <6>[ 0.413459] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
380 16:59:06.312830 <6>[ 0.413792] TCP established hash table entries: 8192 (order: 4, 65536 bytes, linear)
381 16:59:06.313388 <6>[ 0.414287] TCP bind hash table entries: 8192 (order: 6, 262144 bytes, linear)
382 16:59:06.313956 <6>[ 0.414866] TCP: Hash tables configured (established 8192 bind 8192)
383 16:59:06.315336 <6>[ 0.416237] UDP hash table entries: 512 (order: 2, 16384 bytes, linear)
384 16:59:06.315691 <6>[ 0.416635] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes, linear)
385 16:59:06.316960 <6>[ 0.417842] NET: Registered PF_UNIX/PF_LOCAL protocol family
386 16:59:06.319842 <6>[ 0.420714] RPC: Registered named UNIX socket transport module.
387 16:59:06.319978 <6>[ 0.420924] RPC: Registered udp transport module.
388 16:59:06.320094 <6>[ 0.421055] RPC: Registered tcp transport module.
389 16:59:06.320202 <6>[ 0.421212] RPC: Registered tcp NFSv4.1 backchannel transport module.
390 16:59:06.320539 <6>[ 0.421511] PCI: CLS 0 bytes, default 64
391 16:59:06.324462 <6>[ 0.425561] Unpacking initramfs...
392 16:59:06.336355 <6>[ 0.437297] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
393 16:59:06.337228 <6>[ 0.438093] kvm [1]: HYP mode not available
394 16:59:06.345076 <5>[ 0.446092] Initialise system trusted keyrings
395 16:59:06.347252 <6>[ 0.448122] workingset: timestamp_bits=42 max_order=18 bucket_order=0
396 16:59:06.387215 <6>[ 0.488189] squashfs: version 4.0 (2009/01/31) Phillip Lougher
397 16:59:06.392076 <5>[ 0.492880] NFS: Registering the id_resolver key type
398 16:59:06.392553 <5>[ 0.493346] Key type id_resolver registered
399 16:59:06.392728 <5>[ 0.493529] Key type id_legacy registered
400 16:59:06.393202 <6>[ 0.494097] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
401 16:59:06.393416 <6>[ 0.494380] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
402 16:59:06.398474 <6>[ 0.499504] 9p: Installing v9fs 9p2000 file system support
403 16:59:06.464497 <5>[ 0.565422] Key type asymmetric registered
404 16:59:06.465085 <5>[ 0.565642] Asymmetric key parser 'x509' registered
405 16:59:06.465257 <6>[ 0.566127] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
406 16:59:06.465419 <6>[ 0.566428] io scheduler mq-deadline registered
407 16:59:06.465573 <6>[ 0.566657] io scheduler kyber registered
408 16:59:06.539200 <6>[ 0.639761] pl061_gpio 9030000.pl061: PL061 GPIO chip registered
409 16:59:06.554840 <6>[ 0.655497] pci-host-generic 4010000000.pcie: host bridge /pcie@10000000 ranges:
410 16:59:06.555729 <6>[ 0.656450] pci-host-generic 4010000000.pcie: IO 0x003eff0000..0x003effffff -> 0x0000000000
411 16:59:06.556197 <6>[ 0.657157] pci-host-generic 4010000000.pcie: MEM 0x0010000000..0x003efeffff -> 0x0010000000
412 16:59:06.556719 <6>[ 0.657470] pci-host-generic 4010000000.pcie: MEM 0x8000000000..0xffffffffff -> 0x8000000000
413 16:59:06.557184 <4>[ 0.658137] pci-host-generic 4010000000.pcie: Memory resource size exceeds max for 32 bits
414 16:59:06.558337 <6>[ 0.658863] pci-host-generic 4010000000.pcie: ECAM at [mem 0x4010000000-0x401fffffff] for [bus 00-ff]
415 16:59:06.563617 <6>[ 0.664403] pci-host-generic 4010000000.pcie: PCI host bridge to bus 0000:00
416 16:59:06.563836 <6>[ 0.664863] pci_bus 0000:00: root bus resource [bus 00-ff]
417 16:59:06.564339 <6>[ 0.665093] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]
418 16:59:06.564554 <6>[ 0.665333] pci_bus 0000:00: root bus resource [mem 0x10000000-0x3efeffff]
419 16:59:06.564690 <6>[ 0.665565] pci_bus 0000:00: root bus resource [mem 0x8000000000-0xffffffffff]
420 16:59:06.566344 <6>[ 0.667138] pci 0000:00:00.0: [1b36:0008] type 00 class 0x060000
421 16:59:06.577725 <6>[ 0.678735] pci 0000:00:01.0: [1af4:1000] type 00 class 0x020000
422 16:59:06.582551 <6>[ 0.683334] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x001f]
423 16:59:06.582730 <6>[ 0.683567] pci 0000:00:01.0: reg 0x14: [mem 0x00000000-0x00000fff]
424 16:59:06.582930 <6>[ 0.683843] pci 0000:00:01.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
425 16:59:06.583134 <6>[ 0.684188] pci 0000:00:01.0: reg 0x30: [mem 0x00000000-0x0003ffff pref]
426 16:59:06.584092 <6>[ 0.684890] pci 0000:00:02.0: [1af4:1001] type 00 class 0x010000
427 16:59:06.584281 <6>[ 0.685097] pci 0000:00:02.0: reg 0x10: [io 0x0000-0x007f]
428 16:59:06.584450 <6>[ 0.685291] pci 0000:00:02.0: reg 0x14: [mem 0x00000000-0x00000fff]
429 16:59:06.584616 <6>[ 0.685515] pci 0000:00:02.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref]
430 16:59:06.591651 <6>[ 0.692430] pci 0000:00:01.0: BAR 6: assigned [mem 0x10000000-0x1003ffff pref]
431 16:59:06.591904 <6>[ 0.692934] pci 0000:00:01.0: BAR 4: assigned [mem 0x8000000000-0x8000003fff 64bit pref]
432 16:59:06.592327 <6>[ 0.693275] pci 0000:00:02.0: BAR 4: assigned [mem 0x8000004000-0x8000007fff 64bit pref]
433 16:59:06.592539 <6>[ 0.693548] pci 0000:00:01.0: BAR 1: assigned [mem 0x10040000-0x10040fff]
434 16:59:06.593008 <6>[ 0.693854] pci 0000:00:02.0: BAR 1: assigned [mem 0x10041000-0x10041fff]
435 16:59:06.593224 <6>[ 0.694093] pci 0000:00:02.0: BAR 0: assigned [io 0x1000-0x107f]
436 16:59:06.593417 <6>[ 0.694342] pci 0000:00:01.0: BAR 0: assigned [io 0x1080-0x109f]
437 16:59:06.608430 <6>[ 0.709459] EINJ: ACPI disabled.
438 16:59:06.704112 <6>[ 0.805064] virtio-pci 0000:00:01.0: enabling device (0000 -> 0003)
439 16:59:06.711302 <6>[ 0.812259] virtio-pci 0000:00:02.0: enabling device (0000 -> 0003)
440 16:59:06.743724 <6>[ 0.844671] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
441 16:59:06.755615 <6>[ 0.856617] SuperH (H)SCI(F) driver initialized
442 16:59:06.757260 <6>[ 0.858163] msm_serial: driver initialized
443 16:59:06.799818 <4>[ 0.900796] cacheinfo: Unable to detect cache hierarchy for CPU 0
444 16:59:06.830738 <6>[ 0.931717] loop: module loaded
445 16:59:06.831576 <6>[ 0.932639] virtio_blk virtio1: 1/0/0 default/read/poll queues
446 16:59:06.848782 <5>[ 0.949767] virtio_blk virtio1: [vda] 1048576 512-byte logical blocks (537 MB/512 MiB)
447 16:59:06.887749 <6>[ 0.988705] megasas: 07.719.03.00-rc1
448 16:59:06.903792 <5>[ 1.004490] physmap-flash 0.flash: physmap platform flash device: [mem 0x00000000-0x03ffffff]
449 16:59:06.905360 <6>[ 1.006115] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
450 16:59:06.905821 <6>[ 1.006739] Intel/Sharp Extended Query Table at 0x0031
451 16:59:06.910935 <6>[ 1.011696] Using buffer write method
452 16:59:06.911213 <7>[ 1.012152] erase region 0: offset=0x0,size=0x40000,blocks=256
453 16:59:06.911663 <5>[ 1.012514] physmap-flash 0.flash: physmap platform flash device: [mem 0x04000000-0x07ffffff]
454 16:59:06.912427 <6>[ 1.013192] 0.flash: Found 2 x16 devices at 0x0 in 32-bit bank. Manufacturer ID 0x000000 Chip ID 0x000000
455 16:59:06.912578 <6>[ 1.013459] Intel/Sharp Extended Query Table at 0x0031
456 16:59:06.913002 <6>[ 1.014037] Using buffer write method
457 16:59:06.913173 <7>[ 1.014158] erase region 0: offset=0x0,size=0x40000,blocks=256
458 16:59:06.913344 <5>[ 1.014358] Concatenating MTD devices:
459 16:59:06.913487 <5>[ 1.014466] (0): \"0.flash\"
460 16:59:06.913674 <5>[ 1.014544] (1): \"0.flash\"
461 16:59:06.913822 <5>[ 1.014616] into device \"0.flash\"
462 16:59:11.651099 <6>[ 5.752009] Freeing initrd memory: 86888K
463 16:59:11.768892 <6>[ 5.869880] tun: Universal TUN/TAP device driver, 1.6
464 16:59:11.779196 <6>[ 5.880221] thunder_xcv, ver 1.0
465 16:59:11.779715 <6>[ 5.880484] thunder_bgx, ver 1.0
466 16:59:11.779876 <6>[ 5.880701] nicpf, ver 1.0
467 16:59:11.783187 <6>[ 5.883984] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
468 16:59:11.783361 <6>[ 5.884199] hns3: Copyright (c) 2017 Huawei Corporation.
469 16:59:11.783602 <6>[ 5.884624] hclge is initializing
470 16:59:11.783838 <6>[ 5.884876] e1000: Intel(R) PRO/1000 Network Driver
471 16:59:11.784108 <6>[ 5.885027] e1000: Copyright (c) 1999-2006 Intel Corporation.
472 16:59:11.784309 <6>[ 5.885332] e1000e: Intel(R) PRO/1000 Network Driver
473 16:59:11.784495 <6>[ 5.885470] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
474 16:59:11.784724 <6>[ 5.885765] igb: Intel(R) Gigabit Ethernet Network Driver
475 16:59:11.784933 <6>[ 5.885929] igb: Copyright (c) 2007-2014 Intel Corporation.
476 16:59:11.785434 <6>[ 5.886196] igbvf: Intel(R) Gigabit Virtual Function Network Driver
477 16:59:11.785601 <6>[ 5.886402] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
478 16:59:11.786649 <6>[ 5.887499] sky2: driver version 1.30
479 16:59:11.789758 <6>[ 5.890843] VFIO - User Level meta-driver version: 0.3
480 16:59:11.799091 <6>[ 5.899874] usbcore: registered new interface driver usb-storage
481 16:59:11.799792 <6>[ 5.900661] usbcore: registered new device driver onboard-usb-hub
482 16:59:11.808972 <6>[ 5.909757] rtc-pl031 9010000.pl031: registered as rtc0
483 16:59:11.809977 <6>[ 5.910548] rtc-pl031 9010000.pl031: setting system clock to 2023-06-03T16:59:11 UTC (1685811551)
484 16:59:11.812220 <6>[ 5.913051] i2c_dev: i2c /dev entries driver
485 16:59:11.829980 <6>[ 5.930677] sdhci: Secure Digital Host Controller Interface driver
486 16:59:11.830176 <6>[ 5.930912] sdhci: Copyright(c) Pierre Ossman
487 16:59:11.832053 <6>[ 5.932920] Synopsys Designware Multimedia Card Interface Driver
488 16:59:11.834658 <6>[ 5.935493] sdhci-pltfm: SDHCI platform and OF driver helper
489 16:59:11.840130 <6>[ 5.941020] ledtrig-cpu: registered to indicate activity on CPUs
490 16:59:11.846122 <6>[ 5.946883] usbcore: registered new interface driver usbhid
491 16:59:11.846299 <6>[ 5.947095] usbhid: USB HID core driver
492 16:59:11.870425 <6>[ 5.971444] NET: Registered PF_PACKET protocol family
493 16:59:11.871780 <6>[ 5.972605] 9pnet: Installing 9P2000 support
494 16:59:11.872011 <5>[ 5.972972] Key type dns_resolver registered
495 16:59:11.873251 <6>[ 5.974348] registered taskstats version 1
496 16:59:11.873663 <5>[ 5.974711] Loading compiled-in X.509 certificates
497 16:59:11.896041 <6>[ 5.996823] input: gpio-keys as /devices/platform/gpio-keys/input/input0
498 16:59:11.902996 <6>[ 6.004070] ALSA device list:
499 16:59:11.903364 <6>[ 6.004242] No soundcards found.
500 16:59:11.906017 <6>[ 6.006882] uart-pl011 9000000.pl011: no DMA platform data
501 16:59:11.963518 <6>[ 6.064453] Freeing unused kernel memory: 8384K
502 16:59:11.964734 <6>[ 6.065571] Run /init as init process
503 16:59:11.964928 <7>[ 6.065744] with arguments:
504 16:59:11.965127 <7>[ 6.065872] /init
505 16:59:11.965306 <7>[ 6.065956] verbose
506 16:59:11.965440 <7>[ 6.066050] with environment:
507 16:59:11.965562 <7>[ 6.066170] HOME=/
508 16:59:11.965697 <7>[ 6.066277] TERM=linux
509 16:59:12.095896 <30>[ 6.196211] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
510 16:59:12.096723 <31>[ 6.197586] systemd[1]: No virtualization found in DMI
511 16:59:12.097685 <31>[ 6.198563] systemd[1]: UML virtualization not found in /proc/cpuinfo.
512 16:59:12.098161 <31>[ 6.198915] systemd[1]: No virtualization found in CPUID
513 16:59:12.098590 <31>[ 6.199579] systemd[1]: Virtualization XEN not found, /proc/xen does not exist
514 16:59:12.099963 <31>[ 6.200791] systemd[1]: Virtualization QEMU: \"fw-cfg\" present in /proc/device-tree/fw-cfg@9020000
515 16:59:12.100095 <31>[ 6.201137] systemd[1]: Found VM virtualization qemu
516 16:59:12.100438 <30>[ 6.201373] systemd[1]: Detected virtualization qemu.
517 16:59:12.100796 <30>[ 6.201698] systemd[1]: Detected architecture arm64.
518 16:59:12.101149 <31>[ 6.202100] systemd[1]: Detected initialized system, this is not the first boot.
519 16:59:12.105482
520 16:59:12.105857 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
521 16:59:12.106048
522 16:59:12.108321 <30>[ 6.209189] systemd[1]: Set hostname to <debian-bullseye-arm64>.
523 16:59:12.128212 <31>[ 6.228911] systemd[1]: Successfully added address 127.0.0.1 to loopback interface
524 16:59:12.129308 <31>[ 6.230147] systemd[1]: Failed to add address ::1 to loopback interface: Operation not supported
525 16:59:12.129777 <31>[ 6.230659] systemd[1]: Successfully brought loopback interface up
526 16:59:12.134951 <31>[ 6.235748] systemd[1]: Setting 'fs/file-max' to '9223372036854775807'.
527 16:59:12.147358 <31>[ 6.248039] systemd[1]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
528 16:59:12.147539 <31>[ 6.248351] systemd[1]: Unified cgroup hierarchy is located at /sys/fs/cgroup.
529 16:59:12.190792 <31>[ 6.291465] systemd[1]: Got EBADF when using BPF_F_ALLOW_MULTI, which indicates it is supported. Yay!
530 16:59:12.192186 <31>[ 6.292964] systemd[1]: Controller 'cpu' supported: yes
531 16:59:12.192380 <31>[ 6.293174] systemd[1]: Controller 'cpuacct' supported: no
532 16:59:12.192568 <31>[ 6.293356] systemd[1]: Controller 'cpuset' supported: yes
533 16:59:12.192749 <31>[ 6.293528] systemd[1]: Controller 'io' supported: yes
534 16:59:12.192951 <31>[ 6.293719] systemd[1]: Controller 'blkio' supported: no
535 16:59:12.193120 <31>[ 6.293881] systemd[1]: Controller 'memory' supported: yes
536 16:59:12.193301 <31>[ 6.294043] systemd[1]: Controller 'devices' supported: no
537 16:59:12.193457 <31>[ 6.294231] systemd[1]: Controller 'pids' supported: yes
538 16:59:12.193634 <31>[ 6.294443] systemd[1]: Controller 'bpf-firewall' supported: yes
539 16:59:12.193778 <31>[ 6.294652] systemd[1]: Controller 'bpf-devices' supported: yes
540 16:59:12.195103 <31>[ 6.296139] systemd[1]: Set up TFD_TIMER_CANCEL_ON_SET timerfd.
541 16:59:12.195748 <31>[ 6.296567] systemd[1]: Failed to stat /etc/localtime, ignoring: No such file or directory
542 16:59:12.196321 <31>[ 6.297164] systemd[1]: /etc/localtime doesn't exist yet, watching /etc instead.
543 16:59:12.203934 <31>[ 6.304775] systemd[1]: Enabling (yes) showing of status (commandline).
544 16:59:12.212170 <31>[ 6.312915] systemd[1]: Successfully forked off '(sd-executor)' as PID 98.
545 16:59:12.222701 <31>[ 6.323416] systemd[98]: Successfully forked off '(direxec)' as PID 99.
546 16:59:12.224684 <31>[ 6.325526] systemd[98]: Successfully forked off '(direxec)' as PID 100.
547 16:59:12.230977 <31>[ 6.331749] systemd[98]: Successfully forked off '(direxec)' as PID 101.
548 16:59:12.232919 <31>[ 6.333732] systemd[98]: Successfully forked off '(direxec)' as PID 102.
549 16:59:12.251318 <31>[ 6.352232] systemd[98]: Successfully forked off '(direxec)' as PID 103.
550 16:59:12.436740 <31>[ 6.537606] systemd-fstab-generator[100]: Parsing /etc/fstab...
551 16:59:12.447333 <31>[ 6.548075] systemd-bless-boot-generator[99]: Skipping generator, not an EFI boot.
552 16:59:12.453573 <31>[ 6.554370] systemd-getty-generator[101]: Automatically adding serial getty for /dev/ttyAMA0.
553 16:59:12.455669 <31>[ 6.556278] systemd-fstab-generator[100]: Found entry what=/dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76 where=/ type=ext4 makefs=no growfs=no noauto=no nofail=no
554 16:59:12.458443 <31>[ 6.559007] systemd-fstab-generator[100]: Checking was requested for /dev/disk/by-uuid/ffe0be16-960b-4f4f-abe2-c028c6995c76, but fsck.ext4 does not exist.
555 16:59:12.459476 <31>[ 6.560362] systemd-getty-generator[101]: SELinux enabled state cached to: disabled
556 16:59:12.471524 <31>[ 6.572406] systemd[98]: /usr/lib/systemd/system-generators/systemd-run-generator succeeded.
557 16:59:12.475615 <31>[ 6.576429] systemd-fstab-generator[100]: SELinux enabled state cached to: disabled
558 16:59:12.479254 <31>[ 6.580001] systemd[98]: /usr/lib/systemd/system-generators/systemd-veritysetup-generator succeeded.
559 16:59:12.479444 <31>[ 6.580409] systemd[98]: /usr/lib/systemd/system-generators/systemd-getty-generator succeeded.
560 16:59:12.480008 <31>[ 6.580830] systemd[98]: /usr/lib/systemd/system-generators/systemd-bless-boot-generator succeeded.
561 16:59:12.483598 <31>[ 6.584361] systemd[98]: /usr/lib/systemd/system-generators/systemd-fstab-generator succeeded.
562 16:59:12.485986 <31>[ 6.587007] systemd[1]: (sd-executor) succeeded.
563 16:59:12.488411 <31>[ 6.589093] systemd[1]: Looking for unit files in (higher priority first):
564 16:59:12.488591 <31>[ 6.589358] systemd[1]: /etc/systemd/system.control
565 16:59:12.488809 <31>[ 6.589561] systemd[1]: /run/systemd/system.control
566 16:59:12.488977 <31>[ 6.589755] systemd[1]: /run/systemd/transient
567 16:59:12.489167 <31>[ 6.589937] systemd[1]: /run/systemd/generator.early
568 16:59:12.489346 <31>[ 6.590124] systemd[1]: /etc/systemd/system
569 16:59:12.489537 <31>[ 6.590262] systemd[1]: /etc/systemd/system.attached
570 16:59:12.489692 <31>[ 6.590404] systemd[1]: /run/systemd/system
571 16:59:12.489896 <31>[ 6.590531] systemd[1]: /run/systemd/system.attached
572 16:59:12.490084 <31>[ 6.590699] systemd[1]: /run/systemd/generator
573 16:59:12.490215 <31>[ 6.590857] systemd[1]: /usr/local/lib/systemd/system
574 16:59:12.490336 <31>[ 6.591044] systemd[1]: /lib/systemd/system
575 16:59:12.491046 <31>[ 6.591819] systemd[1]: /usr/lib/systemd/system
576 16:59:12.491206 <31>[ 6.592016] systemd[1]: /run/systemd/generator.late
577 16:59:12.527526 <31>[ 6.628211] systemd[1]: Modification times have changed, need to update cache.
578 16:59:12.529027 <31>[ 6.629811] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.network1.service → systemd-networkd.service
579 16:59:12.530054 <31>[ 6.630892] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.timesync1.service → systemd-timesyncd.service
580 16:59:12.531357 <31>[ 6.632121] systemd[1]: unit_file_build_name_map: alias: /etc/systemd/system/dbus-org.freedesktop.resolve1.service → systemd-resolved.service
581 16:59:12.532304 <31>[ 6.633138] systemd[1]: unit_file_build_name_map: normal unit file: /run/systemd/generator/-.mount
582 16:59:12.533175 <31>[ 6.633942] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald@.service
583 16:59:12.533386 <31>[ 6.634199] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/console-getty.service
584 16:59:12.533571 <31>[ 6.634480] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/fstrim.timer
585 16:59:12.534062 <31>[ 6.634763] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-wall.path
586 16:59:12.534199 <31>[ 6.635107] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.service
587 16:59:12.534973 <31>[ 6.635796] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/poweroff.target
588 16:59:12.535341 <31>[ 6.636173] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-pre.target
589 16:59:12.536071 <31>[ 6.636890] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel4.target → multi-user.target
590 16:59:12.536193 <31>[ 6.637169] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend-then-hibernate.target
591 16:59:12.536574 <31>[ 6.637455] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network.target
592 16:59:12.537195 <31>[ 6.638053] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel5.target → graphical.target
593 16:59:12.537566 <31>[ 6.638332] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.service
594 16:59:12.537944 <31>[ 6.638587] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp-runlevel.service
595 16:59:12.538050 <31>[ 6.638870] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-fs.target
596 16:59:12.538158 <31>[ 6.639136] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/slices.target
597 16:59:12.539346 <31>[ 6.640151] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/kmod.service → systemd-modules-load.service
598 16:59:12.539731 <31>[ 6.640474] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-update-utmp.service
599 16:59:12.540346 <31>[ 6.641078] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel1.target → rescue.target
600 16:59:12.540454 <31>[ 6.641349] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup-pre.target
601 16:59:12.540811 <31>[ 6.641594] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-pre.target
602 16:59:12.540915 <31>[ 6.641846] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/machine.slice
603 16:59:12.541429 <31>[ 6.642142] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-fs-pre.target
604 16:59:12.541618 <31>[ 6.642452] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.service
605 16:59:12.542290 <31>[ 6.643034] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel3.target → multi-user.target
606 16:59:12.543358 <31>[ 6.644193] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.timedate1.service → systemd-timedated.service
607 16:59:12.543736 <31>[ 6.644563] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.service
608 16:59:12.544136 <31>[ 6.644894] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/reboot.target
609 16:59:12.544808 <31>[ 6.645497] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-audit.socket
610 16:59:12.544934 <31>[ 6.645859] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty@.service
611 16:59:12.545336 <31>[ 6.646201] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kexec.target
612 16:59:12.545728 <31>[ 6.646582] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-systemd\x2dcryptsetup.slice
613 16:59:12.546102 <31>[ 6.646907] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timedated.service
614 16:59:12.546741 <31>[ 6.647613] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-root-device.target
615 16:59:12.547131 <31>[ 6.648014] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-parse-etc.service
616 16:59:12.547501 <31>[ 6.648327] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd.target
617 16:59:12.547864 <31>[ 6.648625] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.timer
618 16:59:12.548240 <31>[ 6.648911] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-binfmt.service
619 16:59:12.548361 <31>[ 6.649218] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/local-fs-pre.target
620 16:59:12.548712 <31>[ 6.649543] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_all.service
621 16:59:12.549078 <31>[ 6.649860] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/paths.target
622 16:59:12.549203 <31>[ 6.650186] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/modprobe@.service
623 16:59:12.550033 <31>[ 6.650892] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rc.service → /dev/null
624 16:59:12.550749 <31>[ 6.651598] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-static.service
625 16:59:12.551491 <31>[ 6.652327] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/runlevel2.target → multi-user.target
626 16:59:12.551867 <31>[ 6.652600] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-modules-load.service
627 16:59:12.552065 <31>[ 6.653007] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/suspend.target
628 16:59:12.552480 <31>[ 6.653301] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-debug.mount
629 16:59:12.552711 <31>[ 6.653615] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysusers.service
630 16:59:12.553490 <31>[ 6.654262] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/default.target → graphical.target
631 16:59:12.553936 <31>[ 6.654555] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-poweroff.service
632 16:59:12.554047 <31>[ 6.654830] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.target
633 16:59:12.554404 <31>[ 6.655146] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-sysctl.service
634 16:59:12.555443 <31>[ 6.656318] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/procps.service → systemd-sysctl.service
635 16:59:12.555836 <31>[ 6.656665] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-time-wait-sync.service
636 16:59:12.556224 <31>[ 6.657063] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user@.service
637 16:59:12.556915 <31>[ 6.657785] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/udev.service → systemd-udevd.service
638 16:59:12.557297 <31>[ 6.658151] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update-cleanup.service
639 16:59:12.557735 <31>[ 6.658511] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/nss-lookup.target
640 16:59:12.558106 <31>[ 6.658878] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/umount.target
641 16:59:12.558771 <31>[ 6.659646] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-udevadm-cleanup-db.service
642 16:59:12.559145 <31>[ 6.660054] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sys-kernel-tracing.mount
643 16:59:12.559536 <31>[ 6.660411] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.socket
644 16:59:12.559930 <31>[ 6.660728] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-timesyncd.service
645 16:59:12.560069 <31>[ 6.661031] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald.socket
646 16:59:12.560482 <31>[ 6.661374] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/printer.target
647 16:59:12.560700 <31>[ 6.661667] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/network-online.target
648 16:59:12.561230 <31>[ 6.661946] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/usb-gadget.target
649 16:59:12.561496 <31>[ 6.662241] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hybrid-sleep.service
650 16:59:12.561733 <31>[ 6.662581] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-reboot.service
651 16:59:12.561973 <31>[ 6.662906] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/quotaon.service
652 16:59:12.562987 <31>[ 6.663784] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/bluetooth.target
653 16:59:12.563215 <31>[ 6.664124] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rescue.service
654 16:59:12.563410 <31>[ 6.664429] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-backlight@.service
655 16:59:12.564209 <31>[ 6.664979] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks-early.service → /dev/null
656 16:59:12.564337 <31>[ 6.665284] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dev-hugepages.mount
657 16:59:12.564692 <31>[ 6.665574] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/remote-cryptsetup.target
658 16:59:12.565053 <31>[ 6.665890] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-pstore.service
659 16:59:12.565660 <31>[ 6.666412] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/x11-common.service → /dev/null
660 16:59:12.566259 <31>[ 6.667118] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.locale1.service → systemd-localed.service
661 16:59:12.566957 <31>[ 6.667831] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/timers.target
662 16:59:12.567333 <31>[ 6.668156] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/proc-sys-fs-binfmt_misc.automount
663 16:59:12.567790 <31>[ 6.668546] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-ask-password-console.service
664 16:59:12.568161 <31>[ 6.668951] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-rfkill.socket
665 16:59:12.568559 <31>[ 6.669304] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user.slice
666 16:59:12.568675 <31>[ 6.669634] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup.service
667 16:59:12.569275 <31>[ 6.669975] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-fsck-root.service
668 16:59:12.569738 <31>[ 6.670358] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-quotacheck.service
669 16:59:12.569943 <31>[ 6.670722] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-kexec.service
670 16:59:12.570156 <31>[ 6.671050] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/graphical.target
671 16:59:12.571005 <31>[ 6.671704] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-clean.timer
672 16:59:12.571230 <31>[ 6.672039] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/exit.target
673 16:59:12.571442 <31>[ 6.672330] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-fs.target
674 16:59:12.571970 <31>[ 6.672698] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-boot-system-token.service
675 16:59:12.572482 <31>[ 6.673301] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-varlink@.socket
676 16:59:12.572701 <31>[ 6.673650] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd.service
677 16:59:12.573243 <31>[ 6.673984] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/rpcbind.target
678 16:59:12.574091 <31>[ 6.674859] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.hostname1.service → systemd-hostnamed.service
679 16:59:12.574957 <31>[ 6.675691] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/syslog.socket
680 16:59:12.575193 <31>[ 6.676005] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-user-sessions.service
681 16:59:12.575447 <31>[ 6.676286] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-volatile-root.service
682 16:59:12.575705 <31>[ 6.676549] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/user-runtime-dir@.service
683 16:59:12.576311 <31>[ 6.676801] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/kmod-static-nodes.service
684 16:59:12.576502 <31>[ 6.677042] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-logind.service
685 16:59:12.576696 <31>[ 6.677287] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-control.socket
686 16:59:12.576869 <31>[ 6.677593] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-bless-boot.service
687 16:59:12.577069 <31>[ 6.677893] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd.service
688 16:59:12.577275 <31>[ 6.678169] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journal-flush.service
689 16:59:12.577844 <31>[ 6.678465] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty-pre.target
690 16:59:12.578053 <31>[ 6.678756] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/getty.target
691 16:59:12.578228 <31>[ 6.679001] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-network-generator.service
692 16:59:12.578783 <31>[ 6.679486] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/system-update.target
693 16:59:12.579039 <31>[ 6.679832] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/multi-user.target
694 16:59:12.579258 <31>[ 6.680160] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend.service
695 16:59:12.579468 <31>[ 6.680420] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-initctl.service
696 16:59:12.579679 <31>[ 6.680666] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-cleanup.service
697 16:59:12.579883 <31>[ 6.680886] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/basic.target
698 16:59:12.580337 <31>[ 6.681104] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/emergency.target
699 16:59:12.580718 <31>[ 6.681399] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-suspend-then-hibernate.service
700 16:59:12.580836 <31>[ 6.681784] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate-resume@.service
701 16:59:12.581195 <31>[ 6.682089] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udevd-kernel.socket
702 16:59:12.581570 <31>[ 6.682434] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-journald-dev-log.socket
703 16:59:12.581699 <31>[ 6.682727] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-machine-id-commit.service
704 16:59:12.582056 <31>[ 6.683004] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/serial-getty@.service
705 16:59:12.582413 <31>[ 6.683362] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/initrd-switch-root.service
706 16:59:12.582822 <31>[ 6.683630] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/e2scrub_reap.service
707 16:59:12.582943 <31>[ 6.683903] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sockets.target
708 16:59:12.583589 <31>[ 6.684460] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/cryptdisks.service → /dev/null
709 16:59:12.584051 <31>[ 6.684846] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hybrid-sleep.target
710 16:59:12.584673 <31>[ 6.685573] systemd[1]: unit_file_build_name_map: alias: /lib/systemd/system/dbus-org.freedesktop.login1.service → systemd-logind.service
711 16:59:12.585138 <31>[ 6.685953] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sleep.target
712 16:59:12.585262 <31>[ 6.686249] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-hibernate.service
713 16:59:12.585695 <31>[ 6.686512] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-halt.service
714 16:59:12.585914 <31>[ 6.686892] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/halt.target
715 16:59:12.586806 <31>[ 6.687195] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sigpwr.target
716 16:59:12.587076 <31>[ 6.687822] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-tmpfiles-setup-dev.service
717 16:59:12.587315 <31>[ 6.688185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/sound.target
718 16:59:12.587550 <31>[ 6.688474] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/time-set.target
719 16:59:12.588136 <31>[ 6.688805] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-udev-settle.service
720 16:59:12.588360 <31>[ 6.689187] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/dbus.socket
721 16:59:12.589158 <31>[ 6.689762] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/hwclock.service → /dev/null
722 16:59:12.589386 <31>[ 6.690273] systemd[1]: unit_file_build_name_map: linked unit file: /lib/systemd/system/rcS.service → /dev/null
723 16:59:12.589590 <31>[ 6.690585] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/hibernate.target
724 16:59:12.590099 <31>[ 6.690860] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-random-seed.service
725 16:59:12.590352 <31>[ 6.691185] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/cryptsetup.target
726 16:59:12.591136 <31>[ 6.691789] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/boot-complete.target
727 16:59:12.591328 <31>[ 6.692085] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/blockdev@.target
728 16:59:12.591527 <31>[ 6.692405] systemd[1]: unit_file_build_name_map: normal unit file: /lib/systemd/system/systemd-networkd-wait-online.service
729 16:59:13.012137 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
730 16:59:13.017187 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
731 16:59:13.021112 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
732 16:59:13.025012 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
733 16:59:13.029039 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
734 16:59:13.030714 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
735 16:59:13.033030 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
736 16:59:13.034011 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
737 16:59:13.035048 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
738 16:59:13.035819 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
739 16:59:13.036609 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
740 16:59:13.040389 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
741 16:59:13.044545 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
742 16:59:13.047817 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
743 16:59:13.050054 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
744 16:59:13.052798 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
745 16:59:13.055961 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
746 16:59:13.058028 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
747 16:59:13.084552 Mounting [0;1;39mHuge Pages File System[0m...
748 16:59:13.119867 Mounting [0;1;39mPOSIX Message Queue File System[0m...
749 16:59:13.161742 Mounting [0;1;39mKernel Debug File System[0m...
750 16:59:13.208660 Starting [0;1;39mLoad Kernel Module configfs[0m...
751 16:59:13.251910 Starting [0;1;39mLoad Kernel Module drm[0m...
752 16:59:13.308087 Starting [0;1;39mJournal Service[0m...
753 16:59:13.340153 Starting [0;1;39mLoad Kernel Modules[0m...
754 16:59:13.380928 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
755 16:59:13.443776 Starting [0;1;39mColdplug All udev Devices[0m...
756 16:59:13.529020 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
757 16:59:13.549094 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
758 16:59:13.561399 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
759 16:59:13.613999 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
760 16:59:13.672040 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
761 16:59:13.700384 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
762 16:59:13.775395 Mounting [0;1;39mKernel Configuration File System[0m...
763 16:59:13.891819 Starting [0;1;39mApply Kernel Variables[0m...
764 16:59:13.969122 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
765 16:59:13.990141 <47>[ 8.091111] systemd-journald[109]: SELinux enabled state cached to: disabled
766 16:59:14.003460 <47>[ 8.104455] systemd-journald[109]: Auditing in kernel turned off.
767 16:59:14.032213 <47>[ 8.132849] systemd-journald[109]: Found cgroup2 on /sys/fs/cgroup/, full unified hierarchy
768 16:59:14.103369 <47>[ 8.203927] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
769 16:59:14.106025 <47>[ 8.206699] systemd-journald[109]: Fixed min_use=3.8M max_use=19.3M max_size=2.4M min_size=512.0K keep_free=9.6M n_max_files=100
770 16:59:14.120895 <47>[ 8.221625] systemd-journald[109]: Reserving 333 entries in field hash table.
771 16:59:14.124058 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
772 16:59:14.152637 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
773 16:59:14.153588 See 'systemctl status systemd-remount-fs.service' for details.
774 16:59:14.157814 <47>[ 8.258612] systemd-journald[109]: Reserving 4408 entries in data hash table.
775 16:59:14.164792 <47>[ 8.265600] systemd-journald[109]: Vacuuming...
776 16:59:14.165817 <47>[ 8.266446] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
777 16:59:14.166197 <47>[ 8.267156] systemd-journald[109]: Flushing /dev/kmsg...
778 16:59:14.203813 Starting [0;1;39mLoad/Save Random Seed[0m...
779 16:59:14.259970 Starting [0;1;39mCreate System Users[0m...
780 16:59:14.404028 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
781 16:59:14.604568 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
782 16:59:14.648162 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
783 16:59:14.737224 <47>[ 8.837857] systemd-journald[109]: systemd-journald running as PID 109 for the system.
784 16:59:14.755609 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
785 16:59:14.758732 <47>[ 8.859481] systemd-journald[109]: Sent READY=1 notification.
786 16:59:14.758954 <47>[ 8.859919] systemd-journald[109]: Sent WATCHDOG=1 notification.
787 16:59:14.797632 <47>[ 8.898257] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
788 16:59:14.813850 <47>[ 8.914556] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
789 16:59:14.816550 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
790 16:59:14.837812 <47>[ 8.938587] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
791 16:59:14.866913 <47>[ 8.967551] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
792 16:59:14.883202 <47>[ 8.983894] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
793 16:59:14.901248 <47>[ 9.001924] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
794 16:59:14.918747 <47>[ 9.019648] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
795 16:59:14.947658 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
796 16:59:14.950789 <47>[ 9.051585] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
797 16:59:14.953426 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
798 16:59:14.957336 <47>[ 9.058104] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
799 16:59:14.967657 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
800 16:59:14.972955 <47>[ 9.073667] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
801 16:59:14.987952 <47>[ 9.088691] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
802 16:59:14.990214 <47>[ 9.090949] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
803 16:59:15.003175 <47>[ 9.103932] systemd-journald[109]: n/a: New incoming connection.
804 16:59:15.003679 <47>[ 9.104583] systemd-journald[109]: varlink-20: varlink: setting state idle-server
805 16:59:15.020370 <47>[ 9.121095] systemd-journald[109]: varlink-20: New incoming message: {\"method\":\"io.systemd.Journal.FlushToVar\",\"parameters\":{}}
806 16:59:15.022224 <47>[ 9.123137] systemd-journald[109]: varlink-20: varlink: changing state idle-server → processing-method
807 16:59:15.030423 <46>[ 9.131128] systemd-journald[109]: Received client request to flush runtime journal.
808 16:59:15.030935 <47>[ 9.131794] systemd-journald[109]: Journal effective settings seal=yes keyed_hash=no compress=yes compress_threshold_bytes=512B
809 16:59:15.031720 <47>[ 9.132618] systemd-journald[109]: Vacuuming...
810 16:59:15.032335 <47>[ 9.133066] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
811 16:59:15.033477 <47>[ 9.134364] systemd-journald[109]: varlink-20: Sending message: {\"parameters\":{}}
812 16:59:15.033860 <47>[ 9.134619] systemd-journald[109]: varlink-20: varlink: changing state processing-method → processed-method
813 16:59:15.034238 <47>[ 9.135018] systemd-journald[109]: varlink-20: varlink: changing state processed-method → idle-server
814 16:59:15.041109 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
815 16:59:15.055117 <47>[ 9.155716] systemd-journald[109]: varlink-20: varlink: changing state idle-server → pending-disconnect
816 16:59:15.055468 <47>[ 9.156175] systemd-journald[109]: varlink-20: varlink: changing state pending-disconnect → processing-disconnect
817 16:59:15.055659 <47>[ 9.156529] systemd-journald[109]: varlink-20: varlink: changing state processing-disconnect → disconnected
818 16:59:15.057911 <47>[ 9.158710] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
819 16:59:15.077196 <47>[ 9.177895] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
820 16:59:15.092057 <47>[ 9.192775] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
821 16:59:15.103826 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
822 16:59:15.176325 Starting [0;1;39mCreate Volatile Files and Directories[0m...
823 16:59:15.181007 <47>[ 9.281741] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
824 16:59:15.674037 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
825 16:59:15.760401 Starting [0;1;39mNetwork Service[0m...
826 16:59:15.795321 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
827 16:59:15.803992 <47>[ 9.904889] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
828 16:59:15.888520 Starting [0;1;39mNetwork Time Synchronization[0m...
829 16:59:15.933440 <47>[ 10.034077] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
830 16:59:15.956271 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
831 16:59:15.973779 <47>[ 10.074493] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
832 16:59:16.400753 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
833 16:59:17.426366 <47>[ 11.526768] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3308 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
834 16:59:17.443149 <47>[ 11.543788] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
835 16:59:17.443479 <47>[ 11.544250] systemd-journald[109]: Rotating...
836 16:59:17.444594 <47>[ 11.545393] systemd-journald[109]: Journal effective settings seal=no keyed_hash=no compress=yes compress_threshold_bytes=512B
837 16:59:17.463440 <47>[ 11.564054] systemd-journald[109]: Reserving 333 entries in field hash table.
838 16:59:17.481304 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
839 16:59:17.513524 <47>[ 11.614229] systemd-journald[109]: Reserving 4408 entries in data hash table.
840 16:59:17.536897 <47>[ 11.637859] systemd-journald[109]: Vacuuming...
841 16:59:17.567957 <47>[ 11.668539] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
842 16:59:17.601016 Starting [0;1;39mNetwork Name Resolution[0m...
843 16:59:17.613784 <47>[ 11.714494] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
844 16:59:17.950374 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
845 16:59:17.952886 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
846 16:59:17.959604 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
847 16:59:18.482651 <47>[ 12.583520] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
848 16:59:19.672093 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
849 16:59:19.683123 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
850 16:59:19.704556 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
851 16:59:19.721625 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
852 16:59:19.725089 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
853 16:59:19.735568 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
854 16:59:19.767097 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
855 16:59:19.767897 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
856 16:59:19.768314 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
857 16:59:19.823914 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
858 16:59:19.838044 <47>[ 13.938657] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
859 16:59:19.946119 <47>[ 14.046990] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
860 16:59:19.948080 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
861 16:59:20.120392 Starting [0;1;39mUser Login Management[0m...
862 16:59:20.128448 <47>[ 14.229123] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
863 16:59:20.158904 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
864 16:59:20.186550 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
865 16:59:20.191635 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
866 16:59:20.280044 Starting [0;1;39mPermit User Sessions[0m...
867 16:59:20.296084 <47>[ 14.396720] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
868 16:59:20.599446 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
869 16:59:20.673735 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
870 16:59:20.931542 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
871 16:59:21.312413 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
872 16:59:23.428759 [[0m[0;31m* [0m] A start job is running for /dev/ttyAMA0 (10s / 1min 30s)
873 16:59:23.774224 M[K[[0;32m OK [0m] Found device [0;1;39m/dev/ttyAMA0[0m.
874 16:59:23.828798 [K[[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyAMA0[0m.
875 16:59:23.852410 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
876 16:59:23.864533 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
877 16:59:23.878819 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
878 16:59:23.927478 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
879 16:59:23.936309 <47>[ 18.037060] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
880 16:59:24.140971 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
881 16:59:24.200883 <47>[ 18.301518] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
882 16:59:24.210681 <47>[ 18.311498] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
883 16:59:24.271718
884 16:59:24.271933 Debian GNU/Linux 11 debian-bullseye-arm64 ttyAMA0
885 16:59:24.272094
886 16:59:24.272523 debian-bullseye-arm64 login: root (automatic login)
887 16:59:24.272658
888 16:59:24.461773 <6>[ 18.562676] virtio_net virtio0 enp0s1: renamed from eth0
889 16:59:24.491793 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
890 16:59:24.492316
891 16:59:24.492695 The programs included with the Debian GNU/Linux system are free software;
892 16:59:24.492807 the exact distribution terms for each program are described in the
893 16:59:24.492917 individual files in /usr/share/doc/*/copyright.
894 16:59:24.493011
895 16:59:24.493116 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
896 16:59:24.493228 permitted by applicable law.
897 16:59:25.105134 <47>[ 19.205791] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3307 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
898 16:59:25.105699 <47>[ 19.206390] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
899 16:59:25.105791 <47>[ 19.206758] systemd-journald[109]: Rotating...
900 16:59:25.107296 <47>[ 19.208233] systemd-journald[109]: Reserving 333 entries in field hash table.
901 16:59:25.138462 <47>[ 19.231159] systemd-journald[109]: Reserving 4408 entries in data hash table.
902 16:59:25.142259 <47>[ 19.243069] systemd-journald[109]: Vacuuming...
903 16:59:25.146432 <47>[ 19.247056] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
904 16:59:25.210052 <47>[ 19.310768] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
905 16:59:25.544641 <47>[ 19.645521] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
906 16:59:27.301346 <47>[ 21.401969] systemd-journald[109]: Successfully sent stream file descriptor to service manager.
907 16:59:27.587552 Matched prompt #10: / #
909 16:59:27.588138 Setting prompt string to ['/ #']
910 16:59:27.588323 end: 2.2.1 login-action (duration 00:00:22) [common]
912 16:59:27.588737 end: 2.2 auto-login-action (duration 00:00:23) [common]
913 16:59:27.588906 start: 2.3 expect-shell-connection (timeout 00:04:35) [common]
914 16:59:27.589045 Setting prompt string to ['/ #']
915 16:59:27.589166 Forcing a shell prompt, looking for ['/ #']
917 16:59:27.639729 / #
918 16:59:27.640131 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
919 16:59:27.640335 Waiting using forced prompt support (timeout 00:02:30)
920 16:59:27.642161
921 16:59:27.647237 end: 2.3 expect-shell-connection (duration 00:00:00) [common]
922 16:59:27.647481 start: 2.4 export-device-env (timeout 00:04:35) [common]
923 16:59:27.647719 end: 2.4 export-device-env (duration 00:00:00) [common]
924 16:59:27.647941 end: 2 boot-image-retry (duration 00:00:25) [common]
925 16:59:27.648159 start: 3 lava-test-retry (timeout 00:08:44) [common]
926 16:59:27.648377 start: 3.1 lava-test-shell (timeout 00:08:44) [common]
927 16:59:27.648565 Using namespace: common
929 16:59:27.749550 / # #
930 16:59:27.749920 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
931 16:59:27.750514 #
933 16:59:27.859513 / # mkdir /lava-556569
934 16:59:27.860610 mkdir /lava-556569
936 16:59:27.992339 / # mount /dev/disk/by-uuid/5b682d95-87d5-49f7-920c-bfe98cc4e110 -t ext2 /lava-556569
937 16:59:27.993280 mount /dev/disk/by-uuid/5b682d95-87d5-49f7-920c-bfe98cc4e110 -t ext2 /lava-556569
938 16:59:28.016279 <4>[ 22.116926] ext2 filesystem being mounted at /lava-556569 supports timestamps until 2038 (0x7fffffff)
940 16:59:28.149697 / # ls -la /lava-556569/bin/lava-test-runner
941 16:59:28.150573 ls -la /lava-556569/bin/lava-test-runner
942 16:59:28.179533 -rwxr-xr-x 1 root root 1039 Jun 3 16:58 /lava-556569/bin/lava-test-runner
943 16:59:28.190065 Using /lava-556569
945 16:59:28.291082 / # export SHELL=/bin/sh
946 16:59:28.291910 export SHELL=/bin/sh
948 16:59:28.400021 / # . /lava-556569/environment
949 16:59:28.400850 . /lava-556569/environment
951 16:59:28.511690 / # /lava-556569/bin/lava-test-runner /lava-556569/0
952 16:59:28.512024 Test shell timeout: 10s (minimum of the action and connection timeout)
953 16:59:28.513003 /lava-556569/bin/lava-test-runner /lava-556569/0
954 16:59:28.678891 + export TESTRUN_ID=0_timesync-off
955 16:59:28.679164 + cd /lava-556569/0/tests/0_timesync-off
956 16:59:28.681450 + cat uuid
957 16:59:28.691816 + UUID=556569_1.1.3.1
958 16:59:28.691962 + set +x
959 16:59:28.692285 <LAVA_SIGNAL_STARTRUN 0_timesync-off 556569_1.1.3.1>
960 16:59:28.692681 Received signal: <STARTRUN> 0_timesync-off 556569_1.1.3.1
961 16:59:28.692833 Starting test lava.0_timesync-off (556569_1.1.3.1)
962 16:59:28.692999 Skipping test definition patterns.
963 16:59:28.693197 + systemctl stop systemd-timesyncd
964 16:59:28.964867 + set +x
965 16:59:28.965397 <LAVA_SIGNAL_ENDRUN 0_timesync-off 556569_1.1.3.1>
966 16:59:28.965750 Received signal: <ENDRUN> 0_timesync-off 556569_1.1.3.1
967 16:59:28.965921 Ending use of test pattern.
968 16:59:28.966050 Ending test lava.0_timesync-off (556569_1.1.3.1), duration 0.27
970 16:59:29.006901 + export TESTRUN_ID=1_kselftest-arm64_qemu
971 16:59:29.007170 + cd /lava-556569/0/tests/1_kselftest-arm64_qemu
972 16:59:29.009277 + cat uuid
973 16:59:29.016862 + UUID=556569_1.1.3.5
974 16:59:29.017066 + set +x
975 16:59:29.017214 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64_qemu 556569_1.1.3.5>
976 16:59:29.017355 + cd ./automated/linux/kselftest/
977 16:59:29.017700 Received signal: <STARTRUN> 1_kselftest-arm64_qemu 556569_1.1.3.5
978 16:59:29.017866 Starting test lava.1_kselftest-arm64_qemu (556569_1.1.3.5)
979 16:59:29.018026 Skipping test definition patterns.
980 16:59:29.021542 + ./kselftest.sh -c arm64 -T -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L -S /dev/null -b qemu_arm64-virt-gicv3 -g cip-gitlab -e -p /opt/kselftests/mainline/ -n 1 -i 1
981 16:59:29.136438 INFO: install_deps skipped
982 16:59:29.169322 --2023-06-03 16:59:28-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
983 16:59:29.264756 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
984 16:59:29.473381 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
985 16:59:29.664960 HTTP request sent, awaiting response... 200 OK
986 16:59:29.666713 Length: 2713064 (2.6M) [application/octet-stream]
987 16:59:29.667787 Saving to: 'kselftest.tar.xz'
988 16:59:29.668703
989 16:59:30.953268 kselftest.tar.xz 0%[ ] 0 --.-KB/s kselftest.tar.xz 1%[ ] 50.15K 141KB/s kselftest.tar.xz 8%[> ] 219.84K 303KB/s kselftest.tar.xz 28%[====> ] 752.92K 814KB/s kselftest.tar.xz 50%[=========> ] 1.31M 1.16MB/s kselftest.tar.xz 100%[===================>] 2.59M 1.96MB/s in 1.3s
990 16:59:30.953562
991 16:59:30.958406 2023-06-03 16:59:30 (1.96 MB/s) - 'kselftest.tar.xz' saved [2713064/2713064]
992 16:59:30.958593
993 16:59:34.068812 skiplist:
994 16:59:34.069086 ========================================
995 16:59:34.069630 ========================================
996 16:59:34.143054 arm64:tags_test
997 16:59:34.143606 arm64:run_tags_test.sh
998 16:59:34.143777 arm64:fake_sigreturn_bad_magic
999 16:59:34.143914 arm64:fake_sigreturn_bad_size
1000 16:59:34.144123 arm64:fake_sigreturn_bad_size_for_magic0
1001 16:59:34.144308 arm64:fake_sigreturn_duplicated_fpsimd
1002 16:59:34.144527 arm64:fake_sigreturn_misaligned_sp
1003 16:59:34.144724 arm64:fake_sigreturn_missing_fpsimd
1004 16:59:34.144866 arm64:fake_sigreturn_sme_change_vl
1005 16:59:34.145038 arm64:fake_sigreturn_sve_change_vl
1006 16:59:34.145201 arm64:mangle_pstate_invalid_compat_toggle
1007 16:59:34.145366 arm64:mangle_pstate_invalid_daif_bits
1008 16:59:34.145529 arm64:mangle_pstate_invalid_mode_el1h
1009 16:59:34.145903 arm64:mangle_pstate_invalid_mode_el1t
1010 16:59:34.146067 arm64:mangle_pstate_invalid_mode_el2h
1011 16:59:34.146233 arm64:mangle_pstate_invalid_mode_el2t
1012 16:59:34.146398 arm64:mangle_pstate_invalid_mode_el3h
1013 16:59:34.146562 arm64:mangle_pstate_invalid_mode_el3t
1014 16:59:34.146724 arm64:sme_trap_no_sm
1015 16:59:34.147101 arm64:sme_trap_non_streaming
1016 16:59:34.147258 arm64:sme_trap_za
1017 16:59:34.147434 arm64:sme_vl
1018 16:59:34.147574 arm64:ssve_regs
1019 16:59:34.147713 arm64:sve_regs
1020 16:59:34.147886 arm64:sve_vl
1021 16:59:34.148026 arm64:za_no_regs
1022 16:59:34.148196 arm64:za_regs
1023 16:59:34.148360 arm64:pac
1024 16:59:34.148541 arm64:fp-stress
1025 16:59:34.148739 arm64:sve-ptrace
1026 16:59:34.148883 arm64:sve-probe-vls
1027 16:59:34.149076 arm64:vec-syscfg
1028 16:59:34.149225 arm64:za-fork
1029 16:59:34.149354 arm64:za-ptrace
1030 16:59:34.149503 arm64:check_buffer_fill
1031 16:59:34.149632 arm64:check_child_memory
1032 16:59:34.149773 arm64:check_gcr_el1_cswitch
1033 16:59:34.149934 arm64:check_ksm_options
1034 16:59:34.150060 arm64:check_mmap_options
1035 16:59:34.150175 arm64:check_prctl
1036 16:59:34.150309 arm64:check_tags_inclusion
1037 16:59:34.150427 arm64:check_user_mem
1038 16:59:34.150562 arm64:btitest
1039 16:59:34.150681 arm64:nobtitest
1040 16:59:34.150816 arm64:hwcap
1041 16:59:34.150937 arm64:ptrace
1042 16:59:34.151071 arm64:syscall-abi
1043 16:59:34.151190 arm64:tpidr2
1044 16:59:34.166050 ============== Tests to run ===============
1045 16:59:34.170430 arm64:tags_test
1046 16:59:34.170746 arm64:run_tags_test.sh
1047 16:59:34.170871 arm64:fake_sigreturn_bad_magic
1048 16:59:34.170986 arm64:fake_sigreturn_bad_size
1049 16:59:34.171119 arm64:fake_sigreturn_bad_size_for_magic0
1050 16:59:34.171236 arm64:fake_sigreturn_duplicated_fpsimd
1051 16:59:34.171349 arm64:fake_sigreturn_misaligned_sp
1052 16:59:34.171686 arm64:fake_sigreturn_missing_fpsimd
1053 16:59:34.172042 arm64:fake_sigreturn_sme_change_vl
1054 16:59:34.172258 arm64:fake_sigreturn_sve_change_vl
1055 16:59:34.172448 arm64:mangle_pstate_invalid_compat_toggle
1056 16:59:34.172677 arm64:mangle_pstate_invalid_daif_bits
1057 16:59:34.172856 arm64:mangle_pstate_invalid_mode_el1h
1058 16:59:34.173019 arm64:mangle_pstate_invalid_mode_el1t
1059 16:59:34.173191 arm64:mangle_pstate_invalid_mode_el2h
1060 16:59:34.173356 arm64:mangle_pstate_invalid_mode_el2t
1061 16:59:34.173510 arm64:mangle_pstate_invalid_mode_el3h
1062 16:59:34.173687 arm64:mangle_pstate_invalid_mode_el3t
1063 16:59:34.173934 arm64:sme_trap_no_sm
1064 16:59:34.174080 arm64:sme_trap_non_streaming
1065 16:59:34.174199 arm64:sme_trap_za
1066 16:59:34.174315 arm64:sme_vl
1067 16:59:34.174429 arm64:ssve_regs
1068 16:59:34.174541 arm64:sve_regs
1069 16:59:34.174656 arm64:sve_vl
1070 16:59:34.174768 arm64:za_no_regs
1071 16:59:34.174882 arm64:za_regs
1072 16:59:34.175000 arm64:pac
1073 16:59:34.175114 arm64:fp-stress
1074 16:59:34.175228 arm64:sve-ptrace
1075 16:59:34.175342 arm64:sve-probe-vls
1076 16:59:34.175456 arm64:vec-syscfg
1077 16:59:34.175626 arm64:za-fork
1078 16:59:34.175759 arm64:za-ptrace
1079 16:59:34.175874 arm64:check_buffer_fill
1080 16:59:34.175986 arm64:check_child_memory
1081 16:59:34.176098 arm64:check_gcr_el1_cswitch
1082 16:59:34.176212 arm64:check_ksm_options
1083 16:59:34.176325 arm64:check_mmap_options
1084 16:59:34.176439 arm64:check_prctl
1085 16:59:34.176551 arm64:check_tags_inclusion
1086 16:59:34.176665 arm64:check_user_mem
1087 16:59:34.176777 arm64:btitest
1088 16:59:34.176891 arm64:nobtitest
1089 16:59:34.177003 arm64:hwcap
1090 16:59:34.177116 arm64:ptrace
1091 16:59:34.177228 arm64:syscall-abi
1092 16:59:34.177340 arm64:tpidr2
1093 16:59:34.177481 ===========End Tests to run ===============
1094 16:59:35.502225 <12>[ 29.603026] kselftest: Running tests in arm64
1095 16:59:35.534789 TAP version 13
1096 16:59:35.565948 1..48
1097 16:59:35.618741 # selftests: arm64: tags_test
1098 16:59:35.670309 ok 1 selftests: arm64: tags_test
1099 16:59:35.715087 # selftests: arm64: run_tags_test.sh
1100 16:59:35.763464 # --------------------
1101 16:59:35.763567 # running tags test
1102 16:59:35.763649 # --------------------
1103 16:59:35.763725 # [PASS]
1104 16:59:35.768853 ok 2 selftests: arm64: run_tags_test.sh
1105 16:59:35.813721 # selftests: arm64: fake_sigreturn_bad_magic
1106 16:59:35.861802 # Registered handlers for all signals.
1107 16:59:35.862027 # Detected MINSTKSIGSZ:10000
1108 16:59:35.862227 # Testcase initialized.
1109 16:59:35.862406 # uc context validated.
1110 16:59:35.862533 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1111 16:59:35.862877 # Handled SIG_COPYCTX
1112 16:59:35.863037 # Available space:3536
1113 16:59:35.863160 # Using badly built context - ERR: BAD MAGIC !
1114 16:59:35.863278 # SIG_OK -- SP:0xFFFFD0610B00 si_addr@:0xffffd0610b00 si_code:2 token@:0xffffd060f8a0 offset:-4704
1115 16:59:35.863399 # ==>> completed. PASS(1)
1116 16:59:35.863519 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
1117 16:59:35.863634 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD060F8A0
1118 16:59:35.869768 ok 3 selftests: arm64: fake_sigreturn_bad_magic
1119 16:59:35.912723 # selftests: arm64: fake_sigreturn_bad_size
1120 16:59:35.959959 # Registered handlers for all signals.
1121 16:59:35.960190 # Detected MINSTKSIGSZ:10000
1122 16:59:35.960407 # Testcase initialized.
1123 16:59:35.960613 # uc context validated.
1124 16:59:35.960780 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1125 16:59:35.961119 # Handled SIG_COPYCTX
1126 16:59:35.961248 # Available space:3536
1127 16:59:35.961363 # uc context validated.
1128 16:59:35.961478 # Using badly built context - ERR: Bad size for esr_context
1129 16:59:35.961592 # SIG_OK -- SP:0xFFFFC83B1D30 si_addr@:0xffffc83b1d30 si_code:2 token@:0xffffc83b0ad0 offset:-4704
1130 16:59:35.961723 # ==>> completed. PASS(1)
1131 16:59:35.961838 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
1132 16:59:35.961954 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC83B0AD0
1133 16:59:35.967839 ok 4 selftests: arm64: fake_sigreturn_bad_size
1134 16:59:36.011079 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
1135 16:59:36.059850 # Registered handlers for all signals.
1136 16:59:36.060081 # Detected MINSTKSIGSZ:10000
1137 16:59:36.060374 # Testcase initialized.
1138 16:59:36.060476 # uc context validated.
1139 16:59:36.060557 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1140 16:59:36.060634 # Handled SIG_COPYCTX
1141 16:59:36.060707 # Available space:3536
1142 16:59:36.062312 # Using badly built context - ERR: Bad size for terminator
1143 16:59:36.062747 # SIG_OK -- SP:0xFFFFE4E1C290 si_addr@:0xffffe4e1c290 si_code:2 token@:0xffffe4e1b030 offset:-4704
1144 16:59:36.062920 # ==>> completed. PASS(1)
1145 16:59:36.063049 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
1146 16:59:36.063193 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE4E1B030
1147 16:59:36.069613 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
1148 16:59:36.114426 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
1149 16:59:36.166223 # Registered handlers for all signals.
1150 16:59:36.166433 # Detected MINSTKSIGSZ:10000
1151 16:59:36.166643 # Testcase initialized.
1152 16:59:36.166847 # uc context validated.
1153 16:59:36.167053 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1154 16:59:36.167191 # Handled SIG_COPYCTX
1155 16:59:36.167309 # Available space:3536
1156 16:59:36.167422 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
1157 16:59:36.167535 # SIG_OK -- SP:0xFFFFDAA568C0 si_addr@:0xffffdaa568c0 si_code:2 token@:0xffffdaa55660 offset:-4704
1158 16:59:36.167650 # ==>> completed. PASS(1)
1159 16:59:36.168652 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
1160 16:59:36.169050 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDAA55660
1161 16:59:36.175606 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
1162 16:59:36.222000 # selftests: arm64: fake_sigreturn_misaligned_sp
1163 16:59:36.282105 # Registered handlers for all signals.
1164 16:59:36.282207 # Detected MINSTKSIGSZ:10000
1165 16:59:36.282291 # Testcase initialized.
1166 16:59:36.282363 # uc context validated.
1167 16:59:36.282450 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1168 16:59:36.282526 # Handled SIG_COPYCTX
1169 16:59:36.282611 # SIG_OK -- SP:0xFFFFE5FA6373 si_addr@:0xffffe5fa6373 si_code:2 token@:0xffffe5fa6373 offset:0
1170 16:59:36.282698 # ==>> completed. PASS(1)
1171 16:59:36.282784 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
1172 16:59:36.282885 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE5FA6373
1173 16:59:36.291947 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
1174 16:59:36.339144 # selftests: arm64: fake_sigreturn_missing_fpsimd
1175 16:59:36.389152 # Registered handlers for all signals.
1176 16:59:36.389259 # Detected MINSTKSIGSZ:10000
1177 16:59:36.389345 # Testcase initialized.
1178 16:59:36.389424 # uc context validated.
1179 16:59:36.389518 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1180 16:59:36.389603 # Handled SIG_COPYCTX
1181 16:59:36.389688 # Mangling template header. Spare space:4096
1182 16:59:36.389765 # Using badly built context - ERR: Missing FPSIMD
1183 16:59:36.389857 # SIG_OK -- SP:0xFFFFDBC35070 si_addr@:0xffffdbc35070 si_code:2 token@:0xffffdbc33e10 offset:-4704
1184 16:59:36.389938 # ==>> completed. PASS(1)
1185 16:59:36.390027 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
1186 16:59:36.390120 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDBC33E10
1187 16:59:36.398364 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
1188 16:59:36.446730 # selftests: arm64: fake_sigreturn_sme_change_vl
1189 16:59:36.499883 # Registered handlers for all signals.
1190 16:59:36.500084 # Detected MINSTKSIGSZ:10000
1191 16:59:36.500498 # Required Features: [ SME ] supported
1192 16:59:36.500694 # Incompatible Features: [] absent
1193 16:59:36.500902 # Testcase initialized.
1194 16:59:36.501101 # uc context validated.
1195 16:59:36.501236 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1196 16:59:36.501357 # Handled SIG_COPYCTX
1197 16:59:36.501501 # Attempting to change VL from 16 to 256
1198 16:59:36.501625 # SIG_OK -- SP:0xFFFFD7BB5A00 si_addr@:0xffffd7bb5a00 si_code:2 token@:0xffffd7bb47a0 offset:-4704
1199 16:59:36.501760 # ==>> completed. PASS(1)
1200 16:59:36.501876 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
1201 16:59:36.501990 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD7BB47A0
1202 16:59:36.509277 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl
1203 16:59:36.556477 # selftests: arm64: fake_sigreturn_sve_change_vl
1204 16:59:36.608651 # Registered handlers for all signals.
1205 16:59:36.609108 # Detected MINSTKSIGSZ:10000
1206 16:59:36.609305 # Required Features: [ SVE ] supported
1207 16:59:36.609485 # Incompatible Features: [] absent
1208 16:59:36.609670 # Testcase initialized.
1209 16:59:36.609834 # uc context validated.
1210 16:59:36.609958 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1211 16:59:36.610099 # Handled SIG_COPYCTX
1212 16:59:36.610219 # Attempting to change VL from 16 to 256
1213 16:59:36.610333 # SIG_OK -- SP:0xFFFFDDB08BC0 si_addr@:0xffffddb08bc0 si_code:2 token@:0xffffddb07960 offset:-4704
1214 16:59:36.610448 # ==>> completed. PASS(1)
1215 16:59:36.610559 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
1216 16:59:36.610670 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFDDB07960
1217 16:59:36.617673 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl
1218 16:59:36.667235 # selftests: arm64: mangle_pstate_invalid_compat_toggle
1219 16:59:36.717256 # Registered handlers for all signals.
1220 16:59:36.717452 # Detected MINSTKSIGSZ:10000
1221 16:59:36.717912 # Testcase initialized.
1222 16:59:36.718075 # uc context validated.
1223 16:59:36.718204 # Handled SIG_TRIG
1224 16:59:36.718324 # SIG_OK -- SP:0xFFFFDCBB2410 si_addr@:0xffffdcbb2410 si_code:2 token@:(nil) offset:-281474384995344
1225 16:59:36.718445 # ==>> completed. PASS(1)
1226 16:59:36.718585 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
1227 16:59:36.725736 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
1228 16:59:36.772598 # selftests: arm64: mangle_pstate_invalid_daif_bits
1229 16:59:36.822196 # Registered handlers for all signals.
1230 16:59:36.822401 # Detected MINSTKSIGSZ:10000
1231 16:59:36.822589 # Testcase initialized.
1232 16:59:36.822721 # uc context validated.
1233 16:59:36.822864 # Handled SIG_TRIG
1234 16:59:36.822987 # SIG_OK -- SP:0xFFFFD4564000 si_addr@:0xffffd4564000 si_code:2 token@:(nil) offset:-281474244165632
1235 16:59:36.823105 # ==>> completed. PASS(1)
1236 16:59:36.823220 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
1237 16:59:36.830463 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
1238 16:59:36.878191 # selftests: arm64: mangle_pstate_invalid_mode_el1h
1239 16:59:36.928283 # Registered handlers for all signals.
1240 16:59:36.928499 # Detected MINSTKSIGSZ:10000
1241 16:59:36.928905 # Testcase initialized.
1242 16:59:36.929064 # uc context validated.
1243 16:59:36.929192 # Handled SIG_TRIG
1244 16:59:36.929308 # SIG_OK -- SP:0xFFFFF39F1730 si_addr@:0xfffff39f1730 si_code:2 token@:(nil) offset:-281474769033008
1245 16:59:36.929423 # ==>> completed. PASS(1)
1246 16:59:36.929537 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
1247 16:59:36.936823 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
1248 16:59:36.984535 # selftests: arm64: mangle_pstate_invalid_mode_el1t
1249 16:59:37.033419 # Registered handlers for all signals.
1250 16:59:37.033644 # Detected MINSTKSIGSZ:10000
1251 16:59:37.033858 # Testcase initialized.
1252 16:59:37.034023 # uc context validated.
1253 16:59:37.034157 # Handled SIG_TRIG
1254 16:59:37.034308 # SIG_OK -- SP:0xFFFFE319EAF0 si_addr@:0xffffe319eaf0 si_code:2 token@:(nil) offset:-281474491869936
1255 16:59:37.034436 # ==>> completed. PASS(1)
1256 16:59:37.034556 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
1257 16:59:37.042948 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
1258 16:59:37.090919 # selftests: arm64: mangle_pstate_invalid_mode_el2h
1259 16:59:37.140420 # Registered handlers for all signals.
1260 16:59:37.140647 # Detected MINSTKSIGSZ:10000
1261 16:59:37.141086 # Testcase initialized.
1262 16:59:37.141258 # uc context validated.
1263 16:59:37.141391 # Handled SIG_TRIG
1264 16:59:37.141510 # SIG_OK -- SP:0xFFFFEEFC82C0 si_addr@:0xffffeefc82c0 si_code:2 token@:(nil) offset:-281474691269312
1265 16:59:37.141628 # ==>> completed. PASS(1)
1266 16:59:37.141759 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
1267 16:59:37.149362 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
1268 16:59:37.195750 # selftests: arm64: mangle_pstate_invalid_mode_el2t
1269 16:59:37.246682 # Registered handlers for all signals.
1270 16:59:37.248781 # Detected MINSTKSIGSZ:10000
1271 16:59:37.248997 # Testcase initialized.
1272 16:59:37.249161 # uc context validated.
1273 16:59:37.249290 # Handled SIG_TRIG
1274 16:59:37.249433 # SIG_OK -- SP:0xFFFFF092AB80 si_addr@:0xfffff092ab80 si_code:2 token@:(nil) offset:-281474717887360
1275 16:59:37.249557 # ==>> completed. PASS(1)
1276 16:59:37.249707 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
1277 16:59:37.255976 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
1278 16:59:37.302432 # selftests: arm64: mangle_pstate_invalid_mode_el3h
1279 16:59:37.353326 # Registered handlers for all signals.
1280 16:59:37.353622 # Detected MINSTKSIGSZ:10000
1281 16:59:37.353777 # Testcase initialized.
1282 16:59:37.353910 # uc context validated.
1283 16:59:37.354036 # Handled SIG_TRIG
1284 16:59:37.355553 # SIG_OK -- SP:0xFFFFC67BDB70 si_addr@:0xffffc67bdb70 si_code:2 token@:(nil) offset:-281474011749232
1285 16:59:37.355971 # ==>> completed. PASS(1)
1286 16:59:37.356128 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
1287 16:59:37.363032 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
1288 16:59:37.409669 # selftests: arm64: mangle_pstate_invalid_mode_el3t
1289 16:59:37.456964 # Registered handlers for all signals.
1290 16:59:37.457171 # Detected MINSTKSIGSZ:10000
1291 16:59:37.457350 # Testcase initialized.
1292 16:59:37.457486 # uc context validated.
1293 16:59:37.457604 # Handled SIG_TRIG
1294 16:59:37.457812 # SIG_OK -- SP:0xFFFFCECCF6F0 si_addr@:0xffffceccf6f0 si_code:2 token@:(nil) offset:-281474151282416
1295 16:59:37.457958 # ==>> completed. PASS(1)
1296 16:59:37.458077 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
1297 16:59:37.465528 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
1298 16:59:37.510099 # selftests: arm64: sme_trap_no_sm
1299 16:59:37.621860 # Registered handlers for all signals.
1300 16:59:37.622074 # Detected MINSTKSIGSZ:10000
1301 16:59:37.622257 # Required Features: [ SME ] supported
1302 16:59:37.622410 # Incompatible Features: [] absent
1303 16:59:37.622556 # Testcase initialized.
1304 16:59:37.622912 # SIG_OK -- SP:0xFFFFE42B6340 si_addr@:0xaaaae2412514 si_code:1 token@:(nil) offset:-187650917082388
1305 16:59:37.623054 # ==>> completed. PASS(1)
1306 16:59:37.623199 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
1307 16:59:37.639253 ok 19 selftests: arm64: sme_trap_no_sm
1308 16:59:37.729808 # selftests: arm64: sme_trap_non_streaming
1309 16:59:37.788653 # Registered handlers for all signals.
1310 16:59:37.788831 # Detected MINSTKSIGSZ:10000
1311 16:59:37.788960 # Required Features: [] NOT supported
1312 16:59:37.789078 # Incompatible Features: [] supported
1313 16:59:37.789191 # ==>> completed. SKIP.
1314 16:59:37.789525 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
1315 16:59:37.797008 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
1316 16:59:37.845310 # selftests: arm64: sme_trap_za
1317 16:59:37.892583 # Registered handlers for all signals.
1318 16:59:37.892774 # Detected MINSTKSIGSZ:10000
1319 16:59:37.892910 # Testcase initialized.
1320 16:59:37.893032 # SIG_OK -- SP:0xFFFFE155F760 si_addr@:0xaaaae69e2510 si_code:1 token@:(nil) offset:-187650990286096
1321 16:59:37.893358 # ==>> completed. PASS(1)
1322 16:59:37.893490 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
1323 16:59:37.901173 ok 21 selftests: arm64: sme_trap_za
1324 16:59:37.947095 # selftests: arm64: sme_vl
1325 16:59:37.995711 # Registered handlers for all signals.
1326 16:59:37.995929 # Detected MINSTKSIGSZ:10000
1327 16:59:37.996093 # Required Features: [ SME ] supported
1328 16:59:37.996222 # Incompatible Features: [] absent
1329 16:59:37.996340 # Testcase initialized.
1330 16:59:37.996455 # uc context validated.
1331 16:59:37.996782 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1332 16:59:37.996914 # Handled SIG_COPYCTX
1333 16:59:37.997034 # got expected VL 32
1334 16:59:37.997153 # ==>> completed. PASS(1)
1335 16:59:37.997271 # # SME VL :: Check that we get the right SME VL reported
1336 16:59:38.005125 ok 22 selftests: arm64: sme_vl
1337 16:59:38.050954 # selftests: arm64: ssve_regs
1338 16:59:38.307847 # Registered handlers for all signals.
1339 16:59:38.308101 # Detected MINSTKSIGSZ:10000
1340 16:59:38.308495 # Required Features: [ SME FA64 ] supported
1341 16:59:38.308650 # Incompatible Features: [] absent
1342 16:59:38.308778 # Testcase initialized.
1343 16:59:38.308895 # Testing VL 256
1344 16:59:38.309012 # Validating EXTRA...
1345 16:59:38.309129 # uc context validated.
1346 16:59:38.310170 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1347 16:59:38.310359 # Handled SIG_COPYCTX
1348 16:59:38.310766 # Got expected size 8752 and VL 256
1349 16:59:38.310950 # Testing VL 128
1350 16:59:38.311104 # Validating EXTRA...
1351 16:59:38.311258 # uc context validated.
1352 16:59:38.311423 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1353 16:59:38.311591 # Handled SIG_COPYCTX
1354 16:59:38.311748 # Got expected size 4384 and VL 128
1355 16:59:38.311929 # Testing VL 64
1356 16:59:38.312073 # uc context validated.
1357 16:59:38.312253 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1358 16:59:38.312386 # Handled SIG_COPYCTX
1359 16:59:38.312500 # Got expected size 2208 and VL 64
1360 16:59:38.312612 # Testing VL 32
1361 16:59:38.312725 # uc context validated.
1362 16:59:38.312836 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1363 16:59:38.312946 # Handled SIG_COPYCTX
1364 16:59:38.313056 # Got expected size 1120 and VL 32
1365 16:59:38.313165 # Testing VL 16
1366 16:59:38.313275 # uc context validated.
1367 16:59:38.313385 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1368 16:59:38.313495 # Handled SIG_COPYCTX
1369 16:59:38.313604 # Got expected size 576 and VL 16
1370 16:59:38.313822 # ==>> completed. PASS(1)
1371 16:59:38.318225 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
1372 16:59:38.318625 ok 23 selftests: arm64: ssve_regs
1373 16:59:38.363874 # selftests: arm64: sve_regs
1374 16:59:38.782322 # Registered handlers for all signals.
1375 16:59:38.782962 # Detected MINSTKSIGSZ:10000
1376 16:59:38.783154 # Required Features: [ SVE ] supported
1377 16:59:38.783340 # Incompatible Features: [] absent
1378 16:59:38.783494 # Testcase initialized.
1379 16:59:38.783684 # Testing VL 256
1380 16:59:38.783886 # Validating EXTRA...
1381 16:59:38.784059 # uc context validated.
1382 16:59:38.784207 # 9360 byte GOOD CONTEXT grabbed from sig_copyctx handler
1383 16:59:38.784349 # Handled SIG_COPYCTX
1384 16:59:38.784489 # Got expected size 8752 and VL 256
1385 16:59:38.784632 # Testing VL 240
1386 16:59:38.784770 # Validating EXTRA...
1387 16:59:38.784950 # uc context validated.
1388 16:59:38.785084 # 8816 byte GOOD CONTEXT grabbed from sig_copyctx handler
1389 16:59:38.785225 # Handled SIG_COPYCTX
1390 16:59:38.785365 # Got expected size 8208 and VL 240
1391 16:59:38.785504 # Testing VL 224
1392 16:59:38.785643 # Validating EXTRA...
1393 16:59:38.785795 # uc context validated.
1394 16:59:38.785935 # 8272 byte GOOD CONTEXT grabbed from sig_copyctx handler
1395 16:59:38.786074 # Handled SIG_COPYCTX
1396 16:59:38.786213 # Got expected size 7664 and VL 224
1397 16:59:38.786351 # Testing VL 208
1398 16:59:38.786487 # Validating EXTRA...
1399 16:59:38.786627 # uc context validated.
1400 16:59:38.791393 # 7728 byte GOOD CONTEXT grabbed from sig_copyctx handler
1401 16:59:38.791836 # Handled SIG_COPYCTX
1402 16:59:38.791998 # Got expected size 7120 and VL 208
1403 16:59:38.792169 # Testing VL 192
1404 16:59:38.792313 # Validating EXTRA...
1405 16:59:38.792453 # uc context validated.
1406 16:59:38.792650 # 7184 byte GOOD CONTEXT grabbed from sig_copyctx handler
1407 16:59:38.792840 # Handled SIG_COPYCTX
1408 16:59:38.793012 # Got expected size 6576 and VL 192
1409 16:59:38.793210 # Testing VL 176
1410 16:59:38.793449 # Validating EXTRA...
1411 16:59:38.793670 # uc context validated.
1412 16:59:38.793871 # 6640 byte GOOD CONTEXT grabbed from sig_copyctx handler
1413 16:59:38.794036 # Handled SIG_COPYCTX
1414 16:59:38.794187 # Got expected size 6032 and VL 176
1415 16:59:38.794318 # Testing VL 160
1416 16:59:38.794479 # Validating EXTRA...
1417 16:59:38.794603 # uc context validated.
1418 16:59:38.794776 # 6096 byte GOOD CONTEXT grabbed from sig_copyctx handler
1419 16:59:38.795039 # Handled SIG_COPYCTX
1420 16:59:38.795210 # Got expected size 5488 and VL 160
1421 16:59:38.795362 # Testing VL 144
1422 16:59:38.795501 # Validating EXTRA...
1423 16:59:38.795649 # uc context validated.
1424 16:59:38.795815 # 5552 byte GOOD CONTEXT grabbed from sig_copyctx handler
1425 16:59:38.795945 # Handled SIG_COPYCTX
1426 16:59:38.796056 # Got expected size 4944 and VL 144
1427 16:59:38.796161 # Testing VL 128
1428 16:59:38.796266 # Validating EXTRA...
1429 16:59:38.796372 # uc context validated.
1430 16:59:38.796476 # 4992 byte GOOD CONTEXT grabbed from sig_copyctx handler
1431 16:59:38.796584 # Handled SIG_COPYCTX
1432 16:59:38.796691 # Got expected size 4384 and VL 128
1433 16:59:38.796798 # Testing VL 112
1434 16:59:38.796902 # Validating EXTRA...
1435 16:59:38.797008 # uc context validated.
1436 16:59:38.797113 # 4448 byte GOOD CONTEXT grabbed from sig_copyctx handler
1437 16:59:38.797219 # Handled SIG_COPYCTX
1438 16:59:38.797326 # Got expected size 3840 and VL 112
1439 16:59:38.797436 # Testing VL 96
1440 16:59:38.797541 # uc context validated.
1441 16:59:38.797719 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1442 16:59:38.797927 # Handled SIG_COPYCTX
1443 16:59:38.798104 # Got expected size 3296 and VL 96
1444 16:59:38.798277 # Testing VL 80
1445 16:59:38.798447 # uc context validated.
1446 16:59:38.798616 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1447 16:59:38.798792 # Handled SIG_COPYCTX
1448 16:59:38.798930 # Got expected size 2752 and VL 80
1449 16:59:38.799067 # Testing VL 64
1450 16:59:38.799203 # uc context validated.
1451 16:59:38.800032 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1452 16:59:38.800227 # Handled SIG_COPYCTX
1453 16:59:38.800739 # Got expected size 2208 and VL 64
1454 16:59:38.800931 # Testing VL 48
1455 16:59:38.801101 # uc context validated.
1456 16:59:38.801264 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1457 16:59:38.801398 # Handled SIG_COPYCTX
1458 16:59:38.801513 # Got expected size 1664 and VL 48
1459 16:59:38.801660 # Testing VL 32
1460 16:59:38.801867 # uc context validated.
1461 16:59:38.802052 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1462 16:59:38.802189 # Handled SIG_COPYCTX
1463 16:59:38.802330 # Got expected size 1120 and VL 32
1464 16:59:38.802469 # Testing VL 16
1465 16:59:38.802608 # uc context validated.
1466 16:59:38.802751 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1467 16:59:38.802890 # Handled SIG_COPYCTX
1468 16:59:38.803029 # Got expected size 576 and VL 16
1469 16:59:38.803168 # ==>> completed. PASS(1)
1470 16:59:38.803307 # # SVE registers :: Check that we get the right SVE registers reported
1471 16:59:38.803448 ok 24 selftests: arm64: sve_regs
1472 16:59:38.843860 # selftests: arm64: sve_vl
1473 16:59:38.894859 # Registered handlers for all signals.
1474 16:59:38.895213 # Detected MINSTKSIGSZ:10000
1475 16:59:38.895645 # Required Features: [ SVE ] supported
1476 16:59:38.895835 # Incompatible Features: [] absent
1477 16:59:38.898846 # Testcase initialized.
1478 16:59:38.905436 # uc context validated.
1479 16:59:38.905908 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1480 16:59:38.906115 # Handled SIG_COPYCTX
1481 16:59:38.906258 # got expected VL 64
1482 16:59:38.906380 # ==>> completed. PASS(1)
1483 16:59:38.906498 # # SVE VL :: Check that we get the right SVE VL reported
1484 16:59:38.906641 ok 25 selftests: arm64: sve_vl
1485 16:59:38.954896 # selftests: arm64: za_no_regs
1486 16:59:39.013855 # Registered handlers for all signals.
1487 16:59:39.014181 # Detected MINSTKSIGSZ:10000
1488 16:59:39.014319 # Required Features: [ SME ] supported
1489 16:59:39.014659 # Incompatible Features: [] absent
1490 16:59:39.014789 # Testcase initialized.
1491 16:59:39.014910 # Testing VL 256
1492 16:59:39.015651 # uc context validated.
1493 16:59:39.016145 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1494 16:59:39.016326 # Handled SIG_COPYCTX
1495 16:59:39.016514 # Got expected size 16 and VL 256
1496 16:59:39.016683 # Testing VL 128
1497 16:59:39.016848 # uc context validated.
1498 16:59:39.017297 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1499 16:59:39.017539 # Handled SIG_COPYCTX
1500 16:59:39.017754 # Got expected size 16 and VL 128
1501 16:59:39.017912 # Testing VL 64
1502 16:59:39.018035 # uc context validated.
1503 16:59:39.018152 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1504 16:59:39.018270 # Handled SIG_COPYCTX
1505 16:59:39.018386 # Got expected size 16 and VL 64
1506 16:59:39.018503 # Testing VL 32
1507 16:59:39.018617 # uc context validated.
1508 16:59:39.018733 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1509 16:59:39.018849 # Handled SIG_COPYCTX
1510 16:59:39.018964 # Got expected size 16 and VL 32
1511 16:59:39.019082 # Testing VL 16
1512 16:59:39.019199 # uc context validated.
1513 16:59:39.019313 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1514 16:59:39.019430 # Handled SIG_COPYCTX
1515 16:59:39.019831 # Got expected size 16 and VL 16
1516 16:59:39.019964 # ==>> completed. PASS(1)
1517 16:59:39.020083 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
1518 16:59:39.024301 ok 26 selftests: arm64: za_no_regs
1519 16:59:39.068092 # selftests: arm64: za_regs
1520 16:59:39.224614 # Registered handlers for all signals.
1521 16:59:39.225984 # Detected MINSTKSIGSZ:10000
1522 16:59:39.226230 # Required Features: [ SME ] supported
1523 16:59:39.226359 # Incompatible Features: [] absent
1524 16:59:39.226476 # Testcase initialized.
1525 16:59:39.226589 # Testing VL 256
1526 16:59:39.226702 # Validating EXTRA...
1527 16:59:39.226815 # uc context validated.
1528 16:59:39.226927 # 66160 byte GOOD CONTEXT grabbed from sig_copyctx handler
1529 16:59:39.227041 # Handled SIG_COPYCTX
1530 16:59:39.227154 # Got expected size 65552 and VL 256
1531 16:59:39.227266 # Testing VL 128
1532 16:59:39.227377 # Validating EXTRA...
1533 16:59:39.227489 # uc context validated.
1534 16:59:39.227601 # 17008 byte GOOD CONTEXT grabbed from sig_copyctx handler
1535 16:59:39.227744 # Handled SIG_COPYCTX
1536 16:59:39.227864 # Got expected size 16400 and VL 128
1537 16:59:39.227977 # Testing VL 64
1538 16:59:39.228089 # Validating EXTRA...
1539 16:59:39.228200 # uc context validated.
1540 16:59:39.228310 # 4720 byte GOOD CONTEXT grabbed from sig_copyctx handler
1541 16:59:39.228422 # Handled SIG_COPYCTX
1542 16:59:39.228533 # Got expected size 4112 and VL 64
1543 16:59:39.228645 # Testing VL 32
1544 16:59:39.228757 # uc context validated.
1545 16:59:39.228867 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1546 16:59:39.228979 # Handled SIG_COPYCTX
1547 16:59:39.229091 # Got expected size 1040 and VL 32
1548 16:59:39.229202 # Testing VL 16
1549 16:59:39.229313 # uc context validated.
1550 16:59:39.229423 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
1551 16:59:39.229535 # Handled SIG_COPYCTX
1552 16:59:39.229682 # Got expected size 272 and VL 16
1553 16:59:39.229800 # ==>> completed. PASS(1)
1554 16:59:39.229912 # # ZA register :: Check that we get the right ZA registers reported
1555 16:59:39.237750 ok 27 selftests: arm64: za_regs
1556 16:59:39.286052 # selftests: arm64: pac
1557 16:59:39.431565 # TAP version 13
1558 16:59:39.431795 # 1..7
1559 16:59:39.432128 # # Starting 7 tests from 1 test cases.
1560 16:59:39.432332 # # RUN global.corrupt_pac ...
1561 16:59:39.432509 # # OK global.corrupt_pac
1562 16:59:39.432678 # ok 1 global.corrupt_pac
1563 16:59:39.432839 # # RUN global.pac_instructions_not_nop ...
1564 16:59:39.433041 # # OK global.pac_instructions_not_nop
1565 16:59:39.433207 # ok 2 global.pac_instructions_not_nop
1566 16:59:39.433369 # # RUN global.pac_instructions_not_nop_generic ...
1567 16:59:39.433529 # # OK global.pac_instructions_not_nop_generic
1568 16:59:39.433704 # ok 3 global.pac_instructions_not_nop_generic
1569 16:59:39.433872 # # RUN global.single_thread_different_keys ...
1570 16:59:39.434032 # # OK global.single_thread_different_keys
1571 16:59:39.434195 # ok 4 global.single_thread_different_keys
1572 16:59:39.434395 # # RUN global.exec_changed_keys ...
1573 16:59:39.434538 # # OK global.exec_changed_keys
1574 16:59:39.434659 # ok 5 global.exec_changed_keys
1575 16:59:39.434777 # # RUN global.context_switch_keep_keys ...
1576 16:59:39.434898 # # OK global.context_switch_keep_keys
1577 16:59:39.435015 # ok 6 global.context_switch_keep_keys
1578 16:59:39.435131 # # RUN global.context_switch_keep_keys_generic ...
1579 16:59:39.435246 # # OK global.context_switch_keep_keys_generic
1580 16:59:39.435365 # ok 7 global.context_switch_keep_keys_generic
1581 16:59:39.435482 # # PASSED: 7 / 7 tests passed.
1582 16:59:39.435623 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
1583 16:59:39.442387 ok 28 selftests: arm64: pac
1584 16:59:39.485948 # selftests: arm64: fp-stress
1585 16:59:55.494060 # TAP version 13
1586 16:59:55.494350 # 1..27
1587 16:59:55.494481 # # 1 CPUs, 16 SVE VLs, 5 SME VLs
1588 16:59:55.494623 # # Will run for 10s
1589 16:59:55.494744 # # Started FPSIMD-0-0
1590 16:59:55.494857 # # Started SVE-VL-256-0
1591 16:59:55.494968 # # Started SVE-VL-240-0
1592 16:59:55.495078 # # Started SVE-VL-224-0
1593 16:59:55.496093 # # Started SVE-VL-208-0
1594 16:59:55.496682 # # Started SVE-VL-192-0
1595 16:59:55.496861 # # Started SVE-VL-176-0
1596 16:59:55.497018 # # Started SVE-VL-160-0
1597 16:59:55.497174 # # Started SVE-VL-144-0
1598 16:59:55.497336 # # Started SVE-VL-128-0
1599 16:59:55.497500 # # Started SVE-VL-112-0
1600 16:59:55.497638 # # Started SVE-VL-96-0
1601 16:59:55.497801 # # Started SVE-VL-80-0
1602 16:59:55.497967 # # Started SVE-VL-64-0
1603 16:59:55.498155 # # Started SVE-VL-48-0
1604 16:59:55.498316 # # Started SVE-VL-32-0
1605 16:59:55.498436 # # Started SVE-VL-16-0
1606 16:59:55.498546 # # Started SSVE-VL-256-0
1607 16:59:55.498657 # # Started ZA-VL-256-0
1608 16:59:55.498767 # # Started SSVE-VL-128-0
1609 16:59:55.498877 # # Started ZA-VL-128-0
1610 16:59:55.499025 # # Started SSVE-VL-64-0
1611 16:59:55.499178 # # Started ZA-VL-64-0
1612 16:59:55.499336 # # Started SSVE-VL-32-0
1613 16:59:55.499497 # # Started ZA-VL-32-0
1614 16:59:55.499646 # # Started SSVE-VL-16-0
1615 16:59:55.499784 # # Started ZA-VL-16-0
1616 16:59:55.499938 # # FPSIMD-0-0: Vector length: 128 bits
1617 16:59:55.500102 # # FPSIMD-0-0: PID: 912
1618 16:59:55.500265 # # SVE-VL-224-0: Vector length: 1792 bits
1619 16:59:55.500427 # # SVE-VL-224-0: PID: 915
1620 16:59:55.500632 # # SVE-VL-240-0: Vector length: 1920 bits
1621 16:59:55.500800 # # SVE-VL-240-0: PID: 914
1622 16:59:55.500963 # # SVE-VL-192-0: Vector length: 1536 bits
1623 16:59:55.501123 # # SVE-VL-192-0: PID: 917
1624 16:59:55.501283 # # SVE-VL-256-0: Vector length: 2048 bits
1625 16:59:55.501439 # # SVE-VL-256-0: PID: 913
1626 16:59:55.501604 # # SVE-VL-208-0: Vector length: 1664 bits
1627 16:59:55.501776 # # SVE-VL-208-0: PID: 916
1628 16:59:55.501916 # # SVE-VL-176-0: Vector length: 1408 bits
1629 16:59:55.502085 # # SVE-VL-176-0: PID: 918
1630 16:59:55.502233 # # SVE-VL-128-0: Vector length: 1024 bits
1631 16:59:55.502350 # # SVE-VL-128-0: PID: 921
1632 16:59:55.502467 # # SVE-VL-80-0: Vector length: 640 bits
1633 16:59:55.502579 # # SVE-VL-80-0: PID: 924
1634 16:59:55.502691 # # SVE-VL-16-0: Vector length: 128 bits
1635 16:59:55.502803 # # SVE-VL-16-0: PID: 928
1636 16:59:55.502914 # # SVE-VL-160-0: Vector length: 1280 bits
1637 16:59:55.503024 # # SVE-VL-160-0: PID: 919
1638 16:59:55.503135 # # SVE-VL-144-0: Vector length: 1152 bits
1639 16:59:55.503246 # # SVE-VL-144-0: PID: 920
1640 16:59:55.503390 # # ZA-VL-64-0: Streaming mode vector length: 512 bits
1641 16:59:55.503511 # # ZA-VL-64-0: PID: 934
1642 16:59:55.503624 # # SSVE-VL-64-0: Streaming mode Vector length: 512 bits
1643 16:59:55.503737 # # SSVE-VL-64-0: PID: 933
1644 16:59:55.503849 # # SSVE-VL-128-0: Streaming mode Vector length: 1024 bits
1645 16:59:55.503959 # # SSVE-VL-128-0: PID: 931
1646 16:59:55.504071 # # SVE-VL-48-0: Vector length: 384 bits
1647 16:59:55.504184 # # SVE-VL-48-0: PID: 926
1648 16:59:55.504294 # # SVE-VL-64-0: Vector length: 512 bits
1649 16:59:55.504407 # # SVE-VL-64-0: PID: 925
1650 16:59:55.504517 # # SSVE-VL-16-0: Streaming mode Vector length: 128 bits
1651 16:59:55.504626 # # SSVE-VL-16-0: PID: 937
1652 16:59:55.504738 # # ZA-VL-256-0: Streaming mode vector length: 2048 bits
1653 16:59:55.505066 # # ZA-VL-256-0: PID: 930
1654 16:59:55.505190 # # ZA-VL-128-0: Streaming mode vector length: 1024 bits
1655 16:59:55.510244 # # ZA-VL-128-0: PID: 932
1656 16:59:55.510439 # # SSVE-VL-256-0: Streaming mode Vector length: 2048 bits
1657 16:59:55.510559 # # SSVE-VL-256-0: PID: 929
1658 16:59:55.510671 # # SVE-VL-96-0: Vector length: 768 bits
1659 16:59:55.527284 # # SVE-VL-96-0: PID: 923
1660 16:59:55.527688 # # SVE-VL-32-0: Vector length: 256 bits
1661 16:59:55.527793 # # SVE-VL-32-0: PID: 927
1662 16:59:55.527872 # # SVE-VL-112-0: Vector length: 896 bits
1663 16:59:55.527947 # # SVE-VL-112-0: PID: 922
1664 16:59:55.528019 # # SSVE-VL-32-0: Streaming mode Vector length: 256 bits
1665 16:59:55.528109 # # SSVE-VL-32-0: PID: 935
1666 16:59:55.528184 # # ZA-VL-32-0: Streaming mode vector length: 256 bits
1667 16:59:55.528256 # # ZA-VL-32-0: PID: 936
1668 16:59:55.528327 # # ZA-VL-16-0: Streaming mode vector length: 128 bits
1669 16:59:55.528399 # # ZA-VL-16-0: PID: 938
1670 16:59:55.528483 # # Finishing up...
1671 16:59:55.528557 # ok 1 FPSIMD-0-0
1672 16:59:55.528628 # ok 2 SVE-VL-256-0
1673 16:59:55.528699 # ok 3 SVE-VL-240-0
1674 16:59:55.528769 # ok 4 SVE-VL-224-0
1675 16:59:55.528839 # ok 5 SVE-VL-208-0
1676 16:59:55.529120 # ok 6 SVE-VL-192-0
1677 16:59:55.529201 # ok 7 SVE-VL-176-0
1678 16:59:55.529293 # ok 8 SVE-VL-160-0
1679 16:59:55.529368 # ok 9 SVE-VL-144-0
1680 16:59:55.529438 # ok 10 SVE-VL-128-0
1681 16:59:55.529507 # ok 11 SVE-VL-112-0
1682 16:59:55.529586 # ok 12 SVE-VL-96-0
1683 16:59:55.529670 # ok 13 SVE-VL-80-0
1684 16:59:55.529747 # ok 14 SVE-VL-64-0
1685 16:59:55.529820 # ok 15 SVE-VL-48-0
1686 16:59:55.529889 # ok 16 SVE-VL-32-0
1687 16:59:55.529959 # ok 17 SVE-VL-16-0
1688 16:59:55.530029 # ok 18 SSVE-VL-256-0
1689 16:59:55.530099 # ok 19 ZA-VL-256-0
1690 16:59:55.530168 # ok 20 SSVE-VL-128-0
1691 16:59:55.530239 # ok 21 ZA-VL-128-0
1692 16:59:55.530308 # ok 22 SSVE-VL-64-0
1693 16:59:55.530377 # ok 23 ZA-VL-64-0
1694 16:59:55.530464 # ok 24 SSVE-VL-32-0
1695 16:59:55.530535 # ok 25 ZA-VL-32-0
1696 16:59:55.530605 # ok 26 SSVE-VL-16-0
1697 16:59:55.530674 # ok 27 ZA-VL-16-0
1698 16:59:55.530744 # # ZA-VL-16-0: Terminated by signal 15, no error, iterations=1820, signals=9
1699 16:59:55.530813 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=3209, signals=9
1700 16:59:55.530884 # # ZA-VL-64-0: Terminated by signal 15, no error, iterations=1539, signals=9
1701 16:59:55.530953 # # ZA-VL-32-0: Terminated by signal 15, no error, iterations=1663, signals=9
1702 16:59:55.568706 # # SVE-VL-32-0: Terminated by signal 15, no error, iterations=8180, signals=9
1703 16:59:55.569153 # # SVE-VL-16-0: Terminated by signal 15, no error, iterations=12144, signals=9
1704 16:59:55.569364 # # ZA-VL-256-0: Terminated by signal 15, no error, iterations=254, signals=9
1705 16:59:55.569536 # # SSVE-VL-256-0: Terminated by signal 15, no error, iterations=2442, signals=9
1706 16:59:55.569706 # # SSVE-VL-16-0: Terminated by signal 15, no error, iterations=12231, signals=9
1707 16:59:55.569831 # # SSVE-VL-64-0: Terminated by signal 15, no error, iterations=6830, signals=9
1708 16:59:55.681119 # # SSVE-VL-32-0: Terminated by signal 15, no error, iterations=8932, signals=9
1709 16:59:55.681436 # # SVE-VL-176-0: Terminated by signal 15, no error, iterations=3298, signals=9
1710 16:59:55.681643 # # SVE-VL-64-0: Terminated by signal 15, no error, iterations=6114, signals=9
1711 16:59:55.681825 # # SVE-VL-96-0: Terminated by signal 15, no error, iterations=4264, signals=9
1712 16:59:55.681987 # # SVE-VL-144-0: Terminated by signal 15, no error, iterations=3651, signals=9
1713 16:59:55.682127 # # SVE-VL-80-0: Terminated by signal 15, no error, iterations=5922, signals=9
1714 16:59:55.682272 # # SVE-VL-160-0: Terminated by signal 15, no error, iterations=3619, signals=9
1715 16:59:55.682391 # # SVE-VL-48-0: Terminated by signal 15, no error, iterations=7103, signals=9
1716 16:59:55.682506 # # SVE-VL-112-0: Terminated by signal 15, no error, iterations=3886, signals=9
1717 16:59:55.686872 # # SVE-VL-128-0: Terminated by signal 15, no error, iterations=4106, signals=9
1718 16:59:55.687069 # # ZA-VL-128-0: Terminated by signal 15, no error, iterations=517, signals=9
1719 16:59:55.687262 # # SVE-VL-224-0: Terminated by signal 15, no error, iterations=2783, signals=9
1720 16:59:55.687479 # # SVE-VL-208-0: Terminated by signal 15, no error, iterations=2928, signals=9
1721 16:59:55.687670 # # SVE-VL-192-0: Terminated by signal 15, no error, iterations=3072, signals=9
1722 16:59:55.687856 # # SSVE-VL-128-0: Terminated by signal 15, no error, iterations=4194, signals=9
1723 16:59:55.688042 # # SVE-VL-240-0: Terminated by signal 15, no error, iterations=2825, signals=9
1724 16:59:55.688199 # # SVE-VL-256-0: Terminated by signal 15, no error, iterations=2589, signals=9
1725 16:59:55.688343 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:0 error:0
1726 16:59:55.688466 ok 29 selftests: arm64: fp-stress
1727 16:59:55.835344 # selftests: arm64: sve-ptrace
1728 16:59:55.975247 # TAP version 13
1729 16:59:55.975451 # 1..4104
1730 16:59:55.975904 # # Parent is 955, child is 956
1731 16:59:55.976113 # ok 1 SVE FPSIMD set via SVE: 0
1732 16:59:55.976346 # ok 2 SVE get_fpsimd() gave same state
1733 16:59:55.976566 # ok 3 SVE SVE_PT_VL_INHERIT set
1734 16:59:55.976780 # ok 4 SVE SVE_PT_VL_INHERIT cleared
1735 16:59:55.976955 # ok 5 Set SVE VL 16
1736 16:59:55.977146 # ok 6 Set and get SVE data for VL 16
1737 16:59:55.977299 # ok 7 Set and get FPSIMD data for SVE VL 16
1738 16:59:55.977470 # ok 8 Set FPSIMD, read via SVE for SVE VL 16
1739 16:59:55.977695 # ok 9 Set SVE VL 32
1740 16:59:55.977904 # ok 10 Set and get SVE data for VL 32
1741 16:59:55.978091 # ok 11 Set and get FPSIMD data for SVE VL 32
1742 16:59:55.978264 # ok 12 Set FPSIMD, read via SVE for SVE VL 32
1743 16:59:55.978408 # ok 13 Set SVE VL 48
1744 16:59:55.978549 # ok 14 Set and get SVE data for VL 48
1745 16:59:55.978688 # ok 15 Set and get FPSIMD data for SVE VL 48
1746 16:59:55.978826 # ok 16 Set FPSIMD, read via SVE for SVE VL 48
1747 16:59:55.978965 # ok 17 Set SVE VL 64
1748 16:59:55.979104 # ok 18 Set and get SVE data for VL 64
1749 16:59:55.979242 # ok 19 Set and get FPSIMD data for SVE VL 64
1750 16:59:55.979380 # ok 20 Set FPSIMD, read via SVE for SVE VL 64
1751 16:59:55.979519 # ok 21 Set SVE VL 80
1752 16:59:55.979657 # ok 22 Set and get SVE data for VL 80
1753 16:59:55.979795 # ok 23 Set and get FPSIMD data for SVE VL 80
1754 16:59:55.979934 # ok 24 Set FPSIMD, read via SVE for SVE VL 80
1755 16:59:55.980072 # ok 25 Set SVE VL 96
1756 16:59:55.980211 # ok 26 Set and get SVE data for VL 96
1757 16:59:55.980350 # ok 27 Set and get FPSIMD data for SVE VL 96
1758 16:59:55.980507 # ok 28 Set FPSIMD, read via SVE for SVE VL 96
1759 16:59:55.980696 # ok 29 Set SVE VL 112
1760 16:59:55.980897 # ok 30 Set and get SVE data for VL 112
1761 16:59:55.981061 # ok 31 Set and get FPSIMD data for SVE VL 112
1762 16:59:55.981218 # ok 32 Set FPSIMD, read via SVE for SVE VL 112
1763 16:59:55.981425 # ok 33 Set SVE VL 128
1764 16:59:55.981629 # ok 34 Set and get SVE data for VL 128
1765 16:59:55.981807 # ok 35 Set and get FPSIMD data for SVE VL 128
1766 16:59:55.982016 # ok 36 Set FPSIMD, read via SVE for SVE VL 128
1767 16:59:55.982158 # ok 37 Set SVE VL 144
1768 16:59:55.982340 # ok 38 Set and get SVE data for VL 144
1769 16:59:55.982469 # ok 39 Set and get FPSIMD data for SVE VL 144
1770 16:59:55.982606 # ok 40 Set FPSIMD, read via SVE for SVE VL 144
1771 16:59:55.982743 # ok 41 Set SVE VL 160
1772 16:59:55.982900 # ok 42 Set and get SVE data for VL 160
1773 16:59:55.983041 # ok 43 Set and get FPSIMD data for SVE VL 160
1774 16:59:55.983162 # ok 44 Set FPSIMD, read via SVE for SVE VL 160
1775 16:59:55.983275 # ok 45 Set SVE VL 176
1776 16:59:55.983388 # ok 46 Set and get SVE data for VL 176
1777 16:59:55.983532 # ok 47 Set and get FPSIMD data for SVE VL 176
1778 16:59:55.983658 # ok 48 Set FPSIMD, read via SVE for SVE VL 176
1779 16:59:55.983778 # ok 49 Set SVE VL 192
1780 16:59:55.984166 # ok 50 Set and get SVE data for VL 192
1781 16:59:55.984339 # ok 51 Set and get FPSIMD data for SVE VL 192
1782 16:59:55.984484 # ok 52 Set FPSIMD, read via SVE for SVE VL 192
1783 16:59:55.984614 # ok 53 Set SVE VL 208
1784 16:59:55.984786 # ok 54 Set and get SVE data for VL 208
1785 16:59:55.984961 # ok 55 Set and get FPSIMD data for SVE VL 208
1786 16:59:55.985162 # ok 56 Set FPSIMD, read via SVE for SVE VL 208
1787 16:59:55.985359 # ok 57 Set SVE VL 224
1788 16:59:55.985545 # ok 58 Set and get SVE data for VL 224
1789 16:59:55.985732 # ok 59 Set and get FPSIMD data for SVE VL 224
1790 16:59:55.985900 # ok 60 Set FPSIMD, read via SVE for SVE VL 224
1791 16:59:55.986044 # ok 61 Set SVE VL 240
1792 16:59:55.986185 # ok 62 Set and get SVE data for VL 240
1793 16:59:55.986328 # ok 63 Set and get FPSIMD data for SVE VL 240
1794 16:59:55.986469 # ok 64 Set FPSIMD, read via SVE for SVE VL 240
1795 16:59:55.986610 # ok 65 Set SVE VL 256
1796 16:59:55.986749 # ok 66 Set and get SVE data for VL 256
1797 16:59:55.986934 # ok 67 Set and get FPSIMD data for SVE VL 256
1798 16:59:55.987068 # ok 68 Set FPSIMD, read via SVE for SVE VL 256
1799 16:59:55.987211 # ok 69 Set SVE VL 272
1800 16:59:55.987352 # ok 70 # SKIP SVE set SVE get SVE for VL 272
1801 16:59:55.987493 # ok 71 # SKIP SVE set SVE get FPSIMD for VL 272
1802 16:59:55.987632 # ok 72 # SKIP SVE set FPSIMD get SVE for VL 272
1803 16:59:55.987771 # ok 73 Set SVE VL 288
1804 16:59:55.987913 # ok 74 # SKIP SVE set SVE get SVE for VL 288
1805 16:59:55.988054 # ok 75 # SKIP SVE set SVE get FPSIMD for VL 288
1806 16:59:55.988195 # ok 76 # SKIP SVE set FPSIMD get SVE for VL 288
1807 16:59:55.988337 # ok 77 Set SVE VL 304
1808 16:59:55.988476 # ok 78 # SKIP SVE set SVE get SVE for VL 304
1809 16:59:55.988615 # ok 79 # SKIP SVE set SVE get FPSIMD for VL 304
1810 16:59:55.988753 # ok 80 # SKIP SVE set FPSIMD get SVE for VL 304
1811 16:59:55.988893 # ok 81 Set SVE VL 320
1812 16:59:55.989031 # ok 82 # SKIP SVE set SVE get SVE for VL 320
1813 16:59:55.992262 # ok 83 # SKIP SVE set SVE get FPSIMD for VL 320
1814 16:59:55.992628 # ok 84 # SKIP SVE set FPSIMD get SVE for VL 320
1815 16:59:55.992804 # ok 85 Set SVE VL 336
1816 16:59:55.993020 # ok 86 # SKIP SVE set SVE get SVE for VL 336
1817 16:59:55.993248 # ok 87 # SKIP SVE set SVE get FPSIMD for VL 336
1818 16:59:55.993509 # ok 88 # SKIP SVE set FPSIMD get SVE for VL 336
1819 16:59:55.993748 # ok 89 Set SVE VL 352
1820 16:59:55.993949 # ok 90 # SKIP SVE set SVE get SVE for VL 352
1821 16:59:55.994092 # ok 91 # SKIP SVE set SVE get FPSIMD for VL 352
1822 16:59:55.994250 # ok 92 # SKIP SVE set FPSIMD get SVE for VL 352
1823 16:59:55.994426 # ok 93 Set SVE VL 368
1824 16:59:55.994555 # ok 94 # SKIP SVE set SVE get SVE for VL 368
1825 16:59:55.994670 # ok 95 # SKIP SVE set SVE get FPSIMD for VL 368
1826 16:59:55.994785 # ok 96 # SKIP SVE set FPSIMD get SVE for VL 368
1827 16:59:55.994925 # ok 97 Set SVE VL 384
1828 16:59:55.995046 # ok 98 # SKIP SVE set SVE get SVE for VL 384
1829 16:59:55.995217 # ok 99 # SKIP SVE set SVE get FPSIMD for VL 384
1830 16:59:55.995413 # ok 100 # SKIP SVE set FPSIMD get SVE for VL 384
1831 16:59:55.995609 # ok 101 Set SVE VL 400
1832 16:59:55.995854 # ok 102 # SKIP SVE set SVE get SVE for VL 400
1833 16:59:55.996064 # ok 103 # SKIP SVE set SVE get FPSIMD for VL 400
1834 16:59:55.996232 # ok 104 # SKIP SVE set FPSIMD get SVE for VL 400
1835 16:59:55.996412 # ok 105 Set SVE VL 416
1836 16:59:55.996598 # ok 106 # SKIP SVE set SVE get SVE for VL 416
1837 16:59:55.996772 # ok 107 # SKIP SVE set SVE get FPSIMD for VL 416
1838 16:59:55.996930 # ok 108 # SKIP SVE set FPSIMD get SVE for VL 416
1839 16:59:55.997144 # ok 109 Set SVE VL 432
1840 16:59:55.997414 # ok 110 # SKIP SVE set SVE get SVE for VL 432
1841 16:59:55.997640 # ok 111 # SKIP SVE set SVE get FPSIMD for VL 432
1842 16:59:55.998264 # ok 112 # SKIP SVE set FPSIMD get SVE for VL 432
1843 16:59:55.998388 # ok 113 Set SVE VL 448
1844 16:59:55.998504 # ok 114 # SKIP SVE set SVE get SVE for VL 448
1845 16:59:55.998621 # ok 115 # SKIP SVE set SVE get FPSIMD for VL 448
1846 16:59:55.998736 # ok 116 # SKIP SVE set FPSIMD get SVE for VL 448
1847 16:59:55.998850 # ok 117 Set SVE VL 464
1848 16:59:55.998963 # ok 118 # SKIP SVE set SVE get SVE for VL 464
1849 16:59:55.999077 # ok 119 # SKIP SVE set SVE get FPSIMD for VL 464
1850 16:59:55.999192 # ok 120 # SKIP SVE set FPSIMD get SVE for VL 464
1851 16:59:55.999307 # ok 121 Set SVE VL 480
1852 16:59:55.999420 # ok 122 # SKIP SVE set SVE get SVE for VL 480
1853 16:59:55.999534 # ok 123 # SKIP SVE set SVE get FPSIMD for VL 480
1854 16:59:55.999676 # ok 124 # SKIP SVE set FPSIMD get SVE for VL 480
1855 16:59:55.999801 # ok 125 Set SVE VL 496
1856 16:59:55.999917 # ok 126 # SKIP SVE set SVE get SVE for VL 496
1857 16:59:56.000035 # ok 127 # SKIP SVE set SVE get FPSIMD for VL 496
1858 16:59:56.000151 # ok 128 # SKIP SVE set FPSIMD get SVE for VL 496
1859 16:59:56.000471 # ok 129 Set SVE VL 512
1860 16:59:56.009247 # ok 130 # SKIP SVE set SVE get SVE for VL 512
1861 16:59:56.009536 # ok 131 # SKIP SVE set SVE get FPSIMD for VL 512
1862 16:59:56.009640 # ok 132 # SKIP SVE set FPSIMD get SVE for VL 512
1863 16:59:56.009729 # ok 133 Set SVE VL 528
1864 16:59:56.009807 # ok 134 # SKIP SVE set SVE get SVE for VL 528
1865 16:59:56.009899 # ok 135 # SKIP SVE set SVE get FPSIMD for VL 528
1866 16:59:56.009980 # ok 136 # SKIP SVE set FPSIMD get SVE for VL 528
1867 16:59:56.010058 # ok 137 Set SVE VL 544
1868 16:59:56.010521 # ok 138 # SKIP SVE set SVE get SVE for VL 544
1869 16:59:56.010625 # ok 139 # SKIP SVE set SVE get FPSIMD for VL 544
1870 16:59:56.010946 # ok 140 # SKIP SVE set FPSIMD get SVE for VL 544
1871 16:59:56.011142 # ok 141 Set SVE VL 560
1872 16:59:56.011332 # ok 142 # SKIP SVE set SVE get SVE for VL 560
1873 16:59:56.011507 # ok 143 # SKIP SVE set SVE get FPSIMD for VL 560
1874 16:59:56.011653 # ok 144 # SKIP SVE set FPSIMD get SVE for VL 560
1875 16:59:56.011837 # ok 145 Set SVE VL 576
1876 16:59:56.012054 # ok 146 # SKIP SVE set SVE get SVE for VL 576
1877 16:59:56.012210 # ok 147 # SKIP SVE set SVE get FPSIMD for VL 576
1878 16:59:56.012363 # ok 148 # SKIP SVE set FPSIMD get SVE for VL 576
1879 16:59:56.012502 # ok 149 Set SVE VL 592
1880 16:59:56.012660 # ok 150 # SKIP SVE set SVE get SVE for VL 592
1881 16:59:56.012815 # ok 151 # SKIP SVE set SVE get FPSIMD for VL 592
1882 16:59:56.012978 # ok 152 # SKIP SVE set FPSIMD get SVE for VL 592
1883 16:59:56.013148 # ok 153 Set SVE VL 608
1884 16:59:56.013335 # ok 154 # SKIP SVE set SVE get SVE for VL 608
1885 16:59:56.013552 # ok 155 # SKIP SVE set SVE get FPSIMD for VL 608
1886 16:59:56.013743 # ok 156 # SKIP SVE set FPSIMD get SVE for VL 608
1887 16:59:56.013893 # ok 157 Set SVE VL 624
1888 16:59:56.014014 # ok 158 # SKIP SVE set SVE get SVE for VL 624
1889 16:59:56.014129 # ok 159 # SKIP SVE set SVE get FPSIMD for VL 624
1890 16:59:56.014243 # ok 160 # SKIP SVE set FPSIMD get SVE for VL 624
1891 16:59:56.014356 # ok 161 Set SVE VL 640
1892 16:59:56.014469 # ok 162 # SKIP SVE set SVE get SVE for VL 640
1893 16:59:56.014583 # ok 163 # SKIP SVE set SVE get FPSIMD for VL 640
1894 16:59:56.014697 # ok 164 # SKIP SVE set FPSIMD get SVE for VL 640
1895 16:59:56.014811 # ok 165 Set SVE VL 656
1896 16:59:56.014924 # ok 166 # SKIP SVE set SVE get SVE for VL 656
1897 16:59:56.015037 # ok 167 # SKIP SVE set SVE get FPSIMD for VL 656
1898 16:59:56.015152 # ok 168 # SKIP SVE set FPSIMD get SVE for VL 656
1899 16:59:56.015265 # ok 169 Set SVE VL 672
1900 16:59:56.015404 # ok 170 # SKIP SVE set SVE get SVE for VL 672
1901 16:59:56.015523 # ok 171 # SKIP SVE set SVE get FPSIMD for VL 672
1902 16:59:56.015637 # ok 172 # SKIP SVE set FPSIMD get SVE for VL 672
1903 16:59:56.021252 # ok 173 Set SVE VL 688
1904 16:59:56.021707 # ok 174 # SKIP SVE set SVE get SVE for VL 688
1905 16:59:56.021868 # ok 175 # SKIP SVE set SVE get FPSIMD for VL 688
1906 16:59:56.022017 # ok 176 # SKIP SVE set FPSIMD get SVE for VL 688
1907 16:59:56.022160 # ok 177 Set SVE VL 704
1908 16:59:56.022383 # ok 178 # SKIP SVE set SVE get SVE for VL 704
1909 16:59:56.022555 # ok 179 # SKIP SVE set SVE get FPSIMD for VL 704
1910 16:59:56.022734 # ok 180 # SKIP SVE set FPSIMD get SVE for VL 704
1911 16:59:56.022989 # ok 181 Set SVE VL 720
1912 16:59:56.023160 # ok 182 # SKIP SVE set SVE get SVE for VL 720
1913 16:59:56.023317 # ok 183 # SKIP SVE set SVE get FPSIMD for VL 720
1914 16:59:56.023472 # ok 184 # SKIP SVE set FPSIMD get SVE for VL 720
1915 16:59:56.023629 # ok 185 Set SVE VL 736
1916 16:59:56.023777 # ok 186 # SKIP SVE set SVE get SVE for VL 736
1917 16:59:56.023914 # ok 187 # SKIP SVE set SVE get FPSIMD for VL 736
1918 16:59:56.024071 # ok 188 # SKIP SVE set FPSIMD get SVE for VL 736
1919 16:59:56.024229 # ok 189 Set SVE VL 752
1920 16:59:56.024423 # ok 190 # SKIP SVE set SVE get SVE for VL 752
1921 16:59:56.024588 # ok 191 # SKIP SVE set SVE get FPSIMD for VL 752
1922 16:59:56.024745 # ok 192 # SKIP SVE set FPSIMD get SVE for VL 752
1923 16:59:56.024901 # ok 193 Set SVE VL 768
1924 16:59:56.025056 # ok 194 # SKIP SVE set SVE get SVE for VL 768
1925 16:59:56.025211 # ok 195 # SKIP SVE set SVE get FPSIMD for VL 768
1926 16:59:56.025366 # ok 196 # SKIP SVE set FPSIMD get SVE for VL 768
1927 16:59:56.025522 # ok 197 Set SVE VL 784
1928 16:59:56.026083 # ok 198 # SKIP SVE set SVE get SVE for VL 784
1929 16:59:56.026255 # ok 199 # SKIP SVE set SVE get FPSIMD for VL 784
1930 16:59:56.026400 # ok 200 # SKIP SVE set FPSIMD get SVE for VL 784
1931 16:59:56.026540 # ok 201 Set SVE VL 800
1932 16:59:56.026678 # ok 202 # SKIP SVE set SVE get SVE for VL 800
1933 16:59:56.026818 # ok 203 # SKIP SVE set SVE get FPSIMD for VL 800
1934 16:59:56.026956 # ok 204 # SKIP SVE set FPSIMD get SVE for VL 800
1935 16:59:56.027096 # ok 205 Set SVE VL 816
1936 16:59:56.027276 # ok 206 # SKIP SVE set SVE get SVE for VL 816
1937 16:59:56.027413 # ok 207 # SKIP SVE set SVE get FPSIMD for VL 816
1938 16:59:56.027556 # ok 208 # SKIP SVE set FPSIMD get SVE for VL 816
1939 16:59:56.027697 # ok 209 Set SVE VL 832
1940 16:59:56.027837 # ok 210 # SKIP SVE set SVE get SVE for VL 832
1941 16:59:56.027976 # ok 211 # SKIP SVE set SVE get FPSIMD for VL 832
1942 16:59:56.028117 # ok 212 # SKIP SVE set FPSIMD get SVE for VL 832
1943 16:59:56.028257 # ok 213 Set SVE VL 848
1944 16:59:56.028399 # ok 214 # SKIP SVE set SVE get SVE for VL 848
1945 16:59:56.028539 # ok 215 # SKIP SVE set SVE get FPSIMD for VL 848
1946 16:59:56.028678 # ok 216 # SKIP SVE set FPSIMD get SVE for VL 848
1947 16:59:56.028818 # ok 217 Set SVE VL 864
1948 16:59:56.028957 # ok 218 # SKIP SVE set SVE get SVE for VL 864
1949 16:59:56.029309 # ok 219 # SKIP SVE set SVE get FPSIMD for VL 864
1950 16:59:56.029447 # ok 220 # SKIP SVE set FPSIMD get SVE for VL 864
1951 16:59:56.029590 # ok 221 Set SVE VL 880
1952 16:59:56.029743 # ok 222 # SKIP SVE set SVE get SVE for VL 880
1953 16:59:56.032191 # ok 223 # SKIP SVE set SVE get FPSIMD for VL 880
1954 16:59:56.032742 # ok 224 # SKIP SVE set FPSIMD get SVE for VL 880
1955 16:59:56.032937 # ok 225 Set SVE VL 896
1956 16:59:56.033113 # ok 226 # SKIP SVE set SVE get SVE for VL 896
1957 16:59:56.033278 # ok 227 # SKIP SVE set SVE get FPSIMD for VL 896
1958 16:59:56.033459 # ok 228 # SKIP SVE set FPSIMD get SVE for VL 896
1959 16:59:56.033668 # ok 229 Set SVE VL 912
1960 16:59:56.033874 # ok 230 # SKIP SVE set SVE get SVE for VL 912
1961 16:59:56.034012 # ok 231 # SKIP SVE set SVE get FPSIMD for VL 912
1962 16:59:56.034140 # ok 232 # SKIP SVE set FPSIMD get SVE for VL 912
1963 16:59:56.034266 # ok 233 Set SVE VL 928
1964 16:59:56.034426 # ok 234 # SKIP SVE set SVE get SVE for VL 928
1965 16:59:56.034616 # ok 235 # SKIP SVE set SVE get FPSIMD for VL 928
1966 16:59:56.034783 # ok 236 # SKIP SVE set FPSIMD get SVE for VL 928
1967 16:59:56.034944 # ok 237 Set SVE VL 944
1968 16:59:56.035116 # ok 238 # SKIP SVE set SVE get SVE for VL 944
1969 16:59:56.035328 # ok 239 # SKIP SVE set SVE get FPSIMD for VL 944
1970 16:59:56.035514 # ok 240 # SKIP SVE set FPSIMD get SVE for VL 944
1971 16:59:56.035717 # ok 241 Set SVE VL 960
1972 16:59:56.035880 # ok 242 # SKIP SVE set SVE get SVE for VL 960
1973 16:59:56.036030 # ok 243 # SKIP SVE set SVE get FPSIMD for VL 960
1974 16:59:56.036225 # ok 244 # SKIP SVE set FPSIMD get SVE for VL 960
1975 16:59:56.036438 # ok 245 Set SVE VL 976
1976 16:59:56.036638 # ok 246 # SKIP SVE set SVE get SVE for VL 976
1977 16:59:56.036853 # ok 247 # SKIP SVE set SVE get FPSIMD for VL 976
1978 16:59:56.037071 # ok 248 # SKIP SVE set FPSIMD get SVE for VL 976
1979 16:59:56.037279 # ok 249 Set SVE VL 992
1980 16:59:56.037460 # ok 250 # SKIP SVE set SVE get SVE for VL 992
1981 16:59:56.037619 # ok 251 # SKIP SVE set SVE get FPSIMD for VL 992
1982 16:59:56.038206 # ok 252 # SKIP SVE set FPSIMD get SVE for VL 992
1983 16:59:56.038335 # ok 253 Set SVE VL 1008
1984 16:59:56.038454 # ok 254 # SKIP SVE set SVE get SVE for VL 1008
1985 16:59:56.038607 # ok 255 # SKIP SVE set SVE get FPSIMD for VL 1008
1986 16:59:56.038731 # ok 256 # SKIP SVE set FPSIMD get SVE for VL 1008
1987 16:59:56.038847 # ok 257 Set SVE VL 1024
1988 16:59:56.038964 # ok 258 # SKIP SVE set SVE get SVE for VL 1024
1989 16:59:56.039078 # ok 259 # SKIP SVE set SVE get FPSIMD for VL 1024
1990 16:59:56.039192 # ok 260 # SKIP SVE set FPSIMD get SVE for VL 1024
1991 16:59:56.039309 # ok 261 Set SVE VL 1040
1992 16:59:56.039426 # ok 262 # SKIP SVE set SVE get SVE for VL 1040
1993 16:59:56.039542 # ok 263 # SKIP SVE set SVE get FPSIMD for VL 1040
1994 16:59:56.039658 # ok 264 # SKIP SVE set FPSIMD get SVE for VL 1040
1995 16:59:56.039774 # ok 265 Set SVE VL 1056
1996 16:59:56.039890 # ok 266 # SKIP SVE set SVE get SVE for VL 1056
1997 16:59:56.040005 # ok 267 # SKIP SVE set SVE get FPSIMD for VL 1056
1998 16:59:56.040120 # ok 268 # SKIP SVE set FPSIMD get SVE for VL 1056
1999 16:59:56.040456 # ok 269 Set SVE VL 1072
2000 16:59:56.040583 # ok 270 # SKIP SVE set SVE get SVE for VL 1072
2001 16:59:56.040699 # ok 271 # SKIP SVE set SVE get FPSIMD for VL 1072
2002 16:59:56.040815 # ok 272 # SKIP SVE set FPSIMD get SVE for VL 1072
2003 16:59:56.040929 # ok 273 Set SVE VL 1088
2004 16:59:56.041043 # ok 274 # SKIP SVE set SVE get SVE for VL 1088
2005 16:59:56.041158 # ok 275 # SKIP SVE set SVE get FPSIMD for VL 1088
2006 16:59:56.047142 # ok 276 # SKIP SVE set FPSIMD get SVE for VL 1088
2007 16:59:56.047570 # ok 277 Set SVE VL 1104
2008 16:59:56.047687 # ok 278 # SKIP SVE set SVE get SVE for VL 1104
2009 16:59:56.047778 # ok 279 # SKIP SVE set SVE get FPSIMD for VL 1104
2010 16:59:56.047865 # ok 280 # SKIP SVE set FPSIMD get SVE for VL 1104
2011 16:59:56.047965 # ok 281 Set SVE VL 1120
2012 16:59:56.048052 # ok 282 # SKIP SVE set SVE get SVE for VL 1120
2013 16:59:56.048136 # ok 283 # SKIP SVE set SVE get FPSIMD for VL 1120
2014 16:59:56.048239 # ok 284 # SKIP SVE set FPSIMD get SVE for VL 1120
2015 16:59:56.048326 # ok 285 Set SVE VL 1136
2016 16:59:56.048425 # ok 286 # SKIP SVE set SVE get SVE for VL 1136
2017 16:59:56.048513 # ok 287 # SKIP SVE set SVE get FPSIMD for VL 1136
2018 16:59:56.048613 # ok 288 # SKIP SVE set FPSIMD get SVE for VL 1136
2019 16:59:56.048699 # ok 289 Set SVE VL 1152
2020 16:59:56.048799 # ok 290 # SKIP SVE set SVE get SVE for VL 1152
2021 16:59:56.049123 # ok 291 # SKIP SVE set SVE get FPSIMD for VL 1152
2022 16:59:56.049281 # ok 292 # SKIP SVE set FPSIMD get SVE for VL 1152
2023 16:59:56.059765 # ok 293 Set SVE VL 1168
2024 16:59:56.060052 # ok 294 # SKIP SVE set SVE get SVE for VL 1168
2025 16:59:56.060259 # ok 295 # SKIP SVE set SVE get FPSIMD for VL 1168
2026 16:59:56.060486 # ok 296 # SKIP SVE set FPSIMD get SVE for VL 1168
2027 16:59:56.060664 # ok 297 Set SVE VL 1184
2028 16:59:56.060825 # ok 298 # SKIP SVE set SVE get SVE for VL 1184
2029 16:59:56.060972 # ok 299 # SKIP SVE set SVE get FPSIMD for VL 1184
2030 16:59:56.061126 # ok 300 # SKIP SVE set FPSIMD get SVE for VL 1184
2031 16:59:56.061265 # ok 301 Set SVE VL 1200
2032 16:59:56.061417 # ok 302 # SKIP SVE set SVE get SVE for VL 1200
2033 16:59:56.061568 # ok 303 # SKIP SVE set SVE get FPSIMD for VL 1200
2034 16:59:56.061746 # ok 304 # SKIP SVE set FPSIMD get SVE for VL 1200
2035 16:59:56.061946 # ok 305 Set SVE VL 1216
2036 16:59:56.062121 # ok 306 # SKIP SVE set SVE get SVE for VL 1216
2037 16:59:56.062262 # ok 307 # SKIP SVE set SVE get FPSIMD for VL 1216
2038 16:59:56.062445 # ok 308 # SKIP SVE set FPSIMD get SVE for VL 1216
2039 16:59:56.062615 # ok 309 Set SVE VL 1232
2040 16:59:56.062777 # ok 310 # SKIP SVE set SVE get SVE for VL 1232
2041 16:59:56.062950 # ok 311 # SKIP SVE set SVE get FPSIMD for VL 1232
2042 16:59:56.063114 # ok 312 # SKIP SVE set FPSIMD get SVE for VL 1232
2043 16:59:56.063295 # ok 313 Set SVE VL 1248
2044 16:59:56.063525 # ok 314 # SKIP SVE set SVE get SVE for VL 1248
2045 16:59:56.063697 # ok 315 # SKIP SVE set SVE get FPSIMD for VL 1248
2046 16:59:56.063859 # ok 316 # SKIP SVE set FPSIMD get SVE for VL 1248
2047 16:59:56.064018 # ok 317 Set SVE VL 1264
2048 16:59:56.064177 # ok 318 # SKIP SVE set SVE get SVE for VL 1264
2049 16:59:56.064333 # ok 319 # SKIP SVE set SVE get FPSIMD for VL 1264
2050 16:59:56.064494 # ok 320 # SKIP SVE set FPSIMD get SVE for VL 1264
2051 16:59:56.064642 # ok 321 Set SVE VL 1280
2052 16:59:56.064801 # ok 322 # SKIP SVE set SVE get SVE for VL 1280
2053 16:59:56.064960 # ok 323 # SKIP SVE set SVE get FPSIMD for VL 1280
2054 16:59:56.065119 # ok 324 # SKIP SVE set FPSIMD get SVE for VL 1280
2055 16:59:56.065263 # ok 325 Set SVE VL 1296
2056 16:59:56.065421 # ok 326 # SKIP SVE set SVE get SVE for VL 1296
2057 16:59:56.065570 # ok 327 # SKIP SVE set SVE get FPSIMD for VL 1296
2058 16:59:56.066128 # ok 328 # SKIP SVE set FPSIMD get SVE for VL 1296
2059 16:59:56.066285 # ok 329 Set SVE VL 1312
2060 16:59:56.066427 # ok 330 # SKIP SVE set SVE get SVE for VL 1312
2061 16:59:56.066568 # ok 331 # SKIP SVE set SVE get FPSIMD for VL 1312
2062 16:59:56.066706 # ok 332 # SKIP SVE set FPSIMD get SVE for VL 1312
2063 16:59:56.066845 # ok 333 Set SVE VL 1328
2064 16:59:56.066983 # ok 334 # SKIP SVE set SVE get SVE for VL 1328
2065 16:59:56.067123 # ok 335 # SKIP SVE set SVE get FPSIMD for VL 1328
2066 16:59:56.067261 # ok 336 # SKIP SVE set FPSIMD get SVE for VL 1328
2067 16:59:56.067621 # ok 337 Set SVE VL 1344
2068 16:59:56.067756 # ok 338 # SKIP SVE set SVE get SVE for VL 1344
2069 16:59:56.067898 # ok 339 # SKIP SVE set SVE get FPSIMD for VL 1344
2070 16:59:56.068037 # ok 340 # SKIP SVE set FPSIMD get SVE for VL 1344
2071 16:59:56.068176 # ok 341 Set SVE VL 1360
2072 16:59:56.068315 # ok 342 # SKIP SVE set SVE get SVE for VL 1360
2073 16:59:56.068453 # ok 343 # SKIP SVE set SVE get FPSIMD for VL 1360
2074 16:59:56.068597 # ok 344 # SKIP SVE set FPSIMD get SVE for VL 1360
2075 16:59:56.068738 # ok 345 Set SVE VL 1376
2076 16:59:56.068878 # ok 346 # SKIP SVE set SVE get SVE for VL 1376
2077 16:59:56.069019 # ok 347 # SKIP SVE set SVE get FPSIMD for VL 1376
2078 16:59:56.069160 # ok 348 # SKIP SVE set FPSIMD get SVE for VL 1376
2079 16:59:56.069336 # ok 349 Set SVE VL 1392
2080 16:59:56.069513 # ok 350 # SKIP SVE set SVE get SVE for VL 1392
2081 16:59:56.069711 # ok 351 # SKIP SVE set SVE get FPSIMD for VL 1392
2082 16:59:56.069855 # ok 352 # SKIP SVE set FPSIMD get SVE for VL 1392
2083 16:59:56.069972 # ok 353 Set SVE VL 1408
2084 16:59:56.070090 # ok 354 # SKIP SVE set SVE get SVE for VL 1408
2085 16:59:56.070252 # ok 355 # SKIP SVE set SVE get FPSIMD for VL 1408
2086 16:59:56.070407 # ok 356 # SKIP SVE set FPSIMD get SVE for VL 1408
2087 16:59:56.070555 # ok 357 Set SVE VL 1424
2088 16:59:56.070743 # ok 358 # SKIP SVE set SVE get SVE for VL 1424
2089 16:59:56.070883 # ok 359 # SKIP SVE set SVE get FPSIMD for VL 1424
2090 16:59:56.071062 # ok 360 # SKIP SVE set FPSIMD get SVE for VL 1424
2091 16:59:56.071228 # ok 361 Set SVE VL 1440
2092 16:59:56.071379 # ok 362 # SKIP SVE set SVE get SVE for VL 1440
2093 16:59:56.071569 # ok 363 # SKIP SVE set SVE get FPSIMD for VL 1440
2094 16:59:56.071737 # ok 364 # SKIP SVE set FPSIMD get SVE for VL 1440
2095 16:59:56.071896 # ok 365 Set SVE VL 1456
2096 16:59:56.072055 # ok 366 # SKIP SVE set SVE get SVE for VL 1456
2097 16:59:56.072216 # ok 367 # SKIP SVE set SVE get FPSIMD for VL 1456
2098 16:59:56.072374 # ok 368 # SKIP SVE set FPSIMD get SVE for VL 1456
2099 16:59:56.072566 # ok 369 Set SVE VL 1472
2100 16:59:56.072737 # ok 370 # SKIP SVE set SVE get SVE for VL 1472
2101 16:59:56.072899 # ok 371 # SKIP SVE set SVE get FPSIMD for VL 1472
2102 16:59:56.073063 # ok 372 # SKIP SVE set FPSIMD get SVE for VL 1472
2103 16:59:56.073217 # ok 373 Set SVE VL 1488
2104 16:59:56.073369 # ok 374 # SKIP SVE set SVE get SVE for VL 1488
2105 16:59:56.073528 # ok 375 # SKIP SVE set SVE get FPSIMD for VL 1488
2106 16:59:56.073697 # ok 376 # SKIP SVE set FPSIMD get SVE for VL 1488
2107 16:59:56.073838 # ok 377 Set SVE VL 1504
2108 16:59:56.073953 # ok 378 # SKIP SVE set SVE get SVE for VL 1504
2109 16:59:56.074087 # ok 379 # SKIP SVE set SVE get FPSIMD for VL 1504
2110 16:59:56.074423 # ok 380 # SKIP SVE set FPSIMD get SVE for VL 1504
2111 16:59:56.074554 # ok 381 Set SVE VL 1520
2112 16:59:56.074673 # ok 382 # SKIP SVE set SVE get SVE for VL 1520
2113 16:59:56.074789 # ok 383 # SKIP SVE set SVE get FPSIMD for VL 1520
2114 16:59:56.074906 # ok 384 # SKIP SVE set FPSIMD get SVE for VL 1520
2115 16:59:56.075020 # ok 385 Set SVE VL 1536
2116 16:59:56.075137 # ok 386 # SKIP SVE set SVE get SVE for VL 1536
2117 16:59:56.075253 # ok 387 # SKIP SVE set SVE get FPSIMD for VL 1536
2118 16:59:56.075368 # ok 388 # SKIP SVE set FPSIMD get SVE for VL 1536
2119 16:59:56.075486 # ok 389 Set SVE VL 1552
2120 16:59:56.075602 # ok 390 # SKIP SVE set SVE get SVE for VL 1552
2121 16:59:56.078283 # ok 391 # SKIP SVE set SVE get FPSIMD for VL 1552
2122 16:59:56.078684 # ok 392 # SKIP SVE set FPSIMD get SVE for VL 1552
2123 16:59:56.078857 # ok 393 Set SVE VL 1568
2124 16:59:56.079022 # ok 394 # SKIP SVE set SVE get SVE for VL 1568
2125 16:59:56.079180 # ok 395 # SKIP SVE set SVE get FPSIMD for VL 1568
2126 16:59:56.079365 # ok 396 # SKIP SVE set FPSIMD get SVE for VL 1568
2127 16:59:56.079523 # ok 397 Set SVE VL 1584
2128 16:59:56.079669 # ok 398 # SKIP SVE set SVE get SVE for VL 1584
2129 16:59:56.079826 # ok 399 # SKIP SVE set SVE get FPSIMD for VL 1584
2130 16:59:56.079982 # ok 400 # SKIP SVE set FPSIMD get SVE for VL 1584
2131 16:59:56.080139 # ok 401 Set SVE VL 1600
2132 16:59:56.080295 # ok 402 # SKIP SVE set SVE get SVE for VL 1600
2133 16:59:56.080487 # ok 403 # SKIP SVE set SVE get FPSIMD for VL 1600
2134 16:59:56.080647 # ok 404 # SKIP SVE set FPSIMD get SVE for VL 1600
2135 16:59:56.080789 # ok 405 Set SVE VL 1616
2136 16:59:56.080942 # ok 406 # SKIP SVE set SVE get SVE for VL 1616
2137 16:59:56.081094 # ok 407 # SKIP SVE set SVE get FPSIMD for VL 1616
2138 16:59:56.081247 # ok 408 # SKIP SVE set FPSIMD get SVE for VL 1616
2139 16:59:56.081397 # ok 409 Set SVE VL 1632
2140 16:59:56.081549 # ok 410 # SKIP SVE set SVE get SVE for VL 1632
2141 16:59:56.081720 # ok 411 # SKIP SVE set SVE get FPSIMD for VL 1632
2142 16:59:56.081862 # ok 412 # SKIP SVE set FPSIMD get SVE for VL 1632
2143 16:59:56.082013 # ok 413 Set SVE VL 1648
2144 16:59:56.082146 # ok 414 # SKIP SVE set SVE get SVE for VL 1648
2145 16:59:56.082262 # ok 415 # SKIP SVE set SVE get FPSIMD for VL 1648
2146 16:59:56.082412 # ok 416 # SKIP SVE set FPSIMD get SVE for VL 1648
2147 16:59:56.082535 # ok 417 Set SVE VL 1664
2148 16:59:56.082650 # ok 418 # SKIP SVE set SVE get SVE for VL 1664
2149 16:59:56.082765 # ok 419 # SKIP SVE set SVE get FPSIMD for VL 1664
2150 16:59:56.082879 # ok 420 # SKIP SVE set FPSIMD get SVE for VL 1664
2151 16:59:56.082992 # ok 421 Set SVE VL 1680
2152 16:59:56.083107 # ok 422 # SKIP SVE set SVE get SVE for VL 1680
2153 16:59:56.083221 # ok 423 # SKIP SVE set SVE get FPSIMD for VL 1680
2154 16:59:56.083334 # ok 424 # SKIP SVE set FPSIMD get SVE for VL 1680
2155 16:59:56.083448 # ok 425 Set SVE VL 1696
2156 16:59:56.083563 # ok 426 # SKIP SVE set SVE get SVE for VL 1696
2157 16:59:56.083679 # ok 427 # SKIP SVE set SVE get FPSIMD for VL 1696
2158 16:59:56.083793 # ok 428 # SKIP SVE set FPSIMD get SVE for VL 1696
2159 16:59:56.083906 # ok 429 Set SVE VL 1712
2160 16:59:56.084019 # ok 430 # SKIP SVE set SVE get SVE for VL 1712
2161 16:59:56.084134 # ok 431 # SKIP SVE set SVE get FPSIMD for VL 1712
2162 16:59:56.089953 # ok 432 # SKIP SVE set FPSIMD get SVE for VL 1712
2163 16:59:56.090353 # ok 433 Set SVE VL 1728
2164 16:59:56.090530 # ok 434 # SKIP SVE set SVE get SVE for VL 1728
2165 16:59:56.090681 # ok 435 # SKIP SVE set SVE get FPSIMD for VL 1728
2166 16:59:56.090826 # ok 436 # SKIP SVE set FPSIMD get SVE for VL 1728
2167 16:59:56.090974 # ok 437 Set SVE VL 1744
2168 16:59:56.091162 # ok 438 # SKIP SVE set SVE get SVE for VL 1744
2169 16:59:56.091367 # ok 439 # SKIP SVE set SVE get FPSIMD for VL 1744
2170 16:59:56.091550 # ok 440 # SKIP SVE set FPSIMD get SVE for VL 1744
2171 16:59:56.091733 # ok 441 Set SVE VL 1760
2172 16:59:56.091968 # ok 442 # SKIP SVE set SVE get SVE for VL 1760
2173 16:59:56.092183 # ok 443 # SKIP SVE set SVE get FPSIMD for VL 1760
2174 16:59:56.092378 # ok 444 # SKIP SVE set FPSIMD get SVE for VL 1760
2175 16:59:56.092514 # ok 445 Set SVE VL 1776
2176 16:59:56.092635 # ok 446 # SKIP SVE set SVE get SVE for VL 1776
2177 16:59:56.092774 # ok 447 # SKIP SVE set SVE get FPSIMD for VL 1776
2178 16:59:56.092932 # ok 448 # SKIP SVE set FPSIMD get SVE for VL 1776
2179 16:59:56.093096 # ok 449 Set SVE VL 1792
2180 16:59:56.093264 # ok 450 # SKIP SVE set SVE get SVE for VL 1792
2181 16:59:56.093429 # ok 451 # SKIP SVE set SVE get FPSIMD for VL 1792
2182 16:59:56.093585 # ok 452 # SKIP SVE set FPSIMD get SVE for VL 1792
2183 16:59:56.093756 # ok 453 Set SVE VL 1808
2184 16:59:56.093927 # ok 454 # SKIP SVE set SVE get SVE for VL 1808
2185 16:59:56.094055 # ok 455 # SKIP SVE set SVE get FPSIMD for VL 1808
2186 16:59:56.094174 # ok 456 # SKIP SVE set FPSIMD get SVE for VL 1808
2187 16:59:56.094292 # ok 457 Set SVE VL 1824
2188 16:59:56.094408 # ok 458 # SKIP SVE set SVE get SVE for VL 1824
2189 16:59:56.094528 # ok 459 # SKIP SVE set SVE get FPSIMD for VL 1824
2190 16:59:56.094644 # ok 460 # SKIP SVE set FPSIMD get SVE for VL 1824
2191 16:59:56.094761 # ok 461 Set SVE VL 1840
2192 16:59:56.094877 # ok 462 # SKIP SVE set SVE get SVE for VL 1840
2193 16:59:56.094993 # ok 463 # SKIP SVE set SVE get FPSIMD for VL 1840
2194 16:59:56.095110 # ok 464 # SKIP SVE set FPSIMD get SVE for VL 1840
2195 16:59:56.095225 # ok 465 Set SVE VL 1856
2196 16:59:56.095340 # ok 466 # SKIP SVE set SVE get SVE for VL 1856
2197 16:59:56.095455 # ok 467 # SKIP SVE set SVE get FPSIMD for VL 1856
2198 16:59:56.095573 # ok 468 # SKIP SVE set FPSIMD get SVE for VL 1856
2199 16:59:56.095692 # ok 469 Set SVE VL 1872
2200 16:59:56.095807 # ok 470 # SKIP SVE set SVE get SVE for VL 1872
2201 16:59:56.095926 # ok 471 # SKIP SVE set SVE get FPSIMD for VL 1872
2202 16:59:56.096043 # ok 472 # SKIP SVE set FPSIMD get SVE for VL 1872
2203 16:59:56.096159 # ok 473 Set SVE VL 1888
2204 16:59:56.098190 # ok 474 # SKIP SVE set SVE get SVE for VL 1888
2205 16:59:56.098612 # ok 475 # SKIP SVE set SVE get FPSIMD for VL 1888
2206 16:59:56.098782 # ok 476 # SKIP SVE set FPSIMD get SVE for VL 1888
2207 16:59:56.098906 # ok 477 Set SVE VL 1904
2208 16:59:56.099023 # ok 478 # SKIP SVE set SVE get SVE for VL 1904
2209 16:59:56.099162 # ok 479 # SKIP SVE set SVE get FPSIMD for VL 1904
2210 16:59:56.100890 # ok 480 # SKIP SVE set FPSIMD get SVE for VL 1904
2211 16:59:56.101102 # ok 481 Set SVE VL 1920
2212 16:59:56.101268 # ok 482 # SKIP SVE set SVE get SVE for VL 1920
2213 16:59:56.101464 # ok 483 # SKIP SVE set SVE get FPSIMD for VL 1920
2214 16:59:56.101637 # ok 484 # SKIP SVE set FPSIMD get SVE for VL 1920
2215 16:59:56.101846 # ok 485 Set SVE VL 1936
2216 16:59:56.101979 # ok 486 # SKIP SVE set SVE get SVE for VL 1936
2217 16:59:56.102095 # ok 487 # SKIP SVE set SVE get FPSIMD for VL 1936
2218 16:59:56.102257 # ok 488 # SKIP SVE set FPSIMD get SVE for VL 1936
2219 16:59:56.102465 # ok 489 Set SVE VL 1952
2220 16:59:56.102702 # ok 490 # SKIP SVE set SVE get SVE for VL 1952
2221 16:59:56.102945 # ok 491 # SKIP SVE set SVE get FPSIMD for VL 1952
2222 16:59:56.103127 # ok 492 # SKIP SVE set FPSIMD get SVE for VL 1952
2223 16:59:56.103346 # ok 493 Set SVE VL 1968
2224 16:59:56.103558 # ok 494 # SKIP SVE set SVE get SVE for VL 1968
2225 16:59:56.103778 # ok 495 # SKIP SVE set SVE get FPSIMD for VL 1968
2226 16:59:56.103980 # ok 496 # SKIP SVE set FPSIMD get SVE for VL 1968
2227 16:59:56.104148 # ok 497 Set SVE VL 1984
2228 16:59:56.104354 # ok 498 # SKIP SVE set SVE get SVE for VL 1984
2229 16:59:56.104524 # ok 499 # SKIP SVE set SVE get FPSIMD for VL 1984
2230 16:59:56.104675 # ok 500 # SKIP SVE set FPSIMD get SVE for VL 1984
2231 16:59:56.104798 # ok 501 Set SVE VL 2000
2232 16:59:56.104939 # ok 502 # SKIP SVE set SVE get SVE for VL 2000
2233 16:59:56.105089 # ok 503 # SKIP SVE set SVE get FPSIMD for VL 2000
2234 16:59:56.105242 # ok 504 # SKIP SVE set FPSIMD get SVE for VL 2000
2235 16:59:56.105399 # ok 505 Set SVE VL 2016
2236 16:59:56.105530 # ok 506 # SKIP SVE set SVE get SVE for VL 2016
2237 16:59:56.106178 # ok 507 # SKIP SVE set SVE get FPSIMD for VL 2016
2238 16:59:56.106329 # ok 508 # SKIP SVE set FPSIMD get SVE for VL 2016
2239 16:59:56.106448 # ok 509 Set SVE VL 2032
2240 16:59:56.106564 # ok 510 # SKIP SVE set SVE get SVE for VL 2032
2241 16:59:56.106684 # ok 511 # SKIP SVE set SVE get FPSIMD for VL 2032
2242 16:59:56.106832 # ok 512 # SKIP SVE set FPSIMD get SVE for VL 2032
2243 16:59:56.106956 # ok 513 Set SVE VL 2048
2244 16:59:56.107073 # ok 514 # SKIP SVE set SVE get SVE for VL 2048
2245 16:59:56.107189 # ok 515 # SKIP SVE set SVE get FPSIMD for VL 2048
2246 16:59:56.107303 # ok 516 # SKIP SVE set FPSIMD get SVE for VL 2048
2247 16:59:56.107419 # ok 517 Set SVE VL 2064
2248 16:59:56.107535 # ok 518 # SKIP SVE set SVE get SVE for VL 2064
2249 16:59:56.107650 # ok 519 # SKIP SVE set SVE get FPSIMD for VL 2064
2250 16:59:56.107764 # ok 520 # SKIP SVE set FPSIMD get SVE for VL 2064
2251 16:59:56.107880 # ok 521 Set SVE VL 2080
2252 16:59:56.107994 # ok 522 # SKIP SVE set SVE get SVE for VL 2080
2253 16:59:56.108110 # ok 523 # SKIP SVE set SVE get FPSIMD for VL 2080
2254 16:59:56.108435 # ok 524 # SKIP SVE set FPSIMD get SVE for VL 2080
2255 16:59:56.108563 # ok 525 Set SVE VL 2096
2256 16:59:56.108681 # ok 526 # SKIP SVE set SVE get SVE for VL 2096
2257 16:59:56.108797 # ok 527 # SKIP SVE set SVE get FPSIMD for VL 2096
2258 16:59:56.108913 # ok 528 # SKIP SVE set FPSIMD get SVE for VL 2096
2259 16:59:56.110286 # ok 529 Set SVE VL 2112
2260 16:59:56.110741 # ok 530 # SKIP SVE set SVE get SVE for VL 2112
2261 16:59:56.110939 # ok 531 # SKIP SVE set SVE get FPSIMD for VL 2112
2262 16:59:56.111105 # ok 532 # SKIP SVE set FPSIMD get SVE for VL 2112
2263 16:59:56.111285 # ok 533 Set SVE VL 2128
2264 16:59:56.111496 # ok 534 # SKIP SVE set SVE get SVE for VL 2128
2265 16:59:56.111723 # ok 535 # SKIP SVE set SVE get FPSIMD for VL 2128
2266 16:59:56.111918 # ok 536 # SKIP SVE set FPSIMD get SVE for VL 2128
2267 16:59:56.112096 # ok 537 Set SVE VL 2144
2268 16:59:56.112295 # ok 538 # SKIP SVE set SVE get SVE for VL 2144
2269 16:59:56.112493 # ok 539 # SKIP SVE set SVE get FPSIMD for VL 2144
2270 16:59:56.112716 # ok 540 # SKIP SVE set FPSIMD get SVE for VL 2144
2271 16:59:56.112934 # ok 541 Set SVE VL 2160
2272 16:59:56.113127 # ok 542 # SKIP SVE set SVE get SVE for VL 2160
2273 16:59:56.113305 # ok 543 # SKIP SVE set SVE get FPSIMD for VL 2160
2274 16:59:56.113449 # ok 544 # SKIP SVE set FPSIMD get SVE for VL 2160
2275 16:59:56.113656 # ok 545 Set SVE VL 2176
2276 16:59:56.113848 # ok 546 # SKIP SVE set SVE get SVE for VL 2176
2277 16:59:56.113984 # ok 547 # SKIP SVE set SVE get FPSIMD for VL 2176
2278 16:59:56.114103 # ok 548 # SKIP SVE set FPSIMD get SVE for VL 2176
2279 16:59:56.114219 # ok 549 Set SVE VL 2192
2280 16:59:56.114333 # ok 550 # SKIP SVE set SVE get SVE for VL 2192
2281 16:59:56.114479 # ok 551 # SKIP SVE set SVE get FPSIMD for VL 2192
2282 16:59:56.114605 # ok 552 # SKIP SVE set FPSIMD get SVE for VL 2192
2283 16:59:56.114721 # ok 553 Set SVE VL 2208
2284 16:59:56.114836 # ok 554 # SKIP SVE set SVE get SVE for VL 2208
2285 16:59:56.114951 # ok 555 # SKIP SVE set SVE get FPSIMD for VL 2208
2286 16:59:56.115065 # ok 556 # SKIP SVE set FPSIMD get SVE for VL 2208
2287 16:59:56.115181 # ok 557 Set SVE VL 2224
2288 16:59:56.115297 # ok 558 # SKIP SVE set SVE get SVE for VL 2224
2289 16:59:56.115412 # ok 559 # SKIP SVE set SVE get FPSIMD for VL 2224
2290 16:59:56.115527 # ok 560 # SKIP SVE set FPSIMD get SVE for VL 2224
2291 16:59:56.115642 # ok 561 Set SVE VL 2240
2292 16:59:56.118232 # ok 562 # SKIP SVE set SVE get SVE for VL 2240
2293 16:59:56.118699 # ok 563 # SKIP SVE set SVE get FPSIMD for VL 2240
2294 16:59:56.118980 # ok 564 # SKIP SVE set FPSIMD get SVE for VL 2240
2295 16:59:56.119159 # ok 565 Set SVE VL 2256
2296 16:59:56.119331 # ok 566 # SKIP SVE set SVE get SVE for VL 2256
2297 16:59:56.119541 # ok 567 # SKIP SVE set SVE get FPSIMD for VL 2256
2298 16:59:56.119695 # ok 568 # SKIP SVE set FPSIMD get SVE for VL 2256
2299 16:59:56.119891 # ok 569 Set SVE VL 2272
2300 16:59:56.120068 # ok 570 # SKIP SVE set SVE get SVE for VL 2272
2301 16:59:56.120233 # ok 571 # SKIP SVE set SVE get FPSIMD for VL 2272
2302 16:59:56.120379 # ok 572 # SKIP SVE set FPSIMD get SVE for VL 2272
2303 16:59:56.120537 # ok 573 Set SVE VL 2288
2304 16:59:56.120651 # ok 574 # SKIP SVE set SVE get SVE for VL 2288
2305 16:59:56.120775 # ok 575 # SKIP SVE set SVE get FPSIMD for VL 2288
2306 16:59:56.120933 # ok 576 # SKIP SVE set FPSIMD get SVE for VL 2288
2307 16:59:56.121046 # ok 577 Set SVE VL 2304
2308 16:59:56.121182 # ok 578 # SKIP SVE set SVE get SVE for VL 2304
2309 16:59:56.121304 # ok 579 # SKIP SVE set SVE get FPSIMD for VL 2304
2310 16:59:56.121442 # ok 580 # SKIP SVE set FPSIMD get SVE for VL 2304
2311 16:59:56.121596 # ok 581 Set SVE VL 2320
2312 16:59:56.121723 # ok 582 # SKIP SVE set SVE get SVE for VL 2320
2313 16:59:56.121814 # ok 583 # SKIP SVE set SVE get FPSIMD for VL 2320
2314 16:59:56.121900 # ok 584 # SKIP SVE set FPSIMD get SVE for VL 2320
2315 16:59:56.121986 # ok 585 Set SVE VL 2336
2316 16:59:56.122070 # ok 586 # SKIP SVE set SVE get SVE for VL 2336
2317 16:59:56.122155 # ok 587 # SKIP SVE set SVE get FPSIMD for VL 2336
2318 16:59:56.122240 # ok 588 # SKIP SVE set FPSIMD get SVE for VL 2336
2319 16:59:56.122325 # ok 589 Set SVE VL 2352
2320 16:59:56.122433 # ok 590 # SKIP SVE set SVE get SVE for VL 2352
2321 16:59:56.122525 # ok 591 # SKIP SVE set SVE get FPSIMD for VL 2352
2322 16:59:56.122594 # ok 592 # SKIP SVE set FPSIMD get SVE for VL 2352
2323 16:59:56.122653 # ok 593 Set SVE VL 2368
2324 16:59:56.122711 # ok 594 # SKIP SVE set SVE get SVE for VL 2368
2325 16:59:56.122769 # ok 595 # SKIP SVE set SVE get FPSIMD for VL 2368
2326 16:59:56.122827 # ok 596 # SKIP SVE set FPSIMD get SVE for VL 2368
2327 16:59:56.128158 # ok 597 Set SVE VL 2384
2328 16:59:56.128631 # ok 598 # SKIP SVE set SVE get SVE for VL 2384
2329 16:59:56.128837 # ok 599 # SKIP SVE set SVE get FPSIMD for VL 2384
2330 16:59:56.129011 # ok 600 # SKIP SVE set FPSIMD get SVE for VL 2384
2331 16:59:56.129209 # ok 601 Set SVE VL 2400
2332 16:59:56.129414 # ok 602 # SKIP SVE set SVE get SVE for VL 2400
2333 16:59:56.129581 # ok 603 # SKIP SVE set SVE get FPSIMD for VL 2400
2334 16:59:56.129843 # ok 604 # SKIP SVE set FPSIMD get SVE for VL 2400
2335 16:59:56.130018 # ok 605 Set SVE VL 2416
2336 16:59:56.130222 # ok 606 # SKIP SVE set SVE get SVE for VL 2416
2337 16:59:56.130433 # ok 607 # SKIP SVE set SVE get FPSIMD for VL 2416
2338 16:59:56.130621 # ok 608 # SKIP SVE set FPSIMD get SVE for VL 2416
2339 16:59:56.130788 # ok 609 Set SVE VL 2432
2340 16:59:56.130942 # ok 610 # SKIP SVE set SVE get SVE for VL 2432
2341 16:59:56.131094 # ok 611 # SKIP SVE set SVE get FPSIMD for VL 2432
2342 16:59:56.131246 # ok 612 # SKIP SVE set FPSIMD get SVE for VL 2432
2343 16:59:56.131406 # ok 613 Set SVE VL 2448
2344 16:59:56.131533 # ok 614 # SKIP SVE set SVE get SVE for VL 2448
2345 16:59:56.131651 # ok 615 # SKIP SVE set SVE get FPSIMD for VL 2448
2346 16:59:56.131790 # ok 616 # SKIP SVE set FPSIMD get SVE for VL 2448
2347 16:59:56.131909 # ok 617 Set SVE VL 2464
2348 16:59:56.132056 # ok 618 # SKIP SVE set SVE get SVE for VL 2464
2349 16:59:56.132185 # ok 619 # SKIP SVE set SVE get FPSIMD for VL 2464
2350 16:59:56.132335 # ok 620 # SKIP SVE set FPSIMD get SVE for VL 2464
2351 16:59:56.132458 # ok 621 Set SVE VL 2480
2352 16:59:56.132609 # ok 622 # SKIP SVE set SVE get SVE for VL 2480
2353 16:59:56.132743 # ok 623 # SKIP SVE set SVE get FPSIMD for VL 2480
2354 16:59:56.132849 # ok 624 # SKIP SVE set FPSIMD get SVE for VL 2480
2355 16:59:56.132967 # ok 625 Set SVE VL 2496
2356 16:59:56.133108 # ok 626 # SKIP SVE set SVE get SVE for VL 2496
2357 16:59:56.133221 # ok 627 # SKIP SVE set SVE get FPSIMD for VL 2496
2358 16:59:56.133380 # ok 628 # SKIP SVE set FPSIMD get SVE for VL 2496
2359 16:59:56.133508 # ok 629 Set SVE VL 2512
2360 16:59:56.133632 # ok 630 # SKIP SVE set SVE get SVE for VL 2512
2361 16:59:56.133815 # ok 631 # SKIP SVE set SVE get FPSIMD for VL 2512
2362 16:59:56.133959 # ok 632 # SKIP SVE set FPSIMD get SVE for VL 2512
2363 16:59:56.134097 # ok 633 Set SVE VL 2528
2364 16:59:56.134233 # ok 634 # SKIP SVE set SVE get SVE for VL 2528
2365 16:59:56.134368 # ok 635 # SKIP SVE set SVE get FPSIMD for VL 2528
2366 16:59:56.134488 # ok 636 # SKIP SVE set FPSIMD get SVE for VL 2528
2367 16:59:56.134601 # ok 637 Set SVE VL 2544
2368 16:59:56.134714 # ok 638 # SKIP SVE set SVE get SVE for VL 2544
2369 16:59:56.134795 # ok 639 # SKIP SVE set SVE get FPSIMD for VL 2544
2370 16:59:56.134873 # ok 640 # SKIP SVE set FPSIMD get SVE for VL 2544
2371 16:59:56.134943 # ok 641 Set SVE VL 2560
2372 16:59:56.135226 # ok 642 # SKIP SVE set SVE get SVE for VL 2560
2373 16:59:56.135321 # ok 643 # SKIP SVE set SVE get FPSIMD for VL 2560
2374 16:59:56.135411 # ok 644 # SKIP SVE set FPSIMD get SVE for VL 2560
2375 16:59:56.135501 # ok 645 Set SVE VL 2576
2376 16:59:56.135598 # ok 646 # SKIP SVE set SVE get SVE for VL 2576
2377 16:59:56.135699 # ok 647 # SKIP SVE set SVE get FPSIMD for VL 2576
2378 16:59:56.135807 # ok 648 # SKIP SVE set FPSIMD get SVE for VL 2576
2379 16:59:56.135909 # ok 649 Set SVE VL 2592
2380 16:59:56.136008 # ok 650 # SKIP SVE set SVE get SVE for VL 2592
2381 16:59:56.136094 # ok 651 # SKIP SVE set SVE get FPSIMD for VL 2592
2382 16:59:56.136179 # ok 652 # SKIP SVE set FPSIMD get SVE for VL 2592
2383 16:59:56.136263 # ok 653 Set SVE VL 2608
2384 16:59:56.136347 # ok 654 # SKIP SVE set SVE get SVE for VL 2608
2385 16:59:56.136432 # ok 655 # SKIP SVE set SVE get FPSIMD for VL 2608
2386 16:59:56.136517 # ok 656 # SKIP SVE set FPSIMD get SVE for VL 2608
2387 16:59:56.136603 # ok 657 Set SVE VL 2624
2388 16:59:56.136689 # ok 658 # SKIP SVE set SVE get SVE for VL 2624
2389 16:59:56.136795 # ok 659 # SKIP SVE set SVE get FPSIMD for VL 2624
2390 16:59:56.136885 # ok 660 # SKIP SVE set FPSIMD get SVE for VL 2624
2391 16:59:56.136972 # ok 661 Set SVE VL 2640
2392 16:59:56.137057 # ok 662 # SKIP SVE set SVE get SVE for VL 2640
2393 16:59:56.137145 # ok 663 # SKIP SVE set SVE get FPSIMD for VL 2640
2394 16:59:56.137230 # ok 664 # SKIP SVE set FPSIMD get SVE for VL 2640
2395 16:59:56.137315 # ok 665 Set SVE VL 2656
2396 16:59:56.137398 # ok 666 # SKIP SVE set SVE get SVE for VL 2656
2397 16:59:56.148349 # ok 667 # SKIP SVE set SVE get FPSIMD for VL 2656
2398 16:59:56.148734 # ok 668 # SKIP SVE set FPSIMD get SVE for VL 2656
2399 16:59:56.148845 # ok 669 Set SVE VL 2672
2400 16:59:56.148937 # ok 670 # SKIP SVE set SVE get SVE for VL 2672
2401 16:59:56.149027 # ok 671 # SKIP SVE set SVE get FPSIMD for VL 2672
2402 16:59:56.149135 # ok 672 # SKIP SVE set FPSIMD get SVE for VL 2672
2403 16:59:56.149225 # ok 673 Set SVE VL 2688
2404 16:59:56.149311 # ok 674 # SKIP SVE set SVE get SVE for VL 2688
2405 16:59:56.149395 # ok 675 # SKIP SVE set SVE get FPSIMD for VL 2688
2406 16:59:56.149496 # ok 676 # SKIP SVE set FPSIMD get SVE for VL 2688
2407 16:59:56.149584 # ok 677 Set SVE VL 2704
2408 16:59:56.149675 # ok 678 # SKIP SVE set SVE get SVE for VL 2704
2409 16:59:56.149773 # ok 679 # SKIP SVE set SVE get FPSIMD for VL 2704
2410 16:59:56.150316 # ok 680 # SKIP SVE set FPSIMD get SVE for VL 2704
2411 16:59:56.150589 # ok 681 Set SVE VL 2720
2412 16:59:56.150763 # ok 682 # SKIP SVE set SVE get SVE for VL 2720
2413 16:59:56.150960 # ok 683 # SKIP SVE set SVE get FPSIMD for VL 2720
2414 16:59:56.151138 # ok 684 # SKIP SVE set FPSIMD get SVE for VL 2720
2415 16:59:56.151327 # ok 685 Set SVE VL 2736
2416 16:59:56.151504 # ok 686 # SKIP SVE set SVE get SVE for VL 2736
2417 16:59:56.151705 # ok 687 # SKIP SVE set SVE get FPSIMD for VL 2736
2418 16:59:56.151869 # ok 688 # SKIP SVE set FPSIMD get SVE for VL 2736
2419 16:59:56.152031 # ok 689 Set SVE VL 2752
2420 16:59:56.152189 # ok 690 # SKIP SVE set SVE get SVE for VL 2752
2421 16:59:56.152334 # ok 691 # SKIP SVE set SVE get FPSIMD for VL 2752
2422 16:59:56.152475 # ok 692 # SKIP SVE set FPSIMD get SVE for VL 2752
2423 16:59:56.152624 # ok 693 Set SVE VL 2768
2424 16:59:56.152766 # ok 694 # SKIP SVE set SVE get SVE for VL 2768
2425 16:59:56.152962 # ok 695 # SKIP SVE set SVE get FPSIMD for VL 2768
2426 16:59:56.153126 # ok 696 # SKIP SVE set FPSIMD get SVE for VL 2768
2427 16:59:56.153278 # ok 697 Set SVE VL 2784
2428 16:59:56.153434 # ok 698 # SKIP SVE set SVE get SVE for VL 2784
2429 16:59:56.153594 # ok 699 # SKIP SVE set SVE get FPSIMD for VL 2784
2430 16:59:56.153806 # ok 700 # SKIP SVE set FPSIMD get SVE for VL 2784
2431 16:59:56.153997 # ok 701 Set SVE VL 2800
2432 16:59:56.154179 # ok 702 # SKIP SVE set SVE get SVE for VL 2800
2433 16:59:56.154364 # ok 703 # SKIP SVE set SVE get FPSIMD for VL 2800
2434 16:59:56.154573 # ok 704 # SKIP SVE set FPSIMD get SVE for VL 2800
2435 16:59:56.154719 # ok 705 Set SVE VL 2816
2436 16:59:56.154838 # ok 706 # SKIP SVE set SVE get SVE for VL 2816
2437 16:59:56.154963 # ok 707 # SKIP SVE set SVE get FPSIMD for VL 2816
2438 16:59:56.155077 # ok 708 # SKIP SVE set FPSIMD get SVE for VL 2816
2439 16:59:56.155192 # ok 709 Set SVE VL 2832
2440 16:59:56.155292 # ok 710 # SKIP SVE set SVE get SVE for VL 2832
2441 16:59:56.155396 # ok 711 # SKIP SVE set SVE get FPSIMD for VL 2832
2442 16:59:56.155507 # ok 712 # SKIP SVE set FPSIMD get SVE for VL 2832
2443 16:59:56.155606 # ok 713 Set SVE VL 2848
2444 16:59:56.155713 # ok 714 # SKIP SVE set SVE get SVE for VL 2848
2445 16:59:56.155824 # ok 715 # SKIP SVE set SVE get FPSIMD for VL 2848
2446 16:59:56.155931 # ok 716 # SKIP SVE set FPSIMD get SVE for VL 2848
2447 16:59:56.156047 # ok 717 Set SVE VL 2864
2448 16:59:56.156169 # ok 718 # SKIP SVE set SVE get SVE for VL 2864
2449 16:59:56.156290 # ok 719 # SKIP SVE set SVE get FPSIMD for VL 2864
2450 16:59:56.156406 # ok 720 # SKIP SVE set FPSIMD get SVE for VL 2864
2451 16:59:56.156525 # ok 721 Set SVE VL 2880
2452 16:59:56.156641 # ok 722 # SKIP SVE set SVE get SVE for VL 2880
2453 16:59:56.156759 # ok 723 # SKIP SVE set SVE get FPSIMD for VL 2880
2454 16:59:56.156880 # ok 724 # SKIP SVE set FPSIMD get SVE for VL 2880
2455 16:59:56.157240 # ok 725 Set SVE VL 2896
2456 16:59:56.157401 # ok 726 # SKIP SVE set SVE get SVE for VL 2896
2457 16:59:56.157541 # ok 727 # SKIP SVE set SVE get FPSIMD for VL 2896
2458 16:59:56.157680 # ok 728 # SKIP SVE set FPSIMD get SVE for VL 2896
2459 16:59:56.157791 # ok 729 Set SVE VL 2912
2460 16:59:56.157897 # ok 730 # SKIP SVE set SVE get SVE for VL 2912
2461 16:59:56.158010 # ok 731 # SKIP SVE set SVE get FPSIMD for VL 2912
2462 16:59:56.158125 # ok 732 # SKIP SVE set FPSIMD get SVE for VL 2912
2463 16:59:56.158255 # ok 733 Set SVE VL 2928
2464 16:59:56.158401 # ok 734 # SKIP SVE set SVE get SVE for VL 2928
2465 16:59:56.158537 # ok 735 # SKIP SVE set SVE get FPSIMD for VL 2928
2466 16:59:56.158682 # ok 736 # SKIP SVE set FPSIMD get SVE for VL 2928
2467 16:59:56.158823 # ok 737 Set SVE VL 2944
2468 16:59:56.158931 # ok 738 # SKIP SVE set SVE get SVE for VL 2944
2469 16:59:56.159037 # ok 739 # SKIP SVE set SVE get FPSIMD for VL 2944
2470 16:59:56.159142 # ok 740 # SKIP SVE set FPSIMD get SVE for VL 2944
2471 16:59:56.159250 # ok 741 Set SVE VL 2960
2472 16:59:56.159396 # ok 742 # SKIP SVE set SVE get SVE for VL 2960
2473 16:59:56.159547 # ok 743 # SKIP SVE set SVE get FPSIMD for VL 2960
2474 16:59:56.159710 # ok 744 # SKIP SVE set FPSIMD get SVE for VL 2960
2475 16:59:56.159846 # ok 745 Set SVE VL 2976
2476 16:59:56.159981 # ok 746 # SKIP SVE set SVE get SVE for VL 2976
2477 16:59:56.160123 # ok 747 # SKIP SVE set SVE get FPSIMD for VL 2976
2478 16:59:56.160277 # ok 748 # SKIP SVE set FPSIMD get SVE for VL 2976
2479 16:59:56.160436 # ok 749 Set SVE VL 2992
2480 16:59:56.160594 # ok 750 # SKIP SVE set SVE get SVE for VL 2992
2481 16:59:56.160765 # ok 751 # SKIP SVE set SVE get FPSIMD for VL 2992
2482 16:59:56.160899 # ok 752 # SKIP SVE set FPSIMD get SVE for VL 2992
2483 16:59:56.161010 # ok 753 Set SVE VL 3008
2484 16:59:56.161130 # ok 754 # SKIP SVE set SVE get SVE for VL 3008
2485 16:59:56.161258 # ok 755 # SKIP SVE set SVE get FPSIMD for VL 3008
2486 16:59:56.161418 # ok 756 # SKIP SVE set FPSIMD get SVE for VL 3008
2487 16:59:56.161566 # ok 757 Set SVE VL 3024
2488 16:59:56.162518 # ok 758 # SKIP SVE set SVE get SVE for VL 3024
2489 16:59:56.162662 # ok 759 # SKIP SVE set SVE get FPSIMD for VL 3024
2490 16:59:56.162766 # ok 760 # SKIP SVE set FPSIMD get SVE for VL 3024
2491 16:59:56.162869 # ok 761 Set SVE VL 3040
2492 16:59:56.162976 # ok 762 # SKIP SVE set SVE get SVE for VL 3040
2493 16:59:56.163085 # ok 763 # SKIP SVE set SVE get FPSIMD for VL 3040
2494 16:59:56.163201 # ok 764 # SKIP SVE set FPSIMD get SVE for VL 3040
2495 16:59:56.163296 # ok 765 Set SVE VL 3056
2496 16:59:56.163407 # ok 766 # SKIP SVE set SVE get SVE for VL 3056
2497 16:59:56.163513 # ok 767 # SKIP SVE set SVE get FPSIMD for VL 3056
2498 16:59:56.163818 # ok 768 # SKIP SVE set FPSIMD get SVE for VL 3056
2499 16:59:56.163920 # ok 769 Set SVE VL 3072
2500 16:59:56.164006 # ok 770 # SKIP SVE set SVE get SVE for VL 3072
2501 16:59:56.164097 # ok 771 # SKIP SVE set SVE get FPSIMD for VL 3072
2502 16:59:56.164175 # ok 772 # SKIP SVE set FPSIMD get SVE for VL 3072
2503 16:59:56.164262 # ok 773 Set SVE VL 3088
2504 16:59:56.164356 # ok 774 # SKIP SVE set SVE get SVE for VL 3088
2505 16:59:56.164445 # ok 775 # SKIP SVE set SVE get FPSIMD for VL 3088
2506 16:59:56.164538 # ok 776 # SKIP SVE set FPSIMD get SVE for VL 3088
2507 16:59:56.164644 # ok 777 Set SVE VL 3104
2508 16:59:56.164750 # ok 778 # SKIP SVE set SVE get SVE for VL 3104
2509 16:59:56.164856 # ok 779 # SKIP SVE set SVE get FPSIMD for VL 3104
2510 16:59:56.164956 # ok 780 # SKIP SVE set FPSIMD get SVE for VL 3104
2511 16:59:56.165054 # ok 781 Set SVE VL 3120
2512 16:59:56.165145 # ok 782 # SKIP SVE set SVE get SVE for VL 3120
2513 16:59:56.165242 # ok 783 # SKIP SVE set SVE get FPSIMD for VL 3120
2514 16:59:56.165325 # ok 784 # SKIP SVE set FPSIMD get SVE for VL 3120
2515 16:59:56.165412 # ok 785 Set SVE VL 3136
2516 16:59:56.165506 # ok 786 # SKIP SVE set SVE get SVE for VL 3136
2517 16:59:56.165610 # ok 787 # SKIP SVE set SVE get FPSIMD for VL 3136
2518 16:59:56.165706 # ok 788 # SKIP SVE set FPSIMD get SVE for VL 3136
2519 16:59:56.165808 # ok 789 Set SVE VL 3152
2520 16:59:56.165926 # ok 790 # SKIP SVE set SVE get SVE for VL 3152
2521 16:59:56.166014 # ok 791 # SKIP SVE set SVE get FPSIMD for VL 3152
2522 16:59:56.166089 # ok 792 # SKIP SVE set FPSIMD get SVE for VL 3152
2523 16:59:56.166161 # ok 793 Set SVE VL 3168
2524 16:59:56.166233 # ok 794 # SKIP SVE set SVE get SVE for VL 3168
2525 16:59:56.166309 # ok 795 # SKIP SVE set SVE get FPSIMD for VL 3168
2526 16:59:56.166383 # ok 796 # SKIP SVE set FPSIMD get SVE for VL 3168
2527 16:59:56.166464 # ok 797 Set SVE VL 3184
2528 16:59:56.166547 # ok 798 # SKIP SVE set SVE get SVE for VL 3184
2529 16:59:56.166623 # ok 799 # SKIP SVE set SVE get FPSIMD for VL 3184
2530 16:59:56.166695 # ok 800 # SKIP SVE set FPSIMD get SVE for VL 3184
2531 16:59:56.166760 # ok 801 Set SVE VL 3200
2532 16:59:56.166820 # ok 802 # SKIP SVE set SVE get SVE for VL 3200
2533 16:59:56.166901 # ok 803 # SKIP SVE set SVE get FPSIMD for VL 3200
2534 16:59:56.166973 # ok 804 # SKIP SVE set FPSIMD get SVE for VL 3200
2535 16:59:56.167050 # ok 805 Set SVE VL 3216
2536 16:59:56.167155 # ok 806 # SKIP SVE set SVE get SVE for VL 3216
2537 16:59:56.167251 # ok 807 # SKIP SVE set SVE get FPSIMD for VL 3216
2538 16:59:56.167327 # ok 808 # SKIP SVE set FPSIMD get SVE for VL 3216
2539 16:59:56.167426 # ok 809 Set SVE VL 3232
2540 16:59:56.167538 # ok 810 # SKIP SVE set SVE get SVE for VL 3232
2541 16:59:56.167624 # ok 811 # SKIP SVE set SVE get FPSIMD for VL 3232
2542 16:59:56.167968 # ok 812 # SKIP SVE set FPSIMD get SVE for VL 3232
2543 16:59:56.168073 # ok 813 Set SVE VL 3248
2544 16:59:56.168157 # ok 814 # SKIP SVE set SVE get SVE for VL 3248
2545 16:59:56.168243 # ok 815 # SKIP SVE set SVE get FPSIMD for VL 3248
2546 16:59:56.168324 # ok 816 # SKIP SVE set FPSIMD get SVE for VL 3248
2547 16:59:56.168407 # ok 817 Set SVE VL 3264
2548 16:59:56.168487 # ok 818 # SKIP SVE set SVE get SVE for VL 3264
2549 16:59:56.168570 # ok 819 # SKIP SVE set SVE get FPSIMD for VL 3264
2550 16:59:56.168651 # ok 820 # SKIP SVE set FPSIMD get SVE for VL 3264
2551 16:59:56.168733 # ok 821 Set SVE VL 3280
2552 16:59:56.168817 # ok 822 # SKIP SVE set SVE get SVE for VL 3280
2553 16:59:56.168898 # ok 823 # SKIP SVE set SVE get FPSIMD for VL 3280
2554 16:59:56.168983 # ok 824 # SKIP SVE set FPSIMD get SVE for VL 3280
2555 16:59:56.169060 # ok 825 Set SVE VL 3296
2556 16:59:56.169136 # ok 826 # SKIP SVE set SVE get SVE for VL 3296
2557 16:59:56.169209 # ok 827 # SKIP SVE set SVE get FPSIMD for VL 3296
2558 16:59:56.169280 # ok 828 # SKIP SVE set FPSIMD get SVE for VL 3296
2559 16:59:56.169352 # ok 829 Set SVE VL 3312
2560 16:59:56.169423 # ok 830 # SKIP SVE set SVE get SVE for VL 3312
2561 16:59:56.169494 # ok 831 # SKIP SVE set SVE get FPSIMD for VL 3312
2562 16:59:56.169572 # ok 832 # SKIP SVE set FPSIMD get SVE for VL 3312
2563 16:59:56.169668 # ok 833 Set SVE VL 3328
2564 16:59:56.169751 # ok 834 # SKIP SVE set SVE get SVE for VL 3328
2565 16:59:56.169836 # ok 835 # SKIP SVE set SVE get FPSIMD for VL 3328
2566 16:59:56.169919 # ok 836 # SKIP SVE set FPSIMD get SVE for VL 3328
2567 16:59:56.170001 # ok 837 Set SVE VL 3344
2568 16:59:56.170083 # ok 838 # SKIP SVE set SVE get SVE for VL 3344
2569 16:59:56.170164 # ok 839 # SKIP SVE set SVE get FPSIMD for VL 3344
2570 16:59:56.170241 # ok 840 # SKIP SVE set FPSIMD get SVE for VL 3344
2571 16:59:56.170316 # ok 841 Set SVE VL 3360
2572 16:59:56.170389 # ok 842 # SKIP SVE set SVE get SVE for VL 3360
2573 16:59:56.170460 # ok 843 # SKIP SVE set SVE get FPSIMD for VL 3360
2574 16:59:56.170530 # ok 844 # SKIP SVE set FPSIMD get SVE for VL 3360
2575 16:59:56.170602 # ok 845 Set SVE VL 3376
2576 16:59:56.170674 # ok 846 # SKIP SVE set SVE get SVE for VL 3376
2577 16:59:56.170763 # ok 847 # SKIP SVE set SVE get FPSIMD for VL 3376
2578 16:59:56.170840 # ok 848 # SKIP SVE set FPSIMD get SVE for VL 3376
2579 16:59:56.170915 # ok 849 Set SVE VL 3392
2580 16:59:56.170989 # ok 850 # SKIP SVE set SVE get SVE for VL 3392
2581 16:59:56.171062 # ok 851 # SKIP SVE set SVE get FPSIMD for VL 3392
2582 16:59:56.171133 # ok 852 # SKIP SVE set FPSIMD get SVE for VL 3392
2583 16:59:56.171212 # ok 853 Set SVE VL 3408
2584 16:59:56.171287 # ok 854 # SKIP SVE set SVE get SVE for VL 3408
2585 16:59:56.176815 # ok 855 # SKIP SVE set SVE get FPSIMD for VL 3408
2586 16:59:56.176978 # ok 856 # SKIP SVE set FPSIMD get SVE for VL 3408
2587 16:59:56.177079 # ok 857 Set SVE VL 3424
2588 16:59:56.177164 # ok 858 # SKIP SVE set SVE get SVE for VL 3424
2589 16:59:56.181950 # ok 859 # SKIP SVE set SVE get FPSIMD for VL 3424
2590 16:59:56.182066 # ok 860 # SKIP SVE set FPSIMD get SVE for VL 3424
2591 16:59:56.182151 # ok 861 Set SVE VL 3440
2592 16:59:56.182236 # ok 862 # SKIP SVE set SVE get SVE for VL 3440
2593 16:59:56.182319 # ok 863 # SKIP SVE set SVE get FPSIMD for VL 3440
2594 16:59:56.182401 # ok 864 # SKIP SVE set FPSIMD get SVE for VL 3440
2595 16:59:56.182485 # ok 865 Set SVE VL 3456
2596 16:59:56.182567 # ok 866 # SKIP SVE set SVE get SVE for VL 3456
2597 16:59:56.182651 # ok 867 # SKIP SVE set SVE get FPSIMD for VL 3456
2598 16:59:56.182733 # ok 868 # SKIP SVE set FPSIMD get SVE for VL 3456
2599 16:59:56.182823 # ok 869 Set SVE VL 3472
2600 16:59:56.182909 # ok 870 # SKIP SVE set SVE get SVE for VL 3472
2601 16:59:56.182992 # ok 871 # SKIP SVE set SVE get FPSIMD for VL 3472
2602 16:59:56.183075 # ok 872 # SKIP SVE set FPSIMD get SVE for VL 3472
2603 16:59:56.183159 # ok 873 Set SVE VL 3488
2604 16:59:56.183243 # ok 874 # SKIP SVE set SVE get SVE for VL 3488
2605 16:59:56.183327 # ok 875 # SKIP SVE set SVE get FPSIMD for VL 3488
2606 16:59:56.183411 # ok 876 # SKIP SVE set FPSIMD get SVE for VL 3488
2607 16:59:56.183495 # ok 877 Set SVE VL 3504
2608 16:59:56.183579 # ok 878 # SKIP SVE set SVE get SVE for VL 3504
2609 16:59:56.183665 # ok 879 # SKIP SVE set SVE get FPSIMD for VL 3504
2610 16:59:56.183746 # ok 880 # SKIP SVE set FPSIMD get SVE for VL 3504
2611 16:59:56.183833 # ok 881 Set SVE VL 3520
2612 16:59:56.183914 # ok 882 # SKIP SVE set SVE get SVE for VL 3520
2613 16:59:56.183998 # ok 883 # SKIP SVE set SVE get FPSIMD for VL 3520
2614 16:59:56.184080 # ok 884 # SKIP SVE set FPSIMD get SVE for VL 3520
2615 16:59:56.184162 # ok 885 Set SVE VL 3536
2616 16:59:56.184245 # ok 886 # SKIP SVE set SVE get SVE for VL 3536
2617 16:59:56.184327 # ok 887 # SKIP SVE set SVE get FPSIMD for VL 3536
2618 16:59:56.184411 # ok 888 # SKIP SVE set FPSIMD get SVE for VL 3536
2619 16:59:56.184492 # ok 889 Set SVE VL 3552
2620 16:59:56.184575 # ok 890 # SKIP SVE set SVE get SVE for VL 3552
2621 16:59:56.184657 # ok 891 # SKIP SVE set SVE get FPSIMD for VL 3552
2622 16:59:56.184741 # ok 892 # SKIP SVE set FPSIMD get SVE for VL 3552
2623 16:59:56.184826 # ok 893 Set SVE VL 3568
2624 16:59:56.184909 # ok 894 # SKIP SVE set SVE get SVE for VL 3568
2625 16:59:56.187206 # ok 895 # SKIP SVE set SVE get FPSIMD for VL 3568
2626 16:59:56.187310 # ok 896 # SKIP SVE set FPSIMD get SVE for VL 3568
2627 16:59:56.187393 # ok 897 Set SVE VL 3584
2628 16:59:56.187478 # ok 898 # SKIP SVE set SVE get SVE for VL 3584
2629 16:59:56.187560 # ok 899 # SKIP SVE set SVE get FPSIMD for VL 3584
2630 16:59:56.187644 # ok 900 # SKIP SVE set FPSIMD get SVE for VL 3584
2631 16:59:56.187728 # ok 901 Set SVE VL 3600
2632 16:59:56.187810 # ok 902 # SKIP SVE set SVE get SVE for VL 3600
2633 16:59:56.187891 # ok 903 # SKIP SVE set SVE get FPSIMD for VL 3600
2634 16:59:56.187971 # ok 904 # SKIP SVE set FPSIMD get SVE for VL 3600
2635 16:59:56.188052 # ok 905 Set SVE VL 3616
2636 16:59:56.188133 # ok 906 # SKIP SVE set SVE get SVE for VL 3616
2637 16:59:56.188214 # ok 907 # SKIP SVE set SVE get FPSIMD for VL 3616
2638 16:59:56.188296 # ok 908 # SKIP SVE set FPSIMD get SVE for VL 3616
2639 16:59:56.188379 # ok 909 Set SVE VL 3632
2640 16:59:56.188459 # ok 910 # SKIP SVE set SVE get SVE for VL 3632
2641 16:59:56.188540 # ok 911 # SKIP SVE set SVE get FPSIMD for VL 3632
2642 16:59:56.188622 # ok 912 # SKIP SVE set FPSIMD get SVE for VL 3632
2643 16:59:56.188707 # ok 913 Set SVE VL 3648
2644 16:59:56.188793 # ok 914 # SKIP SVE set SVE get SVE for VL 3648
2645 16:59:56.188874 # ok 915 # SKIP SVE set SVE get FPSIMD for VL 3648
2646 16:59:56.188956 # ok 916 # SKIP SVE set FPSIMD get SVE for VL 3648
2647 16:59:56.189039 # ok 917 Set SVE VL 3664
2648 16:59:56.189120 # ok 918 # SKIP SVE set SVE get SVE for VL 3664
2649 16:59:56.189203 # ok 919 # SKIP SVE set SVE get FPSIMD for VL 3664
2650 16:59:56.189283 # ok 920 # SKIP SVE set FPSIMD get SVE for VL 3664
2651 16:59:56.189364 # ok 921 Set SVE VL 3680
2652 16:59:56.189444 # ok 922 # SKIP SVE set SVE get SVE for VL 3680
2653 16:59:56.189525 # ok 923 # SKIP SVE set SVE get FPSIMD for VL 3680
2654 16:59:56.189606 # ok 924 # SKIP SVE set FPSIMD get SVE for VL 3680
2655 16:59:56.189693 # ok 925 Set SVE VL 3696
2656 16:59:56.189776 # ok 926 # SKIP SVE set SVE get SVE for VL 3696
2657 16:59:56.189860 # ok 927 # SKIP SVE set SVE get FPSIMD for VL 3696
2658 16:59:56.189941 # ok 928 # SKIP SVE set FPSIMD get SVE for VL 3696
2659 16:59:56.190025 # ok 929 Set SVE VL 3712
2660 16:59:56.190128 # ok 930 # SKIP SVE set SVE get SVE for VL 3712
2661 16:59:56.190214 # ok 931 # SKIP SVE set SVE get FPSIMD for VL 3712
2662 16:59:56.190296 # ok 932 # SKIP SVE set FPSIMD get SVE for VL 3712
2663 16:59:56.190379 # ok 933 Set SVE VL 3728
2664 16:59:56.190458 # ok 934 # SKIP SVE set SVE get SVE for VL 3728
2665 16:59:56.190540 # ok 935 # SKIP SVE set SVE get FPSIMD for VL 3728
2666 16:59:56.190620 # ok 936 # SKIP SVE set FPSIMD get SVE for VL 3728
2667 16:59:56.190702 # ok 937 Set SVE VL 3744
2668 16:59:56.190783 # ok 938 # SKIP SVE set SVE get SVE for VL 3744
2669 16:59:56.191065 # ok 939 # SKIP SVE set SVE get FPSIMD for VL 3744
2670 16:59:56.191167 # ok 940 # SKIP SVE set FPSIMD get SVE for VL 3744
2671 16:59:56.191251 # ok 941 Set SVE VL 3760
2672 16:59:56.191332 # ok 942 # SKIP SVE set SVE get SVE for VL 3760
2673 16:59:56.191413 # ok 943 # SKIP SVE set SVE get FPSIMD for VL 3760
2674 16:59:56.191493 # ok 944 # SKIP SVE set FPSIMD get SVE for VL 3760
2675 16:59:56.191575 # ok 945 Set SVE VL 3776
2676 16:59:56.191656 # ok 946 # SKIP SVE set SVE get SVE for VL 3776
2677 16:59:56.191741 # ok 947 # SKIP SVE set SVE get FPSIMD for VL 3776
2678 16:59:56.191826 # ok 948 # SKIP SVE set FPSIMD get SVE for VL 3776
2679 16:59:56.191911 # ok 949 Set SVE VL 3792
2680 16:59:56.191995 # ok 950 # SKIP SVE set SVE get SVE for VL 3792
2681 16:59:56.192081 # ok 951 # SKIP SVE set SVE get FPSIMD for VL 3792
2682 16:59:56.192167 # ok 952 # SKIP SVE set FPSIMD get SVE for VL 3792
2683 16:59:56.192254 # ok 953 Set SVE VL 3808
2684 16:59:56.192334 # ok 954 # SKIP SVE set SVE get SVE for VL 3808
2685 16:59:56.192436 # ok 955 # SKIP SVE set SVE get FPSIMD for VL 3808
2686 16:59:56.192522 # ok 956 # SKIP SVE set FPSIMD get SVE for VL 3808
2687 16:59:56.192607 # ok 957 Set SVE VL 3824
2688 16:59:56.192689 # ok 958 # SKIP SVE set SVE get SVE for VL 3824
2689 16:59:56.192771 # ok 959 # SKIP SVE set SVE get FPSIMD for VL 3824
2690 16:59:56.192854 # ok 960 # SKIP SVE set FPSIMD get SVE for VL 3824
2691 16:59:56.192937 # ok 961 Set SVE VL 3840
2692 16:59:56.193019 # ok 962 # SKIP SVE set SVE get SVE for VL 3840
2693 16:59:56.193101 # ok 963 # SKIP SVE set SVE get FPSIMD for VL 3840
2694 16:59:56.193184 # ok 964 # SKIP SVE set FPSIMD get SVE for VL 3840
2695 16:59:56.193270 # ok 965 Set SVE VL 3856
2696 16:59:56.193374 # ok 966 # SKIP SVE set SVE get SVE for VL 3856
2697 16:59:56.193461 # ok 967 # SKIP SVE set SVE get FPSIMD for VL 3856
2698 16:59:56.193545 # ok 968 # SKIP SVE set FPSIMD get SVE for VL 3856
2699 16:59:56.193628 # ok 969 Set SVE VL 3872
2700 16:59:56.193722 # ok 970 # SKIP SVE set SVE get SVE for VL 3872
2701 16:59:56.193809 # ok 971 # SKIP SVE set SVE get FPSIMD for VL 3872
2702 16:59:56.193894 # ok 972 # SKIP SVE set FPSIMD get SVE for VL 3872
2703 16:59:56.193978 # ok 973 Set SVE VL 3888
2704 16:59:56.194078 # ok 974 # SKIP SVE set SVE get SVE for VL 3888
2705 16:59:56.194168 # ok 975 # SKIP SVE set SVE get FPSIMD for VL 3888
2706 16:59:56.194255 # ok 976 # SKIP SVE set FPSIMD get SVE for VL 3888
2707 16:59:56.194340 # ok 977 Set SVE VL 3904
2708 16:59:56.194439 # ok 978 # SKIP SVE set SVE get SVE for VL 3904
2709 16:59:56.194524 # ok 979 # SKIP SVE set SVE get FPSIMD for VL 3904
2710 16:59:56.194609 # ok 980 # SKIP SVE set FPSIMD get SVE for VL 3904
2711 16:59:56.194706 # ok 981 Set SVE VL 3920
2712 16:59:56.194992 # ok 982 # SKIP SVE set SVE get SVE for VL 3920
2713 16:59:56.195091 # ok 983 # SKIP SVE set SVE get FPSIMD for VL 3920
2714 16:59:56.195174 # ok 984 # SKIP SVE set FPSIMD get SVE for VL 3920
2715 16:59:56.195271 # ok 985 Set SVE VL 3936
2716 16:59:56.195357 # ok 986 # SKIP SVE set SVE get SVE for VL 3936
2717 16:59:56.195458 # ok 987 # SKIP SVE set SVE get FPSIMD for VL 3936
2718 16:59:56.195545 # ok 988 # SKIP SVE set FPSIMD get SVE for VL 3936
2719 16:59:56.195644 # ok 989 Set SVE VL 3952
2720 16:59:56.195744 # ok 990 # SKIP SVE set SVE get SVE for VL 3952
2721 16:59:56.195842 # ok 991 # SKIP SVE set SVE get FPSIMD for VL 3952
2722 16:59:56.195951 # ok 992 # SKIP SVE set FPSIMD get SVE for VL 3952
2723 16:59:56.196050 # ok 993 Set SVE VL 3968
2724 16:59:56.196343 # ok 994 # SKIP SVE set SVE get SVE for VL 3968
2725 16:59:56.196458 # ok 995 # SKIP SVE set SVE get FPSIMD for VL 3968
2726 16:59:56.196542 # ok 996 # SKIP SVE set FPSIMD get SVE for VL 3968
2727 16:59:56.196638 # ok 997 Set SVE VL 3984
2728 16:59:56.196720 # ok 998 # SKIP SVE set SVE get SVE for VL 3984
2729 16:59:56.196813 # ok 999 # SKIP SVE set SVE get FPSIMD for VL 3984
2730 16:59:56.197116 # ok 1000 # SKIP SVE set FPSIMD get SVE for VL 3984
2731 16:59:56.197233 # ok 1001 Set SVE VL 4000
2732 16:59:56.197520 # ok 1002 # SKIP SVE set SVE get SVE for VL 4000
2733 16:59:56.197620 # ok 1003 # SKIP SVE set SVE get FPSIMD for VL 4000
2734 16:59:56.197729 # ok 1004 # SKIP SVE set FPSIMD get SVE for VL 4000
2735 16:59:56.197818 # ok 1005 Set SVE VL 4016
2736 16:59:56.197919 # ok 1006 # SKIP SVE set SVE get SVE for VL 4016
2737 16:59:56.198009 # ok 1007 # SKIP SVE set SVE get FPSIMD for VL 4016
2738 16:59:56.198106 # ok 1008 # SKIP SVE set FPSIMD get SVE for VL 4016
2739 16:59:56.198194 # ok 1009 Set SVE VL 4032
2740 16:59:56.198292 # ok 1010 # SKIP SVE set SVE get SVE for VL 4032
2741 16:59:56.198392 # ok 1011 # SKIP SVE set SVE get FPSIMD for VL 4032
2742 16:59:56.198494 # ok 1012 # SKIP SVE set FPSIMD get SVE for VL 4032
2743 16:59:56.198593 # ok 1013 Set SVE VL 4048
2744 16:59:56.198693 # ok 1014 # SKIP SVE set SVE get SVE for VL 4048
2745 16:59:56.198988 # ok 1015 # SKIP SVE set SVE get FPSIMD for VL 4048
2746 16:59:56.199085 # ok 1016 # SKIP SVE set FPSIMD get SVE for VL 4048
2747 16:59:56.199184 # ok 1017 Set SVE VL 4064
2748 16:59:56.199268 # ok 1018 # SKIP SVE set SVE get SVE for VL 4064
2749 16:59:56.199363 # ok 1019 # SKIP SVE set SVE get FPSIMD for VL 4064
2750 16:59:56.199461 # ok 1020 # SKIP SVE set FPSIMD get SVE for VL 4064
2751 16:59:56.199560 # ok 1021 Set SVE VL 4080
2752 16:59:56.199870 # ok 1022 # SKIP SVE set SVE get SVE for VL 4080
2753 16:59:56.199966 # ok 1023 # SKIP SVE set SVE get FPSIMD for VL 4080
2754 16:59:56.200060 # ok 1024 # SKIP SVE set FPSIMD get SVE for VL 4080
2755 16:59:56.200130 # ok 1025 Set SVE VL 4096
2756 16:59:56.200212 # ok 1026 # SKIP SVE set SVE get SVE for VL 4096
2757 16:59:56.200288 # ok 1027 # SKIP SVE set SVE get FPSIMD for VL 4096
2758 16:59:56.200367 # ok 1028 # SKIP SVE set FPSIMD get SVE for VL 4096
2759 16:59:56.200454 # ok 1029 Set SVE VL 4112
2760 16:59:56.200559 # ok 1030 # SKIP SVE set SVE get SVE for VL 4112
2761 16:59:56.200667 # ok 1031 # SKIP SVE set SVE get FPSIMD for VL 4112
2762 16:59:56.200949 # ok 1032 # SKIP SVE set FPSIMD get SVE for VL 4112
2763 16:59:56.201043 # ok 1033 Set SVE VL 4128
2764 16:59:56.201139 # ok 1034 # SKIP SVE set SVE get SVE for VL 4128
2765 16:59:56.201244 # ok 1035 # SKIP SVE set SVE get FPSIMD for VL 4128
2766 16:59:56.201332 # ok 1036 # SKIP SVE set FPSIMD get SVE for VL 4128
2767 16:59:56.201428 # ok 1037 Set SVE VL 4144
2768 16:59:56.201546 # ok 1038 # SKIP SVE set SVE get SVE for VL 4144
2769 16:59:56.201634 # ok 1039 # SKIP SVE set SVE get FPSIMD for VL 4144
2770 16:59:56.201731 # ok 1040 # SKIP SVE set FPSIMD get SVE for VL 4144
2771 16:59:56.209343 # ok 1041 Set SVE VL 4160
2772 16:59:56.209533 # ok 1042 # SKIP SVE set SVE get SVE for VL 4160
2773 16:59:56.209637 # ok 1043 # SKIP SVE set SVE get FPSIMD for VL 4160
2774 16:59:56.209731 # ok 1044 # SKIP SVE set FPSIMD get SVE for VL 4160
2775 16:59:56.209809 # ok 1045 Set SVE VL 4176
2776 16:59:56.210258 # ok 1046 # SKIP SVE set SVE get SVE for VL 4176
2777 16:59:56.210703 # ok 1047 # SKIP SVE set SVE get FPSIMD for VL 4176
2778 16:59:56.210843 # ok 1048 # SKIP SVE set FPSIMD get SVE for VL 4176
2779 16:59:56.210965 # ok 1049 Set SVE VL 4192
2780 16:59:56.211081 # ok 1050 # SKIP SVE set SVE get SVE for VL 4192
2781 16:59:56.211188 # ok 1051 # SKIP SVE set SVE get FPSIMD for VL 4192
2782 16:59:56.211311 # ok 1052 # SKIP SVE set FPSIMD get SVE for VL 4192
2783 16:59:56.211434 # ok 1053 Set SVE VL 4208
2784 16:59:56.211556 # ok 1054 # SKIP SVE set SVE get SVE for VL 4208
2785 16:59:56.211694 # ok 1055 # SKIP SVE set SVE get FPSIMD for VL 4208
2786 16:59:56.211849 # ok 1056 # SKIP SVE set FPSIMD get SVE for VL 4208
2787 16:59:56.212003 # ok 1057 Set SVE VL 4224
2788 16:59:56.212166 # ok 1058 # SKIP SVE set SVE get SVE for VL 4224
2789 16:59:56.212324 # ok 1059 # SKIP SVE set SVE get FPSIMD for VL 4224
2790 16:59:56.212458 # ok 1060 # SKIP SVE set FPSIMD get SVE for VL 4224
2791 16:59:56.212574 # ok 1061 Set SVE VL 4240
2792 16:59:56.212676 # ok 1062 # SKIP SVE set SVE get SVE for VL 4240
2793 16:59:56.212796 # ok 1063 # SKIP SVE set SVE get FPSIMD for VL 4240
2794 16:59:56.212915 # ok 1064 # SKIP SVE set FPSIMD get SVE for VL 4240
2795 16:59:56.213030 # ok 1065 Set SVE VL 4256
2796 16:59:56.213169 # ok 1066 # SKIP SVE set SVE get SVE for VL 4256
2797 16:59:56.213279 # ok 1067 # SKIP SVE set SVE get FPSIMD for VL 4256
2798 16:59:56.213395 # ok 1068 # SKIP SVE set FPSIMD get SVE for VL 4256
2799 16:59:56.213508 # ok 1069 Set SVE VL 4272
2800 16:59:56.213656 # ok 1070 # SKIP SVE set SVE get SVE for VL 4272
2801 16:59:56.213783 # ok 1071 # SKIP SVE set SVE get FPSIMD for VL 4272
2802 16:59:56.213934 # ok 1072 # SKIP SVE set FPSIMD get SVE for VL 4272
2803 16:59:56.214086 # ok 1073 Set SVE VL 4288
2804 16:59:56.214228 # ok 1074 # SKIP SVE set SVE get SVE for VL 4288
2805 16:59:56.214376 # ok 1075 # SKIP SVE set SVE get FPSIMD for VL 4288
2806 16:59:56.214494 # ok 1076 # SKIP SVE set FPSIMD get SVE for VL 4288
2807 16:59:56.214623 # ok 1077 Set SVE VL 4304
2808 16:59:56.214741 # ok 1078 # SKIP SVE set SVE get SVE for VL 4304
2809 16:59:56.214826 # ok 1079 # SKIP SVE set SVE get FPSIMD for VL 4304
2810 16:59:56.214907 # ok 1080 # SKIP SVE set FPSIMD get SVE for VL 4304
2811 16:59:56.215007 # ok 1081 Set SVE VL 4320
2812 16:59:56.215097 # ok 1082 # SKIP SVE set SVE get SVE for VL 4320
2813 16:59:56.215199 # ok 1083 # SKIP SVE set SVE get FPSIMD for VL 4320
2814 16:59:56.215305 # ok 1084 # SKIP SVE set FPSIMD get SVE for VL 4320
2815 16:59:56.215406 # ok 1085 Set SVE VL 4336
2816 16:59:56.215494 # ok 1086 # SKIP SVE set SVE get SVE for VL 4336
2817 16:59:56.215571 # ok 1087 # SKIP SVE set SVE get FPSIMD for VL 4336
2818 16:59:56.215642 # ok 1088 # SKIP SVE set FPSIMD get SVE for VL 4336
2819 16:59:56.215709 # ok 1089 Set SVE VL 4352
2820 16:59:56.215992 # ok 1090 # SKIP SVE set SVE get SVE for VL 4352
2821 16:59:56.216088 # ok 1091 # SKIP SVE set SVE get FPSIMD for VL 4352
2822 16:59:56.216157 # ok 1092 # SKIP SVE set FPSIMD get SVE for VL 4352
2823 16:59:56.216232 # ok 1093 Set SVE VL 4368
2824 16:59:56.216306 # ok 1094 # SKIP SVE set SVE get SVE for VL 4368
2825 16:59:56.216378 # ok 1095 # SKIP SVE set SVE get FPSIMD for VL 4368
2826 16:59:56.216689 # ok 1096 # SKIP SVE set FPSIMD get SVE for VL 4368
2827 16:59:56.216920 # ok 1097 Set SVE VL 4384
2828 16:59:56.217129 # ok 1098 # SKIP SVE set SVE get SVE for VL 4384
2829 16:59:56.217353 # ok 1099 # SKIP SVE set SVE get FPSIMD for VL 4384
2830 16:59:56.217557 # ok 1100 # SKIP SVE set FPSIMD get SVE for VL 4384
2831 16:59:56.217748 # ok 1101 Set SVE VL 4400
2832 16:59:56.217904 # ok 1102 # SKIP SVE set SVE get SVE for VL 4400
2833 16:59:56.218090 # ok 1103 # SKIP SVE set SVE get FPSIMD for VL 4400
2834 16:59:56.218262 # ok 1104 # SKIP SVE set FPSIMD get SVE for VL 4400
2835 16:59:56.218426 # ok 1105 Set SVE VL 4416
2836 16:59:56.218588 # ok 1106 # SKIP SVE set SVE get SVE for VL 4416
2837 16:59:56.218741 # ok 1107 # SKIP SVE set SVE get FPSIMD for VL 4416
2838 16:59:56.218862 # ok 1108 # SKIP SVE set FPSIMD get SVE for VL 4416
2839 16:59:56.218991 # ok 1109 Set SVE VL 4432
2840 16:59:56.219112 # ok 1110 # SKIP SVE set SVE get SVE for VL 4432
2841 16:59:56.219218 # ok 1111 # SKIP SVE set SVE get FPSIMD for VL 4432
2842 16:59:56.219338 # ok 1112 # SKIP SVE set FPSIMD get SVE for VL 4432
2843 16:59:56.219483 # ok 1113 Set SVE VL 4448
2844 16:59:56.219611 # ok 1114 # SKIP SVE set SVE get SVE for VL 4448
2845 16:59:56.219732 # ok 1115 # SKIP SVE set SVE get FPSIMD for VL 4448
2846 16:59:56.219851 # ok 1116 # SKIP SVE set FPSIMD get SVE for VL 4448
2847 16:59:56.219972 # ok 1117 Set SVE VL 4464
2848 16:59:56.220090 # ok 1118 # SKIP SVE set SVE get SVE for VL 4464
2849 16:59:56.220236 # ok 1119 # SKIP SVE set SVE get FPSIMD for VL 4464
2850 16:59:56.220389 # ok 1120 # SKIP SVE set FPSIMD get SVE for VL 4464
2851 16:59:56.220551 # ok 1121 Set SVE VL 4480
2852 16:59:56.220711 # ok 1122 # SKIP SVE set SVE get SVE for VL 4480
2853 16:59:56.220872 # ok 1123 # SKIP SVE set SVE get FPSIMD for VL 4480
2854 16:59:56.221025 # ok 1124 # SKIP SVE set FPSIMD get SVE for VL 4480
2855 16:59:56.221182 # ok 1125 Set SVE VL 4496
2856 16:59:56.221369 # ok 1126 # SKIP SVE set SVE get SVE for VL 4496
2857 16:59:56.221525 # ok 1127 # SKIP SVE set SVE get FPSIMD for VL 4496
2858 16:59:56.221669 # ok 1128 # SKIP SVE set FPSIMD get SVE for VL 4496
2859 16:59:56.221799 # ok 1129 Set SVE VL 4512
2860 16:59:56.221943 # ok 1130 # SKIP SVE set SVE get SVE for VL 4512
2861 16:59:56.222077 # ok 1131 # SKIP SVE set SVE get FPSIMD for VL 4512
2862 16:59:56.222207 # ok 1132 # SKIP SVE set FPSIMD get SVE for VL 4512
2863 16:59:56.222340 # ok 1133 Set SVE VL 4528
2864 16:59:56.222490 # ok 1134 # SKIP SVE set SVE get SVE for VL 4528
2865 16:59:56.222616 # ok 1135 # SKIP SVE set SVE get FPSIMD for VL 4528
2866 16:59:56.222749 # ok 1136 # SKIP SVE set FPSIMD get SVE for VL 4528
2867 16:59:56.222836 # ok 1137 Set SVE VL 4544
2868 16:59:56.222932 # ok 1138 # SKIP SVE set SVE get SVE for VL 4544
2869 16:59:56.223210 # ok 1139 # SKIP SVE set SVE get FPSIMD for VL 4544
2870 16:59:56.223309 # ok 1140 # SKIP SVE set FPSIMD get SVE for VL 4544
2871 16:59:56.223394 # ok 1141 Set SVE VL 4560
2872 16:59:56.223476 # ok 1142 # SKIP SVE set SVE get SVE for VL 4560
2873 16:59:56.223557 # ok 1143 # SKIP SVE set SVE get FPSIMD for VL 4560
2874 16:59:56.223637 # ok 1144 # SKIP SVE set FPSIMD get SVE for VL 4560
2875 16:59:56.223720 # ok 1145 Set SVE VL 4576
2876 16:59:56.223801 # ok 1146 # SKIP SVE set SVE get SVE for VL 4576
2877 16:59:56.223883 # ok 1147 # SKIP SVE set SVE get FPSIMD for VL 4576
2878 16:59:56.223967 # ok 1148 # SKIP SVE set FPSIMD get SVE for VL 4576
2879 16:59:56.224049 # ok 1149 Set SVE VL 4592
2880 16:59:56.224133 # ok 1150 # SKIP SVE set SVE get SVE for VL 4592
2881 16:59:56.224216 # ok 1151 # SKIP SVE set SVE get FPSIMD for VL 4592
2882 16:59:56.224300 # ok 1152 # SKIP SVE set FPSIMD get SVE for VL 4592
2883 16:59:56.224385 # ok 1153 Set SVE VL 4608
2884 16:59:56.224470 # ok 1154 # SKIP SVE set SVE get SVE for VL 4608
2885 16:59:56.224554 # ok 1155 # SKIP SVE set SVE get FPSIMD for VL 4608
2886 16:59:56.224639 # ok 1156 # SKIP SVE set FPSIMD get SVE for VL 4608
2887 16:59:56.224723 # ok 1157 Set SVE VL 4624
2888 16:59:56.224809 # ok 1158 # SKIP SVE set SVE get SVE for VL 4624
2889 16:59:56.224899 # ok 1159 # SKIP SVE set SVE get FPSIMD for VL 4624
2890 16:59:56.225003 # ok 1160 # SKIP SVE set FPSIMD get SVE for VL 4624
2891 16:59:56.225090 # ok 1161 Set SVE VL 4640
2892 16:59:56.225174 # ok 1162 # SKIP SVE set SVE get SVE for VL 4640
2893 16:59:56.225255 # ok 1163 # SKIP SVE set SVE get FPSIMD for VL 4640
2894 16:59:56.225338 # ok 1164 # SKIP SVE set FPSIMD get SVE for VL 4640
2895 16:59:56.225420 # ok 1165 Set SVE VL 4656
2896 16:59:56.225502 # ok 1166 # SKIP SVE set SVE get SVE for VL 4656
2897 16:59:56.225592 # ok 1167 # SKIP SVE set SVE get FPSIMD for VL 4656
2898 16:59:56.225688 # ok 1168 # SKIP SVE set FPSIMD get SVE for VL 4656
2899 16:59:56.225775 # ok 1169 Set SVE VL 4672
2900 16:59:56.225856 # ok 1170 # SKIP SVE set SVE get SVE for VL 4672
2901 16:59:56.225939 # ok 1171 # SKIP SVE set SVE get FPSIMD for VL 4672
2902 16:59:56.226021 # ok 1172 # SKIP SVE set FPSIMD get SVE for VL 4672
2903 16:59:56.226105 # ok 1173 Set SVE VL 4688
2904 16:59:56.226206 # ok 1174 # SKIP SVE set SVE get SVE for VL 4688
2905 16:59:56.226294 # ok 1175 # SKIP SVE set SVE get FPSIMD for VL 4688
2906 16:59:56.226375 # ok 1176 # SKIP SVE set FPSIMD get SVE for VL 4688
2907 16:59:56.226459 # ok 1177 Set SVE VL 4704
2908 16:59:56.226540 # ok 1178 # SKIP SVE set SVE get SVE for VL 4704
2909 16:59:56.226622 # ok 1179 # SKIP SVE set SVE get FPSIMD for VL 4704
2910 16:59:56.226705 # ok 1180 # SKIP SVE set FPSIMD get SVE for VL 4704
2911 16:59:56.226803 # ok 1181 Set SVE VL 4720
2912 16:59:56.227088 # ok 1182 # SKIP SVE set SVE get SVE for VL 4720
2913 16:59:56.227187 # ok 1183 # SKIP SVE set SVE get FPSIMD for VL 4720
2914 16:59:56.227270 # ok 1184 # SKIP SVE set FPSIMD get SVE for VL 4720
2915 16:59:56.227352 # ok 1185 Set SVE VL 4736
2916 16:59:56.227432 # ok 1186 # SKIP SVE set SVE get SVE for VL 4736
2917 16:59:56.227513 # ok 1187 # SKIP SVE set SVE get FPSIMD for VL 4736
2918 16:59:56.227609 # ok 1188 # SKIP SVE set FPSIMD get SVE for VL 4736
2919 16:59:56.227694 # ok 1189 Set SVE VL 4752
2920 16:59:56.227776 # ok 1190 # SKIP SVE set SVE get SVE for VL 4752
2921 16:59:56.227855 # ok 1191 # SKIP SVE set SVE get FPSIMD for VL 4752
2922 16:59:56.227953 # ok 1192 # SKIP SVE set FPSIMD get SVE for VL 4752
2923 16:59:56.228041 # ok 1193 Set SVE VL 4768
2924 16:59:56.228138 # ok 1194 # SKIP SVE set SVE get SVE for VL 4768
2925 16:59:56.228235 # ok 1195 # SKIP SVE set SVE get FPSIMD for VL 4768
2926 16:59:56.228332 # ok 1196 # SKIP SVE set FPSIMD get SVE for VL 4768
2927 16:59:56.228417 # ok 1197 Set SVE VL 4784
2928 16:59:56.228532 # ok 1198 # SKIP SVE set SVE get SVE for VL 4784
2929 16:59:56.228835 # ok 1199 # SKIP SVE set SVE get FPSIMD for VL 4784
2930 16:59:56.228937 # ok 1200 # SKIP SVE set FPSIMD get SVE for VL 4784
2931 16:59:56.229036 # ok 1201 Set SVE VL 4800
2932 16:59:56.229178 # ok 1202 # SKIP SVE set SVE get SVE for VL 4800
2933 16:59:56.229290 # ok 1203 # SKIP SVE set SVE get FPSIMD for VL 4800
2934 16:59:56.229379 # ok 1204 # SKIP SVE set FPSIMD get SVE for VL 4800
2935 16:59:56.229477 # ok 1205 Set SVE VL 4816
2936 16:59:56.229577 # ok 1206 # SKIP SVE set SVE get SVE for VL 4816
2937 16:59:56.229937 # ok 1207 # SKIP SVE set SVE get FPSIMD for VL 4816
2938 16:59:56.230222 # ok 1208 # SKIP SVE set FPSIMD get SVE for VL 4816
2939 16:59:56.230405 # ok 1209 Set SVE VL 4832
2940 16:59:56.230567 # ok 1210 # SKIP SVE set SVE get SVE for VL 4832
2941 16:59:56.230727 # ok 1211 # SKIP SVE set SVE get FPSIMD for VL 4832
2942 16:59:56.230886 # ok 1212 # SKIP SVE set FPSIMD get SVE for VL 4832
2943 16:59:56.231010 # ok 1213 Set SVE VL 4848
2944 16:59:56.231132 # ok 1214 # SKIP SVE set SVE get SVE for VL 4848
2945 16:59:56.231252 # ok 1215 # SKIP SVE set SVE get FPSIMD for VL 4848
2946 16:59:56.231350 # ok 1216 # SKIP SVE set FPSIMD get SVE for VL 4848
2947 16:59:56.231439 # ok 1217 Set SVE VL 4864
2948 16:59:56.231523 # ok 1218 # SKIP SVE set SVE get SVE for VL 4864
2949 16:59:56.231627 # ok 1219 # SKIP SVE set SVE get FPSIMD for VL 4864
2950 16:59:56.231718 # ok 1220 # SKIP SVE set FPSIMD get SVE for VL 4864
2951 16:59:56.231804 # ok 1221 Set SVE VL 4880
2952 16:59:56.231890 # ok 1222 # SKIP SVE set SVE get SVE for VL 4880
2953 16:59:56.231976 # ok 1223 # SKIP SVE set SVE get FPSIMD for VL 4880
2954 16:59:56.240148 # ok 1224 # SKIP SVE set FPSIMD get SVE for VL 4880
2955 16:59:56.240598 # ok 1225 Set SVE VL 4896
2956 16:59:56.240797 # ok 1226 # SKIP SVE set SVE get SVE for VL 4896
2957 16:59:56.240967 # ok 1227 # SKIP SVE set SVE get FPSIMD for VL 4896
2958 16:59:56.241142 # ok 1228 # SKIP SVE set FPSIMD get SVE for VL 4896
2959 16:59:56.241286 # ok 1229 Set SVE VL 4912
2960 16:59:56.241415 # ok 1230 # SKIP SVE set SVE get SVE for VL 4912
2961 16:59:56.241596 # ok 1231 # SKIP SVE set SVE get FPSIMD for VL 4912
2962 16:59:56.241745 # ok 1232 # SKIP SVE set FPSIMD get SVE for VL 4912
2963 16:59:56.241867 # ok 1233 Set SVE VL 4928
2964 16:59:56.241982 # ok 1234 # SKIP SVE set SVE get SVE for VL 4928
2965 16:59:56.242097 # ok 1235 # SKIP SVE set SVE get FPSIMD for VL 4928
2966 16:59:56.242212 # ok 1236 # SKIP SVE set FPSIMD get SVE for VL 4928
2967 16:59:56.242326 # ok 1237 Set SVE VL 4944
2968 16:59:56.242440 # ok 1238 # SKIP SVE set SVE get SVE for VL 4944
2969 16:59:56.242570 # ok 1239 # SKIP SVE set SVE get FPSIMD for VL 4944
2970 16:59:56.242796 # ok 1240 # SKIP SVE set FPSIMD get SVE for VL 4944
2971 16:59:56.242988 # ok 1241 Set SVE VL 4960
2972 16:59:56.243183 # ok 1242 # SKIP SVE set SVE get SVE for VL 4960
2973 16:59:56.243385 # ok 1243 # SKIP SVE set SVE get FPSIMD for VL 4960
2974 16:59:56.243551 # ok 1244 # SKIP SVE set FPSIMD get SVE for VL 4960
2975 16:59:56.243767 # ok 1245 Set SVE VL 4976
2976 16:59:56.243953 # ok 1246 # SKIP SVE set SVE get SVE for VL 4976
2977 16:59:56.244140 # ok 1247 # SKIP SVE set SVE get FPSIMD for VL 4976
2978 16:59:56.244291 # ok 1248 # SKIP SVE set FPSIMD get SVE for VL 4976
2979 16:59:56.244466 # ok 1249 Set SVE VL 4992
2980 16:59:56.244657 # ok 1250 # SKIP SVE set SVE get SVE for VL 4992
2981 16:59:56.244846 # ok 1251 # SKIP SVE set SVE get FPSIMD for VL 4992
2982 16:59:56.245012 # ok 1252 # SKIP SVE set FPSIMD get SVE for VL 4992
2983 16:59:56.245201 # ok 1253 Set SVE VL 5008
2984 16:59:56.245360 # ok 1254 # SKIP SVE set SVE get SVE for VL 5008
2985 16:59:56.245542 # ok 1255 # SKIP SVE set SVE get FPSIMD for VL 5008
2986 16:59:56.245706 # ok 1256 # SKIP SVE set FPSIMD get SVE for VL 5008
2987 16:59:56.245824 # ok 1257 Set SVE VL 5024
2988 16:59:56.245939 # ok 1258 # SKIP SVE set SVE get SVE for VL 5024
2989 16:59:56.246079 # ok 1259 # SKIP SVE set SVE get FPSIMD for VL 5024
2990 16:59:56.246199 # ok 1260 # SKIP SVE set FPSIMD get SVE for VL 5024
2991 16:59:56.246334 # ok 1261 Set SVE VL 5040
2992 16:59:56.246497 # ok 1262 # SKIP SVE set SVE get SVE for VL 5040
2993 16:59:56.246661 # ok 1263 # SKIP SVE set SVE get FPSIMD for VL 5040
2994 16:59:56.246834 # ok 1264 # SKIP SVE set FPSIMD get SVE for VL 5040
2995 16:59:56.246983 # ok 1265 Set SVE VL 5056
2996 16:59:56.247178 # ok 1266 # SKIP SVE set SVE get SVE for VL 5056
2997 16:59:56.247361 # ok 1267 # SKIP SVE set SVE get FPSIMD for VL 5056
2998 16:59:56.247802 # ok 1268 # SKIP SVE set FPSIMD get SVE for VL 5056
2999 16:59:56.247998 # ok 1269 Set SVE VL 5072
3000 16:59:56.248160 # ok 1270 # SKIP SVE set SVE get SVE for VL 5072
3001 16:59:56.248312 # ok 1271 # SKIP SVE set SVE get FPSIMD for VL 5072
3002 16:59:56.248474 # ok 1272 # SKIP SVE set FPSIMD get SVE for VL 5072
3003 16:59:56.248604 # ok 1273 Set SVE VL 5088
3004 16:59:56.248780 # ok 1274 # SKIP SVE set SVE get SVE for VL 5088
3005 16:59:56.248937 # ok 1275 # SKIP SVE set SVE get FPSIMD for VL 5088
3006 16:59:56.249086 # ok 1276 # SKIP SVE set FPSIMD get SVE for VL 5088
3007 16:59:56.249239 # ok 1277 Set SVE VL 5104
3008 16:59:56.249396 # ok 1278 # SKIP SVE set SVE get SVE for VL 5104
3009 16:59:56.249551 # ok 1279 # SKIP SVE set SVE get FPSIMD for VL 5104
3010 16:59:56.249694 # ok 1280 # SKIP SVE set FPSIMD get SVE for VL 5104
3011 16:59:56.249835 # ok 1281 Set SVE VL 5120
3012 16:59:56.250032 # ok 1282 # SKIP SVE set SVE get SVE for VL 5120
3013 16:59:56.250197 # ok 1283 # SKIP SVE set SVE get FPSIMD for VL 5120
3014 16:59:56.250359 # ok 1284 # SKIP SVE set FPSIMD get SVE for VL 5120
3015 16:59:56.250522 # ok 1285 Set SVE VL 5136
3016 16:59:56.250682 # ok 1286 # SKIP SVE set SVE get SVE for VL 5136
3017 16:59:56.250837 # ok 1287 # SKIP SVE set SVE get FPSIMD for VL 5136
3018 16:59:56.250994 # ok 1288 # SKIP SVE set FPSIMD get SVE for VL 5136
3019 16:59:56.251150 # ok 1289 Set SVE VL 5152
3020 16:59:56.251306 # ok 1290 # SKIP SVE set SVE get SVE for VL 5152
3021 16:59:56.251463 # ok 1291 # SKIP SVE set SVE get FPSIMD for VL 5152
3022 16:59:56.251611 # ok 1292 # SKIP SVE set FPSIMD get SVE for VL 5152
3023 16:59:56.251764 # ok 1293 Set SVE VL 5168
3024 16:59:56.251913 # ok 1294 # SKIP SVE set SVE get SVE for VL 5168
3025 16:59:56.252071 # ok 1295 # SKIP SVE set SVE get FPSIMD for VL 5168
3026 16:59:56.252231 # ok 1296 # SKIP SVE set FPSIMD get SVE for VL 5168
3027 16:59:56.252378 # ok 1297 Set SVE VL 5184
3028 16:59:56.252534 # ok 1298 # SKIP SVE set SVE get SVE for VL 5184
3029 16:59:56.252736 # ok 1299 # SKIP SVE set SVE get FPSIMD for VL 5184
3030 16:59:56.252927 # ok 1300 # SKIP SVE set FPSIMD get SVE for VL 5184
3031 16:59:56.253097 # ok 1301 Set SVE VL 5200
3032 16:59:56.253291 # ok 1302 # SKIP SVE set SVE get SVE for VL 5200
3033 16:59:56.253448 # ok 1303 # SKIP SVE set SVE get FPSIMD for VL 5200
3034 16:59:56.253603 # ok 1304 # SKIP SVE set FPSIMD get SVE for VL 5200
3035 16:59:56.253758 # ok 1305 Set SVE VL 5216
3036 16:59:56.253919 # ok 1306 # SKIP SVE set SVE get SVE for VL 5216
3037 16:59:56.254082 # ok 1307 # SKIP SVE set SVE get FPSIMD for VL 5216
3038 16:59:56.254219 # ok 1308 # SKIP SVE set FPSIMD get SVE for VL 5216
3039 16:59:56.254373 # ok 1309 Set SVE VL 5232
3040 16:59:56.254531 # ok 1310 # SKIP SVE set SVE get SVE for VL 5232
3041 16:59:56.254900 # ok 1311 # SKIP SVE set SVE get FPSIMD for VL 5232
3042 16:59:56.255087 # ok 1312 # SKIP SVE set FPSIMD get SVE for VL 5232
3043 16:59:56.255255 # ok 1313 Set SVE VL 5248
3044 16:59:56.255451 # ok 1314 # SKIP SVE set SVE get SVE for VL 5248
3045 16:59:56.255634 # ok 1315 # SKIP SVE set SVE get FPSIMD for VL 5248
3046 16:59:56.255790 # ok 1316 # SKIP SVE set FPSIMD get SVE for VL 5248
3047 16:59:56.255907 # ok 1317 Set SVE VL 5264
3048 16:59:56.256022 # ok 1318 # SKIP SVE set SVE get SVE for VL 5264
3049 16:59:56.256132 # ok 1319 # SKIP SVE set SVE get FPSIMD for VL 5264
3050 16:59:56.256237 # ok 1320 # SKIP SVE set FPSIMD get SVE for VL 5264
3051 16:59:56.256344 # ok 1321 Set SVE VL 5280
3052 16:59:56.256452 # ok 1322 # SKIP SVE set SVE get SVE for VL 5280
3053 16:59:56.256607 # ok 1323 # SKIP SVE set SVE get FPSIMD for VL 5280
3054 16:59:56.256729 # ok 1324 # SKIP SVE set FPSIMD get SVE for VL 5280
3055 16:59:56.256874 # ok 1325 Set SVE VL 5296
3056 16:59:56.257009 # ok 1326 # SKIP SVE set SVE get SVE for VL 5296
3057 16:59:56.257143 # ok 1327 # SKIP SVE set SVE get FPSIMD for VL 5296
3058 16:59:56.257280 # ok 1328 # SKIP SVE set FPSIMD get SVE for VL 5296
3059 16:59:56.257396 # ok 1329 Set SVE VL 5312
3060 16:59:56.257517 # ok 1330 # SKIP SVE set SVE get SVE for VL 5312
3061 16:59:56.257631 # ok 1331 # SKIP SVE set SVE get FPSIMD for VL 5312
3062 16:59:56.257744 # ok 1332 # SKIP SVE set FPSIMD get SVE for VL 5312
3063 16:59:56.257859 # ok 1333 Set SVE VL 5328
3064 16:59:56.257972 # ok 1334 # SKIP SVE set SVE get SVE for VL 5328
3065 16:59:56.258088 # ok 1335 # SKIP SVE set SVE get FPSIMD for VL 5328
3066 16:59:56.258203 # ok 1336 # SKIP SVE set FPSIMD get SVE for VL 5328
3067 16:59:56.258312 # ok 1337 Set SVE VL 5344
3068 16:59:56.258407 # ok 1338 # SKIP SVE set SVE get SVE for VL 5344
3069 16:59:56.258514 # ok 1339 # SKIP SVE set SVE get FPSIMD for VL 5344
3070 16:59:56.258632 # ok 1340 # SKIP SVE set FPSIMD get SVE for VL 5344
3071 16:59:56.258751 # ok 1341 Set SVE VL 5360
3072 16:59:56.258843 # ok 1342 # SKIP SVE set SVE get SVE for VL 5360
3073 16:59:56.258920 # ok 1343 # SKIP SVE set SVE get FPSIMD for VL 5360
3074 16:59:56.259013 # ok 1344 # SKIP SVE set FPSIMD get SVE for VL 5360
3075 16:59:56.259095 # ok 1345 Set SVE VL 5376
3076 16:59:56.259168 # ok 1346 # SKIP SVE set SVE get SVE for VL 5376
3077 16:59:56.259242 # ok 1347 # SKIP SVE set SVE get FPSIMD for VL 5376
3078 16:59:56.259318 # ok 1348 # SKIP SVE set FPSIMD get SVE for VL 5376
3079 16:59:56.259387 # ok 1349 Set SVE VL 5392
3080 16:59:56.259461 # ok 1350 # SKIP SVE set SVE get SVE for VL 5392
3081 16:59:56.259535 # ok 1351 # SKIP SVE set SVE get FPSIMD for VL 5392
3082 16:59:56.259612 # ok 1352 # SKIP SVE set FPSIMD get SVE for VL 5392
3083 16:59:56.259693 # ok 1353 Set SVE VL 5408
3084 16:59:56.259997 # ok 1354 # SKIP SVE set SVE get SVE for VL 5408
3085 16:59:56.260160 # ok 1355 # SKIP SVE set SVE get FPSIMD for VL 5408
3086 16:59:56.260293 # ok 1356 # SKIP SVE set FPSIMD get SVE for VL 5408
3087 16:59:56.260507 # ok 1357 Set SVE VL 5424
3088 16:59:56.260713 # ok 1358 # SKIP SVE set SVE get SVE for VL 5424
3089 16:59:56.260926 # ok 1359 # SKIP SVE set SVE get FPSIMD for VL 5424
3090 16:59:56.261101 # ok 1360 # SKIP SVE set FPSIMD get SVE for VL 5424
3091 16:59:56.261289 # ok 1361 Set SVE VL 5440
3092 16:59:56.261481 # ok 1362 # SKIP SVE set SVE get SVE for VL 5440
3093 16:59:56.261662 # ok 1363 # SKIP SVE set SVE get FPSIMD for VL 5440
3094 16:59:56.261786 # ok 1364 # SKIP SVE set FPSIMD get SVE for VL 5440
3095 16:59:56.261901 # ok 1365 Set SVE VL 5456
3096 16:59:56.262011 # ok 1366 # SKIP SVE set SVE get SVE for VL 5456
3097 16:59:56.262121 # ok 1367 # SKIP SVE set SVE get FPSIMD for VL 5456
3098 16:59:56.262230 # ok 1368 # SKIP SVE set FPSIMD get SVE for VL 5456
3099 16:59:56.262339 # ok 1369 Set SVE VL 5472
3100 16:59:56.262449 # ok 1370 # SKIP SVE set SVE get SVE for VL 5472
3101 16:59:56.262558 # ok 1371 # SKIP SVE set SVE get FPSIMD for VL 5472
3102 16:59:56.262668 # ok 1372 # SKIP SVE set FPSIMD get SVE for VL 5472
3103 16:59:56.262778 # ok 1373 Set SVE VL 5488
3104 16:59:56.262879 # ok 1374 # SKIP SVE set SVE get SVE for VL 5488
3105 16:59:56.262962 # ok 1375 # SKIP SVE set SVE get FPSIMD for VL 5488
3106 16:59:56.263045 # ok 1376 # SKIP SVE set FPSIMD get SVE for VL 5488
3107 16:59:56.263128 # ok 1377 Set SVE VL 5504
3108 16:59:56.263211 # ok 1378 # SKIP SVE set SVE get SVE for VL 5504
3109 16:59:56.263293 # ok 1379 # SKIP SVE set SVE get FPSIMD for VL 5504
3110 16:59:56.263376 # ok 1380 # SKIP SVE set FPSIMD get SVE for VL 5504
3111 16:59:56.263458 # ok 1381 Set SVE VL 5520
3112 16:59:56.263541 # ok 1382 # SKIP SVE set SVE get SVE for VL 5520
3113 16:59:56.263623 # ok 1383 # SKIP SVE set SVE get FPSIMD for VL 5520
3114 16:59:56.263705 # ok 1384 # SKIP SVE set FPSIMD get SVE for VL 5520
3115 16:59:56.263789 # ok 1385 Set SVE VL 5536
3116 16:59:56.263871 # ok 1386 # SKIP SVE set SVE get SVE for VL 5536
3117 16:59:56.263958 # ok 1387 # SKIP SVE set SVE get FPSIMD for VL 5536
3118 16:59:56.264041 # ok 1388 # SKIP SVE set FPSIMD get SVE for VL 5536
3119 16:59:56.264124 # ok 1389 Set SVE VL 5552
3120 16:59:56.264207 # ok 1390 # SKIP SVE set SVE get SVE for VL 5552
3121 16:59:56.264315 # ok 1391 # SKIP SVE set SVE get FPSIMD for VL 5552
3122 16:59:56.264405 # ok 1392 # SKIP SVE set FPSIMD get SVE for VL 5552
3123 16:59:56.264489 # ok 1393 Set SVE VL 5568
3124 16:59:56.264573 # ok 1394 # SKIP SVE set SVE get SVE for VL 5568
3125 16:59:56.264656 # ok 1395 # SKIP SVE set SVE get FPSIMD for VL 5568
3126 16:59:56.264942 # ok 1396 # SKIP SVE set FPSIMD get SVE for VL 5568
3127 16:59:56.265038 # ok 1397 Set SVE VL 5584
3128 16:59:56.265123 # ok 1398 # SKIP SVE set SVE get SVE for VL 5584
3129 16:59:56.265207 # ok 1399 # SKIP SVE set SVE get FPSIMD for VL 5584
3130 16:59:56.265291 # ok 1400 # SKIP SVE set FPSIMD get SVE for VL 5584
3131 16:59:56.265375 # ok 1401 Set SVE VL 5600
3132 16:59:56.265459 # ok 1402 # SKIP SVE set SVE get SVE for VL 5600
3133 16:59:56.265543 # ok 1403 # SKIP SVE set SVE get FPSIMD for VL 5600
3134 16:59:56.265627 # ok 1404 # SKIP SVE set FPSIMD get SVE for VL 5600
3135 16:59:56.265724 # ok 1405 Set SVE VL 5616
3136 16:59:56.265809 # ok 1406 # SKIP SVE set SVE get SVE for VL 5616
3137 16:59:56.296749 # ok 1407 # SKIP SVE set SVE get FPSIMD for VL 5616
3138 16:59:56.296990 # ok 1408 # SKIP SVE set FPSIMD get SVE for VL 5616
3139 16:59:56.297082 # ok 1409 Set SVE VL 5632
3140 16:59:56.297171 # ok 1410 # SKIP SVE set SVE get SVE for VL 5632
3141 16:59:56.297273 # ok 1411 # SKIP SVE set SVE get FPSIMD for VL 5632
3142 16:59:56.297359 # ok 1412 # SKIP SVE set FPSIMD get SVE for VL 5632
3143 16:59:56.297443 # ok 1413 Set SVE VL 5648
3144 16:59:56.297526 # ok 1414 # SKIP SVE set SVE get SVE for VL 5648
3145 16:59:56.297617 # ok 1415 # SKIP SVE set SVE get FPSIMD for VL 5648
3146 16:59:56.298689 # ok 1416 # SKIP SVE set FPSIMD get SVE for VL 5648
3147 16:59:56.298996 # ok 1417 Set SVE VL 5664
3148 16:59:56.299101 # ok 1418 # SKIP SVE set SVE get SVE for VL 5664
3149 16:59:56.299190 # ok 1419 # SKIP SVE set SVE get FPSIMD for VL 5664
3150 16:59:56.299293 # ok 1420 # SKIP SVE set FPSIMD get SVE for VL 5664
3151 16:59:56.299382 # ok 1421 Set SVE VL 5680
3152 16:59:56.299483 # ok 1422 # SKIP SVE set SVE get SVE for VL 5680
3153 16:59:56.299585 # ok 1423 # SKIP SVE set SVE get FPSIMD for VL 5680
3154 16:59:56.299686 # ok 1424 # SKIP SVE set FPSIMD get SVE for VL 5680
3155 16:59:56.299785 # ok 1425 Set SVE VL 5696
3156 16:59:56.299884 # ok 1426 # SKIP SVE set SVE get SVE for VL 5696
3157 16:59:56.300183 # ok 1427 # SKIP SVE set SVE get FPSIMD for VL 5696
3158 16:59:56.300299 # ok 1428 # SKIP SVE set FPSIMD get SVE for VL 5696
3159 16:59:56.300385 # ok 1429 Set SVE VL 5712
3160 16:59:56.300483 # ok 1430 # SKIP SVE set SVE get SVE for VL 5712
3161 16:59:56.300568 # ok 1431 # SKIP SVE set SVE get FPSIMD for VL 5712
3162 16:59:56.300666 # ok 1432 # SKIP SVE set FPSIMD get SVE for VL 5712
3163 16:59:56.300764 # ok 1433 Set SVE VL 5728
3164 16:59:56.301051 # ok 1434 # SKIP SVE set SVE get SVE for VL 5728
3165 16:59:56.301142 # ok 1435 # SKIP SVE set SVE get FPSIMD for VL 5728
3166 16:59:56.301238 # ok 1436 # SKIP SVE set FPSIMD get SVE for VL 5728
3167 16:59:56.301324 # ok 1437 Set SVE VL 5744
3168 16:59:56.301420 # ok 1438 # SKIP SVE set SVE get SVE for VL 5744
3169 16:59:56.301518 # ok 1439 # SKIP SVE set SVE get FPSIMD for VL 5744
3170 16:59:56.303314 # ok 1440 # SKIP SVE set FPSIMD get SVE for VL 5744
3171 16:59:56.303610 # ok 1441 Set SVE VL 5760
3172 16:59:56.303688 # ok 1442 # SKIP SVE set SVE get SVE for VL 5760
3173 16:59:56.303782 # ok 1443 # SKIP SVE set SVE get FPSIMD for VL 5760
3174 16:59:56.303853 # ok 1444 # SKIP SVE set FPSIMD get SVE for VL 5760
3175 16:59:56.303926 # ok 1445 Set SVE VL 5776
3176 16:59:56.304015 # ok 1446 # SKIP SVE set SVE get SVE for VL 5776
3177 16:59:56.304085 # ok 1447 # SKIP SVE set SVE get FPSIMD for VL 5776
3178 16:59:56.304158 # ok 1448 # SKIP SVE set FPSIMD get SVE for VL 5776
3179 16:59:56.304246 # ok 1449 Set SVE VL 5792
3180 16:59:56.304317 # ok 1450 # SKIP SVE set SVE get SVE for VL 5792
3181 16:59:56.304405 # ok 1451 # SKIP SVE set SVE get FPSIMD for VL 5792
3182 16:59:56.304476 # ok 1452 # SKIP SVE set FPSIMD get SVE for VL 5792
3183 16:59:56.304564 # ok 1453 Set SVE VL 5808
3184 16:59:56.304649 # ok 1454 # SKIP SVE set SVE get SVE for VL 5808
3185 16:59:56.304744 # ok 1455 # SKIP SVE set SVE get FPSIMD for VL 5808
3186 16:59:56.304824 # ok 1456 # SKIP SVE set FPSIMD get SVE for VL 5808
3187 16:59:56.304929 # ok 1457 Set SVE VL 5824
3188 16:59:56.305013 # ok 1458 # SKIP SVE set SVE get SVE for VL 5824
3189 16:59:56.305104 # ok 1459 # SKIP SVE set SVE get FPSIMD for VL 5824
3190 16:59:56.305178 # ok 1460 # SKIP SVE set FPSIMD get SVE for VL 5824
3191 16:59:56.305251 # ok 1461 Set SVE VL 5840
3192 16:59:56.305333 # ok 1462 # SKIP SVE set SVE get SVE for VL 5840
3193 16:59:56.305426 # ok 1463 # SKIP SVE set SVE get FPSIMD for VL 5840
3194 16:59:56.305655 # ok 1464 # SKIP SVE set FPSIMD get SVE for VL 5840
3195 16:59:56.308871 # ok 1465 Set SVE VL 5856
3196 16:59:56.309051 # ok 1466 # SKIP SVE set SVE get SVE for VL 5856
3197 16:59:56.309137 # ok 1467 # SKIP SVE set SVE get FPSIMD for VL 5856
3198 16:59:56.309443 # ok 1468 # SKIP SVE set FPSIMD get SVE for VL 5856
3199 16:59:56.309553 # ok 1469 Set SVE VL 5872
3200 16:59:56.309644 # ok 1470 # SKIP SVE set SVE get SVE for VL 5872
3201 16:59:56.309726 # ok 1471 # SKIP SVE set SVE get FPSIMD for VL 5872
3202 16:59:56.309800 # ok 1472 # SKIP SVE set FPSIMD get SVE for VL 5872
3203 16:59:56.309872 # ok 1473 Set SVE VL 5888
3204 16:59:56.309962 # ok 1474 # SKIP SVE set SVE get SVE for VL 5888
3205 16:59:56.311270 # ok 1475 # SKIP SVE set SVE get FPSIMD for VL 5888
3206 16:59:56.311396 # ok 1476 # SKIP SVE set FPSIMD get SVE for VL 5888
3207 16:59:56.311485 # ok 1477 Set SVE VL 5904
3208 16:59:56.311590 # ok 1478 # SKIP SVE set SVE get SVE for VL 5904
3209 16:59:56.311794 # ok 1479 # SKIP SVE set SVE get FPSIMD for VL 5904
3210 16:59:56.311914 # ok 1480 # SKIP SVE set FPSIMD get SVE for VL 5904
3211 16:59:56.312020 # ok 1481 Set SVE VL 5920
3212 16:59:56.312121 # ok 1482 # SKIP SVE set SVE get SVE for VL 5920
3213 16:59:56.312230 # ok 1483 # SKIP SVE set SVE get FPSIMD for VL 5920
3214 16:59:56.312539 # ok 1484 # SKIP SVE set FPSIMD get SVE for VL 5920
3215 16:59:56.312649 # ok 1485 Set SVE VL 5936
3216 16:59:56.312752 # ok 1486 # SKIP SVE set SVE get SVE for VL 5936
3217 16:59:56.312854 # ok 1487 # SKIP SVE set SVE get FPSIMD for VL 5936
3218 16:59:56.312964 # ok 1488 # SKIP SVE set FPSIMD get SVE for VL 5936
3219 16:59:56.313073 # ok 1489 Set SVE VL 5952
3220 16:59:56.313174 # ok 1490 # SKIP SVE set SVE get SVE for VL 5952
3221 16:59:56.313485 # ok 1491 # SKIP SVE set SVE get FPSIMD for VL 5952
3222 16:59:56.313613 # ok 1492 # SKIP SVE set FPSIMD get SVE for VL 5952
3223 16:59:56.313712 # ok 1493 Set SVE VL 5968
3224 16:59:56.314784 # ok 1494 # SKIP SVE set SVE get SVE for VL 5968
3225 16:59:56.314891 # ok 1495 # SKIP SVE set SVE get FPSIMD for VL 5968
3226 16:59:56.315179 # ok 1496 # SKIP SVE set FPSIMD get SVE for VL 5968
3227 16:59:56.315284 # ok 1497 Set SVE VL 5984
3228 16:59:56.315371 # ok 1498 # SKIP SVE set SVE get SVE for VL 5984
3229 16:59:56.315474 # ok 1499 # SKIP SVE set SVE get FPSIMD for VL 5984
3230 16:59:56.315576 # ok 1500 # SKIP SVE set FPSIMD get SVE for VL 5984
3231 16:59:56.315664 # ok 1501 Set SVE VL 6000
3232 16:59:56.315763 # ok 1502 # SKIP SVE set SVE get SVE for VL 6000
3233 16:59:56.316059 # ok 1503 # SKIP SVE set SVE get FPSIMD for VL 6000
3234 16:59:56.316163 # ok 1504 # SKIP SVE set FPSIMD get SVE for VL 6000
3235 16:59:56.316267 # ok 1505 Set SVE VL 6016
3236 16:59:56.316398 # ok 1506 # SKIP SVE set SVE get SVE for VL 6016
3237 16:59:56.316516 # ok 1507 # SKIP SVE set SVE get FPSIMD for VL 6016
3238 16:59:56.316619 # ok 1508 # SKIP SVE set FPSIMD get SVE for VL 6016
3239 16:59:56.316707 # ok 1509 Set SVE VL 6032
3240 16:59:56.316807 # ok 1510 # SKIP SVE set SVE get SVE for VL 6032
3241 16:59:56.316924 # ok 1511 # SKIP SVE set SVE get FPSIMD for VL 6032
3242 16:59:56.317257 # ok 1512 # SKIP SVE set FPSIMD get SVE for VL 6032
3243 16:59:56.317361 # ok 1513 Set SVE VL 6048
3244 16:59:56.317463 # ok 1514 # SKIP SVE set SVE get SVE for VL 6048
3245 16:59:56.317561 # ok 1515 # SKIP SVE set SVE get FPSIMD for VL 6048
3246 16:59:56.318738 # ok 1516 # SKIP SVE set FPSIMD get SVE for VL 6048
3247 16:59:56.319173 # ok 1517 Set SVE VL 6064
3248 16:59:56.319365 # ok 1518 # SKIP SVE set SVE get SVE for VL 6064
3249 16:59:56.319575 # ok 1519 # SKIP SVE set SVE get FPSIMD for VL 6064
3250 16:59:56.319821 # ok 1520 # SKIP SVE set FPSIMD get SVE for VL 6064
3251 16:59:56.319997 # ok 1521 Set SVE VL 6080
3252 16:59:56.320116 # ok 1522 # SKIP SVE set SVE get SVE for VL 6080
3253 16:59:56.320230 # ok 1523 # SKIP SVE set SVE get FPSIMD for VL 6080
3254 16:59:56.320345 # ok 1524 # SKIP SVE set FPSIMD get SVE for VL 6080
3255 16:59:56.320491 # ok 1525 Set SVE VL 6096
3256 16:59:56.320616 # ok 1526 # SKIP SVE set SVE get SVE for VL 6096
3257 16:59:56.320737 # ok 1527 # SKIP SVE set SVE get FPSIMD for VL 6096
3258 16:59:56.320857 # ok 1528 # SKIP SVE set FPSIMD get SVE for VL 6096
3259 16:59:56.320975 # ok 1529 Set SVE VL 6112
3260 16:59:56.321108 # ok 1530 # SKIP SVE set SVE get SVE for VL 6112
3261 16:59:56.321225 # ok 1531 # SKIP SVE set SVE get FPSIMD for VL 6112
3262 16:59:56.321331 # ok 1532 # SKIP SVE set FPSIMD get SVE for VL 6112
3263 16:59:56.321457 # ok 1533 Set SVE VL 6128
3264 16:59:56.321594 # ok 1534 # SKIP SVE set SVE get SVE for VL 6128
3265 16:59:56.321729 # ok 1535 # SKIP SVE set SVE get FPSIMD for VL 6128
3266 16:59:56.321879 # ok 1536 # SKIP SVE set FPSIMD get SVE for VL 6128
3267 16:59:56.321999 # ok 1537 Set SVE VL 6144
3268 16:59:56.322092 # ok 1538 # SKIP SVE set SVE get SVE for VL 6144
3269 16:59:56.322582 # ok 1539 # SKIP SVE set SVE get FPSIMD for VL 6144
3270 16:59:56.322679 # ok 1540 # SKIP SVE set FPSIMD get SVE for VL 6144
3271 16:59:56.322783 # ok 1541 Set SVE VL 6160
3272 16:59:56.322882 # ok 1542 # SKIP SVE set SVE get SVE for VL 6160
3273 16:59:56.322984 # ok 1543 # SKIP SVE set SVE get FPSIMD for VL 6160
3274 16:59:56.323281 # ok 1544 # SKIP SVE set FPSIMD get SVE for VL 6160
3275 16:59:56.323383 # ok 1545 Set SVE VL 6176
3276 16:59:56.323469 # ok 1546 # SKIP SVE set SVE get SVE for VL 6176
3277 16:59:56.323547 # ok 1547 # SKIP SVE set SVE get FPSIMD for VL 6176
3278 16:59:56.323634 # ok 1548 # SKIP SVE set FPSIMD get SVE for VL 6176
3279 16:59:56.323907 # ok 1549 Set SVE VL 6192
3280 16:59:56.324011 # ok 1550 # SKIP SVE set SVE get SVE for VL 6192
3281 16:59:56.324138 # ok 1551 # SKIP SVE set SVE get FPSIMD for VL 6192
3282 16:59:56.324240 # ok 1552 # SKIP SVE set FPSIMD get SVE for VL 6192
3283 16:59:56.324349 # ok 1553 Set SVE VL 6208
3284 16:59:56.324440 # ok 1554 # SKIP SVE set SVE get SVE for VL 6208
3285 16:59:56.324543 # ok 1555 # SKIP SVE set SVE get FPSIMD for VL 6208
3286 16:59:56.324665 # ok 1556 # SKIP SVE set FPSIMD get SVE for VL 6208
3287 16:59:56.324761 # ok 1557 Set SVE VL 6224
3288 16:59:56.324877 # ok 1558 # SKIP SVE set SVE get SVE for VL 6224
3289 16:59:56.324984 # ok 1559 # SKIP SVE set SVE get FPSIMD for VL 6224
3290 16:59:56.325090 # ok 1560 # SKIP SVE set FPSIMD get SVE for VL 6224
3291 16:59:56.325192 # ok 1561 Set SVE VL 6240
3292 16:59:56.325306 # ok 1562 # SKIP SVE set SVE get SVE for VL 6240
3293 16:59:56.325421 # ok 1563 # SKIP SVE set SVE get FPSIMD for VL 6240
3294 16:59:56.325527 # ok 1564 # SKIP SVE set FPSIMD get SVE for VL 6240
3295 16:59:56.326292 # ok 1565 Set SVE VL 6256
3296 16:59:56.326545 # ok 1566 # SKIP SVE set SVE get SVE for VL 6256
3297 16:59:56.326664 # ok 1567 # SKIP SVE set SVE get FPSIMD for VL 6256
3298 16:59:56.326753 # ok 1568 # SKIP SVE set FPSIMD get SVE for VL 6256
3299 16:59:56.326843 # ok 1569 Set SVE VL 6272
3300 16:59:56.326941 # ok 1570 # SKIP SVE set SVE get SVE for VL 6272
3301 16:59:56.327054 # ok 1571 # SKIP SVE set SVE get FPSIMD for VL 6272
3302 16:59:56.327348 # ok 1572 # SKIP SVE set FPSIMD get SVE for VL 6272
3303 16:59:56.327439 # ok 1573 Set SVE VL 6288
3304 16:59:56.327532 # ok 1574 # SKIP SVE set SVE get SVE for VL 6288
3305 16:59:56.327630 # ok 1575 # SKIP SVE set SVE get FPSIMD for VL 6288
3306 16:59:56.327725 # ok 1576 # SKIP SVE set FPSIMD get SVE for VL 6288
3307 16:59:56.327815 # ok 1577 Set SVE VL 6304
3308 16:59:56.328090 # ok 1578 # SKIP SVE set SVE get SVE for VL 6304
3309 16:59:56.328183 # ok 1579 # SKIP SVE set SVE get FPSIMD for VL 6304
3310 16:59:56.328272 # ok 1580 # SKIP SVE set FPSIMD get SVE for VL 6304
3311 16:59:56.328340 # ok 1581 Set SVE VL 6320
3312 16:59:56.328433 # ok 1582 # SKIP SVE set SVE get SVE for VL 6320
3313 16:59:56.328543 # ok 1583 # SKIP SVE set SVE get FPSIMD for VL 6320
3314 16:59:56.328641 # ok 1584 # SKIP SVE set FPSIMD get SVE for VL 6320
3315 16:59:56.328760 # ok 1585 Set SVE VL 6336
3316 16:59:56.328846 # ok 1586 # SKIP SVE set SVE get SVE for VL 6336
3317 16:59:56.328936 # ok 1587 # SKIP SVE set SVE get FPSIMD for VL 6336
3318 16:59:56.329026 # ok 1588 # SKIP SVE set FPSIMD get SVE for VL 6336
3319 16:59:56.329090 # ok 1589 Set SVE VL 6352
3320 16:59:56.332047 # ok 1590 # SKIP SVE set SVE get SVE for VL 6352
3321 16:59:56.332201 # ok 1591 # SKIP SVE set SVE get FPSIMD for VL 6352
3322 16:59:56.332295 # ok 1592 # SKIP SVE set FPSIMD get SVE for VL 6352
3323 16:59:56.332378 # ok 1593 Set SVE VL 6368
3324 16:59:56.332472 # ok 1594 # SKIP SVE set SVE get SVE for VL 6368
3325 16:59:56.332565 # ok 1595 # SKIP SVE set SVE get FPSIMD for VL 6368
3326 16:59:56.332664 # ok 1596 # SKIP SVE set FPSIMD get SVE for VL 6368
3327 16:59:56.332749 # ok 1597 Set SVE VL 6384
3328 16:59:56.332854 # ok 1598 # SKIP SVE set SVE get SVE for VL 6384
3329 16:59:56.332940 # ok 1599 # SKIP SVE set SVE get FPSIMD for VL 6384
3330 16:59:56.333225 # ok 1600 # SKIP SVE set FPSIMD get SVE for VL 6384
3331 16:59:56.333326 # ok 1601 Set SVE VL 6400
3332 16:59:56.333425 # ok 1602 # SKIP SVE set SVE get SVE for VL 6400
3333 16:59:56.333579 # ok 1603 # SKIP SVE set SVE get FPSIMD for VL 6400
3334 16:59:56.334029 # ok 1604 # SKIP SVE set FPSIMD get SVE for VL 6400
3335 16:59:56.334331 # ok 1605 Set SVE VL 6416
3336 16:59:56.334446 # ok 1606 # SKIP SVE set SVE get SVE for VL 6416
3337 16:59:56.334551 # ok 1607 # SKIP SVE set SVE get FPSIMD for VL 6416
3338 16:59:56.334644 # ok 1608 # SKIP SVE set FPSIMD get SVE for VL 6416
3339 16:59:56.334742 # ok 1609 Set SVE VL 6432
3340 16:59:56.334831 # ok 1610 # SKIP SVE set SVE get SVE for VL 6432
3341 16:59:56.334930 # ok 1611 # SKIP SVE set SVE get FPSIMD for VL 6432
3342 16:59:56.335025 # ok 1612 # SKIP SVE set FPSIMD get SVE for VL 6432
3343 16:59:56.335115 # ok 1613 Set SVE VL 6448
3344 16:59:56.335210 # ok 1614 # SKIP SVE set SVE get SVE for VL 6448
3345 16:59:56.335514 # ok 1615 # SKIP SVE set SVE get FPSIMD for VL 6448
3346 16:59:56.335611 # ok 1616 # SKIP SVE set FPSIMD get SVE for VL 6448
3347 16:59:56.335698 # ok 1617 Set SVE VL 6464
3348 16:59:56.335781 # ok 1618 # SKIP SVE set SVE get SVE for VL 6464
3349 16:59:56.335866 # ok 1619 # SKIP SVE set SVE get FPSIMD for VL 6464
3350 16:59:56.335955 # ok 1620 # SKIP SVE set FPSIMD get SVE for VL 6464
3351 16:59:56.336040 # ok 1621 Set SVE VL 6480
3352 16:59:56.336137 # ok 1622 # SKIP SVE set SVE get SVE for VL 6480
3353 16:59:56.336414 # ok 1623 # SKIP SVE set SVE get FPSIMD for VL 6480
3354 16:59:56.336509 # ok 1624 # SKIP SVE set FPSIMD get SVE for VL 6480
3355 16:59:56.336601 # ok 1625 Set SVE VL 6496
3356 16:59:56.336731 # ok 1626 # SKIP SVE set SVE get SVE for VL 6496
3357 16:59:56.336869 # ok 1627 # SKIP SVE set SVE get FPSIMD for VL 6496
3358 16:59:56.336973 # ok 1628 # SKIP SVE set FPSIMD get SVE for VL 6496
3359 16:59:56.337105 # ok 1629 Set SVE VL 6512
3360 16:59:56.337210 # ok 1630 # SKIP SVE set SVE get SVE for VL 6512
3361 16:59:56.337343 # ok 1631 # SKIP SVE set SVE get FPSIMD for VL 6512
3362 16:59:56.337445 # ok 1632 # SKIP SVE set FPSIMD get SVE for VL 6512
3363 16:59:56.337563 # ok 1633 Set SVE VL 6528
3364 16:59:56.337663 # ok 1634 # SKIP SVE set SVE get SVE for VL 6528
3365 16:59:56.337779 # ok 1635 # SKIP SVE set SVE get FPSIMD for VL 6528
3366 16:59:56.338090 # ok 1636 # SKIP SVE set FPSIMD get SVE for VL 6528
3367 16:59:56.338184 # ok 1637 Set SVE VL 6544
3368 16:59:56.338270 # ok 1638 # SKIP SVE set SVE get SVE for VL 6544
3369 16:59:56.338393 # ok 1639 # SKIP SVE set SVE get FPSIMD for VL 6544
3370 16:59:56.338486 # ok 1640 # SKIP SVE set FPSIMD get SVE for VL 6544
3371 16:59:56.338587 # ok 1641 Set SVE VL 6560
3372 16:59:56.338689 # ok 1642 # SKIP SVE set SVE get SVE for VL 6560
3373 16:59:56.338801 # ok 1643 # SKIP SVE set SVE get FPSIMD for VL 6560
3374 16:59:56.338896 # ok 1644 # SKIP SVE set FPSIMD get SVE for VL 6560
3375 16:59:56.338968 # ok 1645 Set SVE VL 6576
3376 16:59:56.339086 # ok 1646 # SKIP SVE set SVE get SVE for VL 6576
3377 16:59:56.339177 # ok 1647 # SKIP SVE set SVE get FPSIMD for VL 6576
3378 16:59:56.339303 # ok 1648 # SKIP SVE set FPSIMD get SVE for VL 6576
3379 16:59:56.339391 # ok 1649 Set SVE VL 6592
3380 16:59:56.339475 # ok 1650 # SKIP SVE set SVE get SVE for VL 6592
3381 16:59:56.339567 # ok 1651 # SKIP SVE set SVE get FPSIMD for VL 6592
3382 16:59:56.339678 # ok 1652 # SKIP SVE set FPSIMD get SVE for VL 6592
3383 16:59:56.339791 # ok 1653 Set SVE VL 6608
3384 16:59:56.339888 # ok 1654 # SKIP SVE set SVE get SVE for VL 6608
3385 16:59:56.340020 # ok 1655 # SKIP SVE set SVE get FPSIMD for VL 6608
3386 16:59:56.340124 # ok 1656 # SKIP SVE set FPSIMD get SVE for VL 6608
3387 16:59:56.340224 # ok 1657 Set SVE VL 6624
3388 16:59:56.340313 # ok 1658 # SKIP SVE set SVE get SVE for VL 6624
3389 16:59:56.340427 # ok 1659 # SKIP SVE set SVE get FPSIMD for VL 6624
3390 16:59:56.340747 # ok 1660 # SKIP SVE set FPSIMD get SVE for VL 6624
3391 16:59:56.340905 # ok 1661 Set SVE VL 6640
3392 16:59:56.341059 # ok 1662 # SKIP SVE set SVE get SVE for VL 6640
3393 16:59:56.341246 # ok 1663 # SKIP SVE set SVE get FPSIMD for VL 6640
3394 16:59:56.341385 # ok 1664 # SKIP SVE set FPSIMD get SVE for VL 6640
3395 16:59:56.341501 # ok 1665 Set SVE VL 6656
3396 16:59:56.341692 # ok 1666 # SKIP SVE set SVE get SVE for VL 6656
3397 16:59:56.341819 # ok 1667 # SKIP SVE set SVE get FPSIMD for VL 6656
3398 16:59:56.341956 # ok 1668 # SKIP SVE set FPSIMD get SVE for VL 6656
3399 16:59:56.342072 # ok 1669 Set SVE VL 6672
3400 16:59:56.342188 # ok 1670 # SKIP SVE set SVE get SVE for VL 6672
3401 16:59:56.342331 # ok 1671 # SKIP SVE set SVE get FPSIMD for VL 6672
3402 16:59:56.342473 # ok 1672 # SKIP SVE set FPSIMD get SVE for VL 6672
3403 16:59:56.342602 # ok 1673 Set SVE VL 6688
3404 16:59:56.342776 # ok 1674 # SKIP SVE set SVE get SVE for VL 6688
3405 16:59:56.342928 # ok 1675 # SKIP SVE set SVE get FPSIMD for VL 6688
3406 16:59:56.343072 # ok 1676 # SKIP SVE set FPSIMD get SVE for VL 6688
3407 16:59:56.343197 # ok 1677 Set SVE VL 6704
3408 16:59:56.343313 # ok 1678 # SKIP SVE set SVE get SVE for VL 6704
3409 16:59:56.343425 # ok 1679 # SKIP SVE set SVE get FPSIMD for VL 6704
3410 16:59:56.343529 # ok 1680 # SKIP SVE set FPSIMD get SVE for VL 6704
3411 16:59:56.343640 # ok 1681 Set SVE VL 6720
3412 16:59:56.343778 # ok 1682 # SKIP SVE set SVE get SVE for VL 6720
3413 16:59:56.343901 # ok 1683 # SKIP SVE set SVE get FPSIMD for VL 6720
3414 16:59:56.344027 # ok 1684 # SKIP SVE set FPSIMD get SVE for VL 6720
3415 16:59:56.344201 # ok 1685 Set SVE VL 6736
3416 16:59:56.344339 # ok 1686 # SKIP SVE set SVE get SVE for VL 6736
3417 16:59:56.344477 # ok 1687 # SKIP SVE set SVE get FPSIMD for VL 6736
3418 16:59:56.344617 # ok 1688 # SKIP SVE set FPSIMD get SVE for VL 6736
3419 16:59:56.344755 # ok 1689 Set SVE VL 6752
3420 16:59:56.344904 # ok 1690 # SKIP SVE set SVE get SVE for VL 6752
3421 16:59:56.345047 # ok 1691 # SKIP SVE set SVE get FPSIMD for VL 6752
3422 16:59:56.345197 # ok 1692 # SKIP SVE set FPSIMD get SVE for VL 6752
3423 16:59:56.345320 # ok 1693 Set SVE VL 6768
3424 16:59:56.345441 # ok 1694 # SKIP SVE set SVE get SVE for VL 6768
3425 16:59:56.345629 # ok 1695 # SKIP SVE set SVE get FPSIMD for VL 6768
3426 16:59:56.346286 # ok 1696 # SKIP SVE set FPSIMD get SVE for VL 6768
3427 16:59:56.346418 # ok 1697 Set SVE VL 6784
3428 16:59:56.346518 # ok 1698 # SKIP SVE set SVE get SVE for VL 6784
3429 16:59:56.346618 # ok 1699 # SKIP SVE set SVE get FPSIMD for VL 6784
3430 16:59:56.346714 # ok 1700 # SKIP SVE set FPSIMD get SVE for VL 6784
3431 16:59:56.346816 # ok 1701 Set SVE VL 6800
3432 16:59:56.346908 # ok 1702 # SKIP SVE set SVE get SVE for VL 6800
3433 16:59:56.347182 # ok 1703 # SKIP SVE set SVE get FPSIMD for VL 6800
3434 16:59:56.347280 # ok 1704 # SKIP SVE set FPSIMD get SVE for VL 6800
3435 16:59:56.347364 # ok 1705 Set SVE VL 6816
3436 16:59:56.347446 # ok 1706 # SKIP SVE set SVE get SVE for VL 6816
3437 16:59:56.347529 # ok 1707 # SKIP SVE set SVE get FPSIMD for VL 6816
3438 16:59:56.347613 # ok 1708 # SKIP SVE set FPSIMD get SVE for VL 6816
3439 16:59:56.347708 # ok 1709 Set SVE VL 6832
3440 16:59:56.347797 # ok 1710 # SKIP SVE set SVE get SVE for VL 6832
3441 16:59:56.347879 # ok 1711 # SKIP SVE set SVE get FPSIMD for VL 6832
3442 16:59:56.347977 # ok 1712 # SKIP SVE set FPSIMD get SVE for VL 6832
3443 16:59:56.348071 # ok 1713 Set SVE VL 6848
3444 16:59:56.348189 # ok 1714 # SKIP SVE set SVE get SVE for VL 6848
3445 16:59:56.348277 # ok 1715 # SKIP SVE set SVE get FPSIMD for VL 6848
3446 16:59:56.348359 # ok 1716 # SKIP SVE set FPSIMD get SVE for VL 6848
3447 16:59:56.348423 # ok 1717 Set SVE VL 6864
3448 16:59:56.348498 # ok 1718 # SKIP SVE set SVE get SVE for VL 6864
3449 16:59:56.348590 # ok 1719 # SKIP SVE set SVE get FPSIMD for VL 6864
3450 16:59:56.348685 # ok 1720 # SKIP SVE set FPSIMD get SVE for VL 6864
3451 16:59:56.348765 # ok 1721 Set SVE VL 6880
3452 16:59:56.348861 # ok 1722 # SKIP SVE set SVE get SVE for VL 6880
3453 16:59:56.348934 # ok 1723 # SKIP SVE set SVE get FPSIMD for VL 6880
3454 16:59:56.349024 # ok 1724 # SKIP SVE set FPSIMD get SVE for VL 6880
3455 16:59:56.349104 # ok 1725 Set SVE VL 6896
3456 16:59:56.349184 # ok 1726 # SKIP SVE set SVE get SVE for VL 6896
3457 16:59:56.349311 # ok 1727 # SKIP SVE set SVE get FPSIMD for VL 6896
3458 16:59:56.349407 # ok 1728 # SKIP SVE set FPSIMD get SVE for VL 6896
3459 16:59:56.349516 # ok 1729 Set SVE VL 6912
3460 16:59:56.349601 # ok 1730 # SKIP SVE set SVE get SVE for VL 6912
3461 16:59:56.349709 # ok 1731 # SKIP SVE set SVE get FPSIMD for VL 6912
3462 16:59:56.350056 # ok 1732 # SKIP SVE set FPSIMD get SVE for VL 6912
3463 16:59:56.350201 # ok 1733 Set SVE VL 6928
3464 16:59:56.350295 # ok 1734 # SKIP SVE set SVE get SVE for VL 6928
3465 16:59:56.350573 # ok 1735 # SKIP SVE set SVE get FPSIMD for VL 6928
3466 16:59:56.350688 # ok 1736 # SKIP SVE set FPSIMD get SVE for VL 6928
3467 16:59:56.350781 # ok 1737 Set SVE VL 6944
3468 16:59:56.350883 # ok 1738 # SKIP SVE set SVE get SVE for VL 6944
3469 16:59:56.350984 # ok 1739 # SKIP SVE set SVE get FPSIMD for VL 6944
3470 16:59:56.351096 # ok 1740 # SKIP SVE set FPSIMD get SVE for VL 6944
3471 16:59:56.351210 # ok 1741 Set SVE VL 6960
3472 16:59:56.351332 # ok 1742 # SKIP SVE set SVE get SVE for VL 6960
3473 16:59:56.351429 # ok 1743 # SKIP SVE set SVE get FPSIMD for VL 6960
3474 16:59:56.351511 # ok 1744 # SKIP SVE set FPSIMD get SVE for VL 6960
3475 16:59:56.351601 # ok 1745 Set SVE VL 6976
3476 16:59:56.351687 # ok 1746 # SKIP SVE set SVE get SVE for VL 6976
3477 16:59:56.351784 # ok 1747 # SKIP SVE set SVE get FPSIMD for VL 6976
3478 16:59:56.351892 # ok 1748 # SKIP SVE set FPSIMD get SVE for VL 6976
3479 16:59:56.351987 # ok 1749 Set SVE VL 6992
3480 16:59:56.352086 # ok 1750 # SKIP SVE set SVE get SVE for VL 6992
3481 16:59:56.352197 # ok 1751 # SKIP SVE set SVE get FPSIMD for VL 6992
3482 16:59:56.352494 # ok 1752 # SKIP SVE set FPSIMD get SVE for VL 6992
3483 16:59:56.352581 # ok 1753 Set SVE VL 7008
3484 16:59:56.352696 # ok 1754 # SKIP SVE set SVE get SVE for VL 7008
3485 16:59:56.352793 # ok 1755 # SKIP SVE set SVE get FPSIMD for VL 7008
3486 16:59:56.352908 # ok 1756 # SKIP SVE set FPSIMD get SVE for VL 7008
3487 16:59:56.353031 # ok 1757 Set SVE VL 7024
3488 16:59:56.353155 # ok 1758 # SKIP SVE set SVE get SVE for VL 7024
3489 16:59:56.353264 # ok 1759 # SKIP SVE set SVE get FPSIMD for VL 7024
3490 16:59:56.353366 # ok 1760 # SKIP SVE set FPSIMD get SVE for VL 7024
3491 16:59:56.353476 # ok 1761 Set SVE VL 7040
3492 16:59:56.353757 # ok 1762 # SKIP SVE set SVE get SVE for VL 7040
3493 16:59:56.353850 # ok 1763 # SKIP SVE set SVE get FPSIMD for VL 7040
3494 16:59:56.353967 # ok 1764 # SKIP SVE set FPSIMD get SVE for VL 7040
3495 16:59:56.354109 # ok 1765 Set SVE VL 7056
3496 16:59:56.354222 # ok 1766 # SKIP SVE set SVE get SVE for VL 7056
3497 16:59:56.354343 # ok 1767 # SKIP SVE set SVE get FPSIMD for VL 7056
3498 16:59:56.354462 # ok 1768 # SKIP SVE set FPSIMD get SVE for VL 7056
3499 16:59:56.354564 # ok 1769 Set SVE VL 7072
3500 16:59:56.354676 # ok 1770 # SKIP SVE set SVE get SVE for VL 7072
3501 16:59:56.354809 # ok 1771 # SKIP SVE set SVE get FPSIMD for VL 7072
3502 16:59:56.354916 # ok 1772 # SKIP SVE set FPSIMD get SVE for VL 7072
3503 16:59:56.357203 # ok 1773 Set SVE VL 7088
3504 16:59:56.357590 # ok 1774 # SKIP SVE set SVE get SVE for VL 7088
3505 16:59:56.358156 # ok 1775 # SKIP SVE set SVE get FPSIMD for VL 7088
3506 16:59:56.358561 # ok 1776 # SKIP SVE set FPSIMD get SVE for VL 7088
3507 16:59:56.358668 # ok 1777 Set SVE VL 7104
3508 16:59:56.358758 # ok 1778 # SKIP SVE set SVE get SVE for VL 7104
3509 16:59:56.358843 # ok 1779 # SKIP SVE set SVE get FPSIMD for VL 7104
3510 16:59:56.358944 # ok 1780 # SKIP SVE set FPSIMD get SVE for VL 7104
3511 16:59:56.359031 # ok 1781 Set SVE VL 7120
3512 16:59:56.359137 # ok 1782 # SKIP SVE set SVE get SVE for VL 7120
3513 16:59:56.359227 # ok 1783 # SKIP SVE set SVE get FPSIMD for VL 7120
3514 16:59:56.359328 # ok 1784 # SKIP SVE set FPSIMD get SVE for VL 7120
3515 16:59:56.359415 # ok 1785 Set SVE VL 7136
3516 16:59:56.359514 # ok 1786 # SKIP SVE set SVE get SVE for VL 7136
3517 16:59:56.359839 # ok 1787 # SKIP SVE set SVE get FPSIMD for VL 7136
3518 16:59:56.359957 # ok 1788 # SKIP SVE set FPSIMD get SVE for VL 7136
3519 16:59:56.360050 # ok 1789 Set SVE VL 7152
3520 16:59:56.360153 # ok 1790 # SKIP SVE set SVE get SVE for VL 7152
3521 16:59:56.360255 # ok 1791 # SKIP SVE set SVE get FPSIMD for VL 7152
3522 16:59:56.360356 # ok 1792 # SKIP SVE set FPSIMD get SVE for VL 7152
3523 16:59:56.360457 # ok 1793 Set SVE VL 7168
3524 16:59:56.360757 # ok 1794 # SKIP SVE set SVE get SVE for VL 7168
3525 16:59:56.360860 # ok 1795 # SKIP SVE set SVE get FPSIMD for VL 7168
3526 16:59:56.360959 # ok 1796 # SKIP SVE set FPSIMD get SVE for VL 7168
3527 16:59:56.361060 # ok 1797 Set SVE VL 7184
3528 16:59:56.361166 # ok 1798 # SKIP SVE set SVE get SVE for VL 7184
3529 16:59:56.361267 # ok 1799 # SKIP SVE set SVE get FPSIMD for VL 7184
3530 16:59:56.361565 # ok 1800 # SKIP SVE set FPSIMD get SVE for VL 7184
3531 16:59:56.361679 # ok 1801 Set SVE VL 7200
3532 16:59:56.361785 # ok 1802 # SKIP SVE set SVE get SVE for VL 7200
3533 16:59:56.362087 # ok 1803 # SKIP SVE set SVE get FPSIMD for VL 7200
3534 16:59:56.362190 # ok 1804 # SKIP SVE set FPSIMD get SVE for VL 7200
3535 16:59:56.362292 # ok 1805 Set SVE VL 7216
3536 16:59:56.362381 # ok 1806 # SKIP SVE set SVE get SVE for VL 7216
3537 16:59:56.362483 # ok 1807 # SKIP SVE set SVE get FPSIMD for VL 7216
3538 16:59:56.362585 # ok 1808 # SKIP SVE set FPSIMD get SVE for VL 7216
3539 16:59:56.362687 # ok 1809 Set SVE VL 7232
3540 16:59:56.362786 # ok 1810 # SKIP SVE set SVE get SVE for VL 7232
3541 16:59:56.363098 # ok 1811 # SKIP SVE set SVE get FPSIMD for VL 7232
3542 16:59:56.363202 # ok 1812 # SKIP SVE set FPSIMD get SVE for VL 7232
3543 16:59:56.363304 # ok 1813 Set SVE VL 7248
3544 16:59:56.363390 # ok 1814 # SKIP SVE set SVE get SVE for VL 7248
3545 16:59:56.363487 # ok 1815 # SKIP SVE set SVE get FPSIMD for VL 7248
3546 16:59:56.363589 # ok 1816 # SKIP SVE set FPSIMD get SVE for VL 7248
3547 16:59:56.363690 # ok 1817 Set SVE VL 7264
3548 16:59:56.363985 # ok 1818 # SKIP SVE set SVE get SVE for VL 7264
3549 16:59:56.364095 # ok 1819 # SKIP SVE set SVE get FPSIMD for VL 7264
3550 16:59:56.364198 # ok 1820 # SKIP SVE set FPSIMD get SVE for VL 7264
3551 16:59:56.364297 # ok 1821 Set SVE VL 7280
3552 16:59:56.364397 # ok 1822 # SKIP SVE set SVE get SVE for VL 7280
3553 16:59:56.364685 # ok 1823 # SKIP SVE set SVE get FPSIMD for VL 7280
3554 16:59:56.364779 # ok 1824 # SKIP SVE set FPSIMD get SVE for VL 7280
3555 16:59:56.364868 # ok 1825 Set SVE VL 7296
3556 16:59:56.364965 # ok 1826 # SKIP SVE set SVE get SVE for VL 7296
3557 16:59:56.365067 # ok 1827 # SKIP SVE set SVE get FPSIMD for VL 7296
3558 16:59:56.365166 # ok 1828 # SKIP SVE set FPSIMD get SVE for VL 7296
3559 16:59:56.365265 # ok 1829 Set SVE VL 7312
3560 16:59:56.365558 # ok 1830 # SKIP SVE set SVE get SVE for VL 7312
3561 16:59:56.365681 # ok 1831 # SKIP SVE set SVE get FPSIMD for VL 7312
3562 16:59:56.365935 # ok 1832 # SKIP SVE set FPSIMD get SVE for VL 7312
3563 16:59:56.366042 # ok 1833 Set SVE VL 7328
3564 16:59:56.366149 # ok 1834 # SKIP SVE set SVE get SVE for VL 7328
3565 16:59:56.366248 # ok 1835 # SKIP SVE set SVE get FPSIMD for VL 7328
3566 16:59:56.366543 # ok 1836 # SKIP SVE set FPSIMD get SVE for VL 7328
3567 16:59:56.366645 # ok 1837 Set SVE VL 7344
3568 16:59:56.366731 # ok 1838 # SKIP SVE set SVE get SVE for VL 7344
3569 16:59:56.366828 # ok 1839 # SKIP SVE set SVE get FPSIMD for VL 7344
3570 16:59:56.366927 # ok 1840 # SKIP SVE set FPSIMD get SVE for VL 7344
3571 16:59:56.367012 # ok 1841 Set SVE VL 7360
3572 16:59:56.367109 # ok 1842 # SKIP SVE set SVE get SVE for VL 7360
3573 16:59:56.367403 # ok 1843 # SKIP SVE set SVE get FPSIMD for VL 7360
3574 16:59:56.367504 # ok 1844 # SKIP SVE set FPSIMD get SVE for VL 7360
3575 16:59:56.367604 # ok 1845 Set SVE VL 7376
3576 16:59:56.367702 # ok 1846 # SKIP SVE set SVE get SVE for VL 7376
3577 16:59:56.367804 # ok 1847 # SKIP SVE set SVE get FPSIMD for VL 7376
3578 16:59:56.368089 # ok 1848 # SKIP SVE set FPSIMD get SVE for VL 7376
3579 16:59:56.368177 # ok 1849 Set SVE VL 7392
3580 16:59:56.368275 # ok 1850 # SKIP SVE set SVE get SVE for VL 7392
3581 16:59:56.368361 # ok 1851 # SKIP SVE set SVE get FPSIMD for VL 7392
3582 16:59:56.368459 # ok 1852 # SKIP SVE set FPSIMD get SVE for VL 7392
3583 16:59:56.368555 # ok 1853 Set SVE VL 7408
3584 16:59:56.368651 # ok 1854 # SKIP SVE set SVE get SVE for VL 7408
3585 16:59:56.368946 # ok 1855 # SKIP SVE set SVE get FPSIMD for VL 7408
3586 16:59:56.369051 # ok 1856 # SKIP SVE set FPSIMD get SVE for VL 7408
3587 16:59:56.369152 # ok 1857 Set SVE VL 7424
3588 16:59:56.369248 # ok 1858 # SKIP SVE set SVE get SVE for VL 7424
3589 16:59:56.369345 # ok 1859 # SKIP SVE set SVE get FPSIMD for VL 7424
3590 16:59:56.369442 # ok 1860 # SKIP SVE set FPSIMD get SVE for VL 7424
3591 16:59:56.373704 # ok 1861 Set SVE VL 7440
3592 16:59:56.373806 # ok 1862 # SKIP SVE set SVE get SVE for VL 7440
3593 16:59:56.373891 # ok 1863 # SKIP SVE set SVE get FPSIMD for VL 7440
3594 16:59:56.373974 # ok 1864 # SKIP SVE set FPSIMD get SVE for VL 7440
3595 16:59:56.374056 # ok 1865 Set SVE VL 7456
3596 16:59:56.374138 # ok 1866 # SKIP SVE set SVE get SVE for VL 7456
3597 16:59:56.374221 # ok 1867 # SKIP SVE set SVE get FPSIMD for VL 7456
3598 16:59:56.374301 # ok 1868 # SKIP SVE set FPSIMD get SVE for VL 7456
3599 16:59:56.374383 # ok 1869 Set SVE VL 7472
3600 16:59:56.374464 # ok 1870 # SKIP SVE set SVE get SVE for VL 7472
3601 16:59:56.374545 # ok 1871 # SKIP SVE set SVE get FPSIMD for VL 7472
3602 16:59:56.374626 # ok 1872 # SKIP SVE set FPSIMD get SVE for VL 7472
3603 16:59:56.374707 # ok 1873 Set SVE VL 7488
3604 16:59:56.374788 # ok 1874 # SKIP SVE set SVE get SVE for VL 7488
3605 16:59:56.374868 # ok 1875 # SKIP SVE set SVE get FPSIMD for VL 7488
3606 16:59:56.374949 # ok 1876 # SKIP SVE set FPSIMD get SVE for VL 7488
3607 16:59:56.375035 # ok 1877 Set SVE VL 7504
3608 16:59:56.375116 # ok 1878 # SKIP SVE set SVE get SVE for VL 7504
3609 16:59:56.375196 # ok 1879 # SKIP SVE set SVE get FPSIMD for VL 7504
3610 16:59:56.375278 # ok 1880 # SKIP SVE set FPSIMD get SVE for VL 7504
3611 16:59:56.375359 # ok 1881 Set SVE VL 7520
3612 16:59:56.375440 # ok 1882 # SKIP SVE set SVE get SVE for VL 7520
3613 16:59:56.375520 # ok 1883 # SKIP SVE set SVE get FPSIMD for VL 7520
3614 16:59:56.375600 # ok 1884 # SKIP SVE set FPSIMD get SVE for VL 7520
3615 16:59:56.375681 # ok 1885 Set SVE VL 7536
3616 16:59:56.375761 # ok 1886 # SKIP SVE set SVE get SVE for VL 7536
3617 16:59:56.375841 # ok 1887 # SKIP SVE set SVE get FPSIMD for VL 7536
3618 16:59:56.375924 # ok 1888 # SKIP SVE set FPSIMD get SVE for VL 7536
3619 16:59:56.376007 # ok 1889 Set SVE VL 7552
3620 16:59:56.376093 # ok 1890 # SKIP SVE set SVE get SVE for VL 7552
3621 16:59:56.376174 # ok 1891 # SKIP SVE set SVE get FPSIMD for VL 7552
3622 16:59:56.376258 # ok 1892 # SKIP SVE set FPSIMD get SVE for VL 7552
3623 16:59:56.376355 # ok 1893 Set SVE VL 7568
3624 16:59:56.376440 # ok 1894 # SKIP SVE set SVE get SVE for VL 7568
3625 16:59:56.376522 # ok 1895 # SKIP SVE set SVE get FPSIMD for VL 7568
3626 16:59:56.376602 # ok 1896 # SKIP SVE set FPSIMD get SVE for VL 7568
3627 16:59:56.376684 # ok 1897 Set SVE VL 7584
3628 16:59:56.376764 # ok 1898 # SKIP SVE set SVE get SVE for VL 7584
3629 16:59:56.376846 # ok 1899 # SKIP SVE set SVE get FPSIMD for VL 7584
3630 16:59:56.376925 # ok 1900 # SKIP SVE set FPSIMD get SVE for VL 7584
3631 16:59:56.377008 # ok 1901 Set SVE VL 7600
3632 16:59:56.377089 # ok 1902 # SKIP SVE set SVE get SVE for VL 7600
3633 16:59:56.377169 # ok 1903 # SKIP SVE set SVE get FPSIMD for VL 7600
3634 16:59:56.377504 # ok 1904 # SKIP SVE set FPSIMD get SVE for VL 7600
3635 16:59:56.377726 # ok 1905 Set SVE VL 7616
3636 16:59:56.377922 # ok 1906 # SKIP SVE set SVE get SVE for VL 7616
3637 16:59:56.378127 # ok 1907 # SKIP SVE set SVE get FPSIMD for VL 7616
3638 16:59:56.378331 # ok 1908 # SKIP SVE set FPSIMD get SVE for VL 7616
3639 16:59:56.378487 # ok 1909 Set SVE VL 7632
3640 16:59:56.378648 # ok 1910 # SKIP SVE set SVE get SVE for VL 7632
3641 16:59:56.378787 # ok 1911 # SKIP SVE set SVE get FPSIMD for VL 7632
3642 16:59:56.378941 # ok 1912 # SKIP SVE set FPSIMD get SVE for VL 7632
3643 16:59:56.379088 # ok 1913 Set SVE VL 7648
3644 16:59:56.379240 # ok 1914 # SKIP SVE set SVE get SVE for VL 7648
3645 16:59:56.379392 # ok 1915 # SKIP SVE set SVE get FPSIMD for VL 7648
3646 16:59:56.379551 # ok 1916 # SKIP SVE set FPSIMD get SVE for VL 7648
3647 16:59:56.379704 # ok 1917 Set SVE VL 7664
3648 16:59:56.379854 # ok 1918 # SKIP SVE set SVE get SVE for VL 7664
3649 16:59:56.380007 # ok 1919 # SKIP SVE set SVE get FPSIMD for VL 7664
3650 16:59:56.380215 # ok 1920 # SKIP SVE set FPSIMD get SVE for VL 7664
3651 16:59:56.380364 # ok 1921 Set SVE VL 7680
3652 16:59:56.380505 # ok 1922 # SKIP SVE set SVE get SVE for VL 7680
3653 16:59:56.380657 # ok 1923 # SKIP SVE set SVE get FPSIMD for VL 7680
3654 16:59:56.380803 # ok 1924 # SKIP SVE set FPSIMD get SVE for VL 7680
3655 16:59:56.380946 # ok 1925 Set SVE VL 7696
3656 16:59:56.381081 # ok 1926 # SKIP SVE set SVE get SVE for VL 7696
3657 16:59:56.381229 # ok 1927 # SKIP SVE set SVE get FPSIMD for VL 7696
3658 16:59:56.381397 # ok 1928 # SKIP SVE set FPSIMD get SVE for VL 7696
3659 16:59:56.381536 # ok 1929 Set SVE VL 7712
3660 16:59:56.381678 # ok 1930 # SKIP SVE set SVE get SVE for VL 7712
3661 16:59:56.381809 # ok 1931 # SKIP SVE set SVE get FPSIMD for VL 7712
3662 16:59:56.381922 # ok 1932 # SKIP SVE set FPSIMD get SVE for VL 7712
3663 16:59:56.382017 # ok 1933 Set SVE VL 7728
3664 16:59:56.382097 # ok 1934 # SKIP SVE set SVE get SVE for VL 7728
3665 16:59:56.382179 # ok 1935 # SKIP SVE set SVE get FPSIMD for VL 7728
3666 16:59:56.382251 # ok 1936 # SKIP SVE set FPSIMD get SVE for VL 7728
3667 16:59:56.382342 # ok 1937 Set SVE VL 7744
3668 16:59:56.382428 # ok 1938 # SKIP SVE set SVE get SVE for VL 7744
3669 16:59:56.382502 # ok 1939 # SKIP SVE set SVE get FPSIMD for VL 7744
3670 16:59:56.382579 # ok 1940 # SKIP SVE set FPSIMD get SVE for VL 7744
3671 16:59:56.382641 # ok 1941 Set SVE VL 7760
3672 16:59:56.382700 # ok 1942 # SKIP SVE set SVE get SVE for VL 7760
3673 16:59:56.382759 # ok 1943 # SKIP SVE set SVE get FPSIMD for VL 7760
3674 16:59:56.382817 # ok 1944 # SKIP SVE set FPSIMD get SVE for VL 7760
3675 16:59:56.382876 # ok 1945 Set SVE VL 7776
3676 16:59:56.382934 # ok 1946 # SKIP SVE set SVE get SVE for VL 7776
3677 16:59:56.383177 # ok 1947 # SKIP SVE set SVE get FPSIMD for VL 7776
3678 16:59:56.383243 # ok 1948 # SKIP SVE set FPSIMD get SVE for VL 7776
3679 16:59:56.383302 # ok 1949 Set SVE VL 7792
3680 16:59:56.383360 # ok 1950 # SKIP SVE set SVE get SVE for VL 7792
3681 16:59:56.383418 # ok 1951 # SKIP SVE set SVE get FPSIMD for VL 7792
3682 16:59:56.383477 # ok 1952 # SKIP SVE set FPSIMD get SVE for VL 7792
3683 16:59:56.383536 # ok 1953 Set SVE VL 7808
3684 16:59:56.383594 # ok 1954 # SKIP SVE set SVE get SVE for VL 7808
3685 16:59:56.383652 # ok 1955 # SKIP SVE set SVE get FPSIMD for VL 7808
3686 16:59:56.385621 # ok 1956 # SKIP SVE set FPSIMD get SVE for VL 7808
3687 16:59:56.386143 # ok 1957 Set SVE VL 7824
3688 16:59:56.386521 # ok 1958 # SKIP SVE set SVE get SVE for VL 7824
3689 16:59:56.386667 # ok 1959 # SKIP SVE set SVE get FPSIMD for VL 7824
3690 16:59:56.386825 # ok 1960 # SKIP SVE set FPSIMD get SVE for VL 7824
3691 16:59:56.386970 # ok 1961 Set SVE VL 7840
3692 16:59:56.387079 # ok 1962 # SKIP SVE set SVE get SVE for VL 7840
3693 16:59:56.387188 # ok 1963 # SKIP SVE set SVE get FPSIMD for VL 7840
3694 16:59:56.387311 # ok 1964 # SKIP SVE set FPSIMD get SVE for VL 7840
3695 16:59:56.387412 # ok 1965 Set SVE VL 7856
3696 16:59:56.387509 # ok 1966 # SKIP SVE set SVE get SVE for VL 7856
3697 16:59:56.387616 # ok 1967 # SKIP SVE set SVE get FPSIMD for VL 7856
3698 16:59:56.387745 # ok 1968 # SKIP SVE set FPSIMD get SVE for VL 7856
3699 16:59:56.387847 # ok 1969 Set SVE VL 7872
3700 16:59:56.387954 # ok 1970 # SKIP SVE set SVE get SVE for VL 7872
3701 16:59:56.388058 # ok 1971 # SKIP SVE set SVE get FPSIMD for VL 7872
3702 16:59:56.388163 # ok 1972 # SKIP SVE set FPSIMD get SVE for VL 7872
3703 16:59:56.388243 # ok 1973 Set SVE VL 7888
3704 16:59:56.388320 # ok 1974 # SKIP SVE set SVE get SVE for VL 7888
3705 16:59:56.389846 # ok 1975 # SKIP SVE set SVE get FPSIMD for VL 7888
3706 16:59:56.389943 # ok 1976 # SKIP SVE set FPSIMD get SVE for VL 7888
3707 16:59:56.390029 # ok 1977 Set SVE VL 7904
3708 16:59:56.390116 # ok 1978 # SKIP SVE set SVE get SVE for VL 7904
3709 16:59:56.390216 # ok 1979 # SKIP SVE set SVE get FPSIMD for VL 7904
3710 16:59:56.390314 # ok 1980 # SKIP SVE set FPSIMD get SVE for VL 7904
3711 16:59:56.390401 # ok 1981 Set SVE VL 7920
3712 16:59:56.390483 # ok 1982 # SKIP SVE set SVE get SVE for VL 7920
3713 16:59:56.390555 # ok 1983 # SKIP SVE set SVE get FPSIMD for VL 7920
3714 16:59:56.390618 # ok 1984 # SKIP SVE set FPSIMD get SVE for VL 7920
3715 16:59:56.390680 # ok 1985 Set SVE VL 7936
3716 16:59:56.390741 # ok 1986 # SKIP SVE set SVE get SVE for VL 7936
3717 16:59:56.390810 # ok 1987 # SKIP SVE set SVE get FPSIMD for VL 7936
3718 16:59:56.390882 # ok 1988 # SKIP SVE set FPSIMD get SVE for VL 7936
3719 16:59:56.390954 # ok 1989 Set SVE VL 7952
3720 16:59:56.391028 # ok 1990 # SKIP SVE set SVE get SVE for VL 7952
3721 16:59:56.391104 # ok 1991 # SKIP SVE set SVE get FPSIMD for VL 7952
3722 16:59:56.391170 # ok 1992 # SKIP SVE set FPSIMD get SVE for VL 7952
3723 16:59:56.391249 # ok 1993 Set SVE VL 7968
3724 16:59:56.391325 # ok 1994 # SKIP SVE set SVE get SVE for VL 7968
3725 16:59:56.391389 # ok 1995 # SKIP SVE set SVE get FPSIMD for VL 7968
3726 16:59:56.391455 # ok 1996 # SKIP SVE set FPSIMD get SVE for VL 7968
3727 16:59:56.391689 # ok 1997 Set SVE VL 7984
3728 16:59:56.391776 # ok 1998 # SKIP SVE set SVE get SVE for VL 7984
3729 16:59:56.391855 # ok 1999 # SKIP SVE set SVE get FPSIMD for VL 7984
3730 16:59:56.391934 # ok 2000 # SKIP SVE set FPSIMD get SVE for VL 7984
3731 16:59:56.392008 # ok 2001 Set SVE VL 8000
3732 16:59:56.392079 # ok 2002 # SKIP SVE set SVE get SVE for VL 8000
3733 16:59:56.392150 # ok 2003 # SKIP SVE set SVE get FPSIMD for VL 8000
3734 16:59:56.392228 # ok 2004 # SKIP SVE set FPSIMD get SVE for VL 8000
3735 16:59:56.392313 # ok 2005 Set SVE VL 8016
3736 16:59:56.392393 # ok 2006 # SKIP SVE set SVE get SVE for VL 8016
3737 16:59:56.392471 # ok 2007 # SKIP SVE set SVE get FPSIMD for VL 8016
3738 16:59:56.392551 # ok 2008 # SKIP SVE set FPSIMD get SVE for VL 8016
3739 16:59:56.392631 # ok 2009 Set SVE VL 8032
3740 16:59:56.392716 # ok 2010 # SKIP SVE set SVE get SVE for VL 8032
3741 16:59:56.392785 # ok 2011 # SKIP SVE set SVE get FPSIMD for VL 8032
3742 16:59:56.392856 # ok 2012 # SKIP SVE set FPSIMD get SVE for VL 8032
3743 16:59:56.392947 # ok 2013 Set SVE VL 8048
3744 16:59:56.393032 # ok 2014 # SKIP SVE set SVE get SVE for VL 8048
3745 16:59:56.393115 # ok 2015 # SKIP SVE set SVE get FPSIMD for VL 8048
3746 16:59:56.393216 # ok 2016 # SKIP SVE set FPSIMD get SVE for VL 8048
3747 16:59:56.393321 # ok 2017 Set SVE VL 8064
3748 16:59:56.393406 # ok 2018 # SKIP SVE set SVE get SVE for VL 8064
3749 16:59:56.393495 # ok 2019 # SKIP SVE set SVE get FPSIMD for VL 8064
3750 16:59:56.393573 # ok 2020 # SKIP SVE set FPSIMD get SVE for VL 8064
3751 16:59:56.393637 # ok 2021 Set SVE VL 8080
3752 16:59:56.393709 # ok 2022 # SKIP SVE set SVE get SVE for VL 8080
3753 16:59:56.393803 # ok 2023 # SKIP SVE set SVE get FPSIMD for VL 8080
3754 16:59:56.393892 # ok 2024 # SKIP SVE set FPSIMD get SVE for VL 8080
3755 16:59:56.393984 # ok 2025 Set SVE VL 8096
3756 16:59:56.394078 # ok 2026 # SKIP SVE set SVE get SVE for VL 8096
3757 16:59:56.394181 # ok 2027 # SKIP SVE set SVE get FPSIMD for VL 8096
3758 16:59:56.394289 # ok 2028 # SKIP SVE set FPSIMD get SVE for VL 8096
3759 16:59:56.394379 # ok 2029 Set SVE VL 8112
3760 16:59:56.394493 # ok 2030 # SKIP SVE set SVE get SVE for VL 8112
3761 16:59:56.394594 # ok 2031 # SKIP SVE set SVE get FPSIMD for VL 8112
3762 16:59:56.394698 # ok 2032 # SKIP SVE set FPSIMD get SVE for VL 8112
3763 16:59:56.394800 # ok 2033 Set SVE VL 8128
3764 16:59:56.394907 # ok 2034 # SKIP SVE set SVE get SVE for VL 8128
3765 16:59:56.394995 # ok 2035 # SKIP SVE set SVE get FPSIMD for VL 8128
3766 16:59:56.395090 # ok 2036 # SKIP SVE set FPSIMD get SVE for VL 8128
3767 16:59:56.395169 # ok 2037 Set SVE VL 8144
3768 16:59:56.395263 # ok 2038 # SKIP SVE set SVE get SVE for VL 8144
3769 16:59:56.395342 # ok 2039 # SKIP SVE set SVE get FPSIMD for VL 8144
3770 16:59:56.395654 # ok 2040 # SKIP SVE set FPSIMD get SVE for VL 8144
3771 16:59:56.395803 # ok 2041 Set SVE VL 8160
3772 16:59:56.395926 # ok 2042 # SKIP SVE set SVE get SVE for VL 8160
3773 16:59:56.396059 # ok 2043 # SKIP SVE set SVE get FPSIMD for VL 8160
3774 16:59:56.396132 # ok 2044 # SKIP SVE set FPSIMD get SVE for VL 8160
3775 16:59:56.396209 # ok 2045 Set SVE VL 8176
3776 16:59:56.396299 # ok 2046 # SKIP SVE set SVE get SVE for VL 8176
3777 16:59:56.396391 # ok 2047 # SKIP SVE set SVE get FPSIMD for VL 8176
3778 16:59:56.396495 # ok 2048 # SKIP SVE set FPSIMD get SVE for VL 8176
3779 16:59:56.396784 # ok 2049 Set SVE VL 8192
3780 16:59:56.396870 # ok 2050 # SKIP SVE set SVE get SVE for VL 8192
3781 16:59:56.396963 # ok 2051 # SKIP SVE set SVE get FPSIMD for VL 8192
3782 16:59:56.397064 # ok 2052 # SKIP SVE set FPSIMD get SVE for VL 8192
3783 16:59:56.397159 # ok 2053 Streaming SVE FPSIMD set via SVE: 0
3784 16:59:56.397464 # ok 2054 Streaming SVE get_fpsimd() gave same state
3785 16:59:56.397588 # ok 2055 Streaming SVE SVE_PT_VL_INHERIT set
3786 16:59:56.397879 # ok 2056 Streaming SVE SVE_PT_VL_INHERIT cleared
3787 16:59:56.397980 # ok 2057 Set Streaming SVE VL 16
3788 16:59:56.398103 # ok 2058 Set and get Streaming SVE data for VL 16
3789 16:59:56.398239 # ok 2059 Set and get FPSIMD data for Streaming SVE VL 16
3790 16:59:56.398365 # ok 2060 Set FPSIMD, read via SVE for Streaming SVE VL 16
3791 16:59:56.398457 # ok 2061 Set Streaming SVE VL 32
3792 16:59:56.398560 # ok 2062 Set and get Streaming SVE data for VL 32
3793 16:59:56.398669 # ok 2063 Set and get FPSIMD data for Streaming SVE VL 32
3794 16:59:56.398979 # ok 2064 Set FPSIMD, read via SVE for Streaming SVE VL 32
3795 16:59:56.399078 # ok 2065 Set Streaming SVE VL 48
3796 16:59:56.399177 # ok 2066 # SKIP Streaming SVE set SVE get SVE for VL 48
3797 16:59:56.399266 # ok 2067 # SKIP Streaming SVE set SVE get FPSIMD for VL 48
3798 16:59:56.399537 # ok 2068 # SKIP Streaming SVE set FPSIMD get SVE for VL 48
3799 16:59:56.399643 # ok 2069 Set Streaming SVE VL 64
3800 16:59:56.399745 # ok 2070 Set and get Streaming SVE data for VL 64
3801 16:59:56.399845 # ok 2071 Set and get FPSIMD data for Streaming SVE VL 64
3802 16:59:56.400130 # ok 2072 Set FPSIMD, read via SVE for Streaming SVE VL 64
3803 16:59:56.400228 # ok 2073 Set Streaming SVE VL 80
3804 16:59:56.400307 # ok 2074 # SKIP Streaming SVE set SVE get SVE for VL 80
3805 16:59:56.400427 # ok 2075 # SKIP Streaming SVE set SVE get FPSIMD for VL 80
3806 16:59:56.400539 # ok 2076 # SKIP Streaming SVE set FPSIMD get SVE for VL 80
3807 16:59:56.400811 # ok 2077 Set Streaming SVE VL 96
3808 16:59:56.400917 # ok 2078 # SKIP Streaming SVE set SVE get SVE for VL 96
3809 16:59:56.401029 # ok 2079 # SKIP Streaming SVE set SVE get FPSIMD for VL 96
3810 16:59:56.401151 # ok 2080 # SKIP Streaming SVE set FPSIMD get SVE for VL 96
3811 16:59:56.401265 # ok 2081 Set Streaming SVE VL 112
3812 16:59:56.401387 # ok 2082 # SKIP Streaming SVE set SVE get SVE for VL 112
3813 16:59:56.401703 # ok 2083 # SKIP Streaming SVE set SVE get FPSIMD for VL 112
3814 16:59:56.401810 # ok 2084 # SKIP Streaming SVE set FPSIMD get SVE for VL 112
3815 16:59:56.401911 # ok 2085 Set Streaming SVE VL 128
3816 16:59:56.402008 # ok 2086 Set and get Streaming SVE data for VL 128
3817 16:59:56.402097 # ok 2087 Set and get FPSIMD data for Streaming SVE VL 128
3818 16:59:56.402377 # ok 2088 Set FPSIMD, read via SVE for Streaming SVE VL 128
3819 16:59:56.402472 # ok 2089 Set Streaming SVE VL 144
3820 16:59:56.402588 # ok 2090 # SKIP Streaming SVE set SVE get SVE for VL 144
3821 16:59:56.402713 # ok 2091 # SKIP Streaming SVE set SVE get FPSIMD for VL 144
3822 16:59:56.403029 # ok 2092 # SKIP Streaming SVE set FPSIMD get SVE for VL 144
3823 16:59:56.403124 # ok 2093 Set Streaming SVE VL 160
3824 16:59:56.403238 # ok 2094 # SKIP Streaming SVE set SVE get SVE for VL 160
3825 16:59:56.403351 # ok 2095 # SKIP Streaming SVE set SVE get FPSIMD for VL 160
3826 16:59:56.403436 # ok 2096 # SKIP Streaming SVE set FPSIMD get SVE for VL 160
3827 16:59:56.403535 # ok 2097 Set Streaming SVE VL 176
3828 16:59:56.403632 # ok 2098 # SKIP Streaming SVE set SVE get SVE for VL 176
3829 16:59:56.403735 # ok 2099 # SKIP Streaming SVE set SVE get FPSIMD for VL 176
3830 16:59:56.403847 # ok 2100 # SKIP Streaming SVE set FPSIMD get SVE for VL 176
3831 16:59:56.403971 # ok 2101 Set Streaming SVE VL 192
3832 16:59:56.404086 # ok 2102 # SKIP Streaming SVE set SVE get SVE for VL 192
3833 16:59:56.404390 # ok 2103 # SKIP Streaming SVE set SVE get FPSIMD for VL 192
3834 16:59:56.404483 # ok 2104 # SKIP Streaming SVE set FPSIMD get SVE for VL 192
3835 16:59:56.404600 # ok 2105 Set Streaming SVE VL 208
3836 16:59:56.404699 # ok 2106 # SKIP Streaming SVE set SVE get SVE for VL 208
3837 16:59:56.404819 # ok 2107 # SKIP Streaming SVE set SVE get FPSIMD for VL 208
3838 16:59:56.404926 # ok 2108 # SKIP Streaming SVE set FPSIMD get SVE for VL 208
3839 16:59:56.405037 # ok 2109 Set Streaming SVE VL 224
3840 16:59:56.405136 # ok 2110 # SKIP Streaming SVE set SVE get SVE for VL 224
3841 16:59:56.405238 # ok 2111 # SKIP Streaming SVE set SVE get FPSIMD for VL 224
3842 16:59:56.405340 # ok 2112 # SKIP Streaming SVE set FPSIMD get SVE for VL 224
3843 16:59:56.405449 # ok 2113 Set Streaming SVE VL 240
3844 16:59:56.405929 # ok 2114 # SKIP Streaming SVE set SVE get SVE for VL 240
3845 16:59:56.406027 # ok 2115 # SKIP Streaming SVE set SVE get FPSIMD for VL 240
3846 16:59:56.406148 # ok 2116 # SKIP Streaming SVE set FPSIMD get SVE for VL 240
3847 16:59:56.406251 # ok 2117 Set Streaming SVE VL 256
3848 16:59:56.406373 # ok 2118 Set and get Streaming SVE data for VL 256
3849 16:59:56.406710 # ok 2119 Set and get FPSIMD data for Streaming SVE VL 256
3850 16:59:56.406858 # ok 2120 Set FPSIMD, read via SVE for Streaming SVE VL 256
3851 16:59:56.406988 # ok 2121 Set Streaming SVE VL 272
3852 16:59:56.407128 # ok 2122 # SKIP Streaming SVE set SVE get SVE for VL 272
3853 16:59:56.407226 # ok 2123 # SKIP Streaming SVE set SVE get FPSIMD for VL 272
3854 16:59:56.407323 # ok 2124 # SKIP Streaming SVE set FPSIMD get SVE for VL 272
3855 16:59:56.407389 # ok 2125 Set Streaming SVE VL 288
3856 16:59:56.409521 # ok 2126 # SKIP Streaming SVE set SVE get SVE for VL 288
3857 16:59:56.410088 # ok 2127 # SKIP Streaming SVE set SVE get FPSIMD for VL 288
3858 16:59:56.410390 # ok 2128 # SKIP Streaming SVE set FPSIMD get SVE for VL 288
3859 16:59:56.410483 # ok 2129 Set Streaming SVE VL 304
3860 16:59:56.410583 # ok 2130 # SKIP Streaming SVE set SVE get SVE for VL 304
3861 16:59:56.410683 # ok 2131 # SKIP Streaming SVE set SVE get FPSIMD for VL 304
3862 16:59:56.410983 # ok 2132 # SKIP Streaming SVE set FPSIMD get SVE for VL 304
3863 16:59:56.411086 # ok 2133 Set Streaming SVE VL 320
3864 16:59:56.411188 # ok 2134 # SKIP Streaming SVE set SVE get SVE for VL 320
3865 16:59:56.411277 # ok 2135 # SKIP Streaming SVE set SVE get FPSIMD for VL 320
3866 16:59:56.411399 # ok 2136 # SKIP Streaming SVE set FPSIMD get SVE for VL 320
3867 16:59:56.411514 # ok 2137 Set Streaming SVE VL 336
3868 16:59:56.411795 # ok 2138 # SKIP Streaming SVE set SVE get SVE for VL 336
3869 16:59:56.411900 # ok 2139 # SKIP Streaming SVE set SVE get FPSIMD for VL 336
3870 16:59:56.412002 # ok 2140 # SKIP Streaming SVE set FPSIMD get SVE for VL 336
3871 16:59:56.412105 # ok 2141 Set Streaming SVE VL 352
3872 16:59:56.412398 # ok 2142 # SKIP Streaming SVE set SVE get SVE for VL 352
3873 16:59:56.412500 # ok 2143 # SKIP Streaming SVE set SVE get FPSIMD for VL 352
3874 16:59:56.412603 # ok 2144 # SKIP Streaming SVE set FPSIMD get SVE for VL 352
3875 16:59:56.412705 # ok 2145 Set Streaming SVE VL 368
3876 16:59:56.412826 # ok 2146 # SKIP Streaming SVE set SVE get SVE for VL 368
3877 16:59:56.413121 # ok 2147 # SKIP Streaming SVE set SVE get FPSIMD for VL 368
3878 16:59:56.413238 # ok 2148 # SKIP Streaming SVE set FPSIMD get SVE for VL 368
3879 16:59:56.413499 # ok 2149 Set Streaming SVE VL 384
3880 16:59:56.413596 # ok 2150 # SKIP Streaming SVE set SVE get SVE for VL 384
3881 16:59:56.413699 # ok 2151 # SKIP Streaming SVE set SVE get FPSIMD for VL 384
3882 16:59:56.414003 # ok 2152 # SKIP Streaming SVE set FPSIMD get SVE for VL 384
3883 16:59:56.414110 # ok 2153 Set Streaming SVE VL 400
3884 16:59:56.414222 # ok 2154 # SKIP Streaming SVE set SVE get SVE for VL 400
3885 16:59:56.414332 # ok 2155 # SKIP Streaming SVE set SVE get FPSIMD for VL 400
3886 16:59:56.414433 # ok 2156 # SKIP Streaming SVE set FPSIMD get SVE for VL 400
3887 16:59:56.414544 # ok 2157 Set Streaming SVE VL 416
3888 16:59:56.414850 # ok 2158 # SKIP Streaming SVE set SVE get SVE for VL 416
3889 16:59:56.414976 # ok 2159 # SKIP Streaming SVE set SVE get FPSIMD for VL 416
3890 16:59:56.415087 # ok 2160 # SKIP Streaming SVE set FPSIMD get SVE for VL 416
3891 16:59:56.415397 # ok 2161 Set Streaming SVE VL 432
3892 16:59:56.415499 # ok 2162 # SKIP Streaming SVE set SVE get SVE for VL 432
3893 16:59:56.415601 # ok 2163 # SKIP Streaming SVE set SVE get FPSIMD for VL 432
3894 16:59:56.415705 # ok 2164 # SKIP Streaming SVE set FPSIMD get SVE for VL 432
3895 16:59:56.415805 # ok 2165 Set Streaming SVE VL 448
3896 16:59:56.416114 # ok 2166 # SKIP Streaming SVE set SVE get SVE for VL 448
3897 16:59:56.416228 # ok 2167 # SKIP Streaming SVE set SVE get FPSIMD for VL 448
3898 16:59:56.416331 # ok 2168 # SKIP Streaming SVE set FPSIMD get SVE for VL 448
3899 16:59:56.416622 # ok 2169 Set Streaming SVE VL 464
3900 16:59:56.416723 # ok 2170 # SKIP Streaming SVE set SVE get SVE for VL 464
3901 16:59:56.416825 # ok 2171 # SKIP Streaming SVE set SVE get FPSIMD for VL 464
3902 16:59:56.416938 # ok 2172 # SKIP Streaming SVE set FPSIMD get SVE for VL 464
3903 16:59:56.417040 # ok 2173 Set Streaming SVE VL 480
3904 16:59:56.417142 # ok 2174 # SKIP Streaming SVE set SVE get SVE for VL 480
3905 16:59:56.417438 # ok 2175 # SKIP Streaming SVE set SVE get FPSIMD for VL 480
3906 16:59:56.417753 # ok 2176 # SKIP Streaming SVE set FPSIMD get SVE for VL 480
3907 16:59:56.417849 # ok 2177 Set Streaming SVE VL 496
3908 16:59:56.417942 # ok 2178 # SKIP Streaming SVE set SVE get SVE for VL 496
3909 16:59:56.418033 # ok 2179 # SKIP Streaming SVE set SVE get FPSIMD for VL 496
3910 16:59:56.418321 # ok 2180 # SKIP Streaming SVE set FPSIMD get SVE for VL 496
3911 16:59:56.418422 # ok 2181 Set Streaming SVE VL 512
3912 16:59:56.418523 # ok 2182 # SKIP Streaming SVE set SVE get SVE for VL 512
3913 16:59:56.418624 # ok 2183 # SKIP Streaming SVE set SVE get FPSIMD for VL 512
3914 16:59:56.418923 # ok 2184 # SKIP Streaming SVE set FPSIMD get SVE for VL 512
3915 16:59:56.419023 # ok 2185 Set Streaming SVE VL 528
3916 16:59:56.419127 # ok 2186 # SKIP Streaming SVE set SVE get SVE for VL 528
3917 16:59:56.419227 # ok 2187 # SKIP Streaming SVE set SVE get FPSIMD for VL 528
3918 16:59:56.419524 # ok 2188 # SKIP Streaming SVE set FPSIMD get SVE for VL 528
3919 16:59:56.419625 # ok 2189 Set Streaming SVE VL 544
3920 16:59:56.419739 # ok 2190 # SKIP Streaming SVE set SVE get SVE for VL 544
3921 16:59:56.419823 # ok 2191 # SKIP Streaming SVE set SVE get FPSIMD for VL 544
3922 16:59:56.419913 # ok 2192 # SKIP Streaming SVE set FPSIMD get SVE for VL 544
3923 16:59:56.420008 # ok 2193 Set Streaming SVE VL 560
3924 16:59:56.420098 # ok 2194 # SKIP Streaming SVE set SVE get SVE for VL 560
3925 16:59:56.420411 # ok 2195 # SKIP Streaming SVE set SVE get FPSIMD for VL 560
3926 16:59:56.420513 # ok 2196 # SKIP Streaming SVE set FPSIMD get SVE for VL 560
3927 16:59:56.420607 # ok 2197 Set Streaming SVE VL 576
3928 16:59:56.420707 # ok 2198 # SKIP Streaming SVE set SVE get SVE for VL 576
3929 16:59:56.420807 # ok 2199 # SKIP Streaming SVE set SVE get FPSIMD for VL 576
3930 16:59:56.420907 # ok 2200 # SKIP Streaming SVE set FPSIMD get SVE for VL 576
3931 16:59:56.421012 # ok 2201 Set Streaming SVE VL 592
3932 16:59:56.421308 # ok 2202 # SKIP Streaming SVE set SVE get SVE for VL 592
3933 16:59:56.421477 # ok 2203 # SKIP Streaming SVE set SVE get FPSIMD for VL 592
3934 16:59:56.421618 # ok 2204 # SKIP Streaming SVE set FPSIMD get SVE for VL 592
3935 16:59:56.421772 # ok 2205 Set Streaming SVE VL 608
3936 16:59:56.421915 # ok 2206 # SKIP Streaming SVE set SVE get SVE for VL 608
3937 16:59:56.422058 # ok 2207 # SKIP Streaming SVE set SVE get FPSIMD for VL 608
3938 16:59:56.422159 # ok 2208 # SKIP Streaming SVE set FPSIMD get SVE for VL 608
3939 16:59:56.422250 # ok 2209 Set Streaming SVE VL 624
3940 16:59:56.422348 # ok 2210 # SKIP Streaming SVE set SVE get SVE for VL 624
3941 16:59:56.422633 # ok 2211 # SKIP Streaming SVE set SVE get FPSIMD for VL 624
3942 16:59:56.422735 # ok 2212 # SKIP Streaming SVE set FPSIMD get SVE for VL 624
3943 16:59:56.422808 # ok 2213 Set Streaming SVE VL 640
3944 16:59:56.422900 # ok 2214 # SKIP Streaming SVE set SVE get SVE for VL 640
3945 16:59:56.422987 # ok 2215 # SKIP Streaming SVE set SVE get FPSIMD for VL 640
3946 16:59:56.423260 # ok 2216 # SKIP Streaming SVE set FPSIMD get SVE for VL 640
3947 16:59:56.423345 # ok 2217 Set Streaming SVE VL 656
3948 16:59:56.423441 # ok 2218 # SKIP Streaming SVE set SVE get SVE for VL 656
3949 16:59:56.423542 # ok 2219 # SKIP Streaming SVE set SVE get FPSIMD for VL 656
3950 16:59:56.423643 # ok 2220 # SKIP Streaming SVE set FPSIMD get SVE for VL 656
3951 16:59:56.423765 # ok 2221 Set Streaming SVE VL 672
3952 16:59:56.423881 # ok 2222 # SKIP Streaming SVE set SVE get SVE for VL 672
3953 16:59:56.424011 # ok 2223 # SKIP Streaming SVE set SVE get FPSIMD for VL 672
3954 16:59:56.424391 # ok 2224 # SKIP Streaming SVE set FPSIMD get SVE for VL 672
3955 16:59:56.424488 # ok 2225 Set Streaming SVE VL 688
3956 16:59:56.424581 # ok 2226 # SKIP Streaming SVE set SVE get SVE for VL 688
3957 16:59:56.424687 # ok 2227 # SKIP Streaming SVE set SVE get FPSIMD for VL 688
3958 16:59:56.424796 # ok 2228 # SKIP Streaming SVE set FPSIMD get SVE for VL 688
3959 16:59:56.424909 # ok 2229 Set Streaming SVE VL 704
3960 16:59:56.425247 # ok 2230 # SKIP Streaming SVE set SVE get SVE for VL 704
3961 16:59:56.425356 # ok 2231 # SKIP Streaming SVE set SVE get FPSIMD for VL 704
3962 16:59:56.425480 # ok 2232 # SKIP Streaming SVE set FPSIMD get SVE for VL 704
3963 16:59:56.425582 # ok 2233 Set Streaming SVE VL 720
3964 16:59:56.425699 # ok 2234 # SKIP Streaming SVE set SVE get SVE for VL 720
3965 16:59:56.425998 # ok 2235 # SKIP Streaming SVE set SVE get FPSIMD for VL 720
3966 16:59:56.426125 # ok 2236 # SKIP Streaming SVE set FPSIMD get SVE for VL 720
3967 16:59:56.426241 # ok 2237 Set Streaming SVE VL 736
3968 16:59:56.426356 # ok 2238 # SKIP Streaming SVE set SVE get SVE for VL 736
3969 16:59:56.426475 # ok 2239 # SKIP Streaming SVE set SVE get FPSIMD for VL 736
3970 16:59:56.426781 # ok 2240 # SKIP Streaming SVE set FPSIMD get SVE for VL 736
3971 16:59:56.426885 # ok 2241 Set Streaming SVE VL 752
3972 16:59:56.426978 # ok 2242 # SKIP Streaming SVE set SVE get SVE for VL 752
3973 16:59:56.427076 # ok 2243 # SKIP Streaming SVE set SVE get FPSIMD for VL 752
3974 16:59:56.427179 # ok 2244 # SKIP Streaming SVE set FPSIMD get SVE for VL 752
3975 16:59:56.427281 # ok 2245 Set Streaming SVE VL 768
3976 16:59:56.427608 # ok 2246 # SKIP Streaming SVE set SVE get SVE for VL 768
3977 16:59:56.427721 # ok 2247 # SKIP Streaming SVE set SVE get FPSIMD for VL 768
3978 16:59:56.427822 # ok 2248 # SKIP Streaming SVE set FPSIMD get SVE for VL 768
3979 16:59:56.427901 # ok 2249 Set Streaming SVE VL 784
3980 16:59:56.428182 # ok 2250 # SKIP Streaming SVE set SVE get SVE for VL 784
3981 16:59:56.428287 # ok 2251 # SKIP Streaming SVE set SVE get FPSIMD for VL 784
3982 16:59:56.428398 # ok 2252 # SKIP Streaming SVE set FPSIMD get SVE for VL 784
3983 16:59:56.428498 # ok 2253 Set Streaming SVE VL 800
3984 16:59:56.428594 # ok 2254 # SKIP Streaming SVE set SVE get SVE for VL 800
3985 16:59:56.428880 # ok 2255 # SKIP Streaming SVE set SVE get FPSIMD for VL 800
3986 16:59:56.428990 # ok 2256 # SKIP Streaming SVE set FPSIMD get SVE for VL 800
3987 16:59:56.429071 # ok 2257 Set Streaming SVE VL 816
3988 16:59:56.429156 # ok 2258 # SKIP Streaming SVE set SVE get SVE for VL 816
3989 16:59:56.429240 # ok 2259 # SKIP Streaming SVE set SVE get FPSIMD for VL 816
3990 16:59:56.429532 # ok 2260 # SKIP Streaming SVE set FPSIMD get SVE for VL 816
3991 16:59:56.429628 # ok 2261 Set Streaming SVE VL 832
3992 16:59:56.429733 # ok 2262 # SKIP Streaming SVE set SVE get SVE for VL 832
3993 16:59:56.429832 # ok 2263 # SKIP Streaming SVE set SVE get FPSIMD for VL 832
3994 16:59:56.430132 # ok 2264 # SKIP Streaming SVE set FPSIMD get SVE for VL 832
3995 16:59:56.430212 # ok 2265 Set Streaming SVE VL 848
3996 16:59:56.430304 # ok 2266 # SKIP Streaming SVE set SVE get SVE for VL 848
3997 16:59:56.430397 # ok 2267 # SKIP Streaming SVE set SVE get FPSIMD for VL 848
3998 16:59:56.430491 # ok 2268 # SKIP Streaming SVE set FPSIMD get SVE for VL 848
3999 16:59:56.430614 # ok 2269 Set Streaming SVE VL 864
4000 16:59:56.430751 # ok 2270 # SKIP Streaming SVE set SVE get SVE for VL 864
4001 16:59:56.430886 # ok 2271 # SKIP Streaming SVE set SVE get FPSIMD for VL 864
4002 16:59:56.431004 # ok 2272 # SKIP Streaming SVE set FPSIMD get SVE for VL 864
4003 16:59:56.431118 # ok 2273 Set Streaming SVE VL 880
4004 16:59:56.431441 # ok 2274 # SKIP Streaming SVE set SVE get SVE for VL 880
4005 16:59:56.431536 # ok 2275 # SKIP Streaming SVE set SVE get FPSIMD for VL 880
4006 16:59:56.431621 # ok 2276 # SKIP Streaming SVE set FPSIMD get SVE for VL 880
4007 16:59:56.431705 # ok 2277 Set Streaming SVE VL 896
4008 16:59:56.431978 # ok 2278 # SKIP Streaming SVE set SVE get SVE for VL 896
4009 16:59:56.434880 # ok 2279 # SKIP Streaming SVE set SVE get FPSIMD for VL 896
4010 16:59:56.435046 # ok 2280 # SKIP Streaming SVE set FPSIMD get SVE for VL 896
4011 16:59:56.435192 # ok 2281 Set Streaming SVE VL 912
4012 16:59:56.435336 # ok 2282 # SKIP Streaming SVE set SVE get SVE for VL 912
4013 16:59:56.435514 # ok 2283 # SKIP Streaming SVE set SVE get FPSIMD for VL 912
4014 16:59:56.435653 # ok 2284 # SKIP Streaming SVE set FPSIMD get SVE for VL 912
4015 16:59:56.435799 # ok 2285 Set Streaming SVE VL 928
4016 16:59:56.435966 # ok 2286 # SKIP Streaming SVE set SVE get SVE for VL 928
4017 16:59:56.436133 # ok 2287 # SKIP Streaming SVE set SVE get FPSIMD for VL 928
4018 16:59:56.436284 # ok 2288 # SKIP Streaming SVE set FPSIMD get SVE for VL 928
4019 16:59:56.436474 # ok 2289 Set Streaming SVE VL 944
4020 16:59:56.436627 # ok 2290 # SKIP Streaming SVE set SVE get SVE for VL 944
4021 16:59:56.436795 # ok 2291 # SKIP Streaming SVE set SVE get FPSIMD for VL 944
4022 16:59:56.436962 # ok 2292 # SKIP Streaming SVE set FPSIMD get SVE for VL 944
4023 16:59:56.437154 # ok 2293 Set Streaming SVE VL 960
4024 16:59:56.437292 # ok 2294 # SKIP Streaming SVE set SVE get SVE for VL 960
4025 16:59:56.437446 # ok 2295 # SKIP Streaming SVE set SVE get FPSIMD for VL 960
4026 16:59:56.437554 # ok 2296 # SKIP Streaming SVE set FPSIMD get SVE for VL 960
4027 16:59:56.437643 # ok 2297 Set Streaming SVE VL 976
4028 16:59:56.437760 # ok 2298 # SKIP Streaming SVE set SVE get SVE for VL 976
4029 16:59:56.438105 # ok 2299 # SKIP Streaming SVE set SVE get FPSIMD for VL 976
4030 16:59:56.438271 # ok 2300 # SKIP Streaming SVE set FPSIMD get SVE for VL 976
4031 16:59:56.438404 # ok 2301 Set Streaming SVE VL 992
4032 16:59:56.438573 # ok 2302 # SKIP Streaming SVE set SVE get SVE for VL 992
4033 16:59:56.438735 # ok 2303 # SKIP Streaming SVE set SVE get FPSIMD for VL 992
4034 16:59:56.438933 # ok 2304 # SKIP Streaming SVE set FPSIMD get SVE for VL 992
4035 16:59:56.439093 # ok 2305 Set Streaming SVE VL 1008
4036 16:59:56.439222 # ok 2306 # SKIP Streaming SVE set SVE get SVE for VL 1008
4037 16:59:56.439309 # ok 2307 # SKIP Streaming SVE set SVE get FPSIMD for VL 1008
4038 16:59:56.439414 # ok 2308 # SKIP Streaming SVE set FPSIMD get SVE for VL 1008
4039 16:59:56.439500 # ok 2309 Set Streaming SVE VL 1024
4040 16:59:56.439790 # ok 2310 # SKIP Streaming SVE set SVE get SVE for VL 1024
4041 16:59:56.439887 # ok 2311 # SKIP Streaming SVE set SVE get FPSIMD for VL 1024
4042 16:59:56.439996 # ok 2312 # SKIP Streaming SVE set FPSIMD get SVE for VL 1024
4043 16:59:56.440113 # ok 2313 Set Streaming SVE VL 1040
4044 16:59:56.440217 # ok 2314 # SKIP Streaming SVE set SVE get SVE for VL 1040
4045 16:59:56.440519 # ok 2315 # SKIP Streaming SVE set SVE get FPSIMD for VL 1040
4046 16:59:56.440626 # ok 2316 # SKIP Streaming SVE set FPSIMD get SVE for VL 1040
4047 16:59:56.440731 # ok 2317 Set Streaming SVE VL 1056
4048 16:59:56.440832 # ok 2318 # SKIP Streaming SVE set SVE get SVE for VL 1056
4049 16:59:56.441156 # ok 2319 # SKIP Streaming SVE set SVE get FPSIMD for VL 1056
4050 16:59:56.441266 # ok 2320 # SKIP Streaming SVE set FPSIMD get SVE for VL 1056
4051 16:59:56.441368 # ok 2321 Set Streaming SVE VL 1072
4052 16:59:56.441471 # ok 2322 # SKIP Streaming SVE set SVE get SVE for VL 1072
4053 16:59:56.441773 # ok 2323 # SKIP Streaming SVE set SVE get FPSIMD for VL 1072
4054 16:59:56.441884 # ok 2324 # SKIP Streaming SVE set FPSIMD get SVE for VL 1072
4055 16:59:56.441984 # ok 2325 Set Streaming SVE VL 1088
4056 16:59:56.442278 # ok 2326 # SKIP Streaming SVE set SVE get SVE for VL 1088
4057 16:59:56.442398 # ok 2327 # SKIP Streaming SVE set SVE get FPSIMD for VL 1088
4058 16:59:56.442529 # ok 2328 # SKIP Streaming SVE set FPSIMD get SVE for VL 1088
4059 16:59:56.442647 # ok 2329 Set Streaming SVE VL 1104
4060 16:59:56.442746 # ok 2330 # SKIP Streaming SVE set SVE get SVE for VL 1104
4061 16:59:56.442846 # ok 2331 # SKIP Streaming SVE set SVE get FPSIMD for VL 1104
4062 16:59:56.443055 # ok 2332 # SKIP Streaming SVE set FPSIMD get SVE for VL 1104
4063 16:59:56.443170 # ok 2333 Set Streaming SVE VL 1120
4064 16:59:56.443268 # ok 2334 # SKIP Streaming SVE set SVE get SVE for VL 1120
4065 16:59:56.443370 # ok 2335 # SKIP Streaming SVE set SVE get FPSIMD for VL 1120
4066 16:59:56.443520 # ok 2336 # SKIP Streaming SVE set FPSIMD get SVE for VL 1120
4067 16:59:56.443646 # ok 2337 Set Streaming SVE VL 1136
4068 16:59:56.443969 # ok 2338 # SKIP Streaming SVE set SVE get SVE for VL 1136
4069 16:59:56.444063 # ok 2339 # SKIP Streaming SVE set SVE get FPSIMD for VL 1136
4070 16:59:56.444160 # ok 2340 # SKIP Streaming SVE set FPSIMD get SVE for VL 1136
4071 16:59:56.444239 # ok 2341 Set Streaming SVE VL 1152
4072 16:59:56.444337 # ok 2342 # SKIP Streaming SVE set SVE get SVE for VL 1152
4073 16:59:56.444628 # ok 2343 # SKIP Streaming SVE set SVE get FPSIMD for VL 1152
4074 16:59:56.444733 # ok 2344 # SKIP Streaming SVE set FPSIMD get SVE for VL 1152
4075 16:59:56.444859 # ok 2345 Set Streaming SVE VL 1168
4076 16:59:56.444992 # ok 2346 # SKIP Streaming SVE set SVE get SVE for VL 1168
4077 16:59:56.445104 # ok 2347 # SKIP Streaming SVE set SVE get FPSIMD for VL 1168
4078 16:59:56.445392 # ok 2348 # SKIP Streaming SVE set FPSIMD get SVE for VL 1168
4079 16:59:56.445691 # ok 2349 Set Streaming SVE VL 1184
4080 16:59:56.445786 # ok 2350 # SKIP Streaming SVE set SVE get SVE for VL 1184
4081 16:59:56.445881 # ok 2351 # SKIP Streaming SVE set SVE get FPSIMD for VL 1184
4082 16:59:56.446165 # ok 2352 # SKIP Streaming SVE set FPSIMD get SVE for VL 1184
4083 16:59:56.446264 # ok 2353 Set Streaming SVE VL 1200
4084 16:59:56.446361 # ok 2354 # SKIP Streaming SVE set SVE get SVE for VL 1200
4085 16:59:56.446458 # ok 2355 # SKIP Streaming SVE set SVE get FPSIMD for VL 1200
4086 16:59:56.446798 # ok 2356 # SKIP Streaming SVE set FPSIMD get SVE for VL 1200
4087 16:59:56.446902 # ok 2357 Set Streaming SVE VL 1216
4088 16:59:56.447002 # ok 2358 # SKIP Streaming SVE set SVE get SVE for VL 1216
4089 16:59:56.447103 # ok 2359 # SKIP Streaming SVE set SVE get FPSIMD for VL 1216
4090 16:59:56.447426 # ok 2360 # SKIP Streaming SVE set FPSIMD get SVE for VL 1216
4091 16:59:56.447530 # ok 2361 Set Streaming SVE VL 1232
4092 16:59:56.447630 # ok 2362 # SKIP Streaming SVE set SVE get SVE for VL 1232
4093 16:59:56.447920 # ok 2363 # SKIP Streaming SVE set SVE get FPSIMD for VL 1232
4094 16:59:56.448016 # ok 2364 # SKIP Streaming SVE set FPSIMD get SVE for VL 1232
4095 16:59:56.448120 # ok 2365 Set Streaming SVE VL 1248
4096 16:59:56.448229 # ok 2366 # SKIP Streaming SVE set SVE get SVE for VL 1248
4097 16:59:56.448528 # ok 2367 # SKIP Streaming SVE set SVE get FPSIMD for VL 1248
4098 16:59:56.448635 # ok 2368 # SKIP Streaming SVE set FPSIMD get SVE for VL 1248
4099 16:59:56.448752 # ok 2369 Set Streaming SVE VL 1264
4100 16:59:56.448857 # ok 2370 # SKIP Streaming SVE set SVE get SVE for VL 1264
4101 16:59:56.448976 # ok 2371 # SKIP Streaming SVE set SVE get FPSIMD for VL 1264
4102 16:59:56.449085 # ok 2372 # SKIP Streaming SVE set FPSIMD get SVE for VL 1264
4103 16:59:56.449195 # ok 2373 Set Streaming SVE VL 1280
4104 16:59:56.449495 # ok 2374 # SKIP Streaming SVE set SVE get SVE for VL 1280
4105 16:59:56.449613 # ok 2375 # SKIP Streaming SVE set SVE get FPSIMD for VL 1280
4106 16:59:56.449739 # ok 2376 # SKIP Streaming SVE set FPSIMD get SVE for VL 1280
4107 16:59:56.449854 # ok 2377 Set Streaming SVE VL 1296
4108 16:59:56.449965 # ok 2378 # SKIP Streaming SVE set SVE get SVE for VL 1296
4109 16:59:56.450262 # ok 2379 # SKIP Streaming SVE set SVE get FPSIMD for VL 1296
4110 16:59:56.450373 # ok 2380 # SKIP Streaming SVE set FPSIMD get SVE for VL 1296
4111 16:59:56.450453 # ok 2381 Set Streaming SVE VL 1312
4112 16:59:56.450529 # ok 2382 # SKIP Streaming SVE set SVE get SVE for VL 1312
4113 16:59:56.450792 # ok 2383 # SKIP Streaming SVE set SVE get FPSIMD for VL 1312
4114 16:59:56.450894 # ok 2384 # SKIP Streaming SVE set FPSIMD get SVE for VL 1312
4115 16:59:56.451013 # ok 2385 Set Streaming SVE VL 1328
4116 16:59:56.451114 # ok 2386 # SKIP Streaming SVE set SVE get SVE for VL 1328
4117 16:59:56.451228 # ok 2387 # SKIP Streaming SVE set SVE get FPSIMD for VL 1328
4118 16:59:56.451329 # ok 2388 # SKIP Streaming SVE set FPSIMD get SVE for VL 1328
4119 16:59:56.451425 # ok 2389 Set Streaming SVE VL 1344
4120 16:59:56.451712 # ok 2390 # SKIP Streaming SVE set SVE get SVE for VL 1344
4121 16:59:56.451827 # ok 2391 # SKIP Streaming SVE set SVE get FPSIMD for VL 1344
4122 16:59:56.451922 # ok 2392 # SKIP Streaming SVE set FPSIMD get SVE for VL 1344
4123 16:59:56.452015 # ok 2393 Set Streaming SVE VL 1360
4124 16:59:56.452319 # ok 2394 # SKIP Streaming SVE set SVE get SVE for VL 1360
4125 16:59:56.452435 # ok 2395 # SKIP Streaming SVE set SVE get FPSIMD for VL 1360
4126 16:59:56.452542 # ok 2396 # SKIP Streaming SVE set FPSIMD get SVE for VL 1360
4127 16:59:56.452648 # ok 2397 Set Streaming SVE VL 1376
4128 16:59:56.452928 # ok 2398 # SKIP Streaming SVE set SVE get SVE for VL 1376
4129 16:59:56.453030 # ok 2399 # SKIP Streaming SVE set SVE get FPSIMD for VL 1376
4130 16:59:56.453161 # ok 2400 # SKIP Streaming SVE set FPSIMD get SVE for VL 1376
4131 16:59:56.453284 # ok 2401 Set Streaming SVE VL 1392
4132 16:59:56.453415 # ok 2402 # SKIP Streaming SVE set SVE get SVE for VL 1392
4133 16:59:56.453753 # ok 2403 # SKIP Streaming SVE set SVE get FPSIMD for VL 1392
4134 16:59:56.454056 # ok 2404 # SKIP Streaming SVE set FPSIMD get SVE for VL 1392
4135 16:59:56.454161 # ok 2405 Set Streaming SVE VL 1408
4136 16:59:56.454268 # ok 2406 # SKIP Streaming SVE set SVE get SVE for VL 1408
4137 16:59:56.454388 # ok 2407 # SKIP Streaming SVE set SVE get FPSIMD for VL 1408
4138 16:59:56.454508 # ok 2408 # SKIP Streaming SVE set FPSIMD get SVE for VL 1408
4139 16:59:56.454603 # ok 2409 Set Streaming SVE VL 1424
4140 16:59:56.454704 # ok 2410 # SKIP Streaming SVE set SVE get SVE for VL 1424
4141 16:59:56.454805 # ok 2411 # SKIP Streaming SVE set SVE get FPSIMD for VL 1424
4142 16:59:56.455096 # ok 2412 # SKIP Streaming SVE set FPSIMD get SVE for VL 1424
4143 16:59:56.455215 # ok 2413 Set Streaming SVE VL 1440
4144 16:59:56.455349 # ok 2414 # SKIP Streaming SVE set SVE get SVE for VL 1440
4145 16:59:56.455470 # ok 2415 # SKIP Streaming SVE set SVE get FPSIMD for VL 1440
4146 16:59:56.455593 # ok 2416 # SKIP Streaming SVE set FPSIMD get SVE for VL 1440
4147 16:59:56.455709 # ok 2417 Set Streaming SVE VL 1456
4148 16:59:56.455992 # ok 2418 # SKIP Streaming SVE set SVE get SVE for VL 1456
4149 16:59:56.456106 # ok 2419 # SKIP Streaming SVE set SVE get FPSIMD for VL 1456
4150 16:59:56.456243 # ok 2420 # SKIP Streaming SVE set FPSIMD get SVE for VL 1456
4151 16:59:56.456354 # ok 2421 Set Streaming SVE VL 1472
4152 16:59:56.456464 # ok 2422 # SKIP Streaming SVE set SVE get SVE for VL 1472
4153 16:59:56.456774 # ok 2423 # SKIP Streaming SVE set SVE get FPSIMD for VL 1472
4154 16:59:56.456891 # ok 2424 # SKIP Streaming SVE set FPSIMD get SVE for VL 1472
4155 16:59:56.456997 # ok 2425 Set Streaming SVE VL 1488
4156 16:59:56.457099 # ok 2426 # SKIP Streaming SVE set SVE get SVE for VL 1488
4157 16:59:56.457237 # ok 2427 # SKIP Streaming SVE set SVE get FPSIMD for VL 1488
4158 16:59:56.457380 # ok 2428 # SKIP Streaming SVE set FPSIMD get SVE for VL 1488
4159 16:59:56.459866 # ok 2429 Set Streaming SVE VL 1504
4160 16:59:56.460037 # ok 2430 # SKIP Streaming SVE set SVE get SVE for VL 1504
4161 16:59:56.460179 # ok 2431 # SKIP Streaming SVE set SVE get FPSIMD for VL 1504
4162 16:59:56.460284 # ok 2432 # SKIP Streaming SVE set FPSIMD get SVE for VL 1504
4163 16:59:56.460374 # ok 2433 Set Streaming SVE VL 1520
4164 16:59:56.460466 # ok 2434 # SKIP Streaming SVE set SVE get SVE for VL 1520
4165 16:59:56.460563 # ok 2435 # SKIP Streaming SVE set SVE get FPSIMD for VL 1520
4166 16:59:56.460664 # ok 2436 # SKIP Streaming SVE set FPSIMD get SVE for VL 1520
4167 16:59:56.460765 # ok 2437 Set Streaming SVE VL 1536
4168 16:59:56.461056 # ok 2438 # SKIP Streaming SVE set SVE get SVE for VL 1536
4169 16:59:56.461162 # ok 2439 # SKIP Streaming SVE set SVE get FPSIMD for VL 1536
4170 16:59:56.461273 # ok 2440 # SKIP Streaming SVE set FPSIMD get SVE for VL 1536
4171 16:59:56.461377 # ok 2441 Set Streaming SVE VL 1552
4172 16:59:56.462139 # ok 2442 # SKIP Streaming SVE set SVE get SVE for VL 1552
4173 16:59:56.462439 # ok 2443 # SKIP Streaming SVE set SVE get FPSIMD for VL 1552
4174 16:59:56.462537 # ok 2444 # SKIP Streaming SVE set FPSIMD get SVE for VL 1552
4175 16:59:56.462632 # ok 2445 Set Streaming SVE VL 1568
4176 16:59:56.462728 # ok 2446 # SKIP Streaming SVE set SVE get SVE for VL 1568
4177 16:59:56.462818 # ok 2447 # SKIP Streaming SVE set SVE get FPSIMD for VL 1568
4178 16:59:56.463110 # ok 2448 # SKIP Streaming SVE set FPSIMD get SVE for VL 1568
4179 16:59:56.463214 # ok 2449 Set Streaming SVE VL 1584
4180 16:59:56.463335 # ok 2450 # SKIP Streaming SVE set SVE get SVE for VL 1584
4181 16:59:56.463441 # ok 2451 # SKIP Streaming SVE set SVE get FPSIMD for VL 1584
4182 16:59:56.463718 # ok 2452 # SKIP Streaming SVE set FPSIMD get SVE for VL 1584
4183 16:59:56.463814 # ok 2453 Set Streaming SVE VL 1600
4184 16:59:56.463902 # ok 2454 # SKIP Streaming SVE set SVE get SVE for VL 1600
4185 16:59:56.464195 # ok 2455 # SKIP Streaming SVE set SVE get FPSIMD for VL 1600
4186 16:59:56.464293 # ok 2456 # SKIP Streaming SVE set FPSIMD get SVE for VL 1600
4187 16:59:56.464383 # ok 2457 Set Streaming SVE VL 1616
4188 16:59:56.464476 # ok 2458 # SKIP Streaming SVE set SVE get SVE for VL 1616
4189 16:59:56.464773 # ok 2459 # SKIP Streaming SVE set SVE get FPSIMD for VL 1616
4190 16:59:56.464877 # ok 2460 # SKIP Streaming SVE set FPSIMD get SVE for VL 1616
4191 16:59:56.464972 # ok 2461 Set Streaming SVE VL 1632
4192 16:59:56.465070 # ok 2462 # SKIP Streaming SVE set SVE get SVE for VL 1632
4193 16:59:56.465172 # ok 2463 # SKIP Streaming SVE set SVE get FPSIMD for VL 1632
4194 16:59:56.465476 # ok 2464 # SKIP Streaming SVE set FPSIMD get SVE for VL 1632
4195 16:59:56.465617 # ok 2465 Set Streaming SVE VL 1648
4196 16:59:56.465752 # ok 2466 # SKIP Streaming SVE set SVE get SVE for VL 1648
4197 16:59:56.465877 # ok 2467 # SKIP Streaming SVE set SVE get FPSIMD for VL 1648
4198 16:59:56.466005 # ok 2468 # SKIP Streaming SVE set FPSIMD get SVE for VL 1648
4199 16:59:56.466319 # ok 2469 Set Streaming SVE VL 1664
4200 16:59:56.466427 # ok 2470 # SKIP Streaming SVE set SVE get SVE for VL 1664
4201 16:59:56.466551 # ok 2471 # SKIP Streaming SVE set SVE get FPSIMD for VL 1664
4202 16:59:56.466717 # ok 2472 # SKIP Streaming SVE set FPSIMD get SVE for VL 1664
4203 16:59:56.466818 # ok 2473 Set Streaming SVE VL 1680
4204 16:59:56.466959 # ok 2474 # SKIP Streaming SVE set SVE get SVE for VL 1680
4205 16:59:56.467231 # ok 2475 # SKIP Streaming SVE set SVE get FPSIMD for VL 1680
4206 16:59:56.467344 # ok 2476 # SKIP Streaming SVE set FPSIMD get SVE for VL 1680
4207 16:59:56.467462 # ok 2477 Set Streaming SVE VL 1696
4208 16:59:56.467569 # ok 2478 # SKIP Streaming SVE set SVE get SVE for VL 1696
4209 16:59:56.467682 # ok 2479 # SKIP Streaming SVE set SVE get FPSIMD for VL 1696
4210 16:59:56.467802 # ok 2480 # SKIP Streaming SVE set FPSIMD get SVE for VL 1696
4211 16:59:56.467910 # ok 2481 Set Streaming SVE VL 1712
4212 16:59:56.468201 # ok 2482 # SKIP Streaming SVE set SVE get SVE for VL 1712
4213 16:59:56.468317 # ok 2483 # SKIP Streaming SVE set SVE get FPSIMD for VL 1712
4214 16:59:56.468612 # ok 2484 # SKIP Streaming SVE set FPSIMD get SVE for VL 1712
4215 16:59:56.468723 # ok 2485 Set Streaming SVE VL 1728
4216 16:59:56.468858 # ok 2486 # SKIP Streaming SVE set SVE get SVE for VL 1728
4217 16:59:56.468977 # ok 2487 # SKIP Streaming SVE set SVE get FPSIMD for VL 1728
4218 16:59:56.469085 # ok 2488 # SKIP Streaming SVE set FPSIMD get SVE for VL 1728
4219 16:59:56.469201 # ok 2489 Set Streaming SVE VL 1744
4220 16:59:56.469304 # ok 2490 # SKIP Streaming SVE set SVE get SVE for VL 1744
4221 16:59:56.469620 # ok 2491 # SKIP Streaming SVE set SVE get FPSIMD for VL 1744
4222 16:59:56.469753 # ok 2492 # SKIP Streaming SVE set FPSIMD get SVE for VL 1744
4223 16:59:56.469858 # ok 2493 Set Streaming SVE VL 1760
4224 16:59:56.470155 # ok 2494 # SKIP Streaming SVE set SVE get SVE for VL 1760
4225 16:59:56.470269 # ok 2495 # SKIP Streaming SVE set SVE get FPSIMD for VL 1760
4226 16:59:56.470370 # ok 2496 # SKIP Streaming SVE set FPSIMD get SVE for VL 1760
4227 16:59:56.470470 # ok 2497 Set Streaming SVE VL 1776
4228 16:59:56.470744 # ok 2498 # SKIP Streaming SVE set SVE get SVE for VL 1776
4229 16:59:56.470866 # ok 2499 # SKIP Streaming SVE set SVE get FPSIMD for VL 1776
4230 16:59:56.470972 # ok 2500 # SKIP Streaming SVE set FPSIMD get SVE for VL 1776
4231 16:59:56.471076 # ok 2501 Set Streaming SVE VL 1792
4232 16:59:56.471388 # ok 2502 # SKIP Streaming SVE set SVE get SVE for VL 1792
4233 16:59:56.471486 # ok 2503 # SKIP Streaming SVE set SVE get FPSIMD for VL 1792
4234 16:59:56.471586 # ok 2504 # SKIP Streaming SVE set FPSIMD get SVE for VL 1792
4235 16:59:56.471687 # ok 2505 Set Streaming SVE VL 1808
4236 16:59:56.471979 # ok 2506 # SKIP Streaming SVE set SVE get SVE for VL 1808
4237 16:59:56.472079 # ok 2507 # SKIP Streaming SVE set SVE get FPSIMD for VL 1808
4238 16:59:56.472254 # ok 2508 # SKIP Streaming SVE set FPSIMD get SVE for VL 1808
4239 16:59:56.472364 # ok 2509 Set Streaming SVE VL 1824
4240 16:59:56.472464 # ok 2510 # SKIP Streaming SVE set SVE get SVE for VL 1824
4241 16:59:56.472555 # ok 2511 # SKIP Streaming SVE set SVE get FPSIMD for VL 1824
4242 16:59:56.472834 # ok 2512 # SKIP Streaming SVE set FPSIMD get SVE for VL 1824
4243 16:59:56.472926 # ok 2513 Set Streaming SVE VL 1840
4244 16:59:56.473015 # ok 2514 # SKIP Streaming SVE set SVE get SVE for VL 1840
4245 16:59:56.473113 # ok 2515 # SKIP Streaming SVE set SVE get FPSIMD for VL 1840
4246 16:59:56.473227 # ok 2516 # SKIP Streaming SVE set FPSIMD get SVE for VL 1840
4247 16:59:56.473518 # ok 2517 Set Streaming SVE VL 1856
4248 16:59:56.473820 # ok 2518 # SKIP Streaming SVE set SVE get SVE for VL 1856
4249 16:59:56.473935 # ok 2519 # SKIP Streaming SVE set SVE get FPSIMD for VL 1856
4250 16:59:56.474032 # ok 2520 # SKIP Streaming SVE set FPSIMD get SVE for VL 1856
4251 16:59:56.474128 # ok 2521 Set Streaming SVE VL 1872
4252 16:59:56.474428 # ok 2522 # SKIP Streaming SVE set SVE get SVE for VL 1872
4253 16:59:56.474542 # ok 2523 # SKIP Streaming SVE set SVE get FPSIMD for VL 1872
4254 16:59:56.474644 # ok 2524 # SKIP Streaming SVE set FPSIMD get SVE for VL 1872
4255 16:59:56.474758 # ok 2525 Set Streaming SVE VL 1888
4256 16:59:56.475067 # ok 2526 # SKIP Streaming SVE set SVE get SVE for VL 1888
4257 16:59:56.475188 # ok 2527 # SKIP Streaming SVE set SVE get FPSIMD for VL 1888
4258 16:59:56.475280 # ok 2528 # SKIP Streaming SVE set FPSIMD get SVE for VL 1888
4259 16:59:56.475375 # ok 2529 Set Streaming SVE VL 1904
4260 16:59:56.475476 # ok 2530 # SKIP Streaming SVE set SVE get SVE for VL 1904
4261 16:59:56.475801 # ok 2531 # SKIP Streaming SVE set SVE get FPSIMD for VL 1904
4262 16:59:56.475893 # ok 2532 # SKIP Streaming SVE set FPSIMD get SVE for VL 1904
4263 16:59:56.476008 # ok 2533 Set Streaming SVE VL 1920
4264 16:59:56.476113 # ok 2534 # SKIP Streaming SVE set SVE get SVE for VL 1920
4265 16:59:56.476223 # ok 2535 # SKIP Streaming SVE set SVE get FPSIMD for VL 1920
4266 16:59:56.476516 # ok 2536 # SKIP Streaming SVE set FPSIMD get SVE for VL 1920
4267 16:59:56.476682 # ok 2537 Set Streaming SVE VL 1936
4268 16:59:56.476843 # ok 2538 # SKIP Streaming SVE set SVE get SVE for VL 1936
4269 16:59:56.476990 # ok 2539 # SKIP Streaming SVE set SVE get FPSIMD for VL 1936
4270 16:59:56.477097 # ok 2540 # SKIP Streaming SVE set FPSIMD get SVE for VL 1936
4271 16:59:56.477187 # ok 2541 Set Streaming SVE VL 1952
4272 16:59:56.477422 # ok 2542 # SKIP Streaming SVE set SVE get SVE for VL 1952
4273 16:59:56.477555 # ok 2543 # SKIP Streaming SVE set SVE get FPSIMD for VL 1952
4274 16:59:56.477713 # ok 2544 # SKIP Streaming SVE set FPSIMD get SVE for VL 1952
4275 16:59:56.477829 # ok 2545 Set Streaming SVE VL 1968
4276 16:59:56.477933 # ok 2546 # SKIP Streaming SVE set SVE get SVE for VL 1968
4277 16:59:56.478253 # ok 2547 # SKIP Streaming SVE set SVE get FPSIMD for VL 1968
4278 16:59:56.478365 # ok 2548 # SKIP Streaming SVE set FPSIMD get SVE for VL 1968
4279 16:59:56.478470 # ok 2549 Set Streaming SVE VL 1984
4280 16:59:56.478563 # ok 2550 # SKIP Streaming SVE set SVE get SVE for VL 1984
4281 16:59:56.478654 # ok 2551 # SKIP Streaming SVE set SVE get FPSIMD for VL 1984
4282 16:59:56.478950 # ok 2552 # SKIP Streaming SVE set FPSIMD get SVE for VL 1984
4283 16:59:56.479049 # ok 2553 Set Streaming SVE VL 2000
4284 16:59:56.479171 # ok 2554 # SKIP Streaming SVE set SVE get SVE for VL 2000
4285 16:59:56.479279 # ok 2555 # SKIP Streaming SVE set SVE get FPSIMD for VL 2000
4286 16:59:56.479395 # ok 2556 # SKIP Streaming SVE set FPSIMD get SVE for VL 2000
4287 16:59:56.479510 # ok 2557 Set Streaming SVE VL 2016
4288 16:59:56.479817 # ok 2558 # SKIP Streaming SVE set SVE get SVE for VL 2016
4289 16:59:56.479908 # ok 2559 # SKIP Streaming SVE set SVE get FPSIMD for VL 2016
4290 16:59:56.479999 # ok 2560 # SKIP Streaming SVE set FPSIMD get SVE for VL 2016
4291 16:59:56.480108 # ok 2561 Set Streaming SVE VL 2032
4292 16:59:56.480223 # ok 2562 # SKIP Streaming SVE set SVE get SVE for VL 2032
4293 16:59:56.480530 # ok 2563 # SKIP Streaming SVE set SVE get FPSIMD for VL 2032
4294 16:59:56.480642 # ok 2564 # SKIP Streaming SVE set FPSIMD get SVE for VL 2032
4295 16:59:56.480725 # ok 2565 Set Streaming SVE VL 2048
4296 16:59:56.480815 # ok 2566 # SKIP Streaming SVE set SVE get SVE for VL 2048
4297 16:59:56.481096 # ok 2567 # SKIP Streaming SVE set SVE get FPSIMD for VL 2048
4298 16:59:56.481207 # ok 2568 # SKIP Streaming SVE set FPSIMD get SVE for VL 2048
4299 16:59:56.481300 # ok 2569 Set Streaming SVE VL 2064
4300 16:59:56.481393 # ok 2570 # SKIP Streaming SVE set SVE get SVE for VL 2064
4301 16:59:56.481689 # ok 2571 # SKIP Streaming SVE set SVE get FPSIMD for VL 2064
4302 16:59:56.481988 # ok 2572 # SKIP Streaming SVE set FPSIMD get SVE for VL 2064
4303 16:59:56.482073 # ok 2573 Set Streaming SVE VL 2080
4304 16:59:56.482197 # ok 2574 # SKIP Streaming SVE set SVE get SVE for VL 2080
4305 16:59:56.482309 # ok 2575 # SKIP Streaming SVE set SVE get FPSIMD for VL 2080
4306 16:59:56.482584 # ok 2576 # SKIP Streaming SVE set FPSIMD get SVE for VL 2080
4307 16:59:56.482683 # ok 2577 Set Streaming SVE VL 2096
4308 16:59:56.482760 # ok 2578 # SKIP Streaming SVE set SVE get SVE for VL 2096
4309 16:59:56.484957 # ok 2579 # SKIP Streaming SVE set SVE get FPSIMD for VL 2096
4310 16:59:56.485119 # ok 2580 # SKIP Streaming SVE set FPSIMD get SVE for VL 2096
4311 16:59:56.485234 # ok 2581 Set Streaming SVE VL 2112
4312 16:59:56.485404 # ok 2582 # SKIP Streaming SVE set SVE get SVE for VL 2112
4313 16:59:56.485955 # ok 2583 # SKIP Streaming SVE set SVE get FPSIMD for VL 2112
4314 16:59:56.486276 # ok 2584 # SKIP Streaming SVE set FPSIMD get SVE for VL 2112
4315 16:59:56.486378 # ok 2585 Set Streaming SVE VL 2128
4316 16:59:56.486482 # ok 2586 # SKIP Streaming SVE set SVE get SVE for VL 2128
4317 16:59:56.486584 # ok 2587 # SKIP Streaming SVE set SVE get FPSIMD for VL 2128
4318 16:59:56.486685 # ok 2588 # SKIP Streaming SVE set FPSIMD get SVE for VL 2128
4319 16:59:56.486794 # ok 2589 Set Streaming SVE VL 2144
4320 16:59:56.487150 # ok 2590 # SKIP Streaming SVE set SVE get SVE for VL 2144
4321 16:59:56.487247 # ok 2591 # SKIP Streaming SVE set SVE get FPSIMD for VL 2144
4322 16:59:56.487332 # ok 2592 # SKIP Streaming SVE set FPSIMD get SVE for VL 2144
4323 16:59:56.487584 # ok 2593 Set Streaming SVE VL 2160
4324 16:59:56.487706 # ok 2594 # SKIP Streaming SVE set SVE get SVE for VL 2160
4325 16:59:56.487806 # ok 2595 # SKIP Streaming SVE set SVE get FPSIMD for VL 2160
4326 16:59:56.488085 # ok 2596 # SKIP Streaming SVE set FPSIMD get SVE for VL 2160
4327 16:59:56.488178 # ok 2597 Set Streaming SVE VL 2176
4328 16:59:56.488279 # ok 2598 # SKIP Streaming SVE set SVE get SVE for VL 2176
4329 16:59:56.488362 # ok 2599 # SKIP Streaming SVE set SVE get FPSIMD for VL 2176
4330 16:59:56.488435 # ok 2600 # SKIP Streaming SVE set FPSIMD get SVE for VL 2176
4331 16:59:56.488687 # ok 2601 Set Streaming SVE VL 2192
4332 16:59:56.488769 # ok 2602 # SKIP Streaming SVE set SVE get SVE for VL 2192
4333 16:59:56.488845 # ok 2603 # SKIP Streaming SVE set SVE get FPSIMD for VL 2192
4334 16:59:56.489125 # ok 2604 # SKIP Streaming SVE set FPSIMD get SVE for VL 2192
4335 16:59:56.489217 # ok 2605 Set Streaming SVE VL 2208
4336 16:59:56.489314 # ok 2606 # SKIP Streaming SVE set SVE get SVE for VL 2208
4337 16:59:56.489394 # ok 2607 # SKIP Streaming SVE set SVE get FPSIMD for VL 2208
4338 16:59:56.490243 # ok 2608 # SKIP Streaming SVE set FPSIMD get SVE for VL 2208
4339 16:59:56.490559 # ok 2609 Set Streaming SVE VL 2224
4340 16:59:56.490665 # ok 2610 # SKIP Streaming SVE set SVE get SVE for VL 2224
4341 16:59:56.490770 # ok 2611 # SKIP Streaming SVE set SVE get FPSIMD for VL 2224
4342 16:59:56.490886 # ok 2612 # SKIP Streaming SVE set FPSIMD get SVE for VL 2224
4343 16:59:56.491003 # ok 2613 Set Streaming SVE VL 2240
4344 16:59:56.491128 # ok 2614 # SKIP Streaming SVE set SVE get SVE for VL 2240
4345 16:59:56.491254 # ok 2615 # SKIP Streaming SVE set SVE get FPSIMD for VL 2240
4346 16:59:56.491376 # ok 2616 # SKIP Streaming SVE set FPSIMD get SVE for VL 2240
4347 16:59:56.491480 # ok 2617 Set Streaming SVE VL 2256
4348 16:59:56.491786 # ok 2618 # SKIP Streaming SVE set SVE get SVE for VL 2256
4349 16:59:56.491908 # ok 2619 # SKIP Streaming SVE set SVE get FPSIMD for VL 2256
4350 16:59:56.492021 # ok 2620 # SKIP Streaming SVE set FPSIMD get SVE for VL 2256
4351 16:59:56.492125 # ok 2621 Set Streaming SVE VL 2272
4352 16:59:56.492419 # ok 2622 # SKIP Streaming SVE set SVE get SVE for VL 2272
4353 16:59:56.492523 # ok 2623 # SKIP Streaming SVE set SVE get FPSIMD for VL 2272
4354 16:59:56.492625 # ok 2624 # SKIP Streaming SVE set FPSIMD get SVE for VL 2272
4355 16:59:56.492725 # ok 2625 Set Streaming SVE VL 2288
4356 16:59:56.493025 # ok 2626 # SKIP Streaming SVE set SVE get SVE for VL 2288
4357 16:59:56.493142 # ok 2627 # SKIP Streaming SVE set SVE get FPSIMD for VL 2288
4358 16:59:56.493445 # ok 2628 # SKIP Streaming SVE set FPSIMD get SVE for VL 2288
4359 16:59:56.493543 # ok 2629 Set Streaming SVE VL 2304
4360 16:59:56.493965 # ok 2630 # SKIP Streaming SVE set SVE get SVE for VL 2304
4361 16:59:56.494254 # ok 2631 # SKIP Streaming SVE set SVE get FPSIMD for VL 2304
4362 16:59:56.494365 # ok 2632 # SKIP Streaming SVE set FPSIMD get SVE for VL 2304
4363 16:59:56.494473 # ok 2633 Set Streaming SVE VL 2320
4364 16:59:56.494575 # ok 2634 # SKIP Streaming SVE set SVE get SVE for VL 2320
4365 16:59:56.494860 # ok 2635 # SKIP Streaming SVE set SVE get FPSIMD for VL 2320
4366 16:59:56.494970 # ok 2636 # SKIP Streaming SVE set FPSIMD get SVE for VL 2320
4367 16:59:56.495065 # ok 2637 Set Streaming SVE VL 2336
4368 16:59:56.495187 # ok 2638 # SKIP Streaming SVE set SVE get SVE for VL 2336
4369 16:59:56.495317 # ok 2639 # SKIP Streaming SVE set SVE get FPSIMD for VL 2336
4370 16:59:56.495436 # ok 2640 # SKIP Streaming SVE set FPSIMD get SVE for VL 2336
4371 16:59:56.495534 # ok 2641 Set Streaming SVE VL 2352
4372 16:59:56.495642 # ok 2642 # SKIP Streaming SVE set SVE get SVE for VL 2352
4373 16:59:56.495890 # ok 2643 # SKIP Streaming SVE set SVE get FPSIMD for VL 2352
4374 16:59:56.496020 # ok 2644 # SKIP Streaming SVE set FPSIMD get SVE for VL 2352
4375 16:59:56.496134 # ok 2645 Set Streaming SVE VL 2368
4376 16:59:56.496454 # ok 2646 # SKIP Streaming SVE set SVE get SVE for VL 2368
4377 16:59:56.496573 # ok 2647 # SKIP Streaming SVE set SVE get FPSIMD for VL 2368
4378 16:59:56.496694 # ok 2648 # SKIP Streaming SVE set FPSIMD get SVE for VL 2368
4379 16:59:56.496827 # ok 2649 Set Streaming SVE VL 2384
4380 16:59:56.496937 # ok 2650 # SKIP Streaming SVE set SVE get SVE for VL 2384
4381 16:59:56.497050 # ok 2651 # SKIP Streaming SVE set SVE get FPSIMD for VL 2384
4382 16:59:56.497289 # ok 2652 # SKIP Streaming SVE set FPSIMD get SVE for VL 2384
4383 16:59:56.497406 # ok 2653 Set Streaming SVE VL 2400
4384 16:59:56.497689 # ok 2654 # SKIP Streaming SVE set SVE get SVE for VL 2400
4385 16:59:56.497980 # ok 2655 # SKIP Streaming SVE set SVE get FPSIMD for VL 2400
4386 16:59:56.498088 # ok 2656 # SKIP Streaming SVE set FPSIMD get SVE for VL 2400
4387 16:59:56.498212 # ok 2657 Set Streaming SVE VL 2416
4388 16:59:56.498310 # ok 2658 # SKIP Streaming SVE set SVE get SVE for VL 2416
4389 16:59:56.498420 # ok 2659 # SKIP Streaming SVE set SVE get FPSIMD for VL 2416
4390 16:59:56.498536 # ok 2660 # SKIP Streaming SVE set FPSIMD get SVE for VL 2416
4391 16:59:56.498668 # ok 2661 Set Streaming SVE VL 2432
4392 16:59:56.498981 # ok 2662 # SKIP Streaming SVE set SVE get SVE for VL 2432
4393 16:59:56.499076 # ok 2663 # SKIP Streaming SVE set SVE get FPSIMD for VL 2432
4394 16:59:56.499175 # ok 2664 # SKIP Streaming SVE set FPSIMD get SVE for VL 2432
4395 16:59:56.499263 # ok 2665 Set Streaming SVE VL 2448
4396 16:59:56.499362 # ok 2666 # SKIP Streaming SVE set SVE get SVE for VL 2448
4397 16:59:56.499645 # ok 2667 # SKIP Streaming SVE set SVE get FPSIMD for VL 2448
4398 16:59:56.499751 # ok 2668 # SKIP Streaming SVE set FPSIMD get SVE for VL 2448
4399 16:59:56.499872 # ok 2669 Set Streaming SVE VL 2464
4400 16:59:56.499999 # ok 2670 # SKIP Streaming SVE set SVE get SVE for VL 2464
4401 16:59:56.500123 # ok 2671 # SKIP Streaming SVE set SVE get FPSIMD for VL 2464
4402 16:59:56.500265 # ok 2672 # SKIP Streaming SVE set FPSIMD get SVE for VL 2464
4403 16:59:56.500406 # ok 2673 Set Streaming SVE VL 2480
4404 16:59:56.500535 # ok 2674 # SKIP Streaming SVE set SVE get SVE for VL 2480
4405 16:59:56.500853 # ok 2675 # SKIP Streaming SVE set SVE get FPSIMD for VL 2480
4406 16:59:56.500959 # ok 2676 # SKIP Streaming SVE set FPSIMD get SVE for VL 2480
4407 16:59:56.501083 # ok 2677 Set Streaming SVE VL 2496
4408 16:59:56.501190 # ok 2678 # SKIP Streaming SVE set SVE get SVE for VL 2496
4409 16:59:56.501316 # ok 2679 # SKIP Streaming SVE set SVE get FPSIMD for VL 2496
4410 16:59:56.501443 # ok 2680 # SKIP Streaming SVE set FPSIMD get SVE for VL 2496
4411 16:59:56.501774 # ok 2681 Set Streaming SVE VL 2512
4412 16:59:56.501880 # ok 2682 # SKIP Streaming SVE set SVE get SVE for VL 2512
4413 16:59:56.502004 # ok 2683 # SKIP Streaming SVE set SVE get FPSIMD for VL 2512
4414 16:59:56.502130 # ok 2684 # SKIP Streaming SVE set FPSIMD get SVE for VL 2512
4415 16:59:56.502251 # ok 2685 Set Streaming SVE VL 2528
4416 16:59:56.502362 # ok 2686 # SKIP Streaming SVE set SVE get SVE for VL 2528
4417 16:59:56.502468 # ok 2687 # SKIP Streaming SVE set SVE get FPSIMD for VL 2528
4418 16:59:56.502789 # ok 2688 # SKIP Streaming SVE set FPSIMD get SVE for VL 2528
4419 16:59:56.502890 # ok 2689 Set Streaming SVE VL 2544
4420 16:59:56.503010 # ok 2690 # SKIP Streaming SVE set SVE get SVE for VL 2544
4421 16:59:56.503112 # ok 2691 # SKIP Streaming SVE set SVE get FPSIMD for VL 2544
4422 16:59:56.503296 # ok 2692 # SKIP Streaming SVE set FPSIMD get SVE for VL 2544
4423 16:59:56.503418 # ok 2693 Set Streaming SVE VL 2560
4424 16:59:56.503520 # ok 2694 # SKIP Streaming SVE set SVE get SVE for VL 2560
4425 16:59:56.503635 # ok 2695 # SKIP Streaming SVE set SVE get FPSIMD for VL 2560
4426 16:59:56.503757 # ok 2696 # SKIP Streaming SVE set FPSIMD get SVE for VL 2560
4427 16:59:56.503877 # ok 2697 Set Streaming SVE VL 2576
4428 16:59:56.503990 # ok 2698 # SKIP Streaming SVE set SVE get SVE for VL 2576
4429 16:59:56.504309 # ok 2699 # SKIP Streaming SVE set SVE get FPSIMD for VL 2576
4430 16:59:56.504466 # ok 2700 # SKIP Streaming SVE set FPSIMD get SVE for VL 2576
4431 16:59:56.504652 # ok 2701 Set Streaming SVE VL 2592
4432 16:59:56.504788 # ok 2702 # SKIP Streaming SVE set SVE get SVE for VL 2592
4433 16:59:56.504873 # ok 2703 # SKIP Streaming SVE set SVE get FPSIMD for VL 2592
4434 16:59:56.504966 # ok 2704 # SKIP Streaming SVE set FPSIMD get SVE for VL 2592
4435 16:59:56.505064 # ok 2705 Set Streaming SVE VL 2608
4436 16:59:56.505364 # ok 2706 # SKIP Streaming SVE set SVE get SVE for VL 2608
4437 16:59:56.505483 # ok 2707 # SKIP Streaming SVE set SVE get FPSIMD for VL 2608
4438 16:59:56.505774 # ok 2708 # SKIP Streaming SVE set FPSIMD get SVE for VL 2608
4439 16:59:56.505887 # ok 2709 Set Streaming SVE VL 2624
4440 16:59:56.506011 # ok 2710 # SKIP Streaming SVE set SVE get SVE for VL 2624
4441 16:59:56.506119 # ok 2711 # SKIP Streaming SVE set SVE get FPSIMD for VL 2624
4442 16:59:56.506224 # ok 2712 # SKIP Streaming SVE set FPSIMD get SVE for VL 2624
4443 16:59:56.506297 # ok 2713 Set Streaming SVE VL 2640
4444 16:59:56.506397 # ok 2714 # SKIP Streaming SVE set SVE get SVE for VL 2640
4445 16:59:56.506488 # ok 2715 # SKIP Streaming SVE set SVE get FPSIMD for VL 2640
4446 16:59:56.506784 # ok 2716 # SKIP Streaming SVE set FPSIMD get SVE for VL 2640
4447 16:59:56.506884 # ok 2717 Set Streaming SVE VL 2656
4448 16:59:56.506986 # ok 2718 # SKIP Streaming SVE set SVE get SVE for VL 2656
4449 16:59:56.507085 # ok 2719 # SKIP Streaming SVE set SVE get FPSIMD for VL 2656
4450 16:59:56.507385 # ok 2720 # SKIP Streaming SVE set FPSIMD get SVE for VL 2656
4451 16:59:56.507488 # ok 2721 Set Streaming SVE VL 2672
4452 16:59:56.507588 # ok 2722 # SKIP Streaming SVE set SVE get SVE for VL 2672
4453 16:59:56.507671 # ok 2723 # SKIP Streaming SVE set SVE get FPSIMD for VL 2672
4454 16:59:56.507761 # ok 2724 # SKIP Streaming SVE set FPSIMD get SVE for VL 2672
4455 16:59:56.507860 # ok 2725 Set Streaming SVE VL 2688
4456 16:59:56.507959 # ok 2726 # SKIP Streaming SVE set SVE get SVE for VL 2688
4457 16:59:56.508244 # ok 2727 # SKIP Streaming SVE set SVE get FPSIMD for VL 2688
4458 16:59:56.510918 # ok 2728 # SKIP Streaming SVE set FPSIMD get SVE for VL 2688
4459 16:59:56.511057 # ok 2729 Set Streaming SVE VL 2704
4460 16:59:56.511159 # ok 2730 # SKIP Streaming SVE set SVE get SVE for VL 2704
4461 16:59:56.511241 # ok 2731 # SKIP Streaming SVE set SVE get FPSIMD for VL 2704
4462 16:59:56.511338 # ok 2732 # SKIP Streaming SVE set FPSIMD get SVE for VL 2704
4463 16:59:56.511437 # ok 2733 Set Streaming SVE VL 2720
4464 16:59:56.511542 # ok 2734 # SKIP Streaming SVE set SVE get SVE for VL 2720
4465 16:59:56.511680 # ok 2735 # SKIP Streaming SVE set SVE get FPSIMD for VL 2720
4466 16:59:56.511796 # ok 2736 # SKIP Streaming SVE set FPSIMD get SVE for VL 2720
4467 16:59:56.511917 # ok 2737 Set Streaming SVE VL 2736
4468 16:59:56.512059 # ok 2738 # SKIP Streaming SVE set SVE get SVE for VL 2736
4469 16:59:56.512372 # ok 2739 # SKIP Streaming SVE set SVE get FPSIMD for VL 2736
4470 16:59:56.512495 # ok 2740 # SKIP Streaming SVE set FPSIMD get SVE for VL 2736
4471 16:59:56.512602 # ok 2741 Set Streaming SVE VL 2752
4472 16:59:56.512710 # ok 2742 # SKIP Streaming SVE set SVE get SVE for VL 2752
4473 16:59:56.512816 # ok 2743 # SKIP Streaming SVE set SVE get FPSIMD for VL 2752
4474 16:59:56.513164 # ok 2744 # SKIP Streaming SVE set FPSIMD get SVE for VL 2752
4475 16:59:56.513286 # ok 2745 Set Streaming SVE VL 2768
4476 16:59:56.513403 # ok 2746 # SKIP Streaming SVE set SVE get SVE for VL 2768
4477 16:59:56.513942 # ok 2747 # SKIP Streaming SVE set SVE get FPSIMD for VL 2768
4478 16:59:56.514241 # ok 2748 # SKIP Streaming SVE set FPSIMD get SVE for VL 2768
4479 16:59:56.514357 # ok 2749 Set Streaming SVE VL 2784
4480 16:59:56.514483 # ok 2750 # SKIP Streaming SVE set SVE get SVE for VL 2784
4481 16:59:56.514607 # ok 2751 # SKIP Streaming SVE set SVE get FPSIMD for VL 2784
4482 16:59:56.514729 # ok 2752 # SKIP Streaming SVE set FPSIMD get SVE for VL 2784
4483 16:59:56.514843 # ok 2753 Set Streaming SVE VL 2800
4484 16:59:56.515082 # ok 2754 # SKIP Streaming SVE set SVE get SVE for VL 2800
4485 16:59:56.515206 # ok 2755 # SKIP Streaming SVE set SVE get FPSIMD for VL 2800
4486 16:59:56.515515 # ok 2756 # SKIP Streaming SVE set FPSIMD get SVE for VL 2800
4487 16:59:56.515619 # ok 2757 Set Streaming SVE VL 2816
4488 16:59:56.515720 # ok 2758 # SKIP Streaming SVE set SVE get SVE for VL 2816
4489 16:59:56.515827 # ok 2759 # SKIP Streaming SVE set SVE get FPSIMD for VL 2816
4490 16:59:56.515931 # ok 2760 # SKIP Streaming SVE set FPSIMD get SVE for VL 2816
4491 16:59:56.516040 # ok 2761 Set Streaming SVE VL 2832
4492 16:59:56.516160 # ok 2762 # SKIP Streaming SVE set SVE get SVE for VL 2832
4493 16:59:56.516450 # ok 2763 # SKIP Streaming SVE set SVE get FPSIMD for VL 2832
4494 16:59:56.516548 # ok 2764 # SKIP Streaming SVE set FPSIMD get SVE for VL 2832
4495 16:59:56.516636 # ok 2765 Set Streaming SVE VL 2848
4496 16:59:56.516750 # ok 2766 # SKIP Streaming SVE set SVE get SVE for VL 2848
4497 16:59:56.516859 # ok 2767 # SKIP Streaming SVE set SVE get FPSIMD for VL 2848
4498 16:59:56.517161 # ok 2768 # SKIP Streaming SVE set FPSIMD get SVE for VL 2848
4499 16:59:56.517273 # ok 2769 Set Streaming SVE VL 2864
4500 16:59:56.517360 # ok 2770 # SKIP Streaming SVE set SVE get SVE for VL 2864
4501 16:59:56.517860 # ok 2771 # SKIP Streaming SVE set SVE get FPSIMD for VL 2864
4502 16:59:56.517965 # ok 2772 # SKIP Streaming SVE set FPSIMD get SVE for VL 2864
4503 16:59:56.518083 # ok 2773 Set Streaming SVE VL 2880
4504 16:59:56.518174 # ok 2774 # SKIP Streaming SVE set SVE get SVE for VL 2880
4505 16:59:56.518413 # ok 2775 # SKIP Streaming SVE set SVE get FPSIMD for VL 2880
4506 16:59:56.518536 # ok 2776 # SKIP Streaming SVE set FPSIMD get SVE for VL 2880
4507 16:59:56.518635 # ok 2777 Set Streaming SVE VL 2896
4508 16:59:56.518854 # ok 2778 # SKIP Streaming SVE set SVE get SVE for VL 2896
4509 16:59:56.518981 # ok 2779 # SKIP Streaming SVE set SVE get FPSIMD for VL 2896
4510 16:59:56.519282 # ok 2780 # SKIP Streaming SVE set FPSIMD get SVE for VL 2896
4511 16:59:56.519393 # ok 2781 Set Streaming SVE VL 2912
4512 16:59:56.519531 # ok 2782 # SKIP Streaming SVE set SVE get SVE for VL 2912
4513 16:59:56.519632 # ok 2783 # SKIP Streaming SVE set SVE get FPSIMD for VL 2912
4514 16:59:56.519752 # ok 2784 # SKIP Streaming SVE set FPSIMD get SVE for VL 2912
4515 16:59:56.519872 # ok 2785 Set Streaming SVE VL 2928
4516 16:59:56.520009 # ok 2786 # SKIP Streaming SVE set SVE get SVE for VL 2928
4517 16:59:56.520334 # ok 2787 # SKIP Streaming SVE set SVE get FPSIMD for VL 2928
4518 16:59:56.520451 # ok 2788 # SKIP Streaming SVE set FPSIMD get SVE for VL 2928
4519 16:59:56.520547 # ok 2789 Set Streaming SVE VL 2944
4520 16:59:56.520665 # ok 2790 # SKIP Streaming SVE set SVE get SVE for VL 2944
4521 16:59:56.520794 # ok 2791 # SKIP Streaming SVE set SVE get FPSIMD for VL 2944
4522 16:59:56.521106 # ok 2792 # SKIP Streaming SVE set FPSIMD get SVE for VL 2944
4523 16:59:56.521222 # ok 2793 Set Streaming SVE VL 2960
4524 16:59:56.521559 # ok 2794 # SKIP Streaming SVE set SVE get SVE for VL 2960
4525 16:59:56.521685 # ok 2795 # SKIP Streaming SVE set SVE get FPSIMD for VL 2960
4526 16:59:56.521988 # ok 2796 # SKIP Streaming SVE set FPSIMD get SVE for VL 2960
4527 16:59:56.522093 # ok 2797 Set Streaming SVE VL 2976
4528 16:59:56.522219 # ok 2798 # SKIP Streaming SVE set SVE get SVE for VL 2976
4529 16:59:56.522328 # ok 2799 # SKIP Streaming SVE set SVE get FPSIMD for VL 2976
4530 16:59:56.522439 # ok 2800 # SKIP Streaming SVE set FPSIMD get SVE for VL 2976
4531 16:59:56.522536 # ok 2801 Set Streaming SVE VL 2992
4532 16:59:56.522632 # ok 2802 # SKIP Streaming SVE set SVE get SVE for VL 2992
4533 16:59:56.522933 # ok 2803 # SKIP Streaming SVE set SVE get FPSIMD for VL 2992
4534 16:59:56.523043 # ok 2804 # SKIP Streaming SVE set FPSIMD get SVE for VL 2992
4535 16:59:56.523203 # ok 2805 Set Streaming SVE VL 3008
4536 16:59:56.523318 # ok 2806 # SKIP Streaming SVE set SVE get SVE for VL 3008
4537 16:59:56.523443 # ok 2807 # SKIP Streaming SVE set SVE get FPSIMD for VL 3008
4538 16:59:56.523533 # ok 2808 # SKIP Streaming SVE set FPSIMD get SVE for VL 3008
4539 16:59:56.523621 # ok 2809 Set Streaming SVE VL 3024
4540 16:59:56.523713 # ok 2810 # SKIP Streaming SVE set SVE get SVE for VL 3024
4541 16:59:56.524020 # ok 2811 # SKIP Streaming SVE set SVE get FPSIMD for VL 3024
4542 16:59:56.524134 # ok 2812 # SKIP Streaming SVE set FPSIMD get SVE for VL 3024
4543 16:59:56.524228 # ok 2813 Set Streaming SVE VL 3040
4544 16:59:56.524329 # ok 2814 # SKIP Streaming SVE set SVE get SVE for VL 3040
4545 16:59:56.524643 # ok 2815 # SKIP Streaming SVE set SVE get FPSIMD for VL 3040
4546 16:59:56.524753 # ok 2816 # SKIP Streaming SVE set FPSIMD get SVE for VL 3040
4547 16:59:56.524853 # ok 2817 Set Streaming SVE VL 3056
4548 16:59:56.525154 # ok 2818 # SKIP Streaming SVE set SVE get SVE for VL 3056
4549 16:59:56.525253 # ok 2819 # SKIP Streaming SVE set SVE get FPSIMD for VL 3056
4550 16:59:56.525345 # ok 2820 # SKIP Streaming SVE set FPSIMD get SVE for VL 3056
4551 16:59:56.525424 # ok 2821 Set Streaming SVE VL 3072
4552 16:59:56.525698 # ok 2822 # SKIP Streaming SVE set SVE get SVE for VL 3072
4553 16:59:56.525994 # ok 2823 # SKIP Streaming SVE set SVE get FPSIMD for VL 3072
4554 16:59:56.526106 # ok 2824 # SKIP Streaming SVE set FPSIMD get SVE for VL 3072
4555 16:59:56.526419 # ok 2825 Set Streaming SVE VL 3088
4556 16:59:56.526516 # ok 2826 # SKIP Streaming SVE set SVE get SVE for VL 3088
4557 16:59:56.526618 # ok 2827 # SKIP Streaming SVE set SVE get FPSIMD for VL 3088
4558 16:59:56.526713 # ok 2828 # SKIP Streaming SVE set FPSIMD get SVE for VL 3088
4559 16:59:56.527000 # ok 2829 Set Streaming SVE VL 3104
4560 16:59:56.527103 # ok 2830 # SKIP Streaming SVE set SVE get SVE for VL 3104
4561 16:59:56.527218 # ok 2831 # SKIP Streaming SVE set SVE get FPSIMD for VL 3104
4562 16:59:56.527533 # ok 2832 # SKIP Streaming SVE set FPSIMD get SVE for VL 3104
4563 16:59:56.527641 # ok 2833 Set Streaming SVE VL 3120
4564 16:59:56.527755 # ok 2834 # SKIP Streaming SVE set SVE get SVE for VL 3120
4565 16:59:56.527874 # ok 2835 # SKIP Streaming SVE set SVE get FPSIMD for VL 3120
4566 16:59:56.528035 # ok 2836 # SKIP Streaming SVE set FPSIMD get SVE for VL 3120
4567 16:59:56.528144 # ok 2837 Set Streaming SVE VL 3136
4568 16:59:56.528253 # ok 2838 # SKIP Streaming SVE set SVE get SVE for VL 3136
4569 16:59:56.528379 # ok 2839 # SKIP Streaming SVE set SVE get FPSIMD for VL 3136
4570 16:59:56.528498 # ok 2840 # SKIP Streaming SVE set FPSIMD get SVE for VL 3136
4571 16:59:56.528781 # ok 2841 Set Streaming SVE VL 3152
4572 16:59:56.528882 # ok 2842 # SKIP Streaming SVE set SVE get SVE for VL 3152
4573 16:59:56.528991 # ok 2843 # SKIP Streaming SVE set SVE get FPSIMD for VL 3152
4574 16:59:56.529301 # ok 2844 # SKIP Streaming SVE set FPSIMD get SVE for VL 3152
4575 16:59:56.529415 # ok 2845 Set Streaming SVE VL 3168
4576 16:59:56.529691 # ok 2846 # SKIP Streaming SVE set SVE get SVE for VL 3168
4577 16:59:56.530001 # ok 2847 # SKIP Streaming SVE set SVE get FPSIMD for VL 3168
4578 16:59:56.530096 # ok 2848 # SKIP Streaming SVE set FPSIMD get SVE for VL 3168
4579 16:59:56.530207 # ok 2849 Set Streaming SVE VL 3184
4580 16:59:56.530311 # ok 2850 # SKIP Streaming SVE set SVE get SVE for VL 3184
4581 16:59:56.530593 # ok 2851 # SKIP Streaming SVE set SVE get FPSIMD for VL 3184
4582 16:59:56.530719 # ok 2852 # SKIP Streaming SVE set FPSIMD get SVE for VL 3184
4583 16:59:56.530815 # ok 2853 Set Streaming SVE VL 3200
4584 16:59:56.531112 # ok 2854 # SKIP Streaming SVE set SVE get SVE for VL 3200
4585 16:59:56.531224 # ok 2855 # SKIP Streaming SVE set SVE get FPSIMD for VL 3200
4586 16:59:56.531327 # ok 2856 # SKIP Streaming SVE set FPSIMD get SVE for VL 3200
4587 16:59:56.531424 # ok 2857 Set Streaming SVE VL 3216
4588 16:59:56.531703 # ok 2858 # SKIP Streaming SVE set SVE get SVE for VL 3216
4589 16:59:56.531820 # ok 2859 # SKIP Streaming SVE set SVE get FPSIMD for VL 3216
4590 16:59:56.531922 # ok 2860 # SKIP Streaming SVE set FPSIMD get SVE for VL 3216
4591 16:59:56.532018 # ok 2861 Set Streaming SVE VL 3232
4592 16:59:56.532266 # ok 2862 # SKIP Streaming SVE set SVE get SVE for VL 3232
4593 16:59:56.532388 # ok 2863 # SKIP Streaming SVE set SVE get FPSIMD for VL 3232
4594 16:59:56.532486 # ok 2864 # SKIP Streaming SVE set FPSIMD get SVE for VL 3232
4595 16:59:56.532582 # ok 2865 Set Streaming SVE VL 3248
4596 16:59:56.532900 # ok 2866 # SKIP Streaming SVE set SVE get SVE for VL 3248
4597 16:59:56.533023 # ok 2867 # SKIP Streaming SVE set SVE get FPSIMD for VL 3248
4598 16:59:56.533158 # ok 2868 # SKIP Streaming SVE set FPSIMD get SVE for VL 3248
4599 16:59:56.533278 # ok 2869 Set Streaming SVE VL 3264
4600 16:59:56.533623 # ok 2870 # SKIP Streaming SVE set SVE get SVE for VL 3264
4601 16:59:56.533758 # ok 2871 # SKIP Streaming SVE set SVE get FPSIMD for VL 3264
4602 16:59:56.534062 # ok 2872 # SKIP Streaming SVE set FPSIMD get SVE for VL 3264
4603 16:59:56.534152 # ok 2873 Set Streaming SVE VL 3280
4604 16:59:56.534262 # ok 2874 # SKIP Streaming SVE set SVE get SVE for VL 3280
4605 16:59:56.534380 # ok 2875 # SKIP Streaming SVE set SVE get FPSIMD for VL 3280
4606 16:59:56.534494 # ok 2876 # SKIP Streaming SVE set FPSIMD get SVE for VL 3280
4607 16:59:56.534595 # ok 2877 Set Streaming SVE VL 3296
4608 16:59:56.543722 # ok 2878 # SKIP Streaming SVE set SVE get SVE for VL 3296
4609 16:59:56.543946 # ok 2879 # SKIP Streaming SVE set SVE get FPSIMD for VL 3296
4610 16:59:56.544048 # ok 2880 # SKIP Streaming SVE set FPSIMD get SVE for VL 3296
4611 16:59:56.544136 # ok 2881 Set Streaming SVE VL 3312
4612 16:59:56.544233 # ok 2882 # SKIP Streaming SVE set SVE get SVE for VL 3312
4613 16:59:56.544330 # ok 2883 # SKIP Streaming SVE set SVE get FPSIMD for VL 3312
4614 16:59:56.544435 # ok 2884 # SKIP Streaming SVE set FPSIMD get SVE for VL 3312
4615 16:59:56.544521 # ok 2885 Set Streaming SVE VL 3328
4616 16:59:56.544621 # ok 2886 # SKIP Streaming SVE set SVE get SVE for VL 3328
4617 16:59:56.544762 # ok 2887 # SKIP Streaming SVE set SVE get FPSIMD for VL 3328
4618 16:59:56.545064 # ok 2888 # SKIP Streaming SVE set FPSIMD get SVE for VL 3328
4619 16:59:56.545164 # ok 2889 Set Streaming SVE VL 3344
4620 16:59:56.545272 # ok 2890 # SKIP Streaming SVE set SVE get SVE for VL 3344
4621 16:59:56.545399 # ok 2891 # SKIP Streaming SVE set SVE get FPSIMD for VL 3344
4622 16:59:56.563710 # ok 2892 # SKIP Streaming SVE set FPSIMD get SVE for VL 3344
4623 16:59:56.563942 # ok 2893 Set Streaming SVE VL 3360
4624 16:59:56.564222 # ok 2894 # SKIP Streaming SVE set SVE get SVE for VL 3360
4625 16:59:56.564329 # ok 2895 # SKIP Streaming SVE set SVE get FPSIMD for VL 3360
4626 16:59:56.564437 # ok 2896 # SKIP Streaming SVE set FPSIMD get SVE for VL 3360
4627 16:59:56.564520 # ok 2897 Set Streaming SVE VL 3376
4628 16:59:56.564611 # ok 2898 # SKIP Streaming SVE set SVE get SVE for VL 3376
4629 16:59:56.564680 # ok 2899 # SKIP Streaming SVE set SVE get FPSIMD for VL 3376
4630 16:59:56.564756 # ok 2900 # SKIP Streaming SVE set FPSIMD get SVE for VL 3376
4631 16:59:56.564833 # ok 2901 Set Streaming SVE VL 3392
4632 16:59:56.564910 # ok 2902 # SKIP Streaming SVE set SVE get SVE for VL 3392
4633 16:59:56.565182 # ok 2903 # SKIP Streaming SVE set SVE get FPSIMD for VL 3392
4634 16:59:56.565286 # ok 2904 # SKIP Streaming SVE set FPSIMD get SVE for VL 3392
4635 16:59:56.565381 # ok 2905 Set Streaming SVE VL 3408
4636 16:59:56.565485 # ok 2906 # SKIP Streaming SVE set SVE get SVE for VL 3408
4637 16:59:56.571200 # ok 2907 # SKIP Streaming SVE set SVE get FPSIMD for VL 3408
4638 16:59:56.571386 # ok 2908 # SKIP Streaming SVE set FPSIMD get SVE for VL 3408
4639 16:59:56.571456 # ok 2909 Set Streaming SVE VL 3424
4640 16:59:56.571529 # ok 2910 # SKIP Streaming SVE set SVE get SVE for VL 3424
4641 16:59:56.571603 # ok 2911 # SKIP Streaming SVE set SVE get FPSIMD for VL 3424
4642 16:59:56.571680 # ok 2912 # SKIP Streaming SVE set FPSIMD get SVE for VL 3424
4643 16:59:56.571930 # ok 2913 Set Streaming SVE VL 3440
4644 16:59:56.571996 # ok 2914 # SKIP Streaming SVE set SVE get SVE for VL 3440
4645 16:59:56.572067 # ok 2915 # SKIP Streaming SVE set SVE get FPSIMD for VL 3440
4646 16:59:56.572329 # ok 2916 # SKIP Streaming SVE set FPSIMD get SVE for VL 3440
4647 16:59:56.572448 # ok 2917 Set Streaming SVE VL 3456
4648 16:59:56.572540 # ok 2918 # SKIP Streaming SVE set SVE get SVE for VL 3456
4649 16:59:56.572646 # ok 2919 # SKIP Streaming SVE set SVE get FPSIMD for VL 3456
4650 16:59:56.572747 # ok 2920 # SKIP Streaming SVE set FPSIMD get SVE for VL 3456
4651 16:59:56.572873 # ok 2921 Set Streaming SVE VL 3472
4652 16:59:56.573206 # ok 2922 # SKIP Streaming SVE set SVE get SVE for VL 3472
4653 16:59:56.573309 # ok 2923 # SKIP Streaming SVE set SVE get FPSIMD for VL 3472
4654 16:59:56.573417 # ok 2924 # SKIP Streaming SVE set FPSIMD get SVE for VL 3472
4655 16:59:56.578604 # ok 2925 Set Streaming SVE VL 3488
4656 16:59:56.579012 # ok 2926 # SKIP Streaming SVE set SVE get SVE for VL 3488
4657 16:59:56.579116 # ok 2927 # SKIP Streaming SVE set SVE get FPSIMD for VL 3488
4658 16:59:56.579217 # ok 2928 # SKIP Streaming SVE set FPSIMD get SVE for VL 3488
4659 16:59:56.579326 # ok 2929 Set Streaming SVE VL 3504
4660 16:59:56.579449 # ok 2930 # SKIP Streaming SVE set SVE get SVE for VL 3504
4661 16:59:56.579533 # ok 2931 # SKIP Streaming SVE set SVE get FPSIMD for VL 3504
4662 16:59:56.579613 # ok 2932 # SKIP Streaming SVE set FPSIMD get SVE for VL 3504
4663 16:59:56.579689 # ok 2933 Set Streaming SVE VL 3520
4664 16:59:56.579941 # ok 2934 # SKIP Streaming SVE set SVE get SVE for VL 3520
4665 16:59:56.580022 # ok 2935 # SKIP Streaming SVE set SVE get FPSIMD for VL 3520
4666 16:59:56.580097 # ok 2936 # SKIP Streaming SVE set FPSIMD get SVE for VL 3520
4667 16:59:56.580357 # ok 2937 Set Streaming SVE VL 3536
4668 16:59:56.580445 # ok 2938 # SKIP Streaming SVE set SVE get SVE for VL 3536
4669 16:59:56.580534 # ok 2939 # SKIP Streaming SVE set SVE get FPSIMD for VL 3536
4670 16:59:56.580823 # ok 2940 # SKIP Streaming SVE set FPSIMD get SVE for VL 3536
4671 16:59:56.580919 # ok 2941 Set Streaming SVE VL 3552
4672 16:59:56.581015 # ok 2942 # SKIP Streaming SVE set SVE get SVE for VL 3552
4673 16:59:56.581109 # ok 2943 # SKIP Streaming SVE set SVE get FPSIMD for VL 3552
4674 16:59:56.581380 # ok 2944 # SKIP Streaming SVE set FPSIMD get SVE for VL 3552
4675 16:59:56.581465 # ok 2945 Set Streaming SVE VL 3568
4676 16:59:56.586733 # ok 2946 # SKIP Streaming SVE set SVE get SVE for VL 3568
4677 16:59:56.587156 # ok 2947 # SKIP Streaming SVE set SVE get FPSIMD for VL 3568
4678 16:59:56.587288 # ok 2948 # SKIP Streaming SVE set FPSIMD get SVE for VL 3568
4679 16:59:56.587388 # ok 2949 Set Streaming SVE VL 3584
4680 16:59:56.587499 # ok 2950 # SKIP Streaming SVE set SVE get SVE for VL 3584
4681 16:59:56.587584 # ok 2951 # SKIP Streaming SVE set SVE get FPSIMD for VL 3584
4682 16:59:56.587684 # ok 2952 # SKIP Streaming SVE set FPSIMD get SVE for VL 3584
4683 16:59:56.587791 # ok 2953 Set Streaming SVE VL 3600
4684 16:59:56.588079 # ok 2954 # SKIP Streaming SVE set SVE get SVE for VL 3600
4685 16:59:56.588183 # ok 2955 # SKIP Streaming SVE set SVE get FPSIMD for VL 3600
4686 16:59:56.588283 # ok 2956 # SKIP Streaming SVE set FPSIMD get SVE for VL 3600
4687 16:59:56.588382 # ok 2957 Set Streaming SVE VL 3616
4688 16:59:56.588670 # ok 2958 # SKIP Streaming SVE set SVE get SVE for VL 3616
4689 16:59:56.588761 # ok 2959 # SKIP Streaming SVE set SVE get FPSIMD for VL 3616
4690 16:59:56.588860 # ok 2960 # SKIP Streaming SVE set FPSIMD get SVE for VL 3616
4691 16:59:56.588958 # ok 2961 Set Streaming SVE VL 3632
4692 16:59:56.589239 # ok 2962 # SKIP Streaming SVE set SVE get SVE for VL 3632
4693 16:59:56.589327 # ok 2963 # SKIP Streaming SVE set SVE get FPSIMD for VL 3632
4694 16:59:56.593061 # ok 2964 # SKIP Streaming SVE set FPSIMD get SVE for VL 3632
4695 16:59:56.593430 # ok 2965 Set Streaming SVE VL 3648
4696 16:59:56.593521 # ok 2966 # SKIP Streaming SVE set SVE get SVE for VL 3648
4697 16:59:56.594665 # ok 2967 # SKIP Streaming SVE set SVE get FPSIMD for VL 3648
4698 16:59:56.594963 # ok 2968 # SKIP Streaming SVE set FPSIMD get SVE for VL 3648
4699 16:59:56.595054 # ok 2969 Set Streaming SVE VL 3664
4700 16:59:56.595149 # ok 2970 # SKIP Streaming SVE set SVE get SVE for VL 3664
4701 16:59:56.595248 # ok 2971 # SKIP Streaming SVE set SVE get FPSIMD for VL 3664
4702 16:59:56.595538 # ok 2972 # SKIP Streaming SVE set FPSIMD get SVE for VL 3664
4703 16:59:56.595643 # ok 2973 Set Streaming SVE VL 3680
4704 16:59:56.595740 # ok 2974 # SKIP Streaming SVE set SVE get SVE for VL 3680
4705 16:59:56.596037 # ok 2975 # SKIP Streaming SVE set SVE get FPSIMD for VL 3680
4706 16:59:56.596165 # ok 2976 # SKIP Streaming SVE set FPSIMD get SVE for VL 3680
4707 16:59:56.596283 # ok 2977 Set Streaming SVE VL 3696
4708 16:59:56.596397 # ok 2978 # SKIP Streaming SVE set SVE get SVE for VL 3696
4709 16:59:56.596710 # ok 2979 # SKIP Streaming SVE set SVE get FPSIMD for VL 3696
4710 16:59:56.596834 # ok 2980 # SKIP Streaming SVE set FPSIMD get SVE for VL 3696
4711 16:59:56.596932 # ok 2981 Set Streaming SVE VL 3712
4712 16:59:56.597052 # ok 2982 # SKIP Streaming SVE set SVE get SVE for VL 3712
4713 16:59:56.597389 # ok 2983 # SKIP Streaming SVE set SVE get FPSIMD for VL 3712
4714 16:59:56.601396 # ok 2984 # SKIP Streaming SVE set FPSIMD get SVE for VL 3712
4715 16:59:56.606558 # ok 2985 Set Streaming SVE VL 3728
4716 16:59:56.606998 # ok 2986 # SKIP Streaming SVE set SVE get SVE for VL 3728
4717 16:59:56.607094 # ok 2987 # SKIP Streaming SVE set SVE get FPSIMD for VL 3728
4718 16:59:56.607193 # ok 2988 # SKIP Streaming SVE set FPSIMD get SVE for VL 3728
4719 16:59:56.607274 # ok 2989 Set Streaming SVE VL 3744
4720 16:59:56.607383 # ok 2990 # SKIP Streaming SVE set SVE get SVE for VL 3744
4721 16:59:56.607680 # ok 2991 # SKIP Streaming SVE set SVE get FPSIMD for VL 3744
4722 16:59:56.607773 # ok 2992 # SKIP Streaming SVE set FPSIMD get SVE for VL 3744
4723 16:59:56.607894 # ok 2993 Set Streaming SVE VL 3760
4724 16:59:56.608024 # ok 2994 # SKIP Streaming SVE set SVE get SVE for VL 3760
4725 16:59:56.608168 # ok 2995 # SKIP Streaming SVE set SVE get FPSIMD for VL 3760
4726 16:59:56.608318 # ok 2996 # SKIP Streaming SVE set FPSIMD get SVE for VL 3760
4727 16:59:56.608430 # ok 2997 Set Streaming SVE VL 3776
4728 16:59:56.608720 # ok 2998 # SKIP Streaming SVE set SVE get SVE for VL 3776
4729 16:59:56.608848 # ok 2999 # SKIP Streaming SVE set SVE get FPSIMD for VL 3776
4730 16:59:56.608973 # ok 3000 # SKIP Streaming SVE set FPSIMD get SVE for VL 3776
4731 16:59:56.609097 # ok 3001 Set Streaming SVE VL 3792
4732 16:59:56.609227 # ok 3002 # SKIP Streaming SVE set SVE get SVE for VL 3792
4733 16:59:56.614734 # ok 3003 # SKIP Streaming SVE set SVE get FPSIMD for VL 3792
4734 16:59:56.615279 # ok 3004 # SKIP Streaming SVE set FPSIMD get SVE for VL 3792
4735 16:59:56.615403 # ok 3005 Set Streaming SVE VL 3808
4736 16:59:56.615534 # ok 3006 # SKIP Streaming SVE set SVE get SVE for VL 3808
4737 16:59:56.615694 # ok 3007 # SKIP Streaming SVE set SVE get FPSIMD for VL 3808
4738 16:59:56.615887 # ok 3008 # SKIP Streaming SVE set FPSIMD get SVE for VL 3808
4739 16:59:56.616134 # ok 3009 Set Streaming SVE VL 3824
4740 16:59:56.616336 # ok 3010 # SKIP Streaming SVE set SVE get SVE for VL 3824
4741 16:59:56.616529 # ok 3011 # SKIP Streaming SVE set SVE get FPSIMD for VL 3824
4742 16:59:56.616706 # ok 3012 # SKIP Streaming SVE set FPSIMD get SVE for VL 3824
4743 16:59:56.616879 # ok 3013 Set Streaming SVE VL 3840
4744 16:59:56.617086 # ok 3014 # SKIP Streaming SVE set SVE get SVE for VL 3840
4745 16:59:56.617269 # ok 3015 # SKIP Streaming SVE set SVE get FPSIMD for VL 3840
4746 16:59:56.617443 # ok 3016 # SKIP Streaming SVE set FPSIMD get SVE for VL 3840
4747 16:59:56.617573 # ok 3017 Set Streaming SVE VL 3856
4748 16:59:56.617731 # ok 3018 # SKIP Streaming SVE set SVE get SVE for VL 3856
4749 16:59:56.617933 # ok 3019 # SKIP Streaming SVE set SVE get FPSIMD for VL 3856
4750 16:59:56.618109 # ok 3020 # SKIP Streaming SVE set FPSIMD get SVE for VL 3856
4751 16:59:56.618288 # ok 3021 Set Streaming SVE VL 3872
4752 16:59:56.622903 # ok 3022 # SKIP Streaming SVE set SVE get SVE for VL 3872
4753 16:59:56.623438 # ok 3023 # SKIP Streaming SVE set SVE get FPSIMD for VL 3872
4754 16:59:56.623596 # ok 3024 # SKIP Streaming SVE set FPSIMD get SVE for VL 3872
4755 16:59:56.623721 # ok 3025 Set Streaming SVE VL 3888
4756 16:59:56.623837 # ok 3026 # SKIP Streaming SVE set SVE get SVE for VL 3888
4757 16:59:56.624395 # ok 3027 # SKIP Streaming SVE set SVE get FPSIMD for VL 3888
4758 16:59:56.624885 # ok 3028 # SKIP Streaming SVE set FPSIMD get SVE for VL 3888
4759 16:59:56.625188 # ok 3029 Set Streaming SVE VL 3904
4760 16:59:56.625415 # ok 3030 # SKIP Streaming SVE set SVE get SVE for VL 3904
4761 16:59:56.625575 # ok 3031 # SKIP Streaming SVE set SVE get FPSIMD for VL 3904
4762 16:59:56.625721 # ok 3032 # SKIP Streaming SVE set FPSIMD get SVE for VL 3904
4763 16:59:56.625886 # ok 3033 Set Streaming SVE VL 3920
4764 16:59:56.631031 # ok 3034 # SKIP Streaming SVE set SVE get SVE for VL 3920
4765 16:59:56.631596 # ok 3035 # SKIP Streaming SVE set SVE get FPSIMD for VL 3920
4766 16:59:56.631764 # ok 3036 # SKIP Streaming SVE set FPSIMD get SVE for VL 3920
4767 16:59:56.631926 # ok 3037 Set Streaming SVE VL 3936
4768 16:59:56.632085 # ok 3038 # SKIP Streaming SVE set SVE get SVE for VL 3936
4769 16:59:56.632285 # ok 3039 # SKIP Streaming SVE set SVE get FPSIMD for VL 3936
4770 16:59:56.632457 # ok 3040 # SKIP Streaming SVE set FPSIMD get SVE for VL 3936
4771 16:59:56.632621 # ok 3041 Set Streaming SVE VL 3952
4772 16:59:56.632778 # ok 3042 # SKIP Streaming SVE set SVE get SVE for VL 3952
4773 16:59:56.632933 # ok 3043 # SKIP Streaming SVE set SVE get FPSIMD for VL 3952
4774 16:59:56.633092 # ok 3044 # SKIP Streaming SVE set FPSIMD get SVE for VL 3952
4775 16:59:56.633300 # ok 3045 Set Streaming SVE VL 3968
4776 16:59:56.633467 # ok 3046 # SKIP Streaming SVE set SVE get SVE for VL 3968
4777 16:59:56.633592 # ok 3047 # SKIP Streaming SVE set SVE get FPSIMD for VL 3968
4778 16:59:56.633731 # ok 3048 # SKIP Streaming SVE set FPSIMD get SVE for VL 3968
4779 16:59:56.633886 # ok 3049 Set Streaming SVE VL 3984
4780 16:59:56.634054 # ok 3050 # SKIP Streaming SVE set SVE get SVE for VL 3984
4781 16:59:56.634233 # ok 3051 # SKIP Streaming SVE set SVE get FPSIMD for VL 3984
4782 16:59:56.634469 # ok 3052 # SKIP Streaming SVE set FPSIMD get SVE for VL 3984
4783 16:59:56.634670 # ok 3053 Set Streaming SVE VL 4000
4784 16:59:56.634837 # ok 3054 # SKIP Streaming SVE set SVE get SVE for VL 4000
4785 16:59:56.634993 # ok 3055 # SKIP Streaming SVE set SVE get FPSIMD for VL 4000
4786 16:59:56.635190 # ok 3056 # SKIP Streaming SVE set FPSIMD get SVE for VL 4000
4787 16:59:56.635362 # ok 3057 Set Streaming SVE VL 4016
4788 16:59:56.635527 # ok 3058 # SKIP Streaming SVE set SVE get SVE for VL 4016
4789 16:59:56.635687 # ok 3059 # SKIP Streaming SVE set SVE get FPSIMD for VL 4016
4790 16:59:56.635849 # ok 3060 # SKIP Streaming SVE set FPSIMD get SVE for VL 4016
4791 16:59:56.636002 # ok 3061 Set Streaming SVE VL 4032
4792 16:59:56.636173 # ok 3062 # SKIP Streaming SVE set SVE get SVE for VL 4032
4793 16:59:56.636340 # ok 3063 # SKIP Streaming SVE set SVE get FPSIMD for VL 4032
4794 16:59:56.636544 # ok 3064 # SKIP Streaming SVE set FPSIMD get SVE for VL 4032
4795 16:59:56.636747 # ok 3065 Set Streaming SVE VL 4048
4796 16:59:56.636938 # ok 3066 # SKIP Streaming SVE set SVE get SVE for VL 4048
4797 16:59:56.637110 # ok 3067 # SKIP Streaming SVE set SVE get FPSIMD for VL 4048
4798 16:59:56.637262 # ok 3068 # SKIP Streaming SVE set FPSIMD get SVE for VL 4048
4799 16:59:56.637407 # ok 3069 Set Streaming SVE VL 4064
4800 16:59:56.637730 # ok 3070 # SKIP Streaming SVE set SVE get SVE for VL 4064
4801 16:59:56.637883 # ok 3071 # SKIP Streaming SVE set SVE get FPSIMD for VL 4064
4802 16:59:56.638007 # ok 3072 # SKIP Streaming SVE set FPSIMD get SVE for VL 4064
4803 16:59:56.638123 # ok 3073 Set Streaming SVE VL 4080
4804 16:59:56.638238 # ok 3074 # SKIP Streaming SVE set SVE get SVE for VL 4080
4805 16:59:56.638353 # ok 3075 # SKIP Streaming SVE set SVE get FPSIMD for VL 4080
4806 16:59:56.638467 # ok 3076 # SKIP Streaming SVE set FPSIMD get SVE for VL 4080
4807 16:59:56.638585 # ok 3077 Set Streaming SVE VL 4096
4808 16:59:56.644396 # ok 3078 # SKIP Streaming SVE set SVE get SVE for VL 4096
4809 16:59:56.644890 # ok 3079 # SKIP Streaming SVE set SVE get FPSIMD for VL 4096
4810 16:59:56.645079 # ok 3080 # SKIP Streaming SVE set FPSIMD get SVE for VL 4096
4811 16:59:56.645247 # ok 3081 Set Streaming SVE VL 4112
4812 16:59:56.645398 # ok 3082 # SKIP Streaming SVE set SVE get SVE for VL 4112
4813 16:59:56.645568 # ok 3083 # SKIP Streaming SVE set SVE get FPSIMD for VL 4112
4814 16:59:56.645766 # ok 3084 # SKIP Streaming SVE set FPSIMD get SVE for VL 4112
4815 16:59:56.645939 # ok 3085 Set Streaming SVE VL 4128
4816 16:59:56.646107 # ok 3086 # SKIP Streaming SVE set SVE get SVE for VL 4128
4817 16:59:56.646250 # ok 3087 # SKIP Streaming SVE set SVE get FPSIMD for VL 4128
4818 16:59:56.651188 # ok 3088 # SKIP Streaming SVE set FPSIMD get SVE for VL 4128
4819 16:59:56.651700 # ok 3089 Set Streaming SVE VL 4144
4820 16:59:56.651865 # ok 3090 # SKIP Streaming SVE set SVE get SVE for VL 4144
4821 16:59:56.652014 # ok 3091 # SKIP Streaming SVE set SVE get FPSIMD for VL 4144
4822 16:59:56.652145 # ok 3092 # SKIP Streaming SVE set FPSIMD get SVE for VL 4144
4823 16:59:56.652290 # ok 3093 Set Streaming SVE VL 4160
4824 16:59:56.652480 # ok 3094 # SKIP Streaming SVE set SVE get SVE for VL 4160
4825 16:59:56.652654 # ok 3095 # SKIP Streaming SVE set SVE get FPSIMD for VL 4160
4826 16:59:56.652809 # ok 3096 # SKIP Streaming SVE set FPSIMD get SVE for VL 4160
4827 16:59:56.652965 # ok 3097 Set Streaming SVE VL 4176
4828 16:59:56.653119 # ok 3098 # SKIP Streaming SVE set SVE get SVE for VL 4176
4829 16:59:56.653265 # ok 3099 # SKIP Streaming SVE set SVE get FPSIMD for VL 4176
4830 16:59:56.653424 # ok 3100 # SKIP Streaming SVE set FPSIMD get SVE for VL 4176
4831 16:59:56.653546 # ok 3101 Set Streaming SVE VL 4192
4832 16:59:56.653673 # ok 3102 # SKIP Streaming SVE set SVE get SVE for VL 4192
4833 16:59:56.653791 # ok 3103 # SKIP Streaming SVE set SVE get FPSIMD for VL 4192
4834 16:59:56.653907 # ok 3104 # SKIP Streaming SVE set FPSIMD get SVE for VL 4192
4835 16:59:56.654024 # ok 3105 Set Streaming SVE VL 4208
4836 16:59:56.658579 # ok 3106 # SKIP Streaming SVE set SVE get SVE for VL 4208
4837 16:59:56.659051 # ok 3107 # SKIP Streaming SVE set SVE get FPSIMD for VL 4208
4838 16:59:56.659244 # ok 3108 # SKIP Streaming SVE set FPSIMD get SVE for VL 4208
4839 16:59:56.659419 # ok 3109 Set Streaming SVE VL 4224
4840 16:59:56.659599 # ok 3110 # SKIP Streaming SVE set SVE get SVE for VL 4224
4841 16:59:56.659832 # ok 3111 # SKIP Streaming SVE set SVE get FPSIMD for VL 4224
4842 16:59:56.660016 # ok 3112 # SKIP Streaming SVE set FPSIMD get SVE for VL 4224
4843 16:59:56.660188 # ok 3113 Set Streaming SVE VL 4240
4844 16:59:56.660381 # ok 3114 # SKIP Streaming SVE set SVE get SVE for VL 4240
4845 16:59:56.660586 # ok 3115 # SKIP Streaming SVE set SVE get FPSIMD for VL 4240
4846 16:59:56.660779 # ok 3116 # SKIP Streaming SVE set FPSIMD get SVE for VL 4240
4847 16:59:56.660952 # ok 3117 Set Streaming SVE VL 4256
4848 16:59:56.661096 # ok 3118 # SKIP Streaming SVE set SVE get SVE for VL 4256
4849 16:59:56.661311 # ok 3119 # SKIP Streaming SVE set SVE get FPSIMD for VL 4256
4850 16:59:56.661468 # ok 3120 # SKIP Streaming SVE set FPSIMD get SVE for VL 4256
4851 16:59:56.661623 # ok 3121 Set Streaming SVE VL 4272
4852 16:59:56.661793 # ok 3122 # SKIP Streaming SVE set SVE get SVE for VL 4272
4853 16:59:56.661913 # ok 3123 # SKIP Streaming SVE set SVE get FPSIMD for VL 4272
4854 16:59:56.662031 # ok 3124 # SKIP Streaming SVE set FPSIMD get SVE for VL 4272
4855 16:59:56.662145 # ok 3125 Set Streaming SVE VL 4288
4856 16:59:56.662259 # ok 3126 # SKIP Streaming SVE set SVE get SVE for VL 4288
4857 16:59:56.662374 # ok 3127 # SKIP Streaming SVE set SVE get FPSIMD for VL 4288
4858 16:59:56.662488 # ok 3128 # SKIP Streaming SVE set FPSIMD get SVE for VL 4288
4859 16:59:56.662603 # ok 3129 Set Streaming SVE VL 4304
4860 16:59:56.662717 # ok 3130 # SKIP Streaming SVE set SVE get SVE for VL 4304
4861 16:59:56.670579 # ok 3131 # SKIP Streaming SVE set SVE get FPSIMD for VL 4304
4862 16:59:56.671130 # ok 3132 # SKIP Streaming SVE set FPSIMD get SVE for VL 4304
4863 16:59:56.671331 # ok 3133 Set Streaming SVE VL 4320
4864 16:59:56.671516 # ok 3134 # SKIP Streaming SVE set SVE get SVE for VL 4320
4865 16:59:56.671676 # ok 3135 # SKIP Streaming SVE set SVE get FPSIMD for VL 4320
4866 16:59:56.671835 # ok 3136 # SKIP Streaming SVE set FPSIMD get SVE for VL 4320
4867 16:59:56.671966 # ok 3137 Set Streaming SVE VL 4336
4868 16:59:56.672093 # ok 3138 # SKIP Streaming SVE set SVE get SVE for VL 4336
4869 16:59:56.672216 # ok 3139 # SKIP Streaming SVE set SVE get FPSIMD for VL 4336
4870 16:59:56.672339 # ok 3140 # SKIP Streaming SVE set FPSIMD get SVE for VL 4336
4871 16:59:56.672461 # ok 3141 Set Streaming SVE VL 4352
4872 16:59:56.672587 # ok 3142 # SKIP Streaming SVE set SVE get SVE for VL 4352
4873 16:59:56.672744 # ok 3143 # SKIP Streaming SVE set SVE get FPSIMD for VL 4352
4874 16:59:56.672875 # ok 3144 # SKIP Streaming SVE set FPSIMD get SVE for VL 4352
4875 16:59:56.673001 # ok 3145 Set Streaming SVE VL 4368
4876 16:59:56.673125 # ok 3146 # SKIP Streaming SVE set SVE get SVE for VL 4368
4877 16:59:56.673310 # ok 3147 # SKIP Streaming SVE set SVE get FPSIMD for VL 4368
4878 16:59:56.673461 # ok 3148 # SKIP Streaming SVE set FPSIMD get SVE for VL 4368
4879 16:59:56.673580 # ok 3149 Set Streaming SVE VL 4384
4880 16:59:56.673732 # ok 3150 # SKIP Streaming SVE set SVE get SVE for VL 4384
4881 16:59:56.673905 # ok 3151 # SKIP Streaming SVE set SVE get FPSIMD for VL 4384
4882 16:59:56.674031 # ok 3152 # SKIP Streaming SVE set FPSIMD get SVE for VL 4384
4883 16:59:56.674148 # ok 3153 Set Streaming SVE VL 4400
4884 16:59:56.674262 # ok 3154 # SKIP Streaming SVE set SVE get SVE for VL 4400
4885 16:59:56.686561 # ok 3155 # SKIP Streaming SVE set SVE get FPSIMD for VL 4400
4886 16:59:56.687153 # ok 3156 # SKIP Streaming SVE set FPSIMD get SVE for VL 4400
4887 16:59:56.687386 # ok 3157 Set Streaming SVE VL 4416
4888 16:59:56.687549 # ok 3158 # SKIP Streaming SVE set SVE get SVE for VL 4416
4889 16:59:56.687702 # ok 3159 # SKIP Streaming SVE set SVE get FPSIMD for VL 4416
4890 16:59:56.687876 # ok 3160 # SKIP Streaming SVE set FPSIMD get SVE for VL 4416
4891 16:59:56.688052 # ok 3161 Set Streaming SVE VL 4432
4892 16:59:56.688220 # ok 3162 # SKIP Streaming SVE set SVE get SVE for VL 4432
4893 16:59:56.688368 # ok 3163 # SKIP Streaming SVE set SVE get FPSIMD for VL 4432
4894 16:59:56.688521 # ok 3164 # SKIP Streaming SVE set FPSIMD get SVE for VL 4432
4895 16:59:56.688683 # ok 3165 Set Streaming SVE VL 4448
4896 16:59:56.688823 # ok 3166 # SKIP Streaming SVE set SVE get SVE for VL 4448
4897 16:59:56.689022 # ok 3167 # SKIP Streaming SVE set SVE get FPSIMD for VL 4448
4898 16:59:56.689170 # ok 3168 # SKIP Streaming SVE set FPSIMD get SVE for VL 4448
4899 16:59:56.689334 # ok 3169 Set Streaming SVE VL 4464
4900 16:59:56.689483 # ok 3170 # SKIP Streaming SVE set SVE get SVE for VL 4464
4901 16:59:56.689628 # ok 3171 # SKIP Streaming SVE set SVE get FPSIMD for VL 4464
4902 16:59:56.689808 # ok 3172 # SKIP Streaming SVE set FPSIMD get SVE for VL 4464
4903 16:59:56.689978 # ok 3173 Set Streaming SVE VL 4480
4904 16:59:56.690147 # ok 3174 # SKIP Streaming SVE set SVE get SVE for VL 4480
4905 16:59:56.702614 # ok 3175 # SKIP Streaming SVE set SVE get FPSIMD for VL 4480
4906 16:59:56.703106 # ok 3176 # SKIP Streaming SVE set FPSIMD get SVE for VL 4480
4907 16:59:56.703757 # ok 3177 Set Streaming SVE VL 4496
4908 16:59:56.703914 # ok 3178 # SKIP Streaming SVE set SVE get SVE for VL 4496
4909 16:59:56.704114 # ok 3179 # SKIP Streaming SVE set SVE get FPSIMD for VL 4496
4910 16:59:56.704274 # ok 3180 # SKIP Streaming SVE set FPSIMD get SVE for VL 4496
4911 16:59:56.704426 # ok 3181 Set Streaming SVE VL 4512
4912 16:59:56.704611 # ok 3182 # SKIP Streaming SVE set SVE get SVE for VL 4512
4913 16:59:56.704772 # ok 3183 # SKIP Streaming SVE set SVE get FPSIMD for VL 4512
4914 16:59:56.704935 # ok 3184 # SKIP Streaming SVE set FPSIMD get SVE for VL 4512
4915 16:59:56.705082 # ok 3185 Set Streaming SVE VL 4528
4916 16:59:56.705245 # ok 3186 # SKIP Streaming SVE set SVE get SVE for VL 4528
4917 16:59:56.705450 # ok 3187 # SKIP Streaming SVE set SVE get FPSIMD for VL 4528
4918 16:59:56.705587 # ok 3188 # SKIP Streaming SVE set FPSIMD get SVE for VL 4528
4919 16:59:56.705746 # ok 3189 Set Streaming SVE VL 4544
4920 16:59:56.705888 # ok 3190 # SKIP Streaming SVE set SVE get SVE for VL 4544
4921 16:59:56.722279 # ok 3191 # SKIP Streaming SVE set SVE get FPSIMD for VL 4544
4922 16:59:56.722835 # ok 3192 # SKIP Streaming SVE set FPSIMD get SVE for VL 4544
4923 16:59:56.723037 # ok 3193 Set Streaming SVE VL 4560
4924 16:59:56.723236 # ok 3194 # SKIP Streaming SVE set SVE get SVE for VL 4560
4925 16:59:56.723415 # ok 3195 # SKIP Streaming SVE set SVE get FPSIMD for VL 4560
4926 16:59:56.723561 # ok 3196 # SKIP Streaming SVE set FPSIMD get SVE for VL 4560
4927 16:59:56.723742 # ok 3197 Set Streaming SVE VL 4576
4928 16:59:56.723888 # ok 3198 # SKIP Streaming SVE set SVE get SVE for VL 4576
4929 16:59:56.724045 # ok 3199 # SKIP Streaming SVE set SVE get FPSIMD for VL 4576
4930 16:59:56.724204 # ok 3200 # SKIP Streaming SVE set FPSIMD get SVE for VL 4576
4931 16:59:56.724365 # ok 3201 Set Streaming SVE VL 4592
4932 16:59:56.724522 # ok 3202 # SKIP Streaming SVE set SVE get SVE for VL 4592
4933 16:59:56.724672 # ok 3203 # SKIP Streaming SVE set SVE get FPSIMD for VL 4592
4934 16:59:56.724846 # ok 3204 # SKIP Streaming SVE set FPSIMD get SVE for VL 4592
4935 16:59:56.724985 # ok 3205 Set Streaming SVE VL 4608
4936 16:59:56.725100 # ok 3206 # SKIP Streaming SVE set SVE get SVE for VL 4608
4937 16:59:56.725228 # ok 3207 # SKIP Streaming SVE set SVE get FPSIMD for VL 4608
4938 16:59:56.725380 # ok 3208 # SKIP Streaming SVE set FPSIMD get SVE for VL 4608
4939 16:59:56.725504 # ok 3209 Set Streaming SVE VL 4624
4940 16:59:56.725624 # ok 3210 # SKIP Streaming SVE set SVE get SVE for VL 4624
4941 16:59:56.725829 # ok 3211 # SKIP Streaming SVE set SVE get FPSIMD for VL 4624
4942 16:59:56.726060 # ok 3212 # SKIP Streaming SVE set FPSIMD get SVE for VL 4624
4943 16:59:56.726249 # ok 3213 Set Streaming SVE VL 4640
4944 16:59:56.726406 # ok 3214 # SKIP Streaming SVE set SVE get SVE for VL 4640
4945 16:59:56.734638 # ok 3215 # SKIP Streaming SVE set SVE get FPSIMD for VL 4640
4946 16:59:56.735199 # ok 3216 # SKIP Streaming SVE set FPSIMD get SVE for VL 4640
4947 16:59:56.735372 # ok 3217 Set Streaming SVE VL 4656
4948 16:59:56.735535 # ok 3218 # SKIP Streaming SVE set SVE get SVE for VL 4656
4949 16:59:56.735693 # ok 3219 # SKIP Streaming SVE set SVE get FPSIMD for VL 4656
4950 16:59:56.735852 # ok 3220 # SKIP Streaming SVE set FPSIMD get SVE for VL 4656
4951 16:59:56.736104 # ok 3221 Set Streaming SVE VL 4672
4952 16:59:56.736294 # ok 3222 # SKIP Streaming SVE set SVE get SVE for VL 4672
4953 16:59:56.736454 # ok 3223 # SKIP Streaming SVE set SVE get FPSIMD for VL 4672
4954 16:59:56.736617 # ok 3224 # SKIP Streaming SVE set FPSIMD get SVE for VL 4672
4955 16:59:56.736827 # ok 3225 Set Streaming SVE VL 4688
4956 16:59:56.736987 # ok 3226 # SKIP Streaming SVE set SVE get SVE for VL 4688
4957 16:59:56.737155 # ok 3227 # SKIP Streaming SVE set SVE get FPSIMD for VL 4688
4958 16:59:56.737384 # ok 3228 # SKIP Streaming SVE set FPSIMD get SVE for VL 4688
4959 16:59:56.737531 # ok 3229 Set Streaming SVE VL 4704
4960 16:59:56.737687 # ok 3230 # SKIP Streaming SVE set SVE get SVE for VL 4704
4961 16:59:56.737833 # ok 3231 # SKIP Streaming SVE set SVE get FPSIMD for VL 4704
4962 16:59:56.737994 # ok 3232 # SKIP Streaming SVE set FPSIMD get SVE for VL 4704
4963 16:59:56.738154 # ok 3233 Set Streaming SVE VL 4720
4964 16:59:56.738297 # ok 3234 # SKIP Streaming SVE set SVE get SVE for VL 4720
4965 16:59:56.738449 # ok 3235 # SKIP Streaming SVE set SVE get FPSIMD for VL 4720
4966 16:59:56.738593 # ok 3236 # SKIP Streaming SVE set FPSIMD get SVE for VL 4720
4967 16:59:56.738733 # ok 3237 Set Streaming SVE VL 4736
4968 16:59:56.749081 # ok 3238 # SKIP Streaming SVE set SVE get SVE for VL 4736
4969 16:59:56.749574 # ok 3239 # SKIP Streaming SVE set SVE get FPSIMD for VL 4736
4970 16:59:56.752530 # ok 3240 # SKIP Streaming SVE set FPSIMD get SVE for VL 4736
4971 16:59:56.755129 # ok 3241 Set Streaming SVE VL 4752
4972 16:59:56.755347 # ok 3242 # SKIP Streaming SVE set SVE get SVE for VL 4752
4973 16:59:56.755521 # ok 3243 # SKIP Streaming SVE set SVE get FPSIMD for VL 4752
4974 16:59:56.755722 # ok 3244 # SKIP Streaming SVE set FPSIMD get SVE for VL 4752
4975 16:59:56.755904 # ok 3245 Set Streaming SVE VL 4768
4976 16:59:56.756116 # ok 3246 # SKIP Streaming SVE set SVE get SVE for VL 4768
4977 16:59:56.756287 # ok 3247 # SKIP Streaming SVE set SVE get FPSIMD for VL 4768
4978 16:59:56.756483 # ok 3248 # SKIP Streaming SVE set FPSIMD get SVE for VL 4768
4979 16:59:56.756657 # ok 3249 Set Streaming SVE VL 4784
4980 16:59:56.756858 # ok 3250 # SKIP Streaming SVE set SVE get SVE for VL 4784
4981 16:59:56.757063 # ok 3251 # SKIP Streaming SVE set SVE get FPSIMD for VL 4784
4982 16:59:56.757234 # ok 3252 # SKIP Streaming SVE set FPSIMD get SVE for VL 4784
4983 16:59:56.757378 # ok 3253 Set Streaming SVE VL 4800
4984 16:59:56.757556 # ok 3254 # SKIP Streaming SVE set SVE get SVE for VL 4800
4985 16:59:56.757707 # ok 3255 # SKIP Streaming SVE set SVE get FPSIMD for VL 4800
4986 16:59:56.757851 # ok 3256 # SKIP Streaming SVE set FPSIMD get SVE for VL 4800
4987 16:59:56.757992 # ok 3257 Set Streaming SVE VL 4816
4988 16:59:56.758133 # ok 3258 # SKIP Streaming SVE set SVE get SVE for VL 4816
4989 16:59:56.758272 # ok 3259 # SKIP Streaming SVE set SVE get FPSIMD for VL 4816
4990 16:59:56.761072 # ok 3260 # SKIP Streaming SVE set FPSIMD get SVE for VL 4816
4991 16:59:56.761292 # ok 3261 Set Streaming SVE VL 4832
4992 16:59:56.761447 # ok 3262 # SKIP Streaming SVE set SVE get SVE for VL 4832
4993 16:59:56.770758 # ok 3263 # SKIP Streaming SVE set SVE get FPSIMD for VL 4832
4994 16:59:56.771345 # ok 3264 # SKIP Streaming SVE set FPSIMD get SVE for VL 4832
4995 16:59:56.771525 # ok 3265 Set Streaming SVE VL 4848
4996 16:59:56.771670 # ok 3266 # SKIP Streaming SVE set SVE get SVE for VL 4848
4997 16:59:56.771814 # ok 3267 # SKIP Streaming SVE set SVE get FPSIMD for VL 4848
4998 16:59:56.771974 # ok 3268 # SKIP Streaming SVE set FPSIMD get SVE for VL 4848
4999 16:59:56.772164 # ok 3269 Set Streaming SVE VL 4864
5000 16:59:56.772333 # ok 3270 # SKIP Streaming SVE set SVE get SVE for VL 4864
5001 16:59:56.772495 # ok 3271 # SKIP Streaming SVE set SVE get FPSIMD for VL 4864
5002 16:59:56.772660 # ok 3272 # SKIP Streaming SVE set FPSIMD get SVE for VL 4864
5003 16:59:56.772820 # ok 3273 Set Streaming SVE VL 4880
5004 16:59:56.772973 # ok 3274 # SKIP Streaming SVE set SVE get SVE for VL 4880
5005 16:59:56.773171 # ok 3275 # SKIP Streaming SVE set SVE get FPSIMD for VL 4880
5006 16:59:56.773300 # ok 3276 # SKIP Streaming SVE set FPSIMD get SVE for VL 4880
5007 16:59:56.773416 # ok 3277 Set Streaming SVE VL 4896
5008 16:59:56.773528 # ok 3278 # SKIP Streaming SVE set SVE get SVE for VL 4896
5009 16:59:56.773639 # ok 3279 # SKIP Streaming SVE set SVE get FPSIMD for VL 4896
5010 16:59:56.773847 # ok 3280 # SKIP Streaming SVE set FPSIMD get SVE for VL 4896
5011 16:59:56.774035 # ok 3281 Set Streaming SVE VL 4912
5012 16:59:56.774177 # ok 3282 # SKIP Streaming SVE set SVE get SVE for VL 4912
5013 16:59:56.774317 # ok 3283 # SKIP Streaming SVE set SVE get FPSIMD for VL 4912
5014 16:59:56.774490 # ok 3284 # SKIP Streaming SVE set FPSIMD get SVE for VL 4912
5015 16:59:56.779034 # ok 3285 Set Streaming SVE VL 4928
5016 16:59:56.779298 # ok 3286 # SKIP Streaming SVE set SVE get SVE for VL 4928
5017 16:59:56.779496 # ok 3287 # SKIP Streaming SVE set SVE get FPSIMD for VL 4928
5018 16:59:56.779666 # ok 3288 # SKIP Streaming SVE set FPSIMD get SVE for VL 4928
5019 16:59:56.779829 # ok 3289 Set Streaming SVE VL 4944
5020 16:59:56.779993 # ok 3290 # SKIP Streaming SVE set SVE get SVE for VL 4944
5021 16:59:56.780190 # ok 3291 # SKIP Streaming SVE set SVE get FPSIMD for VL 4944
5022 16:59:56.780357 # ok 3292 # SKIP Streaming SVE set FPSIMD get SVE for VL 4944
5023 16:59:56.780518 # ok 3293 Set Streaming SVE VL 4960
5024 16:59:56.780677 # ok 3294 # SKIP Streaming SVE set SVE get SVE for VL 4960
5025 16:59:56.780834 # ok 3295 # SKIP Streaming SVE set SVE get FPSIMD for VL 4960
5026 16:59:56.781029 # ok 3296 # SKIP Streaming SVE set FPSIMD get SVE for VL 4960
5027 16:59:56.781191 # ok 3297 Set Streaming SVE VL 4976
5028 16:59:56.781312 # ok 3298 # SKIP Streaming SVE set SVE get SVE for VL 4976
5029 16:59:56.781423 # ok 3299 # SKIP Streaming SVE set SVE get FPSIMD for VL 4976
5030 16:59:56.781535 # ok 3300 # SKIP Streaming SVE set FPSIMD get SVE for VL 4976
5031 16:59:56.781663 # ok 3301 Set Streaming SVE VL 4992
5032 16:59:56.781904 # ok 3302 # SKIP Streaming SVE set SVE get SVE for VL 4992
5033 16:59:56.786529 # ok 3303 # SKIP Streaming SVE set SVE get FPSIMD for VL 4992
5034 16:59:56.787039 # ok 3304 # SKIP Streaming SVE set FPSIMD get SVE for VL 4992
5035 16:59:56.787238 # ok 3305 Set Streaming SVE VL 5008
5036 16:59:56.787409 # ok 3306 # SKIP Streaming SVE set SVE get SVE for VL 5008
5037 16:59:56.787578 # ok 3307 # SKIP Streaming SVE set SVE get FPSIMD for VL 5008
5038 16:59:56.787745 # ok 3308 # SKIP Streaming SVE set FPSIMD get SVE for VL 5008
5039 16:59:56.787946 # ok 3309 Set Streaming SVE VL 5024
5040 16:59:56.788116 # ok 3310 # SKIP Streaming SVE set SVE get SVE for VL 5024
5041 16:59:56.788287 # ok 3311 # SKIP Streaming SVE set SVE get FPSIMD for VL 5024
5042 16:59:56.788499 # ok 3312 # SKIP Streaming SVE set FPSIMD get SVE for VL 5024
5043 16:59:56.788676 # ok 3313 Set Streaming SVE VL 5040
5044 16:59:56.788835 # ok 3314 # SKIP Streaming SVE set SVE get SVE for VL 5040
5045 16:59:56.788984 # ok 3315 # SKIP Streaming SVE set SVE get FPSIMD for VL 5040
5046 16:59:56.789229 # ok 3316 # SKIP Streaming SVE set FPSIMD get SVE for VL 5040
5047 16:59:56.789388 # ok 3317 Set Streaming SVE VL 5056
5048 16:59:56.789546 # ok 3318 # SKIP Streaming SVE set SVE get SVE for VL 5056
5049 16:59:56.789709 # ok 3319 # SKIP Streaming SVE set SVE get FPSIMD for VL 5056
5050 16:59:56.789831 # ok 3320 # SKIP Streaming SVE set FPSIMD get SVE for VL 5056
5051 16:59:56.789949 # ok 3321 Set Streaming SVE VL 5072
5052 16:59:56.790067 # ok 3322 # SKIP Streaming SVE set SVE get SVE for VL 5072
5053 16:59:56.790183 # ok 3323 # SKIP Streaming SVE set SVE get FPSIMD for VL 5072
5054 16:59:56.790299 # ok 3324 # SKIP Streaming SVE set FPSIMD get SVE for VL 5072
5055 16:59:56.790415 # ok 3325 Set Streaming SVE VL 5088
5056 16:59:56.795052 # ok 3326 # SKIP Streaming SVE set SVE get SVE for VL 5088
5057 16:59:56.796199 # ok 3327 # SKIP Streaming SVE set SVE get FPSIMD for VL 5088
5058 16:59:56.796400 # ok 3328 # SKIP Streaming SVE set FPSIMD get SVE for VL 5088
5059 16:59:56.796601 # ok 3329 Set Streaming SVE VL 5104
5060 16:59:56.796770 # ok 3330 # SKIP Streaming SVE set SVE get SVE for VL 5104
5061 16:59:56.796929 # ok 3331 # SKIP Streaming SVE set SVE get FPSIMD for VL 5104
5062 16:59:56.797119 # ok 3332 # SKIP Streaming SVE set FPSIMD get SVE for VL 5104
5063 16:59:56.797251 # ok 3333 Set Streaming SVE VL 5120
5064 16:59:56.797367 # ok 3334 # SKIP Streaming SVE set SVE get SVE for VL 5120
5065 16:59:56.797482 # ok 3335 # SKIP Streaming SVE set SVE get FPSIMD for VL 5120
5066 16:59:56.797618 # ok 3336 # SKIP Streaming SVE set FPSIMD get SVE for VL 5120
5067 16:59:56.798074 # ok 3337 Set Streaming SVE VL 5136
5068 16:59:56.798280 # ok 3338 # SKIP Streaming SVE set SVE get SVE for VL 5136
5069 16:59:56.798449 # ok 3339 # SKIP Streaming SVE set SVE get FPSIMD for VL 5136
5070 16:59:56.798605 # ok 3340 # SKIP Streaming SVE set FPSIMD get SVE for VL 5136
5071 16:59:56.798762 # ok 3341 Set Streaming SVE VL 5152
5072 16:59:56.798948 # ok 3342 # SKIP Streaming SVE set SVE get SVE for VL 5152
5073 16:59:56.799087 # ok 3343 # SKIP Streaming SVE set SVE get FPSIMD for VL 5152
5074 16:59:56.799229 # ok 3344 # SKIP Streaming SVE set FPSIMD get SVE for VL 5152
5075 16:59:56.799403 # ok 3345 Set Streaming SVE VL 5168
5076 16:59:56.799561 # ok 3346 # SKIP Streaming SVE set SVE get SVE for VL 5168
5077 16:59:56.799721 # ok 3347 # SKIP Streaming SVE set SVE get FPSIMD for VL 5168
5078 16:59:56.799841 # ok 3348 # SKIP Streaming SVE set FPSIMD get SVE for VL 5168
5079 16:59:56.799985 # ok 3349 Set Streaming SVE VL 5184
5080 16:59:56.800108 # ok 3350 # SKIP Streaming SVE set SVE get SVE for VL 5184
5081 16:59:56.800226 # ok 3351 # SKIP Streaming SVE set SVE get FPSIMD for VL 5184
5082 16:59:56.800342 # ok 3352 # SKIP Streaming SVE set FPSIMD get SVE for VL 5184
5083 16:59:56.800459 # ok 3353 Set Streaming SVE VL 5200
5084 16:59:56.800598 # ok 3354 # SKIP Streaming SVE set SVE get SVE for VL 5200
5085 16:59:56.800720 # ok 3355 # SKIP Streaming SVE set SVE get FPSIMD for VL 5200
5086 16:59:56.800838 # ok 3356 # SKIP Streaming SVE set FPSIMD get SVE for VL 5200
5087 16:59:56.800993 # ok 3357 Set Streaming SVE VL 5216
5088 16:59:56.801165 # ok 3358 # SKIP Streaming SVE set SVE get SVE for VL 5216
5089 16:59:56.801310 # ok 3359 # SKIP Streaming SVE set SVE get FPSIMD for VL 5216
5090 16:59:56.801488 # ok 3360 # SKIP Streaming SVE set FPSIMD get SVE for VL 5216
5091 16:59:56.801625 # ok 3361 Set Streaming SVE VL 5232
5092 16:59:56.801781 # ok 3362 # SKIP Streaming SVE set SVE get SVE for VL 5232
5093 16:59:56.801924 # ok 3363 # SKIP Streaming SVE set SVE get FPSIMD for VL 5232
5094 16:59:56.802066 # ok 3364 # SKIP Streaming SVE set FPSIMD get SVE for VL 5232
5095 16:59:56.808287 # ok 3365 Set Streaming SVE VL 5248
5096 16:59:56.808863 # ok 3366 # SKIP Streaming SVE set SVE get SVE for VL 5248
5097 16:59:56.809061 # ok 3367 # SKIP Streaming SVE set SVE get FPSIMD for VL 5248
5098 16:59:56.809249 # ok 3368 # SKIP Streaming SVE set FPSIMD get SVE for VL 5248
5099 16:59:56.809386 # ok 3369 Set Streaming SVE VL 5264
5100 16:59:56.809502 # ok 3370 # SKIP Streaming SVE set SVE get SVE for VL 5264
5101 16:59:56.809716 # ok 3371 # SKIP Streaming SVE set SVE get FPSIMD for VL 5264
5102 16:59:56.809871 # ok 3372 # SKIP Streaming SVE set FPSIMD get SVE for VL 5264
5103 16:59:56.810033 # ok 3373 Set Streaming SVE VL 5280
5104 16:59:56.816113 # ok 3374 # SKIP Streaming SVE set SVE get SVE for VL 5280
5105 16:59:56.816452 # ok 3375 # SKIP Streaming SVE set SVE get FPSIMD for VL 5280
5106 16:59:56.816627 # ok 3376 # SKIP Streaming SVE set FPSIMD get SVE for VL 5280
5107 16:59:56.816785 # ok 3377 Set Streaming SVE VL 5296
5108 16:59:56.816943 # ok 3378 # SKIP Streaming SVE set SVE get SVE for VL 5296
5109 16:59:56.817134 # ok 3379 # SKIP Streaming SVE set SVE get FPSIMD for VL 5296
5110 16:59:56.817275 # ok 3380 # SKIP Streaming SVE set FPSIMD get SVE for VL 5296
5111 16:59:56.817393 # ok 3381 Set Streaming SVE VL 5312
5112 16:59:56.817506 # ok 3382 # SKIP Streaming SVE set SVE get SVE for VL 5312
5113 16:59:56.817621 # ok 3383 # SKIP Streaming SVE set SVE get FPSIMD for VL 5312
5114 16:59:56.817847 # ok 3384 # SKIP Streaming SVE set FPSIMD get SVE for VL 5312
5115 16:59:56.820892 # ok 3385 Set Streaming SVE VL 5328
5116 16:59:56.821354 # ok 3386 # SKIP Streaming SVE set SVE get SVE for VL 5328
5117 16:59:56.821510 # ok 3387 # SKIP Streaming SVE set SVE get FPSIMD for VL 5328
5118 16:59:56.821873 # ok 3388 # SKIP Streaming SVE set FPSIMD get SVE for VL 5328
5119 16:59:56.822248 # ok 3389 Set Streaming SVE VL 5344
5120 16:59:56.822354 # ok 3390 # SKIP Streaming SVE set SVE get SVE for VL 5344
5121 16:59:56.822442 # ok 3391 # SKIP Streaming SVE set SVE get FPSIMD for VL 5344
5122 16:59:56.822541 # ok 3392 # SKIP Streaming SVE set FPSIMD get SVE for VL 5344
5123 16:59:56.822625 # ok 3393 Set Streaming SVE VL 5360
5124 16:59:56.822720 # ok 3394 # SKIP Streaming SVE set SVE get SVE for VL 5360
5125 16:59:56.823018 # ok 3395 # SKIP Streaming SVE set SVE get FPSIMD for VL 5360
5126 16:59:56.823120 # ok 3396 # SKIP Streaming SVE set FPSIMD get SVE for VL 5360
5127 16:59:56.823220 # ok 3397 Set Streaming SVE VL 5376
5128 16:59:56.823520 # ok 3398 # SKIP Streaming SVE set SVE get SVE for VL 5376
5129 16:59:56.823622 # ok 3399 # SKIP Streaming SVE set SVE get FPSIMD for VL 5376
5130 16:59:56.823717 # ok 3400 # SKIP Streaming SVE set FPSIMD get SVE for VL 5376
5131 16:59:56.823817 # ok 3401 Set Streaming SVE VL 5392
5132 16:59:56.824144 # ok 3402 # SKIP Streaming SVE set SVE get SVE for VL 5392
5133 16:59:56.824370 # ok 3403 # SKIP Streaming SVE set SVE get FPSIMD for VL 5392
5134 16:59:56.824629 # ok 3404 # SKIP Streaming SVE set FPSIMD get SVE for VL 5392
5135 16:59:56.824803 # ok 3405 Set Streaming SVE VL 5408
5136 16:59:56.824958 # ok 3406 # SKIP Streaming SVE set SVE get SVE for VL 5408
5137 16:59:56.825118 # ok 3407 # SKIP Streaming SVE set SVE get FPSIMD for VL 5408
5138 16:59:56.825277 # ok 3408 # SKIP Streaming SVE set FPSIMD get SVE for VL 5408
5139 16:59:56.825399 # ok 3409 Set Streaming SVE VL 5424
5140 16:59:56.825513 # ok 3410 # SKIP Streaming SVE set SVE get SVE for VL 5424
5141 16:59:56.830478 # ok 3411 # SKIP Streaming SVE set SVE get FPSIMD for VL 5424
5142 16:59:56.831019 # ok 3412 # SKIP Streaming SVE set FPSIMD get SVE for VL 5424
5143 16:59:56.831216 # ok 3413 Set Streaming SVE VL 5440
5144 16:59:56.831386 # ok 3414 # SKIP Streaming SVE set SVE get SVE for VL 5440
5145 16:59:56.831554 # ok 3415 # SKIP Streaming SVE set SVE get FPSIMD for VL 5440
5146 16:59:56.831750 # ok 3416 # SKIP Streaming SVE set FPSIMD get SVE for VL 5440
5147 16:59:56.831913 # ok 3417 Set Streaming SVE VL 5456
5148 16:59:56.832054 # ok 3418 # SKIP Streaming SVE set SVE get SVE for VL 5456
5149 16:59:56.832205 # ok 3419 # SKIP Streaming SVE set SVE get FPSIMD for VL 5456
5150 16:59:56.832352 # ok 3420 # SKIP Streaming SVE set FPSIMD get SVE for VL 5456
5151 16:59:56.832514 # ok 3421 Set Streaming SVE VL 5472
5152 16:59:56.832675 # ok 3422 # SKIP Streaming SVE set SVE get SVE for VL 5472
5153 16:59:56.832872 # ok 3423 # SKIP Streaming SVE set SVE get FPSIMD for VL 5472
5154 16:59:56.833040 # ok 3424 # SKIP Streaming SVE set FPSIMD get SVE for VL 5472
5155 16:59:56.833174 # ok 3425 Set Streaming SVE VL 5488
5156 16:59:56.833293 # ok 3426 # SKIP Streaming SVE set SVE get SVE for VL 5488
5157 16:59:56.833406 # ok 3427 # SKIP Streaming SVE set SVE get FPSIMD for VL 5488
5158 16:59:56.833518 # ok 3428 # SKIP Streaming SVE set FPSIMD get SVE for VL 5488
5159 16:59:56.833630 # ok 3429 Set Streaming SVE VL 5504
5160 16:59:56.833833 # ok 3430 # SKIP Streaming SVE set SVE get SVE for VL 5504
5161 16:59:56.834062 # ok 3431 # SKIP Streaming SVE set SVE get FPSIMD for VL 5504
5162 16:59:56.834249 # ok 3432 # SKIP Streaming SVE set FPSIMD get SVE for VL 5504
5163 16:59:56.834390 # ok 3433 Set Streaming SVE VL 5520
5164 16:59:56.842524 # ok 3434 # SKIP Streaming SVE set SVE get SVE for VL 5520
5165 16:59:56.842822 # ok 3435 # SKIP Streaming SVE set SVE get FPSIMD for VL 5520
5166 16:59:56.843075 # ok 3436 # SKIP Streaming SVE set FPSIMD get SVE for VL 5520
5167 16:59:56.843285 # ok 3437 Set Streaming SVE VL 5536
5168 16:59:56.843462 # ok 3438 # SKIP Streaming SVE set SVE get SVE for VL 5536
5169 16:59:56.843608 # ok 3439 # SKIP Streaming SVE set SVE get FPSIMD for VL 5536
5170 16:59:56.843804 # ok 3440 # SKIP Streaming SVE set FPSIMD get SVE for VL 5536
5171 16:59:56.843966 # ok 3441 Set Streaming SVE VL 5552
5172 16:59:56.844107 # ok 3442 # SKIP Streaming SVE set SVE get SVE for VL 5552
5173 16:59:56.844265 # ok 3443 # SKIP Streaming SVE set SVE get FPSIMD for VL 5552
5174 16:59:56.844414 # ok 3444 # SKIP Streaming SVE set FPSIMD get SVE for VL 5552
5175 16:59:56.844577 # ok 3445 Set Streaming SVE VL 5568
5176 16:59:56.844764 # ok 3446 # SKIP Streaming SVE set SVE get SVE for VL 5568
5177 16:59:56.844929 # ok 3447 # SKIP Streaming SVE set SVE get FPSIMD for VL 5568
5178 16:59:56.845093 # ok 3448 # SKIP Streaming SVE set FPSIMD get SVE for VL 5568
5179 16:59:56.845219 # ok 3449 Set Streaming SVE VL 5584
5180 16:59:56.845332 # ok 3450 # SKIP Streaming SVE set SVE get SVE for VL 5584
5181 16:59:56.845444 # ok 3451 # SKIP Streaming SVE set SVE get FPSIMD for VL 5584
5182 16:59:56.845623 # ok 3452 # SKIP Streaming SVE set FPSIMD get SVE for VL 5584
5183 16:59:56.845924 # ok 3453 Set Streaming SVE VL 5600
5184 16:59:56.846187 # ok 3454 # SKIP Streaming SVE set SVE get SVE for VL 5600
5185 16:59:56.846370 # ok 3455 # SKIP Streaming SVE set SVE get FPSIMD for VL 5600
5186 16:59:56.854265 # ok 3456 # SKIP Streaming SVE set FPSIMD get SVE for VL 5600
5187 16:59:56.854579 # ok 3457 Set Streaming SVE VL 5616
5188 16:59:56.854993 # ok 3458 # SKIP Streaming SVE set SVE get SVE for VL 5616
5189 16:59:56.855191 # ok 3459 # SKIP Streaming SVE set SVE get FPSIMD for VL 5616
5190 16:59:56.855354 # ok 3460 # SKIP Streaming SVE set FPSIMD get SVE for VL 5616
5191 16:59:56.855505 # ok 3461 Set Streaming SVE VL 5632
5192 16:59:56.855658 # ok 3462 # SKIP Streaming SVE set SVE get SVE for VL 5632
5193 16:59:56.855842 # ok 3463 # SKIP Streaming SVE set SVE get FPSIMD for VL 5632
5194 16:59:56.856006 # ok 3464 # SKIP Streaming SVE set FPSIMD get SVE for VL 5632
5195 16:59:56.856166 # ok 3465 Set Streaming SVE VL 5648
5196 16:59:56.856323 # ok 3466 # SKIP Streaming SVE set SVE get SVE for VL 5648
5197 16:59:56.856482 # ok 3467 # SKIP Streaming SVE set SVE get FPSIMD for VL 5648
5198 16:59:56.856618 # ok 3468 # SKIP Streaming SVE set FPSIMD get SVE for VL 5648
5199 16:59:56.856734 # ok 3469 Set Streaming SVE VL 5664
5200 16:59:56.856873 # ok 3470 # SKIP Streaming SVE set SVE get SVE for VL 5664
5201 16:59:56.856995 # ok 3471 # SKIP Streaming SVE set SVE get FPSIMD for VL 5664
5202 16:59:56.857110 # ok 3472 # SKIP Streaming SVE set FPSIMD get SVE for VL 5664
5203 16:59:56.857224 # ok 3473 Set Streaming SVE VL 5680
5204 16:59:56.857342 # ok 3474 # SKIP Streaming SVE set SVE get SVE for VL 5680
5205 16:59:56.857474 # ok 3475 # SKIP Streaming SVE set SVE get FPSIMD for VL 5680
5206 16:59:56.867657 # ok 3476 # SKIP Streaming SVE set FPSIMD get SVE for VL 5680
5207 16:59:56.867884 # ok 3477 Set Streaming SVE VL 5696
5208 16:59:56.867973 # ok 3478 # SKIP Streaming SVE set SVE get SVE for VL 5696
5209 16:59:56.868077 # ok 3479 # SKIP Streaming SVE set SVE get FPSIMD for VL 5696
5210 16:59:56.868165 # ok 3480 # SKIP Streaming SVE set FPSIMD get SVE for VL 5696
5211 16:59:56.868249 # ok 3481 Set Streaming SVE VL 5712
5212 16:59:56.868348 # ok 3482 # SKIP Streaming SVE set SVE get SVE for VL 5712
5213 16:59:56.868447 # ok 3483 # SKIP Streaming SVE set SVE get FPSIMD for VL 5712
5214 16:59:56.868554 # ok 3484 # SKIP Streaming SVE set FPSIMD get SVE for VL 5712
5215 16:59:56.868656 # ok 3485 Set Streaming SVE VL 5728
5216 16:59:56.868999 # ok 3486 # SKIP Streaming SVE set SVE get SVE for VL 5728
5217 16:59:56.869220 # ok 3487 # SKIP Streaming SVE set SVE get FPSIMD for VL 5728
5218 16:59:56.882527 # ok 3488 # SKIP Streaming SVE set FPSIMD get SVE for VL 5728
5219 16:59:56.883077 # ok 3489 Set Streaming SVE VL 5744
5220 16:59:56.883270 # ok 3490 # SKIP Streaming SVE set SVE get SVE for VL 5744
5221 16:59:56.883435 # ok 3491 # SKIP Streaming SVE set SVE get FPSIMD for VL 5744
5222 16:59:56.883597 # ok 3492 # SKIP Streaming SVE set FPSIMD get SVE for VL 5744
5223 16:59:56.883733 # ok 3493 Set Streaming SVE VL 5760
5224 16:59:56.883870 # ok 3494 # SKIP Streaming SVE set SVE get SVE for VL 5760
5225 16:59:56.884033 # ok 3495 # SKIP Streaming SVE set SVE get FPSIMD for VL 5760
5226 16:59:56.884201 # ok 3496 # SKIP Streaming SVE set FPSIMD get SVE for VL 5760
5227 16:59:56.884354 # ok 3497 Set Streaming SVE VL 5776
5228 16:59:56.884514 # ok 3498 # SKIP Streaming SVE set SVE get SVE for VL 5776
5229 16:59:56.884657 # ok 3499 # SKIP Streaming SVE set SVE get FPSIMD for VL 5776
5230 16:59:56.884805 # ok 3500 # SKIP Streaming SVE set FPSIMD get SVE for VL 5776
5231 16:59:56.884928 # ok 3501 Set Streaming SVE VL 5792
5232 16:59:56.885084 # ok 3502 # SKIP Streaming SVE set SVE get SVE for VL 5792
5233 16:59:56.885248 # ok 3503 # SKIP Streaming SVE set SVE get FPSIMD for VL 5792
5234 16:59:56.885373 # ok 3504 # SKIP Streaming SVE set FPSIMD get SVE for VL 5792
5235 16:59:56.885490 # ok 3505 Set Streaming SVE VL 5808
5236 16:59:56.885604 # ok 3506 # SKIP Streaming SVE set SVE get SVE for VL 5808
5237 16:59:56.885735 # ok 3507 # SKIP Streaming SVE set SVE get FPSIMD for VL 5808
5238 16:59:56.885853 # ok 3508 # SKIP Streaming SVE set FPSIMD get SVE for VL 5808
5239 16:59:56.885968 # ok 3509 Set Streaming SVE VL 5824
5240 16:59:56.886082 # ok 3510 # SKIP Streaming SVE set SVE get SVE for VL 5824
5241 16:59:56.894432 # ok 3511 # SKIP Streaming SVE set SVE get FPSIMD for VL 5824
5242 16:59:56.894866 # ok 3512 # SKIP Streaming SVE set FPSIMD get SVE for VL 5824
5243 16:59:56.894971 # ok 3513 Set Streaming SVE VL 5840
5244 16:59:56.895150 # ok 3514 # SKIP Streaming SVE set SVE get SVE for VL 5840
5245 16:59:56.895347 # ok 3515 # SKIP Streaming SVE set SVE get FPSIMD for VL 5840
5246 16:59:56.895532 # ok 3516 # SKIP Streaming SVE set FPSIMD get SVE for VL 5840
5247 16:59:56.895714 # ok 3517 Set Streaming SVE VL 5856
5248 16:59:56.895878 # ok 3518 # SKIP Streaming SVE set SVE get SVE for VL 5856
5249 16:59:56.896063 # ok 3519 # SKIP Streaming SVE set SVE get FPSIMD for VL 5856
5250 16:59:56.896236 # ok 3520 # SKIP Streaming SVE set FPSIMD get SVE for VL 5856
5251 16:59:56.896404 # ok 3521 Set Streaming SVE VL 5872
5252 16:59:56.896560 # ok 3522 # SKIP Streaming SVE set SVE get SVE for VL 5872
5253 16:59:56.896713 # ok 3523 # SKIP Streaming SVE set SVE get FPSIMD for VL 5872
5254 16:59:56.896904 # ok 3524 # SKIP Streaming SVE set FPSIMD get SVE for VL 5872
5255 16:59:56.897066 # ok 3525 Set Streaming SVE VL 5888
5256 16:59:56.897252 # ok 3526 # SKIP Streaming SVE set SVE get SVE for VL 5888
5257 16:59:56.897406 # ok 3527 # SKIP Streaming SVE set SVE get FPSIMD for VL 5888
5258 16:59:56.897551 # ok 3528 # SKIP Streaming SVE set FPSIMD get SVE for VL 5888
5259 16:59:56.897706 # ok 3529 Set Streaming SVE VL 5904
5260 16:59:56.897856 # ok 3530 # SKIP Streaming SVE set SVE get SVE for VL 5904
5261 16:59:56.898000 # ok 3531 # SKIP Streaming SVE set SVE get FPSIMD for VL 5904
5262 16:59:56.898163 # ok 3532 # SKIP Streaming SVE set FPSIMD get SVE for VL 5904
5263 16:59:56.898281 # ok 3533 Set Streaming SVE VL 5920
5264 16:59:56.905999 # ok 3534 # SKIP Streaming SVE set SVE get SVE for VL 5920
5265 16:59:56.906444 # ok 3535 # SKIP Streaming SVE set SVE get FPSIMD for VL 5920
5266 16:59:56.906538 # ok 3536 # SKIP Streaming SVE set FPSIMD get SVE for VL 5920
5267 16:59:56.906640 # ok 3537 Set Streaming SVE VL 5936
5268 16:59:56.906726 # ok 3538 # SKIP Streaming SVE set SVE get SVE for VL 5936
5269 16:59:56.906820 # ok 3539 # SKIP Streaming SVE set SVE get FPSIMD for VL 5936
5270 16:59:56.906899 # ok 3540 # SKIP Streaming SVE set FPSIMD get SVE for VL 5936
5271 16:59:56.906971 # ok 3541 Set Streaming SVE VL 5952
5272 16:59:56.907082 # ok 3542 # SKIP Streaming SVE set SVE get SVE for VL 5952
5273 16:59:56.907238 # ok 3543 # SKIP Streaming SVE set SVE get FPSIMD for VL 5952
5274 16:59:56.907425 # ok 3544 # SKIP Streaming SVE set FPSIMD get SVE for VL 5952
5275 16:59:56.907590 # ok 3545 Set Streaming SVE VL 5968
5276 16:59:56.907747 # ok 3546 # SKIP Streaming SVE set SVE get SVE for VL 5968
5277 16:59:56.907891 # ok 3547 # SKIP Streaming SVE set SVE get FPSIMD for VL 5968
5278 16:59:56.908068 # ok 3548 # SKIP Streaming SVE set FPSIMD get SVE for VL 5968
5279 16:59:56.908228 # ok 3549 Set Streaming SVE VL 5984
5280 16:59:56.908384 # ok 3550 # SKIP Streaming SVE set SVE get SVE for VL 5984
5281 16:59:56.908525 # ok 3551 # SKIP Streaming SVE set SVE get FPSIMD for VL 5984
5282 16:59:56.908717 # ok 3552 # SKIP Streaming SVE set FPSIMD get SVE for VL 5984
5283 16:59:56.908885 # ok 3553 Set Streaming SVE VL 6000
5284 16:59:56.909045 # ok 3554 # SKIP Streaming SVE set SVE get SVE for VL 6000
5285 16:59:56.909191 # ok 3555 # SKIP Streaming SVE set SVE get FPSIMD for VL 6000
5286 16:59:56.909307 # ok 3556 # SKIP Streaming SVE set FPSIMD get SVE for VL 6000
5287 16:59:56.909418 # ok 3557 Set Streaming SVE VL 6016
5288 16:59:56.909530 # ok 3558 # SKIP Streaming SVE set SVE get SVE for VL 6016
5289 16:59:56.910111 # ok 3559 # SKIP Streaming SVE set SVE get FPSIMD for VL 6016
5290 16:59:56.910268 # ok 3560 # SKIP Streaming SVE set FPSIMD get SVE for VL 6016
5291 16:59:56.910386 # ok 3561 Set Streaming SVE VL 6032
5292 16:59:56.921934 # ok 3562 # SKIP Streaming SVE set SVE get SVE for VL 6032
5293 16:59:56.922500 # ok 3563 # SKIP Streaming SVE set SVE get FPSIMD for VL 6032
5294 16:59:56.922676 # ok 3564 # SKIP Streaming SVE set FPSIMD get SVE for VL 6032
5295 16:59:56.922849 # ok 3565 Set Streaming SVE VL 6048
5296 16:59:56.922993 # ok 3566 # SKIP Streaming SVE set SVE get SVE for VL 6048
5297 16:59:56.923135 # ok 3567 # SKIP Streaming SVE set SVE get FPSIMD for VL 6048
5298 16:59:56.923311 # ok 3568 # SKIP Streaming SVE set FPSIMD get SVE for VL 6048
5299 16:59:56.923449 # ok 3569 Set Streaming SVE VL 6064
5300 16:59:56.923590 # ok 3570 # SKIP Streaming SVE set SVE get SVE for VL 6064
5301 16:59:56.923731 # ok 3571 # SKIP Streaming SVE set SVE get FPSIMD for VL 6064
5302 16:59:56.923872 # ok 3572 # SKIP Streaming SVE set FPSIMD get SVE for VL 6064
5303 16:59:56.924012 # ok 3573 Set Streaming SVE VL 6080
5304 16:59:56.924151 # ok 3574 # SKIP Streaming SVE set SVE get SVE for VL 6080
5305 16:59:56.924330 # ok 3575 # SKIP Streaming SVE set SVE get FPSIMD for VL 6080
5306 16:59:56.924464 # ok 3576 # SKIP Streaming SVE set FPSIMD get SVE for VL 6080
5307 16:59:56.924605 # ok 3577 Set Streaming SVE VL 6096
5308 16:59:56.924744 # ok 3578 # SKIP Streaming SVE set SVE get SVE for VL 6096
5309 16:59:56.924884 # ok 3579 # SKIP Streaming SVE set SVE get FPSIMD for VL 6096
5310 16:59:56.925023 # ok 3580 # SKIP Streaming SVE set FPSIMD get SVE for VL 6096
5311 16:59:56.925166 # ok 3581 Set Streaming SVE VL 6112
5312 16:59:56.925304 # ok 3582 # SKIP Streaming SVE set SVE get SVE for VL 6112
5313 16:59:56.925444 # ok 3583 # SKIP Streaming SVE set SVE get FPSIMD for VL 6112
5314 16:59:56.925581 # ok 3584 # SKIP Streaming SVE set FPSIMD get SVE for VL 6112
5315 16:59:56.925775 # ok 3585 Set Streaming SVE VL 6128
5316 16:59:56.925911 # ok 3586 # SKIP Streaming SVE set SVE get SVE for VL 6128
5317 16:59:56.926053 # ok 3587 # SKIP Streaming SVE set SVE get FPSIMD for VL 6128
5318 16:59:56.926196 # ok 3588 # SKIP Streaming SVE set FPSIMD get SVE for VL 6128
5319 16:59:56.926335 # ok 3589 Set Streaming SVE VL 6144
5320 16:59:56.926475 # ok 3590 # SKIP Streaming SVE set SVE get SVE for VL 6144
5321 16:59:56.926614 # ok 3591 # SKIP Streaming SVE set SVE get FPSIMD for VL 6144
5322 16:59:56.934541 # ok 3592 # SKIP Streaming SVE set FPSIMD get SVE for VL 6144
5323 16:59:56.934779 # ok 3593 Set Streaming SVE VL 6160
5324 16:59:56.935069 # ok 3594 # SKIP Streaming SVE set SVE get SVE for VL 6160
5325 16:59:56.935168 # ok 3595 # SKIP Streaming SVE set SVE get FPSIMD for VL 6160
5326 16:59:56.935254 # ok 3596 # SKIP Streaming SVE set FPSIMD get SVE for VL 6160
5327 16:59:56.935340 # ok 3597 Set Streaming SVE VL 6176
5328 16:59:56.935438 # ok 3598 # SKIP Streaming SVE set SVE get SVE for VL 6176
5329 16:59:56.935525 # ok 3599 # SKIP Streaming SVE set SVE get FPSIMD for VL 6176
5330 16:59:56.935610 # ok 3600 # SKIP Streaming SVE set FPSIMD get SVE for VL 6176
5331 16:59:56.935706 # ok 3601 Set Streaming SVE VL 6192
5332 16:59:56.935793 # ok 3602 # SKIP Streaming SVE set SVE get SVE for VL 6192
5333 16:59:56.935892 # ok 3603 # SKIP Streaming SVE set SVE get FPSIMD for VL 6192
5334 16:59:56.935994 # ok 3604 # SKIP Streaming SVE set FPSIMD get SVE for VL 6192
5335 16:59:56.936285 # ok 3605 Set Streaming SVE VL 6208
5336 16:59:56.936391 # ok 3606 # SKIP Streaming SVE set SVE get SVE for VL 6208
5337 16:59:56.936479 # ok 3607 # SKIP Streaming SVE set SVE get FPSIMD for VL 6208
5338 16:59:56.936576 # ok 3608 # SKIP Streaming SVE set FPSIMD get SVE for VL 6208
5339 16:59:56.936658 # ok 3609 Set Streaming SVE VL 6224
5340 16:59:56.936753 # ok 3610 # SKIP Streaming SVE set SVE get SVE for VL 6224
5341 16:59:56.937078 # ok 3611 # SKIP Streaming SVE set SVE get FPSIMD for VL 6224
5342 16:59:56.942638 # ok 3612 # SKIP Streaming SVE set FPSIMD get SVE for VL 6224
5343 16:59:56.943240 # ok 3613 Set Streaming SVE VL 6240
5344 16:59:56.943436 # ok 3614 # SKIP Streaming SVE set SVE get SVE for VL 6240
5345 16:59:56.943604 # ok 3615 # SKIP Streaming SVE set SVE get FPSIMD for VL 6240
5346 16:59:56.943750 # ok 3616 # SKIP Streaming SVE set FPSIMD get SVE for VL 6240
5347 16:59:56.943949 # ok 3617 Set Streaming SVE VL 6256
5348 16:59:56.944123 # ok 3618 # SKIP Streaming SVE set SVE get SVE for VL 6256
5349 16:59:56.944294 # ok 3619 # SKIP Streaming SVE set SVE get FPSIMD for VL 6256
5350 16:59:56.944464 # ok 3620 # SKIP Streaming SVE set FPSIMD get SVE for VL 6256
5351 16:59:56.944608 # ok 3621 Set Streaming SVE VL 6272
5352 16:59:56.944786 # ok 3622 # SKIP Streaming SVE set SVE get SVE for VL 6272
5353 16:59:56.944923 # ok 3623 # SKIP Streaming SVE set SVE get FPSIMD for VL 6272
5354 16:59:56.945068 # ok 3624 # SKIP Streaming SVE set FPSIMD get SVE for VL 6272
5355 16:59:56.945209 # ok 3625 Set Streaming SVE VL 6288
5356 16:59:56.946131 # ok 3626 # SKIP Streaming SVE set SVE get SVE for VL 6288
5357 16:59:56.946369 # ok 3627 # SKIP Streaming SVE set SVE get FPSIMD for VL 6288
5358 16:59:56.946581 # ok 3628 # SKIP Streaming SVE set FPSIMD get SVE for VL 6288
5359 16:59:56.946776 # ok 3629 Set Streaming SVE VL 6304
5360 16:59:56.946978 # ok 3630 # SKIP Streaming SVE set SVE get SVE for VL 6304
5361 16:59:56.947143 # ok 3631 # SKIP Streaming SVE set SVE get FPSIMD for VL 6304
5362 16:59:56.947304 # ok 3632 # SKIP Streaming SVE set FPSIMD get SVE for VL 6304
5363 16:59:56.947466 # ok 3633 Set Streaming SVE VL 6320
5364 16:59:56.947650 # ok 3634 # SKIP Streaming SVE set SVE get SVE for VL 6320
5365 16:59:56.947802 # ok 3635 # SKIP Streaming SVE set SVE get FPSIMD for VL 6320
5366 16:59:56.947957 # ok 3636 # SKIP Streaming SVE set FPSIMD get SVE for VL 6320
5367 16:59:56.948116 # ok 3637 Set Streaming SVE VL 6336
5368 16:59:56.948310 # ok 3638 # SKIP Streaming SVE set SVE get SVE for VL 6336
5369 16:59:56.948478 # ok 3639 # SKIP Streaming SVE set SVE get FPSIMD for VL 6336
5370 16:59:56.948634 # ok 3640 # SKIP Streaming SVE set FPSIMD get SVE for VL 6336
5371 16:59:56.948795 # ok 3641 Set Streaming SVE VL 6352
5372 16:59:56.948995 # ok 3642 # SKIP Streaming SVE set SVE get SVE for VL 6352
5373 16:59:56.949181 # ok 3643 # SKIP Streaming SVE set SVE get FPSIMD for VL 6352
5374 16:59:56.949303 # ok 3644 # SKIP Streaming SVE set FPSIMD get SVE for VL 6352
5375 16:59:56.949414 # ok 3645 Set Streaming SVE VL 6368
5376 16:59:56.949523 # ok 3646 # SKIP Streaming SVE set SVE get SVE for VL 6368
5377 16:59:56.949632 # ok 3647 # SKIP Streaming SVE set SVE get FPSIMD for VL 6368
5378 16:59:56.949870 # ok 3648 # SKIP Streaming SVE set FPSIMD get SVE for VL 6368
5379 16:59:56.950061 # ok 3649 Set Streaming SVE VL 6384
5380 16:59:56.959684 # ok 3650 # SKIP Streaming SVE set SVE get SVE for VL 6384
5381 16:59:56.960479 # ok 3651 # SKIP Streaming SVE set SVE get FPSIMD for VL 6384
5382 16:59:56.960680 # ok 3652 # SKIP Streaming SVE set FPSIMD get SVE for VL 6384
5383 16:59:56.960915 # ok 3653 Set Streaming SVE VL 6400
5384 16:59:56.961089 # ok 3654 # SKIP Streaming SVE set SVE get SVE for VL 6400
5385 16:59:56.961219 # ok 3655 # SKIP Streaming SVE set SVE get FPSIMD for VL 6400
5386 16:59:56.961363 # ok 3656 # SKIP Streaming SVE set FPSIMD get SVE for VL 6400
5387 16:59:56.962035 # ok 3657 Set Streaming SVE VL 6416
5388 16:59:56.962406 # ok 3658 # SKIP Streaming SVE set SVE get SVE for VL 6416
5389 16:59:56.962584 # ok 3659 # SKIP Streaming SVE set SVE get FPSIMD for VL 6416
5390 16:59:56.962804 # ok 3660 # SKIP Streaming SVE set FPSIMD get SVE for VL 6416
5391 16:59:56.962947 # ok 3661 Set Streaming SVE VL 6432
5392 16:59:56.963091 # ok 3662 # SKIP Streaming SVE set SVE get SVE for VL 6432
5393 16:59:56.963629 # ok 3663 # SKIP Streaming SVE set SVE get FPSIMD for VL 6432
5394 16:59:56.963833 # ok 3664 # SKIP Streaming SVE set FPSIMD get SVE for VL 6432
5395 16:59:56.964271 # ok 3665 Set Streaming SVE VL 6448
5396 16:59:56.964495 # ok 3666 # SKIP Streaming SVE set SVE get SVE for VL 6448
5397 16:59:56.964686 # ok 3667 # SKIP Streaming SVE set SVE get FPSIMD for VL 6448
5398 16:59:56.964850 # ok 3668 # SKIP Streaming SVE set FPSIMD get SVE for VL 6448
5399 16:59:56.965089 # ok 3669 Set Streaming SVE VL 6464
5400 16:59:56.965291 # ok 3670 # SKIP Streaming SVE set SVE get SVE for VL 6464
5401 16:59:56.965432 # ok 3671 # SKIP Streaming SVE set SVE get FPSIMD for VL 6464
5402 16:59:56.965575 # ok 3672 # SKIP Streaming SVE set FPSIMD get SVE for VL 6464
5403 16:59:56.965732 # ok 3673 Set Streaming SVE VL 6480
5404 16:59:56.965876 # ok 3674 # SKIP Streaming SVE set SVE get SVE for VL 6480
5405 16:59:56.970782 # ok 3675 # SKIP Streaming SVE set SVE get FPSIMD for VL 6480
5406 16:59:56.971604 # ok 3676 # SKIP Streaming SVE set FPSIMD get SVE for VL 6480
5407 16:59:56.971811 # ok 3677 Set Streaming SVE VL 6496
5408 16:59:56.972018 # ok 3678 # SKIP Streaming SVE set SVE get SVE for VL 6496
5409 16:59:56.972181 # ok 3679 # SKIP Streaming SVE set SVE get FPSIMD for VL 6496
5410 16:59:56.972375 # ok 3680 # SKIP Streaming SVE set FPSIMD get SVE for VL 6496
5411 16:59:56.972550 # ok 3681 Set Streaming SVE VL 6512
5412 16:59:56.972782 # ok 3682 # SKIP Streaming SVE set SVE get SVE for VL 6512
5413 16:59:56.973021 # ok 3683 # SKIP Streaming SVE set SVE get FPSIMD for VL 6512
5414 16:59:56.973199 # ok 3684 # SKIP Streaming SVE set FPSIMD get SVE for VL 6512
5415 16:59:56.973328 # ok 3685 Set Streaming SVE VL 6528
5416 16:59:56.973470 # ok 3686 # SKIP Streaming SVE set SVE get SVE for VL 6528
5417 16:59:56.973593 # ok 3687 # SKIP Streaming SVE set SVE get FPSIMD for VL 6528
5418 16:59:56.981930 # ok 3688 # SKIP Streaming SVE set FPSIMD get SVE for VL 6528
5419 16:59:56.982374 # ok 3689 Set Streaming SVE VL 6544
5420 16:59:56.982618 # ok 3690 # SKIP Streaming SVE set SVE get SVE for VL 6544
5421 16:59:56.982843 # ok 3691 # SKIP Streaming SVE set SVE get FPSIMD for VL 6544
5422 16:59:56.983018 # ok 3692 # SKIP Streaming SVE set FPSIMD get SVE for VL 6544
5423 16:59:56.983180 # ok 3693 Set Streaming SVE VL 6560
5424 16:59:56.983326 # ok 3694 # SKIP Streaming SVE set SVE get SVE for VL 6560
5425 16:59:56.983469 # ok 3695 # SKIP Streaming SVE set SVE get FPSIMD for VL 6560
5426 16:59:56.983680 # ok 3696 # SKIP Streaming SVE set FPSIMD get SVE for VL 6560
5427 16:59:56.983818 # ok 3697 Set Streaming SVE VL 6576
5428 16:59:56.983932 # ok 3698 # SKIP Streaming SVE set SVE get SVE for VL 6576
5429 16:59:56.984046 # ok 3699 # SKIP Streaming SVE set SVE get FPSIMD for VL 6576
5430 16:59:56.984420 # ok 3700 # SKIP Streaming SVE set FPSIMD get SVE for VL 6576
5431 16:59:56.984599 # ok 3701 Set Streaming SVE VL 6592
5432 16:59:56.984775 # ok 3702 # SKIP Streaming SVE set SVE get SVE for VL 6592
5433 16:59:56.984911 # ok 3703 # SKIP Streaming SVE set SVE get FPSIMD for VL 6592
5434 16:59:56.985052 # ok 3704 # SKIP Streaming SVE set FPSIMD get SVE for VL 6592
5435 16:59:56.985193 # ok 3705 Set Streaming SVE VL 6608
5436 16:59:56.985365 # ok 3706 # SKIP Streaming SVE set SVE get SVE for VL 6608
5437 16:59:56.985543 # ok 3707 # SKIP Streaming SVE set SVE get FPSIMD for VL 6608
5438 16:59:56.985770 # ok 3708 # SKIP Streaming SVE set FPSIMD get SVE for VL 6608
5439 16:59:56.985945 # ok 3709 Set Streaming SVE VL 6624
5440 16:59:56.986093 # ok 3710 # SKIP Streaming SVE set SVE get SVE for VL 6624
5441 16:59:56.986278 # ok 3711 # SKIP Streaming SVE set SVE get FPSIMD for VL 6624
5442 16:59:56.986416 # ok 3712 # SKIP Streaming SVE set FPSIMD get SVE for VL 6624
5443 16:59:56.986555 # ok 3713 Set Streaming SVE VL 6640
5444 16:59:56.986709 # ok 3714 # SKIP Streaming SVE set SVE get SVE for VL 6640
5445 16:59:56.986873 # ok 3715 # SKIP Streaming SVE set SVE get FPSIMD for VL 6640
5446 16:59:56.987026 # ok 3716 # SKIP Streaming SVE set FPSIMD get SVE for VL 6640
5447 16:59:56.987163 # ok 3717 Set Streaming SVE VL 6656
5448 16:59:56.987313 # ok 3718 # SKIP Streaming SVE set SVE get SVE for VL 6656
5449 16:59:56.987463 # ok 3719 # SKIP Streaming SVE set SVE get FPSIMD for VL 6656
5450 16:59:56.987618 # ok 3720 # SKIP Streaming SVE set FPSIMD get SVE for VL 6656
5451 16:59:56.987803 # ok 3721 Set Streaming SVE VL 6672
5452 16:59:56.987964 # ok 3722 # SKIP Streaming SVE set SVE get SVE for VL 6672
5453 16:59:56.988121 # ok 3723 # SKIP Streaming SVE set SVE get FPSIMD for VL 6672
5454 16:59:56.988279 # ok 3724 # SKIP Streaming SVE set FPSIMD get SVE for VL 6672
5455 16:59:56.988432 # ok 3725 Set Streaming SVE VL 6688
5456 16:59:56.988586 # ok 3726 # SKIP Streaming SVE set SVE get SVE for VL 6688
5457 16:59:56.988740 # ok 3727 # SKIP Streaming SVE set SVE get FPSIMD for VL 6688
5458 16:59:56.988862 # ok 3728 # SKIP Streaming SVE set FPSIMD get SVE for VL 6688
5459 16:59:56.989035 # ok 3729 Set Streaming SVE VL 6704
5460 16:59:56.989162 # ok 3730 # SKIP Streaming SVE set SVE get SVE for VL 6704
5461 16:59:56.989279 # ok 3731 # SKIP Streaming SVE set SVE get FPSIMD for VL 6704
5462 16:59:56.989397 # ok 3732 # SKIP Streaming SVE set FPSIMD get SVE for VL 6704
5463 16:59:56.989509 # ok 3733 Set Streaming SVE VL 6720
5464 16:59:56.989623 # ok 3734 # SKIP Streaming SVE set SVE get SVE for VL 6720
5465 16:59:56.989754 # ok 3735 # SKIP Streaming SVE set SVE get FPSIMD for VL 6720
5466 16:59:56.990075 # ok 3736 # SKIP Streaming SVE set FPSIMD get SVE for VL 6720
5467 16:59:56.990200 # ok 3737 Set Streaming SVE VL 6736
5468 16:59:56.990314 # ok 3738 # SKIP Streaming SVE set SVE get SVE for VL 6736
5469 16:59:56.993749 # ok 3739 # SKIP Streaming SVE set SVE get FPSIMD for VL 6736
5470 16:59:56.994370 # ok 3740 # SKIP Streaming SVE set FPSIMD get SVE for VL 6736
5471 16:59:56.994475 # ok 3741 Set Streaming SVE VL 6752
5472 16:59:56.994580 # ok 3742 # SKIP Streaming SVE set SVE get SVE for VL 6752
5473 16:59:56.994683 # ok 3743 # SKIP Streaming SVE set SVE get FPSIMD for VL 6752
5474 16:59:56.994793 # ok 3744 # SKIP Streaming SVE set FPSIMD get SVE for VL 6752
5475 16:59:56.994967 # ok 3745 Set Streaming SVE VL 6768
5476 16:59:56.995110 # ok 3746 # SKIP Streaming SVE set SVE get SVE for VL 6768
5477 16:59:56.995427 # ok 3747 # SKIP Streaming SVE set SVE get FPSIMD for VL 6768
5478 16:59:56.995530 # ok 3748 # SKIP Streaming SVE set FPSIMD get SVE for VL 6768
5479 16:59:56.995634 # ok 3749 Set Streaming SVE VL 6784
5480 16:59:56.995737 # ok 3750 # SKIP Streaming SVE set SVE get SVE for VL 6784
5481 16:59:56.995837 # ok 3751 # SKIP Streaming SVE set SVE get FPSIMD for VL 6784
5482 16:59:56.996219 # ok 3752 # SKIP Streaming SVE set FPSIMD get SVE for VL 6784
5483 16:59:56.996320 # ok 3753 Set Streaming SVE VL 6800
5484 16:59:56.996419 # ok 3754 # SKIP Streaming SVE set SVE get SVE for VL 6800
5485 16:59:56.996520 # ok 3755 # SKIP Streaming SVE set SVE get FPSIMD for VL 6800
5486 16:59:56.996693 # ok 3756 # SKIP Streaming SVE set FPSIMD get SVE for VL 6800
5487 16:59:56.996811 # ok 3757 Set Streaming SVE VL 6816
5488 16:59:56.997120 # ok 3758 # SKIP Streaming SVE set SVE get SVE for VL 6816
5489 16:59:57.005291 # ok 3759 # SKIP Streaming SVE set SVE get FPSIMD for VL 6816
5490 16:59:57.005717 # ok 3760 # SKIP Streaming SVE set FPSIMD get SVE for VL 6816
5491 16:59:57.005890 # ok 3761 Set Streaming SVE VL 6832
5492 16:59:57.006080 # ok 3762 # SKIP Streaming SVE set SVE get SVE for VL 6832
5493 16:59:57.006289 # ok 3763 # SKIP Streaming SVE set SVE get FPSIMD for VL 6832
5494 16:59:57.006441 # ok 3764 # SKIP Streaming SVE set FPSIMD get SVE for VL 6832
5495 16:59:57.006631 # ok 3765 Set Streaming SVE VL 6848
5496 16:59:57.006802 # ok 3766 # SKIP Streaming SVE set SVE get SVE for VL 6848
5497 16:59:57.006943 # ok 3767 # SKIP Streaming SVE set SVE get FPSIMD for VL 6848
5498 16:59:57.007121 # ok 3768 # SKIP Streaming SVE set FPSIMD get SVE for VL 6848
5499 16:59:57.007269 # ok 3769 Set Streaming SVE VL 6864
5500 16:59:57.007392 # ok 3770 # SKIP Streaming SVE set SVE get SVE for VL 6864
5501 16:59:57.007508 # ok 3771 # SKIP Streaming SVE set SVE get FPSIMD for VL 6864
5502 16:59:57.007623 # ok 3772 # SKIP Streaming SVE set FPSIMD get SVE for VL 6864
5503 16:59:57.007736 # ok 3773 Set Streaming SVE VL 6880
5504 16:59:57.007871 # ok 3774 # SKIP Streaming SVE set SVE get SVE for VL 6880
5505 16:59:57.025838 # ok 3775 # SKIP Streaming SVE set SVE get FPSIMD for VL 6880
5506 16:59:57.026383 # ok 3776 # SKIP Streaming SVE set FPSIMD get SVE for VL 6880
5507 16:59:57.026576 # ok 3777 Set Streaming SVE VL 6896
5508 16:59:57.026738 # ok 3778 # SKIP Streaming SVE set SVE get SVE for VL 6896
5509 16:59:57.026899 # ok 3779 # SKIP Streaming SVE set SVE get FPSIMD for VL 6896
5510 16:59:57.027053 # ok 3780 # SKIP Streaming SVE set FPSIMD get SVE for VL 6896
5511 16:59:57.027243 # ok 3781 Set Streaming SVE VL 6912
5512 16:59:57.027450 # ok 3782 # SKIP Streaming SVE set SVE get SVE for VL 6912
5513 16:59:57.027618 # ok 3783 # SKIP Streaming SVE set SVE get FPSIMD for VL 6912
5514 16:59:57.027776 # ok 3784 # SKIP Streaming SVE set FPSIMD get SVE for VL 6912
5515 16:59:57.027940 # ok 3785 Set Streaming SVE VL 6928
5516 16:59:57.028102 # ok 3786 # SKIP Streaming SVE set SVE get SVE for VL 6928
5517 16:59:57.028292 # ok 3787 # SKIP Streaming SVE set SVE get FPSIMD for VL 6928
5518 16:59:57.028458 # ok 3788 # SKIP Streaming SVE set FPSIMD get SVE for VL 6928
5519 16:59:57.028621 # ok 3789 Set Streaming SVE VL 6944
5520 16:59:57.028783 # ok 3790 # SKIP Streaming SVE set SVE get SVE for VL 6944
5521 16:59:57.028940 # ok 3791 # SKIP Streaming SVE set SVE get FPSIMD for VL 6944
5522 16:59:57.029123 # ok 3792 # SKIP Streaming SVE set FPSIMD get SVE for VL 6944
5523 16:59:57.029276 # ok 3793 Set Streaming SVE VL 6960
5524 16:59:57.029423 # ok 3794 # SKIP Streaming SVE set SVE get SVE for VL 6960
5525 16:59:57.029544 # ok 3795 # SKIP Streaming SVE set SVE get FPSIMD for VL 6960
5526 16:59:57.029693 # ok 3796 # SKIP Streaming SVE set FPSIMD get SVE for VL 6960
5527 16:59:57.029897 # ok 3797 Set Streaming SVE VL 6976
5528 16:59:57.030079 # ok 3798 # SKIP Streaming SVE set SVE get SVE for VL 6976
5529 16:59:57.037437 # ok 3799 # SKIP Streaming SVE set SVE get FPSIMD for VL 6976
5530 16:59:57.037875 # ok 3800 # SKIP Streaming SVE set FPSIMD get SVE for VL 6976
5531 16:59:57.037976 # ok 3801 Set Streaming SVE VL 6992
5532 16:59:57.038077 # ok 3802 # SKIP Streaming SVE set SVE get SVE for VL 6992
5533 16:59:57.038180 # ok 3803 # SKIP Streaming SVE set SVE get FPSIMD for VL 6992
5534 16:59:57.038325 # ok 3804 # SKIP Streaming SVE set FPSIMD get SVE for VL 6992
5535 16:59:57.038504 # ok 3805 Set Streaming SVE VL 7008
5536 16:59:57.038675 # ok 3806 # SKIP Streaming SVE set SVE get SVE for VL 7008
5537 16:59:57.038876 # ok 3807 # SKIP Streaming SVE set SVE get FPSIMD for VL 7008
5538 16:59:57.039020 # ok 3808 # SKIP Streaming SVE set FPSIMD get SVE for VL 7008
5539 16:59:57.039151 # ok 3809 Set Streaming SVE VL 7024
5540 16:59:57.039308 # ok 3810 # SKIP Streaming SVE set SVE get SVE for VL 7024
5541 16:59:57.039473 # ok 3811 # SKIP Streaming SVE set SVE get FPSIMD for VL 7024
5542 16:59:57.039645 # ok 3812 # SKIP Streaming SVE set FPSIMD get SVE for VL 7024
5543 16:59:57.039818 # ok 3813 Set Streaming SVE VL 7040
5544 16:59:57.039970 # ok 3814 # SKIP Streaming SVE set SVE get SVE for VL 7040
5545 16:59:57.040121 # ok 3815 # SKIP Streaming SVE set SVE get FPSIMD for VL 7040
5546 16:59:57.040282 # ok 3816 # SKIP Streaming SVE set FPSIMD get SVE for VL 7040
5547 16:59:57.040441 # ok 3817 Set Streaming SVE VL 7056
5548 16:59:57.040619 # ok 3818 # SKIP Streaming SVE set SVE get SVE for VL 7056
5549 16:59:57.040766 # ok 3819 # SKIP Streaming SVE set SVE get FPSIMD for VL 7056
5550 16:59:57.040903 # ok 3820 # SKIP Streaming SVE set FPSIMD get SVE for VL 7056
5551 16:59:57.041034 # ok 3821 Set Streaming SVE VL 7072
5552 16:59:57.041157 # ok 3822 # SKIP Streaming SVE set SVE get SVE for VL 7072
5553 16:59:57.041273 # ok 3823 # SKIP Streaming SVE set SVE get FPSIMD for VL 7072
5554 16:59:57.041387 # ok 3824 # SKIP Streaming SVE set FPSIMD get SVE for VL 7072
5555 16:59:57.041527 # ok 3825 Set Streaming SVE VL 7088
5556 16:59:57.041645 # ok 3826 # SKIP Streaming SVE set SVE get SVE for VL 7088
5557 16:59:57.041866 # ok 3827 # SKIP Streaming SVE set SVE get FPSIMD for VL 7088
5558 16:59:57.042979 # ok 3828 # SKIP Streaming SVE set FPSIMD get SVE for VL 7088
5559 16:59:57.043412 # ok 3829 Set Streaming SVE VL 7104
5560 16:59:57.043595 # ok 3830 # SKIP Streaming SVE set SVE get SVE for VL 7104
5561 16:59:57.043758 # ok 3831 # SKIP Streaming SVE set SVE get FPSIMD for VL 7104
5562 16:59:57.043917 # ok 3832 # SKIP Streaming SVE set FPSIMD get SVE for VL 7104
5563 16:59:57.044110 # ok 3833 Set Streaming SVE VL 7120
5564 16:59:57.044276 # ok 3834 # SKIP Streaming SVE set SVE get SVE for VL 7120
5565 16:59:57.044437 # ok 3835 # SKIP Streaming SVE set SVE get FPSIMD for VL 7120
5566 16:59:57.044597 # ok 3836 # SKIP Streaming SVE set FPSIMD get SVE for VL 7120
5567 16:59:57.044759 # ok 3837 Set Streaming SVE VL 7136
5568 16:59:57.044946 # ok 3838 # SKIP Streaming SVE set SVE get SVE for VL 7136
5569 16:59:57.045090 # ok 3839 # SKIP Streaming SVE set SVE get FPSIMD for VL 7136
5570 16:59:57.045208 # ok 3840 # SKIP Streaming SVE set FPSIMD get SVE for VL 7136
5571 16:59:57.045324 # ok 3841 Set Streaming SVE VL 7152
5572 16:59:57.045443 # ok 3842 # SKIP Streaming SVE set SVE get SVE for VL 7152
5573 16:59:57.045557 # ok 3843 # SKIP Streaming SVE set SVE get FPSIMD for VL 7152
5574 16:59:57.045686 # ok 3844 # SKIP Streaming SVE set FPSIMD get SVE for VL 7152
5575 16:59:57.054794 # ok 3845 Set Streaming SVE VL 7168
5576 16:59:57.055241 # ok 3846 # SKIP Streaming SVE set SVE get SVE for VL 7168
5577 16:59:57.055433 # ok 3847 # SKIP Streaming SVE set SVE get FPSIMD for VL 7168
5578 16:59:57.055601 # ok 3848 # SKIP Streaming SVE set FPSIMD get SVE for VL 7168
5579 16:59:57.055776 # ok 3849 Set Streaming SVE VL 7184
5580 16:59:57.055997 # ok 3850 # SKIP Streaming SVE set SVE get SVE for VL 7184
5581 16:59:57.056166 # ok 3851 # SKIP Streaming SVE set SVE get FPSIMD for VL 7184
5582 16:59:57.056327 # ok 3852 # SKIP Streaming SVE set FPSIMD get SVE for VL 7184
5583 16:59:57.056490 # ok 3853 Set Streaming SVE VL 7200
5584 16:59:57.056648 # ok 3854 # SKIP Streaming SVE set SVE get SVE for VL 7200
5585 16:59:57.056800 # ok 3855 # SKIP Streaming SVE set SVE get FPSIMD for VL 7200
5586 16:59:57.056984 # ok 3856 # SKIP Streaming SVE set FPSIMD get SVE for VL 7200
5587 16:59:57.057111 # ok 3857 Set Streaming SVE VL 7216
5588 16:59:57.057227 # ok 3858 # SKIP Streaming SVE set SVE get SVE for VL 7216
5589 16:59:57.057340 # ok 3859 # SKIP Streaming SVE set SVE get FPSIMD for VL 7216
5590 16:59:57.057455 # ok 3860 # SKIP Streaming SVE set FPSIMD get SVE for VL 7216
5591 16:59:57.057568 # ok 3861 Set Streaming SVE VL 7232
5592 16:59:57.057720 # ok 3862 # SKIP Streaming SVE set SVE get SVE for VL 7232
5593 16:59:57.057922 # ok 3863 # SKIP Streaming SVE set SVE get FPSIMD for VL 7232
5594 16:59:57.066022 # ok 3864 # SKIP Streaming SVE set FPSIMD get SVE for VL 7232
5595 16:59:57.066231 # ok 3865 Set Streaming SVE VL 7248
5596 16:59:57.066630 # ok 3866 # SKIP Streaming SVE set SVE get SVE for VL 7248
5597 16:59:57.066812 # ok 3867 # SKIP Streaming SVE set SVE get FPSIMD for VL 7248
5598 16:59:57.066969 # ok 3868 # SKIP Streaming SVE set FPSIMD get SVE for VL 7248
5599 16:59:57.067117 # ok 3869 Set Streaming SVE VL 7264
5600 16:59:57.067293 # ok 3870 # SKIP Streaming SVE set SVE get SVE for VL 7264
5601 16:59:57.067731 # ok 3871 # SKIP Streaming SVE set SVE get FPSIMD for VL 7264
5602 16:59:57.067921 # ok 3872 # SKIP Streaming SVE set FPSIMD get SVE for VL 7264
5603 16:59:57.068062 # ok 3873 Set Streaming SVE VL 7280
5604 16:59:57.068180 # ok 3874 # SKIP Streaming SVE set SVE get SVE for VL 7280
5605 16:59:57.068292 # ok 3875 # SKIP Streaming SVE set SVE get FPSIMD for VL 7280
5606 16:59:57.068406 # ok 3876 # SKIP Streaming SVE set FPSIMD get SVE for VL 7280
5607 16:59:57.068518 # ok 3877 Set Streaming SVE VL 7296
5608 16:59:57.068670 # ok 3878 # SKIP Streaming SVE set SVE get SVE for VL 7296
5609 16:59:57.068800 # ok 3879 # SKIP Streaming SVE set SVE get FPSIMD for VL 7296
5610 16:59:57.068918 # ok 3880 # SKIP Streaming SVE set FPSIMD get SVE for VL 7296
5611 16:59:57.069042 # ok 3881 Set Streaming SVE VL 7312
5612 16:59:57.069190 # ok 3882 # SKIP Streaming SVE set SVE get SVE for VL 7312
5613 16:59:57.069311 # ok 3883 # SKIP Streaming SVE set SVE get FPSIMD for VL 7312
5614 16:59:57.069428 # ok 3884 # SKIP Streaming SVE set FPSIMD get SVE for VL 7312
5615 16:59:57.069540 # ok 3885 Set Streaming SVE VL 7328
5616 16:59:57.069667 # ok 3886 # SKIP Streaming SVE set SVE get SVE for VL 7328
5617 16:59:57.069783 # ok 3887 # SKIP Streaming SVE set SVE get FPSIMD for VL 7328
5618 16:59:57.069895 # ok 3888 # SKIP Streaming SVE set FPSIMD get SVE for VL 7328
5619 16:59:57.070005 # ok 3889 Set Streaming SVE VL 7344
5620 16:59:57.070115 # ok 3890 # SKIP Streaming SVE set SVE get SVE for VL 7344
5621 16:59:57.078228 # ok 3891 # SKIP Streaming SVE set SVE get FPSIMD for VL 7344
5622 16:59:57.078733 # ok 3892 # SKIP Streaming SVE set FPSIMD get SVE for VL 7344
5623 16:59:57.078920 # ok 3893 Set Streaming SVE VL 7360
5624 16:59:57.079069 # ok 3894 # SKIP Streaming SVE set SVE get SVE for VL 7360
5625 16:59:57.079265 # ok 3895 # SKIP Streaming SVE set SVE get FPSIMD for VL 7360
5626 16:59:57.079514 # ok 3896 # SKIP Streaming SVE set FPSIMD get SVE for VL 7360
5627 16:59:57.079691 # ok 3897 Set Streaming SVE VL 7376
5628 16:59:57.079882 # ok 3898 # SKIP Streaming SVE set SVE get SVE for VL 7376
5629 16:59:57.080044 # ok 3899 # SKIP Streaming SVE set SVE get FPSIMD for VL 7376
5630 16:59:57.080178 # ok 3900 # SKIP Streaming SVE set FPSIMD get SVE for VL 7376
5631 16:59:57.080325 # ok 3901 Set Streaming SVE VL 7392
5632 16:59:57.080500 # ok 3902 # SKIP Streaming SVE set SVE get SVE for VL 7392
5633 16:59:57.080654 # ok 3903 # SKIP Streaming SVE set SVE get FPSIMD for VL 7392
5634 16:59:57.080859 # ok 3904 # SKIP Streaming SVE set FPSIMD get SVE for VL 7392
5635 16:59:57.081046 # ok 3905 Set Streaming SVE VL 7408
5636 16:59:57.081174 # ok 3906 # SKIP Streaming SVE set SVE get SVE for VL 7408
5637 16:59:57.081288 # ok 3907 # SKIP Streaming SVE set SVE get FPSIMD for VL 7408
5638 16:59:57.081401 # ok 3908 # SKIP Streaming SVE set FPSIMD get SVE for VL 7408
5639 16:59:57.081511 # ok 3909 Set Streaming SVE VL 7424
5640 16:59:57.081661 # ok 3910 # SKIP Streaming SVE set SVE get SVE for VL 7424
5641 16:59:57.081784 # ok 3911 # SKIP Streaming SVE set SVE get FPSIMD for VL 7424
5642 16:59:57.081898 # ok 3912 # SKIP Streaming SVE set FPSIMD get SVE for VL 7424
5643 16:59:57.086172 # ok 3913 Set Streaming SVE VL 7440
5644 16:59:57.086604 # ok 3914 # SKIP Streaming SVE set SVE get SVE for VL 7440
5645 16:59:57.086769 # ok 3915 # SKIP Streaming SVE set SVE get FPSIMD for VL 7440
5646 16:59:57.086915 # ok 3916 # SKIP Streaming SVE set FPSIMD get SVE for VL 7440
5647 16:59:57.087087 # ok 3917 Set Streaming SVE VL 7456
5648 16:59:57.087235 # ok 3918 # SKIP Streaming SVE set SVE get SVE for VL 7456
5649 16:59:57.087380 # ok 3919 # SKIP Streaming SVE set SVE get FPSIMD for VL 7456
5650 16:59:57.087527 # ok 3920 # SKIP Streaming SVE set FPSIMD get SVE for VL 7456
5651 16:59:57.087670 # ok 3921 Set Streaming SVE VL 7472
5652 16:59:57.087837 # ok 3922 # SKIP Streaming SVE set SVE get SVE for VL 7472
5653 16:59:57.087985 # ok 3923 # SKIP Streaming SVE set SVE get FPSIMD for VL 7472
5654 16:59:57.088154 # ok 3924 # SKIP Streaming SVE set FPSIMD get SVE for VL 7472
5655 16:59:57.088343 # ok 3925 Set Streaming SVE VL 7488
5656 16:59:57.088506 # ok 3926 # SKIP Streaming SVE set SVE get SVE for VL 7488
5657 16:59:57.088695 # ok 3927 # SKIP Streaming SVE set SVE get FPSIMD for VL 7488
5658 16:59:57.088859 # ok 3928 # SKIP Streaming SVE set FPSIMD get SVE for VL 7488
5659 16:59:57.089019 # ok 3929 Set Streaming SVE VL 7504
5660 16:59:57.089205 # ok 3930 # SKIP Streaming SVE set SVE get SVE for VL 7504
5661 16:59:57.089368 # ok 3931 # SKIP Streaming SVE set SVE get FPSIMD for VL 7504
5662 16:59:57.093310 # ok 3932 # SKIP Streaming SVE set FPSIMD get SVE for VL 7504
5663 16:59:57.093627 # ok 3933 Set Streaming SVE VL 7520
5664 16:59:57.093729 # ok 3934 # SKIP Streaming SVE set SVE get SVE for VL 7520
5665 16:59:57.093819 # ok 3935 # SKIP Streaming SVE set SVE get FPSIMD for VL 7520
5666 16:59:57.094162 # ok 3936 # SKIP Streaming SVE set FPSIMD get SVE for VL 7520
5667 16:59:57.094364 # ok 3937 Set Streaming SVE VL 7536
5668 16:59:57.094526 # ok 3938 # SKIP Streaming SVE set SVE get SVE for VL 7536
5669 16:59:57.094686 # ok 3939 # SKIP Streaming SVE set SVE get FPSIMD for VL 7536
5670 16:59:57.094874 # ok 3940 # SKIP Streaming SVE set FPSIMD get SVE for VL 7536
5671 16:59:57.095037 # ok 3941 Set Streaming SVE VL 7552
5672 16:59:57.095195 # ok 3942 # SKIP Streaming SVE set SVE get SVE for VL 7552
5673 16:59:57.095352 # ok 3943 # SKIP Streaming SVE set SVE get FPSIMD for VL 7552
5674 16:59:57.095514 # ok 3944 # SKIP Streaming SVE set FPSIMD get SVE for VL 7552
5675 16:59:57.095673 # ok 3945 Set Streaming SVE VL 7568
5676 16:59:57.095830 # ok 3946 # SKIP Streaming SVE set SVE get SVE for VL 7568
5677 16:59:57.095990 # ok 3947 # SKIP Streaming SVE set SVE get FPSIMD for VL 7568
5678 16:59:57.096186 # ok 3948 # SKIP Streaming SVE set FPSIMD get SVE for VL 7568
5679 16:59:57.096351 # ok 3949 Set Streaming SVE VL 7584
5680 16:59:57.096510 # ok 3950 # SKIP Streaming SVE set SVE get SVE for VL 7584
5681 16:59:57.096671 # ok 3951 # SKIP Streaming SVE set SVE get FPSIMD for VL 7584
5682 16:59:57.096830 # ok 3952 # SKIP Streaming SVE set FPSIMD get SVE for VL 7584
5683 16:59:57.096987 # ok 3953 Set Streaming SVE VL 7600
5684 16:59:57.097146 # ok 3954 # SKIP Streaming SVE set SVE get SVE for VL 7600
5685 16:59:57.097304 # ok 3955 # SKIP Streaming SVE set SVE get FPSIMD for VL 7600
5686 16:59:57.097463 # ok 3956 # SKIP Streaming SVE set FPSIMD get SVE for VL 7600
5687 16:59:57.097620 # ok 3957 Set Streaming SVE VL 7616
5688 16:59:57.097796 # ok 3958 # SKIP Streaming SVE set SVE get SVE for VL 7616
5689 16:59:57.097956 # ok 3959 # SKIP Streaming SVE set SVE get FPSIMD for VL 7616
5690 16:59:57.098114 # ok 3960 # SKIP Streaming SVE set FPSIMD get SVE for VL 7616
5691 16:59:57.098272 # ok 3961 Set Streaming SVE VL 7632
5692 16:59:57.098465 # ok 3962 # SKIP Streaming SVE set SVE get SVE for VL 7632
5693 16:59:57.098637 # ok 3963 # SKIP Streaming SVE set SVE get FPSIMD for VL 7632
5694 16:59:57.098798 # ok 3964 # SKIP Streaming SVE set FPSIMD get SVE for VL 7632
5695 16:59:57.098957 # ok 3965 Set Streaming SVE VL 7648
5696 16:59:57.099115 # ok 3966 # SKIP Streaming SVE set SVE get SVE for VL 7648
5697 16:59:57.099273 # ok 3967 # SKIP Streaming SVE set SVE get FPSIMD for VL 7648
5698 16:59:57.099436 # ok 3968 # SKIP Streaming SVE set FPSIMD get SVE for VL 7648
5699 16:59:57.099608 # ok 3969 Set Streaming SVE VL 7664
5700 16:59:57.101240 # ok 3970 # SKIP Streaming SVE set SVE get SVE for VL 7664
5701 16:59:57.101586 # ok 3971 # SKIP Streaming SVE set SVE get FPSIMD for VL 7664
5702 16:59:57.101837 # ok 3972 # SKIP Streaming SVE set FPSIMD get SVE for VL 7664
5703 16:59:57.102007 # ok 3973 Set Streaming SVE VL 7680
5704 16:59:57.102199 # ok 3974 # SKIP Streaming SVE set SVE get SVE for VL 7680
5705 16:59:57.102362 # ok 3975 # SKIP Streaming SVE set SVE get FPSIMD for VL 7680
5706 16:59:57.102517 # ok 3976 # SKIP Streaming SVE set FPSIMD get SVE for VL 7680
5707 16:59:57.102677 # ok 3977 Set Streaming SVE VL 7696
5708 16:59:57.102837 # ok 3978 # SKIP Streaming SVE set SVE get SVE for VL 7696
5709 16:59:57.103034 # ok 3979 # SKIP Streaming SVE set SVE get FPSIMD for VL 7696
5710 16:59:57.103207 # ok 3980 # SKIP Streaming SVE set FPSIMD get SVE for VL 7696
5711 16:59:57.103372 # ok 3981 Set Streaming SVE VL 7712
5712 16:59:57.103536 # ok 3982 # SKIP Streaming SVE set SVE get SVE for VL 7712
5713 16:59:57.103693 # ok 3983 # SKIP Streaming SVE set SVE get FPSIMD for VL 7712
5714 16:59:57.103851 # ok 3984 # SKIP Streaming SVE set FPSIMD get SVE for VL 7712
5715 16:59:57.104045 # ok 3985 Set Streaming SVE VL 7728
5716 16:59:57.104253 # ok 3986 # SKIP Streaming SVE set SVE get SVE for VL 7728
5717 16:59:57.104452 # ok 3987 # SKIP Streaming SVE set SVE get FPSIMD for VL 7728
5718 16:59:57.104634 # ok 3988 # SKIP Streaming SVE set FPSIMD get SVE for VL 7728
5719 16:59:57.104834 # ok 3989 Set Streaming SVE VL 7744
5720 16:59:57.104978 # ok 3990 # SKIP Streaming SVE set SVE get SVE for VL 7744
5721 16:59:57.105094 # ok 3991 # SKIP Streaming SVE set SVE get FPSIMD for VL 7744
5722 16:59:57.105206 # ok 3992 # SKIP Streaming SVE set FPSIMD get SVE for VL 7744
5723 16:59:57.105318 # ok 3993 Set Streaming SVE VL 7760
5724 16:59:57.105430 # ok 3994 # SKIP Streaming SVE set SVE get SVE for VL 7760
5725 16:59:57.105541 # ok 3995 # SKIP Streaming SVE set SVE get FPSIMD for VL 7760
5726 16:59:57.105662 # ok 3996 # SKIP Streaming SVE set FPSIMD get SVE for VL 7760
5727 16:59:57.105774 # ok 3997 Set Streaming SVE VL 7776
5728 16:59:57.105883 # ok 3998 # SKIP Streaming SVE set SVE get SVE for VL 7776
5729 16:59:57.105992 # ok 3999 # SKIP Streaming SVE set SVE get FPSIMD for VL 7776
5730 16:59:57.106102 # ok 4000 # SKIP Streaming SVE set FPSIMD get SVE for VL 7776
5731 16:59:57.106211 # ok 4001 Set Streaming SVE VL 7792
5732 16:59:57.106320 # ok 4002 # SKIP Streaming SVE set SVE get SVE for VL 7792
5733 16:59:57.106428 # ok 4003 # SKIP Streaming SVE set SVE get FPSIMD for VL 7792
5734 16:59:57.106537 # ok 4004 # SKIP Streaming SVE set FPSIMD get SVE for VL 7792
5735 16:59:57.106669 # ok 4005 Set Streaming SVE VL 7808
5736 16:59:57.106986 # ok 4006 # SKIP Streaming SVE set SVE get SVE for VL 7808
5737 16:59:57.109374 # ok 4007 # SKIP Streaming SVE set SVE get FPSIMD for VL 7808
5738 16:59:57.109573 # ok 4008 # SKIP Streaming SVE set FPSIMD get SVE for VL 7808
5739 16:59:57.109952 # ok 4009 Set Streaming SVE VL 7824
5740 16:59:57.110047 # ok 4010 # SKIP Streaming SVE set SVE get SVE for VL 7824
5741 16:59:57.110125 # ok 4011 # SKIP Streaming SVE set SVE get FPSIMD for VL 7824
5742 16:59:57.110197 # ok 4012 # SKIP Streaming SVE set FPSIMD get SVE for VL 7824
5743 16:59:57.110271 # ok 4013 Set Streaming SVE VL 7840
5744 16:59:57.110356 # ok 4014 # SKIP Streaming SVE set SVE get SVE for VL 7840
5745 16:59:57.110429 # ok 4015 # SKIP Streaming SVE set SVE get FPSIMD for VL 7840
5746 16:59:57.110501 # ok 4016 # SKIP Streaming SVE set FPSIMD get SVE for VL 7840
5747 16:59:57.110572 # ok 4017 Set Streaming SVE VL 7856
5748 16:59:57.110656 # ok 4018 # SKIP Streaming SVE set SVE get SVE for VL 7856
5749 16:59:57.110729 # ok 4019 # SKIP Streaming SVE set SVE get FPSIMD for VL 7856
5750 16:59:57.110813 # ok 4020 # SKIP Streaming SVE set FPSIMD get SVE for VL 7856
5751 16:59:57.110886 # ok 4021 Set Streaming SVE VL 7872
5752 16:59:57.110968 # ok 4022 # SKIP Streaming SVE set SVE get SVE for VL 7872
5753 16:59:57.111295 # ok 4023 # SKIP Streaming SVE set SVE get FPSIMD for VL 7872
5754 16:59:57.111522 # ok 4024 # SKIP Streaming SVE set FPSIMD get SVE for VL 7872
5755 16:59:57.111727 # ok 4025 Set Streaming SVE VL 7888
5756 16:59:57.111974 # ok 4026 # SKIP Streaming SVE set SVE get SVE for VL 7888
5757 16:59:57.112189 # ok 4027 # SKIP Streaming SVE set SVE get FPSIMD for VL 7888
5758 16:59:57.112417 # ok 4028 # SKIP Streaming SVE set FPSIMD get SVE for VL 7888
5759 16:59:57.112636 # ok 4029 Set Streaming SVE VL 7904
5760 16:59:57.112822 # ok 4030 # SKIP Streaming SVE set SVE get SVE for VL 7904
5761 16:59:57.113013 # ok 4031 # SKIP Streaming SVE set SVE get FPSIMD for VL 7904
5762 16:59:57.113185 # ok 4032 # SKIP Streaming SVE set FPSIMD get SVE for VL 7904
5763 16:59:57.113308 # ok 4033 Set Streaming SVE VL 7920
5764 16:59:57.113422 # ok 4034 # SKIP Streaming SVE set SVE get SVE for VL 7920
5765 16:59:57.113533 # ok 4035 # SKIP Streaming SVE set SVE get FPSIMD for VL 7920
5766 16:59:57.113661 # ok 4036 # SKIP Streaming SVE set FPSIMD get SVE for VL 7920
5767 16:59:57.113822 # ok 4037 Set Streaming SVE VL 7936
5768 16:59:57.113987 # ok 4038 # SKIP Streaming SVE set SVE get SVE for VL 7936
5769 16:59:57.114112 # ok 4039 # SKIP Streaming SVE set SVE get FPSIMD for VL 7936
5770 16:59:57.114224 # ok 4040 # SKIP Streaming SVE set FPSIMD get SVE for VL 7936
5771 16:59:57.117180 # ok 4041 Set Streaming SVE VL 7952
5772 16:59:57.117369 # ok 4042 # SKIP Streaming SVE set SVE get SVE for VL 7952
5773 16:59:57.117697 # ok 4043 # SKIP Streaming SVE set SVE get FPSIMD for VL 7952
5774 16:59:57.117793 # ok 4044 # SKIP Streaming SVE set FPSIMD get SVE for VL 7952
5775 16:59:57.117885 # ok 4045 Set Streaming SVE VL 7968
5776 16:59:57.117960 # ok 4046 # SKIP Streaming SVE set SVE get SVE for VL 7968
5777 16:59:57.118033 # ok 4047 # SKIP Streaming SVE set SVE get FPSIMD for VL 7968
5778 16:59:57.118120 # ok 4048 # SKIP Streaming SVE set FPSIMD get SVE for VL 7968
5779 16:59:57.118194 # ok 4049 Set Streaming SVE VL 7984
5780 16:59:57.118266 # ok 4050 # SKIP Streaming SVE set SVE get SVE for VL 7984
5781 16:59:57.118338 # ok 4051 # SKIP Streaming SVE set SVE get FPSIMD for VL 7984
5782 16:59:57.118425 # ok 4052 # SKIP Streaming SVE set FPSIMD get SVE for VL 7984
5783 16:59:57.118499 # ok 4053 Set Streaming SVE VL 8000
5784 16:59:57.118571 # ok 4054 # SKIP Streaming SVE set SVE get SVE for VL 8000
5785 16:59:57.118656 # ok 4055 # SKIP Streaming SVE set SVE get FPSIMD for VL 8000
5786 16:59:57.118744 # ok 4056 # SKIP Streaming SVE set FPSIMD get SVE for VL 8000
5787 16:59:57.119014 # ok 4057 Set Streaming SVE VL 8016
5788 16:59:57.119092 # ok 4058 # SKIP Streaming SVE set SVE get SVE for VL 8016
5789 16:59:57.119178 # ok 4059 # SKIP Streaming SVE set SVE get FPSIMD for VL 8016
5790 16:59:57.119510 # ok 4060 # SKIP Streaming SVE set FPSIMD get SVE for VL 8016
5791 16:59:57.119723 # ok 4061 Set Streaming SVE VL 8032
5792 16:59:57.119959 # ok 4062 # SKIP Streaming SVE set SVE get SVE for VL 8032
5793 16:59:57.120167 # ok 4063 # SKIP Streaming SVE set SVE get FPSIMD for VL 8032
5794 16:59:57.120370 # ok 4064 # SKIP Streaming SVE set FPSIMD get SVE for VL 8032
5795 16:59:57.120569 # ok 4065 Set Streaming SVE VL 8048
5796 16:59:57.120825 # ok 4066 # SKIP Streaming SVE set SVE get SVE for VL 8048
5797 16:59:57.121027 # ok 4067 # SKIP Streaming SVE set SVE get FPSIMD for VL 8048
5798 16:59:57.121186 # ok 4068 # SKIP Streaming SVE set FPSIMD get SVE for VL 8048
5799 16:59:57.121312 # ok 4069 Set Streaming SVE VL 8064
5800 16:59:57.121426 # ok 4070 # SKIP Streaming SVE set SVE get SVE for VL 8064
5801 16:59:57.121539 # ok 4071 # SKIP Streaming SVE set SVE get FPSIMD for VL 8064
5802 16:59:57.121662 # ok 4072 # SKIP Streaming SVE set FPSIMD get SVE for VL 8064
5803 16:59:57.121807 # ok 4073 Set Streaming SVE VL 8080
5804 16:59:57.124224 # ok 4074 # SKIP Streaming SVE set SVE get SVE for VL 8080
5805 16:59:57.124904 # ok 4075 # SKIP Streaming SVE set SVE get FPSIMD for VL 8080
5806 16:59:57.125003 # ok 4076 # SKIP Streaming SVE set FPSIMD get SVE for VL 8080
5807 16:59:57.125091 # ok 4077 Set Streaming SVE VL 8096
5808 16:59:57.125458 # ok 4078 # SKIP Streaming SVE set SVE get SVE for VL 8096
5809 16:59:57.125692 # ok 4079 # SKIP Streaming SVE set SVE get FPSIMD for VL 8096
5810 16:59:57.125876 # ok 4080 # SKIP Streaming SVE set FPSIMD get SVE for VL 8096
5811 16:59:57.126083 # ok 4081 Set Streaming SVE VL 8112
5812 16:59:57.126261 # ok 4082 # SKIP Streaming SVE set SVE get SVE for VL 8112
5813 16:59:57.126416 # ok 4083 # SKIP Streaming SVE set SVE get FPSIMD for VL 8112
5814 16:59:57.126571 # ok 4084 # SKIP Streaming SVE set FPSIMD get SVE for VL 8112
5815 16:59:57.126755 # ok 4085 Set Streaming SVE VL 8128
5816 16:59:57.126898 # ok 4086 # SKIP Streaming SVE set SVE get SVE for VL 8128
5817 16:59:57.127068 # ok 4087 # SKIP Streaming SVE set SVE get FPSIMD for VL 8128
5818 16:59:57.127239 # ok 4088 # SKIP Streaming SVE set FPSIMD get SVE for VL 8128
5819 16:59:57.127445 # ok 4089 Set Streaming SVE VL 8144
5820 16:59:57.127622 # ok 4090 # SKIP Streaming SVE set SVE get SVE for VL 8144
5821 16:59:57.127793 # ok 4091 # SKIP Streaming SVE set SVE get FPSIMD for VL 8144
5822 16:59:57.127957 # ok 4092 # SKIP Streaming SVE set FPSIMD get SVE for VL 8144
5823 16:59:57.128128 # ok 4093 Set Streaming SVE VL 8160
5824 16:59:57.128299 # ok 4094 # SKIP Streaming SVE set SVE get SVE for VL 8160
5825 16:59:57.128469 # ok 4095 # SKIP Streaming SVE set SVE get FPSIMD for VL 8160
5826 16:59:57.128638 # ok 4096 # SKIP Streaming SVE set FPSIMD get SVE for VL 8160
5827 16:59:57.128848 # ok 4097 Set Streaming SVE VL 8176
5828 16:59:57.129026 # ok 4098 # SKIP Streaming SVE set SVE get SVE for VL 8176
5829 16:59:57.129196 # ok 4099 # SKIP Streaming SVE set SVE get FPSIMD for VL 8176
5830 16:59:57.129366 # ok 4100 # SKIP Streaming SVE set FPSIMD get SVE for VL 8176
5831 16:59:57.129537 # ok 4101 Set Streaming SVE VL 8192
5832 16:59:57.129716 # ok 4102 # SKIP Streaming SVE set SVE get SVE for VL 8192
5833 16:59:57.129887 # ok 4103 # SKIP Streaming SVE set SVE get FPSIMD for VL 8192
5834 16:59:57.130055 # ok 4104 # SKIP Streaming SVE set FPSIMD get SVE for VL 8192
5835 16:59:57.130219 # # Totals: pass:1095 fail:0 xfail:0 xpass:0 skip:3009 error:0
5836 16:59:57.130388 ok 30 selftests: arm64: sve-ptrace
5837 16:59:57.130564 # selftests: arm64: sve-probe-vls
5838 16:59:57.130732 # TAP version 13
5839 16:59:57.130900 # 1..2
5840 16:59:57.131068 # ok 1 Enumerated 16 vector lengths
5841 16:59:57.131268 # ok 2 All vector lengths valid
5842 16:59:57.131443 # # 16
5843 16:59:57.131612 # # 32
5844 16:59:57.133575 # # 48
5845 16:59:57.133802 # # 64
5846 16:59:57.133985 # # 80
5847 16:59:57.134163 # # 96
5848 16:59:57.134574 # # 112
5849 16:59:57.134763 # # 128
5850 16:59:57.134941 # # 144
5851 16:59:57.135119 # # 160
5852 16:59:57.135297 # # 176
5853 16:59:57.135474 # # 192
5854 16:59:57.135655 # # 208
5855 16:59:57.135832 # # 224
5856 16:59:57.136008 # # 240
5857 16:59:57.136186 # # 256
5858 16:59:57.136362 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
5859 16:59:57.136541 ok 31 selftests: arm64: sve-probe-vls
5860 16:59:57.246025 # selftests: arm64: vec-syscfg
5861 16:59:58.145275 # TAP version 13
5862 16:59:58.145832 # 1..20
5863 16:59:58.146019 # ok 1 SVE default vector length 64
5864 16:59:58.146164 # ok 2 SVE minimum vector length 16
5865 16:59:58.146295 # ok 3 SVE maximum vector length 256
5866 16:59:58.146424 # ok 4 SVE current VL is 64
5867 16:59:58.146551 # ok 5 SVE set VL 64 and have VL 64
5868 16:59:58.146708 # ok 6 SVE prctl() set min/max
5869 16:59:58.146841 # ok 7 SVE vector length used default
5870 16:59:58.146969 # ok 8 SVE vector length was inherited
5871 16:59:58.147094 # ok 9 SVE vector length set on exec
5872 16:59:58.147221 # ok 10 SVE prctl() set all VLs, 0 errors
5873 16:59:58.147348 # ok 11 SME default vector length 32
5874 16:59:58.147475 # ok 12 SME minimum vector length 16
5875 16:59:58.147601 # ok 13 SME maximum vector length 256
5876 16:59:58.147726 # ok 14 SME current VL is 32
5877 16:59:58.147851 # ok 15 SME set VL 32 and have VL 32
5878 16:59:58.148049 # ok 16 SME prctl() set min/max
5879 16:59:58.148231 # ok 17 SME vector length used default
5880 16:59:58.148369 # ok 18 SME vector length was inherited
5881 16:59:58.148499 # ok 19 SME vector length set on exec
5882 16:59:58.148628 # ok 20 SME prctl() set all VLs, 0 errors
5883 16:59:58.148759 # # Totals: pass:20 fail:0 xfail:0 xpass:0 skip:0 error:0
5884 16:59:58.171090 ok 32 selftests: arm64: vec-syscfg
5885 16:59:58.277861 # selftests: arm64: za-fork
5886 16:59:58.457249 # TAP version 13
5887 16:59:58.457717 # 1..1
5888 16:59:58.457868 # # PID: 1019
5889 16:59:58.457989 # ok 1 fork_test
5890 16:59:58.458105 # # Totals: pass:1 fail:0 xfail:0 xpass:0 skip:0 error:0
5891 16:59:58.478718 ok 33 selftests: arm64: za-fork
5892 16:59:58.615590 # selftests: arm64: za-ptrace
5893 16:59:58.757043 # TAP version 13
5894 16:59:58.757214 # 1..1536
5895 16:59:58.757324 # # Parent is 1037, child is 1038
5896 16:59:58.757412 # ok 1 Set VL 16
5897 16:59:58.757738 # ok 2 Disabled ZA for VL 16
5898 16:59:58.757956 # ok 3 Data match for VL 16
5899 16:59:58.758150 # ok 4 Set VL 32
5900 16:59:58.758326 # ok 5 Disabled ZA for VL 32
5901 16:59:58.758497 # ok 6 Data match for VL 32
5902 16:59:58.758718 # ok 7 Set VL 48
5903 16:59:58.758898 # ok 8 # SKIP Disabled ZA for VL 48
5904 16:59:58.759095 # ok 9 # SKIP Get and set data for VL 48
5905 16:59:58.759308 # ok 10 Set VL 64
5906 16:59:58.759527 # ok 11 Disabled ZA for VL 64
5907 16:59:58.759729 # ok 12 Data match for VL 64
5908 16:59:58.759919 # ok 13 Set VL 80
5909 16:59:58.760051 # ok 14 # SKIP Disabled ZA for VL 80
5910 16:59:58.760168 # ok 15 # SKIP Get and set data for VL 80
5911 16:59:58.760283 # ok 16 Set VL 96
5912 16:59:58.760397 # ok 17 # SKIP Disabled ZA for VL 96
5913 16:59:58.760512 # ok 18 # SKIP Get and set data for VL 96
5914 16:59:58.760628 # ok 19 Set VL 112
5915 16:59:58.760743 # ok 20 # SKIP Disabled ZA for VL 112
5916 16:59:58.760858 # ok 21 # SKIP Get and set data for VL 112
5917 16:59:58.760975 # ok 22 Set VL 128
5918 16:59:58.761088 # ok 23 Disabled ZA for VL 128
5919 16:59:58.761203 # ok 24 Data match for VL 128
5920 16:59:58.761319 # ok 25 Set VL 144
5921 16:59:58.761433 # ok 26 # SKIP Disabled ZA for VL 144
5922 16:59:58.761551 # ok 27 # SKIP Get and set data for VL 144
5923 16:59:58.761679 # ok 28 Set VL 160
5924 16:59:58.761795 # ok 29 # SKIP Disabled ZA for VL 160
5925 16:59:58.761909 # ok 30 # SKIP Get and set data for VL 160
5926 16:59:58.762022 # ok 31 Set VL 176
5927 16:59:58.762134 # ok 32 # SKIP Disabled ZA for VL 176
5928 16:59:58.762247 # ok 33 # SKIP Get and set data for VL 176
5929 16:59:58.762358 # ok 34 Set VL 192
5930 16:59:58.762497 # ok 35 # SKIP Disabled ZA for VL 192
5931 16:59:58.762623 # ok 36 # SKIP Get and set data for VL 192
5932 16:59:58.762739 # ok 37 Set VL 208
5933 16:59:58.762853 # ok 38 # SKIP Disabled ZA for VL 208
5934 16:59:58.763865 # ok 39 # SKIP Get and set data for VL 208
5935 16:59:58.764018 # ok 40 Set VL 224
5936 16:59:58.764403 # ok 41 # SKIP Disabled ZA for VL 224
5937 16:59:58.764613 # ok 42 # SKIP Get and set data for VL 224
5938 16:59:58.764773 # ok 43 Set VL 240
5939 16:59:58.764977 # ok 44 # SKIP Disabled ZA for VL 240
5940 16:59:58.765173 # ok 45 # SKIP Get and set data for VL 240
5941 16:59:58.765348 # ok 46 Set VL 256
5942 16:59:58.765500 # ok 47 Disabled ZA for VL 256
5943 16:59:58.765676 # ok 48 Data match for VL 256
5944 16:59:58.765838 # ok 49 Set VL 272
5945 16:59:58.765988 # ok 50 # SKIP Disabled ZA for VL 272
5946 16:59:58.766176 # ok 51 # SKIP Get and set data for VL 272
5947 16:59:58.766339 # ok 52 Set VL 288
5948 16:59:58.766513 # ok 53 # SKIP Disabled ZA for VL 288
5949 16:59:58.766653 # ok 54 # SKIP Get and set data for VL 288
5950 16:59:58.766778 # ok 55 Set VL 304
5951 16:59:58.766938 # ok 56 # SKIP Disabled ZA for VL 304
5952 16:59:58.767132 # ok 57 # SKIP Get and set data for VL 304
5953 16:59:58.767301 # ok 58 Set VL 320
5954 16:59:58.767488 # ok 59 # SKIP Disabled ZA for VL 320
5955 16:59:58.767656 # ok 60 # SKIP Get and set data for VL 320
5956 16:59:58.767817 # ok 61 Set VL 336
5957 16:59:58.767950 # ok 62 # SKIP Disabled ZA for VL 336
5958 16:59:58.768064 # ok 63 # SKIP Get and set data for VL 336
5959 16:59:58.768177 # ok 64 Set VL 352
5960 16:59:58.768322 # ok 65 # SKIP Disabled ZA for VL 352
5961 16:59:58.768441 # ok 66 # SKIP Get and set data for VL 352
5962 16:59:58.768555 # ok 67 Set VL 368
5963 16:59:58.768664 # ok 68 # SKIP Disabled ZA for VL 368
5964 16:59:58.768774 # ok 69 # SKIP Get and set data for VL 368
5965 16:59:58.768884 # ok 70 Set VL 384
5966 16:59:58.768994 # ok 71 # SKIP Disabled ZA for VL 384
5967 16:59:58.769104 # ok 72 # SKIP Get and set data for VL 384
5968 16:59:58.769214 # ok 73 Set VL 400
5969 16:59:58.769324 # ok 74 # SKIP Disabled ZA for VL 400
5970 16:59:58.769433 # ok 75 # SKIP Get and set data for VL 400
5971 16:59:58.769545 # ok 76 Set VL 416
5972 16:59:58.769701 # ok 77 # SKIP Disabled ZA for VL 416
5973 16:59:58.769913 # ok 78 # SKIP Get and set data for VL 416
5974 16:59:58.770097 # ok 79 Set VL 432
5975 16:59:58.770279 # ok 80 # SKIP Disabled ZA for VL 432
5976 16:59:58.770462 # ok 81 # SKIP Get and set data for VL 432
5977 16:59:58.770645 # ok 82 Set VL 448
5978 16:59:58.770819 # ok 83 # SKIP Disabled ZA for VL 448
5979 16:59:58.770961 # ok 84 # SKIP Get and set data for VL 448
5980 16:59:58.771101 # ok 85 Set VL 464
5981 16:59:58.773969 # ok 86 # SKIP Disabled ZA for VL 464
5982 16:59:58.774390 # ok 87 # SKIP Get and set data for VL 464
5983 16:59:58.774553 # ok 88 Set VL 480
5984 16:59:58.774746 # ok 89 # SKIP Disabled ZA for VL 480
5985 16:59:58.774899 # ok 90 # SKIP Get and set data for VL 480
5986 16:59:58.775055 # ok 91 Set VL 496
5987 16:59:58.775244 # ok 92 # SKIP Disabled ZA for VL 496
5988 16:59:58.775399 # ok 93 # SKIP Get and set data for VL 496
5989 16:59:58.775547 # ok 94 Set VL 512
5990 16:59:58.775678 # ok 95 # SKIP Disabled ZA for VL 512
5991 16:59:58.775823 # ok 96 # SKIP Get and set data for VL 512
5992 16:59:58.775944 # ok 97 Set VL 528
5993 16:59:58.776058 # ok 98 # SKIP Disabled ZA for VL 528
5994 16:59:58.776201 # ok 99 # SKIP Get and set data for VL 528
5995 16:59:58.776361 # ok 100 Set VL 544
5996 16:59:58.776523 # ok 101 # SKIP Disabled ZA for VL 544
5997 16:59:58.776674 # ok 102 # SKIP Get and set data for VL 544
5998 16:59:58.776864 # ok 103 Set VL 560
5999 16:59:58.777035 # ok 104 # SKIP Disabled ZA for VL 560
6000 16:59:58.777191 # ok 105 # SKIP Get and set data for VL 560
6001 16:59:58.777336 # ok 106 Set VL 576
6002 16:59:58.777485 # ok 107 # SKIP Disabled ZA for VL 576
6003 16:59:58.777604 # ok 108 # SKIP Get and set data for VL 576
6004 16:59:58.777798 # ok 109 Set VL 592
6005 16:59:58.777991 # ok 110 # SKIP Disabled ZA for VL 592
6006 16:59:58.778174 # ok 111 # SKIP Get and set data for VL 592
6007 16:59:58.778355 # ok 112 Set VL 608
6008 16:59:58.778532 # ok 113 # SKIP Disabled ZA for VL 608
6009 16:59:58.778680 # ok 114 # SKIP Get and set data for VL 608
6010 16:59:58.778823 # ok 115 Set VL 624
6011 16:59:58.778965 # ok 116 # SKIP Disabled ZA for VL 624
6012 16:59:58.779145 # ok 117 # SKIP Get and set data for VL 624
6013 16:59:58.779282 # ok 118 Set VL 640
6014 16:59:58.779423 # ok 119 # SKIP Disabled ZA for VL 640
6015 16:59:58.779564 # ok 120 # SKIP Get and set data for VL 640
6016 16:59:58.779705 # ok 121 Set VL 656
6017 16:59:58.779846 # ok 122 # SKIP Disabled ZA for VL 656
6018 16:59:58.779986 # ok 123 # SKIP Get and set data for VL 656
6019 16:59:58.780125 # ok 124 Set VL 672
6020 16:59:58.787962 # ok 125 # SKIP Disabled ZA for VL 672
6021 16:59:58.788125 # ok 126 # SKIP Get and set data for VL 672
6022 16:59:58.788360 # ok 127 Set VL 688
6023 16:59:58.788557 # ok 128 # SKIP Disabled ZA for VL 688
6024 16:59:58.788782 # ok 129 # SKIP Get and set data for VL 688
6025 16:59:58.788967 # ok 130 Set VL 704
6026 16:59:58.789132 # ok 131 # SKIP Disabled ZA for VL 704
6027 16:59:58.789302 # ok 132 # SKIP Get and set data for VL 704
6028 16:59:58.789461 # ok 133 Set VL 720
6029 16:59:58.789748 # ok 134 # SKIP Disabled ZA for VL 720
6030 16:59:58.789963 # ok 135 # SKIP Get and set data for VL 720
6031 16:59:58.790140 # ok 136 Set VL 736
6032 16:59:58.790297 # ok 137 # SKIP Disabled ZA for VL 736
6033 16:59:58.790450 # ok 138 # SKIP Get and set data for VL 736
6034 16:59:58.790610 # ok 139 Set VL 752
6035 16:59:58.790766 # ok 140 # SKIP Disabled ZA for VL 752
6036 16:59:58.790920 # ok 141 # SKIP Get and set data for VL 752
6037 16:59:58.791073 # ok 142 Set VL 768
6038 16:59:58.791227 # ok 143 # SKIP Disabled ZA for VL 768
6039 16:59:58.791433 # ok 144 # SKIP Get and set data for VL 768
6040 16:59:58.791609 # ok 145 Set VL 784
6041 16:59:58.791767 # ok 146 # SKIP Disabled ZA for VL 784
6042 16:59:58.791907 # ok 147 # SKIP Get and set data for VL 784
6043 16:59:58.792025 # ok 148 Set VL 800
6044 16:59:58.792138 # ok 149 # SKIP Disabled ZA for VL 800
6045 16:59:58.792252 # ok 150 # SKIP Get and set data for VL 800
6046 16:59:58.792364 # ok 151 Set VL 816
6047 16:59:58.792476 # ok 152 # SKIP Disabled ZA for VL 816
6048 16:59:58.792588 # ok 153 # SKIP Get and set data for VL 816
6049 16:59:58.792698 # ok 154 Set VL 832
6050 16:59:58.792809 # ok 155 # SKIP Disabled ZA for VL 832
6051 16:59:58.792920 # ok 156 # SKIP Get and set data for VL 832
6052 16:59:58.793031 # ok 157 Set VL 848
6053 16:59:58.793142 # ok 158 # SKIP Disabled ZA for VL 848
6054 16:59:58.793255 # ok 159 # SKIP Get and set data for VL 848
6055 16:59:58.793367 # ok 160 Set VL 864
6056 16:59:58.793478 # ok 161 # SKIP Disabled ZA for VL 864
6057 16:59:58.793589 # ok 162 # SKIP Get and set data for VL 864
6058 16:59:58.793791 # ok 163 Set VL 880
6059 16:59:58.793987 # ok 164 # SKIP Disabled ZA for VL 880
6060 16:59:58.794170 # ok 165 # SKIP Get and set data for VL 880
6061 16:59:58.794352 # ok 166 Set VL 896
6062 16:59:58.794537 # ok 167 # SKIP Disabled ZA for VL 896
6063 16:59:58.794761 # ok 168 # SKIP Get and set data for VL 896
6064 16:59:58.794950 # ok 169 Set VL 912
6065 16:59:58.795133 # ok 170 # SKIP Disabled ZA for VL 912
6066 16:59:58.795276 # ok 171 # SKIP Get and set data for VL 912
6067 16:59:58.795419 # ok 172 Set VL 928
6068 16:59:58.795560 # ok 173 # SKIP Disabled ZA for VL 928
6069 16:59:58.800630 # ok 174 # SKIP Get and set data for VL 928
6070 16:59:58.800893 # ok 175 Set VL 944
6071 16:59:58.801273 # ok 176 # SKIP Disabled ZA for VL 944
6072 16:59:58.801465 # ok 177 # SKIP Get and set data for VL 944
6073 16:59:58.801636 # ok 178 Set VL 960
6074 16:59:58.801806 # ok 179 # SKIP Disabled ZA for VL 960
6075 16:59:58.801952 # ok 180 # SKIP Get and set data for VL 960
6076 16:59:58.802108 # ok 181 Set VL 976
6077 16:59:58.802268 # ok 182 # SKIP Disabled ZA for VL 976
6078 16:59:58.802428 # ok 183 # SKIP Get and set data for VL 976
6079 16:59:58.802593 # ok 184 Set VL 992
6080 16:59:58.802794 # ok 185 # SKIP Disabled ZA for VL 992
6081 16:59:58.802973 # ok 186 # SKIP Get and set data for VL 992
6082 16:59:58.803188 # ok 187 Set VL 1008
6083 16:59:58.803364 # ok 188 # SKIP Disabled ZA for VL 1008
6084 16:59:58.803508 # ok 189 # SKIP Get and set data for VL 1008
6085 16:59:58.803631 # ok 190 Set VL 1024
6086 16:59:58.803773 # ok 191 # SKIP Disabled ZA for VL 1024
6087 16:59:58.803907 # ok 192 # SKIP Get and set data for VL 1024
6088 16:59:58.804023 # ok 193 Set VL 1040
6089 16:59:58.804135 # ok 194 # SKIP Disabled ZA for VL 1040
6090 16:59:58.804269 # ok 195 # SKIP Get and set data for VL 1040
6091 16:59:58.804428 # ok 196 Set VL 1056
6092 16:59:58.804563 # ok 197 # SKIP Disabled ZA for VL 1056
6093 16:59:58.804681 # ok 198 # SKIP Get and set data for VL 1056
6094 16:59:58.804794 # ok 199 Set VL 1072
6095 16:59:58.804907 # ok 200 # SKIP Disabled ZA for VL 1072
6096 16:59:58.805019 # ok 201 # SKIP Get and set data for VL 1072
6097 16:59:58.805130 # ok 202 Set VL 1088
6098 16:59:58.805243 # ok 203 # SKIP Disabled ZA for VL 1088
6099 16:59:58.805355 # ok 204 # SKIP Get and set data for VL 1088
6100 16:59:58.805500 # ok 205 Set VL 1104
6101 16:59:58.805623 # ok 206 # SKIP Disabled ZA for VL 1104
6102 16:59:58.805848 # ok 207 # SKIP Get and set data for VL 1104
6103 16:59:58.806042 # ok 208 Set VL 1120
6104 16:59:58.806224 # ok 209 # SKIP Disabled ZA for VL 1120
6105 16:59:58.806408 # ok 210 # SKIP Get and set data for VL 1120
6106 16:59:58.806587 # ok 211 Set VL 1136
6107 16:59:58.806769 # ok 212 # SKIP Disabled ZA for VL 1136
6108 16:59:58.806921 # ok 213 # SKIP Get and set data for VL 1136
6109 16:59:58.807067 # ok 214 Set VL 1152
6110 16:59:58.807210 # ok 215 # SKIP Disabled ZA for VL 1152
6111 16:59:58.807350 # ok 216 # SKIP Get and set data for VL 1152
6112 16:59:58.807491 # ok 217 Set VL 1168
6113 16:59:58.810730 # ok 218 # SKIP Disabled ZA for VL 1168
6114 16:59:58.810930 # ok 219 # SKIP Get and set data for VL 1168
6115 16:59:58.811399 # ok 220 Set VL 1184
6116 16:59:58.811513 # ok 221 # SKIP Disabled ZA for VL 1184
6117 16:59:58.811604 # ok 222 # SKIP Get and set data for VL 1184
6118 16:59:58.811690 # ok 223 Set VL 1200
6119 16:59:58.811771 # ok 224 # SKIP Disabled ZA for VL 1200
6120 16:59:58.811851 # ok 225 # SKIP Get and set data for VL 1200
6121 16:59:58.811927 # ok 226 Set VL 1216
6122 16:59:58.812019 # ok 227 # SKIP Disabled ZA for VL 1216
6123 16:59:58.812100 # ok 228 # SKIP Get and set data for VL 1216
6124 16:59:58.812178 # ok 229 Set VL 1232
6125 16:59:58.812255 # ok 230 # SKIP Disabled ZA for VL 1232
6126 16:59:58.812640 # ok 231 # SKIP Get and set data for VL 1232
6127 16:59:58.812745 # ok 232 Set VL 1248
6128 16:59:58.813027 # ok 233 # SKIP Disabled ZA for VL 1248
6129 16:59:58.813131 # ok 234 # SKIP Get and set data for VL 1248
6130 16:59:58.813218 # ok 235 Set VL 1264
6131 16:59:58.813317 # ok 236 # SKIP Disabled ZA for VL 1264
6132 16:59:58.813406 # ok 237 # SKIP Get and set data for VL 1264
6133 16:59:58.813489 # ok 238 Set VL 1280
6134 16:59:58.813569 # ok 239 # SKIP Disabled ZA for VL 1280
6135 16:59:58.813676 # ok 240 # SKIP Get and set data for VL 1280
6136 16:59:58.813763 # ok 241 Set VL 1296
6137 16:59:58.813846 # ok 242 # SKIP Disabled ZA for VL 1296
6138 16:59:58.813944 # ok 243 # SKIP Get and set data for VL 1296
6139 16:59:58.814040 # ok 244 Set VL 1312
6140 16:59:58.814126 # ok 245 # SKIP Disabled ZA for VL 1312
6141 16:59:58.814223 # ok 246 # SKIP Get and set data for VL 1312
6142 16:59:58.814308 # ok 247 Set VL 1328
6143 16:59:58.814403 # ok 248 # SKIP Disabled ZA for VL 1328
6144 16:59:58.814511 # ok 249 # SKIP Get and set data for VL 1328
6145 16:59:58.814610 # ok 250 Set VL 1344
6146 16:59:58.814708 # ok 251 # SKIP Disabled ZA for VL 1344
6147 16:59:58.815032 # ok 252 # SKIP Get and set data for VL 1344
6148 16:59:58.815275 # ok 253 Set VL 1360
6149 16:59:58.815515 # ok 254 # SKIP Disabled ZA for VL 1360
6150 16:59:58.815697 # ok 255 # SKIP Get and set data for VL 1360
6151 16:59:58.815856 # ok 256 Set VL 1376
6152 16:59:58.815983 # ok 257 # SKIP Disabled ZA for VL 1376
6153 16:59:58.816098 # ok 258 # SKIP Get and set data for VL 1376
6154 16:59:58.816212 # ok 259 Set VL 1392
6155 16:59:58.816351 # ok 260 # SKIP Disabled ZA for VL 1392
6156 16:59:58.816471 # ok 261 # SKIP Get and set data for VL 1392
6157 16:59:58.816587 # ok 262 Set VL 1408
6158 16:59:58.822986 # ok 263 # SKIP Disabled ZA for VL 1408
6159 16:59:58.823473 # ok 264 # SKIP Get and set data for VL 1408
6160 16:59:58.823680 # ok 265 Set VL 1424
6161 16:59:58.823869 # ok 266 # SKIP Disabled ZA for VL 1424
6162 16:59:58.824004 # ok 267 # SKIP Get and set data for VL 1424
6163 16:59:58.824123 # ok 268 Set VL 1440
6164 16:59:58.824315 # ok 269 # SKIP Disabled ZA for VL 1440
6165 16:59:58.824446 # ok 270 # SKIP Get and set data for VL 1440
6166 16:59:58.824564 # ok 271 Set VL 1456
6167 16:59:58.824681 # ok 272 # SKIP Disabled ZA for VL 1456
6168 16:59:58.824799 # ok 273 # SKIP Get and set data for VL 1456
6169 16:59:58.827462 # ok 274 Set VL 1472
6170 16:59:58.827763 # ok 275 # SKIP Disabled ZA for VL 1472
6171 16:59:58.827860 # ok 276 # SKIP Get and set data for VL 1472
6172 16:59:58.827946 # ok 277 Set VL 1488
6173 16:59:58.828690 # ok 278 # SKIP Disabled ZA for VL 1488
6174 16:59:58.828933 # ok 279 # SKIP Get and set data for VL 1488
6175 16:59:58.829016 # ok 280 Set VL 1504
6176 16:59:58.829090 # ok 281 # SKIP Disabled ZA for VL 1504
6177 16:59:58.829172 # ok 282 # SKIP Get and set data for VL 1504
6178 16:59:58.829249 # ok 283 Set VL 1520
6179 16:59:58.829321 # ok 284 # SKIP Disabled ZA for VL 1520
6180 16:59:58.829584 # ok 285 # SKIP Get and set data for VL 1520
6181 16:59:58.829663 # ok 286 Set VL 1536
6182 16:59:58.829737 # ok 287 # SKIP Disabled ZA for VL 1536
6183 16:59:58.829985 # ok 288 # SKIP Get and set data for VL 1536
6184 16:59:58.830052 # ok 289 Set VL 1552
6185 16:59:58.830294 # ok 290 # SKIP Disabled ZA for VL 1552
6186 16:59:58.830360 # ok 291 # SKIP Get and set data for VL 1552
6187 16:59:58.830421 # ok 292 Set VL 1568
6188 16:59:58.830481 # ok 293 # SKIP Disabled ZA for VL 1568
6189 16:59:58.830552 # ok 294 # SKIP Get and set data for VL 1568
6190 16:59:58.830616 # ok 295 Set VL 1584
6191 16:59:58.830687 # ok 296 # SKIP Disabled ZA for VL 1584
6192 16:59:58.830750 # ok 297 # SKIP Get and set data for VL 1584
6193 16:59:58.830821 # ok 298 Set VL 1600
6194 16:59:58.831060 # ok 299 # SKIP Disabled ZA for VL 1600
6195 16:59:58.831127 # ok 300 # SKIP Get and set data for VL 1600
6196 16:59:58.831199 # ok 301 Set VL 1616
6197 16:59:58.831273 # ok 302 # SKIP Disabled ZA for VL 1616
6198 16:59:58.831522 # ok 303 # SKIP Get and set data for VL 1616
6199 16:59:58.831589 # ok 304 Set VL 1632
6200 16:59:58.831650 # ok 305 # SKIP Disabled ZA for VL 1632
6201 16:59:58.831725 # ok 306 # SKIP Get and set data for VL 1632
6202 16:59:58.831788 # ok 307 Set VL 1648
6203 16:59:58.877311 # ok 308 # SKIP Disabled ZA for VL 1648
6204 16:59:58.877538 # ok 309 # SKIP Get and set data for VL 1648
6205 16:59:58.877834 # ok 310 Set VL 1664
6206 16:59:58.877976 # ok 311 # SKIP Disabled ZA for VL 1664
6207 16:59:58.878154 # ok 312 # SKIP Get and set data for VL 1664
6208 16:59:58.878389 # ok 313 Set VL 1680
6209 16:59:58.878569 # ok 314 # SKIP Disabled ZA for VL 1680
6210 16:59:58.878736 # ok 315 # SKIP Get and set data for VL 1680
6211 16:59:58.878878 # ok 316 Set VL 1696
6212 16:59:58.879057 # ok 317 # SKIP Disabled ZA for VL 1696
6213 16:59:58.879243 # ok 318 # SKIP Get and set data for VL 1696
6214 16:59:58.879405 # ok 319 Set VL 1712
6215 16:59:58.879562 # ok 320 # SKIP Disabled ZA for VL 1712
6216 16:59:58.879768 # ok 321 # SKIP Get and set data for VL 1712
6217 16:59:58.879907 # ok 322 Set VL 1728
6218 16:59:58.880024 # ok 323 # SKIP Disabled ZA for VL 1728
6219 16:59:58.880139 # ok 324 # SKIP Get and set data for VL 1728
6220 16:59:58.880251 # ok 325 Set VL 1744
6221 16:59:58.880366 # ok 326 # SKIP Disabled ZA for VL 1744
6222 16:59:58.880481 # ok 327 # SKIP Get and set data for VL 1744
6223 16:59:58.880594 # ok 328 Set VL 1760
6224 16:59:58.880706 # ok 329 # SKIP Disabled ZA for VL 1760
6225 16:59:58.880819 # ok 330 # SKIP Get and set data for VL 1760
6226 16:59:58.880933 # ok 331 Set VL 1776
6227 16:59:58.881047 # ok 332 # SKIP Disabled ZA for VL 1776
6228 16:59:58.881160 # ok 333 # SKIP Get and set data for VL 1776
6229 16:59:58.881273 # ok 334 Set VL 1792
6230 16:59:58.881386 # ok 335 # SKIP Disabled ZA for VL 1792
6231 16:59:58.893589 # ok 336 # SKIP Get and set data for VL 1792
6232 16:59:58.893924 # ok 337 Set VL 1808
6233 16:59:58.894314 # ok 338 # SKIP Disabled ZA for VL 1808
6234 16:59:58.894514 # ok 339 # SKIP Get and set data for VL 1808
6235 16:59:58.894684 # ok 340 Set VL 1824
6236 16:59:58.894842 # ok 341 # SKIP Disabled ZA for VL 1824
6237 16:59:58.894996 # ok 342 # SKIP Get and set data for VL 1824
6238 16:59:58.895145 # ok 343 Set VL 1840
6239 16:59:58.895333 # ok 344 # SKIP Disabled ZA for VL 1840
6240 16:59:58.895491 # ok 345 # SKIP Get and set data for VL 1840
6241 16:59:58.895639 # ok 346 Set VL 1856
6242 16:59:58.895801 # ok 347 # SKIP Disabled ZA for VL 1856
6243 16:59:58.895948 # ok 348 # SKIP Get and set data for VL 1856
6244 16:59:58.896096 # ok 349 Set VL 1872
6245 16:59:58.896245 # ok 350 # SKIP Disabled ZA for VL 1872
6246 16:59:58.896394 # ok 351 # SKIP Get and set data for VL 1872
6247 16:59:58.896542 # ok 352 Set VL 1888
6248 16:59:58.896689 # ok 353 # SKIP Disabled ZA for VL 1888
6249 16:59:58.896841 # ok 354 # SKIP Get and set data for VL 1888
6250 16:59:58.896991 # ok 355 Set VL 1904
6251 16:59:58.897172 # ok 356 # SKIP Disabled ZA for VL 1904
6252 16:59:58.897327 # ok 357 # SKIP Get and set data for VL 1904
6253 16:59:58.897477 # ok 358 Set VL 1920
6254 16:59:58.910785 # ok 359 # SKIP Disabled ZA for VL 1920
6255 16:59:58.911107 # ok 360 # SKIP Get and set data for VL 1920
6256 16:59:58.911273 # ok 361 Set VL 1936
6257 16:59:58.911408 # ok 362 # SKIP Disabled ZA for VL 1936
6258 16:59:58.911607 # ok 363 # SKIP Get and set data for VL 1936
6259 16:59:58.911775 # ok 364 Set VL 1952
6260 16:59:58.911906 # ok 365 # SKIP Disabled ZA for VL 1952
6261 16:59:58.912024 # ok 366 # SKIP Get and set data for VL 1952
6262 16:59:58.912139 # ok 367 Set VL 1968
6263 16:59:58.912253 # ok 368 # SKIP Disabled ZA for VL 1968
6264 16:59:58.912367 # ok 369 # SKIP Get and set data for VL 1968
6265 16:59:58.912479 # ok 370 Set VL 1984
6266 16:59:58.912592 # ok 371 # SKIP Disabled ZA for VL 1984
6267 16:59:58.912732 # ok 372 # SKIP Get and set data for VL 1984
6268 16:59:58.912851 # ok 373 Set VL 2000
6269 16:59:58.919097 # ok 374 # SKIP Disabled ZA for VL 2000
6270 16:59:58.919350 # ok 375 # SKIP Get and set data for VL 2000
6271 16:59:58.919803 # ok 376 Set VL 2016
6272 16:59:58.920019 # ok 377 # SKIP Disabled ZA for VL 2016
6273 16:59:58.920204 # ok 378 # SKIP Get and set data for VL 2016
6274 16:59:58.920382 # ok 379 Set VL 2032
6275 16:59:58.920556 # ok 380 # SKIP Disabled ZA for VL 2032
6276 16:59:58.920734 # ok 381 # SKIP Get and set data for VL 2032
6277 16:59:58.920917 # ok 382 Set VL 2048
6278 16:59:58.921097 # ok 383 # SKIP Disabled ZA for VL 2048
6279 16:59:58.921304 # ok 384 # SKIP Get and set data for VL 2048
6280 16:59:58.921483 # ok 385 Set VL 2064
6281 16:59:58.921669 # ok 386 # SKIP Disabled ZA for VL 2064
6282 16:59:58.921844 # ok 387 # SKIP Get and set data for VL 2064
6283 16:59:58.922016 # ok 388 Set VL 2080
6284 16:59:58.922221 # ok 389 # SKIP Disabled ZA for VL 2080
6285 16:59:58.922399 # ok 390 # SKIP Get and set data for VL 2080
6286 16:59:58.922571 # ok 391 Set VL 2096
6287 16:59:58.922746 # ok 392 # SKIP Disabled ZA for VL 2096
6288 16:59:58.922928 # ok 393 # SKIP Get and set data for VL 2096
6289 16:59:58.923107 # ok 394 Set VL 2112
6290 16:59:58.923286 # ok 395 # SKIP Disabled ZA for VL 2112
6291 16:59:58.923465 # ok 396 # SKIP Get and set data for VL 2112
6292 16:59:58.923647 # ok 397 Set VL 2128
6293 16:59:58.923826 # ok 398 # SKIP Disabled ZA for VL 2128
6294 16:59:58.924052 # ok 399 # SKIP Get and set data for VL 2128
6295 16:59:58.924240 # ok 400 Set VL 2144
6296 16:59:58.924420 # ok 401 # SKIP Disabled ZA for VL 2144
6297 16:59:58.924599 # ok 402 # SKIP Get and set data for VL 2144
6298 16:59:58.924779 # ok 403 Set VL 2160
6299 16:59:58.924956 # ok 404 # SKIP Disabled ZA for VL 2160
6300 16:59:58.925135 # ok 405 # SKIP Get and set data for VL 2160
6301 16:59:58.925313 # ok 406 Set VL 2176
6302 16:59:58.925491 # ok 407 # SKIP Disabled ZA for VL 2176
6303 16:59:58.926554 # ok 408 # SKIP Get and set data for VL 2176
6304 16:59:58.926769 # ok 409 Set VL 2192
6305 16:59:58.926959 # ok 410 # SKIP Disabled ZA for VL 2192
6306 16:59:58.927141 # ok 411 # SKIP Get and set data for VL 2192
6307 16:59:58.927324 # ok 412 Set VL 2208
6308 16:59:58.927506 # ok 413 # SKIP Disabled ZA for VL 2208
6309 16:59:58.927688 # ok 414 # SKIP Get and set data for VL 2208
6310 16:59:58.927870 # ok 415 Set VL 2224
6311 16:59:58.928051 # ok 416 # SKIP Disabled ZA for VL 2224
6312 16:59:58.928232 # ok 417 # SKIP Get and set data for VL 2224
6313 16:59:58.928415 # ok 418 Set VL 2240
6314 16:59:58.928991 # ok 419 # SKIP Disabled ZA for VL 2240
6315 16:59:58.929174 # ok 420 # SKIP Get and set data for VL 2240
6316 16:59:58.929588 # ok 421 Set VL 2256
6317 16:59:58.929769 # ok 422 # SKIP Disabled ZA for VL 2256
6318 16:59:58.929988 # ok 423 # SKIP Get and set data for VL 2256
6319 16:59:58.930206 # ok 424 Set VL 2272
6320 16:59:58.930402 # ok 425 # SKIP Disabled ZA for VL 2272
6321 16:59:58.930594 # ok 426 # SKIP Get and set data for VL 2272
6322 16:59:58.930737 # ok 427 Set VL 2288
6323 16:59:58.930867 # ok 428 # SKIP Disabled ZA for VL 2288
6324 16:59:58.931023 # ok 429 # SKIP Get and set data for VL 2288
6325 16:59:58.931156 # ok 430 Set VL 2304
6326 16:59:58.931281 # ok 431 # SKIP Disabled ZA for VL 2304
6327 16:59:58.931407 # ok 432 # SKIP Get and set data for VL 2304
6328 16:59:58.931532 # ok 433 Set VL 2320
6329 16:59:58.931674 # ok 434 # SKIP Disabled ZA for VL 2320
6330 16:59:58.931859 # ok 435 # SKIP Get and set data for VL 2320
6331 16:59:58.931991 # ok 436 Set VL 2336
6332 16:59:58.932108 # ok 437 # SKIP Disabled ZA for VL 2336
6333 16:59:58.932223 # ok 438 # SKIP Get and set data for VL 2336
6334 16:59:58.932338 # ok 439 Set VL 2352
6335 16:59:58.932453 # ok 440 # SKIP Disabled ZA for VL 2352
6336 16:59:58.932567 # ok 441 # SKIP Get and set data for VL 2352
6337 16:59:58.932681 # ok 442 Set VL 2368
6338 16:59:58.932795 # ok 443 # SKIP Disabled ZA for VL 2368
6339 16:59:58.932940 # ok 444 # SKIP Get and set data for VL 2368
6340 16:59:58.933063 # ok 445 Set VL 2384
6341 16:59:58.933228 # ok 446 # SKIP Disabled ZA for VL 2384
6342 16:59:58.933407 # ok 447 # SKIP Get and set data for VL 2384
6343 16:59:58.933568 # ok 448 Set VL 2400
6344 16:59:58.933737 # ok 449 # SKIP Disabled ZA for VL 2400
6345 16:59:58.933892 # ok 450 # SKIP Get and set data for VL 2400
6346 16:59:58.934047 # ok 451 Set VL 2416
6347 16:59:58.934201 # ok 452 # SKIP Disabled ZA for VL 2416
6348 16:59:58.937242 # ok 453 # SKIP Get and set data for VL 2416
6349 16:59:58.937706 # ok 454 Set VL 2432
6350 16:59:58.937902 # ok 455 # SKIP Disabled ZA for VL 2432
6351 16:59:58.938062 # ok 456 # SKIP Get and set data for VL 2432
6352 16:59:58.938215 # ok 457 Set VL 2448
6353 16:59:58.938365 # ok 458 # SKIP Disabled ZA for VL 2448
6354 16:59:58.938548 # ok 459 # SKIP Get and set data for VL 2448
6355 16:59:58.938714 # ok 460 Set VL 2464
6356 16:59:58.938837 # ok 461 # SKIP Disabled ZA for VL 2464
6357 16:59:58.939012 # ok 462 # SKIP Get and set data for VL 2464
6358 16:59:58.939201 # ok 463 Set VL 2480
6359 16:59:58.939342 # ok 464 # SKIP Disabled ZA for VL 2480
6360 16:59:58.939471 # ok 465 # SKIP Get and set data for VL 2480
6361 16:59:58.939648 # ok 466 Set VL 2496
6362 16:59:58.939869 # ok 467 # SKIP Disabled ZA for VL 2496
6363 16:59:58.940018 # ok 468 # SKIP Get and set data for VL 2496
6364 16:59:58.940140 # ok 469 Set VL 2512
6365 16:59:58.940256 # ok 470 # SKIP Disabled ZA for VL 2512
6366 16:59:58.940371 # ok 471 # SKIP Get and set data for VL 2512
6367 16:59:58.940488 # ok 472 Set VL 2528
6368 16:59:58.940602 # ok 473 # SKIP Disabled ZA for VL 2528
6369 16:59:58.940717 # ok 474 # SKIP Get and set data for VL 2528
6370 16:59:58.940833 # ok 475 Set VL 2544
6371 16:59:58.940948 # ok 476 # SKIP Disabled ZA for VL 2544
6372 16:59:58.941063 # ok 477 # SKIP Get and set data for VL 2544
6373 16:59:58.941179 # ok 478 Set VL 2560
6374 16:59:58.945239 # ok 479 # SKIP Disabled ZA for VL 2560
6375 16:59:58.945606 # ok 480 # SKIP Get and set data for VL 2560
6376 16:59:58.945725 # ok 481 Set VL 2576
6377 16:59:58.945829 # ok 482 # SKIP Disabled ZA for VL 2576
6378 16:59:58.945916 # ok 483 # SKIP Get and set data for VL 2576
6379 16:59:58.945999 # ok 484 Set VL 2592
6380 16:59:58.946096 # ok 485 # SKIP Disabled ZA for VL 2592
6381 16:59:58.946181 # ok 486 # SKIP Get and set data for VL 2592
6382 16:59:58.946264 # ok 487 Set VL 2608
6383 16:59:58.946359 # ok 488 # SKIP Disabled ZA for VL 2608
6384 16:59:58.946443 # ok 489 # SKIP Get and set data for VL 2608
6385 16:59:58.946525 # ok 490 Set VL 2624
6386 16:59:58.946620 # ok 491 # SKIP Disabled ZA for VL 2624
6387 16:59:58.946704 # ok 492 # SKIP Get and set data for VL 2624
6388 16:59:58.946785 # ok 493 Set VL 2640
6389 16:59:58.946881 # ok 494 # SKIP Disabled ZA for VL 2640
6390 16:59:58.946964 # ok 495 # SKIP Get and set data for VL 2640
6391 16:59:58.947048 # ok 496 Set VL 2656
6392 16:59:58.947143 # ok 497 # SKIP Disabled ZA for VL 2656
6393 16:59:58.947227 # ok 498 # SKIP Get and set data for VL 2656
6394 16:59:58.947309 # ok 499 Set VL 2672
6395 16:59:58.947405 # ok 500 # SKIP Disabled ZA for VL 2672
6396 16:59:58.947492 # ok 501 # SKIP Get and set data for VL 2672
6397 16:59:58.947573 # ok 502 Set VL 2688
6398 16:59:58.947861 # ok 503 # SKIP Disabled ZA for VL 2688
6399 16:59:58.947965 # ok 504 # SKIP Get and set data for VL 2688
6400 16:59:58.948051 # ok 505 Set VL 2704
6401 16:59:58.948324 # ok 506 # SKIP Disabled ZA for VL 2704
6402 16:59:58.948414 # ok 507 # SKIP Get and set data for VL 2704
6403 16:59:58.948497 # ok 508 Set VL 2720
6404 16:59:58.948592 # ok 509 # SKIP Disabled ZA for VL 2720
6405 16:59:58.948676 # ok 510 # SKIP Get and set data for VL 2720
6406 16:59:58.948770 # ok 511 Set VL 2736
6407 16:59:58.948856 # ok 512 # SKIP Disabled ZA for VL 2736
6408 16:59:58.948956 # ok 513 # SKIP Get and set data for VL 2736
6409 16:59:58.949039 # ok 514 Set VL 2752
6410 16:59:58.949270 # ok 515 # SKIP Disabled ZA for VL 2752
6411 16:59:58.949361 # ok 516 # SKIP Get and set data for VL 2752
6412 16:59:58.949444 # ok 517 Set VL 2768
6413 16:59:58.949540 # ok 518 # SKIP Disabled ZA for VL 2768
6414 16:59:58.949624 # ok 519 # SKIP Get and set data for VL 2768
6415 16:59:58.949715 # ok 520 Set VL 2784
6416 16:59:58.949811 # ok 521 # SKIP Disabled ZA for VL 2784
6417 16:59:58.949895 # ok 522 # SKIP Get and set data for VL 2784
6418 16:59:58.949977 # ok 523 Set VL 2800
6419 16:59:58.950072 # ok 524 # SKIP Disabled ZA for VL 2800
6420 16:59:58.950155 # ok 525 # SKIP Get and set data for VL 2800
6421 16:59:58.950237 # ok 526 Set VL 2816
6422 16:59:58.950331 # ok 527 # SKIP Disabled ZA for VL 2816
6423 16:59:58.950415 # ok 528 # SKIP Get and set data for VL 2816
6424 16:59:58.950496 # ok 529 Set VL 2832
6425 16:59:58.950591 # ok 530 # SKIP Disabled ZA for VL 2832
6426 16:59:58.950675 # ok 531 # SKIP Get and set data for VL 2832
6427 16:59:58.950756 # ok 532 Set VL 2848
6428 16:59:58.950851 # ok 533 # SKIP Disabled ZA for VL 2848
6429 16:59:58.950948 # ok 534 # SKIP Get and set data for VL 2848
6430 16:59:58.951224 # ok 535 Set VL 2864
6431 16:59:58.951311 # ok 536 # SKIP Disabled ZA for VL 2864
6432 16:59:58.951394 # ok 537 # SKIP Get and set data for VL 2864
6433 16:59:58.951490 # ok 538 Set VL 2880
6434 16:59:58.951574 # ok 539 # SKIP Disabled ZA for VL 2880
6435 16:59:58.951656 # ok 540 # SKIP Get and set data for VL 2880
6436 16:59:58.951738 # ok 541 Set VL 2896
6437 16:59:58.951832 # ok 542 # SKIP Disabled ZA for VL 2896
6438 16:59:58.955109 # ok 543 # SKIP Get and set data for VL 2896
6439 16:59:58.955387 # ok 544 Set VL 2912
6440 16:59:58.955475 # ok 545 # SKIP Disabled ZA for VL 2912
6441 16:59:58.955558 # ok 546 # SKIP Get and set data for VL 2912
6442 16:59:58.955653 # ok 547 Set VL 2928
6443 16:59:58.955750 # ok 548 # SKIP Disabled ZA for VL 2928
6444 16:59:58.955834 # ok 549 # SKIP Get and set data for VL 2928
6445 16:59:58.959702 # ok 550 Set VL 2944
6446 16:59:58.960880 # ok 551 # SKIP Disabled ZA for VL 2944
6447 16:59:58.960972 # ok 552 # SKIP Get and set data for VL 2944
6448 16:59:58.961069 # ok 553 Set VL 2960
6449 16:59:58.961166 # ok 554 # SKIP Disabled ZA for VL 2960
6450 16:59:58.961264 # ok 555 # SKIP Get and set data for VL 2960
6451 16:59:58.961348 # ok 556 Set VL 2976
6452 16:59:58.961443 # ok 557 # SKIP Disabled ZA for VL 2976
6453 16:59:58.961539 # ok 558 # SKIP Get and set data for VL 2976
6454 16:59:58.961624 # ok 559 Set VL 2992
6455 16:59:58.961726 # ok 560 # SKIP Disabled ZA for VL 2992
6456 16:59:58.961824 # ok 561 # SKIP Get and set data for VL 2992
6457 16:59:58.961909 # ok 562 Set VL 3008
6458 16:59:58.962004 # ok 563 # SKIP Disabled ZA for VL 3008
6459 16:59:58.962088 # ok 564 # SKIP Get and set data for VL 3008
6460 16:59:58.962186 # ok 565 Set VL 3024
6461 16:59:58.962268 # ok 566 # SKIP Disabled ZA for VL 3024
6462 16:59:58.962362 # ok 567 # SKIP Get and set data for VL 3024
6463 16:59:58.962444 # ok 568 Set VL 3040
6464 16:59:58.962537 # ok 569 # SKIP Disabled ZA for VL 3040
6465 16:59:58.962620 # ok 570 # SKIP Get and set data for VL 3040
6466 16:59:58.962712 # ok 571 Set VL 3056
6467 16:59:58.962807 # ok 572 # SKIP Disabled ZA for VL 3056
6468 16:59:58.962888 # ok 573 # SKIP Get and set data for VL 3056
6469 16:59:58.962982 # ok 574 Set VL 3072
6470 16:59:58.963063 # ok 575 # SKIP Disabled ZA for VL 3072
6471 16:59:58.963156 # ok 576 # SKIP Get and set data for VL 3072
6472 16:59:58.963251 # ok 577 Set VL 3088
6473 16:59:58.963344 # ok 578 # SKIP Disabled ZA for VL 3088
6474 16:59:58.963439 # ok 579 # SKIP Get and set data for VL 3088
6475 16:59:58.963522 # ok 580 Set VL 3104
6476 16:59:58.963614 # ok 581 # SKIP Disabled ZA for VL 3104
6477 16:59:58.963696 # ok 582 # SKIP Get and set data for VL 3104
6478 16:59:58.963788 # ok 583 Set VL 3120
6479 16:59:58.968983 # ok 584 # SKIP Disabled ZA for VL 3120
6480 16:59:58.969365 # ok 585 # SKIP Get and set data for VL 3120
6481 16:59:58.969485 # ok 586 Set VL 3136
6482 16:59:58.969579 # ok 587 # SKIP Disabled ZA for VL 3136
6483 16:59:58.969697 # ok 588 # SKIP Get and set data for VL 3136
6484 16:59:58.969779 # ok 589 Set VL 3152
6485 16:59:58.970275 # ok 590 # SKIP Disabled ZA for VL 3152
6486 16:59:58.970584 # ok 591 # SKIP Get and set data for VL 3152
6487 16:59:58.970689 # ok 592 Set VL 3168
6488 16:59:58.970794 # ok 593 # SKIP Disabled ZA for VL 3168
6489 16:59:58.970894 # ok 594 # SKIP Get and set data for VL 3168
6490 16:59:58.970964 # ok 595 Set VL 3184
6491 16:59:58.971051 # ok 596 # SKIP Disabled ZA for VL 3184
6492 16:59:58.971143 # ok 597 # SKIP Get and set data for VL 3184
6493 16:59:58.971235 # ok 598 Set VL 3200
6494 16:59:58.971325 # ok 599 # SKIP Disabled ZA for VL 3200
6495 16:59:58.971411 # ok 600 # SKIP Get and set data for VL 3200
6496 16:59:58.971510 # ok 601 Set VL 3216
6497 16:59:58.971637 # ok 602 # SKIP Disabled ZA for VL 3216
6498 16:59:58.971721 # ok 603 # SKIP Get and set data for VL 3216
6499 16:59:58.971786 # ok 604 Set VL 3232
6500 16:59:58.971845 # ok 605 # SKIP Disabled ZA for VL 3232
6501 16:59:58.971904 # ok 606 # SKIP Get and set data for VL 3232
6502 16:59:58.971965 # ok 607 Set VL 3248
6503 16:59:58.977125 # ok 608 # SKIP Disabled ZA for VL 3248
6504 16:59:58.977565 # ok 609 # SKIP Get and set data for VL 3248
6505 16:59:58.977682 # ok 610 Set VL 3264
6506 16:59:58.977774 # ok 611 # SKIP Disabled ZA for VL 3264
6507 16:59:58.977860 # ok 612 # SKIP Get and set data for VL 3264
6508 16:59:58.977963 # ok 613 Set VL 3280
6509 16:59:58.978051 # ok 614 # SKIP Disabled ZA for VL 3280
6510 16:59:58.978138 # ok 615 # SKIP Get and set data for VL 3280
6511 16:59:58.978222 # ok 616 Set VL 3296
6512 16:59:58.978307 # ok 617 # SKIP Disabled ZA for VL 3296
6513 16:59:58.978409 # ok 618 # SKIP Get and set data for VL 3296
6514 16:59:58.978497 # ok 619 Set VL 3312
6515 16:59:58.978580 # ok 620 # SKIP Disabled ZA for VL 3312
6516 16:59:58.978678 # ok 621 # SKIP Get and set data for VL 3312
6517 16:59:58.978765 # ok 622 Set VL 3328
6518 16:59:58.978846 # ok 623 # SKIP Disabled ZA for VL 3328
6519 16:59:58.978944 # ok 624 # SKIP Get and set data for VL 3328
6520 16:59:58.979029 # ok 625 Set VL 3344
6521 16:59:58.979128 # ok 626 # SKIP Disabled ZA for VL 3344
6522 16:59:58.979216 # ok 627 # SKIP Get and set data for VL 3344
6523 16:59:58.979315 # ok 628 Set VL 3360
6524 16:59:58.979404 # ok 629 # SKIP Disabled ZA for VL 3360
6525 16:59:58.979505 # ok 630 # SKIP Get and set data for VL 3360
6526 16:59:58.979592 # ok 631 Set VL 3376
6527 16:59:58.979690 # ok 632 # SKIP Disabled ZA for VL 3376
6528 16:59:58.985194 # ok 633 # SKIP Get and set data for VL 3376
6529 16:59:58.985736 # ok 634 Set VL 3392
6530 16:59:58.985909 # ok 635 # SKIP Disabled ZA for VL 3392
6531 16:59:58.986079 # ok 636 # SKIP Get and set data for VL 3392
6532 16:59:58.986281 # ok 637 Set VL 3408
6533 16:59:58.986447 # ok 638 # SKIP Disabled ZA for VL 3408
6534 16:59:58.986610 # ok 639 # SKIP Get and set data for VL 3408
6535 16:59:58.986830 # ok 640 Set VL 3424
6536 16:59:58.986994 # ok 641 # SKIP Disabled ZA for VL 3424
6537 16:59:58.987142 # ok 642 # SKIP Get and set data for VL 3424
6538 16:59:58.987326 # ok 643 Set VL 3440
6539 16:59:58.987529 # ok 644 # SKIP Disabled ZA for VL 3440
6540 16:59:58.987683 # ok 645 # SKIP Get and set data for VL 3440
6541 16:59:58.987820 # ok 646 Set VL 3456
6542 16:59:58.987940 # ok 647 # SKIP Disabled ZA for VL 3456
6543 16:59:58.988059 # ok 648 # SKIP Get and set data for VL 3456
6544 16:59:58.988178 # ok 649 Set VL 3472
6545 16:59:58.988296 # ok 650 # SKIP Disabled ZA for VL 3472
6546 16:59:58.988445 # ok 651 # SKIP Get and set data for VL 3472
6547 16:59:58.988571 # ok 652 Set VL 3488
6548 16:59:58.988688 # ok 653 # SKIP Disabled ZA for VL 3488
6549 16:59:58.988805 # ok 654 # SKIP Get and set data for VL 3488
6550 16:59:58.988921 # ok 655 Set VL 3504
6551 16:59:58.989038 # ok 656 # SKIP Disabled ZA for VL 3504
6552 16:59:58.989156 # ok 657 # SKIP Get and set data for VL 3504
6553 16:59:58.989273 # ok 658 Set VL 3520
6554 16:59:58.989388 # ok 659 # SKIP Disabled ZA for VL 3520
6555 16:59:58.989506 # ok 660 # SKIP Get and set data for VL 3520
6556 16:59:58.989623 # ok 661 Set VL 3536
6557 16:59:58.990257 # ok 662 # SKIP Disabled ZA for VL 3536
6558 16:59:58.990660 # ok 663 # SKIP Get and set data for VL 3536
6559 16:59:58.990854 # ok 664 Set VL 3552
6560 16:59:58.991024 # ok 665 # SKIP Disabled ZA for VL 3552
6561 16:59:58.991179 # ok 666 # SKIP Get and set data for VL 3552
6562 16:59:58.991331 # ok 667 Set VL 3568
6563 16:59:58.991508 # ok 668 # SKIP Disabled ZA for VL 3568
6564 16:59:58.991668 # ok 669 # SKIP Get and set data for VL 3568
6565 16:59:58.991803 # ok 670 Set VL 3584
6566 16:59:58.991919 # ok 671 # SKIP Disabled ZA for VL 3584
6567 16:59:58.992034 # ok 672 # SKIP Get and set data for VL 3584
6568 16:59:58.992148 # ok 673 Set VL 3600
6569 16:59:58.992261 # ok 674 # SKIP Disabled ZA for VL 3600
6570 16:59:58.992376 # ok 675 # SKIP Get and set data for VL 3600
6571 16:59:58.992516 # ok 676 Set VL 3616
6572 16:59:58.992635 # ok 677 # SKIP Disabled ZA for VL 3616
6573 16:59:58.992750 # ok 678 # SKIP Get and set data for VL 3616
6574 16:59:58.992864 # ok 679 Set VL 3632
6575 16:59:58.995509 # ok 680 # SKIP Disabled ZA for VL 3632
6576 16:59:58.995979 # ok 681 # SKIP Get and set data for VL 3632
6577 16:59:58.996138 # ok 682 Set VL 3648
6578 16:59:58.996264 # ok 683 # SKIP Disabled ZA for VL 3648
6579 16:59:59.000900 # ok 684 # SKIP Get and set data for VL 3648
6580 16:59:59.001201 # ok 685 Set VL 3664
6581 16:59:59.001663 # ok 686 # SKIP Disabled ZA for VL 3664
6582 16:59:59.001857 # ok 687 # SKIP Get and set data for VL 3664
6583 16:59:59.002033 # ok 688 Set VL 3680
6584 16:59:59.002195 # ok 689 # SKIP Disabled ZA for VL 3680
6585 16:59:59.002396 # ok 690 # SKIP Get and set data for VL 3680
6586 16:59:59.002547 # ok 691 Set VL 3696
6587 16:59:59.002705 # ok 692 # SKIP Disabled ZA for VL 3696
6588 16:59:59.002881 # ok 693 # SKIP Get and set data for VL 3696
6589 16:59:59.003047 # ok 694 Set VL 3712
6590 16:59:59.003198 # ok 695 # SKIP Disabled ZA for VL 3712
6591 16:59:59.003352 # ok 696 # SKIP Get and set data for VL 3712
6592 16:59:59.003514 # ok 697 Set VL 3728
6593 16:59:59.003656 # ok 698 # SKIP Disabled ZA for VL 3728
6594 16:59:59.003772 # ok 699 # SKIP Get and set data for VL 3728
6595 16:59:59.003886 # ok 700 Set VL 3744
6596 16:59:59.003998 # ok 701 # SKIP Disabled ZA for VL 3744
6597 16:59:59.004111 # ok 702 # SKIP Get and set data for VL 3744
6598 16:59:59.004225 # ok 703 Set VL 3760
6599 16:59:59.004337 # ok 704 # SKIP Disabled ZA for VL 3760
6600 16:59:59.004450 # ok 705 # SKIP Get and set data for VL 3760
6601 16:59:59.004589 # ok 706 Set VL 3776
6602 16:59:59.004709 # ok 707 # SKIP Disabled ZA for VL 3776
6603 16:59:59.004824 # ok 708 # SKIP Get and set data for VL 3776
6604 16:59:59.004937 # ok 709 Set VL 3792
6605 16:59:59.005050 # ok 710 # SKIP Disabled ZA for VL 3792
6606 16:59:59.005162 # ok 711 # SKIP Get and set data for VL 3792
6607 16:59:59.005274 # ok 712 Set VL 3808
6608 16:59:59.005387 # ok 713 # SKIP Disabled ZA for VL 3808
6609 16:59:59.009123 # ok 714 # SKIP Get and set data for VL 3808
6610 16:59:59.009413 # ok 715 Set VL 3824
6611 16:59:59.009859 # ok 716 # SKIP Disabled ZA for VL 3824
6612 16:59:59.010072 # ok 717 # SKIP Get and set data for VL 3824
6613 16:59:59.010252 # ok 718 Set VL 3840
6614 16:59:59.010459 # ok 719 # SKIP Disabled ZA for VL 3840
6615 16:59:59.010633 # ok 720 # SKIP Get and set data for VL 3840
6616 16:59:59.010846 # ok 721 Set VL 3856
6617 16:59:59.011067 # ok 722 # SKIP Disabled ZA for VL 3856
6618 16:59:59.011312 # ok 723 # SKIP Get and set data for VL 3856
6619 16:59:59.011515 # ok 724 Set VL 3872
6620 16:59:59.011710 # ok 725 # SKIP Disabled ZA for VL 3872
6621 16:59:59.011866 # ok 726 # SKIP Get and set data for VL 3872
6622 16:59:59.011987 # ok 727 Set VL 3888
6623 16:59:59.012103 # ok 728 # SKIP Disabled ZA for VL 3888
6624 16:59:59.012218 # ok 729 # SKIP Get and set data for VL 3888
6625 16:59:59.012334 # ok 730 Set VL 3904
6626 16:59:59.012447 # ok 731 # SKIP Disabled ZA for VL 3904
6627 16:59:59.012562 # ok 732 # SKIP Get and set data for VL 3904
6628 16:59:59.012679 # ok 733 Set VL 3920
6629 16:59:59.012793 # ok 734 # SKIP Disabled ZA for VL 3920
6630 16:59:59.012906 # ok 735 # SKIP Get and set data for VL 3920
6631 16:59:59.013019 # ok 736 Set VL 3936
6632 16:59:59.013134 # ok 737 # SKIP Disabled ZA for VL 3936
6633 16:59:59.013248 # ok 738 # SKIP Get and set data for VL 3936
6634 16:59:59.013394 # ok 739 Set VL 3952
6635 16:59:59.013518 # ok 740 # SKIP Disabled ZA for VL 3952
6636 16:59:59.013635 # ok 741 # SKIP Get and set data for VL 3952
6637 16:59:59.013771 # ok 742 Set VL 3968
6638 16:59:59.013887 # ok 743 # SKIP Disabled ZA for VL 3968
6639 16:59:59.014003 # ok 744 # SKIP Get and set data for VL 3968
6640 16:59:59.014116 # ok 745 Set VL 3984
6641 16:59:59.014230 # ok 746 # SKIP Disabled ZA for VL 3984
6642 16:59:59.019372 # ok 747 # SKIP Get and set data for VL 3984
6643 16:59:59.019914 # ok 748 Set VL 4000
6644 16:59:59.020071 # ok 749 # SKIP Disabled ZA for VL 4000
6645 16:59:59.020195 # ok 750 # SKIP Get and set data for VL 4000
6646 16:59:59.020312 # ok 751 Set VL 4016
6647 16:59:59.024981 # ok 752 # SKIP Disabled ZA for VL 4016
6648 16:59:59.025393 # ok 753 # SKIP Get and set data for VL 4016
6649 16:59:59.025490 # ok 754 Set VL 4032
6650 16:59:59.025578 # ok 755 # SKIP Disabled ZA for VL 4032
6651 16:59:59.025671 # ok 756 # SKIP Get and set data for VL 4032
6652 16:59:59.025755 # ok 757 Set VL 4048
6653 16:59:59.025857 # ok 758 # SKIP Disabled ZA for VL 4048
6654 16:59:59.025976 # ok 759 # SKIP Get and set data for VL 4048
6655 16:59:59.026070 # ok 760 Set VL 4064
6656 16:59:59.026156 # ok 761 # SKIP Disabled ZA for VL 4064
6657 16:59:59.026260 # ok 762 # SKIP Get and set data for VL 4064
6658 16:59:59.026350 # ok 763 Set VL 4080
6659 16:59:59.026436 # ok 764 # SKIP Disabled ZA for VL 4080
6660 16:59:59.026539 # ok 765 # SKIP Get and set data for VL 4080
6661 16:59:59.026629 # ok 766 Set VL 4096
6662 16:59:59.026728 # ok 767 # SKIP Disabled ZA for VL 4096
6663 16:59:59.026816 # ok 768 # SKIP Get and set data for VL 4096
6664 16:59:59.026901 # ok 769 Set VL 4112
6665 16:59:59.027002 # ok 770 # SKIP Disabled ZA for VL 4112
6666 16:59:59.027095 # ok 771 # SKIP Get and set data for VL 4112
6667 16:59:59.027194 # ok 772 Set VL 4128
6668 16:59:59.027282 # ok 773 # SKIP Disabled ZA for VL 4128
6669 16:59:59.027381 # ok 774 # SKIP Get and set data for VL 4128
6670 16:59:59.027469 # ok 775 Set VL 4144
6671 16:59:59.027567 # ok 776 # SKIP Disabled ZA for VL 4144
6672 16:59:59.027706 # ok 777 # SKIP Get and set data for VL 4144
6673 16:59:59.027863 # ok 778 Set VL 4160
6674 16:59:59.037093 # ok 779 # SKIP Disabled ZA for VL 4160
6675 16:59:59.037370 # ok 780 # SKIP Get and set data for VL 4160
6676 16:59:59.037700 # ok 781 Set VL 4176
6677 16:59:59.037795 # ok 782 # SKIP Disabled ZA for VL 4176
6678 16:59:59.037879 # ok 783 # SKIP Get and set data for VL 4176
6679 16:59:59.037953 # ok 784 Set VL 4192
6680 16:59:59.038030 # ok 785 # SKIP Disabled ZA for VL 4192
6681 16:59:59.038109 # ok 786 # SKIP Get and set data for VL 4192
6682 16:59:59.038189 # ok 787 Set VL 4208
6683 16:59:59.038269 # ok 788 # SKIP Disabled ZA for VL 4208
6684 16:59:59.038365 # ok 789 # SKIP Get and set data for VL 4208
6685 16:59:59.038448 # ok 790 Set VL 4224
6686 16:59:59.038526 # ok 791 # SKIP Disabled ZA for VL 4224
6687 16:59:59.038604 # ok 792 # SKIP Get and set data for VL 4224
6688 16:59:59.038685 # ok 793 Set VL 4240
6689 16:59:59.038760 # ok 794 # SKIP Disabled ZA for VL 4240
6690 16:59:59.038850 # ok 795 # SKIP Get and set data for VL 4240
6691 16:59:59.038934 # ok 796 Set VL 4256
6692 16:59:59.039015 # ok 797 # SKIP Disabled ZA for VL 4256
6693 16:59:59.039100 # ok 798 # SKIP Get and set data for VL 4256
6694 16:59:59.039169 # ok 799 Set VL 4272
6695 16:59:59.039268 # ok 800 # SKIP Disabled ZA for VL 4272
6696 16:59:59.039356 # ok 801 # SKIP Get and set data for VL 4272
6697 16:59:59.039432 # ok 802 Set VL 4288
6698 16:59:59.039528 # ok 803 # SKIP Disabled ZA for VL 4288
6699 16:59:59.039613 # ok 804 # SKIP Get and set data for VL 4288
6700 16:59:59.039706 # ok 805 Set VL 4304
6701 16:59:59.053616 # ok 806 # SKIP Disabled ZA for VL 4304
6702 16:59:59.054204 # ok 807 # SKIP Get and set data for VL 4304
6703 16:59:59.054361 # ok 808 Set VL 4320
6704 16:59:59.054484 # ok 809 # SKIP Disabled ZA for VL 4320
6705 16:59:59.054601 # ok 810 # SKIP Get and set data for VL 4320
6706 16:59:59.054717 # ok 811 Set VL 4336
6707 16:59:59.054833 # ok 812 # SKIP Disabled ZA for VL 4336
6708 16:59:59.054948 # ok 813 # SKIP Get and set data for VL 4336
6709 16:59:59.055061 # ok 814 Set VL 4352
6710 16:59:59.055217 # ok 815 # SKIP Disabled ZA for VL 4352
6711 16:59:59.055341 # ok 816 # SKIP Get and set data for VL 4352
6712 16:59:59.055457 # ok 817 Set VL 4368
6713 16:59:59.055572 # ok 818 # SKIP Disabled ZA for VL 4368
6714 16:59:59.055780 # ok 819 # SKIP Get and set data for VL 4368
6715 16:59:59.055917 # ok 820 Set VL 4384
6716 16:59:59.056034 # ok 821 # SKIP Disabled ZA for VL 4384
6717 16:59:59.056180 # ok 822 # SKIP Get and set data for VL 4384
6718 16:59:59.056304 # ok 823 Set VL 4400
6719 16:59:59.073202 # ok 824 # SKIP Disabled ZA for VL 4400
6720 16:59:59.073743 # ok 825 # SKIP Get and set data for VL 4400
6721 16:59:59.073937 # ok 826 Set VL 4416
6722 16:59:59.074085 # ok 827 # SKIP Disabled ZA for VL 4416
6723 16:59:59.074237 # ok 828 # SKIP Get and set data for VL 4416
6724 16:59:59.074371 # ok 829 Set VL 4432
6725 16:59:59.074562 # ok 830 # SKIP Disabled ZA for VL 4432
6726 16:59:59.074718 # ok 831 # SKIP Get and set data for VL 4432
6727 16:59:59.074927 # ok 832 Set VL 4448
6728 16:59:59.075134 # ok 833 # SKIP Disabled ZA for VL 4448
6729 16:59:59.075287 # ok 834 # SKIP Get and set data for VL 4448
6730 16:59:59.075453 # ok 835 Set VL 4464
6731 16:59:59.075605 # ok 836 # SKIP Disabled ZA for VL 4464
6732 16:59:59.075749 # ok 837 # SKIP Get and set data for VL 4464
6733 16:59:59.075915 # ok 838 Set VL 4480
6734 16:59:59.076055 # ok 839 # SKIP Disabled ZA for VL 4480
6735 16:59:59.076215 # ok 840 # SKIP Get and set data for VL 4480
6736 16:59:59.076368 # ok 841 Set VL 4496
6737 16:59:59.076549 # ok 842 # SKIP Disabled ZA for VL 4496
6738 16:59:59.076721 # ok 843 # SKIP Get and set data for VL 4496
6739 16:59:59.076866 # ok 844 Set VL 4512
6740 16:59:59.077032 # ok 845 # SKIP Disabled ZA for VL 4512
6741 16:59:59.077179 # ok 846 # SKIP Get and set data for VL 4512
6742 16:59:59.077329 # ok 847 Set VL 4528
6743 16:59:59.086928 # ok 848 # SKIP Disabled ZA for VL 4528
6744 16:59:59.087254 # ok 849 # SKIP Get and set data for VL 4528
6745 16:59:59.087775 # ok 850 Set VL 4544
6746 16:59:59.087929 # ok 851 # SKIP Disabled ZA for VL 4544
6747 16:59:59.088051 # ok 852 # SKIP Get and set data for VL 4544
6748 16:59:59.088165 # ok 853 Set VL 4560
6749 16:59:59.088277 # ok 854 # SKIP Disabled ZA for VL 4560
6750 16:59:59.088390 # ok 855 # SKIP Get and set data for VL 4560
6751 16:59:59.088637 # ok 856 Set VL 4576
6752 16:59:59.088848 # ok 857 # SKIP Disabled ZA for VL 4576
6753 16:59:59.089032 # ok 858 # SKIP Get and set data for VL 4576
6754 16:59:59.089180 # ok 859 Set VL 4592
6755 16:59:59.089340 # ok 860 # SKIP Disabled ZA for VL 4592
6756 16:59:59.089553 # ok 861 # SKIP Get and set data for VL 4592
6757 16:59:59.089737 # ok 862 Set VL 4608
6758 16:59:59.089893 # ok 863 # SKIP Disabled ZA for VL 4608
6759 16:59:59.090050 # ok 864 # SKIP Get and set data for VL 4608
6760 16:59:59.090210 # ok 865 Set VL 4624
6761 16:59:59.090370 # ok 866 # SKIP Disabled ZA for VL 4624
6762 16:59:59.090503 # ok 867 # SKIP Get and set data for VL 4624
6763 16:59:59.090651 # ok 868 Set VL 4640
6764 16:59:59.090814 # ok 869 # SKIP Disabled ZA for VL 4640
6765 16:59:59.090938 # ok 870 # SKIP Get and set data for VL 4640
6766 16:59:59.091086 # ok 871 Set VL 4656
6767 16:59:59.091245 # ok 872 # SKIP Disabled ZA for VL 4656
6768 16:59:59.091387 # ok 873 # SKIP Get and set data for VL 4656
6769 16:59:59.091526 # ok 874 Set VL 4672
6770 16:59:59.091666 # ok 875 # SKIP Disabled ZA for VL 4672
6771 16:59:59.091782 # ok 876 # SKIP Get and set data for VL 4672
6772 16:59:59.091897 # ok 877 Set VL 4688
6773 16:59:59.092010 # ok 878 # SKIP Disabled ZA for VL 4688
6774 16:59:59.092123 # ok 879 # SKIP Get and set data for VL 4688
6775 16:59:59.092266 # ok 880 Set VL 4704
6776 16:59:59.092387 # ok 881 # SKIP Disabled ZA for VL 4704
6777 16:59:59.092506 # ok 882 # SKIP Get and set data for VL 4704
6778 16:59:59.092621 # ok 883 Set VL 4720
6779 16:59:59.092735 # ok 884 # SKIP Disabled ZA for VL 4720
6780 16:59:59.092848 # ok 885 # SKIP Get and set data for VL 4720
6781 16:59:59.092962 # ok 886 Set VL 4736
6782 16:59:59.093074 # ok 887 # SKIP Disabled ZA for VL 4736
6783 16:59:59.093191 # ok 888 # SKIP Get and set data for VL 4736
6784 16:59:59.093303 # ok 889 Set VL 4752
6785 16:59:59.093417 # ok 890 # SKIP Disabled ZA for VL 4752
6786 16:59:59.098558 # ok 891 # SKIP Get and set data for VL 4752
6787 16:59:59.098817 # ok 892 Set VL 4768
6788 16:59:59.098981 # ok 893 # SKIP Disabled ZA for VL 4768
6789 16:59:59.099173 # ok 894 # SKIP Get and set data for VL 4768
6790 16:59:59.099340 # ok 895 Set VL 4784
6791 16:59:59.099497 # ok 896 # SKIP Disabled ZA for VL 4784
6792 16:59:59.099651 # ok 897 # SKIP Get and set data for VL 4784
6793 16:59:59.099773 # ok 898 Set VL 4800
6794 16:59:59.099885 # ok 899 # SKIP Disabled ZA for VL 4800
6795 16:59:59.099997 # ok 900 # SKIP Get and set data for VL 4800
6796 16:59:59.100109 # ok 901 Set VL 4816
6797 16:59:59.100250 # ok 902 # SKIP Disabled ZA for VL 4816
6798 16:59:59.100369 # ok 903 # SKIP Get and set data for VL 4816
6799 16:59:59.100483 # ok 904 Set VL 4832
6800 16:59:59.100596 # ok 905 # SKIP Disabled ZA for VL 4832
6801 16:59:59.100709 # ok 906 # SKIP Get and set data for VL 4832
6802 16:59:59.100820 # ok 907 Set VL 4848
6803 16:59:59.100932 # ok 908 # SKIP Disabled ZA for VL 4848
6804 16:59:59.111149 # ok 909 # SKIP Get and set data for VL 4848
6805 16:59:59.111475 # ok 910 Set VL 4864
6806 16:59:59.111688 # ok 911 # SKIP Disabled ZA for VL 4864
6807 16:59:59.112060 # ok 912 # SKIP Get and set data for VL 4864
6808 16:59:59.112198 # ok 913 Set VL 4880
6809 16:59:59.112316 # ok 914 # SKIP Disabled ZA for VL 4880
6810 16:59:59.112433 # ok 915 # SKIP Get and set data for VL 4880
6811 16:59:59.112549 # ok 916 Set VL 4896
6812 16:59:59.112664 # ok 917 # SKIP Disabled ZA for VL 4896
6813 16:59:59.117313 # ok 918 # SKIP Get and set data for VL 4896
6814 16:59:59.117546 # ok 919 Set VL 4912
6815 16:59:59.117833 # ok 920 # SKIP Disabled ZA for VL 4912
6816 16:59:59.118008 # ok 921 # SKIP Get and set data for VL 4912
6817 16:59:59.118146 # ok 922 Set VL 4928
6818 16:59:59.118277 # ok 923 # SKIP Disabled ZA for VL 4928
6819 16:59:59.118405 # ok 924 # SKIP Get and set data for VL 4928
6820 16:59:59.118535 # ok 925 Set VL 4944
6821 16:59:59.118661 # ok 926 # SKIP Disabled ZA for VL 4944
6822 16:59:59.118790 # ok 927 # SKIP Get and set data for VL 4944
6823 16:59:59.118944 # ok 928 Set VL 4960
6824 16:59:59.119077 # ok 929 # SKIP Disabled ZA for VL 4960
6825 16:59:59.119205 # ok 930 # SKIP Get and set data for VL 4960
6826 16:59:59.119330 # ok 931 Set VL 4976
6827 16:59:59.119455 # ok 932 # SKIP Disabled ZA for VL 4976
6828 16:59:59.119588 # ok 933 # SKIP Get and set data for VL 4976
6829 16:59:59.119716 # ok 934 Set VL 4992
6830 16:59:59.119839 # ok 935 # SKIP Disabled ZA for VL 4992
6831 16:59:59.119957 # ok 936 # SKIP Get and set data for VL 4992
6832 16:59:59.120073 # ok 937 Set VL 5008
6833 16:59:59.120220 # ok 938 # SKIP Disabled ZA for VL 5008
6834 16:59:59.120344 # ok 939 # SKIP Get and set data for VL 5008
6835 16:59:59.120462 # ok 940 Set VL 5024
6836 16:59:59.120578 # ok 941 # SKIP Disabled ZA for VL 5024
6837 16:59:59.120695 # ok 942 # SKIP Get and set data for VL 5024
6838 16:59:59.120811 # ok 943 Set VL 5040
6839 16:59:59.120927 # ok 944 # SKIP Disabled ZA for VL 5040
6840 16:59:59.125125 # ok 945 # SKIP Get and set data for VL 5040
6841 16:59:59.125277 # ok 946 Set VL 5056
6842 16:59:59.125695 # ok 947 # SKIP Disabled ZA for VL 5056
6843 16:59:59.125875 # ok 948 # SKIP Get and set data for VL 5056
6844 16:59:59.126029 # ok 949 Set VL 5072
6845 16:59:59.126193 # ok 950 # SKIP Disabled ZA for VL 5072
6846 16:59:59.126388 # ok 951 # SKIP Get and set data for VL 5072
6847 16:59:59.126565 # ok 952 Set VL 5088
6848 16:59:59.126735 # ok 953 # SKIP Disabled ZA for VL 5088
6849 16:59:59.126892 # ok 954 # SKIP Get and set data for VL 5088
6850 16:59:59.127043 # ok 955 Set VL 5104
6851 16:59:59.127187 # ok 956 # SKIP Disabled ZA for VL 5104
6852 16:59:59.127382 # ok 957 # SKIP Get and set data for VL 5104
6853 16:59:59.127547 # ok 958 Set VL 5120
6854 16:59:59.127739 # ok 959 # SKIP Disabled ZA for VL 5120
6855 16:59:59.127869 # ok 960 # SKIP Get and set data for VL 5120
6856 16:59:59.128028 # ok 961 Set VL 5136
6857 16:59:59.128154 # ok 962 # SKIP Disabled ZA for VL 5136
6858 16:59:59.128271 # ok 963 # SKIP Get and set data for VL 5136
6859 16:59:59.128386 # ok 964 Set VL 5152
6860 16:59:59.128499 # ok 965 # SKIP Disabled ZA for VL 5152
6861 16:59:59.128613 # ok 966 # SKIP Get and set data for VL 5152
6862 16:59:59.128728 # ok 967 Set VL 5168
6863 16:59:59.128843 # ok 968 # SKIP Disabled ZA for VL 5168
6864 16:59:59.128958 # ok 969 # SKIP Get and set data for VL 5168
6865 16:59:59.129071 # ok 970 Set VL 5184
6866 16:59:59.129215 # ok 971 # SKIP Disabled ZA for VL 5184
6867 16:59:59.129339 # ok 972 # SKIP Get and set data for VL 5184
6868 16:59:59.129455 # ok 973 Set VL 5200
6869 16:59:59.129571 # ok 974 # SKIP Disabled ZA for VL 5200
6870 16:59:59.133063 # ok 975 # SKIP Get and set data for VL 5200
6871 16:59:59.133191 # ok 976 Set VL 5216
6872 16:59:59.133296 # ok 977 # SKIP Disabled ZA for VL 5216
6873 16:59:59.133384 # ok 978 # SKIP Get and set data for VL 5216
6874 16:59:59.133463 # ok 979 Set VL 5232
6875 16:59:59.133556 # ok 980 # SKIP Disabled ZA for VL 5232
6876 16:59:59.133631 # ok 981 # SKIP Get and set data for VL 5232
6877 16:59:59.133751 # ok 982 Set VL 5248
6878 16:59:59.133834 # ok 983 # SKIP Disabled ZA for VL 5248
6879 16:59:59.133909 # ok 984 # SKIP Get and set data for VL 5248
6880 16:59:59.134002 # ok 985 Set VL 5264
6881 16:59:59.134101 # ok 986 # SKIP Disabled ZA for VL 5264
6882 16:59:59.134184 # ok 987 # SKIP Get and set data for VL 5264
6883 16:59:59.134265 # ok 988 Set VL 5280
6884 16:59:59.134343 # ok 989 # SKIP Disabled ZA for VL 5280
6885 16:59:59.134434 # ok 990 # SKIP Get and set data for VL 5280
6886 16:59:59.134513 # ok 991 Set VL 5296
6887 16:59:59.134586 # ok 992 # SKIP Disabled ZA for VL 5296
6888 16:59:59.134660 # ok 993 # SKIP Get and set data for VL 5296
6889 16:59:59.134735 # ok 994 Set VL 5312
6890 16:59:59.134827 # ok 995 # SKIP Disabled ZA for VL 5312
6891 16:59:59.134906 # ok 996 # SKIP Get and set data for VL 5312
6892 16:59:59.134982 # ok 997 Set VL 5328
6893 16:59:59.135057 # ok 998 # SKIP Disabled ZA for VL 5328
6894 16:59:59.135148 # ok 999 # SKIP Get and set data for VL 5328
6895 16:59:59.135226 # ok 1000 Set VL 5344
6896 16:59:59.135302 # ok 1001 # SKIP Disabled ZA for VL 5344
6897 16:59:59.135392 # ok 1002 # SKIP Get and set data for VL 5344
6898 16:59:59.135468 # ok 1003 Set VL 5360
6899 16:59:59.135532 # ok 1004 # SKIP Disabled ZA for VL 5360
6900 16:59:59.135607 # ok 1005 # SKIP Get and set data for VL 5360
6901 16:59:59.135671 # ok 1006 Set VL 5376
6902 16:59:59.141160 # ok 1007 # SKIP Disabled ZA for VL 5376
6903 16:59:59.141558 # ok 1008 # SKIP Get and set data for VL 5376
6904 16:59:59.141674 # ok 1009 Set VL 5392
6905 16:59:59.141762 # ok 1010 # SKIP Disabled ZA for VL 5392
6906 16:59:59.141844 # ok 1011 # SKIP Get and set data for VL 5392
6907 16:59:59.141942 # ok 1012 Set VL 5408
6908 16:59:59.142028 # ok 1013 # SKIP Disabled ZA for VL 5408
6909 16:59:59.142111 # ok 1014 # SKIP Get and set data for VL 5408
6910 16:59:59.142193 # ok 1015 Set VL 5424
6911 16:59:59.142294 # ok 1016 # SKIP Disabled ZA for VL 5424
6912 16:59:59.142378 # ok 1017 # SKIP Get and set data for VL 5424
6913 16:59:59.142460 # ok 1018 Set VL 5440
6914 16:59:59.142555 # ok 1019 # SKIP Disabled ZA for VL 5440
6915 16:59:59.142639 # ok 1020 # SKIP Get and set data for VL 5440
6916 16:59:59.142735 # ok 1021 Set VL 5456
6917 16:59:59.142818 # ok 1022 # SKIP Disabled ZA for VL 5456
6918 16:59:59.142914 # ok 1023 # SKIP Get and set data for VL 5456
6919 16:59:59.142998 # ok 1024 Set VL 5472
6920 16:59:59.143092 # ok 1025 # SKIP Disabled ZA for VL 5472
6921 16:59:59.143176 # ok 1026 # SKIP Get and set data for VL 5472
6922 16:59:59.143279 # ok 1027 Set VL 5488
6923 16:59:59.143362 # ok 1028 # SKIP Disabled ZA for VL 5488
6924 16:59:59.143459 # ok 1029 # SKIP Get and set data for VL 5488
6925 16:59:59.143543 # ok 1030 Set VL 5504
6926 16:59:59.143624 # ok 1031 # SKIP Disabled ZA for VL 5504
6927 16:59:59.144060 # ok 1032 # SKIP Get and set data for VL 5504
6928 16:59:59.144365 # ok 1033 Set VL 5520
6929 16:59:59.144473 # ok 1034 # SKIP Disabled ZA for VL 5520
6930 16:59:59.144557 # ok 1035 # SKIP Get and set data for VL 5520
6931 16:59:59.144639 # ok 1036 Set VL 5536
6932 16:59:59.144735 # ok 1037 # SKIP Disabled ZA for VL 5536
6933 16:59:59.144820 # ok 1038 # SKIP Get and set data for VL 5536
6934 16:59:59.144901 # ok 1039 Set VL 5552
6935 16:59:59.144981 # ok 1040 # SKIP Disabled ZA for VL 5552
6936 16:59:59.145076 # ok 1041 # SKIP Get and set data for VL 5552
6937 16:59:59.145161 # ok 1042 Set VL 5568
6938 16:59:59.145242 # ok 1043 # SKIP Disabled ZA for VL 5568
6939 16:59:59.145341 # ok 1044 # SKIP Get and set data for VL 5568
6940 16:59:59.145425 # ok 1045 Set VL 5584
6941 16:59:59.145520 # ok 1046 # SKIP Disabled ZA for VL 5584
6942 16:59:59.145604 # ok 1047 # SKIP Get and set data for VL 5584
6943 16:59:59.145708 # ok 1048 Set VL 5600
6944 16:59:59.145806 # ok 1049 # SKIP Disabled ZA for VL 5600
6945 16:59:59.145890 # ok 1050 # SKIP Get and set data for VL 5600
6946 16:59:59.145986 # ok 1051 Set VL 5616
6947 16:59:59.146069 # ok 1052 # SKIP Disabled ZA for VL 5616
6948 16:59:59.147439 # ok 1053 # SKIP Get and set data for VL 5616
6949 16:59:59.147544 # ok 1054 Set VL 5632
6950 16:59:59.147816 # ok 1055 # SKIP Disabled ZA for VL 5632
6951 16:59:59.153308 # ok 1056 # SKIP Get and set data for VL 5632
6952 16:59:59.153613 # ok 1057 Set VL 5648
6953 16:59:59.153731 # ok 1058 # SKIP Disabled ZA for VL 5648
6954 16:59:59.153863 # ok 1059 # SKIP Get and set data for VL 5648
6955 16:59:59.153976 # ok 1060 Set VL 5664
6956 16:59:59.154086 # ok 1061 # SKIP Disabled ZA for VL 5664
6957 16:59:59.154200 # ok 1062 # SKIP Get and set data for VL 5664
6958 16:59:59.154284 # ok 1063 Set VL 5680
6959 16:59:59.154373 # ok 1064 # SKIP Disabled ZA for VL 5680
6960 16:59:59.154464 # ok 1065 # SKIP Get and set data for VL 5680
6961 16:59:59.154529 # ok 1066 Set VL 5696
6962 16:59:59.154588 # ok 1067 # SKIP Disabled ZA for VL 5696
6963 16:59:59.154669 # ok 1068 # SKIP Get and set data for VL 5696
6964 16:59:59.154740 # ok 1069 Set VL 5712
6965 16:59:59.154824 # ok 1070 # SKIP Disabled ZA for VL 5712
6966 16:59:59.154932 # ok 1071 # SKIP Get and set data for VL 5712
6967 16:59:59.155020 # ok 1072 Set VL 5728
6968 16:59:59.155111 # ok 1073 # SKIP Disabled ZA for VL 5728
6969 16:59:59.155210 # ok 1074 # SKIP Get and set data for VL 5728
6970 16:59:59.155307 # ok 1075 Set VL 5744
6971 16:59:59.155381 # ok 1076 # SKIP Disabled ZA for VL 5744
6972 16:59:59.155457 # ok 1077 # SKIP Get and set data for VL 5744
6973 16:59:59.155524 # ok 1078 Set VL 5760
6974 16:59:59.155598 # ok 1079 # SKIP Disabled ZA for VL 5760
6975 16:59:59.155683 # ok 1080 # SKIP Get and set data for VL 5760
6976 16:59:59.155746 # ok 1081 Set VL 5776
6977 16:59:59.160813 # ok 1082 # SKIP Disabled ZA for VL 5776
6978 16:59:59.161289 # ok 1083 # SKIP Get and set data for VL 5776
6979 16:59:59.161489 # ok 1084 Set VL 5792
6980 16:59:59.161644 # ok 1085 # SKIP Disabled ZA for VL 5792
6981 16:59:59.161849 # ok 1086 # SKIP Get and set data for VL 5792
6982 16:59:59.162049 # ok 1087 Set VL 5808
6983 16:59:59.162243 # ok 1088 # SKIP Disabled ZA for VL 5808
6984 16:59:59.162383 # ok 1089 # SKIP Get and set data for VL 5808
6985 16:59:59.162528 # ok 1090 Set VL 5824
6986 16:59:59.162669 # ok 1091 # SKIP Disabled ZA for VL 5824
6987 16:59:59.162811 # ok 1092 # SKIP Get and set data for VL 5824
6988 16:59:59.162953 # ok 1093 Set VL 5840
6989 16:59:59.163093 # ok 1094 # SKIP Disabled ZA for VL 5840
6990 16:59:59.163234 # ok 1095 # SKIP Get and set data for VL 5840
6991 16:59:59.163376 # ok 1096 Set VL 5856
6992 16:59:59.163525 # ok 1097 # SKIP Disabled ZA for VL 5856
6993 16:59:59.163686 # ok 1098 # SKIP Get and set data for VL 5856
6994 16:59:59.163838 # ok 1099 Set VL 5872
6995 16:59:59.163979 # ok 1100 # SKIP Disabled ZA for VL 5872
6996 16:59:59.164098 # ok 1101 # SKIP Get and set data for VL 5872
6997 16:59:59.164215 # ok 1102 Set VL 5888
6998 16:59:59.164333 # ok 1103 # SKIP Disabled ZA for VL 5888
6999 16:59:59.164448 # ok 1104 # SKIP Get and set data for VL 5888
7000 16:59:59.164565 # ok 1105 Set VL 5904
7001 16:59:59.164680 # ok 1106 # SKIP Disabled ZA for VL 5904
7002 16:59:59.164797 # ok 1107 # SKIP Get and set data for VL 5904
7003 16:59:59.164915 # ok 1108 Set VL 5920
7004 16:59:59.165031 # ok 1109 # SKIP Disabled ZA for VL 5920
7005 16:59:59.165148 # ok 1110 # SKIP Get and set data for VL 5920
7006 16:59:59.165266 # ok 1111 Set VL 5936
7007 16:59:59.167060 # ok 1112 # SKIP Disabled ZA for VL 5936
7008 16:59:59.167395 # ok 1113 # SKIP Get and set data for VL 5936
7009 16:59:59.167530 # ok 1114 Set VL 5952
7010 16:59:59.167683 # ok 1115 # SKIP Disabled ZA for VL 5952
7011 16:59:59.167807 # ok 1116 # SKIP Get and set data for VL 5952
7012 16:59:59.168715 # ok 1117 Set VL 5968
7013 16:59:59.169049 # ok 1118 # SKIP Disabled ZA for VL 5968
7014 16:59:59.169177 # ok 1119 # SKIP Get and set data for VL 5968
7015 16:59:59.169315 # ok 1120 Set VL 5984
7016 16:59:59.169438 # ok 1121 # SKIP Disabled ZA for VL 5984
7017 16:59:59.169578 # ok 1122 # SKIP Get and set data for VL 5984
7018 16:59:59.169716 # ok 1123 Set VL 6000
7019 16:59:59.169859 # ok 1124 # SKIP Disabled ZA for VL 6000
7020 16:59:59.169981 # ok 1125 # SKIP Get and set data for VL 6000
7021 16:59:59.170154 # ok 1126 Set VL 6016
7022 16:59:59.170350 # ok 1127 # SKIP Disabled ZA for VL 6016
7023 16:59:59.170495 # ok 1128 # SKIP Get and set data for VL 6016
7024 16:59:59.170631 # ok 1129 Set VL 6032
7025 16:59:59.170771 # ok 1130 # SKIP Disabled ZA for VL 6032
7026 16:59:59.170914 # ok 1131 # SKIP Get and set data for VL 6032
7027 16:59:59.171074 # ok 1132 Set VL 6048
7028 16:59:59.171258 # ok 1133 # SKIP Disabled ZA for VL 6048
7029 16:59:59.171412 # ok 1134 # SKIP Get and set data for VL 6048
7030 16:59:59.171610 # ok 1135 Set VL 6064
7031 16:59:59.171779 # ok 1136 # SKIP Disabled ZA for VL 6064
7032 16:59:59.171917 # ok 1137 # SKIP Get and set data for VL 6064
7033 16:59:59.172037 # ok 1138 Set VL 6080
7034 16:59:59.172152 # ok 1139 # SKIP Disabled ZA for VL 6080
7035 16:59:59.172268 # ok 1140 # SKIP Get and set data for VL 6080
7036 16:59:59.172414 # ok 1141 Set VL 6096
7037 16:59:59.172539 # ok 1142 # SKIP Disabled ZA for VL 6096
7038 16:59:59.172659 # ok 1143 # SKIP Get and set data for VL 6096
7039 16:59:59.172775 # ok 1144 Set VL 6112
7040 16:59:59.172892 # ok 1145 # SKIP Disabled ZA for VL 6112
7041 16:59:59.176442 # ok 1146 # SKIP Get and set data for VL 6112
7042 16:59:59.176872 # ok 1147 Set VL 6128
7043 16:59:59.177040 # ok 1148 # SKIP Disabled ZA for VL 6128
7044 16:59:59.177226 # ok 1149 # SKIP Get and set data for VL 6128
7045 16:59:59.177387 # ok 1150 Set VL 6144
7046 16:59:59.177517 # ok 1151 # SKIP Disabled ZA for VL 6144
7047 16:59:59.177688 # ok 1152 # SKIP Get and set data for VL 6144
7048 16:59:59.177826 # ok 1153 Set VL 6160
7049 16:59:59.177953 # ok 1154 # SKIP Disabled ZA for VL 6160
7050 16:59:59.178079 # ok 1155 # SKIP Get and set data for VL 6160
7051 16:59:59.178207 # ok 1156 Set VL 6176
7052 16:59:59.178335 # ok 1157 # SKIP Disabled ZA for VL 6176
7053 16:59:59.178461 # ok 1158 # SKIP Get and set data for VL 6176
7054 16:59:59.178585 # ok 1159 Set VL 6192
7055 16:59:59.178709 # ok 1160 # SKIP Disabled ZA for VL 6192
7056 16:59:59.178866 # ok 1161 # SKIP Get and set data for VL 6192
7057 16:59:59.178995 # ok 1162 Set VL 6208
7058 16:59:59.179123 # ok 1163 # SKIP Disabled ZA for VL 6208
7059 16:59:59.179246 # ok 1164 # SKIP Get and set data for VL 6208
7060 16:59:59.179374 # ok 1165 Set VL 6224
7061 16:59:59.179509 # ok 1166 # SKIP Disabled ZA for VL 6224
7062 16:59:59.179673 # ok 1167 # SKIP Get and set data for VL 6224
7063 16:59:59.179794 # ok 1168 Set VL 6240
7064 16:59:59.179923 # ok 1169 # SKIP Disabled ZA for VL 6240
7065 16:59:59.180041 # ok 1170 # SKIP Get and set data for VL 6240
7066 16:59:59.180159 # ok 1171 Set VL 6256
7067 16:59:59.180274 # ok 1172 # SKIP Disabled ZA for VL 6256
7068 16:59:59.180418 # ok 1173 # SKIP Get and set data for VL 6256
7069 16:59:59.180543 # ok 1174 Set VL 6272
7070 16:59:59.180662 # ok 1175 # SKIP Disabled ZA for VL 6272
7071 16:59:59.180779 # ok 1176 # SKIP Get and set data for VL 6272
7072 16:59:59.180896 # ok 1177 Set VL 6288
7073 16:59:59.181011 # ok 1178 # SKIP Disabled ZA for VL 6288
7074 16:59:59.181126 # ok 1179 # SKIP Get and set data for VL 6288
7075 16:59:59.181241 # ok 1180 Set VL 6304
7076 16:59:59.181356 # ok 1181 # SKIP Disabled ZA for VL 6304
7077 16:59:59.187059 # ok 1182 # SKIP Get and set data for VL 6304
7078 16:59:59.187504 # ok 1183 Set VL 6320
7079 16:59:59.187686 # ok 1184 # SKIP Disabled ZA for VL 6320
7080 16:59:59.187815 # ok 1185 # SKIP Get and set data for VL 6320
7081 16:59:59.187939 # ok 1186 Set VL 6336
7082 16:59:59.188089 # ok 1187 # SKIP Disabled ZA for VL 6336
7083 16:59:59.188311 # ok 1188 # SKIP Get and set data for VL 6336
7084 16:59:59.188483 # ok 1189 Set VL 6352
7085 16:59:59.188654 # ok 1190 # SKIP Disabled ZA for VL 6352
7086 16:59:59.188804 # ok 1191 # SKIP Get and set data for VL 6352
7087 16:59:59.188942 # ok 1192 Set VL 6368
7088 16:59:59.189160 # ok 1193 # SKIP Disabled ZA for VL 6368
7089 16:59:59.189355 # ok 1194 # SKIP Get and set data for VL 6368
7090 16:59:59.189522 # ok 1195 Set VL 6384
7091 16:59:59.189699 # ok 1196 # SKIP Disabled ZA for VL 6384
7092 16:59:59.189849 # ok 1197 # SKIP Get and set data for VL 6384
7093 16:59:59.190011 # ok 1198 Set VL 6400
7094 16:59:59.190175 # ok 1199 # SKIP Disabled ZA for VL 6400
7095 16:59:59.190338 # ok 1200 # SKIP Get and set data for VL 6400
7096 16:59:59.190532 # ok 1201 Set VL 6416
7097 16:59:59.190683 # ok 1202 # SKIP Disabled ZA for VL 6416
7098 16:59:59.190872 # ok 1203 # SKIP Get and set data for VL 6416
7099 16:59:59.191065 # ok 1204 Set VL 6432
7100 16:59:59.191250 # ok 1205 # SKIP Disabled ZA for VL 6432
7101 16:59:59.191420 # ok 1206 # SKIP Get and set data for VL 6432
7102 16:59:59.191615 # ok 1207 Set VL 6448
7103 16:59:59.191776 # ok 1208 # SKIP Disabled ZA for VL 6448
7104 16:59:59.191896 # ok 1209 # SKIP Get and set data for VL 6448
7105 16:59:59.192010 # ok 1210 Set VL 6464
7106 16:59:59.192122 # ok 1211 # SKIP Disabled ZA for VL 6464
7107 16:59:59.192235 # ok 1212 # SKIP Get and set data for VL 6464
7108 16:59:59.192350 # ok 1213 Set VL 6480
7109 16:59:59.192461 # ok 1214 # SKIP Disabled ZA for VL 6480
7110 16:59:59.192573 # ok 1215 # SKIP Get and set data for VL 6480
7111 16:59:59.192684 # ok 1216 Set VL 6496
7112 16:59:59.192795 # ok 1217 # SKIP Disabled ZA for VL 6496
7113 16:59:59.192907 # ok 1218 # SKIP Get and set data for VL 6496
7114 16:59:59.193019 # ok 1219 Set VL 6512
7115 16:59:59.193131 # ok 1220 # SKIP Disabled ZA for VL 6512
7116 16:59:59.193243 # ok 1221 # SKIP Get and set data for VL 6512
7117 16:59:59.193355 # ok 1222 Set VL 6528
7118 16:59:59.193466 # ok 1223 # SKIP Disabled ZA for VL 6528
7119 16:59:59.193607 # ok 1224 # SKIP Get and set data for VL 6528
7120 16:59:59.193842 # ok 1225 Set VL 6544
7121 16:59:59.194035 # ok 1226 # SKIP Disabled ZA for VL 6544
7122 16:59:59.194222 # ok 1227 # SKIP Get and set data for VL 6544
7123 16:59:59.194405 # ok 1228 Set VL 6560
7124 16:59:59.194586 # ok 1229 # SKIP Disabled ZA for VL 6560
7125 16:59:59.194768 # ok 1230 # SKIP Get and set data for VL 6560
7126 16:59:59.194951 # ok 1231 Set VL 6576
7127 16:59:59.197000 # ok 1232 # SKIP Disabled ZA for VL 6576
7128 16:59:59.197445 # ok 1233 # SKIP Get and set data for VL 6576
7129 16:59:59.197639 # ok 1234 Set VL 6592
7130 16:59:59.197832 # ok 1235 # SKIP Disabled ZA for VL 6592
7131 16:59:59.198022 # ok 1236 # SKIP Get and set data for VL 6592
7132 16:59:59.198223 # ok 1237 Set VL 6608
7133 16:59:59.198383 # ok 1238 # SKIP Disabled ZA for VL 6608
7134 16:59:59.198616 # ok 1239 # SKIP Get and set data for VL 6608
7135 16:59:59.198816 # ok 1240 Set VL 6624
7136 16:59:59.198962 # ok 1241 # SKIP Disabled ZA for VL 6624
7137 16:59:59.199130 # ok 1242 # SKIP Get and set data for VL 6624
7138 16:59:59.199303 # ok 1243 Set VL 6640
7139 16:59:59.199534 # ok 1244 # SKIP Disabled ZA for VL 6640
7140 16:59:59.199747 # ok 1245 # SKIP Get and set data for VL 6640
7141 16:59:59.199888 # ok 1246 Set VL 6656
7142 16:59:59.200041 # ok 1247 # SKIP Disabled ZA for VL 6656
7143 16:59:59.200173 # ok 1248 # SKIP Get and set data for VL 6656
7144 16:59:59.200288 # ok 1249 Set VL 6672
7145 16:59:59.200403 # ok 1250 # SKIP Disabled ZA for VL 6672
7146 16:59:59.200516 # ok 1251 # SKIP Get and set data for VL 6672
7147 16:59:59.200659 # ok 1252 Set VL 6688
7148 16:59:59.200779 # ok 1253 # SKIP Disabled ZA for VL 6688
7149 16:59:59.200894 # ok 1254 # SKIP Get and set data for VL 6688
7150 16:59:59.201007 # ok 1255 Set VL 6704
7151 16:59:59.201120 # ok 1256 # SKIP Disabled ZA for VL 6704
7152 16:59:59.201232 # ok 1257 # SKIP Get and set data for VL 6704
7153 16:59:59.201403 # ok 1258 Set VL 6720
7154 16:59:59.201573 # ok 1259 # SKIP Disabled ZA for VL 6720
7155 16:59:59.201774 # ok 1260 # SKIP Get and set data for VL 6720
7156 16:59:59.201971 # ok 1261 Set VL 6736
7157 16:59:59.202152 # ok 1262 # SKIP Disabled ZA for VL 6736
7158 16:59:59.202332 # ok 1263 # SKIP Get and set data for VL 6736
7159 16:59:59.212860 # ok 1264 Set VL 6752
7160 16:59:59.213311 # ok 1265 # SKIP Disabled ZA for VL 6752
7161 16:59:59.213519 # ok 1266 # SKIP Get and set data for VL 6752
7162 16:59:59.213748 # ok 1267 Set VL 6768
7163 16:59:59.213956 # ok 1268 # SKIP Disabled ZA for VL 6768
7164 16:59:59.214127 # ok 1269 # SKIP Get and set data for VL 6768
7165 16:59:59.214309 # ok 1270 Set VL 6784
7166 16:59:59.214450 # ok 1271 # SKIP Disabled ZA for VL 6784
7167 16:59:59.214592 # ok 1272 # SKIP Get and set data for VL 6784
7168 16:59:59.214733 # ok 1273 Set VL 6800
7169 16:59:59.214927 # ok 1274 # SKIP Disabled ZA for VL 6800
7170 16:59:59.215099 # ok 1275 # SKIP Get and set data for VL 6800
7171 16:59:59.215257 # ok 1276 Set VL 6816
7172 16:59:59.215422 # ok 1277 # SKIP Disabled ZA for VL 6816
7173 16:59:59.215649 # ok 1278 # SKIP Get and set data for VL 6816
7174 16:59:59.215793 # ok 1279 Set VL 6832
7175 16:59:59.215910 # ok 1280 # SKIP Disabled ZA for VL 6832
7176 16:59:59.216023 # ok 1281 # SKIP Get and set data for VL 6832
7177 16:59:59.216137 # ok 1282 Set VL 6848
7178 16:59:59.216248 # ok 1283 # SKIP Disabled ZA for VL 6848
7179 16:59:59.216363 # ok 1284 # SKIP Get and set data for VL 6848
7180 16:59:59.216478 # ok 1285 Set VL 6864
7181 16:59:59.216592 # ok 1286 # SKIP Disabled ZA for VL 6864
7182 16:59:59.224922 # ok 1287 # SKIP Get and set data for VL 6864
7183 16:59:59.225030 # ok 1288 Set VL 6880
7184 16:59:59.225129 # ok 1289 # SKIP Disabled ZA for VL 6880
7185 16:59:59.225216 # ok 1290 # SKIP Get and set data for VL 6880
7186 16:59:59.225313 # ok 1291 Set VL 6896
7187 16:59:59.225397 # ok 1292 # SKIP Disabled ZA for VL 6896
7188 16:59:59.225491 # ok 1293 # SKIP Get and set data for VL 6896
7189 16:59:59.225573 # ok 1294 Set VL 6912
7190 16:59:59.225661 # ok 1295 # SKIP Disabled ZA for VL 6912
7191 16:59:59.225741 # ok 1296 # SKIP Get and set data for VL 6912
7192 16:59:59.225835 # ok 1297 Set VL 6928
7193 16:59:59.225917 # ok 1298 # SKIP Disabled ZA for VL 6928
7194 16:59:59.225995 # ok 1299 # SKIP Get and set data for VL 6928
7195 16:59:59.226089 # ok 1300 Set VL 6944
7196 16:59:59.226172 # ok 1301 # SKIP Disabled ZA for VL 6944
7197 16:59:59.226252 # ok 1302 # SKIP Get and set data for VL 6944
7198 16:59:59.226331 # ok 1303 Set VL 6960
7199 16:59:59.226425 # ok 1304 # SKIP Disabled ZA for VL 6960
7200 16:59:59.226508 # ok 1305 # SKIP Get and set data for VL 6960
7201 16:59:59.226588 # ok 1306 Set VL 6976
7202 16:59:59.226667 # ok 1307 # SKIP Disabled ZA for VL 6976
7203 16:59:59.226761 # ok 1308 # SKIP Get and set data for VL 6976
7204 16:59:59.226843 # ok 1309 Set VL 6992
7205 16:59:59.226923 # ok 1310 # SKIP Disabled ZA for VL 6992
7206 16:59:59.227002 # ok 1311 # SKIP Get and set data for VL 6992
7207 16:59:59.227096 # ok 1312 Set VL 7008
7208 16:59:59.227178 # ok 1313 # SKIP Disabled ZA for VL 7008
7209 16:59:59.227257 # ok 1314 # SKIP Get and set data for VL 7008
7210 16:59:59.227336 # ok 1315 Set VL 7024
7211 16:59:59.227434 # ok 1316 # SKIP Disabled ZA for VL 7024
7212 16:59:59.227516 # ok 1317 # SKIP Get and set data for VL 7024
7213 16:59:59.227596 # ok 1318 Set VL 7040
7214 16:59:59.227675 # ok 1319 # SKIP Disabled ZA for VL 7040
7215 16:59:59.227768 # ok 1320 # SKIP Get and set data for VL 7040
7216 16:59:59.227850 # ok 1321 Set VL 7056
7217 16:59:59.236512 # ok 1322 # SKIP Disabled ZA for VL 7056
7218 16:59:59.236922 # ok 1323 # SKIP Get and set data for VL 7056
7219 16:59:59.237028 # ok 1324 Set VL 7072
7220 16:59:59.237111 # ok 1325 # SKIP Disabled ZA for VL 7072
7221 16:59:59.237192 # ok 1326 # SKIP Get and set data for VL 7072
7222 16:59:59.237271 # ok 1327 Set VL 7088
7223 16:59:59.237349 # ok 1328 # SKIP Disabled ZA for VL 7088
7224 16:59:59.237445 # ok 1329 # SKIP Get and set data for VL 7088
7225 16:59:59.237527 # ok 1330 Set VL 7104
7226 16:59:59.237606 # ok 1331 # SKIP Disabled ZA for VL 7104
7227 16:59:59.237694 # ok 1332 # SKIP Get and set data for VL 7104
7228 16:59:59.237774 # ok 1333 Set VL 7120
7229 16:59:59.237868 # ok 1334 # SKIP Disabled ZA for VL 7120
7230 16:59:59.237951 # ok 1335 # SKIP Get and set data for VL 7120
7231 16:59:59.238033 # ok 1336 Set VL 7136
7232 16:59:59.238113 # ok 1337 # SKIP Disabled ZA for VL 7136
7233 16:59:59.238211 # ok 1338 # SKIP Get and set data for VL 7136
7234 16:59:59.238293 # ok 1339 Set VL 7152
7235 16:59:59.238373 # ok 1340 # SKIP Disabled ZA for VL 7152
7236 16:59:59.238451 # ok 1341 # SKIP Get and set data for VL 7152
7237 16:59:59.238545 # ok 1342 Set VL 7168
7238 16:59:59.238627 # ok 1343 # SKIP Disabled ZA for VL 7168
7239 16:59:59.238707 # ok 1344 # SKIP Get and set data for VL 7168
7240 16:59:59.238786 # ok 1345 Set VL 7184
7241 16:59:59.238880 # ok 1346 # SKIP Disabled ZA for VL 7184
7242 16:59:59.238963 # ok 1347 # SKIP Get and set data for VL 7184
7243 16:59:59.239043 # ok 1348 Set VL 7200
7244 16:59:59.239122 # ok 1349 # SKIP Disabled ZA for VL 7200
7245 16:59:59.239216 # ok 1350 # SKIP Get and set data for VL 7200
7246 16:59:59.239299 # ok 1351 Set VL 7216
7247 16:59:59.239378 # ok 1352 # SKIP Disabled ZA for VL 7216
7248 16:59:59.239462 # ok 1353 # SKIP Get and set data for VL 7216
7249 16:59:59.239542 # ok 1354 Set VL 7232
7250 16:59:59.239635 # ok 1355 # SKIP Disabled ZA for VL 7232
7251 16:59:59.239718 # ok 1356 # SKIP Get and set data for VL 7232
7252 16:59:59.239797 # ok 1357 Set VL 7248
7253 16:59:59.248813 # ok 1358 # SKIP Disabled ZA for VL 7248
7254 16:59:59.249272 # ok 1359 # SKIP Get and set data for VL 7248
7255 16:59:59.249487 # ok 1360 Set VL 7264
7256 16:59:59.249684 # ok 1361 # SKIP Disabled ZA for VL 7264
7257 16:59:59.249840 # ok 1362 # SKIP Get and set data for VL 7264
7258 16:59:59.250029 # ok 1363 Set VL 7280
7259 16:59:59.250181 # ok 1364 # SKIP Disabled ZA for VL 7280
7260 16:59:59.250396 # ok 1365 # SKIP Get and set data for VL 7280
7261 16:59:59.250590 # ok 1366 Set VL 7296
7262 16:59:59.250761 # ok 1367 # SKIP Disabled ZA for VL 7296
7263 16:59:59.250926 # ok 1368 # SKIP Get and set data for VL 7296
7264 16:59:59.251071 # ok 1369 Set VL 7312
7265 16:59:59.251188 # ok 1370 # SKIP Disabled ZA for VL 7312
7266 16:59:59.251301 # ok 1371 # SKIP Get and set data for VL 7312
7267 16:59:59.251415 # ok 1372 Set VL 7328
7268 16:59:59.251529 # ok 1373 # SKIP Disabled ZA for VL 7328
7269 16:59:59.251642 # ok 1374 # SKIP Get and set data for VL 7328
7270 16:59:59.251756 # ok 1375 Set VL 7344
7271 16:59:59.251898 # ok 1376 # SKIP Disabled ZA for VL 7344
7272 16:59:59.252020 # ok 1377 # SKIP Get and set data for VL 7344
7273 16:59:59.252136 # ok 1378 Set VL 7360
7274 16:59:59.252250 # ok 1379 # SKIP Disabled ZA for VL 7360
7275 16:59:59.252363 # ok 1380 # SKIP Get and set data for VL 7360
7276 16:59:59.252475 # ok 1381 Set VL 7376
7277 16:59:59.252587 # ok 1382 # SKIP Disabled ZA for VL 7376
7278 16:59:59.252699 # ok 1383 # SKIP Get and set data for VL 7376
7279 16:59:59.252812 # ok 1384 Set VL 7392
7280 16:59:59.256825 # ok 1385 # SKIP Disabled ZA for VL 7392
7281 16:59:59.257024 # ok 1386 # SKIP Get and set data for VL 7392
7282 16:59:59.257253 # ok 1387 Set VL 7408
7283 16:59:59.257438 # ok 1388 # SKIP Disabled ZA for VL 7408
7284 16:59:59.257595 # ok 1389 # SKIP Get and set data for VL 7408
7285 16:59:59.257768 # ok 1390 Set VL 7424
7286 16:59:59.257941 # ok 1391 # SKIP Disabled ZA for VL 7424
7287 16:59:59.258145 # ok 1392 # SKIP Get and set data for VL 7424
7288 16:59:59.258328 # ok 1393 Set VL 7440
7289 16:59:59.258483 # ok 1394 # SKIP Disabled ZA for VL 7440
7290 16:59:59.258640 # ok 1395 # SKIP Get and set data for VL 7440
7291 16:59:59.258789 # ok 1396 Set VL 7456
7292 16:59:59.258932 # ok 1397 # SKIP Disabled ZA for VL 7456
7293 16:59:59.259105 # ok 1398 # SKIP Get and set data for VL 7456
7294 16:59:59.259297 # ok 1399 Set VL 7472
7295 16:59:59.259514 # ok 1400 # SKIP Disabled ZA for VL 7472
7296 16:59:59.259700 # ok 1401 # SKIP Get and set data for VL 7472
7297 16:59:59.259885 # ok 1402 Set VL 7488
7298 16:59:59.260076 # ok 1403 # SKIP Disabled ZA for VL 7488
7299 16:59:59.260214 # ok 1404 # SKIP Get and set data for VL 7488
7300 16:59:59.260355 # ok 1405 Set VL 7504
7301 16:59:59.260498 # ok 1406 # SKIP Disabled ZA for VL 7504
7302 16:59:59.260638 # ok 1407 # SKIP Get and set data for VL 7504
7303 16:59:59.260779 # ok 1408 Set VL 7520
7304 16:59:59.260921 # ok 1409 # SKIP Disabled ZA for VL 7520
7305 16:59:59.261062 # ok 1410 # SKIP Get and set data for VL 7520
7306 16:59:59.261202 # ok 1411 Set VL 7536
7307 16:59:59.261343 # ok 1412 # SKIP Disabled ZA for VL 7536
7308 16:59:59.261483 # ok 1413 # SKIP Get and set data for VL 7536
7309 16:59:59.261623 # ok 1414 Set VL 7552
7310 16:59:59.261775 # ok 1415 # SKIP Disabled ZA for VL 7552
7311 16:59:59.261915 # ok 1416 # SKIP Get and set data for VL 7552
7312 16:59:59.262056 # ok 1417 Set VL 7568
7313 16:59:59.262196 # ok 1418 # SKIP Disabled ZA for VL 7568
7314 16:59:59.262335 # ok 1419 # SKIP Get and set data for VL 7568
7315 16:59:59.269033 # ok 1420 Set VL 7584
7316 16:59:59.269236 # ok 1421 # SKIP Disabled ZA for VL 7584
7317 16:59:59.269431 # ok 1422 # SKIP Get and set data for VL 7584
7318 16:59:59.269589 # ok 1423 Set VL 7600
7319 16:59:59.269765 # ok 1424 # SKIP Disabled ZA for VL 7600
7320 16:59:59.269974 # ok 1425 # SKIP Get and set data for VL 7600
7321 16:59:59.270152 # ok 1426 Set VL 7616
7322 16:59:59.270324 # ok 1427 # SKIP Disabled ZA for VL 7616
7323 16:59:59.270484 # ok 1428 # SKIP Get and set data for VL 7616
7324 16:59:59.270648 # ok 1429 Set VL 7632
7325 16:59:59.270853 # ok 1430 # SKIP Disabled ZA for VL 7632
7326 16:59:59.271041 # ok 1431 # SKIP Get and set data for VL 7632
7327 16:59:59.271272 # ok 1432 Set VL 7648
7328 16:59:59.271493 # ok 1433 # SKIP Disabled ZA for VL 7648
7329 16:59:59.271678 # ok 1434 # SKIP Get and set data for VL 7648
7330 16:59:59.271807 # ok 1435 Set VL 7664
7331 16:59:59.271921 # ok 1436 # SKIP Disabled ZA for VL 7664
7332 16:59:59.272069 # ok 1437 # SKIP Get and set data for VL 7664
7333 16:59:59.272191 # ok 1438 Set VL 7680
7334 16:59:59.272304 # ok 1439 # SKIP Disabled ZA for VL 7680
7335 16:59:59.272419 # ok 1440 # SKIP Get and set data for VL 7680
7336 16:59:59.272533 # ok 1441 Set VL 7696
7337 16:59:59.272645 # ok 1442 # SKIP Disabled ZA for VL 7696
7338 16:59:59.272758 # ok 1443 # SKIP Get and set data for VL 7696
7339 16:59:59.272868 # ok 1444 Set VL 7712
7340 16:59:59.272979 # ok 1445 # SKIP Disabled ZA for VL 7712
7341 16:59:59.273092 # ok 1446 # SKIP Get and set data for VL 7712
7342 16:59:59.273204 # ok 1447 Set VL 7728
7343 16:59:59.273315 # ok 1448 # SKIP Disabled ZA for VL 7728
7344 16:59:59.273427 # ok 1449 # SKIP Get and set data for VL 7728
7345 16:59:59.273539 # ok 1450 Set VL 7744
7346 16:59:59.273682 # ok 1451 # SKIP Disabled ZA for VL 7744
7347 16:59:59.273897 # ok 1452 # SKIP Get and set data for VL 7744
7348 16:59:59.274082 # ok 1453 Set VL 7760
7349 16:59:59.274264 # ok 1454 # SKIP Disabled ZA for VL 7760
7350 16:59:59.274444 # ok 1455 # SKIP Get and set data for VL 7760
7351 16:59:59.274627 # ok 1456 Set VL 7776
7352 16:59:59.277005 # ok 1457 # SKIP Disabled ZA for VL 7776
7353 16:59:59.277443 # ok 1458 # SKIP Get and set data for VL 7776
7354 16:59:59.277543 # ok 1459 Set VL 7792
7355 16:59:59.277632 # ok 1460 # SKIP Disabled ZA for VL 7792
7356 16:59:59.277781 # ok 1461 # SKIP Get and set data for VL 7792
7357 16:59:59.277868 # ok 1462 Set VL 7808
7358 16:59:59.277972 # ok 1463 # SKIP Disabled ZA for VL 7808
7359 16:59:59.278064 # ok 1464 # SKIP Get and set data for VL 7808
7360 16:59:59.278149 # ok 1465 Set VL 7824
7361 16:59:59.278231 # ok 1466 # SKIP Disabled ZA for VL 7824
7362 16:59:59.278329 # ok 1467 # SKIP Get and set data for VL 7824
7363 16:59:59.278416 # ok 1468 Set VL 7840
7364 16:59:59.278497 # ok 1469 # SKIP Disabled ZA for VL 7840
7365 16:59:59.278586 # ok 1470 # SKIP Get and set data for VL 7840
7366 16:59:59.278668 # ok 1471 Set VL 7856
7367 16:59:59.278765 # ok 1472 # SKIP Disabled ZA for VL 7856
7368 16:59:59.278850 # ok 1473 # SKIP Get and set data for VL 7856
7369 16:59:59.278933 # ok 1474 Set VL 7872
7370 16:59:59.279031 # ok 1475 # SKIP Disabled ZA for VL 7872
7371 16:59:59.279118 # ok 1476 # SKIP Get and set data for VL 7872
7372 16:59:59.279217 # ok 1477 Set VL 7888
7373 16:59:59.279302 # ok 1478 # SKIP Disabled ZA for VL 7888
7374 16:59:59.279399 # ok 1479 # SKIP Get and set data for VL 7888
7375 16:59:59.279483 # ok 1480 Set VL 7904
7376 16:59:59.279585 # ok 1481 # SKIP Disabled ZA for VL 7904
7377 16:59:59.297340 # ok 1482 # SKIP Get and set data for VL 7904
7378 16:59:59.297938 # ok 1483 Set VL 7920
7379 16:59:59.298126 # ok 1484 # SKIP Disabled ZA for VL 7920
7380 16:59:59.298339 # ok 1485 # SKIP Get and set data for VL 7920
7381 16:59:59.298534 # ok 1486 Set VL 7936
7382 16:59:59.298708 # ok 1487 # SKIP Disabled ZA for VL 7936
7383 16:59:59.298909 # ok 1488 # SKIP Get and set data for VL 7936
7384 16:59:59.299109 # ok 1489 Set VL 7952
7385 16:59:59.299358 # ok 1490 # SKIP Disabled ZA for VL 7952
7386 16:59:59.299521 # ok 1491 # SKIP Get and set data for VL 7952
7387 16:59:59.299673 # ok 1492 Set VL 7968
7388 16:59:59.299816 # ok 1493 # SKIP Disabled ZA for VL 7968
7389 16:59:59.299959 # ok 1494 # SKIP Get and set data for VL 7968
7390 16:59:59.300101 # ok 1495 Set VL 7984
7391 16:59:59.300242 # ok 1496 # SKIP Disabled ZA for VL 7984
7392 16:59:59.300386 # ok 1497 # SKIP Get and set data for VL 7984
7393 16:59:59.300527 # ok 1498 Set VL 8000
7394 16:59:59.300726 # ok 1499 # SKIP Disabled ZA for VL 8000
7395 16:59:59.300945 # ok 1500 # SKIP Get and set data for VL 8000
7396 16:59:59.301117 # ok 1501 Set VL 8016
7397 16:59:59.301262 # ok 1502 # SKIP Disabled ZA for VL 8016
7398 16:59:59.301474 # ok 1503 # SKIP Get and set data for VL 8016
7399 16:59:59.301663 # ok 1504 Set VL 8032
7400 16:59:59.301838 # ok 1505 # SKIP Disabled ZA for VL 8032
7401 16:59:59.302031 # ok 1506 # SKIP Get and set data for VL 8032
7402 16:59:59.302192 # ok 1507 Set VL 8048
7403 16:59:59.302339 # ok 1508 # SKIP Disabled ZA for VL 8048
7404 16:59:59.302460 # ok 1509 # SKIP Get and set data for VL 8048
7405 16:59:59.302575 # ok 1510 Set VL 8064
7406 16:59:59.302697 # ok 1511 # SKIP Disabled ZA for VL 8064
7407 16:59:59.302888 # ok 1512 # SKIP Get and set data for VL 8064
7408 16:59:59.303027 # ok 1513 Set VL 8080
7409 16:59:59.303156 # ok 1514 # SKIP Disabled ZA for VL 8080
7410 16:59:59.303292 # ok 1515 # SKIP Get and set data for VL 8080
7411 16:59:59.303493 # ok 1516 Set VL 8096
7412 16:59:59.303650 # ok 1517 # SKIP Disabled ZA for VL 8096
7413 16:59:59.303807 # ok 1518 # SKIP Get and set data for VL 8096
7414 16:59:59.303976 # ok 1519 Set VL 8112
7415 16:59:59.304138 # ok 1520 # SKIP Disabled ZA for VL 8112
7416 16:59:59.304351 # ok 1521 # SKIP Get and set data for VL 8112
7417 16:59:59.304494 # ok 1522 Set VL 8128
7418 16:59:59.304612 # ok 1523 # SKIP Disabled ZA for VL 8128
7419 16:59:59.304725 # ok 1524 # SKIP Get and set data for VL 8128
7420 16:59:59.304839 # ok 1525 Set VL 8144
7421 16:59:59.304953 # ok 1526 # SKIP Disabled ZA for VL 8144
7422 16:59:59.305068 # ok 1527 # SKIP Get and set data for VL 8144
7423 16:59:59.305212 # ok 1528 Set VL 8160
7424 16:59:59.305335 # ok 1529 # SKIP Disabled ZA for VL 8160
7425 16:59:59.305452 # ok 1530 # SKIP Get and set data for VL 8160
7426 16:59:59.305570 # ok 1531 Set VL 8176
7427 16:59:59.305746 # ok 1532 # SKIP Disabled ZA for VL 8176
7428 16:59:59.305952 # ok 1533 # SKIP Get and set data for VL 8176
7429 16:59:59.306136 # ok 1534 Set VL 8192
7430 16:59:59.306562 # ok 1535 # SKIP Disabled ZA for VL 8192
7431 16:59:59.306707 # ok 1536 # SKIP Get and set data for VL 8192
7432 16:59:59.306853 # # Totals: pass:522 fail:0 xfail:0 xpass:0 skip:1014 error:0
7433 16:59:59.306997 ok 34 selftests: arm64: za-ptrace
7434 16:59:59.307140 # selftests: arm64: check_buffer_fill
7435 16:59:59.649557 # 1..20
7436 16:59:59.649884 # ok 1 Check buffer correctness by byte with sync err mode and mmap memory
7437 16:59:59.650101 # ok 2 Check buffer correctness by byte with async err mode and mmap memory
7438 16:59:59.650299 # ok 3 Check buffer correctness by byte with sync err mode and mmap/mprotect memory
7439 16:59:59.650730 # ok 4 Check buffer correctness by byte with async err mode and mmap/mprotect memory
7440 16:59:59.650931 # not ok 5 Check buffer write underflow by byte with sync mode and mmap memory
7441 16:59:59.651102 # not ok 6 Check buffer write underflow by byte with async mode and mmap memory
7442 16:59:59.651245 # ok 7 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7443 16:59:59.651379 # ok 8 Check buffer write underflow by byte with sync mode and mmap memory
7444 16:59:59.651506 # ok 9 Check buffer write underflow by byte with async mode and mmap memory
7445 16:59:59.651626 # ok 10 Check buffer write underflow by byte with tag check fault ignore and mmap memory
7446 16:59:59.651775 # not ok 11 Check buffer write overflow by byte with sync mode and mmap memory
7447 16:59:59.651900 # not ok 12 Check buffer write overflow by byte with async mode and mmap memory
7448 16:59:59.652020 # ok 13 Check buffer write overflow by byte with tag fault ignore mode and mmap memory
7449 16:59:59.652140 # not ok 14 Check buffer write correctness by block with sync mode and mmap memory
7450 16:59:59.652259 # not ok 15 Check buffer write correctness by block with async mode and mmap memory
7451 16:59:59.659033 # ok 16 Check buffer write correctness by block with tag fault ignore and mmap memory
7452 16:59:59.659535 # ok 17 Check initial tags with private mapping, sync error mode and mmap memory
7453 16:59:59.659711 # ok 18 Check initial tags with private mapping, sync error mode and mmap/mprotect memory
7454 16:59:59.673610 # ok 19 Check initial tags with shared mapping, sync error mode and mmap memory
7455 16:59:59.674169 # ok 20 Check initial tags with shared mapping, sync error mode and mmap/mprotect memory
7456 16:59:59.674325 # # Totals: pass:14 fail:6 xfail:0 xpass:0 skip:0 error:0
7457 16:59:59.678357 not ok 35 selftests: arm64: check_buffer_fill # exit=1
7458 16:59:59.795112 # selftests: arm64: check_child_memory
7459 17:00:00.221061 # 1..12
7460 17:00:00.221570 # not ok 1 Check child anonymous memory with private mapping, precise mode and mmap memory
7461 17:00:00.221816 # not ok 2 Check child anonymous memory with shared mapping, precise mode and mmap memory
7462 17:00:00.222031 # not ok 3 Check child anonymous memory with private mapping, imprecise mode and mmap memory
7463 17:00:00.222282 # not ok 4 Check child anonymous memory with shared mapping, imprecise mode and mmap memory
7464 17:00:00.222477 # not ok 5 Check child anonymous memory with private mapping, precise mode and mmap/mprotect memory
7465 17:00:00.222679 # not ok 6 Check child anonymous memory with shared mapping, precise mode and mmap/mprotect memory
7466 17:00:00.222880 # not ok 7 Check child file memory with private mapping, precise mode and mmap memory
7467 17:00:00.223028 # not ok 8 Check child file memory with shared mapping, precise mode and mmap memory
7468 17:00:00.223201 # not ok 9 Check child file memory with private mapping, imprecise mode and mmap memory
7469 17:00:00.223386 # not ok 10 Check child file memory with shared mapping, imprecise mode and mmap memory
7470 17:00:00.229627 # not ok 11 Check child file memory with private mapping, precise mode and mmap/mprotect memory
7471 17:00:00.230037 # not ok 12 Check child file memory with shared mapping, precise mode and mmap/mprotect memory
7472 17:00:00.230214 # # Totals: pass:0 fail:12 xfail:0 xpass:0 skip:0 error:0
7473 17:00:00.246440 not ok 36 selftests: arm64: check_child_memory # exit=1
7474 17:00:00.369254 # selftests: arm64: check_gcr_el1_cswitch
7475 17:00:45.634027 <47>[ 99.733287] systemd-journald[109]: Sent WATCHDOG=1 notification.
7476 17:00:46.592855 <47>[ 100.693484] systemd-journald[109]: Data hash table of /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal has a fill level at 75.0 (3308 of 4408 items, 2539520 file size, 767 bytes per hash table item), suggesting rotation.
7477 17:00:46.593538 <47>[ 100.694123] systemd-journald[109]: /run/log/journal/938dcdc227b64155a30c60b8906c70ae/system.journal: Journal header limits reached or header out-of-date, rotating.
7478 17:00:46.593731 <47>[ 100.694565] systemd-journald[109]: Rotating...
7479 17:00:46.639001 <47>[ 100.739909] systemd-journald[109]: Reserving 333 entries in field hash table.
7480 17:00:46.702492 <47>[ 100.803353] systemd-journald[109]: Reserving 4408 entries in data hash table.
7481 17:00:46.716462 <47>[ 100.816535] systemd-journald[109]: Vacuuming...
7482 17:00:46.747821 <47>[ 100.848417] systemd-journald[109]: Vacuuming done, freed 0B of archived journals from /run/log/journal/938dcdc227b64155a30c60b8906c70ae.
7483 17:00:46.965444 # 1..1
7484 17:00:46.965718 # 1..1
7485 17:00:46.965818 # 1..1
7486 17:00:46.965908 # 1..1
7487 17:00:46.965993 # 1..1
7488 17:00:46.966350 # 1..1
7489 17:00:46.966488 # 1..1
7490 17:00:46.966585 # 1..1
7491 17:00:46.966674 # 1..1
7492 17:00:46.966763 # 1..1
7493 17:00:46.966849 # 1..1
7494 17:00:46.966937 # 1..1
7495 17:00:46.967024 # 1..1
7496 17:00:46.967110 # 1..1
7497 17:00:46.967196 # 1..1
7498 17:00:46.967280 # 1..1
7499 17:00:46.967358 # 1..1
7500 17:00:46.967438 # 1..1
7501 17:00:46.967524 # 1..1
7502 17:00:46.967612 # 1..1
7503 17:00:46.967698 # 1..1
7504 17:00:46.967784 # 1..1
7505 17:00:46.967872 # 1..1
7506 17:00:46.967958 # 1..1
7507 17:00:46.968048 # 1..1
7508 17:00:46.968134 # 1..1
7509 17:00:46.968222 # 1..1
7510 17:00:46.968309 # 1..1
7511 17:00:46.968393 # 1..1
7512 17:00:46.968480 # 1..1
7513 17:00:46.968566 # 1..1
7514 17:00:46.968651 # 1..1
7515 17:00:46.968736 # 1..1
7516 17:00:46.968820 # 1..1
7517 17:00:46.968905 # 1..1
7518 17:00:46.968994 # 1..1
7519 17:00:46.969082 # 1..1
7520 17:00:46.969164 # 1..1
7521 17:00:46.969247 # 1..1
7522 17:00:46.969329 # 1..1
7523 17:00:46.969411 # 1..1
7524 17:00:46.969495 # 1..1
7525 17:00:46.969581 # 1..1
7526 17:00:46.969676 # 1..1
7527 17:00:46.969763 # 1..1
7528 17:00:46.969848 # 1..1
7529 17:00:46.969934 # 1..1
7530 17:00:46.970052 # 1..1
7531 17:00:46.970142 # 1..1
7532 17:00:46.970229 # 1..1
7533 17:00:46.970314 # 1..1
7534 17:00:46.970400 # 1..1
7535 17:00:46.970488 # 1..1
7536 17:00:46.970570 # 1..1
7537 17:00:46.970653 # 1..1
7538 17:00:46.970736 # 1..1
7539 17:00:46.970816 # 1..1
7540 17:00:46.970900 # 1..1
7541 17:00:46.970983 # 1..1
7542 17:00:46.971071 # 1..1
7543 17:00:46.971157 # 1..1
7544 17:00:46.971241 # 1..1
7545 17:00:46.971329 # 1..1
7546 17:00:46.971415 # 1..1
7547 17:00:46.971502 # 1..1
7548 17:00:46.971591 # 1..1
7549 17:00:46.971681 # 1..1
7550 17:00:46.971770 # 1..1
7551 17:00:46.971859 # 1..1
7552 17:00:46.971948 # 1..1
7553 17:00:46.972034 # 1..1
7554 17:00:46.972116 # 1..1
7555 17:00:46.972203 # 1..1
7556 17:00:46.972292 # 1..1
7557 17:00:46.972381 # 1..1
7558 17:00:46.972468 # 1..1
7559 17:00:46.972554 # 1..1
7560 17:00:46.972636 # 1..1
7561 17:00:46.972724 # 1..1
7562 17:00:46.972811 # 1..1
7563 17:00:46.972895 # 1..1
7564 17:00:46.972980 # 1..1
7565 17:00:46.973067 # 1..1
7566 17:00:46.973151 # 1..1
7567 17:00:46.973237 # 1..1
7568 17:00:46.973323 # 1..1
7569 17:00:46.973416 # 1..1
7570 17:00:46.973504 # 1..1
7571 17:00:46.973589 # 1..1
7572 17:00:46.973682 # 1..1
7573 17:00:46.973768 # 1..1
7574 17:00:46.973855 # 1..1
7575 17:00:46.973943 # 1..1
7576 17:00:46.974036 # 1..1
7577 17:00:47.039338 # 1..1
7578 17:00:47.039604 # 1..1
7579 17:00:47.039727 # 1..1
7580 17:00:47.039815 # 1..1
7581 17:00:47.039929 # 1..1
7582 17:00:47.040278 # 1..1
7583 17:00:47.040383 # 1..1
7584 17:00:47.040496 # 1..1
7585 17:00:47.040581 # 1..1
7586 17:00:47.060991 # 1..1
7587 17:00:47.061388 # 1..1
7588 17:00:47.061559 # 1..1
7589 17:00:47.061705 # 1..1
7590 17:00:47.061866 # 1..1
7591 17:00:47.062007 # 1..1
7592 17:00:47.062357 # 1..1
7593 17:00:47.062454 # 1..1
7594 17:00:47.062537 # 1..1
7595 17:00:47.062616 # 1..1
7596 17:00:47.062690 # 1..1
7597 17:00:47.062753 # 1..1
7598 17:00:47.062816 # 1..1
7599 17:00:47.062879 # 1..1
7600 17:00:47.062943 # 1..1
7601 17:00:47.063008 # 1..1
7602 17:00:47.063073 # 1..1
7603 17:00:47.063138 # 1..1
7604 17:00:47.063201 # 1..1
7605 17:00:47.063264 # 1..1
7606 17:00:47.063328 # 1..1
7607 17:00:47.063390 # 1..1
7608 17:00:47.063453 # 1..1
7609 17:00:47.063517 # 1..1
7610 17:00:47.063580 # 1..1
7611 17:00:47.063642 # 1..1
7612 17:00:47.063705 # 1..1
7613 17:00:47.063766 # 1..1
7614 17:00:47.063829 # 1..1
7615 17:00:47.063892 # 1..1
7616 17:00:47.063955 # 1..1
7617 17:00:47.064019 # 1..1
7618 17:00:47.064082 # 1..1
7619 17:00:47.064144 # 1..1
7620 17:00:47.064209 # 1..1
7621 17:00:47.064273 # 1..1
7622 17:00:47.064341 # 1..1
7623 17:00:47.064432 # 1..1
7624 17:00:47.064507 # 1..1
7625 17:00:47.064580 # 1..1
7626 17:00:47.064654 # 1..1
7627 17:00:47.064727 # 1..1
7628 17:00:47.064800 # 1..1
7629 17:00:47.064873 # 1..1
7630 17:00:47.064950 # 1..1
7631 17:00:47.065027 # 1..1
7632 17:00:47.065100 # 1..1
7633 17:00:47.065178 # 1..1
7634 17:00:47.065251 # 1..1
7635 17:00:47.065325 # 1..1
7636 17:00:47.065397 # 1..1
7637 17:00:47.065469 # 1..1
7638 17:00:47.065543 # 1..1
7639 17:00:47.065615 # 1..1
7640 17:00:47.065729 # 1..1
7641 17:00:47.065802 # 1..1
7642 17:00:47.065876 # 1..1
7643 17:00:47.065948 # 1..1
7644 17:00:47.066033 # 1..1
7645 17:00:47.066122 # 1..1
7646 17:00:47.066190 # 1..1
7647 17:00:47.066249 # 1..1
7648 17:00:47.066308 # 1..1
7649 17:00:47.066367 # 1..1
7650 17:00:47.066425 # 1..1
7651 17:00:47.066484 # 1..1
7652 17:00:47.066566 # 1..1
7653 17:00:47.066648 # 1..1
7654 17:00:47.066725 # 1..1
7655 17:00:47.066798 # 1..1
7656 17:00:47.066858 # 1..1
7657 17:00:47.066931 # 1..1
7658 17:00:47.066991 # 1..1
7659 17:00:47.067051 # 1..1
7660 17:00:47.067122 # 1..1
7661 17:00:47.067187 # 1..1
7662 17:00:47.067247 # 1..1
7663 17:00:47.067312 # 1..1
7664 17:00:47.067385 # 1..1
7665 17:00:47.067445 # 1..1
7666 17:00:47.067504 # 1..1
7667 17:00:47.067563 # 1..1
7668 17:00:47.067622 # 1..1
7669 17:00:47.074076 # 1..1
7670 17:00:47.074328 # 1..1
7671 17:00:47.074423 # 1..1
7672 17:00:47.074509 # 1..1
7673 17:00:47.074803 # 1..1
7674 17:00:47.074899 # 1..1
7675 17:00:47.074986 # 1..1
7676 17:00:47.075071 # 1..1
7677 17:00:47.075157 # 1..1
7678 17:00:47.075247 # 1..1
7679 17:00:47.075332 # 1..1
7680 17:00:47.075418 # 1..1
7681 17:00:47.075506 # 1..1
7682 17:00:47.075592 # 1..1
7683 17:00:47.075677 # 1..1
7684 17:00:47.075759 # 1..1
7685 17:00:47.075842 # 1..1
7686 17:00:47.075927 # 1..1
7687 17:00:47.076012 # 1..1
7688 17:00:47.076094 # 1..1
7689 17:00:47.076184 # 1..1
7690 17:00:47.076273 # 1..1
7691 17:00:47.076358 # 1..1
7692 17:00:47.076442 # 1..1
7693 17:00:47.076549 # 1..1
7694 17:00:47.076636 # 1..1
7695 17:00:47.076717 # 1..1
7696 17:00:47.076800 # 1..1
7697 17:00:47.076890 # 1..1
7698 17:00:47.076971 # 1..1
7699 17:00:47.077053 # 1..1
7700 17:00:47.077133 # 1..1
7701 17:00:47.077217 # 1..1
7702 17:00:47.077305 # 1..1
7703 17:00:47.077388 # 1..1
7704 17:00:47.077473 # 1..1
7705 17:00:47.077558 # 1..1
7706 17:00:47.077643 # 1..1
7707 17:00:47.077741 # 1..1
7708 17:00:47.077821 # 1..1
7709 17:00:47.077907 # 1..1
7710 17:00:47.077992 # 1..1
7711 17:00:47.078074 # 1..1
7712 17:00:47.078156 # 1..1
7713 17:00:47.078242 # 1..1
7714 17:00:47.078329 # 1..1
7715 17:00:47.078415 # 1..1
7716 17:00:47.078501 # 1..1
7717 17:00:47.078586 # 1..1
7718 17:00:47.078672 # 1..1
7719 17:00:47.097098 # 1..1
7720 17:00:47.097359 # 1..1
7721 17:00:47.097452 # 1..1
7722 17:00:47.097538 # 1..1
7723 17:00:47.097847 # 1..1
7724 17:00:47.097956 # 1..1
7725 17:00:47.098047 # 1..1
7726 17:00:47.098137 # 1..1
7727 17:00:47.098223 # 1..1
7728 17:00:47.098308 # 1..1
7729 17:00:47.098396 # 1..1
7730 17:00:47.098486 # 1..1
7731 17:00:47.098571 # 1..1
7732 17:00:47.098656 # 1..1
7733 17:00:47.098741 # 1..1
7734 17:00:47.098829 # 1..1
7735 17:00:47.098917 # 1..1
7736 17:00:47.099007 # 1..1
7737 17:00:47.099091 # 1..1
7738 17:00:47.099176 # 1..1
7739 17:00:47.099261 # 1..1
7740 17:00:47.099348 # 1..1
7741 17:00:47.099433 # 1..1
7742 17:00:47.099519 # 1..1
7743 17:00:47.099604 # 1..1
7744 17:00:47.099684 # 1..1
7745 17:00:47.099788 # 1..1
7746 17:00:47.099871 # 1..1
7747 17:00:47.099956 # 1..1
7748 17:00:47.100041 # 1..1
7749 17:00:47.100126 # 1..1
7750 17:00:47.100206 # 1..1
7751 17:00:47.100284 # 1..1
7752 17:00:47.100362 # 1..1
7753 17:00:47.100441 # 1..1
7754 17:00:47.100523 # 1..1
7755 17:00:47.100606 # 1..1
7756 17:00:47.100689 # 1..1
7757 17:00:47.100770 # 1..1
7758 17:00:47.100851 # 1..1
7759 17:00:47.100933 # 1..1
7760 17:00:47.101015 # 1..1
7761 17:00:47.101099 # 1..1
7762 17:00:47.101181 # 1..1
7763 17:00:47.101271 # 1..1
7764 17:00:47.101357 # 1..1
7765 17:00:47.101440 # 1..1
7766 17:00:47.101523 # 1..1
7767 17:00:47.101605 # 1..1
7768 17:00:47.101703 # 1..1
7769 17:00:47.101789 # 1..1
7770 17:00:47.101876 # 1..1
7771 17:00:47.101959 # 1..1
7772 17:00:47.102041 # 1..1
7773 17:00:47.102124 # 1..1
7774 17:00:47.102209 # 1..1
7775 17:00:47.102299 # 1..1
7776 17:00:47.102387 # 1..1
7777 17:00:47.102475 # 1..1
7778 17:00:47.102560 # 1..1
7779 17:00:47.102646 # 1..1
7780 17:00:47.102725 # 1..1
7781 17:00:47.102808 # 1..1
7782 17:00:47.102890 # 1..1
7783 17:00:47.102974 # 1..1
7784 17:00:47.103061 # 1..1
7785 17:00:47.103143 # 1..1
7786 17:00:47.133259 # 1..1
7787 17:00:47.133520 # 1..1
7788 17:00:47.133619 # 1..1
7789 17:00:47.133722 # 1..1
7790 17:00:47.133815 # 1..1
7791 17:00:47.133905 # 1..1
7792 17:00:47.134217 # 1..1
7793 17:00:47.134326 # 1..1
7794 17:00:47.134417 # 1..1
7795 17:00:47.134503 # 1..1
7796 17:00:47.134592 # 1..1
7797 17:00:47.134683 # 1..1
7798 17:00:47.134774 # 1..1
7799 17:00:47.134861 # 1..1
7800 17:00:47.134947 # 1..1
7801 17:00:47.135036 # 1..1
7802 17:00:47.135125 # 1..1
7803 17:00:47.135213 # 1..1
7804 17:00:47.135307 # 1..1
7805 17:00:47.135398 # 1..1
7806 17:00:47.135488 # 1..1
7807 17:00:47.135579 # 1..1
7808 17:00:47.135669 # 1..1
7809 17:00:47.135759 # 1..1
7810 17:00:47.135847 # 1..1
7811 17:00:47.135932 # 1..1
7812 17:00:47.136022 # 1..1
7813 17:00:47.136112 # 1..1
7814 17:00:47.136200 # 1..1
7815 17:00:47.136294 # 1..1
7816 17:00:47.136380 # 1..1
7817 17:00:47.136464 # 1..1
7818 17:00:47.136553 # 1..1
7819 17:00:47.136872 # 1..1
7820 17:00:47.136985 # 1..1
7821 17:00:47.137075 # 1..1
7822 17:00:47.137164 # 1..1
7823 17:00:47.137253 # 1..1
7824 17:00:47.137341 # 1..1
7825 17:00:47.137431 # 1..1
7826 17:00:47.137520 # 1..1
7827 17:00:47.137608 # 1..1
7828 17:00:47.137714 # 1..1
7829 17:00:47.137804 # 1..1
7830 17:00:47.137893 # 1..1
7831 17:00:47.137982 # 1..1
7832 17:00:47.138070 # 1..1
7833 17:00:47.138157 # 1..1
7834 17:00:47.138247 # 1..1
7835 17:00:47.138340 # 1..1
7836 17:00:47.138429 # 1..1
7837 17:00:47.138519 # 1..1
7838 17:00:47.138607 # 1..1
7839 17:00:47.138694 # 1..1
7840 17:00:47.138783 # 1..1
7841 17:00:47.138870 # 1..1
7842 17:00:47.138959 # 1..1
7843 17:00:47.139048 # 1..1
7844 17:00:47.139133 # 1..1
7845 17:00:47.139222 # 1..1
7846 17:00:47.139311 # 1..1
7847 17:00:47.139399 # 1..1
7848 17:00:47.139488 # 1..1
7849 17:00:47.139577 # 1..1
7850 17:00:47.139664 # 1..1
7851 17:00:47.139753 # 1..1
7852 17:00:47.139843 # 1..1
7853 17:00:47.139932 # 1..1
7854 17:00:47.140020 # 1..1
7855 17:00:47.140109 # 1..1
7856 17:00:47.140196 # 1..1
7857 17:00:47.140286 # 1..1
7858 17:00:47.140372 # 1..1
7859 17:00:47.140452 # 1..1
7860 17:00:47.140538 # 1..1
7861 17:00:47.140628 # 1..1
7862 17:00:47.140717 # 1..1
7863 17:00:47.140804 # 1..1
7864 17:00:47.140893 # 1..1
7865 17:00:47.140982 # 1..1
7866 17:00:47.153366 # 1..1
7867 17:00:47.153625 # 1..1
7868 17:00:47.153721 # 1..1
7869 17:00:47.153809 # 1..1
7870 17:00:47.153896 # 1..1
7871 17:00:47.154321 # 1..1
7872 17:00:47.154428 # 1..1
7873 17:00:47.154517 # 1..1
7874 17:00:47.154606 # 1..1
7875 17:00:47.154698 # 1..1
7876 17:00:47.154788 # 1..1
7877 17:00:47.154879 # 1..1
7878 17:00:47.154968 # 1..1
7879 17:00:47.155058 # 1..1
7880 17:00:47.155147 # 1..1
7881 17:00:47.155237 # 1..1
7882 17:00:47.155326 # 1..1
7883 17:00:47.155415 # 1..1
7884 17:00:47.155504 # 1..1
7885 17:00:47.155593 # 1..1
7886 17:00:47.155682 # 1..1
7887 17:00:47.155772 # 1..1
7888 17:00:47.155861 # 1..1
7889 17:00:47.155950 # 1..1
7890 17:00:47.156038 # 1..1
7891 17:00:47.156127 # 1..1
7892 17:00:47.156214 # 1..1
7893 17:00:47.156303 # 1..1
7894 17:00:47.156389 # 1..1
7895 17:00:47.156478 # 1..1
7896 17:00:47.156567 # 1..1
7897 17:00:47.156656 # 1..1
7898 17:00:47.156744 # 1..1
7899 17:00:47.156833 # 1..1
7900 17:00:47.156922 # 1..1
7901 17:00:47.157011 # 1..1
7902 17:00:47.157096 # 1..1
7903 17:00:47.157177 # 1..1
7904 17:00:47.157259 # 1..1
7905 17:00:47.157340 # 1..1
7906 17:00:47.157433 # 1..1
7907 17:00:47.157515 # 1..1
7908 17:00:47.157600 # 1..1
7909 17:00:47.157694 # 1..1
7910 17:00:47.157811 # 1..1
7911 17:00:47.157902 # 1..1
7912 17:00:47.157986 # 1..1
7913 17:00:47.158069 # 1..1
7914 17:00:47.158149 # 1..1
7915 17:00:47.158234 # 1..1
7916 17:00:47.158320 # 1..1
7917 17:00:47.158403 # 1..1
7918 17:00:47.158490 # 1..1
7919 17:00:47.158575 # 1..1
7920 17:00:47.158662 # 1..1
7921 17:00:47.158748 # 1..1
7922 17:00:47.158832 # 1..1
7923 17:00:47.158918 # 1..1
7924 17:00:47.159008 # 1..1
7925 17:00:47.159096 # 1..1
7926 17:00:47.159178 # 1..1
7927 17:00:47.159265 # 1..1
7928 17:00:47.159355 # 1..1
7929 17:00:47.159445 # 1..1
7930 17:00:47.159533 # 1..1
7931 17:00:47.159622 # 1..1
7932 17:00:47.159712 # 1..1
7933 17:00:47.159801 # 1..1
7934 17:00:47.159891 # 1..1
7935 17:00:47.159981 # 1..1
7936 17:00:47.160069 # 1..1
7937 17:00:47.160156 # 1..1
7938 17:00:47.160245 # 1..1
7939 17:00:47.160334 # 1..1
7940 17:00:47.160424 # 1..1
7941 17:00:47.160513 # 1..1
7942 17:00:47.160602 # 1..1
7943 17:00:47.160693 # 1..1
7944 17:00:47.160782 # 1..1
7945 17:00:47.160872 # 1..1
7946 17:00:47.160960 # 1..1
7947 17:00:47.161049 # 1..1
7948 17:00:47.161134 # 1..1
7949 17:00:47.166647 # 1..1
7950 17:00:47.166879 # 1..1
7951 17:00:47.166970 # 1..1
7952 17:00:47.167054 # 1..1
7953 17:00:47.167349 # 1..1
7954 17:00:47.167458 # 1..1
7955 17:00:47.167547 # 1..1
7956 17:00:47.167634 # 1..1
7957 17:00:47.167719 # 1..1
7958 17:00:47.167804 # 1..1
7959 17:00:47.167889 # 1..1
7960 17:00:47.167976 # 1..1
7961 17:00:47.168067 # 1..1
7962 17:00:47.168152 # 1..1
7963 17:00:47.168235 # 1..1
7964 17:00:47.168319 # 1..1
7965 17:00:47.168407 # 1..1
7966 17:00:47.168490 # 1..1
7967 17:00:47.168574 # 1..1
7968 17:00:47.168659 # 1..1
7969 17:00:47.168745 # 1..1
7970 17:00:47.168828 # 1..1
7971 17:00:47.168911 # 1..1
7972 17:00:47.168995 # 1..1
7973 17:00:47.169088 # 1..1
7974 17:00:47.169172 # 1..1
7975 17:00:47.169257 # 1..1
7976 17:00:47.169343 # 1..1
7977 17:00:47.169432 # 1..1
7978 17:00:47.169519 # 1..1
7979 17:00:47.169602 # 1..1
7980 17:00:47.169697 # 1..1
7981 17:00:47.169800 #
7982 17:00:47.169888 not ok 37 selftests: arm64: check_gcr_el1_cswitch # TIMEOUT 45 seconds
7983 17:00:47.487158 # selftests: arm64: check_ksm_options
7984 17:00:47.914417 # 1..4
7985 17:00:47.914875 # # Invalid MTE synchronous exception caught!
7986 17:00:47.962804 not ok 38 selftests: arm64: check_ksm_options # exit=1
7987 17:00:48.342455 # selftests: arm64: check_mmap_options
7988 17:00:49.267115 # 1..22
7989 17:00:49.267573 # ok 1 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check off
7990 17:00:49.272882 # ok 2 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check off
7991 17:00:49.273302 # ok 3 Check anonymous memory with private mapping, no error mode, mmap memory and tag check off
7992 17:00:49.273409 # ok 4 Check file memory with private mapping, no error mode, mmap/mprotect memory and tag check off
7993 17:00:49.273691 # not ok 5 Check anonymous memory with private mapping, sync error mode, mmap memory and tag check on
7994 17:00:49.273811 # not ok 6 Check anonymous memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
7995 17:00:49.274117 # not ok 7 Check anonymous memory with shared mapping, sync error mode, mmap memory and tag check on
7996 17:00:49.274417 # not ok 8 Check anonymous memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
7997 17:00:49.274717 # not ok 9 Check anonymous memory with private mapping, async error mode, mmap memory and tag check on
7998 17:00:49.274829 # not ok 10 Check anonymous memory with private mapping, async error mode, mmap/mprotect memory and tag check on
7999 17:00:49.275158 # not ok 11 Check anonymous memory with shared mapping, async error mode, mmap memory and tag check on
8000 17:00:49.275384 # not ok 12 Check anonymous memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8001 17:00:49.294781 # not ok 13 Check file memory with private mapping, sync error mode, mmap memory and tag check on
8002 17:00:49.295237 # not ok 14 Check file memory with private mapping, sync error mode, mmap/mprotect memory and tag check on
8003 17:00:49.295342 # not ok 15 Check file memory with shared mapping, sync error mode, mmap memory and tag check on
8004 17:00:49.295644 # not ok 16 Check file memory with shared mapping, sync error mode, mmap/mprotect memory and tag check on
8005 17:00:49.332666 # not ok 17 Check file memory with private mapping, async error mode, mmap memory and tag check on
8006 17:00:49.333243 # not ok 18 Check file memory with private mapping, async error mode, mmap/mprotect memory and tag check on
8007 17:00:49.333454 # not ok 19 Check file memory with shared mapping, async error mode, mmap memory and tag check on
8008 17:00:49.333701 # not ok 20 Check file memory with shared mapping, async error mode, mmap/mprotect memory and tag check on
8009 17:00:49.333944 # not ok 21 Check clear PROT_MTE flags with private mapping, sync error mode and mmap memory
8010 17:00:49.334089 # not ok 22 Check clear PROT_MTE flags with private mapping and sync error mode and mmap/mprotect memory
8011 17:00:49.334212 # # Totals: pass:4 fail:18 xfail:0 xpass:0 skip:0 error:0
8012 17:00:49.361010 not ok 39 selftests: arm64: check_mmap_options # exit=1
8013 17:00:49.666688 # selftests: arm64: check_prctl
8014 17:00:50.028736 # TAP version 13
8015 17:00:50.029070 # 1..5
8016 17:00:50.029436 # ok 1 check_basic_read
8017 17:00:50.029575 # ok 2 NONE
8018 17:00:50.029715 # ok 3 SYNC
8019 17:00:50.029839 # ok 4 ASYNC
8020 17:00:50.029960 # ok 5 SYNC+ASYNC
8021 17:00:50.030082 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8022 17:00:50.061070 ok 40 selftests: arm64: check_prctl
8023 17:00:50.405152 # selftests: arm64: check_tags_inclusion
8024 17:00:50.837470 # 1..4
8025 17:00:50.838075 # # Unexpected fault recorded for 0x900ffff9c838000-0x900ffff9c838050 in mode 1
8026 17:00:50.838186 # not ok 1 Check an included tag value with sync mode
8027 17:00:50.838278 # # Unexpected fault recorded for 0xa00ffff9c838000-0xa00ffff9c838050 in mode 1
8028 17:00:50.838365 # not ok 2 Check different included tags value with sync mode
8029 17:00:50.838444 # ok 3 Check none included tags value with sync mode
8030 17:00:50.838521 # # Unexpected fault recorded for 0xd00ffff9c838000-0xd00ffff9c838050 in mode 1
8031 17:00:50.838810 # not ok 4 Check all included tags value with sync mode
8032 17:00:50.838905 # # Totals: pass:1 fail:3 xfail:0 xpass:0 skip:0 error:0
8033 17:00:50.893248 not ok 41 selftests: arm64: check_tags_inclusion # exit=1
8034 17:00:51.223367 # selftests: arm64: check_user_mem
8035 17:00:59.928467 # 1..64
8036 17:00:59.928988 # ok 1 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8037 17:00:59.929212 # ok 2 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8038 17:00:59.929399 # ok 3 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8039 17:00:59.929610 # ok 4 test type: read, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8040 17:00:59.929797 # ok 5 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8041 17:00:59.929962 # ok 6 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8042 17:00:59.930123 # ok 7 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8043 17:00:59.930302 # ok 8 test type: read, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8044 17:00:59.930473 # ok 9 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8045 17:00:59.930641 # ok 10 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8046 17:00:59.930843 # ok 11 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8047 17:00:59.931017 # ok 12 test type: read, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8048 17:00:59.931209 # ok 13 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8049 17:00:59.931397 # ok 14 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8050 17:00:59.931612 # ok 15 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8051 17:00:59.931755 # ok 16 test type: read, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8052 17:00:59.931898 # ok 17 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8053 17:00:59.932041 # ok 18 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8054 17:00:59.936957 # ok 19 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8055 17:00:59.937530 # ok 20 test type: write, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8056 17:00:59.937747 # ok 21 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8057 17:00:59.937925 # ok 22 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8058 17:00:59.938110 # ok 23 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8059 17:00:59.938255 # ok 24 test type: write, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8060 17:00:59.938413 # ok 25 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8061 17:00:59.938610 # ok 26 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8062 17:00:59.938777 # ok 27 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8063 17:00:59.938957 # ok 28 test type: write, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8064 17:00:59.939129 # ok 29 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8065 17:00:59.939285 # ok 30 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8066 17:00:59.939519 # ok 31 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8067 17:00:59.939681 # ok 32 test type: write, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8068 17:00:59.939807 # ok 33 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8069 17:00:59.940174 # ok 34 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8070 17:00:59.940357 # ok 35 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8071 17:00:59.940609 # ok 36 test type: readv, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8072 17:00:59.940836 # ok 37 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8073 17:00:59.941054 # ok 38 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8074 17:00:59.941297 # ok 39 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8075 17:00:59.941506 # ok 40 test type: readv, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8076 17:00:59.941714 # ok 41 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8077 17:00:59.941921 # ok 42 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8078 17:00:59.942089 # ok 43 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8079 17:00:59.942269 # ok 44 test type: readv, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8080 17:00:59.942497 # ok 45 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8081 17:00:59.942685 # ok 46 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8082 17:00:59.942904 # ok 47 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8083 17:00:59.943132 # ok 48 test type: readv, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8084 17:00:59.943308 # ok 49 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8085 17:00:59.943439 # ok 50 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8086 17:00:59.943586 # ok 51 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8087 17:01:01.504894 # ok 52 test type: writev, MTE_SYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8088 17:01:01.505487 # ok 53 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8089 17:01:01.505712 # ok 54 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8090 17:01:01.505899 # ok 55 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8091 17:01:01.506077 # ok 56 test type: writev, MTE_SYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8092 17:01:01.506277 # ok 57 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 0
8093 17:01:01.506442 # ok 58 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 0, tag offset: 16
8094 17:01:01.506602 # ok 59 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 0
8095 17:01:01.506758 # ok 60 test type: writev, MTE_ASYNC_ERR, MAP_SHARED, tag len: 16, tag offset: 16
8096 17:01:01.506943 # ok 61 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 0
8097 17:01:01.507097 # ok 62 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 0, tag offset: 16
8098 17:01:01.507253 # ok 63 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 0
8099 17:01:01.507430 # ok 64 test type: writev, MTE_ASYNC_ERR, MAP_PRIVATE, tag len: 16, tag offset: 16
8100 17:01:01.507640 # # Totals: pass:64 fail:0 xfail:0 xpass:0 skip:0 error:0
8101 17:01:01.532794 ok 42 selftests: arm64: check_user_mem
8102 17:01:01.661342 # selftests: arm64: btitest
8103 17:01:01.810107 # TAP version 13
8104 17:01:01.810446 # 1..18
8105 17:01:01.810916 # # HWCAP_PACA present
8106 17:01:01.811136 # # HWCAP2_BTI present
8107 17:01:01.811339 # # Test binary built for BTI
8108 17:01:01.811559 # # [SIGILL in nohint_func/call_using_br_x0, BTYPE=11 (expected)]
8109 17:01:01.811715 # ok 1 nohint_func/call_using_br_x0
8110 17:01:01.811839 # # [SIGILL in nohint_func/call_using_br_x16, BTYPE=01 (expected)]
8111 17:01:01.811956 # ok 2 nohint_func/call_using_br_x16
8112 17:01:01.812101 # # [SIGILL in nohint_func/call_using_blr, BTYPE=10 (expected)]
8113 17:01:01.812226 # ok 3 nohint_func/call_using_blr
8114 17:01:01.812341 # # [SIGILL in bti_none_func/call_using_br_x0, BTYPE=11 (expected)]
8115 17:01:01.812459 # ok 4 bti_none_func/call_using_br_x0
8116 17:01:01.813003 # # [SIGILL in bti_none_func/call_using_br_x16, BTYPE=01 (expected)]
8117 17:01:01.813558 # ok 5 bti_none_func/call_using_br_x16
8118 17:01:01.813795 # # [SIGILL in bti_none_func/call_using_blr, BTYPE=10 (expected)]
8119 17:01:01.814051 # ok 6 bti_none_func/call_using_blr
8120 17:01:01.814280 # # [SIGILL in bti_c_func/call_using_br_x0, BTYPE=11 (expected)]
8121 17:01:01.814529 # ok 7 bti_c_func/call_using_br_x0
8122 17:01:01.814727 # ok 8 bti_c_func/call_using_br_x16
8123 17:01:01.814919 # ok 9 bti_c_func/call_using_blr
8124 17:01:01.815103 # ok 10 bti_j_func/call_using_br_x0
8125 17:01:01.815308 # ok 11 bti_j_func/call_using_br_x16
8126 17:01:01.815458 # # [SIGILL in bti_j_func/call_using_blr, BTYPE=10 (expected)]
8127 17:01:01.815578 # ok 12 bti_j_func/call_using_blr
8128 17:01:01.815710 # ok 13 bti_jc_func/call_using_br_x0
8129 17:01:01.815879 # ok 14 bti_jc_func/call_using_br_x16
8130 17:01:01.816002 # ok 15 bti_jc_func/call_using_blr
8131 17:01:01.816117 # # [SIGILL in paciasp_func/call_using_br_x0, BTYPE=11 (expected)]
8132 17:01:01.816235 # ok 16 paciasp_func/call_using_br_x0
8133 17:01:01.816347 # ok 17 paciasp_func/call_using_br_x16
8134 17:01:01.816459 # ok 18 paciasp_func/call_using_blr
8135 17:01:01.816573 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8136 17:01:01.837543 ok 43 selftests: arm64: btitest
8137 17:01:01.957991 # selftests: arm64: nobtitest
8138 17:01:02.066935 # TAP version 13
8139 17:01:02.067289 # 1..18
8140 17:01:02.067727 # # HWCAP_PACA present
8141 17:01:02.067892 # # HWCAP2_BTI present
8142 17:01:02.068045 # # Test binary not built for BTI
8143 17:01:02.068191 # ok 1 nohint_func/call_using_br_x0
8144 17:01:02.068333 # ok 2 nohint_func/call_using_br_x16
8145 17:01:02.068478 # ok 3 nohint_func/call_using_blr
8146 17:01:02.070709 # ok 4 bti_none_func/call_using_br_x0
8147 17:01:02.071211 # ok 5 bti_none_func/call_using_br_x16
8148 17:01:02.071425 # ok 6 bti_none_func/call_using_blr
8149 17:01:02.071603 # ok 7 bti_c_func/call_using_br_x0
8150 17:01:02.071753 # ok 8 bti_c_func/call_using_br_x16
8151 17:01:02.071929 # ok 9 bti_c_func/call_using_blr
8152 17:01:02.072067 # ok 10 bti_j_func/call_using_br_x0
8153 17:01:02.072729 # ok 11 bti_j_func/call_using_br_x16
8154 17:01:02.073254 # ok 12 bti_j_func/call_using_blr
8155 17:01:02.073485 # ok 13 bti_jc_func/call_using_br_x0
8156 17:01:02.073686 # ok 14 bti_jc_func/call_using_br_x16
8157 17:01:02.073816 # ok 15 bti_jc_func/call_using_blr
8158 17:01:02.073962 # ok 16 paciasp_func/call_using_br_x0
8159 17:01:02.074085 # ok 17 paciasp_func/call_using_br_x16
8160 17:01:02.074203 # ok 18 paciasp_func/call_using_blr
8161 17:01:02.074326 # # Totals: pass:18 fail:0 xfail:0 xpass:0 skip:0 error:0
8162 17:01:02.089867 ok 44 selftests: arm64: nobtitest
8163 17:01:02.243289 # selftests: arm64: hwcap
8164 17:01:02.430405 # TAP version 13
8165 17:01:02.430777 # 1..28
8166 17:01:02.430931 # # RNG present
8167 17:01:02.431263 # ok 1 cpuinfo_match_RNG
8168 17:01:02.431371 # ok 2 sigill_RNG
8169 17:01:02.431456 # # SME present
8170 17:01:02.431533 # ok 3 cpuinfo_match_SME
8171 17:01:02.431607 # ok 4 sigill_SME
8172 17:01:02.431681 # # SVE present
8173 17:01:02.431753 # ok 5 cpuinfo_match_SVE
8174 17:01:02.431827 # ok 6 sigill_SVE
8175 17:01:02.431901 # # SVE 2 present
8176 17:01:02.431973 # ok 7 cpuinfo_match_SVE 2
8177 17:01:02.432045 # ok 8 sigill_SVE 2
8178 17:01:02.432116 # # SVE AES present
8179 17:01:02.432189 # ok 9 cpuinfo_match_SVE AES
8180 17:01:02.432261 # ok 10 sigill_SVE AES
8181 17:01:02.432349 # # SVE2 PMULL present
8182 17:01:02.432431 # ok 11 cpuinfo_match_SVE2 PMULL
8183 17:01:02.436838 # ok 12 sigill_SVE2 PMULL
8184 17:01:02.437375 # # SVE2 BITPERM present
8185 17:01:02.437544 # ok 13 cpuinfo_match_SVE2 BITPERM
8186 17:01:02.437699 # ok 14 sigill_SVE2 BITPERM
8187 17:01:02.437891 # # SVE2 SHA3 present
8188 17:01:02.438059 # ok 15 cpuinfo_match_SVE2 SHA3
8189 17:01:02.438204 # ok 16 sigill_SVE2 SHA3
8190 17:01:02.438363 # # SVE2 SM4 present
8191 17:01:02.438527 # ok 17 cpuinfo_match_SVE2 SM4
8192 17:01:02.438705 # ok 18 sigill_SVE2 SM4
8193 17:01:02.438831 # # SVE2 I8MM present
8194 17:01:02.438948 # ok 19 cpuinfo_match_SVE2 I8MM
8195 17:01:02.439063 # ok 20 sigill_SVE2 I8MM
8196 17:01:02.439178 # # SVE2 F32MM present
8197 17:01:02.439292 # ok 21 cpuinfo_match_SVE2 F32MM
8198 17:01:02.439406 # ok 22 sigill_SVE2 F32MM
8199 17:01:02.439519 # # SVE2 F64MM present
8200 17:01:02.439633 # ok 23 cpuinfo_match_SVE2 F64MM
8201 17:01:02.439747 # ok 24 sigill_SVE2 F64MM
8202 17:01:02.439860 # # SVE2 BF16 present
8203 17:01:02.439975 # ok 25 cpuinfo_match_SVE2 BF16
8204 17:01:02.440089 # ok 26 sigill_SVE2 BF16
8205 17:01:02.440202 # ok 27 cpuinfo_match_SVE2 EBF16
8206 17:01:02.440315 # ok 28 # SKIP sigill_SVE2 EBF16
8207 17:01:02.440430 # # Totals: pass:27 fail:0 xfail:0 xpass:0 skip:1 error:0
8208 17:01:02.469424 ok 45 selftests: arm64: hwcap
8209 17:01:02.678399 # selftests: arm64: ptrace
8210 17:01:02.886771 # TAP version 13
8211 17:01:02.887018 # 1..7
8212 17:01:02.887111 # # Parent is 4261, child is 4262
8213 17:01:02.887455 # ok 1 read_tpidr_one
8214 17:01:02.887550 # ok 2 write_tpidr_one
8215 17:01:02.887627 # ok 3 verify_tpidr_one
8216 17:01:02.887700 # ok 4 count_tpidrs
8217 17:01:02.887773 # ok 5 tpidr2_write
8218 17:01:02.887846 # ok 6 tpidr2_read
8219 17:01:02.887921 # ok 7 write_tpidr_only
8220 17:01:02.887993 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
8221 17:01:02.921372 ok 46 selftests: arm64: ptrace
8222 17:01:03.075201 # selftests: arm64: syscall-abi
8223 17:01:05.757606 # TAP version 13
8224 17:01:05.757958 # 1..514
8225 17:01:05.758741 # # SME with FA64
8226 17:01:05.758968 # ok 1 getpid() FPSIMD
8227 17:01:05.759191 # ok 2 getpid() SVE VL 256
8228 17:01:05.759391 # ok 3 getpid() SVE VL 256/SME VL 256 SM+ZA
8229 17:01:05.759567 # ok 4 getpid() SVE VL 256/SME VL 256 SM
8230 17:01:05.759718 # ok 5 getpid() SVE VL 256/SME VL 256 ZA
8231 17:01:05.759861 # ok 6 getpid() SVE VL 256/SME VL 128 SM+ZA
8232 17:01:05.760057 # ok 7 getpid() SVE VL 256/SME VL 128 SM
8233 17:01:05.760229 # ok 8 getpid() SVE VL 256/SME VL 128 ZA
8234 17:01:05.760369 # ok 9 getpid() SVE VL 256/SME VL 64 SM+ZA
8235 17:01:05.760495 # ok 10 getpid() SVE VL 256/SME VL 64 SM
8236 17:01:05.760620 # ok 11 getpid() SVE VL 256/SME VL 64 ZA
8237 17:01:05.760779 # ok 12 getpid() SVE VL 256/SME VL 32 SM+ZA
8238 17:01:05.760911 # ok 13 getpid() SVE VL 256/SME VL 32 SM
8239 17:01:05.761033 # ok 14 getpid() SVE VL 256/SME VL 32 ZA
8240 17:01:05.761183 # ok 15 getpid() SVE VL 256/SME VL 16 SM+ZA
8241 17:01:05.761334 # ok 16 getpid() SVE VL 256/SME VL 16 SM
8242 17:01:05.761460 # ok 17 getpid() SVE VL 256/SME VL 16 ZA
8243 17:01:05.761582 # ok 18 getpid() SVE VL 240
8244 17:01:05.766161 # ok 19 getpid() SVE VL 240/SME VL 256 SM+ZA
8245 17:01:05.766785 # ok 20 getpid() SVE VL 240/SME VL 256 SM
8246 17:01:05.766961 # ok 21 getpid() SVE VL 240/SME VL 256 ZA
8247 17:01:05.767172 # ok 22 getpid() SVE VL 240/SME VL 128 SM+ZA
8248 17:01:05.767381 # ok 23 getpid() SVE VL 240/SME VL 128 SM
8249 17:01:05.767530 # ok 24 getpid() SVE VL 240/SME VL 128 ZA
8250 17:01:05.767652 # ok 25 getpid() SVE VL 240/SME VL 64 SM+ZA
8251 17:01:05.767797 # ok 26 getpid() SVE VL 240/SME VL 64 SM
8252 17:01:05.767922 # ok 27 getpid() SVE VL 240/SME VL 64 ZA
8253 17:01:05.768040 # ok 28 getpid() SVE VL 240/SME VL 32 SM+ZA
8254 17:01:05.768155 # ok 29 getpid() SVE VL 240/SME VL 32 SM
8255 17:01:05.768275 # ok 30 getpid() SVE VL 240/SME VL 32 ZA
8256 17:01:05.770030 # ok 31 getpid() SVE VL 240/SME VL 16 SM+ZA
8257 17:01:05.770502 # ok 32 getpid() SVE VL 240/SME VL 16 SM
8258 17:01:05.770723 # ok 33 getpid() SVE VL 240/SME VL 16 ZA
8259 17:01:05.770950 # ok 34 getpid() SVE VL 224
8260 17:01:05.771141 # ok 35 getpid() SVE VL 224/SME VL 256 SM+ZA
8261 17:01:05.771320 # ok 36 getpid() SVE VL 224/SME VL 256 SM
8262 17:01:05.771540 # ok 37 getpid() SVE VL 224/SME VL 256 ZA
8263 17:01:05.771695 # ok 38 getpid() SVE VL 224/SME VL 128 SM+ZA
8264 17:01:05.771815 # ok 39 getpid() SVE VL 224/SME VL 128 SM
8265 17:01:05.771931 # ok 40 getpid() SVE VL 224/SME VL 128 ZA
8266 17:01:05.772047 # ok 41 getpid() SVE VL 224/SME VL 64 SM+ZA
8267 17:01:05.772161 # ok 42 getpid() SVE VL 224/SME VL 64 SM
8268 17:01:05.772277 # ok 43 getpid() SVE VL 224/SME VL 64 ZA
8269 17:01:05.772414 # ok 44 getpid() SVE VL 224/SME VL 32 SM+ZA
8270 17:01:05.772618 # ok 45 getpid() SVE VL 224/SME VL 32 SM
8271 17:01:05.772836 # ok 46 getpid() SVE VL 224/SME VL 32 ZA
8272 17:01:05.773011 # ok 47 getpid() SVE VL 224/SME VL 16 SM+ZA
8273 17:01:05.773196 # ok 48 getpid() SVE VL 224/SME VL 16 SM
8274 17:01:05.773404 # ok 49 getpid() SVE VL 224/SME VL 16 ZA
8275 17:01:05.773639 # ok 50 getpid() SVE VL 208
8276 17:01:05.773855 # ok 51 getpid() SVE VL 208/SME VL 256 SM+ZA
8277 17:01:05.774007 # ok 52 getpid() SVE VL 208/SME VL 256 SM
8278 17:01:05.774242 # ok 53 getpid() SVE VL 208/SME VL 256 ZA
8279 17:01:05.774498 # ok 54 getpid() SVE VL 208/SME VL 128 SM+ZA
8280 17:01:05.774724 # ok 55 getpid() SVE VL 208/SME VL 128 SM
8281 17:01:05.774914 # ok 56 getpid() SVE VL 208/SME VL 128 ZA
8282 17:01:05.775128 # ok 57 getpid() SVE VL 208/SME VL 64 SM+ZA
8283 17:01:05.775393 # ok 58 getpid() SVE VL 208/SME VL 64 SM
8284 17:01:05.775554 # ok 59 getpid() SVE VL 208/SME VL 64 ZA
8285 17:01:05.775676 # ok 60 getpid() SVE VL 208/SME VL 32 SM+ZA
8286 17:01:05.775789 # ok 61 getpid() SVE VL 208/SME VL 32 SM
8287 17:01:05.775903 # ok 62 getpid() SVE VL 208/SME VL 32 ZA
8288 17:01:05.776032 # ok 63 getpid() SVE VL 208/SME VL 16 SM+ZA
8289 17:01:05.776149 # ok 64 getpid() SVE VL 208/SME VL 16 SM
8290 17:01:05.776263 # ok 65 getpid() SVE VL 208/SME VL 16 ZA
8291 17:01:05.776376 # ok 66 getpid() SVE VL 192
8292 17:01:05.776497 # ok 67 getpid() SVE VL 192/SME VL 256 SM+ZA
8293 17:01:05.776612 # ok 68 getpid() SVE VL 192/SME VL 256 SM
8294 17:01:05.776729 # ok 69 getpid() SVE VL 192/SME VL 256 ZA
8295 17:01:05.776854 # ok 70 getpid() SVE VL 192/SME VL 128 SM+ZA
8296 17:01:05.776969 # ok 71 getpid() SVE VL 192/SME VL 128 SM
8297 17:01:05.777082 # ok 72 getpid() SVE VL 192/SME VL 128 ZA
8298 17:01:05.777196 # ok 73 getpid() SVE VL 192/SME VL 64 SM+ZA
8299 17:01:05.777308 # ok 74 getpid() SVE VL 192/SME VL 64 SM
8300 17:01:05.777463 # ok 75 getpid() SVE VL 192/SME VL 64 ZA
8301 17:01:05.784253 # ok 76 getpid() SVE VL 192/SME VL 32 SM+ZA
8302 17:01:05.784854 # ok 77 getpid() SVE VL 192/SME VL 32 SM
8303 17:01:05.784971 # ok 78 getpid() SVE VL 192/SME VL 32 ZA
8304 17:01:05.785068 # ok 79 getpid() SVE VL 192/SME VL 16 SM+ZA
8305 17:01:05.785156 # ok 80 getpid() SVE VL 192/SME VL 16 SM
8306 17:01:05.785247 # ok 81 getpid() SVE VL 192/SME VL 16 ZA
8307 17:01:05.785333 # ok 82 getpid() SVE VL 176
8308 17:01:05.785416 # ok 83 getpid() SVE VL 176/SME VL 256 SM+ZA
8309 17:01:05.785518 # ok 84 getpid() SVE VL 176/SME VL 256 SM
8310 17:01:05.785610 # ok 85 getpid() SVE VL 176/SME VL 256 ZA
8311 17:01:05.785708 # ok 86 getpid() SVE VL 176/SME VL 128 SM+ZA
8312 17:01:05.785794 # ok 87 getpid() SVE VL 176/SME VL 128 SM
8313 17:01:05.785897 # ok 88 getpid() SVE VL 176/SME VL 128 ZA
8314 17:01:05.785984 # ok 89 getpid() SVE VL 176/SME VL 64 SM+ZA
8315 17:01:05.786071 # ok 90 getpid() SVE VL 176/SME VL 64 SM
8316 17:01:05.786161 # ok 91 getpid() SVE VL 176/SME VL 64 ZA
8317 17:01:05.786244 # ok 92 getpid() SVE VL 176/SME VL 32 SM+ZA
8318 17:01:05.786348 # ok 93 getpid() SVE VL 176/SME VL 32 SM
8319 17:01:05.786436 # ok 94 getpid() SVE VL 176/SME VL 32 ZA
8320 17:01:05.786523 # ok 95 getpid() SVE VL 176/SME VL 16 SM+ZA
8321 17:01:05.786627 # ok 96 getpid() SVE VL 176/SME VL 16 SM
8322 17:01:05.786735 # ok 97 getpid() SVE VL 176/SME VL 16 ZA
8323 17:01:05.786844 # ok 98 getpid() SVE VL 160
8324 17:01:08.286713 # ok 99 getpid() SVE VL 160/SME VL 256 SM+ZA
8325 17:01:08.286954 # ok 100 getpid() SVE VL 160/SME VL 256 SM
8326 17:01:08.287213 # ok 101 getpid() SVE VL 160/SME VL 256 ZA
8327 17:01:08.287329 # ok 102 getpid() SVE VL 160/SME VL 128 SM+ZA
8328 17:01:08.287421 # ok 103 getpid() SVE VL 160/SME VL 128 SM
8329 17:01:08.287510 # ok 104 getpid() SVE VL 160/SME VL 128 ZA
8330 17:01:08.287596 # ok 105 getpid() SVE VL 160/SME VL 64 SM+ZA
8331 17:01:08.287696 # ok 106 getpid() SVE VL 160/SME VL 64 SM
8332 17:01:08.287986 # ok 107 getpid() SVE VL 160/SME VL 64 ZA
8333 17:01:08.289044 # ok 108 getpid() SVE VL 160/SME VL 32 SM+ZA
8334 17:01:08.289360 # ok 109 getpid() SVE VL 160/SME VL 32 SM
8335 17:01:08.289469 # ok 110 getpid() SVE VL 160/SME VL 32 ZA
8336 17:01:08.289578 # ok 111 getpid() SVE VL 160/SME VL 16 SM+ZA
8337 17:01:08.289687 # ok 112 getpid() SVE VL 160/SME VL 16 SM
8338 17:01:08.289792 # ok 113 getpid() SVE VL 160/SME VL 16 ZA
8339 17:01:08.290106 # ok 114 getpid() SVE VL 144
8340 17:01:08.290208 # ok 115 getpid() SVE VL 144/SME VL 256 SM+ZA
8341 17:01:08.290296 # ok 116 getpid() SVE VL 144/SME VL 256 SM
8342 17:01:08.290632 # ok 117 getpid() SVE VL 144/SME VL 256 ZA
8343 17:01:08.290738 # ok 118 getpid() SVE VL 144/SME VL 128 SM+ZA
8344 17:01:08.290824 # ok 119 getpid() SVE VL 144/SME VL 128 SM
8345 17:01:08.290910 # ok 120 getpid() SVE VL 144/SME VL 128 ZA
8346 17:01:08.291009 # ok 121 getpid() SVE VL 144/SME VL 64 SM+ZA
8347 17:01:08.291096 # ok 122 getpid() SVE VL 144/SME VL 64 SM
8348 17:01:08.291195 # ok 123 getpid() SVE VL 144/SME VL 64 ZA
8349 17:01:08.291281 # ok 124 getpid() SVE VL 144/SME VL 32 SM+ZA
8350 17:01:08.291375 # ok 125 getpid() SVE VL 144/SME VL 32 SM
8351 17:01:08.291462 # ok 126 getpid() SVE VL 144/SME VL 32 ZA
8352 17:01:08.296385 # ok 127 getpid() SVE VL 144/SME VL 16 SM+ZA
8353 17:01:08.296580 # ok 128 getpid() SVE VL 144/SME VL 16 SM
8354 17:01:08.296877 # ok 129 getpid() SVE VL 144/SME VL 16 ZA
8355 17:01:08.296977 # ok 130 getpid() SVE VL 128
8356 17:01:08.297060 # ok 131 getpid() SVE VL 128/SME VL 256 SM+ZA
8357 17:01:08.297143 # ok 132 getpid() SVE VL 128/SME VL 256 SM
8358 17:01:08.297241 # ok 133 getpid() SVE VL 128/SME VL 256 ZA
8359 17:01:08.297325 # ok 134 getpid() SVE VL 128/SME VL 128 SM+ZA
8360 17:01:08.297408 # ok 135 getpid() SVE VL 128/SME VL 128 SM
8361 17:01:08.297511 # ok 136 getpid() SVE VL 128/SME VL 128 ZA
8362 17:01:08.297598 # ok 137 getpid() SVE VL 128/SME VL 64 SM+ZA
8363 17:01:08.297709 # ok 138 getpid() SVE VL 128/SME VL 64 SM
8364 17:01:08.297796 # ok 139 getpid() SVE VL 128/SME VL 64 ZA
8365 17:01:08.297893 # ok 140 getpid() SVE VL 128/SME VL 32 SM+ZA
8366 17:01:08.298180 # ok 141 getpid() SVE VL 128/SME VL 32 SM
8367 17:01:08.298280 # ok 142 getpid() SVE VL 128/SME VL 32 ZA
8368 17:01:08.298379 # ok 143 getpid() SVE VL 128/SME VL 16 SM+ZA
8369 17:01:08.298466 # ok 144 getpid() SVE VL 128/SME VL 16 SM
8370 17:01:08.298560 # ok 145 getpid() SVE VL 128/SME VL 16 ZA
8371 17:01:08.298641 # ok 146 getpid() SVE VL 112
8372 17:01:08.298931 # ok 147 getpid() SVE VL 112/SME VL 256 SM+ZA
8373 17:01:08.299030 # ok 148 getpid() SVE VL 112/SME VL 256 SM
8374 17:01:08.299132 # ok 149 getpid() SVE VL 112/SME VL 256 ZA
8375 17:01:08.299233 # ok 150 getpid() SVE VL 112/SME VL 128 SM+ZA
8376 17:01:08.299331 # ok 151 getpid() SVE VL 112/SME VL 128 SM
8377 17:01:08.304045 # ok 152 getpid() SVE VL 112/SME VL 128 ZA
8378 17:01:08.304425 # ok 153 getpid() SVE VL 112/SME VL 64 SM+ZA
8379 17:01:08.304528 # ok 154 getpid() SVE VL 112/SME VL 64 SM
8380 17:01:08.304614 # ok 155 getpid() SVE VL 112/SME VL 64 ZA
8381 17:01:08.304699 # ok 156 getpid() SVE VL 112/SME VL 32 SM+ZA
8382 17:01:08.304797 # ok 157 getpid() SVE VL 112/SME VL 32 SM
8383 17:01:08.304884 # ok 158 getpid() SVE VL 112/SME VL 32 ZA
8384 17:01:08.304985 # ok 159 getpid() SVE VL 112/SME VL 16 SM+ZA
8385 17:01:08.305353 # ok 160 getpid() SVE VL 112/SME VL 16 SM
8386 17:01:08.305464 # ok 161 getpid() SVE VL 112/SME VL 16 ZA
8387 17:01:08.305551 # ok 162 getpid() SVE VL 96
8388 17:01:08.305656 # ok 163 getpid() SVE VL 96/SME VL 256 SM+ZA
8389 17:01:08.305744 # ok 164 getpid() SVE VL 96/SME VL 256 SM
8390 17:01:08.305828 # ok 165 getpid() SVE VL 96/SME VL 256 ZA
8391 17:01:08.305926 # ok 166 getpid() SVE VL 96/SME VL 128 SM+ZA
8392 17:01:08.306012 # ok 167 getpid() SVE VL 96/SME VL 128 SM
8393 17:01:08.306112 # ok 168 getpid() SVE VL 96/SME VL 128 ZA
8394 17:01:08.306211 # ok 169 getpid() SVE VL 96/SME VL 64 SM+ZA
8395 17:01:08.306312 # ok 170 getpid() SVE VL 96/SME VL 64 SM
8396 17:01:08.306659 # ok 171 getpid() SVE VL 96/SME VL 64 ZA
8397 17:01:08.306762 # ok 172 getpid() SVE VL 96/SME VL 32 SM+ZA
8398 17:01:08.306864 # ok 173 getpid() SVE VL 96/SME VL 32 SM
8399 17:01:08.306953 # ok 174 getpid() SVE VL 96/SME VL 32 ZA
8400 17:01:08.307052 # ok 175 getpid() SVE VL 96/SME VL 16 SM+ZA
8401 17:01:08.307151 # ok 176 getpid() SVE VL 96/SME VL 16 SM
8402 17:01:08.307250 # ok 177 getpid() SVE VL 96/SME VL 16 ZA
8403 17:01:08.307345 # ok 178 getpid() SVE VL 80
8404 17:01:08.312339 # ok 179 getpid() SVE VL 80/SME VL 256 SM+ZA
8405 17:01:08.312742 # ok 180 getpid() SVE VL 80/SME VL 256 SM
8406 17:01:08.312851 # ok 181 getpid() SVE VL 80/SME VL 256 ZA
8407 17:01:08.312941 # ok 182 getpid() SVE VL 80/SME VL 128 SM+ZA
8408 17:01:08.313030 # ok 183 getpid() SVE VL 80/SME VL 128 SM
8409 17:01:08.313133 # ok 184 getpid() SVE VL 80/SME VL 128 ZA
8410 17:01:08.313222 # ok 185 getpid() SVE VL 80/SME VL 64 SM+ZA
8411 17:01:08.313517 # ok 186 getpid() SVE VL 80/SME VL 64 SM
8412 17:01:08.313622 # ok 187 getpid() SVE VL 80/SME VL 64 ZA
8413 17:01:08.313719 # ok 188 getpid() SVE VL 80/SME VL 32 SM+ZA
8414 17:01:08.313821 # ok 189 getpid() SVE VL 80/SME VL 32 SM
8415 17:01:08.314076 # ok 190 getpid() SVE VL 80/SME VL 32 ZA
8416 17:01:08.314168 # ok 191 getpid() SVE VL 80/SME VL 16 SM+ZA
8417 17:01:08.314243 # ok 192 getpid() SVE VL 80/SME VL 16 SM
8418 17:01:08.314317 # ok 193 getpid() SVE VL 80/SME VL 16 ZA
8419 17:01:08.314389 # ok 194 getpid() SVE VL 64
8420 17:01:08.314462 # ok 195 getpid() SVE VL 64/SME VL 256 SM+ZA
8421 17:01:10.617390 # ok 196 getpid() SVE VL 64/SME VL 256 SM
8422 17:01:10.618002 # ok 197 getpid() SVE VL 64/SME VL 256 ZA
8423 17:01:10.618216 # ok 198 getpid() SVE VL 64/SME VL 128 SM+ZA
8424 17:01:10.618377 # ok 199 getpid() SVE VL 64/SME VL 128 SM
8425 17:01:10.618568 # ok 200 getpid() SVE VL 64/SME VL 128 ZA
8426 17:01:10.618722 # ok 201 getpid() SVE VL 64/SME VL 64 SM+ZA
8427 17:01:10.618916 # ok 202 getpid() SVE VL 64/SME VL 64 SM
8428 17:01:10.619081 # ok 203 getpid() SVE VL 64/SME VL 64 ZA
8429 17:01:10.619246 # ok 204 getpid() SVE VL 64/SME VL 32 SM+ZA
8430 17:01:10.619387 # ok 205 getpid() SVE VL 64/SME VL 32 SM
8431 17:01:10.619513 # ok 206 getpid() SVE VL 64/SME VL 32 ZA
8432 17:01:10.619630 # ok 207 getpid() SVE VL 64/SME VL 16 SM+ZA
8433 17:01:10.619745 # ok 208 getpid() SVE VL 64/SME VL 16 SM
8434 17:01:10.619859 # ok 209 getpid() SVE VL 64/SME VL 16 ZA
8435 17:01:10.619982 # ok 210 getpid() SVE VL 48
8436 17:01:10.620167 # ok 211 getpid() SVE VL 48/SME VL 256 SM+ZA
8437 17:01:10.620340 # ok 212 getpid() SVE VL 48/SME VL 256 SM
8438 17:01:10.620491 # ok 213 getpid() SVE VL 48/SME VL 256 ZA
8439 17:01:10.620717 # ok 214 getpid() SVE VL 48/SME VL 128 SM+ZA
8440 17:01:10.620928 # ok 215 getpid() SVE VL 48/SME VL 128 SM
8441 17:01:10.621135 # ok 216 getpid() SVE VL 48/SME VL 128 ZA
8442 17:01:10.621294 # ok 217 getpid() SVE VL 48/SME VL 64 SM+ZA
8443 17:01:10.622060 # ok 218 getpid() SVE VL 48/SME VL 64 SM
8444 17:01:10.622237 # ok 219 getpid() SVE VL 48/SME VL 64 ZA
8445 17:01:10.622418 # ok 220 getpid() SVE VL 48/SME VL 32 SM+ZA
8446 17:01:10.622584 # ok 221 getpid() SVE VL 48/SME VL 32 SM
8447 17:01:10.622733 # ok 222 getpid() SVE VL 48/SME VL 32 ZA
8448 17:01:10.622871 # ok 223 getpid() SVE VL 48/SME VL 16 SM+ZA
8449 17:01:10.623021 # ok 224 getpid() SVE VL 48/SME VL 16 SM
8450 17:01:10.623162 # ok 225 getpid() SVE VL 48/SME VL 16 ZA
8451 17:01:10.623316 # ok 226 getpid() SVE VL 32
8452 17:01:10.623439 # ok 227 getpid() SVE VL 32/SME VL 256 SM+ZA
8453 17:01:10.623556 # ok 228 getpid() SVE VL 32/SME VL 256 SM
8454 17:01:10.623670 # ok 229 getpid() SVE VL 32/SME VL 256 ZA
8455 17:01:10.623784 # ok 230 getpid() SVE VL 32/SME VL 128 SM+ZA
8456 17:01:10.623897 # ok 231 getpid() SVE VL 32/SME VL 128 SM
8457 17:01:10.624012 # ok 232 getpid() SVE VL 32/SME VL 128 ZA
8458 17:01:10.624124 # ok 233 getpid() SVE VL 32/SME VL 64 SM+ZA
8459 17:01:10.624238 # ok 234 getpid() SVE VL 32/SME VL 64 SM
8460 17:01:10.624351 # ok 235 getpid() SVE VL 32/SME VL 64 ZA
8461 17:01:10.624464 # ok 236 getpid() SVE VL 32/SME VL 32 SM+ZA
8462 17:01:10.624578 # ok 237 getpid() SVE VL 32/SME VL 32 SM
8463 17:01:10.624693 # ok 238 getpid() SVE VL 32/SME VL 32 ZA
8464 17:01:10.624806 # ok 239 getpid() SVE VL 32/SME VL 16 SM+ZA
8465 17:01:10.624921 # ok 240 getpid() SVE VL 32/SME VL 16 SM
8466 17:01:10.625034 # ok 241 getpid() SVE VL 32/SME VL 16 ZA
8467 17:01:10.625147 # ok 242 getpid() SVE VL 16
8468 17:01:10.625493 # ok 243 getpid() SVE VL 16/SME VL 256 SM+ZA
8469 17:01:10.625671 # ok 244 getpid() SVE VL 16/SME VL 256 SM
8470 17:01:10.625812 # ok 245 getpid() SVE VL 16/SME VL 256 ZA
8471 17:01:10.632221 # ok 246 getpid() SVE VL 16/SME VL 128 SM+ZA
8472 17:01:10.632459 # ok 247 getpid() SVE VL 16/SME VL 128 SM
8473 17:01:10.632620 # ok 248 getpid() SVE VL 16/SME VL 128 ZA
8474 17:01:10.632817 # ok 249 getpid() SVE VL 16/SME VL 64 SM+ZA
8475 17:01:10.633023 # ok 250 getpid() SVE VL 16/SME VL 64 SM
8476 17:01:10.633209 # ok 251 getpid() SVE VL 16/SME VL 64 ZA
8477 17:01:10.633352 # ok 252 getpid() SVE VL 16/SME VL 32 SM+ZA
8478 17:01:10.633510 # ok 253 getpid() SVE VL 16/SME VL 32 SM
8479 17:01:10.633778 # ok 254 getpid() SVE VL 16/SME VL 32 ZA
8480 17:01:10.633942 # ok 255 getpid() SVE VL 16/SME VL 16 SM+ZA
8481 17:01:10.634141 # ok 256 getpid() SVE VL 16/SME VL 16 SM
8482 17:01:10.634316 # ok 257 getpid() SVE VL 16/SME VL 16 ZA
8483 17:01:10.634488 # ok 258 sched_yield() FPSIMD
8484 17:01:10.634627 # ok 259 sched_yield() SVE VL 256
8485 17:01:10.634751 # ok 260 sched_yield() SVE VL 256/SME VL 256 SM+ZA
8486 17:01:10.634868 # ok 261 sched_yield() SVE VL 256/SME VL 256 SM
8487 17:01:10.634986 # ok 262 sched_yield() SVE VL 256/SME VL 256 ZA
8488 17:01:10.635136 # ok 263 sched_yield() SVE VL 256/SME VL 128 SM+ZA
8489 17:01:10.635261 # ok 264 sched_yield() SVE VL 256/SME VL 128 SM
8490 17:01:10.635378 # ok 265 sched_yield() SVE VL 256/SME VL 128 ZA
8491 17:01:10.635498 # ok 266 sched_yield() SVE VL 256/SME VL 64 SM+ZA
8492 17:01:10.635614 # ok 267 sched_yield() SVE VL 256/SME VL 64 SM
8493 17:01:10.635732 # ok 268 sched_yield() SVE VL 256/SME VL 64 ZA
8494 17:01:10.635847 # ok 269 sched_yield() SVE VL 256/SME VL 32 SM+ZA
8495 17:01:10.635964 # ok 270 sched_yield() SVE VL 256/SME VL 32 SM
8496 17:01:10.636078 # ok 271 sched_yield() SVE VL 256/SME VL 32 ZA
8497 17:01:10.636192 # ok 272 sched_yield() SVE VL 256/SME VL 16 SM+ZA
8498 17:01:10.636307 # ok 273 sched_yield() SVE VL 256/SME VL 16 SM
8499 17:01:10.636420 # ok 274 sched_yield() SVE VL 256/SME VL 16 ZA
8500 17:01:10.636533 # ok 275 sched_yield() SVE VL 240
8501 17:01:10.636647 # ok 276 sched_yield() SVE VL 240/SME VL 256 SM+ZA
8502 17:01:10.636762 # ok 277 sched_yield() SVE VL 240/SME VL 256 SM
8503 17:01:10.636907 # ok 278 sched_yield() SVE VL 240/SME VL 256 ZA
8504 17:01:10.637030 # ok 279 sched_yield() SVE VL 240/SME VL 128 SM+ZA
8505 17:01:10.637146 # ok 280 sched_yield() SVE VL 240/SME VL 128 SM
8506 17:01:10.637261 # ok 281 sched_yield() SVE VL 240/SME VL 128 ZA
8507 17:01:10.644119 # ok 282 sched_yield() SVE VL 240/SME VL 64 SM+ZA
8508 17:01:10.644360 # ok 283 sched_yield() SVE VL 240/SME VL 64 SM
8509 17:01:10.644522 # ok 284 sched_yield() SVE VL 240/SME VL 64 ZA
8510 17:01:10.644644 # ok 285 sched_yield() SVE VL 240/SME VL 32 SM+ZA
8511 17:01:10.644974 # ok 286 sched_yield() SVE VL 240/SME VL 32 SM
8512 17:01:10.645104 # ok 287 sched_yield() SVE VL 240/SME VL 32 ZA
8513 17:01:10.645220 # ok 288 sched_yield() SVE VL 240/SME VL 16 SM+ZA
8514 17:01:10.645336 # ok 289 sched_yield() SVE VL 240/SME VL 16 SM
8515 17:01:12.662845 # ok 290 sched_yield() SVE VL 240/SME VL 16 ZA
8516 17:01:12.663414 # ok 291 sched_yield() SVE VL 224
8517 17:01:12.663581 # ok 292 sched_yield() SVE VL 224/SME VL 256 SM+ZA
8518 17:01:12.663710 # ok 293 sched_yield() SVE VL 224/SME VL 256 SM
8519 17:01:12.663833 # ok 294 sched_yield() SVE VL 224/SME VL 256 ZA
8520 17:01:12.665949 # ok 295 sched_yield() SVE VL 224/SME VL 128 SM+ZA
8521 17:01:12.666474 # ok 296 sched_yield() SVE VL 224/SME VL 128 SM
8522 17:01:12.666579 # ok 297 sched_yield() SVE VL 224/SME VL 128 ZA
8523 17:01:12.666660 # ok 298 sched_yield() SVE VL 224/SME VL 64 SM+ZA
8524 17:01:12.666751 # ok 299 sched_yield() SVE VL 224/SME VL 64 SM
8525 17:01:12.667195 # ok 300 sched_yield() SVE VL 224/SME VL 64 ZA
8526 17:01:12.667376 # ok 301 sched_yield() SVE VL 224/SME VL 32 SM+ZA
8527 17:01:12.667545 # ok 302 sched_yield() SVE VL 224/SME VL 32 SM
8528 17:01:12.667672 # ok 303 sched_yield() SVE VL 224/SME VL 32 ZA
8529 17:01:12.668026 # ok 304 sched_yield() SVE VL 224/SME VL 16 SM+ZA
8530 17:01:12.668247 # ok 305 sched_yield() SVE VL 224/SME VL 16 SM
8531 17:01:12.668412 # ok 306 sched_yield() SVE VL 224/SME VL 16 ZA
8532 17:01:12.668573 # ok 307 sched_yield() SVE VL 208
8533 17:01:12.668769 # ok 308 sched_yield() SVE VL 208/SME VL 256 SM+ZA
8534 17:01:12.668926 # ok 309 sched_yield() SVE VL 208/SME VL 256 SM
8535 17:01:12.669081 # ok 310 sched_yield() SVE VL 208/SME VL 256 ZA
8536 17:01:12.669236 # ok 311 sched_yield() SVE VL 208/SME VL 128 SM+ZA
8537 17:01:12.669387 # ok 312 sched_yield() SVE VL 208/SME VL 128 SM
8538 17:01:12.669539 # ok 313 sched_yield() SVE VL 208/SME VL 128 ZA
8539 17:01:12.669747 # ok 314 sched_yield() SVE VL 208/SME VL 64 SM+ZA
8540 17:01:12.669917 # ok 315 sched_yield() SVE VL 208/SME VL 64 SM
8541 17:01:12.670083 # ok 316 sched_yield() SVE VL 208/SME VL 64 ZA
8542 17:01:12.670248 # ok 317 sched_yield() SVE VL 208/SME VL 32 SM+ZA
8543 17:01:12.670411 # ok 318 sched_yield() SVE VL 208/SME VL 32 SM
8544 17:01:12.670573 # ok 319 sched_yield() SVE VL 208/SME VL 32 ZA
8545 17:01:12.670736 # ok 320 sched_yield() SVE VL 208/SME VL 16 SM+ZA
8546 17:01:12.670880 # ok 321 sched_yield() SVE VL 208/SME VL 16 SM
8547 17:01:12.670996 # ok 322 sched_yield() SVE VL 208/SME VL 16 ZA
8548 17:01:12.671143 # ok 323 sched_yield() SVE VL 192
8549 17:01:12.671308 # ok 324 sched_yield() SVE VL 192/SME VL 256 SM+ZA
8550 17:01:12.671435 # ok 325 sched_yield() SVE VL 192/SME VL 256 SM
8551 17:01:12.671548 # ok 326 sched_yield() SVE VL 192/SME VL 256 ZA
8552 17:01:12.671661 # ok 327 sched_yield() SVE VL 192/SME VL 128 SM+ZA
8553 17:01:12.671773 # ok 328 sched_yield() SVE VL 192/SME VL 128 SM
8554 17:01:12.671884 # ok 329 sched_yield() SVE VL 192/SME VL 128 ZA
8555 17:01:12.671995 # ok 330 sched_yield() SVE VL 192/SME VL 64 SM+ZA
8556 17:01:12.672106 # ok 331 sched_yield() SVE VL 192/SME VL 64 SM
8557 17:01:12.672216 # ok 332 sched_yield() SVE VL 192/SME VL 64 ZA
8558 17:01:12.672354 # ok 333 sched_yield() SVE VL 192/SME VL 32 SM+ZA
8559 17:01:12.672473 # ok 334 sched_yield() SVE VL 192/SME VL 32 SM
8560 17:01:12.679635 # ok 335 sched_yield() SVE VL 192/SME VL 32 ZA
8561 17:01:12.680014 # ok 336 sched_yield() SVE VL 192/SME VL 16 SM+ZA
8562 17:01:12.680123 # ok 337 sched_yield() SVE VL 192/SME VL 16 SM
8563 17:01:12.680214 # ok 338 sched_yield() SVE VL 192/SME VL 16 ZA
8564 17:01:12.680301 # ok 339 sched_yield() SVE VL 176
8565 17:01:12.680403 # ok 340 sched_yield() SVE VL 176/SME VL 256 SM+ZA
8566 17:01:12.680491 # ok 341 sched_yield() SVE VL 176/SME VL 256 SM
8567 17:01:12.680882 # ok 342 sched_yield() SVE VL 176/SME VL 256 ZA
8568 17:01:12.680995 # ok 343 sched_yield() SVE VL 176/SME VL 128 SM+ZA
8569 17:01:12.681094 # ok 344 sched_yield() SVE VL 176/SME VL 128 SM
8570 17:01:12.681184 # ok 345 sched_yield() SVE VL 176/SME VL 128 ZA
8571 17:01:12.681273 # ok 346 sched_yield() SVE VL 176/SME VL 64 SM+ZA
8572 17:01:12.681361 # ok 347 sched_yield() SVE VL 176/SME VL 64 SM
8573 17:01:12.681449 # ok 348 sched_yield() SVE VL 176/SME VL 64 ZA
8574 17:01:12.681536 # ok 349 sched_yield() SVE VL 176/SME VL 32 SM+ZA
8575 17:01:12.681822 # ok 350 sched_yield() SVE VL 176/SME VL 32 SM
8576 17:01:12.681920 # ok 351 sched_yield() SVE VL 176/SME VL 32 ZA
8577 17:01:12.682009 # ok 352 sched_yield() SVE VL 176/SME VL 16 SM+ZA
8578 17:01:12.682096 # ok 353 sched_yield() SVE VL 176/SME VL 16 SM
8579 17:01:12.682183 # ok 354 sched_yield() SVE VL 176/SME VL 16 ZA
8580 17:01:12.682270 # ok 355 sched_yield() SVE VL 160
8581 17:01:12.682357 # ok 356 sched_yield() SVE VL 160/SME VL 256 SM+ZA
8582 17:01:12.682462 # ok 357 sched_yield() SVE VL 160/SME VL 256 SM
8583 17:01:12.682552 # ok 358 sched_yield() SVE VL 160/SME VL 256 ZA
8584 17:01:12.682639 # ok 359 sched_yield() SVE VL 160/SME VL 128 SM+ZA
8585 17:01:12.682726 # ok 360 sched_yield() SVE VL 160/SME VL 128 SM
8586 17:01:12.682813 # ok 361 sched_yield() SVE VL 160/SME VL 128 ZA
8587 17:01:12.682905 # ok 362 sched_yield() SVE VL 160/SME VL 64 SM+ZA
8588 17:01:12.683010 # ok 363 sched_yield() SVE VL 160/SME VL 64 SM
8589 17:01:12.683101 # ok 364 sched_yield() SVE VL 160/SME VL 64 ZA
8590 17:01:12.683185 # ok 365 sched_yield() SVE VL 160/SME VL 32 SM+ZA
8591 17:01:12.683269 # ok 366 sched_yield() SVE VL 160/SME VL 32 SM
8592 17:01:12.683368 # ok 367 sched_yield() SVE VL 160/SME VL 32 ZA
8593 17:01:12.683453 # ok 368 sched_yield() SVE VL 160/SME VL 16 SM+ZA
8594 17:01:12.683551 # ok 369 sched_yield() SVE VL 160/SME VL 16 SM
8595 17:01:12.683637 # ok 370 sched_yield() SVE VL 160/SME VL 16 ZA
8596 17:01:12.687707 # ok 371 sched_yield() SVE VL 144
8597 17:01:12.688027 # ok 372 sched_yield() SVE VL 144/SME VL 256 SM+ZA
8598 17:01:12.688235 # ok 373 sched_yield() SVE VL 144/SME VL 256 SM
8599 17:01:12.688392 # ok 374 sched_yield() SVE VL 144/SME VL 256 ZA
8600 17:01:12.688540 # ok 375 sched_yield() SVE VL 144/SME VL 128 SM+ZA
8601 17:01:12.688663 # ok 376 sched_yield() SVE VL 144/SME VL 128 SM
8602 17:01:14.773393 # ok 377 sched_yield() SVE VL 144/SME VL 128 ZA
8603 17:01:14.773759 # ok 378 sched_yield() SVE VL 144/SME VL 64 SM+ZA
8604 17:01:14.774204 # ok 379 sched_yield() SVE VL 144/SME VL 64 SM
8605 17:01:14.774426 # ok 380 sched_yield() SVE VL 144/SME VL 64 ZA
8606 17:01:14.774626 # ok 381 sched_yield() SVE VL 144/SME VL 32 SM+ZA
8607 17:01:14.774831 # ok 382 sched_yield() SVE VL 144/SME VL 32 SM
8608 17:01:14.775042 # ok 383 sched_yield() SVE VL 144/SME VL 32 ZA
8609 17:01:14.775233 # ok 384 sched_yield() SVE VL 144/SME VL 16 SM+ZA
8610 17:01:14.775403 # ok 385 sched_yield() SVE VL 144/SME VL 16 SM
8611 17:01:14.775653 # ok 386 sched_yield() SVE VL 144/SME VL 16 ZA
8612 17:01:14.775822 # ok 387 sched_yield() SVE VL 128
8613 17:01:14.775955 # ok 388 sched_yield() SVE VL 128/SME VL 256 SM+ZA
8614 17:01:14.776077 # ok 389 sched_yield() SVE VL 128/SME VL 256 SM
8615 17:01:14.776196 # ok 390 sched_yield() SVE VL 128/SME VL 256 ZA
8616 17:01:14.776316 # ok 391 sched_yield() SVE VL 128/SME VL 128 SM+ZA
8617 17:01:14.776433 # ok 392 sched_yield() SVE VL 128/SME VL 128 SM
8618 17:01:14.776551 # ok 393 sched_yield() SVE VL 128/SME VL 128 ZA
8619 17:01:14.776667 # ok 394 sched_yield() SVE VL 128/SME VL 64 SM+ZA
8620 17:01:14.776787 # ok 395 sched_yield() SVE VL 128/SME VL 64 SM
8621 17:01:14.776904 # ok 396 sched_yield() SVE VL 128/SME VL 64 ZA
8622 17:01:14.777818 # ok 397 sched_yield() SVE VL 128/SME VL 32 SM+ZA
8623 17:01:14.778040 # ok 398 sched_yield() SVE VL 128/SME VL 32 SM
8624 17:01:14.778265 # ok 399 sched_yield() SVE VL 128/SME VL 32 ZA
8625 17:01:14.778505 # ok 400 sched_yield() SVE VL 128/SME VL 16 SM+ZA
8626 17:01:14.778726 # ok 401 sched_yield() SVE VL 128/SME VL 16 SM
8627 17:01:14.778960 # ok 402 sched_yield() SVE VL 128/SME VL 16 ZA
8628 17:01:14.779360 # ok 403 sched_yield() SVE VL 112
8629 17:01:14.779458 # ok 404 sched_yield() SVE VL 112/SME VL 256 SM+ZA
8630 17:01:14.779536 # ok 405 sched_yield() SVE VL 112/SME VL 256 SM
8631 17:01:14.779611 # ok 406 sched_yield() SVE VL 112/SME VL 256 ZA
8632 17:01:14.779686 # ok 407 sched_yield() SVE VL 112/SME VL 128 SM+ZA
8633 17:01:14.779764 # ok 408 sched_yield() SVE VL 112/SME VL 128 SM
8634 17:01:14.779849 # ok 409 sched_yield() SVE VL 112/SME VL 128 ZA
8635 17:01:14.779930 # ok 410 sched_yield() SVE VL 112/SME VL 64 SM+ZA
8636 17:01:14.780003 # ok 411 sched_yield() SVE VL 112/SME VL 64 SM
8637 17:01:14.780094 # ok 412 sched_yield() SVE VL 112/SME VL 64 ZA
8638 17:01:14.780175 # ok 413 sched_yield() SVE VL 112/SME VL 32 SM+ZA
8639 17:01:14.780262 # ok 414 sched_yield() SVE VL 112/SME VL 32 SM
8640 17:01:14.780346 # ok 415 sched_yield() SVE VL 112/SME VL 32 ZA
8641 17:01:14.780446 # ok 416 sched_yield() SVE VL 112/SME VL 16 SM+ZA
8642 17:01:14.780533 # ok 417 sched_yield() SVE VL 112/SME VL 16 SM
8643 17:01:14.780617 # ok 418 sched_yield() SVE VL 112/SME VL 16 ZA
8644 17:01:14.780715 # ok 419 sched_yield() SVE VL 96
8645 17:01:14.780996 # ok 420 sched_yield() SVE VL 96/SME VL 256 SM+ZA
8646 17:01:14.781408 # ok 421 sched_yield() SVE VL 96/SME VL 256 SM
8647 17:01:14.781545 # ok 422 sched_yield() SVE VL 96/SME VL 256 ZA
8648 17:01:14.781677 # ok 423 sched_yield() SVE VL 96/SME VL 128 SM+ZA
8649 17:01:14.781771 # ok 424 sched_yield() SVE VL 96/SME VL 128 SM
8650 17:01:14.782070 # ok 425 sched_yield() SVE VL 96/SME VL 128 ZA
8651 17:01:14.782206 # ok 426 sched_yield() SVE VL 96/SME VL 64 SM+ZA
8652 17:01:14.782333 # ok 427 sched_yield() SVE VL 96/SME VL 64 SM
8653 17:01:14.782623 # ok 428 sched_yield() SVE VL 96/SME VL 64 ZA
8654 17:01:14.782750 # ok 429 sched_yield() SVE VL 96/SME VL 32 SM+ZA
8655 17:01:14.782847 # ok 430 sched_yield() SVE VL 96/SME VL 32 SM
8656 17:01:14.782931 # ok 431 sched_yield() SVE VL 96/SME VL 32 ZA
8657 17:01:14.783014 # ok 432 sched_yield() SVE VL 96/SME VL 16 SM+ZA
8658 17:01:14.783096 # ok 433 sched_yield() SVE VL 96/SME VL 16 SM
8659 17:01:14.783179 # ok 434 sched_yield() SVE VL 96/SME VL 16 ZA
8660 17:01:14.783261 # ok 435 sched_yield() SVE VL 80
8661 17:01:14.783344 # ok 436 sched_yield() SVE VL 80/SME VL 256 SM+ZA
8662 17:01:14.783446 # ok 437 sched_yield() SVE VL 80/SME VL 256 SM
8663 17:01:14.783532 # ok 438 sched_yield() SVE VL 80/SME VL 256 ZA
8664 17:01:14.783615 # ok 439 sched_yield() SVE VL 80/SME VL 128 SM+ZA
8665 17:01:14.783699 # ok 440 sched_yield() SVE VL 80/SME VL 128 SM
8666 17:01:14.783782 # ok 441 sched_yield() SVE VL 80/SME VL 128 ZA
8667 17:01:14.783867 # ok 442 sched_yield() SVE VL 80/SME VL 64 SM+ZA
8668 17:01:14.783949 # ok 443 sched_yield() SVE VL 80/SME VL 64 SM
8669 17:01:14.784030 # ok 444 sched_yield() SVE VL 80/SME VL 64 ZA
8670 17:01:14.784127 # ok 445 sched_yield() SVE VL 80/SME VL 32 SM+ZA
8671 17:01:14.791897 # ok 446 sched_yield() SVE VL 80/SME VL 32 SM
8672 17:01:14.792396 # ok 447 sched_yield() SVE VL 80/SME VL 32 ZA
8673 17:01:14.792614 # ok 448 sched_yield() SVE VL 80/SME VL 16 SM+ZA
8674 17:01:14.792790 # ok 449 sched_yield() SVE VL 80/SME VL 16 SM
8675 17:01:14.792958 # ok 450 sched_yield() SVE VL 80/SME VL 16 ZA
8676 17:01:14.793120 # ok 451 sched_yield() SVE VL 64
8677 17:01:14.793318 # ok 452 sched_yield() SVE VL 64/SME VL 256 SM+ZA
8678 17:01:14.793486 # ok 453 sched_yield() SVE VL 64/SME VL 256 SM
8679 17:01:14.793667 # ok 454 sched_yield() SVE VL 64/SME VL 256 ZA
8680 17:01:14.793825 # ok 455 sched_yield() SVE VL 64/SME VL 128 SM+ZA
8681 17:01:14.793987 # ok 456 sched_yield() SVE VL 64/SME VL 128 SM
8682 17:01:14.794142 # ok 457 sched_yield() SVE VL 64/SME VL 128 ZA
8683 17:01:14.794305 # ok 458 sched_yield() SVE VL 64/SME VL 64 SM+ZA
8684 17:01:14.794479 # ok 459 sched_yield() SVE VL 64/SME VL 64 SM
8685 17:01:14.794688 # ok 460 sched_yield() SVE VL 64/SME VL 64 ZA
8686 17:01:14.794863 # ok 461 sched_yield() SVE VL 64/SME VL 32 SM+ZA
8687 17:01:14.795040 # ok 462 sched_yield() SVE VL 64/SME VL 32 SM
8688 17:01:14.795215 # ok 463 sched_yield() SVE VL 64/SME VL 32 ZA
8689 17:01:15.473302 # ok 464 sched_yield() SVE VL 64/SME VL 16 SM+ZA
8690 17:01:15.473662 # ok 465 sched_yield() SVE VL 64/SME VL 16 SM
8691 17:01:15.474121 # ok 466 sched_yield() SVE VL 64/SME VL 16 ZA
8692 17:01:15.474317 # ok 467 sched_yield() SVE VL 48
8693 17:01:15.474479 # ok 468 sched_yield() SVE VL 48/SME VL 256 SM+ZA
8694 17:01:15.474633 # ok 469 sched_yield() SVE VL 48/SME VL 256 SM
8695 17:01:15.474783 # ok 470 sched_yield() SVE VL 48/SME VL 256 ZA
8696 17:01:15.474924 # ok 471 sched_yield() SVE VL 48/SME VL 128 SM+ZA
8697 17:01:15.475065 # ok 472 sched_yield() SVE VL 48/SME VL 128 SM
8698 17:01:15.475209 # ok 473 sched_yield() SVE VL 48/SME VL 128 ZA
8699 17:01:15.475398 # ok 474 sched_yield() SVE VL 48/SME VL 64 SM+ZA
8700 17:01:15.475557 # ok 475 sched_yield() SVE VL 48/SME VL 64 SM
8701 17:01:15.475708 # ok 476 sched_yield() SVE VL 48/SME VL 64 ZA
8702 17:01:15.475862 # ok 477 sched_yield() SVE VL 48/SME VL 32 SM+ZA
8703 17:01:15.476013 # ok 478 sched_yield() SVE VL 48/SME VL 32 SM
8704 17:01:15.476168 # ok 479 sched_yield() SVE VL 48/SME VL 32 ZA
8705 17:01:15.476316 # ok 480 sched_yield() SVE VL 48/SME VL 16 SM+ZA
8706 17:01:15.476435 # ok 481 sched_yield() SVE VL 48/SME VL 16 SM
8707 17:01:15.476551 # ok 482 sched_yield() SVE VL 48/SME VL 16 ZA
8708 17:01:15.476663 # ok 483 sched_yield() SVE VL 32
8709 17:01:15.476775 # ok 484 sched_yield() SVE VL 32/SME VL 256 SM+ZA
8710 17:01:15.476886 # ok 485 sched_yield() SVE VL 32/SME VL 256 SM
8711 17:01:15.477002 # ok 486 sched_yield() SVE VL 32/SME VL 256 ZA
8712 17:01:15.477156 # ok 487 sched_yield() SVE VL 32/SME VL 128 SM+ZA
8713 17:01:15.477287 # ok 488 sched_yield() SVE VL 32/SME VL 128 SM
8714 17:01:15.477415 # ok 489 sched_yield() SVE VL 32/SME VL 128 ZA
8715 17:01:15.482444 # ok 490 sched_yield() SVE VL 32/SME VL 64 SM+ZA
8716 17:01:15.482685 # ok 491 sched_yield() SVE VL 32/SME VL 64 SM
8717 17:01:15.483087 # ok 492 sched_yield() SVE VL 32/SME VL 64 ZA
8718 17:01:15.483230 # ok 493 sched_yield() SVE VL 32/SME VL 32 SM+ZA
8719 17:01:15.483376 # ok 494 sched_yield() SVE VL 32/SME VL 32 SM
8720 17:01:15.483517 # ok 495 sched_yield() SVE VL 32/SME VL 32 ZA
8721 17:01:15.483656 # ok 496 sched_yield() SVE VL 32/SME VL 16 SM+ZA
8722 17:01:15.483830 # ok 497 sched_yield() SVE VL 32/SME VL 16 SM
8723 17:01:15.483993 # ok 498 sched_yield() SVE VL 32/SME VL 16 ZA
8724 17:01:15.484172 # ok 499 sched_yield() SVE VL 16
8725 17:01:15.484374 # ok 500 sched_yield() SVE VL 16/SME VL 256 SM+ZA
8726 17:01:15.484544 # ok 501 sched_yield() SVE VL 16/SME VL 256 SM
8727 17:01:15.484722 # ok 502 sched_yield() SVE VL 16/SME VL 256 ZA
8728 17:01:15.484933 # ok 503 sched_yield() SVE VL 16/SME VL 128 SM+ZA
8729 17:01:15.485149 # ok 504 sched_yield() SVE VL 16/SME VL 128 SM
8730 17:01:15.485349 # ok 505 sched_yield() SVE VL 16/SME VL 128 ZA
8731 17:01:15.485491 # ok 506 sched_yield() SVE VL 16/SME VL 64 SM+ZA
8732 17:01:15.485615 # ok 507 sched_yield() SVE VL 16/SME VL 64 SM
8733 17:01:15.485769 # ok 508 sched_yield() SVE VL 16/SME VL 64 ZA
8734 17:01:15.485886 # ok 509 sched_yield() SVE VL 16/SME VL 32 SM+ZA
8735 17:01:15.486000 # ok 510 sched_yield() SVE VL 16/SME VL 32 SM
8736 17:01:15.486116 # ok 511 sched_yield() SVE VL 16/SME VL 32 ZA
8737 17:01:15.486228 # ok 512 sched_yield() SVE VL 16/SME VL 16 SM+ZA
8738 17:01:15.486371 # ok 513 sched_yield() SVE VL 16/SME VL 16 SM
8739 17:01:15.486493 # ok 514 sched_yield() SVE VL 16/SME VL 16 ZA
8740 17:01:15.486609 # # Totals: pass:514 fail:0 xfail:0 xpass:0 skip:0 error:0
8741 17:01:15.486723 ok 47 selftests: arm64: syscall-abi
8742 17:01:15.532058 # selftests: arm64: tpidr2
8743 17:01:15.684997 # TAP version 13
8744 17:01:15.685316 # 1..5
8745 17:01:15.685483 # # PID: 4296
8746 17:01:15.685875 # ok 1 default_value
8747 17:01:15.686007 # ok 2 write_read
8748 17:01:15.686120 # ok 3 write_sleep_read
8749 17:01:15.686230 # ok 4 write_fork_read
8750 17:01:15.686340 # ok 5 write_clone_read
8751 17:01:15.686450 # # Totals: pass:5 fail:0 xfail:0 xpass:0 skip:0 error:0
8752 17:01:15.700701 ok 48 selftests: arm64: tpidr2
8753 17:01:16.226214 arm64_tags_test pass
8754 17:01:16.226468 arm64_run_tags_test_sh pass
8755 17:01:16.226780 arm64_fake_sigreturn_bad_magic pass
8756 17:01:16.226889 arm64_fake_sigreturn_bad_size pass
8757 17:01:16.226981 arm64_fake_sigreturn_bad_size_for_magic0 pass
8758 17:01:16.227067 arm64_fake_sigreturn_duplicated_fpsimd pass
8759 17:01:16.227148 arm64_fake_sigreturn_misaligned_sp pass
8760 17:01:16.227227 arm64_fake_sigreturn_missing_fpsimd pass
8761 17:01:16.227330 arm64_fake_sigreturn_sme_change_vl pass
8762 17:01:16.227420 arm64_fake_sigreturn_sve_change_vl pass
8763 17:01:16.227509 arm64_mangle_pstate_invalid_compat_toggle pass
8764 17:01:16.227590 arm64_mangle_pstate_invalid_daif_bits pass
8765 17:01:16.227671 arm64_mangle_pstate_invalid_mode_el1h pass
8766 17:01:16.227754 arm64_mangle_pstate_invalid_mode_el1t pass
8767 17:01:16.227838 arm64_mangle_pstate_invalid_mode_el2h pass
8768 17:01:16.227940 arm64_mangle_pstate_invalid_mode_el2t pass
8769 17:01:16.228028 arm64_mangle_pstate_invalid_mode_el3h pass
8770 17:01:16.228114 arm64_mangle_pstate_invalid_mode_el3t pass
8771 17:01:16.228199 arm64_sme_trap_no_sm pass
8772 17:01:16.228283 arm64_sme_trap_non_streaming skip
8773 17:01:16.228367 arm64_sme_trap_za pass
8774 17:01:16.228469 arm64_sme_vl pass
8775 17:01:16.228561 arm64_ssve_regs pass
8776 17:01:16.228654 arm64_sve_regs pass
8777 17:01:16.228747 arm64_sve_vl pass
8778 17:01:16.228836 arm64_za_no_regs pass
8779 17:01:16.228917 arm64_za_regs pass
8780 17:01:16.228993 arm64_pac_global_corrupt_pac pass
8781 17:01:16.229069 arm64_pac_global_pac_instructions_not_nop pass
8782 17:01:16.229696 arm64_pac_global_pac_instructions_not_nop_generic pass
8783 17:01:16.229785 arm64_pac_global_single_thread_different_keys pass
8784 17:01:16.229857 arm64_pac_global_exec_changed_keys pass
8785 17:01:16.229928 arm64_pac_global_context_switch_keep_keys pass
8786 17:01:16.230001 arm64_pac_global_context_switch_keep_keys_generic pass
8787 17:01:16.230073 arm64_pac pass
8788 17:01:16.230151 arm64_fp-stress_FPSIMD-0-0 pass
8789 17:01:16.230231 arm64_fp-stress_SVE-VL-256-0 pass
8790 17:01:16.230314 arm64_fp-stress_SVE-VL-240-0 pass
8791 17:01:16.230395 arm64_fp-stress_SVE-VL-224-0 pass
8792 17:01:16.230474 arm64_fp-stress_SVE-VL-208-0 pass
8793 17:01:16.230559 arm64_fp-stress_SVE-VL-192-0 pass
8794 17:01:16.230639 arm64_fp-stress_SVE-VL-176-0 pass
8795 17:01:16.230721 arm64_fp-stress_SVE-VL-160-0 pass
8796 17:01:16.230802 arm64_fp-stress_SVE-VL-144-0 pass
8797 17:01:16.230883 arm64_fp-stress_SVE-VL-128-0 pass
8798 17:01:16.230963 arm64_fp-stress_SVE-VL-112-0 pass
8799 17:01:16.231065 arm64_fp-stress_SVE-VL-96-0 pass
8800 17:01:16.231148 arm64_fp-stress_SVE-VL-80-0 pass
8801 17:01:16.231227 arm64_fp-stress_SVE-VL-64-0 pass
8802 17:01:16.231309 arm64_fp-stress_SVE-VL-48-0 pass
8803 17:01:16.231391 arm64_fp-stress_SVE-VL-32-0 pass
8804 17:01:16.231475 arm64_fp-stress_SVE-VL-16-0 pass
8805 17:01:16.231562 arm64_fp-stress_SSVE-VL-256-0 pass
8806 17:01:16.231644 arm64_fp-stress_ZA-VL-256-0 pass
8807 17:01:16.231724 arm64_fp-stress_SSVE-VL-128-0 pass
8808 17:01:16.232045 arm64_fp-stress_ZA-VL-128-0 pass
8809 17:01:16.232215 arm64_fp-stress_SSVE-VL-64-0 pass
8810 17:01:16.232349 arm64_fp-stress_ZA-VL-64-0 pass
8811 17:01:16.232467 arm64_fp-stress_SSVE-VL-32-0 pass
8812 17:01:16.232583 arm64_fp-stress_ZA-VL-32-0 pass
8813 17:01:16.232699 arm64_fp-stress_SSVE-VL-16-0 pass
8814 17:01:16.232820 arm64_fp-stress_ZA-VL-16-0 pass
8815 17:01:16.232936 arm64_fp-stress pass
8816 17:01:16.233050 arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 pass
8817 17:01:16.233164 arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state pass
8818 17:01:16.233279 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set pass
8819 17:01:16.233393 arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared pass
8820 17:01:16.233509 arm64_sve-ptrace_Set_SVE_VL_16 pass
8821 17:01:16.233626 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 pass
8822 17:01:16.235748 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 pass
8823 17:01:16.236190 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 pass
8824 17:01:16.236397 arm64_sve-ptrace_Set_SVE_VL_32 pass
8825 17:01:16.236610 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 pass
8826 17:01:16.236826 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 pass
8827 17:01:16.236997 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 pass
8828 17:01:16.237160 arm64_sve-ptrace_Set_SVE_VL_48 pass
8829 17:01:16.237295 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 pass
8830 17:01:16.237480 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 pass
8831 17:01:16.237722 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 pass
8832 17:01:16.237934 arm64_sve-ptrace_Set_SVE_VL_64 pass
8833 17:01:16.238139 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 pass
8834 17:01:16.238317 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 pass
8835 17:01:16.238487 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 pass
8836 17:01:16.238654 arm64_sve-ptrace_Set_SVE_VL_80 pass
8837 17:01:16.238814 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 pass
8838 17:01:16.239021 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 pass
8839 17:01:16.239188 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 pass
8840 17:01:16.239340 arm64_sve-ptrace_Set_SVE_VL_96 pass
8841 17:01:16.239459 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 pass
8842 17:01:16.239577 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 pass
8843 17:01:16.239690 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 pass
8844 17:01:16.239802 arm64_sve-ptrace_Set_SVE_VL_112 pass
8845 17:01:16.239914 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 pass
8846 17:01:16.240028 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 pass
8847 17:01:16.240141 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 pass
8848 17:01:16.240253 arm64_sve-ptrace_Set_SVE_VL_128 pass
8849 17:01:16.240390 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 pass
8850 17:01:16.240510 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 pass
8851 17:01:16.240625 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 pass
8852 17:01:16.243663 arm64_sve-ptrace_Set_SVE_VL_144 pass
8853 17:01:16.243973 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 pass
8854 17:01:16.244070 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 pass
8855 17:01:16.244176 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 pass
8856 17:01:16.244260 arm64_sve-ptrace_Set_SVE_VL_160 pass
8857 17:01:16.244353 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 pass
8858 17:01:16.244447 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 pass
8859 17:01:16.244542 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 pass
8860 17:01:16.244831 arm64_sve-ptrace_Set_SVE_VL_176 pass
8861 17:01:16.244947 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 pass
8862 17:01:16.245035 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 pass
8863 17:01:16.245131 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 pass
8864 17:01:16.245212 arm64_sve-ptrace_Set_SVE_VL_192 pass
8865 17:01:16.245492 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 pass
8866 17:01:16.245586 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 pass
8867 17:01:16.245700 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 pass
8868 17:01:16.245802 arm64_sve-ptrace_Set_SVE_VL_208 pass
8869 17:01:16.245897 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 pass
8870 17:01:16.245998 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 pass
8871 17:01:16.246320 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 pass
8872 17:01:16.246426 arm64_sve-ptrace_Set_SVE_VL_224 pass
8873 17:01:16.246507 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 pass
8874 17:01:16.246599 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 pass
8875 17:01:16.246680 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 pass
8876 17:01:16.246770 arm64_sve-ptrace_Set_SVE_VL_240 pass
8877 17:01:16.246863 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 pass
8878 17:01:16.246963 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 pass
8879 17:01:16.247265 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 pass
8880 17:01:16.247369 arm64_sve-ptrace_Set_SVE_VL_256 pass
8881 17:01:16.247463 arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 pass
8882 17:01:16.251655 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 pass
8883 17:01:16.252104 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 pass
8884 17:01:16.252305 arm64_sve-ptrace_Set_SVE_VL_272 pass
8885 17:01:16.252480 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 skip
8886 17:01:16.252646 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
8887 17:01:16.252843 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
8888 17:01:16.253013 arm64_sve-ptrace_Set_SVE_VL_288 pass
8889 17:01:16.253169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 skip
8890 17:01:16.253334 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
8891 17:01:16.253506 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
8892 17:01:16.253743 arm64_sve-ptrace_Set_SVE_VL_304 pass
8893 17:01:16.253973 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 skip
8894 17:01:16.254156 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
8895 17:01:16.254320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
8896 17:01:16.254531 arm64_sve-ptrace_Set_SVE_VL_320 pass
8897 17:01:16.254748 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 skip
8898 17:01:16.254936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
8899 17:01:16.255107 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
8900 17:01:16.255298 arm64_sve-ptrace_Set_SVE_VL_336 pass
8901 17:01:16.255505 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 skip
8902 17:01:16.255694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
8903 17:01:16.255821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
8904 17:01:16.255940 arm64_sve-ptrace_Set_SVE_VL_352 pass
8905 17:01:16.256053 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 skip
8906 17:01:16.256168 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
8907 17:01:16.256282 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
8908 17:01:16.256396 arm64_sve-ptrace_Set_SVE_VL_368 pass
8909 17:01:16.256511 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 skip
8910 17:01:16.256626 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
8911 17:01:16.256738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
8912 17:01:16.256851 arm64_sve-ptrace_Set_SVE_VL_384 pass
8913 17:01:16.256964 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 skip
8914 17:01:16.259597 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
8915 17:01:16.260077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
8916 17:01:16.260183 arm64_sve-ptrace_Set_SVE_VL_400 pass
8917 17:01:16.260269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 skip
8918 17:01:16.260370 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
8919 17:01:16.260455 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
8920 17:01:16.260534 arm64_sve-ptrace_Set_SVE_VL_416 pass
8921 17:01:16.260631 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 skip
8922 17:01:16.260730 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
8923 17:01:16.260826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
8924 17:01:16.260925 arm64_sve-ptrace_Set_SVE_VL_432 pass
8925 17:01:16.261057 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 skip
8926 17:01:16.261164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
8927 17:01:16.261260 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
8928 17:01:16.261347 arm64_sve-ptrace_Set_SVE_VL_448 pass
8929 17:01:16.261412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 skip
8930 17:01:16.261472 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
8931 17:01:16.276378 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
8932 17:01:16.276625 arm64_sve-ptrace_Set_SVE_VL_464 pass
8933 17:01:16.276925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 skip
8934 17:01:16.277023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
8935 17:01:16.277110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
8936 17:01:16.277195 arm64_sve-ptrace_Set_SVE_VL_480 pass
8937 17:01:16.277274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 skip
8938 17:01:16.277369 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
8939 17:01:16.277448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
8940 17:01:16.277526 arm64_sve-ptrace_Set_SVE_VL_496 pass
8941 17:01:16.277602 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 skip
8942 17:01:16.277701 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
8943 17:01:16.277780 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
8944 17:01:16.277858 arm64_sve-ptrace_Set_SVE_VL_512 pass
8945 17:01:16.277949 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 skip
8946 17:01:16.278035 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
8947 17:01:16.278125 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
8948 17:01:16.278475 arm64_sve-ptrace_Set_SVE_VL_528 pass
8949 17:01:16.278674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 skip
8950 17:01:16.278862 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
8951 17:01:16.279028 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
8952 17:01:16.279177 arm64_sve-ptrace_Set_SVE_VL_544 pass
8953 17:01:16.279354 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 skip
8954 17:01:16.279492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
8955 17:01:16.279637 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
8956 17:01:16.279781 arm64_sve-ptrace_Set_SVE_VL_560 pass
8957 17:01:16.279924 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 skip
8958 17:01:16.280097 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
8959 17:01:16.283672 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
8960 17:01:16.284085 arm64_sve-ptrace_Set_SVE_VL_576 pass
8961 17:01:16.284244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 skip
8962 17:01:16.284443 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
8963 17:01:16.284677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
8964 17:01:16.284839 arm64_sve-ptrace_Set_SVE_VL_592 pass
8965 17:01:16.284986 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 skip
8966 17:01:16.285128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
8967 17:01:16.285270 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
8968 17:01:16.285413 arm64_sve-ptrace_Set_SVE_VL_608 pass
8969 17:01:16.285595 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 skip
8970 17:01:16.285748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
8971 17:01:16.285893 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
8972 17:01:16.286036 arm64_sve-ptrace_Set_SVE_VL_624 pass
8973 17:01:16.286177 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 skip
8974 17:01:16.286318 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
8975 17:01:16.286459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
8976 17:01:16.286599 arm64_sve-ptrace_Set_SVE_VL_640 pass
8977 17:01:16.286743 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 skip
8978 17:01:16.286927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
8979 17:01:16.287063 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
8980 17:01:16.287205 arm64_sve-ptrace_Set_SVE_VL_656 pass
8981 17:01:16.287346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 skip
8982 17:01:16.287487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
8983 17:01:16.287626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
8984 17:01:16.287769 arm64_sve-ptrace_Set_SVE_VL_672 pass
8985 17:01:16.287910 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 skip
8986 17:01:16.288054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
8987 17:01:16.288195 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
8988 17:01:16.288374 arm64_sve-ptrace_Set_SVE_VL_688 pass
8989 17:01:16.288510 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 skip
8990 17:01:16.288653 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
8991 17:01:16.288795 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
8992 17:01:16.291663 arm64_sve-ptrace_Set_SVE_VL_704 pass
8993 17:01:16.292073 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 skip
8994 17:01:16.292259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
8995 17:01:16.292403 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
8996 17:01:16.292562 arm64_sve-ptrace_Set_SVE_VL_720 pass
8997 17:01:16.292838 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 skip
8998 17:01:16.293046 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
8999 17:01:16.293223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
9000 17:01:16.293387 arm64_sve-ptrace_Set_SVE_VL_736 pass
9001 17:01:16.293539 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 skip
9002 17:01:16.293708 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
9003 17:01:16.293905 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
9004 17:01:16.294078 arm64_sve-ptrace_Set_SVE_VL_752 pass
9005 17:01:16.294253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 skip
9006 17:01:16.294451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
9007 17:01:16.294619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
9008 17:01:16.294776 arm64_sve-ptrace_Set_SVE_VL_768 pass
9009 17:01:16.294933 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 skip
9010 17:01:16.295092 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
9011 17:01:16.295258 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
9012 17:01:16.295457 arm64_sve-ptrace_Set_SVE_VL_784 pass
9013 17:01:16.295627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 skip
9014 17:01:16.295755 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
9015 17:01:16.295873 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
9016 17:01:16.295990 arm64_sve-ptrace_Set_SVE_VL_800 pass
9017 17:01:16.296105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 skip
9018 17:01:16.296221 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
9019 17:01:16.296336 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
9020 17:01:16.296453 arm64_sve-ptrace_Set_SVE_VL_816 pass
9021 17:01:16.296567 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 skip
9022 17:01:16.296683 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
9023 17:01:16.296802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
9024 17:01:16.296916 arm64_sve-ptrace_Set_SVE_VL_832 pass
9025 17:01:16.297031 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 skip
9026 17:01:16.297146 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
9027 17:01:16.299599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
9028 17:01:16.300025 arm64_sve-ptrace_Set_SVE_VL_848 pass
9029 17:01:16.300166 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 skip
9030 17:01:16.300286 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
9031 17:01:16.300412 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
9032 17:01:16.300570 arm64_sve-ptrace_Set_SVE_VL_864 pass
9033 17:01:16.300727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 skip
9034 17:01:16.300897 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
9035 17:01:16.301085 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
9036 17:01:16.301253 arm64_sve-ptrace_Set_SVE_VL_880 pass
9037 17:01:16.301422 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 skip
9038 17:01:16.301667 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
9039 17:01:16.301881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
9040 17:01:16.302076 arm64_sve-ptrace_Set_SVE_VL_896 pass
9041 17:01:16.302248 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 skip
9042 17:01:16.302466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
9043 17:01:16.302658 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
9044 17:01:16.302818 arm64_sve-ptrace_Set_SVE_VL_912 pass
9045 17:01:16.302969 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 skip
9046 17:01:16.303116 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
9047 17:01:16.303249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
9048 17:01:16.303380 arm64_sve-ptrace_Set_SVE_VL_928 pass
9049 17:01:16.303506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 skip
9050 17:01:16.303622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
9051 17:01:16.303739 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
9052 17:01:16.303854 arm64_sve-ptrace_Set_SVE_VL_944 pass
9053 17:01:16.304000 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 skip
9054 17:01:16.304127 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
9055 17:01:16.304295 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
9056 17:01:16.304418 arm64_sve-ptrace_Set_SVE_VL_960 pass
9057 17:01:16.304534 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 skip
9058 17:01:16.304649 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
9059 17:01:16.304767 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
9060 17:01:16.304882 arm64_sve-ptrace_Set_SVE_VL_976 pass
9061 17:01:16.304997 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 skip
9062 17:01:16.305112 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
9063 17:01:16.305226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
9064 17:01:16.307662 arm64_sve-ptrace_Set_SVE_VL_992 pass
9065 17:01:16.308046 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 skip
9066 17:01:16.308182 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
9067 17:01:16.308309 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
9068 17:01:16.308435 arm64_sve-ptrace_Set_SVE_VL_1008 pass
9069 17:01:16.308606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 skip
9070 17:01:16.308770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
9071 17:01:16.308913 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
9072 17:01:16.309074 arm64_sve-ptrace_Set_SVE_VL_1024 pass
9073 17:01:16.309238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 skip
9074 17:01:16.309405 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
9075 17:01:16.309590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
9076 17:01:16.309775 arm64_sve-ptrace_Set_SVE_VL_1040 pass
9077 17:01:16.309934 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 skip
9078 17:01:16.310093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
9079 17:01:16.310259 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
9080 17:01:16.310396 arm64_sve-ptrace_Set_SVE_VL_1056 pass
9081 17:01:16.310514 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 skip
9082 17:01:16.310631 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
9083 17:01:16.310750 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
9084 17:01:16.310879 arm64_sve-ptrace_Set_SVE_VL_1072 pass
9085 17:01:16.311028 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 skip
9086 17:01:16.311152 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
9087 17:01:16.311269 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
9088 17:01:16.311386 arm64_sve-ptrace_Set_SVE_VL_1088 pass
9089 17:01:16.311502 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 skip
9090 17:01:16.311618 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
9091 17:01:16.311738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
9092 17:01:16.311855 arm64_sve-ptrace_Set_SVE_VL_1104 pass
9093 17:01:16.325502 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 skip
9094 17:01:16.325765 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
9095 17:01:16.326077 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
9096 17:01:16.326184 arm64_sve-ptrace_Set_SVE_VL_1120 pass
9097 17:01:16.326274 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 skip
9098 17:01:16.326360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
9099 17:01:16.326462 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
9100 17:01:16.326549 arm64_sve-ptrace_Set_SVE_VL_1136 pass
9101 17:01:16.326634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 skip
9102 17:01:16.326720 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
9103 17:01:16.326821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
9104 17:01:16.326907 arm64_sve-ptrace_Set_SVE_VL_1152 pass
9105 17:01:16.326991 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 skip
9106 17:01:16.327090 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
9107 17:01:16.327176 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
9108 17:01:16.327259 arm64_sve-ptrace_Set_SVE_VL_1168 pass
9109 17:01:16.327365 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 skip
9110 17:01:16.327466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
9111 17:01:16.327865 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
9112 17:01:16.327972 arm64_sve-ptrace_Set_SVE_VL_1184 pass
9113 17:01:16.328060 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 skip
9114 17:01:16.328163 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
9115 17:01:16.328263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
9116 17:01:16.328362 arm64_sve-ptrace_Set_SVE_VL_1200 pass
9117 17:01:16.328461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 skip
9118 17:01:16.328562 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
9119 17:01:16.328861 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
9120 17:01:16.328966 arm64_sve-ptrace_Set_SVE_VL_1216 pass
9121 17:01:16.329066 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 skip
9122 17:01:16.329165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
9123 17:01:16.329448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
9124 17:01:16.329560 arm64_sve-ptrace_Set_SVE_VL_1232 pass
9125 17:01:16.329664 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 skip
9126 17:01:16.329997 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
9127 17:01:16.330095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
9128 17:01:16.330188 arm64_sve-ptrace_Set_SVE_VL_1248 pass
9129 17:01:16.330269 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 skip
9130 17:01:16.330364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
9131 17:01:16.330448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
9132 17:01:16.330544 arm64_sve-ptrace_Set_SVE_VL_1264 pass
9133 17:01:16.330641 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 skip
9134 17:01:16.330928 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
9135 17:01:16.331023 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
9136 17:01:16.331306 arm64_sve-ptrace_Set_SVE_VL_1280 pass
9137 17:01:16.331405 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 skip
9138 17:01:16.331492 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
9139 17:01:16.331590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
9140 17:01:16.335630 arm64_sve-ptrace_Set_SVE_VL_1296 pass
9141 17:01:16.336032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 skip
9142 17:01:16.336184 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
9143 17:01:16.336339 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
9144 17:01:16.336531 arm64_sve-ptrace_Set_SVE_VL_1312 pass
9145 17:01:16.336742 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 skip
9146 17:01:16.336917 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
9147 17:01:16.337080 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
9148 17:01:16.337242 arm64_sve-ptrace_Set_SVE_VL_1328 pass
9149 17:01:16.337406 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 skip
9150 17:01:16.337569 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
9151 17:01:16.337784 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
9152 17:01:16.337937 arm64_sve-ptrace_Set_SVE_VL_1344 pass
9153 17:01:16.338133 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 skip
9154 17:01:16.338289 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
9155 17:01:16.338495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
9156 17:01:16.338684 arm64_sve-ptrace_Set_SVE_VL_1360 pass
9157 17:01:16.338881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 skip
9158 17:01:16.339042 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
9159 17:01:16.339214 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
9160 17:01:16.339429 arm64_sve-ptrace_Set_SVE_VL_1376 pass
9161 17:01:16.339563 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 skip
9162 17:01:16.339680 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
9163 17:01:16.339796 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
9164 17:01:16.339909 arm64_sve-ptrace_Set_SVE_VL_1392 pass
9165 17:01:16.340025 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 skip
9166 17:01:16.340141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
9167 17:01:16.340256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
9168 17:01:16.340371 arm64_sve-ptrace_Set_SVE_VL_1408 pass
9169 17:01:16.340520 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 skip
9170 17:01:16.340648 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
9171 17:01:16.340790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
9172 17:01:16.343760 arm64_sve-ptrace_Set_SVE_VL_1424 pass
9173 17:01:16.344242 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 skip
9174 17:01:16.344401 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
9175 17:01:16.344526 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
9176 17:01:16.344644 arm64_sve-ptrace_Set_SVE_VL_1440 pass
9177 17:01:16.344790 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 skip
9178 17:01:16.344914 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
9179 17:01:16.345033 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
9180 17:01:16.345152 arm64_sve-ptrace_Set_SVE_VL_1456 pass
9181 17:01:16.345271 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 skip
9182 17:01:16.345389 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
9183 17:01:16.345558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
9184 17:01:16.345734 arm64_sve-ptrace_Set_SVE_VL_1472 pass
9185 17:01:16.345885 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 skip
9186 17:01:16.346032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
9187 17:01:16.346174 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
9188 17:01:16.346317 arm64_sve-ptrace_Set_SVE_VL_1488 pass
9189 17:01:16.346461 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 skip
9190 17:01:16.346606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
9191 17:01:16.346790 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
9192 17:01:16.346926 arm64_sve-ptrace_Set_SVE_VL_1504 pass
9193 17:01:16.347068 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 skip
9194 17:01:16.347209 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
9195 17:01:16.347350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
9196 17:01:16.347492 arm64_sve-ptrace_Set_SVE_VL_1520 pass
9197 17:01:16.347634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 skip
9198 17:01:16.347778 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
9199 17:01:16.347918 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
9200 17:01:16.348059 arm64_sve-ptrace_Set_SVE_VL_1536 pass
9201 17:01:16.348198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 skip
9202 17:01:16.348338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
9203 17:01:16.348479 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
9204 17:01:16.348656 arm64_sve-ptrace_Set_SVE_VL_1552 pass
9205 17:01:16.348792 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 skip
9206 17:01:16.348932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
9207 17:01:16.349073 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
9208 17:01:16.349214 arm64_sve-ptrace_Set_SVE_VL_1568 pass
9209 17:01:16.349355 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 skip
9210 17:01:16.349495 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
9211 17:01:16.351582 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
9212 17:01:16.351960 arm64_sve-ptrace_Set_SVE_VL_1584 pass
9213 17:01:16.352111 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 skip
9214 17:01:16.352258 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
9215 17:01:16.352401 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
9216 17:01:16.352579 arm64_sve-ptrace_Set_SVE_VL_1600 pass
9217 17:01:16.352716 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 skip
9218 17:01:16.352858 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
9219 17:01:16.353002 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
9220 17:01:16.353143 arm64_sve-ptrace_Set_SVE_VL_1616 pass
9221 17:01:16.353286 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 skip
9222 17:01:16.353464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
9223 17:01:16.353601 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
9224 17:01:16.353772 arm64_sve-ptrace_Set_SVE_VL_1632 pass
9225 17:01:16.353915 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 skip
9226 17:01:16.354057 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
9227 17:01:16.354197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
9228 17:01:16.354340 arm64_sve-ptrace_Set_SVE_VL_1648 pass
9229 17:01:16.354481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 skip
9230 17:01:16.354623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
9231 17:01:16.354807 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
9232 17:01:16.354942 arm64_sve-ptrace_Set_SVE_VL_1664 pass
9233 17:01:16.355083 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 skip
9234 17:01:16.355225 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
9235 17:01:16.355367 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
9236 17:01:16.355508 arm64_sve-ptrace_Set_SVE_VL_1680 pass
9237 17:01:16.355649 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 skip
9238 17:01:16.355792 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
9239 17:01:16.355933 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
9240 17:01:16.356074 arm64_sve-ptrace_Set_SVE_VL_1696 pass
9241 17:01:16.356215 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 skip
9242 17:01:16.356356 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
9243 17:01:16.356498 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
9244 17:01:16.356640 arm64_sve-ptrace_Set_SVE_VL_1712 pass
9245 17:01:16.356780 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 skip
9246 17:01:16.356956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
9247 17:01:16.357094 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
9248 17:01:16.357236 arm64_sve-ptrace_Set_SVE_VL_1728 pass
9249 17:01:16.357594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 skip
9250 17:01:16.357745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
9251 17:01:16.357890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
9252 17:01:16.358033 arm64_sve-ptrace_Set_SVE_VL_1744 pass
9253 17:01:16.373566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 skip
9254 17:01:16.373873 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
9255 17:01:16.374303 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
9256 17:01:16.374506 arm64_sve-ptrace_Set_SVE_VL_1760 pass
9257 17:01:16.374708 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 skip
9258 17:01:16.374927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
9259 17:01:16.375130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
9260 17:01:16.375342 arm64_sve-ptrace_Set_SVE_VL_1776 pass
9261 17:01:16.375512 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 skip
9262 17:01:16.375686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
9263 17:01:16.375859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
9264 17:01:16.376020 arm64_sve-ptrace_Set_SVE_VL_1792 pass
9265 17:01:16.376207 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 skip
9266 17:01:16.376415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
9267 17:01:16.376616 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
9268 17:01:16.376829 arm64_sve-ptrace_Set_SVE_VL_1808 pass
9269 17:01:16.377006 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 skip
9270 17:01:16.377223 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
9271 17:01:16.377421 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
9272 17:01:16.377589 arm64_sve-ptrace_Set_SVE_VL_1824 pass
9273 17:01:16.377761 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 skip
9274 17:01:16.377950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
9275 17:01:16.378130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
9276 17:01:16.378331 arm64_sve-ptrace_Set_SVE_VL_1840 pass
9277 17:01:16.378558 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 skip
9278 17:01:16.378752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
9279 17:01:16.378917 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
9280 17:01:16.379074 arm64_sve-ptrace_Set_SVE_VL_1856 pass
9281 17:01:16.379232 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 skip
9282 17:01:16.379430 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
9283 17:01:16.379606 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
9284 17:01:16.379734 arm64_sve-ptrace_Set_SVE_VL_1872 pass
9285 17:01:16.379850 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 skip
9286 17:01:16.379965 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
9287 17:01:16.380079 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
9288 17:01:16.380192 arm64_sve-ptrace_Set_SVE_VL_1888 pass
9289 17:01:16.380305 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 skip
9290 17:01:16.380417 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
9291 17:01:16.380533 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
9292 17:01:16.380647 arm64_sve-ptrace_Set_SVE_VL_1904 pass
9293 17:01:16.380989 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 skip
9294 17:01:16.381118 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
9295 17:01:16.381238 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
9296 17:01:16.381356 arm64_sve-ptrace_Set_SVE_VL_1920 pass
9297 17:01:16.381472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 skip
9298 17:01:16.381586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
9299 17:01:16.381716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
9300 17:01:16.381831 arm64_sve-ptrace_Set_SVE_VL_1936 pass
9301 17:01:16.381948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 skip
9302 17:01:16.383710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
9303 17:01:16.384038 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
9304 17:01:16.384142 arm64_sve-ptrace_Set_SVE_VL_1952 pass
9305 17:01:16.384231 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 skip
9306 17:01:16.384333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
9307 17:01:16.384422 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
9308 17:01:16.384520 arm64_sve-ptrace_Set_SVE_VL_1968 pass
9309 17:01:16.384822 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 skip
9310 17:01:16.384936 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
9311 17:01:16.385045 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
9312 17:01:16.385133 arm64_sve-ptrace_Set_SVE_VL_1984 pass
9313 17:01:16.385236 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 skip
9314 17:01:16.385338 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
9315 17:01:16.385423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
9316 17:01:16.385517 arm64_sve-ptrace_Set_SVE_VL_2000 pass
9317 17:01:16.385607 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 skip
9318 17:01:16.385745 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
9319 17:01:16.385921 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
9320 17:01:16.386055 arm64_sve-ptrace_Set_SVE_VL_2016 pass
9321 17:01:16.386193 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 skip
9322 17:01:16.386310 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
9323 17:01:16.386443 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
9324 17:01:16.386557 arm64_sve-ptrace_Set_SVE_VL_2032 pass
9325 17:01:16.386698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 skip
9326 17:01:16.386814 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
9327 17:01:16.386945 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
9328 17:01:16.387119 arm64_sve-ptrace_Set_SVE_VL_2048 pass
9329 17:01:16.387259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 skip
9330 17:01:16.387358 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
9331 17:01:16.387465 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
9332 17:01:16.387556 arm64_sve-ptrace_Set_SVE_VL_2064 pass
9333 17:01:16.391854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 skip
9334 17:01:16.392032 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
9335 17:01:16.392192 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
9336 17:01:16.392299 arm64_sve-ptrace_Set_SVE_VL_2080 pass
9337 17:01:16.392407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 skip
9338 17:01:16.392514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
9339 17:01:16.392647 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
9340 17:01:16.392750 arm64_sve-ptrace_Set_SVE_VL_2096 pass
9341 17:01:16.392860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 skip
9342 17:01:16.392992 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
9343 17:01:16.393097 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
9344 17:01:16.393220 arm64_sve-ptrace_Set_SVE_VL_2112 pass
9345 17:01:16.393360 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 skip
9346 17:01:16.393464 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
9347 17:01:16.393581 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
9348 17:01:16.393694 arm64_sve-ptrace_Set_SVE_VL_2128 pass
9349 17:01:16.393823 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 skip
9350 17:01:16.393969 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
9351 17:01:16.394123 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
9352 17:01:16.394230 arm64_sve-ptrace_Set_SVE_VL_2144 pass
9353 17:01:16.394326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 skip
9354 17:01:16.394418 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
9355 17:01:16.394512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
9356 17:01:16.394605 arm64_sve-ptrace_Set_SVE_VL_2160 pass
9357 17:01:16.394718 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 skip
9358 17:01:16.394820 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
9359 17:01:16.394914 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
9360 17:01:16.395013 arm64_sve-ptrace_Set_SVE_VL_2176 pass
9361 17:01:16.395109 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 skip
9362 17:01:16.395206 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
9363 17:01:16.395339 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
9364 17:01:16.395464 arm64_sve-ptrace_Set_SVE_VL_2192 pass
9365 17:01:16.395573 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 skip
9366 17:01:16.395682 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
9367 17:01:16.395788 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
9368 17:01:16.395899 arm64_sve-ptrace_Set_SVE_VL_2208 pass
9369 17:01:16.399674 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 skip
9370 17:01:16.400007 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
9371 17:01:16.400106 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
9372 17:01:16.400196 arm64_sve-ptrace_Set_SVE_VL_2224 pass
9373 17:01:16.400299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 skip
9374 17:01:16.400388 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
9375 17:01:16.400491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
9376 17:01:16.400594 arm64_sve-ptrace_Set_SVE_VL_2240 pass
9377 17:01:16.400696 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 skip
9378 17:01:16.400988 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
9379 17:01:16.401081 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
9380 17:01:16.401186 arm64_sve-ptrace_Set_SVE_VL_2256 pass
9381 17:01:16.401275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 skip
9382 17:01:16.401374 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
9383 17:01:16.401478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
9384 17:01:16.401583 arm64_sve-ptrace_Set_SVE_VL_2272 pass
9385 17:01:16.401901 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 skip
9386 17:01:16.401994 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
9387 17:01:16.402095 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
9388 17:01:16.402182 arm64_sve-ptrace_Set_SVE_VL_2288 pass
9389 17:01:16.402280 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 skip
9390 17:01:16.402601 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
9391 17:01:16.402752 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
9392 17:01:16.402904 arm64_sve-ptrace_Set_SVE_VL_2304 pass
9393 17:01:16.403060 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 skip
9394 17:01:16.403243 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
9395 17:01:16.403484 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
9396 17:01:16.403637 arm64_sve-ptrace_Set_SVE_VL_2320 pass
9397 17:01:16.403758 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 skip
9398 17:01:16.403875 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
9399 17:01:16.403992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
9400 17:01:16.407620 arm64_sve-ptrace_Set_SVE_VL_2336 pass
9401 17:01:16.407942 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 skip
9402 17:01:16.408047 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
9403 17:01:16.408151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
9404 17:01:16.408240 arm64_sve-ptrace_Set_SVE_VL_2352 pass
9405 17:01:16.408326 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 skip
9406 17:01:16.408427 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
9407 17:01:16.408514 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
9408 17:01:16.408616 arm64_sve-ptrace_Set_SVE_VL_2368 pass
9409 17:01:16.408704 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 skip
9410 17:01:16.408790 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
9411 17:01:16.408890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
9412 17:01:16.408978 arm64_sve-ptrace_Set_SVE_VL_2384 pass
9413 17:01:16.424699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 skip
9414 17:01:16.424932 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
9415 17:01:16.425253 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
9416 17:01:16.425363 arm64_sve-ptrace_Set_SVE_VL_2400 pass
9417 17:01:16.425446 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 skip
9418 17:01:16.425619 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
9419 17:01:16.425713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
9420 17:01:16.425817 arm64_sve-ptrace_Set_SVE_VL_2416 pass
9421 17:01:16.425905 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 skip
9422 17:01:16.425986 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
9423 17:01:16.426075 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
9424 17:01:16.426153 arm64_sve-ptrace_Set_SVE_VL_2432 pass
9425 17:01:16.426227 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 skip
9426 17:01:16.426315 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
9427 17:01:16.426414 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
9428 17:01:16.426721 arm64_sve-ptrace_Set_SVE_VL_2448 pass
9429 17:01:16.426825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 skip
9430 17:01:16.426925 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
9431 17:01:16.427027 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
9432 17:01:16.427314 arm64_sve-ptrace_Set_SVE_VL_2464 pass
9433 17:01:16.427428 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 skip
9434 17:01:16.431690 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
9435 17:01:16.432186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
9436 17:01:16.432371 arm64_sve-ptrace_Set_SVE_VL_2480 pass
9437 17:01:16.432577 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 skip
9438 17:01:16.432785 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
9439 17:01:16.432961 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
9440 17:01:16.433125 arm64_sve-ptrace_Set_SVE_VL_2496 pass
9441 17:01:16.433328 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 skip
9442 17:01:16.433563 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
9443 17:01:16.433807 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
9444 17:01:16.434028 arm64_sve-ptrace_Set_SVE_VL_2512 pass
9445 17:01:16.434254 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 skip
9446 17:01:16.434444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
9447 17:01:16.434622 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
9448 17:01:16.434775 arm64_sve-ptrace_Set_SVE_VL_2528 pass
9449 17:01:16.434908 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 skip
9450 17:01:16.435034 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
9451 17:01:16.435219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
9452 17:01:16.435386 arm64_sve-ptrace_Set_SVE_VL_2544 pass
9453 17:01:16.435552 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 skip
9454 17:01:16.435681 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
9455 17:01:16.435798 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
9456 17:01:16.435915 arm64_sve-ptrace_Set_SVE_VL_2560 pass
9457 17:01:16.436036 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 skip
9458 17:01:16.436154 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
9459 17:01:16.436271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
9460 17:01:16.436387 arm64_sve-ptrace_Set_SVE_VL_2576 pass
9461 17:01:16.436503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 skip
9462 17:01:16.436647 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
9463 17:01:16.439627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
9464 17:01:16.440151 arm64_sve-ptrace_Set_SVE_VL_2592 pass
9465 17:01:16.440345 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 skip
9466 17:01:16.440500 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
9467 17:01:16.440700 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
9468 17:01:16.440865 arm64_sve-ptrace_Set_SVE_VL_2608 pass
9469 17:01:16.441104 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 skip
9470 17:01:16.441265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
9471 17:01:16.441418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
9472 17:01:16.441561 arm64_sve-ptrace_Set_SVE_VL_2624 pass
9473 17:01:16.441727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 skip
9474 17:01:16.441875 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
9475 17:01:16.442018 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
9476 17:01:16.442202 arm64_sve-ptrace_Set_SVE_VL_2640 pass
9477 17:01:16.442338 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 skip
9478 17:01:16.442484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
9479 17:01:16.442627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
9480 17:01:16.442770 arm64_sve-ptrace_Set_SVE_VL_2656 pass
9481 17:01:16.442913 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 skip
9482 17:01:16.443054 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
9483 17:01:16.443197 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
9484 17:01:16.443338 arm64_sve-ptrace_Set_SVE_VL_2672 pass
9485 17:01:16.443481 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 skip
9486 17:01:16.443623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
9487 17:01:16.443765 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
9488 17:01:16.443908 arm64_sve-ptrace_Set_SVE_VL_2688 pass
9489 17:01:16.444092 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 skip
9490 17:01:16.444228 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
9491 17:01:16.444369 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
9492 17:01:16.444512 arm64_sve-ptrace_Set_SVE_VL_2704 pass
9493 17:01:16.444652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 skip
9494 17:01:16.444793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
9495 17:01:16.444935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
9496 17:01:16.445077 arm64_sve-ptrace_Set_SVE_VL_2720 pass
9497 17:01:16.445220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 skip
9498 17:01:16.445361 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
9499 17:01:16.445503 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
9500 17:01:16.447606 arm64_sve-ptrace_Set_SVE_VL_2736 pass
9501 17:01:16.447958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 skip
9502 17:01:16.448098 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
9503 17:01:16.448251 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
9504 17:01:16.448412 arm64_sve-ptrace_Set_SVE_VL_2752 pass
9505 17:01:16.448633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 skip
9506 17:01:16.448786 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
9507 17:01:16.448935 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
9508 17:01:16.449103 arm64_sve-ptrace_Set_SVE_VL_2768 pass
9509 17:01:16.449246 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 skip
9510 17:01:16.449392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
9511 17:01:16.449544 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
9512 17:01:16.449699 arm64_sve-ptrace_Set_SVE_VL_2784 pass
9513 17:01:16.449854 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 skip
9514 17:01:16.450024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
9515 17:01:16.450186 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
9516 17:01:16.450319 arm64_sve-ptrace_Set_SVE_VL_2800 pass
9517 17:01:16.450453 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 skip
9518 17:01:16.450579 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
9519 17:01:16.450728 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
9520 17:01:16.450853 arm64_sve-ptrace_Set_SVE_VL_2816 pass
9521 17:01:16.450966 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 skip
9522 17:01:16.451077 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
9523 17:01:16.451189 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
9524 17:01:16.451319 arm64_sve-ptrace_Set_SVE_VL_2832 pass
9525 17:01:16.451471 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 skip
9526 17:01:16.451602 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
9527 17:01:16.451719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
9528 17:01:16.451834 arm64_sve-ptrace_Set_SVE_VL_2848 pass
9529 17:01:16.451948 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 skip
9530 17:01:16.452061 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
9531 17:01:16.452175 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
9532 17:01:16.452292 arm64_sve-ptrace_Set_SVE_VL_2864 pass
9533 17:01:16.452437 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 skip
9534 17:01:16.452561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
9535 17:01:16.452678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
9536 17:01:16.452794 arm64_sve-ptrace_Set_SVE_VL_2880 pass
9537 17:01:16.452907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 skip
9538 17:01:16.453024 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
9539 17:01:16.453350 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
9540 17:01:16.455598 arm64_sve-ptrace_Set_SVE_VL_2896 pass
9541 17:01:16.455903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 skip
9542 17:01:16.456013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
9543 17:01:16.456116 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
9544 17:01:16.456207 arm64_sve-ptrace_Set_SVE_VL_2912 pass
9545 17:01:16.456302 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 skip
9546 17:01:16.456384 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
9547 17:01:16.456476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
9548 17:01:16.456558 arm64_sve-ptrace_Set_SVE_VL_2928 pass
9549 17:01:16.456650 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 skip
9550 17:01:16.456735 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
9551 17:01:16.456829 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
9552 17:01:16.456927 arm64_sve-ptrace_Set_SVE_VL_2944 pass
9553 17:01:16.457010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 skip
9554 17:01:16.457292 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
9555 17:01:16.457390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
9556 17:01:16.457517 arm64_sve-ptrace_Set_SVE_VL_2960 pass
9557 17:01:16.457606 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 skip
9558 17:01:16.457715 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
9559 17:01:16.457804 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
9560 17:01:16.457881 arm64_sve-ptrace_Set_SVE_VL_2976 pass
9561 17:01:16.457960 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 skip
9562 17:01:16.458062 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
9563 17:01:16.458151 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
9564 17:01:16.458236 arm64_sve-ptrace_Set_SVE_VL_2992 pass
9565 17:01:16.458322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 skip
9566 17:01:16.458423 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
9567 17:01:16.458512 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
9568 17:01:16.458597 arm64_sve-ptrace_Set_SVE_VL_3008 pass
9569 17:01:16.458698 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 skip
9570 17:01:16.458787 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
9571 17:01:16.458872 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
9572 17:01:16.458957 arm64_sve-ptrace_Set_SVE_VL_3024 pass
9573 17:01:16.474946 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 skip
9574 17:01:16.475410 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
9575 17:01:16.475509 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
9576 17:01:16.475595 arm64_sve-ptrace_Set_SVE_VL_3040 pass
9577 17:01:16.475682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 skip
9578 17:01:16.475767 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
9579 17:01:16.475850 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
9580 17:01:16.475955 arm64_sve-ptrace_Set_SVE_VL_3056 pass
9581 17:01:16.476048 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 skip
9582 17:01:16.476133 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
9583 17:01:16.476234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
9584 17:01:16.476325 arm64_sve-ptrace_Set_SVE_VL_3072 pass
9585 17:01:16.476427 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 skip
9586 17:01:16.476530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
9587 17:01:16.476821 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
9588 17:01:16.477001 arm64_sve-ptrace_Set_SVE_VL_3088 pass
9589 17:01:16.477096 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 skip
9590 17:01:16.477200 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
9591 17:01:16.477293 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
9592 17:01:16.477580 arm64_sve-ptrace_Set_SVE_VL_3104 pass
9593 17:01:16.477684 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 skip
9594 17:01:16.477806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
9595 17:01:16.477890 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
9596 17:01:16.477988 arm64_sve-ptrace_Set_SVE_VL_3120 pass
9597 17:01:16.478074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 skip
9598 17:01:16.478172 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
9599 17:01:16.478471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
9600 17:01:16.478579 arm64_sve-ptrace_Set_SVE_VL_3136 pass
9601 17:01:16.478682 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 skip
9602 17:01:16.478783 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
9603 17:01:16.478884 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
9604 17:01:16.478993 arm64_sve-ptrace_Set_SVE_VL_3152 pass
9605 17:01:16.479141 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 skip
9606 17:01:16.479397 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
9607 17:01:16.483865 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
9608 17:01:16.484348 arm64_sve-ptrace_Set_SVE_VL_3168 pass
9609 17:01:16.484544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 skip
9610 17:01:16.484711 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
9611 17:01:16.484894 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
9612 17:01:16.485059 arm64_sve-ptrace_Set_SVE_VL_3184 pass
9613 17:01:16.485243 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 skip
9614 17:01:16.485468 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
9615 17:01:16.485718 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
9616 17:01:16.485951 arm64_sve-ptrace_Set_SVE_VL_3200 pass
9617 17:01:16.486176 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 skip
9618 17:01:16.486386 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
9619 17:01:16.486567 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
9620 17:01:16.486734 arm64_sve-ptrace_Set_SVE_VL_3216 pass
9621 17:01:16.486941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 skip
9622 17:01:16.487114 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
9623 17:01:16.487294 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
9624 17:01:16.487505 arm64_sve-ptrace_Set_SVE_VL_3232 pass
9625 17:01:16.487655 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 skip
9626 17:01:16.487774 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
9627 17:01:16.487891 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
9628 17:01:16.488008 arm64_sve-ptrace_Set_SVE_VL_3248 pass
9629 17:01:16.488153 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 skip
9630 17:01:16.488277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
9631 17:01:16.488394 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
9632 17:01:16.488509 arm64_sve-ptrace_Set_SVE_VL_3264 pass
9633 17:01:16.488623 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 skip
9634 17:01:16.491736 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
9635 17:01:16.492131 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
9636 17:01:16.492235 arm64_sve-ptrace_Set_SVE_VL_3280 pass
9637 17:01:16.492322 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 skip
9638 17:01:16.492407 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
9639 17:01:16.492508 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
9640 17:01:16.492595 arm64_sve-ptrace_Set_SVE_VL_3296 pass
9641 17:01:16.492677 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 skip
9642 17:01:16.493894 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
9643 17:01:16.493997 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
9644 17:01:16.494083 arm64_sve-ptrace_Set_SVE_VL_3312 pass
9645 17:01:16.494167 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 skip
9646 17:01:16.494251 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
9647 17:01:16.494330 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
9648 17:01:16.494408 arm64_sve-ptrace_Set_SVE_VL_3328 pass
9649 17:01:16.494482 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 skip
9650 17:01:16.494555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
9651 17:01:16.494627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
9652 17:01:16.494707 arm64_sve-ptrace_Set_SVE_VL_3344 pass
9653 17:01:16.494785 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 skip
9654 17:01:16.494860 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
9655 17:01:16.494934 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
9656 17:01:16.495215 arm64_sve-ptrace_Set_SVE_VL_3360 pass
9657 17:01:16.495358 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 skip
9658 17:01:16.495447 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
9659 17:01:16.495524 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
9660 17:01:16.495606 arm64_sve-ptrace_Set_SVE_VL_3376 pass
9661 17:01:16.495690 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 skip
9662 17:01:16.495770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
9663 17:01:16.495848 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
9664 17:01:16.495923 arm64_sve-ptrace_Set_SVE_VL_3392 pass
9665 17:01:16.495997 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 skip
9666 17:01:16.496072 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
9667 17:01:16.496167 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
9668 17:01:16.499719 arm64_sve-ptrace_Set_SVE_VL_3408 pass
9669 17:01:16.500099 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 skip
9670 17:01:16.500299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
9671 17:01:16.500478 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
9672 17:01:16.500719 arm64_sve-ptrace_Set_SVE_VL_3424 pass
9673 17:01:16.500918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 skip
9674 17:01:16.501101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
9675 17:01:16.501271 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
9676 17:01:16.501414 arm64_sve-ptrace_Set_SVE_VL_3440 pass
9677 17:01:16.501605 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 skip
9678 17:01:16.501834 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
9679 17:01:16.502016 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
9680 17:01:16.502185 arm64_sve-ptrace_Set_SVE_VL_3456 pass
9681 17:01:16.502346 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 skip
9682 17:01:16.502507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
9683 17:01:16.502645 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
9684 17:01:16.502861 arm64_sve-ptrace_Set_SVE_VL_3472 pass
9685 17:01:16.503074 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 skip
9686 17:01:16.503260 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
9687 17:01:16.503488 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
9688 17:01:16.503615 arm64_sve-ptrace_Set_SVE_VL_3488 pass
9689 17:01:16.503729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 skip
9690 17:01:16.503841 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
9691 17:01:16.503956 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
9692 17:01:16.504069 arm64_sve-ptrace_Set_SVE_VL_3504 pass
9693 17:01:16.504184 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 skip
9694 17:01:16.504298 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
9695 17:01:16.504442 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
9696 17:01:16.504564 arm64_sve-ptrace_Set_SVE_VL_3520 pass
9697 17:01:16.504681 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 skip
9698 17:01:16.507624 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
9699 17:01:16.508091 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
9700 17:01:16.508284 arm64_sve-ptrace_Set_SVE_VL_3536 pass
9701 17:01:16.508444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 skip
9702 17:01:16.508721 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
9703 17:01:16.508944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
9704 17:01:16.509144 arm64_sve-ptrace_Set_SVE_VL_3552 pass
9705 17:01:16.509339 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 skip
9706 17:01:16.509509 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
9707 17:01:16.509738 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
9708 17:01:16.509966 arm64_sve-ptrace_Set_SVE_VL_3568 pass
9709 17:01:16.510189 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 skip
9710 17:01:16.510373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
9711 17:01:16.510538 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
9712 17:01:16.510702 arm64_sve-ptrace_Set_SVE_VL_3584 pass
9713 17:01:16.510855 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 skip
9714 17:01:16.511055 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
9715 17:01:16.511226 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
9716 17:01:16.511395 arm64_sve-ptrace_Set_SVE_VL_3600 pass
9717 17:01:16.511521 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 skip
9718 17:01:16.511637 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
9719 17:01:16.511750 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
9720 17:01:16.511865 arm64_sve-ptrace_Set_SVE_VL_3616 pass
9721 17:01:16.511979 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 skip
9722 17:01:16.512093 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
9723 17:01:16.512208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
9724 17:01:16.512321 arm64_sve-ptrace_Set_SVE_VL_3632 pass
9725 17:01:16.512463 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 skip
9726 17:01:16.512582 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
9727 17:01:16.515800 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
9728 17:01:16.516245 arm64_sve-ptrace_Set_SVE_VL_3648 pass
9729 17:01:16.516350 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 skip
9730 17:01:16.516437 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
9731 17:01:16.516537 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
9732 17:01:16.516623 arm64_sve-ptrace_Set_SVE_VL_3664 pass
9733 17:01:16.530720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 skip
9734 17:01:16.531392 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
9735 17:01:16.531558 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
9736 17:01:16.531713 arm64_sve-ptrace_Set_SVE_VL_3680 pass
9737 17:01:16.531860 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 skip
9738 17:01:16.532049 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
9739 17:01:16.532222 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
9740 17:01:16.532367 arm64_sve-ptrace_Set_SVE_VL_3696 pass
9741 17:01:16.532517 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 skip
9742 17:01:16.532696 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
9743 17:01:16.532859 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
9744 17:01:16.533015 arm64_sve-ptrace_Set_SVE_VL_3712 pass
9745 17:01:16.533201 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 skip
9746 17:01:16.533357 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
9747 17:01:16.533482 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
9748 17:01:16.533635 arm64_sve-ptrace_Set_SVE_VL_3728 pass
9749 17:01:16.533766 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 skip
9750 17:01:16.533880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
9751 17:01:16.534012 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
9752 17:01:16.534129 arm64_sve-ptrace_Set_SVE_VL_3744 pass
9753 17:01:16.534265 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 skip
9754 17:01:16.534445 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
9755 17:01:16.534602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
9756 17:01:16.534787 arm64_sve-ptrace_Set_SVE_VL_3760 pass
9757 17:01:16.534941 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 skip
9758 17:01:16.535116 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
9759 17:01:16.535277 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
9760 17:01:16.535430 arm64_sve-ptrace_Set_SVE_VL_3776 pass
9761 17:01:16.535576 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 skip
9762 17:01:16.535698 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
9763 17:01:16.539755 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
9764 17:01:16.540252 arm64_sve-ptrace_Set_SVE_VL_3792 pass
9765 17:01:16.540430 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 skip
9766 17:01:16.540573 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
9767 17:01:16.540758 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
9768 17:01:16.540896 arm64_sve-ptrace_Set_SVE_VL_3808 pass
9769 17:01:16.541014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 skip
9770 17:01:16.541164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
9771 17:01:16.541325 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
9772 17:01:16.541503 arm64_sve-ptrace_Set_SVE_VL_3824 pass
9773 17:01:16.541693 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 skip
9774 17:01:16.541880 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
9775 17:01:16.542042 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
9776 17:01:16.542216 arm64_sve-ptrace_Set_SVE_VL_3840 pass
9777 17:01:16.542374 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 skip
9778 17:01:16.542553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
9779 17:01:16.542730 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
9780 17:01:16.542881 arm64_sve-ptrace_Set_SVE_VL_3856 pass
9781 17:01:16.543029 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 skip
9782 17:01:16.543229 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
9783 17:01:16.543390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
9784 17:01:16.543540 arm64_sve-ptrace_Set_SVE_VL_3872 pass
9785 17:01:16.543710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 skip
9786 17:01:16.543894 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
9787 17:01:16.544049 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
9788 17:01:16.547713 arm64_sve-ptrace_Set_SVE_VL_3888 pass
9789 17:01:16.548238 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 skip
9790 17:01:16.548425 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
9791 17:01:16.548599 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
9792 17:01:16.548759 arm64_sve-ptrace_Set_SVE_VL_3904 pass
9793 17:01:16.548940 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 skip
9794 17:01:16.549114 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
9795 17:01:16.549272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
9796 17:01:16.549417 arm64_sve-ptrace_Set_SVE_VL_3920 pass
9797 17:01:16.549582 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 skip
9798 17:01:16.549755 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
9799 17:01:16.549938 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
9800 17:01:16.550113 arm64_sve-ptrace_Set_SVE_VL_3936 pass
9801 17:01:16.550270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 skip
9802 17:01:16.550415 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
9803 17:01:16.550580 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
9804 17:01:16.550741 arm64_sve-ptrace_Set_SVE_VL_3952 pass
9805 17:01:16.550925 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 skip
9806 17:01:16.551102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
9807 17:01:16.551257 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
9808 17:01:16.551410 arm64_sve-ptrace_Set_SVE_VL_3968 pass
9809 17:01:16.551566 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 skip
9810 17:01:16.551714 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
9811 17:01:16.551877 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
9812 17:01:16.552022 arm64_sve-ptrace_Set_SVE_VL_3984 pass
9813 17:01:16.552170 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 skip
9814 17:01:16.552360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
9815 17:01:16.552511 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
9816 17:01:16.552671 arm64_sve-ptrace_Set_SVE_VL_4000 pass
9817 17:01:16.552810 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 skip
9818 17:01:16.555710 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
9819 17:01:16.556177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
9820 17:01:16.557727 arm64_sve-ptrace_Set_SVE_VL_4016 pass
9821 17:01:16.557828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 skip
9822 17:01:16.557907 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
9823 17:01:16.557985 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
9824 17:01:16.558060 arm64_sve-ptrace_Set_SVE_VL_4032 pass
9825 17:01:16.558137 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 skip
9826 17:01:16.558213 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
9827 17:01:16.558288 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
9828 17:01:16.558367 arm64_sve-ptrace_Set_SVE_VL_4048 pass
9829 17:01:16.558440 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 skip
9830 17:01:16.558514 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
9831 17:01:16.558598 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
9832 17:01:16.558675 arm64_sve-ptrace_Set_SVE_VL_4064 pass
9833 17:01:16.558749 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 skip
9834 17:01:16.558826 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
9835 17:01:16.558904 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
9836 17:01:16.558982 arm64_sve-ptrace_Set_SVE_VL_4080 pass
9837 17:01:16.559060 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 skip
9838 17:01:16.559140 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
9839 17:01:16.559213 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
9840 17:01:16.559476 arm64_sve-ptrace_Set_SVE_VL_4096 pass
9841 17:01:16.559580 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 skip
9842 17:01:16.559666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
9843 17:01:16.559747 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
9844 17:01:16.559827 arm64_sve-ptrace_Set_SVE_VL_4112 pass
9845 17:01:16.559903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 skip
9846 17:01:16.559983 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
9847 17:01:16.560067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
9848 17:01:16.560152 arm64_sve-ptrace_Set_SVE_VL_4128 pass
9849 17:01:16.560233 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 skip
9850 17:01:16.560316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
9851 17:01:16.560400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
9852 17:01:16.560488 arm64_sve-ptrace_Set_SVE_VL_4144 pass
9853 17:01:16.560575 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 skip
9854 17:01:16.560661 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
9855 17:01:16.560750 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
9856 17:01:16.560837 arm64_sve-ptrace_Set_SVE_VL_4160 pass
9857 17:01:16.563696 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 skip
9858 17:01:16.564087 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
9859 17:01:16.564215 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
9860 17:01:16.564309 arm64_sve-ptrace_Set_SVE_VL_4176 pass
9861 17:01:16.564416 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 skip
9862 17:01:16.564508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
9863 17:01:16.564595 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
9864 17:01:16.564704 arm64_sve-ptrace_Set_SVE_VL_4192 pass
9865 17:01:16.564815 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 skip
9866 17:01:16.564923 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
9867 17:01:16.565031 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
9868 17:01:16.565123 arm64_sve-ptrace_Set_SVE_VL_4208 pass
9869 17:01:16.565251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 skip
9870 17:01:16.565373 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
9871 17:01:16.565466 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
9872 17:01:16.565556 arm64_sve-ptrace_Set_SVE_VL_4224 pass
9873 17:01:16.565671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 skip
9874 17:01:16.565773 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
9875 17:01:16.565912 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
9876 17:01:16.566009 arm64_sve-ptrace_Set_SVE_VL_4240 pass
9877 17:01:16.566097 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 skip
9878 17:01:16.566183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
9879 17:01:16.566287 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
9880 17:01:16.566378 arm64_sve-ptrace_Set_SVE_VL_4256 pass
9881 17:01:16.566465 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 skip
9882 17:01:16.566551 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
9883 17:01:16.566839 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
9884 17:01:16.566934 arm64_sve-ptrace_Set_SVE_VL_4272 pass
9885 17:01:16.567022 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 skip
9886 17:01:16.567128 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
9887 17:01:16.567221 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
9888 17:01:16.567314 arm64_sve-ptrace_Set_SVE_VL_4288 pass
9889 17:01:16.567400 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 skip
9890 17:01:16.567487 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
9891 17:01:16.567573 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
9892 17:01:16.567659 arm64_sve-ptrace_Set_SVE_VL_4304 pass
9893 17:01:16.585256 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 skip
9894 17:01:16.585546 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
9895 17:01:16.585944 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
9896 17:01:16.586093 arm64_sve-ptrace_Set_SVE_VL_4320 pass
9897 17:01:16.586223 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 skip
9898 17:01:16.586350 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
9899 17:01:16.586477 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
9900 17:01:16.586626 arm64_sve-ptrace_Set_SVE_VL_4336 pass
9901 17:01:16.586753 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 skip
9902 17:01:16.586901 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
9903 17:01:16.587035 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
9904 17:01:16.587159 arm64_sve-ptrace_Set_SVE_VL_4352 pass
9905 17:01:16.587313 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 skip
9906 17:01:16.587456 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
9907 17:01:16.587585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
9908 17:01:16.587703 arm64_sve-ptrace_Set_SVE_VL_4368 pass
9909 17:01:16.587799 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 skip
9910 17:01:16.587896 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
9911 17:01:16.588017 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
9912 17:01:16.588154 arm64_sve-ptrace_Set_SVE_VL_4384 pass
9913 17:01:16.588353 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 skip
9914 17:01:16.588556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
9915 17:01:16.588721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
9916 17:01:16.588863 arm64_sve-ptrace_Set_SVE_VL_4400 pass
9917 17:01:16.588982 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 skip
9918 17:01:16.589123 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
9919 17:01:16.589314 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
9920 17:01:16.589472 arm64_sve-ptrace_Set_SVE_VL_4416 pass
9921 17:01:16.589620 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 skip
9922 17:01:16.590482 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
9923 17:01:16.590678 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
9924 17:01:16.590841 arm64_sve-ptrace_Set_SVE_VL_4432 pass
9925 17:01:16.590999 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 skip
9926 17:01:16.591164 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
9927 17:01:16.591320 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
9928 17:01:16.591465 arm64_sve-ptrace_Set_SVE_VL_4448 pass
9929 17:01:16.591627 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 skip
9930 17:01:16.591787 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
9931 17:01:16.591897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
9932 17:01:16.592191 arm64_sve-ptrace_Set_SVE_VL_4464 pass
9933 17:01:16.592281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 skip
9934 17:01:16.592347 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
9935 17:01:16.592408 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
9936 17:01:16.592468 arm64_sve-ptrace_Set_SVE_VL_4480 pass
9937 17:01:16.592529 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 skip
9938 17:01:16.592589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
9939 17:01:16.592648 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
9940 17:01:16.599695 arm64_sve-ptrace_Set_SVE_VL_4496 pass
9941 17:01:16.600244 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 skip
9942 17:01:16.600465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
9943 17:01:16.600677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
9944 17:01:16.600867 arm64_sve-ptrace_Set_SVE_VL_4512 pass
9945 17:01:16.601069 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 skip
9946 17:01:16.601265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
9947 17:01:16.601471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
9948 17:01:16.601690 arm64_sve-ptrace_Set_SVE_VL_4528 pass
9949 17:01:16.601898 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 skip
9950 17:01:16.602141 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
9951 17:01:16.602333 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
9952 17:01:16.602530 arm64_sve-ptrace_Set_SVE_VL_4544 pass
9953 17:01:16.602723 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 skip
9954 17:01:16.602909 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
9955 17:01:16.603049 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
9956 17:01:16.603186 arm64_sve-ptrace_Set_SVE_VL_4560 pass
9957 17:01:16.603359 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 skip
9958 17:01:16.604017 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
9959 17:01:16.604208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
9960 17:01:16.604383 arm64_sve-ptrace_Set_SVE_VL_4576 pass
9961 17:01:16.604543 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 skip
9962 17:01:16.604687 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
9963 17:01:16.605715 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
9964 17:01:16.605919 arm64_sve-ptrace_Set_SVE_VL_4592 pass
9965 17:01:16.606082 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 skip
9966 17:01:16.606247 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
9967 17:01:16.606411 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
9968 17:01:16.606608 arm64_sve-ptrace_Set_SVE_VL_4608 pass
9969 17:01:16.606825 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 skip
9970 17:01:16.606973 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
9971 17:01:16.607130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
9972 17:01:16.607248 arm64_sve-ptrace_Set_SVE_VL_4624 pass
9973 17:01:16.607381 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 skip
9974 17:01:16.607510 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
9975 17:01:16.607624 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
9976 17:01:16.607736 arm64_sve-ptrace_Set_SVE_VL_4640 pass
9977 17:01:16.607848 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 skip
9978 17:01:16.607967 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
9979 17:01:16.608330 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
9980 17:01:16.608493 arm64_sve-ptrace_Set_SVE_VL_4656 pass
9981 17:01:16.608619 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 skip
9982 17:01:16.608740 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
9983 17:01:16.608857 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
9984 17:01:16.608972 arm64_sve-ptrace_Set_SVE_VL_4672 pass
9985 17:01:16.609089 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 skip
9986 17:01:16.609249 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
9987 17:01:16.609386 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
9988 17:01:16.609505 arm64_sve-ptrace_Set_SVE_VL_4688 pass
9989 17:01:16.609623 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 skip
9990 17:01:16.609757 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
9991 17:01:16.609874 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
9992 17:01:16.610004 arm64_sve-ptrace_Set_SVE_VL_4704 pass
9993 17:01:16.610124 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 skip
9994 17:01:16.610244 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
9995 17:01:16.610366 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
9996 17:01:16.610485 arm64_sve-ptrace_Set_SVE_VL_4720 pass
9997 17:01:16.610600 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 skip
9998 17:01:16.610717 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
9999 17:01:16.611608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
10000 17:01:16.612155 arm64_sve-ptrace_Set_SVE_VL_4736 pass
10001 17:01:16.612360 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 skip
10002 17:01:16.612520 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
10003 17:01:16.612692 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
10004 17:01:16.612857 arm64_sve-ptrace_Set_SVE_VL_4752 pass
10005 17:01:16.613020 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 skip
10006 17:01:16.613195 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
10007 17:01:16.613446 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
10008 17:01:16.613613 arm64_sve-ptrace_Set_SVE_VL_4768 pass
10009 17:01:16.613796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 skip
10010 17:01:16.613967 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
10011 17:01:16.614181 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
10012 17:01:16.614335 arm64_sve-ptrace_Set_SVE_VL_4784 pass
10013 17:01:16.614506 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 skip
10014 17:01:16.614694 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
10015 17:01:16.614824 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
10016 17:01:16.614985 arm64_sve-ptrace_Set_SVE_VL_4800 pass
10017 17:01:16.615148 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 skip
10018 17:01:16.615304 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
10019 17:01:16.615448 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
10020 17:01:16.615576 arm64_sve-ptrace_Set_SVE_VL_4816 pass
10021 17:01:16.615720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 skip
10022 17:01:16.615844 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
10023 17:01:16.615960 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
10024 17:01:16.616075 arm64_sve-ptrace_Set_SVE_VL_4832 pass
10025 17:01:16.616197 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 skip
10026 17:01:16.616316 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
10027 17:01:16.623735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
10028 17:01:16.624026 arm64_sve-ptrace_Set_SVE_VL_4848 pass
10029 17:01:16.624464 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 skip
10030 17:01:16.624665 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
10031 17:01:16.624883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
10032 17:01:16.625101 arm64_sve-ptrace_Set_SVE_VL_4864 pass
10033 17:01:16.625367 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 skip
10034 17:01:16.625589 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
10035 17:01:16.625835 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
10036 17:01:16.626039 arm64_sve-ptrace_Set_SVE_VL_4880 pass
10037 17:01:16.626220 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 skip
10038 17:01:16.626423 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
10039 17:01:16.626600 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
10040 17:01:16.626800 arm64_sve-ptrace_Set_SVE_VL_4896 pass
10041 17:01:16.626980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 skip
10042 17:01:16.627135 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
10043 17:01:16.627256 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
10044 17:01:16.627378 arm64_sve-ptrace_Set_SVE_VL_4912 pass
10045 17:01:16.627493 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 skip
10046 17:01:16.627606 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
10047 17:01:16.627719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
10048 17:01:16.627834 arm64_sve-ptrace_Set_SVE_VL_4928 pass
10049 17:01:16.627976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 skip
10050 17:01:16.628100 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
10051 17:01:16.628216 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
10052 17:01:16.628333 arm64_sve-ptrace_Set_SVE_VL_4944 pass
10053 17:01:16.645105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 skip
10054 17:01:16.645707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
10055 17:01:16.645796 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
10056 17:01:16.645902 arm64_sve-ptrace_Set_SVE_VL_4960 pass
10057 17:01:16.646010 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 skip
10058 17:01:16.646101 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
10059 17:01:16.646200 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
10060 17:01:16.646320 arm64_sve-ptrace_Set_SVE_VL_4976 pass
10061 17:01:16.646406 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 skip
10062 17:01:16.646476 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
10063 17:01:16.646557 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
10064 17:01:16.646630 arm64_sve-ptrace_Set_SVE_VL_4992 pass
10065 17:01:16.646720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 skip
10066 17:01:16.646806 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
10067 17:01:16.646902 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
10068 17:01:16.646987 arm64_sve-ptrace_Set_SVE_VL_5008 pass
10069 17:01:16.647086 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 skip
10070 17:01:16.647485 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
10071 17:01:16.647608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
10072 17:01:16.647807 arm64_sve-ptrace_Set_SVE_VL_5024 pass
10073 17:01:16.647945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 skip
10074 17:01:16.648076 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
10075 17:01:16.648217 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
10076 17:01:16.648334 arm64_sve-ptrace_Set_SVE_VL_5040 pass
10077 17:01:16.648472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 skip
10078 17:01:16.648614 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
10079 17:01:16.648735 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
10080 17:01:16.649105 arm64_sve-ptrace_Set_SVE_VL_5056 pass
10081 17:01:16.649253 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 skip
10082 17:01:16.649409 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
10083 17:01:16.649525 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
10084 17:01:16.649680 arm64_sve-ptrace_Set_SVE_VL_5072 pass
10085 17:01:16.649813 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 skip
10086 17:01:16.649991 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
10087 17:01:16.650130 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
10088 17:01:16.650279 arm64_sve-ptrace_Set_SVE_VL_5088 pass
10089 17:01:16.650413 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 skip
10090 17:01:16.650560 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
10091 17:01:16.650689 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
10092 17:01:16.650830 arm64_sve-ptrace_Set_SVE_VL_5104 pass
10093 17:01:16.650977 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 skip
10094 17:01:16.651114 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
10095 17:01:16.651244 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
10096 17:01:16.651354 arm64_sve-ptrace_Set_SVE_VL_5120 pass
10097 17:01:16.651459 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 skip
10098 17:01:16.655793 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
10099 17:01:16.655923 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
10100 17:01:16.656043 arm64_sve-ptrace_Set_SVE_VL_5136 pass
10101 17:01:16.656132 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 skip
10102 17:01:16.656231 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
10103 17:01:16.656333 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
10104 17:01:16.656434 arm64_sve-ptrace_Set_SVE_VL_5152 pass
10105 17:01:16.656521 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 skip
10106 17:01:16.656621 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
10107 17:01:16.656722 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
10108 17:01:16.656808 arm64_sve-ptrace_Set_SVE_VL_5168 pass
10109 17:01:16.656908 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 skip
10110 17:01:16.657009 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
10111 17:01:16.657110 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
10112 17:01:16.657208 arm64_sve-ptrace_Set_SVE_VL_5184 pass
10113 17:01:16.657289 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 skip
10114 17:01:16.657382 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
10115 17:01:16.657476 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
10116 17:01:16.657572 arm64_sve-ptrace_Set_SVE_VL_5200 pass
10117 17:01:16.657676 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 skip
10118 17:01:16.657770 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
10119 17:01:16.658060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
10120 17:01:16.658154 arm64_sve-ptrace_Set_SVE_VL_5216 pass
10121 17:01:16.658242 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 skip
10122 17:01:16.658349 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
10123 17:01:16.658438 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
10124 17:01:16.658524 arm64_sve-ptrace_Set_SVE_VL_5232 pass
10125 17:01:16.658625 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 skip
10126 17:01:16.658713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
10127 17:01:16.658816 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
10128 17:01:16.658904 arm64_sve-ptrace_Set_SVE_VL_5248 pass
10129 17:01:16.658990 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 skip
10130 17:01:16.659092 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
10131 17:01:16.659180 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
10132 17:01:16.659266 arm64_sve-ptrace_Set_SVE_VL_5264 pass
10133 17:01:16.659377 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 skip
10134 17:01:16.659466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
10135 17:01:16.659552 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
10136 17:01:16.663759 arm64_sve-ptrace_Set_SVE_VL_5280 pass
10137 17:01:16.663922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 skip
10138 17:01:16.664217 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
10139 17:01:16.664321 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
10140 17:01:16.664406 arm64_sve-ptrace_Set_SVE_VL_5296 pass
10141 17:01:16.664487 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 skip
10142 17:01:16.664572 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
10143 17:01:16.664677 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
10144 17:01:16.664768 arm64_sve-ptrace_Set_SVE_VL_5312 pass
10145 17:01:16.664855 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 skip
10146 17:01:16.664943 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
10147 17:01:16.665032 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
10148 17:01:16.665139 arm64_sve-ptrace_Set_SVE_VL_5328 pass
10149 17:01:16.665222 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 skip
10150 17:01:16.665299 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
10151 17:01:16.665374 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
10152 17:01:16.665451 arm64_sve-ptrace_Set_SVE_VL_5344 pass
10153 17:01:16.665543 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 skip
10154 17:01:16.665622 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
10155 17:01:16.665713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
10156 17:01:16.665787 arm64_sve-ptrace_Set_SVE_VL_5360 pass
10157 17:01:16.665865 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 skip
10158 17:01:16.665959 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
10159 17:01:16.666046 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
10160 17:01:16.666134 arm64_sve-ptrace_Set_SVE_VL_5376 pass
10161 17:01:16.666234 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 skip
10162 17:01:16.666324 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
10163 17:01:16.666428 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
10164 17:01:16.666513 arm64_sve-ptrace_Set_SVE_VL_5392 pass
10165 17:01:16.666610 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 skip
10166 17:01:16.666709 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
10167 17:01:16.667020 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
10168 17:01:16.667125 arm64_sve-ptrace_Set_SVE_VL_5408 pass
10169 17:01:16.667224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 skip
10170 17:01:16.667323 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
10171 17:01:16.671685 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
10172 17:01:16.672224 arm64_sve-ptrace_Set_SVE_VL_5424 pass
10173 17:01:16.672407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 skip
10174 17:01:16.672552 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
10175 17:01:16.672717 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
10176 17:01:16.672937 arm64_sve-ptrace_Set_SVE_VL_5440 pass
10177 17:01:16.673103 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 skip
10178 17:01:16.673266 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
10179 17:01:16.673385 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
10180 17:01:16.673491 arm64_sve-ptrace_Set_SVE_VL_5456 pass
10181 17:01:16.673633 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 skip
10182 17:01:16.673815 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
10183 17:01:16.673943 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
10184 17:01:16.674062 arm64_sve-ptrace_Set_SVE_VL_5472 pass
10185 17:01:16.674185 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 skip
10186 17:01:16.674322 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
10187 17:01:16.674449 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
10188 17:01:16.674579 arm64_sve-ptrace_Set_SVE_VL_5488 pass
10189 17:01:16.674732 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 skip
10190 17:01:16.674853 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
10191 17:01:16.674953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
10192 17:01:16.675054 arm64_sve-ptrace_Set_SVE_VL_5504 pass
10193 17:01:16.675202 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 skip
10194 17:01:16.675351 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
10195 17:01:16.675460 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
10196 17:01:16.675550 arm64_sve-ptrace_Set_SVE_VL_5520 pass
10197 17:01:16.675659 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 skip
10198 17:01:16.675752 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
10199 17:01:16.675840 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
10200 17:01:16.675927 arm64_sve-ptrace_Set_SVE_VL_5536 pass
10201 17:01:16.676014 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 skip
10202 17:01:16.679586 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
10203 17:01:16.679963 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
10204 17:01:16.680075 arm64_sve-ptrace_Set_SVE_VL_5552 pass
10205 17:01:16.680162 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 skip
10206 17:01:16.680451 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
10207 17:01:16.680556 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
10208 17:01:16.680639 arm64_sve-ptrace_Set_SVE_VL_5568 pass
10209 17:01:16.680735 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 skip
10210 17:01:16.680818 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
10211 17:01:16.680898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
10212 17:01:16.680978 arm64_sve-ptrace_Set_SVE_VL_5584 pass
10213 17:01:16.696675 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 skip
10214 17:01:16.696905 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
10215 17:01:16.697219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
10216 17:01:16.697326 arm64_sve-ptrace_Set_SVE_VL_5600 pass
10217 17:01:16.697433 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 skip
10218 17:01:16.697544 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
10219 17:01:16.697656 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
10220 17:01:16.697774 arm64_sve-ptrace_Set_SVE_VL_5616 pass
10221 17:01:16.697873 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 skip
10222 17:01:16.697974 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
10223 17:01:16.698069 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
10224 17:01:16.698147 arm64_sve-ptrace_Set_SVE_VL_5632 pass
10225 17:01:16.698258 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 skip
10226 17:01:16.698364 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
10227 17:01:16.698471 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
10228 17:01:16.698564 arm64_sve-ptrace_Set_SVE_VL_5648 pass
10229 17:01:16.698670 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 skip
10230 17:01:16.698760 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
10231 17:01:16.698826 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
10232 17:01:16.698916 arm64_sve-ptrace_Set_SVE_VL_5664 pass
10233 17:01:16.699032 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 skip
10234 17:01:16.699117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
10235 17:01:16.699219 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
10236 17:01:16.699319 arm64_sve-ptrace_Set_SVE_VL_5680 pass
10237 17:01:16.699413 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 skip
10238 17:01:16.699522 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
10239 17:01:16.703608 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
10240 17:01:16.704076 arm64_sve-ptrace_Set_SVE_VL_5696 pass
10241 17:01:16.704279 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 skip
10242 17:01:16.704465 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
10243 17:01:16.704655 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
10244 17:01:16.704828 arm64_sve-ptrace_Set_SVE_VL_5712 pass
10245 17:01:16.705024 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 skip
10246 17:01:16.705204 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
10247 17:01:16.705391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
10248 17:01:16.705590 arm64_sve-ptrace_Set_SVE_VL_5728 pass
10249 17:01:16.705796 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 skip
10250 17:01:16.705953 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
10251 17:01:16.706083 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
10252 17:01:16.706215 arm64_sve-ptrace_Set_SVE_VL_5744 pass
10253 17:01:16.706396 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 skip
10254 17:01:16.706553 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
10255 17:01:16.706719 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
10256 17:01:16.706888 arm64_sve-ptrace_Set_SVE_VL_5760 pass
10257 17:01:16.707085 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 skip
10258 17:01:16.707277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
10259 17:01:16.707463 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
10260 17:01:16.707606 arm64_sve-ptrace_Set_SVE_VL_5776 pass
10261 17:01:16.707721 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 skip
10262 17:01:16.707835 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
10263 17:01:16.707946 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
10264 17:01:16.708056 arm64_sve-ptrace_Set_SVE_VL_5792 pass
10265 17:01:16.708198 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 skip
10266 17:01:16.708317 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
10267 17:01:16.708430 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
10268 17:01:16.708541 arm64_sve-ptrace_Set_SVE_VL_5808 pass
10269 17:01:16.708652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 skip
10270 17:01:16.708763 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
10271 17:01:16.708875 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
10272 17:01:16.708985 arm64_sve-ptrace_Set_SVE_VL_5824 pass
10273 17:01:16.709095 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 skip
10274 17:01:16.711641 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
10275 17:01:16.712089 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
10276 17:01:16.712287 arm64_sve-ptrace_Set_SVE_VL_5840 pass
10277 17:01:16.712420 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 skip
10278 17:01:16.712555 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
10279 17:01:16.712695 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
10280 17:01:16.712814 arm64_sve-ptrace_Set_SVE_VL_5856 pass
10281 17:01:16.712916 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 skip
10282 17:01:16.713014 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
10283 17:01:16.713109 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
10284 17:01:16.713233 arm64_sve-ptrace_Set_SVE_VL_5872 pass
10285 17:01:16.713380 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 skip
10286 17:01:16.713524 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
10287 17:01:16.713681 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
10288 17:01:16.713815 arm64_sve-ptrace_Set_SVE_VL_5888 pass
10289 17:01:16.713968 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 skip
10290 17:01:16.714136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
10291 17:01:16.714266 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
10292 17:01:16.714384 arm64_sve-ptrace_Set_SVE_VL_5904 pass
10293 17:01:16.714495 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 skip
10294 17:01:16.714611 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
10295 17:01:16.714703 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
10296 17:01:16.714793 arm64_sve-ptrace_Set_SVE_VL_5920 pass
10297 17:01:16.714895 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 skip
10298 17:01:16.714980 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
10299 17:01:16.715082 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
10300 17:01:16.715169 arm64_sve-ptrace_Set_SVE_VL_5936 pass
10301 17:01:16.715266 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 skip
10302 17:01:16.715360 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
10303 17:01:16.715480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
10304 17:01:16.719647 arm64_sve-ptrace_Set_SVE_VL_5952 pass
10305 17:01:16.719845 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 skip
10306 17:01:16.720246 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
10307 17:01:16.720346 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
10308 17:01:16.720467 arm64_sve-ptrace_Set_SVE_VL_5968 pass
10309 17:01:16.720661 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 skip
10310 17:01:16.720859 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
10311 17:01:16.721112 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
10312 17:01:16.721319 arm64_sve-ptrace_Set_SVE_VL_5984 pass
10313 17:01:16.721503 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 skip
10314 17:01:16.721724 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
10315 17:01:16.721897 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
10316 17:01:16.722109 arm64_sve-ptrace_Set_SVE_VL_6000 pass
10317 17:01:16.722370 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 skip
10318 17:01:16.722581 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
10319 17:01:16.722807 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
10320 17:01:16.723008 arm64_sve-ptrace_Set_SVE_VL_6016 pass
10321 17:01:16.723242 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 skip
10322 17:01:16.723450 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
10323 17:01:16.723591 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
10324 17:01:16.723709 arm64_sve-ptrace_Set_SVE_VL_6032 pass
10325 17:01:16.723828 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 skip
10326 17:01:16.723973 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
10327 17:01:16.724099 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
10328 17:01:16.724214 arm64_sve-ptrace_Set_SVE_VL_6048 pass
10329 17:01:16.724332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 skip
10330 17:01:16.724444 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
10331 17:01:16.724561 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
10332 17:01:16.724674 arm64_sve-ptrace_Set_SVE_VL_6064 pass
10333 17:01:16.724786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 skip
10334 17:01:16.724904 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
10335 17:01:16.727670 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
10336 17:01:16.728077 arm64_sve-ptrace_Set_SVE_VL_6080 pass
10337 17:01:16.728291 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 skip
10338 17:01:16.728489 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
10339 17:01:16.728632 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
10340 17:01:16.728737 arm64_sve-ptrace_Set_SVE_VL_6096 pass
10341 17:01:16.728847 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 skip
10342 17:01:16.728956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
10343 17:01:16.729072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
10344 17:01:16.729235 arm64_sve-ptrace_Set_SVE_VL_6112 pass
10345 17:01:16.729369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 skip
10346 17:01:16.729507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
10347 17:01:16.729630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
10348 17:01:16.729762 arm64_sve-ptrace_Set_SVE_VL_6128 pass
10349 17:01:16.729910 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 skip
10350 17:01:16.730038 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
10351 17:01:16.730160 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
10352 17:01:16.730279 arm64_sve-ptrace_Set_SVE_VL_6144 pass
10353 17:01:16.730436 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 skip
10354 17:01:16.730526 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
10355 17:01:16.730602 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
10356 17:01:16.730693 arm64_sve-ptrace_Set_SVE_VL_6160 pass
10357 17:01:16.730804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 skip
10358 17:01:16.730891 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
10359 17:01:16.730973 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
10360 17:01:16.731040 arm64_sve-ptrace_Set_SVE_VL_6176 pass
10361 17:01:16.731148 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 skip
10362 17:01:16.731267 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
10363 17:01:16.731377 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
10364 17:01:16.735805 arm64_sve-ptrace_Set_SVE_VL_6192 pass
10365 17:01:16.736120 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 skip
10366 17:01:16.736231 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
10367 17:01:16.736323 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
10368 17:01:16.736428 arm64_sve-ptrace_Set_SVE_VL_6208 pass
10369 17:01:16.736522 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 skip
10370 17:01:16.736623 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
10371 17:01:16.736727 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
10372 17:01:16.736823 arm64_sve-ptrace_Set_SVE_VL_6224 pass
10373 17:01:16.750958 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 skip
10374 17:01:16.751185 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
10375 17:01:16.751491 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
10376 17:01:16.751600 arm64_sve-ptrace_Set_SVE_VL_6240 pass
10377 17:01:16.751693 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 skip
10378 17:01:16.751780 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
10379 17:01:16.751881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
10380 17:01:16.751967 arm64_sve-ptrace_Set_SVE_VL_6256 pass
10381 17:01:16.752050 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 skip
10382 17:01:16.752150 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
10383 17:01:16.752234 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
10384 17:01:16.752318 arm64_sve-ptrace_Set_SVE_VL_6272 pass
10385 17:01:16.752414 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 skip
10386 17:01:16.752513 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
10387 17:01:16.752610 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
10388 17:01:16.752711 arm64_sve-ptrace_Set_SVE_VL_6288 pass
10389 17:01:16.752807 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 skip
10390 17:01:16.753111 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
10391 17:01:16.753223 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
10392 17:01:16.753331 arm64_sve-ptrace_Set_SVE_VL_6304 pass
10393 17:01:16.753412 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 skip
10394 17:01:16.753526 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
10395 17:01:16.753615 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
10396 17:01:16.753718 arm64_sve-ptrace_Set_SVE_VL_6320 pass
10397 17:01:16.753814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 skip
10398 17:01:16.754104 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
10399 17:01:16.754208 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
10400 17:01:16.754308 arm64_sve-ptrace_Set_SVE_VL_6336 pass
10401 17:01:16.754407 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 skip
10402 17:01:16.754707 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
10403 17:01:16.754802 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
10404 17:01:16.754894 arm64_sve-ptrace_Set_SVE_VL_6352 pass
10405 17:01:16.754980 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 skip
10406 17:01:16.755107 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
10407 17:01:16.755232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
10408 17:01:16.755338 arm64_sve-ptrace_Set_SVE_VL_6368 pass
10409 17:01:16.755434 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 skip
10410 17:01:16.759568 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
10411 17:01:16.759930 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
10412 17:01:16.760055 arm64_sve-ptrace_Set_SVE_VL_6384 pass
10413 17:01:16.760161 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 skip
10414 17:01:16.760285 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
10415 17:01:16.760406 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
10416 17:01:16.760499 arm64_sve-ptrace_Set_SVE_VL_6400 pass
10417 17:01:16.760579 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 skip
10418 17:01:16.760657 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
10419 17:01:16.760736 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
10420 17:01:16.760832 arm64_sve-ptrace_Set_SVE_VL_6416 pass
10421 17:01:16.760918 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 skip
10422 17:01:16.761037 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
10423 17:01:16.761147 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
10424 17:01:16.761266 arm64_sve-ptrace_Set_SVE_VL_6432 pass
10425 17:01:16.761351 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 skip
10426 17:01:16.761466 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
10427 17:01:16.761572 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
10428 17:01:16.761686 arm64_sve-ptrace_Set_SVE_VL_6448 pass
10429 17:01:16.761814 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 skip
10430 17:01:16.761900 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
10431 17:01:16.761994 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
10432 17:01:16.762077 arm64_sve-ptrace_Set_SVE_VL_6464 pass
10433 17:01:16.762169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 skip
10434 17:01:16.762277 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
10435 17:01:16.762391 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
10436 17:01:16.762508 arm64_sve-ptrace_Set_SVE_VL_6480 pass
10437 17:01:16.762618 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 skip
10438 17:01:16.762713 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
10439 17:01:16.762811 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
10440 17:01:16.762904 arm64_sve-ptrace_Set_SVE_VL_6496 pass
10441 17:01:16.763448 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 skip
10442 17:01:16.763530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
10443 17:01:16.763594 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
10444 17:01:16.767664 arm64_sve-ptrace_Set_SVE_VL_6512 pass
10445 17:01:16.767802 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 skip
10446 17:01:16.768136 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
10447 17:01:16.768261 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
10448 17:01:16.768367 arm64_sve-ptrace_Set_SVE_VL_6528 pass
10449 17:01:16.768472 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 skip
10450 17:01:16.768557 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
10451 17:01:16.768659 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
10452 17:01:16.768760 arm64_sve-ptrace_Set_SVE_VL_6544 pass
10453 17:01:16.768863 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 skip
10454 17:01:16.768968 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
10455 17:01:16.769067 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
10456 17:01:16.769176 arm64_sve-ptrace_Set_SVE_VL_6560 pass
10457 17:01:16.769270 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 skip
10458 17:01:16.769365 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
10459 17:01:16.769459 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
10460 17:01:16.769544 arm64_sve-ptrace_Set_SVE_VL_6576 pass
10461 17:01:16.769629 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 skip
10462 17:01:16.769741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
10463 17:01:16.769819 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
10464 17:01:16.769896 arm64_sve-ptrace_Set_SVE_VL_6592 pass
10465 17:01:16.769976 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 skip
10466 17:01:16.770056 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
10467 17:01:16.770156 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
10468 17:01:16.770241 arm64_sve-ptrace_Set_SVE_VL_6608 pass
10469 17:01:16.770323 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 skip
10470 17:01:16.770397 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
10471 17:01:16.770486 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
10472 17:01:16.770571 arm64_sve-ptrace_Set_SVE_VL_6624 pass
10473 17:01:16.770652 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 skip
10474 17:01:16.770748 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
10475 17:01:16.770843 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
10476 17:01:16.770924 arm64_sve-ptrace_Set_SVE_VL_6640 pass
10477 17:01:16.771009 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 skip
10478 17:01:16.771102 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
10479 17:01:16.771196 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
10480 17:01:16.771279 arm64_sve-ptrace_Set_SVE_VL_6656 pass
10481 17:01:16.771372 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 skip
10482 17:01:16.775644 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
10483 17:01:16.776081 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
10484 17:01:16.776187 arm64_sve-ptrace_Set_SVE_VL_6672 pass
10485 17:01:16.776278 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 skip
10486 17:01:16.776381 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
10487 17:01:16.776470 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
10488 17:01:16.776554 arm64_sve-ptrace_Set_SVE_VL_6688 pass
10489 17:01:16.776654 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 skip
10490 17:01:16.776743 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
10491 17:01:16.776850 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
10492 17:01:16.776954 arm64_sve-ptrace_Set_SVE_VL_6704 pass
10493 17:01:16.777243 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 skip
10494 17:01:16.777335 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
10495 17:01:16.777437 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
10496 17:01:16.777538 arm64_sve-ptrace_Set_SVE_VL_6720 pass
10497 17:01:16.777639 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 skip
10498 17:01:16.777933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
10499 17:01:16.778024 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
10500 17:01:16.778124 arm64_sve-ptrace_Set_SVE_VL_6736 pass
10501 17:01:16.778224 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 skip
10502 17:01:16.778324 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
10503 17:01:16.778424 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
10504 17:01:16.778711 arm64_sve-ptrace_Set_SVE_VL_6752 pass
10505 17:01:16.778804 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 skip
10506 17:01:16.778903 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
10507 17:01:16.779004 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
10508 17:01:16.779104 arm64_sve-ptrace_Set_SVE_VL_6768 pass
10509 17:01:16.779437 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 skip
10510 17:01:16.783741 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
10511 17:01:16.783919 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
10512 17:01:16.784235 arm64_sve-ptrace_Set_SVE_VL_6784 pass
10513 17:01:16.784415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 skip
10514 17:01:16.784532 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
10515 17:01:16.784619 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
10516 17:01:16.784698 arm64_sve-ptrace_Set_SVE_VL_6800 pass
10517 17:01:16.784795 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 skip
10518 17:01:16.784889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
10519 17:01:16.784987 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
10520 17:01:16.785098 arm64_sve-ptrace_Set_SVE_VL_6816 pass
10521 17:01:16.785191 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 skip
10522 17:01:16.785314 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
10523 17:01:16.785423 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
10524 17:01:16.785520 arm64_sve-ptrace_Set_SVE_VL_6832 pass
10525 17:01:16.785616 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 skip
10526 17:01:16.785911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
10527 17:01:16.786001 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
10528 17:01:16.786067 arm64_sve-ptrace_Set_SVE_VL_6848 pass
10529 17:01:16.786128 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 skip
10530 17:01:16.786189 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
10531 17:01:16.786249 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
10532 17:01:16.786312 arm64_sve-ptrace_Set_SVE_VL_6864 pass
10533 17:01:16.802359 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 skip
10534 17:01:16.802746 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
10535 17:01:16.802836 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
10536 17:01:16.802934 arm64_sve-ptrace_Set_SVE_VL_6880 pass
10537 17:01:16.803035 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 skip
10538 17:01:16.803169 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
10539 17:01:16.803263 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
10540 17:01:16.803362 arm64_sve-ptrace_Set_SVE_VL_6896 pass
10541 17:01:16.803468 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 skip
10542 17:01:16.803587 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
10543 17:01:16.803684 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
10544 17:01:16.803794 arm64_sve-ptrace_Set_SVE_VL_6912 pass
10545 17:01:16.803901 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 skip
10546 17:01:16.804002 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
10547 17:01:16.804118 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
10548 17:01:16.804219 arm64_sve-ptrace_Set_SVE_VL_6928 pass
10549 17:01:16.804317 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 skip
10550 17:01:16.804398 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
10551 17:01:16.804496 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
10552 17:01:16.804569 arm64_sve-ptrace_Set_SVE_VL_6944 pass
10553 17:01:16.804669 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 skip
10554 17:01:16.804739 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
10555 17:01:16.804823 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
10556 17:01:16.804920 arm64_sve-ptrace_Set_SVE_VL_6960 pass
10557 17:01:16.805043 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 skip
10558 17:01:16.805144 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
10559 17:01:16.805276 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
10560 17:01:16.805375 arm64_sve-ptrace_Set_SVE_VL_6976 pass
10561 17:01:16.805470 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 skip
10562 17:01:16.805572 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
10563 17:01:16.805693 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
10564 17:01:16.805790 arm64_sve-ptrace_Set_SVE_VL_6992 pass
10565 17:01:16.805907 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 skip
10566 17:01:16.806023 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
10567 17:01:16.806129 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
10568 17:01:16.806259 arm64_sve-ptrace_Set_SVE_VL_7008 pass
10569 17:01:16.806366 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 skip
10570 17:01:16.806477 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
10571 17:01:16.806589 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
10572 17:01:16.806937 arm64_sve-ptrace_Set_SVE_VL_7024 pass
10573 17:01:16.807041 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 skip
10574 17:01:16.807138 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
10575 17:01:16.807236 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
10576 17:01:16.807338 arm64_sve-ptrace_Set_SVE_VL_7040 pass
10577 17:01:16.807430 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 skip
10578 17:01:16.807512 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
10579 17:01:16.807577 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
10580 17:01:16.807639 arm64_sve-ptrace_Set_SVE_VL_7056 pass
10581 17:01:16.807699 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 skip
10582 17:01:16.811729 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
10583 17:01:16.812255 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
10584 17:01:16.812482 arm64_sve-ptrace_Set_SVE_VL_7072 pass
10585 17:01:16.812720 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 skip
10586 17:01:16.812956 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
10587 17:01:16.813232 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
10588 17:01:16.813458 arm64_sve-ptrace_Set_SVE_VL_7088 pass
10589 17:01:16.813695 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 skip
10590 17:01:16.813935 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
10591 17:01:16.814137 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
10592 17:01:16.814360 arm64_sve-ptrace_Set_SVE_VL_7104 pass
10593 17:01:16.814544 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 skip
10594 17:01:16.814715 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
10595 17:01:16.814879 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
10596 17:01:16.815036 arm64_sve-ptrace_Set_SVE_VL_7120 pass
10597 17:01:16.815299 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 skip
10598 17:01:16.815484 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
10599 17:01:16.815613 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
10600 17:01:16.815727 arm64_sve-ptrace_Set_SVE_VL_7136 pass
10601 17:01:16.815838 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 skip
10602 17:01:16.815950 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
10603 17:01:16.816060 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
10604 17:01:16.816170 arm64_sve-ptrace_Set_SVE_VL_7152 pass
10605 17:01:16.816281 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 skip
10606 17:01:16.816391 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
10607 17:01:16.816502 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
10608 17:01:16.816615 arm64_sve-ptrace_Set_SVE_VL_7168 pass
10609 17:01:16.816727 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 skip
10610 17:01:16.816838 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
10611 17:01:16.816949 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
10612 17:01:16.817059 arm64_sve-ptrace_Set_SVE_VL_7184 pass
10613 17:01:16.817169 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 skip
10614 17:01:16.817280 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
10615 17:01:16.817390 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
10616 17:01:16.817526 arm64_sve-ptrace_Set_SVE_VL_7200 pass
10617 17:01:16.819646 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 skip
10618 17:01:16.820223 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
10619 17:01:16.820416 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
10620 17:01:16.820578 arm64_sve-ptrace_Set_SVE_VL_7216 pass
10621 17:01:16.820764 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 skip
10622 17:01:16.821013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
10623 17:01:16.821233 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
10624 17:01:16.821444 arm64_sve-ptrace_Set_SVE_VL_7232 pass
10625 17:01:16.821671 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 skip
10626 17:01:16.821947 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
10627 17:01:16.822140 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
10628 17:01:16.822306 arm64_sve-ptrace_Set_SVE_VL_7248 pass
10629 17:01:16.822504 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 skip
10630 17:01:16.822699 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
10631 17:01:16.822883 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
10632 17:01:16.823065 arm64_sve-ptrace_Set_SVE_VL_7264 pass
10633 17:01:16.823275 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 skip
10634 17:01:16.823470 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
10635 17:01:16.823630 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
10636 17:01:16.823796 arm64_sve-ptrace_Set_SVE_VL_7280 pass
10637 17:01:16.823917 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 skip
10638 17:01:16.824030 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
10639 17:01:16.824194 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
10640 17:01:16.824377 arm64_sve-ptrace_Set_SVE_VL_7296 pass
10641 17:01:16.824501 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 skip
10642 17:01:16.824616 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
10643 17:01:16.824731 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
10644 17:01:16.824843 arm64_sve-ptrace_Set_SVE_VL_7312 pass
10645 17:01:16.824954 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 skip
10646 17:01:16.825065 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
10647 17:01:16.825177 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
10648 17:01:16.825289 arm64_sve-ptrace_Set_SVE_VL_7328 pass
10649 17:01:16.825401 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 skip
10650 17:01:16.825516 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
10651 17:01:16.825627 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
10652 17:01:16.825758 arm64_sve-ptrace_Set_SVE_VL_7344 pass
10653 17:01:16.827710 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 skip
10654 17:01:16.827919 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
10655 17:01:16.828317 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
10656 17:01:16.828516 arm64_sve-ptrace_Set_SVE_VL_7360 pass
10657 17:01:16.828676 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 skip
10658 17:01:16.828832 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
10659 17:01:16.828990 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
10660 17:01:16.829177 arm64_sve-ptrace_Set_SVE_VL_7376 pass
10661 17:01:16.829337 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 skip
10662 17:01:16.829494 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
10663 17:01:16.829667 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
10664 17:01:16.829829 arm64_sve-ptrace_Set_SVE_VL_7392 pass
10665 17:01:16.829984 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 skip
10666 17:01:16.830137 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
10667 17:01:16.830290 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
10668 17:01:16.830478 arm64_sve-ptrace_Set_SVE_VL_7408 pass
10669 17:01:16.830641 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 skip
10670 17:01:16.830798 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
10671 17:01:16.830953 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
10672 17:01:16.831106 arm64_sve-ptrace_Set_SVE_VL_7424 pass
10673 17:01:16.831259 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 skip
10674 17:01:16.831413 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
10675 17:01:16.831566 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
10676 17:01:16.831755 arm64_sve-ptrace_Set_SVE_VL_7440 pass
10677 17:01:16.831915 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 skip
10678 17:01:16.832071 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
10679 17:01:16.832225 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
10680 17:01:16.832379 arm64_sve-ptrace_Set_SVE_VL_7456 pass
10681 17:01:16.832532 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 skip
10682 17:01:16.832686 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
10683 17:01:16.832833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
10684 17:01:16.832988 arm64_sve-ptrace_Set_SVE_VL_7472 pass
10685 17:01:16.835922 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 skip
10686 17:01:16.836385 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
10687 17:01:16.836590 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
10688 17:01:16.836776 arm64_sve-ptrace_Set_SVE_VL_7488 pass
10689 17:01:16.836945 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 skip
10690 17:01:16.837117 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
10691 17:01:16.837326 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
10692 17:01:16.837510 arm64_sve-ptrace_Set_SVE_VL_7504 pass
10693 17:01:16.851931 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 skip
10694 17:01:16.852491 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
10695 17:01:16.852706 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
10696 17:01:16.852879 arm64_sve-ptrace_Set_SVE_VL_7520 pass
10697 17:01:16.853041 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 skip
10698 17:01:16.853203 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
10699 17:01:16.853400 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
10700 17:01:16.853567 arm64_sve-ptrace_Set_SVE_VL_7536 pass
10701 17:01:16.853747 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 skip
10702 17:01:16.853911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
10703 17:01:16.854072 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
10704 17:01:16.854234 arm64_sve-ptrace_Set_SVE_VL_7552 pass
10705 17:01:16.854395 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 skip
10706 17:01:16.854556 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
10707 17:01:16.854756 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
10708 17:01:16.854923 arm64_sve-ptrace_Set_SVE_VL_7568 pass
10709 17:01:16.855084 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 skip
10710 17:01:16.855245 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
10711 17:01:16.855406 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
10712 17:01:16.855566 arm64_sve-ptrace_Set_SVE_VL_7584 pass
10713 17:01:16.855729 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 skip
10714 17:01:16.855889 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
10715 17:01:16.856048 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
10716 17:01:16.856209 arm64_sve-ptrace_Set_SVE_VL_7600 pass
10717 17:01:16.856369 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 skip
10718 17:01:16.856529 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
10719 17:01:16.856721 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
10720 17:01:16.856890 arm64_sve-ptrace_Set_SVE_VL_7616 pass
10721 17:01:16.857050 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 skip
10722 17:01:16.857211 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
10723 17:01:16.859716 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
10724 17:01:16.860005 arm64_sve-ptrace_Set_SVE_VL_7632 pass
10725 17:01:16.860415 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 skip
10726 17:01:16.860609 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
10727 17:01:16.860786 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
10728 17:01:16.860969 arm64_sve-ptrace_Set_SVE_VL_7648 pass
10729 17:01:16.861130 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 skip
10730 17:01:16.861336 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
10731 17:01:16.861518 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
10732 17:01:16.861737 arm64_sve-ptrace_Set_SVE_VL_7664 pass
10733 17:01:16.861914 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 skip
10734 17:01:16.862081 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
10735 17:01:16.862250 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
10736 17:01:16.862423 arm64_sve-ptrace_Set_SVE_VL_7680 pass
10737 17:01:16.862635 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 skip
10738 17:01:16.862819 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
10739 17:01:16.862991 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
10740 17:01:16.863161 arm64_sve-ptrace_Set_SVE_VL_7696 pass
10741 17:01:16.863332 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 skip
10742 17:01:16.863507 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
10743 17:01:16.863680 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
10744 17:01:16.863856 arm64_sve-ptrace_Set_SVE_VL_7712 pass
10745 17:01:16.864021 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 skip
10746 17:01:16.864194 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
10747 17:01:16.864364 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
10748 17:01:16.864573 arm64_sve-ptrace_Set_SVE_VL_7728 pass
10749 17:01:16.864756 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 skip
10750 17:01:16.864927 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
10751 17:01:16.865101 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
10752 17:01:16.865273 arm64_sve-ptrace_Set_SVE_VL_7744 pass
10753 17:01:16.865444 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 skip
10754 17:01:16.867676 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
10755 17:01:16.867898 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
10756 17:01:16.868306 arm64_sve-ptrace_Set_SVE_VL_7760 pass
10757 17:01:16.868491 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 skip
10758 17:01:16.868666 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
10759 17:01:16.868833 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
10760 17:01:16.868988 arm64_sve-ptrace_Set_SVE_VL_7776 pass
10761 17:01:16.869180 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 skip
10762 17:01:16.869344 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
10763 17:01:16.869495 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
10764 17:01:16.869643 arm64_sve-ptrace_Set_SVE_VL_7792 pass
10765 17:01:16.869833 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 skip
10766 17:01:16.870006 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
10767 17:01:16.870179 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
10768 17:01:16.870388 arm64_sve-ptrace_Set_SVE_VL_7808 pass
10769 17:01:16.870564 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 skip
10770 17:01:16.870738 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
10771 17:01:16.870892 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
10772 17:01:16.871075 arm64_sve-ptrace_Set_SVE_VL_7824 pass
10773 17:01:16.871257 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 skip
10774 17:01:16.871428 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
10775 17:01:16.871607 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
10776 17:01:16.871826 arm64_sve-ptrace_Set_SVE_VL_7840 pass
10777 17:01:16.872007 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 skip
10778 17:01:16.872183 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
10779 17:01:16.872360 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
10780 17:01:16.872540 arm64_sve-ptrace_Set_SVE_VL_7856 pass
10781 17:01:16.872712 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 skip
10782 17:01:16.872885 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
10783 17:01:16.873065 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
10784 17:01:16.875665 arm64_sve-ptrace_Set_SVE_VL_7872 pass
10785 17:01:16.875765 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 skip
10786 17:01:16.876013 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
10787 17:01:16.876117 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
10788 17:01:16.876214 arm64_sve-ptrace_Set_SVE_VL_7888 pass
10789 17:01:16.876296 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 skip
10790 17:01:16.876387 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
10791 17:01:16.876480 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
10792 17:01:16.876816 arm64_sve-ptrace_Set_SVE_VL_7904 pass
10793 17:01:16.876903 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 skip
10794 17:01:16.877175 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
10795 17:01:16.877272 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
10796 17:01:16.877350 arm64_sve-ptrace_Set_SVE_VL_7920 pass
10797 17:01:16.877438 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 skip
10798 17:01:16.877530 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
10799 17:01:16.877626 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
10800 17:01:16.877725 arm64_sve-ptrace_Set_SVE_VL_7936 pass
10801 17:01:16.877840 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 skip
10802 17:01:16.877937 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
10803 17:01:16.878239 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
10804 17:01:16.878338 arm64_sve-ptrace_Set_SVE_VL_7952 pass
10805 17:01:16.878421 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 skip
10806 17:01:16.878518 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
10807 17:01:16.878808 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
10808 17:01:16.878910 arm64_sve-ptrace_Set_SVE_VL_7968 pass
10809 17:01:16.878995 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 skip
10810 17:01:16.879072 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
10811 17:01:16.879334 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
10812 17:01:16.879430 arm64_sve-ptrace_Set_SVE_VL_7984 pass
10813 17:01:16.879499 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 skip
10814 17:01:16.879561 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
10815 17:01:16.879623 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
10816 17:01:16.879694 arm64_sve-ptrace_Set_SVE_VL_8000 pass
10817 17:01:16.883594 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 skip
10818 17:01:16.883911 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
10819 17:01:16.883992 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
10820 17:01:16.884080 arm64_sve-ptrace_Set_SVE_VL_8016 pass
10821 17:01:16.884170 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 skip
10822 17:01:16.884259 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
10823 17:01:16.884515 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
10824 17:01:16.884775 arm64_sve-ptrace_Set_SVE_VL_8032 pass
10825 17:01:16.884881 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 skip
10826 17:01:16.884982 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
10827 17:01:16.885104 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
10828 17:01:16.885205 arm64_sve-ptrace_Set_SVE_VL_8048 pass
10829 17:01:16.885310 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 skip
10830 17:01:16.885406 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
10831 17:01:16.885485 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
10832 17:01:16.885565 arm64_sve-ptrace_Set_SVE_VL_8064 pass
10833 17:01:16.885634 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 skip
10834 17:01:16.885759 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
10835 17:01:16.885863 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
10836 17:01:16.885945 arm64_sve-ptrace_Set_SVE_VL_8080 pass
10837 17:01:16.886041 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 skip
10838 17:01:16.886333 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
10839 17:01:16.886431 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
10840 17:01:16.886498 arm64_sve-ptrace_Set_SVE_VL_8096 pass
10841 17:01:16.886754 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 skip
10842 17:01:16.886837 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
10843 17:01:16.886910 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
10844 17:01:16.887173 arm64_sve-ptrace_Set_SVE_VL_8112 pass
10845 17:01:16.887251 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 skip
10846 17:01:16.887508 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
10847 17:01:16.891585 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
10848 17:01:16.891878 arm64_sve-ptrace_Set_SVE_VL_8128 pass
10849 17:01:16.892015 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 skip
10850 17:01:16.892165 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
10851 17:01:16.892293 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
10852 17:01:16.892409 arm64_sve-ptrace_Set_SVE_VL_8144 pass
10853 17:01:16.903965 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 skip
10854 17:01:16.904275 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
10855 17:01:16.904713 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
10856 17:01:16.904913 arm64_sve-ptrace_Set_SVE_VL_8160 pass
10857 17:01:16.905105 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 skip
10858 17:01:16.905265 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
10859 17:01:16.905418 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
10860 17:01:16.905609 arm64_sve-ptrace_Set_SVE_VL_8176 pass
10861 17:01:16.905786 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 skip
10862 17:01:16.905933 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
10863 17:01:16.906076 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
10864 17:01:16.906268 arm64_sve-ptrace_Set_SVE_VL_8192 pass
10865 17:01:16.906473 arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 skip
10866 17:01:16.906702 arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
10867 17:01:16.906881 arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
10868 17:01:16.907041 arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 pass
10869 17:01:16.907207 arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state pass
10870 17:01:16.907388 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set pass
10871 17:01:16.907574 arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared pass
10872 17:01:16.907707 arm64_sve-ptrace_Set_Streaming_SVE_VL_16 pass
10873 17:01:16.907823 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 pass
10874 17:01:16.907967 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 pass
10875 17:01:16.908089 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 pass
10876 17:01:16.908202 arm64_sve-ptrace_Set_Streaming_SVE_VL_32 pass
10877 17:01:16.908316 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 pass
10878 17:01:16.908429 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 pass
10879 17:01:16.911658 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 pass
10880 17:01:16.912191 arm64_sve-ptrace_Set_Streaming_SVE_VL_48 pass
10881 17:01:16.912388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 skip
10882 17:01:16.912558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 skip
10883 17:01:16.912744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 skip
10884 17:01:16.912983 arm64_sve-ptrace_Set_Streaming_SVE_VL_64 pass
10885 17:01:16.913143 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 pass
10886 17:01:16.913292 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 pass
10887 17:01:16.913453 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 pass
10888 17:01:16.913613 arm64_sve-ptrace_Set_Streaming_SVE_VL_80 pass
10889 17:01:16.913824 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 skip
10890 17:01:16.914010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 skip
10891 17:01:16.914209 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 skip
10892 17:01:16.914386 arm64_sve-ptrace_Set_Streaming_SVE_VL_96 pass
10893 17:01:16.914575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 skip
10894 17:01:16.914772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 skip
10895 17:01:16.914987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 skip
10896 17:01:16.915155 arm64_sve-ptrace_Set_Streaming_SVE_VL_112 pass
10897 17:01:16.915309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 skip
10898 17:01:16.915442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 skip
10899 17:01:16.915557 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 skip
10900 17:01:16.915671 arm64_sve-ptrace_Set_Streaming_SVE_VL_128 pass
10901 17:01:16.915783 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 pass
10902 17:01:16.915898 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 pass
10903 17:01:16.916255 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 pass
10904 17:01:16.916411 arm64_sve-ptrace_Set_Streaming_SVE_VL_144 pass
10905 17:01:16.916530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 skip
10906 17:01:16.916646 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 skip
10907 17:01:16.919596 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 skip
10908 17:01:16.919697 arm64_sve-ptrace_Set_Streaming_SVE_VL_160 pass
10909 17:01:16.920016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 skip
10910 17:01:16.920221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 skip
10911 17:01:16.920405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 skip
10912 17:01:16.920609 arm64_sve-ptrace_Set_Streaming_SVE_VL_176 pass
10913 17:01:16.920810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 skip
10914 17:01:16.920977 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 skip
10915 17:01:16.921111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 skip
10916 17:01:16.921272 arm64_sve-ptrace_Set_Streaming_SVE_VL_192 pass
10917 17:01:16.921461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 skip
10918 17:01:16.921592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 skip
10919 17:01:16.921726 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 skip
10920 17:01:16.921845 arm64_sve-ptrace_Set_Streaming_SVE_VL_208 pass
10921 17:01:16.921963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 skip
10922 17:01:16.925232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 skip
10923 17:01:16.925369 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 skip
10924 17:01:16.925488 arm64_sve-ptrace_Set_Streaming_SVE_VL_224 pass
10925 17:01:16.925604 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 skip
10926 17:01:16.925734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 skip
10927 17:01:16.925854 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 skip
10928 17:01:16.925971 arm64_sve-ptrace_Set_Streaming_SVE_VL_240 pass
10929 17:01:16.926086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 skip
10930 17:01:16.926202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 skip
10931 17:01:16.926318 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 skip
10932 17:01:16.926435 arm64_sve-ptrace_Set_Streaming_SVE_VL_256 pass
10933 17:01:16.926550 arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 pass
10934 17:01:16.926665 arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 pass
10935 17:01:16.927618 arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 pass
10936 17:01:16.928005 arm64_sve-ptrace_Set_Streaming_SVE_VL_272 pass
10937 17:01:16.928100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 skip
10938 17:01:16.928170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 skip
10939 17:01:16.928286 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 skip
10940 17:01:16.928388 arm64_sve-ptrace_Set_Streaming_SVE_VL_288 pass
10941 17:01:16.928490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 skip
10942 17:01:16.928583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 skip
10943 17:01:16.928871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 skip
10944 17:01:16.928962 arm64_sve-ptrace_Set_Streaming_SVE_VL_304 pass
10945 17:01:16.929078 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 skip
10946 17:01:16.929175 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 skip
10947 17:01:16.929285 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 skip
10948 17:01:16.929379 arm64_sve-ptrace_Set_Streaming_SVE_VL_320 pass
10949 17:01:16.929473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 skip
10950 17:01:16.929796 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 skip
10951 17:01:16.929916 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 skip
10952 17:01:16.930053 arm64_sve-ptrace_Set_Streaming_SVE_VL_336 pass
10953 17:01:16.930164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 skip
10954 17:01:16.930246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 skip
10955 17:01:16.930359 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 skip
10956 17:01:16.930468 arm64_sve-ptrace_Set_Streaming_SVE_VL_352 pass
10957 17:01:16.930572 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 skip
10958 17:01:16.930671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 skip
10959 17:01:16.930975 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 skip
10960 17:01:16.931177 arm64_sve-ptrace_Set_Streaming_SVE_VL_368 pass
10961 17:01:16.931397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 skip
10962 17:01:16.931535 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 skip
10963 17:01:16.935588 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 skip
10964 17:01:16.935905 arm64_sve-ptrace_Set_Streaming_SVE_VL_384 pass
10965 17:01:16.936003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 skip
10966 17:01:16.936112 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 skip
10967 17:01:16.936200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 skip
10968 17:01:16.936284 arm64_sve-ptrace_Set_Streaming_SVE_VL_400 pass
10969 17:01:16.936360 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 skip
10970 17:01:16.936656 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 skip
10971 17:01:16.936751 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 skip
10972 17:01:16.936856 arm64_sve-ptrace_Set_Streaming_SVE_VL_416 pass
10973 17:01:16.936963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 skip
10974 17:01:16.937080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 skip
10975 17:01:16.937366 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 skip
10976 17:01:16.937474 arm64_sve-ptrace_Set_Streaming_SVE_VL_432 pass
10977 17:01:16.937607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 skip
10978 17:01:16.937903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 skip
10979 17:01:16.937998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 skip
10980 17:01:16.938098 arm64_sve-ptrace_Set_Streaming_SVE_VL_448 pass
10981 17:01:16.938202 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 skip
10982 17:01:16.938313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 skip
10983 17:01:16.938429 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 skip
10984 17:01:16.938528 arm64_sve-ptrace_Set_Streaming_SVE_VL_464 pass
10985 17:01:16.938807 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 skip
10986 17:01:16.938934 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 skip
10987 17:01:16.939041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 skip
10988 17:01:16.939151 arm64_sve-ptrace_Set_Streaming_SVE_VL_480 pass
10989 17:01:16.939401 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 skip
10990 17:01:16.954179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 skip
10991 17:01:16.954536 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 skip
10992 17:01:16.954655 arm64_sve-ptrace_Set_Streaming_SVE_VL_496 pass
10993 17:01:16.954762 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 skip
10994 17:01:16.954888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 skip
10995 17:01:16.954990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 skip
10996 17:01:16.955092 arm64_sve-ptrace_Set_Streaming_SVE_VL_512 pass
10997 17:01:16.955204 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 skip
10998 17:01:16.955288 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 skip
10999 17:01:16.955373 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 skip
11000 17:01:16.955639 arm64_sve-ptrace_Set_Streaming_SVE_VL_528 pass
11001 17:01:16.955749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 skip
11002 17:01:16.955843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 skip
11003 17:01:16.956123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 skip
11004 17:01:16.956220 arm64_sve-ptrace_Set_Streaming_SVE_VL_544 pass
11005 17:01:16.956338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 skip
11006 17:01:16.956458 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 skip
11007 17:01:16.956572 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 skip
11008 17:01:16.956667 arm64_sve-ptrace_Set_Streaming_SVE_VL_560 pass
11009 17:01:16.956778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 skip
11010 17:01:16.956890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 skip
11011 17:01:16.956992 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 skip
11012 17:01:16.957335 arm64_sve-ptrace_Set_Streaming_SVE_VL_576 pass
11013 17:01:16.957441 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 skip
11014 17:01:16.957542 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 skip
11015 17:01:16.957665 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 skip
11016 17:01:16.957780 arm64_sve-ptrace_Set_Streaming_SVE_VL_592 pass
11017 17:01:16.957860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 skip
11018 17:01:16.957959 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 skip
11019 17:01:16.958052 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 skip
11020 17:01:16.958166 arm64_sve-ptrace_Set_Streaming_SVE_VL_608 pass
11021 17:01:16.958281 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 skip
11022 17:01:16.958396 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 skip
11023 17:01:16.958541 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 skip
11024 17:01:16.958663 arm64_sve-ptrace_Set_Streaming_SVE_VL_624 pass
11025 17:01:16.958769 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 skip
11026 17:01:16.959117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 skip
11027 17:01:16.959351 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 skip
11028 17:01:16.959497 arm64_sve-ptrace_Set_Streaming_SVE_VL_640 pass
11029 17:01:16.963633 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 skip
11030 17:01:16.963986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 skip
11031 17:01:16.964094 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 skip
11032 17:01:16.964379 arm64_sve-ptrace_Set_Streaming_SVE_VL_656 pass
11033 17:01:16.964482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 skip
11034 17:01:16.964565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 skip
11035 17:01:16.964660 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 skip
11036 17:01:16.964745 arm64_sve-ptrace_Set_Streaming_SVE_VL_672 pass
11037 17:01:16.964837 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 skip
11038 17:01:16.964933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 skip
11039 17:01:16.965226 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 skip
11040 17:01:16.965330 arm64_sve-ptrace_Set_Streaming_SVE_VL_688 pass
11041 17:01:16.965427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 skip
11042 17:01:16.965529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 skip
11043 17:01:16.965629 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 skip
11044 17:01:16.965763 arm64_sve-ptrace_Set_Streaming_SVE_VL_704 pass
11045 17:01:16.966037 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 skip
11046 17:01:16.966306 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 skip
11047 17:01:16.966416 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 skip
11048 17:01:16.966517 arm64_sve-ptrace_Set_Streaming_SVE_VL_720 pass
11049 17:01:16.966630 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 skip
11050 17:01:16.966732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 skip
11051 17:01:16.967014 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 skip
11052 17:01:16.967104 arm64_sve-ptrace_Set_Streaming_SVE_VL_736 pass
11053 17:01:16.967199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 skip
11054 17:01:16.967286 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 skip
11055 17:01:16.971551 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 skip
11056 17:01:16.971890 arm64_sve-ptrace_Set_Streaming_SVE_VL_752 pass
11057 17:01:16.972106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 skip
11058 17:01:16.972333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 skip
11059 17:01:16.972524 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 skip
11060 17:01:16.972690 arm64_sve-ptrace_Set_Streaming_SVE_VL_768 pass
11061 17:01:16.972905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 skip
11062 17:01:16.973079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 skip
11063 17:01:16.973235 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 skip
11064 17:01:16.973393 arm64_sve-ptrace_Set_Streaming_SVE_VL_784 pass
11065 17:01:16.973588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 skip
11066 17:01:16.973788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 skip
11067 17:01:16.973995 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 skip
11068 17:01:16.974210 arm64_sve-ptrace_Set_Streaming_SVE_VL_800 pass
11069 17:01:16.974400 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 skip
11070 17:01:16.974591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 skip
11071 17:01:16.974766 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 skip
11072 17:01:16.974925 arm64_sve-ptrace_Set_Streaming_SVE_VL_816 pass
11073 17:01:16.975089 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 skip
11074 17:01:16.975245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 skip
11075 17:01:16.975392 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 skip
11076 17:01:16.975523 arm64_sve-ptrace_Set_Streaming_SVE_VL_832 pass
11077 17:01:16.975665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 skip
11078 17:01:16.975786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 skip
11079 17:01:16.975902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 skip
11080 17:01:16.976019 arm64_sve-ptrace_Set_Streaming_SVE_VL_848 pass
11081 17:01:16.976132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 skip
11082 17:01:16.976246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 skip
11083 17:01:16.976360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 skip
11084 17:01:16.979587 arm64_sve-ptrace_Set_Streaming_SVE_VL_864 pass
11085 17:01:16.979917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 skip
11086 17:01:16.980019 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 skip
11087 17:01:16.980124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 skip
11088 17:01:16.980226 arm64_sve-ptrace_Set_Streaming_SVE_VL_880 pass
11089 17:01:16.980339 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 skip
11090 17:01:16.980427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 skip
11091 17:01:16.980540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 skip
11092 17:01:16.980642 arm64_sve-ptrace_Set_Streaming_SVE_VL_896 pass
11093 17:01:16.980731 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 skip
11094 17:01:16.981035 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 skip
11095 17:01:16.981129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 skip
11096 17:01:16.981242 arm64_sve-ptrace_Set_Streaming_SVE_VL_912 pass
11097 17:01:16.981526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 skip
11098 17:01:16.981620 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 skip
11099 17:01:16.981719 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 skip
11100 17:01:16.981804 arm64_sve-ptrace_Set_Streaming_SVE_VL_928 pass
11101 17:01:16.981901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 skip
11102 17:01:16.982242 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 skip
11103 17:01:16.982344 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 skip
11104 17:01:16.982429 arm64_sve-ptrace_Set_Streaming_SVE_VL_944 pass
11105 17:01:16.982521 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 skip
11106 17:01:16.982614 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 skip
11107 17:01:16.982703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 skip
11108 17:01:16.982802 arm64_sve-ptrace_Set_Streaming_SVE_VL_960 pass
11109 17:01:16.983096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 skip
11110 17:01:16.983240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 skip
11111 17:01:16.983378 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 skip
11112 17:01:16.983482 arm64_sve-ptrace_Set_Streaming_SVE_VL_976 pass
11113 17:01:16.987588 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 skip
11114 17:01:16.987881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 skip
11115 17:01:16.988058 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 skip
11116 17:01:16.988249 arm64_sve-ptrace_Set_Streaming_SVE_VL_992 pass
11117 17:01:16.988402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 skip
11118 17:01:16.988560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 skip
11119 17:01:16.988753 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 skip
11120 17:01:16.988886 arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 pass
11121 17:01:16.989014 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 skip
11122 17:01:16.989178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 skip
11123 17:01:16.989338 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 skip
11124 17:01:16.989461 arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 pass
11125 17:01:16.989577 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 skip
11126 17:01:17.002030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 skip
11127 17:01:17.002480 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 skip
11128 17:01:17.002664 arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 pass
11129 17:01:17.002834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 skip
11130 17:01:17.003032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 skip
11131 17:01:17.003196 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 skip
11132 17:01:17.003358 arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 pass
11133 17:01:17.003506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 skip
11134 17:01:17.003685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 skip
11135 17:01:17.003837 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 skip
11136 17:01:17.004011 arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 pass
11137 17:01:17.004189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 skip
11138 17:01:17.005960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 skip
11139 17:01:17.006146 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 skip
11140 17:01:17.006303 arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 pass
11141 17:01:17.006460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 skip
11142 17:01:17.006611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 skip
11143 17:01:17.006758 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 skip
11144 17:01:17.006904 arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 pass
11145 17:01:17.007057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 skip
11146 17:01:17.007211 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 skip
11147 17:01:17.007360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 skip
11148 17:01:17.007514 arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 pass
11149 17:01:17.007668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 skip
11150 17:01:17.007826 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 skip
11151 17:01:17.007964 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 skip
11152 17:01:17.008100 arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 pass
11153 17:01:17.008249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 skip
11154 17:01:17.008380 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 skip
11155 17:01:17.008498 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 skip
11156 17:01:17.008614 arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 pass
11157 17:01:17.008729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 skip
11158 17:01:17.010328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 skip
11159 17:01:17.010520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 skip
11160 17:01:17.010659 arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 pass
11161 17:01:17.010784 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 skip
11162 17:01:17.010947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 skip
11163 17:01:17.011123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 skip
11164 17:01:17.011263 arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 pass
11165 17:01:17.011418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 skip
11166 17:01:17.011617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 skip
11167 17:01:17.011826 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 skip
11168 17:01:17.012007 arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 pass
11169 17:01:17.012186 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 skip
11170 17:01:17.012390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 skip
11171 17:01:17.012560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 skip
11172 17:01:17.012980 arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 pass
11173 17:01:17.013182 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 skip
11174 17:01:17.013397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 skip
11175 17:01:17.013570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 skip
11176 17:01:17.013737 arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 pass
11177 17:01:17.013888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 skip
11178 17:01:17.014045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 skip
11179 17:01:17.014191 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 skip
11180 17:01:17.014355 arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 pass
11181 17:01:17.014510 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 skip
11182 17:01:17.014700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 skip
11183 17:01:17.014874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 skip
11184 17:01:17.015052 arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 pass
11185 17:01:17.015241 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 skip
11186 17:01:17.015393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 skip
11187 17:01:17.015513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 skip
11188 17:01:17.015627 arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 pass
11189 17:01:17.015739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 skip
11190 17:01:17.015852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 skip
11191 17:01:17.015965 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 skip
11192 17:01:17.016081 arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 pass
11193 17:01:17.016194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 skip
11194 17:01:17.016338 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 skip
11195 17:01:17.016460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 skip
11196 17:01:17.016575 arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 pass
11197 17:01:17.016689 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 skip
11198 17:01:17.016802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 skip
11199 17:01:17.019686 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 skip
11200 17:01:17.020129 arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 pass
11201 17:01:17.020351 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 skip
11202 17:01:17.020558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 skip
11203 17:01:17.020806 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 skip
11204 17:01:17.021011 arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 pass
11205 17:01:17.021234 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 skip
11206 17:01:17.021432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 skip
11207 17:01:17.021637 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 skip
11208 17:01:17.021849 arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 pass
11209 17:01:17.022106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 skip
11210 17:01:17.022332 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 skip
11211 17:01:17.022530 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 skip
11212 17:01:17.022697 arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 pass
11213 17:01:17.022853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 skip
11214 17:01:17.023015 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 skip
11215 17:01:17.023177 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 skip
11216 17:01:17.023340 arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 pass
11217 17:01:17.023522 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 skip
11218 17:01:17.023688 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 skip
11219 17:01:17.023812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 skip
11220 17:01:17.023925 arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 pass
11221 17:01:17.024040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 skip
11222 17:01:17.024152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 skip
11223 17:01:17.024263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 skip
11224 17:01:17.024375 arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 pass
11225 17:01:17.024486 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 skip
11226 17:01:17.024596 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 skip
11227 17:01:17.024706 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 skip
11228 17:01:17.024817 arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 pass
11229 17:01:17.027778 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 skip
11230 17:01:17.028227 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 skip
11231 17:01:17.028324 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 skip
11232 17:01:17.028433 arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 pass
11233 17:01:17.028529 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 skip
11234 17:01:17.028649 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 skip
11235 17:01:17.028738 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 skip
11236 17:01:17.028839 arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 pass
11237 17:01:17.028932 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 skip
11238 17:01:17.029042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 skip
11239 17:01:17.029134 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 skip
11240 17:01:17.029253 arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 pass
11241 17:01:17.029348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 skip
11242 17:01:17.029437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 skip
11243 17:01:17.029526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 skip
11244 17:01:17.029622 arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 pass
11245 17:01:17.029749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 skip
11246 17:01:17.030010 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 skip
11247 17:01:17.030111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 skip
11248 17:01:17.030208 arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 pass
11249 17:01:17.030312 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 skip
11250 17:01:17.030450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 skip
11251 17:01:17.030570 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 skip
11252 17:01:17.030703 arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 pass
11253 17:01:17.030817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 skip
11254 17:01:17.031168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 skip
11255 17:01:17.031275 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 skip
11256 17:01:17.031360 arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 pass
11257 17:01:17.031437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 skip
11258 17:01:17.031499 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 skip
11259 17:01:17.035556 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 skip
11260 17:01:17.049427 arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 pass
11261 17:01:17.049940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 skip
11262 17:01:17.050151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 skip
11263 17:01:17.050360 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 skip
11264 17:01:17.050559 arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 pass
11265 17:01:17.050764 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 skip
11266 17:01:17.050930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 skip
11267 17:01:17.051088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 skip
11268 17:01:17.051263 arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 pass
11269 17:01:17.051425 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 skip
11270 17:01:17.051545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 skip
11271 17:01:17.051694 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 skip
11272 17:01:17.051941 arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 pass
11273 17:01:17.052118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 skip
11274 17:01:17.052280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 skip
11275 17:01:17.052439 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 skip
11276 17:01:17.052590 arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 pass
11277 17:01:17.052748 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 skip
11278 17:01:17.052944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 skip
11279 17:01:17.053112 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 skip
11280 17:01:17.053275 arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 pass
11281 17:01:17.053428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 skip
11282 17:01:17.053590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 skip
11283 17:01:17.053777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 skip
11284 17:01:17.053946 arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 pass
11285 17:01:17.054113 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 skip
11286 17:01:17.054272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 skip
11287 17:01:17.054445 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 skip
11288 17:01:17.054732 arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 pass
11289 17:01:17.054936 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 skip
11290 17:01:17.055118 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 skip
11291 17:01:17.055284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 skip
11292 17:01:17.055433 arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 pass
11293 17:01:17.055791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 skip
11294 17:01:17.055951 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 skip
11295 17:01:17.056078 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 skip
11296 17:01:17.056196 arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 pass
11297 17:01:17.056313 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 skip
11298 17:01:17.056428 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 skip
11299 17:01:17.056545 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 skip
11300 17:01:17.056663 arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 pass
11301 17:01:17.056779 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 skip
11302 17:01:17.056897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 skip
11303 17:01:17.057013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 skip
11304 17:01:17.057132 arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 pass
11305 17:01:17.057249 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 skip
11306 17:01:17.057366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 skip
11307 17:01:17.057483 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 skip
11308 17:01:17.059649 arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 pass
11309 17:01:17.060057 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 skip
11310 17:01:17.060169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 skip
11311 17:01:17.060254 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 skip
11312 17:01:17.060349 arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 pass
11313 17:01:17.060431 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 skip
11314 17:01:17.060524 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 skip
11315 17:01:17.060606 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 skip
11316 17:01:17.060698 arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 pass
11317 17:01:17.060793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 skip
11318 17:01:17.061076 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 skip
11319 17:01:17.061313 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 skip
11320 17:01:17.061493 arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 pass
11321 17:01:17.061730 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 skip
11322 17:01:17.061895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 skip
11323 17:01:17.062115 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 skip
11324 17:01:17.062288 arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 pass
11325 17:01:17.062435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 skip
11326 17:01:17.062586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 skip
11327 17:01:17.062778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 skip
11328 17:01:17.062941 arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 pass
11329 17:01:17.063092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 skip
11330 17:01:17.063257 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 skip
11331 17:01:17.063394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 skip
11332 17:01:17.063539 arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 pass
11333 17:01:17.063661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 skip
11334 17:01:17.063777 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 skip
11335 17:01:17.063895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 skip
11336 17:01:17.067695 arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 pass
11337 17:01:17.068137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 skip
11338 17:01:17.068324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 skip
11339 17:01:17.068516 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 skip
11340 17:01:17.068719 arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 pass
11341 17:01:17.068918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 skip
11342 17:01:17.069095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 skip
11343 17:01:17.069298 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 skip
11344 17:01:17.069542 arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 pass
11345 17:01:17.069749 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 skip
11346 17:01:17.069917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 skip
11347 17:01:17.070093 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 skip
11348 17:01:17.070279 arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 pass
11349 17:01:17.070442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 skip
11350 17:01:17.070642 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 skip
11351 17:01:17.070816 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 skip
11352 17:01:17.070975 arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 pass
11353 17:01:17.071170 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 skip
11354 17:01:17.071369 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 skip
11355 17:01:17.071538 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 skip
11356 17:01:17.071669 arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 pass
11357 17:01:17.071783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 skip
11358 17:01:17.071925 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 skip
11359 17:01:17.072046 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 skip
11360 17:01:17.072166 arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 pass
11361 17:01:17.072280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 skip
11362 17:01:17.072394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 skip
11363 17:01:17.075759 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 skip
11364 17:01:17.075911 arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 pass
11365 17:01:17.076318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 skip
11366 17:01:17.076460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 skip
11367 17:01:17.076581 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 skip
11368 17:01:17.076753 arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 pass
11369 17:01:17.076915 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 skip
11370 17:01:17.077083 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 skip
11371 17:01:17.077256 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 skip
11372 17:01:17.077404 arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 pass
11373 17:01:17.077525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 skip
11374 17:01:17.077657 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 skip
11375 17:01:17.077802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 skip
11376 17:01:17.077921 arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 pass
11377 17:01:17.078052 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 skip
11378 17:01:17.078178 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 skip
11379 17:01:17.078298 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 skip
11380 17:01:17.078448 arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 pass
11381 17:01:17.078571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 skip
11382 17:01:17.078703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 skip
11383 17:01:17.078848 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 skip
11384 17:01:17.079006 arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 pass
11385 17:01:17.079123 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 skip
11386 17:01:17.079236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 skip
11387 17:01:17.079348 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 skip
11388 17:01:17.079447 arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 pass
11389 17:01:17.079562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 skip
11390 17:01:17.079661 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 skip
11391 17:01:17.083779 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 skip
11392 17:01:17.084003 arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 pass
11393 17:01:17.084385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 skip
11394 17:01:17.097384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 skip
11395 17:01:17.097778 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 skip
11396 17:01:17.097887 arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 pass
11397 17:01:17.097971 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 skip
11398 17:01:17.098065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 skip
11399 17:01:17.098154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 skip
11400 17:01:17.098249 arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 pass
11401 17:01:17.098333 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 skip
11402 17:01:17.098451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 skip
11403 17:01:17.098746 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 skip
11404 17:01:17.098849 arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 pass
11405 17:01:17.098944 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 skip
11406 17:01:17.099024 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 skip
11407 17:01:17.099115 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 skip
11408 17:01:17.099209 arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 pass
11409 17:01:17.099438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 skip
11410 17:01:17.099753 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 skip
11411 17:01:17.099868 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 skip
11412 17:01:17.100179 arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 pass
11413 17:01:17.100326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 skip
11414 17:01:17.100472 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 skip
11415 17:01:17.100595 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 skip
11416 17:01:17.100740 arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 pass
11417 17:01:17.100896 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 skip
11418 17:01:17.101075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 skip
11419 17:01:17.101232 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 skip
11420 17:01:17.101369 arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 pass
11421 17:01:17.101464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 skip
11422 17:01:17.101553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 skip
11423 17:01:17.101671 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 skip
11424 17:01:17.105201 arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 pass
11425 17:01:17.105368 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 skip
11426 17:01:17.105493 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 skip
11427 17:01:17.105611 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 skip
11428 17:01:17.105748 arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 pass
11429 17:01:17.105863 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 skip
11430 17:01:17.105976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 skip
11431 17:01:17.106089 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 skip
11432 17:01:17.106205 arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 pass
11433 17:01:17.106317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 skip
11434 17:01:17.106429 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 skip
11435 17:01:17.106542 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 skip
11436 17:01:17.106654 arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 pass
11437 17:01:17.106766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 skip
11438 17:01:17.107658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 skip
11439 17:01:17.108080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 skip
11440 17:01:17.108275 arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 pass
11441 17:01:17.108435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 skip
11442 17:01:17.108601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 skip
11443 17:01:17.108802 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 skip
11444 17:01:17.108968 arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 pass
11445 17:01:17.109131 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 skip
11446 17:01:17.109295 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 skip
11447 17:01:17.109454 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 skip
11448 17:01:17.109641 arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 pass
11449 17:01:17.109820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 skip
11450 17:01:17.109973 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 skip
11451 17:01:17.110124 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 skip
11452 17:01:17.110283 arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 pass
11453 17:01:17.110464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 skip
11454 17:01:17.110649 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 skip
11455 17:01:17.110834 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 skip
11456 17:01:17.110983 arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 pass
11457 17:01:17.111137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 skip
11458 17:01:17.111287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 skip
11459 17:01:17.111413 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 skip
11460 17:01:17.111533 arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 pass
11461 17:01:17.111678 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 skip
11462 17:01:17.111802 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 skip
11463 17:01:17.111918 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 skip
11464 17:01:17.112038 arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 pass
11465 17:01:17.112155 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 skip
11466 17:01:17.112272 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 skip
11467 17:01:17.115653 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 skip
11468 17:01:17.116053 arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 pass
11469 17:01:17.116224 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 skip
11470 17:01:17.116392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 skip
11471 17:01:17.116560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 skip
11472 17:01:17.116698 arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 pass
11473 17:01:17.116819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 skip
11474 17:01:17.116939 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 skip
11475 17:01:17.117109 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 skip
11476 17:01:17.117236 arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 pass
11477 17:01:17.117363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 skip
11478 17:01:17.117513 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 skip
11479 17:01:17.117680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 skip
11480 17:01:17.117861 arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 pass
11481 17:01:17.118003 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 skip
11482 17:01:17.118137 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 skip
11483 17:01:17.118269 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 skip
11484 17:01:17.118400 arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 pass
11485 17:01:17.118558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 skip
11486 17:01:17.118690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 skip
11487 17:01:17.118860 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 skip
11488 17:01:17.119023 arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 pass
11489 17:01:17.119169 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 skip
11490 17:01:17.119329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 skip
11491 17:01:17.119482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 skip
11492 17:01:17.119578 arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 pass
11493 17:01:17.119665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 skip
11494 17:01:17.119750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 skip
11495 17:01:17.119836 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 skip
11496 17:01:17.119921 arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 pass
11497 17:01:17.123638 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 skip
11498 17:01:17.124060 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 skip
11499 17:01:17.124228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 skip
11500 17:01:17.124431 arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 pass
11501 17:01:17.124605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 skip
11502 17:01:17.124813 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 skip
11503 17:01:17.124993 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 skip
11504 17:01:17.125162 arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 pass
11505 17:01:17.125346 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 skip
11506 17:01:17.125526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 skip
11507 17:01:17.125740 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 skip
11508 17:01:17.125916 arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 pass
11509 17:01:17.126091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 skip
11510 17:01:17.126261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 skip
11511 17:01:17.126427 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 skip
11512 17:01:17.126594 arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 pass
11513 17:01:17.126759 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 skip
11514 17:01:17.126974 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 skip
11515 17:01:17.127148 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 skip
11516 17:01:17.127313 arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 pass
11517 17:01:17.127449 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 skip
11518 17:01:17.127565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 skip
11519 17:01:17.127680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 skip
11520 17:01:17.127793 arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 pass
11521 17:01:17.127905 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 skip
11522 17:01:17.128017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 skip
11523 17:01:17.128130 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 skip
11524 17:01:17.128248 arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 pass
11525 17:01:17.128388 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 skip
11526 17:01:17.128509 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 skip
11527 17:01:17.131590 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 skip
11528 17:01:17.145630 arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 pass
11529 17:01:17.145797 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 skip
11530 17:01:17.146105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 skip
11531 17:01:17.146228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 skip
11532 17:01:17.146385 arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 pass
11533 17:01:17.146607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 skip
11534 17:01:17.146774 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 skip
11535 17:01:17.147001 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 skip
11536 17:01:17.147177 arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 pass
11537 17:01:17.147328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 skip
11538 17:01:17.147483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 skip
11539 17:01:17.147634 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 skip
11540 17:01:17.147794 arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 pass
11541 17:01:17.147961 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 skip
11542 17:01:17.148129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 skip
11543 17:01:17.148333 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 skip
11544 17:01:17.148499 arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 pass
11545 17:01:17.148665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 skip
11546 17:01:17.148828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 skip
11547 17:01:17.148989 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 skip
11548 17:01:17.149141 arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 pass
11549 17:01:17.149326 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 skip
11550 17:01:17.149496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 skip
11551 17:01:17.150185 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 skip
11552 17:01:17.150418 arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 pass
11553 17:01:17.150586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 skip
11554 17:01:17.150788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 skip
11555 17:01:17.150977 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 skip
11556 17:01:17.151126 arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 pass
11557 17:01:17.151299 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 skip
11558 17:01:17.151477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 skip
11559 17:01:17.151598 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 skip
11560 17:01:17.151713 arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 pass
11561 17:01:17.152059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 skip
11562 17:01:17.152218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 skip
11563 17:01:17.152342 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 skip
11564 17:01:17.152459 arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 pass
11565 17:01:17.152575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 skip
11566 17:01:17.152693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 skip
11567 17:01:17.152810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 skip
11568 17:01:17.152988 arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 pass
11569 17:01:17.153141 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 skip
11570 17:01:17.155650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 skip
11571 17:01:17.156050 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 skip
11572 17:01:17.156160 arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 pass
11573 17:01:17.156250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 skip
11574 17:01:17.156331 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 skip
11575 17:01:17.156431 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 skip
11576 17:01:17.156524 arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 pass
11577 17:01:17.156609 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 skip
11578 17:01:17.156707 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 skip
11579 17:01:17.156794 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 skip
11580 17:01:17.156893 arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 pass
11581 17:01:17.156994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 skip
11582 17:01:17.157296 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 skip
11583 17:01:17.157400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 skip
11584 17:01:17.157496 arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 pass
11585 17:01:17.157818 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 skip
11586 17:01:17.158000 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 skip
11587 17:01:17.158192 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 skip
11588 17:01:17.158359 arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 pass
11589 17:01:17.158551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 skip
11590 17:01:17.158710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 skip
11591 17:01:17.158859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 skip
11592 17:01:17.159034 arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 pass
11593 17:01:17.159189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 skip
11594 17:01:17.159349 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 skip
11595 17:01:17.159513 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 skip
11596 17:01:17.159639 arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 pass
11597 17:01:17.159756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 skip
11598 17:01:17.159873 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 skip
11599 17:01:17.163810 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 skip
11600 17:01:17.164224 arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 pass
11601 17:01:17.164433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 skip
11602 17:01:17.164576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 skip
11603 17:01:17.164770 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 skip
11604 17:01:17.164949 arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 pass
11605 17:01:17.165114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 skip
11606 17:01:17.165274 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 skip
11607 17:01:17.165472 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 skip
11608 17:01:17.165624 arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 pass
11609 17:01:17.165790 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 skip
11610 17:01:17.165949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 skip
11611 17:01:17.166103 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 skip
11612 17:01:17.166251 arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 pass
11613 17:01:17.166409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 skip
11614 17:01:17.166531 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 skip
11615 17:01:17.166647 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 skip
11616 17:01:17.166772 arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 pass
11617 17:01:17.166938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 skip
11618 17:01:17.167063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 skip
11619 17:01:17.167180 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 skip
11620 17:01:17.167297 arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 pass
11621 17:01:17.167411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 skip
11622 17:01:17.167526 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 skip
11623 17:01:17.167664 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 skip
11624 17:01:17.167785 arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 pass
11625 17:01:17.167901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 skip
11626 17:01:17.171683 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 skip
11627 17:01:17.172117 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 skip
11628 17:01:17.172308 arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 pass
11629 17:01:17.172467 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 skip
11630 17:01:17.172651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 skip
11631 17:01:17.172812 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 skip
11632 17:01:17.172969 arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 pass
11633 17:01:17.173121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 skip
11634 17:01:17.173304 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 skip
11635 17:01:17.173460 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 skip
11636 17:01:17.173580 arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 pass
11637 17:01:17.173710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 skip
11638 17:01:17.173834 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 skip
11639 17:01:17.173976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 skip
11640 17:01:17.174126 arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 pass
11641 17:01:17.174280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 skip
11642 17:01:17.174435 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 skip
11643 17:01:17.174619 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 skip
11644 17:01:17.174779 arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 pass
11645 17:01:17.174935 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 skip
11646 17:01:17.175091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 skip
11647 17:01:17.175284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 skip
11648 17:01:17.175435 arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 pass
11649 17:01:17.175553 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 skip
11650 17:01:17.175669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 skip
11651 17:01:17.175784 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 skip
11652 17:01:17.175903 arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 pass
11653 17:01:17.176041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 skip
11654 17:01:17.179602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 skip
11655 17:01:17.179899 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 skip
11656 17:01:17.179985 arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 pass
11657 17:01:17.180085 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 skip
11658 17:01:17.180176 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 skip
11659 17:01:17.180467 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 skip
11660 17:01:17.180578 arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 pass
11661 17:01:17.180691 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 skip
11662 17:01:17.194833 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 skip
11663 17:01:17.195070 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 skip
11664 17:01:17.195381 arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 pass
11665 17:01:17.195483 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 skip
11666 17:01:17.195563 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 skip
11667 17:01:17.195656 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 skip
11668 17:01:17.196037 arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 pass
11669 17:01:17.196136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 skip
11670 17:01:17.196413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 skip
11671 17:01:17.196511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 skip
11672 17:01:17.196591 arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 pass
11673 17:01:17.196684 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 skip
11674 17:01:17.196763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 skip
11675 17:01:17.196841 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 skip
11676 17:01:17.196933 arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 pass
11677 17:01:17.197013 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 skip
11678 17:01:17.197109 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 skip
11679 17:01:17.197409 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 skip
11680 17:01:17.197495 arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 pass
11681 17:01:17.197570 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 skip
11682 17:01:17.197660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 skip
11683 17:01:17.197963 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 skip
11684 17:01:17.198089 arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 pass
11685 17:01:17.198208 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 skip
11686 17:01:17.198329 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 skip
11687 17:01:17.198432 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 skip
11688 17:01:17.198519 arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 pass
11689 17:01:17.198597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 skip
11690 17:01:17.198676 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 skip
11691 17:01:17.198767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 skip
11692 17:01:17.198845 arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 pass
11693 17:01:17.198922 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 skip
11694 17:01:17.199027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 skip
11695 17:01:17.199113 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 skip
11696 17:01:17.199207 arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 pass
11697 17:01:17.199301 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 skip
11698 17:01:17.203725 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 skip
11699 17:01:17.204136 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 skip
11700 17:01:17.204237 arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 pass
11701 17:01:17.204320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 skip
11702 17:01:17.204418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 skip
11703 17:01:17.204499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 skip
11704 17:01:17.204578 arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 pass
11705 17:01:17.204670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 skip
11706 17:01:17.204960 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 skip
11707 17:01:17.205083 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 skip
11708 17:01:17.205175 arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 pass
11709 17:01:17.205267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 skip
11710 17:01:17.205366 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 skip
11711 17:01:17.205450 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 skip
11712 17:01:17.205550 arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 pass
11713 17:01:17.205872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 skip
11714 17:01:17.206030 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 skip
11715 17:01:17.206176 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 skip
11716 17:01:17.206503 arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 pass
11717 17:01:17.206602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 skip
11718 17:01:17.206679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 skip
11719 17:01:17.206769 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 skip
11720 17:01:17.206848 arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 pass
11721 17:01:17.206938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 skip
11722 17:01:17.207032 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 skip
11723 17:01:17.207132 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 skip
11724 17:01:17.207420 arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 pass
11725 17:01:17.211735 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 skip
11726 17:01:17.212107 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 skip
11727 17:01:17.212208 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 skip
11728 17:01:17.212302 arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 pass
11729 17:01:17.212398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 skip
11730 17:01:17.212496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 skip
11731 17:01:17.212987 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 skip
11732 17:01:17.213088 arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 pass
11733 17:01:17.213171 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 skip
11734 17:01:17.213266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 skip
11735 17:01:17.213361 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 skip
11736 17:01:17.213465 arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 pass
11737 17:01:17.213562 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 skip
11738 17:01:17.213668 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 skip
11739 17:01:17.213966 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 skip
11740 17:01:17.214063 arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 pass
11741 17:01:17.214164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 skip
11742 17:01:17.214496 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 skip
11743 17:01:17.214617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 skip
11744 17:01:17.214712 arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 pass
11745 17:01:17.214989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 skip
11746 17:01:17.215086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 skip
11747 17:01:17.215194 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 skip
11748 17:01:17.215274 arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 pass
11749 17:01:17.215363 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 skip
11750 17:01:17.219752 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 skip
11751 17:01:17.220188 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 skip
11752 17:01:17.220307 arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 pass
11753 17:01:17.220392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 skip
11754 17:01:17.220487 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 skip
11755 17:01:17.220568 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 skip
11756 17:01:17.220661 arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 pass
11757 17:01:17.220754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 skip
11758 17:01:17.221069 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 skip
11759 17:01:17.221178 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 skip
11760 17:01:17.221487 arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 pass
11761 17:01:17.221578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 skip
11762 17:01:17.221682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 skip
11763 17:01:17.221777 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 skip
11764 17:01:17.221874 arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 pass
11765 17:01:17.222200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 skip
11766 17:01:17.222320 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 skip
11767 17:01:17.222425 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 skip
11768 17:01:17.222520 arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 pass
11769 17:01:17.222810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 skip
11770 17:01:17.222923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 skip
11771 17:01:17.223023 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 skip
11772 17:01:17.223314 arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 pass
11773 17:01:17.223418 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 skip
11774 17:01:17.227793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 skip
11775 17:01:17.228246 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 skip
11776 17:01:17.228347 arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 pass
11777 17:01:17.228434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 skip
11778 17:01:17.228534 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 skip
11779 17:01:17.228630 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 skip
11780 17:01:17.228724 arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 pass
11781 17:01:17.228816 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 skip
11782 17:01:17.229132 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 skip
11783 17:01:17.229238 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 skip
11784 17:01:17.229330 arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 pass
11785 17:01:17.229423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 skip
11786 17:01:17.229740 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 skip
11787 17:01:17.229833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 skip
11788 17:01:17.230126 arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 pass
11789 17:01:17.230225 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 skip
11790 17:01:17.230318 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 skip
11791 17:01:17.230396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 skip
11792 17:01:17.230502 arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 pass
11793 17:01:17.230617 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 skip
11794 17:01:17.230899 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 skip
11795 17:01:17.230991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 skip
11796 17:01:17.250808 arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 pass
11797 17:01:17.251470 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 skip
11798 17:01:17.251641 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 skip
11799 17:01:17.251779 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 skip
11800 17:01:17.251919 arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 pass
11801 17:01:17.252062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 skip
11802 17:01:17.252450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 skip
11803 17:01:17.252617 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 skip
11804 17:01:17.252795 arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 pass
11805 17:01:17.252947 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 skip
11806 17:01:17.253100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 skip
11807 17:01:17.253312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 skip
11808 17:01:17.253471 arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 pass
11809 17:01:17.253705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 skip
11810 17:01:17.253869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 skip
11811 17:01:17.254106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 skip
11812 17:01:17.254258 arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 pass
11813 17:01:17.254433 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 skip
11814 17:01:17.254548 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 skip
11815 17:01:17.254662 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 skip
11816 17:01:17.254772 arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 pass
11817 17:01:17.254882 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 skip
11818 17:01:17.254996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 skip
11819 17:01:17.255106 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 skip
11820 17:01:17.255234 arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 pass
11821 17:01:17.255348 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 skip
11822 17:01:17.255462 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 skip
11823 17:01:17.255575 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 skip
11824 17:01:17.255689 arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 pass
11825 17:01:17.255829 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 skip
11826 17:01:17.259817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 skip
11827 17:01:17.260271 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 skip
11828 17:01:17.260407 arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 pass
11829 17:01:17.260551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 skip
11830 17:01:17.260710 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 skip
11831 17:01:17.260845 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 skip
11832 17:01:17.260969 arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 pass
11833 17:01:17.261122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 skip
11834 17:01:17.261300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 skip
11835 17:01:17.261448 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 skip
11836 17:01:17.261601 arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 pass
11837 17:01:17.261727 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 skip
11838 17:01:17.261854 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 skip
11839 17:01:17.261998 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 skip
11840 17:01:17.262144 arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 pass
11841 17:01:17.262263 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 skip
11842 17:01:17.262390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 skip
11843 17:01:17.262529 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 skip
11844 17:01:17.262616 arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 pass
11845 17:01:17.262705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 skip
11846 17:01:17.262850 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 skip
11847 17:01:17.263150 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 skip
11848 17:01:17.263248 arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 pass
11849 17:01:17.263334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 skip
11850 17:01:17.263410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 skip
11851 17:01:17.263512 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 skip
11852 17:01:17.267714 arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 pass
11853 17:01:17.268122 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 skip
11854 17:01:17.268221 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 skip
11855 17:01:17.268317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 skip
11856 17:01:17.268397 arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 pass
11857 17:01:17.268495 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 skip
11858 17:01:17.268776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 skip
11859 17:01:17.268873 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 skip
11860 17:01:17.269217 arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 pass
11861 17:01:17.269311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 skip
11862 17:01:17.269407 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 skip
11863 17:01:17.269684 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 skip
11864 17:01:17.269780 arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 pass
11865 17:01:17.270218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 skip
11866 17:01:17.270317 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 skip
11867 17:01:17.270410 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 skip
11868 17:01:17.270508 arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 pass
11869 17:01:17.270610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 skip
11870 17:01:17.270938 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 skip
11871 17:01:17.271039 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 skip
11872 17:01:17.271134 arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 pass
11873 17:01:17.271214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 skip
11874 17:01:17.271488 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 skip
11875 17:01:17.275677 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 skip
11876 17:01:17.276019 arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 pass
11877 17:01:17.276121 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 skip
11878 17:01:17.276214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 skip
11879 17:01:17.276306 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 skip
11880 17:01:17.276398 arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 pass
11881 17:01:17.276677 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 skip
11882 17:01:17.276786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 skip
11883 17:01:17.277056 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 skip
11884 17:01:17.277167 arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 pass
11885 17:01:17.277497 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 skip
11886 17:01:17.277597 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 skip
11887 17:01:17.277711 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 skip
11888 17:01:17.277807 arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 pass
11889 17:01:17.277897 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 skip
11890 17:01:17.278181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 skip
11891 17:01:17.278292 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 skip
11892 17:01:17.278393 arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 pass
11893 17:01:17.278679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 skip
11894 17:01:17.278785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 skip
11895 17:01:17.278882 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 skip
11896 17:01:17.279170 arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 pass
11897 17:01:17.279280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 skip
11898 17:01:17.279373 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 skip
11899 17:01:17.283733 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 skip
11900 17:01:17.284025 arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 pass
11901 17:01:17.284110 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 skip
11902 17:01:17.284201 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 skip
11903 17:01:17.284293 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 skip
11904 17:01:17.284585 arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 pass
11905 17:01:17.284718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 skip
11906 17:01:17.284843 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 skip
11907 17:01:17.285120 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 skip
11908 17:01:17.285224 arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 pass
11909 17:01:17.285310 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 skip
11910 17:01:17.285650 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 skip
11911 17:01:17.285792 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 skip
11912 17:01:17.286092 arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 pass
11913 17:01:17.286255 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 skip
11914 17:01:17.286381 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 skip
11915 17:01:17.286520 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 skip
11916 17:01:17.286626 arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 pass
11917 17:01:17.286712 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 skip
11918 17:01:17.286794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 skip
11919 17:01:17.286874 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 skip
11920 17:01:17.286971 arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 pass
11921 17:01:17.287055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 skip
11922 17:01:17.287151 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 skip
11923 17:01:17.287248 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 skip
11924 17:01:17.287344 arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 pass
11925 17:01:17.291782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 skip
11926 17:01:17.291988 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 skip
11927 17:01:17.292334 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 skip
11928 17:01:17.292465 arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 pass
11929 17:01:17.292590 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 skip
11930 17:01:17.306602 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 skip
11931 17:01:17.307102 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 skip
11932 17:01:17.307302 arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 pass
11933 17:01:17.307448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 skip
11934 17:01:17.307607 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 skip
11935 17:01:17.307801 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 skip
11936 17:01:17.307975 arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 pass
11937 17:01:17.308145 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 skip
11938 17:01:17.308334 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 skip
11939 17:01:17.308499 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 skip
11940 17:01:17.308660 arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 pass
11941 17:01:17.308820 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 skip
11942 17:01:17.309016 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 skip
11943 17:01:17.309183 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 skip
11944 17:01:17.309345 arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 pass
11945 17:01:17.309519 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 skip
11946 17:01:17.309772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 skip
11947 17:01:17.309943 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 skip
11948 17:01:17.310081 arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 pass
11949 17:01:17.310256 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 skip
11950 17:01:17.310437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 skip
11951 17:01:17.310625 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 skip
11952 17:01:17.310792 arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 pass
11953 17:01:17.310954 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 skip
11954 17:01:17.311117 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 skip
11955 17:01:17.311278 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 skip
11956 17:01:17.311431 arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 pass
11957 17:01:17.311579 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 skip
11958 17:01:17.311701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 skip
11959 17:01:17.311818 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 skip
11960 17:01:17.311933 arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 pass
11961 17:01:17.312047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 skip
11962 17:01:17.315639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 skip
11963 17:01:17.316030 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 skip
11964 17:01:17.316132 arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 pass
11965 17:01:17.316217 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 skip
11966 17:01:17.316311 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 skip
11967 17:01:17.316395 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 skip
11968 17:01:17.316491 arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 pass
11969 17:01:17.316582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 skip
11970 17:01:17.316698 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 skip
11971 17:01:17.316805 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 skip
11972 17:01:17.316909 arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 pass
11973 17:01:17.317200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 skip
11974 17:01:17.317309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 skip
11975 17:01:17.317423 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 skip
11976 17:01:17.317522 arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 pass
11977 17:01:17.317637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 skip
11978 17:01:17.317756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 skip
11979 17:01:17.318036 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 skip
11980 17:01:17.318151 arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 pass
11981 17:01:17.318453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 skip
11982 17:01:17.318541 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 skip
11983 17:01:17.318859 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 skip
11984 17:01:17.318945 arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 pass
11985 17:01:17.319209 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 skip
11986 17:01:17.319302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 skip
11987 17:01:17.319385 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 skip
11988 17:01:17.323610 arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 pass
11989 17:01:17.323931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 skip
11990 17:01:17.324038 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 skip
11991 17:01:17.324123 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 skip
11992 17:01:17.324463 arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 pass
11993 17:01:17.324665 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 skip
11994 17:01:17.324869 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 skip
11995 17:01:17.325033 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 skip
11996 17:01:17.325185 arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 pass
11997 17:01:17.325575 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 skip
11998 17:01:17.325756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 skip
11999 17:01:17.325950 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 skip
12000 17:01:17.326150 arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 pass
12001 17:01:17.326345 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 skip
12002 17:01:17.326558 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 skip
12003 17:01:17.326703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 skip
12004 17:01:17.326847 arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 pass
12005 17:01:17.326992 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 skip
12006 17:01:17.327136 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 skip
12007 17:01:17.327312 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 skip
12008 17:01:17.327451 arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 pass
12009 17:01:17.327595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 skip
12010 17:01:17.327737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 skip
12011 17:01:17.327877 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 skip
12012 17:01:17.328050 arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 pass
12013 17:01:17.331660 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 skip
12014 17:01:17.332055 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 skip
12015 17:01:17.332211 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 skip
12016 17:01:17.332389 arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 pass
12017 17:01:17.332561 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 skip
12018 17:01:17.332771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 skip
12019 17:01:17.332911 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 skip
12020 17:01:17.333084 arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 pass
12021 17:01:17.333511 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 skip
12022 17:01:17.333686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 skip
12023 17:01:17.333846 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 skip
12024 17:01:17.334075 arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 pass
12025 17:01:17.334335 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 skip
12026 17:01:17.334525 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 skip
12027 17:01:17.334696 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 skip
12028 17:01:17.334923 arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 pass
12029 17:01:17.335106 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 skip
12030 17:01:17.335303 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 skip
12031 17:01:17.335500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 skip
12032 17:01:17.335629 arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 pass
12033 17:01:17.335743 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 skip
12034 17:01:17.335856 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 skip
12035 17:01:17.335970 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 skip
12036 17:01:17.336081 arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 pass
12037 17:01:17.336193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 skip
12038 17:01:17.339636 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 skip
12039 17:01:17.340063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 skip
12040 17:01:17.340250 arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 pass
12041 17:01:17.340397 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 skip
12042 17:01:17.340576 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 skip
12043 17:01:17.340739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 skip
12044 17:01:17.340904 arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 pass
12045 17:01:17.341072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 skip
12046 17:01:17.341280 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 skip
12047 17:01:17.341469 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 skip
12048 17:01:17.341631 arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 pass
12049 17:01:17.341872 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 skip
12050 17:01:17.342120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 skip
12051 17:01:17.342329 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 skip
12052 17:01:17.342521 arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 pass
12053 17:01:17.342700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 skip
12054 17:01:17.342876 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 skip
12055 17:01:17.343032 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 skip
12056 17:01:17.343200 arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 pass
12057 17:01:17.343327 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 skip
12058 17:01:17.343444 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 skip
12059 17:01:17.343560 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 skip
12060 17:01:17.343678 arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 pass
12061 17:01:17.343795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 skip
12062 17:01:17.343913 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 skip
12063 17:01:17.344031 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 skip
12064 17:01:17.357153 arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 pass
12065 17:01:17.357583 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 skip
12066 17:01:17.357791 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 skip
12067 17:01:17.357996 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 skip
12068 17:01:17.358166 arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 pass
12069 17:01:17.358379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 skip
12070 17:01:17.358643 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 skip
12071 17:01:17.358851 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 skip
12072 17:01:17.359022 arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 pass
12073 17:01:17.359179 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 skip
12074 17:01:17.359330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 skip
12075 17:01:17.359517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 skip
12076 17:01:17.359668 arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 pass
12077 17:01:17.359855 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 skip
12078 17:01:17.360025 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 skip
12079 17:01:17.360226 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 skip
12080 17:01:17.360374 arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 pass
12081 17:01:17.360560 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 skip
12082 17:01:17.360694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 skip
12083 17:01:17.360832 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 skip
12084 17:01:17.360936 arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 pass
12085 17:01:17.361071 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 skip
12086 17:01:17.361199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 skip
12087 17:01:17.361317 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 skip
12088 17:01:17.361457 arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 pass
12089 17:01:17.361868 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 skip
12090 17:01:17.361993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 skip
12091 17:01:17.362092 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 skip
12092 17:01:17.362226 arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 pass
12093 17:01:17.362343 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 skip
12094 17:01:17.362438 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 skip
12095 17:01:17.362573 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 skip
12096 17:01:17.362889 arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 pass
12097 17:01:17.362993 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 skip
12098 17:01:17.363092 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 skip
12099 17:01:17.363179 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 skip
12100 17:01:17.363269 arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 pass
12101 17:01:17.363372 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 skip
12102 17:01:17.363439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 skip
12103 17:01:17.363498 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 skip
12104 17:01:17.363555 arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 pass
12105 17:01:17.363625 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 skip
12106 17:01:17.363686 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 skip
12107 17:01:17.363744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 skip
12108 17:01:17.367628 arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 pass
12109 17:01:17.367940 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 skip
12110 17:01:17.368063 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 skip
12111 17:01:17.368154 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 skip
12112 17:01:17.368257 arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 pass
12113 17:01:17.368354 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 skip
12114 17:01:17.368453 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 skip
12115 17:01:17.368755 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 skip
12116 17:01:17.368872 arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 pass
12117 17:01:17.368969 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 skip
12118 17:01:17.369250 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 skip
12119 17:01:17.369353 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 skip
12120 17:01:17.369438 arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 pass
12121 17:01:17.369685 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 skip
12122 17:01:17.369785 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 skip
12123 17:01:17.369879 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 skip
12124 17:01:17.370155 arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 pass
12125 17:01:17.370252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 skip
12126 17:01:17.370546 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 skip
12127 17:01:17.370648 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 skip
12128 17:01:17.370748 arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 pass
12129 17:01:17.370828 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 skip
12130 17:01:17.370919 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 skip
12131 17:01:17.371114 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 skip
12132 17:01:17.371231 arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 pass
12133 17:01:17.371512 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 skip
12134 17:01:17.375669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 skip
12135 17:01:17.376085 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 skip
12136 17:01:17.376247 arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 pass
12137 17:01:17.376408 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 skip
12138 17:01:17.376591 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 skip
12139 17:01:17.376760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 skip
12140 17:01:17.376914 arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 pass
12141 17:01:17.377065 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 skip
12142 17:01:17.377245 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 skip
12143 17:01:17.377400 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 skip
12144 17:01:17.377558 arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 pass
12145 17:01:17.377732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 skip
12146 17:01:17.377918 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 skip
12147 17:01:17.378080 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 skip
12148 17:01:17.378237 arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 pass
12149 17:01:17.378394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 skip
12150 17:01:17.378581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 skip
12151 17:01:17.378739 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 skip
12152 17:01:17.378890 arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 pass
12153 17:01:17.379045 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 skip
12154 17:01:17.379205 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 skip
12155 17:01:17.379396 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 skip
12156 17:01:17.379556 arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 pass
12157 17:01:17.379675 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 skip
12158 17:01:17.379788 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 skip
12159 17:01:17.379902 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 skip
12160 17:01:17.380015 arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 pass
12161 17:01:17.380128 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 skip
12162 17:01:17.387768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 skip
12163 17:01:17.388299 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 skip
12164 17:01:17.388465 arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 pass
12165 17:01:17.388623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 skip
12166 17:01:17.388763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 skip
12167 17:01:17.388939 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 skip
12168 17:01:17.389101 arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 pass
12169 17:01:17.389240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 skip
12170 17:01:17.389377 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 skip
12171 17:01:17.389517 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 skip
12172 17:01:17.389703 arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 pass
12173 17:01:17.389805 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 skip
12174 17:01:17.389901 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 skip
12175 17:01:17.389990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 skip
12176 17:01:17.390086 arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 pass
12177 17:01:17.390199 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 skip
12178 17:01:17.390289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 skip
12179 17:01:17.390379 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 skip
12180 17:01:17.390487 arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 pass
12181 17:01:17.390582 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 skip
12182 17:01:17.390693 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 skip
12183 17:01:17.390800 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 skip
12184 17:01:17.390896 arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 pass
12185 17:01:17.390990 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 skip
12186 17:01:17.391261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 skip
12187 17:01:17.391363 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 skip
12188 17:01:17.395768 arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 pass
12189 17:01:17.396157 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 skip
12190 17:01:17.396240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 skip
12191 17:01:17.396321 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 skip
12192 17:01:17.396400 arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 pass
12193 17:01:17.396477 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 skip
12194 17:01:17.396745 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 skip
12195 17:01:17.396838 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 skip
12196 17:01:17.396930 arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 pass
12197 17:01:17.397200 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 skip
12198 17:01:17.407728 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 skip
12199 17:01:17.408129 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 skip
12200 17:01:17.408201 arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 pass
12201 17:01:17.408271 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 skip
12202 17:01:17.408350 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 skip
12203 17:01:17.408599 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 skip
12204 17:01:17.408671 arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 pass
12205 17:01:17.408739 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 skip
12206 17:01:17.408809 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 skip
12207 17:01:17.408886 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 skip
12208 17:01:17.408952 arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 pass
12209 17:01:17.409041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 skip
12210 17:01:17.409305 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 skip
12211 17:01:17.409386 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 skip
12212 17:01:17.409633 arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 pass
12213 17:01:17.409720 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 skip
12214 17:01:17.409981 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 skip
12215 17:01:17.410063 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 skip
12216 17:01:17.410137 arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 pass
12217 17:01:17.410210 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 skip
12218 17:01:17.410464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 skip
12219 17:01:17.410545 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 skip
12220 17:01:17.410797 arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 pass
12221 17:01:17.410886 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 skip
12222 17:01:17.411298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 skip
12223 17:01:17.411375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 skip
12224 17:01:17.415651 arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 pass
12225 17:01:17.415963 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 skip
12226 17:01:17.416036 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 skip
12227 17:01:17.416297 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 skip
12228 17:01:17.416380 arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 pass
12229 17:01:17.416696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 skip
12230 17:01:17.416767 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 skip
12231 17:01:17.417013 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 skip
12232 17:01:17.417111 arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 pass
12233 17:01:17.417185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 skip
12234 17:01:17.417445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 skip
12235 17:01:17.417673 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 skip
12236 17:01:17.417751 arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 pass
12237 17:01:17.417996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 skip
12238 17:01:17.418072 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 skip
12239 17:01:17.418323 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 skip
12240 17:01:17.418404 arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 pass
12241 17:01:17.418651 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 skip
12242 17:01:17.418726 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 skip
12243 17:01:17.418976 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 skip
12244 17:01:17.419219 arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 pass
12245 17:01:17.419284 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 skip
12246 17:01:17.419355 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 skip
12247 17:01:17.423564 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 skip
12248 17:01:17.423819 arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 pass
12249 17:01:17.423895 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 skip
12250 17:01:17.423968 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 skip
12251 17:01:17.424228 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 skip
12252 17:01:17.424317 arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 pass
12253 17:01:17.424566 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 skip
12254 17:01:17.424648 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 skip
12255 17:01:17.424895 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 skip
12256 17:01:17.424961 arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 pass
12257 17:01:17.425232 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 skip
12258 17:01:17.425307 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 skip
12259 17:01:17.425554 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 skip
12260 17:01:17.425621 arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 pass
12261 17:01:17.425701 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 skip
12262 17:01:17.425950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 skip
12263 17:01:17.426201 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 skip
12264 17:01:17.426277 arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 pass
12265 17:01:17.426517 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 skip
12266 17:01:17.426592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 skip
12267 17:01:17.426843 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 skip
12268 17:01:17.426920 arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 pass
12269 17:01:17.427164 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 skip
12270 17:01:17.427240 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 skip
12271 17:01:17.431544 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 skip
12272 17:01:17.431840 arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 pass
12273 17:01:17.431949 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 skip
12274 17:01:17.432059 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 skip
12275 17:01:17.432340 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 skip
12276 17:01:17.432423 arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 pass
12277 17:01:17.432729 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 skip
12278 17:01:17.432817 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 skip
12279 17:01:17.432925 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 skip
12280 17:01:17.433002 arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 pass
12281 17:01:17.433670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 skip
12282 17:01:17.433771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 skip
12283 17:01:17.433858 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 skip
12284 17:01:17.433939 arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 pass
12285 17:01:17.434023 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 skip
12286 17:01:17.434300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 skip
12287 17:01:17.434397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 skip
12288 17:01:17.434513 arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 pass
12289 17:01:17.434605 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 skip
12290 17:01:17.434696 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 skip
12291 17:01:17.434774 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 skip
12292 17:01:17.434838 arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 pass
12293 17:01:17.435409 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 skip
12294 17:01:17.435705 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 skip
12295 17:01:17.435795 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 skip
12296 17:01:17.435876 arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 pass
12297 17:01:17.440040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 skip
12298 17:01:17.440392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 skip
12299 17:01:17.440477 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 skip
12300 17:01:17.440557 arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 pass
12301 17:01:17.440631 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 skip
12302 17:01:17.442460 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 skip
12303 17:01:17.442561 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 skip
12304 17:01:17.442651 arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 pass
12305 17:01:17.442756 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 skip
12306 17:01:17.442845 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 skip
12307 17:01:17.442934 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 skip
12308 17:01:17.443020 arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 pass
12309 17:01:17.443099 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 skip
12310 17:01:17.443181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 skip
12311 17:01:17.443263 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 skip
12312 17:01:17.443349 arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 pass
12313 17:01:17.443434 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 skip
12314 17:01:17.443508 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 skip
12315 17:01:17.443762 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 skip
12316 17:01:17.443853 arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 pass
12317 17:01:17.443950 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 skip
12318 17:01:17.444027 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 skip
12319 17:01:17.444100 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 skip
12320 17:01:17.444174 arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 pass
12321 17:01:17.447600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 skip
12322 17:01:17.447937 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 skip
12323 17:01:17.448026 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 skip
12324 17:01:17.448134 arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 pass
12325 17:01:17.448222 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 skip
12326 17:01:17.448324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 skip
12327 17:01:17.448603 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 skip
12328 17:01:17.448677 arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 pass
12329 17:01:17.448768 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 skip
12330 17:01:17.448860 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 skip
12331 17:01:17.449149 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 skip
12332 17:01:17.459690 arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 pass
12333 17:01:17.460105 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 skip
12334 17:01:17.460192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 skip
12335 17:01:17.460302 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 skip
12336 17:01:17.460377 arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 pass
12337 17:01:17.460658 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 skip
12338 17:01:17.460763 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 skip
12339 17:01:17.460864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 skip
12340 17:01:17.461154 arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 pass
12341 17:01:17.461261 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 skip
12342 17:01:17.461362 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 skip
12343 17:01:17.461626 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 skip
12344 17:01:17.462189 arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 pass
12345 17:01:17.462262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 skip
12346 17:01:17.462328 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 skip
12347 17:01:17.462393 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 skip
12348 17:01:17.462642 arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 pass
12349 17:01:17.462714 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 skip
12350 17:01:17.462782 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 skip
12351 17:01:17.462871 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 skip
12352 17:01:17.462937 arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 pass
12353 17:01:17.463012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 skip
12354 17:01:17.463266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 skip
12355 17:01:17.463525 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 skip
12356 17:01:17.467615 arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 pass
12357 17:01:17.467989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 skip
12358 17:01:17.468103 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 skip
12359 17:01:17.468204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 skip
12360 17:01:17.468287 arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 pass
12361 17:01:17.468379 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 skip
12362 17:01:17.468473 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 skip
12363 17:01:17.468567 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 skip
12364 17:01:17.468660 arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 pass
12365 17:01:17.468952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 skip
12366 17:01:17.469070 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 skip
12367 17:01:17.469364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 skip
12368 17:01:17.469466 arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 pass
12369 17:01:17.469565 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 skip
12370 17:01:17.469632 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 skip
12371 17:01:17.469744 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 skip
12372 17:01:17.469861 arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 pass
12373 17:01:17.470193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 skip
12374 17:01:17.470298 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 skip
12375 17:01:17.470397 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 skip
12376 17:01:17.470494 arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 pass
12377 17:01:17.470695 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 skip
12378 17:01:17.470801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 skip
12379 17:01:17.470906 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 skip
12380 17:01:17.470992 arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 pass
12381 17:01:17.471088 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 skip
12382 17:01:17.471185 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 skip
12383 17:01:17.471282 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 skip
12384 17:01:17.471378 arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 pass
12385 17:01:17.475793 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 skip
12386 17:01:17.476218 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 skip
12387 17:01:17.476314 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 skip
12388 17:01:17.476387 arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 pass
12389 17:01:17.476478 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 skip
12390 17:01:17.476573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 skip
12391 17:01:17.476646 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 skip
12392 17:01:17.476736 arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 pass
12393 17:01:17.476848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 skip
12394 17:01:17.477139 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 skip
12395 17:01:17.477237 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 skip
12396 17:01:17.477340 arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 pass
12397 17:01:17.477452 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 skip
12398 17:01:17.477554 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 skip
12399 17:01:17.477666 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 skip
12400 17:01:17.477781 arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 pass
12401 17:01:17.477889 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 skip
12402 17:01:17.477985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 skip
12403 17:01:17.478096 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 skip
12404 17:01:17.478222 arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 pass
12405 17:01:17.478337 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 skip
12406 17:01:17.478448 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 skip
12407 17:01:17.478565 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 skip
12408 17:01:17.478689 arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 pass
12409 17:01:17.478786 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 skip
12410 17:01:17.478906 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 skip
12411 17:01:17.479006 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 skip
12412 17:01:17.479092 arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 pass
12413 17:01:17.479189 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 skip
12414 17:01:17.479287 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 skip
12415 17:01:17.479604 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 skip
12416 17:01:17.483785 arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 pass
12417 17:01:17.484062 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 skip
12418 17:01:17.484395 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 skip
12419 17:01:17.484500 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 skip
12420 17:01:17.484581 arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 pass
12421 17:01:17.484690 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 skip
12422 17:01:17.484772 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 skip
12423 17:01:17.484857 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 skip
12424 17:01:17.484958 arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 pass
12425 17:01:17.485040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 skip
12426 17:01:17.485120 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 skip
12427 17:01:17.485198 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 skip
12428 17:01:17.485277 arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 pass
12429 17:01:17.485374 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 skip
12430 17:01:17.485461 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 skip
12431 17:01:17.485543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 skip
12432 17:01:17.485641 arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 pass
12433 17:01:17.485952 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 skip
12434 17:01:17.486041 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 skip
12435 17:01:17.486125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 skip
12436 17:01:17.486222 arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 pass
12437 17:01:17.486309 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 skip
12438 17:01:17.486406 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 skip
12439 17:01:17.486713 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 skip
12440 17:01:17.486819 arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 pass
12441 17:01:17.486921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 skip
12442 17:01:17.487018 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 skip
12443 17:01:17.487138 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 skip
12444 17:01:17.487250 arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 pass
12445 17:01:17.487543 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 skip
12446 17:01:17.491623 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 skip
12447 17:01:17.491991 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 skip
12448 17:01:17.492081 arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 pass
12449 17:01:17.492172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 skip
12450 17:01:17.492445 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 skip
12451 17:01:17.492539 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 skip
12452 17:01:17.492630 arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 pass
12453 17:01:17.492903 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 skip
12454 17:01:17.492996 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 skip
12455 17:01:17.493271 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 skip
12456 17:01:17.493353 arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 pass
12457 17:01:17.493443 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 skip
12458 17:01:17.493533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 skip
12459 17:01:17.493842 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 skip
12460 17:01:17.493947 arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 pass
12461 17:01:17.494039 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 skip
12462 17:01:17.494129 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 skip
12463 17:01:17.494415 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 skip
12464 17:01:17.494513 arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 pass
12465 17:01:17.494618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 skip
12466 17:01:17.509270 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 skip
12467 17:01:17.509675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 skip
12468 17:01:17.509766 arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 pass
12469 17:01:17.509846 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 skip
12470 17:01:17.509946 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 skip
12471 17:01:17.510028 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 skip
12472 17:01:17.510122 arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 pass
12473 17:01:17.510411 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 skip
12474 17:01:17.510520 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 skip
12475 17:01:17.510633 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 skip
12476 17:01:17.510776 arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 pass
12477 17:01:17.511096 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 skip
12478 17:01:17.511214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 skip
12479 17:01:17.511338 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 skip
12480 17:01:17.511645 arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 pass
12481 17:01:17.511771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 skip
12482 17:01:17.511890 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 skip
12483 17:01:17.512009 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 skip
12484 17:01:17.512116 arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 pass
12485 17:01:17.512266 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 skip
12486 17:01:17.512390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 skip
12487 17:01:17.512498 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 skip
12488 17:01:17.512601 arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 pass
12489 17:01:17.512703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 skip
12490 17:01:17.512909 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 skip
12491 17:01:17.513041 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 skip
12492 17:01:17.513150 arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 pass
12493 17:01:17.513252 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 skip
12494 17:01:17.513357 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 skip
12495 17:01:17.513457 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 skip
12496 17:01:17.513554 arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 pass
12497 17:01:17.513862 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 skip
12498 17:01:17.513986 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 skip
12499 17:01:17.514289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 skip
12500 17:01:17.514396 arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 pass
12501 17:01:17.514751 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 skip
12502 17:01:17.514853 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 skip
12503 17:01:17.514935 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 skip
12504 17:01:17.515282 arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 pass
12505 17:01:17.515384 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 skip
12506 17:01:17.515466 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 skip
12507 17:01:17.515545 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 skip
12508 17:01:17.515624 arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 pass
12509 17:01:17.515716 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 skip
12510 17:01:17.519823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 skip
12511 17:01:17.519964 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 skip
12512 17:01:17.520073 arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 pass
12513 17:01:17.520181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 skip
12514 17:01:17.520491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 skip
12515 17:01:17.520607 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 skip
12516 17:01:17.520694 arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 pass
12517 17:01:17.520795 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 skip
12518 17:01:17.521094 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 skip
12519 17:01:17.521200 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 skip
12520 17:01:17.521305 arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 pass
12521 17:01:17.521390 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 skip
12522 17:01:17.521489 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 skip
12523 17:01:17.521581 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 skip
12524 17:01:17.521721 arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 pass
12525 17:01:17.522029 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 skip
12526 17:01:17.522135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 skip
12527 17:01:17.522223 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 skip
12528 17:01:17.522345 arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 pass
12529 17:01:17.522450 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 skip
12530 17:01:17.522573 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 skip
12531 17:01:17.522675 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 skip
12532 17:01:17.522787 arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 pass
12533 17:01:17.522894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 skip
12534 17:01:17.523017 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 skip
12535 17:01:17.523133 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 skip
12536 17:01:17.523237 arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 pass
12537 17:01:17.523340 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 skip
12538 17:01:17.527600 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 skip
12539 17:01:17.527960 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 skip
12540 17:01:17.528070 arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 pass
12541 17:01:17.528160 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 skip
12542 17:01:17.528437 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 skip
12543 17:01:17.528540 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 skip
12544 17:01:17.528630 arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 pass
12545 17:01:17.528718 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 skip
12546 17:01:17.528823 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 skip
12547 17:01:17.528908 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 skip
12548 17:01:17.529000 arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 pass
12549 17:01:17.529091 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 skip
12550 17:01:17.529172 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 skip
12551 17:01:17.529266 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 skip
12552 17:01:17.529345 arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 pass
12553 17:01:17.529432 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 skip
12554 17:01:17.529523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 skip
12555 17:01:17.529823 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 skip
12556 17:01:17.529924 arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 pass
12557 17:01:17.530049 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 skip
12558 17:01:17.530168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 skip
12559 17:01:17.530284 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 skip
12560 17:01:17.530397 arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 pass
12561 17:01:17.530682 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 skip
12562 17:01:17.530775 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 skip
12563 17:01:17.530880 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 skip
12564 17:01:17.530988 arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 pass
12565 17:01:17.531114 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 skip
12566 17:01:17.531410 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 skip
12567 17:01:17.535543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 skip
12568 17:01:17.535859 arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 pass
12569 17:01:17.535955 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 skip
12570 17:01:17.536079 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 skip
12571 17:01:17.536204 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 skip
12572 17:01:17.536322 arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 pass
12573 17:01:17.536639 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 skip
12574 17:01:17.536758 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 skip
12575 17:01:17.536864 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 skip
12576 17:01:17.536976 arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 pass
12577 17:01:17.537100 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 skip
12578 17:01:17.537402 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 skip
12579 17:01:17.537526 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 skip
12580 17:01:17.537625 arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 pass
12581 17:01:17.537760 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 skip
12582 17:01:17.537881 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 skip
12583 17:01:17.537990 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 skip
12584 17:01:17.538292 arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 pass
12585 17:01:17.538398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 skip
12586 17:01:17.538502 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 skip
12587 17:01:17.538608 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 skip
12588 17:01:17.538714 arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 pass
12589 17:01:17.538815 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 skip
12590 17:01:17.539140 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 skip
12591 17:01:17.539260 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 skip
12592 17:01:17.539362 arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 pass
12593 17:01:17.548194 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 skip
12594 17:01:17.548424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 skip
12595 17:01:17.548521 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 skip
12596 17:01:17.548610 arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 pass
12597 17:01:17.548700 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 skip
12598 17:01:17.548997 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 skip
12599 17:01:17.549104 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 skip
12600 17:01:17.562133 arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 pass
12601 17:01:17.562592 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 skip
12602 17:01:17.562706 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 skip
12603 17:01:17.562798 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 skip
12604 17:01:17.563095 arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 pass
12605 17:01:17.563207 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 skip
12606 17:01:17.563302 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 skip
12607 17:01:17.563408 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 skip
12608 17:01:17.563495 arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 pass
12609 17:01:17.563780 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 skip
12610 17:01:17.563894 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 skip
12611 17:01:17.564189 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 skip
12612 17:01:17.564300 arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 pass
12613 17:01:17.564398 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 skip
12614 17:01:17.564680 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 skip
12615 17:01:17.564780 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 skip
12616 17:01:17.565058 arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 pass
12617 17:01:17.565158 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 skip
12618 17:01:17.565254 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 skip
12619 17:01:17.565532 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 skip
12620 17:01:17.565631 arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 pass
12621 17:01:17.565737 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 skip
12622 17:01:17.565994 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 skip
12623 17:01:17.566107 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 skip
12624 17:01:17.566204 arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 pass
12625 17:01:17.566300 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 skip
12626 17:01:17.566581 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 skip
12627 17:01:17.566680 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 skip
12628 17:01:17.566957 arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 pass
12629 17:01:17.567048 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 skip
12630 17:01:17.567324 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 skip
12631 17:01:17.567411 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 skip
12632 17:01:17.567504 arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 pass
12633 17:01:17.571571 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 skip
12634 17:01:17.571917 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 skip
12635 17:01:17.572022 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 skip
12636 17:01:17.572136 arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 pass
12637 17:01:17.572262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 skip
12638 17:01:17.574464 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 skip
12639 17:01:17.574621 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 skip
12640 17:01:17.574689 arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 pass
12641 17:01:17.574750 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 skip
12642 17:01:17.574810 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 skip
12643 17:01:17.574870 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 skip
12644 17:01:17.574929 arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 pass
12645 17:01:17.574989 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 skip
12646 17:01:17.575082 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 skip
12647 17:01:17.575164 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 skip
12648 17:01:17.575242 arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 pass
12649 17:01:17.575321 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 skip
12650 17:01:17.575424 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 skip
12651 17:01:17.575511 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 skip
12652 17:01:17.575591 arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 pass
12653 17:01:17.575671 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 skip
12654 17:01:17.575734 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 skip
12655 17:01:17.579728 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 skip
12656 17:01:17.580250 arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 pass
12657 17:01:17.580356 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 skip
12658 17:01:17.580420 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 skip
12659 17:01:17.580482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 skip
12660 17:01:17.580735 arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 pass
12661 17:01:17.580819 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 skip
12662 17:01:17.580923 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 skip
12663 17:01:17.581027 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 skip
12664 17:01:17.581141 arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 pass
12665 17:01:17.581910 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 skip
12666 17:01:17.582040 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 skip
12667 17:01:17.582125 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 skip
12668 17:01:17.582204 arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 pass
12669 17:01:17.582277 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 skip
12670 17:01:17.582358 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 skip
12671 17:01:17.582433 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 skip
12672 17:01:17.582698 arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 pass
12673 17:01:17.582776 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 skip
12674 17:01:17.582852 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 skip
12675 17:01:17.582926 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 skip
12676 17:01:17.582997 arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 pass
12677 17:01:17.583075 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 skip
12678 17:01:17.583168 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 skip
12679 17:01:17.583248 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 skip
12680 17:01:17.583337 arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 pass
12681 17:01:17.583427 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 skip
12682 17:01:17.587930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 skip
12683 17:01:17.588215 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 skip
12684 17:01:17.588316 arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 pass
12685 17:01:17.588394 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 skip
12686 17:01:17.588491 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 skip
12687 17:01:17.588584 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 skip
12688 17:01:17.588874 arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 pass
12689 17:01:17.588976 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 skip
12690 17:01:17.589090 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 skip
12691 17:01:17.589394 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 skip
12692 17:01:17.589522 arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 pass
12693 17:01:17.589619 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 skip
12694 17:01:17.589926 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 skip
12695 17:01:17.590020 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 skip
12696 17:01:17.590118 arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 pass
12697 17:01:17.590236 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 skip
12698 17:01:17.590530 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 skip
12699 17:01:17.590640 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 skip
12700 17:01:17.590747 arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 pass
12701 17:01:17.591051 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 skip
12702 17:01:17.591188 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 skip
12703 17:01:17.591482 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 skip
12704 17:01:17.595660 arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 pass
12705 17:01:17.596154 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 skip
12706 17:01:17.596246 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 skip
12707 17:01:17.596327 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 skip
12708 17:01:17.596423 arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 pass
12709 17:01:17.596506 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 skip
12710 17:01:17.596601 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 skip
12711 17:01:17.596695 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 skip
12712 17:01:17.596797 arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 pass
12713 17:01:17.597081 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 skip
12714 17:01:17.597181 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 skip
12715 17:01:17.597486 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 skip
12716 17:01:17.597581 arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 pass
12717 17:01:17.597674 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 skip
12718 17:01:17.597945 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 skip
12719 17:01:17.598036 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 skip
12720 17:01:17.598310 arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 pass
12721 17:01:17.598393 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 skip
12722 17:01:17.598482 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 skip
12723 17:01:17.598760 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 skip
12724 17:01:17.598850 arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 pass
12725 17:01:17.598942 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 skip
12726 17:01:17.599223 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 skip
12727 17:01:17.599322 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 skip
12728 17:01:17.603684 arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 pass
12729 17:01:17.604192 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 skip
12730 17:01:17.604289 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 skip
12731 17:01:17.604375 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 skip
12732 17:01:17.604469 arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 pass
12733 17:01:17.604551 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 skip
12734 17:01:17.615888 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 skip
12735 17:01:17.616405 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 skip
12736 17:01:17.616504 arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 pass
12737 17:01:17.616586 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 skip
12738 17:01:17.616670 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 skip
12739 17:01:17.616765 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 skip
12740 17:01:17.616842 arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 pass
12741 17:01:17.616930 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 skip
12742 17:01:17.617214 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 skip
12743 17:01:17.617308 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 skip
12744 17:01:17.617386 arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 pass
12745 17:01:17.617475 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 skip
12746 17:01:17.617564 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 skip
12747 17:01:17.617898 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 skip
12748 17:01:17.617995 arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 pass
12749 17:01:17.618086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 skip
12750 17:01:17.618392 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 skip
12751 17:01:17.618487 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 skip
12752 17:01:17.618565 arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 pass
12753 17:01:17.618655 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 skip
12754 17:01:17.618744 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 skip
12755 17:01:17.618833 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 skip
12756 17:01:17.618923 arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 pass
12757 17:01:17.619011 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 skip
12758 17:01:17.619269 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 skip
12759 17:01:17.619367 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 skip
12760 17:01:17.623820 arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 pass
12761 17:01:17.624138 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 skip
12762 17:01:17.624490 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 skip
12763 17:01:17.624587 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 skip
12764 17:01:17.624652 arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 pass
12765 17:01:17.624711 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 skip
12766 17:01:17.624771 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 skip
12767 17:01:17.624854 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 skip
12768 17:01:17.624957 arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 pass
12769 17:01:17.625042 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 skip
12770 17:01:17.625135 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 skip
12771 17:01:17.625242 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 skip
12772 17:01:17.625345 arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 pass
12773 17:01:17.625679 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 skip
12774 17:01:17.625783 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 skip
12775 17:01:17.625885 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 skip
12776 17:01:17.625986 arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 pass
12777 17:01:17.626086 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 skip
12778 17:01:17.626423 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 skip
12779 17:01:17.626537 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 skip
12780 17:01:17.626886 arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 pass
12781 17:01:17.626985 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 skip
12782 17:01:17.627279 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 skip
12783 17:01:17.627379 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 skip
12784 17:01:17.627463 arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 pass
12785 17:01:17.627557 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 skip
12786 17:01:17.631754 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 skip
12787 17:01:17.632250 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 skip
12788 17:01:17.632353 arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 pass
12789 17:01:17.632439 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 skip
12790 17:01:17.632523 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 skip
12791 17:01:17.632620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 skip
12792 17:01:17.632704 arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 pass
12793 17:01:17.632799 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 skip
12794 17:01:17.632898 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 skip
12795 17:01:17.633206 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 skip
12796 17:01:17.633297 arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 pass
12797 17:01:17.633385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 skip
12798 17:01:17.633669 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 skip
12799 17:01:17.633766 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 skip
12800 17:01:17.633873 arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 pass
12801 17:01:17.634152 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 skip
12802 17:01:17.634260 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 skip
12803 17:01:17.634543 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 skip
12804 17:01:17.634642 arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 pass
12805 17:01:17.634921 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 skip
12806 17:01:17.635865 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 skip
12807 17:01:17.635971 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 skip
12808 17:01:17.636051 arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 pass
12809 17:01:17.639618 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 skip
12810 17:01:17.639980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 skip
12811 17:01:17.640088 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 skip
12812 17:01:17.640190 arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 pass
12813 17:01:17.640290 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 skip
12814 17:01:17.640386 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 skip
12815 17:01:17.640703 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 skip
12816 17:01:17.640804 arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 pass
12817 17:01:17.640900 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 skip
12818 17:01:17.641258 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 skip
12819 17:01:17.641364 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 skip
12820 17:01:17.641460 arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 pass
12821 17:01:17.641545 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 skip
12822 17:01:17.641637 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 skip
12823 17:01:17.641947 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 skip
12824 17:01:17.642056 arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 pass
12825 17:01:17.642413 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 skip
12826 17:01:17.642518 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 skip
12827 17:01:17.642620 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 skip
12828 17:01:17.642702 arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 pass
12829 17:01:17.642794 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 skip
12830 17:01:17.642887 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 skip
12831 17:01:17.642982 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 skip
12832 17:01:17.643241 arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 pass
12833 17:01:17.643361 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 skip
12834 17:01:17.647703 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 skip
12835 17:01:17.648127 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 skip
12836 17:01:17.648215 arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 pass
12837 17:01:17.648285 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 skip
12838 17:01:17.648613 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 skip
12839 17:01:17.648700 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 skip
12840 17:01:17.648769 arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 pass
12841 17:01:17.648848 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 skip
12842 17:01:17.648916 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 skip
12843 17:01:17.649012 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 skip
12844 17:01:17.649358 arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 pass
12845 17:01:17.649451 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 skip
12846 17:01:17.653206 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 skip
12847 17:01:17.653429 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 skip
12848 17:01:17.653514 arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 pass
12849 17:01:17.653595 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 skip
12850 17:01:17.653687 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 skip
12851 17:01:17.653767 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 skip
12852 17:01:17.653846 arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 pass
12853 17:01:17.653933 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 skip
12854 17:01:17.654012 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 skip
12855 17:01:17.654091 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 skip
12856 17:01:17.654169 arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 pass
12857 17:01:17.654251 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 skip
12858 17:01:17.654330 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 skip
12859 17:01:17.654407 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 skip
12860 17:01:17.654485 arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 pass
12861 17:01:17.655611 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 skip
12862 17:01:17.655891 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 skip
12863 17:01:17.656035 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 skip
12864 17:01:17.656161 arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 pass
12865 17:01:17.656247 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 skip
12866 17:01:17.656347 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 skip
12867 17:01:17.656442 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 skip
12868 17:01:17.674245 arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 pass
12869 17:01:17.674492 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 skip
12870 17:01:17.674578 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 skip
12871 17:01:17.674884 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 skip
12872 17:01:17.674996 arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 pass
12873 17:01:17.675080 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 skip
12874 17:01:17.675262 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 skip
12875 17:01:17.675372 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 skip
12876 17:01:17.675455 arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 pass
12877 17:01:17.675533 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 skip
12878 17:01:17.675610 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 skip
12879 17:01:17.675708 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 skip
12880 17:01:17.675815 arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 pass
12881 17:01:17.676095 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 skip
12882 17:01:17.676193 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 skip
12883 17:01:17.676289 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 skip
12884 17:01:17.676570 arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 pass
12885 17:01:17.676663 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 skip
12886 17:01:17.676766 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 skip
12887 17:01:17.677069 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 skip
12888 17:01:17.677167 arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 pass
12889 17:01:17.677442 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 skip
12890 17:01:17.677539 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 skip
12891 17:01:17.677636 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 skip
12892 17:01:17.677754 arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 pass
12893 17:01:17.678047 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 skip
12894 17:01:17.678385 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 skip
12895 17:01:17.678485 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 skip
12896 17:01:17.678565 arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 pass
12897 17:01:17.678931 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 skip
12898 17:01:17.679031 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 skip
12899 17:01:17.679111 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 skip
12900 17:01:17.679190 arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 pass
12901 17:01:17.679267 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 skip
12902 17:01:17.679359 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 skip
12903 17:01:17.679439 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 skip
12904 17:01:17.679517 arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 pass
12905 17:01:17.683732 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 skip
12906 17:01:17.684126 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 skip
12907 17:01:17.684232 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 skip
12908 17:01:17.684319 arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 pass
12909 17:01:17.684416 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 skip
12910 17:01:17.684498 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 skip
12911 17:01:17.684592 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 skip
12912 17:01:17.684876 arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 pass
12913 17:01:17.684980 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 skip
12914 17:01:17.685149 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 skip
12915 17:01:17.685249 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 skip
12916 17:01:17.685343 arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 pass
12917 17:01:17.685694 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 skip
12918 17:01:17.685801 arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 skip
12919 17:01:17.685905 arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 skip
12920 17:01:17.685995 arm64_sve-ptrace pass
12921 17:01:17.686090 arm64_sve-probe-vls_Enumerated_16_vector_lengths pass
12922 17:01:17.686189 arm64_sve-probe-vls_All_vector_lengths_valid pass
12923 17:01:17.686291 arm64_sve-probe-vls pass
12924 17:01:17.686427 arm64_vec-syscfg_SVE_default_vector_length_64 pass
12925 17:01:17.686735 arm64_vec-syscfg_SVE_minimum_vector_length_16 pass
12926 17:01:17.686831 arm64_vec-syscfg_SVE_maximum_vector_length_256 pass
12927 17:01:17.686934 arm64_vec-syscfg_SVE_current_VL_is_64 pass
12928 17:01:17.687022 arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 pass
12929 17:01:17.687122 arm64_vec-syscfg_SVE_prctl_set_min_max pass
12930 17:01:17.687211 arm64_vec-syscfg_SVE_vector_length_used_default pass
12931 17:01:17.687309 arm64_vec-syscfg_SVE_vector_length_was_inherited pass
12932 17:01:17.691605 arm64_vec-syscfg_SVE_vector_length_set_on_exec pass
12933 17:01:17.691903 arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors pass
12934 17:01:17.691992 arm64_vec-syscfg_SME_default_vector_length_32 pass
12935 17:01:17.692086 arm64_vec-syscfg_SME_minimum_vector_length_16 pass
12936 17:01:17.692182 arm64_vec-syscfg_SME_maximum_vector_length_256 pass
12937 17:01:17.692277 arm64_vec-syscfg_SME_current_VL_is_32 pass
12938 17:01:17.692372 arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 pass
12939 17:01:17.692650 arm64_vec-syscfg_SME_prctl_set_min_max pass
12940 17:01:17.692738 arm64_vec-syscfg_SME_vector_length_used_default pass
12941 17:01:17.692846 arm64_vec-syscfg_SME_vector_length_was_inherited pass
12942 17:01:17.693130 arm64_vec-syscfg_SME_vector_length_set_on_exec pass
12943 17:01:17.693234 arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors pass
12944 17:01:17.693338 arm64_vec-syscfg pass
12945 17:01:17.693422 arm64_za-fork_fork_test pass
12946 17:01:17.693506 arm64_za-fork pass
12947 17:01:17.693591 arm64_za-ptrace_Set_VL_16 pass
12948 17:01:17.693700 arm64_za-ptrace_Disabled_ZA_for_VL_16 pass
12949 17:01:17.693782 arm64_za-ptrace_Data_match_for_VL_16 pass
12950 17:01:17.693860 arm64_za-ptrace_Set_VL_32 pass
12951 17:01:17.694129 arm64_za-ptrace_Disabled_ZA_for_VL_32 pass
12952 17:01:17.694213 arm64_za-ptrace_Data_match_for_VL_32 pass
12953 17:01:17.694292 arm64_za-ptrace_Set_VL_48 pass
12954 17:01:17.694370 arm64_za-ptrace_Disabled_ZA_for_VL_48 skip
12955 17:01:17.694462 arm64_za-ptrace_Get_and_set_data_for_VL_48 skip
12956 17:01:17.694543 arm64_za-ptrace_Set_VL_64 pass
12957 17:01:17.694622 arm64_za-ptrace_Disabled_ZA_for_VL_64 pass
12958 17:01:17.694713 arm64_za-ptrace_Data_match_for_VL_64 pass
12959 17:01:17.694794 arm64_za-ptrace_Set_VL_80 pass
12960 17:01:17.694885 arm64_za-ptrace_Disabled_ZA_for_VL_80 skip
12961 17:01:17.694981 arm64_za-ptrace_Get_and_set_data_for_VL_80 skip
12962 17:01:17.695069 arm64_za-ptrace_Set_VL_96 pass
12963 17:01:17.695169 arm64_za-ptrace_Disabled_ZA_for_VL_96 skip
12964 17:01:17.695257 arm64_za-ptrace_Get_and_set_data_for_VL_96 skip
12965 17:01:17.695358 arm64_za-ptrace_Set_VL_112 pass
12966 17:01:17.699633 arm64_za-ptrace_Disabled_ZA_for_VL_112 skip
12967 17:01:17.699938 arm64_za-ptrace_Get_and_set_data_for_VL_112 skip
12968 17:01:17.700036 arm64_za-ptrace_Set_VL_128 pass
12969 17:01:17.700118 arm64_za-ptrace_Disabled_ZA_for_VL_128 pass
12970 17:01:17.700212 arm64_za-ptrace_Data_match_for_VL_128 pass
12971 17:01:17.700295 arm64_za-ptrace_Set_VL_144 pass
12972 17:01:17.700388 arm64_za-ptrace_Disabled_ZA_for_VL_144 skip
12973 17:01:17.700471 arm64_za-ptrace_Get_and_set_data_for_VL_144 skip
12974 17:01:17.700551 arm64_za-ptrace_Set_VL_160 pass
12975 17:01:17.700644 arm64_za-ptrace_Disabled_ZA_for_VL_160 skip
12976 17:01:17.700727 arm64_za-ptrace_Get_and_set_data_for_VL_160 skip
12977 17:01:17.700820 arm64_za-ptrace_Set_VL_176 pass
12978 17:01:17.700914 arm64_za-ptrace_Disabled_ZA_for_VL_176 skip
12979 17:01:17.701195 arm64_za-ptrace_Get_and_set_data_for_VL_176 skip
12980 17:01:17.701283 arm64_za-ptrace_Set_VL_192 pass
12981 17:01:17.701383 arm64_za-ptrace_Disabled_ZA_for_VL_192 skip
12982 17:01:17.701479 arm64_za-ptrace_Get_and_set_data_for_VL_192 skip
12983 17:01:17.701572 arm64_za-ptrace_Set_VL_208 pass
12984 17:01:17.701856 arm64_za-ptrace_Disabled_ZA_for_VL_208 skip
12985 17:01:17.702273 arm64_za-ptrace_Get_and_set_data_for_VL_208 skip
12986 17:01:17.702370 arm64_za-ptrace_Set_VL_224 pass
12987 17:01:17.702457 arm64_za-ptrace_Disabled_ZA_for_VL_224 skip
12988 17:01:17.702543 arm64_za-ptrace_Get_and_set_data_for_VL_224 skip
12989 17:01:17.702628 arm64_za-ptrace_Set_VL_240 pass
12990 17:01:17.702901 arm64_za-ptrace_Disabled_ZA_for_VL_240 skip
12991 17:01:17.702986 arm64_za-ptrace_Get_and_set_data_for_VL_240 skip
12992 17:01:17.703066 arm64_za-ptrace_Set_VL_256 pass
12993 17:01:17.703145 arm64_za-ptrace_Disabled_ZA_for_VL_256 pass
12994 17:01:17.703222 arm64_za-ptrace_Data_match_for_VL_256 pass
12995 17:01:17.703314 arm64_za-ptrace_Set_VL_272 pass
12996 17:01:17.703394 arm64_za-ptrace_Disabled_ZA_for_VL_272 skip
12997 17:01:17.703472 arm64_za-ptrace_Get_and_set_data_for_VL_272 skip
12998 17:01:17.703564 arm64_za-ptrace_Set_VL_288 pass
12999 17:01:17.707613 arm64_za-ptrace_Disabled_ZA_for_VL_288 skip
13000 17:01:17.707915 arm64_za-ptrace_Get_and_set_data_for_VL_288 skip
13001 17:01:17.708001 arm64_za-ptrace_Set_VL_304 pass
13002 17:01:17.708094 arm64_za-ptrace_Disabled_ZA_for_VL_304 skip
13003 17:01:17.708186 arm64_za-ptrace_Get_and_set_data_for_VL_304 skip
13004 17:01:17.708268 arm64_za-ptrace_Set_VL_320 pass
13005 17:01:17.708358 arm64_za-ptrace_Disabled_ZA_for_VL_320 skip
13006 17:01:17.708438 arm64_za-ptrace_Get_and_set_data_for_VL_320 skip
13007 17:01:17.708531 arm64_za-ptrace_Set_VL_336 pass
13008 17:01:17.708624 arm64_za-ptrace_Disabled_ZA_for_VL_336 skip
13009 17:01:17.708901 arm64_za-ptrace_Get_and_set_data_for_VL_336 skip
13010 17:01:17.708987 arm64_za-ptrace_Set_VL_352 pass
13011 17:01:17.709082 arm64_za-ptrace_Disabled_ZA_for_VL_352 skip
13012 17:01:17.709173 arm64_za-ptrace_Get_and_set_data_for_VL_352 skip
13013 17:01:17.709261 arm64_za-ptrace_Set_VL_368 pass
13014 17:01:17.709349 arm64_za-ptrace_Disabled_ZA_for_VL_368 skip
13015 17:01:17.709441 arm64_za-ptrace_Get_and_set_data_for_VL_368 skip
13016 17:01:17.709682 arm64_za-ptrace_Set_VL_384 pass
13017 17:01:17.709769 arm64_za-ptrace_Disabled_ZA_for_VL_384 skip
13018 17:01:17.709860 arm64_za-ptrace_Get_and_set_data_for_VL_384 skip
13019 17:01:17.709956 arm64_za-ptrace_Set_VL_400 pass
13020 17:01:17.710057 arm64_za-ptrace_Disabled_ZA_for_VL_400 skip
13021 17:01:17.710163 arm64_za-ptrace_Get_and_set_data_for_VL_400 skip
13022 17:01:17.710261 arm64_za-ptrace_Set_VL_416 pass
13023 17:01:17.710358 arm64_za-ptrace_Disabled_ZA_for_VL_416 skip
13024 17:01:17.710644 arm64_za-ptrace_Get_and_set_data_for_VL_416 skip
13025 17:01:17.710736 arm64_za-ptrace_Set_VL_432 pass
13026 17:01:17.710835 arm64_za-ptrace_Disabled_ZA_for_VL_432 skip
13027 17:01:17.710921 arm64_za-ptrace_Get_and_set_data_for_VL_432 skip
13028 17:01:17.711021 arm64_za-ptrace_Set_VL_448 pass
13029 17:01:17.711107 arm64_za-ptrace_Disabled_ZA_for_VL_448 skip
13030 17:01:17.711204 arm64_za-ptrace_Get_and_set_data_for_VL_448 skip
13031 17:01:17.711302 arm64_za-ptrace_Set_VL_464 pass
13032 17:01:17.711397 arm64_za-ptrace_Disabled_ZA_for_VL_464 skip
13033 17:01:17.715797 arm64_za-ptrace_Get_and_set_data_for_VL_464 skip
13034 17:01:17.715953 arm64_za-ptrace_Set_VL_480 pass
13035 17:01:17.716050 arm64_za-ptrace_Disabled_ZA_for_VL_480 skip
13036 17:01:17.716133 arm64_za-ptrace_Get_and_set_data_for_VL_480 skip
13037 17:01:17.716227 arm64_za-ptrace_Set_VL_496 pass
13038 17:01:17.716311 arm64_za-ptrace_Disabled_ZA_for_VL_496 skip
13039 17:01:17.731330 arm64_za-ptrace_Get_and_set_data_for_VL_496 skip
13040 17:01:17.731567 arm64_za-ptrace_Set_VL_512 pass
13041 17:01:17.731851 arm64_za-ptrace_Disabled_ZA_for_VL_512 skip
13042 17:01:17.731939 arm64_za-ptrace_Get_and_set_data_for_VL_512 skip
13043 17:01:17.732033 arm64_za-ptrace_Set_VL_528 pass
13044 17:01:17.732312 arm64_za-ptrace_Disabled_ZA_for_VL_528 skip
13045 17:01:17.732591 arm64_za-ptrace_Get_and_set_data_for_VL_528 skip
13046 17:01:17.732689 arm64_za-ptrace_Set_VL_544 pass
13047 17:01:17.732833 arm64_za-ptrace_Disabled_ZA_for_VL_544 skip
13048 17:01:17.733152 arm64_za-ptrace_Get_and_set_data_for_VL_544 skip
13049 17:01:17.733251 arm64_za-ptrace_Set_VL_560 pass
13050 17:01:17.733344 arm64_za-ptrace_Disabled_ZA_for_VL_560 skip
13051 17:01:17.733598 arm64_za-ptrace_Get_and_set_data_for_VL_560 skip
13052 17:01:17.733718 arm64_za-ptrace_Set_VL_576 pass
13053 17:01:17.733835 arm64_za-ptrace_Disabled_ZA_for_VL_576 skip
13054 17:01:17.733936 arm64_za-ptrace_Get_and_set_data_for_VL_576 skip
13055 17:01:17.734027 arm64_za-ptrace_Set_VL_592 pass
13056 17:01:17.734115 arm64_za-ptrace_Disabled_ZA_for_VL_592 skip
13057 17:01:17.734382 arm64_za-ptrace_Get_and_set_data_for_VL_592 skip
13058 17:01:17.734458 arm64_za-ptrace_Set_VL_608 pass
13059 17:01:17.734548 arm64_za-ptrace_Disabled_ZA_for_VL_608 skip
13060 17:01:17.734634 arm64_za-ptrace_Get_and_set_data_for_VL_608 skip
13061 17:01:17.734899 arm64_za-ptrace_Set_VL_624 pass
13062 17:01:17.734983 arm64_za-ptrace_Disabled_ZA_for_VL_624 skip
13063 17:01:17.735079 arm64_za-ptrace_Get_and_set_data_for_VL_624 skip
13064 17:01:17.735182 arm64_za-ptrace_Set_VL_640 pass
13065 17:01:17.735456 arm64_za-ptrace_Disabled_ZA_for_VL_640 skip
13066 17:01:17.739741 arm64_za-ptrace_Get_and_set_data_for_VL_640 skip
13067 17:01:17.739901 arm64_za-ptrace_Set_VL_656 pass
13068 17:01:17.740019 arm64_za-ptrace_Disabled_ZA_for_VL_656 skip
13069 17:01:17.740093 arm64_za-ptrace_Get_and_set_data_for_VL_656 skip
13070 17:01:17.740184 arm64_za-ptrace_Set_VL_672 pass
13071 17:01:17.740271 arm64_za-ptrace_Disabled_ZA_for_VL_672 skip
13072 17:01:17.740358 arm64_za-ptrace_Get_and_set_data_for_VL_672 skip
13073 17:01:17.740449 arm64_za-ptrace_Set_VL_688 pass
13074 17:01:17.740537 arm64_za-ptrace_Disabled_ZA_for_VL_688 skip
13075 17:01:17.740623 arm64_za-ptrace_Get_and_set_data_for_VL_688 skip
13076 17:01:17.740891 arm64_za-ptrace_Set_VL_704 pass
13077 17:01:17.740972 arm64_za-ptrace_Disabled_ZA_for_VL_704 skip
13078 17:01:17.741101 arm64_za-ptrace_Get_and_set_data_for_VL_704 skip
13079 17:01:17.741173 arm64_za-ptrace_Set_VL_720 pass
13080 17:01:17.741247 arm64_za-ptrace_Disabled_ZA_for_VL_720 skip
13081 17:01:17.741320 arm64_za-ptrace_Get_and_set_data_for_VL_720 skip
13082 17:01:17.741593 arm64_za-ptrace_Set_VL_736 pass
13083 17:01:17.741727 arm64_za-ptrace_Disabled_ZA_for_VL_736 skip
13084 17:01:17.741839 arm64_za-ptrace_Get_and_set_data_for_VL_736 skip
13085 17:01:17.741927 arm64_za-ptrace_Set_VL_752 pass
13086 17:01:17.742022 arm64_za-ptrace_Disabled_ZA_for_VL_752 skip
13087 17:01:17.742124 arm64_za-ptrace_Get_and_set_data_for_VL_752 skip
13088 17:01:17.742226 arm64_za-ptrace_Set_VL_768 pass
13089 17:01:17.742329 arm64_za-ptrace_Disabled_ZA_for_VL_768 skip
13090 17:01:17.742440 arm64_za-ptrace_Get_and_set_data_for_VL_768 skip
13091 17:01:17.742541 arm64_za-ptrace_Set_VL_784 pass
13092 17:01:17.742642 arm64_za-ptrace_Disabled_ZA_for_VL_784 skip
13093 17:01:17.742744 arm64_za-ptrace_Get_and_set_data_for_VL_784 skip
13094 17:01:17.742852 arm64_za-ptrace_Set_VL_800 pass
13095 17:01:17.742960 arm64_za-ptrace_Disabled_ZA_for_VL_800 skip
13096 17:01:17.743072 arm64_za-ptrace_Get_and_set_data_for_VL_800 skip
13097 17:01:17.743177 arm64_za-ptrace_Set_VL_816 pass
13098 17:01:17.743280 arm64_za-ptrace_Disabled_ZA_for_VL_816 skip
13099 17:01:17.747650 arm64_za-ptrace_Get_and_set_data_for_VL_816 skip
13100 17:01:17.748057 arm64_za-ptrace_Set_VL_832 pass
13101 17:01:17.748168 arm64_za-ptrace_Disabled_ZA_for_VL_832 skip
13102 17:01:17.748254 arm64_za-ptrace_Get_and_set_data_for_VL_832 skip
13103 17:01:17.748334 arm64_za-ptrace_Set_VL_848 pass
13104 17:01:17.748430 arm64_za-ptrace_Disabled_ZA_for_VL_848 skip
13105 17:01:17.748516 arm64_za-ptrace_Get_and_set_data_for_VL_848 skip
13106 17:01:17.748600 arm64_za-ptrace_Set_VL_864 pass
13107 17:01:17.748697 arm64_za-ptrace_Disabled_ZA_for_VL_864 skip
13108 17:01:17.748785 arm64_za-ptrace_Get_and_set_data_for_VL_864 skip
13109 17:01:17.748886 arm64_za-ptrace_Set_VL_880 pass
13110 17:01:17.748968 arm64_za-ptrace_Disabled_ZA_for_VL_880 skip
13111 17:01:17.749059 arm64_za-ptrace_Get_and_set_data_for_VL_880 skip
13112 17:01:17.749153 arm64_za-ptrace_Set_VL_896 pass
13113 17:01:17.749509 arm64_za-ptrace_Disabled_ZA_for_VL_896 skip
13114 17:01:17.749611 arm64_za-ptrace_Get_and_set_data_for_VL_896 skip
13115 17:01:17.749709 arm64_za-ptrace_Set_VL_912 pass
13116 17:01:17.749807 arm64_za-ptrace_Disabled_ZA_for_VL_912 skip
13117 17:01:17.749893 arm64_za-ptrace_Get_and_set_data_for_VL_912 skip
13118 17:01:17.749991 arm64_za-ptrace_Set_VL_928 pass
13119 17:01:17.750075 arm64_za-ptrace_Disabled_ZA_for_VL_928 skip
13120 17:01:17.750158 arm64_za-ptrace_Get_and_set_data_for_VL_928 skip
13121 17:01:17.750254 arm64_za-ptrace_Set_VL_944 pass
13122 17:01:17.750333 arm64_za-ptrace_Disabled_ZA_for_VL_944 skip
13123 17:01:17.750424 arm64_za-ptrace_Get_and_set_data_for_VL_944 skip
13124 17:01:17.750502 arm64_za-ptrace_Set_VL_960 pass
13125 17:01:17.750594 arm64_za-ptrace_Disabled_ZA_for_VL_960 skip
13126 17:01:17.750688 arm64_za-ptrace_Get_and_set_data_for_VL_960 skip
13127 17:01:17.750785 arm64_za-ptrace_Set_VL_976 pass
13128 17:01:17.750883 arm64_za-ptrace_Disabled_ZA_for_VL_976 skip
13129 17:01:17.750978 arm64_za-ptrace_Get_and_set_data_for_VL_976 skip
13130 17:01:17.751075 arm64_za-ptrace_Set_VL_992 pass
13131 17:01:17.751519 arm64_za-ptrace_Disabled_ZA_for_VL_992 skip
13132 17:01:17.751624 arm64_za-ptrace_Get_and_set_data_for_VL_992 skip
13133 17:01:17.755589 arm64_za-ptrace_Set_VL_1008 pass
13134 17:01:17.755950 arm64_za-ptrace_Disabled_ZA_for_VL_1008 skip
13135 17:01:17.756039 arm64_za-ptrace_Get_and_set_data_for_VL_1008 skip
13136 17:01:17.756119 arm64_za-ptrace_Set_VL_1024 pass
13137 17:01:17.756197 arm64_za-ptrace_Disabled_ZA_for_VL_1024 skip
13138 17:01:17.756292 arm64_za-ptrace_Get_and_set_data_for_VL_1024 skip
13139 17:01:17.756373 arm64_za-ptrace_Set_VL_1040 pass
13140 17:01:17.756473 arm64_za-ptrace_Disabled_ZA_for_VL_1040 skip
13141 17:01:17.756569 arm64_za-ptrace_Get_and_set_data_for_VL_1040 skip
13142 17:01:17.756650 arm64_za-ptrace_Set_VL_1056 pass
13143 17:01:17.756742 arm64_za-ptrace_Disabled_ZA_for_VL_1056 skip
13144 17:01:17.757022 arm64_za-ptrace_Get_and_set_data_for_VL_1056 skip
13145 17:01:17.757125 arm64_za-ptrace_Set_VL_1072 pass
13146 17:01:17.757223 arm64_za-ptrace_Disabled_ZA_for_VL_1072 skip
13147 17:01:17.757322 arm64_za-ptrace_Get_and_set_data_for_VL_1072 skip
13148 17:01:17.757417 arm64_za-ptrace_Set_VL_1088 pass
13149 17:01:17.757514 arm64_za-ptrace_Disabled_ZA_for_VL_1088 skip
13150 17:01:17.757798 arm64_za-ptrace_Get_and_set_data_for_VL_1088 skip
13151 17:01:17.757893 arm64_za-ptrace_Set_VL_1104 pass
13152 17:01:17.757994 arm64_za-ptrace_Disabled_ZA_for_VL_1104 skip
13153 17:01:17.758082 arm64_za-ptrace_Get_and_set_data_for_VL_1104 skip
13154 17:01:17.758182 arm64_za-ptrace_Set_VL_1120 pass
13155 17:01:17.758282 arm64_za-ptrace_Disabled_ZA_for_VL_1120 skip
13156 17:01:17.758564 arm64_za-ptrace_Get_and_set_data_for_VL_1120 skip
13157 17:01:17.758656 arm64_za-ptrace_Set_VL_1136 pass
13158 17:01:17.758737 arm64_za-ptrace_Disabled_ZA_for_VL_1136 skip
13159 17:01:17.758831 arm64_za-ptrace_Get_and_set_data_for_VL_1136 skip
13160 17:01:17.758927 arm64_za-ptrace_Set_VL_1152 pass
13161 17:01:17.759009 arm64_za-ptrace_Disabled_ZA_for_VL_1152 skip
13162 17:01:17.759103 arm64_za-ptrace_Get_and_set_data_for_VL_1152 skip
13163 17:01:17.759374 arm64_za-ptrace_Set_VL_1168 pass
13164 17:01:17.759461 arm64_za-ptrace_Disabled_ZA_for_VL_1168 skip
13165 17:01:17.759542 arm64_za-ptrace_Get_and_set_data_for_VL_1168 skip
13166 17:01:17.759622 arm64_za-ptrace_Set_VL_1184 pass
13167 17:01:17.763589 arm64_za-ptrace_Disabled_ZA_for_VL_1184 skip
13168 17:01:17.763961 arm64_za-ptrace_Get_and_set_data_for_VL_1184 skip
13169 17:01:17.764070 arm64_za-ptrace_Set_VL_1200 pass
13170 17:01:17.764157 arm64_za-ptrace_Disabled_ZA_for_VL_1200 skip
13171 17:01:17.764257 arm64_za-ptrace_Get_and_set_data_for_VL_1200 skip
13172 17:01:17.764342 arm64_za-ptrace_Set_VL_1216 pass
13173 17:01:17.764427 arm64_za-ptrace_Disabled_ZA_for_VL_1216 skip
13174 17:01:17.764534 arm64_za-ptrace_Get_and_set_data_for_VL_1216 skip
13175 17:01:17.764619 arm64_za-ptrace_Set_VL_1232 pass
13176 17:01:17.764696 arm64_za-ptrace_Disabled_ZA_for_VL_1232 skip
13177 17:01:17.764786 arm64_za-ptrace_Get_and_set_data_for_VL_1232 skip
13178 17:01:17.764866 arm64_za-ptrace_Set_VL_1248 pass
13179 17:01:17.764942 arm64_za-ptrace_Disabled_ZA_for_VL_1248 skip
13180 17:01:17.765033 arm64_za-ptrace_Get_and_set_data_for_VL_1248 skip
13181 17:01:17.765128 arm64_za-ptrace_Set_VL_1264 pass
13182 17:01:17.765208 arm64_za-ptrace_Disabled_ZA_for_VL_1264 skip
13183 17:01:17.765299 arm64_za-ptrace_Get_and_set_data_for_VL_1264 skip
13184 17:01:17.765391 arm64_za-ptrace_Set_VL_1280 pass
13185 17:01:17.765494 arm64_za-ptrace_Disabled_ZA_for_VL_1280 skip
13186 17:01:17.765590 arm64_za-ptrace_Get_and_set_data_for_VL_1280 skip
13187 17:01:17.766002 arm64_za-ptrace_Set_VL_1296 pass
13188 17:01:17.766097 arm64_za-ptrace_Disabled_ZA_for_VL_1296 skip
13189 17:01:17.766179 arm64_za-ptrace_Get_and_set_data_for_VL_1296 skip
13190 17:01:17.766258 arm64_za-ptrace_Set_VL_1312 pass
13191 17:01:17.766351 arm64_za-ptrace_Disabled_ZA_for_VL_1312 skip
13192 17:01:17.766433 arm64_za-ptrace_Get_and_set_data_for_VL_1312 skip
13193 17:01:17.766518 arm64_za-ptrace_Set_VL_1328 pass
13194 17:01:17.766611 arm64_za-ptrace_Disabled_ZA_for_VL_1328 skip
13195 17:01:17.766693 arm64_za-ptrace_Get_and_set_data_for_VL_1328 skip
13196 17:01:17.766773 arm64_za-ptrace_Set_VL_1344 pass
13197 17:01:17.766864 arm64_za-ptrace_Disabled_ZA_for_VL_1344 skip
13198 17:01:17.766945 arm64_za-ptrace_Get_and_set_data_for_VL_1344 skip
13199 17:01:17.767038 arm64_za-ptrace_Set_VL_1360 pass
13200 17:01:17.767131 arm64_za-ptrace_Disabled_ZA_for_VL_1360 skip
13201 17:01:17.767225 arm64_za-ptrace_Get_and_set_data_for_VL_1360 skip
13202 17:01:17.767317 arm64_za-ptrace_Set_VL_1376 pass
13203 17:01:17.771577 arm64_za-ptrace_Disabled_ZA_for_VL_1376 skip
13204 17:01:17.771904 arm64_za-ptrace_Get_and_set_data_for_VL_1376 skip
13205 17:01:17.772012 arm64_za-ptrace_Set_VL_1392 pass
13206 17:01:17.772096 arm64_za-ptrace_Disabled_ZA_for_VL_1392 skip
13207 17:01:17.772192 arm64_za-ptrace_Get_and_set_data_for_VL_1392 skip
13208 17:01:17.772275 arm64_za-ptrace_Set_VL_1408 pass
13209 17:01:17.772355 arm64_za-ptrace_Disabled_ZA_for_VL_1408 skip
13210 17:01:17.772448 arm64_za-ptrace_Get_and_set_data_for_VL_1408 skip
13211 17:01:17.772538 arm64_za-ptrace_Set_VL_1424 pass
13212 17:01:17.772618 arm64_za-ptrace_Disabled_ZA_for_VL_1424 skip
13213 17:01:17.772712 arm64_za-ptrace_Get_and_set_data_for_VL_1424 skip
13214 17:01:17.772795 arm64_za-ptrace_Set_VL_1440 pass
13215 17:01:17.772889 arm64_za-ptrace_Disabled_ZA_for_VL_1440 skip
13216 17:01:17.772986 arm64_za-ptrace_Get_and_set_data_for_VL_1440 skip
13217 17:01:17.773073 arm64_za-ptrace_Set_VL_1456 pass
13218 17:01:17.773166 arm64_za-ptrace_Disabled_ZA_for_VL_1456 skip
13219 17:01:17.773245 arm64_za-ptrace_Get_and_set_data_for_VL_1456 skip
13220 17:01:17.773336 arm64_za-ptrace_Set_VL_1472 pass
13221 17:01:17.773413 arm64_za-ptrace_Disabled_ZA_for_VL_1472 skip
13222 17:01:17.773502 arm64_za-ptrace_Get_and_set_data_for_VL_1472 skip
13223 17:01:17.773591 arm64_za-ptrace_Set_VL_1488 pass
13224 17:01:17.773711 arm64_za-ptrace_Disabled_ZA_for_VL_1488 skip
13225 17:01:17.773793 arm64_za-ptrace_Get_and_set_data_for_VL_1488 skip
13226 17:01:17.773892 arm64_za-ptrace_Set_VL_1504 pass
13227 17:01:17.774398 arm64_za-ptrace_Disabled_ZA_for_VL_1504 skip
13228 17:01:17.774507 arm64_za-ptrace_Get_and_set_data_for_VL_1504 skip
13229 17:01:17.774593 arm64_za-ptrace_Set_VL_1520 pass
13230 17:01:17.774692 arm64_za-ptrace_Disabled_ZA_for_VL_1520 skip
13231 17:01:17.774777 arm64_za-ptrace_Get_and_set_data_for_VL_1520 skip
13232 17:01:17.774861 arm64_za-ptrace_Set_VL_1536 pass
13233 17:01:17.774944 arm64_za-ptrace_Disabled_ZA_for_VL_1536 skip
13234 17:01:17.788581 arm64_za-ptrace_Get_and_set_data_for_VL_1536 skip
13235 17:01:17.788823 arm64_za-ptrace_Set_VL_1552 pass
13236 17:01:17.789129 arm64_za-ptrace_Disabled_ZA_for_VL_1552 skip
13237 17:01:17.789227 arm64_za-ptrace_Get_and_set_data_for_VL_1552 skip
13238 17:01:17.789306 arm64_za-ptrace_Set_VL_1568 pass
13239 17:01:17.789382 arm64_za-ptrace_Disabled_ZA_for_VL_1568 skip
13240 17:01:17.789456 arm64_za-ptrace_Get_and_set_data_for_VL_1568 skip
13241 17:01:17.789703 arm64_za-ptrace_Set_VL_1584 pass
13242 17:01:17.789814 arm64_za-ptrace_Disabled_ZA_for_VL_1584 skip
13243 17:01:17.789896 arm64_za-ptrace_Get_and_set_data_for_VL_1584 skip
13244 17:01:17.789976 arm64_za-ptrace_Set_VL_1600 pass
13245 17:01:17.790055 arm64_za-ptrace_Disabled_ZA_for_VL_1600 skip
13246 17:01:17.790136 arm64_za-ptrace_Get_and_set_data_for_VL_1600 skip
13247 17:01:17.790215 arm64_za-ptrace_Set_VL_1616 pass
13248 17:01:17.790291 arm64_za-ptrace_Disabled_ZA_for_VL_1616 skip
13249 17:01:17.790383 arm64_za-ptrace_Get_and_set_data_for_VL_1616 skip
13250 17:01:17.790463 arm64_za-ptrace_Set_VL_1632 pass
13251 17:01:17.790540 arm64_za-ptrace_Disabled_ZA_for_VL_1632 skip
13252 17:01:17.790617 arm64_za-ptrace_Get_and_set_data_for_VL_1632 skip
13253 17:01:17.790694 arm64_za-ptrace_Set_VL_1648 pass
13254 17:01:17.790791 arm64_za-ptrace_Disabled_ZA_for_VL_1648 skip
13255 17:01:17.790874 arm64_za-ptrace_Get_and_set_data_for_VL_1648 skip
13256 17:01:17.790953 arm64_za-ptrace_Set_VL_1664 pass
13257 17:01:17.791035 arm64_za-ptrace_Disabled_ZA_for_VL_1664 skip
13258 17:01:17.791131 arm64_za-ptrace_Get_and_set_data_for_VL_1664 skip
13259 17:01:17.791215 arm64_za-ptrace_Set_VL_1680 pass
13260 17:01:17.791292 arm64_za-ptrace_Disabled_ZA_for_VL_1680 skip
13261 17:01:17.791372 arm64_za-ptrace_Get_and_set_data_for_VL_1680 skip
13262 17:01:17.791469 arm64_za-ptrace_Set_VL_1696 pass
13263 17:01:17.791554 arm64_za-ptrace_Disabled_ZA_for_VL_1696 skip
13264 17:01:17.791636 arm64_za-ptrace_Get_and_set_data_for_VL_1696 skip
13265 17:01:17.795587 arm64_za-ptrace_Set_VL_1712 pass
13266 17:01:17.795968 arm64_za-ptrace_Disabled_ZA_for_VL_1712 skip
13267 17:01:17.796075 arm64_za-ptrace_Get_and_set_data_for_VL_1712 skip
13268 17:01:17.796162 arm64_za-ptrace_Set_VL_1728 pass
13269 17:01:17.796247 arm64_za-ptrace_Disabled_ZA_for_VL_1728 skip
13270 17:01:17.796346 arm64_za-ptrace_Get_and_set_data_for_VL_1728 skip
13271 17:01:17.796432 arm64_za-ptrace_Set_VL_1744 pass
13272 17:01:17.796538 arm64_za-ptrace_Disabled_ZA_for_VL_1744 skip
13273 17:01:17.796625 arm64_za-ptrace_Get_and_set_data_for_VL_1744 skip
13274 17:01:17.796709 arm64_za-ptrace_Set_VL_1760 pass
13275 17:01:17.796792 arm64_za-ptrace_Disabled_ZA_for_VL_1760 skip
13276 17:01:17.796890 arm64_za-ptrace_Get_and_set_data_for_VL_1760 skip
13277 17:01:17.796983 arm64_za-ptrace_Set_VL_1776 pass
13278 17:01:17.797086 arm64_za-ptrace_Disabled_ZA_for_VL_1776 skip
13279 17:01:17.797173 arm64_za-ptrace_Get_and_set_data_for_VL_1776 skip
13280 17:01:17.797257 arm64_za-ptrace_Set_VL_1792 pass
13281 17:01:17.797340 arm64_za-ptrace_Disabled_ZA_for_VL_1792 skip
13282 17:01:17.797440 arm64_za-ptrace_Get_and_set_data_for_VL_1792 skip
13283 17:01:17.797531 arm64_za-ptrace_Set_VL_1808 pass
13284 17:01:17.797615 arm64_za-ptrace_Disabled_ZA_for_VL_1808 skip
13285 17:01:17.797723 arm64_za-ptrace_Get_and_set_data_for_VL_1808 skip
13286 17:01:17.797809 arm64_za-ptrace_Set_VL_1824 pass
13287 17:01:17.797893 arm64_za-ptrace_Disabled_ZA_for_VL_1824 skip
13288 17:01:17.797993 arm64_za-ptrace_Get_and_set_data_for_VL_1824 skip
13289 17:01:17.798079 arm64_za-ptrace_Set_VL_1840 pass
13290 17:01:17.798178 arm64_za-ptrace_Disabled_ZA_for_VL_1840 skip
13291 17:01:17.798265 arm64_za-ptrace_Get_and_set_data_for_VL_1840 skip
13292 17:01:17.798348 arm64_za-ptrace_Set_VL_1856 pass
13293 17:01:17.798446 arm64_za-ptrace_Disabled_ZA_for_VL_1856 skip
13294 17:01:17.798536 arm64_za-ptrace_Get_and_set_data_for_VL_1856 skip
13295 17:01:17.798623 arm64_za-ptrace_Set_VL_1872 pass
13296 17:01:17.798724 arm64_za-ptrace_Disabled_ZA_for_VL_1872 skip
13297 17:01:17.798811 arm64_za-ptrace_Get_and_set_data_for_VL_1872 skip
13298 17:01:17.798896 arm64_za-ptrace_Set_VL_1888 pass
13299 17:01:17.798995 arm64_za-ptrace_Disabled_ZA_for_VL_1888 skip
13300 17:01:17.799625 arm64_za-ptrace_Get_and_set_data_for_VL_1888 skip
13301 17:01:17.799723 arm64_za-ptrace_Set_VL_1904 pass
13302 17:01:17.799800 arm64_za-ptrace_Disabled_ZA_for_VL_1904 skip
13303 17:01:17.799875 arm64_za-ptrace_Get_and_set_data_for_VL_1904 skip
13304 17:01:17.799949 arm64_za-ptrace_Set_VL_1920 pass
13305 17:01:17.800023 arm64_za-ptrace_Disabled_ZA_for_VL_1920 skip
13306 17:01:17.803654 arm64_za-ptrace_Get_and_set_data_for_VL_1920 skip
13307 17:01:17.803880 arm64_za-ptrace_Set_VL_1936 pass
13308 17:01:17.804218 arm64_za-ptrace_Disabled_ZA_for_VL_1936 skip
13309 17:01:17.804323 arm64_za-ptrace_Get_and_set_data_for_VL_1936 skip
13310 17:01:17.804410 arm64_za-ptrace_Set_VL_1952 pass
13311 17:01:17.804500 arm64_za-ptrace_Disabled_ZA_for_VL_1952 skip
13312 17:01:17.804585 arm64_za-ptrace_Get_and_set_data_for_VL_1952 skip
13313 17:01:17.804673 arm64_za-ptrace_Set_VL_1968 pass
13314 17:01:17.804783 arm64_za-ptrace_Disabled_ZA_for_VL_1968 skip
13315 17:01:17.804872 arm64_za-ptrace_Get_and_set_data_for_VL_1968 skip
13316 17:01:17.804958 arm64_za-ptrace_Set_VL_1984 pass
13317 17:01:17.805227 arm64_za-ptrace_Disabled_ZA_for_VL_1984 skip
13318 17:01:17.805310 arm64_za-ptrace_Get_and_set_data_for_VL_1984 skip
13319 17:01:17.805450 arm64_za-ptrace_Set_VL_2000 pass
13320 17:01:17.805544 arm64_za-ptrace_Disabled_ZA_for_VL_2000 skip
13321 17:01:17.805627 arm64_za-ptrace_Get_and_set_data_for_VL_2000 skip
13322 17:01:17.805715 arm64_za-ptrace_Set_VL_2016 pass
13323 17:01:17.805791 arm64_za-ptrace_Disabled_ZA_for_VL_2016 skip
13324 17:01:17.805864 arm64_za-ptrace_Get_and_set_data_for_VL_2016 skip
13325 17:01:17.805953 arm64_za-ptrace_Set_VL_2032 pass
13326 17:01:17.806027 arm64_za-ptrace_Disabled_ZA_for_VL_2032 skip
13327 17:01:17.806098 arm64_za-ptrace_Get_and_set_data_for_VL_2032 skip
13328 17:01:17.806169 arm64_za-ptrace_Set_VL_2048 pass
13329 17:01:17.806242 arm64_za-ptrace_Disabled_ZA_for_VL_2048 skip
13330 17:01:17.806340 arm64_za-ptrace_Get_and_set_data_for_VL_2048 skip
13331 17:01:17.806427 arm64_za-ptrace_Set_VL_2064 pass
13332 17:01:17.806511 arm64_za-ptrace_Disabled_ZA_for_VL_2064 skip
13333 17:01:17.806594 arm64_za-ptrace_Get_and_set_data_for_VL_2064 skip
13334 17:01:17.806677 arm64_za-ptrace_Set_VL_2080 pass
13335 17:01:17.806779 arm64_za-ptrace_Disabled_ZA_for_VL_2080 skip
13336 17:01:17.806865 arm64_za-ptrace_Get_and_set_data_for_VL_2080 skip
13337 17:01:17.806948 arm64_za-ptrace_Set_VL_2096 pass
13338 17:01:17.807031 arm64_za-ptrace_Disabled_ZA_for_VL_2096 skip
13339 17:01:17.807114 arm64_za-ptrace_Get_and_set_data_for_VL_2096 skip
13340 17:01:17.807197 arm64_za-ptrace_Set_VL_2112 pass
13341 17:01:17.807280 arm64_za-ptrace_Disabled_ZA_for_VL_2112 skip
13342 17:01:17.807380 arm64_za-ptrace_Get_and_set_data_for_VL_2112 skip
13343 17:01:17.807466 arm64_za-ptrace_Set_VL_2128 pass
13344 17:01:17.807555 arm64_za-ptrace_Disabled_ZA_for_VL_2128 skip
13345 17:01:17.807637 arm64_za-ptrace_Get_and_set_data_for_VL_2128 skip
13346 17:01:17.807716 arm64_za-ptrace_Set_VL_2144 pass
13347 17:01:17.807788 arm64_za-ptrace_Disabled_ZA_for_VL_2144 skip
13348 17:01:17.807861 arm64_za-ptrace_Get_and_set_data_for_VL_2144 skip
13349 17:01:17.811823 arm64_za-ptrace_Set_VL_2160 pass
13350 17:01:17.812020 arm64_za-ptrace_Disabled_ZA_for_VL_2160 skip
13351 17:01:17.812125 arm64_za-ptrace_Get_and_set_data_for_VL_2160 skip
13352 17:01:17.812214 arm64_za-ptrace_Set_VL_2176 pass
13353 17:01:17.812301 arm64_za-ptrace_Disabled_ZA_for_VL_2176 skip
13354 17:01:17.812404 arm64_za-ptrace_Get_and_set_data_for_VL_2176 skip
13355 17:01:17.812498 arm64_za-ptrace_Set_VL_2192 pass
13356 17:01:17.812586 arm64_za-ptrace_Disabled_ZA_for_VL_2192 skip
13357 17:01:17.812669 arm64_za-ptrace_Get_and_set_data_for_VL_2192 skip
13358 17:01:17.812770 arm64_za-ptrace_Set_VL_2208 pass
13359 17:01:17.812857 arm64_za-ptrace_Disabled_ZA_for_VL_2208 skip
13360 17:01:17.812941 arm64_za-ptrace_Get_and_set_data_for_VL_2208 skip
13361 17:01:17.813042 arm64_za-ptrace_Set_VL_2224 pass
13362 17:01:17.813123 arm64_za-ptrace_Disabled_ZA_for_VL_2224 skip
13363 17:01:17.813209 arm64_za-ptrace_Get_and_set_data_for_VL_2224 skip
13364 17:01:17.813285 arm64_za-ptrace_Set_VL_2240 pass
13365 17:01:17.813374 arm64_za-ptrace_Disabled_ZA_for_VL_2240 skip
13366 17:01:17.813450 arm64_za-ptrace_Get_and_set_data_for_VL_2240 skip
13367 17:01:17.813705 arm64_za-ptrace_Set_VL_2256 pass
13368 17:01:17.813813 arm64_za-ptrace_Disabled_ZA_for_VL_2256 skip
13369 17:01:17.813895 arm64_za-ptrace_Get_and_set_data_for_VL_2256 skip
13370 17:01:17.814172 arm64_za-ptrace_Set_VL_2272 pass
13371 17:01:17.814273 arm64_za-ptrace_Disabled_ZA_for_VL_2272 skip
13372 17:01:17.814357 arm64_za-ptrace_Get_and_set_data_for_VL_2272 skip
13373 17:01:17.814437 arm64_za-ptrace_Set_VL_2288 pass
13374 17:01:17.814521 arm64_za-ptrace_Disabled_ZA_for_VL_2288 skip
13375 17:01:17.814616 arm64_za-ptrace_Get_and_set_data_for_VL_2288 skip
13376 17:01:17.814699 arm64_za-ptrace_Set_VL_2304 pass
13377 17:01:17.814779 arm64_za-ptrace_Disabled_ZA_for_VL_2304 skip
13378 17:01:17.814860 arm64_za-ptrace_Get_and_set_data_for_VL_2304 skip
13379 17:01:17.814953 arm64_za-ptrace_Set_VL_2320 pass
13380 17:01:17.815033 arm64_za-ptrace_Disabled_ZA_for_VL_2320 skip
13381 17:01:17.815111 arm64_za-ptrace_Get_and_set_data_for_VL_2320 skip
13382 17:01:17.815188 arm64_za-ptrace_Set_VL_2336 pass
13383 17:01:17.815468 arm64_za-ptrace_Disabled_ZA_for_VL_2336 skip
13384 17:01:17.815571 arm64_za-ptrace_Get_and_set_data_for_VL_2336 skip
13385 17:01:17.815653 arm64_za-ptrace_Set_VL_2352 pass
13386 17:01:17.815733 arm64_za-ptrace_Disabled_ZA_for_VL_2352 skip
13387 17:01:17.815812 arm64_za-ptrace_Get_and_set_data_for_VL_2352 skip
13388 17:01:17.815891 arm64_za-ptrace_Set_VL_2368 pass
13389 17:01:17.815969 arm64_za-ptrace_Disabled_ZA_for_VL_2368 skip
13390 17:01:17.819589 arm64_za-ptrace_Get_and_set_data_for_VL_2368 skip
13391 17:01:17.819972 arm64_za-ptrace_Set_VL_2384 pass
13392 17:01:17.820079 arm64_za-ptrace_Disabled_ZA_for_VL_2384 skip
13393 17:01:17.820168 arm64_za-ptrace_Get_and_set_data_for_VL_2384 skip
13394 17:01:17.820256 arm64_za-ptrace_Set_VL_2400 pass
13395 17:01:17.820358 arm64_za-ptrace_Disabled_ZA_for_VL_2400 skip
13396 17:01:17.820447 arm64_za-ptrace_Get_and_set_data_for_VL_2400 skip
13397 17:01:17.820538 arm64_za-ptrace_Set_VL_2416 pass
13398 17:01:17.821144 arm64_za-ptrace_Disabled_ZA_for_VL_2416 skip
13399 17:01:17.821235 arm64_za-ptrace_Get_and_set_data_for_VL_2416 skip
13400 17:01:17.821313 arm64_za-ptrace_Set_VL_2432 pass
13401 17:01:17.821391 arm64_za-ptrace_Disabled_ZA_for_VL_2432 skip
13402 17:01:17.821467 arm64_za-ptrace_Get_and_set_data_for_VL_2432 skip
13403 17:01:17.821548 arm64_za-ptrace_Set_VL_2448 pass
13404 17:01:17.821627 arm64_za-ptrace_Disabled_ZA_for_VL_2448 skip
13405 17:01:17.821713 arm64_za-ptrace_Get_and_set_data_for_VL_2448 skip
13406 17:01:17.821795 arm64_za-ptrace_Set_VL_2464 pass
13407 17:01:17.821879 arm64_za-ptrace_Disabled_ZA_for_VL_2464 skip
13408 17:01:17.822155 arm64_za-ptrace_Get_and_set_data_for_VL_2464 skip
13409 17:01:17.822248 arm64_za-ptrace_Set_VL_2480 pass
13410 17:01:17.822334 arm64_za-ptrace_Disabled_ZA_for_VL_2480 skip
13411 17:01:17.822420 arm64_za-ptrace_Get_and_set_data_for_VL_2480 skip
13412 17:01:17.822507 arm64_za-ptrace_Set_VL_2496 pass
13413 17:01:17.822596 arm64_za-ptrace_Disabled_ZA_for_VL_2496 skip
13414 17:01:17.822682 arm64_za-ptrace_Get_and_set_data_for_VL_2496 skip
13415 17:01:17.822767 arm64_za-ptrace_Set_VL_2512 pass
13416 17:01:17.822870 arm64_za-ptrace_Disabled_ZA_for_VL_2512 skip
13417 17:01:17.822958 arm64_za-ptrace_Get_and_set_data_for_VL_2512 skip
13418 17:01:17.823044 arm64_za-ptrace_Set_VL_2528 pass
13419 17:01:17.823129 arm64_za-ptrace_Disabled_ZA_for_VL_2528 skip
13420 17:01:17.823214 arm64_za-ptrace_Get_and_set_data_for_VL_2528 skip
13421 17:01:17.823296 arm64_za-ptrace_Set_VL_2544 pass
13422 17:01:17.823373 arm64_za-ptrace_Disabled_ZA_for_VL_2544 skip
13423 17:01:17.823466 arm64_za-ptrace_Get_and_set_data_for_VL_2544 skip
13424 17:01:17.823553 arm64_za-ptrace_Set_VL_2560 pass
13425 17:01:17.823631 arm64_za-ptrace_Disabled_ZA_for_VL_2560 skip
13426 17:01:17.827799 arm64_za-ptrace_Get_and_set_data_for_VL_2560 skip
13427 17:01:17.841037 arm64_za-ptrace_Set_VL_2576 pass
13428 17:01:17.841738 arm64_za-ptrace_Disabled_ZA_for_VL_2576 skip
13429 17:01:17.841862 arm64_za-ptrace_Get_and_set_data_for_VL_2576 skip
13430 17:01:17.841951 arm64_za-ptrace_Set_VL_2592 pass
13431 17:01:17.842036 arm64_za-ptrace_Disabled_ZA_for_VL_2592 skip
13432 17:01:17.842114 arm64_za-ptrace_Get_and_set_data_for_VL_2592 skip
13433 17:01:17.842190 arm64_za-ptrace_Set_VL_2608 pass
13434 17:01:17.842268 arm64_za-ptrace_Disabled_ZA_for_VL_2608 skip
13435 17:01:17.842552 arm64_za-ptrace_Get_and_set_data_for_VL_2608 skip
13436 17:01:17.842658 arm64_za-ptrace_Set_VL_2624 pass
13437 17:01:17.842741 arm64_za-ptrace_Disabled_ZA_for_VL_2624 skip
13438 17:01:17.842818 arm64_za-ptrace_Get_and_set_data_for_VL_2624 skip
13439 17:01:17.842895 arm64_za-ptrace_Set_VL_2640 pass
13440 17:01:17.842970 arm64_za-ptrace_Disabled_ZA_for_VL_2640 skip
13441 17:01:17.843047 arm64_za-ptrace_Get_and_set_data_for_VL_2640 skip
13442 17:01:17.843122 arm64_za-ptrace_Set_VL_2656 pass
13443 17:01:17.843198 arm64_za-ptrace_Disabled_ZA_for_VL_2656 skip
13444 17:01:17.843292 arm64_za-ptrace_Get_and_set_data_for_VL_2656 skip
13445 17:01:17.843371 arm64_za-ptrace_Set_VL_2672 pass
13446 17:01:17.843448 arm64_za-ptrace_Disabled_ZA_for_VL_2672 skip
13447 17:01:17.843523 arm64_za-ptrace_Get_and_set_data_for_VL_2672 skip
13448 17:01:17.843604 arm64_za-ptrace_Set_VL_2688 pass
13449 17:01:17.843680 arm64_za-ptrace_Disabled_ZA_for_VL_2688 skip
13450 17:01:17.843756 arm64_za-ptrace_Get_and_set_data_for_VL_2688 skip
13451 17:01:17.843848 arm64_za-ptrace_Set_VL_2704 pass
13452 17:01:17.843927 arm64_za-ptrace_Disabled_ZA_for_VL_2704 skip
13453 17:01:17.844002 arm64_za-ptrace_Get_and_set_data_for_VL_2704 skip
13454 17:01:17.844079 arm64_za-ptrace_Set_VL_2720 pass
13455 17:01:17.844154 arm64_za-ptrace_Disabled_ZA_for_VL_2720 skip
13456 17:01:17.844246 arm64_za-ptrace_Get_and_set_data_for_VL_2720 skip
13457 17:01:17.844326 arm64_za-ptrace_Set_VL_2736 pass
13458 17:01:17.844401 arm64_za-ptrace_Disabled_ZA_for_VL_2736 skip
13459 17:01:17.844479 arm64_za-ptrace_Get_and_set_data_for_VL_2736 skip
13460 17:01:17.844569 arm64_za-ptrace_Set_VL_2752 pass
13461 17:01:17.844648 arm64_za-ptrace_Disabled_ZA_for_VL_2752 skip
13462 17:01:17.844724 arm64_za-ptrace_Get_and_set_data_for_VL_2752 skip
13463 17:01:17.844814 arm64_za-ptrace_Set_VL_2768 pass
13464 17:01:17.844893 arm64_za-ptrace_Disabled_ZA_for_VL_2768 skip
13465 17:01:17.844986 arm64_za-ptrace_Get_and_set_data_for_VL_2768 skip
13466 17:01:17.845067 arm64_za-ptrace_Set_VL_2784 pass
13467 17:01:17.845361 arm64_za-ptrace_Disabled_ZA_for_VL_2784 skip
13468 17:01:17.845461 arm64_za-ptrace_Get_and_set_data_for_VL_2784 skip
13469 17:01:17.845539 arm64_za-ptrace_Set_VL_2800 pass
13470 17:01:17.845623 arm64_za-ptrace_Disabled_ZA_for_VL_2800 skip
13471 17:01:17.845735 arm64_za-ptrace_Get_and_set_data_for_VL_2800 skip
13472 17:01:17.845817 arm64_za-ptrace_Set_VL_2816 pass
13473 17:01:17.845897 arm64_za-ptrace_Disabled_ZA_for_VL_2816 skip
13474 17:01:17.845982 arm64_za-ptrace_Get_and_set_data_for_VL_2816 skip
13475 17:01:17.846082 arm64_za-ptrace_Set_VL_2832 pass
13476 17:01:17.846166 arm64_za-ptrace_Disabled_ZA_for_VL_2832 skip
13477 17:01:17.846246 arm64_za-ptrace_Get_and_set_data_for_VL_2832 skip
13478 17:01:17.846337 arm64_za-ptrace_Set_VL_2848 pass
13479 17:01:17.846417 arm64_za-ptrace_Disabled_ZA_for_VL_2848 skip
13480 17:01:17.846497 arm64_za-ptrace_Get_and_set_data_for_VL_2848 skip
13481 17:01:17.846591 arm64_za-ptrace_Set_VL_2864 pass
13482 17:01:17.846676 arm64_za-ptrace_Disabled_ZA_for_VL_2864 skip
13483 17:01:17.846771 arm64_za-ptrace_Get_and_set_data_for_VL_2864 skip
13484 17:01:17.846852 arm64_za-ptrace_Set_VL_2880 pass
13485 17:01:17.846933 arm64_za-ptrace_Disabled_ZA_for_VL_2880 skip
13486 17:01:17.847022 arm64_za-ptrace_Get_and_set_data_for_VL_2880 skip
13487 17:01:17.847097 arm64_za-ptrace_Set_VL_2896 pass
13488 17:01:17.847174 arm64_za-ptrace_Disabled_ZA_for_VL_2896 skip
13489 17:01:17.847264 arm64_za-ptrace_Get_and_set_data_for_VL_2896 skip
13490 17:01:17.847342 arm64_za-ptrace_Set_VL_2912 pass
13491 17:01:17.847431 arm64_za-ptrace_Disabled_ZA_for_VL_2912 skip
13492 17:01:17.851671 arm64_za-ptrace_Get_and_set_data_for_VL_2912 skip
13493 17:01:17.851798 arm64_za-ptrace_Set_VL_2928 pass
13494 17:01:17.851882 arm64_za-ptrace_Disabled_ZA_for_VL_2928 skip
13495 17:01:17.852173 arm64_za-ptrace_Get_and_set_data_for_VL_2928 skip
13496 17:01:17.852274 arm64_za-ptrace_Set_VL_2944 pass
13497 17:01:17.852356 arm64_za-ptrace_Disabled_ZA_for_VL_2944 skip
13498 17:01:17.852433 arm64_za-ptrace_Get_and_set_data_for_VL_2944 skip
13499 17:01:17.852509 arm64_za-ptrace_Set_VL_2960 pass
13500 17:01:17.852600 arm64_za-ptrace_Disabled_ZA_for_VL_2960 skip
13501 17:01:17.852680 arm64_za-ptrace_Get_and_set_data_for_VL_2960 skip
13502 17:01:17.852757 arm64_za-ptrace_Set_VL_2976 pass
13503 17:01:17.852846 arm64_za-ptrace_Disabled_ZA_for_VL_2976 skip
13504 17:01:17.852924 arm64_za-ptrace_Get_and_set_data_for_VL_2976 skip
13505 17:01:17.853088 arm64_za-ptrace_Set_VL_2992 pass
13506 17:01:17.853191 arm64_za-ptrace_Disabled_ZA_for_VL_2992 skip
13507 17:01:17.853276 arm64_za-ptrace_Get_and_set_data_for_VL_2992 skip
13508 17:01:17.853440 arm64_za-ptrace_Set_VL_3008 pass
13509 17:01:17.853543 arm64_za-ptrace_Disabled_ZA_for_VL_3008 skip
13510 17:01:17.853625 arm64_za-ptrace_Get_and_set_data_for_VL_3008 skip
13511 17:01:17.853711 arm64_za-ptrace_Set_VL_3024 pass
13512 17:01:17.853790 arm64_za-ptrace_Disabled_ZA_for_VL_3024 skip
13513 17:01:17.853882 arm64_za-ptrace_Get_and_set_data_for_VL_3024 skip
13514 17:01:17.853962 arm64_za-ptrace_Set_VL_3040 pass
13515 17:01:17.854052 arm64_za-ptrace_Disabled_ZA_for_VL_3040 skip
13516 17:01:17.854145 arm64_za-ptrace_Get_and_set_data_for_VL_3040 skip
13517 17:01:17.854226 arm64_za-ptrace_Set_VL_3056 pass
13518 17:01:17.854316 arm64_za-ptrace_Disabled_ZA_for_VL_3056 skip
13519 17:01:17.854601 arm64_za-ptrace_Get_and_set_data_for_VL_3056 skip
13520 17:01:17.854702 arm64_za-ptrace_Set_VL_3072 pass
13521 17:01:17.854782 arm64_za-ptrace_Disabled_ZA_for_VL_3072 skip
13522 17:01:17.854858 arm64_za-ptrace_Get_and_set_data_for_VL_3072 skip
13523 17:01:17.854934 arm64_za-ptrace_Set_VL_3088 pass
13524 17:01:17.855026 arm64_za-ptrace_Disabled_ZA_for_VL_3088 skip
13525 17:01:17.855105 arm64_za-ptrace_Get_and_set_data_for_VL_3088 skip
13526 17:01:17.855180 arm64_za-ptrace_Set_VL_3104 pass
13527 17:01:17.855254 arm64_za-ptrace_Disabled_ZA_for_VL_3104 skip
13528 17:01:17.855343 arm64_za-ptrace_Get_and_set_data_for_VL_3104 skip
13529 17:01:17.855420 arm64_za-ptrace_Set_VL_3120 pass
13530 17:01:17.855494 arm64_za-ptrace_Disabled_ZA_for_VL_3120 skip
13531 17:01:17.859630 arm64_za-ptrace_Get_and_set_data_for_VL_3120 skip
13532 17:01:17.859814 arm64_za-ptrace_Set_VL_3136 pass
13533 17:01:17.860103 arm64_za-ptrace_Disabled_ZA_for_VL_3136 skip
13534 17:01:17.860205 arm64_za-ptrace_Get_and_set_data_for_VL_3136 skip
13535 17:01:17.860284 arm64_za-ptrace_Set_VL_3152 pass
13536 17:01:17.860360 arm64_za-ptrace_Disabled_ZA_for_VL_3152 skip
13537 17:01:17.860450 arm64_za-ptrace_Get_and_set_data_for_VL_3152 skip
13538 17:01:17.860529 arm64_za-ptrace_Set_VL_3168 pass
13539 17:01:17.860604 arm64_za-ptrace_Disabled_ZA_for_VL_3168 skip
13540 17:01:17.860693 arm64_za-ptrace_Get_and_set_data_for_VL_3168 skip
13541 17:01:17.860982 arm64_za-ptrace_Set_VL_3184 pass
13542 17:01:17.861127 arm64_za-ptrace_Disabled_ZA_for_VL_3184 skip
13543 17:01:17.861210 arm64_za-ptrace_Get_and_set_data_for_VL_3184 skip
13544 17:01:17.861386 arm64_za-ptrace_Set_VL_3200 pass
13545 17:01:17.861471 arm64_za-ptrace_Disabled_ZA_for_VL_3200 skip
13546 17:01:17.861547 arm64_za-ptrace_Get_and_set_data_for_VL_3200 skip
13547 17:01:17.861649 arm64_za-ptrace_Set_VL_3216 pass
13548 17:01:17.861730 arm64_za-ptrace_Disabled_ZA_for_VL_3216 skip
13549 17:01:17.861806 arm64_za-ptrace_Get_and_set_data_for_VL_3216 skip
13550 17:01:17.861882 arm64_za-ptrace_Set_VL_3232 pass
13551 17:01:17.861957 arm64_za-ptrace_Disabled_ZA_for_VL_3232 skip
13552 17:01:17.862032 arm64_za-ptrace_Get_and_set_data_for_VL_3232 skip
13553 17:01:17.862106 arm64_za-ptrace_Set_VL_3248 pass
13554 17:01:17.862196 arm64_za-ptrace_Disabled_ZA_for_VL_3248 skip
13555 17:01:17.862273 arm64_za-ptrace_Get_and_set_data_for_VL_3248 skip
13556 17:01:17.862349 arm64_za-ptrace_Set_VL_3264 pass
13557 17:01:17.862424 arm64_za-ptrace_Disabled_ZA_for_VL_3264 skip
13558 17:01:17.862499 arm64_za-ptrace_Get_and_set_data_for_VL_3264 skip
13559 17:01:17.862573 arm64_za-ptrace_Set_VL_3280 pass
13560 17:01:17.862665 arm64_za-ptrace_Disabled_ZA_for_VL_3280 skip
13561 17:01:17.862743 arm64_za-ptrace_Get_and_set_data_for_VL_3280 skip
13562 17:01:17.862818 arm64_za-ptrace_Set_VL_3296 pass
13563 17:01:17.862892 arm64_za-ptrace_Disabled_ZA_for_VL_3296 skip
13564 17:01:17.862981 arm64_za-ptrace_Get_and_set_data_for_VL_3296 skip
13565 17:01:17.863059 arm64_za-ptrace_Set_VL_3312 pass
13566 17:01:17.863134 arm64_za-ptrace_Disabled_ZA_for_VL_3312 skip
13567 17:01:17.863210 arm64_za-ptrace_Get_and_set_data_for_VL_3312 skip
13568 17:01:17.863299 arm64_za-ptrace_Set_VL_3328 pass
13569 17:01:17.863376 arm64_za-ptrace_Disabled_ZA_for_VL_3328 skip
13570 17:01:17.863451 arm64_za-ptrace_Get_and_set_data_for_VL_3328 skip
13571 17:01:17.863538 arm64_za-ptrace_Set_VL_3344 pass
13572 17:01:17.871623 arm64_za-ptrace_Disabled_ZA_for_VL_3344 skip
13573 17:01:17.872076 arm64_za-ptrace_Get_and_set_data_for_VL_3344 skip
13574 17:01:17.872186 arm64_za-ptrace_Set_VL_3360 pass
13575 17:01:17.872277 arm64_za-ptrace_Disabled_ZA_for_VL_3360 skip
13576 17:01:17.872363 arm64_za-ptrace_Get_and_set_data_for_VL_3360 skip
13577 17:01:17.872465 arm64_za-ptrace_Set_VL_3376 pass
13578 17:01:17.872555 arm64_za-ptrace_Disabled_ZA_for_VL_3376 skip
13579 17:01:17.872845 arm64_za-ptrace_Get_and_set_data_for_VL_3376 skip
13580 17:01:17.872957 arm64_za-ptrace_Set_VL_3392 pass
13581 17:01:17.873038 arm64_za-ptrace_Disabled_ZA_for_VL_3392 skip
13582 17:01:17.873114 arm64_za-ptrace_Get_and_set_data_for_VL_3392 skip
13583 17:01:17.873189 arm64_za-ptrace_Set_VL_3408 pass
13584 17:01:17.873263 arm64_za-ptrace_Disabled_ZA_for_VL_3408 skip
13585 17:01:17.873339 arm64_za-ptrace_Get_and_set_data_for_VL_3408 skip
13586 17:01:17.873415 arm64_za-ptrace_Set_VL_3424 pass
13587 17:01:17.873490 arm64_za-ptrace_Disabled_ZA_for_VL_3424 skip
13588 17:01:17.873585 arm64_za-ptrace_Get_and_set_data_for_VL_3424 skip
13589 17:01:17.873671 arm64_za-ptrace_Set_VL_3440 pass
13590 17:01:17.873747 arm64_za-ptrace_Disabled_ZA_for_VL_3440 skip
13591 17:01:17.873823 arm64_za-ptrace_Get_and_set_data_for_VL_3440 skip
13592 17:01:17.873898 arm64_za-ptrace_Set_VL_3456 pass
13593 17:01:17.873976 arm64_za-ptrace_Disabled_ZA_for_VL_3456 skip
13594 17:01:17.874051 arm64_za-ptrace_Get_and_set_data_for_VL_3456 skip
13595 17:01:17.874126 arm64_za-ptrace_Set_VL_3472 pass
13596 17:01:17.874221 arm64_za-ptrace_Disabled_ZA_for_VL_3472 skip
13597 17:01:17.874304 arm64_za-ptrace_Get_and_set_data_for_VL_3472 skip
13598 17:01:17.874386 arm64_za-ptrace_Set_VL_3488 pass
13599 17:01:17.874460 arm64_za-ptrace_Disabled_ZA_for_VL_3488 skip
13600 17:01:17.874534 arm64_za-ptrace_Get_and_set_data_for_VL_3488 skip
13601 17:01:17.874609 arm64_za-ptrace_Set_VL_3504 pass
13602 17:01:17.874695 arm64_za-ptrace_Disabled_ZA_for_VL_3504 skip
13603 17:01:17.874797 arm64_za-ptrace_Get_and_set_data_for_VL_3504 skip
13604 17:01:17.874884 arm64_za-ptrace_Set_VL_3520 pass
13605 17:01:17.874968 arm64_za-ptrace_Disabled_ZA_for_VL_3520 skip
13606 17:01:17.875053 arm64_za-ptrace_Get_and_set_data_for_VL_3520 skip
13607 17:01:17.875136 arm64_za-ptrace_Set_VL_3536 pass
13608 17:01:17.875219 arm64_za-ptrace_Disabled_ZA_for_VL_3536 skip
13609 17:01:17.875302 arm64_za-ptrace_Get_and_set_data_for_VL_3536 skip
13610 17:01:17.875403 arm64_za-ptrace_Set_VL_3552 pass
13611 17:01:17.875490 arm64_za-ptrace_Disabled_ZA_for_VL_3552 skip
13612 17:01:17.875573 arm64_za-ptrace_Get_and_set_data_for_VL_3552 skip
13613 17:01:17.875656 arm64_za-ptrace_Set_VL_3568 pass
13614 17:01:17.875739 arm64_za-ptrace_Disabled_ZA_for_VL_3568 skip
13615 17:01:17.875821 arm64_za-ptrace_Get_and_set_data_for_VL_3568 skip
13616 17:01:17.875904 arm64_za-ptrace_Set_VL_3584 pass
13617 17:01:17.879638 arm64_za-ptrace_Disabled_ZA_for_VL_3584 skip
13618 17:01:17.879830 arm64_za-ptrace_Get_and_set_data_for_VL_3584 skip
13619 17:01:17.893688 arm64_za-ptrace_Set_VL_3600 pass
13620 17:01:17.893934 arm64_za-ptrace_Disabled_ZA_for_VL_3600 skip
13621 17:01:17.894235 arm64_za-ptrace_Get_and_set_data_for_VL_3600 skip
13622 17:01:17.894341 arm64_za-ptrace_Set_VL_3616 pass
13623 17:01:17.894429 arm64_za-ptrace_Disabled_ZA_for_VL_3616 skip
13624 17:01:17.894514 arm64_za-ptrace_Get_and_set_data_for_VL_3616 skip
13625 17:01:17.894598 arm64_za-ptrace_Set_VL_3632 pass
13626 17:01:17.894698 arm64_za-ptrace_Disabled_ZA_for_VL_3632 skip
13627 17:01:17.894784 arm64_za-ptrace_Get_and_set_data_for_VL_3632 skip
13628 17:01:17.894869 arm64_za-ptrace_Set_VL_3648 pass
13629 17:01:17.894952 arm64_za-ptrace_Disabled_ZA_for_VL_3648 skip
13630 17:01:17.895053 arm64_za-ptrace_Get_and_set_data_for_VL_3648 skip
13631 17:01:17.895141 arm64_za-ptrace_Set_VL_3664 pass
13632 17:01:17.895224 arm64_za-ptrace_Disabled_ZA_for_VL_3664 skip
13633 17:01:17.895308 arm64_za-ptrace_Get_and_set_data_for_VL_3664 skip
13634 17:01:17.895407 arm64_za-ptrace_Set_VL_3680 pass
13635 17:01:17.895493 arm64_za-ptrace_Disabled_ZA_for_VL_3680 skip
13636 17:01:17.895577 arm64_za-ptrace_Get_and_set_data_for_VL_3680 skip
13637 17:01:17.895676 arm64_za-ptrace_Set_VL_3696 pass
13638 17:01:17.895963 arm64_za-ptrace_Disabled_ZA_for_VL_3696 skip
13639 17:01:17.896047 arm64_za-ptrace_Get_and_set_data_for_VL_3696 skip
13640 17:01:17.896137 arm64_za-ptrace_Set_VL_3712 pass
13641 17:01:17.896220 arm64_za-ptrace_Disabled_ZA_for_VL_3712 skip
13642 17:01:17.896309 arm64_za-ptrace_Get_and_set_data_for_VL_3712 skip
13643 17:01:17.896398 arm64_za-ptrace_Set_VL_3728 pass
13644 17:01:17.896492 arm64_za-ptrace_Disabled_ZA_for_VL_3728 skip
13645 17:01:17.896771 arm64_za-ptrace_Get_and_set_data_for_VL_3728 skip
13646 17:01:17.896859 arm64_za-ptrace_Set_VL_3744 pass
13647 17:01:17.896947 arm64_za-ptrace_Disabled_ZA_for_VL_3744 skip
13648 17:01:17.897228 arm64_za-ptrace_Get_and_set_data_for_VL_3744 skip
13649 17:01:17.897309 arm64_za-ptrace_Set_VL_3760 pass
13650 17:01:17.897396 arm64_za-ptrace_Disabled_ZA_for_VL_3760 skip
13651 17:01:17.897472 arm64_za-ptrace_Get_and_set_data_for_VL_3760 skip
13652 17:01:17.897561 arm64_za-ptrace_Set_VL_3776 pass
13653 17:01:17.897642 arm64_za-ptrace_Disabled_ZA_for_VL_3776 skip
13654 17:01:17.897749 arm64_za-ptrace_Get_and_set_data_for_VL_3776 skip
13655 17:01:17.897845 arm64_za-ptrace_Set_VL_3792 pass
13656 17:01:17.897936 arm64_za-ptrace_Disabled_ZA_for_VL_3792 skip
13657 17:01:17.898214 arm64_za-ptrace_Get_and_set_data_for_VL_3792 skip
13658 17:01:17.898296 arm64_za-ptrace_Set_VL_3808 pass
13659 17:01:17.898387 arm64_za-ptrace_Disabled_ZA_for_VL_3808 skip
13660 17:01:17.898477 arm64_za-ptrace_Get_and_set_data_for_VL_3808 skip
13661 17:01:17.898554 arm64_za-ptrace_Set_VL_3824 pass
13662 17:01:17.898650 arm64_za-ptrace_Disabled_ZA_for_VL_3824 skip
13663 17:01:17.898746 arm64_za-ptrace_Get_and_set_data_for_VL_3824 skip
13664 17:01:17.898840 arm64_za-ptrace_Set_VL_3840 pass
13665 17:01:17.899114 arm64_za-ptrace_Disabled_ZA_for_VL_3840 skip
13666 17:01:17.899211 arm64_za-ptrace_Get_and_set_data_for_VL_3840 skip
13667 17:01:17.899304 arm64_za-ptrace_Set_VL_3856 pass
13668 17:01:17.899402 arm64_za-ptrace_Disabled_ZA_for_VL_3856 skip
13669 17:01:17.903993 arm64_za-ptrace_Get_and_set_data_for_VL_3856 skip
13670 17:01:17.904224 arm64_za-ptrace_Set_VL_3872 pass
13671 17:01:17.904313 arm64_za-ptrace_Disabled_ZA_for_VL_3872 skip
13672 17:01:17.904414 arm64_za-ptrace_Get_and_set_data_for_VL_3872 skip
13673 17:01:17.904502 arm64_za-ptrace_Set_VL_3888 pass
13674 17:01:17.904586 arm64_za-ptrace_Disabled_ZA_for_VL_3888 skip
13675 17:01:17.904692 arm64_za-ptrace_Get_and_set_data_for_VL_3888 skip
13676 17:01:17.904778 arm64_za-ptrace_Set_VL_3904 pass
13677 17:01:17.904878 arm64_za-ptrace_Disabled_ZA_for_VL_3904 skip
13678 17:01:17.905190 arm64_za-ptrace_Get_and_set_data_for_VL_3904 skip
13679 17:01:17.905286 arm64_za-ptrace_Set_VL_3920 pass
13680 17:01:17.905373 arm64_za-ptrace_Disabled_ZA_for_VL_3920 skip
13681 17:01:17.905449 arm64_za-ptrace_Get_and_set_data_for_VL_3920 skip
13682 17:01:17.905523 arm64_za-ptrace_Set_VL_3936 pass
13683 17:01:17.905612 arm64_za-ptrace_Disabled_ZA_for_VL_3936 skip
13684 17:01:17.905703 arm64_za-ptrace_Get_and_set_data_for_VL_3936 skip
13685 17:01:17.905788 arm64_za-ptrace_Set_VL_3952 pass
13686 17:01:17.905885 arm64_za-ptrace_Disabled_ZA_for_VL_3952 skip
13687 17:01:17.905973 arm64_za-ptrace_Get_and_set_data_for_VL_3952 skip
13688 17:01:17.906060 arm64_za-ptrace_Set_VL_3968 pass
13689 17:01:17.906152 arm64_za-ptrace_Disabled_ZA_for_VL_3968 skip
13690 17:01:17.906540 arm64_za-ptrace_Get_and_set_data_for_VL_3968 skip
13691 17:01:17.906632 arm64_za-ptrace_Set_VL_3984 pass
13692 17:01:17.906717 arm64_za-ptrace_Disabled_ZA_for_VL_3984 skip
13693 17:01:17.907000 arm64_za-ptrace_Get_and_set_data_for_VL_3984 skip
13694 17:01:17.907090 arm64_za-ptrace_Set_VL_4000 pass
13695 17:01:17.907189 arm64_za-ptrace_Disabled_ZA_for_VL_4000 skip
13696 17:01:17.907276 arm64_za-ptrace_Get_and_set_data_for_VL_4000 skip
13697 17:01:17.907360 arm64_za-ptrace_Set_VL_4016 pass
13698 17:01:17.907460 arm64_za-ptrace_Disabled_ZA_for_VL_4016 skip
13699 17:01:17.907547 arm64_za-ptrace_Get_and_set_data_for_VL_4016 skip
13700 17:01:17.911696 arm64_za-ptrace_Set_VL_4032 pass
13701 17:01:17.911907 arm64_za-ptrace_Disabled_ZA_for_VL_4032 skip
13702 17:01:17.912207 arm64_za-ptrace_Get_and_set_data_for_VL_4032 skip
13703 17:01:17.912310 arm64_za-ptrace_Set_VL_4048 pass
13704 17:01:17.912396 arm64_za-ptrace_Disabled_ZA_for_VL_4048 skip
13705 17:01:17.912480 arm64_za-ptrace_Get_and_set_data_for_VL_4048 skip
13706 17:01:17.912581 arm64_za-ptrace_Set_VL_4064 pass
13707 17:01:17.912668 arm64_za-ptrace_Disabled_ZA_for_VL_4064 skip
13708 17:01:17.912757 arm64_za-ptrace_Get_and_set_data_for_VL_4064 skip
13709 17:01:17.912841 arm64_za-ptrace_Set_VL_4080 pass
13710 17:01:17.912940 arm64_za-ptrace_Disabled_ZA_for_VL_4080 skip
13711 17:01:17.913020 arm64_za-ptrace_Get_and_set_data_for_VL_4080 skip
13712 17:01:17.913092 arm64_za-ptrace_Set_VL_4096 pass
13713 17:01:17.913163 arm64_za-ptrace_Disabled_ZA_for_VL_4096 skip
13714 17:01:17.913247 arm64_za-ptrace_Get_and_set_data_for_VL_4096 skip
13715 17:01:17.913322 arm64_za-ptrace_Set_VL_4112 pass
13716 17:01:17.913406 arm64_za-ptrace_Disabled_ZA_for_VL_4112 skip
13717 17:01:17.913491 arm64_za-ptrace_Get_and_set_data_for_VL_4112 skip
13718 17:01:17.913564 arm64_za-ptrace_Set_VL_4128 pass
13719 17:01:17.913654 arm64_za-ptrace_Disabled_ZA_for_VL_4128 skip
13720 17:01:17.913936 arm64_za-ptrace_Get_and_set_data_for_VL_4128 skip
13721 17:01:17.914016 arm64_za-ptrace_Set_VL_4144 pass
13722 17:01:17.914088 arm64_za-ptrace_Disabled_ZA_for_VL_4144 skip
13723 17:01:17.914172 arm64_za-ptrace_Get_and_set_data_for_VL_4144 skip
13724 17:01:17.914245 arm64_za-ptrace_Set_VL_4160 pass
13725 17:01:17.914328 arm64_za-ptrace_Disabled_ZA_for_VL_4160 skip
13726 17:01:17.914413 arm64_za-ptrace_Get_and_set_data_for_VL_4160 skip
13727 17:01:17.914679 arm64_za-ptrace_Set_VL_4176 pass
13728 17:01:17.914759 arm64_za-ptrace_Disabled_ZA_for_VL_4176 skip
13729 17:01:17.914843 arm64_za-ptrace_Get_and_set_data_for_VL_4176 skip
13730 17:01:17.914920 arm64_za-ptrace_Set_VL_4192 pass
13731 17:01:17.915013 arm64_za-ptrace_Disabled_ZA_for_VL_4192 skip
13732 17:01:17.915113 arm64_za-ptrace_Get_and_set_data_for_VL_4192 skip
13733 17:01:17.915398 arm64_za-ptrace_Set_VL_4208 pass
13734 17:01:17.915488 arm64_za-ptrace_Disabled_ZA_for_VL_4208 skip
13735 17:01:17.919618 arm64_za-ptrace_Get_and_set_data_for_VL_4208 skip
13736 17:01:17.920043 arm64_za-ptrace_Set_VL_4224 pass
13737 17:01:17.920157 arm64_za-ptrace_Disabled_ZA_for_VL_4224 skip
13738 17:01:17.920254 arm64_za-ptrace_Get_and_set_data_for_VL_4224 skip
13739 17:01:17.920348 arm64_za-ptrace_Set_VL_4240 pass
13740 17:01:17.920459 arm64_za-ptrace_Disabled_ZA_for_VL_4240 skip
13741 17:01:17.920554 arm64_za-ptrace_Get_and_set_data_for_VL_4240 skip
13742 17:01:17.920646 arm64_za-ptrace_Set_VL_4256 pass
13743 17:01:17.920743 arm64_za-ptrace_Disabled_ZA_for_VL_4256 skip
13744 17:01:17.921093 arm64_za-ptrace_Get_and_set_data_for_VL_4256 skip
13745 17:01:17.921192 arm64_za-ptrace_Set_VL_4272 pass
13746 17:01:17.921271 arm64_za-ptrace_Disabled_ZA_for_VL_4272 skip
13747 17:01:17.921347 arm64_za-ptrace_Get_and_set_data_for_VL_4272 skip
13748 17:01:17.921644 arm64_za-ptrace_Set_VL_4288 pass
13749 17:01:17.921739 arm64_za-ptrace_Disabled_ZA_for_VL_4288 skip
13750 17:01:17.921814 arm64_za-ptrace_Get_and_set_data_for_VL_4288 skip
13751 17:01:17.921886 arm64_za-ptrace_Set_VL_4304 pass
13752 17:01:17.921962 arm64_za-ptrace_Disabled_ZA_for_VL_4304 skip
13753 17:01:17.922035 arm64_za-ptrace_Get_and_set_data_for_VL_4304 skip
13754 17:01:17.922139 arm64_za-ptrace_Set_VL_4320 pass
13755 17:01:17.922223 arm64_za-ptrace_Disabled_ZA_for_VL_4320 skip
13756 17:01:17.922300 arm64_za-ptrace_Get_and_set_data_for_VL_4320 skip
13757 17:01:17.922407 arm64_za-ptrace_Set_VL_4336 pass
13758 17:01:17.922502 arm64_za-ptrace_Disabled_ZA_for_VL_4336 skip
13759 17:01:17.922584 arm64_za-ptrace_Get_and_set_data_for_VL_4336 skip
13760 17:01:17.922660 arm64_za-ptrace_Set_VL_4352 pass
13761 17:01:17.922737 arm64_za-ptrace_Disabled_ZA_for_VL_4352 skip
13762 17:01:17.922815 arm64_za-ptrace_Get_and_set_data_for_VL_4352 skip
13763 17:01:17.922914 arm64_za-ptrace_Set_VL_4368 pass
13764 17:01:17.922996 arm64_za-ptrace_Disabled_ZA_for_VL_4368 skip
13765 17:01:17.923078 arm64_za-ptrace_Get_and_set_data_for_VL_4368 skip
13766 17:01:17.923159 arm64_za-ptrace_Set_VL_4384 pass
13767 17:01:17.923231 arm64_za-ptrace_Disabled_ZA_for_VL_4384 skip
13768 17:01:17.923307 arm64_za-ptrace_Get_and_set_data_for_VL_4384 skip
13769 17:01:17.923384 arm64_za-ptrace_Set_VL_4400 pass
13770 17:01:17.923478 arm64_za-ptrace_Disabled_ZA_for_VL_4400 skip
13771 17:01:17.923558 arm64_za-ptrace_Get_and_set_data_for_VL_4400 skip
13772 17:01:17.923635 arm64_za-ptrace_Set_VL_4416 pass
13773 17:01:17.923712 arm64_za-ptrace_Disabled_ZA_for_VL_4416 skip
13774 17:01:17.923789 arm64_za-ptrace_Get_and_set_data_for_VL_4416 skip
13775 17:01:17.927693 arm64_za-ptrace_Set_VL_4432 pass
13776 17:01:17.927907 arm64_za-ptrace_Disabled_ZA_for_VL_4432 skip
13777 17:01:17.928200 arm64_za-ptrace_Get_and_set_data_for_VL_4432 skip
13778 17:01:17.928292 arm64_za-ptrace_Set_VL_4448 pass
13779 17:01:17.928378 arm64_za-ptrace_Disabled_ZA_for_VL_4448 skip
13780 17:01:17.928462 arm64_za-ptrace_Get_and_set_data_for_VL_4448 skip
13781 17:01:17.928547 arm64_za-ptrace_Set_VL_4464 pass
13782 17:01:17.928647 arm64_za-ptrace_Disabled_ZA_for_VL_4464 skip
13783 17:01:17.928739 arm64_za-ptrace_Get_and_set_data_for_VL_4464 skip
13784 17:01:17.928824 arm64_za-ptrace_Set_VL_4480 pass
13785 17:01:17.928923 arm64_za-ptrace_Disabled_ZA_for_VL_4480 skip
13786 17:01:17.929004 arm64_za-ptrace_Get_and_set_data_for_VL_4480 skip
13787 17:01:17.929077 arm64_za-ptrace_Set_VL_4496 pass
13788 17:01:17.929163 arm64_za-ptrace_Disabled_ZA_for_VL_4496 skip
13789 17:01:17.929240 arm64_za-ptrace_Get_and_set_data_for_VL_4496 skip
13790 17:01:17.929324 arm64_za-ptrace_Set_VL_4512 pass
13791 17:01:17.929408 arm64_za-ptrace_Disabled_ZA_for_VL_4512 skip
13792 17:01:17.929493 arm64_za-ptrace_Get_and_set_data_for_VL_4512 skip
13793 17:01:17.929765 arm64_za-ptrace_Set_VL_4528 pass
13794 17:01:17.929846 arm64_za-ptrace_Disabled_ZA_for_VL_4528 skip
13795 17:01:17.929931 arm64_za-ptrace_Get_and_set_data_for_VL_4528 skip
13796 17:01:17.930016 arm64_za-ptrace_Set_VL_4544 pass
13797 17:01:17.930291 arm64_za-ptrace_Disabled_ZA_for_VL_4544 skip
13798 17:01:17.930375 arm64_za-ptrace_Get_and_set_data_for_VL_4544 skip
13799 17:01:17.930465 arm64_za-ptrace_Set_VL_4560 pass
13800 17:01:17.930561 arm64_za-ptrace_Disabled_ZA_for_VL_4560 skip
13801 17:01:17.930652 arm64_za-ptrace_Get_and_set_data_for_VL_4560 skip
13802 17:01:17.930932 arm64_za-ptrace_Set_VL_4576 pass
13803 17:01:17.931019 arm64_za-ptrace_Disabled_ZA_for_VL_4576 skip
13804 17:01:17.931120 arm64_za-ptrace_Get_and_set_data_for_VL_4576 skip
13805 17:01:17.931220 arm64_za-ptrace_Set_VL_4592 pass
13806 17:01:17.931495 arm64_za-ptrace_Disabled_ZA_for_VL_4592 skip
13807 17:01:17.931584 arm64_za-ptrace_Get_and_set_data_for_VL_4592 skip
13808 17:01:17.935695 arm64_za-ptrace_Set_VL_4608 pass
13809 17:01:17.936119 arm64_za-ptrace_Disabled_ZA_for_VL_4608 skip
13810 17:01:17.936212 arm64_za-ptrace_Get_and_set_data_for_VL_4608 skip
13811 17:01:17.936487 arm64_za-ptrace_Set_VL_4624 pass
13812 17:01:17.952508 arm64_za-ptrace_Disabled_ZA_for_VL_4624 skip
13813 17:01:17.952951 arm64_za-ptrace_Get_and_set_data_for_VL_4624 skip
13814 17:01:17.953042 arm64_za-ptrace_Set_VL_4640 pass
13815 17:01:17.953121 arm64_za-ptrace_Disabled_ZA_for_VL_4640 skip
13816 17:01:17.953198 arm64_za-ptrace_Get_and_set_data_for_VL_4640 skip
13817 17:01:17.953289 arm64_za-ptrace_Set_VL_4656 pass
13818 17:01:17.953371 arm64_za-ptrace_Disabled_ZA_for_VL_4656 skip
13819 17:01:17.953461 arm64_za-ptrace_Get_and_set_data_for_VL_4656 skip
13820 17:01:17.953541 arm64_za-ptrace_Set_VL_4672 pass
13821 17:01:17.953633 arm64_za-ptrace_Disabled_ZA_for_VL_4672 skip
13822 17:01:17.953717 arm64_za-ptrace_Get_and_set_data_for_VL_4672 skip
13823 17:01:17.953808 arm64_za-ptrace_Set_VL_4688 pass
13824 17:01:17.953904 arm64_za-ptrace_Disabled_ZA_for_VL_4688 skip
13825 17:01:17.954000 arm64_za-ptrace_Get_and_set_data_for_VL_4688 skip
13826 17:01:17.954275 arm64_za-ptrace_Set_VL_4704 pass
13827 17:01:17.954363 arm64_za-ptrace_Disabled_ZA_for_VL_4704 skip
13828 17:01:17.954458 arm64_za-ptrace_Get_and_set_data_for_VL_4704 skip
13829 17:01:17.954541 arm64_za-ptrace_Set_VL_4720 pass
13830 17:01:17.954633 arm64_za-ptrace_Disabled_ZA_for_VL_4720 skip
13831 17:01:17.954911 arm64_za-ptrace_Get_and_set_data_for_VL_4720 skip
13832 17:01:17.955001 arm64_za-ptrace_Set_VL_4736 pass
13833 17:01:17.955293 arm64_za-ptrace_Disabled_ZA_for_VL_4736 skip
13834 17:01:17.955399 arm64_za-ptrace_Get_and_set_data_for_VL_4736 skip
13835 17:01:17.955483 arm64_za-ptrace_Set_VL_4752 pass
13836 17:01:17.955577 arm64_za-ptrace_Disabled_ZA_for_VL_4752 skip
13837 17:01:17.963666 arm64_za-ptrace_Get_and_set_data_for_VL_4752 skip
13838 17:01:17.964183 arm64_za-ptrace_Set_VL_4768 pass
13839 17:01:17.964345 arm64_za-ptrace_Disabled_ZA_for_VL_4768 skip
13840 17:01:17.964498 arm64_za-ptrace_Get_and_set_data_for_VL_4768 skip
13841 17:01:17.964643 arm64_za-ptrace_Set_VL_4784 pass
13842 17:01:17.964784 arm64_za-ptrace_Disabled_ZA_for_VL_4784 skip
13843 17:01:17.964964 arm64_za-ptrace_Get_and_set_data_for_VL_4784 skip
13844 17:01:17.965099 arm64_za-ptrace_Set_VL_4800 pass
13845 17:01:17.965241 arm64_za-ptrace_Disabled_ZA_for_VL_4800 skip
13846 17:01:17.965381 arm64_za-ptrace_Get_and_set_data_for_VL_4800 skip
13847 17:01:17.965522 arm64_za-ptrace_Set_VL_4816 pass
13848 17:01:17.965694 arm64_za-ptrace_Disabled_ZA_for_VL_4816 skip
13849 17:01:17.965877 arm64_za-ptrace_Get_and_set_data_for_VL_4816 skip
13850 17:01:17.966125 arm64_za-ptrace_Set_VL_4832 pass
13851 17:01:17.966319 arm64_za-ptrace_Disabled_ZA_for_VL_4832 skip
13852 17:01:17.966486 arm64_za-ptrace_Get_and_set_data_for_VL_4832 skip
13853 17:01:17.966613 arm64_za-ptrace_Set_VL_4848 pass
13854 17:01:17.966741 arm64_za-ptrace_Disabled_ZA_for_VL_4848 skip
13855 17:01:17.966871 arm64_za-ptrace_Get_and_set_data_for_VL_4848 skip
13856 17:01:17.966998 arm64_za-ptrace_Set_VL_4864 pass
13857 17:01:17.967142 arm64_za-ptrace_Disabled_ZA_for_VL_4864 skip
13858 17:01:17.967290 arm64_za-ptrace_Get_and_set_data_for_VL_4864 skip
13859 17:01:17.967469 arm64_za-ptrace_Set_VL_4880 pass
13860 17:01:17.967634 arm64_za-ptrace_Disabled_ZA_for_VL_4880 skip
13861 17:01:17.967761 arm64_za-ptrace_Get_and_set_data_for_VL_4880 skip
13862 17:01:17.967884 arm64_za-ptrace_Set_VL_4896 pass
13863 17:01:17.968004 arm64_za-ptrace_Disabled_ZA_for_VL_4896 skip
13864 17:01:17.968122 arm64_za-ptrace_Get_and_set_data_for_VL_4896 skip
13865 17:01:17.968243 arm64_za-ptrace_Set_VL_4912 pass
13866 17:01:17.968358 arm64_za-ptrace_Disabled_ZA_for_VL_4912 skip
13867 17:01:17.968480 arm64_za-ptrace_Get_and_set_data_for_VL_4912 skip
13868 17:01:17.968598 arm64_za-ptrace_Set_VL_4928 pass
13869 17:01:17.968714 arm64_za-ptrace_Disabled_ZA_for_VL_4928 skip
13870 17:01:17.968835 arm64_za-ptrace_Get_and_set_data_for_VL_4928 skip
13871 17:01:17.968961 arm64_za-ptrace_Set_VL_4944 pass
13872 17:01:17.969078 arm64_za-ptrace_Disabled_ZA_for_VL_4944 skip
13873 17:01:17.969228 arm64_za-ptrace_Get_and_set_data_for_VL_4944 skip
13874 17:01:17.969355 arm64_za-ptrace_Set_VL_4960 pass
13875 17:01:17.969472 arm64_za-ptrace_Disabled_ZA_for_VL_4960 skip
13876 17:01:17.969593 arm64_za-ptrace_Get_and_set_data_for_VL_4960 skip
13877 17:01:17.969734 arm64_za-ptrace_Set_VL_4976 pass
13878 17:01:17.969853 arm64_za-ptrace_Disabled_ZA_for_VL_4976 skip
13879 17:01:17.969974 arm64_za-ptrace_Get_and_set_data_for_VL_4976 skip
13880 17:01:17.970091 arm64_za-ptrace_Set_VL_4992 pass
13881 17:01:17.970212 arm64_za-ptrace_Disabled_ZA_for_VL_4992 skip
13882 17:01:17.970333 arm64_za-ptrace_Get_and_set_data_for_VL_4992 skip
13883 17:01:17.970662 arm64_za-ptrace_Set_VL_5008 pass
13884 17:01:17.970771 arm64_za-ptrace_Disabled_ZA_for_VL_5008 skip
13885 17:01:17.970861 arm64_za-ptrace_Get_and_set_data_for_VL_5008 skip
13886 17:01:17.970947 arm64_za-ptrace_Set_VL_5024 pass
13887 17:01:17.971034 arm64_za-ptrace_Disabled_ZA_for_VL_5024 skip
13888 17:01:17.971120 arm64_za-ptrace_Get_and_set_data_for_VL_5024 skip
13889 17:01:17.971206 arm64_za-ptrace_Set_VL_5040 pass
13890 17:01:17.971291 arm64_za-ptrace_Disabled_ZA_for_VL_5040 skip
13891 17:01:17.971377 arm64_za-ptrace_Get_and_set_data_for_VL_5040 skip
13892 17:01:17.971463 arm64_za-ptrace_Set_VL_5056 pass
13893 17:01:17.971548 arm64_za-ptrace_Disabled_ZA_for_VL_5056 skip
13894 17:01:17.971633 arm64_za-ptrace_Get_and_set_data_for_VL_5056 skip
13895 17:01:17.971718 arm64_za-ptrace_Set_VL_5072 pass
13896 17:01:17.971804 arm64_za-ptrace_Disabled_ZA_for_VL_5072 skip
13897 17:01:17.971890 arm64_za-ptrace_Get_and_set_data_for_VL_5072 skip
13898 17:01:17.971976 arm64_za-ptrace_Set_VL_5088 pass
13899 17:01:17.972078 arm64_za-ptrace_Disabled_ZA_for_VL_5088 skip
13900 17:01:17.972167 arm64_za-ptrace_Get_and_set_data_for_VL_5088 skip
13901 17:01:17.972253 arm64_za-ptrace_Set_VL_5104 pass
13902 17:01:17.972339 arm64_za-ptrace_Disabled_ZA_for_VL_5104 skip
13903 17:01:17.972424 arm64_za-ptrace_Get_and_set_data_for_VL_5104 skip
13904 17:01:17.972509 arm64_za-ptrace_Set_VL_5120 pass
13905 17:01:17.975565 arm64_za-ptrace_Disabled_ZA_for_VL_5120 skip
13906 17:01:17.975937 arm64_za-ptrace_Get_and_set_data_for_VL_5120 skip
13907 17:01:17.976137 arm64_za-ptrace_Set_VL_5136 pass
13908 17:01:17.976305 arm64_za-ptrace_Disabled_ZA_for_VL_5136 skip
13909 17:01:17.976514 arm64_za-ptrace_Get_and_set_data_for_VL_5136 skip
13910 17:01:17.976689 arm64_za-ptrace_Set_VL_5152 pass
13911 17:01:17.976847 arm64_za-ptrace_Disabled_ZA_for_VL_5152 skip
13912 17:01:17.976996 arm64_za-ptrace_Get_and_set_data_for_VL_5152 skip
13913 17:01:17.977143 arm64_za-ptrace_Set_VL_5168 pass
13914 17:01:17.977282 arm64_za-ptrace_Disabled_ZA_for_VL_5168 skip
13915 17:01:17.977401 arm64_za-ptrace_Get_and_set_data_for_VL_5168 skip
13916 17:01:17.977522 arm64_za-ptrace_Set_VL_5184 pass
13917 17:01:17.977634 arm64_za-ptrace_Disabled_ZA_for_VL_5184 skip
13918 17:01:17.977792 arm64_za-ptrace_Get_and_set_data_for_VL_5184 skip
13919 17:01:17.977902 arm64_za-ptrace_Set_VL_5200 pass
13920 17:01:17.978005 arm64_za-ptrace_Disabled_ZA_for_VL_5200 skip
13921 17:01:17.978098 arm64_za-ptrace_Get_and_set_data_for_VL_5200 skip
13922 17:01:17.978199 arm64_za-ptrace_Set_VL_5216 pass
13923 17:01:17.978279 arm64_za-ptrace_Disabled_ZA_for_VL_5216 skip
13924 17:01:17.978357 arm64_za-ptrace_Get_and_set_data_for_VL_5216 skip
13925 17:01:17.978434 arm64_za-ptrace_Set_VL_5232 pass
13926 17:01:17.978510 arm64_za-ptrace_Disabled_ZA_for_VL_5232 skip
13927 17:01:17.978584 arm64_za-ptrace_Get_and_set_data_for_VL_5232 skip
13928 17:01:17.978659 arm64_za-ptrace_Set_VL_5248 pass
13929 17:01:17.978734 arm64_za-ptrace_Disabled_ZA_for_VL_5248 skip
13930 17:01:17.978809 arm64_za-ptrace_Get_and_set_data_for_VL_5248 skip
13931 17:01:17.978905 arm64_za-ptrace_Set_VL_5264 pass
13932 17:01:17.978985 arm64_za-ptrace_Disabled_ZA_for_VL_5264 skip
13933 17:01:17.979059 arm64_za-ptrace_Get_and_set_data_for_VL_5264 skip
13934 17:01:17.979132 arm64_za-ptrace_Set_VL_5280 pass
13935 17:01:17.979208 arm64_za-ptrace_Disabled_ZA_for_VL_5280 skip
13936 17:01:17.979522 arm64_za-ptrace_Get_and_set_data_for_VL_5280 skip
13937 17:01:17.979603 arm64_za-ptrace_Set_VL_5296 pass
13938 17:01:17.979666 arm64_za-ptrace_Disabled_ZA_for_VL_5296 skip
13939 17:01:17.979743 arm64_za-ptrace_Get_and_set_data_for_VL_5296 skip
13940 17:01:17.979808 arm64_za-ptrace_Set_VL_5312 pass
13941 17:01:17.979870 arm64_za-ptrace_Disabled_ZA_for_VL_5312 skip
13942 17:01:17.979931 arm64_za-ptrace_Get_and_set_data_for_VL_5312 skip
13943 17:01:17.983583 arm64_za-ptrace_Set_VL_5328 pass
13944 17:01:17.983904 arm64_za-ptrace_Disabled_ZA_for_VL_5328 skip
13945 17:01:17.983997 arm64_za-ptrace_Get_and_set_data_for_VL_5328 skip
13946 17:01:17.984075 arm64_za-ptrace_Set_VL_5344 pass
13947 17:01:17.984169 arm64_za-ptrace_Disabled_ZA_for_VL_5344 skip
13948 17:01:17.984248 arm64_za-ptrace_Get_and_set_data_for_VL_5344 skip
13949 17:01:17.984338 arm64_za-ptrace_Set_VL_5360 pass
13950 17:01:17.984416 arm64_za-ptrace_Disabled_ZA_for_VL_5360 skip
13951 17:01:17.984505 arm64_za-ptrace_Get_and_set_data_for_VL_5360 skip
13952 17:01:17.984587 arm64_za-ptrace_Set_VL_5376 pass
13953 17:01:17.984680 arm64_za-ptrace_Disabled_ZA_for_VL_5376 skip
13954 17:01:17.984781 arm64_za-ptrace_Get_and_set_data_for_VL_5376 skip
13955 17:01:17.984886 arm64_za-ptrace_Set_VL_5392 pass
13956 17:01:17.984986 arm64_za-ptrace_Disabled_ZA_for_VL_5392 skip
13957 17:01:17.985079 arm64_za-ptrace_Get_and_set_data_for_VL_5392 skip
13958 17:01:17.985167 arm64_za-ptrace_Set_VL_5408 pass
13959 17:01:17.985255 arm64_za-ptrace_Disabled_ZA_for_VL_5408 skip
13960 17:01:17.985551 arm64_za-ptrace_Get_and_set_data_for_VL_5408 skip
13961 17:01:17.985703 arm64_za-ptrace_Set_VL_5424 pass
13962 17:01:17.985853 arm64_za-ptrace_Disabled_ZA_for_VL_5424 skip
13963 17:01:17.985988 arm64_za-ptrace_Get_and_set_data_for_VL_5424 skip
13964 17:01:17.986141 arm64_za-ptrace_Set_VL_5440 pass
13965 17:01:17.986310 arm64_za-ptrace_Disabled_ZA_for_VL_5440 skip
13966 17:01:17.986475 arm64_za-ptrace_Get_and_set_data_for_VL_5440 skip
13967 17:01:17.986684 arm64_za-ptrace_Set_VL_5456 pass
13968 17:01:17.986862 arm64_za-ptrace_Disabled_ZA_for_VL_5456 skip
13969 17:01:17.986989 arm64_za-ptrace_Get_and_set_data_for_VL_5456 skip
13970 17:01:17.987137 arm64_za-ptrace_Set_VL_5472 pass
13971 17:01:17.987301 arm64_za-ptrace_Disabled_ZA_for_VL_5472 skip
13972 17:01:17.987424 arm64_za-ptrace_Get_and_set_data_for_VL_5472 skip
13973 17:01:17.987518 arm64_za-ptrace_Set_VL_5488 pass
13974 17:01:17.987603 arm64_za-ptrace_Disabled_ZA_for_VL_5488 skip
13975 17:01:17.987690 arm64_za-ptrace_Get_and_set_data_for_VL_5488 skip
13976 17:01:17.987776 arm64_za-ptrace_Set_VL_5504 pass
13977 17:01:17.987883 arm64_za-ptrace_Disabled_ZA_for_VL_5504 skip
13978 17:01:17.991591 arm64_za-ptrace_Get_and_set_data_for_VL_5504 skip
13979 17:01:17.991944 arm64_za-ptrace_Set_VL_5520 pass
13980 17:01:17.992051 arm64_za-ptrace_Disabled_ZA_for_VL_5520 skip
13981 17:01:17.992141 arm64_za-ptrace_Get_and_set_data_for_VL_5520 skip
13982 17:01:17.992245 arm64_za-ptrace_Set_VL_5536 pass
13983 17:01:17.992333 arm64_za-ptrace_Disabled_ZA_for_VL_5536 skip
13984 17:01:17.992419 arm64_za-ptrace_Get_and_set_data_for_VL_5536 skip
13985 17:01:17.992521 arm64_za-ptrace_Set_VL_5552 pass
13986 17:01:17.992609 arm64_za-ptrace_Disabled_ZA_for_VL_5552 skip
13987 17:01:17.992709 arm64_za-ptrace_Get_and_set_data_for_VL_5552 skip
13988 17:01:17.992798 arm64_za-ptrace_Set_VL_5568 pass
13989 17:01:17.992904 arm64_za-ptrace_Disabled_ZA_for_VL_5568 skip
13990 17:01:17.992989 arm64_za-ptrace_Get_and_set_data_for_VL_5568 skip
13991 17:01:17.993087 arm64_za-ptrace_Set_VL_5584 pass
13992 17:01:17.993167 arm64_za-ptrace_Disabled_ZA_for_VL_5584 skip
13993 17:01:17.993258 arm64_za-ptrace_Get_and_set_data_for_VL_5584 skip
13994 17:01:17.993349 arm64_za-ptrace_Set_VL_5600 pass
13995 17:01:17.993440 arm64_za-ptrace_Disabled_ZA_for_VL_5600 skip
13996 17:01:17.993535 arm64_za-ptrace_Get_and_set_data_for_VL_5600 skip
13997 17:01:17.993638 arm64_za-ptrace_Set_VL_5616 pass
13998 17:01:17.993749 arm64_za-ptrace_Disabled_ZA_for_VL_5616 skip
13999 17:01:17.993850 arm64_za-ptrace_Get_and_set_data_for_VL_5616 skip
14000 17:01:17.994147 arm64_za-ptrace_Set_VL_5632 pass
14001 17:01:17.994251 arm64_za-ptrace_Disabled_ZA_for_VL_5632 skip
14002 17:01:17.994354 arm64_za-ptrace_Get_and_set_data_for_VL_5632 skip
14003 17:01:17.994443 arm64_za-ptrace_Set_VL_5648 pass
14004 17:01:18.012254 arm64_za-ptrace_Disabled_ZA_for_VL_5648 skip
14005 17:01:18.012498 arm64_za-ptrace_Get_and_set_data_for_VL_5648 skip
14006 17:01:18.012809 arm64_za-ptrace_Set_VL_5664 pass
14007 17:01:18.012921 arm64_za-ptrace_Disabled_ZA_for_VL_5664 skip
14008 17:01:18.013007 arm64_za-ptrace_Get_and_set_data_for_VL_5664 skip
14009 17:01:18.013084 arm64_za-ptrace_Set_VL_5680 pass
14010 17:01:18.013158 arm64_za-ptrace_Disabled_ZA_for_VL_5680 skip
14011 17:01:18.013231 arm64_za-ptrace_Get_and_set_data_for_VL_5680 skip
14012 17:01:18.013319 arm64_za-ptrace_Set_VL_5696 pass
14013 17:01:18.013395 arm64_za-ptrace_Disabled_ZA_for_VL_5696 skip
14014 17:01:18.013469 arm64_za-ptrace_Get_and_set_data_for_VL_5696 skip
14015 17:01:18.013541 arm64_za-ptrace_Set_VL_5712 pass
14016 17:01:18.013629 arm64_za-ptrace_Disabled_ZA_for_VL_5712 skip
14017 17:01:18.013715 arm64_za-ptrace_Get_and_set_data_for_VL_5712 skip
14018 17:01:18.013805 arm64_za-ptrace_Set_VL_5728 pass
14019 17:01:18.013896 arm64_za-ptrace_Disabled_ZA_for_VL_5728 skip
14020 17:01:18.013991 arm64_za-ptrace_Get_and_set_data_for_VL_5728 skip
14021 17:01:18.014084 arm64_za-ptrace_Set_VL_5744 pass
14022 17:01:18.014177 arm64_za-ptrace_Disabled_ZA_for_VL_5744 skip
14023 17:01:18.014638 arm64_za-ptrace_Get_and_set_data_for_VL_5744 skip
14024 17:01:18.014750 arm64_za-ptrace_Set_VL_5760 pass
14025 17:01:18.014837 arm64_za-ptrace_Disabled_ZA_for_VL_5760 skip
14026 17:01:18.014941 arm64_za-ptrace_Get_and_set_data_for_VL_5760 skip
14027 17:01:18.015033 arm64_za-ptrace_Set_VL_5776 pass
14028 17:01:18.015134 arm64_za-ptrace_Disabled_ZA_for_VL_5776 skip
14029 17:01:18.015222 arm64_za-ptrace_Get_and_set_data_for_VL_5776 skip
14030 17:01:18.015306 arm64_za-ptrace_Set_VL_5792 pass
14031 17:01:18.015406 arm64_za-ptrace_Disabled_ZA_for_VL_5792 skip
14032 17:01:18.015492 arm64_za-ptrace_Get_and_set_data_for_VL_5792 skip
14033 17:01:18.015576 arm64_za-ptrace_Set_VL_5808 pass
14034 17:01:18.019586 arm64_za-ptrace_Disabled_ZA_for_VL_5808 skip
14035 17:01:18.020168 arm64_za-ptrace_Get_and_set_data_for_VL_5808 skip
14036 17:01:18.020352 arm64_za-ptrace_Set_VL_5824 pass
14037 17:01:18.020524 arm64_za-ptrace_Disabled_ZA_for_VL_5824 skip
14038 17:01:18.020671 arm64_za-ptrace_Get_and_set_data_for_VL_5824 skip
14039 17:01:18.020815 arm64_za-ptrace_Set_VL_5840 pass
14040 17:01:18.021043 arm64_za-ptrace_Disabled_ZA_for_VL_5840 skip
14041 17:01:18.021204 arm64_za-ptrace_Get_and_set_data_for_VL_5840 skip
14042 17:01:18.021350 arm64_za-ptrace_Set_VL_5856 pass
14043 17:01:18.021493 arm64_za-ptrace_Disabled_ZA_for_VL_5856 skip
14044 17:01:18.021635 arm64_za-ptrace_Get_and_set_data_for_VL_5856 skip
14045 17:01:18.021792 arm64_za-ptrace_Set_VL_5872 pass
14046 17:01:18.021933 arm64_za-ptrace_Disabled_ZA_for_VL_5872 skip
14047 17:01:18.022075 arm64_za-ptrace_Get_and_set_data_for_VL_5872 skip
14048 17:01:18.022258 arm64_za-ptrace_Set_VL_5888 pass
14049 17:01:18.022393 arm64_za-ptrace_Disabled_ZA_for_VL_5888 skip
14050 17:01:18.022535 arm64_za-ptrace_Get_and_set_data_for_VL_5888 skip
14051 17:01:18.022677 arm64_za-ptrace_Set_VL_5904 pass
14052 17:01:18.022818 arm64_za-ptrace_Disabled_ZA_for_VL_5904 skip
14053 17:01:18.022961 arm64_za-ptrace_Get_and_set_data_for_VL_5904 skip
14054 17:01:18.023102 arm64_za-ptrace_Set_VL_5920 pass
14055 17:01:18.023241 arm64_za-ptrace_Disabled_ZA_for_VL_5920 skip
14056 17:01:18.023381 arm64_za-ptrace_Get_and_set_data_for_VL_5920 skip
14057 17:01:18.023523 arm64_za-ptrace_Set_VL_5936 pass
14058 17:01:18.023663 arm64_za-ptrace_Disabled_ZA_for_VL_5936 skip
14059 17:01:18.023866 arm64_za-ptrace_Get_and_set_data_for_VL_5936 skip
14060 17:01:18.024004 arm64_za-ptrace_Set_VL_5952 pass
14061 17:01:18.024146 arm64_za-ptrace_Disabled_ZA_for_VL_5952 skip
14062 17:01:18.024287 arm64_za-ptrace_Get_and_set_data_for_VL_5952 skip
14063 17:01:18.024429 arm64_za-ptrace_Set_VL_5968 pass
14064 17:01:18.024570 arm64_za-ptrace_Disabled_ZA_for_VL_5968 skip
14065 17:01:18.024711 arm64_za-ptrace_Get_and_set_data_for_VL_5968 skip
14066 17:01:18.024852 arm64_za-ptrace_Set_VL_5984 pass
14067 17:01:18.025004 arm64_za-ptrace_Disabled_ZA_for_VL_5984 skip
14068 17:01:18.025142 arm64_za-ptrace_Get_and_set_data_for_VL_5984 skip
14069 17:01:18.025284 arm64_za-ptrace_Set_VL_6000 pass
14070 17:01:18.027656 arm64_za-ptrace_Disabled_ZA_for_VL_6000 skip
14071 17:01:18.027788 arm64_za-ptrace_Get_and_set_data_for_VL_6000 skip
14072 17:01:18.028077 arm64_za-ptrace_Set_VL_6016 pass
14073 17:01:18.028185 arm64_za-ptrace_Disabled_ZA_for_VL_6016 skip
14074 17:01:18.028271 arm64_za-ptrace_Get_and_set_data_for_VL_6016 skip
14075 17:01:18.028356 arm64_za-ptrace_Set_VL_6032 pass
14076 17:01:18.028455 arm64_za-ptrace_Disabled_ZA_for_VL_6032 skip
14077 17:01:18.028542 arm64_za-ptrace_Get_and_set_data_for_VL_6032 skip
14078 17:01:18.028627 arm64_za-ptrace_Set_VL_6048 pass
14079 17:01:18.028729 arm64_za-ptrace_Disabled_ZA_for_VL_6048 skip
14080 17:01:18.028817 arm64_za-ptrace_Get_and_set_data_for_VL_6048 skip
14081 17:01:18.028924 arm64_za-ptrace_Set_VL_6064 pass
14082 17:01:18.029137 arm64_za-ptrace_Disabled_ZA_for_VL_6064 skip
14083 17:01:18.029244 arm64_za-ptrace_Get_and_set_data_for_VL_6064 skip
14084 17:01:18.029415 arm64_za-ptrace_Set_VL_6080 pass
14085 17:01:18.029490 arm64_za-ptrace_Disabled_ZA_for_VL_6080 skip
14086 17:01:18.029564 arm64_za-ptrace_Get_and_set_data_for_VL_6080 skip
14087 17:01:18.029661 arm64_za-ptrace_Set_VL_6096 pass
14088 17:01:18.029738 arm64_za-ptrace_Disabled_ZA_for_VL_6096 skip
14089 17:01:18.029811 arm64_za-ptrace_Get_and_set_data_for_VL_6096 skip
14090 17:01:18.029899 arm64_za-ptrace_Set_VL_6112 pass
14091 17:01:18.029976 arm64_za-ptrace_Disabled_ZA_for_VL_6112 skip
14092 17:01:18.030052 arm64_za-ptrace_Get_and_set_data_for_VL_6112 skip
14093 17:01:18.030126 arm64_za-ptrace_Set_VL_6128 pass
14094 17:01:18.030198 arm64_za-ptrace_Disabled_ZA_for_VL_6128 skip
14095 17:01:18.030287 arm64_za-ptrace_Get_and_set_data_for_VL_6128 skip
14096 17:01:18.030370 arm64_za-ptrace_Set_VL_6144 pass
14097 17:01:18.030454 arm64_za-ptrace_Disabled_ZA_for_VL_6144 skip
14098 17:01:18.030553 arm64_za-ptrace_Get_and_set_data_for_VL_6144 skip
14099 17:01:18.030640 arm64_za-ptrace_Set_VL_6160 pass
14100 17:01:18.030738 arm64_za-ptrace_Disabled_ZA_for_VL_6160 skip
14101 17:01:18.030824 arm64_za-ptrace_Get_and_set_data_for_VL_6160 skip
14102 17:01:18.030923 arm64_za-ptrace_Set_VL_6176 pass
14103 17:01:18.031023 arm64_za-ptrace_Disabled_ZA_for_VL_6176 skip
14104 17:01:18.031109 arm64_za-ptrace_Get_and_set_data_for_VL_6176 skip
14105 17:01:18.031207 arm64_za-ptrace_Set_VL_6192 pass
14106 17:01:18.031293 arm64_za-ptrace_Disabled_ZA_for_VL_6192 skip
14107 17:01:18.031391 arm64_za-ptrace_Get_and_set_data_for_VL_6192 skip
14108 17:01:18.031477 arm64_za-ptrace_Set_VL_6208 pass
14109 17:01:18.035626 arm64_za-ptrace_Disabled_ZA_for_VL_6208 skip
14110 17:01:18.036125 arm64_za-ptrace_Get_and_set_data_for_VL_6208 skip
14111 17:01:18.036232 arm64_za-ptrace_Set_VL_6224 pass
14112 17:01:18.036315 arm64_za-ptrace_Disabled_ZA_for_VL_6224 skip
14113 17:01:18.036395 arm64_za-ptrace_Get_and_set_data_for_VL_6224 skip
14114 17:01:18.036475 arm64_za-ptrace_Set_VL_6240 pass
14115 17:01:18.036756 arm64_za-ptrace_Disabled_ZA_for_VL_6240 skip
14116 17:01:18.036858 arm64_za-ptrace_Get_and_set_data_for_VL_6240 skip
14117 17:01:18.036945 arm64_za-ptrace_Set_VL_6256 pass
14118 17:01:18.037024 arm64_za-ptrace_Disabled_ZA_for_VL_6256 skip
14119 17:01:18.037104 arm64_za-ptrace_Get_and_set_data_for_VL_6256 skip
14120 17:01:18.037184 arm64_za-ptrace_Set_VL_6272 pass
14121 17:01:18.037261 arm64_za-ptrace_Disabled_ZA_for_VL_6272 skip
14122 17:01:18.037544 arm64_za-ptrace_Get_and_set_data_for_VL_6272 skip
14123 17:01:18.037645 arm64_za-ptrace_Set_VL_6288 pass
14124 17:01:18.037741 arm64_za-ptrace_Disabled_ZA_for_VL_6288 skip
14125 17:01:18.037825 arm64_za-ptrace_Get_and_set_data_for_VL_6288 skip
14126 17:01:18.037909 arm64_za-ptrace_Set_VL_6304 pass
14127 17:01:18.037996 arm64_za-ptrace_Disabled_ZA_for_VL_6304 skip
14128 17:01:18.038078 arm64_za-ptrace_Get_and_set_data_for_VL_6304 skip
14129 17:01:18.038178 arm64_za-ptrace_Set_VL_6320 pass
14130 17:01:18.038263 arm64_za-ptrace_Disabled_ZA_for_VL_6320 skip
14131 17:01:18.038347 arm64_za-ptrace_Get_and_set_data_for_VL_6320 skip
14132 17:01:18.038430 arm64_za-ptrace_Set_VL_6336 pass
14133 17:01:18.038513 arm64_za-ptrace_Disabled_ZA_for_VL_6336 skip
14134 17:01:18.038615 arm64_za-ptrace_Get_and_set_data_for_VL_6336 skip
14135 17:01:18.038703 arm64_za-ptrace_Set_VL_6352 pass
14136 17:01:18.038787 arm64_za-ptrace_Disabled_ZA_for_VL_6352 skip
14137 17:01:18.038886 arm64_za-ptrace_Get_and_set_data_for_VL_6352 skip
14138 17:01:18.038976 arm64_za-ptrace_Set_VL_6368 pass
14139 17:01:18.039069 arm64_za-ptrace_Disabled_ZA_for_VL_6368 skip
14140 17:01:18.039160 arm64_za-ptrace_Get_and_set_data_for_VL_6368 skip
14141 17:01:18.039246 arm64_za-ptrace_Set_VL_6384 pass
14142 17:01:18.039346 arm64_za-ptrace_Disabled_ZA_for_VL_6384 skip
14143 17:01:18.043617 arm64_za-ptrace_Get_and_set_data_for_VL_6384 skip
14144 17:01:18.044023 arm64_za-ptrace_Set_VL_6400 pass
14145 17:01:18.044128 arm64_za-ptrace_Disabled_ZA_for_VL_6400 skip
14146 17:01:18.044217 arm64_za-ptrace_Get_and_set_data_for_VL_6400 skip
14147 17:01:18.044301 arm64_za-ptrace_Set_VL_6416 pass
14148 17:01:18.044400 arm64_za-ptrace_Disabled_ZA_for_VL_6416 skip
14149 17:01:18.044487 arm64_za-ptrace_Get_and_set_data_for_VL_6416 skip
14150 17:01:18.044572 arm64_za-ptrace_Set_VL_6432 pass
14151 17:01:18.044656 arm64_za-ptrace_Disabled_ZA_for_VL_6432 skip
14152 17:01:18.044755 arm64_za-ptrace_Get_and_set_data_for_VL_6432 skip
14153 17:01:18.044841 arm64_za-ptrace_Set_VL_6448 pass
14154 17:01:18.044924 arm64_za-ptrace_Disabled_ZA_for_VL_6448 skip
14155 17:01:18.045007 arm64_za-ptrace_Get_and_set_data_for_VL_6448 skip
14156 17:01:18.045100 arm64_za-ptrace_Set_VL_6464 pass
14157 17:01:18.045178 arm64_za-ptrace_Disabled_ZA_for_VL_6464 skip
14158 17:01:18.045250 arm64_za-ptrace_Get_and_set_data_for_VL_6464 skip
14159 17:01:18.045336 arm64_za-ptrace_Set_VL_6480 pass
14160 17:01:18.045412 arm64_za-ptrace_Disabled_ZA_for_VL_6480 skip
14161 17:01:18.045485 arm64_za-ptrace_Get_and_set_data_for_VL_6480 skip
14162 17:01:18.045570 arm64_za-ptrace_Set_VL_6496 pass
14163 17:01:18.045654 arm64_za-ptrace_Disabled_ZA_for_VL_6496 skip
14164 17:01:18.045730 arm64_za-ptrace_Get_and_set_data_for_VL_6496 skip
14165 17:01:18.045819 arm64_za-ptrace_Set_VL_6512 pass
14166 17:01:18.045894 arm64_za-ptrace_Disabled_ZA_for_VL_6512 skip
14167 17:01:18.045982 arm64_za-ptrace_Get_and_set_data_for_VL_6512 skip
14168 17:01:18.046062 arm64_za-ptrace_Set_VL_6528 pass
14169 17:01:18.046160 arm64_za-ptrace_Disabled_ZA_for_VL_6528 skip
14170 17:01:18.046248 arm64_za-ptrace_Get_and_set_data_for_VL_6528 skip
14171 17:01:18.046348 arm64_za-ptrace_Set_VL_6544 pass
14172 17:01:18.046436 arm64_za-ptrace_Disabled_ZA_for_VL_6544 skip
14173 17:01:18.046533 arm64_za-ptrace_Get_and_set_data_for_VL_6544 skip
14174 17:01:18.046621 arm64_za-ptrace_Set_VL_6560 pass
14175 17:01:18.046720 arm64_za-ptrace_Disabled_ZA_for_VL_6560 skip
14176 17:01:18.046825 arm64_za-ptrace_Get_and_set_data_for_VL_6560 skip
14177 17:01:18.046912 arm64_za-ptrace_Set_VL_6576 pass
14178 17:01:18.046995 arm64_za-ptrace_Disabled_ZA_for_VL_6576 skip
14179 17:01:18.047094 arm64_za-ptrace_Get_and_set_data_for_VL_6576 skip
14180 17:01:18.047180 arm64_za-ptrace_Set_VL_6592 pass
14181 17:01:18.047263 arm64_za-ptrace_Disabled_ZA_for_VL_6592 skip
14182 17:01:18.047359 arm64_za-ptrace_Get_and_set_data_for_VL_6592 skip
14183 17:01:18.047445 arm64_za-ptrace_Set_VL_6608 pass
14184 17:01:18.047543 arm64_za-ptrace_Disabled_ZA_for_VL_6608 skip
14185 17:01:18.052010 arm64_za-ptrace_Get_and_set_data_for_VL_6608 skip
14186 17:01:18.052326 arm64_za-ptrace_Set_VL_6624 pass
14187 17:01:18.052545 arm64_za-ptrace_Disabled_ZA_for_VL_6624 skip
14188 17:01:18.052741 arm64_za-ptrace_Get_and_set_data_for_VL_6624 skip
14189 17:01:18.052869 arm64_za-ptrace_Set_VL_6640 pass
14190 17:01:18.053053 arm64_za-ptrace_Disabled_ZA_for_VL_6640 skip
14191 17:01:18.053203 arm64_za-ptrace_Get_and_set_data_for_VL_6640 skip
14192 17:01:18.053357 arm64_za-ptrace_Set_VL_6656 pass
14193 17:01:18.053490 arm64_za-ptrace_Disabled_ZA_for_VL_6656 skip
14194 17:01:18.053605 arm64_za-ptrace_Get_and_set_data_for_VL_6656 skip
14195 17:01:18.053796 arm64_za-ptrace_Set_VL_6672 pass
14196 17:01:18.054031 arm64_za-ptrace_Disabled_ZA_for_VL_6672 skip
14197 17:01:18.067236 arm64_za-ptrace_Get_and_set_data_for_VL_6672 skip
14198 17:01:18.067481 arm64_za-ptrace_Set_VL_6688 pass
14199 17:01:18.067779 arm64_za-ptrace_Disabled_ZA_for_VL_6688 skip
14200 17:01:18.067881 arm64_za-ptrace_Get_and_set_data_for_VL_6688 skip
14201 17:01:18.067974 arm64_za-ptrace_Set_VL_6704 pass
14202 17:01:18.068066 arm64_za-ptrace_Disabled_ZA_for_VL_6704 skip
14203 17:01:18.068173 arm64_za-ptrace_Get_and_set_data_for_VL_6704 skip
14204 17:01:18.068265 arm64_za-ptrace_Set_VL_6720 pass
14205 17:01:18.068349 arm64_za-ptrace_Disabled_ZA_for_VL_6720 skip
14206 17:01:18.068449 arm64_za-ptrace_Get_and_set_data_for_VL_6720 skip
14207 17:01:18.068536 arm64_za-ptrace_Set_VL_6736 pass
14208 17:01:18.068620 arm64_za-ptrace_Disabled_ZA_for_VL_6736 skip
14209 17:01:18.068720 arm64_za-ptrace_Get_and_set_data_for_VL_6736 skip
14210 17:01:18.068807 arm64_za-ptrace_Set_VL_6752 pass
14211 17:01:18.068891 arm64_za-ptrace_Disabled_ZA_for_VL_6752 skip
14212 17:01:18.068994 arm64_za-ptrace_Get_and_set_data_for_VL_6752 skip
14213 17:01:18.069080 arm64_za-ptrace_Set_VL_6768 pass
14214 17:01:18.069156 arm64_za-ptrace_Disabled_ZA_for_VL_6768 skip
14215 17:01:18.069243 arm64_za-ptrace_Get_and_set_data_for_VL_6768 skip
14216 17:01:18.069317 arm64_za-ptrace_Set_VL_6784 pass
14217 17:01:18.069402 arm64_za-ptrace_Disabled_ZA_for_VL_6784 skip
14218 17:01:18.069488 arm64_za-ptrace_Get_and_set_data_for_VL_6784 skip
14219 17:01:18.069573 arm64_za-ptrace_Set_VL_6800 pass
14220 17:01:18.069667 arm64_za-ptrace_Disabled_ZA_for_VL_6800 skip
14221 17:01:18.070134 arm64_za-ptrace_Get_and_set_data_for_VL_6800 skip
14222 17:01:18.070232 arm64_za-ptrace_Set_VL_6816 pass
14223 17:01:18.070306 arm64_za-ptrace_Disabled_ZA_for_VL_6816 skip
14224 17:01:18.070379 arm64_za-ptrace_Get_and_set_data_for_VL_6816 skip
14225 17:01:18.070468 arm64_za-ptrace_Set_VL_6832 pass
14226 17:01:18.070545 arm64_za-ptrace_Disabled_ZA_for_VL_6832 skip
14227 17:01:18.070631 arm64_za-ptrace_Get_and_set_data_for_VL_6832 skip
14228 17:01:18.070722 arm64_za-ptrace_Set_VL_6848 pass
14229 17:01:18.070803 arm64_za-ptrace_Disabled_ZA_for_VL_6848 skip
14230 17:01:18.070898 arm64_za-ptrace_Get_and_set_data_for_VL_6848 skip
14231 17:01:18.070982 arm64_za-ptrace_Set_VL_6864 pass
14232 17:01:18.071060 arm64_za-ptrace_Disabled_ZA_for_VL_6864 skip
14233 17:01:18.071159 arm64_za-ptrace_Get_and_set_data_for_VL_6864 skip
14234 17:01:18.071259 arm64_za-ptrace_Set_VL_6880 pass
14235 17:01:18.071346 arm64_za-ptrace_Disabled_ZA_for_VL_6880 skip
14236 17:01:18.071441 arm64_za-ptrace_Get_and_set_data_for_VL_6880 skip
14237 17:01:18.071522 arm64_za-ptrace_Set_VL_6896 pass
14238 17:01:18.075711 arm64_za-ptrace_Disabled_ZA_for_VL_6896 skip
14239 17:01:18.076116 arm64_za-ptrace_Get_and_set_data_for_VL_6896 skip
14240 17:01:18.076223 arm64_za-ptrace_Set_VL_6912 pass
14241 17:01:18.076313 arm64_za-ptrace_Disabled_ZA_for_VL_6912 skip
14242 17:01:18.076402 arm64_za-ptrace_Get_and_set_data_for_VL_6912 skip
14243 17:01:18.076503 arm64_za-ptrace_Set_VL_6928 pass
14244 17:01:18.076590 arm64_za-ptrace_Disabled_ZA_for_VL_6928 skip
14245 17:01:18.076674 arm64_za-ptrace_Get_and_set_data_for_VL_6928 skip
14246 17:01:18.076773 arm64_za-ptrace_Set_VL_6944 pass
14247 17:01:18.076860 arm64_za-ptrace_Disabled_ZA_for_VL_6944 skip
14248 17:01:18.076957 arm64_za-ptrace_Get_and_set_data_for_VL_6944 skip
14249 17:01:18.077053 arm64_za-ptrace_Set_VL_6960 pass
14250 17:01:18.077412 arm64_za-ptrace_Disabled_ZA_for_VL_6960 skip
14251 17:01:18.077663 arm64_za-ptrace_Get_and_set_data_for_VL_6960 skip
14252 17:01:18.077900 arm64_za-ptrace_Set_VL_6976 pass
14253 17:01:18.078140 arm64_za-ptrace_Disabled_ZA_for_VL_6976 skip
14254 17:01:18.078337 arm64_za-ptrace_Get_and_set_data_for_VL_6976 skip
14255 17:01:18.078504 arm64_za-ptrace_Set_VL_6992 pass
14256 17:01:18.078660 arm64_za-ptrace_Disabled_ZA_for_VL_6992 skip
14257 17:01:18.078824 arm64_za-ptrace_Get_and_set_data_for_VL_6992 skip
14258 17:01:18.078965 arm64_za-ptrace_Set_VL_7008 pass
14259 17:01:18.079113 arm64_za-ptrace_Disabled_ZA_for_VL_7008 skip
14260 17:01:18.079582 arm64_za-ptrace_Get_and_set_data_for_VL_7008 skip
14261 17:01:18.079743 arm64_za-ptrace_Set_VL_7024 pass
14262 17:01:18.079866 arm64_za-ptrace_Disabled_ZA_for_VL_7024 skip
14263 17:01:18.079982 arm64_za-ptrace_Get_and_set_data_for_VL_7024 skip
14264 17:01:18.080099 arm64_za-ptrace_Set_VL_7040 pass
14265 17:01:18.080214 arm64_za-ptrace_Disabled_ZA_for_VL_7040 skip
14266 17:01:18.080328 arm64_za-ptrace_Get_and_set_data_for_VL_7040 skip
14267 17:01:18.080443 arm64_za-ptrace_Set_VL_7056 pass
14268 17:01:18.080556 arm64_za-ptrace_Disabled_ZA_for_VL_7056 skip
14269 17:01:18.080671 arm64_za-ptrace_Get_and_set_data_for_VL_7056 skip
14270 17:01:18.080785 arm64_za-ptrace_Set_VL_7072 pass
14271 17:01:18.083696 arm64_za-ptrace_Disabled_ZA_for_VL_7072 skip
14272 17:01:18.084184 arm64_za-ptrace_Get_and_set_data_for_VL_7072 skip
14273 17:01:18.084385 arm64_za-ptrace_Set_VL_7088 pass
14274 17:01:18.084556 arm64_za-ptrace_Disabled_ZA_for_VL_7088 skip
14275 17:01:18.084701 arm64_za-ptrace_Get_and_set_data_for_VL_7088 skip
14276 17:01:18.084843 arm64_za-ptrace_Set_VL_7104 pass
14277 17:01:18.085129 arm64_za-ptrace_Disabled_ZA_for_VL_7104 skip
14278 17:01:18.085291 arm64_za-ptrace_Get_and_set_data_for_VL_7104 skip
14279 17:01:18.085530 arm64_za-ptrace_Set_VL_7120 pass
14280 17:01:18.085716 arm64_za-ptrace_Disabled_ZA_for_VL_7120 skip
14281 17:01:18.085863 arm64_za-ptrace_Get_and_set_data_for_VL_7120 skip
14282 17:01:18.086014 arm64_za-ptrace_Set_VL_7136 pass
14283 17:01:18.086204 arm64_za-ptrace_Disabled_ZA_for_VL_7136 skip
14284 17:01:18.086374 arm64_za-ptrace_Get_and_set_data_for_VL_7136 skip
14285 17:01:18.086587 arm64_za-ptrace_Set_VL_7152 pass
14286 17:01:18.086773 arm64_za-ptrace_Disabled_ZA_for_VL_7152 skip
14287 17:01:18.086958 arm64_za-ptrace_Get_and_set_data_for_VL_7152 skip
14288 17:01:18.087131 arm64_za-ptrace_Set_VL_7168 pass
14289 17:01:18.087322 arm64_za-ptrace_Disabled_ZA_for_VL_7168 skip
14290 17:01:18.087512 arm64_za-ptrace_Get_and_set_data_for_VL_7168 skip
14291 17:01:18.087673 arm64_za-ptrace_Set_VL_7184 pass
14292 17:01:18.087807 arm64_za-ptrace_Disabled_ZA_for_VL_7184 skip
14293 17:01:18.087925 arm64_za-ptrace_Get_and_set_data_for_VL_7184 skip
14294 17:01:18.088037 arm64_za-ptrace_Set_VL_7200 pass
14295 17:01:18.088149 arm64_za-ptrace_Disabled_ZA_for_VL_7200 skip
14296 17:01:18.088261 arm64_za-ptrace_Get_and_set_data_for_VL_7200 skip
14297 17:01:18.088403 arm64_za-ptrace_Set_VL_7216 pass
14298 17:01:18.088525 arm64_za-ptrace_Disabled_ZA_for_VL_7216 skip
14299 17:01:18.088641 arm64_za-ptrace_Get_and_set_data_for_VL_7216 skip
14300 17:01:18.088754 arm64_za-ptrace_Set_VL_7232 pass
14301 17:01:18.088867 arm64_za-ptrace_Disabled_ZA_for_VL_7232 skip
14302 17:01:18.089034 arm64_za-ptrace_Get_and_set_data_for_VL_7232 skip
14303 17:01:18.089164 arm64_za-ptrace_Set_VL_7248 pass
14304 17:01:18.089292 arm64_za-ptrace_Disabled_ZA_for_VL_7248 skip
14305 17:01:18.089408 arm64_za-ptrace_Get_and_set_data_for_VL_7248 skip
14306 17:01:18.091598 arm64_za-ptrace_Set_VL_7264 pass
14307 17:01:18.092058 arm64_za-ptrace_Disabled_ZA_for_VL_7264 skip
14308 17:01:18.092238 arm64_za-ptrace_Get_and_set_data_for_VL_7264 skip
14309 17:01:18.092411 arm64_za-ptrace_Set_VL_7280 pass
14310 17:01:18.092557 arm64_za-ptrace_Disabled_ZA_for_VL_7280 skip
14311 17:01:18.092738 arm64_za-ptrace_Get_and_set_data_for_VL_7280 skip
14312 17:01:18.092876 arm64_za-ptrace_Set_VL_7296 pass
14313 17:01:18.093024 arm64_za-ptrace_Disabled_ZA_for_VL_7296 skip
14314 17:01:18.093167 arm64_za-ptrace_Get_and_set_data_for_VL_7296 skip
14315 17:01:18.093309 arm64_za-ptrace_Set_VL_7312 pass
14316 17:01:18.093452 arm64_za-ptrace_Disabled_ZA_for_VL_7312 skip
14317 17:01:18.093595 arm64_za-ptrace_Get_and_set_data_for_VL_7312 skip
14318 17:01:18.093753 arm64_za-ptrace_Set_VL_7328 pass
14319 17:01:18.093898 arm64_za-ptrace_Disabled_ZA_for_VL_7328 skip
14320 17:01:18.094081 arm64_za-ptrace_Get_and_set_data_for_VL_7328 skip
14321 17:01:18.094217 arm64_za-ptrace_Set_VL_7344 pass
14322 17:01:18.094359 arm64_za-ptrace_Disabled_ZA_for_VL_7344 skip
14323 17:01:18.094503 arm64_za-ptrace_Get_and_set_data_for_VL_7344 skip
14324 17:01:18.094645 arm64_za-ptrace_Set_VL_7360 pass
14325 17:01:18.094788 arm64_za-ptrace_Disabled_ZA_for_VL_7360 skip
14326 17:01:18.094929 arm64_za-ptrace_Get_and_set_data_for_VL_7360 skip
14327 17:01:18.095075 arm64_za-ptrace_Set_VL_7376 pass
14328 17:01:18.095216 arm64_za-ptrace_Disabled_ZA_for_VL_7376 skip
14329 17:01:18.095364 arm64_za-ptrace_Get_and_set_data_for_VL_7376 skip
14330 17:01:18.095508 arm64_za-ptrace_Set_VL_7392 pass
14331 17:01:18.095649 arm64_za-ptrace_Disabled_ZA_for_VL_7392 skip
14332 17:01:18.095828 arm64_za-ptrace_Get_and_set_data_for_VL_7392 skip
14333 17:01:18.095964 arm64_za-ptrace_Set_VL_7408 pass
14334 17:01:18.096106 arm64_za-ptrace_Disabled_ZA_for_VL_7408 skip
14335 17:01:18.096247 arm64_za-ptrace_Get_and_set_data_for_VL_7408 skip
14336 17:01:18.096389 arm64_za-ptrace_Set_VL_7424 pass
14337 17:01:18.096531 arm64_za-ptrace_Disabled_ZA_for_VL_7424 skip
14338 17:01:18.096671 arm64_za-ptrace_Get_and_set_data_for_VL_7424 skip
14339 17:01:18.096813 arm64_za-ptrace_Set_VL_7440 pass
14340 17:01:18.096954 arm64_za-ptrace_Disabled_ZA_for_VL_7440 skip
14341 17:01:18.097097 arm64_za-ptrace_Get_and_set_data_for_VL_7440 skip
14342 17:01:18.097239 arm64_za-ptrace_Set_VL_7456 pass
14343 17:01:18.097381 arm64_za-ptrace_Disabled_ZA_for_VL_7456 skip
14344 17:01:18.099546 arm64_za-ptrace_Get_and_set_data_for_VL_7456 skip
14345 17:01:18.099875 arm64_za-ptrace_Set_VL_7472 pass
14346 17:01:18.100073 arm64_za-ptrace_Disabled_ZA_for_VL_7472 skip
14347 17:01:18.100322 arm64_za-ptrace_Get_and_set_data_for_VL_7472 skip
14348 17:01:18.100550 arm64_za-ptrace_Set_VL_7488 pass
14349 17:01:18.100749 arm64_za-ptrace_Disabled_ZA_for_VL_7488 skip
14350 17:01:18.100958 arm64_za-ptrace_Get_and_set_data_for_VL_7488 skip
14351 17:01:18.101172 arm64_za-ptrace_Set_VL_7504 pass
14352 17:01:18.101360 arm64_za-ptrace_Disabled_ZA_for_VL_7504 skip
14353 17:01:18.101523 arm64_za-ptrace_Get_and_set_data_for_VL_7504 skip
14354 17:01:18.101723 arm64_za-ptrace_Set_VL_7520 pass
14355 17:01:18.101863 arm64_za-ptrace_Disabled_ZA_for_VL_7520 skip
14356 17:01:18.102002 arm64_za-ptrace_Get_and_set_data_for_VL_7520 skip
14357 17:01:18.102166 arm64_za-ptrace_Set_VL_7536 pass
14358 17:01:18.102325 arm64_za-ptrace_Disabled_ZA_for_VL_7536 skip
14359 17:01:18.102483 arm64_za-ptrace_Get_and_set_data_for_VL_7536 skip
14360 17:01:18.102652 arm64_za-ptrace_Set_VL_7552 pass
14361 17:01:18.102858 arm64_za-ptrace_Disabled_ZA_for_VL_7552 skip
14362 17:01:18.103157 arm64_za-ptrace_Get_and_set_data_for_VL_7552 skip
14363 17:01:18.103411 arm64_za-ptrace_Set_VL_7568 pass
14364 17:01:18.103563 arm64_za-ptrace_Disabled_ZA_for_VL_7568 skip
14365 17:01:18.103682 arm64_za-ptrace_Get_and_set_data_for_VL_7568 skip
14366 17:01:18.103796 arm64_za-ptrace_Set_VL_7584 pass
14367 17:01:18.103908 arm64_za-ptrace_Disabled_ZA_for_VL_7584 skip
14368 17:01:18.104021 arm64_za-ptrace_Get_and_set_data_for_VL_7584 skip
14369 17:01:18.104133 arm64_za-ptrace_Set_VL_7600 pass
14370 17:01:18.104246 arm64_za-ptrace_Disabled_ZA_for_VL_7600 skip
14371 17:01:18.104360 arm64_za-ptrace_Get_and_set_data_for_VL_7600 skip
14372 17:01:18.104473 arm64_za-ptrace_Set_VL_7616 pass
14373 17:01:18.104585 arm64_za-ptrace_Disabled_ZA_for_VL_7616 skip
14374 17:01:18.104697 arm64_za-ptrace_Get_and_set_data_for_VL_7616 skip
14375 17:01:18.104810 arm64_za-ptrace_Set_VL_7632 pass
14376 17:01:18.104923 arm64_za-ptrace_Disabled_ZA_for_VL_7632 skip
14377 17:01:18.105035 arm64_za-ptrace_Get_and_set_data_for_VL_7632 skip
14378 17:01:18.105148 arm64_za-ptrace_Set_VL_7648 pass
14379 17:01:18.105260 arm64_za-ptrace_Disabled_ZA_for_VL_7648 skip
14380 17:01:18.105371 arm64_za-ptrace_Get_and_set_data_for_VL_7648 skip
14381 17:01:18.105516 arm64_za-ptrace_Set_VL_7664 pass
14382 17:01:18.105637 arm64_za-ptrace_Disabled_ZA_for_VL_7664 skip
14383 17:01:18.107606 arm64_za-ptrace_Get_and_set_data_for_VL_7664 skip
14384 17:01:18.107722 arm64_za-ptrace_Set_VL_7680 pass
14385 17:01:18.108036 arm64_za-ptrace_Disabled_ZA_for_VL_7680 skip
14386 17:01:18.108196 arm64_za-ptrace_Get_and_set_data_for_VL_7680 skip
14387 17:01:18.108350 arm64_za-ptrace_Set_VL_7696 pass
14388 17:01:18.108472 arm64_za-ptrace_Disabled_ZA_for_VL_7696 skip
14389 17:01:18.130897 arm64_za-ptrace_Get_and_set_data_for_VL_7696 skip
14390 17:01:18.131265 arm64_za-ptrace_Set_VL_7712 pass
14391 17:01:18.131699 arm64_za-ptrace_Disabled_ZA_for_VL_7712 skip
14392 17:01:18.131890 arm64_za-ptrace_Get_and_set_data_for_VL_7712 skip
14393 17:01:18.132061 arm64_za-ptrace_Set_VL_7728 pass
14394 17:01:18.132230 arm64_za-ptrace_Disabled_ZA_for_VL_7728 skip
14395 17:01:18.132581 arm64_za-ptrace_Get_and_set_data_for_VL_7728 skip
14396 17:01:18.132764 arm64_za-ptrace_Set_VL_7744 pass
14397 17:01:18.132924 arm64_za-ptrace_Disabled_ZA_for_VL_7744 skip
14398 17:01:18.133064 arm64_za-ptrace_Get_and_set_data_for_VL_7744 skip
14399 17:01:18.133238 arm64_za-ptrace_Set_VL_7760 pass
14400 17:01:18.133405 arm64_za-ptrace_Disabled_ZA_for_VL_7760 skip
14401 17:01:18.133563 arm64_za-ptrace_Get_and_set_data_for_VL_7760 skip
14402 17:01:18.133740 arm64_za-ptrace_Set_VL_7776 pass
14403 17:01:18.133882 arm64_za-ptrace_Disabled_ZA_for_VL_7776 skip
14404 17:01:18.134034 arm64_za-ptrace_Get_and_set_data_for_VL_7776 skip
14405 17:01:18.134208 arm64_za-ptrace_Set_VL_7792 pass
14406 17:01:18.134355 arm64_za-ptrace_Disabled_ZA_for_VL_7792 skip
14407 17:01:18.134497 arm64_za-ptrace_Get_and_set_data_for_VL_7792 skip
14408 17:01:18.134640 arm64_za-ptrace_Set_VL_7808 pass
14409 17:01:18.134781 arm64_za-ptrace_Disabled_ZA_for_VL_7808 skip
14410 17:01:18.134923 arm64_za-ptrace_Get_and_set_data_for_VL_7808 skip
14411 17:01:18.135066 arm64_za-ptrace_Set_VL_7824 pass
14412 17:01:18.135255 arm64_za-ptrace_Disabled_ZA_for_VL_7824 skip
14413 17:01:18.135391 arm64_za-ptrace_Get_and_set_data_for_VL_7824 skip
14414 17:01:18.135535 arm64_za-ptrace_Set_VL_7840 pass
14415 17:01:18.135677 arm64_za-ptrace_Disabled_ZA_for_VL_7840 skip
14416 17:01:18.135819 arm64_za-ptrace_Get_and_set_data_for_VL_7840 skip
14417 17:01:18.135961 arm64_za-ptrace_Set_VL_7856 pass
14418 17:01:18.136102 arm64_za-ptrace_Disabled_ZA_for_VL_7856 skip
14419 17:01:18.136246 arm64_za-ptrace_Get_and_set_data_for_VL_7856 skip
14420 17:01:18.136387 arm64_za-ptrace_Set_VL_7872 pass
14421 17:01:18.136527 arm64_za-ptrace_Disabled_ZA_for_VL_7872 skip
14422 17:01:18.136668 arm64_za-ptrace_Get_and_set_data_for_VL_7872 skip
14423 17:01:18.136811 arm64_za-ptrace_Set_VL_7888 pass
14424 17:01:18.136952 arm64_za-ptrace_Disabled_ZA_for_VL_7888 skip
14425 17:01:18.137093 arm64_za-ptrace_Get_and_set_data_for_VL_7888 skip
14426 17:01:18.137237 arm64_za-ptrace_Set_VL_7904 pass
14427 17:01:18.137380 arm64_za-ptrace_Disabled_ZA_for_VL_7904 skip
14428 17:01:18.137521 arm64_za-ptrace_Get_and_set_data_for_VL_7904 skip
14429 17:01:18.137675 arm64_za-ptrace_Set_VL_7920 pass
14430 17:01:18.137819 arm64_za-ptrace_Disabled_ZA_for_VL_7920 skip
14431 17:01:18.137963 arm64_za-ptrace_Get_and_set_data_for_VL_7920 skip
14432 17:01:18.138112 arm64_za-ptrace_Set_VL_7936 pass
14433 17:01:18.138256 arm64_za-ptrace_Disabled_ZA_for_VL_7936 skip
14434 17:01:18.138397 arm64_za-ptrace_Get_and_set_data_for_VL_7936 skip
14435 17:01:18.138541 arm64_za-ptrace_Set_VL_7952 pass
14436 17:01:18.138914 arm64_za-ptrace_Disabled_ZA_for_VL_7952 skip
14437 17:01:18.139056 arm64_za-ptrace_Get_and_set_data_for_VL_7952 skip
14438 17:01:18.139204 arm64_za-ptrace_Set_VL_7968 pass
14439 17:01:18.139348 arm64_za-ptrace_Disabled_ZA_for_VL_7968 skip
14440 17:01:18.139719 arm64_za-ptrace_Get_and_set_data_for_VL_7968 skip
14441 17:01:18.139829 arm64_za-ptrace_Set_VL_7984 pass
14442 17:01:18.139921 arm64_za-ptrace_Disabled_ZA_for_VL_7984 skip
14443 17:01:18.140022 arm64_za-ptrace_Get_and_set_data_for_VL_7984 skip
14444 17:01:18.140109 arm64_za-ptrace_Set_VL_8000 pass
14445 17:01:18.140208 arm64_za-ptrace_Disabled_ZA_for_VL_8000 skip
14446 17:01:18.140295 arm64_za-ptrace_Get_and_set_data_for_VL_8000 skip
14447 17:01:18.140394 arm64_za-ptrace_Set_VL_8016 pass
14448 17:01:18.140481 arm64_za-ptrace_Disabled_ZA_for_VL_8016 skip
14449 17:01:18.140580 arm64_za-ptrace_Get_and_set_data_for_VL_8016 skip
14450 17:01:18.140666 arm64_za-ptrace_Set_VL_8032 pass
14451 17:01:18.140765 arm64_za-ptrace_Disabled_ZA_for_VL_8032 skip
14452 17:01:18.140865 arm64_za-ptrace_Get_and_set_data_for_VL_8032 skip
14453 17:01:18.140944 arm64_za-ptrace_Set_VL_8048 pass
14454 17:01:18.141036 arm64_za-ptrace_Disabled_ZA_for_VL_8048 skip
14455 17:01:18.141125 arm64_za-ptrace_Get_and_set_data_for_VL_8048 skip
14456 17:01:18.141213 arm64_za-ptrace_Set_VL_8064 pass
14457 17:01:18.141301 arm64_za-ptrace_Disabled_ZA_for_VL_8064 skip
14458 17:01:18.141585 arm64_za-ptrace_Get_and_set_data_for_VL_8064 skip
14459 17:01:18.141696 arm64_za-ptrace_Set_VL_8080 pass
14460 17:01:18.141791 arm64_za-ptrace_Disabled_ZA_for_VL_8080 skip
14461 17:01:18.141870 arm64_za-ptrace_Get_and_set_data_for_VL_8080 skip
14462 17:01:18.141945 arm64_za-ptrace_Set_VL_8096 pass
14463 17:01:18.142033 arm64_za-ptrace_Disabled_ZA_for_VL_8096 skip
14464 17:01:18.142123 arm64_za-ptrace_Get_and_set_data_for_VL_8096 skip
14465 17:01:18.142409 arm64_za-ptrace_Set_VL_8112 pass
14466 17:01:18.142512 arm64_za-ptrace_Disabled_ZA_for_VL_8112 skip
14467 17:01:18.142606 arm64_za-ptrace_Get_and_set_data_for_VL_8112 skip
14468 17:01:18.142688 arm64_za-ptrace_Set_VL_8128 pass
14469 17:01:18.142766 arm64_za-ptrace_Disabled_ZA_for_VL_8128 skip
14470 17:01:18.142856 arm64_za-ptrace_Get_and_set_data_for_VL_8128 skip
14471 17:01:18.142936 arm64_za-ptrace_Set_VL_8144 pass
14472 17:01:18.143026 arm64_za-ptrace_Disabled_ZA_for_VL_8144 skip
14473 17:01:18.143123 arm64_za-ptrace_Get_and_set_data_for_VL_8144 skip
14474 17:01:18.143272 arm64_za-ptrace_Set_VL_8160 pass
14475 17:01:18.143379 arm64_za-ptrace_Disabled_ZA_for_VL_8160 skip
14476 17:01:18.143473 arm64_za-ptrace_Get_and_set_data_for_VL_8160 skip
14477 17:01:18.143553 arm64_za-ptrace_Set_VL_8176 pass
14478 17:01:18.143832 arm64_za-ptrace_Disabled_ZA_for_VL_8176 skip
14479 17:01:18.143934 arm64_za-ptrace_Get_and_set_data_for_VL_8176 skip
14480 17:01:18.144016 arm64_za-ptrace_Set_VL_8192 pass
14481 17:01:18.144095 arm64_za-ptrace_Disabled_ZA_for_VL_8192 skip
14482 17:01:18.147610 arm64_za-ptrace_Get_and_set_data_for_VL_8192 skip
14483 17:01:18.147754 arm64_za-ptrace pass
14484 17:01:18.148041 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory pass
14485 17:01:18.148146 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory pass
14486 17:01:18.148486 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory pass
14487 17:01:18.148774 arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory pass
14488 17:01:18.148974 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory fail
14489 17:01:18.149195 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory fail
14490 17:01:18.149361 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14491 17:01:18.149566 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory pass
14492 17:01:18.149783 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory pass
14493 17:01:18.149992 arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory pass
14494 17:01:18.150219 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory fail
14495 17:01:18.150435 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory fail
14496 17:01:18.150602 arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory pass
14497 17:01:18.150796 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory fail
14498 17:01:18.150967 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory fail
14499 17:01:18.151163 arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory pass
14500 17:01:18.151341 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory pass
14501 17:01:18.151539 arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14502 17:01:18.155581 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory pass
14503 17:01:18.155949 arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory pass
14504 17:01:18.156055 arm64_check_buffer_fill fail
14505 17:01:18.156163 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14506 17:01:18.156505 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14507 17:01:18.156734 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14508 17:01:18.156969 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14509 17:01:18.157245 arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14510 17:01:18.157521 arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14511 17:01:18.157800 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory fail
14512 17:01:18.157996 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory fail
14513 17:01:18.158276 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory fail
14514 17:01:18.158480 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory fail
14515 17:01:18.158688 arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory fail
14516 17:01:18.158921 arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory fail
14517 17:01:18.159143 arm64_check_child_memory fail
14518 17:01:18.159400 arm64_check_gcr_el1_cswitch fail
14519 17:01:18.159594 arm64_check_ksm_options fail
14520 17:01:18.159716 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off pass
14521 17:01:18.167629 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14522 17:01:18.168168 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off pass
14523 17:01:18.168410 arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off pass
14524 17:01:18.168653 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14525 17:01:18.173919 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14526 17:01:18.174305 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14527 17:01:18.174425 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14528 17:01:18.174725 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14529 17:01:18.175106 arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14530 17:01:18.175416 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14531 17:01:18.175808 arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14532 17:01:18.176087 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14533 17:01:18.176500 arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14534 17:01:18.176756 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on fail
14535 17:01:18.176993 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14536 17:01:18.177218 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14537 17:01:18.177411 arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14538 17:01:18.177851 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on fail
14539 17:01:18.178101 arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on fail
14540 17:01:18.178335 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory fail
14541 17:01:18.178540 arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory fail
14542 17:01:18.178756 arm64_check_mmap_options fail
14543 17:01:18.178953 arm64_check_prctl_check_basic_read pass
14544 17:01:18.179200 arm64_check_prctl_NONE pass
14545 17:01:18.179400 arm64_check_prctl_SYNC pass
14546 17:01:18.179577 arm64_check_prctl_ASYNC pass
14547 17:01:18.179705 arm64_check_prctl_SYNC_ASYNC pass
14548 17:01:18.179823 arm64_check_prctl pass
14549 17:01:18.179964 arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode fail
14550 17:01:18.180088 arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode fail
14551 17:01:18.183658 arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode pass
14552 17:01:18.184102 arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode fail
14553 17:01:18.184316 arm64_check_tags_inclusion fail
14554 17:01:18.184551 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14555 17:01:18.184738 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14556 17:01:18.184919 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14557 17:01:18.185102 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14558 17:01:18.185362 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14559 17:01:18.185583 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14560 17:01:18.185820 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14561 17:01:18.186020 arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14562 17:01:18.186239 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14563 17:01:18.186426 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14564 17:01:18.186681 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14565 17:01:18.186890 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14566 17:01:18.187099 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14567 17:01:18.187345 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14568 17:01:18.187515 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14569 17:01:18.187698 arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14570 17:01:18.191647 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14571 17:01:18.192104 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14572 17:01:18.192302 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14573 17:01:18.192516 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14574 17:01:18.192709 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14575 17:01:18.192960 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14576 17:01:18.193164 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14577 17:01:18.193400 arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14578 17:01:18.193615 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14579 17:01:18.193883 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14580 17:01:18.194103 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14581 17:01:18.194370 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14582 17:01:18.194584 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14583 17:01:18.194805 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14584 17:01:18.195053 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14585 17:01:18.195229 arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14586 17:01:18.195456 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14587 17:01:18.195608 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14588 17:01:18.199839 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14589 17:01:18.200076 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14590 17:01:18.200481 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14591 17:01:18.200607 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14592 17:01:18.200704 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14593 17:01:18.201014 arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14594 17:01:18.201195 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14595 17:01:18.201371 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14596 17:01:18.201497 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14597 17:01:18.201637 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14598 17:01:18.201829 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14599 17:01:18.202224 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14600 17:01:18.202338 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14601 17:01:18.202459 arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14602 17:01:18.202786 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14603 17:01:18.202898 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14604 17:01:18.205683 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14605 17:01:18.205791 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14606 17:01:18.211757 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14607 17:01:18.211869 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14608 17:01:18.212173 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14609 17:01:18.212266 arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14610 17:01:18.212366 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 pass
14611 17:01:18.212673 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 pass
14612 17:01:18.213043 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 pass
14613 17:01:18.213171 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 pass
14614 17:01:18.213667 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 pass
14615 17:01:18.213751 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 pass
14616 17:01:18.228143 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 pass
14617 17:01:18.228563 arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 pass
14618 17:01:18.228662 arm64_check_user_mem pass
14619 17:01:18.228742 arm64_btitest_nohint_func_call_using_br_x0 pass
14620 17:01:18.228819 arm64_btitest_nohint_func_call_using_br_x16 pass
14621 17:01:18.228893 arm64_btitest_nohint_func_call_using_blr pass
14622 17:01:18.228982 arm64_btitest_bti_none_func_call_using_br_x0 pass
14623 17:01:18.229059 arm64_btitest_bti_none_func_call_using_br_x16 pass
14624 17:01:18.229133 arm64_btitest_bti_none_func_call_using_blr pass
14625 17:01:18.229207 arm64_btitest_bti_c_func_call_using_br_x0 pass
14626 17:01:18.229294 arm64_btitest_bti_c_func_call_using_br_x16 pass
14627 17:01:18.229370 arm64_btitest_bti_c_func_call_using_blr pass
14628 17:01:18.229444 arm64_btitest_bti_j_func_call_using_br_x0 pass
14629 17:01:18.229517 arm64_btitest_bti_j_func_call_using_br_x16 pass
14630 17:01:18.229591 arm64_btitest_bti_j_func_call_using_blr pass
14631 17:01:18.229690 arm64_btitest_bti_jc_func_call_using_br_x0 pass
14632 17:01:18.229770 arm64_btitest_bti_jc_func_call_using_br_x16 pass
14633 17:01:18.229844 arm64_btitest_bti_jc_func_call_using_blr pass
14634 17:01:18.229916 arm64_btitest_paciasp_func_call_using_br_x0 pass
14635 17:01:18.230002 arm64_btitest_paciasp_func_call_using_br_x16 pass
14636 17:01:18.230077 arm64_btitest_paciasp_func_call_using_blr pass
14637 17:01:18.230149 arm64_btitest pass
14638 17:01:18.230586 arm64_nobtitest_nohint_func_call_using_br_x0 pass
14639 17:01:18.230668 arm64_nobtitest_nohint_func_call_using_br_x16 pass
14640 17:01:18.230743 arm64_nobtitest_nohint_func_call_using_blr pass
14641 17:01:18.230817 arm64_nobtitest_bti_none_func_call_using_br_x0 pass
14642 17:01:18.230890 arm64_nobtitest_bti_none_func_call_using_br_x16 pass
14643 17:01:18.230963 arm64_nobtitest_bti_none_func_call_using_blr pass
14644 17:01:18.231036 arm64_nobtitest_bti_c_func_call_using_br_x0 pass
14645 17:01:18.231109 arm64_nobtitest_bti_c_func_call_using_br_x16 pass
14646 17:01:18.231368 arm64_nobtitest_bti_c_func_call_using_blr pass
14647 17:01:18.231448 arm64_nobtitest_bti_j_func_call_using_br_x0 pass
14648 17:01:18.231523 arm64_nobtitest_bti_j_func_call_using_br_x16 pass
14649 17:01:18.231596 arm64_nobtitest_bti_j_func_call_using_blr pass
14650 17:01:18.231669 arm64_nobtitest_bti_jc_func_call_using_br_x0 pass
14651 17:01:18.231742 arm64_nobtitest_bti_jc_func_call_using_br_x16 pass
14652 17:01:18.231815 arm64_nobtitest_bti_jc_func_call_using_blr pass
14653 17:01:18.231903 arm64_nobtitest_paciasp_func_call_using_br_x0 pass
14654 17:01:18.231978 arm64_nobtitest_paciasp_func_call_using_br_x16 pass
14655 17:01:18.235904 arm64_nobtitest_paciasp_func_call_using_blr pass
14656 17:01:18.235987 arm64_nobtitest pass
14657 17:01:18.236061 arm64_hwcap_cpuinfo_match_RNG pass
14658 17:01:18.236135 arm64_hwcap_sigill_RNG pass
14659 17:01:18.236208 arm64_hwcap_cpuinfo_match_SME pass
14660 17:01:18.236281 arm64_hwcap_sigill_SME pass
14661 17:01:18.236544 arm64_hwcap_cpuinfo_match_SVE pass
14662 17:01:18.236623 arm64_hwcap_sigill_SVE pass
14663 17:01:18.236697 arm64_hwcap_cpuinfo_match_SVE_2 pass
14664 17:01:18.236772 arm64_hwcap_sigill_SVE_2 pass
14665 17:01:18.236845 arm64_hwcap_cpuinfo_match_SVE_AES pass
14666 17:01:18.236919 arm64_hwcap_sigill_SVE_AES pass
14667 17:01:18.236992 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
14668 17:01:18.237274 arm64_hwcap_sigill_SVE2_PMULL pass
14669 17:01:18.237381 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
14670 17:01:18.237465 arm64_hwcap_sigill_SVE2_BITPERM pass
14671 17:01:18.237549 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
14672 17:01:18.237637 arm64_hwcap_sigill_SVE2_SHA3 pass
14673 17:01:18.237946 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
14674 17:01:18.238047 arm64_hwcap_sigill_SVE2_SM4 pass
14675 17:01:18.238134 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
14676 17:01:18.238220 arm64_hwcap_sigill_SVE2_I8MM pass
14677 17:01:18.238306 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
14678 17:01:18.238389 arm64_hwcap_sigill_SVE2_F32MM pass
14679 17:01:18.238472 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
14680 17:01:18.238557 arm64_hwcap_sigill_SVE2_F64MM pass
14681 17:01:18.238642 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
14682 17:01:18.238749 arm64_hwcap_sigill_SVE2_BF16 pass
14683 17:01:18.238865 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
14684 17:01:18.238952 arm64_hwcap_sigill_SVE2_EBF16 skip
14685 17:01:18.239034 arm64_hwcap pass
14686 17:01:18.239159 arm64_ptrace_read_tpidr_one pass
14687 17:01:18.239281 arm64_ptrace_write_tpidr_one pass
14688 17:01:18.239394 arm64_ptrace_verify_tpidr_one pass
14689 17:01:18.239489 arm64_ptrace_count_tpidrs pass
14690 17:01:18.239566 arm64_ptrace_tpidr2_write pass
14691 17:01:18.239639 arm64_ptrace_tpidr2_read pass
14692 17:01:18.239701 arm64_ptrace_write_tpidr_only pass
14693 17:01:18.239761 arm64_ptrace pass
14694 17:01:18.239820 arm64_syscall-abi_getpid_FPSIMD pass
14695 17:01:18.239880 arm64_syscall-abi_getpid_SVE_VL_256 pass
14696 17:01:18.239939 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA pass
14697 17:01:18.239999 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM pass
14698 17:01:18.240081 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA pass
14699 17:01:18.240144 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA pass
14700 17:01:18.240205 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM pass
14701 17:01:18.240265 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA pass
14702 17:01:18.243565 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA pass
14703 17:01:18.243864 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM pass
14704 17:01:18.243986 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA pass
14705 17:01:18.244129 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA pass
14706 17:01:18.244270 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM pass
14707 17:01:18.244410 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA pass
14708 17:01:18.244513 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA pass
14709 17:01:18.244816 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM pass
14710 17:01:18.244919 arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA pass
14711 17:01:18.245017 arm64_syscall-abi_getpid_SVE_VL_240 pass
14712 17:01:18.245101 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA pass
14713 17:01:18.245401 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM pass
14714 17:01:18.245494 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA pass
14715 17:01:18.245574 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA pass
14716 17:01:18.245674 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM pass
14717 17:01:18.245771 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA pass
14718 17:01:18.245869 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA pass
14719 17:01:18.246178 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM pass
14720 17:01:18.246275 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA pass
14721 17:01:18.246379 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA pass
14722 17:01:18.246468 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM pass
14723 17:01:18.246557 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA pass
14724 17:01:18.246851 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA pass
14725 17:01:18.247148 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM pass
14726 17:01:18.247243 arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA pass
14727 17:01:18.247320 arm64_syscall-abi_getpid_SVE_VL_224 pass
14728 17:01:18.247412 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA pass
14729 17:01:18.251623 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM pass
14730 17:01:18.251722 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA pass
14731 17:01:18.251993 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA pass
14732 17:01:18.252088 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM pass
14733 17:01:18.252176 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA pass
14734 17:01:18.252264 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA pass
14735 17:01:18.252350 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM pass
14736 17:01:18.252655 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA pass
14737 17:01:18.252754 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA pass
14738 17:01:18.252843 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM pass
14739 17:01:18.252931 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA pass
14740 17:01:18.253208 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA pass
14741 17:01:18.253321 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM pass
14742 17:01:18.253410 arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA pass
14743 17:01:18.253699 arm64_syscall-abi_getpid_SVE_VL_208 pass
14744 17:01:18.253811 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA pass
14745 17:01:18.253899 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM pass
14746 17:01:18.253986 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA pass
14747 17:01:18.254262 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA pass
14748 17:01:18.254369 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM pass
14749 17:01:18.254652 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA pass
14750 17:01:18.254763 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA pass
14751 17:01:18.254854 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM pass
14752 17:01:18.254957 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA pass
14753 17:01:18.255244 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA pass
14754 17:01:18.255343 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM pass
14755 17:01:18.255453 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA pass
14756 17:01:18.259619 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA pass
14757 17:01:18.259909 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM pass
14758 17:01:18.260001 arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA pass
14759 17:01:18.260086 arm64_syscall-abi_getpid_SVE_VL_192 pass
14760 17:01:18.260183 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA pass
14761 17:01:18.260459 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM pass
14762 17:01:18.260736 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA pass
14763 17:01:18.260824 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA pass
14764 17:01:18.260895 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM pass
14765 17:01:18.260971 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA pass
14766 17:01:18.261038 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA pass
14767 17:01:18.261106 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM pass
14768 17:01:18.261183 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA pass
14769 17:01:18.261265 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA pass
14770 17:01:18.261342 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM pass
14771 17:01:18.261617 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA pass
14772 17:01:18.261717 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA pass
14773 17:01:18.261805 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM pass
14774 17:01:18.261905 arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA pass
14775 17:01:18.261990 arm64_syscall-abi_getpid_SVE_VL_176 pass
14776 17:01:18.262311 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA pass
14777 17:01:18.262415 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM pass
14778 17:01:18.262508 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA pass
14779 17:01:18.262621 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA pass
14780 17:01:18.262711 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM pass
14781 17:01:18.262982 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA pass
14782 17:01:18.263089 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA pass
14783 17:01:18.263208 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM pass
14784 17:01:18.263331 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA pass
14785 17:01:18.268002 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA pass
14786 17:01:18.276042 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM pass
14787 17:01:18.276320 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA pass
14788 17:01:18.276415 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA pass
14789 17:01:18.276505 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM pass
14790 17:01:18.276594 arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA pass
14791 17:01:18.276683 arm64_syscall-abi_getpid_SVE_VL_160 pass
14792 17:01:18.276771 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA pass
14793 17:01:18.276858 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM pass
14794 17:01:18.277014 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA pass
14795 17:01:18.277318 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA pass
14796 17:01:18.277434 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM pass
14797 17:01:18.277533 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA pass
14798 17:01:18.277635 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA pass
14799 17:01:18.277955 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM pass
14800 17:01:18.278069 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA pass
14801 17:01:18.278181 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA pass
14802 17:01:18.278309 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM pass
14803 17:01:18.278437 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA pass
14804 17:01:18.278768 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA pass
14805 17:01:18.278864 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM pass
14806 17:01:18.278979 arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA pass
14807 17:01:18.279080 arm64_syscall-abi_getpid_SVE_VL_144 pass
14808 17:01:18.279220 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA pass
14809 17:01:18.279341 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM pass
14810 17:01:18.279452 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA pass
14811 17:01:18.283796 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA pass
14812 17:01:18.283905 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM pass
14813 17:01:18.284006 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA pass
14814 17:01:18.284106 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA pass
14815 17:01:18.284240 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM pass
14816 17:01:18.284556 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA pass
14817 17:01:18.284675 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA pass
14818 17:01:18.284761 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM pass
14819 17:01:18.284867 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA pass
14820 17:01:18.285167 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA pass
14821 17:01:18.285268 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM pass
14822 17:01:18.285369 arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA pass
14823 17:01:18.285717 arm64_syscall-abi_getpid_SVE_VL_128 pass
14824 17:01:18.285877 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA pass
14825 17:01:18.286013 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM pass
14826 17:01:18.286113 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA pass
14827 17:01:18.286279 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA pass
14828 17:01:18.286437 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM pass
14829 17:01:18.286631 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA pass
14830 17:01:18.286773 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA pass
14831 17:01:18.286924 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM pass
14832 17:01:18.287042 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA pass
14833 17:01:18.287158 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA pass
14834 17:01:18.287326 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM pass
14835 17:01:18.287444 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA pass
14836 17:01:18.287536 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA pass
14837 17:01:18.291616 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM pass
14838 17:01:18.292005 arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA pass
14839 17:01:18.292145 arm64_syscall-abi_getpid_SVE_VL_112 pass
14840 17:01:18.292250 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA pass
14841 17:01:18.292372 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM pass
14842 17:01:18.292512 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA pass
14843 17:01:18.292677 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA pass
14844 17:01:18.292875 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM pass
14845 17:01:18.293090 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA pass
14846 17:01:18.293291 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA pass
14847 17:01:18.293535 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM pass
14848 17:01:18.293739 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA pass
14849 17:01:18.293935 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA pass
14850 17:01:18.294112 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM pass
14851 17:01:18.294307 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA pass
14852 17:01:18.294528 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA pass
14853 17:01:18.294673 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM pass
14854 17:01:18.294862 arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA pass
14855 17:01:18.295052 arm64_syscall-abi_getpid_SVE_VL_96 pass
14856 17:01:18.295220 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA pass
14857 17:01:18.295379 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM pass
14858 17:01:18.295500 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA pass
14859 17:01:18.295642 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA pass
14860 17:01:18.295766 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM pass
14861 17:01:18.295883 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA pass
14862 17:01:18.295999 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA pass
14863 17:01:18.299623 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM pass
14864 17:01:18.299941 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA pass
14865 17:01:18.300054 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA pass
14866 17:01:18.300133 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM pass
14867 17:01:18.300220 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA pass
14868 17:01:18.300315 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA pass
14869 17:01:18.300589 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM pass
14870 17:01:18.300697 arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA pass
14871 17:01:18.300787 arm64_syscall-abi_getpid_SVE_VL_80 pass
14872 17:01:18.300874 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA pass
14873 17:01:18.301169 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM pass
14874 17:01:18.302410 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA pass
14875 17:01:18.302516 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA pass
14876 17:01:18.302593 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM pass
14877 17:01:18.303019 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA pass
14878 17:01:18.303118 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA pass
14879 17:01:18.303196 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM pass
14880 17:01:18.303270 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA pass
14881 17:01:18.303344 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA pass
14882 17:01:18.303418 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM pass
14883 17:01:18.303492 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA pass
14884 17:01:18.303565 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA pass
14885 17:01:18.303653 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM pass
14886 17:01:18.303730 arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA pass
14887 17:01:18.303803 arm64_syscall-abi_getpid_SVE_VL_64 pass
14888 17:01:18.303877 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA pass
14889 17:01:18.307619 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM pass
14890 17:01:18.308098 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA pass
14891 17:01:18.308297 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA pass
14892 17:01:18.308469 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM pass
14893 17:01:18.308671 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA pass
14894 17:01:18.308844 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA pass
14895 17:01:18.309006 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM pass
14896 17:01:18.309158 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA pass
14897 17:01:18.309359 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA pass
14898 17:01:18.309537 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM pass
14899 17:01:18.309716 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA pass
14900 17:01:18.309883 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA pass
14901 17:01:18.310130 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM pass
14902 17:01:18.310322 arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA pass
14903 17:01:18.310557 arm64_syscall-abi_getpid_SVE_VL_48 pass
14904 17:01:18.310758 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA pass
14905 17:01:18.310933 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM pass
14906 17:01:18.311122 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA pass
14907 17:01:18.311405 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA pass
14908 17:01:18.311585 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM pass
14909 17:01:18.311716 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA pass
14910 17:01:18.311834 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA pass
14911 17:01:18.311949 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM pass
14912 17:01:18.312062 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA pass
14913 17:01:18.312176 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA pass
14914 17:01:18.312289 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM pass
14915 17:01:18.315555 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA pass
14916 17:01:18.315847 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA pass
14917 17:01:18.315952 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM pass
14918 17:01:18.316251 arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA pass
14919 17:01:18.316355 arm64_syscall-abi_getpid_SVE_VL_32 pass
14920 17:01:18.316455 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA pass
14921 17:01:18.316933 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM pass
14922 17:01:18.317040 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA pass
14923 17:01:18.317125 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA pass
14924 17:01:18.317208 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM pass
14925 17:01:18.317288 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA pass
14926 17:01:18.317619 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA pass
14927 17:01:18.317809 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM pass
14928 17:01:18.317981 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA pass
14929 17:01:18.318201 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA pass
14930 17:01:18.318459 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM pass
14931 17:01:18.318655 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA pass
14932 17:01:18.318830 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA pass
14933 17:01:18.318966 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM pass
14934 17:01:18.319081 arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA pass
14935 17:01:18.319231 arm64_syscall-abi_getpid_SVE_VL_16 pass
14936 17:01:18.319356 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA pass
14937 17:01:18.319474 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM pass
14938 17:01:18.326038 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA pass
14939 17:01:18.326605 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA pass
14940 17:01:18.326808 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM pass
14941 17:01:18.326984 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA pass
14942 17:01:18.327154 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA pass
14943 17:01:18.327326 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM pass
14944 17:01:18.327556 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA pass
14945 17:01:18.327747 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA pass
14946 17:01:18.327919 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM pass
14947 17:01:18.328086 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA pass
14948 17:01:18.328251 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA pass
14949 17:01:18.328445 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM pass
14950 17:01:18.328619 arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA pass
14951 17:01:18.328787 arm64_syscall-abi_sched_yield_FPSIMD pass
14952 17:01:18.328954 arm64_syscall-abi_sched_yield_SVE_VL_256 pass
14953 17:01:18.329119 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA pass
14954 17:01:18.329352 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM pass
14955 17:01:18.329631 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA pass
14956 17:01:18.329896 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA pass
14957 17:01:18.330147 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM pass
14958 17:01:18.330431 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA pass
14959 17:01:18.330680 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA pass
14960 17:01:18.330914 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM pass
14961 17:01:18.331216 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA pass
14962 17:01:18.331485 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA pass
14963 17:01:18.331680 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM pass
14964 17:01:18.331839 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA pass
14965 17:01:18.331993 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA pass
14966 17:01:18.332144 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM pass
14967 17:01:18.332265 arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA pass
14968 17:01:18.332432 arm64_syscall-abi_sched_yield_SVE_VL_240 pass
14969 17:01:18.332598 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA pass
14970 17:01:18.332749 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM pass
14971 17:01:18.332911 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA pass
14972 17:01:18.333033 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA pass
14973 17:01:18.333399 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM pass
14974 17:01:18.333503 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA pass
14975 17:01:18.335621 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA pass
14976 17:01:18.335944 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM pass
14977 17:01:18.336052 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA pass
14978 17:01:18.336153 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA pass
14979 17:01:18.336240 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM pass
14980 17:01:18.336341 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA pass
14981 17:01:18.336648 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA pass
14982 17:01:18.336755 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM pass
14983 17:01:18.337447 arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA pass
14984 17:01:18.337555 arm64_syscall-abi_sched_yield_SVE_VL_224 pass
14985 17:01:18.337641 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA pass
14986 17:01:18.337733 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM pass
14987 17:01:18.337816 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA pass
14988 17:01:18.338101 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA pass
14989 17:01:18.338432 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM pass
14990 17:01:18.338541 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA pass
14991 17:01:18.338646 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA pass
14992 17:01:18.338734 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM pass
14993 17:01:18.338818 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA pass
14994 17:01:18.338914 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA pass
14995 17:01:18.339011 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM pass
14996 17:01:18.339108 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA pass
14997 17:01:18.339407 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA pass
14998 17:01:18.343589 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM pass
14999 17:01:18.344009 arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA pass
15000 17:01:18.344306 arm64_syscall-abi_sched_yield_SVE_VL_208 pass
15001 17:01:18.344482 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA pass
15002 17:01:18.344643 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM pass
15003 17:01:18.344791 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA pass
15004 17:01:18.344957 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA pass
15005 17:01:18.345107 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM pass
15006 17:01:18.345263 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA pass
15007 17:01:18.345455 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA pass
15008 17:01:18.345610 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM pass
15009 17:01:18.345816 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA pass
15010 17:01:18.345987 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA pass
15011 17:01:18.346155 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM pass
15012 17:01:18.346348 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA pass
15013 17:01:18.346519 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA pass
15014 17:01:18.346685 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM pass
15015 17:01:18.346880 arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA pass
15016 17:01:18.347049 arm64_syscall-abi_sched_yield_SVE_VL_192 pass
15017 17:01:18.347221 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA pass
15018 17:01:18.347376 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM pass
15019 17:01:18.347526 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA pass
15020 17:01:18.347652 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA pass
15021 17:01:18.347769 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM pass
15022 17:01:18.351595 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA pass
15023 17:01:18.352018 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA pass
15024 17:01:18.352204 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM pass
15025 17:01:18.352374 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA pass
15026 17:01:18.352575 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA pass
15027 17:01:18.352748 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM pass
15028 17:01:18.352915 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA pass
15029 17:01:18.353082 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA pass
15030 17:01:18.353280 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM pass
15031 17:01:18.353469 arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA pass
15032 17:01:18.353633 arm64_syscall-abi_sched_yield_SVE_VL_176 pass
15033 17:01:18.353808 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA pass
15034 17:01:18.353966 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM pass
15035 17:01:18.354156 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA pass
15036 17:01:18.354321 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA pass
15037 17:01:18.354477 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM pass
15038 17:01:18.354640 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA pass
15039 17:01:18.354773 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA pass
15040 17:01:18.354894 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM pass
15041 17:01:18.355048 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA pass
15042 17:01:18.355178 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA pass
15043 17:01:18.355300 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM pass
15044 17:01:18.355451 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA pass
15045 17:01:18.355581 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA pass
15046 17:01:18.355702 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM pass
15047 17:01:18.355817 arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA pass
15048 17:01:18.355913 arm64_syscall-abi_sched_yield_SVE_VL_160 pass
15049 17:01:18.356005 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA pass
15050 17:01:18.359698 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM pass
15051 17:01:18.359803 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA pass
15052 17:01:18.360081 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA pass
15053 17:01:18.360180 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM pass
15054 17:01:18.360257 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA pass
15055 17:01:18.360345 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA pass
15056 17:01:18.360422 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM pass
15057 17:01:18.360508 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA pass
15058 17:01:18.360870 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA pass
15059 17:01:18.361022 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM pass
15060 17:01:18.361140 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA pass
15061 17:01:18.361253 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA pass
15062 17:01:18.361584 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM pass
15063 17:01:18.361837 arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA pass
15064 17:01:18.361996 arm64_syscall-abi_sched_yield_SVE_VL_144 pass
15065 17:01:18.362128 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA pass
15066 17:01:18.362264 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM pass
15067 17:01:18.362424 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA pass
15068 17:01:18.362566 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA pass
15069 17:01:18.362683 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM pass
15070 17:01:18.362852 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA pass
15071 17:01:18.363013 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA pass
15072 17:01:18.363197 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM pass
15073 17:01:18.363341 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA pass
15074 17:01:18.363475 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA pass
15075 17:01:18.363617 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM pass
15076 17:01:18.367636 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA pass
15077 17:01:18.367976 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA pass
15078 17:01:18.376153 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM pass
15079 17:01:18.376281 arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA pass
15080 17:01:18.376559 arm64_syscall-abi_sched_yield_SVE_VL_128 pass
15081 17:01:18.376648 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA pass
15082 17:01:18.376730 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM pass
15083 17:01:18.376825 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA pass
15084 17:01:18.376908 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA pass
15085 17:01:18.377004 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM pass
15086 17:01:18.377117 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA pass
15087 17:01:18.377398 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA pass
15088 17:01:18.377485 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM pass
15089 17:01:18.377579 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA pass
15090 17:01:18.377682 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA pass
15091 17:01:18.377779 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM pass
15092 17:01:18.378089 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA pass
15093 17:01:18.378193 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA pass
15094 17:01:18.378290 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM pass
15095 17:01:18.378385 arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA pass
15096 17:01:18.378479 arm64_syscall-abi_sched_yield_SVE_VL_112 pass
15097 17:01:18.378762 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA pass
15098 17:01:18.378852 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM pass
15099 17:01:18.378948 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA pass
15100 17:01:18.379044 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA pass
15101 17:01:18.379153 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM pass
15102 17:01:18.379458 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA pass
15103 17:01:18.383603 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA pass
15104 17:01:18.383926 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM pass
15105 17:01:18.384030 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA pass
15106 17:01:18.384134 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA pass
15107 17:01:18.384236 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM pass
15108 17:01:18.384338 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA pass
15109 17:01:18.384671 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA pass
15110 17:01:18.384844 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM pass
15111 17:01:18.385053 arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA pass
15112 17:01:18.385195 arm64_syscall-abi_sched_yield_SVE_VL_96 pass
15113 17:01:18.385373 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA pass
15114 17:01:18.385514 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM pass
15115 17:01:18.385673 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA pass
15116 17:01:18.385819 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA pass
15117 17:01:18.385999 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM pass
15118 17:01:18.386135 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA pass
15119 17:01:18.386297 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA pass
15120 17:01:18.386473 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM pass
15121 17:01:18.386619 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA pass
15122 17:01:18.386800 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA pass
15123 17:01:18.386939 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM pass
15124 17:01:18.387085 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA pass
15125 17:01:18.387229 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA pass
15126 17:01:18.387371 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM pass
15127 17:01:18.387512 arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA pass
15128 17:01:18.387693 arm64_syscall-abi_sched_yield_SVE_VL_80 pass
15129 17:01:18.387831 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA pass
15130 17:01:18.387974 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM pass
15131 17:01:18.388115 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA pass
15132 17:01:18.388258 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA pass
15133 17:01:18.388400 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM pass
15134 17:01:18.391605 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA pass
15135 17:01:18.391955 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA pass
15136 17:01:18.392137 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM pass
15137 17:01:18.392370 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA pass
15138 17:01:18.392561 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA pass
15139 17:01:18.392702 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM pass
15140 17:01:18.392848 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA pass
15141 17:01:18.392992 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA pass
15142 17:01:18.393138 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM pass
15143 17:01:18.393329 arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA pass
15144 17:01:18.393485 arm64_syscall-abi_sched_yield_SVE_VL_64 pass
15145 17:01:18.393628 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA pass
15146 17:01:18.393784 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM pass
15147 17:01:18.393928 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA pass
15148 17:01:18.394106 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA pass
15149 17:01:18.394244 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM pass
15150 17:01:18.394386 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA pass
15151 17:01:18.394528 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA pass
15152 17:01:18.394671 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM pass
15153 17:01:18.394847 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA pass
15154 17:01:18.394987 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA pass
15155 17:01:18.395131 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM pass
15156 17:01:18.395274 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA pass
15157 17:01:18.395416 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA pass
15158 17:01:18.395590 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM pass
15159 17:01:18.395728 arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA pass
15160 17:01:18.395871 arm64_syscall-abi_sched_yield_SVE_VL_48 pass
15161 17:01:18.396013 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA pass
15162 17:01:18.399573 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM pass
15163 17:01:18.399957 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA pass
15164 17:01:18.400170 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA pass
15165 17:01:18.400402 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM pass
15166 17:01:18.400674 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA pass
15167 17:01:18.400884 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA pass
15168 17:01:18.401054 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM pass
15169 17:01:18.401218 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA pass
15170 17:01:18.401417 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA pass
15171 17:01:18.401589 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM pass
15172 17:01:18.401766 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA pass
15173 17:01:18.401923 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA pass
15174 17:01:18.402111 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM pass
15175 17:01:18.402281 arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA pass
15176 17:01:18.402515 arm64_syscall-abi_sched_yield_SVE_VL_32 pass
15177 17:01:18.402771 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA pass
15178 17:01:18.402976 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM pass
15179 17:01:18.403165 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA pass
15180 17:01:18.403336 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA pass
15181 17:01:18.403479 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM pass
15182 17:01:18.403599 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA pass
15183 17:01:18.403719 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA pass
15184 17:01:18.403836 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM pass
15185 17:01:18.403979 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA pass
15186 17:01:18.404103 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA pass
15187 17:01:18.404222 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM pass
15188 17:01:18.404341 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA pass
15189 17:01:18.404458 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA pass
15190 17:01:18.404575 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM pass
15191 17:01:18.407632 arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA pass
15192 17:01:18.407942 arm64_syscall-abi_sched_yield_SVE_VL_16 pass
15193 17:01:18.408043 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA pass
15194 17:01:18.408139 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM pass
15195 17:01:18.408231 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA pass
15196 17:01:18.408568 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA pass
15197 17:01:18.408679 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM pass
15198 17:01:18.408976 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA pass
15199 17:01:18.409082 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA pass
15200 17:01:18.409693 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM pass
15201 17:01:18.409801 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA pass
15202 17:01:18.409888 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA pass
15203 17:01:18.409974 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM pass
15204 17:01:18.410059 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA pass
15205 17:01:18.410144 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA pass
15206 17:01:18.410562 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM pass
15207 17:01:18.410688 arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA pass
15208 17:01:18.410779 arm64_syscall-abi pass
15209 17:01:18.410862 arm64_tpidr2_default_value pass
15210 17:01:18.410945 arm64_tpidr2_write_read pass
15211 17:01:18.411033 arm64_tpidr2_write_sleep_read pass
15212 17:01:18.411121 arm64_tpidr2_write_fork_read pass
15213 17:01:18.411223 arm64_tpidr2_write_clone_read pass
15214 17:01:18.411309 arm64_tpidr2 pass
15215 17:01:18.425827 + ../../utils/send-to-lava.sh ./output/result.txt
15216 17:01:18.469734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
15217 17:01:18.470840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
15219 17:01:18.501900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
15220 17:01:18.502452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
15222 17:01:18.535422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
15223 17:01:18.535851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
15225 17:01:18.571566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
15226 17:01:18.572020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
15228 17:01:18.605434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
15229 17:01:18.605924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
15231 17:01:18.638040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
15232 17:01:18.638475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
15234 17:01:18.670194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
15235 17:01:18.670620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
15237 17:01:18.702973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
15238 17:01:18.703393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
15240 17:01:18.735063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass>
15241 17:01:18.735507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=pass
15243 17:01:18.766968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass>
15244 17:01:18.767397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=pass
15246 17:01:18.800106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
15247 17:01:18.800521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
15249 17:01:18.831644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
15251 17:01:18.832104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
15252 17:01:18.864373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
15253 17:01:18.864802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
15255 17:01:18.897610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
15257 17:01:18.898077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
15258 17:01:18.928933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
15259 17:01:18.929359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
15261 17:01:18.961428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
15262 17:01:18.961875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
15264 17:01:18.993412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
15266 17:01:18.993888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
15267 17:01:19.024918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
15268 17:01:19.025376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
15270 17:01:19.061006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass>
15271 17:01:19.061403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=pass
15273 17:01:19.096789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
15275 17:01:19.097214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
15276 17:01:19.130561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
15277 17:01:19.130955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
15279 17:01:19.165009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=pass
15281 17:01:19.165383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=pass>
15282 17:01:19.197980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=pass>
15283 17:01:19.198460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=pass
15285 17:01:19.234728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=pass
15287 17:01:19.235442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=pass>
15288 17:01:19.273308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=pass
15290 17:01:19.273953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=pass>
15291 17:01:19.306556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=pass>
15292 17:01:19.307048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=pass
15294 17:01:19.340173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=pass
15296 17:01:19.340784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=pass>
15297 17:01:19.372160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass
15299 17:01:19.372585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_corrupt_pac RESULT=pass>
15300 17:01:19.403507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass
15302 17:01:19.403925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop RESULT=pass>
15303 17:01:19.435331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass
15305 17:01:19.435962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_pac_instructions_not_nop_generic RESULT=pass>
15306 17:01:19.467275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass>
15307 17:01:19.467689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_single_thread_different_keys RESULT=pass
15309 17:01:19.498923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass>
15310 17:01:19.499336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_exec_changed_keys RESULT=pass
15312 17:01:19.530377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass
15314 17:01:19.530802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys RESULT=pass>
15315 17:01:19.561875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass>
15316 17:01:19.562300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_global_context_switch_keep_keys_generic RESULT=pass
15318 17:01:19.593269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
15319 17:01:19.593692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
15321 17:01:19.625134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
15323 17:01:19.625869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
15324 17:01:19.657530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass
15326 17:01:19.658154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-256-0 RESULT=pass>
15327 17:01:19.688760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass
15329 17:01:19.689215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-240-0 RESULT=pass>
15330 17:01:19.720161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass
15332 17:01:19.720617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-224-0 RESULT=pass>
15333 17:01:19.751303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass>
15334 17:01:19.751727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-208-0 RESULT=pass
15336 17:01:19.782796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass>
15337 17:01:19.783237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-192-0 RESULT=pass
15339 17:01:19.813840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass>
15340 17:01:19.814288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-176-0 RESULT=pass
15342 17:01:19.845950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass
15344 17:01:19.846402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-160-0 RESULT=pass>
15345 17:01:19.877413 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass
15347 17:01:19.877884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-144-0 RESULT=pass>
15348 17:01:19.908799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass
15350 17:01:19.909412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-128-0 RESULT=pass>
15351 17:01:19.940946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass
15353 17:01:19.941529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-112-0 RESULT=pass>
15354 17:01:19.972939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass>
15355 17:01:19.973422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-96-0 RESULT=pass
15357 17:01:20.005800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass
15359 17:01:20.006352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-80-0 RESULT=pass>
15360 17:01:20.040330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass>
15361 17:01:20.040749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-64-0 RESULT=pass
15363 17:01:20.077472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass>
15364 17:01:20.077961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-48-0 RESULT=pass
15366 17:01:20.110671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass>
15367 17:01:20.111152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-32-0 RESULT=pass
15369 17:01:20.143364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass>
15370 17:01:20.143793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SVE-VL-16-0 RESULT=pass
15372 17:01:20.177311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass>
15373 17:01:20.177753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-256-0 RESULT=pass
15375 17:01:20.212344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass
15377 17:01:20.212972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-256-0 RESULT=pass>
15378 17:01:20.245570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass
15380 17:01:20.246153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-128-0 RESULT=pass>
15381 17:01:20.278043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass>
15382 17:01:20.278522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-128-0 RESULT=pass
15384 17:01:20.310708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass>
15385 17:01:20.311168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-64-0 RESULT=pass
15387 17:01:20.343162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass>
15388 17:01:20.343665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-64-0 RESULT=pass
15390 17:01:20.378885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass
15392 17:01:20.379340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-32-0 RESULT=pass>
15393 17:01:20.412423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass
15395 17:01:20.412884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-32-0 RESULT=pass>
15396 17:01:20.445527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass>
15397 17:01:20.445976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_SSVE-VL-16-0 RESULT=pass
15399 17:01:20.478703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass
15401 17:01:20.479168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_ZA-VL-16-0 RESULT=pass>
15402 17:01:20.512302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
15403 17:01:20.512745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
15405 17:01:20.550112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
15406 17:01:20.550492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
15408 17:01:20.584148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass>
15409 17:01:20.584547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state RESULT=pass
15411 17:01:20.617354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
15413 17:01:20.617820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
15414 17:01:20.650670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
15415 17:01:20.651085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
15417 17:01:20.685056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass>
15418 17:01:20.685480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_16 RESULT=pass
15420 17:01:20.718124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass>
15421 17:01:20.718541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16 RESULT=pass
15423 17:01:20.750587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass
15425 17:01:20.751059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16 RESULT=pass>
15426 17:01:20.783863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass
15428 17:01:20.784326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16 RESULT=pass>
15429 17:01:20.816787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass>
15430 17:01:20.817228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_32 RESULT=pass
15432 17:01:20.850722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass>
15433 17:01:20.851150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32 RESULT=pass
15435 17:01:20.884595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass>
15436 17:01:20.885011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32 RESULT=pass
15438 17:01:20.920893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass>
15439 17:01:20.921319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32 RESULT=pass
15441 17:01:20.955021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass>
15442 17:01:20.955442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_48 RESULT=pass
15444 17:01:20.989918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass>
15445 17:01:20.990314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48 RESULT=pass
15447 17:01:21.025711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass>
15448 17:01:21.026094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48 RESULT=pass
15450 17:01:21.061476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass>
15451 17:01:21.061926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48 RESULT=pass
15453 17:01:21.097549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass>
15454 17:01:21.097994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_64 RESULT=pass
15456 17:01:21.131208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass
15458 17:01:21.131651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64 RESULT=pass>
15459 17:01:21.165590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass>
15460 17:01:21.166010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64 RESULT=pass
15462 17:01:21.202792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass>
15463 17:01:21.203252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64 RESULT=pass
15465 17:01:21.237908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass>
15466 17:01:21.238348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_80 RESULT=pass
15468 17:01:21.271171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass>
15469 17:01:21.271617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80 RESULT=pass
15471 17:01:21.304393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass>
15472 17:01:21.304905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80 RESULT=pass
15474 17:01:21.337045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass
15476 17:01:21.337711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80 RESULT=pass>
15477 17:01:21.368673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass>
15478 17:01:21.369167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_96 RESULT=pass
15480 17:01:21.400923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass>
15481 17:01:21.401414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96 RESULT=pass
15483 17:01:21.433248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass>
15484 17:01:21.433703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96 RESULT=pass
15486 17:01:21.466752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass>
15487 17:01:21.467180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96 RESULT=pass
15489 17:01:21.500977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass>
15490 17:01:21.501422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_112 RESULT=pass
15492 17:01:21.535846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass
15494 17:01:21.536304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112 RESULT=pass>
15495 17:01:21.570229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass>
15496 17:01:21.570605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112 RESULT=pass
15498 17:01:21.605959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass
15500 17:01:21.606527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112 RESULT=pass>
15501 17:01:21.640073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass>
15502 17:01:21.640502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_128 RESULT=pass
15504 17:01:21.674303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass
15506 17:01:21.674750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128 RESULT=pass>
15507 17:01:21.708046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass
15509 17:01:21.708632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128 RESULT=pass>
15510 17:01:21.742393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass>
15511 17:01:21.742859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128 RESULT=pass
15513 17:01:21.776566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass
15515 17:01:21.777186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_144 RESULT=pass>
15516 17:01:21.810321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass>
15517 17:01:21.810743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144 RESULT=pass
15519 17:01:21.844097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass>
15520 17:01:21.844511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144 RESULT=pass
15522 17:01:21.877412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass>
15523 17:01:21.877858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144 RESULT=pass
15525 17:01:21.912304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass>
15526 17:01:21.912739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_160 RESULT=pass
15528 17:01:21.944892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass>
15529 17:01:21.945354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160 RESULT=pass
15531 17:01:21.982246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass>
15532 17:01:21.982630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160 RESULT=pass
15534 17:01:22.019113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass>
15535 17:01:22.019533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160 RESULT=pass
15537 17:01:22.055023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass>
15538 17:01:22.055560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_176 RESULT=pass
15540 17:01:22.097077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass>
15541 17:01:22.097453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176 RESULT=pass
15543 17:01:22.133990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass
15545 17:01:22.134465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176 RESULT=pass>
15546 17:01:22.183235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass>
15547 17:01:22.183676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176 RESULT=pass
15549 17:01:22.221528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass>
15550 17:01:22.221933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_192 RESULT=pass
15552 17:01:22.262098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass>
15553 17:01:22.262530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192 RESULT=pass
15555 17:01:22.304986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass>
15556 17:01:22.305380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192 RESULT=pass
15558 17:01:22.346426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass>
15559 17:01:22.346805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192 RESULT=pass
15561 17:01:22.399172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass>
15562 17:01:22.399586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_208 RESULT=pass
15564 17:01:22.441270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass>
15565 17:01:22.441713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208 RESULT=pass
15567 17:01:22.478154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass>
15568 17:01:22.478549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208 RESULT=pass
15570 17:01:22.535771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass
15572 17:01:22.536198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208 RESULT=pass>
15573 17:01:22.593859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass>
15574 17:01:22.594390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_224 RESULT=pass
15576 17:01:22.641743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass>
15577 17:01:22.642157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224 RESULT=pass
15579 17:01:22.676862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass
15581 17:01:22.677341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224 RESULT=pass>
15582 17:01:22.712458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass>
15583 17:01:22.712894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224 RESULT=pass
15585 17:01:22.747048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass
15587 17:01:22.747676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_240 RESULT=pass>
15588 17:01:22.782890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass>
15589 17:01:22.783351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240 RESULT=pass
15591 17:01:22.820794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass>
15592 17:01:22.821364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240 RESULT=pass
15594 17:01:22.865597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass
15596 17:01:22.866371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240 RESULT=pass>
15597 17:01:22.905694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass>
15598 17:01:22.906146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_256 RESULT=pass
15600 17:01:22.941475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass
15602 17:01:22.941945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256 RESULT=pass>
15603 17:01:22.979932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass
15605 17:01:22.980415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256 RESULT=pass>
15606 17:01:23.021143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass>
15607 17:01:23.021578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256 RESULT=pass
15609 17:01:23.057942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass
15611 17:01:23.058408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_272 RESULT=pass>
15612 17:01:23.093399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
15614 17:01:23.093869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
15615 17:01:23.130122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
15617 17:01:23.130578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
15618 17:01:23.179717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
15620 17:01:23.180133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
15621 17:01:23.214021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass>
15622 17:01:23.214445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_288 RESULT=pass
15624 17:01:23.248265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
15626 17:01:23.248894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
15627 17:01:23.281439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
15628 17:01:23.281946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
15630 17:01:23.316224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
15632 17:01:23.316892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
15633 17:01:23.349753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass>
15634 17:01:23.350246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_304 RESULT=pass
15636 17:01:23.383919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
15638 17:01:23.384398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
15639 17:01:23.417509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
15640 17:01:23.417944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
15642 17:01:23.451957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
15644 17:01:23.452416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
15645 17:01:23.485599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass>
15646 17:01:23.486042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_320 RESULT=pass
15648 17:01:23.519267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
15650 17:01:23.519726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
15651 17:01:23.553215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
15652 17:01:23.553630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
15654 17:01:23.587340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
15655 17:01:23.587773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
15657 17:01:23.620558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass>
15658 17:01:23.620992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_336 RESULT=pass
15660 17:01:23.653823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
15661 17:01:23.654259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
15663 17:01:23.687824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
15665 17:01:23.688269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
15666 17:01:23.721794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
15667 17:01:23.722222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
15669 17:01:23.755213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass>
15670 17:01:23.755657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_352 RESULT=pass
15672 17:01:23.789040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
15673 17:01:23.789457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
15675 17:01:23.822622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
15677 17:01:23.823082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
15678 17:01:23.857485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
15680 17:01:23.857961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
15681 17:01:23.891007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass
15683 17:01:23.891443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_368 RESULT=pass>
15684 17:01:23.924851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
15686 17:01:23.925336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
15687 17:01:23.958048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
15689 17:01:23.958493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
15690 17:01:23.997909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
15692 17:01:23.998430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
15693 17:01:24.032722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass>
15694 17:01:24.033169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_384 RESULT=pass
15696 17:01:24.066504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
15697 17:01:24.066918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
15699 17:01:24.101178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
15701 17:01:24.101638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
15702 17:01:24.137360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
15703 17:01:24.137759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
15705 17:01:24.170594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass
15707 17:01:24.171042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_400 RESULT=pass>
15708 17:01:24.203430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
15710 17:01:24.203895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
15711 17:01:24.236843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
15712 17:01:24.237270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
15714 17:01:24.270458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
15715 17:01:24.270874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
15717 17:01:24.303433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass
15719 17:01:24.303900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_416 RESULT=pass>
15720 17:01:24.338007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
15722 17:01:24.338467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
15723 17:01:24.371965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
15724 17:01:24.372402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
15726 17:01:24.405807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
15728 17:01:24.406435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
15729 17:01:24.438300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass>
15730 17:01:24.438784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_432 RESULT=pass
15732 17:01:24.470540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
15733 17:01:24.471015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
15735 17:01:24.502835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
15736 17:01:24.503263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
15738 17:01:24.535184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
15739 17:01:24.535631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
15741 17:01:24.567954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass>
15742 17:01:24.568389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_448 RESULT=pass
15744 17:01:24.600945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
15746 17:01:24.601547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
15747 17:01:24.634087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
15748 17:01:24.634553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
15750 17:01:24.668158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
15752 17:01:24.668721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
15753 17:01:24.701466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass>
15754 17:01:24.701952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_464 RESULT=pass
15756 17:01:24.735077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
15757 17:01:24.735513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
15759 17:01:24.768320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
15761 17:01:24.768895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
15762 17:01:24.800788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
15763 17:01:24.801258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
15765 17:01:24.835390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass>
15766 17:01:24.836800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_480 RESULT=pass
15768 17:01:24.868428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
15769 17:01:24.868927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
15771 17:01:24.902036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
15772 17:01:24.902465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
15774 17:01:24.938501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
15775 17:01:24.938922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
15777 17:01:24.973037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass>
15778 17:01:24.973503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_496 RESULT=pass
15780 17:01:25.007422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
15782 17:01:25.007882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
15783 17:01:25.040768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
15784 17:01:25.041216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
15786 17:01:25.074156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
15787 17:01:25.074618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
15789 17:01:25.106996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass>
15790 17:01:25.107466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_512 RESULT=pass
15792 17:01:25.140257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
15794 17:01:25.140842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
15795 17:01:25.172788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
15796 17:01:25.173295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
15798 17:01:25.207190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
15799 17:01:25.207669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
15801 17:01:25.242331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass>
15802 17:01:25.242892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_528 RESULT=pass
15804 17:01:25.288368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
15806 17:01:25.288847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
15807 17:01:25.323293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
15808 17:01:25.323792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
15810 17:01:25.359905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
15812 17:01:25.360386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
15813 17:01:25.397057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass
15815 17:01:25.397477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_544 RESULT=pass>
15816 17:01:25.429823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
15817 17:01:25.430211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
15819 17:01:25.462229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
15820 17:01:25.462716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
15822 17:01:25.495576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
15824 17:01:25.496048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
15825 17:01:25.528731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass>
15826 17:01:25.529245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_560 RESULT=pass
15828 17:01:25.561522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
15830 17:01:25.562289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
15831 17:01:25.594986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
15833 17:01:25.595605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
15834 17:01:25.629125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
15835 17:01:25.629612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
15837 17:01:25.661754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass>
15838 17:01:25.662237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_576 RESULT=pass
15840 17:01:25.694947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
15841 17:01:25.695491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
15843 17:01:25.728792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
15844 17:01:25.729284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
15846 17:01:25.764458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
15847 17:01:25.764956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
15849 17:01:25.797566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass>
15850 17:01:25.798006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_592 RESULT=pass
15852 17:01:25.831289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
15854 17:01:25.831747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
15855 17:01:25.864733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
15856 17:01:25.865163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
15858 17:01:25.897816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
15859 17:01:25.898306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
15861 17:01:25.930969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass>
15862 17:01:25.931459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_608 RESULT=pass
15864 17:01:25.964458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
15865 17:01:25.964946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
15867 17:01:25.997518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
15868 17:01:25.998014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
15870 17:01:26.031666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
15872 17:01:26.032345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
15873 17:01:26.065590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass>
15874 17:01:26.066021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_624 RESULT=pass
15876 17:01:26.098288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
15878 17:01:26.098753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
15879 17:01:26.131238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
15881 17:01:26.131701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
15882 17:01:26.163717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
15884 17:01:26.164399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
15885 17:01:26.196148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass>
15886 17:01:26.196632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_640 RESULT=pass
15888 17:01:26.228380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
15889 17:01:26.228859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
15891 17:01:26.261043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
15892 17:01:26.261471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
15894 17:01:26.293875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
15895 17:01:26.294297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
15897 17:01:26.326224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass
15899 17:01:26.326688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_656 RESULT=pass>
15900 17:01:26.358597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
15902 17:01:26.359059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
15903 17:01:26.392828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
15905 17:01:26.393274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
15906 17:01:26.425241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
15907 17:01:26.425668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
15909 17:01:26.457538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass
15911 17:01:26.458012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_672 RESULT=pass>
15912 17:01:26.491173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
15913 17:01:26.491632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
15915 17:01:26.523856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
15917 17:01:26.524496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
15918 17:01:26.557111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
15920 17:01:26.557733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
15921 17:01:26.589422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass>
15922 17:01:26.589890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_688 RESULT=pass
15924 17:01:26.623554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
15925 17:01:26.624014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
15927 17:01:26.657897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
15928 17:01:26.658379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
15930 17:01:26.691470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
15931 17:01:26.691939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
15933 17:01:26.724537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass>
15934 17:01:26.725032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_704 RESULT=pass
15936 17:01:26.757142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
15937 17:01:26.757624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
15939 17:01:26.790099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
15941 17:01:26.790655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
15942 17:01:26.823885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
15944 17:01:26.824328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
15945 17:01:26.856931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass>
15946 17:01:26.857434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_720 RESULT=pass
15948 17:01:26.891431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
15950 17:01:26.891894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
15951 17:01:26.925281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
15953 17:01:26.925750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
15954 17:01:26.958492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
15955 17:01:26.958955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
15957 17:01:26.991048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass
15959 17:01:26.991510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_736 RESULT=pass>
15960 17:01:27.024063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
15962 17:01:27.024803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
15963 17:01:27.059285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
15964 17:01:27.059707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
15966 17:01:27.094032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
15968 17:01:27.094506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
15969 17:01:27.127272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass>
15970 17:01:27.127701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_752 RESULT=pass
15972 17:01:27.160798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
15974 17:01:27.161378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
15975 17:01:27.194071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
15976 17:01:27.194552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
15978 17:01:27.227463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
15980 17:01:27.228020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
15981 17:01:27.260403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass>
15982 17:01:27.260849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_768 RESULT=pass
15984 17:01:27.293837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
15986 17:01:27.294410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
15987 17:01:27.326305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
15989 17:01:27.326947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
15990 17:01:27.359361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
15991 17:01:27.359835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
15993 17:01:27.393699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass>
15994 17:01:27.394109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_784 RESULT=pass
15996 17:01:27.429093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
15998 17:01:27.429554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
15999 17:01:27.465914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
16000 17:01:27.466332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
16002 17:01:27.500530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
16004 17:01:27.501153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
16005 17:01:27.533990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass>
16006 17:01:27.534472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_800 RESULT=pass
16008 17:01:27.567667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
16010 17:01:27.568127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
16011 17:01:27.602907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
16013 17:01:27.603361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
16014 17:01:27.637218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
16016 17:01:27.637645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
16017 17:01:27.669895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass>
16018 17:01:27.670330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_816 RESULT=pass
16020 17:01:27.702869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
16022 17:01:27.703336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
16023 17:01:27.735209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
16024 17:01:27.735650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
16026 17:01:27.770077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
16027 17:01:27.770630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
16029 17:01:27.804669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass
16031 17:01:27.805289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_832 RESULT=pass>
16032 17:01:27.840915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
16034 17:01:27.841490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
16035 17:01:27.877828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
16037 17:01:27.878390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
16038 17:01:27.913956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
16039 17:01:27.914379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
16041 17:01:27.948152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass>
16042 17:01:27.948642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_848 RESULT=pass
16044 17:01:27.983515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
16046 17:01:27.984079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
16047 17:01:28.018296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
16048 17:01:28.018713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
16050 17:01:28.054151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
16051 17:01:28.054612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
16053 17:01:28.087485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass>
16054 17:01:28.087924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_864 RESULT=pass
16056 17:01:28.120577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
16058 17:01:28.120976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
16059 17:01:28.154174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
16061 17:01:28.154636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
16062 17:01:28.189135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
16063 17:01:28.189555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
16065 17:01:28.222881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass
16067 17:01:28.223344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_880 RESULT=pass>
16068 17:01:28.256035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
16069 17:01:28.256464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
16071 17:01:28.289330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
16073 17:01:28.289804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
16074 17:01:28.322915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
16075 17:01:28.323340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
16077 17:01:28.355804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass
16079 17:01:28.356254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_896 RESULT=pass>
16080 17:01:28.389129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
16081 17:01:28.389554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
16083 17:01:28.422191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
16085 17:01:28.422647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
16086 17:01:28.456278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
16087 17:01:28.456683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
16089 17:01:28.489305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass>
16090 17:01:28.489728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_912 RESULT=pass
16092 17:01:28.521724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
16093 17:01:28.522152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
16095 17:01:28.554162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
16097 17:01:28.554618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
16098 17:01:28.586756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
16099 17:01:28.587198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
16101 17:01:28.619464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass
16103 17:01:28.619927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_928 RESULT=pass>
16104 17:01:28.652225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
16105 17:01:28.652725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
16107 17:01:28.688996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
16109 17:01:28.689458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
16110 17:01:28.725997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
16111 17:01:28.726440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
16113 17:01:28.761672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass>
16114 17:01:28.762103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_944 RESULT=pass
16116 17:01:28.797851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
16117 17:01:28.798295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
16119 17:01:28.833896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
16121 17:01:28.834358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
16122 17:01:28.870053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
16124 17:01:28.870504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
16125 17:01:28.907441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass>
16126 17:01:28.907882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_960 RESULT=pass
16128 17:01:28.944463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
16129 17:01:28.944903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
16131 17:01:28.980667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
16133 17:01:28.981141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
16134 17:01:29.013670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
16135 17:01:29.014113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
16137 17:01:29.048867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass
16139 17:01:29.049244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_976 RESULT=pass>
16140 17:01:29.083354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
16141 17:01:29.083833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
16143 17:01:29.117892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
16145 17:01:29.118360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
16146 17:01:29.152000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
16148 17:01:29.152634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
16149 17:01:29.185864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass>
16150 17:01:29.186353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_992 RESULT=pass
16152 17:01:29.220084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
16153 17:01:29.220580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
16155 17:01:29.254257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
16157 17:01:29.254837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
16158 17:01:29.288562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
16160 17:01:29.289142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
16161 17:01:29.323334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass
16163 17:01:29.323884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1008 RESULT=pass>
16164 17:01:29.357938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
16166 17:01:29.358483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
16167 17:01:29.392197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
16168 17:01:29.392620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
16170 17:01:29.426693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
16172 17:01:29.427203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
16173 17:01:29.461005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass>
16174 17:01:29.461427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1024 RESULT=pass
16176 17:01:29.496647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
16178 17:01:29.497218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
16179 17:01:29.532399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
16181 17:01:29.533047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
16182 17:01:29.566092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
16183 17:01:29.566561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
16185 17:01:29.600078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass>
16186 17:01:29.600565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1040 RESULT=pass
16188 17:01:29.633434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
16189 17:01:29.633933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
16191 17:01:29.666905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
16192 17:01:29.667373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
16194 17:01:29.700390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
16195 17:01:29.700885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
16197 17:01:29.733371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass>
16198 17:01:29.733857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1056 RESULT=pass
16200 17:01:29.766808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
16202 17:01:29.767369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
16203 17:01:29.800239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
16204 17:01:29.800742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
16206 17:01:29.833263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
16207 17:01:29.833702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
16209 17:01:29.868051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass>
16210 17:01:29.868528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1072 RESULT=pass
16212 17:01:29.901876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
16213 17:01:29.902364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
16215 17:01:29.936489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
16216 17:01:29.936985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
16218 17:01:29.969904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
16220 17:01:29.970466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
16221 17:01:30.002814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass>
16222 17:01:30.003288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1088 RESULT=pass
16224 17:01:30.035500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
16225 17:01:30.035979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
16227 17:01:30.068830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
16228 17:01:30.069325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
16230 17:01:30.101889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
16231 17:01:30.102366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
16233 17:01:30.135402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass>
16234 17:01:30.135881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1104 RESULT=pass
16236 17:01:30.170331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
16238 17:01:30.170784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
16239 17:01:30.207400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
16241 17:01:30.207874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
16242 17:01:30.245011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
16243 17:01:30.245501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
16245 17:01:30.284882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass
16247 17:01:30.285699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1120 RESULT=pass>
16248 17:01:30.324899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
16249 17:01:30.325404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
16251 17:01:30.366782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
16252 17:01:30.367325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
16254 17:01:30.403949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
16255 17:01:30.404396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
16257 17:01:30.437635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass>
16258 17:01:30.438090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1136 RESULT=pass
16260 17:01:30.470785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
16262 17:01:30.471252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
16263 17:01:30.503077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
16264 17:01:30.503570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
16266 17:01:30.536683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
16267 17:01:30.537189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
16269 17:01:30.570463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass>
16270 17:01:30.570933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1152 RESULT=pass
16272 17:01:30.604465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
16273 17:01:30.604939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
16275 17:01:30.638700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
16276 17:01:30.639134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
16278 17:01:30.672674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
16280 17:01:30.673291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
16281 17:01:30.705512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass>
16282 17:01:30.705998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1168 RESULT=pass
16284 17:01:30.739076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
16285 17:01:30.739500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
16287 17:01:30.772858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
16289 17:01:30.773334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
16290 17:01:30.806030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
16291 17:01:30.806456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
16293 17:01:30.839228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass
16295 17:01:30.839699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1184 RESULT=pass>
16296 17:01:30.873569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
16297 17:01:30.874026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
16299 17:01:30.908632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
16301 17:01:30.909290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
16302 17:01:30.943260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
16303 17:01:30.943717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
16305 17:01:30.978570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass>
16306 17:01:30.978993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1200 RESULT=pass
16308 17:01:31.012073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
16309 17:01:31.012509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
16311 17:01:31.043813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
16313 17:01:31.044284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
16314 17:01:31.077681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
16315 17:01:31.078180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
16317 17:01:31.112153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass>
16318 17:01:31.112655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1216 RESULT=pass
16320 17:01:31.146619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
16321 17:01:31.147110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
16323 17:01:31.180234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
16324 17:01:31.180748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
16326 17:01:31.214878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
16328 17:01:31.215338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
16329 17:01:31.252685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass
16331 17:01:31.253151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1232 RESULT=pass>
16332 17:01:31.289665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
16334 17:01:31.290124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
16335 17:01:31.326891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
16337 17:01:31.327356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
16338 17:01:31.362758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
16339 17:01:31.363203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
16341 17:01:31.398248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass>
16342 17:01:31.398680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1248 RESULT=pass
16344 17:01:31.433955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
16345 17:01:31.434394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
16347 17:01:31.470292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
16349 17:01:31.471013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
16350 17:01:31.505586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
16351 17:01:31.505985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
16353 17:01:31.542562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass
16355 17:01:31.543158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1264 RESULT=pass>
16356 17:01:31.581258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
16358 17:01:31.581903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
16359 17:01:31.617690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
16360 17:01:31.618169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
16362 17:01:31.653446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
16364 17:01:31.653918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
16365 17:01:31.688315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass>
16366 17:01:31.688801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1280 RESULT=pass
16368 17:01:31.727279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
16369 17:01:31.727767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
16371 17:01:31.769291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
16372 17:01:31.769847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
16374 17:01:31.825913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
16375 17:01:31.826365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
16377 17:01:31.883556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass
16379 17:01:31.884031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1296 RESULT=pass>
16380 17:01:31.933919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
16381 17:01:31.934328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
16383 17:01:31.969229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
16384 17:01:31.969624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
16386 17:01:32.006153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
16388 17:01:32.006609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
16389 17:01:32.046755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass
16391 17:01:32.047310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1312 RESULT=pass>
16392 17:01:32.094717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
16393 17:01:32.095079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
16395 17:01:32.138505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
16396 17:01:32.138905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
16398 17:01:32.177499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
16399 17:01:32.177928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
16401 17:01:32.215558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass>
16402 17:01:32.215979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1328 RESULT=pass
16404 17:01:32.255868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
16406 17:01:32.256338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
16407 17:01:32.289972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
16408 17:01:32.290389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
16410 17:01:32.323428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
16412 17:01:32.324005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
16413 17:01:32.357354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass>
16414 17:01:32.357780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1344 RESULT=pass
16416 17:01:32.390745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
16417 17:01:32.391167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
16419 17:01:32.425971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
16421 17:01:32.426447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
16422 17:01:32.461295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
16423 17:01:32.461674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
16425 17:01:32.496421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass
16427 17:01:32.496896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1360 RESULT=pass>
16428 17:01:32.531282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
16429 17:01:32.531706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
16431 17:01:32.565703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
16433 17:01:32.566078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
16434 17:01:32.599837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
16436 17:01:32.600203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
16437 17:01:32.633324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass>
16438 17:01:32.633747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1376 RESULT=pass
16440 17:01:32.667299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
16441 17:01:32.667710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
16443 17:01:32.713465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
16444 17:01:32.713912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
16446 17:01:32.749714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
16448 17:01:32.750167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
16449 17:01:32.786243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass>
16450 17:01:32.786711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1392 RESULT=pass
16452 17:01:32.822639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
16453 17:01:32.823136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
16455 17:01:32.857458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
16456 17:01:32.857961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
16458 17:01:32.890581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
16459 17:01:32.891026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
16461 17:01:32.923510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass
16463 17:01:32.923969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1408 RESULT=pass>
16464 17:01:32.957271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
16465 17:01:32.957682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
16467 17:01:32.993917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
16468 17:01:32.994410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
16470 17:01:33.033714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
16471 17:01:33.034119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
16473 17:01:33.074146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass
16475 17:01:33.074584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1424 RESULT=pass>
16476 17:01:33.111053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
16477 17:01:33.111471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
16479 17:01:33.143203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
16481 17:01:33.143675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
16482 17:01:33.175945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
16484 17:01:33.176372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
16485 17:01:33.214079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass>
16486 17:01:33.214521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1440 RESULT=pass
16488 17:01:33.254807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
16489 17:01:33.255197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
16491 17:01:33.311203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
16493 17:01:33.311914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
16494 17:01:33.356679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
16496 17:01:33.357128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
16497 17:01:33.398534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass
16499 17:01:33.398991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1456 RESULT=pass>
16500 17:01:33.433247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
16501 17:01:33.433673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
16503 17:01:33.469151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
16505 17:01:33.469597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
16506 17:01:33.517540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
16507 17:01:33.517975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
16509 17:01:33.557153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass>
16510 17:01:33.557604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1472 RESULT=pass
16512 17:01:33.595905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
16514 17:01:33.596389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
16515 17:01:33.633342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
16517 17:01:33.633968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
16518 17:01:33.673247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
16520 17:01:33.673730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
16521 17:01:33.710409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass
16523 17:01:33.710872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1488 RESULT=pass>
16524 17:01:33.746132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
16525 17:01:33.746557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
16527 17:01:33.785449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
16528 17:01:33.785886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
16530 17:01:33.824770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
16531 17:01:33.825229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
16533 17:01:33.877538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass>
16534 17:01:33.877980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1504 RESULT=pass
16536 17:01:33.928439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
16538 17:01:33.928918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
16539 17:01:33.969625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
16541 17:01:33.970029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
16542 17:01:34.023333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
16543 17:01:34.023789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
16545 17:01:34.070392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass>
16546 17:01:34.070823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1520 RESULT=pass
16548 17:01:34.110462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
16549 17:01:34.110913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
16551 17:01:34.153763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
16552 17:01:34.154175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
16554 17:01:34.193373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
16555 17:01:34.193804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
16557 17:01:34.231076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass>
16558 17:01:34.231513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1536 RESULT=pass
16560 17:01:34.266985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
16561 17:01:34.267415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
16563 17:01:34.303450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
16565 17:01:34.304064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
16566 17:01:34.341341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
16567 17:01:34.341779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
16569 17:01:34.376374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass
16571 17:01:34.377830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1552 RESULT=pass>
16572 17:01:34.413812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
16574 17:01:34.414402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
16575 17:01:34.466970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
16576 17:01:34.467467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
16578 17:01:34.505164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
16579 17:01:34.505569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
16581 17:01:34.540271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass>
16582 17:01:34.540728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1568 RESULT=pass
16584 17:01:34.574983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
16586 17:01:34.575388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
16587 17:01:34.610093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
16588 17:01:34.610529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
16590 17:01:34.644793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
16592 17:01:34.645313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
16593 17:01:34.680610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass
16595 17:01:34.681124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1584 RESULT=pass>
16596 17:01:34.714838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
16597 17:01:34.715256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
16599 17:01:34.758113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
16600 17:01:34.758525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
16602 17:01:34.801892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
16603 17:01:34.802344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
16605 17:01:34.838648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass>
16606 17:01:34.839011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1600 RESULT=pass
16608 17:01:34.880959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
16609 17:01:34.881353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
16611 17:01:34.937051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
16613 17:01:34.937484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
16614 17:01:34.991801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
16616 17:01:34.992524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
16617 17:01:35.036945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass>
16618 17:01:35.037341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1616 RESULT=pass
16620 17:01:35.071944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
16622 17:01:35.072415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
16623 17:01:35.106975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
16624 17:01:35.107416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
16626 17:01:35.142046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
16628 17:01:35.142659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
16629 17:01:35.175178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass>
16630 17:01:35.175667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1632 RESULT=pass
16632 17:01:35.212697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
16633 17:01:35.213125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
16635 17:01:35.250024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
16637 17:01:35.250493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
16638 17:01:35.288598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
16639 17:01:35.289007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
16641 17:01:35.326626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass>
16642 17:01:35.327056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1648 RESULT=pass
16644 17:01:35.364319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
16645 17:01:35.364768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
16647 17:01:35.404892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
16648 17:01:35.405271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
16650 17:01:35.463326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
16651 17:01:35.463811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
16653 17:01:35.524775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass
16655 17:01:35.525283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1664 RESULT=pass>
16656 17:01:35.579392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
16657 17:01:35.579789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
16659 17:01:35.636848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
16661 17:01:35.637605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
16662 17:01:35.686300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
16663 17:01:35.686740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
16665 17:01:35.723700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass
16667 17:01:35.724160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1680 RESULT=pass>
16668 17:01:35.758255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
16669 17:01:35.758705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
16671 17:01:35.793310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
16673 17:01:35.793764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
16674 17:01:35.828099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
16675 17:01:35.828538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
16677 17:01:35.861133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass>
16678 17:01:35.861616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1696 RESULT=pass
16680 17:01:35.894823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
16681 17:01:35.895311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
16683 17:01:35.930337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
16685 17:01:35.930906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
16686 17:01:35.965586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
16688 17:01:35.966085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
16689 17:01:36.001102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass>
16690 17:01:36.001600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1712 RESULT=pass
16692 17:01:36.036121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
16693 17:01:36.036604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
16695 17:01:36.069798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
16696 17:01:36.070279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
16698 17:01:36.104295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
16699 17:01:36.104750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
16701 17:01:36.138157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass>
16702 17:01:36.138591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1728 RESULT=pass
16704 17:01:36.173088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
16706 17:01:36.173538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
16707 17:01:36.207895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
16709 17:01:36.208361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
16710 17:01:36.242942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
16712 17:01:36.243554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
16713 17:01:36.278418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass>
16714 17:01:36.278891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1744 RESULT=pass
16716 17:01:36.313657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
16717 17:01:36.314109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
16719 17:01:36.349011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
16721 17:01:36.349603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
16722 17:01:36.384585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
16723 17:01:36.385014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
16725 17:01:36.419808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass
16727 17:01:36.420423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1760 RESULT=pass>
16728 17:01:36.455967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
16730 17:01:36.456413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
16731 17:01:36.491954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
16733 17:01:36.492385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
16734 17:01:36.528670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
16736 17:01:36.529252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
16737 17:01:36.564676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass>
16738 17:01:36.565124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1776 RESULT=pass
16740 17:01:36.602947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
16741 17:01:36.603390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
16743 17:01:36.656046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
16745 17:01:36.656524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
16746 17:01:36.702885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
16747 17:01:36.703310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
16749 17:01:36.752990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass>
16750 17:01:36.753463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1792 RESULT=pass
16752 17:01:36.795618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
16754 17:01:36.796089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
16755 17:01:36.834561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
16757 17:01:36.835223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
16758 17:01:36.881452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
16760 17:01:36.881944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
16761 17:01:36.925987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass>
16762 17:01:36.926472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1808 RESULT=pass
16764 17:01:36.974068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
16765 17:01:36.974627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
16767 17:01:37.015230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
16769 17:01:37.015858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
16770 17:01:37.059042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
16771 17:01:37.059591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
16773 17:01:37.110307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass>
16774 17:01:37.110788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1824 RESULT=pass
16776 17:01:37.168989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
16778 17:01:37.169638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
16779 17:01:37.216207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
16780 17:01:37.216656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
16782 17:01:37.259113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
16783 17:01:37.259536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
16785 17:01:37.311745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass
16787 17:01:37.312467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1840 RESULT=pass>
16788 17:01:37.361455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
16789 17:01:37.361944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
16791 17:01:37.399068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
16792 17:01:37.399492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
16794 17:01:37.440987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
16795 17:01:37.441486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
16797 17:01:37.479054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass>
16798 17:01:37.479624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1856 RESULT=pass
16800 17:01:37.517494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
16801 17:01:37.517998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
16803 17:01:37.555166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
16805 17:01:37.555920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
16806 17:01:37.594332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
16807 17:01:37.594756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
16809 17:01:37.632330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass>
16810 17:01:37.632744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1872 RESULT=pass
16812 17:01:37.670406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
16813 17:01:37.670826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
16815 17:01:37.707318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
16817 17:01:37.707796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
16818 17:01:37.747769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
16820 17:01:37.748607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
16821 17:01:37.791800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass
16823 17:01:37.792299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1888 RESULT=pass>
16824 17:01:37.835977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
16826 17:01:37.836438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
16827 17:01:37.878619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
16828 17:01:37.879036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
16830 17:01:37.922255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
16831 17:01:37.922692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
16833 17:01:37.962539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass>
16834 17:01:37.962991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1904 RESULT=pass
16836 17:01:38.017392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
16837 17:01:38.017823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
16839 17:01:38.069142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
16840 17:01:38.069566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
16842 17:01:38.126925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
16843 17:01:38.127329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
16845 17:01:38.173442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass
16847 17:01:38.173893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1920 RESULT=pass>
16848 17:01:38.216679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
16850 17:01:38.217143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
16851 17:01:38.255354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
16852 17:01:38.255904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
16854 17:01:38.297274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
16856 17:01:38.297873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
16857 17:01:38.334530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass
16859 17:01:38.335093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1936 RESULT=pass>
16860 17:01:38.371925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
16862 17:01:38.372484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
16863 17:01:38.410241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
16864 17:01:38.410666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
16866 17:01:38.445304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
16867 17:01:38.445754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
16869 17:01:38.486212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass
16871 17:01:38.486680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1952 RESULT=pass>
16872 17:01:38.530988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
16873 17:01:38.531496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
16875 17:01:38.571291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
16876 17:01:38.571859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
16878 17:01:38.628348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
16879 17:01:38.628773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
16881 17:01:38.670592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass>
16882 17:01:38.671019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1968 RESULT=pass
16884 17:01:38.718758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
16886 17:01:38.719224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
16887 17:01:38.765000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
16888 17:01:38.765408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
16890 17:01:38.805907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
16891 17:01:38.806297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
16893 17:01:38.846418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass>
16894 17:01:38.846860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_1984 RESULT=pass
16896 17:01:38.884668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
16897 17:01:38.885115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
16899 17:01:38.921398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
16900 17:01:38.921819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
16902 17:01:38.959960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
16904 17:01:38.960996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
16905 17:01:38.999579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass
16907 17:01:39.000191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2000 RESULT=pass>
16908 17:01:39.038182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
16910 17:01:39.038949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
16911 17:01:39.076454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
16912 17:01:39.076961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
16914 17:01:39.116901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
16916 17:01:39.117368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
16917 17:01:39.157517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass>
16918 17:01:39.157969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2016 RESULT=pass
16920 17:01:39.192296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
16921 17:01:39.192769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
16923 17:01:39.239266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
16924 17:01:39.239757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
16926 17:01:39.284590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
16927 17:01:39.285029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
16929 17:01:39.322265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass>
16930 17:01:39.322694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2032 RESULT=pass
16932 17:01:39.363523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
16934 17:01:39.364006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
16935 17:01:39.400616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
16936 17:01:39.401048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
16938 17:01:39.437271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
16939 17:01:39.437691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
16941 17:01:39.482054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass>
16942 17:01:39.482503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2048 RESULT=pass
16944 17:01:39.525838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
16945 17:01:39.526270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
16947 17:01:39.570699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
16949 17:01:39.571168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
16950 17:01:39.616443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
16952 17:01:39.616915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
16953 17:01:39.664580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass>
16954 17:01:39.665040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2064 RESULT=pass
16956 17:01:39.702160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
16957 17:01:39.702589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
16959 17:01:39.738193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
16960 17:01:39.738752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
16962 17:01:39.774217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
16964 17:01:39.774595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
16965 17:01:39.809984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass
16967 17:01:39.810745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2080 RESULT=pass>
16968 17:01:39.850919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
16970 17:01:39.851576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
16971 17:01:39.886892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
16972 17:01:39.887327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
16974 17:01:39.926312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
16975 17:01:39.926813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
16977 17:01:39.963897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass
16979 17:01:39.964533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2096 RESULT=pass>
16980 17:01:40.000973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
16981 17:01:40.001401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
16983 17:01:40.045984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
16984 17:01:40.046411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
16986 17:01:40.090801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
16987 17:01:40.091233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
16989 17:01:40.126053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass>
16990 17:01:40.126521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2112 RESULT=pass
16992 17:01:40.160959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
16993 17:01:40.161426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
16995 17:01:40.205714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
16997 17:01:40.206374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
16998 17:01:40.243534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
17000 17:01:40.244010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
17001 17:01:40.278495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass
17003 17:01:40.279074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2128 RESULT=pass>
17004 17:01:40.321867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
17005 17:01:40.322418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
17007 17:01:40.361323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
17009 17:01:40.361851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
17010 17:01:40.406088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
17011 17:01:40.406519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
17013 17:01:40.449425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass
17015 17:01:40.449912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2144 RESULT=pass>
17016 17:01:40.499740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
17017 17:01:40.500195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
17019 17:01:40.553855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
17020 17:01:40.554289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
17022 17:01:40.603477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
17023 17:01:40.603879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
17025 17:01:40.661889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass
17027 17:01:40.662366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2160 RESULT=pass>
17028 17:01:40.704866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
17030 17:01:40.705370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
17031 17:01:40.741445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
17032 17:01:40.741889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
17034 17:01:40.783009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
17036 17:01:40.783499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
17037 17:01:40.823568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass
17039 17:01:40.824048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2176 RESULT=pass>
17040 17:01:40.861707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
17041 17:01:40.862092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
17043 17:01:40.903345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
17044 17:01:40.903793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
17046 17:01:40.946912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
17048 17:01:40.947675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
17049 17:01:40.991321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass>
17050 17:01:40.991832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2192 RESULT=pass
17052 17:01:41.034838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
17053 17:01:41.035397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
17055 17:01:41.086796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
17056 17:01:41.087215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
17058 17:01:41.126618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
17059 17:01:41.127017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
17061 17:01:41.170122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass>
17062 17:01:41.170589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2208 RESULT=pass
17064 17:01:41.220478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
17065 17:01:41.220895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
17067 17:01:41.270074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
17069 17:01:41.270565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
17070 17:01:41.315596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
17072 17:01:41.316080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
17073 17:01:41.372396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass>
17074 17:01:41.372861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2224 RESULT=pass
17076 17:01:41.410633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
17078 17:01:41.411004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
17079 17:01:41.450708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
17080 17:01:41.451219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
17082 17:01:41.490528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
17083 17:01:41.491021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
17085 17:01:41.527455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass>
17086 17:01:41.527931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2240 RESULT=pass
17088 17:01:41.567435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
17089 17:01:41.567942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
17091 17:01:41.605364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
17092 17:01:41.605799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
17094 17:01:41.643273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
17095 17:01:41.643702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
17097 17:01:41.685340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass
17099 17:01:41.685834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2256 RESULT=pass>
17100 17:01:41.737119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
17101 17:01:41.737525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
17103 17:01:41.780884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
17104 17:01:41.781425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
17106 17:01:41.827032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
17108 17:01:41.827554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
17109 17:01:41.877711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass
17111 17:01:41.878182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2272 RESULT=pass>
17112 17:01:41.932495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
17114 17:01:41.932967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
17115 17:01:41.986952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
17116 17:01:41.987335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
17118 17:01:42.042076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
17120 17:01:42.042553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
17121 17:01:42.098038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass
17123 17:01:42.098414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2288 RESULT=pass>
17124 17:01:42.153384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
17126 17:01:42.153847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
17127 17:01:42.206815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
17128 17:01:42.207251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
17130 17:01:42.262739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
17132 17:01:42.263203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
17133 17:01:42.310798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass>
17134 17:01:42.311254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2304 RESULT=pass
17136 17:01:42.350413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
17137 17:01:42.350853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
17139 17:01:42.390461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
17140 17:01:42.390913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
17142 17:01:42.428672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
17143 17:01:42.429201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
17145 17:01:42.470854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass>
17146 17:01:42.471273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2320 RESULT=pass
17148 17:01:42.510163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
17149 17:01:42.510584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
17151 17:01:42.549290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
17153 17:01:42.549749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
17154 17:01:42.586861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
17155 17:01:42.587297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
17157 17:01:42.625214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass
17159 17:01:42.625702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2336 RESULT=pass>
17160 17:01:42.664725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
17161 17:01:42.665154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
17163 17:01:42.702312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
17164 17:01:42.702871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
17166 17:01:42.745501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
17167 17:01:42.745932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
17169 17:01:42.793228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass
17171 17:01:42.793691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2352 RESULT=pass>
17172 17:01:42.853616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
17173 17:01:42.854062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
17175 17:01:42.914447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
17176 17:01:42.914863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
17178 17:01:42.962325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
17180 17:01:42.962775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
17181 17:01:43.018718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass
17183 17:01:43.019173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2368 RESULT=pass>
17184 17:01:43.087343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
17185 17:01:43.087745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
17187 17:01:43.134543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
17188 17:01:43.134974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
17190 17:01:43.176556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
17191 17:01:43.176985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
17193 17:01:43.221405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass>
17194 17:01:43.221864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2384 RESULT=pass
17196 17:01:43.262303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
17198 17:01:43.262757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
17199 17:01:43.302306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
17200 17:01:43.302729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
17202 17:01:43.351798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
17204 17:01:43.352404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
17205 17:01:43.410840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass
17207 17:01:43.411307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2400 RESULT=pass>
17208 17:01:43.467577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
17209 17:01:43.468005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
17211 17:01:43.526644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
17212 17:01:43.527099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
17214 17:01:43.582068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
17215 17:01:43.582486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
17217 17:01:43.627027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass>
17218 17:01:43.627420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2416 RESULT=pass
17220 17:01:43.664867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
17221 17:01:43.665252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
17223 17:01:43.703022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
17224 17:01:43.703443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
17226 17:01:43.753420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
17227 17:01:43.753863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
17229 17:01:43.808922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass>
17230 17:01:43.809359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2432 RESULT=pass
17232 17:01:43.862886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
17234 17:01:43.863347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
17235 17:01:43.913243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
17236 17:01:43.913698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
17238 17:01:43.956276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
17239 17:01:43.956663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
17241 17:01:43.997307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass>
17242 17:01:43.997686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2448 RESULT=pass
17244 17:01:44.043391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
17245 17:01:44.043836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
17247 17:01:44.091448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
17249 17:01:44.092190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
17250 17:01:44.134838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
17251 17:01:44.135264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
17253 17:01:44.182779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass>
17254 17:01:44.183161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2464 RESULT=pass
17256 17:01:44.229431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
17258 17:01:44.230056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
17259 17:01:44.270585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
17261 17:01:44.271283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
17262 17:01:44.308649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
17263 17:01:44.309212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
17265 17:01:44.358460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass>
17266 17:01:44.358866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2480 RESULT=pass
17268 17:01:44.405329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
17269 17:01:44.405745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
17271 17:01:44.448513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
17273 17:01:44.448994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
17274 17:01:44.488800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
17275 17:01:44.489238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
17277 17:01:44.528548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass>
17278 17:01:44.529036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2496 RESULT=pass
17280 17:01:44.567361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
17281 17:01:44.567774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
17283 17:01:44.603515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
17284 17:01:44.603944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
17286 17:01:44.642682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
17287 17:01:44.643115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
17289 17:01:44.686955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass
17291 17:01:44.687411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2512 RESULT=pass>
17292 17:01:44.731873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
17294 17:01:44.732335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
17295 17:01:44.770009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
17297 17:01:44.770451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
17298 17:01:44.810486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
17300 17:01:44.810959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
17301 17:01:44.848466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass
17303 17:01:44.848920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2528 RESULT=pass>
17304 17:01:44.885910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
17305 17:01:44.886336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
17307 17:01:44.926909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
17309 17:01:44.927368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
17310 17:01:44.966598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
17312 17:01:44.967052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
17313 17:01:45.006018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass
17315 17:01:45.006458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2544 RESULT=pass>
17316 17:01:45.044800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
17318 17:01:45.045275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
17319 17:01:45.082674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
17320 17:01:45.083091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
17322 17:01:45.122729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
17323 17:01:45.123153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
17325 17:01:45.161420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass>
17326 17:01:45.161833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2560 RESULT=pass
17328 17:01:45.198402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
17329 17:01:45.198831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
17331 17:01:45.236665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
17333 17:01:45.237126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
17334 17:01:45.273377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
17335 17:01:45.273779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
17337 17:01:45.311368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass>
17338 17:01:45.311799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2576 RESULT=pass
17340 17:01:45.350751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
17342 17:01:45.351220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
17343 17:01:45.390725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
17345 17:01:45.391192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
17346 17:01:45.430854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
17348 17:01:45.431325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
17349 17:01:45.470261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass>
17350 17:01:45.470704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2592 RESULT=pass
17352 17:01:45.509725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
17353 17:01:45.510135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
17355 17:01:45.547285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
17357 17:01:45.547761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
17358 17:01:45.585478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
17359 17:01:45.585908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
17361 17:01:45.624743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass>
17362 17:01:45.625173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2608 RESULT=pass
17364 17:01:45.662083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
17365 17:01:45.662498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
17367 17:01:45.699252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
17368 17:01:45.699682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
17370 17:01:45.737959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
17372 17:01:45.738427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
17373 17:01:45.776419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass>
17374 17:01:45.776872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2624 RESULT=pass
17376 17:01:45.815093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
17378 17:01:45.815566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
17379 17:01:45.852677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
17380 17:01:45.853156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
17382 17:01:45.889926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
17383 17:01:45.890390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
17385 17:01:45.925789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass>
17386 17:01:45.926357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2640 RESULT=pass
17388 17:01:45.963110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
17389 17:01:45.963558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
17391 17:01:46.012508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
17392 17:01:46.012939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
17394 17:01:46.055496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
17395 17:01:46.055896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
17397 17:01:46.097361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass
17399 17:01:46.098072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2656 RESULT=pass>
17400 17:01:46.137398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
17401 17:01:46.137890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
17403 17:01:46.176663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
17404 17:01:46.177106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
17406 17:01:46.214066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
17407 17:01:46.214515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
17409 17:01:46.250357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass
17411 17:01:46.250824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2672 RESULT=pass>
17412 17:01:46.286119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
17414 17:01:46.286870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
17415 17:01:46.322359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
17416 17:01:46.322751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
17418 17:01:46.359217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
17419 17:01:46.359767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
17421 17:01:46.396277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass>
17422 17:01:46.396773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2688 RESULT=pass
17424 17:01:46.431290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
17425 17:01:46.431737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
17427 17:01:46.469779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
17429 17:01:46.470237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
17430 17:01:46.507113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
17431 17:01:46.507515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
17433 17:01:46.544718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass
17435 17:01:46.545381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2704 RESULT=pass>
17436 17:01:46.586628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
17437 17:01:46.587171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
17439 17:01:46.627457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
17441 17:01:46.628035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
17442 17:01:46.670290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
17444 17:01:46.670764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
17445 17:01:46.725740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass>
17446 17:01:46.726230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2720 RESULT=pass
17448 17:01:46.775493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
17449 17:01:46.776002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
17451 17:01:46.814867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
17452 17:01:46.815293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
17454 17:01:46.854888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
17455 17:01:46.855318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
17457 17:01:46.893527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass
17459 17:01:46.894006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2736 RESULT=pass>
17460 17:01:46.929921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
17461 17:01:46.930342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
17463 17:01:46.967813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
17465 17:01:46.968240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
17466 17:01:47.005365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
17468 17:01:47.005843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
17469 17:01:47.042720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass>
17470 17:01:47.043196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2752 RESULT=pass
17472 17:01:47.079264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
17474 17:01:47.079749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
17475 17:01:47.122553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
17476 17:01:47.122944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
17478 17:01:47.162707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
17480 17:01:47.163120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
17481 17:01:47.200523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass>
17482 17:01:47.200953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2768 RESULT=pass
17484 17:01:47.237378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
17485 17:01:47.237796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
17487 17:01:47.274352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
17489 17:01:47.274820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
17490 17:01:47.311348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
17492 17:01:47.311831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
17493 17:01:47.348755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass>
17494 17:01:47.349195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2784 RESULT=pass
17496 17:01:47.386120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
17497 17:01:47.386575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
17499 17:01:47.426844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
17500 17:01:47.427329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
17502 17:01:47.466681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
17503 17:01:47.467169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
17505 17:01:47.507320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass>
17506 17:01:47.507807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2800 RESULT=pass
17508 17:01:47.546527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
17509 17:01:47.546969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
17511 17:01:47.585944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
17513 17:01:47.586435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
17514 17:01:47.629353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
17516 17:01:47.629842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
17517 17:01:47.666685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass>
17518 17:01:47.667105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2816 RESULT=pass
17520 17:01:47.718198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
17521 17:01:47.718656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
17523 17:01:47.781562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
17525 17:01:47.782067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
17526 17:01:47.820823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
17528 17:01:47.821294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
17529 17:01:47.857426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass>
17530 17:01:47.857889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2832 RESULT=pass
17532 17:01:47.894429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
17534 17:01:47.894902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
17535 17:01:47.930918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
17537 17:01:47.931383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
17538 17:01:47.967876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
17540 17:01:47.968352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
17541 17:01:48.005579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass
17543 17:01:48.006412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2848 RESULT=pass>
17544 17:01:48.042994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
17545 17:01:48.043462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
17547 17:01:48.095288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
17549 17:01:48.095930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
17550 17:01:48.154022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
17552 17:01:48.154492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
17553 17:01:48.210843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass>
17554 17:01:48.211297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2864 RESULT=pass
17556 17:01:48.265448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
17557 17:01:48.265903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
17559 17:01:48.305288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
17561 17:01:48.305735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
17562 17:01:48.344421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
17563 17:01:48.344860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
17565 17:01:48.383079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass
17567 17:01:48.383542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2880 RESULT=pass>
17568 17:01:48.421119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
17569 17:01:48.421564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
17571 17:01:48.461512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
17572 17:01:48.461906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
17574 17:01:48.497157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
17575 17:01:48.497637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
17577 17:01:48.539181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass>
17578 17:01:48.539632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2896 RESULT=pass
17580 17:01:48.576951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
17581 17:01:48.577376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
17583 17:01:48.614648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
17585 17:01:48.615112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
17586 17:01:48.670346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
17587 17:01:48.670735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
17589 17:01:48.725725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass>
17590 17:01:48.726189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2912 RESULT=pass
17592 17:01:48.767819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
17594 17:01:48.768434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
17595 17:01:48.805637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
17596 17:01:48.806062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
17598 17:01:48.842956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
17599 17:01:48.843375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
17601 17:01:48.881066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass>
17602 17:01:48.881487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2928 RESULT=pass
17604 17:01:48.917528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
17605 17:01:48.918039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
17607 17:01:48.951751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
17609 17:01:48.952424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
17610 17:01:48.996505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
17611 17:01:48.996981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
17613 17:01:49.033694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass>
17614 17:01:49.034253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2944 RESULT=pass
17616 17:01:49.069946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
17617 17:01:49.070387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
17619 17:01:49.108905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
17620 17:01:49.109391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
17622 17:01:49.145162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
17623 17:01:49.145668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
17625 17:01:49.181855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass>
17626 17:01:49.182345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2960 RESULT=pass
17628 17:01:49.217953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
17629 17:01:49.218441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
17631 17:01:49.259489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
17633 17:01:49.260047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
17634 17:01:49.297359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
17635 17:01:49.297840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
17637 17:01:49.340596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass>
17638 17:01:49.341089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2976 RESULT=pass
17640 17:01:49.382879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
17641 17:01:49.383379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
17643 17:01:49.426541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
17644 17:01:49.427031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
17646 17:01:49.462964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
17647 17:01:49.463411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
17649 17:01:49.500232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass
17651 17:01:49.500688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_2992 RESULT=pass>
17652 17:01:49.541182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
17653 17:01:49.541675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
17655 17:01:49.588760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
17656 17:01:49.589170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
17658 17:01:49.624537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
17659 17:01:49.624987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
17661 17:01:49.661317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass>
17662 17:01:49.661681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3008 RESULT=pass
17664 17:01:49.697060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
17665 17:01:49.697554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
17667 17:01:49.732670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
17668 17:01:49.733163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
17670 17:01:49.768607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
17671 17:01:49.769022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
17673 17:01:49.809485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass
17675 17:01:49.809924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3024 RESULT=pass>
17676 17:01:49.844929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
17677 17:01:49.845345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
17679 17:01:49.881185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
17680 17:01:49.881598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
17682 17:01:49.915903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
17684 17:01:49.916361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
17685 17:01:49.954822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass
17687 17:01:49.955419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3040 RESULT=pass>
17688 17:01:49.990223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
17690 17:01:49.990682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
17691 17:01:50.025584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
17692 17:01:50.026023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
17694 17:01:50.075408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
17695 17:01:50.075899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
17697 17:01:50.115156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass>
17698 17:01:50.115640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3056 RESULT=pass
17700 17:01:50.150782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
17701 17:01:50.151254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
17703 17:01:50.187918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
17705 17:01:50.188353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
17706 17:01:50.224333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
17707 17:01:50.224756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
17709 17:01:50.259948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass
17711 17:01:50.260414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3072 RESULT=pass>
17712 17:01:50.295719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
17714 17:01:50.296193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
17715 17:01:50.330877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
17716 17:01:50.331312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
17718 17:01:50.365836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
17720 17:01:50.366262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
17721 17:01:50.400827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass>
17722 17:01:50.401268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3088 RESULT=pass
17724 17:01:50.436901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
17726 17:01:50.437361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
17727 17:01:50.472288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
17728 17:01:50.472831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
17730 17:01:50.508859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
17731 17:01:50.509239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
17733 17:01:50.551445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass>
17734 17:01:50.551865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3104 RESULT=pass
17736 17:01:50.590522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
17737 17:01:50.591018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
17739 17:01:50.633906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
17740 17:01:50.634424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
17742 17:01:50.680312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
17743 17:01:50.680844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
17745 17:01:50.717839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass>
17746 17:01:50.718239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3120 RESULT=pass
17748 17:01:50.752741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
17749 17:01:50.753237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
17751 17:01:50.788358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
17752 17:01:50.788839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
17754 17:01:50.824684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
17755 17:01:50.825168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
17757 17:01:50.859437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass
17759 17:01:50.860004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3136 RESULT=pass>
17760 17:01:50.893383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
17761 17:01:50.893889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
17763 17:01:50.928864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
17764 17:01:50.929382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
17766 17:01:50.964934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
17768 17:01:50.965380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
17769 17:01:51.000393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass
17771 17:01:51.000853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3152 RESULT=pass>
17772 17:01:51.035259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
17773 17:01:51.035687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
17775 17:01:51.070379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
17776 17:01:51.070798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
17778 17:01:51.105272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
17780 17:01:51.105745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
17781 17:01:51.140686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass>
17782 17:01:51.141189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3168 RESULT=pass
17784 17:01:51.176246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
17786 17:01:51.176887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
17787 17:01:51.210308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
17788 17:01:51.210730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
17790 17:01:51.246405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
17792 17:01:51.246867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
17793 17:01:51.281857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass
17795 17:01:51.282309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3184 RESULT=pass>
17796 17:01:51.317166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
17797 17:01:51.317588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
17799 17:01:51.351144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
17800 17:01:51.351571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
17802 17:01:51.386603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
17804 17:01:51.387252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
17805 17:01:51.421519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass>
17806 17:01:51.421957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3200 RESULT=pass
17808 17:01:51.455658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
17810 17:01:51.456261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
17811 17:01:51.499799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
17813 17:01:51.500260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
17814 17:01:51.535186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
17815 17:01:51.535602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
17817 17:01:51.570607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass>
17818 17:01:51.571100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3216 RESULT=pass
17820 17:01:51.605532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
17821 17:01:51.606003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
17823 17:01:51.641728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
17825 17:01:51.642374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
17826 17:01:51.677392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
17828 17:01:51.677986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
17829 17:01:51.712308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass>
17830 17:01:51.712758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3232 RESULT=pass
17832 17:01:51.747367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
17833 17:01:51.747809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
17835 17:01:51.782309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
17836 17:01:51.782706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
17838 17:01:51.817074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
17839 17:01:51.817497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
17841 17:01:51.852394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass>
17842 17:01:51.852876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3248 RESULT=pass
17844 17:01:51.886241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
17845 17:01:51.886711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
17847 17:01:51.921427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
17848 17:01:51.921914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
17850 17:01:51.962679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
17851 17:01:51.963121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
17853 17:01:51.997131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass>
17854 17:01:51.997637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3264 RESULT=pass
17856 17:01:52.032184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
17857 17:01:52.032628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
17859 17:01:52.067512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
17861 17:01:52.067978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
17862 17:01:52.102041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
17863 17:01:52.102455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
17865 17:01:52.137602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass>
17866 17:01:52.138103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3280 RESULT=pass
17868 17:01:52.171796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
17870 17:01:52.172431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
17871 17:01:52.205739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
17872 17:01:52.206221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
17874 17:01:52.240945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
17876 17:01:52.241389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
17877 17:01:52.275695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass
17879 17:01:52.276359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3296 RESULT=pass>
17880 17:01:52.310895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
17882 17:01:52.311356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
17883 17:01:52.345584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
17884 17:01:52.346097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
17886 17:01:52.380336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
17887 17:01:52.380827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
17889 17:01:52.415329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass
17891 17:01:52.415787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3312 RESULT=pass>
17892 17:01:52.450629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
17893 17:01:52.451047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
17895 17:01:52.485838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
17896 17:01:52.486251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
17898 17:01:52.520988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
17900 17:01:52.521604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
17901 17:01:52.556569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass>
17902 17:01:52.557044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3328 RESULT=pass
17904 17:01:52.591241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
17905 17:01:52.591793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
17907 17:01:52.625747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
17908 17:01:52.626221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
17910 17:01:52.660721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
17911 17:01:52.661140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
17913 17:01:52.695376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass>
17914 17:01:52.695803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3344 RESULT=pass
17916 17:01:52.730839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
17917 17:01:52.731281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
17919 17:01:52.766160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
17921 17:01:52.766622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
17922 17:01:52.800510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
17924 17:01:52.801090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
17925 17:01:52.834498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass>
17926 17:01:52.835007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3360 RESULT=pass
17928 17:01:52.869736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
17929 17:01:52.870196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
17931 17:01:52.904448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
17932 17:01:52.904899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
17934 17:01:52.941147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
17935 17:01:52.941710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
17937 17:01:52.977516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass>
17938 17:01:52.978042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3376 RESULT=pass
17940 17:01:53.016714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
17941 17:01:53.017126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
17943 17:01:53.052795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
17944 17:01:53.053242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
17946 17:01:53.084614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
17947 17:01:53.085075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
17949 17:01:53.116080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass>
17950 17:01:53.116552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3392 RESULT=pass
17952 17:01:53.147625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
17954 17:01:53.148184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
17955 17:01:53.180015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
17957 17:01:53.180561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
17958 17:01:53.211926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
17960 17:01:53.212668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
17961 17:01:53.252824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass>
17962 17:01:53.253328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3408 RESULT=pass
17964 17:01:53.292603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
17966 17:01:53.292989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
17967 17:01:53.332838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
17968 17:01:53.333317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
17970 17:01:53.386921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
17972 17:01:53.387499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
17973 17:01:53.425123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass>
17974 17:01:53.425572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3424 RESULT=pass
17976 17:01:53.462100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
17977 17:01:53.462539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
17979 17:01:53.499184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
17981 17:01:53.499806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
17982 17:01:53.536270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
17983 17:01:53.536747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
17985 17:01:53.569382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass
17987 17:01:53.570057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3440 RESULT=pass>
17988 17:01:53.600918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
17990 17:01:53.601562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
17991 17:01:53.633103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
17992 17:01:53.633627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
17994 17:01:53.669292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
17996 17:01:53.669778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
17997 17:01:53.706067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass>
17998 17:01:53.706485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3456 RESULT=pass
18000 17:01:53.740857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
18001 17:01:53.741296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
18003 17:01:53.778751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
18004 17:01:53.779250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
18006 17:01:53.843202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
18007 17:01:53.843638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
18009 17:01:53.883797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass
18011 17:01:53.884439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3472 RESULT=pass>
18012 17:01:53.920784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
18014 17:01:53.921236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
18015 17:01:53.956470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
18016 17:01:53.956935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
18018 17:01:53.992312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
18020 17:01:53.992883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
18021 17:01:54.028386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass>
18022 17:01:54.028848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3488 RESULT=pass
18024 17:01:54.062704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
18026 17:01:54.063166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
18027 17:01:54.097937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
18028 17:01:54.098408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
18030 17:01:54.134999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
18031 17:01:54.135491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
18033 17:01:54.170753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass
18035 17:01:54.171211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3504 RESULT=pass>
18036 17:01:54.207274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
18037 17:01:54.207712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
18039 17:01:54.245120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
18040 17:01:54.245536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
18042 17:01:54.282871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
18044 17:01:54.283334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
18045 17:01:54.318709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass>
18046 17:01:54.319204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3520 RESULT=pass
18048 17:01:54.355706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
18050 17:01:54.356524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
18051 17:01:54.390929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
18052 17:01:54.391420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
18054 17:01:54.424738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
18056 17:01:54.425196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
18057 17:01:54.457692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass
18059 17:01:54.458101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3536 RESULT=pass>
18060 17:01:54.491423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
18062 17:01:54.491806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
18063 17:01:54.524490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
18065 17:01:54.525238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
18066 17:01:54.558845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
18067 17:01:54.559293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
18069 17:01:54.592428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass>
18070 17:01:54.592923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3552 RESULT=pass
18072 17:01:54.624906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
18074 17:01:54.625572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
18075 17:01:54.675378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
18076 17:01:54.675878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
18078 17:01:54.708898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
18080 17:01:54.709669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
18081 17:01:54.742647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass>
18082 17:01:54.743202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3568 RESULT=pass
18084 17:01:54.777113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
18085 17:01:54.777565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
18087 17:01:54.810891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
18089 17:01:54.811304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
18090 17:01:54.843283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
18092 17:01:54.843750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
18093 17:01:54.874612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass>
18094 17:01:54.875053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3584 RESULT=pass
18096 17:01:54.906165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
18097 17:01:54.906585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
18099 17:01:54.938328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
18101 17:01:54.938791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
18102 17:01:54.970535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
18103 17:01:54.971032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
18105 17:01:55.002353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass>
18106 17:01:55.002816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3600 RESULT=pass
18108 17:01:55.034431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
18110 17:01:55.035009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
18111 17:01:55.068030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
18112 17:01:55.068523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
18114 17:01:55.100655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
18115 17:01:55.101091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
18117 17:01:55.132243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass>
18118 17:01:55.132710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3616 RESULT=pass
18120 17:01:55.164455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
18122 17:01:55.165033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
18123 17:01:55.196464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
18125 17:01:55.197025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
18126 17:01:55.228155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
18127 17:01:55.228658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
18129 17:01:55.259994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass>
18130 17:01:55.260487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3632 RESULT=pass
18132 17:01:55.291943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
18134 17:01:55.292509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
18135 17:01:55.323431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
18136 17:01:55.323859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
18138 17:01:55.355312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
18140 17:01:55.355779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
18141 17:01:55.387043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass>
18142 17:01:55.387468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3648 RESULT=pass
18144 17:01:55.418848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
18146 17:01:55.419409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
18147 17:01:55.449821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
18148 17:01:55.450272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
18150 17:01:55.482020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
18151 17:01:55.482441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
18153 17:01:55.514285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass>
18154 17:01:55.514724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3664 RESULT=pass
18156 17:01:55.546516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
18157 17:01:55.547020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
18159 17:01:55.578596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
18161 17:01:55.579161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
18162 17:01:55.610354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
18164 17:01:55.610910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
18165 17:01:55.641691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass
18167 17:01:55.642259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3680 RESULT=pass>
18168 17:01:55.673479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
18170 17:01:55.674054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
18171 17:01:55.707001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
18172 17:01:55.707466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
18174 17:01:55.738288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
18176 17:01:55.738749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
18177 17:01:55.770765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass
18179 17:01:55.771401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3696 RESULT=pass>
18180 17:01:55.802498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
18182 17:01:55.803105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
18183 17:01:55.834145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
18185 17:01:55.834747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
18186 17:01:55.865707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
18187 17:01:55.866133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
18189 17:01:55.897138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass>
18190 17:01:55.897557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3712 RESULT=pass
18192 17:01:55.929438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
18193 17:01:55.929866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
18195 17:01:55.964218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
18197 17:01:55.964678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
18198 17:01:55.996422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
18199 17:01:55.996842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
18201 17:01:56.028211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass
18203 17:01:56.028765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3728 RESULT=pass>
18204 17:01:56.060569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
18206 17:01:56.061032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
18207 17:01:56.093033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
18208 17:01:56.093443 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
18210 17:01:56.125017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
18212 17:01:56.125449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
18213 17:01:56.156990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass
18215 17:01:56.157418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3744 RESULT=pass>
18216 17:01:56.188807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
18218 17:01:56.189243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
18219 17:01:56.220860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
18220 17:01:56.221301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
18222 17:01:56.252870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
18223 17:01:56.253311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
18225 17:01:56.285106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass>
18226 17:01:56.285603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3760 RESULT=pass
18228 17:01:56.317394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
18229 17:01:56.317894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
18231 17:01:56.349460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
18233 17:01:56.350110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
18234 17:01:56.381340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
18236 17:01:56.381988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
18237 17:01:56.412936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass
18239 17:01:56.413564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3776 RESULT=pass>
18240 17:01:56.444759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
18242 17:01:56.445347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
18243 17:01:56.476740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
18244 17:01:56.477217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
18246 17:01:56.508969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
18248 17:01:56.509585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
18249 17:01:56.541459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass
18251 17:01:56.542067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3792 RESULT=pass>
18252 17:01:56.573571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
18253 17:01:56.574005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
18255 17:01:56.605853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
18256 17:01:56.606283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
18258 17:01:56.638315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
18260 17:01:56.638925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
18261 17:01:56.670305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass
18263 17:01:56.670873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3808 RESULT=pass>
18264 17:01:56.702133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
18265 17:01:56.702618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
18267 17:01:56.734465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
18268 17:01:56.734962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
18270 17:01:56.765833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
18272 17:01:56.766467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
18273 17:01:56.797107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass>
18274 17:01:56.797593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3824 RESULT=pass
18276 17:01:56.828792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
18278 17:01:56.829366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
18279 17:01:56.860160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
18280 17:01:56.860570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
18282 17:01:56.890584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
18283 17:01:56.891023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
18285 17:01:56.921206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass
18287 17:01:56.921629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3840 RESULT=pass>
18288 17:01:56.952657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
18289 17:01:56.953103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
18291 17:01:56.984812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
18292 17:01:56.985248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
18294 17:01:57.016796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
18295 17:01:57.017275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
18297 17:01:57.048552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass>
18298 17:01:57.049027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3856 RESULT=pass
18300 17:01:57.080686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
18302 17:01:57.081233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
18303 17:01:57.112722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
18304 17:01:57.113189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
18306 17:01:57.144825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
18307 17:01:57.145282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
18309 17:01:57.176877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass
18311 17:01:57.177428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3872 RESULT=pass>
18312 17:01:57.208568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
18313 17:01:57.209039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
18315 17:01:57.240461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
18316 17:01:57.240943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
18318 17:01:57.272460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
18319 17:01:57.272925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
18321 17:01:57.304811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass
18323 17:01:57.305333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3888 RESULT=pass>
18324 17:01:57.337588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
18325 17:01:57.338071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
18327 17:01:57.369670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
18329 17:01:57.370210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
18330 17:01:57.401504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
18331 17:01:57.401960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
18333 17:01:57.432688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass>
18334 17:01:57.433150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3904 RESULT=pass
18336 17:01:57.463485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
18337 17:01:57.463955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
18339 17:01:57.494982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
18340 17:01:57.495461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
18342 17:01:57.526196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
18344 17:01:57.526842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
18345 17:01:57.557722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass
18347 17:01:57.558359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3920 RESULT=pass>
18348 17:01:57.588620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
18349 17:01:57.589090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
18351 17:01:57.619955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
18353 17:01:57.620540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
18354 17:01:57.651379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
18356 17:01:57.651953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
18357 17:01:57.682611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass>
18358 17:01:57.683097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3936 RESULT=pass
18360 17:01:57.714174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
18361 17:01:57.714638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
18363 17:01:57.746728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
18365 17:01:57.747333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
18366 17:01:57.779023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
18368 17:01:57.779627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
18369 17:01:57.812348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass>
18370 17:01:57.812835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3952 RESULT=pass
18372 17:01:57.843816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
18374 17:01:57.844285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
18375 17:01:57.875675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
18377 17:01:57.876144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
18378 17:01:57.906599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
18379 17:01:57.907034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
18381 17:01:57.937452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass>
18382 17:01:57.937893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3968 RESULT=pass
18384 17:01:57.968773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
18386 17:01:57.969238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
18387 17:01:58.000777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
18389 17:01:58.001225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
18390 17:01:58.033905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
18392 17:01:58.034330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
18393 17:01:58.066048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass>
18394 17:01:58.066483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_3984 RESULT=pass
18396 17:01:58.100488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
18397 17:01:58.100961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
18399 17:01:58.134043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
18400 17:01:58.134545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
18402 17:01:58.168860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
18403 17:01:58.169279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
18405 17:01:58.203382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass>
18406 17:01:58.203756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4000 RESULT=pass
18408 17:01:58.235681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
18410 17:01:58.236264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
18411 17:01:58.267126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
18413 17:01:58.267714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
18414 17:01:58.298338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
18415 17:01:58.298768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
18417 17:01:58.329309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass>
18418 17:01:58.329736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4016 RESULT=pass
18420 17:01:58.360266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
18421 17:01:58.360704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
18423 17:01:58.391125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
18425 17:01:58.391689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
18426 17:01:58.422500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
18428 17:01:58.423120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
18429 17:01:58.453011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass>
18430 17:01:58.453499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4032 RESULT=pass
18432 17:01:58.484172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
18433 17:01:58.484612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
18435 17:01:58.515515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
18437 17:01:58.516153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
18438 17:01:58.546727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
18439 17:01:58.547203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
18441 17:01:58.578587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass
18443 17:01:58.579043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4048 RESULT=pass>
18444 17:01:58.609927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
18445 17:01:58.610357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
18447 17:01:58.641513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
18449 17:01:58.641996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
18450 17:01:58.672840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
18452 17:01:58.673421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
18453 17:01:58.704233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass
18455 17:01:58.704787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4064 RESULT=pass>
18456 17:01:58.735547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
18458 17:01:58.736101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
18459 17:01:58.766570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
18460 17:01:58.767016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
18462 17:01:58.797380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
18464 17:01:58.797947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
18465 17:01:58.828931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass>
18466 17:01:58.829404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4080 RESULT=pass
18468 17:01:58.860511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
18469 17:01:58.860994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
18471 17:01:58.891403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
18472 17:01:58.891834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
18474 17:01:58.937121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
18476 17:01:58.937548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
18477 17:01:58.973106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass>
18478 17:01:58.973603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4096 RESULT=pass
18480 17:01:59.004256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
18482 17:01:59.004901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
18483 17:01:59.036525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
18485 17:01:59.036974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
18486 17:01:59.068357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
18488 17:01:59.068796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
18489 17:01:59.099066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass>
18490 17:01:59.099537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4112 RESULT=pass
18492 17:01:59.131851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
18494 17:01:59.132416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
18495 17:01:59.166759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
18496 17:01:59.167239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
18498 17:01:59.199073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
18499 17:01:59.199532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
18501 17:01:59.230756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass
18503 17:01:59.231307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4128 RESULT=pass>
18504 17:01:59.262561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
18506 17:01:59.263108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
18507 17:01:59.294037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
18508 17:01:59.294501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
18510 17:01:59.325679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
18511 17:01:59.326140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
18513 17:01:59.358481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass
18515 17:01:59.359056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4144 RESULT=pass>
18516 17:01:59.391726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
18517 17:01:59.392207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
18519 17:01:59.424536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
18521 17:01:59.425123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
18522 17:01:59.456796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
18523 17:01:59.457252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
18525 17:01:59.488230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass
18527 17:01:59.488794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4160 RESULT=pass>
18528 17:01:59.519986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
18529 17:01:59.520465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
18531 17:01:59.551469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
18532 17:01:59.551891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
18534 17:01:59.582795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
18536 17:01:59.583370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
18537 17:01:59.616401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass
18539 17:01:59.616974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4176 RESULT=pass>
18540 17:01:59.649044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
18541 17:01:59.649516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
18543 17:01:59.680960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
18545 17:01:59.681689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
18546 17:01:59.713681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
18547 17:01:59.714108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
18549 17:01:59.745814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass>
18550 17:01:59.746257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4192 RESULT=pass
18552 17:01:59.778166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
18554 17:01:59.778638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
18555 17:01:59.809720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
18557 17:01:59.810292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
18558 17:01:59.841432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
18559 17:01:59.841921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
18561 17:01:59.874430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass
18563 17:01:59.874983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4208 RESULT=pass>
18564 17:01:59.906174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
18566 17:01:59.906715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
18567 17:01:59.938163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
18569 17:01:59.938700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
18570 17:01:59.970247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
18571 17:01:59.970724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
18573 17:02:00.001996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass>
18574 17:02:00.002461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4224 RESULT=pass
18576 17:02:00.034153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
18577 17:02:00.034599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
18579 17:02:00.066411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
18580 17:02:00.066877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
18582 17:02:00.098585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
18584 17:02:00.099126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
18585 17:02:00.130119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass
18587 17:02:00.130662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4240 RESULT=pass>
18588 17:02:00.161732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
18589 17:02:00.162181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
18591 17:02:00.193979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
18592 17:02:00.194448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
18594 17:02:00.226509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
18596 17:02:00.227058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
18597 17:02:00.257740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass>
18598 17:02:00.258194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4256 RESULT=pass
18600 17:02:00.289539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
18601 17:02:00.290012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
18603 17:02:00.321185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
18604 17:02:00.321654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
18606 17:02:00.352852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
18607 17:02:00.353309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
18609 17:02:00.385335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass>
18610 17:02:00.385804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4272 RESULT=pass
18612 17:02:00.417765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
18614 17:02:00.418244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
18615 17:02:00.454201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
18616 17:02:00.454640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
18618 17:02:00.486118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
18619 17:02:00.486595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
18621 17:02:00.517738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass>
18622 17:02:00.518217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4288 RESULT=pass
18624 17:02:00.549608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
18626 17:02:00.550196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
18627 17:02:00.582563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
18629 17:02:00.583130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
18630 17:02:00.613920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
18631 17:02:00.614364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
18633 17:02:00.647142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass>
18634 17:02:00.647557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4304 RESULT=pass
18636 17:02:00.680812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
18638 17:02:00.681362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
18639 17:02:00.716747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
18641 17:02:00.717188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
18642 17:02:00.752422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
18643 17:02:00.752922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
18645 17:02:00.788082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass>
18646 17:02:00.788559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4320 RESULT=pass
18648 17:02:00.823010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
18649 17:02:00.823480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
18651 17:02:00.857821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
18653 17:02:00.858262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
18654 17:02:00.890153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
18655 17:02:00.890534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
18657 17:02:00.922727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass
18659 17:02:00.923351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4336 RESULT=pass>
18660 17:02:00.954475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
18662 17:02:00.954928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
18663 17:02:00.985973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
18665 17:02:00.986425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
18666 17:02:01.017755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
18668 17:02:01.018208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
18669 17:02:01.049106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass>
18670 17:02:01.049550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4352 RESULT=pass
18672 17:02:01.081065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
18673 17:02:01.081532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
18675 17:02:01.114109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
18677 17:02:01.114743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
18678 17:02:01.145941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
18680 17:02:01.146574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
18681 17:02:01.177904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass
18683 17:02:01.178358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4368 RESULT=pass>
18684 17:02:01.209945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
18685 17:02:01.210363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
18687 17:02:01.242278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
18689 17:02:01.242738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
18690 17:02:01.274094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
18692 17:02:01.274551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
18693 17:02:01.306440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass>
18694 17:02:01.306839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4384 RESULT=pass
18696 17:02:01.338720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
18697 17:02:01.339125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
18699 17:02:01.370546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
18700 17:02:01.370947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
18702 17:02:01.402335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
18703 17:02:01.402756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
18705 17:02:01.434994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass>
18706 17:02:01.435424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4400 RESULT=pass
18708 17:02:01.467236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
18709 17:02:01.467739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
18711 17:02:01.499326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
18713 17:02:01.499973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
18714 17:02:01.530931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
18715 17:02:01.531393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
18717 17:02:01.567157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass>
18718 17:02:01.567649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4416 RESULT=pass
18720 17:02:01.600380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
18722 17:02:01.600848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
18723 17:02:01.632302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
18724 17:02:01.632788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
18726 17:02:01.664517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
18727 17:02:01.664984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
18729 17:02:01.696768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass>
18730 17:02:01.697205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4432 RESULT=pass
18732 17:02:01.728852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
18733 17:02:01.729287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
18735 17:02:01.761053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
18737 17:02:01.761489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
18738 17:02:01.792777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
18740 17:02:01.793225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
18741 17:02:01.824471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass>
18742 17:02:01.824903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4448 RESULT=pass
18744 17:02:01.856888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
18746 17:02:01.857470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
18747 17:02:01.889063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
18748 17:02:01.889533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
18750 17:02:01.920891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
18751 17:02:01.921362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
18753 17:02:01.954286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass
18755 17:02:01.954866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4464 RESULT=pass>
18756 17:02:01.986166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
18758 17:02:01.986723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
18759 17:02:02.017861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
18760 17:02:02.018306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
18762 17:02:02.050087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
18763 17:02:02.050576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
18765 17:02:02.082078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass>
18766 17:02:02.082554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4480 RESULT=pass
18768 17:02:02.115326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
18769 17:02:02.115806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
18771 17:02:02.148336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
18773 17:02:02.148900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
18774 17:02:02.179482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
18775 17:02:02.179916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
18777 17:02:02.210595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass
18779 17:02:02.211166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4496 RESULT=pass>
18780 17:02:02.241514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
18781 17:02:02.242005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
18783 17:02:02.273390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
18784 17:02:02.273854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
18786 17:02:02.304492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
18787 17:02:02.304923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
18789 17:02:02.334957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass>
18790 17:02:02.335388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4512 RESULT=pass
18792 17:02:02.368788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
18794 17:02:02.369253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
18795 17:02:02.400701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
18796 17:02:02.401154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
18798 17:02:02.431990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
18800 17:02:02.432568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
18801 17:02:02.464361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass
18803 17:02:02.464909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4528 RESULT=pass>
18804 17:02:02.495771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
18806 17:02:02.496319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
18807 17:02:02.527032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
18808 17:02:02.527522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
18810 17:02:02.558465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
18812 17:02:02.559040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
18813 17:02:02.589803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass
18815 17:02:02.590380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4544 RESULT=pass>
18816 17:02:02.621900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
18818 17:02:02.622449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
18819 17:02:02.654874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
18820 17:02:02.655316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
18822 17:02:02.687140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
18823 17:02:02.687584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
18825 17:02:02.720777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass
18827 17:02:02.721260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4560 RESULT=pass>
18828 17:02:02.753500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
18829 17:02:02.753950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
18831 17:02:02.786192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
18832 17:02:02.786649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
18834 17:02:02.818940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
18836 17:02:02.819402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
18837 17:02:02.853320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass>
18838 17:02:02.853794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4576 RESULT=pass
18840 17:02:02.886922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
18841 17:02:02.887362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
18843 17:02:02.918485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
18845 17:02:02.918941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
18846 17:02:02.949725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
18847 17:02:02.950182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
18849 17:02:02.981570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass>
18850 17:02:02.982008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4592 RESULT=pass
18852 17:02:03.014071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
18853 17:02:03.014579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
18855 17:02:03.050947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
18857 17:02:03.051342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
18858 17:02:03.083342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
18859 17:02:03.083713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
18861 17:02:03.115092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass
18863 17:02:03.115458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4608 RESULT=pass>
18864 17:02:03.147254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
18866 17:02:03.147886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
18867 17:02:03.189257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
18868 17:02:03.189743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
18870 17:02:03.234317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
18871 17:02:03.234792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
18873 17:02:03.265941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass>
18874 17:02:03.266381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4624 RESULT=pass
18876 17:02:03.297881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
18877 17:02:03.298340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
18879 17:02:03.329236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
18881 17:02:03.329764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
18882 17:02:03.360619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
18883 17:02:03.361075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
18885 17:02:03.395817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass
18887 17:02:03.396382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4640 RESULT=pass>
18888 17:02:03.427740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
18890 17:02:03.428295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
18891 17:02:03.460943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
18892 17:02:03.461440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
18894 17:02:03.492396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
18895 17:02:03.492849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
18897 17:02:03.524435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass>
18898 17:02:03.524905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4656 RESULT=pass
18900 17:02:03.555830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
18902 17:02:03.556374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
18903 17:02:03.587495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
18904 17:02:03.587940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
18906 17:02:03.619029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
18907 17:02:03.619512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
18909 17:02:03.649894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass>
18910 17:02:03.650348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4672 RESULT=pass
18912 17:02:03.681431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
18914 17:02:03.682011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
18915 17:02:03.712903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
18916 17:02:03.713399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
18918 17:02:03.746209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
18919 17:02:03.746684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
18921 17:02:03.780684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass>
18922 17:02:03.781173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4688 RESULT=pass
18924 17:02:03.812432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
18925 17:02:03.812911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
18927 17:02:03.844051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
18928 17:02:03.844544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
18930 17:02:03.874913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
18931 17:02:03.875351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
18933 17:02:03.905379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass>
18934 17:02:03.905784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4704 RESULT=pass
18936 17:02:03.936589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
18937 17:02:03.937041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
18939 17:02:03.967369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
18940 17:02:03.967829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
18942 17:02:03.998389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
18943 17:02:03.998802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
18945 17:02:04.029771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass>
18946 17:02:04.030234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4720 RESULT=pass
18948 17:02:04.089329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
18950 17:02:04.089823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
18951 17:02:04.121439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
18953 17:02:04.121910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
18954 17:02:04.154489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
18955 17:02:04.154865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
18957 17:02:04.186042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass>
18958 17:02:04.186407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4736 RESULT=pass
18960 17:02:04.217684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
18962 17:02:04.218234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
18963 17:02:04.250534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
18964 17:02:04.250993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
18966 17:02:04.282740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
18967 17:02:04.283193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
18969 17:02:04.314416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass
18971 17:02:04.314965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4752 RESULT=pass>
18972 17:02:04.346111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
18973 17:02:04.346518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
18975 17:02:04.378813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
18977 17:02:04.379270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
18978 17:02:04.414422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
18980 17:02:04.415124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
18981 17:02:04.446902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass>
18982 17:02:04.447374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4768 RESULT=pass
18984 17:02:04.479080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
18986 17:02:04.479633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
18987 17:02:04.513671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
18988 17:02:04.514052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
18990 17:02:04.546980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
18991 17:02:04.547370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
18993 17:02:04.584342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass>
18994 17:02:04.584799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4784 RESULT=pass
18996 17:02:04.619357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
18997 17:02:04.619793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
18999 17:02:04.657312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
19000 17:02:04.657732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
19002 17:02:04.689948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
19004 17:02:04.690420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
19005 17:02:04.729854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass>
19006 17:02:04.730275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4800 RESULT=pass
19008 17:02:04.762310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
19009 17:02:04.762734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
19011 17:02:04.799701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
19013 17:02:04.800066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
19014 17:02:04.836920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
19015 17:02:04.837340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
19017 17:02:04.872357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass>
19018 17:02:04.872779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4816 RESULT=pass
19020 17:02:04.905425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
19021 17:02:04.905836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
19023 17:02:04.939278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
19024 17:02:04.939650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
19026 17:02:04.972191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
19027 17:02:04.972565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
19029 17:02:05.005021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass>
19030 17:02:05.005499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4832 RESULT=pass
19032 17:02:05.037955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
19033 17:02:05.038416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
19035 17:02:05.072481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
19036 17:02:05.072952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
19038 17:02:05.106511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
19039 17:02:05.107050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
19041 17:02:05.139496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass
19043 17:02:05.140141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4848 RESULT=pass>
19044 17:02:05.172864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
19045 17:02:05.173323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
19047 17:02:05.205827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
19048 17:02:05.206303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
19050 17:02:05.239581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
19051 17:02:05.240080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
19053 17:02:05.274367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass>
19054 17:02:05.274766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4864 RESULT=pass
19056 17:02:05.307848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
19058 17:02:05.308273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
19059 17:02:05.342858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
19060 17:02:05.343321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
19062 17:02:05.375523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
19063 17:02:05.375989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
19065 17:02:05.407153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass>
19066 17:02:05.407622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4880 RESULT=pass
19068 17:02:05.440482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
19069 17:02:05.440911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
19071 17:02:05.474451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
19072 17:02:05.474989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
19074 17:02:05.518850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
19075 17:02:05.519350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
19077 17:02:05.575070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass
19079 17:02:05.575540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4896 RESULT=pass>
19080 17:02:05.632596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
19081 17:02:05.633020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
19083 17:02:05.680553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
19084 17:02:05.681039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
19086 17:02:05.724591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
19087 17:02:05.725021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
19089 17:02:05.760543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass
19091 17:02:05.761134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4912 RESULT=pass>
19092 17:02:05.805907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
19094 17:02:05.806615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
19095 17:02:05.848516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
19096 17:02:05.848900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
19098 17:02:05.891388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
19099 17:02:05.891769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
19101 17:02:05.931913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass
19103 17:02:05.932310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4928 RESULT=pass>
19104 17:02:05.981930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
19105 17:02:05.982392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
19107 17:02:06.044046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
19108 17:02:06.044462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
19110 17:02:06.095551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
19112 17:02:06.095955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
19113 17:02:06.134514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass
19115 17:02:06.134985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4944 RESULT=pass>
19116 17:02:06.177059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
19117 17:02:06.177466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
19119 17:02:06.215883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
19121 17:02:06.216600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
19122 17:02:06.252555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
19123 17:02:06.252987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
19125 17:02:06.291079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass>
19126 17:02:06.291660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4960 RESULT=pass
19128 17:02:06.336909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
19130 17:02:06.337349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
19131 17:02:06.372998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
19132 17:02:06.373486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
19134 17:02:06.420715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
19136 17:02:06.421151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
19137 17:02:06.454106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass
19139 17:02:06.454684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4976 RESULT=pass>
19140 17:02:06.495345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
19141 17:02:06.495916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
19143 17:02:06.537587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
19144 17:02:06.538028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
19146 17:02:06.575246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
19147 17:02:06.575674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
19149 17:02:06.622731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass>
19150 17:02:06.623159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_4992 RESULT=pass
19152 17:02:06.680637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
19154 17:02:06.681412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
19155 17:02:06.733216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
19156 17:02:06.733670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
19158 17:02:06.781913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
19159 17:02:06.782344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
19161 17:02:06.831144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass>
19162 17:02:06.831546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5008 RESULT=pass
19164 17:02:06.876012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
19166 17:02:06.876709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
19167 17:02:06.919953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
19169 17:02:06.920680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
19170 17:02:06.962956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
19171 17:02:06.963440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
19173 17:02:07.013084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass>
19174 17:02:07.013491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5024 RESULT=pass
19176 17:02:07.060917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
19177 17:02:07.061345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
19179 17:02:07.103425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
19180 17:02:07.103849 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
19182 17:02:07.147892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
19184 17:02:07.148355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
19185 17:02:07.194894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass>
19186 17:02:07.195293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5040 RESULT=pass
19188 17:02:07.238210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
19189 17:02:07.238653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
19191 17:02:07.284738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
19192 17:02:07.285173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
19194 17:02:07.329023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
19196 17:02:07.329524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
19197 17:02:07.373721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass
19199 17:02:07.374207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5056 RESULT=pass>
19200 17:02:07.420014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
19201 17:02:07.420438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
19203 17:02:07.461595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
19204 17:02:07.462015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
19206 17:02:07.507212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
19207 17:02:07.507675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
19209 17:02:07.549618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass>
19210 17:02:07.550065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5072 RESULT=pass
19212 17:02:07.601792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
19213 17:02:07.602227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
19215 17:02:07.653867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
19217 17:02:07.654345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
19218 17:02:07.699924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
19220 17:02:07.700429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
19221 17:02:07.751858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass
19223 17:02:07.752341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5088 RESULT=pass>
19224 17:02:07.803387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
19226 17:02:07.803888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
19227 17:02:07.847855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
19229 17:02:07.848302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
19230 17:02:07.905817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
19231 17:02:07.906308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
19233 17:02:07.963354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass>
19234 17:02:07.963762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5104 RESULT=pass
19236 17:02:08.021381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
19237 17:02:08.021825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
19239 17:02:08.078595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
19240 17:02:08.079029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
19242 17:02:08.133693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
19244 17:02:08.134090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
19245 17:02:08.193600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass>
19246 17:02:08.194061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5120 RESULT=pass
19248 17:02:08.255067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
19249 17:02:08.255515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
19251 17:02:08.311866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
19253 17:02:08.312347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
19254 17:02:08.365507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
19255 17:02:08.365964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
19257 17:02:08.409105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass>
19258 17:02:08.409570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5136 RESULT=pass
19260 17:02:08.453112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
19261 17:02:08.453587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
19263 17:02:08.496426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
19264 17:02:08.496848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
19266 17:02:08.538107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
19267 17:02:08.538561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
19269 17:02:08.586805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass>
19270 17:02:08.587275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5152 RESULT=pass
19272 17:02:08.629681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
19273 17:02:08.630091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
19275 17:02:08.677619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
19276 17:02:08.678056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
19278 17:02:08.727884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
19280 17:02:08.728390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
19281 17:02:08.781508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass>
19282 17:02:08.781982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5168 RESULT=pass
19284 17:02:08.825551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
19285 17:02:08.826023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
19287 17:02:08.873499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
19288 17:02:08.873947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
19290 17:02:08.915541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
19292 17:02:08.916027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
19293 17:02:08.959612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass
19295 17:02:08.960308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5184 RESULT=pass>
19296 17:02:09.015432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
19297 17:02:09.015905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
19299 17:02:09.065591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
19301 17:02:09.066001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
19302 17:02:09.109394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
19303 17:02:09.109991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
19305 17:02:09.149922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass>
19306 17:02:09.150502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5200 RESULT=pass
19308 17:02:09.218123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
19310 17:02:09.218808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
19311 17:02:09.263313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
19313 17:02:09.264114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
19314 17:02:09.311292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
19315 17:02:09.311747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
19317 17:02:09.358282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass>
19318 17:02:09.358711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5216 RESULT=pass
19320 17:02:09.407982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
19322 17:02:09.408421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
19323 17:02:09.456438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
19324 17:02:09.456857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
19326 17:02:09.499593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
19327 17:02:09.500048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
19329 17:02:09.540344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass>
19330 17:02:09.540792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5232 RESULT=pass
19332 17:02:09.581521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
19333 17:02:09.581979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
19335 17:02:09.630587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
19336 17:02:09.631043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
19338 17:02:09.682275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
19340 17:02:09.682714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
19341 17:02:09.730740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass>
19342 17:02:09.731192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5248 RESULT=pass
19344 17:02:09.776606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
19345 17:02:09.777181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
19347 17:02:09.816918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
19348 17:02:09.817376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
19350 17:02:09.861644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
19351 17:02:09.862091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
19353 17:02:09.902622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass>
19354 17:02:09.903048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5264 RESULT=pass
19356 17:02:09.941836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
19357 17:02:09.942269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
19359 17:02:09.989320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
19360 17:02:09.989680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
19362 17:02:10.037725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
19363 17:02:10.038147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
19365 17:02:10.076775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass>
19366 17:02:10.077213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5280 RESULT=pass
19368 17:02:10.120643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
19370 17:02:10.121237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
19371 17:02:10.165025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
19372 17:02:10.165580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
19374 17:02:10.205734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
19375 17:02:10.206143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
19377 17:02:10.244938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass>
19378 17:02:10.245442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5296 RESULT=pass
19380 17:02:10.290942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
19381 17:02:10.291359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
19383 17:02:10.337776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
19384 17:02:10.338227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
19386 17:02:10.380630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
19388 17:02:10.381096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
19389 17:02:10.430074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass>
19390 17:02:10.430502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5312 RESULT=pass
19392 17:02:10.485627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
19393 17:02:10.486076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
19395 17:02:10.534171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
19397 17:02:10.534624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
19398 17:02:10.571563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
19399 17:02:10.571985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
19401 17:02:10.614508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass>
19402 17:02:10.614951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5328 RESULT=pass
19404 17:02:10.657660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
19406 17:02:10.658127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
19407 17:02:10.707337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
19408 17:02:10.707742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
19410 17:02:10.749471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
19412 17:02:10.749943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
19413 17:02:10.788843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass
19415 17:02:10.789305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5344 RESULT=pass>
19416 17:02:10.826597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
19418 17:02:10.827015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
19419 17:02:10.865474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
19420 17:02:10.866041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
19422 17:02:10.908517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
19423 17:02:10.908905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
19425 17:02:10.951305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass>
19426 17:02:10.951733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5360 RESULT=pass
19428 17:02:10.997421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
19430 17:02:10.997881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
19431 17:02:11.043250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
19432 17:02:11.043691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
19434 17:02:11.088902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
19436 17:02:11.089349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
19437 17:02:11.130411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass>
19438 17:02:11.130861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5376 RESULT=pass
19440 17:02:11.173414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
19441 17:02:11.173859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
19443 17:02:11.218430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
19445 17:02:11.219241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
19446 17:02:11.262725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
19447 17:02:11.263177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
19449 17:02:11.301554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass>
19450 17:02:11.301999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5392 RESULT=pass
19452 17:02:11.343456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
19454 17:02:11.343828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
19455 17:02:11.383076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
19456 17:02:11.383515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
19458 17:02:11.424360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
19459 17:02:11.424794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
19461 17:02:11.467330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass>
19462 17:02:11.467764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5408 RESULT=pass
19464 17:02:11.508552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
19465 17:02:11.508986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
19467 17:02:11.555328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
19468 17:02:11.555757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
19470 17:02:11.614108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
19471 17:02:11.614550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
19473 17:02:11.674664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass>
19474 17:02:11.675112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5424 RESULT=pass
19476 17:02:11.734395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
19477 17:02:11.734816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
19479 17:02:11.793850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
19480 17:02:11.794277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
19482 17:02:11.852443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
19483 17:02:11.852852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
19485 17:02:11.900614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass>
19486 17:02:11.901055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5440 RESULT=pass
19488 17:02:11.948638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
19489 17:02:11.949058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
19491 17:02:12.000504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
19492 17:02:12.000902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
19494 17:02:12.043587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
19495 17:02:12.044029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
19497 17:02:12.091168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass>
19498 17:02:12.091607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5456 RESULT=pass
19500 17:02:12.136461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
19502 17:02:12.136932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
19503 17:02:12.178272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
19505 17:02:12.178731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
19506 17:02:12.220154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
19507 17:02:12.220583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
19509 17:02:12.257061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass>
19510 17:02:12.257494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5472 RESULT=pass
19512 17:02:12.294187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
19513 17:02:12.294611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
19515 17:02:12.337820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
19516 17:02:12.338256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
19518 17:02:12.386063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
19520 17:02:12.386517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
19521 17:02:12.434800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass
19523 17:02:12.435255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5488 RESULT=pass>
19524 17:02:12.481464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
19525 17:02:12.481882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
19527 17:02:12.527710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
19528 17:02:12.528166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
19530 17:02:12.573300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
19532 17:02:12.574036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
19533 17:02:12.613347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass
19535 17:02:12.613800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5504 RESULT=pass>
19536 17:02:12.655106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
19538 17:02:12.655578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
19539 17:02:12.700674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
19540 17:02:12.701100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
19542 17:02:12.745074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
19543 17:02:12.745495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
19545 17:02:12.792790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass>
19546 17:02:12.793213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5520 RESULT=pass
19548 17:02:12.841683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
19549 17:02:12.842119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
19551 17:02:12.888845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
19552 17:02:12.889245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
19554 17:02:12.930353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
19555 17:02:12.930751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
19557 17:02:12.965726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass>
19558 17:02:12.966139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5536 RESULT=pass
19560 17:02:13.013735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
19561 17:02:13.014176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
19563 17:02:13.058537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
19564 17:02:13.059585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
19566 17:02:13.102856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
19568 17:02:13.103306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
19569 17:02:13.148422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass
19571 17:02:13.148883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5552 RESULT=pass>
19572 17:02:13.192957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
19573 17:02:13.193384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
19575 17:02:13.234638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
19576 17:02:13.235071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
19578 17:02:13.275416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
19579 17:02:13.275862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
19581 17:02:13.314936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass>
19582 17:02:13.315378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5568 RESULT=pass
19584 17:02:13.360493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
19585 17:02:13.360942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
19587 17:02:13.402311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
19588 17:02:13.402765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
19590 17:02:13.442569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
19591 17:02:13.443024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
19593 17:02:13.483195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass>
19594 17:02:13.483647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5584 RESULT=pass
19596 17:02:13.526777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
19598 17:02:13.527230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
19599 17:02:13.566269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
19601 17:02:13.566723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
19602 17:02:13.606245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
19604 17:02:13.606683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
19605 17:02:13.645550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass
19607 17:02:13.646016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5600 RESULT=pass>
19608 17:02:13.684813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
19609 17:02:13.685219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
19611 17:02:13.727642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
19613 17:02:13.728065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
19614 17:02:13.772513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
19615 17:02:13.772948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
19617 17:02:13.820687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass>
19618 17:02:13.821081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5616 RESULT=pass
19620 17:02:13.875292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
19621 17:02:13.875718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
19623 17:02:13.930083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
19624 17:02:13.930494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
19626 17:02:13.985786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
19627 17:02:13.986294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
19629 17:02:14.032754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass>
19630 17:02:14.033326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5632 RESULT=pass
19632 17:02:14.081977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
19634 17:02:14.082400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
19635 17:02:14.139083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
19636 17:02:14.139537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
19638 17:02:14.187532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
19640 17:02:14.188004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
19641 17:02:14.233760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass
19643 17:02:14.234224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5648 RESULT=pass>
19644 17:02:14.274416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
19646 17:02:14.274877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
19647 17:02:14.335760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
19649 17:02:14.336235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
19650 17:02:14.378063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
19651 17:02:14.378486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
19653 17:02:14.417252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass>
19654 17:02:14.417820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5664 RESULT=pass
19656 17:02:14.455302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
19658 17:02:14.455784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
19659 17:02:14.501559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
19660 17:02:14.502011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
19662 17:02:14.551029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
19664 17:02:14.551506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
19665 17:02:14.588874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass>
19666 17:02:14.589314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5680 RESULT=pass
19668 17:02:14.627368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
19669 17:02:14.627807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
19671 17:02:14.674811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
19672 17:02:14.675245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
19674 17:02:14.718700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
19675 17:02:14.719094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
19677 17:02:14.759226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass>
19678 17:02:14.759673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5696 RESULT=pass
19680 17:02:14.802549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
19681 17:02:14.802984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
19683 17:02:14.855372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
19684 17:02:14.855799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
19686 17:02:14.898737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
19688 17:02:14.899164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
19689 17:02:14.940679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass>
19690 17:02:14.941133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5712 RESULT=pass
19692 17:02:14.984733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
19693 17:02:14.985162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
19695 17:02:15.025125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
19696 17:02:15.025572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
19698 17:02:15.067157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
19699 17:02:15.067598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
19701 17:02:15.105358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass>
19702 17:02:15.105799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5728 RESULT=pass
19704 17:02:15.144458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
19705 17:02:15.144886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
19707 17:02:15.195168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
19708 17:02:15.195735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
19710 17:02:15.236995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
19711 17:02:15.237452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
19713 17:02:15.277236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass>
19714 17:02:15.277593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5744 RESULT=pass
19716 17:02:15.324680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
19717 17:02:15.325118 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
19719 17:02:15.370125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
19720 17:02:15.370525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
19722 17:02:15.413986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
19723 17:02:15.414430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
19725 17:02:15.453414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass>
19726 17:02:15.454176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5760 RESULT=pass
19728 17:02:15.501020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
19729 17:02:15.501516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
19731 17:02:15.551958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
19733 17:02:15.552419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
19734 17:02:15.602625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
19735 17:02:15.603144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
19737 17:02:15.644587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass
19739 17:02:15.645069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5776 RESULT=pass>
19740 17:02:15.689436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
19742 17:02:15.689925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
19743 17:02:15.733407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
19745 17:02:15.733866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
19746 17:02:15.772722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
19747 17:02:15.773269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
19749 17:02:15.815481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass
19751 17:02:15.816102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5792 RESULT=pass>
19752 17:02:15.857264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
19753 17:02:15.857692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
19755 17:02:15.898661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
19757 17:02:15.899153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
19758 17:02:15.941488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
19759 17:02:15.941932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
19761 17:02:15.984697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass>
19762 17:02:15.985145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5808 RESULT=pass
19764 17:02:16.023484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
19765 17:02:16.023931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
19767 17:02:16.065337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
19768 17:02:16.065742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
19770 17:02:16.109879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
19771 17:02:16.110285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
19773 17:02:16.154304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass
19775 17:02:16.154771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5824 RESULT=pass>
19776 17:02:16.194813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
19778 17:02:16.195262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
19779 17:02:16.235175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
19780 17:02:16.235602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
19782 17:02:16.274233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
19783 17:02:16.274790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
19785 17:02:16.315164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass>
19786 17:02:16.315599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5840 RESULT=pass
19788 17:02:16.358692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
19789 17:02:16.359122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
19791 17:02:16.398800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
19792 17:02:16.399245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
19794 17:02:16.438173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
19795 17:02:16.438724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
19797 17:02:16.480898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass
19799 17:02:16.481358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5856 RESULT=pass>
19800 17:02:16.522078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
19801 17:02:16.522508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
19803 17:02:16.564861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
19804 17:02:16.565289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
19806 17:02:16.605967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
19807 17:02:16.606555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
19809 17:02:16.651023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass>
19810 17:02:16.651479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5872 RESULT=pass
19812 17:02:16.692609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
19813 17:02:16.693039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
19815 17:02:16.748904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
19816 17:02:16.749308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
19818 17:02:16.802780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
19819 17:02:16.803211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
19821 17:02:16.854586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass>
19822 17:02:16.855010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5888 RESULT=pass
19824 17:02:16.907950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
19826 17:02:16.908419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
19827 17:02:16.958081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
19828 17:02:16.958497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
19830 17:02:17.003171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
19832 17:02:17.003644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
19833 17:02:17.042641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass>
19834 17:02:17.043083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5904 RESULT=pass
19836 17:02:17.103336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
19837 17:02:17.103713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
19839 17:02:17.151416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
19840 17:02:17.151850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
19842 17:02:17.196760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
19843 17:02:17.197197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
19845 17:02:17.246031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass>
19846 17:02:17.246459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5920 RESULT=pass
19848 17:02:17.289145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
19850 17:02:17.289527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
19851 17:02:17.336831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
19853 17:02:17.337303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
19854 17:02:17.383235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
19855 17:02:17.383669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
19857 17:02:17.427257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass>
19858 17:02:17.427700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5936 RESULT=pass
19860 17:02:17.466786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
19861 17:02:17.467189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
19863 17:02:17.503039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
19865 17:02:17.503494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
19866 17:02:17.549074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
19867 17:02:17.549483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
19869 17:02:17.587207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass>
19870 17:02:17.587637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5952 RESULT=pass
19872 17:02:17.628333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
19874 17:02:17.630453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
19875 17:02:17.673429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
19877 17:02:17.673914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
19878 17:02:17.709567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
19879 17:02:17.710003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
19881 17:02:17.765675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass>
19882 17:02:17.766117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5968 RESULT=pass
19884 17:02:17.815033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
19885 17:02:17.815430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
19887 17:02:17.860574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
19889 17:02:17.861156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
19890 17:02:17.903041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
19891 17:02:17.903460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
19893 17:02:17.946828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass>
19894 17:02:17.947263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_5984 RESULT=pass
19896 17:02:17.989383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
19898 17:02:17.989823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
19899 17:02:18.029447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
19900 17:02:18.029896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
19902 17:02:18.075049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
19903 17:02:18.081707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
19905 17:02:18.125205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass
19907 17:02:18.125660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6000 RESULT=pass>
19908 17:02:18.177427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
19909 17:02:18.177875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
19911 17:02:18.229357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
19912 17:02:18.229784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
19914 17:02:18.281993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
19915 17:02:18.282418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
19917 17:02:18.328671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass
19919 17:02:18.329145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6016 RESULT=pass>
19920 17:02:18.377123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
19922 17:02:18.377616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
19923 17:02:18.422619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
19924 17:02:18.423030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
19926 17:02:18.470499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
19928 17:02:18.470934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
19929 17:02:18.514450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass
19931 17:02:18.515045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6032 RESULT=pass>
19932 17:02:18.557070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
19933 17:02:18.557511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
19935 17:02:18.605481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
19937 17:02:18.605943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
19938 17:02:18.652634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
19939 17:02:18.653113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
19941 17:02:18.699381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass>
19942 17:02:18.699901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6048 RESULT=pass
19944 17:02:18.745825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
19946 17:02:18.746596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
19947 17:02:18.794852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
19948 17:02:18.795278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
19950 17:02:18.838591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
19951 17:02:18.839039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
19953 17:02:18.880881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass>
19954 17:02:18.881331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6064 RESULT=pass
19956 17:02:18.934533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
19958 17:02:18.934997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
19959 17:02:18.980560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
19961 17:02:18.981045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
19962 17:02:19.020795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
19963 17:02:19.021236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
19965 17:02:19.063207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass>
19966 17:02:19.063636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6080 RESULT=pass
19968 17:02:19.106126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
19969 17:02:19.106556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
19971 17:02:19.151219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
19973 17:02:19.151698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
19974 17:02:19.193720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
19975 17:02:19.194139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
19977 17:02:19.233873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass>
19978 17:02:19.234324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6096 RESULT=pass
19980 17:02:19.275256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
19981 17:02:19.275720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
19983 17:02:19.315850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
19985 17:02:19.316319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
19986 17:02:19.356832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
19988 17:02:19.357296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
19989 17:02:19.405699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass
19991 17:02:19.406155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6112 RESULT=pass>
19992 17:02:19.472823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
19994 17:02:19.473286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
19995 17:02:19.513415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
19997 17:02:19.513890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
19998 17:02:19.554531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
19999 17:02:19.554952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
20001 17:02:19.596615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass
20003 17:02:19.597047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6128 RESULT=pass>
20004 17:02:19.641671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
20005 17:02:19.642123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
20007 17:02:19.690569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
20008 17:02:19.691005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
20010 17:02:19.741904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
20012 17:02:19.742371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
20013 17:02:19.785928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass>
20014 17:02:19.786387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6144 RESULT=pass
20016 17:02:19.830121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
20018 17:02:19.830601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
20019 17:02:19.875662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
20021 17:02:19.876145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
20022 17:02:19.923884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
20024 17:02:19.924355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
20025 17:02:19.971549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass>
20026 17:02:19.971959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6160 RESULT=pass
20028 17:02:20.024594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
20029 17:02:20.025010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
20031 17:02:20.081856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
20032 17:02:20.082336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
20034 17:02:20.137174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
20035 17:02:20.137569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
20037 17:02:20.185299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass>
20038 17:02:20.185684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6176 RESULT=pass
20040 17:02:20.233523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
20041 17:02:20.233969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
20043 17:02:20.288076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
20045 17:02:20.288758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
20046 17:02:20.345559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
20048 17:02:20.346281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
20049 17:02:20.396796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass>
20050 17:02:20.397236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6192 RESULT=pass
20052 17:02:20.443347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
20054 17:02:20.443808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
20055 17:02:20.497436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
20056 17:02:20.497836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
20058 17:02:20.553885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
20059 17:02:20.554309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
20061 17:02:20.599204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass
20063 17:02:20.599664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6208 RESULT=pass>
20064 17:02:20.642908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
20065 17:02:20.643297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
20067 17:02:20.684734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
20068 17:02:20.685165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
20070 17:02:20.727822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
20072 17:02:20.728583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
20073 17:02:20.770742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass>
20074 17:02:20.771154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6224 RESULT=pass
20076 17:02:20.811794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
20078 17:02:20.812234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
20079 17:02:20.854434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
20080 17:02:20.854818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
20082 17:02:20.897257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
20083 17:02:20.897684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
20085 17:02:20.940865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass>
20086 17:02:20.941284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6240 RESULT=pass
20088 17:02:20.978483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
20089 17:02:20.978910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
20091 17:02:21.022232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
20092 17:02:21.022669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
20094 17:02:21.063888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
20096 17:02:21.064359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
20097 17:02:21.104891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass>
20098 17:02:21.105315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6256 RESULT=pass
20100 17:02:21.149720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
20101 17:02:21.150139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
20103 17:02:21.191280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
20104 17:02:21.191725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
20106 17:02:21.241132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
20107 17:02:21.241572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
20109 17:02:21.281552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass>
20110 17:02:21.282017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6272 RESULT=pass
20112 17:02:21.323836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
20114 17:02:21.324295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
20115 17:02:21.367505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
20116 17:02:21.367943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
20118 17:02:21.417240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
20120 17:02:21.417704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
20121 17:02:21.459068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass>
20122 17:02:21.459500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6288 RESULT=pass
20124 17:02:21.505375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
20125 17:02:21.505819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
20127 17:02:21.549993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
20129 17:02:21.550466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
20130 17:02:21.591031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
20131 17:02:21.591466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
20133 17:02:21.633135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass
20135 17:02:21.633587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6304 RESULT=pass>
20136 17:02:21.678221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
20137 17:02:21.678639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
20139 17:02:21.723030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
20140 17:02:21.723485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
20142 17:02:21.771960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
20144 17:02:21.772455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
20145 17:02:21.811170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass>
20146 17:02:21.811632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6320 RESULT=pass
20148 17:02:21.854006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
20149 17:02:21.854456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
20151 17:02:21.902732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
20153 17:02:21.903178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
20154 17:02:21.951065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
20155 17:02:21.951506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
20157 17:02:21.995262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass
20159 17:02:21.995764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6336 RESULT=pass>
20160 17:02:22.038071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
20161 17:02:22.038515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
20163 17:02:22.081274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
20164 17:02:22.081678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
20166 17:02:22.127196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
20168 17:02:22.127657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
20169 17:02:22.186829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass>
20170 17:02:22.187255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6352 RESULT=pass
20172 17:02:22.238852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
20173 17:02:22.239245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
20175 17:02:22.281804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
20176 17:02:22.282194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
20178 17:02:22.327398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
20179 17:02:22.327841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
20181 17:02:22.366556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass>
20182 17:02:22.366984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6368 RESULT=pass
20184 17:02:22.413295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
20185 17:02:22.413703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
20187 17:02:22.458337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
20188 17:02:22.458762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
20190 17:02:22.500527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
20191 17:02:22.500980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
20193 17:02:22.544664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass>
20194 17:02:22.545125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6384 RESULT=pass
20196 17:02:22.589146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
20198 17:02:22.589632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
20199 17:02:22.635089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
20200 17:02:22.635523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
20202 17:02:22.681592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
20203 17:02:22.682024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
20205 17:02:22.730771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass>
20206 17:02:22.731222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6400 RESULT=pass
20208 17:02:22.779736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
20210 17:02:22.780254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
20211 17:02:22.825198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
20212 17:02:22.825634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
20214 17:02:22.873150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
20215 17:02:22.873590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
20217 17:02:22.922552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass
20219 17:02:22.923010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6416 RESULT=pass>
20220 17:02:22.966877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
20221 17:02:22.967325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
20223 17:02:23.011604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
20225 17:02:23.012058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
20226 17:02:23.061372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
20228 17:02:23.061861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
20229 17:02:23.110084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass
20231 17:02:23.110564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6432 RESULT=pass>
20232 17:02:23.163313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
20234 17:02:23.163791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
20235 17:02:23.225787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
20236 17:02:23.226221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
20238 17:02:23.283223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
20239 17:02:23.283678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
20241 17:02:23.336307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass
20243 17:02:23.336815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6448 RESULT=pass>
20244 17:02:23.389067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
20246 17:02:23.389554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
20247 17:02:23.438422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
20249 17:02:23.438879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
20250 17:02:23.482996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
20251 17:02:23.483424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
20253 17:02:23.532773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass>
20254 17:02:23.533229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6464 RESULT=pass
20256 17:02:23.582056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
20257 17:02:23.582480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
20259 17:02:23.638510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
20261 17:02:23.639010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
20262 17:02:23.698139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
20263 17:02:23.698552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
20265 17:02:23.760796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass>
20266 17:02:23.761225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6480 RESULT=pass
20268 17:02:23.815193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
20269 17:02:23.815631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
20271 17:02:23.872679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
20272 17:02:23.873094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
20274 17:02:23.927165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
20275 17:02:23.927613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
20277 17:02:23.982796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass
20279 17:02:23.983262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6496 RESULT=pass>
20280 17:02:24.037543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
20282 17:02:24.038016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
20283 17:02:24.091761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
20285 17:02:24.092347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
20286 17:02:24.143579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
20288 17:02:24.144034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
20289 17:02:24.198020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass>
20290 17:02:24.198448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6512 RESULT=pass
20292 17:02:24.249838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
20294 17:02:24.250315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
20295 17:02:24.301976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
20296 17:02:24.302407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
20298 17:02:24.353348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
20299 17:02:24.353771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
20301 17:02:24.414155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass
20303 17:02:24.414541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6528 RESULT=pass>
20304 17:02:24.474653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
20305 17:02:24.475096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
20307 17:02:24.515224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
20308 17:02:24.515683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
20310 17:02:24.599827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
20312 17:02:24.600303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
20313 17:02:24.655379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass
20315 17:02:24.655871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6544 RESULT=pass>
20316 17:02:24.707820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
20318 17:02:24.708365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
20319 17:02:24.760580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
20320 17:02:24.760967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
20322 17:02:24.814044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
20324 17:02:24.814484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
20325 17:02:24.867217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass>
20326 17:02:24.867623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6560 RESULT=pass
20328 17:02:24.919511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
20329 17:02:24.919932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
20331 17:02:24.973539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
20332 17:02:24.973961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
20334 17:02:25.027266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
20335 17:02:25.027652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
20337 17:02:25.081318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass>
20338 17:02:25.081683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6576 RESULT=pass
20340 17:02:25.133601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
20341 17:02:25.134059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
20343 17:02:25.177680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
20345 17:02:25.178156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
20346 17:02:25.219134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
20347 17:02:25.219657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
20349 17:02:25.247878 <47>[ 199.348526] systemd-journald[109]: Sent WATCHDOG=1 notification.
20350 17:02:25.273606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass>
20351 17:02:25.274071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6592 RESULT=pass
20353 17:02:25.312387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
20354 17:02:25.312831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
20356 17:02:25.355657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
20358 17:02:25.356134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
20359 17:02:25.400338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
20360 17:02:25.400850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
20362 17:02:25.457711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass>
20363 17:02:25.458098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6608 RESULT=pass
20365 17:02:25.501057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
20366 17:02:25.501507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
20368 17:02:25.545653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
20369 17:02:25.546096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
20371 17:02:25.593423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
20372 17:02:25.593884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
20374 17:02:25.641066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass>
20375 17:02:25.641521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6624 RESULT=pass
20377 17:02:25.685152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
20378 17:02:25.685599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
20380 17:02:25.729409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
20382 17:02:25.729850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
20383 17:02:25.775096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
20385 17:02:25.775562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
20386 17:02:25.825769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass>
20387 17:02:25.826203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6640 RESULT=pass
20389 17:02:25.869855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
20390 17:02:25.870395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
20392 17:02:25.922706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
20393 17:02:25.923162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
20395 17:02:25.969324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
20396 17:02:25.969746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
20398 17:02:26.010206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass>
20399 17:02:26.010637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6656 RESULT=pass
20401 17:02:26.058431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
20403 17:02:26.058883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
20404 17:02:26.107073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
20405 17:02:26.107521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
20407 17:02:26.155566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
20408 17:02:26.155986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
20410 17:02:26.202699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass
20412 17:02:26.203131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6672 RESULT=pass>
20413 17:02:26.251186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
20415 17:02:26.251648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
20416 17:02:26.294054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
20417 17:02:26.294475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
20419 17:02:26.338091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
20421 17:02:26.338561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
20422 17:02:26.378410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass>
20423 17:02:26.378852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6688 RESULT=pass
20425 17:02:26.425808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
20426 17:02:26.426228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
20428 17:02:26.474640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
20429 17:02:26.475054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
20431 17:02:26.517548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
20433 17:02:26.517981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
20434 17:02:26.565917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass>
20435 17:02:26.566336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6704 RESULT=pass
20437 17:02:26.611286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
20438 17:02:26.611727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
20440 17:02:26.654344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
20441 17:02:26.654769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
20443 17:02:26.704547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
20445 17:02:26.705165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
20446 17:02:26.755385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass>
20447 17:02:26.755838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6720 RESULT=pass
20449 17:02:26.794832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
20450 17:02:26.795295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
20452 17:02:26.837437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
20453 17:02:26.837870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
20455 17:02:26.887575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
20457 17:02:26.888061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
20458 17:02:26.929741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass>
20459 17:02:26.930194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6736 RESULT=pass
20461 17:02:26.978789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
20462 17:02:26.979199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
20464 17:02:27.025575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
20465 17:02:27.026019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
20467 17:02:27.074218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
20468 17:02:27.074627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
20470 17:02:27.124336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass>
20471 17:02:27.124723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6752 RESULT=pass
20473 17:02:27.180445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
20474 17:02:27.180829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
20476 17:02:27.229853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
20478 17:02:27.230331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
20479 17:02:27.275281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
20480 17:02:27.275690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
20482 17:02:27.322305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass>
20483 17:02:27.322765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6768 RESULT=pass
20485 17:02:27.376471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
20487 17:02:27.376944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
20488 17:02:27.430809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
20490 17:02:27.431262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
20491 17:02:27.475284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
20492 17:02:27.475718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
20494 17:02:27.524906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass>
20495 17:02:27.525302 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6784 RESULT=pass
20497 17:02:27.574268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
20498 17:02:27.574718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
20500 17:02:27.623268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
20501 17:02:27.623718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
20503 17:02:27.681042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
20504 17:02:27.681464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
20506 17:02:27.733727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass>
20507 17:02:27.734184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6800 RESULT=pass
20509 17:02:27.787450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
20510 17:02:27.787880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
20512 17:02:27.840665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
20514 17:02:27.841091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
20515 17:02:27.890814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
20516 17:02:27.891244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
20518 17:02:27.934356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass>
20519 17:02:27.934791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6816 RESULT=pass
20521 17:02:27.985200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
20522 17:02:27.985631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
20524 17:02:28.040572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
20526 17:02:28.041014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
20527 17:02:28.085662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
20528 17:02:28.086092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
20530 17:02:28.134739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass>
20531 17:02:28.135184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6832 RESULT=pass
20533 17:02:28.187741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
20535 17:02:28.188385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
20536 17:02:28.238749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
20537 17:02:28.239208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
20539 17:02:28.283083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
20540 17:02:28.283479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
20542 17:02:28.328294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass>
20543 17:02:28.328714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6848 RESULT=pass
20545 17:02:28.383361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
20546 17:02:28.383763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
20548 17:02:28.429035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
20549 17:02:28.429469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
20551 17:02:28.477134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
20552 17:02:28.477594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
20554 17:02:28.525183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass>
20555 17:02:28.525656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6864 RESULT=pass
20557 17:02:28.566574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
20558 17:02:28.566980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
20560 17:02:28.617366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
20561 17:02:28.617819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
20563 17:02:28.672712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
20565 17:02:28.673177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
20566 17:02:28.731023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass>
20567 17:02:28.731496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6880 RESULT=pass
20569 17:02:28.779545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
20570 17:02:28.779979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
20572 17:02:28.829963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
20574 17:02:28.830443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
20575 17:02:28.871256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
20576 17:02:28.871714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
20578 17:02:28.918907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass
20580 17:02:28.919335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6896 RESULT=pass>
20581 17:02:28.963120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
20582 17:02:28.963520 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
20584 17:02:29.010013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
20585 17:02:29.010440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
20587 17:02:29.059870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
20589 17:02:29.060375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
20590 17:02:29.109585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass
20592 17:02:29.110060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6912 RESULT=pass>
20593 17:02:29.167640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
20595 17:02:29.168120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
20596 17:02:29.225507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
20597 17:02:29.225942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
20599 17:02:29.283417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
20601 17:02:29.283849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
20602 17:02:29.341166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass
20604 17:02:29.341627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6928 RESULT=pass>
20605 17:02:29.394105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
20607 17:02:29.394546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
20608 17:02:29.442405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
20609 17:02:29.442842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
20611 17:02:29.495307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
20612 17:02:29.495719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
20614 17:02:29.534027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass
20616 17:02:29.534553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6944 RESULT=pass>
20617 17:02:29.585640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
20618 17:02:29.586059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
20620 17:02:29.635882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
20622 17:02:29.644077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
20623 17:02:29.717914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
20625 17:02:29.718407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
20626 17:02:29.765776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass>
20627 17:02:29.766200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6960 RESULT=pass
20629 17:02:29.806211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
20630 17:02:29.806640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
20632 17:02:29.862632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
20634 17:02:29.863107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
20635 17:02:29.922486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
20636 17:02:29.923047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
20638 17:02:29.970593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass>
20639 17:02:29.971012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6976 RESULT=pass
20641 17:02:30.012646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
20642 17:02:30.013212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
20644 17:02:30.058152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
20646 17:02:30.058584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
20647 17:02:30.106168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
20648 17:02:30.106614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
20650 17:02:30.152264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass>
20651 17:02:30.152695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_6992 RESULT=pass
20653 17:02:30.201524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
20654 17:02:30.201958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
20656 17:02:30.258457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
20657 17:02:30.258867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
20659 17:02:30.318276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
20661 17:02:30.318774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
20662 17:02:30.377801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass>
20663 17:02:30.378226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7008 RESULT=pass
20665 17:02:30.428911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
20666 17:02:30.429313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
20668 17:02:30.475492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
20669 17:02:30.475910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
20671 17:02:30.519325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
20672 17:02:30.519747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
20674 17:02:30.562154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass
20676 17:02:30.562599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7024 RESULT=pass>
20677 17:02:30.614846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
20678 17:02:30.615281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
20680 17:02:30.668581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
20682 17:02:30.669190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
20683 17:02:30.722204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
20684 17:02:30.722651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
20686 17:02:30.774559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass
20688 17:02:30.775032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7040 RESULT=pass>
20689 17:02:30.820978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
20690 17:02:30.821425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
20692 17:02:30.868295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
20693 17:02:30.868717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
20695 17:02:30.921708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
20696 17:02:30.922096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
20698 17:02:30.973813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass
20700 17:02:30.974231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7056 RESULT=pass>
20701 17:02:31.022859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
20703 17:02:31.023303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
20704 17:02:31.073954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
20705 17:02:31.074383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
20707 17:02:31.124935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
20709 17:02:31.125422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
20710 17:02:31.175347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass
20712 17:02:31.175767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7072 RESULT=pass>
20713 17:02:31.228830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
20714 17:02:31.229244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
20716 17:02:31.282150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
20717 17:02:31.282576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
20719 17:02:31.333242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
20720 17:02:31.333680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
20722 17:02:31.377237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass>
20723 17:02:31.377703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7088 RESULT=pass
20725 17:02:31.425515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
20727 17:02:31.425991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
20728 17:02:31.473207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
20729 17:02:31.473635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
20731 17:02:31.517163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
20733 17:02:31.517635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
20734 17:02:31.566676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass>
20735 17:02:31.567138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7104 RESULT=pass
20737 17:02:31.612626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
20739 17:02:31.613360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
20740 17:02:31.660823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
20741 17:02:31.661256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
20743 17:02:31.710712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
20744 17:02:31.711150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
20746 17:02:31.757819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass>
20747 17:02:31.758262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7120 RESULT=pass
20749 17:02:31.798624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
20750 17:02:31.799017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
20752 17:02:31.842772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
20753 17:02:31.843224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
20755 17:02:31.894167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
20757 17:02:31.894641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
20758 17:02:31.940869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass>
20759 17:02:31.941323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7136 RESULT=pass
20761 17:02:31.991446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
20762 17:02:31.991864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
20764 17:02:32.040790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
20765 17:02:32.041211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
20767 17:02:32.089511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
20769 17:02:32.089987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
20770 17:02:32.141355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass
20772 17:02:32.141830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7152 RESULT=pass>
20773 17:02:32.190302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
20774 17:02:32.190743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
20776 17:02:32.241374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
20777 17:02:32.241853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
20779 17:02:32.292677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
20781 17:02:32.293155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
20782 17:02:32.340906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass>
20783 17:02:32.341378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7168 RESULT=pass
20785 17:02:32.390181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
20786 17:02:32.390609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
20788 17:02:32.450890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
20789 17:02:32.451300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
20791 17:02:32.496592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
20792 17:02:32.497015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
20794 17:02:32.533781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass>
20795 17:02:32.534161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7184 RESULT=pass
20797 17:02:32.583733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
20799 17:02:32.584354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
20800 17:02:32.630990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
20801 17:02:32.631390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
20803 17:02:32.680761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
20805 17:02:32.681241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
20806 17:02:32.730168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass
20808 17:02:32.730626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7200 RESULT=pass>
20809 17:02:32.780863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
20810 17:02:32.781268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
20812 17:02:32.830152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
20813 17:02:32.830576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
20815 17:02:32.882051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
20817 17:02:32.882502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
20818 17:02:32.931411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass
20820 17:02:32.931887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7216 RESULT=pass>
20821 17:02:32.978860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
20822 17:02:32.979294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
20824 17:02:33.025566 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
20826 17:02:33.025999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
20827 17:02:33.074016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
20829 17:02:33.074438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
20830 17:02:33.128426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass>
20831 17:02:33.128866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7232 RESULT=pass
20833 17:02:33.179669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
20835 17:02:33.180348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
20836 17:02:33.228928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
20837 17:02:33.229369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
20839 17:02:33.280749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
20840 17:02:33.281186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
20842 17:02:33.332719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass>
20843 17:02:33.333169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7248 RESULT=pass
20845 17:02:33.378310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
20847 17:02:33.378771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
20848 17:02:33.430108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
20849 17:02:33.430563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
20851 17:02:33.474728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
20852 17:02:33.475151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
20854 17:02:33.520246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass>
20855 17:02:33.520648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7264 RESULT=pass
20857 17:02:33.563859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
20859 17:02:33.564371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
20860 17:02:33.614338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
20862 17:02:33.614822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
20863 17:02:33.671313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
20865 17:02:33.671793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
20866 17:02:33.725985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass>
20867 17:02:33.726415 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7280 RESULT=pass
20869 17:02:33.772533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
20870 17:02:33.773030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
20872 17:02:33.817334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
20874 17:02:33.817802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
20875 17:02:33.870255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
20876 17:02:33.870682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
20878 17:02:33.912877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass>
20879 17:02:33.913319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7296 RESULT=pass
20881 17:02:33.961171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
20882 17:02:33.961599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
20884 17:02:34.007397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
20885 17:02:34.007832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
20887 17:02:34.052691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
20889 17:02:34.053181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
20890 17:02:34.100049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass
20892 17:02:34.100556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7312 RESULT=pass>
20893 17:02:34.148442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
20894 17:02:34.148898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
20896 17:02:34.195919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
20898 17:02:34.196392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
20899 17:02:34.248738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
20901 17:02:34.249218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
20902 17:02:34.295411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass>
20903 17:02:34.295844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7328 RESULT=pass
20905 17:02:34.338115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
20906 17:02:34.338551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
20908 17:02:34.389795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
20909 17:02:34.390245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
20911 17:02:34.439302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
20912 17:02:34.439761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
20914 17:02:34.490706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass>
20915 17:02:34.491131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7344 RESULT=pass
20917 17:02:34.537230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
20919 17:02:34.537694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
20920 17:02:34.584394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
20922 17:02:34.584857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
20923 17:02:34.628990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
20925 17:02:34.629449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
20926 17:02:34.673335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass
20928 17:02:34.673800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7360 RESULT=pass>
20929 17:02:34.714514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
20930 17:02:34.714946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
20932 17:02:34.774417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
20933 17:02:34.774841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
20935 17:02:34.853738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
20936 17:02:34.854181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
20938 17:02:34.912342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass>
20939 17:02:34.912777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7376 RESULT=pass
20941 17:02:34.957210 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
20943 17:02:34.957690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
20944 17:02:34.997645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
20945 17:02:34.998082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
20947 17:02:35.044287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
20948 17:02:35.044735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
20950 17:02:35.086829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass>
20951 17:02:35.087298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7392 RESULT=pass
20953 17:02:35.136657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
20954 17:02:35.137053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
20956 17:02:35.178383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
20957 17:02:35.178839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
20959 17:02:35.226194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
20960 17:02:35.226633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
20962 17:02:35.277784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass>
20963 17:02:35.278235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7408 RESULT=pass
20965 17:02:35.336501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
20966 17:02:35.336910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
20968 17:02:35.381078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
20970 17:02:35.381551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
20971 17:02:35.426369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
20972 17:02:35.426815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
20974 17:02:35.485243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass>
20975 17:02:35.485671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7424 RESULT=pass
20977 17:02:35.538420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
20979 17:02:35.538852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
20980 17:02:35.597718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
20982 17:02:35.598118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
20983 17:02:35.646813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
20985 17:02:35.647291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
20986 17:02:35.690008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass>
20987 17:02:35.690465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7440 RESULT=pass
20989 17:02:35.734495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
20990 17:02:35.734933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
20992 17:02:35.789524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
20993 17:02:35.789988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
20995 17:02:35.837359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
20996 17:02:35.837814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
20998 17:02:35.880699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass>
20999 17:02:35.881130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7456 RESULT=pass
21001 17:02:35.921453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
21002 17:02:35.921890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
21004 17:02:35.970841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
21006 17:02:35.971314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
21007 17:02:36.011149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
21009 17:02:36.011652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
21010 17:02:36.051454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass>
21011 17:02:36.051908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7472 RESULT=pass
21013 17:02:36.091015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
21015 17:02:36.091484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
21016 17:02:36.142397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
21017 17:02:36.142848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
21019 17:02:36.189729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
21020 17:02:36.190134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
21022 17:02:36.238502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass>
21023 17:02:36.238946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7488 RESULT=pass
21025 17:02:36.283152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
21027 17:02:36.283639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
21028 17:02:36.325613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
21030 17:02:36.326101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
21031 17:02:36.365967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
21033 17:02:36.366441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
21034 17:02:36.408802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass
21036 17:02:36.409281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7504 RESULT=pass>
21037 17:02:36.455048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
21039 17:02:36.455475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
21040 17:02:36.499500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
21042 17:02:36.500159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
21043 17:02:36.545094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
21045 17:02:36.545762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
21046 17:02:36.582662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass>
21047 17:02:36.583228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7520 RESULT=pass
21049 17:02:36.630428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
21050 17:02:36.630818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
21052 17:02:36.675947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
21054 17:02:36.676563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
21055 17:02:36.714618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
21056 17:02:36.715028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
21058 17:02:36.757108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass
21060 17:02:36.757562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7536 RESULT=pass>
21061 17:02:36.800933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
21063 17:02:36.801392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
21064 17:02:36.849889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
21065 17:02:36.850308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
21067 17:02:36.901503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
21068 17:02:36.901927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
21070 17:02:36.948357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass>
21071 17:02:36.948782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7552 RESULT=pass
21073 17:02:37.001678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
21074 17:02:37.002106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
21076 17:02:37.051321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
21078 17:02:37.051829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
21079 17:02:37.104867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
21080 17:02:37.105294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
21082 17:02:37.155898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass
21084 17:02:37.156651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7568 RESULT=pass>
21085 17:02:37.200895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
21087 17:02:37.201284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
21088 17:02:37.245773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
21089 17:02:37.246206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
21091 17:02:37.289305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
21092 17:02:37.289825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
21094 17:02:37.331346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass
21096 17:02:37.331740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7584 RESULT=pass>
21097 17:02:37.377572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
21099 17:02:37.378070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
21100 17:02:37.421643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
21101 17:02:37.422064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
21103 17:02:37.465703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
21104 17:02:37.466129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
21106 17:02:37.501864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass>
21107 17:02:37.502269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7600 RESULT=pass
21109 17:02:37.538552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
21110 17:02:37.538971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
21112 17:02:37.574821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
21114 17:02:37.575243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
21115 17:02:37.611381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
21117 17:02:37.611867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
21118 17:02:37.648729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass>
21119 17:02:37.649172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7616 RESULT=pass
21121 17:02:37.692748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
21122 17:02:37.693171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
21124 17:02:37.729135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
21125 17:02:37.729683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
21127 17:02:37.768813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
21129 17:02:37.769323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
21130 17:02:37.807221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass>
21131 17:02:37.807668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7632 RESULT=pass
21133 17:02:37.845601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
21134 17:02:37.846058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
21136 17:02:37.882266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
21137 17:02:37.882699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
21139 17:02:37.930139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
21141 17:02:37.930558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
21142 17:02:37.973451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass
21144 17:02:37.973925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7648 RESULT=pass>
21145 17:02:38.022714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
21146 17:02:38.023143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
21148 17:02:38.074101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
21149 17:02:38.074514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
21151 17:02:38.117141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
21153 17:02:38.117587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
21154 17:02:38.162006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass>
21155 17:02:38.162405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7664 RESULT=pass
21157 17:02:38.209209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
21158 17:02:38.209657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
21160 17:02:38.262571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
21161 17:02:38.263005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
21163 17:02:38.323461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
21164 17:02:38.323882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
21166 17:02:38.370774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass>
21167 17:02:38.371181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7680 RESULT=pass
21169 17:02:38.421041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
21170 17:02:38.421470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
21172 17:02:38.465136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
21173 17:02:38.465665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
21175 17:02:38.515867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
21177 17:02:38.516356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
21178 17:02:38.566692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass
21180 17:02:38.567170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7696 RESULT=pass>
21181 17:02:38.612178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
21182 17:02:38.612595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
21184 17:02:38.658559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
21186 17:02:38.659230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
21187 17:02:38.703208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
21188 17:02:38.703623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
21190 17:02:38.747476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass
21192 17:02:38.747960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7712 RESULT=pass>
21193 17:02:38.786704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
21194 17:02:38.787127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
21196 17:02:38.821896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
21197 17:02:38.822328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
21199 17:02:38.860729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
21200 17:02:38.861140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
21202 17:02:38.913306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass
21204 17:02:38.913776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7728 RESULT=pass>
21205 17:02:38.959396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
21206 17:02:38.959830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
21208 17:02:39.008856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
21210 17:02:39.009331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
21211 17:02:39.055170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
21212 17:02:39.055615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
21214 17:02:39.095326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass>
21215 17:02:39.095787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7744 RESULT=pass
21217 17:02:39.135364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
21218 17:02:39.135932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
21220 17:02:39.185725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
21221 17:02:39.186151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
21223 17:02:39.234873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
21224 17:02:39.235324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
21226 17:02:39.282383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass>
21227 17:02:39.282786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7760 RESULT=pass
21229 17:02:39.320379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
21230 17:02:39.320818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
21232 17:02:39.356723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
21233 17:02:39.357134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
21235 17:02:39.393053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
21236 17:02:39.393462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
21238 17:02:39.434440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass>
21239 17:02:39.434864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7776 RESULT=pass
21241 17:02:39.473496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
21242 17:02:39.473909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
21244 17:02:39.510399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
21246 17:02:39.510827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
21247 17:02:39.552835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
21248 17:02:39.553249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
21250 17:02:39.604519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass>
21251 17:02:39.605056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7792 RESULT=pass
21253 17:02:39.645407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
21255 17:02:39.646125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
21256 17:02:39.682511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
21258 17:02:39.682982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
21259 17:02:39.726578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
21261 17:02:39.727031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
21262 17:02:39.770576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass>
21263 17:02:39.771022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7808 RESULT=pass
21265 17:02:39.812298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
21266 17:02:39.812734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
21268 17:02:39.851436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
21269 17:02:39.851867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
21271 17:02:39.914724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
21273 17:02:39.915188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
21274 17:02:39.953309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass
21276 17:02:39.953781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7824 RESULT=pass>
21277 17:02:39.991851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
21279 17:02:39.992297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
21280 17:02:40.034036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
21281 17:02:40.034461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
21283 17:02:40.077204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
21284 17:02:40.077619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
21286 17:02:40.115752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass
21288 17:02:40.116209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7840 RESULT=pass>
21289 17:02:40.161806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
21290 17:02:40.162221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
21292 17:02:40.210284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
21293 17:02:40.210829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
21295 17:02:40.258243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
21296 17:02:40.258656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
21298 17:02:40.298040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass>
21299 17:02:40.298478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7856 RESULT=pass
21301 17:02:40.343728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
21303 17:02:40.344217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
21304 17:02:40.393103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
21306 17:02:40.393572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
21307 17:02:40.434891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
21308 17:02:40.435292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
21310 17:02:40.484418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass>
21311 17:02:40.484855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7872 RESULT=pass
21313 17:02:40.530367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
21314 17:02:40.530814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
21316 17:02:40.582158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
21318 17:02:40.582583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
21319 17:02:40.624786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
21320 17:02:40.625214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
21322 17:02:40.667059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass
21324 17:02:40.667490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7888 RESULT=pass>
21325 17:02:40.711641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
21326 17:02:40.712037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
21328 17:02:40.758857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
21329 17:02:40.759299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
21331 17:02:40.799847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
21333 17:02:40.800323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
21334 17:02:40.837279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass
21336 17:02:40.837745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7904 RESULT=pass>
21337 17:02:40.875041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
21339 17:02:40.875508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
21340 17:02:40.911400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
21341 17:02:40.911842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
21343 17:02:40.951525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
21344 17:02:40.952014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
21346 17:02:40.993012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass>
21347 17:02:40.993529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7920 RESULT=pass
21349 17:02:41.037250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
21350 17:02:41.037627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
21352 17:02:41.082876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
21353 17:02:41.083318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
21355 17:02:41.124686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
21356 17:02:41.125193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
21358 17:02:41.166082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass
21360 17:02:41.166843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7936 RESULT=pass>
21361 17:02:41.205058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
21362 17:02:41.205625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
21364 17:02:41.254607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
21365 17:02:41.255048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
21367 17:02:41.296656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
21369 17:02:41.297123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
21370 17:02:41.343175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass
21372 17:02:41.343661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7952 RESULT=pass>
21373 17:02:41.391507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
21374 17:02:41.391935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
21376 17:02:41.429456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
21378 17:02:41.429935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
21379 17:02:41.468346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
21380 17:02:41.468776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
21382 17:02:41.505398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass>
21383 17:02:41.505811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7968 RESULT=pass
21385 17:02:41.543813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
21386 17:02:41.544235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
21388 17:02:41.581678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
21389 17:02:41.582126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
21391 17:02:41.618567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
21392 17:02:41.618987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
21394 17:02:41.654672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass>
21395 17:02:41.655119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_7984 RESULT=pass
21397 17:02:41.694782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
21398 17:02:41.695221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
21400 17:02:41.745514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
21401 17:02:41.745951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
21403 17:02:41.794288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
21404 17:02:41.794665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
21406 17:02:41.832495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass>
21407 17:02:41.832932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8000 RESULT=pass
21409 17:02:41.871854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
21411 17:02:41.872335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
21412 17:02:41.918514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
21414 17:02:41.918892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
21415 17:02:41.961836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
21417 17:02:41.962516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
21418 17:02:42.001572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass>
21419 17:02:42.002045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8016 RESULT=pass
21421 17:02:42.047350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
21422 17:02:42.047736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
21424 17:02:42.097512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
21425 17:02:42.098020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
21427 17:02:42.141095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
21429 17:02:42.141532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
21430 17:02:42.181179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass>
21431 17:02:42.181576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8032 RESULT=pass
21433 17:02:42.229581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
21434 17:02:42.230021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
21436 17:02:42.279426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
21437 17:02:42.279830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
21439 17:02:42.331011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
21440 17:02:42.331392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
21442 17:02:42.383352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass>
21443 17:02:42.383753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8048 RESULT=pass
21445 17:02:42.435312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
21446 17:02:42.435682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
21448 17:02:42.487084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
21449 17:02:42.487469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
21451 17:02:42.539362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
21452 17:02:42.539773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
21454 17:02:42.591188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass>
21455 17:02:42.591581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8064 RESULT=pass
21457 17:02:42.643439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
21459 17:02:42.643871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
21460 17:02:42.697182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
21461 17:02:42.697696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
21463 17:02:42.748970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
21464 17:02:42.749421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
21466 17:02:42.801264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass>
21467 17:02:42.801685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8080 RESULT=pass
21469 17:02:42.853895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
21470 17:02:42.854322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
21472 17:02:42.906918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
21474 17:02:42.907640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
21475 17:02:42.949392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
21476 17:02:42.949815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
21478 17:02:42.985291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass>
21479 17:02:42.985692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8096 RESULT=pass
21481 17:02:43.033254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
21482 17:02:43.033660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
21484 17:02:43.081089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
21486 17:02:43.081557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
21487 17:02:43.121716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
21489 17:02:43.122170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
21490 17:02:43.165088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass>
21491 17:02:43.165527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8112 RESULT=pass
21493 17:02:43.201147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
21495 17:02:43.201532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
21496 17:02:43.247055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
21497 17:02:43.247483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
21499 17:02:43.294794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
21500 17:02:43.295266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
21502 17:02:43.338860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass>
21503 17:02:43.339308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8128 RESULT=pass
21505 17:02:43.384493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
21506 17:02:43.384921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
21508 17:02:43.428847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
21510 17:02:43.429556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
21511 17:02:43.481272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
21512 17:02:43.481689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
21514 17:02:43.529572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass
21516 17:02:43.530026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8144 RESULT=pass>
21517 17:02:43.586511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
21518 17:02:43.586923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
21520 17:02:43.634889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
21522 17:02:43.635332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
21523 17:02:43.673002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
21524 17:02:43.673445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
21526 17:02:43.715401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass>
21527 17:02:43.715819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8160 RESULT=pass
21529 17:02:43.764782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
21530 17:02:43.765180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
21532 17:02:43.801729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
21533 17:02:43.802215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
21535 17:02:43.843315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
21536 17:02:43.843869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
21538 17:02:43.884927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass>
21539 17:02:43.885299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8176 RESULT=pass
21541 17:02:43.933458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
21542 17:02:43.933974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
21544 17:02:43.983619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
21545 17:02:43.984072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
21547 17:02:44.025520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
21548 17:02:44.026027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
21550 17:02:44.065610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass>
21551 17:02:44.066114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_SVE_VL_8192 RESULT=pass
21553 17:02:44.109024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
21555 17:02:44.109518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
21556 17:02:44.154733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
21557 17:02:44.155165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
21559 17:02:44.201383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
21560 17:02:44.201814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
21562 17:02:44.246097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass
21564 17:02:44.246480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0 RESULT=pass>
21565 17:02:44.288174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass>
21566 17:02:44.288495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state RESULT=pass
21568 17:02:44.329721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass>
21569 17:02:44.330121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set RESULT=pass
21571 17:02:44.374326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass>
21572 17:02:44.374824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared RESULT=pass
21574 17:02:44.421069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass
21576 17:02:44.421452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_16 RESULT=pass>
21577 17:02:44.458949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass>
21578 17:02:44.459374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16 RESULT=pass
21580 17:02:44.505456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass>
21581 17:02:44.506039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16 RESULT=pass
21583 17:02:44.557369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass>
21584 17:02:44.557951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16 RESULT=pass
21586 17:02:44.605076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass>
21587 17:02:44.605600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_32 RESULT=pass
21589 17:02:44.643374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass>
21590 17:02:44.643770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32 RESULT=pass
21592 17:02:44.687134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass>
21593 17:02:44.687532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32 RESULT=pass
21595 17:02:44.733069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass
21597 17:02:44.733572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32 RESULT=pass>
21598 17:02:44.780857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass
21600 17:02:44.781295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_48 RESULT=pass>
21601 17:02:44.830018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip
21603 17:02:44.830489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48 RESULT=skip>
21604 17:02:44.865842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip>
21605 17:02:44.866274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48 RESULT=skip
21607 17:02:44.902479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip>
21608 17:02:44.902912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48 RESULT=skip
21610 17:02:44.939163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass>
21611 17:02:44.939589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_64 RESULT=pass
21613 17:02:44.976912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass>
21614 17:02:44.977337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64 RESULT=pass
21616 17:02:45.032755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass
21618 17:02:45.033158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64 RESULT=pass>
21619 17:02:45.070224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass>
21620 17:02:45.070607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64 RESULT=pass
21622 17:02:45.113899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass>
21623 17:02:45.114322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_80 RESULT=pass
21625 17:02:45.154184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip>
21626 17:02:45.154598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80 RESULT=skip
21628 17:02:45.190316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip>
21629 17:02:45.190719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80 RESULT=skip
21631 17:02:45.233620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip>
21632 17:02:45.233990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80 RESULT=skip
21634 17:02:45.282456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass>
21635 17:02:45.282891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_96 RESULT=pass
21637 17:02:45.322312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip>
21638 17:02:45.322726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96 RESULT=skip
21640 17:02:45.358498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip
21642 17:02:45.358947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96 RESULT=skip>
21643 17:02:45.395274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip
21645 17:02:45.395703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96 RESULT=skip>
21646 17:02:45.430952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass>
21647 17:02:45.431342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_112 RESULT=pass
21649 17:02:45.466356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip
21651 17:02:45.466816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112 RESULT=skip>
21652 17:02:45.511191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip>
21653 17:02:45.511611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112 RESULT=skip
21655 17:02:45.552000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip
21657 17:02:45.552457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112 RESULT=skip>
21658 17:02:45.599316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass>
21659 17:02:45.599725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_128 RESULT=pass
21661 17:02:45.643979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass
21663 17:02:45.644465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128 RESULT=pass>
21664 17:02:45.687888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass
21666 17:02:45.688822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128 RESULT=pass>
21667 17:02:45.737501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass
21669 17:02:45.737965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128 RESULT=pass>
21670 17:02:45.779855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass
21672 17:02:45.780280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_144 RESULT=pass>
21673 17:02:45.821713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip>
21674 17:02:45.822103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144 RESULT=skip
21676 17:02:45.865152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip>
21677 17:02:45.865606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144 RESULT=skip
21679 17:02:45.910546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip>
21680 17:02:45.910997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144 RESULT=skip
21682 17:02:45.956356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass>
21683 17:02:45.956905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_160 RESULT=pass
21685 17:02:45.995427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip>
21686 17:02:45.995874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160 RESULT=skip
21688 17:02:46.039049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip
21690 17:02:46.039479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160 RESULT=skip>
21691 17:02:46.085776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip
21693 17:02:46.086234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160 RESULT=skip>
21694 17:02:46.132725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass
21696 17:02:46.133180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_176 RESULT=pass>
21697 17:02:46.186643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip
21699 17:02:46.187071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176 RESULT=skip>
21700 17:02:46.229476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip>
21701 17:02:46.229892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176 RESULT=skip
21703 17:02:46.276694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip>
21704 17:02:46.277072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176 RESULT=skip
21706 17:02:46.325880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass
21708 17:02:46.326325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_192 RESULT=pass>
21709 17:02:46.373180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip
21711 17:02:46.373899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192 RESULT=skip>
21712 17:02:46.417123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip>
21713 17:02:46.417479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192 RESULT=skip
21715 17:02:46.464685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip
21717 17:02:46.465154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192 RESULT=skip>
21718 17:02:46.510982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass
21720 17:02:46.511428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_208 RESULT=pass>
21721 17:02:46.563473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip>
21722 17:02:46.563894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208 RESULT=skip
21724 17:02:46.622732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip>
21725 17:02:46.623216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208 RESULT=skip
21727 17:02:46.679701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip
21729 17:02:46.680159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208 RESULT=skip>
21730 17:02:46.726536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass>
21731 17:02:46.727035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_224 RESULT=pass
21733 17:02:46.773811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip>
21734 17:02:46.774219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224 RESULT=skip
21736 17:02:46.816881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip>
21737 17:02:46.817334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224 RESULT=skip
21739 17:02:46.858155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip
21741 17:02:46.858601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224 RESULT=skip>
21742 17:02:46.904345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass>
21743 17:02:46.904800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_240 RESULT=pass
21745 17:02:46.948375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip
21747 17:02:46.948813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240 RESULT=skip>
21748 17:02:46.987740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip>
21749 17:02:46.988170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240 RESULT=skip
21751 17:02:47.030334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip>
21752 17:02:47.030735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240 RESULT=skip
21754 17:02:47.079140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass>
21755 17:02:47.079573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_256 RESULT=pass
21757 17:02:47.117583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass>
21758 17:02:47.118007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256 RESULT=pass
21760 17:02:47.166742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass
21762 17:02:47.167190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256 RESULT=pass>
21763 17:02:47.217065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass
21765 17:02:47.217517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256 RESULT=pass>
21766 17:02:47.264837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass>
21767 17:02:47.265267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_272 RESULT=pass
21769 17:02:47.306982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip>
21770 17:02:47.307440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272 RESULT=skip
21772 17:02:47.358398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip>
21773 17:02:47.358974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272 RESULT=skip
21775 17:02:47.408915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip>
21776 17:02:47.409343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272 RESULT=skip
21778 17:02:47.451010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass>
21779 17:02:47.451463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_288 RESULT=pass
21781 17:02:47.501785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip>
21782 17:02:47.502199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288 RESULT=skip
21784 17:02:47.548735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip
21786 17:02:47.549422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288 RESULT=skip>
21787 17:02:47.598013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip>
21788 17:02:47.598437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288 RESULT=skip
21790 17:02:47.646550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass>
21791 17:02:47.647005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_304 RESULT=pass
21793 17:02:47.695499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip>
21794 17:02:47.695935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304 RESULT=skip
21796 17:02:47.739468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip>
21797 17:02:47.739836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304 RESULT=skip
21799 17:02:47.787527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip
21801 17:02:47.787968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304 RESULT=skip>
21802 17:02:47.836339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass>
21803 17:02:47.836777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_320 RESULT=pass
21805 17:02:47.885833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip>
21806 17:02:47.886255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320 RESULT=skip
21808 17:02:47.933116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip
21810 17:02:47.933540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320 RESULT=skip>
21811 17:02:47.981681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip
21813 17:02:47.982082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320 RESULT=skip>
21814 17:02:48.029294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass>
21815 17:02:48.029682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_336 RESULT=pass
21817 17:02:48.070715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip>
21818 17:02:48.071080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336 RESULT=skip
21820 17:02:48.120538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip>
21821 17:02:48.120939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336 RESULT=skip
21823 17:02:48.169989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip>
21824 17:02:48.170435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336 RESULT=skip
21826 17:02:48.207455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass>
21827 17:02:48.207900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_352 RESULT=pass
21829 17:02:48.252464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip>
21830 17:02:48.252910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352 RESULT=skip
21832 17:02:48.298892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip>
21833 17:02:48.299306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352 RESULT=skip
21835 17:02:48.348400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip>
21836 17:02:48.348797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352 RESULT=skip
21838 17:02:48.396807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass>
21839 17:02:48.397216 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_368 RESULT=pass
21841 17:02:48.445206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip
21843 17:02:48.445673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368 RESULT=skip>
21844 17:02:48.495486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip>
21845 17:02:48.495871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368 RESULT=skip
21847 17:02:48.545028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip>
21848 17:02:48.545454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368 RESULT=skip
21850 17:02:48.598308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass>
21851 17:02:48.598868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_384 RESULT=pass
21853 17:02:48.650651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip>
21854 17:02:48.651082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384 RESULT=skip
21856 17:02:48.706533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip>
21857 17:02:48.706966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384 RESULT=skip
21859 17:02:48.760986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip>
21860 17:02:48.761358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384 RESULT=skip
21862 17:02:48.808671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass>
21863 17:02:48.809082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_400 RESULT=pass
21865 17:02:48.855035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip
21867 17:02:48.855501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400 RESULT=skip>
21868 17:02:48.894538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip>
21869 17:02:48.894960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400 RESULT=skip
21871 17:02:48.940041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip
21873 17:02:48.940518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400 RESULT=skip>
21874 17:02:48.989114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass>
21875 17:02:48.989522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_416 RESULT=pass
21877 17:02:49.029223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip>
21878 17:02:49.029663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416 RESULT=skip
21880 17:02:49.077465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip>
21881 17:02:49.077900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416 RESULT=skip
21883 17:02:49.118675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip>
21884 17:02:49.119094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416 RESULT=skip
21886 17:02:49.166529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass
21888 17:02:49.166965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_432 RESULT=pass>
21889 17:02:49.211075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip
21891 17:02:49.211534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432 RESULT=skip>
21892 17:02:49.248595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip
21894 17:02:49.249045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432 RESULT=skip>
21895 17:02:49.297711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip>
21896 17:02:49.298142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432 RESULT=skip
21898 17:02:49.343671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass
21900 17:02:49.344119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_448 RESULT=pass>
21901 17:02:49.390144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip>
21902 17:02:49.390582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448 RESULT=skip
21904 17:02:49.436737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip>
21905 17:02:49.437169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448 RESULT=skip
21907 17:02:49.481446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip>
21908 17:02:49.481847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448 RESULT=skip
21910 17:02:49.529965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass
21912 17:02:49.530418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_464 RESULT=pass>
21913 17:02:49.577678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip>
21914 17:02:49.578055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464 RESULT=skip
21916 17:02:49.627269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip>
21917 17:02:49.627687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464 RESULT=skip
21919 17:02:49.679314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip>
21920 17:02:49.679733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464 RESULT=skip
21922 17:02:49.729850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass>
21923 17:02:49.730272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_480 RESULT=pass
21925 17:02:49.777590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip>
21926 17:02:49.777987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480 RESULT=skip
21928 17:02:49.834247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip
21930 17:02:49.834704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480 RESULT=skip>
21931 17:02:49.879876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip
21933 17:02:49.880652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480 RESULT=skip>
21934 17:02:49.929111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass
21936 17:02:49.929564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_496 RESULT=pass>
21937 17:02:49.972910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip>
21938 17:02:49.973316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496 RESULT=skip
21940 17:02:50.025775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip>
21941 17:02:50.026225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496 RESULT=skip
21943 17:02:50.080882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip>
21944 17:02:50.081325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496 RESULT=skip
21946 17:02:50.145722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass>
21947 17:02:50.146163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_512 RESULT=pass
21949 17:02:50.194555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip>
21950 17:02:50.195000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512 RESULT=skip
21952 17:02:50.242681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip>
21953 17:02:50.243108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512 RESULT=skip
21955 17:02:50.289896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip>
21956 17:02:50.290337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512 RESULT=skip
21958 17:02:50.333474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass
21960 17:02:50.333969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_528 RESULT=pass>
21961 17:02:50.387277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip>
21962 17:02:50.387714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528 RESULT=skip
21964 17:02:50.445861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip>
21965 17:02:50.446289 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528 RESULT=skip
21967 17:02:50.494178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip>
21968 17:02:50.494596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528 RESULT=skip
21970 17:02:50.540856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass>
21971 17:02:50.541279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_544 RESULT=pass
21973 17:02:50.585417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip>
21974 17:02:50.585767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544 RESULT=skip
21976 17:02:50.633849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip>
21977 17:02:50.634341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544 RESULT=skip
21979 17:02:50.683434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip
21981 17:02:50.684051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544 RESULT=skip>
21982 17:02:50.731517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass
21984 17:02:50.732032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_560 RESULT=pass>
21985 17:02:50.775154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip>
21986 17:02:50.775574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560 RESULT=skip
21988 17:02:50.831427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip>
21989 17:02:50.831913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560 RESULT=skip
21991 17:02:50.886877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip
21993 17:02:50.887304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560 RESULT=skip>
21994 17:02:50.938640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass>
21995 17:02:50.939068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_576 RESULT=pass
21997 17:02:50.984940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip
21999 17:02:50.985334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576 RESULT=skip>
22000 17:02:51.035183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip>
22001 17:02:51.035645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576 RESULT=skip
22003 17:02:51.080596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip>
22004 17:02:51.081031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576 RESULT=skip
22006 17:02:51.127307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass>
22007 17:02:51.127728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_592 RESULT=pass
22009 17:02:51.167404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip>
22010 17:02:51.167798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592 RESULT=skip
22012 17:02:51.210315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip>
22013 17:02:51.210699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592 RESULT=skip
22015 17:02:51.254430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip>
22016 17:02:51.254864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592 RESULT=skip
22018 17:02:51.299779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass
22020 17:02:51.300593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_608 RESULT=pass>
22021 17:02:51.350423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip
22023 17:02:51.350911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608 RESULT=skip>
22024 17:02:51.399116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip>
22025 17:02:51.399648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608 RESULT=skip
22027 17:02:51.448491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip>
22028 17:02:51.448915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608 RESULT=skip
22030 17:02:51.491705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass
22032 17:02:51.492173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_624 RESULT=pass>
22033 17:02:51.539470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip>
22034 17:02:51.539913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624 RESULT=skip
22036 17:02:51.578495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip
22038 17:02:51.578968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624 RESULT=skip>
22039 17:02:51.621013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip>
22040 17:02:51.621457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624 RESULT=skip
22042 17:02:51.662280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass>
22043 17:02:51.662666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_640 RESULT=pass
22045 17:02:51.704748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip
22047 17:02:51.705140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640 RESULT=skip>
22048 17:02:51.744381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip
22050 17:02:51.745068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640 RESULT=skip>
22051 17:02:51.793917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip>
22052 17:02:51.794342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640 RESULT=skip
22054 17:02:51.838692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass>
22055 17:02:51.839122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_656 RESULT=pass
22057 17:02:51.886599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip>
22058 17:02:51.887027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656 RESULT=skip
22060 17:02:51.929406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip>
22061 17:02:51.929806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656 RESULT=skip
22063 17:02:51.970452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip>
22064 17:02:51.970875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656 RESULT=skip
22066 17:02:52.011138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass>
22067 17:02:52.011531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_672 RESULT=pass
22069 17:02:52.055284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip>
22070 17:02:52.055838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672 RESULT=skip
22072 17:02:52.097641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip>
22073 17:02:52.098040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672 RESULT=skip
22075 17:02:52.145488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip
22077 17:02:52.146255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672 RESULT=skip>
22078 17:02:52.184692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass
22080 17:02:52.185171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_688 RESULT=pass>
22081 17:02:52.226482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip>
22082 17:02:52.226906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688 RESULT=skip
22084 17:02:52.269383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip>
22085 17:02:52.269903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688 RESULT=skip
22087 17:02:52.309109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip>
22088 17:02:52.309539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688 RESULT=skip
22090 17:02:52.350039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass>
22091 17:02:52.350426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_704 RESULT=pass
22093 17:02:52.397371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip>
22094 17:02:52.397803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704 RESULT=skip
22096 17:02:52.449081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip
22098 17:02:52.449543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704 RESULT=skip>
22099 17:02:52.490458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip>
22100 17:02:52.490892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704 RESULT=skip
22102 17:02:52.543346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass>
22103 17:02:52.543835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_720 RESULT=pass
22105 17:02:52.585816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip>
22106 17:02:52.586364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720 RESULT=skip
22108 17:02:52.632540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip>
22109 17:02:52.632989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720 RESULT=skip
22111 17:02:52.673005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip>
22112 17:02:52.673425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720 RESULT=skip
22114 17:02:52.718811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass>
22115 17:02:52.719272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_736 RESULT=pass
22117 17:02:52.766660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip
22119 17:02:52.767131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736 RESULT=skip>
22120 17:02:52.813896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip>
22121 17:02:52.814333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736 RESULT=skip
22123 17:02:52.860599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip>
22124 17:02:52.861048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736 RESULT=skip
22126 17:02:52.909662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass>
22127 17:02:52.910078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_752 RESULT=pass
22129 17:02:52.958468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip>
22130 17:02:52.958897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752 RESULT=skip
22132 17:02:53.009488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip
22134 17:02:53.009980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752 RESULT=skip>
22135 17:02:53.057577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip
22137 17:02:53.058054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752 RESULT=skip>
22138 17:02:53.101191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass>
22139 17:02:53.101601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_768 RESULT=pass
22141 17:02:53.147461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip
22143 17:02:53.148182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768 RESULT=skip>
22144 17:02:53.188482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip>
22145 17:02:53.188906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768 RESULT=skip
22147 17:02:53.228894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip
22149 17:02:53.229367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768 RESULT=skip>
22150 17:02:53.269921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass>
22151 17:02:53.270307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_784 RESULT=pass
22153 17:02:53.315220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip>
22154 17:02:53.315638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784 RESULT=skip
22156 17:02:53.373337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip>
22157 17:02:53.373760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784 RESULT=skip
22159 17:02:53.429723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip>
22160 17:02:53.430143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784 RESULT=skip
22162 17:02:53.481494 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass
22164 17:02:53.481955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_800 RESULT=pass>
22165 17:02:53.535844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip
22167 17:02:53.536312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800 RESULT=skip>
22168 17:02:53.586372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip>
22169 17:02:53.586813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800 RESULT=skip
22171 17:02:53.629058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip>
22172 17:02:53.629450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800 RESULT=skip
22174 17:02:53.681375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass>
22175 17:02:53.681794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_816 RESULT=pass
22177 17:02:53.730337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip
22179 17:02:53.730761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816 RESULT=skip>
22180 17:02:53.777194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip
22182 17:02:53.777907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816 RESULT=skip>
22183 17:02:53.826643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip
22185 17:02:53.827081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816 RESULT=skip>
22186 17:02:53.875115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass
22188 17:02:53.875549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_832 RESULT=pass>
22189 17:02:53.925010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip>
22190 17:02:53.925446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832 RESULT=skip
22192 17:02:53.976594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip>
22193 17:02:53.977021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832 RESULT=skip
22195 17:02:54.026343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip>
22196 17:02:54.026781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832 RESULT=skip
22198 17:02:54.077433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass
22200 17:02:54.077897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_848 RESULT=pass>
22201 17:02:54.121158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip
22203 17:02:54.121603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848 RESULT=skip>
22204 17:02:54.164970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip
22206 17:02:54.165431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848 RESULT=skip>
22207 17:02:54.206774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip>
22208 17:02:54.207202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848 RESULT=skip
22210 17:02:54.252182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass>
22211 17:02:54.252638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_864 RESULT=pass
22213 17:02:54.301290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip>
22214 17:02:54.301763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864 RESULT=skip
22216 17:02:54.349631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip>
22217 17:02:54.350050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864 RESULT=skip
22219 17:02:54.397002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip>
22220 17:02:54.397424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864 RESULT=skip
22222 17:02:54.445536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass
22224 17:02:54.446002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_880 RESULT=pass>
22225 17:02:54.489191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip>
22226 17:02:54.489583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880 RESULT=skip
22228 17:02:54.530847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip>
22229 17:02:54.531279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880 RESULT=skip
22231 17:02:54.570775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip
22233 17:02:54.571288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880 RESULT=skip>
22234 17:02:54.623511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass>
22235 17:02:54.623918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_896 RESULT=pass
22237 17:02:54.673439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip>
22238 17:02:54.673851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896 RESULT=skip
22240 17:02:54.727004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip>
22241 17:02:54.727397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896 RESULT=skip
22243 17:02:54.788384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip>
22244 17:02:54.788816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896 RESULT=skip
22246 17:02:54.843895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass
22248 17:02:54.844455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_912 RESULT=pass>
22249 17:02:54.899621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip
22251 17:02:54.900102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912 RESULT=skip>
22252 17:02:54.938711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip>
22253 17:02:54.939143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912 RESULT=skip
22255 17:02:54.989202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip
22257 17:02:54.989661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912 RESULT=skip>
22258 17:02:55.034199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass>
22259 17:02:55.034635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_928 RESULT=pass
22261 17:02:55.083852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip
22263 17:02:55.084357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928 RESULT=skip>
22264 17:02:55.137221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip>
22265 17:02:55.137618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928 RESULT=skip
22267 17:02:55.179150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip>
22268 17:02:55.179545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928 RESULT=skip
22270 17:02:55.225343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass>
22271 17:02:55.225741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_944 RESULT=pass
22273 17:02:55.295221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip>
22274 17:02:55.295644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944 RESULT=skip
22276 17:02:55.345331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip>
22277 17:02:55.345735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944 RESULT=skip
22279 17:02:55.388922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip>
22280 17:02:55.389360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944 RESULT=skip
22282 17:02:55.433192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass>
22283 17:02:55.433636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_960 RESULT=pass
22285 17:02:55.485115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip>
22286 17:02:55.485674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960 RESULT=skip
22288 17:02:55.531175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip>
22289 17:02:55.531620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960 RESULT=skip
22291 17:02:55.571886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip
22293 17:02:55.572362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960 RESULT=skip>
22294 17:02:55.618670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass>
22295 17:02:55.619115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_976 RESULT=pass
22297 17:02:55.664750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip>
22298 17:02:55.665191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976 RESULT=skip
22300 17:02:55.713769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip>
22301 17:02:55.714140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976 RESULT=skip
22303 17:02:55.759200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip>
22304 17:02:55.759624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976 RESULT=skip
22306 17:02:55.807073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass>
22307 17:02:55.807466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_992 RESULT=pass
22309 17:02:55.843248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip>
22310 17:02:55.843818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992 RESULT=skip
22312 17:02:55.886237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip>
22313 17:02:55.886686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992 RESULT=skip
22315 17:02:55.933203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip>
22316 17:02:55.933630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992 RESULT=skip
22318 17:02:55.980397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass>
22319 17:02:55.980961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1008 RESULT=pass
22321 17:02:56.019380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip>
22322 17:02:56.019813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008 RESULT=skip
22324 17:02:56.062730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip
22326 17:02:56.063174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008 RESULT=skip>
22327 17:02:56.110405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip>
22328 17:02:56.110762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008 RESULT=skip
22330 17:02:56.157916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass>
22331 17:02:56.158324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1024 RESULT=pass
22333 17:02:56.208056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip
22335 17:02:56.208468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024 RESULT=skip>
22336 17:02:56.259346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip>
22337 17:02:56.259714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024 RESULT=skip
22339 17:02:56.313083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip
22341 17:02:56.313804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024 RESULT=skip>
22342 17:02:56.356931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass>
22343 17:02:56.357331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1040 RESULT=pass
22345 17:02:56.403445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip>
22346 17:02:56.403833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040 RESULT=skip
22348 17:02:56.449112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip
22350 17:02:56.449500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040 RESULT=skip>
22351 17:02:56.501980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip
22353 17:02:56.502404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040 RESULT=skip>
22354 17:02:56.555476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass
22356 17:02:56.555961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1056 RESULT=pass>
22357 17:02:56.609629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip>
22358 17:02:56.610023 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056 RESULT=skip
22360 17:02:56.662068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip>
22361 17:02:56.662461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056 RESULT=skip
22363 17:02:56.715166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip>
22364 17:02:56.715580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056 RESULT=skip
22366 17:02:56.769250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass>
22367 17:02:56.769692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1072 RESULT=pass
22369 17:02:56.822918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip>
22370 17:02:56.823316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072 RESULT=skip
22372 17:02:56.875615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip>
22373 17:02:56.876030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072 RESULT=skip
22375 17:02:56.927401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip>
22376 17:02:56.927792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072 RESULT=skip
22378 17:02:56.982191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass>
22379 17:02:56.982606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1088 RESULT=pass
22381 17:02:57.025237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip
22383 17:02:57.026013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088 RESULT=skip>
22384 17:02:57.066086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip>
22385 17:02:57.066534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088 RESULT=skip
22387 17:02:57.107307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip
22389 17:02:57.107768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088 RESULT=skip>
22390 17:02:57.153393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass>
22391 17:02:57.153827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1104 RESULT=pass
22393 17:02:57.197365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip>
22394 17:02:57.197771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104 RESULT=skip
22396 17:02:57.244297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip>
22397 17:02:57.244722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104 RESULT=skip
22399 17:02:57.291448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip>
22400 17:02:57.292101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104 RESULT=skip
22402 17:02:57.347334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass>
22403 17:02:57.347771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1120 RESULT=pass
22405 17:02:57.402299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip
22407 17:02:57.403011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120 RESULT=skip>
22408 17:02:57.455240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip>
22409 17:02:57.455786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120 RESULT=skip
22411 17:02:57.509074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip>
22412 17:02:57.509558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120 RESULT=skip
22414 17:02:57.561552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass
22416 17:02:57.561982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1136 RESULT=pass>
22417 17:02:57.610469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip>
22418 17:02:57.610882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136 RESULT=skip
22420 17:02:57.660798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip>
22421 17:02:57.661239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136 RESULT=skip
22423 17:02:57.707936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip
22425 17:02:57.708421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136 RESULT=skip>
22426 17:02:57.750499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass>
22427 17:02:57.750896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1152 RESULT=pass
22429 17:02:57.792544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip>
22430 17:02:57.792960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152 RESULT=skip
22432 17:02:57.835280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip
22434 17:02:57.835767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152 RESULT=skip>
22435 17:02:57.883958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip
22437 17:02:57.884443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152 RESULT=skip>
22438 17:02:57.929846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass>
22439 17:02:57.930244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1168 RESULT=pass
22441 17:02:57.974667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip>
22442 17:02:57.975116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168 RESULT=skip
22444 17:02:58.025852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip>
22445 17:02:58.026277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168 RESULT=skip
22447 17:02:58.073183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip>
22448 17:02:58.073615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168 RESULT=skip
22450 17:02:58.118750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass>
22451 17:02:58.119179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1184 RESULT=pass
22453 17:02:58.167161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip
22455 17:02:58.167657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184 RESULT=skip>
22456 17:02:58.214141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip>
22457 17:02:58.214546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184 RESULT=skip
22459 17:02:58.264042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip
22461 17:02:58.264509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184 RESULT=skip>
22462 17:02:58.308902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass>
22463 17:02:58.309331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1200 RESULT=pass
22465 17:02:58.358592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip>
22466 17:02:58.359047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200 RESULT=skip
22468 17:02:58.409342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip>
22469 17:02:58.409858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200 RESULT=skip
22471 17:02:58.453967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip>
22472 17:02:58.454411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200 RESULT=skip
22474 17:02:58.497167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass>
22475 17:02:58.497586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1216 RESULT=pass
22477 17:02:58.543095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip>
22478 17:02:58.543653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216 RESULT=skip
22480 17:02:58.588501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip>
22481 17:02:58.588948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216 RESULT=skip
22483 17:02:58.633701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip>
22484 17:02:58.634098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216 RESULT=skip
22486 17:02:58.682092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass>
22487 17:02:58.682526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1232 RESULT=pass
22489 17:02:58.730406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip
22491 17:02:58.730871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232 RESULT=skip>
22492 17:02:58.784395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip>
22493 17:02:58.784826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232 RESULT=skip
22495 17:02:58.844038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip
22497 17:02:58.844503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232 RESULT=skip>
22498 17:02:58.885401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass>
22499 17:02:58.885850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1248 RESULT=pass
22501 17:02:58.923908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip
22503 17:02:58.924542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248 RESULT=skip>
22504 17:02:58.978803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip
22506 17:02:58.979560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248 RESULT=skip>
22507 17:02:59.028447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip>
22508 17:02:59.028934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248 RESULT=skip
22510 17:02:59.071089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass>
22511 17:02:59.071480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1264 RESULT=pass
22513 17:02:59.119014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip>
22514 17:02:59.119410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264 RESULT=skip
22516 17:02:59.171185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip
22518 17:02:59.171660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264 RESULT=skip>
22519 17:02:59.218919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip>
22520 17:02:59.219354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264 RESULT=skip
22522 17:02:59.265561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass>
22523 17:02:59.265989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1280 RESULT=pass
22525 17:02:59.312031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip
22527 17:02:59.312507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280 RESULT=skip>
22528 17:02:59.366350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip>
22529 17:02:59.366772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280 RESULT=skip
22531 17:02:59.409951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip>
22532 17:02:59.410336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280 RESULT=skip
22534 17:02:59.450136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass>
22535 17:02:59.450577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1296 RESULT=pass
22537 17:02:59.494555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip>
22538 17:02:59.495354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296 RESULT=skip
22540 17:02:59.542082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip
22542 17:02:59.542539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296 RESULT=skip>
22543 17:02:59.582655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip>
22544 17:02:59.583151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296 RESULT=skip
22546 17:02:59.621059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass>
22547 17:02:59.621507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1312 RESULT=pass
22549 17:02:59.661153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip
22551 17:02:59.661578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312 RESULT=skip>
22552 17:02:59.711505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip>
22553 17:02:59.711934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312 RESULT=skip
22555 17:02:59.748859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip
22557 17:02:59.749324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312 RESULT=skip>
22558 17:02:59.786425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass>
22559 17:02:59.787011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1328 RESULT=pass
22561 17:02:59.833237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip>
22562 17:02:59.833692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328 RESULT=skip
22564 17:02:59.886754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip>
22565 17:02:59.887187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328 RESULT=skip
22567 17:02:59.939556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip>
22568 17:02:59.939975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328 RESULT=skip
22570 17:02:59.993616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass
22572 17:02:59.994089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1344 RESULT=pass>
22573 17:03:00.049970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip>
22574 17:03:00.050353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344 RESULT=skip
22576 17:03:00.102182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip>
22577 17:03:00.102619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344 RESULT=skip
22579 17:03:00.156539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip>
22580 17:03:00.156923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344 RESULT=skip
22582 17:03:00.206647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass
22584 17:03:00.207127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1360 RESULT=pass>
22585 17:03:00.249160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip>
22586 17:03:00.249608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360 RESULT=skip
22588 17:03:00.299222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip>
22589 17:03:00.299618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360 RESULT=skip
22591 17:03:00.354738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip>
22592 17:03:00.355127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360 RESULT=skip
22594 17:03:00.434874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass>
22595 17:03:00.435321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1376 RESULT=pass
22597 17:03:00.482230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip>
22598 17:03:00.482651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376 RESULT=skip
22600 17:03:00.527896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip
22602 17:03:00.528344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376 RESULT=skip>
22603 17:03:00.577715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip
22605 17:03:00.578179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376 RESULT=skip>
22606 17:03:00.629779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass>
22607 17:03:00.630192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1392 RESULT=pass
22609 17:03:00.675355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip>
22610 17:03:00.675786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392 RESULT=skip
22612 17:03:00.727058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip
22614 17:03:00.727707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392 RESULT=skip>
22615 17:03:00.769566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip>
22616 17:03:00.770026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392 RESULT=skip
22618 17:03:00.820426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass
22620 17:03:00.821203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1408 RESULT=pass>
22621 17:03:00.865139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip>
22622 17:03:00.865567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408 RESULT=skip
22624 17:03:00.909142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip>
22625 17:03:00.909608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408 RESULT=skip
22627 17:03:00.950411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip
22629 17:03:00.950876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408 RESULT=skip>
22630 17:03:00.989022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass
22632 17:03:00.989493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1424 RESULT=pass>
22633 17:03:01.033826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip>
22634 17:03:01.034227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424 RESULT=skip
22636 17:03:01.076619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip>
22637 17:03:01.077053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424 RESULT=skip
22639 17:03:01.116053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip>
22640 17:03:01.116502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424 RESULT=skip
22642 17:03:01.165241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass>
22643 17:03:01.165693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1440 RESULT=pass
22645 17:03:01.211009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip>
22646 17:03:01.211408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440 RESULT=skip
22648 17:03:01.259412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip>
22649 17:03:01.259846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440 RESULT=skip
22651 17:03:01.303183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip>
22652 17:03:01.303641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440 RESULT=skip
22654 17:03:01.345469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass>
22655 17:03:01.345907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1456 RESULT=pass
22657 17:03:01.393992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip>
22658 17:03:01.394427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456 RESULT=skip
22660 17:03:01.438539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip>
22661 17:03:01.438972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456 RESULT=skip
22663 17:03:01.479480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip>
22664 17:03:01.479921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456 RESULT=skip
22666 17:03:01.525990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass>
22667 17:03:01.526432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1472 RESULT=pass
22669 17:03:01.570589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip>
22670 17:03:01.570999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472 RESULT=skip
22672 17:03:01.609070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip>
22673 17:03:01.609496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472 RESULT=skip
22675 17:03:01.649110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip>
22676 17:03:01.649498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472 RESULT=skip
22678 17:03:01.691922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass
22680 17:03:01.692444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1488 RESULT=pass>
22681 17:03:01.738553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip>
22682 17:03:01.739031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488 RESULT=skip
22684 17:03:01.786935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip>
22685 17:03:01.787356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488 RESULT=skip
22687 17:03:01.833151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip>
22688 17:03:01.833578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488 RESULT=skip
22690 17:03:01.881015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass
22692 17:03:01.881501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1504 RESULT=pass>
22693 17:03:01.926836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip>
22694 17:03:01.927290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504 RESULT=skip
22696 17:03:01.969713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip>
22697 17:03:01.970130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504 RESULT=skip
22699 17:03:02.011592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip
22701 17:03:02.012046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504 RESULT=skip>
22702 17:03:02.057785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass>
22703 17:03:02.058204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1520 RESULT=pass
22705 17:03:02.104659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip
22707 17:03:02.105088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520 RESULT=skip>
22708 17:03:02.150454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip>
22709 17:03:02.150847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520 RESULT=skip
22711 17:03:02.202789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip>
22712 17:03:02.203204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520 RESULT=skip
22714 17:03:02.255183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass
22716 17:03:02.255585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1536 RESULT=pass>
22717 17:03:02.305433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip>
22718 17:03:02.305879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536 RESULT=skip
22720 17:03:02.349560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip>
22721 17:03:02.349995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536 RESULT=skip
22723 17:03:02.391643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip>
22724 17:03:02.392062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536 RESULT=skip
22726 17:03:02.440760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass>
22727 17:03:02.441120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1552 RESULT=pass
22729 17:03:02.491042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip>
22730 17:03:02.491479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552 RESULT=skip
22732 17:03:02.540963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip
22734 17:03:02.541442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552 RESULT=skip>
22735 17:03:02.589178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip>
22736 17:03:02.589676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552 RESULT=skip
22738 17:03:02.629849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass>
22739 17:03:02.630293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1568 RESULT=pass
22741 17:03:02.676876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip
22743 17:03:02.677354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568 RESULT=skip>
22744 17:03:02.721576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip>
22745 17:03:02.722017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568 RESULT=skip
22747 17:03:02.769200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip>
22748 17:03:02.769630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568 RESULT=skip
22750 17:03:02.813916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass
22752 17:03:02.814378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1584 RESULT=pass>
22753 17:03:02.866648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip>
22754 17:03:02.867101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584 RESULT=skip
22756 17:03:02.915257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip>
22757 17:03:02.915677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584 RESULT=skip
22759 17:03:02.966979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip>
22760 17:03:02.967535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584 RESULT=skip
22762 17:03:03.013518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass
22764 17:03:03.013983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1600 RESULT=pass>
22765 17:03:03.061172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip>
22766 17:03:03.061604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600 RESULT=skip
22768 17:03:03.107282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip>
22769 17:03:03.107708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600 RESULT=skip
22771 17:03:03.155792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip
22773 17:03:03.156380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600 RESULT=skip>
22774 17:03:03.198229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass
22776 17:03:03.198699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1616 RESULT=pass>
22777 17:03:03.244087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip
22779 17:03:03.244542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616 RESULT=skip>
22780 17:03:03.295096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip>
22781 17:03:03.295518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616 RESULT=skip
22783 17:03:03.341214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip>
22784 17:03:03.341642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616 RESULT=skip
22786 17:03:03.389266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass
22788 17:03:03.389745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1632 RESULT=pass>
22789 17:03:03.437183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip
22791 17:03:03.437644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632 RESULT=skip>
22792 17:03:03.484594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip
22794 17:03:03.485047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632 RESULT=skip>
22795 17:03:03.530127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip>
22796 17:03:03.530557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632 RESULT=skip
22798 17:03:03.573989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass>
22799 17:03:03.574418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1648 RESULT=pass
22801 17:03:03.623173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip>
22802 17:03:03.623599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648 RESULT=skip
22804 17:03:03.670099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip>
22805 17:03:03.670505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648 RESULT=skip
22807 17:03:03.714045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip
22809 17:03:03.714517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648 RESULT=skip>
22810 17:03:03.757063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass>
22811 17:03:03.757479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1664 RESULT=pass
22813 17:03:03.798383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip>
22814 17:03:03.798808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664 RESULT=skip
22816 17:03:03.843154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip
22818 17:03:03.843629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664 RESULT=skip>
22819 17:03:03.883085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip>
22820 17:03:03.883487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664 RESULT=skip
22822 17:03:03.931153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass>
22823 17:03:03.931589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1680 RESULT=pass
22825 17:03:03.972651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip>
22826 17:03:03.973040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680 RESULT=skip
22828 17:03:04.018733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip>
22829 17:03:04.019137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680 RESULT=skip
22831 17:03:04.065761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip>
22832 17:03:04.066212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680 RESULT=skip
22834 17:03:04.112493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass
22836 17:03:04.112977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1696 RESULT=pass>
22837 17:03:04.148894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip
22839 17:03:04.149353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696 RESULT=skip>
22840 17:03:04.193855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip>
22841 17:03:04.194241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696 RESULT=skip
22843 17:03:04.237305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip
22845 17:03:04.237790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696 RESULT=skip>
22846 17:03:04.287492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass
22848 17:03:04.288003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1712 RESULT=pass>
22849 17:03:04.337384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip>
22850 17:03:04.337813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712 RESULT=skip
22852 17:03:04.388486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip
22854 17:03:04.388925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712 RESULT=skip>
22855 17:03:04.438034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip>
22856 17:03:04.438477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712 RESULT=skip
22858 17:03:04.484682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass
22860 17:03:04.485152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1728 RESULT=pass>
22861 17:03:04.530823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip
22863 17:03:04.531285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728 RESULT=skip>
22864 17:03:04.575817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip
22866 17:03:04.576208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728 RESULT=skip>
22867 17:03:04.621084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip>
22868 17:03:04.621516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728 RESULT=skip
22870 17:03:04.665496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass
22872 17:03:04.666297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1744 RESULT=pass>
22873 17:03:04.714637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip>
22874 17:03:04.715062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744 RESULT=skip
22876 17:03:04.760572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip>
22877 17:03:04.761017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744 RESULT=skip
22879 17:03:04.797353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip>
22880 17:03:04.797788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744 RESULT=skip
22882 17:03:04.838207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass>
22883 17:03:04.838645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1760 RESULT=pass
22885 17:03:04.884844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip>
22886 17:03:04.885271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760 RESULT=skip
22888 17:03:04.951089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip>
22889 17:03:04.951581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760 RESULT=skip
22891 17:03:05.001515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip
22893 17:03:05.001977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760 RESULT=skip>
22894 17:03:05.049758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass>
22895 17:03:05.050222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1776 RESULT=pass
22897 17:03:05.102435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip>
22898 17:03:05.102891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776 RESULT=skip
22900 17:03:05.158611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip>
22901 17:03:05.159006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776 RESULT=skip
22903 17:03:05.223956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip
22905 17:03:05.224450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776 RESULT=skip>
22906 17:03:05.269980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass>
22907 17:03:05.270407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1792 RESULT=pass
22909 17:03:05.315771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip
22911 17:03:05.316239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792 RESULT=skip>
22912 17:03:05.369164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip>
22913 17:03:05.369611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792 RESULT=skip
22915 17:03:05.418544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip>
22916 17:03:05.418961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792 RESULT=skip
22918 17:03:05.468130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass>
22919 17:03:05.468565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1808 RESULT=pass
22921 17:03:05.545694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip
22923 17:03:05.546164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808 RESULT=skip>
22924 17:03:05.605099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip>
22925 17:03:05.605541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808 RESULT=skip
22927 17:03:05.658468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip>
22928 17:03:05.658900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808 RESULT=skip
22930 17:03:05.715282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass>
22931 17:03:05.715690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1824 RESULT=pass
22933 17:03:05.777977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip>
22934 17:03:05.778385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824 RESULT=skip
22936 17:03:05.838002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip>
22937 17:03:05.838467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824 RESULT=skip
22939 17:03:05.890420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip>
22940 17:03:05.890846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824 RESULT=skip
22942 17:03:05.932881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass>
22943 17:03:05.933268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1840 RESULT=pass
22945 17:03:05.975758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip
22947 17:03:05.976418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840 RESULT=skip>
22948 17:03:06.029943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip>
22949 17:03:06.030383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840 RESULT=skip
22951 17:03:06.081976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip>
22952 17:03:06.082422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840 RESULT=skip
22954 17:03:06.135274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass>
22955 17:03:06.135716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1856 RESULT=pass
22957 17:03:06.187896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip
22959 17:03:06.188320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856 RESULT=skip>
22960 17:03:06.233222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip>
22961 17:03:06.233692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856 RESULT=skip
22963 17:03:06.281899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip>
22964 17:03:06.282290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856 RESULT=skip
22966 17:03:06.333516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass
22968 17:03:06.333947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1872 RESULT=pass>
22969 17:03:06.387037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip>
22970 17:03:06.387461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872 RESULT=skip
22972 17:03:06.435582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip>
22973 17:03:06.436020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872 RESULT=skip
22975 17:03:06.491454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip>
22976 17:03:06.491898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872 RESULT=skip
22978 17:03:06.545671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass>
22979 17:03:06.546109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1888 RESULT=pass
22981 17:03:06.603209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip
22983 17:03:06.603647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888 RESULT=skip>
22984 17:03:06.654024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip
22986 17:03:06.654521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888 RESULT=skip>
22987 17:03:06.706256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip>
22988 17:03:06.706688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888 RESULT=skip
22990 17:03:06.762085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass>
22991 17:03:06.762591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1904 RESULT=pass
22993 17:03:06.821663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip>
22994 17:03:06.822074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904 RESULT=skip
22996 17:03:06.881983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip
22998 17:03:06.882407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904 RESULT=skip>
22999 17:03:06.941971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip>
23000 17:03:06.942407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904 RESULT=skip
23002 17:03:07.001115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass>
23003 17:03:07.001576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1920 RESULT=pass
23005 17:03:07.059463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip>
23006 17:03:07.059899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920 RESULT=skip
23008 17:03:07.110046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip>
23009 17:03:07.110491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920 RESULT=skip
23011 17:03:07.165004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip>
23012 17:03:07.165450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920 RESULT=skip
23014 17:03:07.209707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass>
23015 17:03:07.210163 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1936 RESULT=pass
23017 17:03:07.251108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip>
23018 17:03:07.251544 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936 RESULT=skip
23020 17:03:07.291446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip>
23021 17:03:07.291882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936 RESULT=skip
23023 17:03:07.337207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip>
23024 17:03:07.337637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936 RESULT=skip
23026 17:03:07.389387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass>
23027 17:03:07.389857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1952 RESULT=pass
23029 17:03:07.440699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip
23031 17:03:07.441122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952 RESULT=skip>
23032 17:03:07.493097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip>
23033 17:03:07.493522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952 RESULT=skip
23035 17:03:07.542500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip>
23036 17:03:07.542932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952 RESULT=skip
23038 17:03:07.593663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass
23040 17:03:07.594154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1968 RESULT=pass>
23041 17:03:07.653557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip
23043 17:03:07.654029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968 RESULT=skip>
23044 17:03:07.709104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip>
23045 17:03:07.709546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968 RESULT=skip
23047 17:03:07.765243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip
23049 17:03:07.765723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968 RESULT=skip>
23050 17:03:07.814823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass>
23051 17:03:07.815252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_1984 RESULT=pass
23053 17:03:07.870248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip>
23054 17:03:07.870665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984 RESULT=skip
23056 17:03:07.920789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip
23058 17:03:07.921255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984 RESULT=skip>
23059 17:03:07.971297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip>
23060 17:03:07.971729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984 RESULT=skip
23062 17:03:08.021920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass
23064 17:03:08.022413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2000 RESULT=pass>
23065 17:03:08.074298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip>
23066 17:03:08.074707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000 RESULT=skip
23068 17:03:08.127443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip>
23069 17:03:08.127837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000 RESULT=skip
23071 17:03:08.181087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip>
23072 17:03:08.181480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000 RESULT=skip
23074 17:03:08.228448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass>
23075 17:03:08.228894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2016 RESULT=pass
23077 17:03:08.278930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip>
23078 17:03:08.279368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016 RESULT=skip
23080 17:03:08.332903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip>
23081 17:03:08.333290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016 RESULT=skip
23083 17:03:08.381385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip>
23084 17:03:08.381802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016 RESULT=skip
23086 17:03:08.431561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass
23088 17:03:08.432065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2032 RESULT=pass>
23089 17:03:08.482096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip>
23090 17:03:08.482565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032 RESULT=skip
23092 17:03:08.529945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip>
23093 17:03:08.530388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032 RESULT=skip
23095 17:03:08.575385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip>
23096 17:03:08.575810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032 RESULT=skip
23098 17:03:08.627884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass
23100 17:03:08.628496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2048 RESULT=pass>
23101 17:03:08.678715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip>
23102 17:03:08.679153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048 RESULT=skip
23104 17:03:08.721903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip>
23105 17:03:08.722350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048 RESULT=skip
23107 17:03:08.768716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip>
23108 17:03:08.769162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048 RESULT=skip
23110 17:03:08.810031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass>
23111 17:03:08.810450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2064 RESULT=pass
23113 17:03:08.853102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip>
23114 17:03:08.853528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064 RESULT=skip
23116 17:03:08.897114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip>
23117 17:03:08.897586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064 RESULT=skip
23119 17:03:08.946306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip>
23120 17:03:08.946739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064 RESULT=skip
23122 17:03:08.997229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass
23124 17:03:08.997625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2080 RESULT=pass>
23125 17:03:09.041000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip>
23126 17:03:09.041419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080 RESULT=skip
23128 17:03:09.097788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip>
23129 17:03:09.098191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080 RESULT=skip
23131 17:03:09.154787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip
23133 17:03:09.155206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080 RESULT=skip>
23134 17:03:09.200677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass
23136 17:03:09.201152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2096 RESULT=pass>
23137 17:03:09.241770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip
23139 17:03:09.242275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096 RESULT=skip>
23140 17:03:09.282608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip
23142 17:03:09.283046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096 RESULT=skip>
23143 17:03:09.326764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip>
23144 17:03:09.327172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096 RESULT=skip
23146 17:03:09.377901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass
23148 17:03:09.378397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2112 RESULT=pass>
23149 17:03:09.428575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip>
23150 17:03:09.429031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112 RESULT=skip
23152 17:03:09.466825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip>
23153 17:03:09.467255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112 RESULT=skip
23155 17:03:09.510719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip>
23156 17:03:09.511159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112 RESULT=skip
23158 17:03:09.550181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass>
23159 17:03:09.550620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2128 RESULT=pass
23161 17:03:09.588758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip>
23162 17:03:09.589177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128 RESULT=skip
23164 17:03:09.634774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip
23166 17:03:09.635230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128 RESULT=skip>
23167 17:03:09.672643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip>
23168 17:03:09.673041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128 RESULT=skip
23170 17:03:09.714996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass
23172 17:03:09.715469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2144 RESULT=pass>
23173 17:03:09.758758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip>
23174 17:03:09.759175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144 RESULT=skip
23176 17:03:09.799954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip
23178 17:03:09.800351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144 RESULT=skip>
23179 17:03:09.843061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip>
23180 17:03:09.843451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144 RESULT=skip
23182 17:03:09.889570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass>
23183 17:03:09.890037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2160 RESULT=pass
23185 17:03:09.941376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip
23187 17:03:09.941885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160 RESULT=skip>
23188 17:03:10.001624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip>
23189 17:03:10.002077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160 RESULT=skip
23191 17:03:10.050587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip>
23192 17:03:10.051004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160 RESULT=skip
23194 17:03:10.108620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass>
23195 17:03:10.109067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2176 RESULT=pass
23197 17:03:10.158737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip>
23198 17:03:10.159171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176 RESULT=skip
23200 17:03:10.205602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip>
23201 17:03:10.206061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176 RESULT=skip
23203 17:03:10.253145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip>
23204 17:03:10.253576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176 RESULT=skip
23206 17:03:10.305239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass>
23207 17:03:10.305702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2192 RESULT=pass
23209 17:03:10.352426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip>
23210 17:03:10.352838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192 RESULT=skip
23212 17:03:10.402588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip>
23213 17:03:10.403055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192 RESULT=skip
23215 17:03:10.445785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip>
23216 17:03:10.446223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192 RESULT=skip
23218 17:03:10.485229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass
23220 17:03:10.485670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2208 RESULT=pass>
23221 17:03:10.532599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip>
23222 17:03:10.532988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208 RESULT=skip
23224 17:03:10.581172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip>
23225 17:03:10.581628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208 RESULT=skip
23227 17:03:10.649326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip>
23228 17:03:10.649755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208 RESULT=skip
23230 17:03:10.699695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass
23232 17:03:10.700160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2224 RESULT=pass>
23233 17:03:10.743373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip>
23234 17:03:10.743833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224 RESULT=skip
23236 17:03:10.782414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip>
23237 17:03:10.782848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224 RESULT=skip
23239 17:03:10.830107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip>
23240 17:03:10.830555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224 RESULT=skip
23242 17:03:10.876981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass>
23243 17:03:10.877441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2240 RESULT=pass
23245 17:03:10.920492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip
23247 17:03:10.920930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240 RESULT=skip>
23248 17:03:10.965444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip>
23249 17:03:10.965918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240 RESULT=skip
23251 17:03:11.005554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip>
23252 17:03:11.005962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240 RESULT=skip
23254 17:03:11.053916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass
23256 17:03:11.054376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2256 RESULT=pass>
23257 17:03:11.102826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip
23259 17:03:11.103303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256 RESULT=skip>
23260 17:03:11.147440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip>
23261 17:03:11.147882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256 RESULT=skip
23263 17:03:11.195319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip>
23264 17:03:11.195759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256 RESULT=skip
23266 17:03:11.241452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass>
23267 17:03:11.241933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2272 RESULT=pass
23269 17:03:11.286641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip
23271 17:03:11.287112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272 RESULT=skip>
23272 17:03:11.333640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip>
23273 17:03:11.334039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272 RESULT=skip
23275 17:03:11.377874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip>
23276 17:03:11.378309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272 RESULT=skip
23278 17:03:11.416222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass>
23279 17:03:11.416642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2288 RESULT=pass
23281 17:03:11.460784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip>
23282 17:03:11.461218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288 RESULT=skip
23284 17:03:11.510315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip>
23285 17:03:11.510758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288 RESULT=skip
23287 17:03:11.553881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip>
23288 17:03:11.554344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288 RESULT=skip
23290 17:03:11.595611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass
23292 17:03:11.596043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2304 RESULT=pass>
23293 17:03:11.642693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip>
23294 17:03:11.643282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304 RESULT=skip
23296 17:03:11.691645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip
23298 17:03:11.692088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304 RESULT=skip>
23299 17:03:11.734696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip>
23300 17:03:11.735146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304 RESULT=skip
23302 17:03:11.782597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass>
23303 17:03:11.783028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2320 RESULT=pass
23305 17:03:11.828392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip
23307 17:03:11.828777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320 RESULT=skip>
23308 17:03:11.875053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip>
23309 17:03:11.875489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320 RESULT=skip
23311 17:03:11.925723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip>
23312 17:03:11.926154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320 RESULT=skip
23314 17:03:11.972444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass
23316 17:03:11.972916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2336 RESULT=pass>
23317 17:03:12.023163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip>
23318 17:03:12.023525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336 RESULT=skip
23320 17:03:12.067280 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip
23322 17:03:12.067746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336 RESULT=skip>
23323 17:03:12.111502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip>
23324 17:03:12.111938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336 RESULT=skip
23326 17:03:12.152645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass>
23327 17:03:12.153047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2352 RESULT=pass
23329 17:03:12.199057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip>
23330 17:03:12.199487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352 RESULT=skip
23332 17:03:12.244484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip>
23333 17:03:12.244899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352 RESULT=skip
23335 17:03:12.285328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip>
23336 17:03:12.285756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352 RESULT=skip
23338 17:03:12.329385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass>
23339 17:03:12.329824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2368 RESULT=pass
23341 17:03:12.369659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip
23343 17:03:12.370092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368 RESULT=skip>
23344 17:03:12.409857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip>
23345 17:03:12.410291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368 RESULT=skip
23347 17:03:12.450156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip
23349 17:03:12.450636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368 RESULT=skip>
23350 17:03:12.502674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass
23352 17:03:12.503129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2384 RESULT=pass>
23353 17:03:12.545937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip>
23354 17:03:12.546380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384 RESULT=skip
23356 17:03:12.586688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip>
23357 17:03:12.587117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384 RESULT=skip
23359 17:03:12.638489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip>
23360 17:03:12.638885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384 RESULT=skip
23362 17:03:12.688754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass>
23363 17:03:12.689193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2400 RESULT=pass
23365 17:03:12.733203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip>
23366 17:03:12.733701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400 RESULT=skip
23368 17:03:12.780497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip
23370 17:03:12.781033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400 RESULT=skip>
23371 17:03:12.829770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip>
23372 17:03:12.830201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400 RESULT=skip
23374 17:03:12.878342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass
23376 17:03:12.878750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2416 RESULT=pass>
23377 17:03:12.915398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip>
23378 17:03:12.915842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416 RESULT=skip
23380 17:03:12.954235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip
23382 17:03:12.954616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416 RESULT=skip>
23383 17:03:13.001444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip>
23384 17:03:13.001873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416 RESULT=skip
23386 17:03:13.042538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass>
23387 17:03:13.042955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2432 RESULT=pass
23389 17:03:13.083972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip
23391 17:03:13.084478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432 RESULT=skip>
23392 17:03:13.126430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip>
23393 17:03:13.126833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432 RESULT=skip
23395 17:03:13.178781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip>
23396 17:03:13.179231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432 RESULT=skip
23398 17:03:13.228980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass
23400 17:03:13.229447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2448 RESULT=pass>
23401 17:03:13.274795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip>
23402 17:03:13.275208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448 RESULT=skip
23404 17:03:13.338780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip>
23405 17:03:13.339166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448 RESULT=skip
23407 17:03:13.394089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip
23409 17:03:13.394915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448 RESULT=skip>
23410 17:03:13.445054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass>
23411 17:03:13.445500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2464 RESULT=pass
23413 17:03:13.504571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip>
23414 17:03:13.504996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464 RESULT=skip
23416 17:03:13.563266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip>
23417 17:03:13.563703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464 RESULT=skip
23419 17:03:13.624391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip>
23420 17:03:13.624836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464 RESULT=skip
23422 17:03:13.682729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass
23424 17:03:13.683219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2480 RESULT=pass>
23425 17:03:13.741717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip>
23426 17:03:13.742142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480 RESULT=skip
23428 17:03:13.800513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip>
23429 17:03:13.800916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480 RESULT=skip
23431 17:03:13.852905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip>
23432 17:03:13.853343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480 RESULT=skip
23434 17:03:13.896862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass>
23435 17:03:13.897297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2496 RESULT=pass
23437 17:03:13.941547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip>
23438 17:03:13.942004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496 RESULT=skip
23440 17:03:13.986243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip>
23441 17:03:13.986679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496 RESULT=skip
23443 17:03:14.028116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip
23445 17:03:14.028569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496 RESULT=skip>
23446 17:03:14.079768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass>
23447 17:03:14.080276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2512 RESULT=pass
23449 17:03:14.138511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip>
23450 17:03:14.138930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512 RESULT=skip
23452 17:03:14.185814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip>
23453 17:03:14.186247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512 RESULT=skip
23455 17:03:14.226905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip>
23456 17:03:14.227315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512 RESULT=skip
23458 17:03:14.273135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass>
23459 17:03:14.273581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2528 RESULT=pass
23461 17:03:14.321608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip>
23462 17:03:14.322165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528 RESULT=skip
23464 17:03:14.365108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip>
23465 17:03:14.365555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528 RESULT=skip
23467 17:03:14.407201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip>
23468 17:03:14.407657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528 RESULT=skip
23470 17:03:14.459283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass>
23471 17:03:14.459732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2544 RESULT=pass
23473 17:03:14.505319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip>
23474 17:03:14.505738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544 RESULT=skip
23476 17:03:14.551247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip>
23477 17:03:14.551704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544 RESULT=skip
23479 17:03:14.601545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip>
23480 17:03:14.601971 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544 RESULT=skip
23482 17:03:14.646579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass>
23483 17:03:14.647005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2560 RESULT=pass
23485 17:03:14.688873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip>
23486 17:03:14.689312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560 RESULT=skip
23488 17:03:14.729587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip>
23489 17:03:14.730165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560 RESULT=skip
23491 17:03:14.775705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip
23493 17:03:14.776121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560 RESULT=skip>
23494 17:03:14.821442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass
23496 17:03:14.821911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2576 RESULT=pass>
23497 17:03:14.868786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip>
23498 17:03:14.869208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576 RESULT=skip
23500 17:03:14.921298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip>
23501 17:03:14.921695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576 RESULT=skip
23503 17:03:14.970552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip>
23504 17:03:14.970972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576 RESULT=skip
23506 17:03:15.013115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass>
23507 17:03:15.013545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2592 RESULT=pass
23509 17:03:15.054001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip>
23510 17:03:15.054578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592 RESULT=skip
23512 17:03:15.102296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip>
23513 17:03:15.102728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592 RESULT=skip
23515 17:03:15.151417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip
23517 17:03:15.151933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592 RESULT=skip>
23518 17:03:15.207728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass
23520 17:03:15.208228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2608 RESULT=pass>
23521 17:03:15.270285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip>
23522 17:03:15.270680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608 RESULT=skip
23524 17:03:15.310304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip>
23525 17:03:15.310746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608 RESULT=skip
23527 17:03:15.358131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip
23529 17:03:15.358558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608 RESULT=skip>
23530 17:03:15.399380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass>
23531 17:03:15.399788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2624 RESULT=pass
23533 17:03:15.444769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip>
23534 17:03:15.445168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624 RESULT=skip
23536 17:03:15.492872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip>
23537 17:03:15.493374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624 RESULT=skip
23539 17:03:15.553015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip>
23540 17:03:15.553537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624 RESULT=skip
23542 17:03:15.610841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass>
23543 17:03:15.611283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2640 RESULT=pass
23545 17:03:15.653243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip>
23546 17:03:15.653690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640 RESULT=skip
23548 17:03:15.693933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip>
23549 17:03:15.694342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640 RESULT=skip
23551 17:03:15.758597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip>
23552 17:03:15.759005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640 RESULT=skip
23554 17:03:15.805936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass>
23555 17:03:15.806352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2656 RESULT=pass
23557 17:03:15.867811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip
23559 17:03:15.868266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656 RESULT=skip>
23560 17:03:15.931469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip>
23561 17:03:15.933752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656 RESULT=skip
23563 17:03:15.984235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip
23565 17:03:15.984784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656 RESULT=skip>
23566 17:03:16.037877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass>
23567 17:03:16.038411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2672 RESULT=pass
23569 17:03:16.086949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip>
23570 17:03:16.087367 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672 RESULT=skip
23572 17:03:16.141079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip>
23573 17:03:16.141516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672 RESULT=skip
23575 17:03:16.192484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip
23577 17:03:16.193219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672 RESULT=skip>
23578 17:03:16.247152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass>
23579 17:03:16.247595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2688 RESULT=pass
23581 17:03:16.300412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip>
23582 17:03:16.300922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688 RESULT=skip
23584 17:03:16.348834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip
23586 17:03:16.349282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688 RESULT=skip>
23587 17:03:16.405103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip>
23588 17:03:16.405518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688 RESULT=skip
23590 17:03:16.454087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass>
23591 17:03:16.454530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2704 RESULT=pass
23593 17:03:16.505955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip>
23594 17:03:16.506361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704 RESULT=skip
23596 17:03:16.555277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip>
23597 17:03:16.555683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704 RESULT=skip
23599 17:03:16.603887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip
23601 17:03:16.604400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704 RESULT=skip>
23602 17:03:16.653357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass>
23603 17:03:16.653773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2720 RESULT=pass
23605 17:03:16.705627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip>
23606 17:03:16.706065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720 RESULT=skip
23608 17:03:16.762077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip>
23609 17:03:16.762501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720 RESULT=skip
23611 17:03:16.825460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip>
23612 17:03:16.825824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720 RESULT=skip
23614 17:03:16.876715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass>
23615 17:03:16.877124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2736 RESULT=pass
23617 17:03:16.939120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip
23619 17:03:16.939585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736 RESULT=skip>
23620 17:03:16.991892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip
23622 17:03:16.992509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736 RESULT=skip>
23623 17:03:17.051937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip
23625 17:03:17.052413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736 RESULT=skip>
23626 17:03:17.109696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass
23628 17:03:17.110101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2752 RESULT=pass>
23629 17:03:17.170607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip>
23630 17:03:17.171046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752 RESULT=skip
23632 17:03:17.231547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip>
23633 17:03:17.231940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752 RESULT=skip
23635 17:03:17.288741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip>
23636 17:03:17.289767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752 RESULT=skip
23638 17:03:17.337547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass
23640 17:03:17.338246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2768 RESULT=pass>
23641 17:03:17.383112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip>
23642 17:03:17.383558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768 RESULT=skip
23644 17:03:17.429693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip>
23645 17:03:17.430214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768 RESULT=skip
23647 17:03:17.476999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip>
23648 17:03:17.477437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768 RESULT=skip
23650 17:03:17.530172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass>
23651 17:03:17.530563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2784 RESULT=pass
23653 17:03:17.581502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip>
23654 17:03:17.581947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784 RESULT=skip
23656 17:03:17.630466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip>
23657 17:03:17.630900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784 RESULT=skip
23659 17:03:17.683476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip>
23660 17:03:17.683931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784 RESULT=skip
23662 17:03:17.726198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass>
23663 17:03:17.726634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2800 RESULT=pass
23665 17:03:17.775841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip
23667 17:03:17.776330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800 RESULT=skip>
23668 17:03:17.821155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip>
23669 17:03:17.821603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800 RESULT=skip
23671 17:03:17.871847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip
23673 17:03:17.872298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800 RESULT=skip>
23674 17:03:17.930083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass>
23675 17:03:17.930607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2816 RESULT=pass
23677 17:03:17.983052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip
23679 17:03:17.983832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816 RESULT=skip>
23680 17:03:18.038498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip
23682 17:03:18.039016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816 RESULT=skip>
23683 17:03:18.091054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip>
23684 17:03:18.091451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816 RESULT=skip
23686 17:03:18.135476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass
23688 17:03:18.135942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2832 RESULT=pass>
23689 17:03:18.180029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip
23691 17:03:18.180526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832 RESULT=skip>
23692 17:03:18.227590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip>
23693 17:03:18.228025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832 RESULT=skip
23695 17:03:18.278206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip
23697 17:03:18.278675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832 RESULT=skip>
23698 17:03:18.326524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass>
23699 17:03:18.326958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2848 RESULT=pass
23701 17:03:18.370670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip>
23702 17:03:18.371124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848 RESULT=skip
23704 17:03:18.422196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip
23706 17:03:18.422662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848 RESULT=skip>
23707 17:03:18.480739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip>
23708 17:03:18.481183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848 RESULT=skip
23710 17:03:18.537409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass>
23711 17:03:18.537883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2864 RESULT=pass
23713 17:03:18.590003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip>
23714 17:03:18.590422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864 RESULT=skip
23716 17:03:18.641537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip
23718 17:03:18.642051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864 RESULT=skip>
23719 17:03:18.688500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip>
23720 17:03:18.688904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864 RESULT=skip
23722 17:03:18.734617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass>
23723 17:03:18.735038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2880 RESULT=pass
23725 17:03:18.788224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip
23727 17:03:18.788838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880 RESULT=skip>
23728 17:03:18.852091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip
23730 17:03:18.852617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880 RESULT=skip>
23731 17:03:18.910499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip
23733 17:03:18.910970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880 RESULT=skip>
23734 17:03:18.969782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass>
23735 17:03:18.970248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2896 RESULT=pass
23737 17:03:19.027380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip
23739 17:03:19.027860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896 RESULT=skip>
23740 17:03:19.081536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip>
23741 17:03:19.081982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896 RESULT=skip
23743 17:03:19.138224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip>
23744 17:03:19.138657 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896 RESULT=skip
23746 17:03:19.201462 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass
23748 17:03:19.201940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2912 RESULT=pass>
23749 17:03:19.259842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip
23751 17:03:19.260528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912 RESULT=skip>
23752 17:03:19.319416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip>
23753 17:03:19.319854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912 RESULT=skip
23755 17:03:19.379567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip
23757 17:03:19.379986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912 RESULT=skip>
23758 17:03:19.434390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass>
23759 17:03:19.434853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2928 RESULT=pass
23761 17:03:19.491460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip>
23762 17:03:19.491889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928 RESULT=skip
23764 17:03:19.544957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip
23766 17:03:19.545441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928 RESULT=skip>
23767 17:03:19.603215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip>
23768 17:03:19.603673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928 RESULT=skip
23770 17:03:19.662521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass
23772 17:03:19.662957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2944 RESULT=pass>
23773 17:03:19.719103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip
23775 17:03:19.719577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944 RESULT=skip>
23776 17:03:19.771387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip>
23777 17:03:19.771814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944 RESULT=skip
23779 17:03:19.827903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip
23781 17:03:19.828412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944 RESULT=skip>
23782 17:03:19.885301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass>
23783 17:03:19.885749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2960 RESULT=pass
23785 17:03:19.942002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip>
23786 17:03:19.942467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960 RESULT=skip
23788 17:03:19.995050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip>
23789 17:03:19.995477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960 RESULT=skip
23791 17:03:20.054033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip>
23792 17:03:20.054471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960 RESULT=skip
23794 17:03:20.105540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass>
23795 17:03:20.105927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2976 RESULT=pass
23797 17:03:20.161584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip
23799 17:03:20.162078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976 RESULT=skip>
23800 17:03:20.209575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip
23802 17:03:20.210062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976 RESULT=skip>
23803 17:03:20.267625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip>
23804 17:03:20.268077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976 RESULT=skip
23806 17:03:20.327440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass
23808 17:03:20.327856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_2992 RESULT=pass>
23809 17:03:20.388429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip>
23810 17:03:20.388890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992 RESULT=skip
23812 17:03:20.450327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip
23814 17:03:20.450757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992 RESULT=skip>
23815 17:03:20.506556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip>
23816 17:03:20.507016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992 RESULT=skip
23818 17:03:20.570028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass>
23819 17:03:20.570481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3008 RESULT=pass
23821 17:03:20.628265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip
23823 17:03:20.628746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008 RESULT=skip>
23824 17:03:20.688252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip
23826 17:03:20.688744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008 RESULT=skip>
23827 17:03:20.742089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip
23829 17:03:20.742554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008 RESULT=skip>
23830 17:03:20.801472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass
23832 17:03:20.801970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3024 RESULT=pass>
23833 17:03:20.894277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip>
23834 17:03:20.894734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024 RESULT=skip
23836 17:03:20.952780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip>
23837 17:03:20.953223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024 RESULT=skip
23839 17:03:21.012937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip
23841 17:03:21.013400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024 RESULT=skip>
23842 17:03:21.072848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass>
23843 17:03:21.073279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3040 RESULT=pass
23845 17:03:21.129658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip>
23846 17:03:21.130097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040 RESULT=skip
23848 17:03:21.184964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip>
23849 17:03:21.185405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040 RESULT=skip
23851 17:03:21.243089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip>
23852 17:03:21.243539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040 RESULT=skip
23854 17:03:21.301703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass>
23855 17:03:21.302142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3056 RESULT=pass
23857 17:03:21.360028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip
23859 17:03:21.360518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056 RESULT=skip>
23860 17:03:21.419804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip
23862 17:03:21.420948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056 RESULT=skip>
23863 17:03:21.482310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip
23865 17:03:21.482739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056 RESULT=skip>
23866 17:03:21.542860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass
23868 17:03:21.543342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3072 RESULT=pass>
23869 17:03:21.602956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip
23871 17:03:21.603431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072 RESULT=skip>
23872 17:03:21.665783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip>
23873 17:03:21.666222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072 RESULT=skip
23875 17:03:21.726479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip>
23876 17:03:21.726923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072 RESULT=skip
23878 17:03:21.778111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass>
23879 17:03:21.778576 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3088 RESULT=pass
23881 17:03:21.836985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip>
23882 17:03:21.837398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088 RESULT=skip
23884 17:03:21.895360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip>
23885 17:03:21.895804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088 RESULT=skip
23887 17:03:21.947829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip
23889 17:03:21.948486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088 RESULT=skip>
23890 17:03:22.001962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass>
23891 17:03:22.002409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3104 RESULT=pass
23893 17:03:22.057500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip
23895 17:03:22.057997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104 RESULT=skip>
23896 17:03:22.113178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip
23898 17:03:22.113682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104 RESULT=skip>
23899 17:03:22.167708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip
23901 17:03:22.168283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104 RESULT=skip>
23902 17:03:22.221318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass
23904 17:03:22.221823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3120 RESULT=pass>
23905 17:03:22.275179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip
23907 17:03:22.275660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120 RESULT=skip>
23908 17:03:22.329177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip>
23909 17:03:22.329621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120 RESULT=skip
23911 17:03:22.383391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip
23913 17:03:22.383835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120 RESULT=skip>
23914 17:03:22.445382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass>
23915 17:03:22.445913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3136 RESULT=pass
23917 17:03:22.494845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip>
23918 17:03:22.495301 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136 RESULT=skip
23920 17:03:22.542229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip>
23921 17:03:22.542604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136 RESULT=skip
23923 17:03:22.589456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip>
23924 17:03:22.589912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136 RESULT=skip
23926 17:03:22.637659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass
23928 17:03:22.638139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3152 RESULT=pass>
23929 17:03:22.683730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip
23931 17:03:22.684174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152 RESULT=skip>
23932 17:03:22.729882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip>
23933 17:03:22.730349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152 RESULT=skip
23935 17:03:22.780956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip>
23936 17:03:22.781429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152 RESULT=skip
23938 17:03:22.833315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass
23940 17:03:22.833926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3168 RESULT=pass>
23941 17:03:22.875013 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip
23943 17:03:22.875486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168 RESULT=skip>
23944 17:03:22.918813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip>
23945 17:03:22.919239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168 RESULT=skip
23947 17:03:22.973782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip>
23948 17:03:22.974199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168 RESULT=skip
23950 17:03:23.029167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass>
23951 17:03:23.029595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3184 RESULT=pass
23953 17:03:23.087005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip
23955 17:03:23.087461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184 RESULT=skip>
23956 17:03:23.143741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip
23958 17:03:23.144166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184 RESULT=skip>
23959 17:03:23.194828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip>
23960 17:03:23.195291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184 RESULT=skip
23962 17:03:23.248819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass>
23963 17:03:23.249235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3200 RESULT=pass
23965 17:03:23.305227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip>
23966 17:03:23.305670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200 RESULT=skip
23968 17:03:23.352530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip>
23969 17:03:23.352960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200 RESULT=skip
23971 17:03:23.400897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip>
23972 17:03:23.401297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200 RESULT=skip
23974 17:03:23.446250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass>
23975 17:03:23.446712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3216 RESULT=pass
23977 17:03:23.504851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip>
23978 17:03:23.505296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216 RESULT=skip
23980 17:03:23.555698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip
23982 17:03:23.556172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216 RESULT=skip>
23983 17:03:23.614625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip>
23984 17:03:23.615066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216 RESULT=skip
23986 17:03:23.673215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass>
23987 17:03:23.673676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3232 RESULT=pass
23989 17:03:23.729562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip>
23990 17:03:23.730027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232 RESULT=skip
23992 17:03:23.791383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip>
23993 17:03:23.791829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232 RESULT=skip
23995 17:03:23.845951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip>
23996 17:03:23.846395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232 RESULT=skip
23998 17:03:23.901524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass
24000 17:03:23.902005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3248 RESULT=pass>
24001 17:03:23.962397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip
24003 17:03:23.962872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248 RESULT=skip>
24004 17:03:24.017608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip
24006 17:03:24.018140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248 RESULT=skip>
24007 17:03:24.070530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip
24009 17:03:24.071014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248 RESULT=skip>
24010 17:03:24.125472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass>
24011 17:03:24.125927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3264 RESULT=pass
24013 17:03:24.181662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip>
24014 17:03:24.182101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264 RESULT=skip
24016 17:03:24.233943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip>
24017 17:03:24.234412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264 RESULT=skip
24019 17:03:24.293896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip
24021 17:03:24.294373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264 RESULT=skip>
24022 17:03:24.347165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass
24024 17:03:24.347661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3280 RESULT=pass>
24025 17:03:24.402046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip>
24026 17:03:24.402482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280 RESULT=skip
24028 17:03:24.450237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip>
24029 17:03:24.450672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280 RESULT=skip
24031 17:03:24.505842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip>
24032 17:03:24.506287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280 RESULT=skip
24034 17:03:24.567212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass>
24035 17:03:24.567658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3296 RESULT=pass
24037 17:03:24.626644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip>
24038 17:03:24.627089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296 RESULT=skip
24040 17:03:24.684393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip>
24041 17:03:24.684842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296 RESULT=skip
24043 17:03:24.738319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip>
24044 17:03:24.738759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296 RESULT=skip
24046 17:03:24.795783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass
24048 17:03:24.796416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3312 RESULT=pass>
24049 17:03:24.847740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip
24051 17:03:24.848247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312 RESULT=skip>
24052 17:03:24.897866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip>
24053 17:03:24.898310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312 RESULT=skip
24055 17:03:24.953150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip
24057 17:03:24.953613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312 RESULT=skip>
24058 17:03:25.007969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass
24060 17:03:25.008437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3328 RESULT=pass>
24061 17:03:25.066135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip
24063 17:03:25.066652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328 RESULT=skip>
24064 17:03:25.115550 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip
24066 17:03:25.116024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328 RESULT=skip>
24067 17:03:25.177170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip>
24068 17:03:25.177617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328 RESULT=skip
24070 17:03:25.227877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass
24072 17:03:25.228444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3344 RESULT=pass>
24073 17:03:25.298349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip>
24074 17:03:25.298747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344 RESULT=skip
24076 17:03:25.358989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip>
24077 17:03:25.359423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344 RESULT=skip
24079 17:03:25.422381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip>
24080 17:03:25.422827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344 RESULT=skip
24082 17:03:25.474840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass
24084 17:03:25.475279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3360 RESULT=pass>
24085 17:03:25.529924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip>
24086 17:03:25.530375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360 RESULT=skip
24088 17:03:25.585365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip>
24089 17:03:25.585765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360 RESULT=skip
24091 17:03:25.637122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip>
24092 17:03:25.637558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360 RESULT=skip
24094 17:03:25.694658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass
24096 17:03:25.695138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3376 RESULT=pass>
24097 17:03:25.750592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip>
24098 17:03:25.750964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376 RESULT=skip
24100 17:03:25.803043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip>
24101 17:03:25.803482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376 RESULT=skip
24103 17:03:25.855285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip>
24104 17:03:25.855755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376 RESULT=skip
24106 17:03:25.910197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass>
24107 17:03:25.910661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3392 RESULT=pass
24109 17:03:25.993345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip>
24110 17:03:25.993787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392 RESULT=skip
24112 17:03:26.043688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip
24114 17:03:26.044139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392 RESULT=skip>
24115 17:03:26.099416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip>
24116 17:03:26.099862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392 RESULT=skip
24118 17:03:26.155952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass
24120 17:03:26.157108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3408 RESULT=pass>
24121 17:03:26.208454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip
24123 17:03:26.208942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408 RESULT=skip>
24124 17:03:26.263823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip
24126 17:03:26.264340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408 RESULT=skip>
24127 17:03:26.319346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip>
24128 17:03:26.319805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408 RESULT=skip
24130 17:03:26.378098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass>
24131 17:03:26.378536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3424 RESULT=pass
24133 17:03:26.431257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip>
24134 17:03:26.431694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424 RESULT=skip
24136 17:03:26.485027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip>
24137 17:03:26.485466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424 RESULT=skip
24139 17:03:26.540679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip>
24140 17:03:26.541123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424 RESULT=skip
24142 17:03:26.593203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass>
24143 17:03:26.593637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3440 RESULT=pass
24145 17:03:26.645579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip>
24146 17:03:26.646027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440 RESULT=skip
24148 17:03:26.700603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip
24150 17:03:26.701089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440 RESULT=skip>
24151 17:03:26.754154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip>
24152 17:03:26.754594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440 RESULT=skip
24154 17:03:26.808822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass>
24155 17:03:26.809241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3456 RESULT=pass
24157 17:03:26.863562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip>
24158 17:03:26.864021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456 RESULT=skip
24160 17:03:26.918717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip
24162 17:03:26.919140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456 RESULT=skip>
24163 17:03:26.973594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip>
24164 17:03:26.974054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456 RESULT=skip
24166 17:03:27.030952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass>
24167 17:03:27.031401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3472 RESULT=pass
24169 17:03:27.092549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip>
24170 17:03:27.092980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472 RESULT=skip
24172 17:03:27.150621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip>
24173 17:03:27.151073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472 RESULT=skip
24175 17:03:27.202828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip>
24176 17:03:27.203262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472 RESULT=skip
24178 17:03:27.260286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass>
24179 17:03:27.260739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3488 RESULT=pass
24181 17:03:27.308734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip>
24182 17:03:27.309183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488 RESULT=skip
24184 17:03:27.359421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip>
24185 17:03:27.359844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488 RESULT=skip
24187 17:03:27.415530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip
24189 17:03:27.416029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488 RESULT=skip>
24190 17:03:27.471231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass>
24191 17:03:27.471626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3504 RESULT=pass
24193 17:03:27.532808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip
24195 17:03:27.533288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504 RESULT=skip>
24196 17:03:27.585107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip>
24197 17:03:27.585559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504 RESULT=skip
24199 17:03:27.635793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip
24201 17:03:27.636310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504 RESULT=skip>
24202 17:03:27.687841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass
24204 17:03:27.688316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3520 RESULT=pass>
24205 17:03:27.743360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip>
24206 17:03:27.743760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520 RESULT=skip
24208 17:03:27.798199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip>
24209 17:03:27.798654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520 RESULT=skip
24211 17:03:27.858011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip>
24212 17:03:27.858448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520 RESULT=skip
24214 17:03:27.915273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass
24216 17:03:27.915761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3536 RESULT=pass>
24217 17:03:27.969790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip>
24218 17:03:27.970221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536 RESULT=skip
24220 17:03:28.025978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip>
24221 17:03:28.026433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536 RESULT=skip
24223 17:03:28.081505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip
24225 17:03:28.081999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536 RESULT=skip>
24226 17:03:28.140734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass>
24227 17:03:28.141195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3552 RESULT=pass
24229 17:03:28.195732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip
24231 17:03:28.196177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552 RESULT=skip>
24232 17:03:28.252241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip
24234 17:03:28.252793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552 RESULT=skip>
24235 17:03:28.307436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip>
24236 17:03:28.307837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552 RESULT=skip
24238 17:03:28.361790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass
24240 17:03:28.362287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3568 RESULT=pass>
24241 17:03:28.420019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip
24243 17:03:28.420716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568 RESULT=skip>
24244 17:03:28.474801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip>
24245 17:03:28.475244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568 RESULT=skip
24247 17:03:28.534746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip>
24248 17:03:28.535194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568 RESULT=skip
24250 17:03:28.600214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass
24252 17:03:28.600714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3584 RESULT=pass>
24253 17:03:28.653240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip>
24254 17:03:28.653687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584 RESULT=skip
24256 17:03:28.709258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip>
24257 17:03:28.709693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584 RESULT=skip
24259 17:03:28.768459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip>
24260 17:03:28.768884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584 RESULT=skip
24262 17:03:28.823259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass>
24263 17:03:28.823726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3600 RESULT=pass
24265 17:03:28.875760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip
24267 17:03:28.876207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600 RESULT=skip>
24268 17:03:28.937883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip
24270 17:03:28.938343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600 RESULT=skip>
24271 17:03:28.998832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip>
24272 17:03:28.999269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600 RESULT=skip
24274 17:03:29.060031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass>
24275 17:03:29.060496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3616 RESULT=pass
24277 17:03:29.117761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip>
24278 17:03:29.118207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616 RESULT=skip
24280 17:03:29.178574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip>
24281 17:03:29.179017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616 RESULT=skip
24283 17:03:29.237713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip>
24284 17:03:29.238159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616 RESULT=skip
24286 17:03:29.298010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass>
24287 17:03:29.298444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3632 RESULT=pass
24289 17:03:29.359426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip>
24290 17:03:29.359867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632 RESULT=skip
24292 17:03:29.419781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip
24294 17:03:29.420266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632 RESULT=skip>
24295 17:03:29.482857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip>
24296 17:03:29.483255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632 RESULT=skip
24298 17:03:29.549868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass>
24299 17:03:29.550321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3648 RESULT=pass
24301 17:03:29.609310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip>
24302 17:03:29.609774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648 RESULT=skip
24304 17:03:29.672486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip>
24305 17:03:29.672940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648 RESULT=skip
24307 17:03:29.733702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip>
24308 17:03:29.734144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648 RESULT=skip
24310 17:03:29.793701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass>
24311 17:03:29.794127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3664 RESULT=pass
24313 17:03:29.846308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip
24315 17:03:29.846809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664 RESULT=skip>
24316 17:03:29.905151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip
24318 17:03:29.905681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664 RESULT=skip>
24319 17:03:29.963568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip
24321 17:03:29.963983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664 RESULT=skip>
24322 17:03:30.017914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass>
24323 17:03:30.018365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3680 RESULT=pass
24325 17:03:30.078170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip>
24326 17:03:30.078617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680 RESULT=skip
24328 17:03:30.127020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip>
24329 17:03:30.127463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680 RESULT=skip
24331 17:03:30.182292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip>
24332 17:03:30.182732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680 RESULT=skip
24334 17:03:30.242016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass>
24335 17:03:30.242475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3696 RESULT=pass
24337 17:03:30.297666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip
24339 17:03:30.298109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696 RESULT=skip>
24340 17:03:30.360584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip
24342 17:03:30.361285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696 RESULT=skip>
24343 17:03:30.419322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip>
24344 17:03:30.419766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696 RESULT=skip
24346 17:03:30.476818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass>
24347 17:03:30.477265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3712 RESULT=pass
24349 17:03:30.536975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip
24351 17:03:30.537416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712 RESULT=skip>
24352 17:03:30.594239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip
24354 17:03:30.594719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712 RESULT=skip>
24355 17:03:30.653131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip
24357 17:03:30.653624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712 RESULT=skip>
24358 17:03:30.709779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass>
24359 17:03:30.710223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3728 RESULT=pass
24361 17:03:30.769589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip
24363 17:03:30.770091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728 RESULT=skip>
24364 17:03:30.827659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip>
24365 17:03:30.828121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728 RESULT=skip
24367 17:03:30.883864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip>
24368 17:03:30.884320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728 RESULT=skip
24370 17:03:30.942962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass>
24371 17:03:30.943410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3744 RESULT=pass
24373 17:03:30.999877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip
24375 17:03:31.000372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744 RESULT=skip>
24376 17:03:31.058650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip
24378 17:03:31.059116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744 RESULT=skip>
24379 17:03:31.144554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip>
24380 17:03:31.144984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744 RESULT=skip
24382 17:03:31.199082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass>
24383 17:03:31.199515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3760 RESULT=pass
24385 17:03:31.257890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip>
24386 17:03:31.258364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760 RESULT=skip
24388 17:03:31.313734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip>
24389 17:03:31.314180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760 RESULT=skip
24391 17:03:31.370065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip>
24392 17:03:31.370504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760 RESULT=skip
24394 17:03:31.424494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass>
24395 17:03:31.424932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3776 RESULT=pass
24397 17:03:31.482084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip>
24398 17:03:31.482521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776 RESULT=skip
24400 17:03:31.536808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip>
24401 17:03:31.537255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776 RESULT=skip
24403 17:03:31.594026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip>
24404 17:03:31.594481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776 RESULT=skip
24406 17:03:31.651722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass
24408 17:03:31.652491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3792 RESULT=pass>
24409 17:03:31.710359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip>
24410 17:03:31.710804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792 RESULT=skip
24412 17:03:31.768584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip>
24413 17:03:31.769026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792 RESULT=skip
24415 17:03:31.826306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip>
24416 17:03:31.826726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792 RESULT=skip
24418 17:03:31.887435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass>
24419 17:03:31.887875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3808 RESULT=pass
24421 17:03:31.945602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip>
24422 17:03:31.946043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808 RESULT=skip
24424 17:03:32.006494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip>
24425 17:03:32.006947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808 RESULT=skip
24427 17:03:32.070692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip
24429 17:03:32.071165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808 RESULT=skip>
24430 17:03:32.130671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass>
24431 17:03:32.131127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3824 RESULT=pass
24433 17:03:32.190060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip>
24434 17:03:32.190504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824 RESULT=skip
24436 17:03:32.246809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip>
24437 17:03:32.247256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824 RESULT=skip
24439 17:03:32.303694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip
24441 17:03:32.304198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824 RESULT=skip>
24442 17:03:32.362071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass>
24443 17:03:32.362504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3840 RESULT=pass
24445 17:03:32.420069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip
24447 17:03:32.420587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840 RESULT=skip>
24448 17:03:32.478628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip>
24449 17:03:32.479077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840 RESULT=skip
24451 17:03:32.535267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip>
24452 17:03:32.535715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840 RESULT=skip
24454 17:03:32.591533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass>
24455 17:03:32.591979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3856 RESULT=pass
24457 17:03:32.649156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip>
24458 17:03:32.649592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856 RESULT=skip
24460 17:03:32.701367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip>
24461 17:03:32.701782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856 RESULT=skip
24463 17:03:32.763191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip>
24464 17:03:32.763640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856 RESULT=skip
24466 17:03:32.823541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass
24468 17:03:32.824029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3872 RESULT=pass>
24469 17:03:32.882222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip>
24470 17:03:32.882655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872 RESULT=skip
24472 17:03:32.941358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip>
24473 17:03:32.941797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872 RESULT=skip
24475 17:03:33.002819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip>
24476 17:03:33.003246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872 RESULT=skip
24478 17:03:33.061069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass>
24479 17:03:33.061499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3888 RESULT=pass
24481 17:03:33.117836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip>
24482 17:03:33.118307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888 RESULT=skip
24484 17:03:33.181105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip
24486 17:03:33.181557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888 RESULT=skip>
24487 17:03:33.239894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip
24489 17:03:33.240390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888 RESULT=skip>
24490 17:03:33.296846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass>
24491 17:03:33.297283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3904 RESULT=pass
24493 17:03:33.355394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip
24495 17:03:33.355874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904 RESULT=skip>
24496 17:03:33.412609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip>
24497 17:03:33.413043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904 RESULT=skip
24499 17:03:33.471201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip>
24500 17:03:33.471649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904 RESULT=skip
24502 17:03:33.522391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass
24504 17:03:33.522863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3920 RESULT=pass>
24505 17:03:33.583966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip
24507 17:03:33.584605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920 RESULT=skip>
24508 17:03:33.647088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip>
24509 17:03:33.647521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920 RESULT=skip
24511 17:03:33.703383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip>
24512 17:03:33.703828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920 RESULT=skip
24514 17:03:33.758502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass>
24515 17:03:33.758921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3936 RESULT=pass
24517 17:03:33.819047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip>
24518 17:03:33.819505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936 RESULT=skip
24520 17:03:33.878590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip>
24521 17:03:33.879019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936 RESULT=skip
24523 17:03:33.939783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip
24525 17:03:33.940210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936 RESULT=skip>
24526 17:03:34.000734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass>
24527 17:03:34.001159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3952 RESULT=pass
24529 17:03:34.059504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip>
24530 17:03:34.059955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952 RESULT=skip
24532 17:03:34.121242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip
24534 17:03:34.121728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952 RESULT=skip>
24535 17:03:34.181490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip>
24536 17:03:34.182044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952 RESULT=skip
24538 17:03:34.241465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass>
24539 17:03:34.241899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3968 RESULT=pass
24541 17:03:34.294718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip>
24542 17:03:34.295151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968 RESULT=skip
24544 17:03:34.347631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip>
24545 17:03:34.348089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968 RESULT=skip
24547 17:03:34.406044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip
24549 17:03:34.406527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968 RESULT=skip>
24550 17:03:34.465982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass>
24551 17:03:34.466425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_3984 RESULT=pass
24553 17:03:34.520696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip>
24554 17:03:34.521081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984 RESULT=skip
24556 17:03:34.579063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip
24558 17:03:34.579638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984 RESULT=skip>
24559 17:03:34.636698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip>
24560 17:03:34.637150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984 RESULT=skip
24562 17:03:34.691283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass>
24563 17:03:34.691747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4000 RESULT=pass
24565 17:03:34.751402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip>
24566 17:03:34.751844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000 RESULT=skip
24568 17:03:34.810176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip>
24569 17:03:34.810630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000 RESULT=skip
24571 17:03:34.871430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip>
24572 17:03:34.871862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000 RESULT=skip
24574 17:03:34.931489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass>
24575 17:03:34.931916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4016 RESULT=pass
24577 17:03:34.990082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip>
24578 17:03:34.990499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016 RESULT=skip
24580 17:03:35.047114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip>
24581 17:03:35.047569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016 RESULT=skip
24583 17:03:35.105726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip>
24584 17:03:35.106164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016 RESULT=skip
24586 17:03:35.162082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass>
24587 17:03:35.162515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4032 RESULT=pass
24589 17:03:35.214369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip>
24590 17:03:35.214833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032 RESULT=skip
24592 17:03:35.273680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip>
24593 17:03:35.274132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032 RESULT=skip
24595 17:03:35.329227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip>
24596 17:03:35.329705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032 RESULT=skip
24598 17:03:35.384698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass
24600 17:03:35.385156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4048 RESULT=pass>
24601 17:03:35.440614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip>
24602 17:03:35.441053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048 RESULT=skip
24604 17:03:35.502183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip>
24605 17:03:35.502628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048 RESULT=skip
24607 17:03:35.564073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip
24609 17:03:35.564471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048 RESULT=skip>
24610 17:03:35.627489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass>
24611 17:03:35.628004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4064 RESULT=pass
24613 17:03:35.688149 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip
24615 17:03:35.688592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064 RESULT=skip>
24616 17:03:35.743259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip>
24617 17:03:35.743723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064 RESULT=skip
24619 17:03:35.798399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip>
24620 17:03:35.798820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064 RESULT=skip
24622 17:03:35.853574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass
24624 17:03:35.854028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4080 RESULT=pass>
24625 17:03:35.908914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip
24627 17:03:35.909711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080 RESULT=skip>
24628 17:03:35.966113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip>
24629 17:03:35.966557 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080 RESULT=skip
24631 17:03:36.025981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip>
24632 17:03:36.026425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080 RESULT=skip
24634 17:03:36.084859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass>
24635 17:03:36.085317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4096 RESULT=pass
24637 17:03:36.143333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip>
24638 17:03:36.143734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096 RESULT=skip
24640 17:03:36.218513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip>
24641 17:03:36.218927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096 RESULT=skip
24643 17:03:36.285484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip>
24644 17:03:36.285921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096 RESULT=skip
24646 17:03:36.341838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass>
24647 17:03:36.342274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4112 RESULT=pass
24649 17:03:36.394508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip
24651 17:03:36.394999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112 RESULT=skip>
24652 17:03:36.445814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip>
24653 17:03:36.446277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112 RESULT=skip
24655 17:03:36.501422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip
24657 17:03:36.501927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112 RESULT=skip>
24658 17:03:36.556147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass>
24659 17:03:36.556563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4128 RESULT=pass
24661 17:03:36.611609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip
24663 17:03:36.613260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128 RESULT=skip>
24664 17:03:36.668987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip>
24665 17:03:36.669377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128 RESULT=skip
24667 17:03:36.715767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip
24669 17:03:36.716268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128 RESULT=skip>
24670 17:03:36.765963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass>
24671 17:03:36.766363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4144 RESULT=pass
24673 17:03:36.825803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip>
24674 17:03:36.826247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144 RESULT=skip
24676 17:03:36.887389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip>
24677 17:03:36.887830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144 RESULT=skip
24679 17:03:36.947580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip>
24680 17:03:36.948030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144 RESULT=skip
24682 17:03:37.006610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass>
24683 17:03:37.007041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4160 RESULT=pass
24685 17:03:37.069386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip>
24686 17:03:37.069868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160 RESULT=skip
24688 17:03:37.125792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip
24690 17:03:37.126287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160 RESULT=skip>
24691 17:03:37.182154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip>
24692 17:03:37.182591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160 RESULT=skip
24694 17:03:37.232777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass
24696 17:03:37.233259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4176 RESULT=pass>
24697 17:03:37.290034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip>
24698 17:03:37.290468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176 RESULT=skip
24700 17:03:37.354313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip>
24701 17:03:37.354703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176 RESULT=skip
24703 17:03:37.404458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip>
24704 17:03:37.404906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176 RESULT=skip
24706 17:03:37.459153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass>
24707 17:03:37.459596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4192 RESULT=pass
24709 17:03:37.510599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip
24711 17:03:37.511071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192 RESULT=skip>
24712 17:03:37.565626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip>
24713 17:03:37.566098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192 RESULT=skip
24715 17:03:37.618923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip>
24716 17:03:37.619293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192 RESULT=skip
24718 17:03:37.673492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass>
24719 17:03:37.673969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4208 RESULT=pass
24721 17:03:37.727074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip
24723 17:03:37.727512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208 RESULT=skip>
24724 17:03:37.792650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip>
24725 17:03:37.793069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208 RESULT=skip
24727 17:03:37.845996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip>
24728 17:03:37.846453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208 RESULT=skip
24730 17:03:37.898705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass>
24731 17:03:37.899114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4224 RESULT=pass
24733 17:03:37.953851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip>
24734 17:03:37.954298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224 RESULT=skip
24736 17:03:38.013865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip>
24737 17:03:38.014311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224 RESULT=skip
24739 17:03:38.077342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip>
24740 17:03:38.077788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224 RESULT=skip
24742 17:03:38.140806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass
24744 17:03:38.141446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4240 RESULT=pass>
24745 17:03:38.204052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip
24747 17:03:38.204831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240 RESULT=skip>
24748 17:03:38.267907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip
24750 17:03:38.268399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240 RESULT=skip>
24751 17:03:38.331373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip>
24752 17:03:38.331819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240 RESULT=skip
24754 17:03:38.389857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass>
24755 17:03:38.390299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4256 RESULT=pass
24757 17:03:38.444551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip>
24758 17:03:38.444973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256 RESULT=skip
24760 17:03:38.503636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip
24762 17:03:38.504125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256 RESULT=skip>
24763 17:03:38.565296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip>
24764 17:03:38.565687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256 RESULT=skip
24766 17:03:38.623258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass>
24767 17:03:38.623691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4272 RESULT=pass
24769 17:03:38.678052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip>
24770 17:03:38.678487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272 RESULT=skip
24772 17:03:38.730946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip>
24773 17:03:38.731349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272 RESULT=skip
24775 17:03:38.782447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip>
24776 17:03:38.782866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272 RESULT=skip
24778 17:03:38.837918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass
24780 17:03:38.838402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4288 RESULT=pass>
24781 17:03:38.891770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip
24783 17:03:38.892181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288 RESULT=skip>
24784 17:03:38.945271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip>
24785 17:03:38.945688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288 RESULT=skip
24787 17:03:38.994719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip>
24788 17:03:38.995158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288 RESULT=skip
24790 17:03:39.043868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass
24792 17:03:39.044348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4304 RESULT=pass>
24793 17:03:39.091376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip>
24794 17:03:39.091812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304 RESULT=skip
24796 17:03:39.137436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip>
24797 17:03:39.137867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304 RESULT=skip
24799 17:03:39.190353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip
24801 17:03:39.190833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304 RESULT=skip>
24802 17:03:39.250721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass>
24803 17:03:39.251123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4320 RESULT=pass
24805 17:03:39.310122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip
24807 17:03:39.310880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320 RESULT=skip>
24808 17:03:39.368567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip>
24809 17:03:39.369019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320 RESULT=skip
24811 17:03:39.425447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip>
24812 17:03:39.425891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320 RESULT=skip
24814 17:03:39.472692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass>
24815 17:03:39.473120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4336 RESULT=pass
24817 17:03:39.521802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip>
24818 17:03:39.522235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336 RESULT=skip
24820 17:03:39.573843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip>
24821 17:03:39.574253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336 RESULT=skip
24823 17:03:39.630932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip>
24824 17:03:39.631361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336 RESULT=skip
24826 17:03:39.684729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass>
24827 17:03:39.685287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4352 RESULT=pass
24829 17:03:39.733361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip>
24830 17:03:39.733767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352 RESULT=skip
24832 17:03:39.778364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip>
24833 17:03:39.778787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352 RESULT=skip
24835 17:03:39.833941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip>
24836 17:03:39.834374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352 RESULT=skip
24838 17:03:39.880021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass
24840 17:03:39.880519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4368 RESULT=pass>
24841 17:03:39.921578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip>
24842 17:03:39.921999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368 RESULT=skip
24844 17:03:39.966983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip>
24845 17:03:39.967380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368 RESULT=skip
24847 17:03:40.005656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip>
24848 17:03:40.006078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368 RESULT=skip
24850 17:03:40.050636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass
24852 17:03:40.051085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4384 RESULT=pass>
24853 17:03:40.098443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip>
24854 17:03:40.098880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384 RESULT=skip
24856 17:03:40.147056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip>
24857 17:03:40.147456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384 RESULT=skip
24859 17:03:40.195841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip
24861 17:03:40.196244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384 RESULT=skip>
24862 17:03:40.245715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass>
24863 17:03:40.246135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4400 RESULT=pass
24865 17:03:40.294752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip
24867 17:03:40.295203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400 RESULT=skip>
24868 17:03:40.344034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip
24870 17:03:40.344475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400 RESULT=skip>
24871 17:03:40.388535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip>
24872 17:03:40.388932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400 RESULT=skip
24874 17:03:40.436448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass>
24875 17:03:40.436897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4416 RESULT=pass
24877 17:03:40.473617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip>
24878 17:03:40.474050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416 RESULT=skip
24880 17:03:40.511114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip>
24881 17:03:40.511559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416 RESULT=skip
24883 17:03:40.548283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip>
24884 17:03:40.548730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416 RESULT=skip
24886 17:03:40.589129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass
24888 17:03:40.589556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4432 RESULT=pass>
24889 17:03:40.635949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip
24891 17:03:40.636458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432 RESULT=skip>
24892 17:03:40.682263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip>
24893 17:03:40.682726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432 RESULT=skip
24895 17:03:40.730484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip
24897 17:03:40.730951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432 RESULT=skip>
24898 17:03:40.777171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass>
24899 17:03:40.777613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4448 RESULT=pass
24901 17:03:40.818690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip>
24902 17:03:40.819130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448 RESULT=skip
24904 17:03:40.859026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip>
24905 17:03:40.859431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448 RESULT=skip
24907 17:03:40.903207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip>
24908 17:03:40.903670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448 RESULT=skip
24910 17:03:40.949323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass>
24911 17:03:40.949758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4464 RESULT=pass
24913 17:03:40.986629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip
24915 17:03:40.987020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464 RESULT=skip>
24916 17:03:41.040714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip>
24917 17:03:41.041284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464 RESULT=skip
24919 17:03:41.090109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip>
24920 17:03:41.090529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464 RESULT=skip
24922 17:03:41.142621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass
24924 17:03:41.143089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4480 RESULT=pass>
24925 17:03:41.182553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip>
24926 17:03:41.182951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480 RESULT=skip
24928 17:03:41.225521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip
24930 17:03:41.225992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480 RESULT=skip>
24931 17:03:41.266681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip
24933 17:03:41.267180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480 RESULT=skip>
24934 17:03:41.325657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass>
24935 17:03:41.326093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4496 RESULT=pass
24937 17:03:41.398077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip>
24938 17:03:41.398474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496 RESULT=skip
24940 17:03:41.445637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip>
24941 17:03:41.446042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496 RESULT=skip
24943 17:03:41.490430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip
24945 17:03:41.490902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496 RESULT=skip>
24946 17:03:41.530213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass>
24947 17:03:41.530647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4512 RESULT=pass
24949 17:03:41.581209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip
24951 17:03:41.581679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512 RESULT=skip>
24952 17:03:41.624989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip>
24953 17:03:41.625420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512 RESULT=skip
24955 17:03:41.663668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip
24957 17:03:41.664108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512 RESULT=skip>
24958 17:03:41.717840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass>
24959 17:03:41.718344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4528 RESULT=pass
24961 17:03:41.774755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip>
24962 17:03:41.775207 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528 RESULT=skip
24964 17:03:41.814844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip
24966 17:03:41.815462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528 RESULT=skip>
24967 17:03:41.856682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip>
24968 17:03:41.857276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528 RESULT=skip
24970 17:03:41.899427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass>
24971 17:03:41.899835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4544 RESULT=pass
24973 17:03:41.950065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip>
24974 17:03:41.950521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544 RESULT=skip
24976 17:03:42.003851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip
24978 17:03:42.004346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544 RESULT=skip>
24979 17:03:42.053819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip
24981 17:03:42.054269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544 RESULT=skip>
24982 17:03:42.101058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass>
24983 17:03:42.101445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4560 RESULT=pass
24985 17:03:42.151398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip>
24986 17:03:42.151786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560 RESULT=skip
24988 17:03:42.200690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip>
24989 17:03:42.201080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560 RESULT=skip
24991 17:03:42.249969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip>
24992 17:03:42.250398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560 RESULT=skip
24994 17:03:42.300729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass
24996 17:03:42.301202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4576 RESULT=pass>
24997 17:03:42.340748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip>
24998 17:03:42.341240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576 RESULT=skip
25000 17:03:42.380867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip
25002 17:03:42.381335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576 RESULT=skip>
25003 17:03:42.418113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip>
25004 17:03:42.418556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576 RESULT=skip
25006 17:03:42.456698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass>
25007 17:03:42.457206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4592 RESULT=pass
25009 17:03:42.513912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip
25011 17:03:42.514336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592 RESULT=skip>
25012 17:03:42.556164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip
25014 17:03:42.556654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592 RESULT=skip>
25015 17:03:42.597249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip
25017 17:03:42.597712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592 RESULT=skip>
25018 17:03:42.637083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass
25020 17:03:42.637529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4608 RESULT=pass>
25021 17:03:42.674572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip
25023 17:03:42.675034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608 RESULT=skip>
25024 17:03:42.722241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip>
25025 17:03:42.722672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608 RESULT=skip
25027 17:03:42.768983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip
25029 17:03:42.769434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608 RESULT=skip>
25030 17:03:42.810173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass>
25031 17:03:42.810619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4624 RESULT=pass
25033 17:03:42.849041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip>
25034 17:03:42.849454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624 RESULT=skip
25036 17:03:42.887785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip
25038 17:03:42.888324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624 RESULT=skip>
25039 17:03:42.925368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip>
25040 17:03:42.925809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624 RESULT=skip
25042 17:03:42.963987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass
25044 17:03:42.964452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4640 RESULT=pass>
25045 17:03:43.002881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip
25047 17:03:43.003355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640 RESULT=skip>
25048 17:03:43.042284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip
25050 17:03:43.043039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640 RESULT=skip>
25051 17:03:43.082445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip>
25052 17:03:43.082874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640 RESULT=skip
25054 17:03:43.123605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass>
25055 17:03:43.123991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4656 RESULT=pass
25057 17:03:43.181229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip>
25058 17:03:43.181612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656 RESULT=skip
25060 17:03:43.240679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip
25062 17:03:43.241409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656 RESULT=skip>
25063 17:03:43.292786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip
25065 17:03:43.293449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656 RESULT=skip>
25066 17:03:43.334312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass>
25067 17:03:43.334753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4672 RESULT=pass
25069 17:03:43.371458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip>
25070 17:03:43.371905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672 RESULT=skip
25072 17:03:43.409609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip>
25073 17:03:43.410126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672 RESULT=skip
25075 17:03:43.452007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip
25077 17:03:43.452488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672 RESULT=skip>
25078 17:03:43.497953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass>
25079 17:03:43.498391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4688 RESULT=pass
25081 17:03:43.540796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip>
25082 17:03:43.541225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688 RESULT=skip
25084 17:03:43.581455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip
25086 17:03:43.581909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688 RESULT=skip>
25087 17:03:43.625775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip>
25088 17:03:43.626197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688 RESULT=skip
25090 17:03:43.669326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass>
25091 17:03:43.669738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4704 RESULT=pass
25093 17:03:43.718478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip
25095 17:03:43.718895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704 RESULT=skip>
25096 17:03:43.756057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip
25098 17:03:43.756516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704 RESULT=skip>
25099 17:03:43.793398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip
25101 17:03:43.793881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704 RESULT=skip>
25102 17:03:43.830905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass
25104 17:03:43.831370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4720 RESULT=pass>
25105 17:03:43.868725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip>
25106 17:03:43.869154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720 RESULT=skip
25108 17:03:43.909074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip
25110 17:03:43.909703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720 RESULT=skip>
25111 17:03:43.955223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip>
25112 17:03:43.955660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720 RESULT=skip
25114 17:03:44.002649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass
25116 17:03:44.003116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4736 RESULT=pass>
25117 17:03:44.047542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip
25119 17:03:44.048047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736 RESULT=skip>
25120 17:03:44.087861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip
25122 17:03:44.088556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736 RESULT=skip>
25123 17:03:44.125869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip>
25124 17:03:44.126359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736 RESULT=skip
25126 17:03:44.162906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass>
25127 17:03:44.163376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4752 RESULT=pass
25129 17:03:44.200271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip>
25130 17:03:44.200721 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752 RESULT=skip
25132 17:03:44.237561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip>
25133 17:03:44.238009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752 RESULT=skip
25135 17:03:44.274224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip>
25136 17:03:44.274679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752 RESULT=skip
25138 17:03:44.313626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass>
25139 17:03:44.314079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4768 RESULT=pass
25141 17:03:44.353868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip>
25142 17:03:44.354293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768 RESULT=skip
25144 17:03:44.395276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip>
25145 17:03:44.395731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768 RESULT=skip
25147 17:03:44.434418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip>
25148 17:03:44.434842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768 RESULT=skip
25150 17:03:44.477455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass>
25151 17:03:44.477907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4784 RESULT=pass
25153 17:03:44.517418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip>
25154 17:03:44.518004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784 RESULT=skip
25156 17:03:44.555697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip
25158 17:03:44.556392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784 RESULT=skip>
25159 17:03:44.595397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip
25161 17:03:44.595980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784 RESULT=skip>
25162 17:03:44.638530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass>
25163 17:03:44.639101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4800 RESULT=pass
25165 17:03:44.695264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip>
25166 17:03:44.695695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800 RESULT=skip
25168 17:03:44.736748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip>
25169 17:03:44.737176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800 RESULT=skip
25171 17:03:44.774397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip>
25172 17:03:44.774894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800 RESULT=skip
25174 17:03:44.813736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass>
25175 17:03:44.814288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4816 RESULT=pass
25177 17:03:44.852531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip>
25178 17:03:44.852940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816 RESULT=skip
25180 17:03:44.902343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip
25182 17:03:44.902995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816 RESULT=skip>
25183 17:03:44.951562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip>
25184 17:03:44.951960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816 RESULT=skip
25186 17:03:45.004948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass
25188 17:03:45.005422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4832 RESULT=pass>
25189 17:03:45.058538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip>
25190 17:03:45.058961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832 RESULT=skip
25192 17:03:45.100904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip>
25193 17:03:45.101339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832 RESULT=skip
25195 17:03:45.146408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip>
25196 17:03:45.146835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832 RESULT=skip
25198 17:03:45.192449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass
25200 17:03:45.192914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4848 RESULT=pass>
25201 17:03:45.233530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip>
25202 17:03:45.233959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848 RESULT=skip
25204 17:03:45.277496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip>
25205 17:03:45.277906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848 RESULT=skip
25207 17:03:45.325332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip>
25208 17:03:45.325786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848 RESULT=skip
25210 17:03:45.361926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass>
25211 17:03:45.362465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4864 RESULT=pass
25213 17:03:45.403322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip
25215 17:03:45.403756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864 RESULT=skip>
25216 17:03:45.454880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip
25218 17:03:45.455298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864 RESULT=skip>
25219 17:03:45.499479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip
25221 17:03:45.499969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864 RESULT=skip>
25222 17:03:45.538554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass>
25223 17:03:45.538961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4880 RESULT=pass
25225 17:03:45.578873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip>
25226 17:03:45.579306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880 RESULT=skip
25228 17:03:45.633034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip
25230 17:03:45.633819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880 RESULT=skip>
25231 17:03:45.679221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip
25233 17:03:45.679685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880 RESULT=skip>
25234 17:03:45.725705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass
25236 17:03:45.726174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4896 RESULT=pass>
25237 17:03:45.765723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip>
25238 17:03:45.766317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896 RESULT=skip
25240 17:03:45.805204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip
25242 17:03:45.805687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896 RESULT=skip>
25243 17:03:45.843392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip>
25244 17:03:45.843958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896 RESULT=skip
25246 17:03:45.890692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass>
25247 17:03:45.891151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4912 RESULT=pass
25249 17:03:45.943152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip
25251 17:03:45.943863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912 RESULT=skip>
25252 17:03:45.989112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip
25254 17:03:45.989568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912 RESULT=skip>
25255 17:03:46.038034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip>
25256 17:03:46.038446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912 RESULT=skip
25258 17:03:46.081371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass
25260 17:03:46.081825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4928 RESULT=pass>
25261 17:03:46.125709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip
25263 17:03:46.126357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928 RESULT=skip>
25264 17:03:46.170486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip>
25265 17:03:46.170914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928 RESULT=skip
25267 17:03:46.210873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip>
25268 17:03:46.211250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928 RESULT=skip
25270 17:03:46.250311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass>
25271 17:03:46.250690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4944 RESULT=pass
25273 17:03:46.289362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip>
25274 17:03:46.289831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944 RESULT=skip
25276 17:03:46.342130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip
25278 17:03:46.342852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944 RESULT=skip>
25279 17:03:46.381491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip
25281 17:03:46.382072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944 RESULT=skip>
25282 17:03:46.422138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass>
25283 17:03:46.422701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4960 RESULT=pass
25285 17:03:46.486954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip
25287 17:03:46.487737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960 RESULT=skip>
25288 17:03:46.538212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip>
25289 17:03:46.538669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960 RESULT=skip
25291 17:03:46.591864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip
25293 17:03:46.592597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960 RESULT=skip>
25294 17:03:46.641572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass>
25295 17:03:46.641988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4976 RESULT=pass
25297 17:03:46.685244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip>
25298 17:03:46.685767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976 RESULT=skip
25300 17:03:46.725717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip
25302 17:03:46.726309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976 RESULT=skip>
25303 17:03:46.777999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip
25305 17:03:46.778598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976 RESULT=skip>
25306 17:03:46.829668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass>
25307 17:03:46.830107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_4992 RESULT=pass
25309 17:03:46.878193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip
25311 17:03:46.878903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992 RESULT=skip>
25312 17:03:46.917382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip>
25313 17:03:46.917854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992 RESULT=skip
25315 17:03:46.961791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip
25317 17:03:46.962205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992 RESULT=skip>
25318 17:03:46.999481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass>
25319 17:03:46.999958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5008 RESULT=pass
25321 17:03:47.037681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip
25323 17:03:47.038123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008 RESULT=skip>
25324 17:03:47.075350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip>
25325 17:03:47.075724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008 RESULT=skip
25327 17:03:47.127392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip>
25328 17:03:47.127822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008 RESULT=skip
25330 17:03:47.182672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass>
25331 17:03:47.183064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5024 RESULT=pass
25333 17:03:47.233902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip>
25334 17:03:47.234303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024 RESULT=skip
25336 17:03:47.289501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip
25338 17:03:47.290078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024 RESULT=skip>
25339 17:03:47.340371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip>
25340 17:03:47.340766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024 RESULT=skip
25342 17:03:47.400601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass>
25343 17:03:47.401078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5040 RESULT=pass
25345 17:03:47.462179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip>
25346 17:03:47.462696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040 RESULT=skip
25348 17:03:47.525405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip
25350 17:03:47.526121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040 RESULT=skip>
25351 17:03:47.586590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip>
25352 17:03:47.587019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040 RESULT=skip
25354 17:03:47.636782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass>
25355 17:03:47.637241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5056 RESULT=pass
25357 17:03:47.692639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip>
25358 17:03:47.693069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056 RESULT=skip
25360 17:03:47.739446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip
25362 17:03:47.740097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056 RESULT=skip>
25363 17:03:47.780456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip
25365 17:03:47.780921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056 RESULT=skip>
25366 17:03:47.832886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass
25368 17:03:47.833366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5072 RESULT=pass>
25369 17:03:47.878398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip
25371 17:03:47.878826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072 RESULT=skip>
25372 17:03:47.917718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip
25374 17:03:47.918173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072 RESULT=skip>
25375 17:03:47.967260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip>
25376 17:03:47.967655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072 RESULT=skip
25378 17:03:48.019432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass>
25379 17:03:48.019886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5088 RESULT=pass
25381 17:03:48.072845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip>
25382 17:03:48.073237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088 RESULT=skip
25384 17:03:48.125177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip>
25385 17:03:48.125567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088 RESULT=skip
25387 17:03:48.176758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip>
25388 17:03:48.177158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088 RESULT=skip
25390 17:03:48.217656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass>
25391 17:03:48.218055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5104 RESULT=pass
25393 17:03:48.262551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip>
25394 17:03:48.262973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104 RESULT=skip
25396 17:03:48.312356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip>
25397 17:03:48.312785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104 RESULT=skip
25399 17:03:48.360759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip>
25400 17:03:48.361211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104 RESULT=skip
25402 17:03:48.405116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass>
25403 17:03:48.405539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5120 RESULT=pass
25405 17:03:48.449812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip>
25406 17:03:48.450312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120 RESULT=skip
25408 17:03:48.501014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip
25410 17:03:48.501477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120 RESULT=skip>
25411 17:03:48.545788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip>
25412 17:03:48.546218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120 RESULT=skip
25414 17:03:48.582917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass
25416 17:03:48.583374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5136 RESULT=pass>
25417 17:03:48.625736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip>
25418 17:03:48.626133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136 RESULT=skip
25420 17:03:48.677256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip>
25421 17:03:48.677681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136 RESULT=skip
25423 17:03:48.737199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip>
25424 17:03:48.737629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136 RESULT=skip
25426 17:03:48.780933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass>
25427 17:03:48.781347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5152 RESULT=pass
25429 17:03:48.822325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip
25431 17:03:48.822795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152 RESULT=skip>
25432 17:03:48.862803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip>
25433 17:03:48.863230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152 RESULT=skip
25435 17:03:48.906825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip
25437 17:03:48.907304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152 RESULT=skip>
25438 17:03:48.959546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass>
25439 17:03:48.959983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5168 RESULT=pass
25441 17:03:49.012486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip>
25442 17:03:49.012900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168 RESULT=skip
25444 17:03:49.050700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip>
25445 17:03:49.051123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168 RESULT=skip
25447 17:03:49.091773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip
25449 17:03:49.092244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168 RESULT=skip>
25450 17:03:49.150032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass
25452 17:03:49.150501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5184 RESULT=pass>
25453 17:03:49.210164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip
25455 17:03:49.210945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184 RESULT=skip>
25456 17:03:49.271243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip
25458 17:03:49.271820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184 RESULT=skip>
25459 17:03:49.327662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip>
25460 17:03:49.328131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184 RESULT=skip
25462 17:03:49.369137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass>
25463 17:03:49.369563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5200 RESULT=pass
25465 17:03:49.408916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip>
25466 17:03:49.409311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200 RESULT=skip
25468 17:03:49.456510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip>
25469 17:03:49.456962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200 RESULT=skip
25471 17:03:49.495659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip
25473 17:03:49.496351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200 RESULT=skip>
25474 17:03:49.543269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass
25476 17:03:49.543697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5216 RESULT=pass>
25477 17:03:49.582393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip>
25478 17:03:49.582806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216 RESULT=skip
25480 17:03:49.619783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip
25482 17:03:49.620442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216 RESULT=skip>
25483 17:03:49.662895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip>
25484 17:03:49.663332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216 RESULT=skip
25486 17:03:49.705405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass>
25487 17:03:49.705866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5232 RESULT=pass
25489 17:03:49.747325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip>
25490 17:03:49.747815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232 RESULT=skip
25492 17:03:49.786929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip
25494 17:03:49.787409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232 RESULT=skip>
25495 17:03:49.824760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip>
25496 17:03:49.825146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232 RESULT=skip
25498 17:03:49.863783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass
25500 17:03:49.864279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5248 RESULT=pass>
25501 17:03:49.913505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip>
25502 17:03:49.913924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248 RESULT=skip
25504 17:03:49.950978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip
25506 17:03:49.951456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248 RESULT=skip>
25507 17:03:49.987007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip
25509 17:03:49.987410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248 RESULT=skip>
25510 17:03:50.028306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass>
25511 17:03:50.028742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5264 RESULT=pass
25513 17:03:50.079055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip>
25514 17:03:50.079517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264 RESULT=skip
25516 17:03:50.124543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip
25518 17:03:50.125021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264 RESULT=skip>
25519 17:03:50.162300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip>
25520 17:03:50.162720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264 RESULT=skip
25522 17:03:50.198261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass
25524 17:03:50.198631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5280 RESULT=pass>
25525 17:03:50.250594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip>
25526 17:03:50.251031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280 RESULT=skip
25528 17:03:50.299842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip
25530 17:03:50.300401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280 RESULT=skip>
25531 17:03:50.338140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip>
25532 17:03:50.338554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280 RESULT=skip
25534 17:03:50.379079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass>
25535 17:03:50.379561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5296 RESULT=pass
25537 17:03:50.429739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip>
25538 17:03:50.430227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296 RESULT=skip
25540 17:03:50.473261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip>
25541 17:03:50.473815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296 RESULT=skip
25543 17:03:50.519053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip>
25544 17:03:50.519454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296 RESULT=skip
25546 17:03:50.556814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass>
25547 17:03:50.557260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5312 RESULT=pass
25549 17:03:50.600846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip>
25550 17:03:50.601362 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312 RESULT=skip
25552 17:03:50.647529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip>
25553 17:03:50.647947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312 RESULT=skip
25555 17:03:50.684198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip>
25556 17:03:50.684638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312 RESULT=skip
25558 17:03:50.722682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass>
25559 17:03:50.723164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5328 RESULT=pass
25561 17:03:50.761804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip>
25562 17:03:50.762335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328 RESULT=skip
25564 17:03:50.801952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip>
25565 17:03:50.802368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328 RESULT=skip
25567 17:03:50.856721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip>
25568 17:03:50.857101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328 RESULT=skip
25570 17:03:50.905710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass
25572 17:03:50.906184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5344 RESULT=pass>
25573 17:03:50.963107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip>
25574 17:03:50.963486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344 RESULT=skip
25576 17:03:51.014049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip>
25577 17:03:51.014558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344 RESULT=skip
25579 17:03:51.070858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip>
25580 17:03:51.071266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344 RESULT=skip
25582 17:03:51.128538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass
25584 17:03:51.128975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5360 RESULT=pass>
25585 17:03:51.166525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip>
25586 17:03:51.166959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360 RESULT=skip
25588 17:03:51.211217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip>
25589 17:03:51.211594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360 RESULT=skip
25591 17:03:51.257220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip>
25592 17:03:51.257634 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360 RESULT=skip
25594 17:03:51.301302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass>
25595 17:03:51.301763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5376 RESULT=pass
25597 17:03:51.341788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip>
25598 17:03:51.342220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376 RESULT=skip
25600 17:03:51.381670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip
25602 17:03:51.382126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376 RESULT=skip>
25603 17:03:51.434806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip>
25604 17:03:51.435270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376 RESULT=skip
25606 17:03:51.480906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass>
25607 17:03:51.481391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5392 RESULT=pass
25609 17:03:51.525876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip>
25610 17:03:51.526308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392 RESULT=skip
25612 17:03:51.586409 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip
25614 17:03:51.586869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392 RESULT=skip>
25615 17:03:51.637663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip>
25616 17:03:51.638082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392 RESULT=skip
25618 17:03:51.682709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass
25620 17:03:51.683188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5408 RESULT=pass>
25621 17:03:51.722998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip>
25622 17:03:51.723456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408 RESULT=skip
25624 17:03:51.769550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip>
25625 17:03:51.770005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408 RESULT=skip
25627 17:03:51.809930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip>
25628 17:03:51.810356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408 RESULT=skip
25630 17:03:51.854649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass>
25631 17:03:51.855060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5424 RESULT=pass
25633 17:03:51.901245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip>
25634 17:03:51.901686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424 RESULT=skip
25636 17:03:51.942209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip>
25637 17:03:51.942624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424 RESULT=skip
25639 17:03:51.990561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip>
25640 17:03:51.990970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424 RESULT=skip
25642 17:03:52.034153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass>
25643 17:03:52.034729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5440 RESULT=pass
25645 17:03:52.084954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip
25647 17:03:52.085481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440 RESULT=skip>
25648 17:03:52.143889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip
25650 17:03:52.144354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440 RESULT=skip>
25651 17:03:52.195219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip>
25652 17:03:52.195668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440 RESULT=skip
25654 17:03:52.250884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass
25656 17:03:52.251414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5456 RESULT=pass>
25657 17:03:52.298868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip>
25658 17:03:52.299408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456 RESULT=skip
25660 17:03:52.347218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip>
25661 17:03:52.347652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456 RESULT=skip
25663 17:03:52.394186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip>
25664 17:03:52.394671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456 RESULT=skip
25666 17:03:52.439252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass>
25667 17:03:52.439659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5472 RESULT=pass
25669 17:03:52.481551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip
25671 17:03:52.482321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472 RESULT=skip>
25672 17:03:52.527932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip
25674 17:03:52.528350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472 RESULT=skip>
25675 17:03:52.577537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip
25677 17:03:52.577973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472 RESULT=skip>
25678 17:03:52.626485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass>
25679 17:03:52.626935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5488 RESULT=pass
25681 17:03:52.670520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip>
25682 17:03:52.671001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488 RESULT=skip
25684 17:03:52.711565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip>
25685 17:03:52.712084 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488 RESULT=skip
25687 17:03:52.753501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip>
25688 17:03:52.753917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488 RESULT=skip
25690 17:03:52.793933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass
25692 17:03:52.794403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5504 RESULT=pass>
25693 17:03:52.853058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip
25695 17:03:52.853538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504 RESULT=skip>
25696 17:03:52.913528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip>
25697 17:03:52.913976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504 RESULT=skip
25699 17:03:52.966618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip>
25700 17:03:52.967070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504 RESULT=skip
25702 17:03:53.004433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass>
25703 17:03:53.004891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5520 RESULT=pass
25705 17:03:53.057654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip>
25706 17:03:53.058052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520 RESULT=skip
25708 17:03:53.112313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip>
25709 17:03:53.112755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520 RESULT=skip
25711 17:03:53.152168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip>
25712 17:03:53.152627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520 RESULT=skip
25714 17:03:53.189758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass>
25715 17:03:53.190177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5536 RESULT=pass
25717 17:03:53.233869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip>
25718 17:03:53.234257 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536 RESULT=skip
25720 17:03:53.275252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip
25722 17:03:53.275740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536 RESULT=skip>
25723 17:03:53.326016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip>
25724 17:03:53.326437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536 RESULT=skip
25726 17:03:53.372838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass
25728 17:03:53.373300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5552 RESULT=pass>
25729 17:03:53.417150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip
25731 17:03:53.417614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552 RESULT=skip>
25732 17:03:53.469440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip
25734 17:03:53.469916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552 RESULT=skip>
25735 17:03:53.515803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip
25737 17:03:53.516257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552 RESULT=skip>
25738 17:03:53.561715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass>
25739 17:03:53.562131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5568 RESULT=pass
25741 17:03:53.602523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip
25743 17:03:53.602963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568 RESULT=skip>
25744 17:03:53.653940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip>
25745 17:03:53.654303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568 RESULT=skip
25747 17:03:53.707786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip
25749 17:03:53.708445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568 RESULT=skip>
25750 17:03:53.754140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass>
25751 17:03:53.754568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5584 RESULT=pass
25753 17:03:53.807293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip
25755 17:03:53.807714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584 RESULT=skip>
25756 17:03:53.849580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip>
25757 17:03:53.849993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584 RESULT=skip
25759 17:03:53.906933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip>
25760 17:03:53.907356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584 RESULT=skip
25762 17:03:53.957709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass>
25763 17:03:53.958272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5600 RESULT=pass
25765 17:03:53.994362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip>
25766 17:03:53.994751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600 RESULT=skip
25768 17:03:54.030800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip>
25769 17:03:54.031252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600 RESULT=skip
25771 17:03:54.070579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip
25773 17:03:54.071159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600 RESULT=skip>
25774 17:03:54.107251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass
25776 17:03:54.107730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5616 RESULT=pass>
25777 17:03:54.146256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip>
25778 17:03:54.146670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616 RESULT=skip
25780 17:03:54.189829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip>
25781 17:03:54.190329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616 RESULT=skip
25783 17:03:54.241225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip>
25784 17:03:54.241793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616 RESULT=skip
25786 17:03:54.280963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass>
25787 17:03:54.281405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5632 RESULT=pass
25789 17:03:54.329266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip>
25790 17:03:54.329691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632 RESULT=skip
25792 17:03:54.371400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip>
25793 17:03:54.371894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632 RESULT=skip
25795 17:03:54.415092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip
25797 17:03:54.415558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632 RESULT=skip>
25798 17:03:54.452736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass
25800 17:03:54.453503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5648 RESULT=pass>
25801 17:03:54.500379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip>
25802 17:03:54.500810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648 RESULT=skip
25804 17:03:54.547474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip>
25805 17:03:54.547879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648 RESULT=skip
25807 17:03:54.597024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip>
25808 17:03:54.597453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648 RESULT=skip
25810 17:03:54.642652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass>
25811 17:03:54.643101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5664 RESULT=pass
25813 17:03:54.702165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip>
25814 17:03:54.702585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664 RESULT=skip
25816 17:03:54.750018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip>
25817 17:03:54.750434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664 RESULT=skip
25819 17:03:54.793169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip>
25820 17:03:54.793630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664 RESULT=skip
25822 17:03:54.834708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass
25824 17:03:54.835141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5680 RESULT=pass>
25825 17:03:54.878171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip>
25826 17:03:54.878582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680 RESULT=skip
25828 17:03:54.927178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip>
25829 17:03:54.927620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680 RESULT=skip
25831 17:03:54.964510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip
25833 17:03:54.964990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680 RESULT=skip>
25834 17:03:55.001779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass
25836 17:03:55.002250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5696 RESULT=pass>
25837 17:03:55.039460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip>
25838 17:03:55.039894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696 RESULT=skip
25840 17:03:55.078068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip>
25841 17:03:55.078493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696 RESULT=skip
25843 17:03:55.115247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip>
25844 17:03:55.115683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696 RESULT=skip
25846 17:03:55.152572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass
25848 17:03:55.153037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5712 RESULT=pass>
25849 17:03:55.189986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip>
25850 17:03:55.190542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712 RESULT=skip
25852 17:03:55.229235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip>
25853 17:03:55.229676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712 RESULT=skip
25855 17:03:55.270483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip>
25856 17:03:55.270870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712 RESULT=skip
25858 17:03:55.321373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass
25860 17:03:55.321795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5728 RESULT=pass>
25861 17:03:55.366945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip>
25862 17:03:55.367333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728 RESULT=skip
25864 17:03:55.411706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip
25866 17:03:55.412467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728 RESULT=skip>
25867 17:03:55.456109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip
25869 17:03:55.456879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728 RESULT=skip>
25870 17:03:55.502738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass>
25871 17:03:55.503165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5744 RESULT=pass
25873 17:03:55.540931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip
25875 17:03:55.541422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744 RESULT=skip>
25876 17:03:55.587895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip
25878 17:03:55.588367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744 RESULT=skip>
25879 17:03:55.632589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip>
25880 17:03:55.633025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744 RESULT=skip
25882 17:03:55.674231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass>
25883 17:03:55.674737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5760 RESULT=pass
25885 17:03:55.717508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip>
25886 17:03:55.717906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760 RESULT=skip
25888 17:03:55.761046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip>
25889 17:03:55.761472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760 RESULT=skip
25891 17:03:55.811885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip
25893 17:03:55.812629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760 RESULT=skip>
25894 17:03:55.861940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass>
25895 17:03:55.862372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5776 RESULT=pass
25897 17:03:55.910304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip>
25898 17:03:55.910743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776 RESULT=skip
25900 17:03:55.960538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip>
25901 17:03:55.961041 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776 RESULT=skip
25903 17:03:55.996833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip>
25904 17:03:55.997282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776 RESULT=skip
25906 17:03:56.033791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass>
25907 17:03:56.034189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5792 RESULT=pass
25909 17:03:56.075972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip
25911 17:03:56.076442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792 RESULT=skip>
25912 17:03:56.117978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip>
25913 17:03:56.118421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792 RESULT=skip
25915 17:03:56.153982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip
25917 17:03:56.154443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792 RESULT=skip>
25918 17:03:56.194318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass
25920 17:03:56.194754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5808 RESULT=pass>
25921 17:03:56.243833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip
25923 17:03:56.244381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808 RESULT=skip>
25924 17:03:56.293193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip>
25925 17:03:56.293628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808 RESULT=skip
25927 17:03:56.331460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip>
25928 17:03:56.331894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808 RESULT=skip
25930 17:03:56.377265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass>
25931 17:03:56.377662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5824 RESULT=pass
25933 17:03:56.423436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip
25935 17:03:56.423867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824 RESULT=skip>
25936 17:03:56.467382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip
25938 17:03:56.467812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824 RESULT=skip>
25939 17:03:56.511875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip
25941 17:03:56.512347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824 RESULT=skip>
25942 17:03:56.558955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass>
25943 17:03:56.559399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5840 RESULT=pass
25945 17:03:56.606824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip>
25946 17:03:56.607263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840 RESULT=skip
25948 17:03:56.653886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip>
25949 17:03:56.654310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840 RESULT=skip
25951 17:03:56.709883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip
25953 17:03:56.710356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840 RESULT=skip>
25954 17:03:56.760764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass
25956 17:03:56.761146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5856 RESULT=pass>
25957 17:03:56.811347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip>
25958 17:03:56.811746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856 RESULT=skip
25960 17:03:56.857617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip
25962 17:03:56.858054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856 RESULT=skip>
25963 17:03:56.903201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip>
25964 17:03:56.903583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856 RESULT=skip
25966 17:03:56.948977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass>
25967 17:03:56.949416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5872 RESULT=pass
25969 17:03:56.996694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip
25971 17:03:56.997163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872 RESULT=skip>
25972 17:03:57.038416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip>
25973 17:03:57.038864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872 RESULT=skip
25975 17:03:57.074838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip>
25976 17:03:57.075267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872 RESULT=skip
25978 17:03:57.113405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass>
25979 17:03:57.113870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5888 RESULT=pass
25981 17:03:57.157417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip
25983 17:03:57.157865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888 RESULT=skip>
25984 17:03:57.196865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip
25986 17:03:57.197342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888 RESULT=skip>
25987 17:03:57.238735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip>
25988 17:03:57.239181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888 RESULT=skip
25990 17:03:57.282938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass>
25991 17:03:57.283381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5904 RESULT=pass
25993 17:03:57.324431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip
25995 17:03:57.324898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904 RESULT=skip>
25996 17:03:57.366867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip
25998 17:03:57.367301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904 RESULT=skip>
25999 17:03:57.413261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip>
26000 17:03:57.413686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904 RESULT=skip
26002 17:03:57.458494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass>
26003 17:03:57.458928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5920 RESULT=pass
26005 17:03:57.503472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip
26007 17:03:57.504186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920 RESULT=skip>
26008 17:03:57.548814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip>
26009 17:03:57.549346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920 RESULT=skip
26011 17:03:57.591314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip>
26012 17:03:57.591749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920 RESULT=skip
26014 17:03:57.630361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass
26016 17:03:57.630840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5936 RESULT=pass>
26017 17:03:57.670016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip
26019 17:03:57.670437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936 RESULT=skip>
26020 17:03:57.715090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip>
26021 17:03:57.715671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936 RESULT=skip
26023 17:03:57.762542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip>
26024 17:03:57.762969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936 RESULT=skip
26026 17:03:57.806659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass>
26027 17:03:57.807112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5952 RESULT=pass
26029 17:03:57.849183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip
26031 17:03:57.849958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952 RESULT=skip>
26032 17:03:57.889337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip>
26033 17:03:57.889765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952 RESULT=skip
26035 17:03:57.946700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip>
26036 17:03:57.947112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952 RESULT=skip
26038 17:03:58.002133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass>
26039 17:03:58.002570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5968 RESULT=pass
26041 17:03:58.056611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip
26043 17:03:58.057095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968 RESULT=skip>
26044 17:03:58.106210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip>
26045 17:03:58.106676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968 RESULT=skip
26047 17:03:58.152883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip>
26048 17:03:58.153320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968 RESULT=skip
26050 17:03:58.192684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass>
26051 17:03:58.193126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_5984 RESULT=pass
26053 17:03:58.237504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip>
26054 17:03:58.237945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984 RESULT=skip
26056 17:03:58.281236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip>
26057 17:03:58.281663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984 RESULT=skip
26059 17:03:58.319666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip>
26060 17:03:58.320058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984 RESULT=skip
26062 17:03:58.361972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass>
26063 17:03:58.362394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6000 RESULT=pass
26065 17:03:58.412934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip>
26066 17:03:58.413317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000 RESULT=skip
26068 17:03:58.461178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip
26070 17:03:58.461642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000 RESULT=skip>
26071 17:03:58.508046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip
26073 17:03:58.511496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000 RESULT=skip>
26074 17:03:58.559130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass>
26075 17:03:58.559585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6016 RESULT=pass
26077 17:03:58.605137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip>
26078 17:03:58.605573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016 RESULT=skip
26080 17:03:58.662326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip>
26081 17:03:58.662771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016 RESULT=skip
26083 17:03:58.722347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip>
26084 17:03:58.722770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016 RESULT=skip
26086 17:03:58.778284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass>
26087 17:03:58.778672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6032 RESULT=pass
26089 17:03:58.834888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip>
26090 17:03:58.835303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032 RESULT=skip
26092 17:03:58.894114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip>
26093 17:03:58.894583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032 RESULT=skip
26095 17:03:58.953822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip
26097 17:03:58.954304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032 RESULT=skip>
26098 17:03:59.011169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass>
26099 17:03:59.011627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6048 RESULT=pass
26101 17:03:59.057393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip>
26102 17:03:59.057855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048 RESULT=skip
26104 17:03:59.106360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip>
26105 17:03:59.106793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048 RESULT=skip
26107 17:03:59.162166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip>
26108 17:03:59.162601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048 RESULT=skip
26110 17:03:59.219313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass>
26111 17:03:59.219774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6064 RESULT=pass
26113 17:03:59.267450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip>
26114 17:03:59.267880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064 RESULT=skip
26116 17:03:59.318168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip
26118 17:03:59.318929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064 RESULT=skip>
26119 17:03:59.369057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip>
26120 17:03:59.369442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064 RESULT=skip
26122 17:03:59.419677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass
26124 17:03:59.420118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6080 RESULT=pass>
26125 17:03:59.462398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip
26127 17:03:59.462861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080 RESULT=skip>
26128 17:03:59.498181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip>
26129 17:03:59.498627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080 RESULT=skip
26131 17:03:59.533715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip
26133 17:03:59.534187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080 RESULT=skip>
26134 17:03:59.572724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass>
26135 17:03:59.573104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6096 RESULT=pass
26137 17:03:59.608579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip>
26138 17:03:59.609135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096 RESULT=skip
26140 17:03:59.643916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip
26142 17:03:59.644380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096 RESULT=skip>
26143 17:03:59.678828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip>
26144 17:03:59.679255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096 RESULT=skip
26146 17:03:59.714355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass
26148 17:03:59.714771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6112 RESULT=pass>
26149 17:03:59.749463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip>
26150 17:03:59.749789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112 RESULT=skip
26152 17:03:59.796091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip
26154 17:03:59.796500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112 RESULT=skip>
26155 17:03:59.837868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip>
26156 17:03:59.838325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112 RESULT=skip
26158 17:03:59.878803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass>
26159 17:03:59.879281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6128 RESULT=pass
26161 17:03:59.919141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip
26163 17:03:59.919735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128 RESULT=skip>
26164 17:03:59.958004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip>
26165 17:03:59.958447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128 RESULT=skip
26167 17:03:59.994157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip
26169 17:03:59.994919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128 RESULT=skip>
26170 17:04:00.028847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass>
26171 17:04:00.029325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6144 RESULT=pass
26173 17:04:00.078044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip>
26174 17:04:00.078480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144 RESULT=skip
26176 17:04:00.114521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip>
26177 17:04:00.114936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144 RESULT=skip
26179 17:04:00.150730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip>
26180 17:04:00.151296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144 RESULT=skip
26182 17:04:00.187067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass
26184 17:04:00.187692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6160 RESULT=pass>
26185 17:04:00.222862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip>
26186 17:04:00.223361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160 RESULT=skip
26188 17:04:00.259193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip
26190 17:04:00.259571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160 RESULT=skip>
26191 17:04:00.296359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip>
26192 17:04:00.296925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160 RESULT=skip
26194 17:04:00.332065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass>
26195 17:04:00.332642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6176 RESULT=pass
26197 17:04:00.368080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip
26199 17:04:00.368739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176 RESULT=skip>
26200 17:04:00.405980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip>
26201 17:04:00.406355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176 RESULT=skip
26203 17:04:00.447461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip>
26204 17:04:00.447887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176 RESULT=skip
26206 17:04:00.491200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass
26208 17:04:00.491675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6192 RESULT=pass>
26209 17:04:00.532664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip>
26210 17:04:00.533100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192 RESULT=skip
26212 17:04:00.583836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip
26214 17:04:00.584304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192 RESULT=skip>
26215 17:04:00.628438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip
26217 17:04:00.628895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192 RESULT=skip>
26218 17:04:00.681499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass>
26219 17:04:00.681897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6208 RESULT=pass
26221 17:04:00.742068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip>
26222 17:04:00.742484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208 RESULT=skip
26224 17:04:00.778732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip>
26225 17:04:00.779186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208 RESULT=skip
26227 17:04:00.820785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip>
26228 17:04:00.821224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208 RESULT=skip
26230 17:04:00.861991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass
26232 17:04:00.862452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6224 RESULT=pass>
26233 17:04:00.907246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip>
26234 17:04:00.907690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224 RESULT=skip
26236 17:04:00.954265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip>
26237 17:04:00.954700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224 RESULT=skip
26239 17:04:00.989185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip>
26240 17:04:00.989610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224 RESULT=skip
26242 17:04:01.025429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass
26244 17:04:01.025900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6240 RESULT=pass>
26245 17:04:01.065902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip
26247 17:04:01.066340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240 RESULT=skip>
26248 17:04:01.101261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip>
26249 17:04:01.101707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240 RESULT=skip
26251 17:04:01.137506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip>
26252 17:04:01.138004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240 RESULT=skip
26254 17:04:01.185822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass>
26255 17:04:01.186244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6256 RESULT=pass
26257 17:04:01.233062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip>
26258 17:04:01.233480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256 RESULT=skip
26260 17:04:01.281926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip>
26261 17:04:01.282377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256 RESULT=skip
26263 17:04:01.330052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip>
26264 17:04:01.330598 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256 RESULT=skip
26266 17:04:01.373932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass
26268 17:04:01.374715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6272 RESULT=pass>
26269 17:04:01.420816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip>
26270 17:04:01.421368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272 RESULT=skip
26272 17:04:01.461693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip
26274 17:04:01.462454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272 RESULT=skip>
26275 17:04:01.513450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip>
26276 17:04:01.513887 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272 RESULT=skip
26278 17:04:01.563778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass
26280 17:04:01.564189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6288 RESULT=pass>
26281 17:04:01.603229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip>
26282 17:04:01.603649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288 RESULT=skip
26284 17:04:01.658857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip>
26285 17:04:01.659297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288 RESULT=skip
26287 17:04:01.704661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip>
26288 17:04:01.705082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288 RESULT=skip
26290 17:04:01.751684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass
26292 17:04:01.752184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6304 RESULT=pass>
26293 17:04:01.810056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip>
26294 17:04:01.810484 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304 RESULT=skip
26296 17:04:01.864645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip>
26297 17:04:01.865079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304 RESULT=skip
26299 17:04:01.910226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip>
26300 17:04:01.910636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304 RESULT=skip
26302 17:04:01.954300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass>
26303 17:04:01.954728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6320 RESULT=pass
26305 17:04:02.005231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip>
26306 17:04:02.005683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320 RESULT=skip
26308 17:04:02.050219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip>
26309 17:04:02.050652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320 RESULT=skip
26311 17:04:02.096296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip>
26312 17:04:02.096722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320 RESULT=skip
26314 17:04:02.137638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass>
26315 17:04:02.138172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6336 RESULT=pass
26317 17:04:02.181017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip>
26318 17:04:02.181426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336 RESULT=skip
26320 17:04:02.225449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip
26322 17:04:02.225939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336 RESULT=skip>
26323 17:04:02.266852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip>
26324 17:04:02.267252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336 RESULT=skip
26326 17:04:02.321024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass>
26327 17:04:02.321416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6352 RESULT=pass
26329 17:04:02.378980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip>
26330 17:04:02.379412 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352 RESULT=skip
26332 17:04:02.413992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip>
26333 17:04:02.414422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352 RESULT=skip
26335 17:04:02.449968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip
26337 17:04:02.450376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352 RESULT=skip>
26338 17:04:02.486619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass>
26339 17:04:02.487035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6368 RESULT=pass
26341 17:04:02.522313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip
26343 17:04:02.522779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368 RESULT=skip>
26344 17:04:02.567448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip
26346 17:04:02.567925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368 RESULT=skip>
26347 17:04:02.606070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip>
26348 17:04:02.606486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368 RESULT=skip
26350 17:04:02.641097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass
26352 17:04:02.641557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6384 RESULT=pass>
26353 17:04:02.676936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip>
26354 17:04:02.677341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384 RESULT=skip
26356 17:04:02.718195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip
26358 17:04:02.718661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384 RESULT=skip>
26359 17:04:02.753215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip
26361 17:04:02.754049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384 RESULT=skip>
26362 17:04:02.795373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass>
26363 17:04:02.795784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6400 RESULT=pass
26365 17:04:02.837146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip>
26366 17:04:02.837567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400 RESULT=skip
26368 17:04:02.872244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip>
26369 17:04:02.872661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400 RESULT=skip
26371 17:04:02.911484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip>
26372 17:04:02.911915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400 RESULT=skip
26374 17:04:02.945954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass
26376 17:04:02.946426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6416 RESULT=pass>
26377 17:04:02.980718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip
26379 17:04:02.981188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416 RESULT=skip>
26380 17:04:03.020481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip
26382 17:04:03.020947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416 RESULT=skip>
26383 17:04:03.073584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip>
26384 17:04:03.073984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416 RESULT=skip
26386 17:04:03.126913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass>
26387 17:04:03.127359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6432 RESULT=pass
26389 17:04:03.181698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip>
26390 17:04:03.182153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432 RESULT=skip
26392 17:04:03.222745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip>
26393 17:04:03.223109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432 RESULT=skip
26395 17:04:03.266843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip>
26396 17:04:03.267249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432 RESULT=skip
26398 17:04:03.303019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass
26400 17:04:03.303487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6448 RESULT=pass>
26401 17:04:03.340503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip>
26402 17:04:03.340893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448 RESULT=skip
26404 17:04:03.379358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip>
26405 17:04:03.379775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448 RESULT=skip
26407 17:04:03.425857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip>
26408 17:04:03.426269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448 RESULT=skip
26410 17:04:03.461326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass>
26411 17:04:03.461686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6464 RESULT=pass
26413 17:04:03.505721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip>
26414 17:04:03.506146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464 RESULT=skip
26416 17:04:03.547185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip
26418 17:04:03.547947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464 RESULT=skip>
26419 17:04:03.589086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip>
26420 17:04:03.589517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464 RESULT=skip
26422 17:04:03.629817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass
26424 17:04:03.630414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6480 RESULT=pass>
26425 17:04:03.670841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip>
26426 17:04:03.671310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480 RESULT=skip
26428 17:04:03.714609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip>
26429 17:04:03.715070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480 RESULT=skip
26431 17:04:03.761529 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip
26433 17:04:03.762065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480 RESULT=skip>
26434 17:04:03.804791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass>
26435 17:04:03.805206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6496 RESULT=pass
26437 17:04:03.850925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip
26439 17:04:03.851477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496 RESULT=skip>
26440 17:04:03.893995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip
26442 17:04:03.894479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496 RESULT=skip>
26443 17:04:03.938933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip>
26444 17:04:03.939328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496 RESULT=skip
26446 17:04:03.995204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass>
26447 17:04:03.995579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6512 RESULT=pass
26449 17:04:04.037688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip
26451 17:04:04.038448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512 RESULT=skip>
26452 17:04:04.078995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip>
26453 17:04:04.079527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512 RESULT=skip
26455 17:04:04.116687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip>
26456 17:04:04.117049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512 RESULT=skip
26458 17:04:04.164652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass
26460 17:04:04.165034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6528 RESULT=pass>
26461 17:04:04.209348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip
26463 17:04:04.209981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528 RESULT=skip>
26464 17:04:04.251446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip
26466 17:04:04.252139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528 RESULT=skip>
26467 17:04:04.292733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip
26469 17:04:04.293191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528 RESULT=skip>
26470 17:04:04.327328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass
26472 17:04:04.327808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6544 RESULT=pass>
26473 17:04:04.365366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip>
26474 17:04:04.365788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544 RESULT=skip
26476 17:04:04.411281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip
26478 17:04:04.412053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544 RESULT=skip>
26479 17:04:04.449937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip>
26480 17:04:04.450503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544 RESULT=skip
26482 17:04:04.485393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass
26484 17:04:04.486066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6560 RESULT=pass>
26485 17:04:04.522271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip
26487 17:04:04.522732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560 RESULT=skip>
26488 17:04:04.560638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip>
26489 17:04:04.561059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560 RESULT=skip
26491 17:04:04.609866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip>
26492 17:04:04.610292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560 RESULT=skip
26494 17:04:04.650873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass
26496 17:04:04.651299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6576 RESULT=pass>
26497 17:04:04.688825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip>
26498 17:04:04.689249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576 RESULT=skip
26500 17:04:04.732358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip
26502 17:04:04.732831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576 RESULT=skip>
26503 17:04:04.780471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip>
26504 17:04:04.780942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576 RESULT=skip
26506 17:04:04.832694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass>
26507 17:04:04.833156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6592 RESULT=pass
26509 17:04:04.879952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip
26511 17:04:04.880353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592 RESULT=skip>
26512 17:04:04.925908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip>
26513 17:04:04.926330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592 RESULT=skip
26515 17:04:04.963620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip
26517 17:04:04.964203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592 RESULT=skip>
26518 17:04:05.003260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass>
26519 17:04:05.003642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6608 RESULT=pass
26521 17:04:05.038129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip>
26522 17:04:05.038549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608 RESULT=skip
26524 17:04:05.075326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip>
26525 17:04:05.075829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608 RESULT=skip
26527 17:04:05.123832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip
26529 17:04:05.124386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608 RESULT=skip>
26530 17:04:05.168851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass
26532 17:04:05.169239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6624 RESULT=pass>
26533 17:04:05.218980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip>
26534 17:04:05.219372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624 RESULT=skip
26536 17:04:05.248183 <47>[ 299.348878] systemd-journald[109]: Sent WATCHDOG=1 notification.
26537 17:04:05.284662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip>
26538 17:04:05.285086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624 RESULT=skip
26540 17:04:05.330328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip
26542 17:04:05.330794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624 RESULT=skip>
26543 17:04:05.380780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass>
26544 17:04:05.381282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6640 RESULT=pass
26546 17:04:05.430037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip>
26547 17:04:05.430612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640 RESULT=skip
26549 17:04:05.484349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip>
26550 17:04:05.484734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640 RESULT=skip
26552 17:04:05.534879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip>
26553 17:04:05.535266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640 RESULT=skip
26555 17:04:05.578388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass
26557 17:04:05.578821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6656 RESULT=pass>
26558 17:04:05.629726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip
26560 17:04:05.630478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656 RESULT=skip>
26561 17:04:05.681140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip
26563 17:04:05.681538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656 RESULT=skip>
26564 17:04:05.726356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip
26566 17:04:05.726781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656 RESULT=skip>
26567 17:04:05.763732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass
26569 17:04:05.764514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6672 RESULT=pass>
26570 17:04:05.806586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip>
26571 17:04:05.807165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672 RESULT=skip
26573 17:04:05.850432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip>
26574 17:04:05.850861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672 RESULT=skip
26576 17:04:05.898467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip
26578 17:04:05.898943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672 RESULT=skip>
26579 17:04:05.943337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass>
26580 17:04:05.943788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6688 RESULT=pass
26582 17:04:05.984684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip
26584 17:04:05.985189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688 RESULT=skip>
26585 17:04:06.024873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip>
26586 17:04:06.025315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688 RESULT=skip
26588 17:04:06.062590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip>
26589 17:04:06.063027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688 RESULT=skip
26591 17:04:06.097715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass>
26592 17:04:06.098269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6704 RESULT=pass
26594 17:04:06.133071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip
26596 17:04:06.133689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704 RESULT=skip>
26597 17:04:06.172474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip>
26598 17:04:06.172895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704 RESULT=skip
26600 17:04:06.207027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip>
26601 17:04:06.207496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704 RESULT=skip
26603 17:04:06.245172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass>
26604 17:04:06.245575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6720 RESULT=pass
26606 17:04:06.301092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip>
26607 17:04:06.301526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720 RESULT=skip
26609 17:04:06.344648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip>
26610 17:04:06.345071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720 RESULT=skip
26612 17:04:06.382048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip>
26613 17:04:06.382499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720 RESULT=skip
26615 17:04:06.417251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass
26617 17:04:06.417632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6736 RESULT=pass>
26618 17:04:06.457566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip>
26619 17:04:06.457989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736 RESULT=skip
26621 17:04:06.493786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip>
26622 17:04:06.494359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736 RESULT=skip
26624 17:04:06.541888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip
26626 17:04:06.542273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736 RESULT=skip>
26627 17:04:06.592462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass>
26628 17:04:06.592894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6752 RESULT=pass
26630 17:04:06.642219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip>
26631 17:04:06.642681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752 RESULT=skip
26633 17:04:06.691138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip>
26634 17:04:06.691622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752 RESULT=skip
26636 17:04:06.734219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip>
26637 17:04:06.734637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752 RESULT=skip
26639 17:04:06.783749 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass
26641 17:04:06.784212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6768 RESULT=pass>
26642 17:04:06.830781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip>
26643 17:04:06.831169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768 RESULT=skip
26645 17:04:06.870234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip
26647 17:04:06.870673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768 RESULT=skip>
26648 17:04:06.910599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip>
26649 17:04:06.911017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768 RESULT=skip
26651 17:04:06.965004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass>
26652 17:04:06.965382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6784 RESULT=pass
26654 17:04:07.009737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip>
26655 17:04:07.010200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784 RESULT=skip
26657 17:04:07.056494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip>
26658 17:04:07.057008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784 RESULT=skip
26660 17:04:07.096044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip
26662 17:04:07.096513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784 RESULT=skip>
26663 17:04:07.131213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass
26665 17:04:07.131686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6800 RESULT=pass>
26666 17:04:07.173271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip>
26667 17:04:07.173680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800 RESULT=skip
26669 17:04:07.213263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip>
26670 17:04:07.213700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800 RESULT=skip
26672 17:04:07.259907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip
26674 17:04:07.260572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800 RESULT=skip>
26675 17:04:07.294260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass>
26676 17:04:07.294673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6816 RESULT=pass
26678 17:04:07.332422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip
26680 17:04:07.332888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816 RESULT=skip>
26681 17:04:07.373148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip
26683 17:04:07.373616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816 RESULT=skip>
26684 17:04:07.418256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip>
26685 17:04:07.418795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816 RESULT=skip
26687 17:04:07.461601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass
26689 17:04:07.461992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6832 RESULT=pass>
26690 17:04:07.513278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip>
26691 17:04:07.513684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832 RESULT=skip
26693 17:04:07.553250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip>
26694 17:04:07.553708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832 RESULT=skip
26696 17:04:07.594390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip
26698 17:04:07.594880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832 RESULT=skip>
26699 17:04:07.630838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass>
26700 17:04:07.631213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6848 RESULT=pass
26702 17:04:07.665409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip>
26703 17:04:07.665921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848 RESULT=skip
26705 17:04:07.711016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip>
26706 17:04:07.711448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848 RESULT=skip
26708 17:04:07.745217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip>
26709 17:04:07.745715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848 RESULT=skip
26711 17:04:07.795601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass
26713 17:04:07.796195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6864 RESULT=pass>
26714 17:04:07.844239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip>
26715 17:04:07.844695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864 RESULT=skip
26717 17:04:07.888984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip>
26718 17:04:07.889473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864 RESULT=skip
26720 17:04:07.921911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip>
26721 17:04:07.922297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864 RESULT=skip
26723 17:04:07.956095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass>
26724 17:04:07.956541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6880 RESULT=pass
26726 17:04:07.990185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip
26728 17:04:07.990816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880 RESULT=skip>
26729 17:04:08.026746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip
26731 17:04:08.027201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880 RESULT=skip>
26732 17:04:08.067843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip
26734 17:04:08.068319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880 RESULT=skip>
26735 17:04:08.102840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass>
26736 17:04:08.103282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6896 RESULT=pass
26738 17:04:08.139479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip>
26739 17:04:08.139908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896 RESULT=skip
26741 17:04:08.176413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip>
26742 17:04:08.176841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896 RESULT=skip
26744 17:04:08.211400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip>
26745 17:04:08.211835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896 RESULT=skip
26747 17:04:08.247046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass
26749 17:04:08.247699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6912 RESULT=pass>
26750 17:04:08.281212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip>
26751 17:04:08.281698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912 RESULT=skip
26753 17:04:08.317294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip>
26754 17:04:08.317868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912 RESULT=skip
26756 17:04:08.353548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip
26758 17:04:08.354017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912 RESULT=skip>
26759 17:04:08.393673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass>
26760 17:04:08.394191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6928 RESULT=pass
26762 17:04:08.449795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip>
26763 17:04:08.453730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928 RESULT=skip
26765 17:04:08.494641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip>
26766 17:04:08.495100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928 RESULT=skip
26768 17:04:08.535219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip>
26769 17:04:08.535599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928 RESULT=skip
26771 17:04:08.577392 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass
26773 17:04:08.578018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6944 RESULT=pass>
26774 17:04:08.620979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip>
26775 17:04:08.621390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944 RESULT=skip
26777 17:04:08.656774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip>
26778 17:04:08.657150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944 RESULT=skip
26780 17:04:08.701072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip>
26781 17:04:08.701498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944 RESULT=skip
26783 17:04:08.741831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass>
26784 17:04:08.742249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6960 RESULT=pass
26786 17:04:08.779627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip
26788 17:04:08.780055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960 RESULT=skip>
26789 17:04:08.819234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip
26791 17:04:08.819639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960 RESULT=skip>
26792 17:04:08.856519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip
26794 17:04:08.856909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960 RESULT=skip>
26795 17:04:08.894745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass
26797 17:04:08.895727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6976 RESULT=pass>
26798 17:04:08.931496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip>
26799 17:04:08.931931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976 RESULT=skip
26801 17:04:08.970584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip>
26802 17:04:08.970993 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976 RESULT=skip
26804 17:04:09.005764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip
26806 17:04:09.006242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976 RESULT=skip>
26807 17:04:09.041174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass>
26808 17:04:09.041601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_6992 RESULT=pass
26810 17:04:09.079285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip>
26811 17:04:09.079742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992 RESULT=skip
26813 17:04:09.122782 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip
26815 17:04:09.123381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992 RESULT=skip>
26816 17:04:09.158672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip>
26817 17:04:09.159047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992 RESULT=skip
26819 17:04:09.206749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass>
26820 17:04:09.207189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7008 RESULT=pass
26822 17:04:09.254590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip
26824 17:04:09.255072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008 RESULT=skip>
26825 17:04:09.288729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip>
26826 17:04:09.289200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008 RESULT=skip
26828 17:04:09.337775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip
26830 17:04:09.338391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008 RESULT=skip>
26831 17:04:09.371773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass
26833 17:04:09.372249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7024 RESULT=pass>
26834 17:04:09.406912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip
26836 17:04:09.407376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024 RESULT=skip>
26837 17:04:09.442902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip>
26838 17:04:09.443319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024 RESULT=skip
26840 17:04:09.478283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip>
26841 17:04:09.478698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024 RESULT=skip
26843 17:04:09.513301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass>
26844 17:04:09.513680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7040 RESULT=pass
26846 17:04:09.548621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip
26848 17:04:09.549078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040 RESULT=skip>
26849 17:04:09.581422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip>
26850 17:04:09.581858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040 RESULT=skip
26852 17:04:09.616343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip
26854 17:04:09.616804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040 RESULT=skip>
26855 17:04:09.651099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass>
26856 17:04:09.651572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7056 RESULT=pass
26858 17:04:09.686217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip>
26859 17:04:09.686643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056 RESULT=skip
26861 17:04:09.722530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip>
26862 17:04:09.722950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056 RESULT=skip
26864 17:04:09.758288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip
26866 17:04:09.758701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056 RESULT=skip>
26867 17:04:09.791746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass
26869 17:04:09.792386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7072 RESULT=pass>
26870 17:04:09.827238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip>
26871 17:04:09.827688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072 RESULT=skip
26873 17:04:09.862346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip
26875 17:04:09.863086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072 RESULT=skip>
26876 17:04:09.896968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip>
26877 17:04:09.897384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072 RESULT=skip
26879 17:04:09.931139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass>
26880 17:04:09.931560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7088 RESULT=pass
26882 17:04:09.966595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip>
26883 17:04:09.966996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088 RESULT=skip
26885 17:04:10.001258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip>
26886 17:04:10.001689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088 RESULT=skip
26888 17:04:10.035750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip
26890 17:04:10.036222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088 RESULT=skip>
26891 17:04:10.081551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass>
26892 17:04:10.081973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7104 RESULT=pass
26894 17:04:10.128248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip>
26895 17:04:10.128683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104 RESULT=skip
26897 17:04:10.173633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip>
26898 17:04:10.174059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104 RESULT=skip
26900 17:04:10.217710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip
26902 17:04:10.218169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104 RESULT=skip>
26903 17:04:10.259090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass
26905 17:04:10.259562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7120 RESULT=pass>
26906 17:04:10.297066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip>
26907 17:04:10.297501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120 RESULT=skip
26909 17:04:10.333581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip>
26910 17:04:10.334025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120 RESULT=skip
26912 17:04:10.377623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip>
26913 17:04:10.378056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120 RESULT=skip
26915 17:04:10.426480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass>
26916 17:04:10.426901 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7136 RESULT=pass
26918 17:04:10.473731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip>
26919 17:04:10.474180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136 RESULT=skip
26921 17:04:10.518819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip>
26922 17:04:10.519305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136 RESULT=skip
26924 17:04:10.558943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip
26926 17:04:10.559355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136 RESULT=skip>
26927 17:04:10.600269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass>
26928 17:04:10.600833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7152 RESULT=pass
26930 17:04:10.644902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip>
26931 17:04:10.645351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152 RESULT=skip
26933 17:04:10.695300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip>
26934 17:04:10.695732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152 RESULT=skip
26936 17:04:10.738185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip>
26937 17:04:10.738625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152 RESULT=skip
26939 17:04:10.782874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass>
26940 17:04:10.783370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7168 RESULT=pass
26942 17:04:10.822465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip>
26943 17:04:10.822863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168 RESULT=skip
26945 17:04:10.864752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip
26947 17:04:10.865214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168 RESULT=skip>
26948 17:04:10.900937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip>
26949 17:04:10.901376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168 RESULT=skip
26951 17:04:10.947387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass>
26952 17:04:10.947952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7184 RESULT=pass
26954 17:04:10.981723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip>
26955 17:04:10.982166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184 RESULT=skip
26957 17:04:11.030050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip>
26958 17:04:11.030531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184 RESULT=skip
26960 17:04:11.067148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip>
26961 17:04:11.067573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184 RESULT=skip
26963 17:04:11.104615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass
26965 17:04:11.105070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7200 RESULT=pass>
26966 17:04:11.138112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip>
26967 17:04:11.138558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200 RESULT=skip
26969 17:04:11.174658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip>
26970 17:04:11.175074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200 RESULT=skip
26972 17:04:11.213066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip>
26973 17:04:11.213503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200 RESULT=skip
26975 17:04:11.267846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass
26977 17:04:11.268411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7216 RESULT=pass>
26978 17:04:11.312891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip>
26979 17:04:11.313322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216 RESULT=skip
26981 17:04:11.361300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip>
26982 17:04:11.361760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216 RESULT=skip
26984 17:04:11.409609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip>
26985 17:04:11.410060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216 RESULT=skip
26987 17:04:11.447206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass
26989 17:04:11.447677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7232 RESULT=pass>
26990 17:04:11.484213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip>
26991 17:04:11.484654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232 RESULT=skip
26993 17:04:11.519306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip>
26994 17:04:11.519741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232 RESULT=skip
26996 17:04:11.554015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip
26998 17:04:11.554481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232 RESULT=skip>
26999 17:04:11.588340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass>
27000 17:04:11.588775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7248 RESULT=pass
27002 17:04:11.622437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip>
27003 17:04:11.622861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248 RESULT=skip
27005 17:04:11.656876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip>
27006 17:04:11.657222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248 RESULT=skip
27008 17:04:11.695165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip
27010 17:04:11.695640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248 RESULT=skip>
27011 17:04:11.743623 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass
27013 17:04:11.744094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7264 RESULT=pass>
27014 17:04:11.778330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip
27016 17:04:11.778797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264 RESULT=skip>
27017 17:04:11.813553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip>
27018 17:04:11.813983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264 RESULT=skip
27020 17:04:11.848751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip>
27021 17:04:11.849176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264 RESULT=skip
27023 17:04:11.882882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass
27025 17:04:11.883334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7280 RESULT=pass>
27026 17:04:11.916955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip>
27027 17:04:11.917370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280 RESULT=skip
27029 17:04:11.950472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip
27031 17:04:11.950928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280 RESULT=skip>
27032 17:04:11.983027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip>
27033 17:04:11.983445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280 RESULT=skip
27035 17:04:12.015215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass>
27036 17:04:12.015630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7296 RESULT=pass
27038 17:04:12.062815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip>
27039 17:04:12.063229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296 RESULT=skip
27041 17:04:12.096181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip>
27042 17:04:12.096615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296 RESULT=skip
27044 17:04:12.129194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip>
27045 17:04:12.129698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296 RESULT=skip
27047 17:04:12.163831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass
27049 17:04:12.164288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7312 RESULT=pass>
27050 17:04:12.198034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip>
27051 17:04:12.198469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312 RESULT=skip
27053 17:04:12.238833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip>
27054 17:04:12.239363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312 RESULT=skip
27056 17:04:12.288776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip
27058 17:04:12.289245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312 RESULT=skip>
27059 17:04:12.320932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass>
27060 17:04:12.321306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7328 RESULT=pass
27062 17:04:12.353427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip
27064 17:04:12.353869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328 RESULT=skip>
27065 17:04:12.385624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip
27067 17:04:12.386277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328 RESULT=skip>
27068 17:04:12.419601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip>
27069 17:04:12.420094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328 RESULT=skip
27071 17:04:12.462619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass>
27072 17:04:12.463054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7344 RESULT=pass
27074 17:04:12.509251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip>
27075 17:04:12.509676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344 RESULT=skip
27077 17:04:12.547135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip>
27078 17:04:12.547583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344 RESULT=skip
27080 17:04:12.582122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip>
27081 17:04:12.582543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344 RESULT=skip
27083 17:04:12.617262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass>
27084 17:04:12.617687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7360 RESULT=pass
27086 17:04:12.651808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip
27088 17:04:12.652279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360 RESULT=skip>
27089 17:04:12.689700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip
27091 17:04:12.690144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360 RESULT=skip>
27092 17:04:12.724985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip>
27093 17:04:12.725399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360 RESULT=skip
27095 17:04:12.757134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass>
27096 17:04:12.757614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7376 RESULT=pass
27098 17:04:12.796555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip>
27099 17:04:12.797067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376 RESULT=skip
27101 17:04:12.834310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip>
27102 17:04:12.834743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376 RESULT=skip
27104 17:04:12.870535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip>
27105 17:04:12.870940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376 RESULT=skip
27107 17:04:12.913328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass>
27108 17:04:12.913732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7392 RESULT=pass
27110 17:04:12.948748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip>
27111 17:04:12.949316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392 RESULT=skip
27113 17:04:12.983067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip>
27114 17:04:12.983490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392 RESULT=skip
27116 17:04:13.017075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip
27118 17:04:13.017462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392 RESULT=skip>
27119 17:04:13.052499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass>
27120 17:04:13.052899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7408 RESULT=pass
27122 17:04:13.087773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip
27124 17:04:13.088258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408 RESULT=skip>
27125 17:04:13.125565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip>
27126 17:04:13.126000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408 RESULT=skip
27128 17:04:13.172949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip>
27129 17:04:13.173372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408 RESULT=skip
27131 17:04:13.207169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass
27133 17:04:13.207616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7424 RESULT=pass>
27134 17:04:13.241131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip>
27135 17:04:13.241622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424 RESULT=skip
27137 17:04:13.293166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip>
27138 17:04:13.293589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424 RESULT=skip
27140 17:04:13.337321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip>
27141 17:04:13.337747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424 RESULT=skip
27143 17:04:13.380274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass>
27144 17:04:13.380709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7440 RESULT=pass
27146 17:04:13.418349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip>
27147 17:04:13.418841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440 RESULT=skip
27149 17:04:13.460789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip>
27150 17:04:13.461170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440 RESULT=skip
27152 17:04:13.515353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip>
27153 17:04:13.515794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440 RESULT=skip
27155 17:04:13.565268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass>
27156 17:04:13.565629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7456 RESULT=pass
27158 17:04:13.605005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip
27160 17:04:13.605448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456 RESULT=skip>
27161 17:04:13.646157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip>
27162 17:04:13.646640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456 RESULT=skip
27164 17:04:13.681578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip>
27165 17:04:13.682011 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456 RESULT=skip
27167 17:04:13.717957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass
27169 17:04:13.718435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7472 RESULT=pass>
27170 17:04:13.753125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip>
27171 17:04:13.753569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472 RESULT=skip
27173 17:04:13.794984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip
27175 17:04:13.795368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472 RESULT=skip>
27176 17:04:13.850130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip>
27177 17:04:13.850510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472 RESULT=skip
27179 17:04:13.898777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass>
27180 17:04:13.899182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7488 RESULT=pass
27182 17:04:13.934039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip
27184 17:04:13.934757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488 RESULT=skip>
27185 17:04:13.969066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip>
27186 17:04:13.969485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488 RESULT=skip
27188 17:04:14.006519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip
27190 17:04:14.006964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488 RESULT=skip>
27191 17:04:14.041167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass
27193 17:04:14.041603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7504 RESULT=pass>
27194 17:04:14.076541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip>
27195 17:04:14.076975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504 RESULT=skip
27197 17:04:14.112277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip>
27198 17:04:14.112684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504 RESULT=skip
27200 17:04:14.155814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip
27202 17:04:14.156170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504 RESULT=skip>
27203 17:04:14.202621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass
27205 17:04:14.203069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7520 RESULT=pass>
27206 17:04:14.241935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip
27208 17:04:14.242393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520 RESULT=skip>
27209 17:04:14.282672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip
27211 17:04:14.283136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520 RESULT=skip>
27212 17:04:14.323736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip
27214 17:04:14.324180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520 RESULT=skip>
27215 17:04:14.360848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass>
27216 17:04:14.361247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7536 RESULT=pass
27218 17:04:14.401635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip>
27219 17:04:14.401985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536 RESULT=skip
27221 17:04:14.441673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip>
27222 17:04:14.442153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536 RESULT=skip
27224 17:04:14.482781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip
27226 17:04:14.483326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536 RESULT=skip>
27227 17:04:14.524544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass>
27228 17:04:14.524907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7552 RESULT=pass
27230 17:04:14.565563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip
27232 17:04:14.565874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552 RESULT=skip>
27233 17:04:14.611095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip>
27234 17:04:14.611475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552 RESULT=skip
27236 17:04:14.657130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip>
27237 17:04:14.657563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552 RESULT=skip
27239 17:04:14.694089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass
27241 17:04:14.694690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7568 RESULT=pass>
27242 17:04:14.735061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip>
27243 17:04:14.735435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568 RESULT=skip
27245 17:04:14.772953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip>
27246 17:04:14.773318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568 RESULT=skip
27248 17:04:14.810792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip>
27249 17:04:14.811211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568 RESULT=skip
27251 17:04:14.851092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass>
27252 17:04:14.851515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7584 RESULT=pass
27254 17:04:14.886671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip>
27255 17:04:14.887141 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584 RESULT=skip
27257 17:04:14.922463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip>
27258 17:04:14.923005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584 RESULT=skip
27260 17:04:14.958071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip>
27261 17:04:14.958481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584 RESULT=skip
27263 17:04:15.002767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass
27265 17:04:15.003516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7600 RESULT=pass>
27266 17:04:15.046110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip>
27267 17:04:15.046536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600 RESULT=skip
27269 17:04:15.083841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip
27271 17:04:15.084303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600 RESULT=skip>
27272 17:04:15.124731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip>
27273 17:04:15.125110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600 RESULT=skip
27275 17:04:15.160565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass
27277 17:04:15.160923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7616 RESULT=pass>
27278 17:04:15.197624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip
27280 17:04:15.198094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616 RESULT=skip>
27281 17:04:15.234403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip>
27282 17:04:15.234812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616 RESULT=skip
27284 17:04:15.280366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip
27286 17:04:15.280894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616 RESULT=skip>
27287 17:04:15.320499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass>
27288 17:04:15.320898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7632 RESULT=pass
27290 17:04:15.362826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip>
27291 17:04:15.363196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632 RESULT=skip
27293 17:04:15.401889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip>
27294 17:04:15.402304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632 RESULT=skip
27296 17:04:15.437204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip>
27297 17:04:15.437689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632 RESULT=skip
27299 17:04:15.482226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass
27301 17:04:15.482848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7648 RESULT=pass>
27302 17:04:15.523865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip
27304 17:04:15.524332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648 RESULT=skip>
27305 17:04:15.571342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip>
27306 17:04:15.571747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648 RESULT=skip
27308 17:04:15.619561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip>
27309 17:04:15.620063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648 RESULT=skip
27311 17:04:15.666963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass>
27312 17:04:15.667419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7664 RESULT=pass
27314 17:04:15.708926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip>
27315 17:04:15.709346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664 RESULT=skip
27317 17:04:15.748531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip
27319 17:04:15.748987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664 RESULT=skip>
27320 17:04:15.785227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip
27322 17:04:15.785933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664 RESULT=skip>
27323 17:04:15.820959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass>
27324 17:04:15.821503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7680 RESULT=pass
27326 17:04:15.858069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip
27328 17:04:15.858672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680 RESULT=skip>
27329 17:04:15.894180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip>
27330 17:04:15.894563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680 RESULT=skip
27332 17:04:15.932742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip>
27333 17:04:15.933227 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680 RESULT=skip
27335 17:04:15.974639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass
27337 17:04:15.975082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7696 RESULT=pass>
27338 17:04:16.020977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip>
27339 17:04:16.021390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696 RESULT=skip
27341 17:04:16.057209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip>
27342 17:04:16.057597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696 RESULT=skip
27344 17:04:16.101695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip>
27345 17:04:16.102109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696 RESULT=skip
27347 17:04:16.150060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass>
27348 17:04:16.150506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7712 RESULT=pass
27350 17:04:16.200446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip>
27351 17:04:16.200860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712 RESULT=skip
27353 17:04:16.248779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip>
27354 17:04:16.249326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712 RESULT=skip
27356 17:04:16.286768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip>
27357 17:04:16.287195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712 RESULT=skip
27359 17:04:16.322842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass>
27360 17:04:16.323261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7728 RESULT=pass
27362 17:04:16.369072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip>
27363 17:04:16.369499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728 RESULT=skip
27365 17:04:16.422540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip
27367 17:04:16.423134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728 RESULT=skip>
27368 17:04:16.457872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip>
27369 17:04:16.458306 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728 RESULT=skip
27371 17:04:16.504131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass>
27372 17:04:16.504582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7744 RESULT=pass
27374 17:04:16.549081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip>
27375 17:04:16.549505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744 RESULT=skip
27377 17:04:16.585254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip>
27378 17:04:16.585688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744 RESULT=skip
27380 17:04:16.630577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip
27382 17:04:16.631020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744 RESULT=skip>
27383 17:04:16.673442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass>
27384 17:04:16.673950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7760 RESULT=pass
27386 17:04:16.712954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip>
27387 17:04:16.713391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760 RESULT=skip
27389 17:04:16.756995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip>
27390 17:04:16.757423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760 RESULT=skip
27392 17:04:16.794036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip
27394 17:04:16.794492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760 RESULT=skip>
27395 17:04:16.830705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass
27397 17:04:16.831168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7776 RESULT=pass>
27398 17:04:16.875423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip>
27399 17:04:16.875850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776 RESULT=skip
27401 17:04:16.921807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip
27403 17:04:16.922269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776 RESULT=skip>
27404 17:04:16.971304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip
27406 17:04:16.972072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776 RESULT=skip>
27407 17:04:17.019567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass
27409 17:04:17.020067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7792 RESULT=pass>
27410 17:04:17.067005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip>
27411 17:04:17.067428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792 RESULT=skip
27413 17:04:17.109804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip>
27414 17:04:17.110182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792 RESULT=skip
27416 17:04:17.145972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip>
27417 17:04:17.146399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792 RESULT=skip
27419 17:04:17.219073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass
27421 17:04:17.219544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7808 RESULT=pass>
27422 17:04:17.254909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip
27424 17:04:17.255383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808 RESULT=skip>
27425 17:04:17.291126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip>
27426 17:04:17.291553 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808 RESULT=skip
27428 17:04:17.335057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip>
27429 17:04:17.335438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808 RESULT=skip
27431 17:04:17.371925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass
27433 17:04:17.372399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7824 RESULT=pass>
27434 17:04:17.408132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip
27436 17:04:17.408593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824 RESULT=skip>
27437 17:04:17.454218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip>
27438 17:04:17.454654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824 RESULT=skip
27440 17:04:17.503004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip
27442 17:04:17.503469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824 RESULT=skip>
27443 17:04:17.550927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass
27445 17:04:17.551371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7840 RESULT=pass>
27446 17:04:17.588528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip
27448 17:04:17.588998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840 RESULT=skip>
27449 17:04:17.628854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip>
27450 17:04:17.629237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840 RESULT=skip
27452 17:04:17.684447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip>
27453 17:04:17.684857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840 RESULT=skip
27455 17:04:17.739954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass
27457 17:04:17.740328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7856 RESULT=pass>
27458 17:04:17.782733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip>
27459 17:04:17.783209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856 RESULT=skip
27461 17:04:17.839800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip
27463 17:04:17.840214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856 RESULT=skip>
27464 17:04:17.889860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip>
27465 17:04:17.890243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856 RESULT=skip
27467 17:04:17.941129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass>
27468 17:04:17.941577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7872 RESULT=pass
27470 17:04:17.984742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip>
27471 17:04:17.985188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872 RESULT=skip
27473 17:04:18.021313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip
27475 17:04:18.021789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872 RESULT=skip>
27476 17:04:18.057878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip
27478 17:04:18.058333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872 RESULT=skip>
27479 17:04:18.096740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass
27481 17:04:18.097119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7888 RESULT=pass>
27482 17:04:18.128878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip>
27483 17:04:18.129294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888 RESULT=skip
27485 17:04:18.160940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip>
27486 17:04:18.161427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888 RESULT=skip
27488 17:04:18.210044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip
27490 17:04:18.210872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888 RESULT=skip>
27491 17:04:18.255352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass
27493 17:04:18.255796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7904 RESULT=pass>
27494 17:04:18.297094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip>
27495 17:04:18.297514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904 RESULT=skip
27497 17:04:18.334917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip>
27498 17:04:18.335340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904 RESULT=skip
27500 17:04:18.373494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip>
27501 17:04:18.373898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904 RESULT=skip
27503 17:04:18.417788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass>
27504 17:04:18.418230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7920 RESULT=pass
27506 17:04:18.452518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip>
27507 17:04:18.452940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920 RESULT=skip
27509 17:04:18.493937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip>
27510 17:04:18.494501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920 RESULT=skip
27512 17:04:18.547208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip
27514 17:04:18.547859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920 RESULT=skip>
27515 17:04:18.583050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass>
27516 17:04:18.583542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7936 RESULT=pass
27518 17:04:18.620414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip
27520 17:04:18.621146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936 RESULT=skip>
27521 17:04:18.664032 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip
27523 17:04:18.664504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936 RESULT=skip>
27524 17:04:18.710006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip>
27525 17:04:18.710499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936 RESULT=skip
27527 17:04:18.751747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass
27529 17:04:18.752219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7952 RESULT=pass>
27530 17:04:18.804986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip
27532 17:04:18.805361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952 RESULT=skip>
27533 17:04:18.853849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip>
27534 17:04:18.854276 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952 RESULT=skip
27536 17:04:18.898350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip
27538 17:04:18.898822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952 RESULT=skip>
27539 17:04:18.942544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass>
27540 17:04:18.942986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7968 RESULT=pass
27542 17:04:18.992898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip>
27543 17:04:18.993323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968 RESULT=skip
27545 17:04:19.039320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip>
27546 17:04:19.039759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968 RESULT=skip
27548 17:04:19.081312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip>
27549 17:04:19.081737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968 RESULT=skip
27551 17:04:19.122169 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass
27553 17:04:19.122841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_7984 RESULT=pass>
27554 17:04:19.163407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip
27556 17:04:19.163863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984 RESULT=skip>
27557 17:04:19.202121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip
27559 17:04:19.202576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984 RESULT=skip>
27560 17:04:19.259975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip
27562 17:04:19.260418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984 RESULT=skip>
27563 17:04:19.303069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass>
27564 17:04:19.303497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8000 RESULT=pass
27566 17:04:19.349152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip>
27567 17:04:19.349581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000 RESULT=skip
27569 17:04:19.397126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip>
27570 17:04:19.397597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000 RESULT=skip
27572 17:04:19.439074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip
27574 17:04:19.439657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000 RESULT=skip>
27575 17:04:19.483991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass
27577 17:04:19.484467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8016 RESULT=pass>
27578 17:04:19.532444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip>
27579 17:04:19.532855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016 RESULT=skip
27581 17:04:19.580514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip>
27582 17:04:19.580933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016 RESULT=skip
27584 17:04:19.624990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip>
27585 17:04:19.625405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016 RESULT=skip
27587 17:04:19.674149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass>
27588 17:04:19.674612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8032 RESULT=pass
27590 17:04:19.715900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip
27592 17:04:19.716532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032 RESULT=skip>
27593 17:04:19.762316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip>
27594 17:04:19.762743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032 RESULT=skip
27596 17:04:19.806873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip>
27597 17:04:19.807294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032 RESULT=skip
27599 17:04:19.853476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass
27601 17:04:19.853963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8048 RESULT=pass>
27602 17:04:19.899295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip>
27603 17:04:19.899734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048 RESULT=skip
27605 17:04:19.942211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip>
27606 17:04:19.942626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048 RESULT=skip
27608 17:04:19.985520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip>
27609 17:04:19.985931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048 RESULT=skip
27611 17:04:20.025830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass
27613 17:04:20.026252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8064 RESULT=pass>
27614 17:04:20.073047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip>
27615 17:04:20.073431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064 RESULT=skip
27617 17:04:20.117191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip>
27618 17:04:20.117581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064 RESULT=skip
27620 17:04:20.160851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip>
27621 17:04:20.161250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064 RESULT=skip
27623 17:04:20.198342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass>
27624 17:04:20.198784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8080 RESULT=pass
27626 17:04:20.236500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip
27628 17:04:20.236877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080 RESULT=skip>
27629 17:04:20.278089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip>
27630 17:04:20.278432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080 RESULT=skip
27632 17:04:20.324290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip>
27633 17:04:20.324726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080 RESULT=skip
27635 17:04:20.361006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass>
27636 17:04:20.361456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8096 RESULT=pass
27638 17:04:20.409715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip>
27639 17:04:20.410199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096 RESULT=skip
27641 17:04:20.460507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip
27643 17:04:20.460990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096 RESULT=skip>
27644 17:04:20.510359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip>
27645 17:04:20.510703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096 RESULT=skip
27647 17:04:20.546076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass>
27648 17:04:20.546467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8112 RESULT=pass
27650 17:04:20.590218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip
27652 17:04:20.590799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112 RESULT=skip>
27653 17:04:20.644660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip>
27654 17:04:20.645102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112 RESULT=skip
27656 17:04:20.690405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip>
27657 17:04:20.690806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112 RESULT=skip
27659 17:04:20.735862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass
27661 17:04:20.737148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8128 RESULT=pass>
27662 17:04:20.782873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip>
27663 17:04:20.783277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128 RESULT=skip
27665 17:04:20.825921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip>
27666 17:04:20.826472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128 RESULT=skip
27668 17:04:20.867733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip
27670 17:04:20.868314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128 RESULT=skip>
27671 17:04:20.913477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass>
27672 17:04:20.913939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8144 RESULT=pass
27674 17:04:20.962160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip>
27675 17:04:20.962595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144 RESULT=skip
27677 17:04:21.009701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip
27679 17:04:21.010353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144 RESULT=skip>
27680 17:04:21.051614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip>
27681 17:04:21.052097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144 RESULT=skip
27683 17:04:21.097445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass>
27684 17:04:21.097963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8160 RESULT=pass
27686 17:04:21.149440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip>
27687 17:04:21.149932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160 RESULT=skip
27689 17:04:21.199204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip>
27690 17:04:21.199656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160 RESULT=skip
27692 17:04:21.245098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip>
27693 17:04:21.245472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160 RESULT=skip
27695 17:04:21.285260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass
27697 17:04:21.285758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8176 RESULT=pass>
27698 17:04:21.326678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip
27700 17:04:21.327215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176 RESULT=skip>
27701 17:04:21.371232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip>
27702 17:04:21.371661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176 RESULT=skip
27704 17:04:21.413827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip>
27705 17:04:21.414252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176 RESULT=skip
27707 17:04:21.457644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass
27709 17:04:21.458126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Set_Streaming_SVE_VL_8192 RESULT=pass>
27710 17:04:21.503248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip>
27711 17:04:21.503699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192 RESULT=skip
27713 17:04:21.551483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip>
27714 17:04:21.551946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192 RESULT=skip
27716 17:04:21.598772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip
27718 17:04:21.599235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192 RESULT=skip>
27719 17:04:21.641848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=pass>
27720 17:04:21.642287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=pass
27722 17:04:21.681818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass>
27723 17:04:21.682259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_Enumerated_16_vector_lengths RESULT=pass
27725 17:04:21.730295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass>
27726 17:04:21.730745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_All_vector_lengths_valid RESULT=pass
27728 17:04:21.781494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass>
27729 17:04:21.782072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=pass
27731 17:04:21.832015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass
27733 17:04:21.832601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_default_vector_length_64 RESULT=pass>
27734 17:04:21.882339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass
27736 17:04:21.882815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_minimum_vector_length_16 RESULT=pass>
27737 17:04:21.921060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass>
27738 17:04:21.921485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_maximum_vector_length_256 RESULT=pass
27740 17:04:21.962073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass
27742 17:04:21.962758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_current_VL_is_64 RESULT=pass>
27743 17:04:22.001764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass>
27744 17:04:22.002188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64 RESULT=pass
27746 17:04:22.038472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass>
27747 17:04:22.038884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_min_max RESULT=pass
27749 17:04:22.083648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass>
27750 17:04:22.084074 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_used_default RESULT=pass
27752 17:04:22.139530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass>
27753 17:04:22.139954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_was_inherited RESULT=pass
27755 17:04:22.195841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass
27757 17:04:22.196526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_vector_length_set_on_exec RESULT=pass>
27758 17:04:22.241553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass>
27759 17:04:22.241956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors RESULT=pass
27761 17:04:22.316872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass>
27762 17:04:22.317329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_default_vector_length_32 RESULT=pass
27764 17:04:22.366759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass>
27765 17:04:22.367270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_minimum_vector_length_16 RESULT=pass
27767 17:04:22.415308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass>
27768 17:04:22.415759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_maximum_vector_length_256 RESULT=pass
27770 17:04:22.460512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass>
27771 17:04:22.461055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_current_VL_is_32 RESULT=pass
27773 17:04:22.498641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass>
27774 17:04:22.499205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32 RESULT=pass
27776 17:04:22.549143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass>
27777 17:04:22.549720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_min_max RESULT=pass
27779 17:04:22.598765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass>
27780 17:04:22.599250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_used_default RESULT=pass
27782 17:04:22.649960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass>
27783 17:04:22.650427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_was_inherited RESULT=pass
27785 17:04:22.698676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass>
27786 17:04:22.699248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_vector_length_set_on_exec RESULT=pass
27788 17:04:22.743803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass
27790 17:04:22.744514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors RESULT=pass>
27791 17:04:22.789175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
27792 17:04:22.789599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
27794 17:04:22.838265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass>
27795 17:04:22.838692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_fork_test RESULT=pass
27797 17:04:22.877023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
27798 17:04:22.877580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
27800 17:04:22.926594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass
27802 17:04:22.927200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_16 RESULT=pass>
27803 17:04:22.978138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass>
27804 17:04:22.978608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_16 RESULT=pass
27806 17:04:23.029044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass>
27807 17:04:23.029582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_16 RESULT=pass
27809 17:04:23.068565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass>
27810 17:04:23.068953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_32 RESULT=pass
27812 17:04:23.114322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass>
27813 17:04:23.114744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_32 RESULT=pass
27815 17:04:23.158290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass>
27816 17:04:23.158709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_32 RESULT=pass
27818 17:04:23.202409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass>
27819 17:04:23.202848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_48 RESULT=pass
27821 17:04:23.249555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip>
27822 17:04:23.249992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_48 RESULT=skip
27824 17:04:23.290745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip>
27825 17:04:23.291145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_48 RESULT=skip
27827 17:04:23.331364 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass
27829 17:04:23.331841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_64 RESULT=pass>
27830 17:04:23.370941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass>
27831 17:04:23.371385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_64 RESULT=pass
27833 17:04:23.414183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass>
27834 17:04:23.414607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_64 RESULT=pass
27836 17:04:23.458941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass>
27837 17:04:23.459351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_80 RESULT=pass
27839 17:04:23.502679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip
27841 17:04:23.503116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_80 RESULT=skip>
27842 17:04:23.550459 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip
27844 17:04:23.550876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_80 RESULT=skip>
27845 17:04:23.593239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass>
27846 17:04:23.593615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_96 RESULT=pass
27848 17:04:23.641304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip>
27849 17:04:23.641687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_96 RESULT=skip
27851 17:04:23.689010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip>
27852 17:04:23.689422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_96 RESULT=skip
27854 17:04:23.735264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass
27856 17:04:23.735719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_112 RESULT=pass>
27857 17:04:23.779784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip
27859 17:04:23.780264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_112 RESULT=skip>
27860 17:04:23.818027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip>
27861 17:04:23.818607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_112 RESULT=skip
27863 17:04:23.869601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass>
27864 17:04:23.870043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_128 RESULT=pass
27866 17:04:23.913820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass>
27867 17:04:23.914204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_128 RESULT=pass
27869 17:04:23.956344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass>
27870 17:04:23.956741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_128 RESULT=pass
27872 17:04:23.993609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass>
27873 17:04:23.994015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_144 RESULT=pass
27875 17:04:24.036730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip>
27876 17:04:24.037156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_144 RESULT=skip
27878 17:04:24.081876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip>
27879 17:04:24.082247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_144 RESULT=skip
27881 17:04:24.125306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass>
27882 17:04:24.125779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_160 RESULT=pass
27884 17:04:24.167639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip
27886 17:04:24.168094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_160 RESULT=skip>
27887 17:04:24.206995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip>
27888 17:04:24.207424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_160 RESULT=skip
27890 17:04:24.248771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass>
27891 17:04:24.249218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_176 RESULT=pass
27893 17:04:24.288174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip>
27894 17:04:24.288629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_176 RESULT=skip
27896 17:04:24.326610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip>
27897 17:04:24.327052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_176 RESULT=skip
27899 17:04:24.368142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass
27901 17:04:24.368563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_192 RESULT=pass>
27902 17:04:24.417120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip>
27903 17:04:24.417682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_192 RESULT=skip
27905 17:04:24.464521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip
27907 17:04:24.465111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_192 RESULT=skip>
27908 17:04:24.510102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass>
27909 17:04:24.510593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_208 RESULT=pass
27911 17:04:24.558138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip
27913 17:04:24.558736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_208 RESULT=skip>
27914 17:04:24.601511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip>
27915 17:04:24.602071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_208 RESULT=skip
27917 17:04:24.646672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass>
27918 17:04:24.647063 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_224 RESULT=pass
27920 17:04:24.696709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip>
27921 17:04:24.697155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_224 RESULT=skip
27923 17:04:24.734128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip
27925 17:04:24.734592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_224 RESULT=skip>
27926 17:04:24.778573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass>
27927 17:04:24.778973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_240 RESULT=pass
27929 17:04:24.822387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip>
27930 17:04:24.822828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_240 RESULT=skip
27932 17:04:24.863827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip
27934 17:04:24.864258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_240 RESULT=skip>
27935 17:04:24.911026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass>
27936 17:04:24.911433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_256 RESULT=pass
27938 17:04:24.958443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass>
27939 17:04:24.958837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_256 RESULT=pass
27941 17:04:25.002536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass>
27942 17:04:25.002943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Data_match_for_VL_256 RESULT=pass
27944 17:04:25.045589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass
27946 17:04:25.046004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_272 RESULT=pass>
27947 17:04:25.093745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip>
27948 17:04:25.094283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_272 RESULT=skip
27950 17:04:25.137818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip>
27951 17:04:25.138282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_272 RESULT=skip
27953 17:04:25.183384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass>
27954 17:04:25.183824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_288 RESULT=pass
27956 17:04:25.233751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip>
27957 17:04:25.234298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_288 RESULT=skip
27959 17:04:25.281881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip>
27960 17:04:25.282315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_288 RESULT=skip
27962 17:04:25.330043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass
27964 17:04:25.330463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_304 RESULT=pass>
27965 17:04:25.367064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip>
27966 17:04:25.367460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_304 RESULT=skip
27968 17:04:25.404537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip
27970 17:04:25.404989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_304 RESULT=skip>
27971 17:04:25.442760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass>
27972 17:04:25.443209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_320 RESULT=pass
27974 17:04:25.480516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip>
27975 17:04:25.480996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_320 RESULT=skip
27977 17:04:25.526212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip
27979 17:04:25.526614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_320 RESULT=skip>
27980 17:04:25.569908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass
27982 17:04:25.570394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_336 RESULT=pass>
27983 17:04:25.614971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip>
27984 17:04:25.615393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_336 RESULT=skip
27986 17:04:25.661224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip
27988 17:04:25.661713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_336 RESULT=skip>
27989 17:04:25.705963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass>
27990 17:04:25.706361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_352 RESULT=pass
27992 17:04:25.747400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip>
27993 17:04:25.747852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_352 RESULT=skip
27995 17:04:25.801123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip
27997 17:04:25.801599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_352 RESULT=skip>
27998 17:04:25.857967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass>
27999 17:04:25.858510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_368 RESULT=pass
28001 17:04:25.915809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip
28003 17:04:25.916585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_368 RESULT=skip>
28004 17:04:25.960170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip>
28005 17:04:25.960584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_368 RESULT=skip
28007 17:04:26.000754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass
28009 17:04:26.001221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_384 RESULT=pass>
28010 17:04:26.049035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip>
28011 17:04:26.049475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_384 RESULT=skip
28013 17:04:26.093396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip>
28014 17:04:26.093828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_384 RESULT=skip
28016 17:04:26.132914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass>
28017 17:04:26.133380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_400 RESULT=pass
28019 17:04:26.173438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip
28021 17:04:26.173936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_400 RESULT=skip>
28022 17:04:26.218918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip>
28023 17:04:26.219347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_400 RESULT=skip
28025 17:04:26.265307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass>
28026 17:04:26.265686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_416 RESULT=pass
28028 17:04:26.313703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip>
28029 17:04:26.314108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_416 RESULT=skip
28031 17:04:26.353426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip>
28032 17:04:26.353842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_416 RESULT=skip
28034 17:04:26.393327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass>
28035 17:04:26.393766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_432 RESULT=pass
28037 17:04:26.441550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip>
28038 17:04:26.441984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_432 RESULT=skip
28040 17:04:26.485404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip>
28041 17:04:26.485820 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_432 RESULT=skip
28043 17:04:26.526240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass>
28044 17:04:26.526682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_448 RESULT=pass
28046 17:04:26.571477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip
28048 17:04:26.572233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_448 RESULT=skip>
28049 17:04:26.622094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip
28051 17:04:26.622558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_448 RESULT=skip>
28052 17:04:26.669183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass>
28053 17:04:26.669603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_464 RESULT=pass
28055 17:04:26.711869 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip
28057 17:04:26.712458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_464 RESULT=skip>
28058 17:04:26.762291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip>
28059 17:04:26.762833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_464 RESULT=skip
28061 17:04:26.805956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass
28063 17:04:26.806432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_480 RESULT=pass>
28064 17:04:26.858450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip>
28065 17:04:26.858871 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_480 RESULT=skip
28067 17:04:26.898017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip
28069 17:04:26.898682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_480 RESULT=skip>
28070 17:04:26.945799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass
28072 17:04:26.946257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_496 RESULT=pass>
28073 17:04:26.994467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip>
28074 17:04:26.994909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_496 RESULT=skip
28076 17:04:27.033845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip>
28077 17:04:27.034268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_496 RESULT=skip
28079 17:04:27.073312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass
28081 17:04:27.074086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_512 RESULT=pass>
28082 17:04:27.117096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip
28084 17:04:27.117571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_512 RESULT=skip>
28085 17:04:27.161077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip
28087 17:04:27.161496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_512 RESULT=skip>
28088 17:04:27.199138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass>
28089 17:04:27.199551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_528 RESULT=pass
28091 17:04:27.239002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip
28093 17:04:27.239459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_528 RESULT=skip>
28094 17:04:27.278554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip
28096 17:04:27.279037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_528 RESULT=skip>
28097 17:04:27.318385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass
28099 17:04:27.318862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_544 RESULT=pass>
28100 17:04:27.357834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip>
28101 17:04:27.358212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_544 RESULT=skip
28103 17:04:27.421152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip>
28104 17:04:27.421688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_544 RESULT=skip
28106 17:04:27.466936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass
28108 17:04:27.467639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_560 RESULT=pass>
28109 17:04:27.508381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip>
28110 17:04:27.508760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_560 RESULT=skip
28112 17:04:27.550499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip>
28113 17:04:27.550952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_560 RESULT=skip
28115 17:04:27.589667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass>
28116 17:04:27.590111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_576 RESULT=pass
28118 17:04:27.625210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip>
28119 17:04:27.625618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_576 RESULT=skip
28121 17:04:27.662965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip>
28122 17:04:27.663390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_576 RESULT=skip
28124 17:04:27.707817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass
28126 17:04:27.708208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_592 RESULT=pass>
28127 17:04:27.748288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip>
28128 17:04:27.748698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_592 RESULT=skip
28130 17:04:27.791300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip
28132 17:04:27.791826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_592 RESULT=skip>
28133 17:04:27.835161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass>
28134 17:04:27.835540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_608 RESULT=pass
28136 17:04:27.882246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip>
28137 17:04:27.882636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_608 RESULT=skip
28139 17:04:27.932489 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip
28141 17:04:27.932917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_608 RESULT=skip>
28142 17:04:27.973542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass>
28143 17:04:27.973938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_624 RESULT=pass
28145 17:04:28.020889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip
28147 17:04:28.021368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_624 RESULT=skip>
28148 17:04:28.064798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip>
28149 17:04:28.065263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_624 RESULT=skip
28151 17:04:28.105939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass>
28152 17:04:28.106512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_640 RESULT=pass
28154 17:04:28.147855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip
28156 17:04:28.148602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_640 RESULT=skip>
28157 17:04:28.198741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip>
28158 17:04:28.199284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_640 RESULT=skip
28160 17:04:28.245222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass
28162 17:04:28.245705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_656 RESULT=pass>
28163 17:04:28.283061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip>
28164 17:04:28.283500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_656 RESULT=skip
28166 17:04:28.326539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip>
28167 17:04:28.326997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_656 RESULT=skip
28169 17:04:28.369712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass
28171 17:04:28.370134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_672 RESULT=pass>
28172 17:04:28.413692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip>
28173 17:04:28.414127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_672 RESULT=skip
28175 17:04:28.457494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip>
28176 17:04:28.457919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_672 RESULT=skip
28178 17:04:28.505112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass
28180 17:04:28.505581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_688 RESULT=pass>
28181 17:04:28.562390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip>
28182 17:04:28.562795 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_688 RESULT=skip
28184 17:04:28.613327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip>
28185 17:04:28.613734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_688 RESULT=skip
28187 17:04:28.658314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass
28189 17:04:28.658776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_704 RESULT=pass>
28190 17:04:28.700576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip>
28191 17:04:28.701007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_704 RESULT=skip
28193 17:04:28.742076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip>
28194 17:04:28.744182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_704 RESULT=skip
28196 17:04:28.794607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass>
28197 17:04:28.794983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_720 RESULT=pass
28199 17:04:28.838334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip
28201 17:04:28.838821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_720 RESULT=skip>
28202 17:04:28.885964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip
28204 17:04:28.886442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_720 RESULT=skip>
28205 17:04:28.922484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass>
28206 17:04:28.922906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_736 RESULT=pass
28208 17:04:28.959217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip
28210 17:04:28.959699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_736 RESULT=skip>
28211 17:04:28.997162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip
28213 17:04:28.997657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_736 RESULT=skip>
28214 17:04:29.045611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass>
28215 17:04:29.046030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_752 RESULT=pass
28217 17:04:29.093585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip>
28218 17:04:29.094166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_752 RESULT=skip
28220 17:04:29.142483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip>
28221 17:04:29.142956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_752 RESULT=skip
28223 17:04:29.194058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass>
28224 17:04:29.194592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_768 RESULT=pass
28226 17:04:29.243445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip>
28227 17:04:29.243942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_768 RESULT=skip
28229 17:04:29.282173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip>
28230 17:04:29.282664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_768 RESULT=skip
28232 17:04:29.329016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass>
28233 17:04:29.329595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_784 RESULT=pass
28235 17:04:29.374349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip>
28236 17:04:29.374919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_784 RESULT=skip
28238 17:04:29.416747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip>
28239 17:04:29.417310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_784 RESULT=skip
28241 17:04:29.461229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass
28243 17:04:29.461760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_800 RESULT=pass>
28244 17:04:29.505806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip>
28245 17:04:29.506224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_800 RESULT=skip
28247 17:04:29.545014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip>
28248 17:04:29.545437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_800 RESULT=skip
28250 17:04:29.590053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass>
28251 17:04:29.590449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_816 RESULT=pass
28253 17:04:29.633705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip>
28254 17:04:29.634113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_816 RESULT=skip
28256 17:04:29.671474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip>
28257 17:04:29.671903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_816 RESULT=skip
28259 17:04:29.710463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass>
28260 17:04:29.710886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_832 RESULT=pass
28262 17:04:29.753073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip>
28263 17:04:29.753491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_832 RESULT=skip
28265 17:04:29.805809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip
28267 17:04:29.806519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_832 RESULT=skip>
28268 17:04:29.842898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass>
28269 17:04:29.843473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_848 RESULT=pass
28271 17:04:29.886032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip>
28272 17:04:29.886414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_848 RESULT=skip
28274 17:04:29.926017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip>
28275 17:04:29.926435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_848 RESULT=skip
28277 17:04:29.966204 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass
28279 17:04:29.966651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_864 RESULT=pass>
28280 17:04:30.014603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip
28282 17:04:30.015086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_864 RESULT=skip>
28283 17:04:30.051097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip>
28284 17:04:30.051555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_864 RESULT=skip
28286 17:04:30.089027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass>
28287 17:04:30.089480 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_880 RESULT=pass
28289 17:04:30.126164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip>
28290 17:04:30.126615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_880 RESULT=skip
28292 17:04:30.173913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip>
28293 17:04:30.174339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_880 RESULT=skip
28295 17:04:30.216831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass>
28296 17:04:30.217243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_896 RESULT=pass
28298 17:04:30.261821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip>
28299 17:04:30.262214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_896 RESULT=skip
28301 17:04:30.305171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip
28303 17:04:30.305609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_896 RESULT=skip>
28304 17:04:30.348502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass>
28305 17:04:30.348947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_912 RESULT=pass
28307 17:04:30.392416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip>
28308 17:04:30.392877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_912 RESULT=skip
28310 17:04:30.438566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip>
28311 17:04:30.439024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_912 RESULT=skip
28313 17:04:30.487477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass>
28314 17:04:30.487889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_928 RESULT=pass
28316 17:04:30.533871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip>
28317 17:04:30.534293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_928 RESULT=skip
28319 17:04:30.579360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip>
28320 17:04:30.579760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_928 RESULT=skip
28322 17:04:30.620051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass
28324 17:04:30.620516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_944 RESULT=pass>
28325 17:04:30.663485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip>
28326 17:04:30.663916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_944 RESULT=skip
28328 17:04:30.711382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip>
28329 17:04:30.711870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_944 RESULT=skip
28331 17:04:30.756390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass
28333 17:04:30.756872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_960 RESULT=pass>
28334 17:04:30.799456 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip
28336 17:04:30.799872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_960 RESULT=skip>
28337 17:04:30.844623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip>
28338 17:04:30.845133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_960 RESULT=skip
28340 17:04:30.894900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass
28342 17:04:30.895540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_976 RESULT=pass>
28343 17:04:30.938367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip>
28344 17:04:30.938798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_976 RESULT=skip
28346 17:04:30.982257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip>
28347 17:04:30.982661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_976 RESULT=skip
28349 17:04:31.025237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass
28351 17:04:31.025932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_992 RESULT=pass>
28352 17:04:31.069740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip>
28353 17:04:31.070197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_992 RESULT=skip
28355 17:04:31.115805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip
28357 17:04:31.116246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_992 RESULT=skip>
28358 17:04:31.164626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass>
28359 17:04:31.165056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1008 RESULT=pass
28361 17:04:31.212939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip>
28362 17:04:31.213358 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1008 RESULT=skip
28364 17:04:31.255210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip>
28365 17:04:31.255639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1008 RESULT=skip
28367 17:04:31.297091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass
28369 17:04:31.297516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1024 RESULT=pass>
28370 17:04:31.340471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip
28372 17:04:31.340928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1024 RESULT=skip>
28373 17:04:31.387044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip>
28374 17:04:31.387501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1024 RESULT=skip
28376 17:04:31.429315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass>
28377 17:04:31.429683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1040 RESULT=pass
28379 17:04:31.475201 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip
28381 17:04:31.475697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1040 RESULT=skip>
28382 17:04:31.516760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip>
28383 17:04:31.517159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1040 RESULT=skip
28385 17:04:31.565618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass
28387 17:04:31.566431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1056 RESULT=pass>
28388 17:04:31.614036 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip
28390 17:04:31.614739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1056 RESULT=skip>
28391 17:04:31.654351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip
28393 17:04:31.654832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1056 RESULT=skip>
28394 17:04:31.704642 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass
28396 17:04:31.705105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1072 RESULT=pass>
28397 17:04:31.754185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip>
28398 17:04:31.754612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1072 RESULT=skip
28400 17:04:31.800693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip
28402 17:04:31.801121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1072 RESULT=skip>
28403 17:04:31.854497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass
28405 17:04:31.854948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1088 RESULT=pass>
28406 17:04:31.908731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip>
28407 17:04:31.909162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1088 RESULT=skip
28409 17:04:31.960660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip>
28410 17:04:31.961104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1088 RESULT=skip
28412 17:04:32.014732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass>
28413 17:04:32.015179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1104 RESULT=pass
28415 17:04:32.067427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip>
28416 17:04:32.067990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1104 RESULT=skip
28418 17:04:32.114818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip>
28419 17:04:32.115231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1104 RESULT=skip
28421 17:04:32.158778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass
28423 17:04:32.159262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1120 RESULT=pass>
28424 17:04:32.215253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip>
28425 17:04:32.215696 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1120 RESULT=skip
28427 17:04:32.262921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip
28429 17:04:32.263536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1120 RESULT=skip>
28430 17:04:32.315106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass>
28431 17:04:32.315508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1136 RESULT=pass
28433 17:04:32.365138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip>
28434 17:04:32.365581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1136 RESULT=skip
28436 17:04:32.415582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip>
28437 17:04:32.416134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1136 RESULT=skip
28439 17:04:32.466281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass>
28440 17:04:32.466827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1152 RESULT=pass
28442 17:04:32.511897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip
28444 17:04:32.512389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1152 RESULT=skip>
28445 17:04:32.574165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip
28447 17:04:32.574759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1152 RESULT=skip>
28448 17:04:32.620920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass>
28449 17:04:32.621352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1168 RESULT=pass
28451 17:04:32.661778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip>
28452 17:04:32.662205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1168 RESULT=skip
28454 17:04:32.705180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip>
28455 17:04:32.705592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1168 RESULT=skip
28457 17:04:32.743228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass>
28458 17:04:32.743686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1184 RESULT=pass
28460 17:04:32.783424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip
28462 17:04:32.783897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1184 RESULT=skip>
28463 17:04:32.821524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip
28465 17:04:32.821894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1184 RESULT=skip>
28466 17:04:32.861307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass>
28467 17:04:32.861754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1200 RESULT=pass
28469 17:04:32.902809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip>
28470 17:04:32.903287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1200 RESULT=skip
28472 17:04:32.943936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip
28474 17:04:32.944801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1200 RESULT=skip>
28475 17:04:32.985491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass>
28476 17:04:32.986017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1216 RESULT=pass
28478 17:04:33.026769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip>
28479 17:04:33.027182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1216 RESULT=skip
28481 17:04:33.069078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip>
28482 17:04:33.069491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1216 RESULT=skip
28484 17:04:33.113737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass>
28485 17:04:33.114271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1232 RESULT=pass
28487 17:04:33.153946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip
28489 17:04:33.154397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1232 RESULT=skip>
28490 17:04:33.199891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip
28492 17:04:33.200289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1232 RESULT=skip>
28493 17:04:33.243261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass>
28494 17:04:33.243704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1248 RESULT=pass
28496 17:04:33.282935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip>
28497 17:04:33.283370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1248 RESULT=skip
28499 17:04:33.320914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip>
28500 17:04:33.321329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1248 RESULT=skip
28502 17:04:33.364995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass>
28503 17:04:33.365455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1264 RESULT=pass
28505 17:04:33.406400 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip
28507 17:04:33.407130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1264 RESULT=skip>
28508 17:04:33.449681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip>
28509 17:04:33.450197 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1264 RESULT=skip
28511 17:04:33.493478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass
28513 17:04:33.493975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1280 RESULT=pass>
28514 17:04:33.542303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip>
28515 17:04:33.542699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1280 RESULT=skip
28517 17:04:33.589900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip
28519 17:04:33.590322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1280 RESULT=skip>
28520 17:04:33.637230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass>
28521 17:04:33.637687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1296 RESULT=pass
28523 17:04:33.686028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip
28525 17:04:33.686494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1296 RESULT=skip>
28526 17:04:33.729370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip>
28527 17:04:33.729862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1296 RESULT=skip
28529 17:04:33.778944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass
28531 17:04:33.779745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1312 RESULT=pass>
28532 17:04:33.824828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip
28534 17:04:33.825267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1312 RESULT=skip>
28535 17:04:33.873722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip
28537 17:04:33.874267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1312 RESULT=skip>
28538 17:04:33.932904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass
28540 17:04:33.933313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1328 RESULT=pass>
28541 17:04:33.989456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip>
28542 17:04:33.989885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1328 RESULT=skip
28544 17:04:34.038344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip>
28545 17:04:34.038799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1328 RESULT=skip
28547 17:04:34.082655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass>
28548 17:04:34.083103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1344 RESULT=pass
28550 17:04:34.124752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip>
28551 17:04:34.125184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1344 RESULT=skip
28553 17:04:34.173673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip>
28554 17:04:34.174105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1344 RESULT=skip
28556 17:04:34.216438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass>
28557 17:04:34.216859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1360 RESULT=pass
28559 17:04:34.261952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip>
28560 17:04:34.262385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1360 RESULT=skip
28562 17:04:34.304965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip>
28563 17:04:34.305516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1360 RESULT=skip
28565 17:04:34.345129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass>
28566 17:04:34.345583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1376 RESULT=pass
28568 17:04:34.386546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip>
28569 17:04:34.387072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1376 RESULT=skip
28571 17:04:34.431202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip
28573 17:04:34.431685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1376 RESULT=skip>
28574 17:04:34.479452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass>
28575 17:04:34.479867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1392 RESULT=pass
28577 17:04:34.525739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip>
28578 17:04:34.526182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1392 RESULT=skip
28580 17:04:34.578970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip>
28581 17:04:34.579422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1392 RESULT=skip
28583 17:04:34.630972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass>
28584 17:04:34.631596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1408 RESULT=pass
28586 17:04:34.681694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip>
28587 17:04:34.682194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1408 RESULT=skip
28589 17:04:34.731415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip>
28590 17:04:34.731874 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1408 RESULT=skip
28592 17:04:34.781059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass>
28593 17:04:34.781511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1424 RESULT=pass
28595 17:04:34.830676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip>
28596 17:04:34.831142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1424 RESULT=skip
28598 17:04:34.871549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip>
28599 17:04:34.871985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1424 RESULT=skip
28601 17:04:34.920001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass>
28602 17:04:34.920368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1440 RESULT=pass
28604 17:04:34.963207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip>
28605 17:04:34.963666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1440 RESULT=skip
28607 17:04:35.006298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip>
28608 17:04:35.006755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1440 RESULT=skip
28610 17:04:35.054677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass>
28611 17:04:35.055115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1456 RESULT=pass
28613 17:04:35.105282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip>
28614 17:04:35.105710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1456 RESULT=skip
28616 17:04:35.145392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip>
28617 17:04:35.145810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1456 RESULT=skip
28619 17:04:35.189152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass
28621 17:04:35.189628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1472 RESULT=pass>
28622 17:04:35.233801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip
28624 17:04:35.234242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1472 RESULT=skip>
28625 17:04:35.281257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip>
28626 17:04:35.281675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1472 RESULT=skip
28628 17:04:35.325283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass
28630 17:04:35.325764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1488 RESULT=pass>
28631 17:04:35.373429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip>
28632 17:04:35.373902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1488 RESULT=skip
28634 17:04:35.417143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip>
28635 17:04:35.417543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1488 RESULT=skip
28637 17:04:35.465428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass>
28638 17:04:35.465880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1504 RESULT=pass
28640 17:04:35.509702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip>
28641 17:04:35.510078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1504 RESULT=skip
28643 17:04:35.555146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip>
28644 17:04:35.555654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1504 RESULT=skip
28646 17:04:35.590871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass>
28647 17:04:35.591317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1520 RESULT=pass
28649 17:04:35.629999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip
28651 17:04:35.630457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1520 RESULT=skip>
28652 17:04:35.675395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip>
28653 17:04:35.675961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1520 RESULT=skip
28655 17:04:35.711674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass
28657 17:04:35.712425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1536 RESULT=pass>
28658 17:04:35.747066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip>
28659 17:04:35.747545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1536 RESULT=skip
28661 17:04:35.783156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip>
28662 17:04:35.783593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1536 RESULT=skip
28664 17:04:35.824978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass>
28665 17:04:35.825374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1552 RESULT=pass
28667 17:04:35.865682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip
28669 17:04:35.866143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1552 RESULT=skip>
28670 17:04:35.909942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip>
28671 17:04:35.910430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1552 RESULT=skip
28673 17:04:35.956622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass
28675 17:04:35.957121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1568 RESULT=pass>
28676 17:04:35.993816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip>
28677 17:04:35.994217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1568 RESULT=skip
28679 17:04:36.029698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip
28681 17:04:36.030037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1568 RESULT=skip>
28682 17:04:36.069125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass>
28683 17:04:36.069512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1584 RESULT=pass
28685 17:04:36.119205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip
28687 17:04:36.119666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1584 RESULT=skip>
28688 17:04:36.160160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip
28690 17:04:36.160575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1584 RESULT=skip>
28691 17:04:36.202329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass>
28692 17:04:36.202716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1600 RESULT=pass
28694 17:04:36.242472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip>
28695 17:04:36.242911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1600 RESULT=skip
28697 17:04:36.279571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip>
28698 17:04:36.280064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1600 RESULT=skip
28700 17:04:36.320628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass>
28701 17:04:36.321133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1616 RESULT=pass
28703 17:04:36.362453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip>
28704 17:04:36.362963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1616 RESULT=skip
28706 17:04:36.407070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip>
28707 17:04:36.407510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1616 RESULT=skip
28709 17:04:36.460534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass>
28710 17:04:36.460974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1632 RESULT=pass
28712 17:04:36.500837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip>
28713 17:04:36.501259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1632 RESULT=skip
28715 17:04:36.552274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip>
28716 17:04:36.552832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1632 RESULT=skip
28718 17:04:36.598918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass>
28719 17:04:36.599495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1648 RESULT=pass
28721 17:04:36.655231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip>
28722 17:04:36.655635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1648 RESULT=skip
28724 17:04:36.694607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip>
28725 17:04:36.695037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1648 RESULT=skip
28727 17:04:36.738319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass
28729 17:04:36.738765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1664 RESULT=pass>
28730 17:04:36.781585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip>
28731 17:04:36.782018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1664 RESULT=skip
28733 17:04:36.834130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip>
28734 17:04:36.834702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1664 RESULT=skip
28736 17:04:36.872370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass>
28737 17:04:36.872860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1680 RESULT=pass
28739 17:04:36.913610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip
28741 17:04:36.914314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1680 RESULT=skip>
28742 17:04:36.970214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip>
28743 17:04:36.970604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1680 RESULT=skip
28745 17:04:37.019074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass>
28746 17:04:37.019611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1696 RESULT=pass
28748 17:04:37.065514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip>
28749 17:04:37.065921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1696 RESULT=skip
28751 17:04:37.109490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip
28753 17:04:37.109876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1696 RESULT=skip>
28754 17:04:37.153063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass>
28755 17:04:37.153516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1712 RESULT=pass
28757 17:04:37.198934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip
28759 17:04:37.199414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1712 RESULT=skip>
28760 17:04:37.247975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip
28762 17:04:37.248561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1712 RESULT=skip>
28763 17:04:37.295347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass
28765 17:04:37.296060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1728 RESULT=pass>
28766 17:04:37.341953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip>
28767 17:04:37.342394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1728 RESULT=skip
28769 17:04:37.377179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip>
28770 17:04:37.377613 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1728 RESULT=skip
28772 17:04:37.422680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass
28774 17:04:37.423426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1744 RESULT=pass>
28775 17:04:37.468723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip>
28776 17:04:37.469331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1744 RESULT=skip
28778 17:04:37.505639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip
28780 17:04:37.506156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1744 RESULT=skip>
28781 17:04:37.542587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass>
28782 17:04:37.543153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1760 RESULT=pass
28784 17:04:37.581707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip
28786 17:04:37.582120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1760 RESULT=skip>
28787 17:04:37.623836 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip
28789 17:04:37.624374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1760 RESULT=skip>
28790 17:04:37.694666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass>
28791 17:04:37.695093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1776 RESULT=pass
28793 17:04:37.734991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip>
28794 17:04:37.735440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1776 RESULT=skip
28796 17:04:37.773919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip>
28797 17:04:37.774295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1776 RESULT=skip
28799 17:04:37.819521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass>
28800 17:04:37.819927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1792 RESULT=pass
28802 17:04:37.860390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip
28804 17:04:37.860775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1792 RESULT=skip>
28805 17:04:37.896820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip>
28806 17:04:37.897275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1792 RESULT=skip
28808 17:04:37.941054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass
28810 17:04:37.941722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1808 RESULT=pass>
28811 17:04:37.990172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip>
28812 17:04:37.990653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1808 RESULT=skip
28814 17:04:38.037517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip>
28815 17:04:38.037943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1808 RESULT=skip
28817 17:04:38.076661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass
28819 17:04:38.077042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1824 RESULT=pass>
28820 17:04:38.118054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip
28822 17:04:38.118531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1824 RESULT=skip>
28823 17:04:38.160474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip
28825 17:04:38.161080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1824 RESULT=skip>
28826 17:04:38.197771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass
28828 17:04:38.198056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1840 RESULT=pass>
28829 17:04:38.238284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip>
28830 17:04:38.238685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1840 RESULT=skip
28832 17:04:38.279761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip
28834 17:04:38.280119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1840 RESULT=skip>
28835 17:04:38.321672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass>
28836 17:04:38.322054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1856 RESULT=pass
28838 17:04:38.363028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip>
28839 17:04:38.363335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1856 RESULT=skip
28841 17:04:38.403032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip>
28842 17:04:38.403490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1856 RESULT=skip
28844 17:04:38.445038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass
28846 17:04:38.445495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1872 RESULT=pass>
28847 17:04:38.485620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip>
28848 17:04:38.485934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1872 RESULT=skip
28850 17:04:38.527292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip>
28851 17:04:38.527671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1872 RESULT=skip
28853 17:04:38.585141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass>
28854 17:04:38.585643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1888 RESULT=pass
28856 17:04:38.623034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip
28858 17:04:38.623579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1888 RESULT=skip>
28859 17:04:38.661775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip>
28860 17:04:38.662189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1888 RESULT=skip
28862 17:04:38.694859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass
28864 17:04:38.695320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1904 RESULT=pass>
28865 17:04:38.726716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip>
28866 17:04:38.727284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1904 RESULT=skip
28868 17:04:38.761595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip>
28869 17:04:38.762019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1904 RESULT=skip
28871 17:04:38.801241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass>
28872 17:04:38.801685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1920 RESULT=pass
28874 17:04:38.838101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip>
28875 17:04:38.838547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1920 RESULT=skip
28877 17:04:38.879549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip
28879 17:04:38.880048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1920 RESULT=skip>
28880 17:04:38.915487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass>
28881 17:04:38.916124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1936 RESULT=pass
28883 17:04:38.953225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip
28885 17:04:38.953603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1936 RESULT=skip>
28886 17:04:38.995079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip
28888 17:04:38.995540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1936 RESULT=skip>
28889 17:04:39.036416 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass
28891 17:04:39.036805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1952 RESULT=pass>
28892 17:04:39.079462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip>
28893 17:04:39.079826 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1952 RESULT=skip
28895 17:04:39.120975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip>
28896 17:04:39.121335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1952 RESULT=skip
28898 17:04:39.165884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass>
28899 17:04:39.166329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1968 RESULT=pass
28901 17:04:39.209049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip
28903 17:04:39.209787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1968 RESULT=skip>
28904 17:04:39.254025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip>
28905 17:04:39.254508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1968 RESULT=skip
28907 17:04:39.298093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass
28909 17:04:39.298534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_1984 RESULT=pass>
28910 17:04:39.336807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip
28912 17:04:39.337381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_1984 RESULT=skip>
28913 17:04:39.379661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip
28915 17:04:39.380209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_1984 RESULT=skip>
28916 17:04:39.415238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass>
28917 17:04:39.415691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2000 RESULT=pass
28919 17:04:39.449999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip>
28920 17:04:39.450441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2000 RESULT=skip
28922 17:04:39.494573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip
28924 17:04:39.495107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2000 RESULT=skip>
28925 17:04:39.540235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass>
28926 17:04:39.540624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2016 RESULT=pass
28928 17:04:39.579002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip>
28929 17:04:39.579503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2016 RESULT=skip
28931 17:04:39.618981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip
28933 17:04:39.619577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2016 RESULT=skip>
28934 17:04:39.664950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass>
28935 17:04:39.665423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2032 RESULT=pass
28937 17:04:39.709712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip
28939 17:04:39.710257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2032 RESULT=skip>
28940 17:04:39.748223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip
28942 17:04:39.748753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2032 RESULT=skip>
28943 17:04:39.786961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass>
28944 17:04:39.787405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2048 RESULT=pass
28946 17:04:39.825051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip>
28947 17:04:39.825471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2048 RESULT=skip
28949 17:04:39.864810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip>
28950 17:04:39.865222 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2048 RESULT=skip
28952 17:04:39.899219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass>
28953 17:04:39.899629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2064 RESULT=pass
28955 17:04:39.941817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip
28957 17:04:39.942543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2064 RESULT=skip>
28958 17:04:39.996898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip>
28959 17:04:39.997395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2064 RESULT=skip
28961 17:04:40.045531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass>
28962 17:04:40.045984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2080 RESULT=pass
28964 17:04:40.088957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip>
28965 17:04:40.089378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2080 RESULT=skip
28967 17:04:40.130097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip>
28968 17:04:40.130560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2080 RESULT=skip
28970 17:04:40.173694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass>
28971 17:04:40.174137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2096 RESULT=pass
28973 17:04:40.211727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip
28975 17:04:40.212215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2096 RESULT=skip>
28976 17:04:40.250542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip>
28977 17:04:40.250987 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2096 RESULT=skip
28979 17:04:40.289207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass>
28980 17:04:40.289627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2112 RESULT=pass
28982 17:04:40.333808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip
28984 17:04:40.334438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2112 RESULT=skip>
28985 17:04:40.381998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip>
28986 17:04:40.382460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2112 RESULT=skip
28988 17:04:40.431522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass>
28989 17:04:40.431954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2128 RESULT=pass
28991 17:04:40.468237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip>
28992 17:04:40.468667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2128 RESULT=skip
28994 17:04:40.503131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip
28996 17:04:40.503844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2128 RESULT=skip>
28997 17:04:40.550133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass>
28998 17:04:40.550664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2144 RESULT=pass
29000 17:04:40.585459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip>
29001 17:04:40.585853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2144 RESULT=skip
29003 17:04:40.624626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip>
29004 17:04:40.625048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2144 RESULT=skip
29006 17:04:40.666752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass
29008 17:04:40.667311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2160 RESULT=pass>
29009 17:04:40.717694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip
29011 17:04:40.718106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2160 RESULT=skip>
29012 17:04:40.765488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip>
29013 17:04:40.765922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2160 RESULT=skip
29015 17:04:40.806182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass>
29016 17:04:40.806587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2176 RESULT=pass
29018 17:04:40.845265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip>
29019 17:04:40.845695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2176 RESULT=skip
29021 17:04:40.892883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip>
29022 17:04:40.893272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2176 RESULT=skip
29024 17:04:40.936670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass>
29025 17:04:40.937047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2192 RESULT=pass
29027 17:04:40.975093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip
29029 17:04:40.975566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2192 RESULT=skip>
29030 17:04:41.010952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip
29032 17:04:41.011488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2192 RESULT=skip>
29033 17:04:41.045615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass
29035 17:04:41.046393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2208 RESULT=pass>
29036 17:04:41.079151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip>
29037 17:04:41.079629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2208 RESULT=skip
29039 17:04:41.113005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip
29041 17:04:41.113601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2208 RESULT=skip>
29042 17:04:41.145027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass>
29043 17:04:41.145465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2224 RESULT=pass
29045 17:04:41.178111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip
29047 17:04:41.178671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2224 RESULT=skip>
29048 17:04:41.210651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip>
29049 17:04:41.211108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2224 RESULT=skip
29051 17:04:41.242161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass
29053 17:04:41.242704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2240 RESULT=pass>
29054 17:04:41.274934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip>
29055 17:04:41.275414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2240 RESULT=skip
29057 17:04:41.309822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip
29059 17:04:41.310303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2240 RESULT=skip>
29060 17:04:41.346795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass>
29061 17:04:41.347242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2256 RESULT=pass
29063 17:04:41.384628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip>
29064 17:04:41.385053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2256 RESULT=skip
29066 17:04:41.419355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip>
29067 17:04:41.419784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2256 RESULT=skip
29069 17:04:41.455217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass
29071 17:04:41.455694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2272 RESULT=pass>
29072 17:04:41.492450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip
29074 17:04:41.493067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2272 RESULT=skip>
29075 17:04:41.527424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip>
29076 17:04:41.527847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2272 RESULT=skip
29078 17:04:41.567241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass>
29079 17:04:41.567668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2288 RESULT=pass
29081 17:04:41.606430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip>
29082 17:04:41.606834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2288 RESULT=skip
29084 17:04:41.645885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip>
29085 17:04:41.646312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2288 RESULT=skip
29087 17:04:41.685644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass>
29088 17:04:41.686039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2304 RESULT=pass
29090 17:04:41.730959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip
29092 17:04:41.731344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2304 RESULT=skip>
29093 17:04:41.766313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip>
29094 17:04:41.766739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2304 RESULT=skip
29096 17:04:41.800911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass
29098 17:04:41.801515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2320 RESULT=pass>
29099 17:04:41.853709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip
29101 17:04:41.854079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2320 RESULT=skip>
29102 17:04:41.886834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip>
29103 17:04:41.887319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2320 RESULT=skip
29105 17:04:41.921287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass
29107 17:04:41.921986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2336 RESULT=pass>
29108 17:04:41.955343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip
29110 17:04:41.956089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2336 RESULT=skip>
29111 17:04:41.989208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip>
29112 17:04:41.989607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2336 RESULT=skip
29114 17:04:42.023852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass
29116 17:04:42.024371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2352 RESULT=pass>
29117 17:04:42.060053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip>
29118 17:04:42.060466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2352 RESULT=skip
29120 17:04:42.095453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip
29122 17:04:42.095834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2352 RESULT=skip>
29123 17:04:42.131045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass>
29124 17:04:42.131395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2368 RESULT=pass
29126 17:04:42.166893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip
29128 17:04:42.167619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2368 RESULT=skip>
29129 17:04:42.206411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip>
29130 17:04:42.206945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2368 RESULT=skip
29132 17:04:42.244366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass>
29133 17:04:42.244831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2384 RESULT=pass
29135 17:04:42.276780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip
29137 17:04:42.277241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2384 RESULT=skip>
29138 17:04:42.310402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip>
29139 17:04:42.310817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2384 RESULT=skip
29141 17:04:42.344517 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass
29143 17:04:42.344970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2400 RESULT=pass>
29144 17:04:42.379503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip
29146 17:04:42.379971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2400 RESULT=skip>
29147 17:04:42.412429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip
29149 17:04:42.412880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2400 RESULT=skip>
29150 17:04:42.443730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass
29152 17:04:42.444186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2416 RESULT=pass>
29153 17:04:42.476820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip>
29154 17:04:42.477336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2416 RESULT=skip
29156 17:04:42.510909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip
29158 17:04:42.511555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2416 RESULT=skip>
29159 17:04:42.544493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass>
29160 17:04:42.544921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2432 RESULT=pass
29162 17:04:42.578042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip
29164 17:04:42.578498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2432 RESULT=skip>
29165 17:04:42.611018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip
29167 17:04:42.611472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2432 RESULT=skip>
29168 17:04:42.643011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass>
29169 17:04:42.643488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2448 RESULT=pass
29171 17:04:42.674755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip
29173 17:04:42.675321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2448 RESULT=skip>
29174 17:04:42.706114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip
29176 17:04:42.706685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2448 RESULT=skip>
29177 17:04:42.738824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass>
29178 17:04:42.739307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2464 RESULT=pass
29180 17:04:42.787856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip>
29181 17:04:42.788339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2464 RESULT=skip
29183 17:04:42.821294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip>
29184 17:04:42.821687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2464 RESULT=skip
29186 17:04:42.857419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass
29188 17:04:42.857885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2480 RESULT=pass>
29189 17:04:42.891928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip
29191 17:04:42.892580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2480 RESULT=skip>
29192 17:04:42.927916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip
29194 17:04:42.928504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2480 RESULT=skip>
29195 17:04:42.961983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass>
29196 17:04:42.962472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2496 RESULT=pass
29198 17:04:42.994974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip>
29199 17:04:42.995474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2496 RESULT=skip
29201 17:04:43.031696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip>
29202 17:04:43.032256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2496 RESULT=skip
29204 17:04:43.072655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass>
29205 17:04:43.073056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2512 RESULT=pass
29207 17:04:43.108428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip>
29208 17:04:43.108792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2512 RESULT=skip
29210 17:04:43.141306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip>
29211 17:04:43.141682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2512 RESULT=skip
29213 17:04:43.176723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass>
29214 17:04:43.177274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2528 RESULT=pass
29216 17:04:43.218940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip>
29217 17:04:43.219417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2528 RESULT=skip
29219 17:04:43.253474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip
29221 17:04:43.254056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2528 RESULT=skip>
29222 17:04:43.286918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass
29224 17:04:43.287298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2544 RESULT=pass>
29225 17:04:43.319404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip
29227 17:04:43.320016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2544 RESULT=skip>
29228 17:04:43.353189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip
29230 17:04:43.353794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2544 RESULT=skip>
29231 17:04:43.385966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass>
29232 17:04:43.386433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2560 RESULT=pass
29234 17:04:43.419107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip>
29235 17:04:43.419591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2560 RESULT=skip
29237 17:04:43.453558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip>
29238 17:04:43.454039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2560 RESULT=skip
29240 17:04:43.486506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass>
29241 17:04:43.486981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2576 RESULT=pass
29243 17:04:43.520030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip
29245 17:04:43.520789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2576 RESULT=skip>
29246 17:04:43.554311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip
29248 17:04:43.555013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2576 RESULT=skip>
29249 17:04:43.587105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass>
29250 17:04:43.587596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2592 RESULT=pass
29252 17:04:43.620256 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip
29254 17:04:43.620855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2592 RESULT=skip>
29255 17:04:43.652667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip>
29256 17:04:43.653148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2592 RESULT=skip
29258 17:04:43.685689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass>
29259 17:04:43.686110 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2608 RESULT=pass
29261 17:04:43.720851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip>
29262 17:04:43.721283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2608 RESULT=skip
29264 17:04:43.754601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip>
29265 17:04:43.755005 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2608 RESULT=skip
29267 17:04:43.789568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass
29269 17:04:43.790163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2624 RESULT=pass>
29270 17:04:43.830113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip
29272 17:04:43.830822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2624 RESULT=skip>
29273 17:04:43.864805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip
29275 17:04:43.865205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2624 RESULT=skip>
29276 17:04:43.900644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass>
29277 17:04:43.901033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2640 RESULT=pass
29279 17:04:43.943337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip
29281 17:04:43.944010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2640 RESULT=skip>
29282 17:04:43.983922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip
29284 17:04:43.984685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2640 RESULT=skip>
29285 17:04:44.023150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass>
29286 17:04:44.023586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2656 RESULT=pass
29288 17:04:44.058768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip>
29289 17:04:44.059161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2656 RESULT=skip
29291 17:04:44.099894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip
29293 17:04:44.100547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2656 RESULT=skip>
29294 17:04:44.142259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass>
29295 17:04:44.142852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2672 RESULT=pass
29297 17:04:44.187054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip>
29298 17:04:44.187449 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2672 RESULT=skip
29300 17:04:44.226045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip>
29301 17:04:44.226538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2672 RESULT=skip
29303 17:04:44.263882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass
29305 17:04:44.264361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2688 RESULT=pass>
29306 17:04:44.314583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip
29308 17:04:44.315052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2688 RESULT=skip>
29309 17:04:44.351761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip
29311 17:04:44.352295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2688 RESULT=skip>
29312 17:04:44.390003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass>
29313 17:04:44.390385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2704 RESULT=pass
29315 17:04:44.429262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip
29317 17:04:44.429902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2704 RESULT=skip>
29318 17:04:44.475906 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip
29320 17:04:44.476391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2704 RESULT=skip>
29321 17:04:44.522459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass>
29322 17:04:44.522817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2720 RESULT=pass
29324 17:04:44.561884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip>
29325 17:04:44.562237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2720 RESULT=skip
29327 17:04:44.605530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip
29329 17:04:44.605873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2720 RESULT=skip>
29330 17:04:44.653115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass
29332 17:04:44.653589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2736 RESULT=pass>
29333 17:04:44.704360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip
29335 17:04:44.704834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2736 RESULT=skip>
29336 17:04:44.746089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip
29338 17:04:44.746556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2736 RESULT=skip>
29339 17:04:44.783286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass
29341 17:04:44.783897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2752 RESULT=pass>
29342 17:04:44.820923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip>
29343 17:04:44.821427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2752 RESULT=skip
29345 17:04:44.857726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip>
29346 17:04:44.858152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2752 RESULT=skip
29348 17:04:44.897709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass
29350 17:04:44.898125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2768 RESULT=pass>
29351 17:04:44.936492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip
29353 17:04:44.936899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2768 RESULT=skip>
29354 17:04:44.985638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip>
29355 17:04:44.986088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2768 RESULT=skip
29357 17:04:45.026038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass>
29358 17:04:45.026447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2784 RESULT=pass
29360 17:04:45.071193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip>
29361 17:04:45.071597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2784 RESULT=skip
29363 17:04:45.110198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip>
29364 17:04:45.110756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2784 RESULT=skip
29366 17:04:45.147856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass
29368 17:04:45.148355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2800 RESULT=pass>
29369 17:04:45.189199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip
29371 17:04:45.189675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2800 RESULT=skip>
29372 17:04:45.226655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip>
29373 17:04:45.227060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2800 RESULT=skip
29375 17:04:45.263875 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass
29377 17:04:45.264346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2816 RESULT=pass>
29378 17:04:45.298655 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip
29380 17:04:45.299108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2816 RESULT=skip>
29381 17:04:45.335355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip>
29382 17:04:45.335751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2816 RESULT=skip
29384 17:04:45.369078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass>
29385 17:04:45.369470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2832 RESULT=pass
29387 17:04:45.402945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip>
29388 17:04:45.403349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2832 RESULT=skip
29390 17:04:45.437167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip>
29391 17:04:45.437579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2832 RESULT=skip
29393 17:04:45.471742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass
29395 17:04:45.472134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2848 RESULT=pass>
29396 17:04:45.506172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip>
29397 17:04:45.506569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2848 RESULT=skip
29399 17:04:45.540979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip
29401 17:04:45.541381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2848 RESULT=skip>
29402 17:04:45.574192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass>
29403 17:04:45.574607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2864 RESULT=pass
29405 17:04:45.608571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip>
29406 17:04:45.608978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2864 RESULT=skip
29408 17:04:45.643956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip
29410 17:04:45.644544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2864 RESULT=skip>
29411 17:04:45.677319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass>
29412 17:04:45.677725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2880 RESULT=pass
29414 17:04:45.710413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip>
29415 17:04:45.710790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2880 RESULT=skip
29417 17:04:45.745552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip>
29418 17:04:45.745943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2880 RESULT=skip
29420 17:04:45.778994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass>
29421 17:04:45.779461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2896 RESULT=pass
29423 17:04:45.814660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip>
29424 17:04:45.815077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2896 RESULT=skip
29426 17:04:45.848513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip
29428 17:04:45.848888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2896 RESULT=skip>
29429 17:04:45.882048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass
29431 17:04:45.882486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2912 RESULT=pass>
29432 17:04:45.915928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip
29434 17:04:45.916598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2912 RESULT=skip>
29435 17:04:45.949361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip
29437 17:04:45.949788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2912 RESULT=skip>
29438 17:04:45.983187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass
29440 17:04:45.983683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2928 RESULT=pass>
29441 17:04:46.016980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip>
29442 17:04:46.017376 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2928 RESULT=skip
29444 17:04:46.051536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip>
29445 17:04:46.052009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2928 RESULT=skip
29447 17:04:46.085107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass
29449 17:04:46.085515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2944 RESULT=pass>
29450 17:04:46.119928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip
29452 17:04:46.120365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2944 RESULT=skip>
29453 17:04:46.169589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip>
29454 17:04:46.170020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2944 RESULT=skip
29456 17:04:46.206064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass>
29457 17:04:46.206419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2960 RESULT=pass
29459 17:04:46.247882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip
29461 17:04:46.248570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2960 RESULT=skip>
29462 17:04:46.293668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip
29464 17:04:46.294176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2960 RESULT=skip>
29465 17:04:46.330403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass>
29466 17:04:46.330756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2976 RESULT=pass
29468 17:04:46.371252 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip
29470 17:04:46.371638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2976 RESULT=skip>
29471 17:04:46.420373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip>
29472 17:04:46.420833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2976 RESULT=skip
29474 17:04:46.453672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass
29476 17:04:46.454094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_2992 RESULT=pass>
29477 17:04:46.487324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip
29479 17:04:46.487671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_2992 RESULT=skip>
29480 17:04:46.522148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip>
29481 17:04:46.522496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_2992 RESULT=skip
29483 17:04:46.556903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass>
29484 17:04:46.557322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3008 RESULT=pass
29486 17:04:46.601988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip>
29487 17:04:46.602326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3008 RESULT=skip
29489 17:04:46.635083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip
29491 17:04:46.635691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3008 RESULT=skip>
29492 17:04:46.669217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass>
29493 17:04:46.669780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3024 RESULT=pass
29495 17:04:46.703184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip>
29496 17:04:46.703816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3024 RESULT=skip
29498 17:04:46.737611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip
29500 17:04:46.738182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3024 RESULT=skip>
29501 17:04:46.771894 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass
29503 17:04:46.772302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3040 RESULT=pass>
29504 17:04:46.806494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip>
29505 17:04:46.806972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3040 RESULT=skip
29507 17:04:46.841937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip>
29508 17:04:46.842423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3040 RESULT=skip
29510 17:04:46.889995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass
29512 17:04:46.890679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3056 RESULT=pass>
29513 17:04:46.925969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip
29515 17:04:46.926657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3056 RESULT=skip>
29516 17:04:46.962905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip>
29517 17:04:46.963286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3056 RESULT=skip
29519 17:04:46.998355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass>
29520 17:04:46.998784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3072 RESULT=pass
29522 17:04:47.033958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip>
29523 17:04:47.034454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3072 RESULT=skip
29525 17:04:47.071145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip>
29526 17:04:47.071620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3072 RESULT=skip
29528 17:04:47.109439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass>
29529 17:04:47.109885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3088 RESULT=pass
29531 17:04:47.151746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip
29533 17:04:47.152224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3088 RESULT=skip>
29534 17:04:47.198427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip
29536 17:04:47.198897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3088 RESULT=skip>
29537 17:04:47.232466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass>
29538 17:04:47.232907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3104 RESULT=pass
29540 17:04:47.270281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip>
29541 17:04:47.270831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3104 RESULT=skip
29543 17:04:47.305939 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip
29545 17:04:47.306408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3104 RESULT=skip>
29546 17:04:47.342473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass
29548 17:04:47.343230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3120 RESULT=pass>
29549 17:04:47.386005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip>
29550 17:04:47.386417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3120 RESULT=skip
29552 17:04:47.423465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip
29554 17:04:47.423841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3120 RESULT=skip>
29555 17:04:47.465604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass
29557 17:04:47.466274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3136 RESULT=pass>
29558 17:04:47.517479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip>
29559 17:04:47.517923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3136 RESULT=skip
29561 17:04:47.565509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip>
29562 17:04:47.565938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3136 RESULT=skip
29564 17:04:47.607411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass>
29565 17:04:47.607830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3152 RESULT=pass
29567 17:04:47.659600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip>
29568 17:04:47.660022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3152 RESULT=skip
29570 17:04:47.700988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip>
29571 17:04:47.701401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3152 RESULT=skip
29573 17:04:47.747654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass
29575 17:04:47.748087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3168 RESULT=pass>
29576 17:04:47.800524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip>
29577 17:04:47.800966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3168 RESULT=skip
29579 17:04:47.849593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip>
29580 17:04:47.850022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3168 RESULT=skip
29582 17:04:47.932728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass>
29583 17:04:47.933165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3184 RESULT=pass
29585 17:04:47.977865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip>
29586 17:04:47.978244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3184 RESULT=skip
29588 17:04:48.017399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip>
29589 17:04:48.017785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3184 RESULT=skip
29591 17:04:48.066256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass>
29592 17:04:48.066669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3200 RESULT=pass
29594 17:04:48.108761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip>
29595 17:04:48.109194 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3200 RESULT=skip
29597 17:04:48.149895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip>
29598 17:04:48.150238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3200 RESULT=skip
29600 17:04:48.193399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass>
29601 17:04:48.193923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3216 RESULT=pass
29603 17:04:48.235567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip
29605 17:04:48.236045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3216 RESULT=skip>
29606 17:04:48.282586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip
29608 17:04:48.283027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3216 RESULT=skip>
29609 17:04:48.324812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass
29611 17:04:48.325282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3232 RESULT=pass>
29612 17:04:48.370519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip
29614 17:04:48.371028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3232 RESULT=skip>
29615 17:04:48.413393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip
29617 17:04:48.413877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3232 RESULT=skip>
29618 17:04:48.455661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass
29620 17:04:48.456176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3248 RESULT=pass>
29621 17:04:48.502727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip>
29622 17:04:48.503131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3248 RESULT=skip
29624 17:04:48.562584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip>
29625 17:04:48.562989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3248 RESULT=skip
29627 17:04:48.605147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass>
29628 17:04:48.605580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3264 RESULT=pass
29630 17:04:48.656527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip>
29631 17:04:48.658026 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3264 RESULT=skip
29633 17:04:48.707310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip>
29634 17:04:48.707769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3264 RESULT=skip
29636 17:04:48.744968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass>
29637 17:04:48.745421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3280 RESULT=pass
29639 17:04:48.781165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip>
29640 17:04:48.781551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3280 RESULT=skip
29642 17:04:48.817761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip>
29643 17:04:48.818145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3280 RESULT=skip
29645 17:04:48.869201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass>
29646 17:04:48.869632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3296 RESULT=pass
29648 17:04:48.912017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip
29650 17:04:48.912519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3296 RESULT=skip>
29651 17:04:48.961955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip>
29652 17:04:48.962386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3296 RESULT=skip
29654 17:04:49.009254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass>
29655 17:04:49.009701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3312 RESULT=pass
29657 17:04:49.051810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip
29659 17:04:49.052278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3312 RESULT=skip>
29660 17:04:49.099777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip
29662 17:04:49.100505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3312 RESULT=skip>
29663 17:04:49.142507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass>
29664 17:04:49.142957 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3328 RESULT=pass
29666 17:04:49.186764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip>
29667 17:04:49.187325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3328 RESULT=skip
29669 17:04:49.226394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip>
29670 17:04:49.226816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3328 RESULT=skip
29672 17:04:49.271779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass
29674 17:04:49.272251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3344 RESULT=pass>
29675 17:04:49.323751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip
29677 17:04:49.324292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3344 RESULT=skip>
29678 17:04:49.371533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip>
29679 17:04:49.371904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3344 RESULT=skip
29681 17:04:49.423137 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass
29683 17:04:49.423610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3360 RESULT=pass>
29684 17:04:49.469516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip>
29685 17:04:49.469923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3360 RESULT=skip
29687 17:04:49.516690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip
29689 17:04:49.517064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3360 RESULT=skip>
29690 17:04:49.561255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass>
29691 17:04:49.561692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3376 RESULT=pass
29693 17:04:49.605274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip
29695 17:04:49.605940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3376 RESULT=skip>
29696 17:04:49.650227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip>
29697 17:04:49.650789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3376 RESULT=skip
29699 17:04:49.698825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass
29701 17:04:49.699286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3392 RESULT=pass>
29702 17:04:49.741506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip
29704 17:04:49.741925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3392 RESULT=skip>
29705 17:04:49.784872 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip
29707 17:04:49.785463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3392 RESULT=skip>
29708 17:04:49.832239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass>
29709 17:04:49.832661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3408 RESULT=pass
29711 17:04:49.883567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip>
29712 17:04:49.883943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3408 RESULT=skip
29714 17:04:49.937339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip>
29715 17:04:49.937792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3408 RESULT=skip
29717 17:04:49.984928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass>
29718 17:04:49.985382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3424 RESULT=pass
29720 17:04:50.030787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip>
29721 17:04:50.031225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3424 RESULT=skip
29723 17:04:50.073701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip
29725 17:04:50.074139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3424 RESULT=skip>
29726 17:04:50.118260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass>
29727 17:04:50.118654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3440 RESULT=pass
29729 17:04:50.173798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip>
29730 17:04:50.174267 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3440 RESULT=skip
29732 17:04:50.220782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip>
29733 17:04:50.221206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3440 RESULT=skip
29735 17:04:50.261188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass
29737 17:04:50.261606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3456 RESULT=pass>
29738 17:04:50.297933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip>
29739 17:04:50.298311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3456 RESULT=skip
29741 17:04:50.334364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip>
29742 17:04:50.334765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3456 RESULT=skip
29744 17:04:50.378830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass>
29745 17:04:50.379231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3472 RESULT=pass
29747 17:04:50.426198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip>
29748 17:04:50.426717 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3472 RESULT=skip
29750 17:04:50.476780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip
29752 17:04:50.477322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3472 RESULT=skip>
29753 17:04:50.521800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass
29755 17:04:50.522285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3488 RESULT=pass>
29756 17:04:50.564707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip>
29757 17:04:50.565143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3488 RESULT=skip
29759 17:04:50.598714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip>
29760 17:04:50.599183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3488 RESULT=skip
29762 17:04:50.635404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass
29764 17:04:50.635871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3504 RESULT=pass>
29765 17:04:50.681786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip
29767 17:04:50.682415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3504 RESULT=skip>
29768 17:04:50.729513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip>
29769 17:04:50.730002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3504 RESULT=skip
29771 17:04:50.772665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass>
29772 17:04:50.773116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3520 RESULT=pass
29774 17:04:50.817060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip>
29775 17:04:50.817426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3520 RESULT=skip
29777 17:04:50.861671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip
29779 17:04:50.862166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3520 RESULT=skip>
29780 17:04:50.907331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass>
29781 17:04:50.907718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3536 RESULT=pass
29783 17:04:50.953947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip>
29784 17:04:50.954337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3536 RESULT=skip
29786 17:04:50.995081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip>
29787 17:04:50.995450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3536 RESULT=skip
29789 17:04:51.039157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass>
29790 17:04:51.039532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3552 RESULT=pass
29792 17:04:51.073128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip>
29793 17:04:51.073499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3552 RESULT=skip
29795 17:04:51.115665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip
29797 17:04:51.116085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3552 RESULT=skip>
29798 17:04:51.149948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass
29800 17:04:51.150320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3568 RESULT=pass>
29801 17:04:51.184582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip>
29802 17:04:51.184920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3568 RESULT=skip
29804 17:04:51.219468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip>
29805 17:04:51.219923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3568 RESULT=skip
29807 17:04:51.253986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass>
29808 17:04:51.254428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3584 RESULT=pass
29810 17:04:51.294967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip>
29811 17:04:51.295478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3584 RESULT=skip
29813 17:04:51.332918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip>
29814 17:04:51.333369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3584 RESULT=skip
29816 17:04:51.384316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass>
29817 17:04:51.384671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3600 RESULT=pass
29819 17:04:51.437670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip>
29820 17:04:51.438101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3600 RESULT=skip
29822 17:04:51.480511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip
29824 17:04:51.480970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3600 RESULT=skip>
29825 17:04:51.516760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass
29827 17:04:51.517227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3616 RESULT=pass>
29828 17:04:51.553848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip
29830 17:04:51.554334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3616 RESULT=skip>
29831 17:04:51.595103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip>
29832 17:04:51.595512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3616 RESULT=skip
29834 17:04:51.636522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass>
29835 17:04:51.636930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3632 RESULT=pass
29837 17:04:51.674941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip>
29838 17:04:51.675388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3632 RESULT=skip
29840 17:04:51.722625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip>
29841 17:04:51.723044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3632 RESULT=skip
29843 17:04:51.763595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass
29845 17:04:51.763958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3648 RESULT=pass>
29846 17:04:51.802544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip>
29847 17:04:51.802833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3648 RESULT=skip
29849 17:04:51.857263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip>
29850 17:04:51.857548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3648 RESULT=skip
29852 17:04:51.893136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass>
29853 17:04:51.893475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3664 RESULT=pass
29855 17:04:51.933388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip>
29856 17:04:51.933824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3664 RESULT=skip
29858 17:04:51.973306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip>
29859 17:04:51.973685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3664 RESULT=skip
29861 17:04:52.014404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass>
29862 17:04:52.014832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3680 RESULT=pass
29864 17:04:52.053711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip>
29865 17:04:52.054120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3680 RESULT=skip
29867 17:04:52.095781 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip
29869 17:04:52.096208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3680 RESULT=skip>
29870 17:04:52.135539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass
29872 17:04:52.136072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3696 RESULT=pass>
29873 17:04:52.179372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip>
29874 17:04:52.179785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3696 RESULT=skip
29876 17:04:52.214318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip>
29877 17:04:52.214666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3696 RESULT=skip
29879 17:04:52.249506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass>
29880 17:04:52.249848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3712 RESULT=pass
29882 17:04:52.289269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip>
29883 17:04:52.289667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3712 RESULT=skip
29885 17:04:52.336643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip>
29886 17:04:52.337150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3712 RESULT=skip
29888 17:04:52.383534 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass
29890 17:04:52.383975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3728 RESULT=pass>
29891 17:04:52.433672 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip
29893 17:04:52.434147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3728 RESULT=skip>
29894 17:04:52.478025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip>
29895 17:04:52.478452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3728 RESULT=skip
29897 17:04:52.518202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass>
29898 17:04:52.518654 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3744 RESULT=pass
29900 17:04:52.559209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip>
29901 17:04:52.559693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3744 RESULT=skip
29903 17:04:52.605946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip>
29904 17:04:52.606309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3744 RESULT=skip
29906 17:04:52.645666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass>
29907 17:04:52.646065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3760 RESULT=pass
29909 17:04:52.691766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip
29911 17:04:52.692330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3760 RESULT=skip>
29912 17:04:52.735764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip
29914 17:04:52.736172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3760 RESULT=skip>
29915 17:04:52.769537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass
29917 17:04:52.769939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3776 RESULT=pass>
29918 17:04:52.808875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip>
29919 17:04:52.809299 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3776 RESULT=skip
29921 17:04:52.843469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip
29923 17:04:52.843840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3776 RESULT=skip>
29924 17:04:52.878075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass
29926 17:04:52.878539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3792 RESULT=pass>
29927 17:04:52.914162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip
29929 17:04:52.914620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3792 RESULT=skip>
29930 17:04:52.948223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip>
29931 17:04:52.948729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3792 RESULT=skip
29933 17:04:52.982605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass>
29934 17:04:52.983175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3808 RESULT=pass
29936 17:04:53.042329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip
29938 17:04:53.042782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3808 RESULT=skip>
29939 17:04:53.076221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip>
29940 17:04:53.076660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3808 RESULT=skip
29942 17:04:53.110315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass>
29943 17:04:53.110744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3824 RESULT=pass
29945 17:04:53.143282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip>
29946 17:04:53.143844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3824 RESULT=skip
29948 17:04:53.181698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip
29950 17:04:53.182429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3824 RESULT=skip>
29951 17:04:53.228504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass
29953 17:04:53.229259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3840 RESULT=pass>
29954 17:04:53.274023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip>
29955 17:04:53.274463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3840 RESULT=skip
29957 17:04:53.318077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip>
29958 17:04:53.318432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3840 RESULT=skip
29960 17:04:53.367794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass
29962 17:04:53.368297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3856 RESULT=pass>
29963 17:04:53.415882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip
29965 17:04:53.416302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3856 RESULT=skip>
29966 17:04:53.460932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip>
29967 17:04:53.461319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3856 RESULT=skip
29969 17:04:53.515178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass
29971 17:04:53.515597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3872 RESULT=pass>
29972 17:04:53.551292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip
29974 17:04:53.551776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3872 RESULT=skip>
29975 17:04:53.586560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip>
29976 17:04:53.586943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3872 RESULT=skip
29978 17:04:53.621304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass>
29979 17:04:53.621841 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3888 RESULT=pass
29981 17:04:53.657138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip>
29982 17:04:53.657602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3888 RESULT=skip
29984 17:04:53.692424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip>
29985 17:04:53.692860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3888 RESULT=skip
29987 17:04:53.730725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass>
29988 17:04:53.731177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3904 RESULT=pass
29990 17:04:53.784811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip>
29991 17:04:53.785284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3904 RESULT=skip
29993 17:04:53.818359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip>
29994 17:04:53.818885 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3904 RESULT=skip
29996 17:04:53.861229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass>
29997 17:04:53.861710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3920 RESULT=pass
29999 17:04:53.914955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip
30001 17:04:53.915617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3920 RESULT=skip>
30002 17:04:53.960723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip>
30003 17:04:53.961152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3920 RESULT=skip
30005 17:04:54.006218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass>
30006 17:04:54.006637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3936 RESULT=pass
30008 17:04:54.046881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip
30010 17:04:54.047362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3936 RESULT=skip>
30011 17:04:54.083528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip
30013 17:04:54.084003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3936 RESULT=skip>
30014 17:04:54.121064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass>
30015 17:04:54.121463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3952 RESULT=pass
30017 17:04:54.164388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip
30019 17:04:54.165157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3952 RESULT=skip>
30020 17:04:54.199957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip>
30021 17:04:54.200460 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3952 RESULT=skip
30023 17:04:54.235533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass>
30024 17:04:54.235891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3968 RESULT=pass
30026 17:04:54.271542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip>
30027 17:04:54.272015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3968 RESULT=skip
30029 17:04:54.308290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip>
30030 17:04:54.308727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3968 RESULT=skip
30032 17:04:54.345111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass>
30033 17:04:54.345504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_3984 RESULT=pass
30035 17:04:54.381993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip>
30036 17:04:54.382395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_3984 RESULT=skip
30038 17:04:54.418998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip
30040 17:04:54.419413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_3984 RESULT=skip>
30041 17:04:54.457110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass>
30042 17:04:54.457435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4000 RESULT=pass
30044 17:04:54.494832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip
30046 17:04:54.495174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4000 RESULT=skip>
30047 17:04:54.538831 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip
30049 17:04:54.539285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4000 RESULT=skip>
30050 17:04:54.577399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass>
30051 17:04:54.577750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4016 RESULT=pass
30053 17:04:54.621900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip>
30054 17:04:54.622251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4016 RESULT=skip
30056 17:04:54.662259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip>
30057 17:04:54.662649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4016 RESULT=skip
30059 17:04:54.698986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass>
30060 17:04:54.699506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4032 RESULT=pass
30062 17:04:54.733778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip>
30063 17:04:54.734225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4032 RESULT=skip
30065 17:04:54.768120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip>
30066 17:04:54.768515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4032 RESULT=skip
30068 17:04:54.810562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass>
30069 17:04:54.811010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4048 RESULT=pass
30071 17:04:54.854070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip
30073 17:04:54.854530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4048 RESULT=skip>
30074 17:04:54.889368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip
30076 17:04:54.889817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4048 RESULT=skip>
30077 17:04:54.935329 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass
30079 17:04:54.935699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4064 RESULT=pass>
30080 17:04:54.970740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip
30082 17:04:54.971180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4064 RESULT=skip>
30083 17:04:55.012289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip>
30084 17:04:55.012649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4064 RESULT=skip
30086 17:04:55.064597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass>
30087 17:04:55.065066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4080 RESULT=pass
30089 17:04:55.106585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip>
30090 17:04:55.107150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4080 RESULT=skip
30092 17:04:55.142146 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip
30094 17:04:55.142617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4080 RESULT=skip>
30095 17:04:55.181200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass>
30096 17:04:55.181750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4096 RESULT=pass
30098 17:04:55.218145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip>
30099 17:04:55.218563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4096 RESULT=skip
30101 17:04:55.256414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip
30103 17:04:55.256887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4096 RESULT=skip>
30104 17:04:55.292874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass>
30105 17:04:55.293316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4112 RESULT=pass
30107 17:04:55.329295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip>
30108 17:04:55.329685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4112 RESULT=skip
30110 17:04:55.373072 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip
30112 17:04:55.373794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4112 RESULT=skip>
30113 17:04:55.416631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass>
30114 17:04:55.417078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4128 RESULT=pass
30116 17:04:55.454784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip>
30117 17:04:55.455341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4128 RESULT=skip
30119 17:04:55.510437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip
30121 17:04:55.511219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4128 RESULT=skip>
30122 17:04:55.545159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass
30124 17:04:55.545661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4144 RESULT=pass>
30125 17:04:55.586382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip>
30126 17:04:55.586801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4144 RESULT=skip
30128 17:04:55.620549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip
30130 17:04:55.620966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4144 RESULT=skip>
30131 17:04:55.653405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass
30133 17:04:55.653850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4160 RESULT=pass>
30134 17:04:55.687053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip>
30135 17:04:55.687472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4160 RESULT=skip
30137 17:04:55.719840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip
30139 17:04:55.720248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4160 RESULT=skip>
30140 17:04:55.756862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass
30142 17:04:55.757273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4176 RESULT=pass>
30143 17:04:55.801771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip
30145 17:04:55.802240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4176 RESULT=skip>
30146 17:04:55.843264 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip
30148 17:04:55.843737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4176 RESULT=skip>
30149 17:04:55.885734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass>
30150 17:04:55.886175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4192 RESULT=pass
30152 17:04:55.930433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip
30154 17:04:55.930854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4192 RESULT=skip>
30155 17:04:55.980371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip>
30156 17:04:55.980799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4192 RESULT=skip
30158 17:04:56.022723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass
30160 17:04:56.023135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4208 RESULT=pass>
30161 17:04:56.063459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip>
30162 17:04:56.063863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4208 RESULT=skip
30164 17:04:56.104429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip>
30165 17:04:56.104787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4208 RESULT=skip
30167 17:04:56.144553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass>
30168 17:04:56.145000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4224 RESULT=pass
30170 17:04:56.182778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip
30172 17:04:56.183366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4224 RESULT=skip>
30173 17:04:56.224530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip>
30174 17:04:56.224963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4224 RESULT=skip
30176 17:04:56.269720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass>
30177 17:04:56.270278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4240 RESULT=pass
30179 17:04:56.321621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip>
30180 17:04:56.322076 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4240 RESULT=skip
30182 17:04:56.358917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip
30184 17:04:56.359295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4240 RESULT=skip>
30185 17:04:56.394137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass>
30186 17:04:56.394562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4256 RESULT=pass
30188 17:04:56.429789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip>
30189 17:04:56.430191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4256 RESULT=skip
30191 17:04:56.465914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip>
30192 17:04:56.466246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4256 RESULT=skip
30194 17:04:56.506386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass
30196 17:04:56.506818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4272 RESULT=pass>
30197 17:04:56.546920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip
30199 17:04:56.547376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4272 RESULT=skip>
30200 17:04:56.593007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip
30202 17:04:56.593433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4272 RESULT=skip>
30203 17:04:56.642881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass>
30204 17:04:56.643411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4288 RESULT=pass
30206 17:04:56.679288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip>
30207 17:04:56.680113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4288 RESULT=skip
30209 17:04:56.731380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip>
30210 17:04:56.731722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4288 RESULT=skip
30212 17:04:56.773429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass>
30213 17:04:56.773892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4304 RESULT=pass
30215 17:04:56.814221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip>
30216 17:04:56.814650 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4304 RESULT=skip
30218 17:04:56.850320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip>
30219 17:04:56.850839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4304 RESULT=skip
30221 17:04:56.885798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass>
30222 17:04:56.886230 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4320 RESULT=pass
30224 17:04:56.921479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip>
30225 17:04:56.921928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4320 RESULT=skip
30227 17:04:56.956949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip
30229 17:04:56.957413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4320 RESULT=skip>
30230 17:04:56.999850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass
30232 17:04:57.000283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4336 RESULT=pass>
30233 17:04:57.036968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip>
30234 17:04:57.037374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4336 RESULT=skip
30236 17:04:57.077096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip
30238 17:04:57.077562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4336 RESULT=skip>
30239 17:04:57.111371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass>
30240 17:04:57.111774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4352 RESULT=pass
30242 17:04:57.149759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip>
30243 17:04:57.150202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4352 RESULT=skip
30245 17:04:57.187345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip
30247 17:04:57.187806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4352 RESULT=skip>
30248 17:04:57.222602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass>
30249 17:04:57.222969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4368 RESULT=pass
30251 17:04:57.258420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip>
30252 17:04:57.258910 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4368 RESULT=skip
30254 17:04:57.293674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip>
30255 17:04:57.294107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4368 RESULT=skip
30257 17:04:57.329900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass
30259 17:04:57.330341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4384 RESULT=pass>
30260 17:04:57.370930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip>
30261 17:04:57.371343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4384 RESULT=skip
30263 17:04:57.421822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip>
30264 17:04:57.422307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4384 RESULT=skip
30266 17:04:57.468862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass>
30267 17:04:57.469167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4400 RESULT=pass
30269 17:04:57.506587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip>
30270 17:04:57.506877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4400 RESULT=skip
30272 17:04:57.548599 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip
30274 17:04:57.549052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4400 RESULT=skip>
30275 17:04:57.584771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass>
30276 17:04:57.585188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4416 RESULT=pass
30278 17:04:57.620878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip
30280 17:04:57.621328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4416 RESULT=skip>
30281 17:04:57.653540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip
30283 17:04:57.654011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4416 RESULT=skip>
30284 17:04:57.688446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass>
30285 17:04:57.688897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4432 RESULT=pass
30287 17:04:57.723550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip>
30288 17:04:57.724033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4432 RESULT=skip
30290 17:04:57.757941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip
30292 17:04:57.758385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4432 RESULT=skip>
30293 17:04:57.792915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass
30295 17:04:57.793488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4448 RESULT=pass>
30296 17:04:57.828984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip
30298 17:04:57.829434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4448 RESULT=skip>
30299 17:04:57.863251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip>
30300 17:04:57.863722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4448 RESULT=skip
30302 17:04:57.898288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass>
30303 17:04:57.898715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4464 RESULT=pass
30305 17:04:57.933707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip>
30306 17:04:57.934086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4464 RESULT=skip
30308 17:04:57.969686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip>
30309 17:04:57.970130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4464 RESULT=skip
30311 17:04:58.005096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass>
30312 17:04:58.005545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4480 RESULT=pass
30314 17:04:58.040922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip>
30315 17:04:58.041375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4480 RESULT=skip
30317 17:04:58.078516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip>
30318 17:04:58.078955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4480 RESULT=skip
30320 17:04:58.113911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass>
30321 17:04:58.114349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4496 RESULT=pass
30323 17:04:58.189303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip>
30324 17:04:58.189786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4496 RESULT=skip
30326 17:04:58.242855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip>
30327 17:04:58.243303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4496 RESULT=skip
30329 17:04:58.285261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass
30331 17:04:58.285688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4512 RESULT=pass>
30332 17:04:58.321158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip
30334 17:04:58.321621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4512 RESULT=skip>
30335 17:04:58.355434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip>
30336 17:04:58.355825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4512 RESULT=skip
30338 17:04:58.388636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass
30340 17:04:58.389295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4528 RESULT=pass>
30341 17:04:58.422263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip
30343 17:04:58.422710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4528 RESULT=skip>
30344 17:04:58.457366 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip
30346 17:04:58.457833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4528 RESULT=skip>
30347 17:04:58.493634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass>
30348 17:04:58.494059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4544 RESULT=pass
30350 17:04:58.530710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip>
30351 17:04:58.531130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4544 RESULT=skip
30353 17:04:58.566399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip
30355 17:04:58.566843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4544 RESULT=skip>
30356 17:04:58.604986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass>
30357 17:04:58.605396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4560 RESULT=pass
30359 17:04:58.641601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip
30361 17:04:58.641989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4560 RESULT=skip>
30362 17:04:58.677497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip>
30363 17:04:58.677998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4560 RESULT=skip
30365 17:04:58.716926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass
30367 17:04:58.717603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4576 RESULT=pass>
30368 17:04:58.752882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip>
30369 17:04:58.753281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4576 RESULT=skip
30371 17:04:58.791924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip
30373 17:04:58.792373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4576 RESULT=skip>
30374 17:04:58.826056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass>
30375 17:04:58.826457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4592 RESULT=pass
30377 17:04:58.861289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip>
30378 17:04:58.861788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4592 RESULT=skip
30380 17:04:58.899271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip
30382 17:04:58.899934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4592 RESULT=skip>
30383 17:04:58.940741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass>
30384 17:04:58.941192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4608 RESULT=pass
30386 17:04:58.979713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip
30388 17:04:58.980142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4608 RESULT=skip>
30389 17:04:59.015099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip>
30390 17:04:59.015552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4608 RESULT=skip
30392 17:04:59.050176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass>
30393 17:04:59.050656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4624 RESULT=pass
30395 17:04:59.097580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip
30397 17:04:59.098214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4624 RESULT=skip>
30398 17:04:59.137838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip>
30399 17:04:59.138283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4624 RESULT=skip
30401 17:04:59.172955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass>
30402 17:04:59.173375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4640 RESULT=pass
30404 17:04:59.222358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip>
30405 17:04:59.222798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4640 RESULT=skip
30407 17:04:59.266633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip>
30408 17:04:59.267049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4640 RESULT=skip
30410 17:04:59.301002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass>
30411 17:04:59.301423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4656 RESULT=pass
30413 17:04:59.340615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip
30415 17:04:59.341075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4656 RESULT=skip>
30416 17:04:59.379185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip>
30417 17:04:59.379570 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4656 RESULT=skip
30419 17:04:59.416450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass
30421 17:04:59.416909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4672 RESULT=pass>
30422 17:04:59.460526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip
30424 17:04:59.460981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4672 RESULT=skip>
30425 17:04:59.495595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip
30427 17:04:59.496046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4672 RESULT=skip>
30428 17:04:59.534975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass>
30429 17:04:59.535403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4688 RESULT=pass
30431 17:04:59.576792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip>
30432 17:04:59.577175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4688 RESULT=skip
30434 17:04:59.612716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip
30436 17:04:59.613089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4688 RESULT=skip>
30437 17:04:59.645574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass
30439 17:04:59.646160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4704 RESULT=pass>
30440 17:04:59.678177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip>
30441 17:04:59.678592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4704 RESULT=skip
30443 17:04:59.711143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip>
30444 17:04:59.711567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4704 RESULT=skip
30446 17:04:59.750892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass
30448 17:04:59.751477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4720 RESULT=pass>
30449 17:04:59.792952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip>
30450 17:04:59.793394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4720 RESULT=skip
30452 17:04:59.831122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip
30454 17:04:59.831592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4720 RESULT=skip>
30455 17:04:59.873679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass>
30456 17:04:59.874232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4736 RESULT=pass
30458 17:04:59.909342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip>
30459 17:04:59.909758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4736 RESULT=skip
30461 17:04:59.953716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip
30463 17:04:59.954164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4736 RESULT=skip>
30464 17:05:00.001472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass>
30465 17:05:00.001892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4752 RESULT=pass
30467 17:05:00.043083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip>
30468 17:05:00.043512 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4752 RESULT=skip
30470 17:05:00.084466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip>
30471 17:05:00.085016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4752 RESULT=skip
30473 17:05:00.130114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass>
30474 17:05:00.130563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4768 RESULT=pass
30476 17:05:00.174055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip>
30477 17:05:00.174445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4768 RESULT=skip
30479 17:05:00.228872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip>
30480 17:05:00.229258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4768 RESULT=skip
30482 17:05:00.264561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass>
30483 17:05:00.264934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4784 RESULT=pass
30485 17:05:00.303201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip>
30486 17:05:00.303640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4784 RESULT=skip
30488 17:05:00.355444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip
30490 17:05:00.355881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4784 RESULT=skip>
30491 17:05:00.410715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass
30493 17:05:00.411152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4800 RESULT=pass>
30494 17:05:00.448838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip
30496 17:05:00.449437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4800 RESULT=skip>
30497 17:05:00.487481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip
30499 17:05:00.487860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4800 RESULT=skip>
30500 17:05:00.529536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass>
30501 17:05:00.529945 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4816 RESULT=pass
30503 17:05:00.564743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip>
30504 17:05:00.565188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4816 RESULT=skip
30506 17:05:00.602055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip>
30507 17:05:00.602503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4816 RESULT=skip
30509 17:05:00.642534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass>
30510 17:05:00.642973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4832 RESULT=pass
30512 17:05:00.682462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip>
30513 17:05:00.682892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4832 RESULT=skip
30515 17:05:00.718320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip
30517 17:05:00.718767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4832 RESULT=skip>
30518 17:05:00.753553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass>
30519 17:05:00.754015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4848 RESULT=pass
30521 17:05:00.791062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip>
30522 17:05:00.791492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4848 RESULT=skip
30524 17:05:00.829437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip
30526 17:05:00.829820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4848 RESULT=skip>
30527 17:05:00.865938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass>
30528 17:05:00.866356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4864 RESULT=pass
30530 17:05:00.909636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip>
30531 17:05:00.909975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4864 RESULT=skip
30533 17:05:00.950854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip>
30534 17:05:00.951297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4864 RESULT=skip
30536 17:05:00.991098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass>
30537 17:05:00.991521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4880 RESULT=pass
30539 17:05:01.027313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip
30541 17:05:01.027712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4880 RESULT=skip>
30542 17:05:01.074013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip>
30543 17:05:01.074423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4880 RESULT=skip
30545 17:05:01.116192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass
30547 17:05:01.116587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4896 RESULT=pass>
30548 17:05:01.158474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip>
30549 17:05:01.158949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4896 RESULT=skip
30551 17:05:01.193540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip>
30552 17:05:01.193992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4896 RESULT=skip
30554 17:05:01.229941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass>
30555 17:05:01.230308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4912 RESULT=pass
30557 17:05:01.265808 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip
30559 17:05:01.266491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4912 RESULT=skip>
30560 17:05:01.302087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip>
30561 17:05:01.302554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4912 RESULT=skip
30563 17:05:01.340810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass>
30564 17:05:01.341198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4928 RESULT=pass
30566 17:05:01.384502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip>
30567 17:05:01.384949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4928 RESULT=skip
30569 17:05:01.429105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip>
30570 17:05:01.429565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4928 RESULT=skip
30572 17:05:01.466582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass>
30573 17:05:01.467129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4944 RESULT=pass
30575 17:05:01.505511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip>
30576 17:05:01.505950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4944 RESULT=skip
30578 17:05:01.561985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip
30580 17:05:01.562557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4944 RESULT=skip>
30581 17:05:01.598333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass
30583 17:05:01.598742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4960 RESULT=pass>
30584 17:05:01.645234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip
30586 17:05:01.645940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4960 RESULT=skip>
30587 17:05:01.699544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip>
30588 17:05:01.699953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4960 RESULT=skip
30590 17:05:01.742147 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass
30592 17:05:01.742738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4976 RESULT=pass>
30593 17:05:01.786431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip>
30594 17:05:01.786882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4976 RESULT=skip
30596 17:05:01.833618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip>
30597 17:05:01.834175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4976 RESULT=skip
30599 17:05:01.869933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass>
30600 17:05:01.870455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_4992 RESULT=pass
30602 17:05:01.915340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip>
30603 17:05:01.915753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_4992 RESULT=skip
30605 17:05:01.966272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip
30607 17:05:01.966752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_4992 RESULT=skip>
30608 17:05:02.008720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass>
30609 17:05:02.009112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5008 RESULT=pass
30611 17:05:02.044450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip>
30612 17:05:02.044873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5008 RESULT=skip
30614 17:05:02.085911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip>
30615 17:05:02.086292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5008 RESULT=skip
30617 17:05:02.132206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass>
30618 17:05:02.132758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5024 RESULT=pass
30620 17:05:02.177853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip
30622 17:05:02.178283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5024 RESULT=skip>
30623 17:05:02.212685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip
30625 17:05:02.213061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5024 RESULT=skip>
30626 17:05:02.249671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass
30628 17:05:02.250362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5040 RESULT=pass>
30629 17:05:02.294342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip>
30630 17:05:02.294773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5040 RESULT=skip
30632 17:05:02.330106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip>
30633 17:05:02.330528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5040 RESULT=skip
30635 17:05:02.378539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass>
30636 17:05:02.378955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5056 RESULT=pass
30638 17:05:02.435170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip
30640 17:05:02.435611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5056 RESULT=skip>
30641 17:05:02.493297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip>
30642 17:05:02.493740 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5056 RESULT=skip
30644 17:05:02.549643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass>
30645 17:05:02.550034 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5072 RESULT=pass
30647 17:05:02.605668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip>
30648 17:05:02.606139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5072 RESULT=skip
30650 17:05:02.653948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip>
30651 17:05:02.654388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5072 RESULT=skip
30653 17:05:02.689843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass>
30654 17:05:02.690381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5088 RESULT=pass
30656 17:05:02.724924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip>
30657 17:05:02.725253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5088 RESULT=skip
30659 17:05:02.773708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip
30661 17:05:02.774082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5088 RESULT=skip>
30662 17:05:02.820945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass>
30663 17:05:02.821377 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5104 RESULT=pass
30665 17:05:02.869352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip>
30666 17:05:02.869806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5104 RESULT=skip
30668 17:05:02.915202 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip
30670 17:05:02.915566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5104 RESULT=skip>
30671 17:05:02.962025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass
30673 17:05:02.962596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5120 RESULT=pass>
30674 17:05:02.998600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip>
30675 17:05:02.999129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5120 RESULT=skip
30677 17:05:03.036264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip>
30678 17:05:03.036725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5120 RESULT=skip
30680 17:05:03.084991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass
30682 17:05:03.085455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5136 RESULT=pass>
30683 17:05:03.137112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip
30685 17:05:03.137582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5136 RESULT=skip>
30686 17:05:03.171504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip>
30687 17:05:03.171922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5136 RESULT=skip
30689 17:05:03.210738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass>
30690 17:05:03.211193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5152 RESULT=pass
30692 17:05:03.265320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip>
30693 17:05:03.265830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5152 RESULT=skip
30695 17:05:03.314229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip>
30696 17:05:03.314694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5152 RESULT=skip
30698 17:05:03.359149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass>
30699 17:05:03.359725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5168 RESULT=pass
30701 17:05:03.402926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip
30703 17:05:03.403409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5168 RESULT=skip>
30704 17:05:03.449054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip>
30705 17:05:03.449505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5168 RESULT=skip
30707 17:05:03.495056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass>
30708 17:05:03.495522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5184 RESULT=pass
30710 17:05:03.534604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip>
30711 17:05:03.535059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5184 RESULT=skip
30713 17:05:03.579495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip>
30714 17:05:03.579949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5184 RESULT=skip
30716 17:05:03.622101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass>
30717 17:05:03.622546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5200 RESULT=pass
30719 17:05:03.667506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip>
30720 17:05:03.667989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5200 RESULT=skip
30722 17:05:03.704470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip
30724 17:05:03.704966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5200 RESULT=skip>
30725 17:05:03.739571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass
30727 17:05:03.740042 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5216 RESULT=pass>
30728 17:05:03.775457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip>
30729 17:05:03.775886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5216 RESULT=skip
30731 17:05:03.811196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip>
30732 17:05:03.811648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5216 RESULT=skip
30734 17:05:03.846285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass>
30735 17:05:03.846761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5232 RESULT=pass
30737 17:05:03.882438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip
30739 17:05:03.882844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5232 RESULT=skip>
30740 17:05:03.917508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip>
30741 17:05:03.917920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5232 RESULT=skip
30743 17:05:03.952526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass>
30744 17:05:03.952924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5248 RESULT=pass
30746 17:05:03.999567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip>
30747 17:05:03.999981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5248 RESULT=skip
30749 17:05:04.042141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip>
30750 17:05:04.042562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5248 RESULT=skip
30752 17:05:04.085294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass>
30753 17:05:04.085783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5264 RESULT=pass
30755 17:05:04.130781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip>
30756 17:05:04.131164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5264 RESULT=skip
30758 17:05:04.167649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip
30760 17:05:04.168246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5264 RESULT=skip>
30761 17:05:04.202411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass>
30762 17:05:04.202838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5280 RESULT=pass
30764 17:05:04.253564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip
30766 17:05:04.254112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5280 RESULT=skip>
30767 17:05:04.293568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip>
30768 17:05:04.294155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5280 RESULT=skip
30770 17:05:04.331767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass
30772 17:05:04.332259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5296 RESULT=pass>
30773 17:05:04.385210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip>
30774 17:05:04.385527 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5296 RESULT=skip
30776 17:05:04.430794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip
30778 17:05:04.431475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5296 RESULT=skip>
30779 17:05:04.481012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass>
30780 17:05:04.481577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5312 RESULT=pass
30782 17:05:04.517542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip>
30783 17:05:04.518108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5312 RESULT=skip
30785 17:05:04.564635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip>
30786 17:05:04.565030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5312 RESULT=skip
30788 17:05:04.612271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass>
30789 17:05:04.612719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5328 RESULT=pass
30791 17:05:04.660595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip
30793 17:05:04.660984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5328 RESULT=skip>
30794 17:05:04.706259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip
30796 17:05:04.706865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5328 RESULT=skip>
30797 17:05:04.740852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass
30799 17:05:04.741422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5344 RESULT=pass>
30800 17:05:04.775574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip>
30801 17:05:04.775999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5344 RESULT=skip
30803 17:05:04.812956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip>
30804 17:05:04.813446 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5344 RESULT=skip
30806 17:05:04.849370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass>
30807 17:05:04.849854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5360 RESULT=pass
30809 17:05:04.889508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip>
30810 17:05:04.889959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5360 RESULT=skip
30812 17:05:04.925705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip
30814 17:05:04.926079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5360 RESULT=skip>
30815 17:05:04.961620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass
30817 17:05:04.962095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5376 RESULT=pass>
30818 17:05:05.009656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip
30820 17:05:05.010121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5376 RESULT=skip>
30821 17:05:05.045784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip
30823 17:05:05.046177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5376 RESULT=skip>
30824 17:05:05.086942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass
30826 17:05:05.087381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5392 RESULT=pass>
30827 17:05:05.135694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip>
30828 17:05:05.136148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5392 RESULT=skip
30830 17:05:05.173220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip>
30831 17:05:05.173610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5392 RESULT=skip
30833 17:05:05.224270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass>
30834 17:05:05.224813 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5408 RESULT=pass
30836 17:05:05.264912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip
30838 17:05:05.265299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5408 RESULT=skip>
30839 17:05:05.299308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip>
30840 17:05:05.299741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5408 RESULT=skip
30842 17:05:05.342574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass>
30843 17:05:05.342961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5424 RESULT=pass
30845 17:05:05.390465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip
30847 17:05:05.390855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5424 RESULT=skip>
30848 17:05:05.435452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip>
30849 17:05:05.435915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5424 RESULT=skip
30851 17:05:05.473553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass>
30852 17:05:05.474129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5440 RESULT=pass
30854 17:05:05.514296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip>
30855 17:05:05.514845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5440 RESULT=skip
30857 17:05:05.561818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip>
30858 17:05:05.562296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5440 RESULT=skip
30860 17:05:05.599786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass
30862 17:05:05.600262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5456 RESULT=pass>
30863 17:05:05.637477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip
30865 17:05:05.637942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5456 RESULT=skip>
30866 17:05:05.686379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip>
30867 17:05:05.686810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5456 RESULT=skip
30869 17:05:05.731148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass>
30870 17:05:05.731705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5472 RESULT=pass
30872 17:05:05.768651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip>
30873 17:05:05.769130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5472 RESULT=skip
30875 17:05:05.803267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip>
30876 17:05:05.803714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5472 RESULT=skip
30878 17:05:05.840646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass
30880 17:05:05.841112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5488 RESULT=pass>
30881 17:05:05.875663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip
30883 17:05:05.876143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5488 RESULT=skip>
30884 17:05:05.914757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip>
30885 17:05:05.915238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5488 RESULT=skip
30887 17:05:05.950359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass
30889 17:05:05.950826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5504 RESULT=pass>
30890 17:05:05.985302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip>
30891 17:05:05.985676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5504 RESULT=skip
30893 17:05:06.019067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip>
30894 17:05:06.019458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5504 RESULT=skip
30896 17:05:06.053674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass>
30897 17:05:06.054162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5520 RESULT=pass
30899 17:05:06.088428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip
30901 17:05:06.089192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5520 RESULT=skip>
30902 17:05:06.122266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip
30904 17:05:06.122761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5520 RESULT=skip>
30905 17:05:06.156092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass>
30906 17:05:06.156580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5536 RESULT=pass
30908 17:05:06.191215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip>
30909 17:05:06.191707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5536 RESULT=skip
30911 17:05:06.226061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip>
30912 17:05:06.226522 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5536 RESULT=skip
30914 17:05:06.261273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass>
30915 17:05:06.261664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5552 RESULT=pass
30917 17:05:06.296472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip>
30918 17:05:06.296899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5552 RESULT=skip
30920 17:05:06.330048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip>
30921 17:05:06.330609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5552 RESULT=skip
30923 17:05:06.369083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass
30925 17:05:06.369869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5568 RESULT=pass>
30926 17:05:06.403363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip>
30927 17:05:06.403779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5568 RESULT=skip
30929 17:05:06.438824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip>
30930 17:05:06.439268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5568 RESULT=skip
30932 17:05:06.471710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass
30934 17:05:06.472118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5584 RESULT=pass>
30935 17:05:06.504630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip>
30936 17:05:06.505088 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5584 RESULT=skip
30938 17:05:06.539578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip
30940 17:05:06.540043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5584 RESULT=skip>
30941 17:05:06.583151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass
30943 17:05:06.583790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5600 RESULT=pass>
30944 17:05:06.630941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip>
30945 17:05:06.631389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5600 RESULT=skip
30947 17:05:06.684380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip
30949 17:05:06.684870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5600 RESULT=skip>
30950 17:05:06.732597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass>
30951 17:05:06.733049 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5616 RESULT=pass
30953 17:05:06.767738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip
30955 17:05:06.768224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5616 RESULT=skip>
30956 17:05:06.810480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip>
30957 17:05:06.810916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5616 RESULT=skip
30959 17:05:06.854927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass>
30960 17:05:06.855375 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5632 RESULT=pass
30962 17:05:06.894347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip
30964 17:05:06.895017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5632 RESULT=skip>
30965 17:05:06.940773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip
30967 17:05:06.941197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5632 RESULT=skip>
30968 17:05:06.986593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass>
30969 17:05:06.987010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5648 RESULT=pass
30971 17:05:07.031093 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip
30973 17:05:07.031733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5648 RESULT=skip>
30974 17:05:07.079259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip
30976 17:05:07.079886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5648 RESULT=skip>
30977 17:05:07.125784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass>
30978 17:05:07.126229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5664 RESULT=pass
30980 17:05:07.160920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip>
30981 17:05:07.161373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5664 RESULT=skip
30983 17:05:07.206548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip>
30984 17:05:07.206999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5664 RESULT=skip
30986 17:05:07.245477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass>
30987 17:05:07.245929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5680 RESULT=pass
30989 17:05:07.288823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip
30991 17:05:07.289292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5680 RESULT=skip>
30992 17:05:07.322599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip>
30993 17:05:07.323031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5680 RESULT=skip
30995 17:05:07.356759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass>
30996 17:05:07.357175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5696 RESULT=pass
30998 17:05:07.392280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip>
30999 17:05:07.392726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5696 RESULT=skip
31001 17:05:07.438752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip>
31002 17:05:07.439261 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5696 RESULT=skip
31004 17:05:07.475649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass
31006 17:05:07.476176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5712 RESULT=pass>
31007 17:05:07.526846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip>
31008 17:05:07.527281 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5712 RESULT=skip
31010 17:05:07.578021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip
31012 17:05:07.578680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5712 RESULT=skip>
31013 17:05:07.624614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass>
31014 17:05:07.625070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5728 RESULT=pass
31016 17:05:07.667092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip
31018 17:05:07.667633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5728 RESULT=skip>
31019 17:05:07.709618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip>
31020 17:05:07.710112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5728 RESULT=skip
31022 17:05:07.753794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass>
31023 17:05:07.754214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5744 RESULT=pass
31025 17:05:07.785060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip>
31026 17:05:07.785510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5744 RESULT=skip
31028 17:05:07.820792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip
31030 17:05:07.821169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5744 RESULT=skip>
31031 17:05:07.861464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass
31033 17:05:07.861970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5760 RESULT=pass>
31034 17:05:07.897964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip>
31035 17:05:07.898410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5760 RESULT=skip
31037 17:05:07.933686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip>
31038 17:05:07.934133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5760 RESULT=skip
31040 17:05:07.980876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass
31042 17:05:07.981272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5776 RESULT=pass>
31043 17:05:08.039436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip>
31044 17:05:08.039860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5776 RESULT=skip
31046 17:05:08.087354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip
31048 17:05:08.087870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5776 RESULT=skip>
31049 17:05:08.140984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass>
31050 17:05:08.141369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5792 RESULT=pass
31052 17:05:08.186654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip>
31053 17:05:08.187060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5792 RESULT=skip
31055 17:05:08.229123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip>
31056 17:05:08.229631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5792 RESULT=skip
31058 17:05:08.277277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass>
31059 17:05:08.277771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5808 RESULT=pass
31061 17:05:08.326664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip>
31062 17:05:08.327148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5808 RESULT=skip
31064 17:05:08.401734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip>
31065 17:05:08.402226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5808 RESULT=skip
31067 17:05:08.436286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass
31069 17:05:08.436749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5824 RESULT=pass>
31070 17:05:08.483342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip
31072 17:05:08.483796 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5824 RESULT=skip>
31073 17:05:08.529789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip>
31074 17:05:08.530233 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5824 RESULT=skip
31076 17:05:08.581616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass>
31077 17:05:08.582031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5840 RESULT=pass
31079 17:05:08.636788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip>
31080 17:05:08.637223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5840 RESULT=skip
31082 17:05:08.687804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip
31084 17:05:08.688273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5840 RESULT=skip>
31085 17:05:08.732445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass
31087 17:05:08.732919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5856 RESULT=pass>
31088 17:05:08.774205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip>
31089 17:05:08.774627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5856 RESULT=skip
31091 17:05:08.821899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip>
31092 17:05:08.822427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5856 RESULT=skip
31094 17:05:08.857887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass>
31095 17:05:08.858326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5872 RESULT=pass
31097 17:05:08.901092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip>
31098 17:05:08.901535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5872 RESULT=skip
31100 17:05:08.945435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip
31102 17:05:08.945825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5872 RESULT=skip>
31103 17:05:08.992949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass>
31104 17:05:08.993398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5888 RESULT=pass
31106 17:05:09.031166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip>
31107 17:05:09.031558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5888 RESULT=skip
31109 17:05:09.077338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip
31111 17:05:09.077725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5888 RESULT=skip>
31112 17:05:09.128364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass>
31113 17:05:09.128778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5904 RESULT=pass
31115 17:05:09.174742 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip
31117 17:05:09.175110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5904 RESULT=skip>
31118 17:05:09.225778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip>
31119 17:05:09.226161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5904 RESULT=skip
31121 17:05:09.276903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass
31123 17:05:09.277319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5920 RESULT=pass>
31124 17:05:09.323933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip
31126 17:05:09.324338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5920 RESULT=skip>
31127 17:05:09.362822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip>
31128 17:05:09.363219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5920 RESULT=skip
31130 17:05:09.402981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass>
31131 17:05:09.403373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5936 RESULT=pass
31133 17:05:09.447466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip
31135 17:05:09.447942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5936 RESULT=skip>
31136 17:05:09.482919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip
31138 17:05:09.483387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5936 RESULT=skip>
31139 17:05:09.518488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass>
31140 17:05:09.518928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5952 RESULT=pass
31142 17:05:09.555209 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip
31144 17:05:09.555600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5952 RESULT=skip>
31145 17:05:09.594471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip>
31146 17:05:09.594895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5952 RESULT=skip
31148 17:05:09.633191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass
31150 17:05:09.633982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5968 RESULT=pass>
31151 17:05:09.671408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip>
31152 17:05:09.671923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5968 RESULT=skip
31154 17:05:09.709127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip>
31155 17:05:09.709568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5968 RESULT=skip
31157 17:05:09.749938 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass
31159 17:05:09.750392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_5984 RESULT=pass>
31160 17:05:09.788749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip>
31161 17:05:09.789182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_5984 RESULT=skip
31163 17:05:09.829699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip
31165 17:05:09.830159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_5984 RESULT=skip>
31166 17:05:09.867988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass
31168 17:05:09.868716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6000 RESULT=pass>
31169 17:05:09.909584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip>
31170 17:05:09.910040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6000 RESULT=skip
31172 17:05:09.948565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip
31174 17:05:09.949104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6000 RESULT=skip>
31175 17:05:09.998082 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass
31177 17:05:09.998534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6016 RESULT=pass>
31178 17:05:10.034531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip
31180 17:05:10.034987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6016 RESULT=skip>
31181 17:05:10.082423 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip
31183 17:05:10.082889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6016 RESULT=skip>
31184 17:05:10.123029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass>
31185 17:05:10.123471 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6032 RESULT=pass
31187 17:05:10.162126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip>
31188 17:05:10.162581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6032 RESULT=skip
31190 17:05:10.197228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip
31192 17:05:10.197741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6032 RESULT=skip>
31193 17:05:10.234831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass>
31194 17:05:10.235243 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6048 RESULT=pass
31196 17:05:10.280683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip>
31197 17:05:10.281211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6048 RESULT=skip
31199 17:05:10.320349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip>
31200 17:05:10.320758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6048 RESULT=skip
31202 17:05:10.357306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass>
31203 17:05:10.357754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6064 RESULT=pass
31205 17:05:10.395265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip>
31206 17:05:10.395738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6064 RESULT=skip
31208 17:05:10.440012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip
31210 17:05:10.440508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6064 RESULT=skip>
31211 17:05:10.490885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass>
31212 17:05:10.491374 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6080 RESULT=pass
31214 17:05:10.534479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip
31216 17:05:10.534963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6080 RESULT=skip>
31217 17:05:10.588923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip
31219 17:05:10.589368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6080 RESULT=skip>
31220 17:05:10.627050 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass
31222 17:05:10.627490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6096 RESULT=pass>
31223 17:05:10.670678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip>
31224 17:05:10.671103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6096 RESULT=skip
31226 17:05:10.708540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip>
31227 17:05:10.709003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6096 RESULT=skip
31229 17:05:10.749999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass>
31230 17:05:10.750455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6112 RESULT=pass
31232 17:05:10.790805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip>
31233 17:05:10.791198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6112 RESULT=skip
31235 17:05:10.833689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip>
31236 17:05:10.834292 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6112 RESULT=skip
31238 17:05:10.884520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass>
31239 17:05:10.884982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6128 RESULT=pass
31241 17:05:10.931463 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip
31243 17:05:10.931943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6128 RESULT=skip>
31244 17:05:10.974009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip>
31245 17:05:10.974441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6128 RESULT=skip
31247 17:05:11.022856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass>
31248 17:05:11.023287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6144 RESULT=pass
31250 17:05:11.061043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip>
31251 17:05:11.061420 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6144 RESULT=skip
31253 17:05:11.098584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip>
31254 17:05:11.099054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6144 RESULT=skip
31256 17:05:11.134101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass>
31257 17:05:11.134583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6160 RESULT=pass
31259 17:05:11.174096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip>
31260 17:05:11.174524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6160 RESULT=skip
31262 17:05:11.212590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip>
31263 17:05:11.213012 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6160 RESULT=skip
31265 17:05:11.250725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass>
31266 17:05:11.251179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6176 RESULT=pass
31268 17:05:11.290830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip>
31269 17:05:11.291607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6176 RESULT=skip
31271 17:05:11.329560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip>
31272 17:05:11.330007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6176 RESULT=skip
31274 17:05:11.366488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass>
31275 17:05:11.366926 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6192 RESULT=pass
31277 17:05:11.401569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip>
31278 17:05:11.402015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6192 RESULT=skip
31280 17:05:11.439320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip>
31281 17:05:11.439741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6192 RESULT=skip
31283 17:05:11.476186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass>
31284 17:05:11.476627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6208 RESULT=pass
31286 17:05:11.526385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip
31288 17:05:11.526833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6208 RESULT=skip>
31289 17:05:11.575046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip>
31290 17:05:11.575461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6208 RESULT=skip
31292 17:05:11.624786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass
31294 17:05:11.625411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6224 RESULT=pass>
31295 17:05:11.679405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip>
31296 17:05:11.679799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6224 RESULT=skip
31298 17:05:11.736607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip
31300 17:05:11.737094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6224 RESULT=skip>
31301 17:05:11.773976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass
31303 17:05:11.774401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6240 RESULT=pass>
31304 17:05:11.812712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip
31306 17:05:11.813293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6240 RESULT=skip>
31307 17:05:11.855835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip
31309 17:05:11.856510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6240 RESULT=skip>
31310 17:05:11.905937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass>
31311 17:05:11.906442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6256 RESULT=pass
31313 17:05:11.946579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip
31315 17:05:11.947224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6256 RESULT=skip>
31316 17:05:11.997434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip
31318 17:05:11.997910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6256 RESULT=skip>
31319 17:05:12.046644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass>
31320 17:05:12.047182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6272 RESULT=pass
31322 17:05:12.097306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip>
31323 17:05:12.097846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6272 RESULT=skip
31325 17:05:12.146186 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip
31327 17:05:12.146650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6272 RESULT=skip>
31328 17:05:12.197642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass>
31329 17:05:12.198078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6288 RESULT=pass
31331 17:05:12.247122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip>
31332 17:05:12.247586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6288 RESULT=skip
31334 17:05:12.294554 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip
31336 17:05:12.295193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6288 RESULT=skip>
31337 17:05:12.338357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass
31339 17:05:12.338809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6304 RESULT=pass>
31340 17:05:12.381707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip
31342 17:05:12.382183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6304 RESULT=skip>
31343 17:05:12.420389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip>
31344 17:05:12.420792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6304 RESULT=skip
31346 17:05:12.462470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass>
31347 17:05:12.462911 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6320 RESULT=pass
31349 17:05:12.513185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip>
31350 17:05:12.513700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6320 RESULT=skip
31352 17:05:12.561126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip
31354 17:05:12.561623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6320 RESULT=skip>
31355 17:05:12.598789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass
31357 17:05:12.599259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6336 RESULT=pass>
31358 17:05:12.634741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip>
31359 17:05:12.635181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6336 RESULT=skip
31361 17:05:12.672385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip>
31362 17:05:12.672812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6336 RESULT=skip
31364 17:05:12.723271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass>
31365 17:05:12.723666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6352 RESULT=pass
31367 17:05:12.771668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip
31369 17:05:12.772234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6352 RESULT=skip>
31370 17:05:12.810151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip>
31371 17:05:12.810597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6352 RESULT=skip
31373 17:05:12.848686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass>
31374 17:05:12.849140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6368 RESULT=pass
31376 17:05:12.887490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip
31378 17:05:12.888113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6368 RESULT=skip>
31379 17:05:12.926802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip
31381 17:05:12.927506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6368 RESULT=skip>
31382 17:05:12.970535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass>
31383 17:05:12.971057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6384 RESULT=pass
31385 17:05:13.013361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip>
31386 17:05:13.013816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6384 RESULT=skip
31388 17:05:13.055786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip
31390 17:05:13.056385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6384 RESULT=skip>
31391 17:05:13.106878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass
31393 17:05:13.107349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6400 RESULT=pass>
31394 17:05:13.153709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip>
31395 17:05:13.154108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6400 RESULT=skip
31397 17:05:13.192743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip
31399 17:05:13.193221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6400 RESULT=skip>
31400 17:05:13.233439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass>
31401 17:05:13.233877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6416 RESULT=pass
31403 17:05:13.274824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip
31405 17:05:13.275281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6416 RESULT=skip>
31406 17:05:13.315563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip>
31407 17:05:13.316053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6416 RESULT=skip
31409 17:05:13.354860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass>
31410 17:05:13.355361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6432 RESULT=pass
31412 17:05:13.392227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip>
31413 17:05:13.392675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6432 RESULT=skip
31415 17:05:13.440619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip
31417 17:05:13.441080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6432 RESULT=skip>
31418 17:05:13.529730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass>
31419 17:05:13.530315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6448 RESULT=pass
31421 17:05:13.574585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip>
31422 17:05:13.575136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6448 RESULT=skip
31424 17:05:13.612292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip>
31425 17:05:13.612765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6448 RESULT=skip
31427 17:05:13.649797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass>
31428 17:05:13.650238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6464 RESULT=pass
31430 17:05:13.686182 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip
31432 17:05:13.686644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6464 RESULT=skip>
31433 17:05:13.724773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip>
31434 17:05:13.725217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6464 RESULT=skip
31436 17:05:13.765837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass>
31437 17:05:13.766278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6480 RESULT=pass
31439 17:05:13.804685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip>
31440 17:05:13.805116 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6480 RESULT=skip
31442 17:05:13.851122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip>
31443 17:05:13.851547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6480 RESULT=skip
31445 17:05:13.897132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass
31447 17:05:13.897592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6496 RESULT=pass>
31448 17:05:13.937126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip>
31449 17:05:13.937624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6496 RESULT=skip
31451 17:05:13.975266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip>
31452 17:05:13.975751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6496 RESULT=skip
31454 17:05:14.010929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass>
31455 17:05:14.012780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6512 RESULT=pass
31457 17:05:14.054737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip
31459 17:05:14.055237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6512 RESULT=skip>
31460 17:05:14.107564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip
31462 17:05:14.108041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6512 RESULT=skip>
31463 17:05:14.152790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass
31465 17:05:14.153169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6528 RESULT=pass>
31466 17:05:14.198002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip>
31467 17:05:14.198482 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6528 RESULT=skip
31469 17:05:14.257341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip
31471 17:05:14.257732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6528 RESULT=skip>
31472 17:05:14.314314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass>
31473 17:05:14.314880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6544 RESULT=pass
31475 17:05:14.358721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip>
31476 17:05:14.359122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6544 RESULT=skip
31478 17:05:14.405114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip
31480 17:05:14.405611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6544 RESULT=skip>
31481 17:05:14.448466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass>
31482 17:05:14.448931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6560 RESULT=pass
31484 17:05:14.482924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip>
31485 17:05:14.483372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6560 RESULT=skip
31487 17:05:14.516345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip>
31488 17:05:14.516746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6560 RESULT=skip
31490 17:05:14.550768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass>
31491 17:05:14.551167 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6576 RESULT=pass
31493 17:05:14.587027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip>
31494 17:05:14.587455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6576 RESULT=skip
31496 17:05:14.627129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip>
31497 17:05:14.627578 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6576 RESULT=skip
31499 17:05:14.668421 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass
31501 17:05:14.669081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6592 RESULT=pass>
31502 17:05:14.706192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip>
31503 17:05:14.706648 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6592 RESULT=skip
31505 17:05:14.749772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip
31507 17:05:14.750236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6592 RESULT=skip>
31508 17:05:14.789662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass>
31509 17:05:14.790067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6608 RESULT=pass
31511 17:05:14.828884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip
31513 17:05:14.829303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6608 RESULT=skip>
31514 17:05:14.866994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip>
31515 17:05:14.867414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6608 RESULT=skip
31517 17:05:14.905559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass>
31518 17:05:14.906006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6624 RESULT=pass
31520 17:05:14.956240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip>
31521 17:05:14.956643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6624 RESULT=skip
31523 17:05:15.003424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip
31525 17:05:15.003953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6624 RESULT=skip>
31526 17:05:15.041263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass>
31527 17:05:15.041692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6640 RESULT=pass
31529 17:05:15.085051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip>
31530 17:05:15.085485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6640 RESULT=skip
31532 17:05:15.126119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip>
31533 17:05:15.126547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6640 RESULT=skip
31535 17:05:15.169876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass>
31536 17:05:15.170326 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6656 RESULT=pass
31538 17:05:15.207912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip
31540 17:05:15.208362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6656 RESULT=skip>
31541 17:05:15.243915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip
31543 17:05:15.244377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6656 RESULT=skip>
31544 17:05:15.285132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass>
31545 17:05:15.285549 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6672 RESULT=pass
31547 17:05:15.330156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip>
31548 17:05:15.330624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6672 RESULT=skip
31550 17:05:15.376812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip>
31551 17:05:15.377315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6672 RESULT=skip
31553 17:05:15.413883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass
31555 17:05:15.414297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6688 RESULT=pass>
31556 17:05:15.463150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip
31558 17:05:15.463675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6688 RESULT=skip>
31559 17:05:15.497295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip
31561 17:05:15.497674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6688 RESULT=skip>
31562 17:05:15.532476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass>
31563 17:05:15.532886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6704 RESULT=pass
31565 17:05:15.567465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip
31567 17:05:15.568220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6704 RESULT=skip>
31568 17:05:15.601316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip>
31569 17:05:15.601786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6704 RESULT=skip
31571 17:05:15.635254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass>
31572 17:05:15.635658 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6720 RESULT=pass
31574 17:05:15.671029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip>
31575 17:05:15.671441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6720 RESULT=skip
31577 17:05:15.706127 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip
31579 17:05:15.706593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6720 RESULT=skip>
31580 17:05:15.740879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass
31582 17:05:15.741347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6736 RESULT=pass>
31583 17:05:15.778249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip>
31584 17:05:15.778640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6736 RESULT=skip
31586 17:05:15.813978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip>
31587 17:05:15.814472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6736 RESULT=skip
31589 17:05:15.847616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass
31591 17:05:15.848402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6752 RESULT=pass>
31592 17:05:15.895866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip
31594 17:05:15.896425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6752 RESULT=skip>
31595 17:05:15.937714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip
31597 17:05:15.938176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6752 RESULT=skip>
31598 17:05:15.980635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass
31600 17:05:15.981243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6768 RESULT=pass>
31601 17:05:16.024483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip>
31602 17:05:16.025056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6768 RESULT=skip
31604 17:05:16.061186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip>
31605 17:05:16.061684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6768 RESULT=skip
31607 17:05:16.105454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass>
31608 17:05:16.105943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6784 RESULT=pass
31610 17:05:16.143220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip>
31611 17:05:16.143607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6784 RESULT=skip
31613 17:05:16.187279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip>
31614 17:05:16.187700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6784 RESULT=skip
31616 17:05:16.224228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass>
31617 17:05:16.224565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6800 RESULT=pass
31619 17:05:16.262309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip>
31620 17:05:16.262718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6800 RESULT=skip
31622 17:05:16.308302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip>
31623 17:05:16.308846 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6800 RESULT=skip
31625 17:05:16.345590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass>
31626 17:05:16.346027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6816 RESULT=pass
31628 17:05:16.384189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip>
31629 17:05:16.384625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6816 RESULT=skip
31631 17:05:16.420649 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip
31633 17:05:16.421062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6816 RESULT=skip>
31634 17:05:16.461278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass>
31635 17:05:16.461825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6832 RESULT=pass
31637 17:05:16.500464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip>
31638 17:05:16.500864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6832 RESULT=skip
31640 17:05:16.539801 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip
31642 17:05:16.540582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6832 RESULT=skip>
31643 17:05:16.576495 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass
31645 17:05:16.577141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6848 RESULT=pass>
31646 17:05:16.620593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip
31648 17:05:16.621248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6848 RESULT=skip>
31649 17:05:16.662739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip
31651 17:05:16.663311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6848 RESULT=skip>
31652 17:05:16.718387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass>
31653 17:05:16.718867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6864 RESULT=pass
31655 17:05:16.771313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip>
31656 17:05:16.771809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6864 RESULT=skip
31658 17:05:16.814251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip>
31659 17:05:16.814699 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6864 RESULT=skip
31661 17:05:16.853641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass
31663 17:05:16.854242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6880 RESULT=pass>
31664 17:05:16.890852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip>
31665 17:05:16.891322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6880 RESULT=skip
31667 17:05:16.934689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip>
31668 17:05:16.935191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6880 RESULT=skip
31670 17:05:16.974541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass>
31671 17:05:16.975087 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6896 RESULT=pass
31673 17:05:17.010788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip>
31674 17:05:17.011339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6896 RESULT=skip
31676 17:05:17.052462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip>
31677 17:05:17.052840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6896 RESULT=skip
31679 17:05:17.094966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass>
31680 17:05:17.095390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6912 RESULT=pass
31682 17:05:17.134425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip
31684 17:05:17.134912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6912 RESULT=skip>
31685 17:05:17.167206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip>
31686 17:05:17.167652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6912 RESULT=skip
31688 17:05:17.201468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass>
31689 17:05:17.201904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6928 RESULT=pass
31691 17:05:17.238968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip>
31692 17:05:17.239357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6928 RESULT=skip
31694 17:05:17.274440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip>
31695 17:05:17.274940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6928 RESULT=skip
31697 17:05:17.310608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass
31699 17:05:17.311173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6944 RESULT=pass>
31700 17:05:17.357408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip>
31701 17:05:17.357878 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6944 RESULT=skip
31703 17:05:17.400894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip>
31704 17:05:17.401339 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6944 RESULT=skip
31706 17:05:17.436345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass>
31707 17:05:17.436913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6960 RESULT=pass
31709 17:05:17.472131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip
31711 17:05:17.472568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6960 RESULT=skip>
31712 17:05:17.517191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip>
31713 17:05:17.517600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6960 RESULT=skip
31715 17:05:17.552489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass>
31716 17:05:17.553004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6976 RESULT=pass
31718 17:05:17.586807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip>
31719 17:05:17.587334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6976 RESULT=skip
31721 17:05:17.622498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip>
31722 17:05:17.622912 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6976 RESULT=skip
31724 17:05:17.657481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass
31726 17:05:17.657951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_6992 RESULT=pass>
31727 17:05:17.695660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip>
31728 17:05:17.696091 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_6992 RESULT=skip
31730 17:05:17.730688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip>
31731 17:05:17.731145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_6992 RESULT=skip
31733 17:05:17.767329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass>
31734 17:05:17.767817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7008 RESULT=pass
31736 17:05:17.806306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip>
31737 17:05:17.806734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7008 RESULT=skip
31739 17:05:17.846575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip>
31740 17:05:17.847001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7008 RESULT=skip
31742 17:05:17.882636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass>
31743 17:05:17.883029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7024 RESULT=pass
31745 17:05:17.917681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip>
31746 17:05:17.918171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7024 RESULT=skip
31748 17:05:17.953477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip
31750 17:05:17.954237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7024 RESULT=skip>
31751 17:05:17.989161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass>
31752 17:05:17.989669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7040 RESULT=pass
31754 17:05:18.024856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip>
31755 17:05:18.025317 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7040 RESULT=skip
31757 17:05:18.059101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip>
31758 17:05:18.059577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7040 RESULT=skip
31760 17:05:18.093812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass
31762 17:05:18.094403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7056 RESULT=pass>
31763 17:05:18.133883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip>
31764 17:05:18.134430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7056 RESULT=skip
31766 17:05:18.172570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip>
31767 17:05:18.173039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7056 RESULT=skip
31769 17:05:18.213105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass>
31770 17:05:18.213579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7072 RESULT=pass
31772 17:05:18.250902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip>
31773 17:05:18.251324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7072 RESULT=skip
31775 17:05:18.290235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip>
31776 17:05:18.290638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7072 RESULT=skip
31778 17:05:18.333807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass
31780 17:05:18.334264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7088 RESULT=pass>
31781 17:05:18.371429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip
31783 17:05:18.371910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7088 RESULT=skip>
31784 17:05:18.411118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip>
31785 17:05:18.411539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7088 RESULT=skip
31787 17:05:18.469292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass>
31788 17:05:18.469686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7104 RESULT=pass
31790 17:05:18.519104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip>
31791 17:05:18.519540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7104 RESULT=skip
31793 17:05:18.570242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip>
31794 17:05:18.570673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7104 RESULT=skip
31796 17:05:18.629808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass>
31797 17:05:18.630297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7120 RESULT=pass
31799 17:05:18.669178 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip
31801 17:05:18.669619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7120 RESULT=skip>
31802 17:05:18.710221 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip
31804 17:05:18.710590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7120 RESULT=skip>
31805 17:05:18.757758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass>
31806 17:05:18.758103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7136 RESULT=pass
31808 17:05:18.793355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip>
31809 17:05:18.793779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7136 RESULT=skip
31811 17:05:18.830465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip
31813 17:05:18.830904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7136 RESULT=skip>
31814 17:05:18.869919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass>
31815 17:05:18.870328 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7152 RESULT=pass
31817 17:05:18.914572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip
31819 17:05:18.915048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7152 RESULT=skip>
31820 17:05:18.950111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip
31822 17:05:18.950768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7152 RESULT=skip>
31823 17:05:18.984256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass>
31824 17:05:18.984739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7168 RESULT=pass
31826 17:05:19.018387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip
31828 17:05:19.019092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7168 RESULT=skip>
31829 17:05:19.056675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip>
31830 17:05:19.057250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7168 RESULT=skip
31832 17:05:19.108948 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass
31834 17:05:19.109328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7184 RESULT=pass>
31835 17:05:19.159777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip
31837 17:05:19.160250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7184 RESULT=skip>
31838 17:05:19.204531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip>
31839 17:05:19.204913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7184 RESULT=skip
31841 17:05:19.240848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass>
31842 17:05:19.241291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7200 RESULT=pass
31844 17:05:19.278976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip>
31845 17:05:19.279407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7200 RESULT=skip
31847 17:05:19.313513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip
31849 17:05:19.314093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7200 RESULT=skip>
31850 17:05:19.349083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass
31852 17:05:19.349669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7216 RESULT=pass>
31853 17:05:19.385611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip>
31854 17:05:19.385981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7216 RESULT=skip
31856 17:05:19.425885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip>
31857 17:05:19.426259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7216 RESULT=skip
31859 17:05:19.462080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass
31861 17:05:19.462447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7232 RESULT=pass>
31862 17:05:19.497166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip
31864 17:05:19.497581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7232 RESULT=skip>
31865 17:05:19.531100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip>
31866 17:05:19.531510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7232 RESULT=skip
31868 17:05:19.571503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass>
31869 17:05:19.571896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7248 RESULT=pass
31871 17:05:19.608861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip>
31872 17:05:19.609255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7248 RESULT=skip
31874 17:05:19.643368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip
31876 17:05:19.643724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7248 RESULT=skip>
31877 17:05:19.679729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass
31879 17:05:19.680204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7264 RESULT=pass>
31880 17:05:19.717043 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip
31882 17:05:19.717748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7264 RESULT=skip>
31883 17:05:19.765029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip>
31884 17:05:19.765479 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7264 RESULT=skip
31886 17:05:19.809152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass>
31887 17:05:19.809577 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7280 RESULT=pass
31889 17:05:19.849388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip>
31890 17:05:19.849830 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7280 RESULT=skip
31892 17:05:19.895861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip
31894 17:05:19.896331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7280 RESULT=skip>
31895 17:05:19.943278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass>
31896 17:05:19.943705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7296 RESULT=pass
31898 17:05:19.988430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip
31900 17:05:19.988835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7296 RESULT=skip>
31901 17:05:20.027286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip
31903 17:05:20.028053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7296 RESULT=skip>
31904 17:05:20.076436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass
31906 17:05:20.076900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7312 RESULT=pass>
31907 17:05:20.114220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip>
31908 17:05:20.114647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7312 RESULT=skip
31910 17:05:20.158560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip>
31911 17:05:20.159001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7312 RESULT=skip
31913 17:05:20.209300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass
31915 17:05:20.209890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7328 RESULT=pass>
31916 17:05:20.263884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip
31918 17:05:20.264453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7328 RESULT=skip>
31919 17:05:20.305441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip>
31920 17:05:20.305856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7328 RESULT=skip
31922 17:05:20.345385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass
31924 17:05:20.345828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7344 RESULT=pass>
31925 17:05:20.389855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip>
31926 17:05:20.390245 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7344 RESULT=skip
31928 17:05:20.446244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip>
31929 17:05:20.446803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7344 RESULT=skip
31931 17:05:20.485903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass>
31932 17:05:20.486346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7360 RESULT=pass
31934 17:05:20.530855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip>
31935 17:05:20.531255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7360 RESULT=skip
31937 17:05:20.590266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip
31939 17:05:20.590920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7360 RESULT=skip>
31940 17:05:20.643883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass
31942 17:05:20.644282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7376 RESULT=pass>
31943 17:05:20.686391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip>
31944 17:05:20.686825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7376 RESULT=skip
31946 17:05:20.739084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip>
31947 17:05:20.739533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7376 RESULT=skip
31949 17:05:20.784093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass>
31950 17:05:20.784551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7392 RESULT=pass
31952 17:05:20.826089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip>
31953 17:05:20.826530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7392 RESULT=skip
31955 17:05:20.862811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip>
31956 17:05:20.863266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7392 RESULT=skip
31958 17:05:20.909851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass>
31959 17:05:20.910285 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7408 RESULT=pass
31961 17:05:20.962359 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip
31963 17:05:20.963142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7408 RESULT=skip>
31964 17:05:21.005061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip>
31965 17:05:21.005508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7408 RESULT=skip
31967 17:05:21.045882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass>
31968 17:05:21.046360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7424 RESULT=pass
31970 17:05:21.083622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip
31972 17:05:21.084115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7424 RESULT=skip>
31973 17:05:21.126252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip>
31974 17:05:21.126954 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7424 RESULT=skip
31976 17:05:21.165604 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass
31978 17:05:21.166084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7440 RESULT=pass>
31979 17:05:21.206135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip>
31980 17:05:21.206555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7440 RESULT=skip
31982 17:05:21.249663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip>
31983 17:05:21.250085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7440 RESULT=skip
31985 17:05:21.295892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass
31987 17:05:21.296268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7456 RESULT=pass>
31988 17:05:21.332738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip>
31989 17:05:21.333214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7456 RESULT=skip
31991 17:05:21.369198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip>
31992 17:05:21.369682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7456 RESULT=skip
31994 17:05:21.405352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass
31996 17:05:21.405936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7472 RESULT=pass>
31997 17:05:21.441455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip>
31998 17:05:21.441921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7472 RESULT=skip
32000 17:05:21.478305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip>
32001 17:05:21.478775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7472 RESULT=skip
32003 17:05:21.512833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass>
32004 17:05:21.513290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7488 RESULT=pass
32006 17:05:21.554599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip>
32007 17:05:21.554974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7488 RESULT=skip
32009 17:05:21.590491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip
32011 17:05:21.591207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7488 RESULT=skip>
32012 17:05:21.626058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass
32014 17:05:21.626622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7504 RESULT=pass>
32015 17:05:21.661438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip>
32016 17:05:21.661937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7504 RESULT=skip
32018 17:05:21.697113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip>
32019 17:05:21.697638 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7504 RESULT=skip
32021 17:05:21.734121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass>
32022 17:05:21.734603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7520 RESULT=pass
32024 17:05:21.771778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip
32026 17:05:21.772167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7520 RESULT=skip>
32027 17:05:21.810521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip>
32028 17:05:21.810893 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7520 RESULT=skip
32030 17:05:21.849877 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass
32032 17:05:21.850334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7536 RESULT=pass>
32033 17:05:21.885382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip>
32034 17:05:21.885942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7536 RESULT=skip
32036 17:05:21.922030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip
32038 17:05:21.922768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7536 RESULT=skip>
32039 17:05:21.956859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass>
32040 17:05:21.957236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7552 RESULT=pass
32042 17:05:21.991427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip
32044 17:05:21.991907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7552 RESULT=skip>
32045 17:05:22.025923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip>
32046 17:05:22.026340 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7552 RESULT=skip
32048 17:05:22.063988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass
32050 17:05:22.064464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7568 RESULT=pass>
32051 17:05:22.100357 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip
32053 17:05:22.100760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7568 RESULT=skip>
32054 17:05:22.134527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip>
32055 17:05:22.134900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7568 RESULT=skip
32057 17:05:22.170609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass
32059 17:05:22.170990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7584 RESULT=pass>
32060 17:05:22.208960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip
32062 17:05:22.209349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7584 RESULT=skip>
32063 17:05:22.246644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip>
32064 17:05:22.247068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7584 RESULT=skip
32066 17:05:22.285802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass>
32067 17:05:22.286284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7600 RESULT=pass
32069 17:05:22.322969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip>
32070 17:05:22.323405 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7600 RESULT=skip
32072 17:05:22.359583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip>
32073 17:05:22.360067 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7600 RESULT=skip
32075 17:05:22.397689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass>
32076 17:05:22.398181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7616 RESULT=pass
32078 17:05:22.438154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip
32080 17:05:22.438619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7616 RESULT=skip>
32081 17:05:22.477712 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip
32083 17:05:22.478173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7616 RESULT=skip>
32084 17:05:22.517898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass>
32085 17:05:22.518325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7632 RESULT=pass
32087 17:05:22.554617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip
32089 17:05:22.555087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7632 RESULT=skip>
32090 17:05:22.592258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip>
32091 17:05:22.592679 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7632 RESULT=skip
32093 17:05:22.639447 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass
32095 17:05:22.639923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7648 RESULT=pass>
32096 17:05:22.677545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip>
32097 17:05:22.677959 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7648 RESULT=skip
32099 17:05:22.716671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip>
32100 17:05:22.717066 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7648 RESULT=skip
32102 17:05:22.750741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass>
32103 17:05:22.751219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7664 RESULT=pass
32105 17:05:22.785605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip>
32106 17:05:22.786179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7664 RESULT=skip
32108 17:05:22.821767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip>
32109 17:05:22.822156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7664 RESULT=skip
32111 17:05:22.856703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass
32113 17:05:22.857163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7680 RESULT=pass>
32114 17:05:22.892410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip
32116 17:05:22.892864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7680 RESULT=skip>
32117 17:05:22.931852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip
32119 17:05:22.932625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7680 RESULT=skip>
32120 17:05:22.976714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass>
32121 17:05:22.977258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7696 RESULT=pass
32123 17:05:23.017774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip>
32124 17:05:23.018184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7696 RESULT=skip
32126 17:05:23.054170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip>
32127 17:05:23.054582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7696 RESULT=skip
32129 17:05:23.099240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass>
32130 17:05:23.099741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7712 RESULT=pass
32132 17:05:23.145192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip>
32133 17:05:23.145607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7712 RESULT=skip
32135 17:05:23.191154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip>
32136 17:05:23.191583 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7712 RESULT=skip
32138 17:05:23.234870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass>
32139 17:05:23.235308 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7728 RESULT=pass
32141 17:05:23.270500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip>
32142 17:05:23.270981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7728 RESULT=skip
32144 17:05:23.306179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip>
32145 17:05:23.306664 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7728 RESULT=skip
32147 17:05:23.341696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass>
32148 17:05:23.342220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7744 RESULT=pass
32150 17:05:23.378254 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip
32152 17:05:23.378746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7744 RESULT=skip>
32153 17:05:23.413578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip>
32154 17:05:23.414024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7744 RESULT=skip
32156 17:05:23.449949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass>
32157 17:05:23.450363 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7760 RESULT=pass
32159 17:05:23.484586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip>
32160 17:05:23.485070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7760 RESULT=skip
32162 17:05:23.525371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip
32164 17:05:23.526087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7760 RESULT=skip>
32165 17:05:23.569555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass>
32166 17:05:23.569997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7776 RESULT=pass
32168 17:05:23.605037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip>
32169 17:05:23.605438 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7776 RESULT=skip
32171 17:05:23.641725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip
32173 17:05:23.642204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7776 RESULT=skip>
32174 17:05:23.676905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass>
32175 17:05:23.677384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7792 RESULT=pass
32177 17:05:23.726262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip
32179 17:05:23.726873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7792 RESULT=skip>
32180 17:05:23.773249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip>
32181 17:05:23.773689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7792 RESULT=skip
32183 17:05:23.808596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass
32185 17:05:23.809069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7808 RESULT=pass>
32186 17:05:23.844569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip>
32187 17:05:23.845021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7808 RESULT=skip
32189 17:05:23.878975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip
32191 17:05:23.879448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7808 RESULT=skip>
32192 17:05:23.912674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass
32194 17:05:23.913138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7824 RESULT=pass>
32195 17:05:23.948552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip>
32196 17:05:23.949057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7824 RESULT=skip
32198 17:05:23.983001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip
32200 17:05:23.983463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7824 RESULT=skip>
32201 17:05:24.017339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass>
32202 17:05:24.017786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7840 RESULT=pass
32204 17:05:24.052402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip
32206 17:05:24.052864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7840 RESULT=skip>
32207 17:05:24.099727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip
32209 17:05:24.100522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7840 RESULT=skip>
32210 17:05:24.137629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass
32212 17:05:24.138092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7856 RESULT=pass>
32213 17:05:24.175356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip
32215 17:05:24.175840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7856 RESULT=skip>
32216 17:05:24.213895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip>
32217 17:05:24.214386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7856 RESULT=skip
32219 17:05:24.249931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass
32221 17:05:24.250324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7872 RESULT=pass>
32222 17:05:24.284038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip>
32223 17:05:24.284445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7872 RESULT=skip
32225 17:05:24.318019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip
32227 17:05:24.318384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7872 RESULT=skip>
32228 17:05:24.353142 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass
32230 17:05:24.353722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7888 RESULT=pass>
32231 17:05:24.387393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip
32233 17:05:24.387868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7888 RESULT=skip>
32234 17:05:24.422000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip>
32235 17:05:24.422417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7888 RESULT=skip
32237 17:05:24.457844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass>
32238 17:05:24.458259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7904 RESULT=pass
32240 17:05:24.500414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip>
32241 17:05:24.500867 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7904 RESULT=skip
32243 17:05:24.550802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip>
32244 17:05:24.551246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7904 RESULT=skip
32246 17:05:24.601020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass
32248 17:05:24.601501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7920 RESULT=pass>
32249 17:05:24.649984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip>
32250 17:05:24.650562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7920 RESULT=skip
32252 17:05:24.690151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip
32254 17:05:24.690567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7920 RESULT=skip>
32255 17:05:24.726376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass>
32256 17:05:24.726744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7936 RESULT=pass
32258 17:05:24.764337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip>
32259 17:05:24.764785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7936 RESULT=skip
32261 17:05:24.815459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip>
32262 17:05:24.815847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7936 RESULT=skip
32264 17:05:24.868364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass>
32265 17:05:24.868785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7952 RESULT=pass
32267 17:05:24.917466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip
32269 17:05:24.917943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7952 RESULT=skip>
32270 17:05:24.964719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip>
32271 17:05:24.965148 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7952 RESULT=skip
32273 17:05:25.020634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass>
32274 17:05:25.021150 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7968 RESULT=pass
32276 17:05:25.075391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip
32278 17:05:25.075843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7968 RESULT=skip>
32279 17:05:25.123180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip
32281 17:05:25.123603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7968 RESULT=skip>
32282 17:05:25.158521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass
32284 17:05:25.158939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_7984 RESULT=pass>
32285 17:05:25.192802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip>
32286 17:05:25.193179 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_7984 RESULT=skip
32288 17:05:25.229218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip>
32289 17:05:25.229697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_7984 RESULT=skip
32291 17:05:25.250541 <47>[ 379.351396] systemd-journald[109]: Sent WATCHDOG=1 notification.
32292 17:05:25.285656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass>
32293 17:05:25.286173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8000 RESULT=pass
32295 17:05:25.331235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip
32297 17:05:25.331806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8000 RESULT=skip>
32298 17:05:25.370789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip>
32299 17:05:25.371330 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8000 RESULT=skip
32301 17:05:25.411591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass
32303 17:05:25.412356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8016 RESULT=pass>
32304 17:05:25.447446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip>
32305 17:05:25.447816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8016 RESULT=skip
32307 17:05:25.483616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip
32309 17:05:25.484227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8016 RESULT=skip>
32310 17:05:25.519135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass>
32311 17:05:25.519565 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8032 RESULT=pass
32313 17:05:25.564515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip
32315 17:05:25.564983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8032 RESULT=skip>
32316 17:05:25.613532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip>
32317 17:05:25.613925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8032 RESULT=skip
32319 17:05:25.662560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass>
32320 17:05:25.662999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8048 RESULT=pass
32322 17:05:25.710959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip>
32323 17:05:25.711385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8048 RESULT=skip
32325 17:05:25.762300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip
32327 17:05:25.762798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8048 RESULT=skip>
32328 17:05:25.810436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass
32330 17:05:25.810810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8064 RESULT=pass>
32331 17:05:25.858072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip>
32332 17:05:25.858563 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8064 RESULT=skip
32334 17:05:25.905714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip>
32335 17:05:25.906130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8064 RESULT=skip
32337 17:05:25.952879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass>
32338 17:05:25.953307 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8080 RESULT=pass
32340 17:05:26.002342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip>
32341 17:05:26.002833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8080 RESULT=skip
32343 17:05:26.042244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip>
32344 17:05:26.042690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8080 RESULT=skip
32346 17:05:26.082327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass>
32347 17:05:26.082853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8096 RESULT=pass
32349 17:05:26.123796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip
32351 17:05:26.124558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8096 RESULT=skip>
32352 17:05:26.168805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip
32354 17:05:26.169309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8096 RESULT=skip>
32355 17:05:26.215010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass>
32356 17:05:26.215439 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8112 RESULT=pass
32358 17:05:26.266206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip
32360 17:05:26.266922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8112 RESULT=skip>
32361 17:05:26.313298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip>
32362 17:05:26.313675 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8112 RESULT=skip
32364 17:05:26.361181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass>
32365 17:05:26.361627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8128 RESULT=pass
32367 17:05:26.400490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip
32369 17:05:26.400966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8128 RESULT=skip>
32370 17:05:26.447861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip>
32371 17:05:26.448295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8128 RESULT=skip
32373 17:05:26.494230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass>
32374 17:05:26.494787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8144 RESULT=pass
32376 17:05:26.538162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip
32378 17:05:26.538633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8144 RESULT=skip>
32379 17:05:26.585095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip
32381 17:05:26.585878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8144 RESULT=skip>
32382 17:05:26.630861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass>
32383 17:05:26.631304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8160 RESULT=pass
32385 17:05:26.678714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip>
32386 17:05:26.679211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8160 RESULT=skip
32388 17:05:26.727267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip>
32389 17:05:26.727792 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8160 RESULT=skip
32391 17:05:26.770577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass>
32392 17:05:26.770994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8176 RESULT=pass
32394 17:05:26.811126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip>
32395 17:05:26.811574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8176 RESULT=skip
32397 17:05:26.847415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip>
32398 17:05:26.847844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8176 RESULT=skip
32400 17:05:26.883426 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass
32402 17:05:26.883906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Set_VL_8192 RESULT=pass>
32403 17:05:26.920909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip>
32404 17:05:26.921351 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Disabled_ZA_for_VL_8192 RESULT=skip
32406 17:05:26.961212 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip
32408 17:05:26.962011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_Get_and_set_data_for_VL_8192 RESULT=skip>
32409 17:05:27.010563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=pass>
32410 17:05:27.010989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=pass
32412 17:05:27.050637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass>
32413 17:05:27.051021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory RESULT=pass
32415 17:05:27.098765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass>
32416 17:05:27.099262 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory RESULT=pass
32418 17:05:27.141964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass
32420 17:05:27.142345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory RESULT=pass>
32421 17:05:27.182920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass>
32422 17:05:27.183470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory RESULT=pass
32424 17:05:27.219608 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32426 17:05:27.220422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32427 17:05:27.258030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32428 17:05:27.258437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32430 17:05:27.305364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32431 17:05:27.305754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32433 17:05:27.339859 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass
32435 17:05:27.340612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory RESULT=pass>
32436 17:05:27.374122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass>
32437 17:05:27.374504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory RESULT=pass
32439 17:05:27.410573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass>
32440 17:05:27.411114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory RESULT=pass
32442 17:05:27.454633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail>
32443 17:05:27.455065 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory RESULT=fail
32445 17:05:27.500015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail
32447 17:05:27.500634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory RESULT=fail>
32448 17:05:27.545055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass>
32449 17:05:27.545455 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory RESULT=pass
32451 17:05:27.592298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail>
32452 17:05:27.592724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory RESULT=fail
32454 17:05:27.638284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail
32456 17:05:27.638673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory RESULT=fail>
32457 17:05:27.687702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass
32459 17:05:27.688139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory RESULT=pass>
32460 17:05:27.736647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32461 17:05:27.737157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32463 17:05:27.775737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32465 17:05:27.776235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32466 17:05:27.824678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass>
32467 17:05:27.825106 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory RESULT=pass
32469 17:05:27.876685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass>
32470 17:05:27.877165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory RESULT=pass
32472 17:05:27.931695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail
32474 17:05:27.932366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=fail>
32475 17:05:27.974328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32476 17:05:27.974774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32478 17:05:28.013198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32480 17:05:28.013819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32481 17:05:28.052693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32482 17:05:28.053121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32484 17:05:28.101048 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32486 17:05:28.101465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32487 17:05:28.152488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32488 17:05:28.152943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32490 17:05:28.190270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32491 17:05:28.190702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32493 17:05:28.231828 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail
32495 17:05:28.232295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory RESULT=fail>
32496 17:05:28.277081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail>
32497 17:05:28.277503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory RESULT=fail
32499 17:05:28.325431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32500 17:05:28.325881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32502 17:05:28.374248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail
32504 17:05:28.374718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory RESULT=fail>
32505 17:05:28.423333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32506 17:05:28.423777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32508 17:05:28.472998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail
32510 17:05:28.473472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory RESULT=fail>
32511 17:05:28.520100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=fail>
32512 17:05:28.520492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=fail
32514 17:05:28.561122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail>
32515 17:05:28.561546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=fail
32517 17:05:28.603079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=fail>
32518 17:05:28.603509 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=fail
32520 17:05:28.639077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32521 17:05:28.639508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32523 17:05:28.688929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32524 17:05:28.689380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32526 17:05:28.736691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass
32528 17:05:28.737169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off RESULT=pass>
32529 17:05:28.775980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass
32531 17:05:28.776453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off RESULT=pass>
32532 17:05:28.821051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32533 17:05:28.821474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32535 17:05:28.891111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32537 17:05:28.891599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32538 17:05:28.939335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32539 17:05:28.939757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32541 17:05:28.979136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32542 17:05:28.979580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32544 17:05:29.019237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32545 17:05:29.019652 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32547 17:05:29.067833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32549 17:05:29.068235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32550 17:05:29.113780 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32552 17:05:29.114169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32553 17:05:29.163104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32554 17:05:29.163536 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32556 17:05:29.201458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32557 17:05:29.201899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32559 17:05:29.245004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32560 17:05:29.245388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32562 17:05:29.282759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32564 17:05:29.283129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32565 17:05:29.332646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32566 17:05:29.332998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32568 17:05:29.382170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32569 17:05:29.382562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32571 17:05:29.432639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32572 17:05:29.433055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32574 17:05:29.480572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail>
32575 17:05:29.481003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on RESULT=fail
32577 17:05:29.523694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail
32579 17:05:29.524373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on RESULT=fail>
32580 17:05:29.560784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail
32582 17:05:29.561447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory RESULT=fail>
32583 17:05:29.597399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail>
32584 17:05:29.597914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory RESULT=fail
32586 17:05:29.633077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=fail>
32587 17:05:29.633579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=fail
32589 17:05:29.668598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
32590 17:05:29.669124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
32592 17:05:29.703668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
32593 17:05:29.704241 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
32595 17:05:29.738711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass>
32596 17:05:29.739126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=pass
32598 17:05:29.782195 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass
32600 17:05:29.782675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=pass>
32601 17:05:29.831546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass>
32602 17:05:29.831997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=pass
32604 17:05:29.874587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
32605 17:05:29.875030 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
32607 17:05:29.913394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail>
32608 17:05:29.913847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode RESULT=fail
32610 17:05:29.954968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail
32612 17:05:29.955364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode RESULT=fail>
32613 17:05:29.997410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass>
32614 17:05:29.997797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode RESULT=pass
32616 17:05:30.049299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail>
32617 17:05:30.049750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode RESULT=fail
32619 17:05:30.096236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail>
32620 17:05:30.096647 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=fail
32622 17:05:30.148303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32624 17:05:30.148759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32625 17:05:30.189301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32626 17:05:30.189752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32628 17:05:30.225407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32629 17:05:30.225842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32631 17:05:30.261655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32632 17:05:30.262085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32634 17:05:30.296914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32635 17:05:30.297341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32637 17:05:30.331716 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32639 17:05:30.332119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32640 17:05:30.374093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32641 17:05:30.374502 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32643 17:05:30.420907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32644 17:05:30.421313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32646 17:05:30.469706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32647 17:05:30.470138 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32649 17:05:30.514303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32650 17:05:30.514735 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32652 17:05:30.560928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32654 17:05:30.561418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32655 17:05:30.603260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32656 17:05:30.603695 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32658 17:05:30.644831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32659 17:05:30.645303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32661 17:05:30.693722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32663 17:05:30.694484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32664 17:05:30.750024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32666 17:05:30.750515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32667 17:05:30.786493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32668 17:05:30.786916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32670 17:05:30.823593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32672 17:05:30.824005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32673 17:05:30.871758 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32675 17:05:30.872222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32676 17:05:30.909356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32677 17:05:30.909991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32679 17:05:30.943955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32681 17:05:30.944417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32682 17:05:30.980935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32683 17:05:30.981404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32685 17:05:31.017129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32687 17:05:31.017592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32688 17:05:31.055149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32689 17:05:31.055574 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32691 17:05:31.110668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32692 17:05:31.111105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32694 17:05:31.152320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32695 17:05:31.152773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32697 17:05:31.198424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32698 17:05:31.198847 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32700 17:05:31.240905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32701 17:05:31.241336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32703 17:05:31.281542 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32705 17:05:31.282080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32706 17:05:31.325464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32708 17:05:31.325940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32709 17:05:31.367173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32710 17:05:31.367635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32712 17:05:31.411072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32713 17:05:31.411508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32715 17:05:31.454722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32717 17:05:31.455154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32718 17:05:31.498999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32719 17:05:31.499391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32721 17:05:31.541910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32722 17:05:31.542333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32724 17:05:31.585346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32726 17:05:31.585790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32727 17:05:31.624354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32728 17:05:31.624772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32730 17:05:31.670798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32731 17:05:31.671187 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32733 17:05:31.720390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32734 17:05:31.720832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32736 17:05:31.756943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32737 17:05:31.757368 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32739 17:05:31.793552 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32741 17:05:31.794032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32742 17:05:31.829799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32743 17:05:31.830223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32745 17:05:31.880070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32747 17:05:31.880659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32748 17:05:31.931731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32750 17:05:31.932322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32751 17:05:31.970143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32752 17:05:31.970589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32754 17:05:32.011023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32755 17:05:32.011496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32757 17:05:32.056984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32758 17:05:32.057453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32760 17:05:32.105436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32761 17:05:32.105853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32763 17:05:32.154653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32765 17:05:32.155396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32766 17:05:32.206527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32767 17:05:32.206962 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32769 17:05:32.246016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32770 17:05:32.246437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32772 17:05:32.289706 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32774 17:05:32.290167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32775 17:05:32.326342 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32777 17:05:32.326836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32778 17:05:32.366054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32779 17:05:32.366437 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32781 17:05:32.401744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32782 17:05:32.402224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32784 17:05:32.442201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32785 17:05:32.442718 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32787 17:05:32.487923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32789 17:05:32.488386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32790 17:05:32.529532 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass
32792 17:05:32.530014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0 RESULT=pass>
32793 17:05:32.567816 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass
32795 17:05:32.568456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16 RESULT=pass>
32796 17:05:32.605788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass>
32797 17:05:32.606263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0 RESULT=pass
32799 17:05:32.649209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass>
32800 17:05:32.649754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16 RESULT=pass
32802 17:05:32.686939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass>
32803 17:05:32.687398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0 RESULT=pass
32805 17:05:32.725397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass>
32806 17:05:32.725765 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16 RESULT=pass
32808 17:05:32.764097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass
32810 17:05:32.764565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0 RESULT=pass>
32811 17:05:32.803905 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass
32813 17:05:32.804467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16 RESULT=pass>
32814 17:05:32.844556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=pass
32816 17:05:32.845020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=pass>
32817 17:05:32.880786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass
32819 17:05:32.881526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=pass>
32820 17:05:32.916394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass>
32821 17:05:32.916863 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=pass
32823 17:05:32.952472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass>
32824 17:05:32.952888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=pass
32826 17:05:32.994377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass>
32827 17:05:32.994866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=pass
32829 17:05:33.030867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass>
32830 17:05:33.031290 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=pass
32832 17:05:33.071088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass>
32833 17:05:33.071594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=pass
32835 17:05:33.113961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass>
32836 17:05:33.114389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=pass
32838 17:05:33.154398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass>
32839 17:05:33.154819 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=pass
32841 17:05:33.197309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass>
32842 17:05:33.197732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=pass
32844 17:05:33.233848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass>
32845 17:05:33.234291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=pass
32847 17:05:33.271829 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass
32849 17:05:33.272299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=pass>
32850 17:05:33.309005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass>
32851 17:05:33.309430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=pass
32853 17:05:33.351453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass
32855 17:05:33.351996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32856 17:05:33.391951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass
32858 17:05:33.392688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32859 17:05:33.430927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass
32861 17:05:33.431400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=pass>
32862 17:05:33.468353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass>
32863 17:05:33.468803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=pass
32865 17:05:33.506710 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass
32867 17:05:33.507171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=pass>
32868 17:05:33.547316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass>
32869 17:05:33.547692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=pass
32871 17:05:33.584698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
32872 17:05:33.585155 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
32874 17:05:33.622677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass>
32875 17:05:33.623124 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=pass
32877 17:05:33.660332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass
32879 17:05:33.660810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=pass>
32880 17:05:33.697115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass>
32881 17:05:33.697559 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=pass
32883 17:05:33.734272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass>
32884 17:05:33.734713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=pass
32886 17:05:33.770920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass>
32887 17:05:33.771355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=pass
32889 17:05:33.810726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass
32891 17:05:33.811198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=pass>
32892 17:05:33.853036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass>
32893 17:05:33.853700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=pass
32895 17:05:33.894876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass>
32896 17:05:33.895300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=pass
32898 17:05:33.933208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass
32900 17:05:33.933687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=pass>
32901 17:05:34.002266 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass
32903 17:05:34.002731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=pass>
32904 17:05:34.045628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass>
32905 17:05:34.046060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=pass
32907 17:05:34.086566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass>
32908 17:05:34.087042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=pass
32910 17:05:34.129117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass>
32911 17:05:34.129545 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=pass
32913 17:05:34.186404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass
32915 17:05:34.186855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=pass>
32916 17:05:34.226035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass>
32917 17:05:34.226445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=pass
32919 17:05:34.264965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass>
32920 17:05:34.265402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=pass
32922 17:05:34.302383 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass
32924 17:05:34.302849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=pass>
32925 17:05:34.341589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass>
32926 17:05:34.342024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=pass
32928 17:05:34.380989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
32929 17:05:34.381425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
32931 17:05:34.416967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
32932 17:05:34.417507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
32934 17:05:34.466587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass>
32935 17:05:34.467145 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=pass
32937 17:05:34.504444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
32938 17:05:34.504969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
32940 17:05:34.540726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
32942 17:05:34.541132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
32943 17:05:34.585978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
32945 17:05:34.586376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
32946 17:05:34.623619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
32948 17:05:34.624032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
32949 17:05:34.660168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
32950 17:05:34.660580 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
32952 17:05:34.711671 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass
32954 17:05:34.712284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=pass>
32955 17:05:34.750363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
32956 17:05:34.750799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
32958 17:05:34.797366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass>
32959 17:05:34.797790 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=pass
32961 17:05:34.835314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
32963 17:05:34.835761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
32964 17:05:34.870895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass>
32965 17:05:34.871303 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=pass
32967 17:05:34.925680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
32968 17:05:34.926203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
32970 17:05:34.977283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass>
32971 17:05:34.977805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=pass
32973 17:05:35.016311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
32974 17:05:35.016803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
32976 17:05:35.057797 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass
32978 17:05:35.058424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=pass>
32979 17:05:35.103527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
32980 17:05:35.104051 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
32982 17:05:35.162548 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass
32984 17:05:35.163079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=pass>
32985 17:05:35.199220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
32986 17:05:35.199615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
32988 17:05:35.237506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass>
32989 17:05:35.237892 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=pass
32991 17:05:35.275457 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
32993 17:05:35.275855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
32994 17:05:35.315760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass
32996 17:05:35.316197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=pass>
32997 17:05:35.355804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
32999 17:05:35.356139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
33000 17:05:35.392734 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass
33002 17:05:35.393182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=pass>
33003 17:05:35.430539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
33004 17:05:35.430908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
33006 17:05:35.472189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass
33008 17:05:35.472636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=pass>
33009 17:05:35.517120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
33010 17:05:35.517596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
33012 17:05:35.553792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
33013 17:05:35.554199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
33015 17:05:35.590047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
33016 17:05:35.590393 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
33018 17:05:35.630161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
33019 17:05:35.630603 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
33021 17:05:35.671117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
33022 17:05:35.671572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
33024 17:05:35.710451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
33025 17:05:35.710793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
33027 17:05:35.750805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
33028 17:05:35.751164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
33030 17:05:35.796922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
33031 17:05:35.797343 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
33033 17:05:35.833092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
33034 17:05:35.833556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
33036 17:05:35.877630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
33038 17:05:35.878192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
33039 17:05:35.937388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
33041 17:05:35.937751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
33042 17:05:35.978482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
33043 17:05:35.978999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
33045 17:05:36.014096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass>
33046 17:05:36.014411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256 RESULT=pass
33048 17:05:36.062385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33049 17:05:36.062799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33051 17:05:36.099821 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass
33053 17:05:36.100237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33054 17:05:36.135240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33055 17:05:36.135619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33057 17:05:36.184661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33058 17:05:36.185080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33060 17:05:36.220356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass
33062 17:05:36.220817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33063 17:05:36.261029 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33065 17:05:36.261454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33066 17:05:36.298097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33067 17:05:36.298483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33069 17:05:36.333982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass
33071 17:05:36.334385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33072 17:05:36.371159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33073 17:05:36.371498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33075 17:05:36.410281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33076 17:05:36.410612 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33078 17:05:36.448933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33079 17:05:36.449378 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM RESULT=pass
33081 17:05:36.497209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33082 17:05:36.497590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33084 17:05:36.546940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33085 17:05:36.547346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33087 17:05:36.599508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33088 17:05:36.599927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM RESULT=pass
33090 17:05:36.641432 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33092 17:05:36.641910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33093 17:05:36.675239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass>
33094 17:05:36.675686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240 RESULT=pass
33096 17:05:36.717387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33097 17:05:36.717817 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33099 17:05:36.773592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33100 17:05:36.774052 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM RESULT=pass
33102 17:05:36.818754 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33104 17:05:36.819173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33105 17:05:36.856900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33106 17:05:36.857315 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33108 17:05:36.896909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass
33110 17:05:36.897399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33111 17:05:36.938276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33112 17:05:36.938727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33114 17:05:36.973108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33116 17:05:36.973778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33117 17:05:37.009399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass
33119 17:05:37.010193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33120 17:05:37.050566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33121 17:05:37.051009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33123 17:05:37.093860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33124 17:05:37.094309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33126 17:05:37.130966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass
33128 17:05:37.131439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33129 17:05:37.165825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33130 17:05:37.166272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33132 17:05:37.201107 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33134 17:05:37.201573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33135 17:05:37.238816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33136 17:05:37.239238 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM RESULT=pass
33138 17:05:37.278541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33140 17:05:37.279217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33141 17:05:37.334320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass>
33142 17:05:37.334815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224 RESULT=pass
33144 17:05:37.374701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33145 17:05:37.375117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33147 17:05:37.410025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33148 17:05:37.410467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM RESULT=pass
33150 17:05:37.450273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33151 17:05:37.450670 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33153 17:05:37.489806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33155 17:05:37.490272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33156 17:05:37.527454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33157 17:05:37.528015 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM RESULT=pass
33159 17:05:37.565153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33160 17:05:37.565589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33162 17:05:37.603332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33164 17:05:37.603822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33165 17:05:37.651788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass
33167 17:05:37.652468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33168 17:05:37.690737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33170 17:05:37.691326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33171 17:05:37.724257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33172 17:05:37.724738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33174 17:05:37.757528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33175 17:05:37.757936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM RESULT=pass
33177 17:05:37.806260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33179 17:05:37.806825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33180 17:05:37.841469 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33182 17:05:37.841936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33183 17:05:37.874847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33184 17:05:37.875291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM RESULT=pass
33186 17:05:37.910397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33187 17:05:37.910796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33189 17:05:37.947698 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass
33191 17:05:37.948186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208 RESULT=pass>
33192 17:05:37.981712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33193 17:05:37.982125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33195 17:05:38.016861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass
33197 17:05:38.017318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33198 17:05:38.064318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33199 17:05:38.064750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33201 17:05:38.098455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33202 17:05:38.098949 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33204 17:05:38.131578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33205 17:05:38.131966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM RESULT=pass
33207 17:05:38.170310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33208 17:05:38.170833 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33210 17:05:38.216675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33211 17:05:38.217089 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33213 17:05:38.261934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33214 17:05:38.262386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM RESULT=pass
33216 17:05:38.296903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33217 17:05:38.297304 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33219 17:05:38.341797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33220 17:05:38.342183 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33222 17:05:38.398593 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass
33224 17:05:38.399018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33225 17:05:38.441314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33227 17:05:38.441786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33228 17:05:38.485211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
33229 17:05:38.485606 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
33231 17:05:38.526485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass>
33232 17:05:38.526899 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM RESULT=pass
33234 17:05:38.571224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
33235 17:05:38.571726 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA RESULT=pass
33237 17:05:38.605539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass>
33238 17:05:38.605990 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192 RESULT=pass
33240 17:05:38.638728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
33241 17:05:38.639174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
33243 17:05:38.672867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass>
33244 17:05:38.673411 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM RESULT=pass
33246 17:05:38.707937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass
33248 17:05:38.708622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
33249 17:05:38.740505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
33251 17:05:38.740967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
33252 17:05:38.776450 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass
33254 17:05:38.777253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM RESULT=pass>
33255 17:05:38.809456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
33256 17:05:38.810022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA RESULT=pass
33258 17:05:38.846980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
33259 17:05:38.847431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
33261 17:05:38.881529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass>
33262 17:05:38.881946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM RESULT=pass
33264 17:05:38.914493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
33265 17:05:38.914936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA RESULT=pass
33267 17:05:38.949221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
33268 17:05:38.949693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
33270 17:05:38.985473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass>
33271 17:05:38.985925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM RESULT=pass
33273 17:05:39.035408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
33274 17:05:39.035803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA RESULT=pass
33276 17:05:39.080340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
33277 17:05:39.080770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
33279 17:05:39.149411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass>
33280 17:05:39.149815 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM RESULT=pass
33282 17:05:39.206970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
33283 17:05:39.207399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA RESULT=pass
33285 17:05:39.245632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass>
33286 17:05:39.246085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176 RESULT=pass
33288 17:05:39.299095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
33289 17:05:39.299526 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
33291 17:05:39.344316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass>
33292 17:05:39.344773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM RESULT=pass
33294 17:05:39.388293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass
33296 17:05:39.388774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
33297 17:05:39.424809 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
33299 17:05:39.425303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
33300 17:05:39.462454 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass
33302 17:05:39.463117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM RESULT=pass>
33303 17:05:39.502850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass
33305 17:05:39.503482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
33306 17:05:39.538983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
33307 17:05:39.539472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
33309 17:05:39.573498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass>
33310 17:05:39.574002 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM RESULT=pass
33312 17:05:39.612653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
33313 17:05:39.613047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA RESULT=pass
33315 17:05:39.646348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
33316 17:05:39.646731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
33318 17:05:39.680889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass
33320 17:05:39.681325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM RESULT=pass>
33321 17:05:39.717991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
33322 17:05:39.718539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA RESULT=pass
33324 17:05:39.758288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
33325 17:05:39.758674 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
33327 17:05:39.794287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass>
33328 17:05:39.794690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM RESULT=pass
33330 17:05:39.829684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
33331 17:05:39.830166 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA RESULT=pass
33333 17:05:39.865880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass>
33334 17:05:39.866372 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160 RESULT=pass
33336 17:05:39.902351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
33337 17:05:39.902772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
33339 17:05:39.937120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass>
33340 17:05:39.937561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM RESULT=pass
33342 17:05:39.972855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
33343 17:05:39.973305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA RESULT=pass
33345 17:05:40.009636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
33346 17:05:40.010071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
33348 17:05:40.045134 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass
33350 17:05:40.045831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM RESULT=pass>
33351 17:05:40.080248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
33352 17:05:40.080741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA RESULT=pass
33354 17:05:40.116347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
33356 17:05:40.116916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
33357 17:05:40.152800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass
33359 17:05:40.153394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM RESULT=pass>
33360 17:05:40.187180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
33361 17:05:40.187778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA RESULT=pass
33363 17:05:40.223237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
33364 17:05:40.223693 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
33366 17:05:40.260972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass
33368 17:05:40.261594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM RESULT=pass>
33369 17:05:40.296397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass
33371 17:05:40.296963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
33372 17:05:40.331258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
33373 17:05:40.331750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
33375 17:05:40.367246 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass
33377 17:05:40.367709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM RESULT=pass>
33378 17:05:40.404623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
33379 17:05:40.405077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA RESULT=pass
33381 17:05:40.441223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass>
33382 17:05:40.441656 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144 RESULT=pass
33384 17:05:40.478784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
33385 17:05:40.479322 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
33387 17:05:40.514609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass>
33388 17:05:40.514997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM RESULT=pass
33390 17:05:40.552735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
33391 17:05:40.553160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA RESULT=pass
33393 17:05:40.587873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
33395 17:05:40.588596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
33396 17:05:40.623799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass
33398 17:05:40.624264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM RESULT=pass>
33399 17:05:40.659142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
33400 17:05:40.659584 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA RESULT=pass
33402 17:05:40.696624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
33403 17:05:40.697045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
33405 17:05:40.733687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass
33407 17:05:40.734116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM RESULT=pass>
33408 17:05:40.772564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass
33410 17:05:40.773062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
33411 17:05:40.809185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
33412 17:05:40.809555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
33414 17:05:40.844958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass>
33415 17:05:40.845402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM RESULT=pass
33417 17:05:40.880313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
33418 17:05:40.880741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA RESULT=pass
33420 17:05:40.915489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
33421 17:05:40.915916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
33423 17:05:40.951247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass>
33424 17:05:40.951750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM RESULT=pass
33426 17:05:40.986818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
33427 17:05:40.987310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA RESULT=pass
33429 17:05:41.021857 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass
33431 17:05:41.022325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128 RESULT=pass>
33432 17:05:41.057363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
33433 17:05:41.057784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
33435 17:05:41.093236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass>
33436 17:05:41.093694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM RESULT=pass
33438 17:05:41.128605 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass
33440 17:05:41.129176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
33441 17:05:41.163474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
33442 17:05:41.163915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
33444 17:05:41.198996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass
33446 17:05:41.199460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM RESULT=pass>
33447 17:05:41.234964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass
33449 17:05:41.235535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
33450 17:05:41.271230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
33451 17:05:41.271661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
33453 17:05:41.310262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass>
33454 17:05:41.310687 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM RESULT=pass
33456 17:05:41.346491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass
33458 17:05:41.347096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
33459 17:05:41.383537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
33460 17:05:41.384018 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
33462 17:05:41.419252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass>
33463 17:05:41.419728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM RESULT=pass
33465 17:05:41.455101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass
33467 17:05:41.455680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
33468 17:05:41.492641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
33469 17:05:41.493100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
33471 17:05:41.528784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass>
33472 17:05:41.529185 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM RESULT=pass
33474 17:05:41.563773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass
33476 17:05:41.564179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
33477 17:05:41.598664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass>
33478 17:05:41.599014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112 RESULT=pass
33480 17:05:41.642012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
33481 17:05:41.642473 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
33483 17:05:41.684944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass>
33484 17:05:41.685381 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM RESULT=pass
33486 17:05:41.723622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
33487 17:05:41.724153 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA RESULT=pass
33489 17:05:41.770189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
33491 17:05:41.770940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
33492 17:05:41.818354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass
33494 17:05:41.818924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM RESULT=pass>
33495 17:05:41.864574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
33496 17:05:41.865101 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA RESULT=pass
33498 17:05:41.900688 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
33500 17:05:41.901404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
33501 17:05:41.935701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass
33503 17:05:41.936330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM RESULT=pass>
33504 17:05:41.969086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
33505 17:05:41.969486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA RESULT=pass
33507 17:05:42.001592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
33508 17:05:42.002057 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
33510 17:05:42.034024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass>
33511 17:05:42.034481 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM RESULT=pass
33513 17:05:42.076978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass
33515 17:05:42.077464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
33516 17:05:42.122300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
33517 17:05:42.122741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
33519 17:05:42.158907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass>
33520 17:05:42.159338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM RESULT=pass
33522 17:05:42.198377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
33523 17:05:42.198803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA RESULT=pass
33525 17:05:42.245055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass
33527 17:05:42.245437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96 RESULT=pass>
33528 17:05:42.285896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
33529 17:05:42.286284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
33531 17:05:42.332636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass
33533 17:05:42.333081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM RESULT=pass>
33534 17:05:42.368225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
33535 17:05:42.368676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA RESULT=pass
33537 17:05:42.402995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
33538 17:05:42.403441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
33540 17:05:42.442683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass>
33541 17:05:42.443154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM RESULT=pass
33543 17:05:42.478384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
33544 17:05:42.478850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA RESULT=pass
33546 17:05:42.523264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
33547 17:05:42.523759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
33549 17:05:42.570361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass>
33550 17:05:42.570803 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM RESULT=pass
33552 17:05:42.617824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
33553 17:05:42.618214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA RESULT=pass
33555 17:05:42.662516 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
33557 17:05:42.662992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
33558 17:05:42.704774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass>
33559 17:05:42.705208 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM RESULT=pass
33561 17:05:42.757324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
33562 17:05:42.757755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA RESULT=pass
33564 17:05:42.804878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
33565 17:05:42.805300 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
33567 17:05:42.846268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass>
33568 17:05:42.846738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM RESULT=pass
33570 17:05:42.899030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
33571 17:05:42.899441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA RESULT=pass
33573 17:05:42.947087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass>
33574 17:05:42.947488 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80 RESULT=pass
33576 17:05:42.987714 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
33578 17:05:42.988321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
33579 17:05:43.034178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass>
33580 17:05:43.034631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM RESULT=pass
33582 17:05:43.080172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
33583 17:05:43.080621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA RESULT=pass
33585 17:05:43.118550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
33586 17:05:43.119001 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
33588 17:05:43.162748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass
33590 17:05:43.163185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM RESULT=pass>
33591 17:05:43.214770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
33592 17:05:43.215199 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA RESULT=pass
33594 17:05:43.261724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
33595 17:05:43.262226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
33597 17:05:43.313799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass>
33598 17:05:43.314205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM RESULT=pass
33600 17:05:43.357436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
33601 17:05:43.357866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA RESULT=pass
33603 17:05:43.392877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
33604 17:05:43.393370 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
33606 17:05:43.429640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass>
33607 17:05:43.430095 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM RESULT=pass
33609 17:05:43.474562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
33610 17:05:43.474967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA RESULT=pass
33612 17:05:43.521553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
33613 17:05:43.522162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
33615 17:05:43.565434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass>
33616 17:05:43.565873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM RESULT=pass
33618 17:05:43.606291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass
33620 17:05:43.606979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
33621 17:05:43.649728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass
33623 17:05:43.650217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64 RESULT=pass>
33624 17:05:43.696532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
33625 17:05:43.696979 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
33627 17:05:43.735755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass
33629 17:05:43.736236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM RESULT=pass>
33630 17:05:43.772620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass
33632 17:05:43.773279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
33633 17:05:43.809840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
33635 17:05:43.810300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
33636 17:05:43.864540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass>
33637 17:05:43.864986 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM RESULT=pass
33639 17:05:43.909723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
33640 17:05:43.910162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA RESULT=pass
33642 17:05:43.957116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
33643 17:05:43.957519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
33645 17:05:43.997124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass>
33646 17:05:43.997546 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM RESULT=pass
33648 17:05:44.042553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
33649 17:05:44.042988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA RESULT=pass
33651 17:05:44.085807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
33652 17:05:44.086231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
33654 17:05:44.134250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass>
33655 17:05:44.134673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM RESULT=pass
33657 17:05:44.172027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass
33659 17:05:44.172499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
33660 17:05:44.246495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
33661 17:05:44.246927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
33663 17:05:44.285696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass>
33664 17:05:44.286152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM RESULT=pass
33666 17:05:44.327347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
33667 17:05:44.327772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA RESULT=pass
33669 17:05:44.367474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass
33671 17:05:44.367950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48 RESULT=pass>
33672 17:05:44.407402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
33673 17:05:44.407786 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
33675 17:05:44.446542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass>
33676 17:05:44.446934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM RESULT=pass
33678 17:05:44.482876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass
33680 17:05:44.483309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
33681 17:05:44.522538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
33682 17:05:44.522997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
33684 17:05:44.564688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass>
33685 17:05:44.565112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM RESULT=pass
33687 17:05:44.602639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass
33689 17:05:44.603094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
33690 17:05:44.642206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
33691 17:05:44.642624 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
33693 17:05:44.690678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass>
33694 17:05:44.691109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM RESULT=pass
33696 17:05:44.730879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
33697 17:05:44.731310 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA RESULT=pass
33699 17:05:44.778389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
33701 17:05:44.778813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
33702 17:05:44.813046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass>
33703 17:05:44.813441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM RESULT=pass
33705 17:05:44.848991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
33706 17:05:44.849394 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA RESULT=pass
33708 17:05:44.885844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
33709 17:05:44.886270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
33711 17:05:44.921512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass>
33712 17:05:44.922105 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM RESULT=pass
33714 17:05:44.955880 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass
33716 17:05:44.956504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
33717 17:05:44.990780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass>
33718 17:05:44.991283 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32 RESULT=pass
33720 17:05:45.025975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
33721 17:05:45.026422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
33723 17:05:45.061128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass>
33724 17:05:45.061568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM RESULT=pass
33726 17:05:45.097781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
33727 17:05:45.098235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA RESULT=pass
33729 17:05:45.137053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
33730 17:05:45.137483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
33732 17:05:45.177419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass>
33733 17:05:45.177958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM RESULT=pass
33735 17:05:45.215249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass
33737 17:05:45.215621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
33738 17:05:45.259890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
33740 17:05:45.260318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
33741 17:05:45.317659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass
33743 17:05:45.318414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM RESULT=pass>
33744 17:05:45.357000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
33745 17:05:45.357492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA RESULT=pass
33747 17:05:45.400045 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
33749 17:05:45.400819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
33750 17:05:45.455032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass>
33751 17:05:45.455466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM RESULT=pass
33753 17:05:45.498155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
33754 17:05:45.498564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA RESULT=pass
33756 17:05:45.536902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
33757 17:05:45.537312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
33759 17:05:45.578472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass>
33760 17:05:45.578923 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM RESULT=pass
33762 17:05:45.619659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass
33764 17:05:45.620143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
33765 17:05:45.656668 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass
33767 17:05:45.657150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16 RESULT=pass>
33768 17:05:45.693346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
33770 17:05:45.693830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
33771 17:05:45.729789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass
33773 17:05:45.730245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM RESULT=pass>
33774 17:05:45.770122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
33775 17:05:45.770525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA RESULT=pass
33777 17:05:45.821504 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
33779 17:05:45.822147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
33780 17:05:45.865253 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass
33782 17:05:45.865937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM RESULT=pass>
33783 17:05:45.905056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
33784 17:05:45.905508 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA RESULT=pass
33786 17:05:45.948033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
33788 17:05:45.948498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
33789 17:05:45.995190 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass
33791 17:05:45.995857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM RESULT=pass>
33792 17:05:46.032547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
33793 17:05:46.033126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA RESULT=pass
33795 17:05:46.073523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
33796 17:05:46.074038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
33798 17:05:46.118018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass>
33799 17:05:46.118500 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM RESULT=pass
33801 17:05:46.168593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
33802 17:05:46.168998 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA RESULT=pass
33804 17:05:46.213941 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
33806 17:05:46.214563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
33807 17:05:46.250883 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass
33809 17:05:46.251368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM RESULT=pass>
33810 17:05:46.286958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
33811 17:05:46.287385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA RESULT=pass
33813 17:05:46.335335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
33814 17:05:46.335727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
33816 17:05:46.375840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass
33818 17:05:46.376238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256 RESULT=pass>
33819 17:05:46.421636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass
33821 17:05:46.422129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA RESULT=pass>
33822 17:05:46.469660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass
33824 17:05:46.470375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM RESULT=pass>
33825 17:05:46.505423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass>
33826 17:05:46.505919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA RESULT=pass
33828 17:05:46.540976 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass
33830 17:05:46.541570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA RESULT=pass>
33831 17:05:46.591376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass>
33832 17:05:46.591864 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM RESULT=pass
33834 17:05:46.645706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass>
33835 17:05:46.646213 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA RESULT=pass
33837 17:05:46.689174 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass
33839 17:05:46.689957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA RESULT=pass>
33840 17:05:46.731040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass>
33841 17:05:46.731468 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM RESULT=pass
33843 17:05:46.767478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass>
33844 17:05:46.767898 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA RESULT=pass
33846 17:05:46.802231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass
33848 17:05:46.802819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA RESULT=pass>
33849 17:05:46.838004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass>
33850 17:05:46.838491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM RESULT=pass
33852 17:05:46.874670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass>
33853 17:05:46.875103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA RESULT=pass
33855 17:05:46.913203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass>
33856 17:05:46.913629 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA RESULT=pass
33858 17:05:46.955337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass>
33859 17:05:46.955794 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM RESULT=pass
33861 17:05:46.993888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass
33863 17:05:46.994466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA RESULT=pass>
33864 17:05:47.034820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass>
33865 17:05:47.035297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240 RESULT=pass
33867 17:05:47.074242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass>
33868 17:05:47.074669 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA RESULT=pass
33870 17:05:47.117951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass
33872 17:05:47.118427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM RESULT=pass>
33873 17:05:47.167421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass>
33874 17:05:47.167982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA RESULT=pass
33876 17:05:47.204549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass>
33877 17:05:47.204981 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA RESULT=pass
33879 17:05:47.243060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass
33881 17:05:47.243479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM RESULT=pass>
33882 17:05:47.285116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass>
33883 17:05:47.285515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA RESULT=pass
33885 17:05:47.329574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass>
33886 17:05:47.330113 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA RESULT=pass
33888 17:05:47.368808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass>
33889 17:05:47.369247 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM RESULT=pass
33891 17:05:47.407924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass
33893 17:05:47.408393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA RESULT=pass>
33894 17:05:47.445106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass>
33895 17:05:47.445637 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA RESULT=pass
33897 17:05:47.484705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass
33899 17:05:47.485407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM RESULT=pass>
33900 17:05:47.522171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass
33902 17:05:47.522873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA RESULT=pass>
33903 17:05:47.565895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass>
33904 17:05:47.566346 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA RESULT=pass
33906 17:05:47.615865 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass
33908 17:05:47.616363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM RESULT=pass>
33909 17:05:47.661802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass>
33910 17:05:47.662193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA RESULT=pass
33912 17:05:47.699973 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass
33914 17:05:47.700420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224 RESULT=pass>
33915 17:05:47.738884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass
33917 17:05:47.739359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA RESULT=pass>
33918 17:05:47.776548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass>
33919 17:05:47.776984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM RESULT=pass
33921 17:05:47.812533 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass
33923 17:05:47.812981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA RESULT=pass>
33924 17:05:47.855856 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass
33926 17:05:47.856340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA RESULT=pass>
33927 17:05:47.893794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass>
33928 17:05:47.894232 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM RESULT=pass
33930 17:05:47.934259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass>
33931 17:05:47.934678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA RESULT=pass
33933 17:05:47.973424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass
33935 17:05:47.973929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA RESULT=pass>
33936 17:05:48.011424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass>
33937 17:05:48.011879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM RESULT=pass
33939 17:05:48.050648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass>
33940 17:05:48.051068 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA RESULT=pass
33942 17:05:48.095832 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass
33944 17:05:48.096259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA RESULT=pass>
33945 17:05:48.138702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass>
33946 17:05:48.139143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM RESULT=pass
33948 17:05:48.184531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass>
33949 17:05:48.184966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA RESULT=pass
33951 17:05:48.229784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass>
33952 17:05:48.230211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA RESULT=pass
33954 17:05:48.268463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass>
33955 17:05:48.268900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM RESULT=pass
33957 17:05:48.305620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass
33959 17:05:48.306090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA RESULT=pass>
33960 17:05:48.344858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass
33962 17:05:48.345333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208 RESULT=pass>
33963 17:05:48.382586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass>
33964 17:05:48.382970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA RESULT=pass
33966 17:05:48.419844 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass
33968 17:05:48.420279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM RESULT=pass>
33969 17:05:48.465098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass>
33970 17:05:48.465511 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA RESULT=pass
33972 17:05:48.511360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass>
33973 17:05:48.511767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA RESULT=pass
33975 17:05:48.553097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass>
33976 17:05:48.553492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM RESULT=pass
33978 17:05:48.587247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass>
33979 17:05:48.587666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA RESULT=pass
33981 17:05:48.620990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass>
33982 17:05:48.621404 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA RESULT=pass
33984 17:05:48.659218 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass
33986 17:05:48.659689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM RESULT=pass>
33987 17:05:48.699272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass>
33988 17:05:48.699778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA RESULT=pass
33990 17:05:48.745773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass>
33991 17:05:48.746191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA RESULT=pass
33993 17:05:48.786463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass>
33994 17:05:48.786879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM RESULT=pass
33996 17:05:48.830302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass>
33997 17:05:48.830681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA RESULT=pass
33999 17:05:48.871287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass
34001 17:05:48.871755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA RESULT=pass>
34002 17:05:48.909197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass>
34003 17:05:48.909620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM RESULT=pass
34005 17:05:48.952910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass>
34006 17:05:48.953331 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA RESULT=pass
34008 17:05:48.989401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass>
34009 17:05:48.989861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192 RESULT=pass
34011 17:05:49.024806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass>
34012 17:05:49.025228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA RESULT=pass
34014 17:05:49.078542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass>
34015 17:05:49.078967 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM RESULT=pass
34017 17:05:49.133105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass>
34018 17:05:49.133615 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA RESULT=pass
34020 17:05:49.185271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass
34022 17:05:49.186031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA RESULT=pass>
34023 17:05:49.233720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass>
34024 17:05:49.234157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM RESULT=pass
34026 17:05:49.277674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass>
34027 17:05:49.278111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA RESULT=pass
34029 17:05:49.342746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass
34031 17:05:49.343209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA RESULT=pass>
34032 17:05:49.387461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass
34034 17:05:49.387943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM RESULT=pass>
34035 17:05:49.425555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass>
34036 17:05:49.425988 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA RESULT=pass
34038 17:05:49.463016 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass
34040 17:05:49.463398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA RESULT=pass>
34041 17:05:49.510041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass>
34042 17:05:49.510466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM RESULT=pass
34044 17:05:49.546862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass>
34045 17:05:49.547287 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA RESULT=pass
34047 17:05:49.585060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass>
34048 17:05:49.585485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA RESULT=pass
34050 17:05:49.621524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass
34052 17:05:49.621923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM RESULT=pass>
34053 17:05:49.656078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass
34055 17:05:49.656544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA RESULT=pass>
34056 17:05:49.691963 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass
34058 17:05:49.692746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176 RESULT=pass>
34059 17:05:49.745159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass>
34060 17:05:49.745573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA RESULT=pass
34062 17:05:49.799044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass
34064 17:05:49.799418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM RESULT=pass>
34065 17:05:49.850392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass>
34066 17:05:49.850769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA RESULT=pass
34068 17:05:49.893951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass>
34069 17:05:49.894521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA RESULT=pass
34071 17:05:49.934264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass>
34072 17:05:49.934702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM RESULT=pass
34074 17:05:49.976832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass>
34075 17:05:49.977335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA RESULT=pass
34077 17:05:50.012753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass
34079 17:05:50.013499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA RESULT=pass>
34080 17:05:50.047916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass
34082 17:05:50.048474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM RESULT=pass>
34083 17:05:50.097429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass>
34084 17:05:50.097860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA RESULT=pass
34086 17:05:50.144135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass
34088 17:05:50.144795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA RESULT=pass>
34089 17:05:50.186693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass>
34090 17:05:50.187172 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM RESULT=pass
34092 17:05:50.230770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass>
34093 17:05:50.231220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA RESULT=pass
34095 17:05:50.284624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass>
34096 17:05:50.285031 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA RESULT=pass
34098 17:05:50.333781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass>
34099 17:05:50.334236 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM RESULT=pass
34101 17:05:50.377369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass>
34102 17:05:50.377958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA RESULT=pass
34104 17:05:50.425547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass>
34105 17:05:50.426009 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160 RESULT=pass
34107 17:05:50.465252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass>
34108 17:05:50.465684 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA RESULT=pass
34110 17:05:50.510917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass>
34111 17:05:50.511355 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM RESULT=pass
34113 17:05:50.557953 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass
34115 17:05:50.558431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA RESULT=pass>
34116 17:05:50.600285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass>
34117 17:05:50.600739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA RESULT=pass
34119 17:05:50.637838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass>
34120 17:05:50.638272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM RESULT=pass
34122 17:05:50.673417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass>
34123 17:05:50.673853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA RESULT=pass
34125 17:05:50.708676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass>
34126 17:05:50.709098 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA RESULT=pass
34128 17:05:50.744593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass>
34129 17:05:50.745033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM RESULT=pass
34131 17:05:50.779176 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass
34133 17:05:50.779657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA RESULT=pass>
34134 17:05:50.814612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass>
34135 17:05:50.815020 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA RESULT=pass
34137 17:05:50.850307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass>
34138 17:05:50.850787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM RESULT=pass
34140 17:05:50.884492 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass
34142 17:05:50.884957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA RESULT=pass>
34143 17:05:50.920555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass>
34144 17:05:50.921003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA RESULT=pass
34146 17:05:50.956868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass>
34147 17:05:50.957297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM RESULT=pass
34149 17:05:50.995134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass>
34150 17:05:50.995541 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA RESULT=pass
34152 17:05:51.035169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass>
34153 17:05:51.035518 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144 RESULT=pass
34155 17:05:51.073393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass>
34156 17:05:51.073763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA RESULT=pass
34158 17:05:51.111383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass>
34159 17:05:51.111739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM RESULT=pass
34161 17:05:51.158029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass>
34162 17:05:51.158515 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA RESULT=pass
34164 17:05:51.202274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass>
34165 17:05:51.202757 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA RESULT=pass
34167 17:05:51.254680 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass
34169 17:05:51.255144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM RESULT=pass>
34170 17:05:51.295437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass>
34171 17:05:51.295858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA RESULT=pass
34173 17:05:51.342316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass
34175 17:05:51.343099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA RESULT=pass>
34176 17:05:51.381432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass>
34177 17:05:51.381851 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM RESULT=pass
34179 17:05:51.425722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass
34181 17:05:51.426162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA RESULT=pass>
34182 17:05:51.481618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass
34184 17:05:51.482108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA RESULT=pass>
34185 17:05:51.525256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass>
34186 17:05:51.525667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM RESULT=pass
34188 17:05:51.564958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass>
34189 17:05:51.565338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA RESULT=pass
34191 17:05:51.605115 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass
34193 17:05:51.605714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA RESULT=pass>
34194 17:05:51.641730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass>
34195 17:05:51.642217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM RESULT=pass
34197 17:05:51.683148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass>
34198 17:05:51.683585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA RESULT=pass
34200 17:05:51.720774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass>
34201 17:05:51.721160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128 RESULT=pass
34203 17:05:51.774332 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass
34205 17:05:51.775141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA RESULT=pass>
34206 17:05:51.811044 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass
34208 17:05:51.811522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM RESULT=pass>
34209 17:05:51.865824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass>
34210 17:05:51.866312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA RESULT=pass
34212 17:05:51.909855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass>
34213 17:05:51.910345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA RESULT=pass
34215 17:05:51.953944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass>
34216 17:05:51.954320 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM RESULT=pass
34218 17:05:52.002323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass
34220 17:05:52.003071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA RESULT=pass>
34221 17:05:52.048651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass>
34222 17:05:52.049100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA RESULT=pass
34224 17:05:52.085658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass>
34225 17:05:52.086104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM RESULT=pass
34227 17:05:52.125896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass>
34228 17:05:52.126275 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA RESULT=pass
34230 17:05:52.162491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass>
34231 17:05:52.162930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA RESULT=pass
34233 17:05:52.198957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass>
34234 17:05:52.199403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM RESULT=pass
34236 17:05:52.241788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass
34238 17:05:52.242273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA RESULT=pass>
34239 17:05:52.290478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass>
34240 17:05:52.290868 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA RESULT=pass
34242 17:05:52.327884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass
34244 17:05:52.328366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM RESULT=pass>
34245 17:05:52.365110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass>
34246 17:05:52.365530 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA RESULT=pass
34248 17:05:52.404879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass
34250 17:05:52.405359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112 RESULT=pass>
34251 17:05:52.451540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass>
34252 17:05:52.451991 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA RESULT=pass
34254 17:05:52.488288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass>
34255 17:05:52.488741 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM RESULT=pass
34257 17:05:52.525353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass>
34258 17:05:52.525942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA RESULT=pass
34260 17:05:52.563753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass
34262 17:05:52.564194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA RESULT=pass>
34263 17:05:52.601978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass>
34264 17:05:52.602406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM RESULT=pass
34266 17:05:52.639502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass>
34267 17:05:52.639884 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA RESULT=pass
34269 17:05:52.676537 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass
34271 17:05:52.676972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA RESULT=pass>
34272 17:05:52.711924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass
34274 17:05:52.712386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM RESULT=pass>
34275 17:05:52.748724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass>
34276 17:05:52.749154 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA RESULT=pass
34278 17:05:52.783508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass>
34279 17:05:52.783942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA RESULT=pass
34281 17:05:52.819321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass>
34282 17:05:52.819720 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM RESULT=pass
34284 17:05:52.867184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass>
34285 17:05:52.867614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA RESULT=pass
34287 17:05:52.908918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass>
34288 17:05:52.909365 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA RESULT=pass
34290 17:05:52.949558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass>
34291 17:05:52.949961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM RESULT=pass
34293 17:05:52.993315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass>
34294 17:05:52.993752 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA RESULT=pass
34296 17:05:53.030379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass>
34297 17:05:53.030823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96 RESULT=pass
34299 17:05:53.065074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass>
34300 17:05:53.065626 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA RESULT=pass
34302 17:05:53.100546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass>
34303 17:05:53.101004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM RESULT=pass
34305 17:05:53.149467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass>
34306 17:05:53.149924 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA RESULT=pass
34308 17:05:53.192690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass>
34309 17:05:53.193112 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA RESULT=pass
34311 17:05:53.235345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass>
34312 17:05:53.235771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM RESULT=pass
34314 17:05:53.274089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass>
34315 17:05:53.274521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA RESULT=pass
34317 17:05:53.315475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass>
34318 17:05:53.315984 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA RESULT=pass
34320 17:05:53.358666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass>
34321 17:05:53.359108 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM RESULT=pass
34323 17:05:53.409150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass>
34324 17:05:53.409585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA RESULT=pass
34326 17:05:53.460574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass>
34327 17:05:53.461060 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA RESULT=pass
34329 17:05:53.508948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass>
34330 17:05:53.509402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM RESULT=pass
34332 17:05:53.555080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass>
34333 17:05:53.555575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA RESULT=pass
34335 17:05:53.601691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass>
34336 17:05:53.602269 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA RESULT=pass
34338 17:05:53.642193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass>
34339 17:05:53.642701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM RESULT=pass
34341 17:05:53.679897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass
34343 17:05:53.680663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA RESULT=pass>
34344 17:05:53.727326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass>
34345 17:05:53.727975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80 RESULT=pass
34347 17:05:53.770453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass>
34348 17:05:53.770858 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA RESULT=pass
34350 17:05:53.806962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass>
34351 17:05:53.807337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM RESULT=pass
34353 17:05:53.844596 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass
34355 17:05:53.845251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA RESULT=pass>
34356 17:05:53.882200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass
34358 17:05:53.882873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA RESULT=pass>
34359 17:05:53.917924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass>
34360 17:05:53.918425 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM RESULT=pass
34362 17:05:53.955410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass>
34363 17:05:53.955915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA RESULT=pass
34365 17:05:53.992594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass>
34366 17:05:53.993109 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA RESULT=pass
34368 17:05:54.028134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass>
34369 17:05:54.028625 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM RESULT=pass
34371 17:05:54.063491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass>
34372 17:05:54.063896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA RESULT=pass
34374 17:05:54.099958 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass
34376 17:05:54.100441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA RESULT=pass>
34377 17:05:54.141575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass>
34378 17:05:54.142160 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM RESULT=pass
34380 17:05:54.199046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass
34382 17:05:54.199777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA RESULT=pass>
34383 17:05:54.259178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass>
34384 17:05:54.259630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA RESULT=pass
34386 17:05:54.299974 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass
34388 17:05:54.300393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM RESULT=pass>
34389 17:05:54.354281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass>
34390 17:05:54.354707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA RESULT=pass
34392 17:05:54.401672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass>
34393 17:05:54.402086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64 RESULT=pass
34395 17:05:54.461712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass>
34396 17:05:54.462117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA RESULT=pass
34398 17:05:54.510474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass
34400 17:05:54.510941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM RESULT=pass>
34401 17:05:54.550845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass
34403 17:05:54.551229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA RESULT=pass>
34404 17:05:54.590252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass>
34405 17:05:54.590685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA RESULT=pass
34407 17:05:54.628311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass>
34408 17:05:54.628731 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM RESULT=pass
34410 17:05:54.678440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass>
34411 17:05:54.678931 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA RESULT=pass
34413 17:05:54.718939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass>
34414 17:05:54.719335 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA RESULT=pass
34416 17:05:54.766039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass>
34417 17:05:54.766539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM RESULT=pass
34419 17:05:54.805640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass>
34420 17:05:54.806090 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA RESULT=pass
34422 17:05:54.856696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass>
34423 17:05:54.857128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA RESULT=pass
34425 17:05:54.908721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass>
34426 17:05:54.909122 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM RESULT=pass
34428 17:05:54.946591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass>
34429 17:05:54.947046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA RESULT=pass
34431 17:05:54.990704 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass
34433 17:05:54.991181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA RESULT=pass>
34434 17:05:55.033569 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass
34436 17:05:55.034076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM RESULT=pass>
34437 17:05:55.075845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass
34439 17:05:55.076326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA RESULT=pass>
34440 17:05:55.114148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass>
34441 17:05:55.114582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48 RESULT=pass
34443 17:05:55.149029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass>
34444 17:05:55.149464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA RESULT=pass
34446 17:05:55.201117 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass
34448 17:05:55.201597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM RESULT=pass>
34449 17:05:55.246663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass>
34450 17:05:55.247081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA RESULT=pass
34452 17:05:55.288918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass>
34453 17:05:55.289353 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA RESULT=pass
34455 17:05:55.326287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass>
34456 17:05:55.326730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM RESULT=pass
34458 17:05:55.365004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass>
34459 17:05:55.365442 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA RESULT=pass
34461 17:05:55.402604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass>
34462 17:05:55.403047 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA RESULT=pass
34464 17:05:55.439363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass>
34465 17:05:55.439748 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM RESULT=pass
34467 17:05:55.477714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass>
34468 17:05:55.478180 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA RESULT=pass
34470 17:05:55.515319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass>
34471 17:05:55.515739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA RESULT=pass
34473 17:05:55.553659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass
34475 17:05:55.554132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM RESULT=pass>
34476 17:05:55.591335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass>
34477 17:05:55.591770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA RESULT=pass
34479 17:05:55.627943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass
34481 17:05:55.628414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA RESULT=pass>
34482 17:05:55.664849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass>
34483 17:05:55.665282 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM RESULT=pass
34485 17:05:55.703208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass>
34486 17:05:55.703633 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA RESULT=pass
34488 17:05:55.740952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass>
34489 17:05:55.741458 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32 RESULT=pass
34491 17:05:55.798760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass>
34492 17:05:55.799237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA RESULT=pass
34494 17:05:55.840269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass>
34495 17:05:55.840837 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM RESULT=pass
34497 17:05:55.878831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass>
34498 17:05:55.879226 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA RESULT=pass
34500 17:05:55.916575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass>
34501 17:05:55.917006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA RESULT=pass
34503 17:05:55.953721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass>
34504 17:05:55.954152 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM RESULT=pass
34506 17:05:55.990957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass>
34507 17:05:55.991384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA RESULT=pass
34509 17:05:56.027461 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass
34511 17:05:56.027930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA RESULT=pass>
34512 17:05:56.062340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass>
34513 17:05:56.062763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM RESULT=pass
34515 17:05:56.099278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass>
34516 17:05:56.099701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA RESULT=pass
34518 17:05:56.136769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass>
34519 17:05:56.137198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA RESULT=pass
34521 17:05:56.174834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass
34523 17:05:56.175288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM RESULT=pass>
34524 17:05:56.215486 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass
34526 17:05:56.215903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA RESULT=pass>
34527 17:05:56.262378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass>
34528 17:05:56.262799 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA RESULT=pass
34530 17:05:56.305923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass>
34531 17:05:56.306399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM RESULT=pass
34533 17:05:56.345707 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass
34535 17:05:56.346375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA RESULT=pass>
34536 17:05:56.384854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass>
34537 17:05:56.385371 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16 RESULT=pass
34539 17:05:56.424758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass>
34540 17:05:56.425298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA RESULT=pass
34542 17:05:56.481314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass>
34543 17:05:56.481681 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM RESULT=pass
34545 17:05:56.522827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass>
34546 17:05:56.523277 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA RESULT=pass
34548 17:05:56.565127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass>
34549 17:05:56.565635 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA RESULT=pass
34551 17:05:56.606204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass>
34552 17:05:56.606666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM RESULT=pass
34554 17:05:56.647713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass
34556 17:05:56.648178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA RESULT=pass>
34557 17:05:56.693643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass>
34558 17:05:56.694157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA RESULT=pass
34560 17:05:56.748799 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass>
34561 17:05:56.749220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM RESULT=pass
34563 17:05:56.806037 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass
34565 17:05:56.806460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA RESULT=pass>
34566 17:05:56.853380 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass
34568 17:05:56.853849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA RESULT=pass>
34569 17:05:56.897622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass>
34570 17:05:56.898062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM RESULT=pass
34572 17:05:56.933510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass
34574 17:05:56.934004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA RESULT=pass>
34575 17:05:56.971237 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass
34577 17:05:56.971617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA RESULT=pass>
34578 17:05:57.011431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass>
34579 17:05:57.011861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM RESULT=pass
34581 17:05:57.048683 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass
34583 17:05:57.049134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA RESULT=pass>
34584 17:05:57.085007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
34585 17:05:57.085430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
34587 17:05:57.124700 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass
34589 17:05:57.125167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_default_value RESULT=pass>
34590 17:05:57.163573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass
34592 17:05:57.164044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_read RESULT=pass>
34593 17:05:57.202292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass>
34594 17:05:57.202743 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_sleep_read RESULT=pass
34596 17:05:57.238369 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass
34598 17:05:57.238843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_fork_read RESULT=pass>
34599 17:05:57.279064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass
34601 17:05:57.279516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_write_clone_read RESULT=pass>
34602 17:05:57.325187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
34603 17:05:57.325538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
34605 17:05:57.329954 + set +x
34606 17:05:57.330114 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64_qemu 556569_1.1.3.5>
34607 17:05:57.330380 Received signal: <ENDRUN> 1_kselftest-arm64_qemu 556569_1.1.3.5
34608 17:05:57.330488 Ending use of test pattern.
34609 17:05:57.330568 Ending test lava.1_kselftest-arm64_qemu (556569_1.1.3.5), duration 388.31
34611 17:05:57.335354 <LAVA_TEST_RUNNER EXIT>
34612 17:05:57.335737 ok: lava_test_shell seems to have completed
34613 17:05:57.393814 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: pass
arm64_btitest_bti_c_func_call_using_br_x0: pass
arm64_btitest_bti_c_func_call_using_br_x16: pass
arm64_btitest_bti_j_func_call_using_blr: pass
arm64_btitest_bti_j_func_call_using_br_x0: pass
arm64_btitest_bti_j_func_call_using_br_x16: pass
arm64_btitest_bti_jc_func_call_using_blr: pass
arm64_btitest_bti_jc_func_call_using_br_x0: pass
arm64_btitest_bti_jc_func_call_using_br_x16: pass
arm64_btitest_bti_none_func_call_using_blr: pass
arm64_btitest_bti_none_func_call_using_br_x0: pass
arm64_btitest_bti_none_func_call_using_br_x16: pass
arm64_btitest_nohint_func_call_using_blr: pass
arm64_btitest_nohint_func_call_using_br_x0: pass
arm64_btitest_nohint_func_call_using_br_x16: pass
arm64_btitest_paciasp_func_call_using_blr: pass
arm64_btitest_paciasp_func_call_using_br_x0: pass
arm64_btitest_paciasp_func_call_using_br_x16: pass
arm64_check_buffer_fill: fail
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_async_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_correctness_by_byte_with_sync_err_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_correctness_by_block_with_tag_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_async_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_sync_mode_and_mmap_memory: fail
arm64_check_buffer_fill_Check_buffer_write_overflow_by_byte_with_tag_fault_ignore_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_async_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_sync_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_buffer_write_underflow_by_byte_with_tag_check_fault_ignore_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_private_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_memory: pass
arm64_check_buffer_fill_Check_initial_tags_with_shared_mapping_sync_error_mode_and_mmap_mprotect_memory: pass
arm64_check_child_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_anonymous_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_private_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_imprecise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_memory: fail
arm64_check_child_memory_Check_child_file_memory_with_shared_mapping_precise_mode_and_mmap_mprotect_memory: fail
arm64_check_gcr_el1_cswitch: fail
arm64_check_ksm_options: fail
arm64_check_mmap_options: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_no_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_anonymous_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_and_sync_error_mode_and_mmap_mprotect_memory: fail
arm64_check_mmap_options_Check_clear_PROT_MTE_flags_with_private_mapping_sync_error_mode_and_mmap_memory: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_no_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_off: pass
arm64_check_mmap_options_Check_file_memory_with_private_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_async_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_memory_and_tag_check_on: fail
arm64_check_mmap_options_Check_file_memory_with_shared_mapping_sync_error_mode_mmap_mprotect_memory_and_tag_check_on: fail
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: pass
arm64_check_prctl_SYNC_ASYNC: pass
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: fail
arm64_check_tags_inclusion_Check_all_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_an_included_tag_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_different_included_tags_value_with_sync_mode: fail
arm64_check_tags_inclusion_Check_none_included_tags_value_with_sync_mode: pass
arm64_check_user_mem: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_read_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_readv_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_write_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_ASYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_PRIVATE_tag_len_16_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_0_tag_offset_16: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_0: pass
arm64_check_user_mem_test_type_writev_MTE_SYNC_ERR_MAP_SHARED_tag_len_16_tag_offset_16: pass
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: pass
arm64_fake_sigreturn_sve_change_vl: pass
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_SSVE-VL-128-0: pass
arm64_fp-stress_SSVE-VL-16-0: pass
arm64_fp-stress_SSVE-VL-256-0: pass
arm64_fp-stress_SSVE-VL-32-0: pass
arm64_fp-stress_SSVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-112-0: pass
arm64_fp-stress_SVE-VL-128-0: pass
arm64_fp-stress_SVE-VL-144-0: pass
arm64_fp-stress_SVE-VL-16-0: pass
arm64_fp-stress_SVE-VL-160-0: pass
arm64_fp-stress_SVE-VL-176-0: pass
arm64_fp-stress_SVE-VL-192-0: pass
arm64_fp-stress_SVE-VL-208-0: pass
arm64_fp-stress_SVE-VL-224-0: pass
arm64_fp-stress_SVE-VL-240-0: pass
arm64_fp-stress_SVE-VL-256-0: pass
arm64_fp-stress_SVE-VL-32-0: pass
arm64_fp-stress_SVE-VL-48-0: pass
arm64_fp-stress_SVE-VL-64-0: pass
arm64_fp-stress_SVE-VL-80-0: pass
arm64_fp-stress_SVE-VL-96-0: pass
arm64_fp-stress_ZA-VL-128-0: pass
arm64_fp-stress_ZA-VL-16-0: pass
arm64_fp-stress_ZA-VL-256-0: pass
arm64_fp-stress_ZA-VL-32-0: pass
arm64_fp-stress_ZA-VL-64-0: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: pass
arm64_hwcap_sigill_SVE2_BITPERM: pass
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: pass
arm64_hwcap_sigill_SVE2_F64MM: pass
arm64_hwcap_sigill_SVE2_I8MM: pass
arm64_hwcap_sigill_SVE2_PMULL: pass
arm64_hwcap_sigill_SVE2_SHA3: pass
arm64_hwcap_sigill_SVE2_SM4: pass
arm64_hwcap_sigill_SVE_2: pass
arm64_hwcap_sigill_SVE_AES: pass
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: pass
arm64_nobtitest_bti_c_func_call_using_br_x0: pass
arm64_nobtitest_bti_c_func_call_using_br_x16: pass
arm64_nobtitest_bti_j_func_call_using_blr: pass
arm64_nobtitest_bti_j_func_call_using_br_x0: pass
arm64_nobtitest_bti_j_func_call_using_br_x16: pass
arm64_nobtitest_bti_jc_func_call_using_blr: pass
arm64_nobtitest_bti_jc_func_call_using_br_x0: pass
arm64_nobtitest_bti_jc_func_call_using_br_x16: pass
arm64_nobtitest_bti_none_func_call_using_blr: pass
arm64_nobtitest_bti_none_func_call_using_br_x0: pass
arm64_nobtitest_bti_none_func_call_using_br_x16: pass
arm64_nobtitest_nohint_func_call_using_blr: pass
arm64_nobtitest_nohint_func_call_using_br_x0: pass
arm64_nobtitest_nohint_func_call_using_br_x16: pass
arm64_nobtitest_paciasp_func_call_using_blr: pass
arm64_nobtitest_paciasp_func_call_using_br_x0: pass
arm64_nobtitest_paciasp_func_call_using_br_x16: pass
arm64_pac: pass
arm64_pac_global_context_switch_keep_keys: pass
arm64_pac_global_context_switch_keep_keys_generic: pass
arm64_pac_global_corrupt_pac: pass
arm64_pac_global_exec_changed_keys: pass
arm64_pac_global_pac_instructions_not_nop: pass
arm64_pac_global_pac_instructions_not_nop_generic: pass
arm64_pac_global_single_thread_different_keys: pass
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: pass
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: pass
arm64_ssve_regs: pass
arm64_sve-probe-vls: pass
arm64_sve-probe-vls_All_vector_lengths_valid: pass
arm64_sve-probe-vls_Enumerated_16_vector_lengths: pass
arm64_sve-ptrace: pass
arm64_sve-ptrace_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_FPSIMD_read_via_SVE_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_1008: pass
arm64_sve-ptrace_Set_SVE_VL_1024: pass
arm64_sve-ptrace_Set_SVE_VL_1040: pass
arm64_sve-ptrace_Set_SVE_VL_1056: pass
arm64_sve-ptrace_Set_SVE_VL_1072: pass
arm64_sve-ptrace_Set_SVE_VL_1088: pass
arm64_sve-ptrace_Set_SVE_VL_1104: pass
arm64_sve-ptrace_Set_SVE_VL_112: pass
arm64_sve-ptrace_Set_SVE_VL_1120: pass
arm64_sve-ptrace_Set_SVE_VL_1136: pass
arm64_sve-ptrace_Set_SVE_VL_1152: pass
arm64_sve-ptrace_Set_SVE_VL_1168: pass
arm64_sve-ptrace_Set_SVE_VL_1184: pass
arm64_sve-ptrace_Set_SVE_VL_1200: pass
arm64_sve-ptrace_Set_SVE_VL_1216: pass
arm64_sve-ptrace_Set_SVE_VL_1232: pass
arm64_sve-ptrace_Set_SVE_VL_1248: pass
arm64_sve-ptrace_Set_SVE_VL_1264: pass
arm64_sve-ptrace_Set_SVE_VL_128: pass
arm64_sve-ptrace_Set_SVE_VL_1280: pass
arm64_sve-ptrace_Set_SVE_VL_1296: pass
arm64_sve-ptrace_Set_SVE_VL_1312: pass
arm64_sve-ptrace_Set_SVE_VL_1328: pass
arm64_sve-ptrace_Set_SVE_VL_1344: pass
arm64_sve-ptrace_Set_SVE_VL_1360: pass
arm64_sve-ptrace_Set_SVE_VL_1376: pass
arm64_sve-ptrace_Set_SVE_VL_1392: pass
arm64_sve-ptrace_Set_SVE_VL_1408: pass
arm64_sve-ptrace_Set_SVE_VL_1424: pass
arm64_sve-ptrace_Set_SVE_VL_144: pass
arm64_sve-ptrace_Set_SVE_VL_1440: pass
arm64_sve-ptrace_Set_SVE_VL_1456: pass
arm64_sve-ptrace_Set_SVE_VL_1472: pass
arm64_sve-ptrace_Set_SVE_VL_1488: pass
arm64_sve-ptrace_Set_SVE_VL_1504: pass
arm64_sve-ptrace_Set_SVE_VL_1520: pass
arm64_sve-ptrace_Set_SVE_VL_1536: pass
arm64_sve-ptrace_Set_SVE_VL_1552: pass
arm64_sve-ptrace_Set_SVE_VL_1568: pass
arm64_sve-ptrace_Set_SVE_VL_1584: pass
arm64_sve-ptrace_Set_SVE_VL_16: pass
arm64_sve-ptrace_Set_SVE_VL_160: pass
arm64_sve-ptrace_Set_SVE_VL_1600: pass
arm64_sve-ptrace_Set_SVE_VL_1616: pass
arm64_sve-ptrace_Set_SVE_VL_1632: pass
arm64_sve-ptrace_Set_SVE_VL_1648: pass
arm64_sve-ptrace_Set_SVE_VL_1664: pass
arm64_sve-ptrace_Set_SVE_VL_1680: pass
arm64_sve-ptrace_Set_SVE_VL_1696: pass
arm64_sve-ptrace_Set_SVE_VL_1712: pass
arm64_sve-ptrace_Set_SVE_VL_1728: pass
arm64_sve-ptrace_Set_SVE_VL_1744: pass
arm64_sve-ptrace_Set_SVE_VL_176: pass
arm64_sve-ptrace_Set_SVE_VL_1760: pass
arm64_sve-ptrace_Set_SVE_VL_1776: pass
arm64_sve-ptrace_Set_SVE_VL_1792: pass
arm64_sve-ptrace_Set_SVE_VL_1808: pass
arm64_sve-ptrace_Set_SVE_VL_1824: pass
arm64_sve-ptrace_Set_SVE_VL_1840: pass
arm64_sve-ptrace_Set_SVE_VL_1856: pass
arm64_sve-ptrace_Set_SVE_VL_1872: pass
arm64_sve-ptrace_Set_SVE_VL_1888: pass
arm64_sve-ptrace_Set_SVE_VL_1904: pass
arm64_sve-ptrace_Set_SVE_VL_192: pass
arm64_sve-ptrace_Set_SVE_VL_1920: pass
arm64_sve-ptrace_Set_SVE_VL_1936: pass
arm64_sve-ptrace_Set_SVE_VL_1952: pass
arm64_sve-ptrace_Set_SVE_VL_1968: pass
arm64_sve-ptrace_Set_SVE_VL_1984: pass
arm64_sve-ptrace_Set_SVE_VL_2000: pass
arm64_sve-ptrace_Set_SVE_VL_2016: pass
arm64_sve-ptrace_Set_SVE_VL_2032: pass
arm64_sve-ptrace_Set_SVE_VL_2048: pass
arm64_sve-ptrace_Set_SVE_VL_2064: pass
arm64_sve-ptrace_Set_SVE_VL_208: pass
arm64_sve-ptrace_Set_SVE_VL_2080: pass
arm64_sve-ptrace_Set_SVE_VL_2096: pass
arm64_sve-ptrace_Set_SVE_VL_2112: pass
arm64_sve-ptrace_Set_SVE_VL_2128: pass
arm64_sve-ptrace_Set_SVE_VL_2144: pass
arm64_sve-ptrace_Set_SVE_VL_2160: pass
arm64_sve-ptrace_Set_SVE_VL_2176: pass
arm64_sve-ptrace_Set_SVE_VL_2192: pass
arm64_sve-ptrace_Set_SVE_VL_2208: pass
arm64_sve-ptrace_Set_SVE_VL_2224: pass
arm64_sve-ptrace_Set_SVE_VL_224: pass
arm64_sve-ptrace_Set_SVE_VL_2240: pass
arm64_sve-ptrace_Set_SVE_VL_2256: pass
arm64_sve-ptrace_Set_SVE_VL_2272: pass
arm64_sve-ptrace_Set_SVE_VL_2288: pass
arm64_sve-ptrace_Set_SVE_VL_2304: pass
arm64_sve-ptrace_Set_SVE_VL_2320: pass
arm64_sve-ptrace_Set_SVE_VL_2336: pass
arm64_sve-ptrace_Set_SVE_VL_2352: pass
arm64_sve-ptrace_Set_SVE_VL_2368: pass
arm64_sve-ptrace_Set_SVE_VL_2384: pass
arm64_sve-ptrace_Set_SVE_VL_240: pass
arm64_sve-ptrace_Set_SVE_VL_2400: pass
arm64_sve-ptrace_Set_SVE_VL_2416: pass
arm64_sve-ptrace_Set_SVE_VL_2432: pass
arm64_sve-ptrace_Set_SVE_VL_2448: pass
arm64_sve-ptrace_Set_SVE_VL_2464: pass
arm64_sve-ptrace_Set_SVE_VL_2480: pass
arm64_sve-ptrace_Set_SVE_VL_2496: pass
arm64_sve-ptrace_Set_SVE_VL_2512: pass
arm64_sve-ptrace_Set_SVE_VL_2528: pass
arm64_sve-ptrace_Set_SVE_VL_2544: pass
arm64_sve-ptrace_Set_SVE_VL_256: pass
arm64_sve-ptrace_Set_SVE_VL_2560: pass
arm64_sve-ptrace_Set_SVE_VL_2576: pass
arm64_sve-ptrace_Set_SVE_VL_2592: pass
arm64_sve-ptrace_Set_SVE_VL_2608: pass
arm64_sve-ptrace_Set_SVE_VL_2624: pass
arm64_sve-ptrace_Set_SVE_VL_2640: pass
arm64_sve-ptrace_Set_SVE_VL_2656: pass
arm64_sve-ptrace_Set_SVE_VL_2672: pass
arm64_sve-ptrace_Set_SVE_VL_2688: pass
arm64_sve-ptrace_Set_SVE_VL_2704: pass
arm64_sve-ptrace_Set_SVE_VL_272: pass
arm64_sve-ptrace_Set_SVE_VL_2720: pass
arm64_sve-ptrace_Set_SVE_VL_2736: pass
arm64_sve-ptrace_Set_SVE_VL_2752: pass
arm64_sve-ptrace_Set_SVE_VL_2768: pass
arm64_sve-ptrace_Set_SVE_VL_2784: pass
arm64_sve-ptrace_Set_SVE_VL_2800: pass
arm64_sve-ptrace_Set_SVE_VL_2816: pass
arm64_sve-ptrace_Set_SVE_VL_2832: pass
arm64_sve-ptrace_Set_SVE_VL_2848: pass
arm64_sve-ptrace_Set_SVE_VL_2864: pass
arm64_sve-ptrace_Set_SVE_VL_288: pass
arm64_sve-ptrace_Set_SVE_VL_2880: pass
arm64_sve-ptrace_Set_SVE_VL_2896: pass
arm64_sve-ptrace_Set_SVE_VL_2912: pass
arm64_sve-ptrace_Set_SVE_VL_2928: pass
arm64_sve-ptrace_Set_SVE_VL_2944: pass
arm64_sve-ptrace_Set_SVE_VL_2960: pass
arm64_sve-ptrace_Set_SVE_VL_2976: pass
arm64_sve-ptrace_Set_SVE_VL_2992: pass
arm64_sve-ptrace_Set_SVE_VL_3008: pass
arm64_sve-ptrace_Set_SVE_VL_3024: pass
arm64_sve-ptrace_Set_SVE_VL_304: pass
arm64_sve-ptrace_Set_SVE_VL_3040: pass
arm64_sve-ptrace_Set_SVE_VL_3056: pass
arm64_sve-ptrace_Set_SVE_VL_3072: pass
arm64_sve-ptrace_Set_SVE_VL_3088: pass
arm64_sve-ptrace_Set_SVE_VL_3104: pass
arm64_sve-ptrace_Set_SVE_VL_3120: pass
arm64_sve-ptrace_Set_SVE_VL_3136: pass
arm64_sve-ptrace_Set_SVE_VL_3152: pass
arm64_sve-ptrace_Set_SVE_VL_3168: pass
arm64_sve-ptrace_Set_SVE_VL_3184: pass
arm64_sve-ptrace_Set_SVE_VL_32: pass
arm64_sve-ptrace_Set_SVE_VL_320: pass
arm64_sve-ptrace_Set_SVE_VL_3200: pass
arm64_sve-ptrace_Set_SVE_VL_3216: pass
arm64_sve-ptrace_Set_SVE_VL_3232: pass
arm64_sve-ptrace_Set_SVE_VL_3248: pass
arm64_sve-ptrace_Set_SVE_VL_3264: pass
arm64_sve-ptrace_Set_SVE_VL_3280: pass
arm64_sve-ptrace_Set_SVE_VL_3296: pass
arm64_sve-ptrace_Set_SVE_VL_3312: pass
arm64_sve-ptrace_Set_SVE_VL_3328: pass
arm64_sve-ptrace_Set_SVE_VL_3344: pass
arm64_sve-ptrace_Set_SVE_VL_336: pass
arm64_sve-ptrace_Set_SVE_VL_3360: pass
arm64_sve-ptrace_Set_SVE_VL_3376: pass
arm64_sve-ptrace_Set_SVE_VL_3392: pass
arm64_sve-ptrace_Set_SVE_VL_3408: pass
arm64_sve-ptrace_Set_SVE_VL_3424: pass
arm64_sve-ptrace_Set_SVE_VL_3440: pass
arm64_sve-ptrace_Set_SVE_VL_3456: pass
arm64_sve-ptrace_Set_SVE_VL_3472: pass
arm64_sve-ptrace_Set_SVE_VL_3488: pass
arm64_sve-ptrace_Set_SVE_VL_3504: pass
arm64_sve-ptrace_Set_SVE_VL_352: pass
arm64_sve-ptrace_Set_SVE_VL_3520: pass
arm64_sve-ptrace_Set_SVE_VL_3536: pass
arm64_sve-ptrace_Set_SVE_VL_3552: pass
arm64_sve-ptrace_Set_SVE_VL_3568: pass
arm64_sve-ptrace_Set_SVE_VL_3584: pass
arm64_sve-ptrace_Set_SVE_VL_3600: pass
arm64_sve-ptrace_Set_SVE_VL_3616: pass
arm64_sve-ptrace_Set_SVE_VL_3632: pass
arm64_sve-ptrace_Set_SVE_VL_3648: pass
arm64_sve-ptrace_Set_SVE_VL_3664: pass
arm64_sve-ptrace_Set_SVE_VL_368: pass
arm64_sve-ptrace_Set_SVE_VL_3680: pass
arm64_sve-ptrace_Set_SVE_VL_3696: pass
arm64_sve-ptrace_Set_SVE_VL_3712: pass
arm64_sve-ptrace_Set_SVE_VL_3728: pass
arm64_sve-ptrace_Set_SVE_VL_3744: pass
arm64_sve-ptrace_Set_SVE_VL_3760: pass
arm64_sve-ptrace_Set_SVE_VL_3776: pass
arm64_sve-ptrace_Set_SVE_VL_3792: pass
arm64_sve-ptrace_Set_SVE_VL_3808: pass
arm64_sve-ptrace_Set_SVE_VL_3824: pass
arm64_sve-ptrace_Set_SVE_VL_384: pass
arm64_sve-ptrace_Set_SVE_VL_3840: pass
arm64_sve-ptrace_Set_SVE_VL_3856: pass
arm64_sve-ptrace_Set_SVE_VL_3872: pass
arm64_sve-ptrace_Set_SVE_VL_3888: pass
arm64_sve-ptrace_Set_SVE_VL_3904: pass
arm64_sve-ptrace_Set_SVE_VL_3920: pass
arm64_sve-ptrace_Set_SVE_VL_3936: pass
arm64_sve-ptrace_Set_SVE_VL_3952: pass
arm64_sve-ptrace_Set_SVE_VL_3968: pass
arm64_sve-ptrace_Set_SVE_VL_3984: pass
arm64_sve-ptrace_Set_SVE_VL_400: pass
arm64_sve-ptrace_Set_SVE_VL_4000: pass
arm64_sve-ptrace_Set_SVE_VL_4016: pass
arm64_sve-ptrace_Set_SVE_VL_4032: pass
arm64_sve-ptrace_Set_SVE_VL_4048: pass
arm64_sve-ptrace_Set_SVE_VL_4064: pass
arm64_sve-ptrace_Set_SVE_VL_4080: pass
arm64_sve-ptrace_Set_SVE_VL_4096: pass
arm64_sve-ptrace_Set_SVE_VL_4112: pass
arm64_sve-ptrace_Set_SVE_VL_4128: pass
arm64_sve-ptrace_Set_SVE_VL_4144: pass
arm64_sve-ptrace_Set_SVE_VL_416: pass
arm64_sve-ptrace_Set_SVE_VL_4160: pass
arm64_sve-ptrace_Set_SVE_VL_4176: pass
arm64_sve-ptrace_Set_SVE_VL_4192: pass
arm64_sve-ptrace_Set_SVE_VL_4208: pass
arm64_sve-ptrace_Set_SVE_VL_4224: pass
arm64_sve-ptrace_Set_SVE_VL_4240: pass
arm64_sve-ptrace_Set_SVE_VL_4256: pass
arm64_sve-ptrace_Set_SVE_VL_4272: pass
arm64_sve-ptrace_Set_SVE_VL_4288: pass
arm64_sve-ptrace_Set_SVE_VL_4304: pass
arm64_sve-ptrace_Set_SVE_VL_432: pass
arm64_sve-ptrace_Set_SVE_VL_4320: pass
arm64_sve-ptrace_Set_SVE_VL_4336: pass
arm64_sve-ptrace_Set_SVE_VL_4352: pass
arm64_sve-ptrace_Set_SVE_VL_4368: pass
arm64_sve-ptrace_Set_SVE_VL_4384: pass
arm64_sve-ptrace_Set_SVE_VL_4400: pass
arm64_sve-ptrace_Set_SVE_VL_4416: pass
arm64_sve-ptrace_Set_SVE_VL_4432: pass
arm64_sve-ptrace_Set_SVE_VL_4448: pass
arm64_sve-ptrace_Set_SVE_VL_4464: pass
arm64_sve-ptrace_Set_SVE_VL_448: pass
arm64_sve-ptrace_Set_SVE_VL_4480: pass
arm64_sve-ptrace_Set_SVE_VL_4496: pass
arm64_sve-ptrace_Set_SVE_VL_4512: pass
arm64_sve-ptrace_Set_SVE_VL_4528: pass
arm64_sve-ptrace_Set_SVE_VL_4544: pass
arm64_sve-ptrace_Set_SVE_VL_4560: pass
arm64_sve-ptrace_Set_SVE_VL_4576: pass
arm64_sve-ptrace_Set_SVE_VL_4592: pass
arm64_sve-ptrace_Set_SVE_VL_4608: pass
arm64_sve-ptrace_Set_SVE_VL_4624: pass
arm64_sve-ptrace_Set_SVE_VL_464: pass
arm64_sve-ptrace_Set_SVE_VL_4640: pass
arm64_sve-ptrace_Set_SVE_VL_4656: pass
arm64_sve-ptrace_Set_SVE_VL_4672: pass
arm64_sve-ptrace_Set_SVE_VL_4688: pass
arm64_sve-ptrace_Set_SVE_VL_4704: pass
arm64_sve-ptrace_Set_SVE_VL_4720: pass
arm64_sve-ptrace_Set_SVE_VL_4736: pass
arm64_sve-ptrace_Set_SVE_VL_4752: pass
arm64_sve-ptrace_Set_SVE_VL_4768: pass
arm64_sve-ptrace_Set_SVE_VL_4784: pass
arm64_sve-ptrace_Set_SVE_VL_48: pass
arm64_sve-ptrace_Set_SVE_VL_480: pass
arm64_sve-ptrace_Set_SVE_VL_4800: pass
arm64_sve-ptrace_Set_SVE_VL_4816: pass
arm64_sve-ptrace_Set_SVE_VL_4832: pass
arm64_sve-ptrace_Set_SVE_VL_4848: pass
arm64_sve-ptrace_Set_SVE_VL_4864: pass
arm64_sve-ptrace_Set_SVE_VL_4880: pass
arm64_sve-ptrace_Set_SVE_VL_4896: pass
arm64_sve-ptrace_Set_SVE_VL_4912: pass
arm64_sve-ptrace_Set_SVE_VL_4928: pass
arm64_sve-ptrace_Set_SVE_VL_4944: pass
arm64_sve-ptrace_Set_SVE_VL_496: pass
arm64_sve-ptrace_Set_SVE_VL_4960: pass
arm64_sve-ptrace_Set_SVE_VL_4976: pass
arm64_sve-ptrace_Set_SVE_VL_4992: pass
arm64_sve-ptrace_Set_SVE_VL_5008: pass
arm64_sve-ptrace_Set_SVE_VL_5024: pass
arm64_sve-ptrace_Set_SVE_VL_5040: pass
arm64_sve-ptrace_Set_SVE_VL_5056: pass
arm64_sve-ptrace_Set_SVE_VL_5072: pass
arm64_sve-ptrace_Set_SVE_VL_5088: pass
arm64_sve-ptrace_Set_SVE_VL_5104: pass
arm64_sve-ptrace_Set_SVE_VL_512: pass
arm64_sve-ptrace_Set_SVE_VL_5120: pass
arm64_sve-ptrace_Set_SVE_VL_5136: pass
arm64_sve-ptrace_Set_SVE_VL_5152: pass
arm64_sve-ptrace_Set_SVE_VL_5168: pass
arm64_sve-ptrace_Set_SVE_VL_5184: pass
arm64_sve-ptrace_Set_SVE_VL_5200: pass
arm64_sve-ptrace_Set_SVE_VL_5216: pass
arm64_sve-ptrace_Set_SVE_VL_5232: pass
arm64_sve-ptrace_Set_SVE_VL_5248: pass
arm64_sve-ptrace_Set_SVE_VL_5264: pass
arm64_sve-ptrace_Set_SVE_VL_528: pass
arm64_sve-ptrace_Set_SVE_VL_5280: pass
arm64_sve-ptrace_Set_SVE_VL_5296: pass
arm64_sve-ptrace_Set_SVE_VL_5312: pass
arm64_sve-ptrace_Set_SVE_VL_5328: pass
arm64_sve-ptrace_Set_SVE_VL_5344: pass
arm64_sve-ptrace_Set_SVE_VL_5360: pass
arm64_sve-ptrace_Set_SVE_VL_5376: pass
arm64_sve-ptrace_Set_SVE_VL_5392: pass
arm64_sve-ptrace_Set_SVE_VL_5408: pass
arm64_sve-ptrace_Set_SVE_VL_5424: pass
arm64_sve-ptrace_Set_SVE_VL_544: pass
arm64_sve-ptrace_Set_SVE_VL_5440: pass
arm64_sve-ptrace_Set_SVE_VL_5456: pass
arm64_sve-ptrace_Set_SVE_VL_5472: pass
arm64_sve-ptrace_Set_SVE_VL_5488: pass
arm64_sve-ptrace_Set_SVE_VL_5504: pass
arm64_sve-ptrace_Set_SVE_VL_5520: pass
arm64_sve-ptrace_Set_SVE_VL_5536: pass
arm64_sve-ptrace_Set_SVE_VL_5552: pass
arm64_sve-ptrace_Set_SVE_VL_5568: pass
arm64_sve-ptrace_Set_SVE_VL_5584: pass
arm64_sve-ptrace_Set_SVE_VL_560: pass
arm64_sve-ptrace_Set_SVE_VL_5600: pass
arm64_sve-ptrace_Set_SVE_VL_5616: pass
arm64_sve-ptrace_Set_SVE_VL_5632: pass
arm64_sve-ptrace_Set_SVE_VL_5648: pass
arm64_sve-ptrace_Set_SVE_VL_5664: pass
arm64_sve-ptrace_Set_SVE_VL_5680: pass
arm64_sve-ptrace_Set_SVE_VL_5696: pass
arm64_sve-ptrace_Set_SVE_VL_5712: pass
arm64_sve-ptrace_Set_SVE_VL_5728: pass
arm64_sve-ptrace_Set_SVE_VL_5744: pass
arm64_sve-ptrace_Set_SVE_VL_576: pass
arm64_sve-ptrace_Set_SVE_VL_5760: pass
arm64_sve-ptrace_Set_SVE_VL_5776: pass
arm64_sve-ptrace_Set_SVE_VL_5792: pass
arm64_sve-ptrace_Set_SVE_VL_5808: pass
arm64_sve-ptrace_Set_SVE_VL_5824: pass
arm64_sve-ptrace_Set_SVE_VL_5840: pass
arm64_sve-ptrace_Set_SVE_VL_5856: pass
arm64_sve-ptrace_Set_SVE_VL_5872: pass
arm64_sve-ptrace_Set_SVE_VL_5888: pass
arm64_sve-ptrace_Set_SVE_VL_5904: pass
arm64_sve-ptrace_Set_SVE_VL_592: pass
arm64_sve-ptrace_Set_SVE_VL_5920: pass
arm64_sve-ptrace_Set_SVE_VL_5936: pass
arm64_sve-ptrace_Set_SVE_VL_5952: pass
arm64_sve-ptrace_Set_SVE_VL_5968: pass
arm64_sve-ptrace_Set_SVE_VL_5984: pass
arm64_sve-ptrace_Set_SVE_VL_6000: pass
arm64_sve-ptrace_Set_SVE_VL_6016: pass
arm64_sve-ptrace_Set_SVE_VL_6032: pass
arm64_sve-ptrace_Set_SVE_VL_6048: pass
arm64_sve-ptrace_Set_SVE_VL_6064: pass
arm64_sve-ptrace_Set_SVE_VL_608: pass
arm64_sve-ptrace_Set_SVE_VL_6080: pass
arm64_sve-ptrace_Set_SVE_VL_6096: pass
arm64_sve-ptrace_Set_SVE_VL_6112: pass
arm64_sve-ptrace_Set_SVE_VL_6128: pass
arm64_sve-ptrace_Set_SVE_VL_6144: pass
arm64_sve-ptrace_Set_SVE_VL_6160: pass
arm64_sve-ptrace_Set_SVE_VL_6176: pass
arm64_sve-ptrace_Set_SVE_VL_6192: pass
arm64_sve-ptrace_Set_SVE_VL_6208: pass
arm64_sve-ptrace_Set_SVE_VL_6224: pass
arm64_sve-ptrace_Set_SVE_VL_624: pass
arm64_sve-ptrace_Set_SVE_VL_6240: pass
arm64_sve-ptrace_Set_SVE_VL_6256: pass
arm64_sve-ptrace_Set_SVE_VL_6272: pass
arm64_sve-ptrace_Set_SVE_VL_6288: pass
arm64_sve-ptrace_Set_SVE_VL_6304: pass
arm64_sve-ptrace_Set_SVE_VL_6320: pass
arm64_sve-ptrace_Set_SVE_VL_6336: pass
arm64_sve-ptrace_Set_SVE_VL_6352: pass
arm64_sve-ptrace_Set_SVE_VL_6368: pass
arm64_sve-ptrace_Set_SVE_VL_6384: pass
arm64_sve-ptrace_Set_SVE_VL_64: pass
arm64_sve-ptrace_Set_SVE_VL_640: pass
arm64_sve-ptrace_Set_SVE_VL_6400: pass
arm64_sve-ptrace_Set_SVE_VL_6416: pass
arm64_sve-ptrace_Set_SVE_VL_6432: pass
arm64_sve-ptrace_Set_SVE_VL_6448: pass
arm64_sve-ptrace_Set_SVE_VL_6464: pass
arm64_sve-ptrace_Set_SVE_VL_6480: pass
arm64_sve-ptrace_Set_SVE_VL_6496: pass
arm64_sve-ptrace_Set_SVE_VL_6512: pass
arm64_sve-ptrace_Set_SVE_VL_6528: pass
arm64_sve-ptrace_Set_SVE_VL_6544: pass
arm64_sve-ptrace_Set_SVE_VL_656: pass
arm64_sve-ptrace_Set_SVE_VL_6560: pass
arm64_sve-ptrace_Set_SVE_VL_6576: pass
arm64_sve-ptrace_Set_SVE_VL_6592: pass
arm64_sve-ptrace_Set_SVE_VL_6608: pass
arm64_sve-ptrace_Set_SVE_VL_6624: pass
arm64_sve-ptrace_Set_SVE_VL_6640: pass
arm64_sve-ptrace_Set_SVE_VL_6656: pass
arm64_sve-ptrace_Set_SVE_VL_6672: pass
arm64_sve-ptrace_Set_SVE_VL_6688: pass
arm64_sve-ptrace_Set_SVE_VL_6704: pass
arm64_sve-ptrace_Set_SVE_VL_672: pass
arm64_sve-ptrace_Set_SVE_VL_6720: pass
arm64_sve-ptrace_Set_SVE_VL_6736: pass
arm64_sve-ptrace_Set_SVE_VL_6752: pass
arm64_sve-ptrace_Set_SVE_VL_6768: pass
arm64_sve-ptrace_Set_SVE_VL_6784: pass
arm64_sve-ptrace_Set_SVE_VL_6800: pass
arm64_sve-ptrace_Set_SVE_VL_6816: pass
arm64_sve-ptrace_Set_SVE_VL_6832: pass
arm64_sve-ptrace_Set_SVE_VL_6848: pass
arm64_sve-ptrace_Set_SVE_VL_6864: pass
arm64_sve-ptrace_Set_SVE_VL_688: pass
arm64_sve-ptrace_Set_SVE_VL_6880: pass
arm64_sve-ptrace_Set_SVE_VL_6896: pass
arm64_sve-ptrace_Set_SVE_VL_6912: pass
arm64_sve-ptrace_Set_SVE_VL_6928: pass
arm64_sve-ptrace_Set_SVE_VL_6944: pass
arm64_sve-ptrace_Set_SVE_VL_6960: pass
arm64_sve-ptrace_Set_SVE_VL_6976: pass
arm64_sve-ptrace_Set_SVE_VL_6992: pass
arm64_sve-ptrace_Set_SVE_VL_7008: pass
arm64_sve-ptrace_Set_SVE_VL_7024: pass
arm64_sve-ptrace_Set_SVE_VL_704: pass
arm64_sve-ptrace_Set_SVE_VL_7040: pass
arm64_sve-ptrace_Set_SVE_VL_7056: pass
arm64_sve-ptrace_Set_SVE_VL_7072: pass
arm64_sve-ptrace_Set_SVE_VL_7088: pass
arm64_sve-ptrace_Set_SVE_VL_7104: pass
arm64_sve-ptrace_Set_SVE_VL_7120: pass
arm64_sve-ptrace_Set_SVE_VL_7136: pass
arm64_sve-ptrace_Set_SVE_VL_7152: pass
arm64_sve-ptrace_Set_SVE_VL_7168: pass
arm64_sve-ptrace_Set_SVE_VL_7184: pass
arm64_sve-ptrace_Set_SVE_VL_720: pass
arm64_sve-ptrace_Set_SVE_VL_7200: pass
arm64_sve-ptrace_Set_SVE_VL_7216: pass
arm64_sve-ptrace_Set_SVE_VL_7232: pass
arm64_sve-ptrace_Set_SVE_VL_7248: pass
arm64_sve-ptrace_Set_SVE_VL_7264: pass
arm64_sve-ptrace_Set_SVE_VL_7280: pass
arm64_sve-ptrace_Set_SVE_VL_7296: pass
arm64_sve-ptrace_Set_SVE_VL_7312: pass
arm64_sve-ptrace_Set_SVE_VL_7328: pass
arm64_sve-ptrace_Set_SVE_VL_7344: pass
arm64_sve-ptrace_Set_SVE_VL_736: pass
arm64_sve-ptrace_Set_SVE_VL_7360: pass
arm64_sve-ptrace_Set_SVE_VL_7376: pass
arm64_sve-ptrace_Set_SVE_VL_7392: pass
arm64_sve-ptrace_Set_SVE_VL_7408: pass
arm64_sve-ptrace_Set_SVE_VL_7424: pass
arm64_sve-ptrace_Set_SVE_VL_7440: pass
arm64_sve-ptrace_Set_SVE_VL_7456: pass
arm64_sve-ptrace_Set_SVE_VL_7472: pass
arm64_sve-ptrace_Set_SVE_VL_7488: pass
arm64_sve-ptrace_Set_SVE_VL_7504: pass
arm64_sve-ptrace_Set_SVE_VL_752: pass
arm64_sve-ptrace_Set_SVE_VL_7520: pass
arm64_sve-ptrace_Set_SVE_VL_7536: pass
arm64_sve-ptrace_Set_SVE_VL_7552: pass
arm64_sve-ptrace_Set_SVE_VL_7568: pass
arm64_sve-ptrace_Set_SVE_VL_7584: pass
arm64_sve-ptrace_Set_SVE_VL_7600: pass
arm64_sve-ptrace_Set_SVE_VL_7616: pass
arm64_sve-ptrace_Set_SVE_VL_7632: pass
arm64_sve-ptrace_Set_SVE_VL_7648: pass
arm64_sve-ptrace_Set_SVE_VL_7664: pass
arm64_sve-ptrace_Set_SVE_VL_768: pass
arm64_sve-ptrace_Set_SVE_VL_7680: pass
arm64_sve-ptrace_Set_SVE_VL_7696: pass
arm64_sve-ptrace_Set_SVE_VL_7712: pass
arm64_sve-ptrace_Set_SVE_VL_7728: pass
arm64_sve-ptrace_Set_SVE_VL_7744: pass
arm64_sve-ptrace_Set_SVE_VL_7760: pass
arm64_sve-ptrace_Set_SVE_VL_7776: pass
arm64_sve-ptrace_Set_SVE_VL_7792: pass
arm64_sve-ptrace_Set_SVE_VL_7808: pass
arm64_sve-ptrace_Set_SVE_VL_7824: pass
arm64_sve-ptrace_Set_SVE_VL_784: pass
arm64_sve-ptrace_Set_SVE_VL_7840: pass
arm64_sve-ptrace_Set_SVE_VL_7856: pass
arm64_sve-ptrace_Set_SVE_VL_7872: pass
arm64_sve-ptrace_Set_SVE_VL_7888: pass
arm64_sve-ptrace_Set_SVE_VL_7904: pass
arm64_sve-ptrace_Set_SVE_VL_7920: pass
arm64_sve-ptrace_Set_SVE_VL_7936: pass
arm64_sve-ptrace_Set_SVE_VL_7952: pass
arm64_sve-ptrace_Set_SVE_VL_7968: pass
arm64_sve-ptrace_Set_SVE_VL_7984: pass
arm64_sve-ptrace_Set_SVE_VL_80: pass
arm64_sve-ptrace_Set_SVE_VL_800: pass
arm64_sve-ptrace_Set_SVE_VL_8000: pass
arm64_sve-ptrace_Set_SVE_VL_8016: pass
arm64_sve-ptrace_Set_SVE_VL_8032: pass
arm64_sve-ptrace_Set_SVE_VL_8048: pass
arm64_sve-ptrace_Set_SVE_VL_8064: pass
arm64_sve-ptrace_Set_SVE_VL_8080: pass
arm64_sve-ptrace_Set_SVE_VL_8096: pass
arm64_sve-ptrace_Set_SVE_VL_8112: pass
arm64_sve-ptrace_Set_SVE_VL_8128: pass
arm64_sve-ptrace_Set_SVE_VL_8144: pass
arm64_sve-ptrace_Set_SVE_VL_816: pass
arm64_sve-ptrace_Set_SVE_VL_8160: pass
arm64_sve-ptrace_Set_SVE_VL_8176: pass
arm64_sve-ptrace_Set_SVE_VL_8192: pass
arm64_sve-ptrace_Set_SVE_VL_832: pass
arm64_sve-ptrace_Set_SVE_VL_848: pass
arm64_sve-ptrace_Set_SVE_VL_864: pass
arm64_sve-ptrace_Set_SVE_VL_880: pass
arm64_sve-ptrace_Set_SVE_VL_896: pass
arm64_sve-ptrace_Set_SVE_VL_912: pass
arm64_sve-ptrace_Set_SVE_VL_928: pass
arm64_sve-ptrace_Set_SVE_VL_944: pass
arm64_sve-ptrace_Set_SVE_VL_96: pass
arm64_sve-ptrace_Set_SVE_VL_960: pass
arm64_sve-ptrace_Set_SVE_VL_976: pass
arm64_sve-ptrace_Set_SVE_VL_992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_1984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_2992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_3984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_48: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_4992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_5984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6208: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6224: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6240: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6256: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6272: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6288: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6304: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6320: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6336: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6352: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6368: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6384: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6400: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6416: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6432: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6448: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6464: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6480: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6496: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6512: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6528: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6544: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6560: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6576: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6592: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6608: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6624: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6640: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6656: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_672: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_688: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_6992: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7008: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7024: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_704: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7040: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7056: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7072: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7088: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7104: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7120: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7136: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7152: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7168: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7184: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_720: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7200: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7216: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7232: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7248: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7264: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7280: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7296: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7312: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7328: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7344: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_736: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7360: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7376: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7392: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7408: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7424: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7440: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7456: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7472: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7488: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7504: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_752: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7520: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7536: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7552: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7568: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7584: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7600: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7616: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7632: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7648: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7664: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_768: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7680: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7696: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7712: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7728: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7744: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7760: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7776: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7792: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7808: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7824: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_784: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7840: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7856: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7872: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7888: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7904: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7920: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7936: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7952: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7968: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_7984: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_80: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_800: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8000: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8016: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8032: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8048: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8064: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8080: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8096: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8112: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8128: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8144: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_816: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8160: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8176: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_8192: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_832: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_848: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_864: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_880: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_896: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_912: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_928: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_944: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_96: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_960: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_976: pass
arm64_sve-ptrace_Set_Streaming_SVE_VL_992: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_112: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_144: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_160: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_176: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_192: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_208: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_224: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_240: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_48: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_80: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_SVE_VL_96: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_128: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_16: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_256: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_32: pass
arm64_sve-ptrace_Set_and_get_FPSIMD_data_for_Streaming_SVE_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_112: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_144: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_160: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_176: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_192: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_208: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_224: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_240: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_48: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_80: pass
arm64_sve-ptrace_Set_and_get_SVE_data_for_VL_96: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_128: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_16: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_256: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_32: pass
arm64_sve-ptrace_Set_and_get_Streaming_SVE_data_for_VL_64: pass
arm64_sve-ptrace_Streaming_SVE_FPSIMD_set_via_SVE_0: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_cleared: pass
arm64_sve-ptrace_Streaming_SVE_SVE_PT_VL_INHERIT_set: pass
arm64_sve-ptrace_Streaming_SVE_get_fpsimd_gave_same_state: pass
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_FPSIMD_get_SVE_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_FPSIMD_for_VL_992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_1984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_2992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_3984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_48: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_4992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_5984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6208: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6224: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6240: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6256: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6272: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6288: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6304: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6320: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6336: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6352: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6368: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6384: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6400: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6416: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6432: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6448: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6464: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6480: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6496: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6512: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6528: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6544: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6560: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6576: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6592: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6608: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6624: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6640: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6656: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_672: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_688: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_6992: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7008: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7024: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_704: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7040: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7056: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7072: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7088: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7104: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7120: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7136: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7152: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7168: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7184: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_720: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7200: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7216: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7232: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7248: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7264: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7280: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7296: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7312: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7328: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7344: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_736: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7360: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7376: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7392: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7408: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7424: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7440: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7456: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7472: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7488: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7504: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_752: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7520: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7536: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7552: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7568: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7584: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7600: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7616: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7632: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7648: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7664: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_768: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7680: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7696: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7712: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7728: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7744: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7760: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7776: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7792: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7808: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7824: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_784: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7840: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7856: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7872: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7888: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7904: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7920: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7936: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7952: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7968: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_7984: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_80: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_800: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8000: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8016: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8032: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8048: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8064: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8080: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8096: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8112: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8128: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8144: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_816: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8160: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8176: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_8192: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_832: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_848: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_864: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_880: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_896: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_912: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_928: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_944: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_96: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_960: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_976: skip
arm64_sve-ptrace_Streaming_SVE_set_SVE_get_SVE_for_VL_992: skip
arm64_sve_regs: pass
arm64_sve_vl: pass
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_getpid_SVE_VL_112: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16: pass
arm64_syscall-abi_getpid_SVE_VL_160: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_getpid_SVE_VL_96_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_syscall-abi_sched_yield_SVE_VL_112: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_112_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_128_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_144_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16: pass
arm64_syscall-abi_sched_yield_SVE_VL_160: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_160_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_16_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_176_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_192_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_208_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_224_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_240_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_256_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_32_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_48_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_64_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_80_SME_VL_64_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_128_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_16_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_256_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_32_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_SM_ZA: pass
arm64_syscall-abi_sched_yield_SVE_VL_96_SME_VL_64_ZA: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_default_value: pass
arm64_tpidr2_write_clone_read: pass
arm64_tpidr2_write_fork_read: pass
arm64_tpidr2_write_read: pass
arm64_tpidr2_write_sleep_read: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_current_VL_is_32: pass
arm64_vec-syscfg_SME_default_vector_length_32: pass
arm64_vec-syscfg_SME_maximum_vector_length_256: pass
arm64_vec-syscfg_SME_minimum_vector_length_16: pass
arm64_vec-syscfg_SME_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SME_prctl_set_min_max: pass
arm64_vec-syscfg_SME_set_VL_32_and_have_VL_32: pass
arm64_vec-syscfg_SME_vector_length_set_on_exec: pass
arm64_vec-syscfg_SME_vector_length_used_default: pass
arm64_vec-syscfg_SME_vector_length_was_inherited: pass
arm64_vec-syscfg_SVE_current_VL_is_64: pass
arm64_vec-syscfg_SVE_default_vector_length_64: pass
arm64_vec-syscfg_SVE_maximum_vector_length_256: pass
arm64_vec-syscfg_SVE_minimum_vector_length_16: pass
arm64_vec-syscfg_SVE_prctl_set_all_VLs_0_errors: pass
arm64_vec-syscfg_SVE_prctl_set_min_max: pass
arm64_vec-syscfg_SVE_set_VL_64_and_have_VL_64: pass
arm64_vec-syscfg_SVE_vector_length_set_on_exec: pass
arm64_vec-syscfg_SVE_vector_length_used_default: pass
arm64_vec-syscfg_SVE_vector_length_was_inherited: pass
arm64_za-fork: pass
arm64_za-fork_fork_test: pass
arm64_za-ptrace: pass
arm64_za-ptrace_Data_match_for_VL_128: pass
arm64_za-ptrace_Data_match_for_VL_16: pass
arm64_za-ptrace_Data_match_for_VL_256: pass
arm64_za-ptrace_Data_match_for_VL_32: pass
arm64_za-ptrace_Data_match_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_128: pass
arm64_za-ptrace_Disabled_ZA_for_VL_1280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_16: pass
arm64_za-ptrace_Disabled_ZA_for_VL_160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_1984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_256: pass
arm64_za-ptrace_Disabled_ZA_for_VL_2560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_2992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_32: pass
arm64_za-ptrace_Disabled_ZA_for_VL_320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_3984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_48: skip
arm64_za-ptrace_Disabled_ZA_for_VL_480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_4992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_5984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6208: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6224: skip
arm64_za-ptrace_Disabled_ZA_for_VL_624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6240: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6256: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6272: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6288: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6304: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6320: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6336: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6352: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6368: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6384: skip
arm64_za-ptrace_Disabled_ZA_for_VL_64: pass
arm64_za-ptrace_Disabled_ZA_for_VL_640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6400: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6416: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6432: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6448: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6464: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6480: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6496: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6512: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6528: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6544: skip
arm64_za-ptrace_Disabled_ZA_for_VL_656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6560: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6576: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6592: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6608: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6624: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6640: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6656: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_672: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_688: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_6992: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7008: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7024: skip
arm64_za-ptrace_Disabled_ZA_for_VL_704: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7040: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7056: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7072: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7088: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7104: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7120: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7136: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7152: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7168: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7184: skip
arm64_za-ptrace_Disabled_ZA_for_VL_720: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7200: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7216: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7232: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7248: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7264: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7280: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7296: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7312: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7328: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7344: skip
arm64_za-ptrace_Disabled_ZA_for_VL_736: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7360: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7376: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7392: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7408: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7424: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7440: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7456: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7472: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7488: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7504: skip
arm64_za-ptrace_Disabled_ZA_for_VL_752: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7520: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7536: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7552: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7568: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7584: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7600: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7616: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7632: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7648: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7664: skip
arm64_za-ptrace_Disabled_ZA_for_VL_768: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7680: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7696: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7712: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7728: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7744: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7760: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7776: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7792: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7808: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7824: skip
arm64_za-ptrace_Disabled_ZA_for_VL_784: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7840: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7856: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7872: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7888: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7904: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7920: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7936: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7952: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7968: skip
arm64_za-ptrace_Disabled_ZA_for_VL_7984: skip
arm64_za-ptrace_Disabled_ZA_for_VL_80: skip
arm64_za-ptrace_Disabled_ZA_for_VL_800: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8000: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8016: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8032: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8048: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8064: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8080: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8096: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8112: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8128: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8144: skip
arm64_za-ptrace_Disabled_ZA_for_VL_816: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8160: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8176: skip
arm64_za-ptrace_Disabled_ZA_for_VL_8192: skip
arm64_za-ptrace_Disabled_ZA_for_VL_832: skip
arm64_za-ptrace_Disabled_ZA_for_VL_848: skip
arm64_za-ptrace_Disabled_ZA_for_VL_864: skip
arm64_za-ptrace_Disabled_ZA_for_VL_880: skip
arm64_za-ptrace_Disabled_ZA_for_VL_896: skip
arm64_za-ptrace_Disabled_ZA_for_VL_912: skip
arm64_za-ptrace_Disabled_ZA_for_VL_928: skip
arm64_za-ptrace_Disabled_ZA_for_VL_944: skip
arm64_za-ptrace_Disabled_ZA_for_VL_96: skip
arm64_za-ptrace_Disabled_ZA_for_VL_960: skip
arm64_za-ptrace_Disabled_ZA_for_VL_976: skip
arm64_za-ptrace_Disabled_ZA_for_VL_992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_1984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_2992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_3984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_48: skip
arm64_za-ptrace_Get_and_set_data_for_VL_480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_4992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_5984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6208: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6224: skip
arm64_za-ptrace_Get_and_set_data_for_VL_624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6240: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6256: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6272: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6288: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6304: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6320: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6336: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6352: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6368: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6384: skip
arm64_za-ptrace_Get_and_set_data_for_VL_640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6400: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6416: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6432: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6448: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6464: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6480: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6496: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6512: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6528: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6544: skip
arm64_za-ptrace_Get_and_set_data_for_VL_656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6560: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6576: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6592: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6608: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6624: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6640: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6656: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_672: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_688: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_6992: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7008: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7024: skip
arm64_za-ptrace_Get_and_set_data_for_VL_704: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7040: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7056: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7072: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7088: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7104: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7120: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7136: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7152: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7168: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7184: skip
arm64_za-ptrace_Get_and_set_data_for_VL_720: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7200: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7216: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7232: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7248: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7264: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7280: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7296: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7312: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7328: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7344: skip
arm64_za-ptrace_Get_and_set_data_for_VL_736: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7360: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7376: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7392: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7408: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7424: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7440: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7456: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7472: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7488: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7504: skip
arm64_za-ptrace_Get_and_set_data_for_VL_752: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7520: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7536: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7552: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7568: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7584: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7600: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7616: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7632: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7648: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7664: skip
arm64_za-ptrace_Get_and_set_data_for_VL_768: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7680: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7696: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7712: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7728: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7744: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7760: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7776: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7792: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7808: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7824: skip
arm64_za-ptrace_Get_and_set_data_for_VL_784: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7840: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7856: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7872: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7888: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7904: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7920: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7936: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7952: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7968: skip
arm64_za-ptrace_Get_and_set_data_for_VL_7984: skip
arm64_za-ptrace_Get_and_set_data_for_VL_80: skip
arm64_za-ptrace_Get_and_set_data_for_VL_800: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8000: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8016: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8032: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8048: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8064: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8080: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8096: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8112: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8128: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8144: skip
arm64_za-ptrace_Get_and_set_data_for_VL_816: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8160: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8176: skip
arm64_za-ptrace_Get_and_set_data_for_VL_8192: skip
arm64_za-ptrace_Get_and_set_data_for_VL_832: skip
arm64_za-ptrace_Get_and_set_data_for_VL_848: skip
arm64_za-ptrace_Get_and_set_data_for_VL_864: skip
arm64_za-ptrace_Get_and_set_data_for_VL_880: skip
arm64_za-ptrace_Get_and_set_data_for_VL_896: skip
arm64_za-ptrace_Get_and_set_data_for_VL_912: skip
arm64_za-ptrace_Get_and_set_data_for_VL_928: skip
arm64_za-ptrace_Get_and_set_data_for_VL_944: skip
arm64_za-ptrace_Get_and_set_data_for_VL_96: skip
arm64_za-ptrace_Get_and_set_data_for_VL_960: skip
arm64_za-ptrace_Get_and_set_data_for_VL_976: skip
arm64_za-ptrace_Get_and_set_data_for_VL_992: skip
arm64_za-ptrace_Set_VL_1008: pass
arm64_za-ptrace_Set_VL_1024: pass
arm64_za-ptrace_Set_VL_1040: pass
arm64_za-ptrace_Set_VL_1056: pass
arm64_za-ptrace_Set_VL_1072: pass
arm64_za-ptrace_Set_VL_1088: pass
arm64_za-ptrace_Set_VL_1104: pass
arm64_za-ptrace_Set_VL_112: pass
arm64_za-ptrace_Set_VL_1120: pass
arm64_za-ptrace_Set_VL_1136: pass
arm64_za-ptrace_Set_VL_1152: pass
arm64_za-ptrace_Set_VL_1168: pass
arm64_za-ptrace_Set_VL_1184: pass
arm64_za-ptrace_Set_VL_1200: pass
arm64_za-ptrace_Set_VL_1216: pass
arm64_za-ptrace_Set_VL_1232: pass
arm64_za-ptrace_Set_VL_1248: pass
arm64_za-ptrace_Set_VL_1264: pass
arm64_za-ptrace_Set_VL_128: pass
arm64_za-ptrace_Set_VL_1280: pass
arm64_za-ptrace_Set_VL_1296: pass
arm64_za-ptrace_Set_VL_1312: pass
arm64_za-ptrace_Set_VL_1328: pass
arm64_za-ptrace_Set_VL_1344: pass
arm64_za-ptrace_Set_VL_1360: pass
arm64_za-ptrace_Set_VL_1376: pass
arm64_za-ptrace_Set_VL_1392: pass
arm64_za-ptrace_Set_VL_1408: pass
arm64_za-ptrace_Set_VL_1424: pass
arm64_za-ptrace_Set_VL_144: pass
arm64_za-ptrace_Set_VL_1440: pass
arm64_za-ptrace_Set_VL_1456: pass
arm64_za-ptrace_Set_VL_1472: pass
arm64_za-ptrace_Set_VL_1488: pass
arm64_za-ptrace_Set_VL_1504: pass
arm64_za-ptrace_Set_VL_1520: pass
arm64_za-ptrace_Set_VL_1536: pass
arm64_za-ptrace_Set_VL_1552: pass
arm64_za-ptrace_Set_VL_1568: pass
arm64_za-ptrace_Set_VL_1584: pass
arm64_za-ptrace_Set_VL_16: pass
arm64_za-ptrace_Set_VL_160: pass
arm64_za-ptrace_Set_VL_1600: pass
arm64_za-ptrace_Set_VL_1616: pass
arm64_za-ptrace_Set_VL_1632: pass
arm64_za-ptrace_Set_VL_1648: pass
arm64_za-ptrace_Set_VL_1664: pass
arm64_za-ptrace_Set_VL_1680: pass
arm64_za-ptrace_Set_VL_1696: pass
arm64_za-ptrace_Set_VL_1712: pass
arm64_za-ptrace_Set_VL_1728: pass
arm64_za-ptrace_Set_VL_1744: pass
arm64_za-ptrace_Set_VL_176: pass
arm64_za-ptrace_Set_VL_1760: pass
arm64_za-ptrace_Set_VL_1776: pass
arm64_za-ptrace_Set_VL_1792: pass
arm64_za-ptrace_Set_VL_1808: pass
arm64_za-ptrace_Set_VL_1824: pass
arm64_za-ptrace_Set_VL_1840: pass
arm64_za-ptrace_Set_VL_1856: pass
arm64_za-ptrace_Set_VL_1872: pass
arm64_za-ptrace_Set_VL_1888: pass
arm64_za-ptrace_Set_VL_1904: pass
arm64_za-ptrace_Set_VL_192: pass
arm64_za-ptrace_Set_VL_1920: pass
arm64_za-ptrace_Set_VL_1936: pass
arm64_za-ptrace_Set_VL_1952: pass
arm64_za-ptrace_Set_VL_1968: pass
arm64_za-ptrace_Set_VL_1984: pass
arm64_za-ptrace_Set_VL_2000: pass
arm64_za-ptrace_Set_VL_2016: pass
arm64_za-ptrace_Set_VL_2032: pass
arm64_za-ptrace_Set_VL_2048: pass
arm64_za-ptrace_Set_VL_2064: pass
arm64_za-ptrace_Set_VL_208: pass
arm64_za-ptrace_Set_VL_2080: pass
arm64_za-ptrace_Set_VL_2096: pass
arm64_za-ptrace_Set_VL_2112: pass
arm64_za-ptrace_Set_VL_2128: pass
arm64_za-ptrace_Set_VL_2144: pass
arm64_za-ptrace_Set_VL_2160: pass
arm64_za-ptrace_Set_VL_2176: pass
arm64_za-ptrace_Set_VL_2192: pass
arm64_za-ptrace_Set_VL_2208: pass
arm64_za-ptrace_Set_VL_2224: pass
arm64_za-ptrace_Set_VL_224: pass
arm64_za-ptrace_Set_VL_2240: pass
arm64_za-ptrace_Set_VL_2256: pass
arm64_za-ptrace_Set_VL_2272: pass
arm64_za-ptrace_Set_VL_2288: pass
arm64_za-ptrace_Set_VL_2304: pass
arm64_za-ptrace_Set_VL_2320: pass
arm64_za-ptrace_Set_VL_2336: pass
arm64_za-ptrace_Set_VL_2352: pass
arm64_za-ptrace_Set_VL_2368: pass
arm64_za-ptrace_Set_VL_2384: pass
arm64_za-ptrace_Set_VL_240: pass
arm64_za-ptrace_Set_VL_2400: pass
arm64_za-ptrace_Set_VL_2416: pass
arm64_za-ptrace_Set_VL_2432: pass
arm64_za-ptrace_Set_VL_2448: pass
arm64_za-ptrace_Set_VL_2464: pass
arm64_za-ptrace_Set_VL_2480: pass
arm64_za-ptrace_Set_VL_2496: pass
arm64_za-ptrace_Set_VL_2512: pass
arm64_za-ptrace_Set_VL_2528: pass
arm64_za-ptrace_Set_VL_2544: pass
arm64_za-ptrace_Set_VL_256: pass
arm64_za-ptrace_Set_VL_2560: pass
arm64_za-ptrace_Set_VL_2576: pass
arm64_za-ptrace_Set_VL_2592: pass
arm64_za-ptrace_Set_VL_2608: pass
arm64_za-ptrace_Set_VL_2624: pass
arm64_za-ptrace_Set_VL_2640: pass
arm64_za-ptrace_Set_VL_2656: pass
arm64_za-ptrace_Set_VL_2672: pass
arm64_za-ptrace_Set_VL_2688: pass
arm64_za-ptrace_Set_VL_2704: pass
arm64_za-ptrace_Set_VL_272: pass
arm64_za-ptrace_Set_VL_2720: pass
arm64_za-ptrace_Set_VL_2736: pass
arm64_za-ptrace_Set_VL_2752: pass
arm64_za-ptrace_Set_VL_2768: pass
arm64_za-ptrace_Set_VL_2784: pass
arm64_za-ptrace_Set_VL_2800: pass
arm64_za-ptrace_Set_VL_2816: pass
arm64_za-ptrace_Set_VL_2832: pass
arm64_za-ptrace_Set_VL_2848: pass
arm64_za-ptrace_Set_VL_2864: pass
arm64_za-ptrace_Set_VL_288: pass
arm64_za-ptrace_Set_VL_2880: pass
arm64_za-ptrace_Set_VL_2896: pass
arm64_za-ptrace_Set_VL_2912: pass
arm64_za-ptrace_Set_VL_2928: pass
arm64_za-ptrace_Set_VL_2944: pass
arm64_za-ptrace_Set_VL_2960: pass
arm64_za-ptrace_Set_VL_2976: pass
arm64_za-ptrace_Set_VL_2992: pass
arm64_za-ptrace_Set_VL_3008: pass
arm64_za-ptrace_Set_VL_3024: pass
arm64_za-ptrace_Set_VL_304: pass
arm64_za-ptrace_Set_VL_3040: pass
arm64_za-ptrace_Set_VL_3056: pass
arm64_za-ptrace_Set_VL_3072: pass
arm64_za-ptrace_Set_VL_3088: pass
arm64_za-ptrace_Set_VL_3104: pass
arm64_za-ptrace_Set_VL_3120: pass
arm64_za-ptrace_Set_VL_3136: pass
arm64_za-ptrace_Set_VL_3152: pass
arm64_za-ptrace_Set_VL_3168: pass
arm64_za-ptrace_Set_VL_3184: pass
arm64_za-ptrace_Set_VL_32: pass
arm64_za-ptrace_Set_VL_320: pass
arm64_za-ptrace_Set_VL_3200: pass
arm64_za-ptrace_Set_VL_3216: pass
arm64_za-ptrace_Set_VL_3232: pass
arm64_za-ptrace_Set_VL_3248: pass
arm64_za-ptrace_Set_VL_3264: pass
arm64_za-ptrace_Set_VL_3280: pass
arm64_za-ptrace_Set_VL_3296: pass
arm64_za-ptrace_Set_VL_3312: pass
arm64_za-ptrace_Set_VL_3328: pass
arm64_za-ptrace_Set_VL_3344: pass
arm64_za-ptrace_Set_VL_336: pass
arm64_za-ptrace_Set_VL_3360: pass
arm64_za-ptrace_Set_VL_3376: pass
arm64_za-ptrace_Set_VL_3392: pass
arm64_za-ptrace_Set_VL_3408: pass
arm64_za-ptrace_Set_VL_3424: pass
arm64_za-ptrace_Set_VL_3440: pass
arm64_za-ptrace_Set_VL_3456: pass
arm64_za-ptrace_Set_VL_3472: pass
arm64_za-ptrace_Set_VL_3488: pass
arm64_za-ptrace_Set_VL_3504: pass
arm64_za-ptrace_Set_VL_352: pass
arm64_za-ptrace_Set_VL_3520: pass
arm64_za-ptrace_Set_VL_3536: pass
arm64_za-ptrace_Set_VL_3552: pass
arm64_za-ptrace_Set_VL_3568: pass
arm64_za-ptrace_Set_VL_3584: pass
arm64_za-ptrace_Set_VL_3600: pass
arm64_za-ptrace_Set_VL_3616: pass
arm64_za-ptrace_Set_VL_3632: pass
arm64_za-ptrace_Set_VL_3648: pass
arm64_za-ptrace_Set_VL_3664: pass
arm64_za-ptrace_Set_VL_368: pass
arm64_za-ptrace_Set_VL_3680: pass
arm64_za-ptrace_Set_VL_3696: pass
arm64_za-ptrace_Set_VL_3712: pass
arm64_za-ptrace_Set_VL_3728: pass
arm64_za-ptrace_Set_VL_3744: pass
arm64_za-ptrace_Set_VL_3760: pass
arm64_za-ptrace_Set_VL_3776: pass
arm64_za-ptrace_Set_VL_3792: pass
arm64_za-ptrace_Set_VL_3808: pass
arm64_za-ptrace_Set_VL_3824: pass
arm64_za-ptrace_Set_VL_384: pass
arm64_za-ptrace_Set_VL_3840: pass
arm64_za-ptrace_Set_VL_3856: pass
arm64_za-ptrace_Set_VL_3872: pass
arm64_za-ptrace_Set_VL_3888: pass
arm64_za-ptrace_Set_VL_3904: pass
arm64_za-ptrace_Set_VL_3920: pass
arm64_za-ptrace_Set_VL_3936: pass
arm64_za-ptrace_Set_VL_3952: pass
arm64_za-ptrace_Set_VL_3968: pass
arm64_za-ptrace_Set_VL_3984: pass
arm64_za-ptrace_Set_VL_400: pass
arm64_za-ptrace_Set_VL_4000: pass
arm64_za-ptrace_Set_VL_4016: pass
arm64_za-ptrace_Set_VL_4032: pass
arm64_za-ptrace_Set_VL_4048: pass
arm64_za-ptrace_Set_VL_4064: pass
arm64_za-ptrace_Set_VL_4080: pass
arm64_za-ptrace_Set_VL_4096: pass
arm64_za-ptrace_Set_VL_4112: pass
arm64_za-ptrace_Set_VL_4128: pass
arm64_za-ptrace_Set_VL_4144: pass
arm64_za-ptrace_Set_VL_416: pass
arm64_za-ptrace_Set_VL_4160: pass
arm64_za-ptrace_Set_VL_4176: pass
arm64_za-ptrace_Set_VL_4192: pass
arm64_za-ptrace_Set_VL_4208: pass
arm64_za-ptrace_Set_VL_4224: pass
arm64_za-ptrace_Set_VL_4240: pass
arm64_za-ptrace_Set_VL_4256: pass
arm64_za-ptrace_Set_VL_4272: pass
arm64_za-ptrace_Set_VL_4288: pass
arm64_za-ptrace_Set_VL_4304: pass
arm64_za-ptrace_Set_VL_432: pass
arm64_za-ptrace_Set_VL_4320: pass
arm64_za-ptrace_Set_VL_4336: pass
arm64_za-ptrace_Set_VL_4352: pass
arm64_za-ptrace_Set_VL_4368: pass
arm64_za-ptrace_Set_VL_4384: pass
arm64_za-ptrace_Set_VL_4400: pass
arm64_za-ptrace_Set_VL_4416: pass
arm64_za-ptrace_Set_VL_4432: pass
arm64_za-ptrace_Set_VL_4448: pass
arm64_za-ptrace_Set_VL_4464: pass
arm64_za-ptrace_Set_VL_448: pass
arm64_za-ptrace_Set_VL_4480: pass
arm64_za-ptrace_Set_VL_4496: pass
arm64_za-ptrace_Set_VL_4512: pass
arm64_za-ptrace_Set_VL_4528: pass
arm64_za-ptrace_Set_VL_4544: pass
arm64_za-ptrace_Set_VL_4560: pass
arm64_za-ptrace_Set_VL_4576: pass
arm64_za-ptrace_Set_VL_4592: pass
arm64_za-ptrace_Set_VL_4608: pass
arm64_za-ptrace_Set_VL_4624: pass
arm64_za-ptrace_Set_VL_464: pass
arm64_za-ptrace_Set_VL_4640: pass
arm64_za-ptrace_Set_VL_4656: pass
arm64_za-ptrace_Set_VL_4672: pass
arm64_za-ptrace_Set_VL_4688: pass
arm64_za-ptrace_Set_VL_4704: pass
arm64_za-ptrace_Set_VL_4720: pass
arm64_za-ptrace_Set_VL_4736: pass
arm64_za-ptrace_Set_VL_4752: pass
arm64_za-ptrace_Set_VL_4768: pass
arm64_za-ptrace_Set_VL_4784: pass
arm64_za-ptrace_Set_VL_48: pass
arm64_za-ptrace_Set_VL_480: pass
arm64_za-ptrace_Set_VL_4800: pass
arm64_za-ptrace_Set_VL_4816: pass
arm64_za-ptrace_Set_VL_4832: pass
arm64_za-ptrace_Set_VL_4848: pass
arm64_za-ptrace_Set_VL_4864: pass
arm64_za-ptrace_Set_VL_4880: pass
arm64_za-ptrace_Set_VL_4896: pass
arm64_za-ptrace_Set_VL_4912: pass
arm64_za-ptrace_Set_VL_4928: pass
arm64_za-ptrace_Set_VL_4944: pass
arm64_za-ptrace_Set_VL_496: pass
arm64_za-ptrace_Set_VL_4960: pass
arm64_za-ptrace_Set_VL_4976: pass
arm64_za-ptrace_Set_VL_4992: pass
arm64_za-ptrace_Set_VL_5008: pass
arm64_za-ptrace_Set_VL_5024: pass
arm64_za-ptrace_Set_VL_5040: pass
arm64_za-ptrace_Set_VL_5056: pass
arm64_za-ptrace_Set_VL_5072: pass
arm64_za-ptrace_Set_VL_5088: pass
arm64_za-ptrace_Set_VL_5104: pass
arm64_za-ptrace_Set_VL_512: pass
arm64_za-ptrace_Set_VL_5120: pass
arm64_za-ptrace_Set_VL_5136: pass
arm64_za-ptrace_Set_VL_5152: pass
arm64_za-ptrace_Set_VL_5168: pass
arm64_za-ptrace_Set_VL_5184: pass
arm64_za-ptrace_Set_VL_5200: pass
arm64_za-ptrace_Set_VL_5216: pass
arm64_za-ptrace_Set_VL_5232: pass
arm64_za-ptrace_Set_VL_5248: pass
arm64_za-ptrace_Set_VL_5264: pass
arm64_za-ptrace_Set_VL_528: pass
arm64_za-ptrace_Set_VL_5280: pass
arm64_za-ptrace_Set_VL_5296: pass
arm64_za-ptrace_Set_VL_5312: pass
arm64_za-ptrace_Set_VL_5328: pass
arm64_za-ptrace_Set_VL_5344: pass
arm64_za-ptrace_Set_VL_5360: pass
arm64_za-ptrace_Set_VL_5376: pass
arm64_za-ptrace_Set_VL_5392: pass
arm64_za-ptrace_Set_VL_5408: pass
arm64_za-ptrace_Set_VL_5424: pass
arm64_za-ptrace_Set_VL_544: pass
arm64_za-ptrace_Set_VL_5440: pass
arm64_za-ptrace_Set_VL_5456: pass
arm64_za-ptrace_Set_VL_5472: pass
arm64_za-ptrace_Set_VL_5488: pass
arm64_za-ptrace_Set_VL_5504: pass
arm64_za-ptrace_Set_VL_5520: pass
arm64_za-ptrace_Set_VL_5536: pass
arm64_za-ptrace_Set_VL_5552: pass
arm64_za-ptrace_Set_VL_5568: pass
arm64_za-ptrace_Set_VL_5584: pass
arm64_za-ptrace_Set_VL_560: pass
arm64_za-ptrace_Set_VL_5600: pass
arm64_za-ptrace_Set_VL_5616: pass
arm64_za-ptrace_Set_VL_5632: pass
arm64_za-ptrace_Set_VL_5648: pass
arm64_za-ptrace_Set_VL_5664: pass
arm64_za-ptrace_Set_VL_5680: pass
arm64_za-ptrace_Set_VL_5696: pass
arm64_za-ptrace_Set_VL_5712: pass
arm64_za-ptrace_Set_VL_5728: pass
arm64_za-ptrace_Set_VL_5744: pass
arm64_za-ptrace_Set_VL_576: pass
arm64_za-ptrace_Set_VL_5760: pass
arm64_za-ptrace_Set_VL_5776: pass
arm64_za-ptrace_Set_VL_5792: pass
arm64_za-ptrace_Set_VL_5808: pass
arm64_za-ptrace_Set_VL_5824: pass
arm64_za-ptrace_Set_VL_5840: pass
arm64_za-ptrace_Set_VL_5856: pass
arm64_za-ptrace_Set_VL_5872: pass
arm64_za-ptrace_Set_VL_5888: pass
arm64_za-ptrace_Set_VL_5904: pass
arm64_za-ptrace_Set_VL_592: pass
arm64_za-ptrace_Set_VL_5920: pass
arm64_za-ptrace_Set_VL_5936: pass
arm64_za-ptrace_Set_VL_5952: pass
arm64_za-ptrace_Set_VL_5968: pass
arm64_za-ptrace_Set_VL_5984: pass
arm64_za-ptrace_Set_VL_6000: pass
arm64_za-ptrace_Set_VL_6016: pass
arm64_za-ptrace_Set_VL_6032: pass
arm64_za-ptrace_Set_VL_6048: pass
arm64_za-ptrace_Set_VL_6064: pass
arm64_za-ptrace_Set_VL_608: pass
arm64_za-ptrace_Set_VL_6080: pass
arm64_za-ptrace_Set_VL_6096: pass
arm64_za-ptrace_Set_VL_6112: pass
arm64_za-ptrace_Set_VL_6128: pass
arm64_za-ptrace_Set_VL_6144: pass
arm64_za-ptrace_Set_VL_6160: pass
arm64_za-ptrace_Set_VL_6176: pass
arm64_za-ptrace_Set_VL_6192: pass
arm64_za-ptrace_Set_VL_6208: pass
arm64_za-ptrace_Set_VL_6224: pass
arm64_za-ptrace_Set_VL_624: pass
arm64_za-ptrace_Set_VL_6240: pass
arm64_za-ptrace_Set_VL_6256: pass
arm64_za-ptrace_Set_VL_6272: pass
arm64_za-ptrace_Set_VL_6288: pass
arm64_za-ptrace_Set_VL_6304: pass
arm64_za-ptrace_Set_VL_6320: pass
arm64_za-ptrace_Set_VL_6336: pass
arm64_za-ptrace_Set_VL_6352: pass
arm64_za-ptrace_Set_VL_6368: pass
arm64_za-ptrace_Set_VL_6384: pass
arm64_za-ptrace_Set_VL_64: pass
arm64_za-ptrace_Set_VL_640: pass
arm64_za-ptrace_Set_VL_6400: pass
arm64_za-ptrace_Set_VL_6416: pass
arm64_za-ptrace_Set_VL_6432: pass
arm64_za-ptrace_Set_VL_6448: pass
arm64_za-ptrace_Set_VL_6464: pass
arm64_za-ptrace_Set_VL_6480: pass
arm64_za-ptrace_Set_VL_6496: pass
arm64_za-ptrace_Set_VL_6512: pass
arm64_za-ptrace_Set_VL_6528: pass
arm64_za-ptrace_Set_VL_6544: pass
arm64_za-ptrace_Set_VL_656: pass
arm64_za-ptrace_Set_VL_6560: pass
arm64_za-ptrace_Set_VL_6576: pass
arm64_za-ptrace_Set_VL_6592: pass
arm64_za-ptrace_Set_VL_6608: pass
arm64_za-ptrace_Set_VL_6624: pass
arm64_za-ptrace_Set_VL_6640: pass
arm64_za-ptrace_Set_VL_6656: pass
arm64_za-ptrace_Set_VL_6672: pass
arm64_za-ptrace_Set_VL_6688: pass
arm64_za-ptrace_Set_VL_6704: pass
arm64_za-ptrace_Set_VL_672: pass
arm64_za-ptrace_Set_VL_6720: pass
arm64_za-ptrace_Set_VL_6736: pass
arm64_za-ptrace_Set_VL_6752: pass
arm64_za-ptrace_Set_VL_6768: pass
arm64_za-ptrace_Set_VL_6784: pass
arm64_za-ptrace_Set_VL_6800: pass
arm64_za-ptrace_Set_VL_6816: pass
arm64_za-ptrace_Set_VL_6832: pass
arm64_za-ptrace_Set_VL_6848: pass
arm64_za-ptrace_Set_VL_6864: pass
arm64_za-ptrace_Set_VL_688: pass
arm64_za-ptrace_Set_VL_6880: pass
arm64_za-ptrace_Set_VL_6896: pass
arm64_za-ptrace_Set_VL_6912: pass
arm64_za-ptrace_Set_VL_6928: pass
arm64_za-ptrace_Set_VL_6944: pass
arm64_za-ptrace_Set_VL_6960: pass
arm64_za-ptrace_Set_VL_6976: pass
arm64_za-ptrace_Set_VL_6992: pass
arm64_za-ptrace_Set_VL_7008: pass
arm64_za-ptrace_Set_VL_7024: pass
arm64_za-ptrace_Set_VL_704: pass
arm64_za-ptrace_Set_VL_7040: pass
arm64_za-ptrace_Set_VL_7056: pass
arm64_za-ptrace_Set_VL_7072: pass
arm64_za-ptrace_Set_VL_7088: pass
arm64_za-ptrace_Set_VL_7104: pass
arm64_za-ptrace_Set_VL_7120: pass
arm64_za-ptrace_Set_VL_7136: pass
arm64_za-ptrace_Set_VL_7152: pass
arm64_za-ptrace_Set_VL_7168: pass
arm64_za-ptrace_Set_VL_7184: pass
arm64_za-ptrace_Set_VL_720: pass
arm64_za-ptrace_Set_VL_7200: pass
arm64_za-ptrace_Set_VL_7216: pass
arm64_za-ptrace_Set_VL_7232: pass
arm64_za-ptrace_Set_VL_7248: pass
arm64_za-ptrace_Set_VL_7264: pass
arm64_za-ptrace_Set_VL_7280: pass
arm64_za-ptrace_Set_VL_7296: pass
arm64_za-ptrace_Set_VL_7312: pass
arm64_za-ptrace_Set_VL_7328: pass
arm64_za-ptrace_Set_VL_7344: pass
arm64_za-ptrace_Set_VL_736: pass
arm64_za-ptrace_Set_VL_7360: pass
arm64_za-ptrace_Set_VL_7376: pass
arm64_za-ptrace_Set_VL_7392: pass
arm64_za-ptrace_Set_VL_7408: pass
arm64_za-ptrace_Set_VL_7424: pass
arm64_za-ptrace_Set_VL_7440: pass
arm64_za-ptrace_Set_VL_7456: pass
arm64_za-ptrace_Set_VL_7472: pass
arm64_za-ptrace_Set_VL_7488: pass
arm64_za-ptrace_Set_VL_7504: pass
arm64_za-ptrace_Set_VL_752: pass
arm64_za-ptrace_Set_VL_7520: pass
arm64_za-ptrace_Set_VL_7536: pass
arm64_za-ptrace_Set_VL_7552: pass
arm64_za-ptrace_Set_VL_7568: pass
arm64_za-ptrace_Set_VL_7584: pass
arm64_za-ptrace_Set_VL_7600: pass
arm64_za-ptrace_Set_VL_7616: pass
arm64_za-ptrace_Set_VL_7632: pass
arm64_za-ptrace_Set_VL_7648: pass
arm64_za-ptrace_Set_VL_7664: pass
arm64_za-ptrace_Set_VL_768: pass
arm64_za-ptrace_Set_VL_7680: pass
arm64_za-ptrace_Set_VL_7696: pass
arm64_za-ptrace_Set_VL_7712: pass
arm64_za-ptrace_Set_VL_7728: pass
arm64_za-ptrace_Set_VL_7744: pass
arm64_za-ptrace_Set_VL_7760: pass
arm64_za-ptrace_Set_VL_7776: pass
arm64_za-ptrace_Set_VL_7792: pass
arm64_za-ptrace_Set_VL_7808: pass
arm64_za-ptrace_Set_VL_7824: pass
arm64_za-ptrace_Set_VL_784: pass
arm64_za-ptrace_Set_VL_7840: pass
arm64_za-ptrace_Set_VL_7856: pass
arm64_za-ptrace_Set_VL_7872: pass
arm64_za-ptrace_Set_VL_7888: pass
arm64_za-ptrace_Set_VL_7904: pass
arm64_za-ptrace_Set_VL_7920: pass
arm64_za-ptrace_Set_VL_7936: pass
arm64_za-ptrace_Set_VL_7952: pass
arm64_za-ptrace_Set_VL_7968: pass
arm64_za-ptrace_Set_VL_7984: pass
arm64_za-ptrace_Set_VL_80: pass
arm64_za-ptrace_Set_VL_800: pass
arm64_za-ptrace_Set_VL_8000: pass
arm64_za-ptrace_Set_VL_8016: pass
arm64_za-ptrace_Set_VL_8032: pass
arm64_za-ptrace_Set_VL_8048: pass
arm64_za-ptrace_Set_VL_8064: pass
arm64_za-ptrace_Set_VL_8080: pass
arm64_za-ptrace_Set_VL_8096: pass
arm64_za-ptrace_Set_VL_8112: pass
arm64_za-ptrace_Set_VL_8128: pass
arm64_za-ptrace_Set_VL_8144: pass
arm64_za-ptrace_Set_VL_816: pass
arm64_za-ptrace_Set_VL_8160: pass
arm64_za-ptrace_Set_VL_8176: pass
arm64_za-ptrace_Set_VL_8192: pass
arm64_za-ptrace_Set_VL_832: pass
arm64_za-ptrace_Set_VL_848: pass
arm64_za-ptrace_Set_VL_864: pass
arm64_za-ptrace_Set_VL_880: pass
arm64_za-ptrace_Set_VL_896: pass
arm64_za-ptrace_Set_VL_912: pass
arm64_za-ptrace_Set_VL_928: pass
arm64_za-ptrace_Set_VL_944: pass
arm64_za-ptrace_Set_VL_96: pass
arm64_za-ptrace_Set_VL_960: pass
arm64_za-ptrace_Set_VL_976: pass
arm64_za-ptrace_Set_VL_992: pass
arm64_za_no_regs: pass
arm64_za_regs: pass
34614 17:05:57.397061 end: 3.1 lava-test-shell (duration 00:06:30) [common]
34615 17:05:57.397183 end: 3 lava-test-retry (duration 00:06:30) [common]
34616 17:05:57.397281 start: 4 finalize (timeout 00:02:15) [common]
34617 17:05:57.397377 start: 4.1 power-off (timeout 00:00:30) [common]
34618 17:05:57.397464 end: 4.1 power-off (duration 00:00:00) [common]
34619 17:05:57.397567 start: 4.2 read-feedback (timeout 00:02:15) [common]
34620 17:05:57.397787 Listened to connection for namespace 'common' for up to 1s
34621 17:05:57.398084 Listened to connection for namespace 'common' for up to 1s
34622 17:05:58.401754 Finalising connection for namespace 'common'
34624 17:05:58.502699 / # poweroff
34625 17:05:58.503432 Already disconnected
34626 17:05:58.503680 poweroff
34627 17:05:58.905749 end: 4.2 read-feedback (duration 00:00:02) [common]
34628 17:05:58.905979 Already disconnected
34629 17:05:58.906108 end: 4 finalize (duration 00:00:02) [common]
34630 17:05:58.906229 Cleaning after the job
34631 17:05:58.906364 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/556569/deployimages-3mxgxodd/kernel
34632 17:05:58.912495 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/556569/deployimages-3mxgxodd/ramdisk
34633 17:05:58.925586 Stopping the qemu container lava-docker-qemu-556569-2.1.1-6gztugztbn
34634 17:05:59.825908 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/556569
34635 17:05:59.900127 Job finished correctly