Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 31
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 23
1 16:43:28.624784 lava-dispatcher, installed at version: 2023.03
2 16:43:28.624985 start: 0 validate
3 16:43:28.625104 Start time: 2023-06-03 16:43:28.625097+00:00 (UTC)
4 16:43:28.625220 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:43:28.625342 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 16:43:28.915614 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:43:28.916420 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:43:29.210500 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:43:29.211294 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:43:48.159016 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:43:48.159745 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:43:48.892193 validate duration: 20.27
14 16:43:48.892449 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:43:48.892543 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:43:48.892629 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:43:48.892745 Not decompressing ramdisk as can be used compressed.
18 16:43:48.892830 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 16:43:48.892895 saving as /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/ramdisk/rootfs.cpio.gz
20 16:43:48.892958 total size: 8186575 (7MB)
21 16:43:51.815965 progress 0% (0MB)
22 16:43:51.820728 progress 5% (0MB)
23 16:43:51.822767 progress 10% (0MB)
24 16:43:51.824900 progress 15% (1MB)
25 16:43:51.826881 progress 20% (1MB)
26 16:43:51.829006 progress 25% (1MB)
27 16:43:51.831016 progress 30% (2MB)
28 16:43:51.833119 progress 35% (2MB)
29 16:43:51.835144 progress 40% (3MB)
30 16:43:51.837244 progress 45% (3MB)
31 16:43:51.839312 progress 50% (3MB)
32 16:43:51.841446 progress 55% (4MB)
33 16:43:51.843436 progress 60% (4MB)
34 16:43:51.845668 progress 65% (5MB)
35 16:43:51.847669 progress 70% (5MB)
36 16:43:51.849767 progress 75% (5MB)
37 16:43:51.851800 progress 80% (6MB)
38 16:43:51.854022 progress 85% (6MB)
39 16:43:51.856072 progress 90% (7MB)
40 16:43:51.858212 progress 95% (7MB)
41 16:43:51.860250 progress 100% (7MB)
42 16:43:51.860460 7MB downloaded in 2.97s (2.63MB/s)
43 16:43:51.860605 end: 1.1.1 http-download (duration 00:00:03) [common]
45 16:43:51.860878 end: 1.1 download-retry (duration 00:00:03) [common]
46 16:43:51.860966 start: 1.2 download-retry (timeout 00:09:57) [common]
47 16:43:51.861050 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 16:43:51.861190 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:43:51.861260 saving as /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/kernel/Image
50 16:43:51.861320 total size: 45746688 (43MB)
51 16:43:51.861380 No compression specified
52 16:43:52.146728 progress 0% (0MB)
53 16:43:52.194980 progress 5% (2MB)
54 16:43:52.212431 progress 10% (4MB)
55 16:43:52.224900 progress 15% (6MB)
56 16:43:52.236000 progress 20% (8MB)
57 16:43:52.247281 progress 25% (10MB)
58 16:43:52.258398 progress 30% (13MB)
59 16:43:52.269702 progress 35% (15MB)
60 16:43:52.281128 progress 40% (17MB)
61 16:43:52.292501 progress 45% (19MB)
62 16:43:52.303845 progress 50% (21MB)
63 16:43:52.314998 progress 55% (24MB)
64 16:43:52.326083 progress 60% (26MB)
65 16:43:52.337158 progress 65% (28MB)
66 16:43:52.348461 progress 70% (30MB)
67 16:43:52.359729 progress 75% (32MB)
68 16:43:52.370812 progress 80% (34MB)
69 16:43:52.382049 progress 85% (37MB)
70 16:43:52.393234 progress 90% (39MB)
71 16:43:52.404433 progress 95% (41MB)
72 16:43:52.415624 progress 100% (43MB)
73 16:43:52.415742 43MB downloaded in 0.55s (78.69MB/s)
74 16:43:52.415887 end: 1.2.1 http-download (duration 00:00:01) [common]
76 16:43:52.416117 end: 1.2 download-retry (duration 00:00:01) [common]
77 16:43:52.416202 start: 1.3 download-retry (timeout 00:09:56) [common]
78 16:43:52.416291 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 16:43:52.416424 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:43:52.416493 saving as /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/dtb/mt8192-asurada-spherion-r0.dtb
81 16:43:52.416555 total size: 46924 (0MB)
82 16:43:52.416615 No compression specified
83 16:43:52.417716 progress 69% (0MB)
84 16:43:52.417979 progress 100% (0MB)
85 16:43:52.418125 0MB downloaded in 0.00s (28.53MB/s)
86 16:43:52.418242 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:43:52.418470 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:43:52.418555 start: 1.4 download-retry (timeout 00:09:56) [common]
90 16:43:52.418637 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 16:43:52.418742 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:43:52.418811 saving as /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/modules/modules.tar
93 16:43:52.418872 total size: 8545664 (8MB)
94 16:43:52.418931 Using unxz to decompress xz
95 16:43:52.422386 progress 0% (0MB)
96 16:43:52.443035 progress 5% (0MB)
97 16:43:52.467182 progress 10% (0MB)
98 16:43:52.492730 progress 15% (1MB)
99 16:43:52.516892 progress 20% (1MB)
100 16:43:52.541567 progress 25% (2MB)
101 16:43:52.565595 progress 30% (2MB)
102 16:43:52.590141 progress 35% (2MB)
103 16:43:52.614423 progress 40% (3MB)
104 16:43:52.638657 progress 45% (3MB)
105 16:43:52.661690 progress 50% (4MB)
106 16:43:52.683742 progress 55% (4MB)
107 16:43:52.707949 progress 60% (4MB)
108 16:43:52.732593 progress 65% (5MB)
109 16:43:52.757046 progress 70% (5MB)
110 16:43:52.782872 progress 75% (6MB)
111 16:43:52.811363 progress 80% (6MB)
112 16:43:52.833315 progress 85% (6MB)
113 16:43:52.857721 progress 90% (7MB)
114 16:43:52.880560 progress 95% (7MB)
115 16:43:52.903537 progress 100% (8MB)
116 16:43:52.909351 8MB downloaded in 0.49s (16.62MB/s)
117 16:43:52.909623 end: 1.4.1 http-download (duration 00:00:00) [common]
119 16:43:52.909881 end: 1.4 download-retry (duration 00:00:00) [common]
120 16:43:52.909974 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 16:43:52.910071 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 16:43:52.910153 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:43:52.910244 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 16:43:52.910509 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s
125 16:43:52.910639 makedir: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin
126 16:43:52.910739 makedir: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/tests
127 16:43:52.910835 makedir: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/results
128 16:43:52.910949 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-add-keys
129 16:43:52.911091 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-add-sources
130 16:43:52.911221 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-background-process-start
131 16:43:52.911349 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-background-process-stop
132 16:43:52.911470 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-common-functions
133 16:43:52.911588 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-echo-ipv4
134 16:43:52.911711 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-install-packages
135 16:43:52.911832 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-installed-packages
136 16:43:52.911952 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-os-build
137 16:43:52.912071 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-probe-channel
138 16:43:52.912195 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-probe-ip
139 16:43:52.912314 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-target-ip
140 16:43:52.912436 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-target-mac
141 16:43:52.912554 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-target-storage
142 16:43:52.912678 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-case
143 16:43:52.912799 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-event
144 16:43:52.912917 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-feedback
145 16:43:52.913037 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-raise
146 16:43:52.913162 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-reference
147 16:43:52.913281 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-runner
148 16:43:52.913401 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-set
149 16:43:52.913522 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-test-shell
150 16:43:52.913645 Updating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-install-packages (oe)
151 16:43:52.913795 Updating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/bin/lava-installed-packages (oe)
152 16:43:52.913913 Creating /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/environment
153 16:43:52.914010 LAVA metadata
154 16:43:52.914085 - LAVA_JOB_ID=10576340
155 16:43:52.914151 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:43:52.914254 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 16:43:52.914322 skipped lava-vland-overlay
158 16:43:52.914402 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:43:52.914483 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 16:43:52.914548 skipped lava-multinode-overlay
161 16:43:52.914624 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:43:52.914706 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 16:43:52.914782 Loading test definitions
164 16:43:52.914880 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 16:43:52.914955 Using /lava-10576340 at stage 0
166 16:43:52.915251 uuid=10576340_1.5.2.3.1 testdef=None
167 16:43:52.915340 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:43:52.915428 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 16:43:52.915943 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:43:52.916167 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 16:43:52.916796 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:43:52.917028 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 16:43:52.917630 runner path: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/0/tests/0_dmesg test_uuid 10576340_1.5.2.3.1
176 16:43:52.917783 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:43:52.918010 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:56) [common]
179 16:43:52.918082 Using /lava-10576340 at stage 1
180 16:43:52.918375 uuid=10576340_1.5.2.3.5 testdef=None
181 16:43:52.918465 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 16:43:52.918549 start: 1.5.2.3.6 test-overlay (timeout 00:09:56) [common]
183 16:43:52.919016 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 16:43:52.919230 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:56) [common]
186 16:43:52.920314 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 16:43:52.920543 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:56) [common]
189 16:43:52.921149 runner path: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/1/tests/1_bootrr test_uuid 10576340_1.5.2.3.5
190 16:43:52.921296 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 16:43:52.921503 Creating lava-test-runner.conf files
193 16:43:52.921587 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/0 for stage 0
194 16:43:52.921679 - 0_dmesg
195 16:43:52.921760 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576340/lava-overlay-zsc1h51s/lava-10576340/1 for stage 1
196 16:43:52.921849 - 1_bootrr
197 16:43:52.921941 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 16:43:52.922030 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
199 16:43:52.929670 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 16:43:52.929775 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
201 16:43:52.929861 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 16:43:52.929947 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 16:43:52.930034 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
204 16:43:53.157780 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 16:43:53.158149 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
206 16:43:53.158255 extracting modules file /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576340/extract-overlay-ramdisk-49_mvomr/ramdisk
207 16:43:53.353127 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 16:43:53.353295 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
209 16:43:53.353385 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576340/compress-overlay-si3rlufe/overlay-1.5.2.4.tar.gz to ramdisk
210 16:43:53.353458 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576340/compress-overlay-si3rlufe/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576340/extract-overlay-ramdisk-49_mvomr/ramdisk
211 16:43:53.361531 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 16:43:53.361640 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
213 16:43:53.361731 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 16:43:53.361821 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
215 16:43:53.361900 Building ramdisk /var/lib/lava/dispatcher/tmp/10576340/extract-overlay-ramdisk-49_mvomr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576340/extract-overlay-ramdisk-49_mvomr/ramdisk
216 16:43:53.759953 >> 143711 blocks
217 16:43:56.007699 rename /var/lib/lava/dispatcher/tmp/10576340/extract-overlay-ramdisk-49_mvomr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/ramdisk/ramdisk.cpio.gz
218 16:43:56.008113 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 16:43:56.008240 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
220 16:43:56.008334 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
221 16:43:56.008435 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/kernel/Image'
222 16:44:07.136134 Returned 0 in 11 seconds
223 16:44:07.237174 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/kernel/image.itb
224 16:44:07.700867 output: FIT description: Kernel Image image with one or more FDT blobs
225 16:44:07.701213 output: Created: Sat Jun 3 17:44:07 2023
226 16:44:07.701290 output: Image 0 (kernel-1)
227 16:44:07.701360 output: Description:
228 16:44:07.701426 output: Created: Sat Jun 3 17:44:07 2023
229 16:44:07.701490 output: Type: Kernel Image
230 16:44:07.701551 output: Compression: lzma compressed
231 16:44:07.701612 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
232 16:44:07.701670 output: Architecture: AArch64
233 16:44:07.701729 output: OS: Linux
234 16:44:07.701784 output: Load Address: 0x00000000
235 16:44:07.701839 output: Entry Point: 0x00000000
236 16:44:07.701896 output: Hash algo: crc32
237 16:44:07.701951 output: Hash value: b48eba69
238 16:44:07.702005 output: Image 1 (fdt-1)
239 16:44:07.702058 output: Description: mt8192-asurada-spherion-r0
240 16:44:07.702112 output: Created: Sat Jun 3 17:44:07 2023
241 16:44:07.702166 output: Type: Flat Device Tree
242 16:44:07.702219 output: Compression: uncompressed
243 16:44:07.702272 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 16:44:07.702325 output: Architecture: AArch64
245 16:44:07.702410 output: Hash algo: crc32
246 16:44:07.702491 output: Hash value: 1df858fa
247 16:44:07.702546 output: Image 2 (ramdisk-1)
248 16:44:07.702599 output: Description: unavailable
249 16:44:07.702652 output: Created: Sat Jun 3 17:44:07 2023
250 16:44:07.702706 output: Type: RAMDisk Image
251 16:44:07.702759 output: Compression: Unknown Compression
252 16:44:07.702812 output: Data Size: 21231557 Bytes = 20733.94 KiB = 20.25 MiB
253 16:44:07.702865 output: Architecture: AArch64
254 16:44:07.702918 output: OS: Linux
255 16:44:07.703001 output: Load Address: unavailable
256 16:44:07.703119 output: Entry Point: unavailable
257 16:44:07.703187 output: Hash algo: crc32
258 16:44:07.703241 output: Hash value: 0ff3745d
259 16:44:07.703294 output: Default Configuration: 'conf-1'
260 16:44:07.703348 output: Configuration 0 (conf-1)
261 16:44:07.703401 output: Description: mt8192-asurada-spherion-r0
262 16:44:07.703454 output: Kernel: kernel-1
263 16:44:07.703508 output: Init Ramdisk: ramdisk-1
264 16:44:07.703561 output: FDT: fdt-1
265 16:44:07.703613 output: Loadables: kernel-1
266 16:44:07.703666 output:
267 16:44:07.703854 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 16:44:07.703948 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 16:44:07.704051 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
270 16:44:07.704147 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
271 16:44:07.704227 No LXC device requested
272 16:44:07.704304 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 16:44:07.704389 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
274 16:44:07.704466 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 16:44:07.704534 Checking files for TFTP limit of 4294967296 bytes.
276 16:44:07.705107 end: 1 tftp-deploy (duration 00:00:19) [common]
277 16:44:07.705220 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 16:44:07.705307 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 16:44:07.705427 substitutions:
280 16:44:07.705493 - {DTB}: 10576340/tftp-deploy-enr8th00/dtb/mt8192-asurada-spherion-r0.dtb
281 16:44:07.705557 - {INITRD}: 10576340/tftp-deploy-enr8th00/ramdisk/ramdisk.cpio.gz
282 16:44:07.705616 - {KERNEL}: 10576340/tftp-deploy-enr8th00/kernel/Image
283 16:44:07.705698 - {LAVA_MAC}: None
284 16:44:07.705785 - {PRESEED_CONFIG}: None
285 16:44:07.705853 - {PRESEED_LOCAL}: None
286 16:44:07.705908 - {RAMDISK}: 10576340/tftp-deploy-enr8th00/ramdisk/ramdisk.cpio.gz
287 16:44:07.705962 - {ROOT_PART}: None
288 16:44:07.706017 - {ROOT}: None
289 16:44:07.706071 - {SERVER_IP}: 192.168.201.1
290 16:44:07.706125 - {TEE}: None
291 16:44:07.706179 Parsed boot commands:
292 16:44:07.706232 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 16:44:07.706482 Parsed boot commands: tftpboot 192.168.201.1 10576340/tftp-deploy-enr8th00/kernel/image.itb 10576340/tftp-deploy-enr8th00/kernel/cmdline
294 16:44:07.706592 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 16:44:07.706682 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 16:44:07.706783 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 16:44:07.706871 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 16:44:07.706957 Not connected, no need to disconnect.
299 16:44:07.707048 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 16:44:07.707130 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 16:44:07.707199 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
302 16:44:07.710956 Setting prompt string to ['lava-test: # ']
303 16:44:07.711529 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 16:44:07.711630 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 16:44:07.711723 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 16:44:07.711811 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 16:44:07.711995 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
308 16:44:12.859512 >> Command sent successfully.
309 16:44:12.865620 Returned 0 in 5 seconds
310 16:44:12.966423 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 16:44:12.967928 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 16:44:12.968508 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 16:44:12.969020 Setting prompt string to 'Starting depthcharge on Spherion...'
315 16:44:12.969418 Changing prompt to 'Starting depthcharge on Spherion...'
316 16:44:12.969800 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 16:44:12.971126 [Enter `^Ec?' for help]
318 16:44:13.137714
319 16:44:13.138335
320 16:44:13.138774 F0: 102B 0000
321 16:44:13.139189
322 16:44:13.139528 F3: 1001 0000 [0200]
323 16:44:13.139863
324 16:44:13.141549 F3: 1001 0000
325 16:44:13.142019
326 16:44:13.142427 F7: 102D 0000
327 16:44:13.142787
328 16:44:13.143183 F1: 0000 0000
329 16:44:13.143521
330 16:44:13.144558 V0: 0000 0000 [0001]
331 16:44:13.145176
332 16:44:13.145670 00: 0007 8000
333 16:44:13.146056
334 16:44:13.148517 01: 0000 0000
335 16:44:13.149139
336 16:44:13.149526 BP: 0C00 0209 [0000]
337 16:44:13.149877
338 16:44:13.150213 G0: 1182 0000
339 16:44:13.152253
340 16:44:13.152818 EC: 0000 0021 [4000]
341 16:44:13.153260
342 16:44:13.155900 S7: 0000 0000 [0000]
343 16:44:13.156632
344 16:44:13.157045 CC: 0000 0000 [0001]
345 16:44:13.157463
346 16:44:13.159777 T0: 0000 0040 [010F]
347 16:44:13.160366
348 16:44:13.160742 Jump to BL
349 16:44:13.161092
350 16:44:13.184384
351 16:44:13.184949
352 16:44:13.185323
353 16:44:13.191422 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 16:44:13.195414 ARM64: Exception handlers installed.
355 16:44:13.198717 ARM64: Testing exception
356 16:44:13.202644 ARM64: Done test exception
357 16:44:13.211613 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 16:44:13.216705 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 16:44:13.227523 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 16:44:13.237103 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 16:44:13.243388 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 16:44:13.250275 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 16:44:13.260946 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 16:44:13.268120 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 16:44:13.287269 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 16:44:13.290487 WDT: Last reset was cold boot
367 16:44:13.293468 SPI1(PAD0) initialized at 2873684 Hz
368 16:44:13.296975 SPI5(PAD0) initialized at 992727 Hz
369 16:44:13.300223 VBOOT: Loading verstage.
370 16:44:13.307228 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 16:44:13.310622 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 16:44:13.313180 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 16:44:13.316646 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 16:44:13.324517 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 16:44:13.330677 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 16:44:13.341833 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 16:44:13.342434
378 16:44:13.342813
379 16:44:13.351819 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 16:44:13.355078 ARM64: Exception handlers installed.
381 16:44:13.358256 ARM64: Testing exception
382 16:44:13.358857 ARM64: Done test exception
383 16:44:13.365124 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 16:44:13.368109 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 16:44:13.382799 Probing TPM: . done!
386 16:44:13.383378 TPM ready after 0 ms
387 16:44:13.390010 Connected to device vid:did:rid of 1ae0:0028:00
388 16:44:13.396741 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
389 16:44:13.454275 Initialized TPM device CR50 revision 0
390 16:44:13.465820 tlcl_send_startup: Startup return code is 0
391 16:44:13.466298 TPM: setup succeeded
392 16:44:13.477428 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 16:44:13.486138 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 16:44:13.496606 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 16:44:13.505326 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 16:44:13.508191 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 16:44:13.518004 in-header: 03 07 00 00 08 00 00 00
398 16:44:13.520907 in-data: aa e4 47 04 13 02 00 00
399 16:44:13.523938 Chrome EC: UHEPI supported
400 16:44:13.531024 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 16:44:13.534170 in-header: 03 ad 00 00 08 00 00 00
402 16:44:13.537925 in-data: 00 20 20 08 00 00 00 00
403 16:44:13.538439 Phase 1
404 16:44:13.541994 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 16:44:13.549124 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 16:44:13.552879 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 16:44:13.556729 Recovery requested (1009000e)
408 16:44:13.566814 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 16:44:13.573374 tlcl_extend: response is 0
410 16:44:13.584670 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 16:44:13.588682 tlcl_extend: response is 0
412 16:44:13.595254 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 16:44:13.615570 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 16:44:13.622689 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 16:44:13.623269
416 16:44:13.623652
417 16:44:13.632189 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 16:44:13.635292 ARM64: Exception handlers installed.
419 16:44:13.635773 ARM64: Testing exception
420 16:44:13.638870 ARM64: Done test exception
421 16:44:13.660944 pmic_efuse_setting: Set efuses in 11 msecs
422 16:44:13.663598 pmwrap_interface_init: Select PMIF_VLD_RDY
423 16:44:13.670656 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 16:44:13.674076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 16:44:13.680436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 16:44:13.684065 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 16:44:13.687233 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 16:44:13.694514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 16:44:13.698190 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 16:44:13.702073 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 16:44:13.709697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 16:44:13.712697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 16:44:13.716332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 16:44:13.720396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 16:44:13.726823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 16:44:13.733512 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 16:44:13.736813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 16:44:13.744158 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 16:44:13.751310 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 16:44:13.754732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 16:44:13.762201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 16:44:13.766244 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 16:44:13.772949 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 16:44:13.776361 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 16:44:13.782679 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 16:44:13.789554 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 16:44:13.792944 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 16:44:13.799457 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 16:44:13.806182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 16:44:13.809545 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 16:44:13.812647 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 16:44:13.819306 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 16:44:13.823292 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 16:44:13.829222 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 16:44:13.832826 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 16:44:13.839487 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 16:44:13.842787 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 16:44:13.849547 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 16:44:13.856135 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 16:44:13.859108 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 16:44:13.862868 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 16:44:13.869638 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 16:44:13.872691 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 16:44:13.876261 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 16:44:13.882789 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 16:44:13.886573 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 16:44:13.890239 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 16:44:13.892896 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 16:44:13.899607 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 16:44:13.902846 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 16:44:13.906300 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 16:44:13.912833 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 16:44:13.916239 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 16:44:13.923307 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 16:44:13.932846 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 16:44:13.936666 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 16:44:13.946300 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 16:44:13.952850 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 16:44:13.956189 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 16:44:13.962400 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 16:44:13.965745 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 16:44:13.973105 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0xa
483 16:44:13.979941 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 16:44:13.982961 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 16:44:13.986527 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 16:44:13.998448 [RTC]rtc_get_frequency_meter,154: input=15, output=772
487 16:44:14.006879 [RTC]rtc_get_frequency_meter,154: input=23, output=957
488 16:44:14.016764 [RTC]rtc_get_frequency_meter,154: input=19, output=865
489 16:44:14.026091 [RTC]rtc_get_frequency_meter,154: input=17, output=818
490 16:44:14.035241 [RTC]rtc_get_frequency_meter,154: input=16, output=795
491 16:44:14.038948 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
492 16:44:14.045890 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 16:44:14.048996 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
494 16:44:14.052150 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 16:44:14.055276 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
496 16:44:14.059731 ADC[4]: Raw value=902876 ID=7
497 16:44:14.062548 ADC[3]: Raw value=213179 ID=1
498 16:44:14.065693 RAM Code: 0x71
499 16:44:14.068777 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 16:44:14.072185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 16:44:14.082311 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 16:44:14.089264 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 16:44:14.092958 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 16:44:14.095479 in-header: 03 07 00 00 08 00 00 00
505 16:44:14.098949 in-data: aa e4 47 04 13 02 00 00
506 16:44:14.103011 Chrome EC: UHEPI supported
507 16:44:14.109637 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 16:44:14.116442 in-header: 03 ed 00 00 08 00 00 00
509 16:44:14.120048 in-data: 80 20 60 08 00 00 00 00
510 16:44:14.123757 MRC: failed to locate region type 0.
511 16:44:14.130688 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 16:44:14.131162 DRAM-K: Running full calibration
513 16:44:14.138667 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 16:44:14.141989 header.status = 0x0
515 16:44:14.145884 header.version = 0x6 (expected: 0x6)
516 16:44:14.146421 header.size = 0xd00 (expected: 0xd00)
517 16:44:14.149937 header.flags = 0x0
518 16:44:14.157031 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 16:44:14.172973 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
520 16:44:14.179574 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 16:44:14.182846 dram_init: ddr_geometry: 2
522 16:44:14.186048 [EMI] MDL number = 2
523 16:44:14.186665 [EMI] Get MDL freq = 0
524 16:44:14.189462 dram_init: ddr_type: 0
525 16:44:14.190034 is_discrete_lpddr4: 1
526 16:44:14.192620 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 16:44:14.193140
528 16:44:14.193513
529 16:44:14.196191 [Bian_co] ETT version 0.0.0.1
530 16:44:14.202807 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 16:44:14.203386
532 16:44:14.206261 dramc_set_vcore_voltage set vcore to 650000
533 16:44:14.209537 Read voltage for 800, 4
534 16:44:14.210115 Vio18 = 0
535 16:44:14.210524 Vcore = 650000
536 16:44:14.213210 Vdram = 0
537 16:44:14.213681 Vddq = 0
538 16:44:14.214052 Vmddr = 0
539 16:44:14.216059 dram_init: config_dvfs: 1
540 16:44:14.219761 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 16:44:14.226342 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 16:44:14.230877 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
543 16:44:14.234387 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
544 16:44:14.237655 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
545 16:44:14.241473 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
546 16:44:14.245090 MEM_TYPE=3, freq_sel=18
547 16:44:14.245575 sv_algorithm_assistance_LP4_1600
548 16:44:14.251648 ============ PULL DRAM RESETB DOWN ============
549 16:44:14.255022 ========== PULL DRAM RESETB DOWN end =========
550 16:44:14.257959 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 16:44:14.261667 ===================================
552 16:44:14.265079 LPDDR4 DRAM CONFIGURATION
553 16:44:14.267883 ===================================
554 16:44:14.271836 EX_ROW_EN[0] = 0x0
555 16:44:14.272413 EX_ROW_EN[1] = 0x0
556 16:44:14.274823 LP4Y_EN = 0x0
557 16:44:14.275441 WORK_FSP = 0x0
558 16:44:14.278210 WL = 0x2
559 16:44:14.278822 RL = 0x2
560 16:44:14.281188 BL = 0x2
561 16:44:14.281834 RPST = 0x0
562 16:44:14.286147 RD_PRE = 0x0
563 16:44:14.286762 WR_PRE = 0x1
564 16:44:14.289120 WR_PST = 0x0
565 16:44:14.289695 DBI_WR = 0x0
566 16:44:14.292055 DBI_RD = 0x0
567 16:44:14.292632 OTF = 0x1
568 16:44:14.294902 ===================================
569 16:44:14.298070 ===================================
570 16:44:14.301264 ANA top config
571 16:44:14.304435 ===================================
572 16:44:14.307749 DLL_ASYNC_EN = 0
573 16:44:14.308324 ALL_SLAVE_EN = 1
574 16:44:14.311236 NEW_RANK_MODE = 1
575 16:44:14.315469 DLL_IDLE_MODE = 1
576 16:44:14.318288 LP45_APHY_COMB_EN = 1
577 16:44:14.318892 TX_ODT_DIS = 1
578 16:44:14.321331 NEW_8X_MODE = 1
579 16:44:14.324523 ===================================
580 16:44:14.327600 ===================================
581 16:44:14.331097 data_rate = 1600
582 16:44:14.334977 CKR = 1
583 16:44:14.337601 DQ_P2S_RATIO = 8
584 16:44:14.341120 ===================================
585 16:44:14.344625 CA_P2S_RATIO = 8
586 16:44:14.345102 DQ_CA_OPEN = 0
587 16:44:14.348173 DQ_SEMI_OPEN = 0
588 16:44:14.350993 CA_SEMI_OPEN = 0
589 16:44:14.354474 CA_FULL_RATE = 0
590 16:44:14.357923 DQ_CKDIV4_EN = 1
591 16:44:14.361432 CA_CKDIV4_EN = 1
592 16:44:14.362006 CA_PREDIV_EN = 0
593 16:44:14.364785 PH8_DLY = 0
594 16:44:14.367706 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 16:44:14.371061 DQ_AAMCK_DIV = 4
596 16:44:14.374249 CA_AAMCK_DIV = 4
597 16:44:14.378028 CA_ADMCK_DIV = 4
598 16:44:14.378694 DQ_TRACK_CA_EN = 0
599 16:44:14.382449 CA_PICK = 800
600 16:44:14.384534 CA_MCKIO = 800
601 16:44:14.387579 MCKIO_SEMI = 0
602 16:44:14.391608 PLL_FREQ = 3068
603 16:44:14.394983 DQ_UI_PI_RATIO = 32
604 16:44:14.397796 CA_UI_PI_RATIO = 0
605 16:44:14.401222 ===================================
606 16:44:14.404470 ===================================
607 16:44:14.405058 memory_type:LPDDR4
608 16:44:14.409280 GP_NUM : 10
609 16:44:14.411448 SRAM_EN : 1
610 16:44:14.412053 MD32_EN : 0
611 16:44:14.415581 ===================================
612 16:44:14.418898 [ANA_INIT] >>>>>>>>>>>>>>
613 16:44:14.419502 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 16:44:14.422142 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 16:44:14.426833 ===================================
616 16:44:14.429959 data_rate = 1600,PCW = 0X7600
617 16:44:14.433971 ===================================
618 16:44:14.437173 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 16:44:14.441363 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 16:44:14.448639 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 16:44:14.452119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 16:44:14.455902 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 16:44:14.459231 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 16:44:14.459750 [ANA_INIT] flow start
625 16:44:14.463701 [ANA_INIT] PLL >>>>>>>>
626 16:44:14.466445 [ANA_INIT] PLL <<<<<<<<
627 16:44:14.466921 [ANA_INIT] MIDPI >>>>>>>>
628 16:44:14.470482 [ANA_INIT] MIDPI <<<<<<<<
629 16:44:14.474141 [ANA_INIT] DLL >>>>>>>>
630 16:44:14.474799 [ANA_INIT] flow end
631 16:44:14.477224 ============ LP4 DIFF to SE enter ============
632 16:44:14.481334 ============ LP4 DIFF to SE exit ============
633 16:44:14.484851 [ANA_INIT] <<<<<<<<<<<<<
634 16:44:14.488616 [Flow] Enable top DCM control >>>>>
635 16:44:14.491978 [Flow] Enable top DCM control <<<<<
636 16:44:14.495884 Enable DLL master slave shuffle
637 16:44:14.499899 ==============================================================
638 16:44:14.503368 Gating Mode config
639 16:44:14.507228 ==============================================================
640 16:44:14.510165 Config description:
641 16:44:14.517875 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 16:44:14.524951 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 16:44:14.529208 SELPH_MODE 0: By rank 1: By Phase
644 16:44:14.536193 ==============================================================
645 16:44:14.539562 GAT_TRACK_EN = 1
646 16:44:14.540069 RX_GATING_MODE = 2
647 16:44:14.543573 RX_GATING_TRACK_MODE = 2
648 16:44:14.547082 SELPH_MODE = 1
649 16:44:14.550742 PICG_EARLY_EN = 1
650 16:44:14.554415 VALID_LAT_VALUE = 1
651 16:44:14.558340 ==============================================================
652 16:44:14.561658 Enter into Gating configuration >>>>
653 16:44:14.565596 Exit from Gating configuration <<<<
654 16:44:14.569441 Enter into DVFS_PRE_config >>>>>
655 16:44:14.580759 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 16:44:14.584273 Exit from DVFS_PRE_config <<<<<
657 16:44:14.587991 Enter into PICG configuration >>>>
658 16:44:14.588588 Exit from PICG configuration <<<<
659 16:44:14.591444 [RX_INPUT] configuration >>>>>
660 16:44:14.594742 [RX_INPUT] configuration <<<<<
661 16:44:14.598613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
662 16:44:14.605815 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
663 16:44:14.613503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
664 16:44:14.617750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
665 16:44:14.624885 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
666 16:44:14.631984 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
667 16:44:14.636007 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
668 16:44:14.639313 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
669 16:44:14.643265 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
670 16:44:14.646911 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
671 16:44:14.650655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
672 16:44:14.654058 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 16:44:14.658544 ===================================
674 16:44:14.661909 LPDDR4 DRAM CONFIGURATION
675 16:44:14.665473 ===================================
676 16:44:14.665950 EX_ROW_EN[0] = 0x0
677 16:44:14.669184 EX_ROW_EN[1] = 0x0
678 16:44:14.669724 LP4Y_EN = 0x0
679 16:44:14.673052 WORK_FSP = 0x0
680 16:44:14.673782 WL = 0x2
681 16:44:14.676743 RL = 0x2
682 16:44:14.677218 BL = 0x2
683 16:44:14.677597 RPST = 0x0
684 16:44:14.680212 RD_PRE = 0x0
685 16:44:14.680684 WR_PRE = 0x1
686 16:44:14.684081 WR_PST = 0x0
687 16:44:14.684623 DBI_WR = 0x0
688 16:44:14.687759 DBI_RD = 0x0
689 16:44:14.688236 OTF = 0x1
690 16:44:14.691518 ===================================
691 16:44:14.694873 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
692 16:44:14.698828 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
693 16:44:14.705814 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
694 16:44:14.709583 ===================================
695 16:44:14.710175 LPDDR4 DRAM CONFIGURATION
696 16:44:14.713185 ===================================
697 16:44:14.717161 EX_ROW_EN[0] = 0x10
698 16:44:14.717752 EX_ROW_EN[1] = 0x0
699 16:44:14.720531 LP4Y_EN = 0x0
700 16:44:14.721121 WORK_FSP = 0x0
701 16:44:14.723784 WL = 0x2
702 16:44:14.724381 RL = 0x2
703 16:44:14.727667 BL = 0x2
704 16:44:14.728262 RPST = 0x0
705 16:44:14.731713 RD_PRE = 0x0
706 16:44:14.732303 WR_PRE = 0x1
707 16:44:14.734748 WR_PST = 0x0
708 16:44:14.735219 DBI_WR = 0x0
709 16:44:14.735592 DBI_RD = 0x0
710 16:44:14.738817 OTF = 0x1
711 16:44:14.742319 ===================================
712 16:44:14.745770 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
713 16:44:14.751993 nWR fixed to 40
714 16:44:14.755393 [ModeRegInit_LP4] CH0 RK0
715 16:44:14.755862 [ModeRegInit_LP4] CH0 RK1
716 16:44:14.758763 [ModeRegInit_LP4] CH1 RK0
717 16:44:14.759234 [ModeRegInit_LP4] CH1 RK1
718 16:44:14.762221 match AC timing 13
719 16:44:14.766058 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
720 16:44:14.769230 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
721 16:44:14.775371 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
722 16:44:14.778783 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
723 16:44:14.785649 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
724 16:44:14.786255 [EMI DOE] emi_dcm 0
725 16:44:14.792662 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
726 16:44:14.793240 ==
727 16:44:14.795759 Dram Type= 6, Freq= 0, CH_0, rank 0
728 16:44:14.798892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
729 16:44:14.799371 ==
730 16:44:14.805526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
731 16:44:14.809006 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
732 16:44:14.819304 [CA 0] Center 38 (7~69) winsize 63
733 16:44:14.822844 [CA 1] Center 38 (7~69) winsize 63
734 16:44:14.825554 [CA 2] Center 35 (5~66) winsize 62
735 16:44:14.828948 [CA 3] Center 35 (5~66) winsize 62
736 16:44:14.832372 [CA 4] Center 34 (4~65) winsize 62
737 16:44:14.835612 [CA 5] Center 33 (3~64) winsize 62
738 16:44:14.836189
739 16:44:14.838695 [CmdBusTrainingLP45] Vref(ca) range 1: 34
740 16:44:14.839167
741 16:44:14.841918 [CATrainingPosCal] consider 1 rank data
742 16:44:14.845822 u2DelayCellTimex100 = 270/100 ps
743 16:44:14.848586 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
744 16:44:14.855286 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
745 16:44:14.858649 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
746 16:44:14.862470 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
747 16:44:14.865514 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
748 16:44:14.868704 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
749 16:44:14.869190
750 16:44:14.872113 CA PerBit enable=1, Macro0, CA PI delay=33
751 16:44:14.872591
752 16:44:14.875574 [CBTSetCACLKResult] CA Dly = 33
753 16:44:14.876055 CS Dly: 6 (0~37)
754 16:44:14.878820 ==
755 16:44:14.882161 Dram Type= 6, Freq= 0, CH_0, rank 1
756 16:44:14.885222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
757 16:44:14.885716 ==
758 16:44:14.891721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
759 16:44:14.895100 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
760 16:44:14.906443 [CA 0] Center 38 (7~69) winsize 63
761 16:44:14.908489 [CA 1] Center 38 (8~69) winsize 62
762 16:44:14.911895 [CA 2] Center 36 (5~67) winsize 63
763 16:44:14.915607 [CA 3] Center 35 (5~66) winsize 62
764 16:44:14.919013 [CA 4] Center 35 (4~66) winsize 63
765 16:44:14.922099 [CA 5] Center 34 (4~65) winsize 62
766 16:44:14.922725
767 16:44:14.925886 [CmdBusTrainingLP45] Vref(ca) range 1: 34
768 16:44:14.926408
769 16:44:14.928921 [CATrainingPosCal] consider 2 rank data
770 16:44:14.932142 u2DelayCellTimex100 = 270/100 ps
771 16:44:14.935628 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
772 16:44:14.938784 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
773 16:44:14.945362 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
774 16:44:14.948438 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
775 16:44:14.951795 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
776 16:44:14.955201 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
777 16:44:14.955773
778 16:44:14.958827 CA PerBit enable=1, Macro0, CA PI delay=34
779 16:44:14.959303
780 16:44:14.962083 [CBTSetCACLKResult] CA Dly = 34
781 16:44:14.962718 CS Dly: 6 (0~38)
782 16:44:14.965217
783 16:44:14.968184 ----->DramcWriteLeveling(PI) begin...
784 16:44:14.968668 ==
785 16:44:14.972290 Dram Type= 6, Freq= 0, CH_0, rank 0
786 16:44:14.975222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
787 16:44:14.975721 ==
788 16:44:14.978189 Write leveling (Byte 0): 33 => 33
789 16:44:14.981832 Write leveling (Byte 1): 28 => 28
790 16:44:14.985622 DramcWriteLeveling(PI) end<-----
791 16:44:14.986196
792 16:44:14.986611 ==
793 16:44:14.988068 Dram Type= 6, Freq= 0, CH_0, rank 0
794 16:44:14.992157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
795 16:44:14.992739 ==
796 16:44:14.996199 [Gating] SW mode calibration
797 16:44:15.003010 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
798 16:44:15.006923 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
799 16:44:15.010053 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
800 16:44:15.016811 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
801 16:44:15.020505 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
802 16:44:15.024461 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 16:44:15.027027 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 16:44:15.033928 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:44:15.037845 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 16:44:15.040559 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 16:44:15.047484 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 16:44:15.050333 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 16:44:15.054100 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 16:44:15.060774 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 16:44:15.064125 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 16:44:15.067063 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 16:44:15.073877 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 16:44:15.076826 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 16:44:15.080553 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 16:44:15.087606 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
817 16:44:15.090959 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
818 16:44:15.093654 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 16:44:15.100506 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 16:44:15.104130 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 16:44:15.107186 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 16:44:15.113690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:44:15.117608 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 16:44:15.120457 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
825 16:44:15.123837 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
826 16:44:15.130593 0 9 12 | B1->B0 | 3231 3434 | 1 1 | (1 1) (1 1)
827 16:44:15.134039 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
828 16:44:15.137123 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 16:44:15.143874 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 16:44:15.147376 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 16:44:15.150342 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 16:44:15.157368 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
833 16:44:15.160916 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
834 16:44:15.164169 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
835 16:44:15.170339 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 16:44:15.173795 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 16:44:15.177845 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 16:44:15.183755 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 16:44:15.188524 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 16:44:15.190487 0 11 4 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
841 16:44:15.197245 0 11 8 | B1->B0 | 2424 4646 | 1 0 | (0 0) (0 0)
842 16:44:15.200343 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
843 16:44:15.204426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
844 16:44:15.210991 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 16:44:15.213651 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 16:44:15.216809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 16:44:15.223647 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 16:44:15.226875 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
849 16:44:15.230141 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
850 16:44:15.236811 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 16:44:15.239953 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 16:44:15.243860 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 16:44:15.250083 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 16:44:15.253852 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 16:44:15.256947 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 16:44:15.261072 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 16:44:15.267246 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 16:44:15.270003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 16:44:15.273837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 16:44:15.280246 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 16:44:15.283235 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 16:44:15.286618 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 16:44:15.293665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 16:44:15.297513 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
865 16:44:15.300016 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 16:44:15.303195 Total UI for P1: 0, mck2ui 16
867 16:44:15.306888 best dqsien dly found for B0: ( 0, 14, 4)
868 16:44:15.310171 Total UI for P1: 0, mck2ui 16
869 16:44:15.312957 best dqsien dly found for B1: ( 0, 14, 4)
870 16:44:15.316424 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
871 16:44:15.320248 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
872 16:44:15.320842
873 16:44:15.326436 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
874 16:44:15.329559 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
875 16:44:15.330038 [Gating] SW calibration Done
876 16:44:15.332986 ==
877 16:44:15.336256 Dram Type= 6, Freq= 0, CH_0, rank 0
878 16:44:15.339417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
879 16:44:15.339893 ==
880 16:44:15.340503 RX Vref Scan: 0
881 16:44:15.340906
882 16:44:15.342687 RX Vref 0 -> 0, step: 1
883 16:44:15.343157
884 16:44:15.346633 RX Delay -130 -> 252, step: 16
885 16:44:15.349444 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
886 16:44:15.353356 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
887 16:44:15.360360 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
888 16:44:15.363262 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
889 16:44:15.366729 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
890 16:44:15.369526 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
891 16:44:15.373519 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
892 16:44:15.379707 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
893 16:44:15.383090 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
894 16:44:15.386198 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
895 16:44:15.389676 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
896 16:44:15.393076 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
897 16:44:15.399722 iDelay=222, Bit 12, Center 85 (-18 ~ 189) 208
898 16:44:15.404084 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
899 16:44:15.406384 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
900 16:44:15.409589 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
901 16:44:15.410244 ==
902 16:44:15.413117 Dram Type= 6, Freq= 0, CH_0, rank 0
903 16:44:15.419374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 16:44:15.419949 ==
905 16:44:15.420337 DQS Delay:
906 16:44:15.420766 DQS0 = 0, DQS1 = 0
907 16:44:15.422775 DQM Delay:
908 16:44:15.423504 DQM0 = 94, DQM1 = 80
909 16:44:15.426600 DQ Delay:
910 16:44:15.429623 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
911 16:44:15.433168 DQ4 =93, DQ5 =85, DQ6 =109, DQ7 =101
912 16:44:15.436757 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
913 16:44:15.439678 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
914 16:44:15.440261
915 16:44:15.440640
916 16:44:15.441004 ==
917 16:44:15.442564 Dram Type= 6, Freq= 0, CH_0, rank 0
918 16:44:15.445955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 16:44:15.446564 ==
920 16:44:15.446951
921 16:44:15.447366
922 16:44:15.449071 TX Vref Scan disable
923 16:44:15.449549 == TX Byte 0 ==
924 16:44:15.455819 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
925 16:44:15.459138 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
926 16:44:15.459618 == TX Byte 1 ==
927 16:44:15.466562 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
928 16:44:15.469221 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
929 16:44:15.469697 ==
930 16:44:15.472667 Dram Type= 6, Freq= 0, CH_0, rank 0
931 16:44:15.476313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
932 16:44:15.476916 ==
933 16:44:15.490655 TX Vref=22, minBit 8, minWin=26, winSum=437
934 16:44:15.493931 TX Vref=24, minBit 8, minWin=26, winSum=442
935 16:44:15.497498 TX Vref=26, minBit 11, minWin=26, winSum=446
936 16:44:15.500639 TX Vref=28, minBit 11, minWin=27, winSum=451
937 16:44:15.504406 TX Vref=30, minBit 0, minWin=28, winSum=453
938 16:44:15.510738 TX Vref=32, minBit 5, minWin=28, winSum=456
939 16:44:15.513891 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 32
940 16:44:15.514505
941 16:44:15.517533 Final TX Range 1 Vref 32
942 16:44:15.518114
943 16:44:15.518549 ==
944 16:44:15.520503 Dram Type= 6, Freq= 0, CH_0, rank 0
945 16:44:15.524867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
946 16:44:15.525468 ==
947 16:44:15.527003
948 16:44:15.527480
949 16:44:15.527857 TX Vref Scan disable
950 16:44:15.530513 == TX Byte 0 ==
951 16:44:15.535545 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
952 16:44:15.540862 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
953 16:44:15.541343 == TX Byte 1 ==
954 16:44:15.543580 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
955 16:44:15.550835 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
956 16:44:15.551581
957 16:44:15.552047 [DATLAT]
958 16:44:15.552410 Freq=800, CH0 RK0
959 16:44:15.552762
960 16:44:15.553883 DATLAT Default: 0xa
961 16:44:15.554387 0, 0xFFFF, sum = 0
962 16:44:15.557299 1, 0xFFFF, sum = 0
963 16:44:15.557781 2, 0xFFFF, sum = 0
964 16:44:15.560842 3, 0xFFFF, sum = 0
965 16:44:15.564278 4, 0xFFFF, sum = 0
966 16:44:15.564865 5, 0xFFFF, sum = 0
967 16:44:15.567565 6, 0xFFFF, sum = 0
968 16:44:15.568152 7, 0xFFFF, sum = 0
969 16:44:15.570612 8, 0xFFFF, sum = 0
970 16:44:15.571095 9, 0x0, sum = 1
971 16:44:15.571479 10, 0x0, sum = 2
972 16:44:15.573956 11, 0x0, sum = 3
973 16:44:15.574574 12, 0x0, sum = 4
974 16:44:15.576919 best_step = 10
975 16:44:15.577396
976 16:44:15.577772 ==
977 16:44:15.580589 Dram Type= 6, Freq= 0, CH_0, rank 0
978 16:44:15.583539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
979 16:44:15.584028 ==
980 16:44:15.587016 RX Vref Scan: 1
981 16:44:15.587485
982 16:44:15.591303 Set Vref Range= 32 -> 127
983 16:44:15.591876
984 16:44:15.592247 RX Vref 32 -> 127, step: 1
985 16:44:15.592596
986 16:44:15.593434 RX Delay -95 -> 252, step: 8
987 16:44:15.593834
988 16:44:15.597076 Set Vref, RX VrefLevel [Byte0]: 32
989 16:44:15.600862 [Byte1]: 32
990 16:44:15.601439
991 16:44:15.603639 Set Vref, RX VrefLevel [Byte0]: 33
992 16:44:15.607648 [Byte1]: 33
993 16:44:15.611270
994 16:44:15.611763 Set Vref, RX VrefLevel [Byte0]: 34
995 16:44:15.614621 [Byte1]: 34
996 16:44:15.618633
997 16:44:15.622138 Set Vref, RX VrefLevel [Byte0]: 35
998 16:44:15.622761 [Byte1]: 35
999 16:44:15.626845
1000 16:44:15.627471 Set Vref, RX VrefLevel [Byte0]: 36
1001 16:44:15.629481 [Byte1]: 36
1002 16:44:15.634170
1003 16:44:15.634727 Set Vref, RX VrefLevel [Byte0]: 37
1004 16:44:15.636862 [Byte1]: 37
1005 16:44:15.641691
1006 16:44:15.642291 Set Vref, RX VrefLevel [Byte0]: 38
1007 16:44:15.645391 [Byte1]: 38
1008 16:44:15.648766
1009 16:44:15.649231 Set Vref, RX VrefLevel [Byte0]: 39
1010 16:44:15.652023 [Byte1]: 39
1011 16:44:15.656611
1012 16:44:15.657079 Set Vref, RX VrefLevel [Byte0]: 40
1013 16:44:15.659815 [Byte1]: 40
1014 16:44:15.664348
1015 16:44:15.664918 Set Vref, RX VrefLevel [Byte0]: 41
1016 16:44:15.667767 [Byte1]: 41
1017 16:44:15.672252
1018 16:44:15.672870 Set Vref, RX VrefLevel [Byte0]: 42
1019 16:44:15.675872 [Byte1]: 42
1020 16:44:15.679988
1021 16:44:15.680589 Set Vref, RX VrefLevel [Byte0]: 43
1022 16:44:15.682985 [Byte1]: 43
1023 16:44:15.687389
1024 16:44:15.688004 Set Vref, RX VrefLevel [Byte0]: 44
1025 16:44:15.690796 [Byte1]: 44
1026 16:44:15.694578
1027 16:44:15.697573 Set Vref, RX VrefLevel [Byte0]: 45
1028 16:44:15.698103 [Byte1]: 45
1029 16:44:15.702792
1030 16:44:15.703355 Set Vref, RX VrefLevel [Byte0]: 46
1031 16:44:15.705445 [Byte1]: 46
1032 16:44:15.709786
1033 16:44:15.710347 Set Vref, RX VrefLevel [Byte0]: 47
1034 16:44:15.713257 [Byte1]: 47
1035 16:44:15.717825
1036 16:44:15.718411 Set Vref, RX VrefLevel [Byte0]: 48
1037 16:44:15.721394 [Byte1]: 48
1038 16:44:15.725197
1039 16:44:15.725757 Set Vref, RX VrefLevel [Byte0]: 49
1040 16:44:15.728158 [Byte1]: 49
1041 16:44:15.732704
1042 16:44:15.733273 Set Vref, RX VrefLevel [Byte0]: 50
1043 16:44:15.736240 [Byte1]: 50
1044 16:44:15.739857
1045 16:44:15.740320 Set Vref, RX VrefLevel [Byte0]: 51
1046 16:44:15.743743 [Byte1]: 51
1047 16:44:15.747602
1048 16:44:15.748085 Set Vref, RX VrefLevel [Byte0]: 52
1049 16:44:15.751469 [Byte1]: 52
1050 16:44:15.754958
1051 16:44:15.755416 Set Vref, RX VrefLevel [Byte0]: 53
1052 16:44:15.758441 [Byte1]: 53
1053 16:44:15.762964
1054 16:44:15.763531 Set Vref, RX VrefLevel [Byte0]: 54
1055 16:44:15.766068 [Byte1]: 54
1056 16:44:15.770584
1057 16:44:15.771198 Set Vref, RX VrefLevel [Byte0]: 55
1058 16:44:15.773529 [Byte1]: 55
1059 16:44:15.778191
1060 16:44:15.778709 Set Vref, RX VrefLevel [Byte0]: 56
1061 16:44:15.781357 [Byte1]: 56
1062 16:44:15.785315
1063 16:44:15.785776 Set Vref, RX VrefLevel [Byte0]: 57
1064 16:44:15.789134 [Byte1]: 57
1065 16:44:15.793426
1066 16:44:15.793993 Set Vref, RX VrefLevel [Byte0]: 58
1067 16:44:15.796480 [Byte1]: 58
1068 16:44:15.800746
1069 16:44:15.801304 Set Vref, RX VrefLevel [Byte0]: 59
1070 16:44:15.804405 [Byte1]: 59
1071 16:44:15.809060
1072 16:44:15.809627 Set Vref, RX VrefLevel [Byte0]: 60
1073 16:44:15.811525 [Byte1]: 60
1074 16:44:15.816484
1075 16:44:15.817048 Set Vref, RX VrefLevel [Byte0]: 61
1076 16:44:15.819296 [Byte1]: 61
1077 16:44:15.823793
1078 16:44:15.824364 Set Vref, RX VrefLevel [Byte0]: 62
1079 16:44:15.826949 [Byte1]: 62
1080 16:44:15.831287
1081 16:44:15.831855 Set Vref, RX VrefLevel [Byte0]: 63
1082 16:44:15.835000 [Byte1]: 63
1083 16:44:15.839240
1084 16:44:15.839817 Set Vref, RX VrefLevel [Byte0]: 64
1085 16:44:15.842441 [Byte1]: 64
1086 16:44:15.846737
1087 16:44:15.847296 Set Vref, RX VrefLevel [Byte0]: 65
1088 16:44:15.849703 [Byte1]: 65
1089 16:44:15.853949
1090 16:44:15.854448 Set Vref, RX VrefLevel [Byte0]: 66
1091 16:44:15.857455 [Byte1]: 66
1092 16:44:15.861715
1093 16:44:15.862177 Set Vref, RX VrefLevel [Byte0]: 67
1094 16:44:15.865233 [Byte1]: 67
1095 16:44:15.869374
1096 16:44:15.869945 Set Vref, RX VrefLevel [Byte0]: 68
1097 16:44:15.872574 [Byte1]: 68
1098 16:44:15.876915
1099 16:44:15.877492 Set Vref, RX VrefLevel [Byte0]: 69
1100 16:44:15.880163 [Byte1]: 69
1101 16:44:15.884282
1102 16:44:15.884767 Set Vref, RX VrefLevel [Byte0]: 70
1103 16:44:15.887651 [Byte1]: 70
1104 16:44:15.891943
1105 16:44:15.892498 Set Vref, RX VrefLevel [Byte0]: 71
1106 16:44:15.895513 [Byte1]: 71
1107 16:44:15.899530
1108 16:44:15.899991 Set Vref, RX VrefLevel [Byte0]: 72
1109 16:44:15.903150 [Byte1]: 72
1110 16:44:15.907383
1111 16:44:15.907941 Set Vref, RX VrefLevel [Byte0]: 73
1112 16:44:15.910945 [Byte1]: 73
1113 16:44:15.914781
1114 16:44:15.915243 Set Vref, RX VrefLevel [Byte0]: 74
1115 16:44:15.917779 [Byte1]: 74
1116 16:44:15.922638
1117 16:44:15.923100 Set Vref, RX VrefLevel [Byte0]: 75
1118 16:44:15.925898 [Byte1]: 75
1119 16:44:15.930454
1120 16:44:15.931016 Set Vref, RX VrefLevel [Byte0]: 76
1121 16:44:15.933850 [Byte1]: 76
1122 16:44:15.938612
1123 16:44:15.939186 Set Vref, RX VrefLevel [Byte0]: 77
1124 16:44:15.940677 [Byte1]: 77
1125 16:44:15.945489
1126 16:44:15.946049 Final RX Vref Byte 0 = 61 to rank0
1127 16:44:15.948751 Final RX Vref Byte 1 = 61 to rank0
1128 16:44:15.952370 Final RX Vref Byte 0 = 61 to rank1
1129 16:44:15.954956 Final RX Vref Byte 1 = 61 to rank1==
1130 16:44:15.958733 Dram Type= 6, Freq= 0, CH_0, rank 0
1131 16:44:15.965513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1132 16:44:15.966089 ==
1133 16:44:15.966501 DQS Delay:
1134 16:44:15.966849 DQS0 = 0, DQS1 = 0
1135 16:44:15.968641 DQM Delay:
1136 16:44:15.969200 DQM0 = 93, DQM1 = 83
1137 16:44:15.971806 DQ Delay:
1138 16:44:15.975118 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1139 16:44:15.978293 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1140 16:44:15.981545 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1141 16:44:15.985239 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1142 16:44:15.985705
1143 16:44:15.986068
1144 16:44:15.991660 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
1145 16:44:15.994932 CH0 RK0: MR19=606, MR18=3B36
1146 16:44:16.001315 CH0_RK0: MR19=0x606, MR18=0x3B36, DQSOSC=394, MR23=63, INC=95, DEC=63
1147 16:44:16.001776
1148 16:44:16.005677 ----->DramcWriteLeveling(PI) begin...
1149 16:44:16.006249 ==
1150 16:44:16.009054 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 16:44:16.011560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 16:44:16.012029 ==
1153 16:44:16.015075 Write leveling (Byte 0): 30 => 30
1154 16:44:16.018943 Write leveling (Byte 1): 28 => 28
1155 16:44:16.021998 DramcWriteLeveling(PI) end<-----
1156 16:44:16.022668
1157 16:44:16.023043 ==
1158 16:44:16.025544 Dram Type= 6, Freq= 0, CH_0, rank 1
1159 16:44:16.028614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1160 16:44:16.029077 ==
1161 16:44:16.032338 [Gating] SW mode calibration
1162 16:44:16.038861 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1163 16:44:16.045603 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1164 16:44:16.049133 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1165 16:44:16.052123 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1166 16:44:16.059083 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1167 16:44:16.061991 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 16:44:16.105596 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 16:44:16.106188 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 16:44:16.106619 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 16:44:16.106972 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 16:44:16.107647 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 16:44:16.108042 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 16:44:16.108514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 16:44:16.109000 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 16:44:16.109362 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 16:44:16.109689 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 16:44:16.110347 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 16:44:16.113971 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 16:44:16.120775 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 16:44:16.123993 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1182 16:44:16.127767 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 16:44:16.134162 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 16:44:16.137176 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 16:44:16.140272 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 16:44:16.143516 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 16:44:16.150690 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 16:44:16.154342 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 16:44:16.157208 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1190 16:44:16.164796 0 9 8 | B1->B0 | 2d2d 3434 | 1 0 | (1 1) (0 0)
1191 16:44:16.167465 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 16:44:16.170580 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 16:44:16.177078 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 16:44:16.180630 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 16:44:16.184181 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 16:44:16.190462 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 16:44:16.194007 0 10 4 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
1198 16:44:16.197032 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1199 16:44:16.203418 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 16:44:16.207070 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 16:44:16.210096 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 16:44:16.217237 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 16:44:16.220388 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 16:44:16.223744 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 16:44:16.230504 0 11 4 | B1->B0 | 2424 2d2d | 0 1 | (0 0) (0 0)
1206 16:44:16.233591 0 11 8 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
1207 16:44:16.237195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 16:44:16.243671 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 16:44:16.247569 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 16:44:16.251792 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 16:44:16.255006 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 16:44:16.258077 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 16:44:16.265140 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 16:44:16.268805 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1215 16:44:16.271803 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 16:44:16.278523 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 16:44:16.281842 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 16:44:16.285037 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 16:44:16.292301 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 16:44:16.294912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 16:44:16.298382 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 16:44:16.305341 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 16:44:16.308347 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 16:44:16.311901 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 16:44:16.314975 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 16:44:16.321565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 16:44:16.325418 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 16:44:16.328651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 16:44:16.335289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1230 16:44:16.338478 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1231 16:44:16.341599 Total UI for P1: 0, mck2ui 16
1232 16:44:16.344987 best dqsien dly found for B0: ( 0, 14, 4)
1233 16:44:16.349007 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1234 16:44:16.352269 Total UI for P1: 0, mck2ui 16
1235 16:44:16.355004 best dqsien dly found for B1: ( 0, 14, 6)
1236 16:44:16.358148 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1237 16:44:16.361785 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1238 16:44:16.362257
1239 16:44:16.368531 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1240 16:44:16.371682 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1241 16:44:16.372158 [Gating] SW calibration Done
1242 16:44:16.375050 ==
1243 16:44:16.378805 Dram Type= 6, Freq= 0, CH_0, rank 1
1244 16:44:16.381465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1245 16:44:16.381949 ==
1246 16:44:16.382474 RX Vref Scan: 0
1247 16:44:16.382927
1248 16:44:16.384951 RX Vref 0 -> 0, step: 1
1249 16:44:16.385525
1250 16:44:16.388237 RX Delay -130 -> 252, step: 16
1251 16:44:16.391500 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1252 16:44:16.395148 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1253 16:44:16.401630 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1254 16:44:16.404938 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1255 16:44:16.408384 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1256 16:44:16.411377 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1257 16:44:16.415031 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1258 16:44:16.421412 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1259 16:44:16.424517 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
1260 16:44:16.428096 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1261 16:44:16.431547 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1262 16:44:16.434587 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1263 16:44:16.441345 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1264 16:44:16.445095 iDelay=222, Bit 13, Center 85 (-18 ~ 189) 208
1265 16:44:16.448525 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1266 16:44:16.451037 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1267 16:44:16.451506 ==
1268 16:44:16.454541 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 16:44:16.461698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 16:44:16.462272 ==
1271 16:44:16.462699 DQS Delay:
1272 16:44:16.464661 DQS0 = 0, DQS1 = 0
1273 16:44:16.465227 DQM Delay:
1274 16:44:16.465600 DQM0 = 90, DQM1 = 80
1275 16:44:16.467936 DQ Delay:
1276 16:44:16.470933 DQ0 =85, DQ1 =93, DQ2 =93, DQ3 =77
1277 16:44:16.474752 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1278 16:44:16.477779 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1279 16:44:16.481507 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1280 16:44:16.482092
1281 16:44:16.482504
1282 16:44:16.482851 ==
1283 16:44:16.485032 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 16:44:16.487936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 16:44:16.488512 ==
1286 16:44:16.488892
1287 16:44:16.489236
1288 16:44:16.490985 TX Vref Scan disable
1289 16:44:16.494481 == TX Byte 0 ==
1290 16:44:16.497783 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1291 16:44:16.500737 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1292 16:44:16.504842 == TX Byte 1 ==
1293 16:44:16.507505 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1294 16:44:16.510991 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1295 16:44:16.511563 ==
1296 16:44:16.514230 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 16:44:16.517393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 16:44:16.517922 ==
1299 16:44:16.532364 TX Vref=22, minBit 3, minWin=27, winSum=443
1300 16:44:16.535805 TX Vref=24, minBit 8, minWin=27, winSum=446
1301 16:44:16.538874 TX Vref=26, minBit 8, minWin=27, winSum=452
1302 16:44:16.542638 TX Vref=28, minBit 8, minWin=27, winSum=449
1303 16:44:16.545902 TX Vref=30, minBit 8, minWin=27, winSum=454
1304 16:44:16.548719 TX Vref=32, minBit 8, minWin=27, winSum=455
1305 16:44:16.555190 [TxChooseVref] Worse bit 8, Min win 27, Win sum 455, Final Vref 32
1306 16:44:16.555752
1307 16:44:16.558692 Final TX Range 1 Vref 32
1308 16:44:16.559159
1309 16:44:16.559520 ==
1310 16:44:16.561784 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 16:44:16.565566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 16:44:16.566024 ==
1313 16:44:16.566410
1314 16:44:16.568644
1315 16:44:16.569094 TX Vref Scan disable
1316 16:44:16.572083 == TX Byte 0 ==
1317 16:44:16.575098 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1318 16:44:16.581616 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1319 16:44:16.582026 == TX Byte 1 ==
1320 16:44:16.585171 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1321 16:44:16.591895 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1322 16:44:16.592286
1323 16:44:16.592520 [DATLAT]
1324 16:44:16.592734 Freq=800, CH0 RK1
1325 16:44:16.592940
1326 16:44:16.595229 DATLAT Default: 0xa
1327 16:44:16.595628 0, 0xFFFF, sum = 0
1328 16:44:16.598381 1, 0xFFFF, sum = 0
1329 16:44:16.598677 2, 0xFFFF, sum = 0
1330 16:44:16.602242 3, 0xFFFF, sum = 0
1331 16:44:16.602672 4, 0xFFFF, sum = 0
1332 16:44:16.606412 5, 0xFFFF, sum = 0
1333 16:44:16.609372 6, 0xFFFF, sum = 0
1334 16:44:16.609769 7, 0xFFFF, sum = 0
1335 16:44:16.612381 8, 0xFFFF, sum = 0
1336 16:44:16.612780 9, 0x0, sum = 1
1337 16:44:16.613024 10, 0x0, sum = 2
1338 16:44:16.615093 11, 0x0, sum = 3
1339 16:44:16.615493 12, 0x0, sum = 4
1340 16:44:16.618242 best_step = 10
1341 16:44:16.618659
1342 16:44:16.618898 ==
1343 16:44:16.621388 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 16:44:16.624751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 16:44:16.625047 ==
1346 16:44:16.628268 RX Vref Scan: 0
1347 16:44:16.628664
1348 16:44:16.628918 RX Vref 0 -> 0, step: 1
1349 16:44:16.631713
1350 16:44:16.632103 RX Delay -79 -> 252, step: 8
1351 16:44:16.638418 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1352 16:44:16.642021 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1353 16:44:16.644624 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1354 16:44:16.647970 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1355 16:44:16.655291 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1356 16:44:16.658267 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1357 16:44:16.661465 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1358 16:44:16.665135 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1359 16:44:16.668525 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1360 16:44:16.675074 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1361 16:44:16.678130 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1362 16:44:16.681591 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1363 16:44:16.684996 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1364 16:44:16.688098 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1365 16:44:16.694838 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1366 16:44:16.698191 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1367 16:44:16.698773 ==
1368 16:44:16.701645 Dram Type= 6, Freq= 0, CH_0, rank 1
1369 16:44:16.704811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1370 16:44:16.705466 ==
1371 16:44:16.707879 DQS Delay:
1372 16:44:16.708335 DQS0 = 0, DQS1 = 0
1373 16:44:16.708695 DQM Delay:
1374 16:44:16.711083 DQM0 = 90, DQM1 = 82
1375 16:44:16.711542 DQ Delay:
1376 16:44:16.714722 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =84
1377 16:44:16.718139 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1378 16:44:16.721451 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1379 16:44:16.724629 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =92
1380 16:44:16.725180
1381 16:44:16.725542
1382 16:44:16.734254 [DQSOSCAuto] RK1, (LSB)MR18= 0x4721, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1383 16:44:16.737977 CH0 RK1: MR19=606, MR18=4721
1384 16:44:16.741622 CH0_RK1: MR19=0x606, MR18=0x4721, DQSOSC=392, MR23=63, INC=96, DEC=64
1385 16:44:16.744608 [RxdqsGatingPostProcess] freq 800
1386 16:44:16.751145 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1387 16:44:16.754277 Pre-setting of DQS Precalculation
1388 16:44:16.757993 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1389 16:44:16.758529 ==
1390 16:44:16.761112 Dram Type= 6, Freq= 0, CH_1, rank 0
1391 16:44:16.767890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 16:44:16.768448 ==
1393 16:44:16.771120 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1394 16:44:16.777676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1395 16:44:16.787161 [CA 0] Center 36 (6~67) winsize 62
1396 16:44:16.790461 [CA 1] Center 36 (6~67) winsize 62
1397 16:44:16.794003 [CA 2] Center 35 (5~65) winsize 61
1398 16:44:16.796788 [CA 3] Center 34 (4~65) winsize 62
1399 16:44:16.800220 [CA 4] Center 34 (4~65) winsize 62
1400 16:44:16.803738 [CA 5] Center 33 (3~64) winsize 62
1401 16:44:16.804287
1402 16:44:16.807038 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1403 16:44:16.807496
1404 16:44:16.810745 [CATrainingPosCal] consider 1 rank data
1405 16:44:16.813668 u2DelayCellTimex100 = 270/100 ps
1406 16:44:16.817389 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1407 16:44:16.824134 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1408 16:44:16.827039 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1409 16:44:16.830447 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 16:44:16.834048 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1411 16:44:16.837162 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1412 16:44:16.837709
1413 16:44:16.839915 CA PerBit enable=1, Macro0, CA PI delay=33
1414 16:44:16.840398
1415 16:44:16.843303 [CBTSetCACLKResult] CA Dly = 33
1416 16:44:16.846664 CS Dly: 5 (0~36)
1417 16:44:16.847120 ==
1418 16:44:16.850131 Dram Type= 6, Freq= 0, CH_1, rank 1
1419 16:44:16.853565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 16:44:16.854116 ==
1421 16:44:16.856948 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1422 16:44:16.863185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1423 16:44:16.873472 [CA 0] Center 37 (7~67) winsize 61
1424 16:44:16.876743 [CA 1] Center 37 (6~68) winsize 63
1425 16:44:16.879828 [CA 2] Center 35 (5~66) winsize 62
1426 16:44:16.883786 [CA 3] Center 34 (4~65) winsize 62
1427 16:44:16.886741 [CA 4] Center 35 (5~65) winsize 61
1428 16:44:16.890268 [CA 5] Center 34 (4~65) winsize 62
1429 16:44:16.890759
1430 16:44:16.893346 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1431 16:44:16.893915
1432 16:44:16.896791 [CATrainingPosCal] consider 2 rank data
1433 16:44:16.899686 u2DelayCellTimex100 = 270/100 ps
1434 16:44:16.904029 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1435 16:44:16.910307 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1436 16:44:16.913573 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1437 16:44:16.917550 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 16:44:16.921064 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1439 16:44:16.921644 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1440 16:44:16.925303
1441 16:44:16.928677 CA PerBit enable=1, Macro0, CA PI delay=34
1442 16:44:16.929259
1443 16:44:16.929635 [CBTSetCACLKResult] CA Dly = 34
1444 16:44:16.932589 CS Dly: 5 (0~37)
1445 16:44:16.933165
1446 16:44:16.936708 ----->DramcWriteLeveling(PI) begin...
1447 16:44:16.937294 ==
1448 16:44:16.939949 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 16:44:16.943543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 16:44:16.944141 ==
1451 16:44:16.946821 Write leveling (Byte 0): 26 => 26
1452 16:44:16.950558 Write leveling (Byte 1): 29 => 29
1453 16:44:16.953843 DramcWriteLeveling(PI) end<-----
1454 16:44:16.954311
1455 16:44:16.954730 ==
1456 16:44:16.957057 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 16:44:16.960012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 16:44:16.960486 ==
1459 16:44:16.963828 [Gating] SW mode calibration
1460 16:44:16.969799 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1461 16:44:16.973136 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1462 16:44:16.979756 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1463 16:44:16.983152 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1464 16:44:16.988130 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1465 16:44:16.993126 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 16:44:16.996503 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 16:44:17.000044 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 16:44:17.006331 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 16:44:17.009891 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 16:44:17.013126 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 16:44:17.020329 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 16:44:17.022840 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 16:44:17.026482 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 16:44:17.033035 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 16:44:17.036488 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 16:44:17.039979 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 16:44:17.046701 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1478 16:44:17.049842 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1479 16:44:17.053277 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1480 16:44:17.059251 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1481 16:44:17.062821 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 16:44:17.065810 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 16:44:17.072386 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 16:44:17.075716 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 16:44:17.079084 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 16:44:17.085928 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 16:44:17.089393 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 16:44:17.092858 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1489 16:44:17.099134 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 16:44:17.102527 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 16:44:17.106138 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 16:44:17.112802 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 16:44:17.115438 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 16:44:17.119089 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1495 16:44:17.125636 0 10 4 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
1496 16:44:17.129122 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 16:44:17.132144 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 16:44:17.139094 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 16:44:17.142638 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 16:44:17.145770 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 16:44:17.152966 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 16:44:17.155503 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 16:44:17.158730 0 11 4 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
1504 16:44:17.162297 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 16:44:17.168946 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 16:44:17.172506 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 16:44:17.175374 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 16:44:17.181970 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 16:44:17.185261 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 16:44:17.188970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 16:44:17.195428 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1512 16:44:17.198391 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 16:44:17.201550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 16:44:17.208857 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 16:44:17.211887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 16:44:17.215155 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 16:44:17.222424 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 16:44:17.225341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 16:44:17.228915 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 16:44:17.235104 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 16:44:17.238746 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 16:44:17.241772 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 16:44:17.247852 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 16:44:17.251576 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 16:44:17.254930 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 16:44:17.261718 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 16:44:17.264858 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1528 16:44:17.268024 Total UI for P1: 0, mck2ui 16
1529 16:44:17.271808 best dqsien dly found for B0: ( 0, 14, 2)
1530 16:44:17.274956 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1531 16:44:17.278019 Total UI for P1: 0, mck2ui 16
1532 16:44:17.281810 best dqsien dly found for B1: ( 0, 14, 4)
1533 16:44:17.284656 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1534 16:44:17.287761 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1535 16:44:17.288227
1536 16:44:17.294676 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1537 16:44:17.297998 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1538 16:44:17.300797 [Gating] SW calibration Done
1539 16:44:17.301287 ==
1540 16:44:17.304401 Dram Type= 6, Freq= 0, CH_1, rank 0
1541 16:44:17.307575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1542 16:44:17.308145 ==
1543 16:44:17.308515 RX Vref Scan: 0
1544 16:44:17.308856
1545 16:44:17.310994 RX Vref 0 -> 0, step: 1
1546 16:44:17.311560
1547 16:44:17.314646 RX Delay -130 -> 252, step: 16
1548 16:44:17.317810 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1549 16:44:17.321019 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1550 16:44:17.327377 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1551 16:44:17.330861 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1552 16:44:17.334044 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1553 16:44:17.337614 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1554 16:44:17.340807 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1555 16:44:17.347670 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1556 16:44:17.350696 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1557 16:44:17.355008 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1558 16:44:17.357924 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1559 16:44:17.361117 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1560 16:44:17.367633 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1561 16:44:17.370666 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1562 16:44:17.374010 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1563 16:44:17.377390 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1564 16:44:17.378025 ==
1565 16:44:17.380292 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 16:44:17.387616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 16:44:17.388159 ==
1568 16:44:17.388533 DQS Delay:
1569 16:44:17.388878 DQS0 = 0, DQS1 = 0
1570 16:44:17.390595 DQM Delay:
1571 16:44:17.391059 DQM0 = 91, DQM1 = 83
1572 16:44:17.393864 DQ Delay:
1573 16:44:17.397139 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1574 16:44:17.400609 DQ4 =93, DQ5 =101, DQ6 =93, DQ7 =93
1575 16:44:17.404245 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1576 16:44:17.407703 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1577 16:44:17.408279
1578 16:44:17.408651
1579 16:44:17.408991 ==
1580 16:44:17.411395 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 16:44:17.414724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 16:44:17.415298 ==
1583 16:44:17.415669
1584 16:44:17.416010
1585 16:44:17.417261 TX Vref Scan disable
1586 16:44:17.417726 == TX Byte 0 ==
1587 16:44:17.423850 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1588 16:44:17.427009 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1589 16:44:17.427478 == TX Byte 1 ==
1590 16:44:17.433970 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1591 16:44:17.437057 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1592 16:44:17.437627 ==
1593 16:44:17.440570 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 16:44:17.443432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 16:44:17.443902 ==
1596 16:44:17.457518 TX Vref=22, minBit 15, minWin=26, winSum=445
1597 16:44:17.461302 TX Vref=24, minBit 10, minWin=26, winSum=448
1598 16:44:17.464748 TX Vref=26, minBit 8, minWin=27, winSum=451
1599 16:44:17.467966 TX Vref=28, minBit 8, minWin=27, winSum=450
1600 16:44:17.471357 TX Vref=30, minBit 10, minWin=27, winSum=457
1601 16:44:17.478135 TX Vref=32, minBit 8, minWin=27, winSum=457
1602 16:44:17.481130 [TxChooseVref] Worse bit 10, Min win 27, Win sum 457, Final Vref 30
1603 16:44:17.481599
1604 16:44:17.484460 Final TX Range 1 Vref 30
1605 16:44:17.484928
1606 16:44:17.485290 ==
1607 16:44:17.487624 Dram Type= 6, Freq= 0, CH_1, rank 0
1608 16:44:17.491825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1609 16:44:17.492397 ==
1610 16:44:17.494465
1611 16:44:17.494926
1612 16:44:17.495293 TX Vref Scan disable
1613 16:44:17.498281 == TX Byte 0 ==
1614 16:44:17.501169 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1615 16:44:17.508322 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1616 16:44:17.508941 == TX Byte 1 ==
1617 16:44:17.511010 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1618 16:44:17.518082 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1619 16:44:17.518713
1620 16:44:17.519087 [DATLAT]
1621 16:44:17.519431 Freq=800, CH1 RK0
1622 16:44:17.519788
1623 16:44:17.520913 DATLAT Default: 0xa
1624 16:44:17.521377 0, 0xFFFF, sum = 0
1625 16:44:17.524722 1, 0xFFFF, sum = 0
1626 16:44:17.525302 2, 0xFFFF, sum = 0
1627 16:44:17.528512 3, 0xFFFF, sum = 0
1628 16:44:17.531618 4, 0xFFFF, sum = 0
1629 16:44:17.532200 5, 0xFFFF, sum = 0
1630 16:44:17.534209 6, 0xFFFF, sum = 0
1631 16:44:17.534727 7, 0xFFFF, sum = 0
1632 16:44:17.537994 8, 0xFFFF, sum = 0
1633 16:44:17.538625 9, 0x0, sum = 1
1634 16:44:17.541108 10, 0x0, sum = 2
1635 16:44:17.541685 11, 0x0, sum = 3
1636 16:44:17.542063 12, 0x0, sum = 4
1637 16:44:17.544715 best_step = 10
1638 16:44:17.545288
1639 16:44:17.545656 ==
1640 16:44:17.547507 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 16:44:17.550717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 16:44:17.551212 ==
1643 16:44:17.554268 RX Vref Scan: 1
1644 16:44:17.554773
1645 16:44:17.557835 Set Vref Range= 32 -> 127
1646 16:44:17.558463
1647 16:44:17.558867 RX Vref 32 -> 127, step: 1
1648 16:44:17.559217
1649 16:44:17.560939 RX Delay -95 -> 252, step: 8
1650 16:44:17.561402
1651 16:44:17.563839 Set Vref, RX VrefLevel [Byte0]: 32
1652 16:44:17.567263 [Byte1]: 32
1653 16:44:17.571055
1654 16:44:17.571622 Set Vref, RX VrefLevel [Byte0]: 33
1655 16:44:17.574319 [Byte1]: 33
1656 16:44:17.578785
1657 16:44:17.579356 Set Vref, RX VrefLevel [Byte0]: 34
1658 16:44:17.581448 [Byte1]: 34
1659 16:44:17.585921
1660 16:44:17.586532 Set Vref, RX VrefLevel [Byte0]: 35
1661 16:44:17.589122 [Byte1]: 35
1662 16:44:17.593971
1663 16:44:17.594583 Set Vref, RX VrefLevel [Byte0]: 36
1664 16:44:17.597699 [Byte1]: 36
1665 16:44:17.600932
1666 16:44:17.601399 Set Vref, RX VrefLevel [Byte0]: 37
1667 16:44:17.605000 [Byte1]: 37
1668 16:44:17.609039
1669 16:44:17.609614 Set Vref, RX VrefLevel [Byte0]: 38
1670 16:44:17.611950 [Byte1]: 38
1671 16:44:17.616280
1672 16:44:17.616857 Set Vref, RX VrefLevel [Byte0]: 39
1673 16:44:17.619912 [Byte1]: 39
1674 16:44:17.624727
1675 16:44:17.625295 Set Vref, RX VrefLevel [Byte0]: 40
1676 16:44:17.627443 [Byte1]: 40
1677 16:44:17.631585
1678 16:44:17.632157 Set Vref, RX VrefLevel [Byte0]: 41
1679 16:44:17.634528 [Byte1]: 41
1680 16:44:17.639141
1681 16:44:17.639714 Set Vref, RX VrefLevel [Byte0]: 42
1682 16:44:17.642944 [Byte1]: 42
1683 16:44:17.646711
1684 16:44:17.647291 Set Vref, RX VrefLevel [Byte0]: 43
1685 16:44:17.649830 [Byte1]: 43
1686 16:44:17.654345
1687 16:44:17.654964 Set Vref, RX VrefLevel [Byte0]: 44
1688 16:44:17.658186 [Byte1]: 44
1689 16:44:17.662003
1690 16:44:17.662711 Set Vref, RX VrefLevel [Byte0]: 45
1691 16:44:17.665415 [Byte1]: 45
1692 16:44:17.669486
1693 16:44:17.670058 Set Vref, RX VrefLevel [Byte0]: 46
1694 16:44:17.672806 [Byte1]: 46
1695 16:44:17.677348
1696 16:44:17.677923 Set Vref, RX VrefLevel [Byte0]: 47
1697 16:44:17.680125 [Byte1]: 47
1698 16:44:17.685064
1699 16:44:17.685638 Set Vref, RX VrefLevel [Byte0]: 48
1700 16:44:17.688158 [Byte1]: 48
1701 16:44:17.692286
1702 16:44:17.692755 Set Vref, RX VrefLevel [Byte0]: 49
1703 16:44:17.698554 [Byte1]: 49
1704 16:44:17.699110
1705 16:44:17.702165 Set Vref, RX VrefLevel [Byte0]: 50
1706 16:44:17.705173 [Byte1]: 50
1707 16:44:17.705639
1708 16:44:17.709046 Set Vref, RX VrefLevel [Byte0]: 51
1709 16:44:17.711705 [Byte1]: 51
1710 16:44:17.715248
1711 16:44:17.715830 Set Vref, RX VrefLevel [Byte0]: 52
1712 16:44:17.718415 [Byte1]: 52
1713 16:44:17.722818
1714 16:44:17.723381 Set Vref, RX VrefLevel [Byte0]: 53
1715 16:44:17.726576 [Byte1]: 53
1716 16:44:17.730449
1717 16:44:17.731012 Set Vref, RX VrefLevel [Byte0]: 54
1718 16:44:17.733754 [Byte1]: 54
1719 16:44:17.737867
1720 16:44:17.738448 Set Vref, RX VrefLevel [Byte0]: 55
1721 16:44:17.741956 [Byte1]: 55
1722 16:44:17.745513
1723 16:44:17.746078 Set Vref, RX VrefLevel [Byte0]: 56
1724 16:44:17.748758 [Byte1]: 56
1725 16:44:17.752976
1726 16:44:17.753434 Set Vref, RX VrefLevel [Byte0]: 57
1727 16:44:17.756746 [Byte1]: 57
1728 16:44:17.760915
1729 16:44:17.761476 Set Vref, RX VrefLevel [Byte0]: 58
1730 16:44:17.764139 [Byte1]: 58
1731 16:44:17.768262
1732 16:44:17.768821 Set Vref, RX VrefLevel [Byte0]: 59
1733 16:44:17.771668 [Byte1]: 59
1734 16:44:17.776555
1735 16:44:17.777118 Set Vref, RX VrefLevel [Byte0]: 60
1736 16:44:17.779038 [Byte1]: 60
1737 16:44:17.783701
1738 16:44:17.784263 Set Vref, RX VrefLevel [Byte0]: 61
1739 16:44:17.786844 [Byte1]: 61
1740 16:44:17.791197
1741 16:44:17.791761 Set Vref, RX VrefLevel [Byte0]: 62
1742 16:44:17.795080 [Byte1]: 62
1743 16:44:17.798769
1744 16:44:17.799317 Set Vref, RX VrefLevel [Byte0]: 63
1745 16:44:17.801728 [Byte1]: 63
1746 16:44:17.806155
1747 16:44:17.806775 Set Vref, RX VrefLevel [Byte0]: 64
1748 16:44:17.809734 [Byte1]: 64
1749 16:44:17.813732
1750 16:44:17.814302 Set Vref, RX VrefLevel [Byte0]: 65
1751 16:44:17.816961 [Byte1]: 65
1752 16:44:17.821553
1753 16:44:17.822120 Set Vref, RX VrefLevel [Byte0]: 66
1754 16:44:17.824974 [Byte1]: 66
1755 16:44:17.829298
1756 16:44:17.829855 Set Vref, RX VrefLevel [Byte0]: 67
1757 16:44:17.832453 [Byte1]: 67
1758 16:44:17.836947
1759 16:44:17.837519 Set Vref, RX VrefLevel [Byte0]: 68
1760 16:44:17.839939 [Byte1]: 68
1761 16:44:17.844601
1762 16:44:17.845171 Set Vref, RX VrefLevel [Byte0]: 69
1763 16:44:17.847620 [Byte1]: 69
1764 16:44:17.851751
1765 16:44:17.852215 Set Vref, RX VrefLevel [Byte0]: 70
1766 16:44:17.854877 [Byte1]: 70
1767 16:44:17.859659
1768 16:44:17.860235 Set Vref, RX VrefLevel [Byte0]: 71
1769 16:44:17.862573 [Byte1]: 71
1770 16:44:17.867795
1771 16:44:17.868365 Set Vref, RX VrefLevel [Byte0]: 72
1772 16:44:17.871057 [Byte1]: 72
1773 16:44:17.874410
1774 16:44:17.874875 Set Vref, RX VrefLevel [Byte0]: 73
1775 16:44:17.878453 [Byte1]: 73
1776 16:44:17.882171
1777 16:44:17.882675 Set Vref, RX VrefLevel [Byte0]: 74
1778 16:44:17.885762 [Byte1]: 74
1779 16:44:17.889967
1780 16:44:17.890569 Set Vref, RX VrefLevel [Byte0]: 75
1781 16:44:17.893378 [Byte1]: 75
1782 16:44:17.897815
1783 16:44:17.898421 Final RX Vref Byte 0 = 49 to rank0
1784 16:44:17.900932 Final RX Vref Byte 1 = 62 to rank0
1785 16:44:17.904013 Final RX Vref Byte 0 = 49 to rank1
1786 16:44:17.907839 Final RX Vref Byte 1 = 62 to rank1==
1787 16:44:17.910809 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 16:44:17.917636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 16:44:17.918243 ==
1790 16:44:17.918680 DQS Delay:
1791 16:44:17.919031 DQS0 = 0, DQS1 = 0
1792 16:44:17.920858 DQM Delay:
1793 16:44:17.921322 DQM0 = 92, DQM1 = 84
1794 16:44:17.924399 DQ Delay:
1795 16:44:17.927004 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
1796 16:44:17.930398 DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =88
1797 16:44:17.933826 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =80
1798 16:44:17.936908 DQ12 =92, DQ13 =92, DQ14 =88, DQ15 =88
1799 16:44:17.937476
1800 16:44:17.937843
1801 16:44:17.943741 [DQSOSCAuto] RK0, (LSB)MR18= 0x3452, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
1802 16:44:17.947116 CH1 RK0: MR19=606, MR18=3452
1803 16:44:17.953883 CH1_RK0: MR19=0x606, MR18=0x3452, DQSOSC=389, MR23=63, INC=97, DEC=65
1804 16:44:17.954520
1805 16:44:17.956921 ----->DramcWriteLeveling(PI) begin...
1806 16:44:17.957500 ==
1807 16:44:17.960494 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 16:44:17.963839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 16:44:17.964331 ==
1810 16:44:17.967063 Write leveling (Byte 0): 27 => 27
1811 16:44:17.970752 Write leveling (Byte 1): 28 => 28
1812 16:44:17.973802 DramcWriteLeveling(PI) end<-----
1813 16:44:17.974406
1814 16:44:17.974819 ==
1815 16:44:17.977231 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 16:44:17.980443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 16:44:17.980914 ==
1818 16:44:17.983921 [Gating] SW mode calibration
1819 16:44:17.990497 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 16:44:17.996895 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 16:44:18.000116 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1822 16:44:18.007094 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 16:44:18.009946 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 16:44:18.013325 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 16:44:18.019784 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 16:44:18.023869 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 16:44:18.026706 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 16:44:18.033041 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 16:44:18.036545 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 16:44:18.039812 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 16:44:18.046244 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 16:44:18.050713 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 16:44:18.053606 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 16:44:18.059664 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 16:44:18.062964 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 16:44:18.066303 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 16:44:18.073230 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1838 16:44:18.076114 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1839 16:44:18.079475 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1840 16:44:18.082863 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 16:44:18.089437 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 16:44:18.092731 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 16:44:18.099224 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 16:44:18.102659 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 16:44:18.106059 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 16:44:18.109234 0 9 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1847 16:44:18.116021 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1848 16:44:18.119200 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 16:44:18.122166 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 16:44:18.129051 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 16:44:18.132208 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 16:44:18.135664 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 16:44:18.142401 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 16:44:18.145361 0 10 4 | B1->B0 | 2c2c 3131 | 1 1 | (0 0) (0 1)
1855 16:44:18.148956 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1856 16:44:18.155759 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 16:44:18.158811 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 16:44:18.162469 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 16:44:18.169498 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 16:44:18.172007 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 16:44:18.175489 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 16:44:18.182556 0 11 4 | B1->B0 | 3333 2a2a | 1 0 | (0 0) (0 0)
1863 16:44:18.185534 0 11 8 | B1->B0 | 4545 3e3e | 0 0 | (0 0) (0 0)
1864 16:44:18.189109 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 16:44:18.195523 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 16:44:18.198515 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 16:44:18.202003 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 16:44:18.208693 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 16:44:18.211827 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1870 16:44:18.215242 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1871 16:44:18.221878 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1872 16:44:18.224878 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 16:44:18.228999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 16:44:18.235168 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 16:44:18.238651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 16:44:18.241921 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 16:44:18.248645 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 16:44:18.251476 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 16:44:18.254919 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 16:44:18.261484 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 16:44:18.265062 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 16:44:18.268502 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 16:44:18.275034 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 16:44:18.278708 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 16:44:18.281677 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 16:44:18.288667 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1887 16:44:18.291524 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1888 16:44:18.294956 Total UI for P1: 0, mck2ui 16
1889 16:44:18.298212 best dqsien dly found for B0: ( 0, 14, 4)
1890 16:44:18.302526 Total UI for P1: 0, mck2ui 16
1891 16:44:18.304887 best dqsien dly found for B1: ( 0, 14, 4)
1892 16:44:18.308878 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1893 16:44:18.311162 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1894 16:44:18.311637
1895 16:44:18.315630 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1896 16:44:18.318185 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 16:44:18.321240 [Gating] SW calibration Done
1898 16:44:18.321711 ==
1899 16:44:18.325019 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 16:44:18.328111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 16:44:18.328691 ==
1902 16:44:18.331937 RX Vref Scan: 0
1903 16:44:18.332506
1904 16:44:18.332880 RX Vref 0 -> 0, step: 1
1905 16:44:18.334865
1906 16:44:18.335377 RX Delay -130 -> 252, step: 16
1907 16:44:18.341498 iDelay=206, Bit 0, Center 101 (-2 ~ 205) 208
1908 16:44:18.344429 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1909 16:44:18.347966 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1910 16:44:18.351168 iDelay=206, Bit 3, Center 85 (-18 ~ 189) 208
1911 16:44:18.354752 iDelay=206, Bit 4, Center 85 (-18 ~ 189) 208
1912 16:44:18.361138 iDelay=206, Bit 5, Center 101 (-2 ~ 205) 208
1913 16:44:18.364487 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1914 16:44:18.367686 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1915 16:44:18.370760 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1916 16:44:18.374645 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1917 16:44:18.381471 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1918 16:44:18.384447 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1919 16:44:18.388028 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1920 16:44:18.390669 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1921 16:44:18.394180 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1922 16:44:18.401083 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1923 16:44:18.401301 ==
1924 16:44:18.404506 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 16:44:18.407652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 16:44:18.407890 ==
1927 16:44:18.408022 DQS Delay:
1928 16:44:18.410968 DQS0 = 0, DQS1 = 0
1929 16:44:18.411203 DQM Delay:
1930 16:44:18.414268 DQM0 = 91, DQM1 = 85
1931 16:44:18.414545 DQ Delay:
1932 16:44:18.417304 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1933 16:44:18.421041 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1934 16:44:18.424335 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
1935 16:44:18.427889 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1936 16:44:18.428281
1937 16:44:18.428527
1938 16:44:18.428746 ==
1939 16:44:18.430822 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 16:44:18.434510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 16:44:18.437810 ==
1942 16:44:18.438411
1943 16:44:18.438803
1944 16:44:18.439142 TX Vref Scan disable
1945 16:44:18.440801 == TX Byte 0 ==
1946 16:44:18.444038 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1947 16:44:18.447538 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1948 16:44:18.450914 == TX Byte 1 ==
1949 16:44:18.454440 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1950 16:44:18.457687 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1951 16:44:18.460632 ==
1952 16:44:18.461104 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 16:44:18.467476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 16:44:18.468075 ==
1955 16:44:18.479722 TX Vref=22, minBit 8, minWin=27, winSum=447
1956 16:44:18.482981 TX Vref=24, minBit 8, minWin=27, winSum=450
1957 16:44:18.486263 TX Vref=26, minBit 1, minWin=28, winSum=455
1958 16:44:18.490026 TX Vref=28, minBit 8, minWin=28, winSum=459
1959 16:44:18.492784 TX Vref=30, minBit 8, minWin=28, winSum=460
1960 16:44:18.499367 TX Vref=32, minBit 15, minWin=27, winSum=460
1961 16:44:18.502955 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
1962 16:44:18.503526
1963 16:44:18.506398 Final TX Range 1 Vref 30
1964 16:44:18.506964
1965 16:44:18.507338 ==
1966 16:44:18.509591 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 16:44:18.512402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 16:44:18.516145 ==
1969 16:44:18.516706
1970 16:44:18.517094
1971 16:44:18.517439 TX Vref Scan disable
1972 16:44:18.519936 == TX Byte 0 ==
1973 16:44:18.522518 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1974 16:44:18.529811 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1975 16:44:18.530410 == TX Byte 1 ==
1976 16:44:18.532704 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1977 16:44:18.540257 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1978 16:44:18.540824
1979 16:44:18.541195 [DATLAT]
1980 16:44:18.541540 Freq=800, CH1 RK1
1981 16:44:18.541876
1982 16:44:18.542539 DATLAT Default: 0xa
1983 16:44:18.542899 0, 0xFFFF, sum = 0
1984 16:44:18.546100 1, 0xFFFF, sum = 0
1985 16:44:18.546716 2, 0xFFFF, sum = 0
1986 16:44:18.549553 3, 0xFFFF, sum = 0
1987 16:44:18.552816 4, 0xFFFF, sum = 0
1988 16:44:18.553294 5, 0xFFFF, sum = 0
1989 16:44:18.555900 6, 0xFFFF, sum = 0
1990 16:44:18.556378 7, 0xFFFF, sum = 0
1991 16:44:18.559564 8, 0xFFFF, sum = 0
1992 16:44:18.560139 9, 0x0, sum = 1
1993 16:44:18.560522 10, 0x0, sum = 2
1994 16:44:18.562663 11, 0x0, sum = 3
1995 16:44:18.563139 12, 0x0, sum = 4
1996 16:44:18.565769 best_step = 10
1997 16:44:18.566262
1998 16:44:18.566686 ==
1999 16:44:18.569348 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 16:44:18.572591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 16:44:18.573161 ==
2002 16:44:18.576045 RX Vref Scan: 0
2003 16:44:18.576515
2004 16:44:18.576886 RX Vref 0 -> 0, step: 1
2005 16:44:18.579247
2006 16:44:18.579713 RX Delay -95 -> 252, step: 8
2007 16:44:18.586130 iDelay=209, Bit 0, Center 96 (1 ~ 192) 192
2008 16:44:18.589650 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
2009 16:44:18.593064 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2010 16:44:18.596006 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2011 16:44:18.599270 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
2012 16:44:18.606083 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2013 16:44:18.609468 iDelay=209, Bit 6, Center 100 (1 ~ 200) 200
2014 16:44:18.612825 iDelay=209, Bit 7, Center 92 (-7 ~ 192) 200
2015 16:44:18.617064 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2016 16:44:18.619441 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2017 16:44:18.625865 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2018 16:44:18.629655 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2019 16:44:18.632514 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2020 16:44:18.636307 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2021 16:44:18.639170 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2022 16:44:18.645864 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2023 16:44:18.646460 ==
2024 16:44:18.649362 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 16:44:18.652650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 16:44:18.653221 ==
2027 16:44:18.653595 DQS Delay:
2028 16:44:18.655658 DQS0 = 0, DQS1 = 0
2029 16:44:18.656129 DQM Delay:
2030 16:44:18.658971 DQM0 = 93, DQM1 = 84
2031 16:44:18.659544 DQ Delay:
2032 16:44:18.662640 DQ0 =96, DQ1 =84, DQ2 =84, DQ3 =88
2033 16:44:18.665699 DQ4 =96, DQ5 =108, DQ6 =100, DQ7 =92
2034 16:44:18.668706 DQ8 =68, DQ9 =76, DQ10 =84, DQ11 =80
2035 16:44:18.672134 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2036 16:44:18.672646
2037 16:44:18.673112
2038 16:44:18.682254 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a0f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
2039 16:44:18.682913 CH1 RK1: MR19=606, MR18=3A0F
2040 16:44:18.688796 CH1_RK1: MR19=0x606, MR18=0x3A0F, DQSOSC=395, MR23=63, INC=94, DEC=63
2041 16:44:18.692516 [RxdqsGatingPostProcess] freq 800
2042 16:44:18.699145 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 16:44:18.702321 Pre-setting of DQS Precalculation
2044 16:44:18.705884 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 16:44:18.712579 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 16:44:18.719560 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 16:44:18.722278
2048 16:44:18.722892
2049 16:44:18.723369 [Calibration Summary] 1600 Mbps
2050 16:44:18.725690 CH 0, Rank 0
2051 16:44:18.726161 SW Impedance : PASS
2052 16:44:18.729095 DUTY Scan : NO K
2053 16:44:18.732671 ZQ Calibration : PASS
2054 16:44:18.733244 Jitter Meter : NO K
2055 16:44:18.735671 CBT Training : PASS
2056 16:44:18.739247 Write leveling : PASS
2057 16:44:18.739857 RX DQS gating : PASS
2058 16:44:18.742494 RX DQ/DQS(RDDQC) : PASS
2059 16:44:18.745460 TX DQ/DQS : PASS
2060 16:44:18.746041 RX DATLAT : PASS
2061 16:44:18.748647 RX DQ/DQS(Engine): PASS
2062 16:44:18.751877 TX OE : NO K
2063 16:44:18.752347 All Pass.
2064 16:44:18.752708
2065 16:44:18.753042 CH 0, Rank 1
2066 16:44:18.755857 SW Impedance : PASS
2067 16:44:18.759219 DUTY Scan : NO K
2068 16:44:18.759682 ZQ Calibration : PASS
2069 16:44:18.762052 Jitter Meter : NO K
2070 16:44:18.762551 CBT Training : PASS
2071 16:44:18.765655 Write leveling : PASS
2072 16:44:18.768710 RX DQS gating : PASS
2073 16:44:18.769173 RX DQ/DQS(RDDQC) : PASS
2074 16:44:18.771936 TX DQ/DQS : PASS
2075 16:44:18.775633 RX DATLAT : PASS
2076 16:44:18.776372 RX DQ/DQS(Engine): PASS
2077 16:44:18.778673 TX OE : NO K
2078 16:44:18.779202 All Pass.
2079 16:44:18.779573
2080 16:44:18.781894 CH 1, Rank 0
2081 16:44:18.782396 SW Impedance : PASS
2082 16:44:18.785401 DUTY Scan : NO K
2083 16:44:18.788420 ZQ Calibration : PASS
2084 16:44:18.788876 Jitter Meter : NO K
2085 16:44:18.791836 CBT Training : PASS
2086 16:44:18.795339 Write leveling : PASS
2087 16:44:18.795799 RX DQS gating : PASS
2088 16:44:18.798773 RX DQ/DQS(RDDQC) : PASS
2089 16:44:18.802109 TX DQ/DQS : PASS
2090 16:44:18.802620 RX DATLAT : PASS
2091 16:44:18.805048 RX DQ/DQS(Engine): PASS
2092 16:44:18.805509 TX OE : NO K
2093 16:44:18.808792 All Pass.
2094 16:44:18.809371
2095 16:44:18.809748 CH 1, Rank 1
2096 16:44:18.812194 SW Impedance : PASS
2097 16:44:18.812751 DUTY Scan : NO K
2098 16:44:18.815449 ZQ Calibration : PASS
2099 16:44:18.819140 Jitter Meter : NO K
2100 16:44:18.819699 CBT Training : PASS
2101 16:44:18.821691 Write leveling : PASS
2102 16:44:18.825601 RX DQS gating : PASS
2103 16:44:18.826156 RX DQ/DQS(RDDQC) : PASS
2104 16:44:18.829017 TX DQ/DQS : PASS
2105 16:44:18.832012 RX DATLAT : PASS
2106 16:44:18.832570 RX DQ/DQS(Engine): PASS
2107 16:44:18.835369 TX OE : NO K
2108 16:44:18.835930 All Pass.
2109 16:44:18.836321
2110 16:44:18.838679 DramC Write-DBI off
2111 16:44:18.841702 PER_BANK_REFRESH: Hybrid Mode
2112 16:44:18.842273 TX_TRACKING: ON
2113 16:44:18.845223 [GetDramInforAfterCalByMRR] Vendor 6.
2114 16:44:18.848251 [GetDramInforAfterCalByMRR] Revision 606.
2115 16:44:18.851852 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 16:44:18.855082 MR0 0x3b3b
2117 16:44:18.855543 MR8 0x5151
2118 16:44:18.858120 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 16:44:18.858636
2120 16:44:18.862568 MR0 0x3b3b
2121 16:44:18.863125 MR8 0x5151
2122 16:44:18.864926 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 16:44:18.865486
2124 16:44:18.875061 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 16:44:18.878664 [FAST_K] Save calibration result to emmc
2126 16:44:18.881687 [FAST_K] Save calibration result to emmc
2127 16:44:18.885360 dram_init: config_dvfs: 1
2128 16:44:18.888277 dramc_set_vcore_voltage set vcore to 662500
2129 16:44:18.888925 Read voltage for 1200, 2
2130 16:44:18.891404 Vio18 = 0
2131 16:44:18.891863 Vcore = 662500
2132 16:44:18.892228 Vdram = 0
2133 16:44:18.894829 Vddq = 0
2134 16:44:18.895309 Vmddr = 0
2135 16:44:18.898169 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 16:44:18.904884 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 16:44:18.908094 MEM_TYPE=3, freq_sel=15
2138 16:44:18.912009 sv_algorithm_assistance_LP4_1600
2139 16:44:18.915328 ============ PULL DRAM RESETB DOWN ============
2140 16:44:18.918456 ========== PULL DRAM RESETB DOWN end =========
2141 16:44:18.921910 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 16:44:18.924782 ===================================
2143 16:44:18.928361 LPDDR4 DRAM CONFIGURATION
2144 16:44:18.931542 ===================================
2145 16:44:18.935215 EX_ROW_EN[0] = 0x0
2146 16:44:18.935772 EX_ROW_EN[1] = 0x0
2147 16:44:18.938232 LP4Y_EN = 0x0
2148 16:44:18.938835 WORK_FSP = 0x0
2149 16:44:18.941392 WL = 0x4
2150 16:44:18.941947 RL = 0x4
2151 16:44:18.945289 BL = 0x2
2152 16:44:18.945846 RPST = 0x0
2153 16:44:18.948135 RD_PRE = 0x0
2154 16:44:18.948601 WR_PRE = 0x1
2155 16:44:18.951864 WR_PST = 0x0
2156 16:44:18.955084 DBI_WR = 0x0
2157 16:44:18.955656 DBI_RD = 0x0
2158 16:44:18.959543 OTF = 0x1
2159 16:44:18.961182 ===================================
2160 16:44:18.965385 ===================================
2161 16:44:18.965961 ANA top config
2162 16:44:18.968477 ===================================
2163 16:44:18.971240 DLL_ASYNC_EN = 0
2164 16:44:18.971705 ALL_SLAVE_EN = 0
2165 16:44:18.974518 NEW_RANK_MODE = 1
2166 16:44:18.978177 DLL_IDLE_MODE = 1
2167 16:44:18.981828 LP45_APHY_COMB_EN = 1
2168 16:44:18.984621 TX_ODT_DIS = 1
2169 16:44:18.985188 NEW_8X_MODE = 1
2170 16:44:18.988179 ===================================
2171 16:44:18.991158 ===================================
2172 16:44:18.994741 data_rate = 2400
2173 16:44:18.998027 CKR = 1
2174 16:44:19.001165 DQ_P2S_RATIO = 8
2175 16:44:19.004525 ===================================
2176 16:44:19.007821 CA_P2S_RATIO = 8
2177 16:44:19.011589 DQ_CA_OPEN = 0
2178 16:44:19.012159 DQ_SEMI_OPEN = 0
2179 16:44:19.014529 CA_SEMI_OPEN = 0
2180 16:44:19.017993 CA_FULL_RATE = 0
2181 16:44:19.021635 DQ_CKDIV4_EN = 0
2182 16:44:19.024727 CA_CKDIV4_EN = 0
2183 16:44:19.028224 CA_PREDIV_EN = 0
2184 16:44:19.028791 PH8_DLY = 17
2185 16:44:19.031082 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 16:44:19.035234 DQ_AAMCK_DIV = 4
2187 16:44:19.037706 CA_AAMCK_DIV = 4
2188 16:44:19.041609 CA_ADMCK_DIV = 4
2189 16:44:19.044931 DQ_TRACK_CA_EN = 0
2190 16:44:19.045504 CA_PICK = 1200
2191 16:44:19.047657 CA_MCKIO = 1200
2192 16:44:19.051258 MCKIO_SEMI = 0
2193 16:44:19.054988 PLL_FREQ = 2366
2194 16:44:19.057717 DQ_UI_PI_RATIO = 32
2195 16:44:19.061288 CA_UI_PI_RATIO = 0
2196 16:44:19.064911 ===================================
2197 16:44:19.067983 ===================================
2198 16:44:19.068449 memory_type:LPDDR4
2199 16:44:19.071545 GP_NUM : 10
2200 16:44:19.075142 SRAM_EN : 1
2201 16:44:19.075714 MD32_EN : 0
2202 16:44:19.077706 ===================================
2203 16:44:19.081827 [ANA_INIT] >>>>>>>>>>>>>>
2204 16:44:19.084438 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 16:44:19.088059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 16:44:19.091085 ===================================
2207 16:44:19.094556 data_rate = 2400,PCW = 0X5b00
2208 16:44:19.097585 ===================================
2209 16:44:19.100968 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 16:44:19.104401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 16:44:19.111232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 16:44:19.114198 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 16:44:19.117565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 16:44:19.124532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 16:44:19.125104 [ANA_INIT] flow start
2216 16:44:19.127581 [ANA_INIT] PLL >>>>>>>>
2217 16:44:19.130754 [ANA_INIT] PLL <<<<<<<<
2218 16:44:19.131221 [ANA_INIT] MIDPI >>>>>>>>
2219 16:44:19.134444 [ANA_INIT] MIDPI <<<<<<<<
2220 16:44:19.137474 [ANA_INIT] DLL >>>>>>>>
2221 16:44:19.138035 [ANA_INIT] DLL <<<<<<<<
2222 16:44:19.141424 [ANA_INIT] flow end
2223 16:44:19.144105 ============ LP4 DIFF to SE enter ============
2224 16:44:19.147516 ============ LP4 DIFF to SE exit ============
2225 16:44:19.150793 [ANA_INIT] <<<<<<<<<<<<<
2226 16:44:19.154309 [Flow] Enable top DCM control >>>>>
2227 16:44:19.157798 [Flow] Enable top DCM control <<<<<
2228 16:44:19.161082 Enable DLL master slave shuffle
2229 16:44:19.167450 ==============================================================
2230 16:44:19.168055 Gating Mode config
2231 16:44:19.173804 ==============================================================
2232 16:44:19.174431 Config description:
2233 16:44:19.184016 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 16:44:19.190594 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 16:44:19.197651 SELPH_MODE 0: By rank 1: By Phase
2236 16:44:19.200405 ==============================================================
2237 16:44:19.203642 GAT_TRACK_EN = 1
2238 16:44:19.207114 RX_GATING_MODE = 2
2239 16:44:19.210603 RX_GATING_TRACK_MODE = 2
2240 16:44:19.213773 SELPH_MODE = 1
2241 16:44:19.217378 PICG_EARLY_EN = 1
2242 16:44:19.220196 VALID_LAT_VALUE = 1
2243 16:44:19.227140 ==============================================================
2244 16:44:19.230718 Enter into Gating configuration >>>>
2245 16:44:19.231220 Exit from Gating configuration <<<<
2246 16:44:19.233810 Enter into DVFS_PRE_config >>>>>
2247 16:44:19.247271 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 16:44:19.250565 Exit from DVFS_PRE_config <<<<<
2249 16:44:19.253816 Enter into PICG configuration >>>>
2250 16:44:19.257181 Exit from PICG configuration <<<<
2251 16:44:19.257751 [RX_INPUT] configuration >>>>>
2252 16:44:19.260316 [RX_INPUT] configuration <<<<<
2253 16:44:19.267400 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 16:44:19.270390 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 16:44:19.277092 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 16:44:19.283817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 16:44:19.290234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 16:44:19.297420 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 16:44:19.300432 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 16:44:19.303780 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 16:44:19.310496 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 16:44:19.313468 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 16:44:19.316699 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 16:44:19.320216 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 16:44:19.323401 ===================================
2266 16:44:19.326964 LPDDR4 DRAM CONFIGURATION
2267 16:44:19.330414 ===================================
2268 16:44:19.333949 EX_ROW_EN[0] = 0x0
2269 16:44:19.334572 EX_ROW_EN[1] = 0x0
2270 16:44:19.336533 LP4Y_EN = 0x0
2271 16:44:19.337004 WORK_FSP = 0x0
2272 16:44:19.340123 WL = 0x4
2273 16:44:19.340696 RL = 0x4
2274 16:44:19.343490 BL = 0x2
2275 16:44:19.344061 RPST = 0x0
2276 16:44:19.346586 RD_PRE = 0x0
2277 16:44:19.347056 WR_PRE = 0x1
2278 16:44:19.350342 WR_PST = 0x0
2279 16:44:19.350955 DBI_WR = 0x0
2280 16:44:19.353648 DBI_RD = 0x0
2281 16:44:19.357709 OTF = 0x1
2282 16:44:19.358285 ===================================
2283 16:44:19.364567 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 16:44:19.366509 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 16:44:19.370116 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 16:44:19.373142 ===================================
2287 16:44:19.376719 LPDDR4 DRAM CONFIGURATION
2288 16:44:19.379814 ===================================
2289 16:44:19.382895 EX_ROW_EN[0] = 0x10
2290 16:44:19.383368 EX_ROW_EN[1] = 0x0
2291 16:44:19.386436 LP4Y_EN = 0x0
2292 16:44:19.386976 WORK_FSP = 0x0
2293 16:44:19.389886 WL = 0x4
2294 16:44:19.390536 RL = 0x4
2295 16:44:19.393105 BL = 0x2
2296 16:44:19.393778 RPST = 0x0
2297 16:44:19.396256 RD_PRE = 0x0
2298 16:44:19.396717 WR_PRE = 0x1
2299 16:44:19.400263 WR_PST = 0x0
2300 16:44:19.400823 DBI_WR = 0x0
2301 16:44:19.403546 DBI_RD = 0x0
2302 16:44:19.404108 OTF = 0x1
2303 16:44:19.406398 ===================================
2304 16:44:19.413694 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 16:44:19.414262 ==
2306 16:44:19.416806 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 16:44:19.422918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 16:44:19.423456 ==
2309 16:44:19.423828 [Duty_Offset_Calibration]
2310 16:44:19.426223 B0:2 B1:0 CA:1
2311 16:44:19.426694
2312 16:44:19.429540 [DutyScan_Calibration_Flow] k_type=0
2313 16:44:19.437714
2314 16:44:19.438240 ==CLK 0==
2315 16:44:19.440831 Final CLK duty delay cell = -4
2316 16:44:19.444052 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2317 16:44:19.447512 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2318 16:44:19.451168 [-4] AVG Duty = 4953%(X100)
2319 16:44:19.451609
2320 16:44:19.454677 CH0 CLK Duty spec in!! Max-Min= 156%
2321 16:44:19.457845 [DutyScan_Calibration_Flow] ====Done====
2322 16:44:19.458264
2323 16:44:19.460559 [DutyScan_Calibration_Flow] k_type=1
2324 16:44:19.476998
2325 16:44:19.477553 ==DQS 0 ==
2326 16:44:19.480210 Final DQS duty delay cell = 0
2327 16:44:19.483648 [0] MAX Duty = 5187%(X100), DQS PI = 30
2328 16:44:19.487508 [0] MIN Duty = 4938%(X100), DQS PI = 2
2329 16:44:19.488065 [0] AVG Duty = 5062%(X100)
2330 16:44:19.489787
2331 16:44:19.490237 ==DQS 1 ==
2332 16:44:19.493039 Final DQS duty delay cell = -4
2333 16:44:19.496464 [-4] MAX Duty = 5156%(X100), DQS PI = 32
2334 16:44:19.500150 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2335 16:44:19.503354 [-4] AVG Duty = 5047%(X100)
2336 16:44:19.503907
2337 16:44:19.506998 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2338 16:44:19.507551
2339 16:44:19.510298 CH0 DQS 1 Duty spec in!! Max-Min= 218%
2340 16:44:19.513716 [DutyScan_Calibration_Flow] ====Done====
2341 16:44:19.514270
2342 16:44:19.516433 [DutyScan_Calibration_Flow] k_type=3
2343 16:44:19.533208
2344 16:44:19.533791 ==DQM 0 ==
2345 16:44:19.536976 Final DQM duty delay cell = 0
2346 16:44:19.540203 [0] MAX Duty = 5062%(X100), DQS PI = 24
2347 16:44:19.543170 [0] MIN Duty = 4844%(X100), DQS PI = 2
2348 16:44:19.546957 [0] AVG Duty = 4953%(X100)
2349 16:44:19.547516
2350 16:44:19.547872 ==DQM 1 ==
2351 16:44:19.549627 Final DQM duty delay cell = 0
2352 16:44:19.553241 [0] MAX Duty = 5218%(X100), DQS PI = 50
2353 16:44:19.556724 [0] MIN Duty = 5000%(X100), DQS PI = 24
2354 16:44:19.559404 [0] AVG Duty = 5109%(X100)
2355 16:44:19.559888
2356 16:44:19.562873 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2357 16:44:19.563331
2358 16:44:19.566644 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2359 16:44:19.569506 [DutyScan_Calibration_Flow] ====Done====
2360 16:44:19.569961
2361 16:44:19.573313 [DutyScan_Calibration_Flow] k_type=2
2362 16:44:19.589362
2363 16:44:19.589924 ==DQ 0 ==
2364 16:44:19.592736 Final DQ duty delay cell = -4
2365 16:44:19.595777 [-4] MAX Duty = 5031%(X100), DQS PI = 32
2366 16:44:19.599220 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2367 16:44:19.602539 [-4] AVG Duty = 4969%(X100)
2368 16:44:19.603113
2369 16:44:19.603593 ==DQ 1 ==
2370 16:44:19.606152 Final DQ duty delay cell = 0
2371 16:44:19.608972 [0] MAX Duty = 4938%(X100), DQS PI = 4
2372 16:44:19.612407 [0] MIN Duty = 4907%(X100), DQS PI = 0
2373 16:44:19.612988 [0] AVG Duty = 4922%(X100)
2374 16:44:19.615705
2375 16:44:19.618824 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2376 16:44:19.619402
2377 16:44:19.622957 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2378 16:44:19.625597 [DutyScan_Calibration_Flow] ====Done====
2379 16:44:19.626177 ==
2380 16:44:19.629631 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 16:44:19.632345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 16:44:19.632931 ==
2383 16:44:19.636860 [Duty_Offset_Calibration]
2384 16:44:19.637433 B0:0 B1:-1 CA:2
2385 16:44:19.637923
2386 16:44:19.638769 [DutyScan_Calibration_Flow] k_type=0
2387 16:44:19.648971
2388 16:44:19.649551 ==CLK 0==
2389 16:44:19.652613 Final CLK duty delay cell = 0
2390 16:44:19.655591 [0] MAX Duty = 5156%(X100), DQS PI = 10
2391 16:44:19.659374 [0] MIN Duty = 4969%(X100), DQS PI = 44
2392 16:44:19.659859 [0] AVG Duty = 5062%(X100)
2393 16:44:19.662270
2394 16:44:19.665522 CH1 CLK Duty spec in!! Max-Min= 187%
2395 16:44:19.668635 [DutyScan_Calibration_Flow] ====Done====
2396 16:44:19.669125
2397 16:44:19.672305 [DutyScan_Calibration_Flow] k_type=1
2398 16:44:19.688589
2399 16:44:19.689162 ==DQS 0 ==
2400 16:44:19.691927 Final DQS duty delay cell = 0
2401 16:44:19.695299 [0] MAX Duty = 5093%(X100), DQS PI = 24
2402 16:44:19.698716 [0] MIN Duty = 4969%(X100), DQS PI = 0
2403 16:44:19.699295 [0] AVG Duty = 5031%(X100)
2404 16:44:19.702332
2405 16:44:19.702966 ==DQS 1 ==
2406 16:44:19.705204 Final DQS duty delay cell = 0
2407 16:44:19.708643 [0] MAX Duty = 5156%(X100), DQS PI = 0
2408 16:44:19.711684 [0] MIN Duty = 4844%(X100), DQS PI = 36
2409 16:44:19.712264 [0] AVG Duty = 5000%(X100)
2410 16:44:19.715067
2411 16:44:19.718560 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2412 16:44:19.719142
2413 16:44:19.721966 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2414 16:44:19.724954 [DutyScan_Calibration_Flow] ====Done====
2415 16:44:19.725513
2416 16:44:19.728467 [DutyScan_Calibration_Flow] k_type=3
2417 16:44:19.745898
2418 16:44:19.746505 ==DQM 0 ==
2419 16:44:19.749209 Final DQM duty delay cell = 4
2420 16:44:19.751306 [4] MAX Duty = 5093%(X100), DQS PI = 6
2421 16:44:19.755100 [4] MIN Duty = 4969%(X100), DQS PI = 28
2422 16:44:19.755666 [4] AVG Duty = 5031%(X100)
2423 16:44:19.758491
2424 16:44:19.759061 ==DQM 1 ==
2425 16:44:19.761861 Final DQM duty delay cell = -4
2426 16:44:19.764902 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2427 16:44:19.769195 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2428 16:44:19.772305 [-4] AVG Duty = 4875%(X100)
2429 16:44:19.772816
2430 16:44:19.774724 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2431 16:44:19.775373
2432 16:44:19.778253 CH1 DQM 1 Duty spec in!! Max-Min= 249%
2433 16:44:19.781775 [DutyScan_Calibration_Flow] ====Done====
2434 16:44:19.782344
2435 16:44:19.784835 [DutyScan_Calibration_Flow] k_type=2
2436 16:44:19.801899
2437 16:44:19.802502 ==DQ 0 ==
2438 16:44:19.805351 Final DQ duty delay cell = 0
2439 16:44:19.808609 [0] MAX Duty = 5062%(X100), DQS PI = 20
2440 16:44:19.812149 [0] MIN Duty = 4938%(X100), DQS PI = 30
2441 16:44:19.812723 [0] AVG Duty = 5000%(X100)
2442 16:44:19.815268
2443 16:44:19.815833 ==DQ 1 ==
2444 16:44:19.818641 Final DQ duty delay cell = 0
2445 16:44:19.821905 [0] MAX Duty = 5031%(X100), DQS PI = 2
2446 16:44:19.824752 [0] MIN Duty = 4813%(X100), DQS PI = 34
2447 16:44:19.825217 [0] AVG Duty = 4922%(X100)
2448 16:44:19.825587
2449 16:44:19.828563 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2450 16:44:19.831591
2451 16:44:19.835170 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2452 16:44:19.839281 [DutyScan_Calibration_Flow] ====Done====
2453 16:44:19.841739 nWR fixed to 30
2454 16:44:19.842313 [ModeRegInit_LP4] CH0 RK0
2455 16:44:19.845034 [ModeRegInit_LP4] CH0 RK1
2456 16:44:19.848399 [ModeRegInit_LP4] CH1 RK0
2457 16:44:19.851815 [ModeRegInit_LP4] CH1 RK1
2458 16:44:19.852379 match AC timing 7
2459 16:44:19.855099 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 16:44:19.861779 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 16:44:19.865226 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 16:44:19.871483 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 16:44:19.874600 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 16:44:19.875096 ==
2465 16:44:19.877806 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 16:44:19.881859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 16:44:19.882333 ==
2468 16:44:19.888221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 16:44:19.894584 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 16:44:19.901893 [CA 0] Center 38 (7~69) winsize 63
2471 16:44:19.904978 [CA 1] Center 38 (7~69) winsize 63
2472 16:44:19.908117 [CA 2] Center 35 (5~66) winsize 62
2473 16:44:19.912093 [CA 3] Center 34 (4~65) winsize 62
2474 16:44:19.915497 [CA 4] Center 34 (4~65) winsize 62
2475 16:44:19.918192 [CA 5] Center 33 (3~63) winsize 61
2476 16:44:19.918800
2477 16:44:19.921713 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 16:44:19.922282
2479 16:44:19.924981 [CATrainingPosCal] consider 1 rank data
2480 16:44:19.928267 u2DelayCellTimex100 = 270/100 ps
2481 16:44:19.931511 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2482 16:44:19.938478 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2483 16:44:19.941425 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2484 16:44:19.944854 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2485 16:44:19.948508 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2486 16:44:19.951141 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2487 16:44:19.951628
2488 16:44:19.955203 CA PerBit enable=1, Macro0, CA PI delay=33
2489 16:44:19.955789
2490 16:44:19.958060 [CBTSetCACLKResult] CA Dly = 33
2491 16:44:19.958691 CS Dly: 6 (0~37)
2492 16:44:19.961297 ==
2493 16:44:19.965356 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 16:44:19.967909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 16:44:19.968382 ==
2496 16:44:19.970988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 16:44:19.978109 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2498 16:44:19.987296 [CA 0] Center 39 (8~70) winsize 63
2499 16:44:19.990394 [CA 1] Center 38 (8~69) winsize 62
2500 16:44:19.994300 [CA 2] Center 35 (5~66) winsize 62
2501 16:44:19.997762 [CA 3] Center 35 (5~66) winsize 62
2502 16:44:20.000662 [CA 4] Center 34 (4~65) winsize 62
2503 16:44:20.004218 [CA 5] Center 33 (3~64) winsize 62
2504 16:44:20.004795
2505 16:44:20.007867 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2506 16:44:20.008436
2507 16:44:20.010537 [CATrainingPosCal] consider 2 rank data
2508 16:44:20.013882 u2DelayCellTimex100 = 270/100 ps
2509 16:44:20.018247 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2510 16:44:20.020735 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2511 16:44:20.027548 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2512 16:44:20.030658 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2513 16:44:20.034266 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2514 16:44:20.037132 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2515 16:44:20.037707
2516 16:44:20.040534 CA PerBit enable=1, Macro0, CA PI delay=33
2517 16:44:20.041108
2518 16:44:20.043912 [CBTSetCACLKResult] CA Dly = 33
2519 16:44:20.044487 CS Dly: 7 (0~39)
2520 16:44:20.044863
2521 16:44:20.047152 ----->DramcWriteLeveling(PI) begin...
2522 16:44:20.050502 ==
2523 16:44:20.053871 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 16:44:20.057209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 16:44:20.057774 ==
2526 16:44:20.060535 Write leveling (Byte 0): 35 => 35
2527 16:44:20.064443 Write leveling (Byte 1): 32 => 32
2528 16:44:20.067384 DramcWriteLeveling(PI) end<-----
2529 16:44:20.067855
2530 16:44:20.068223 ==
2531 16:44:20.070395 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 16:44:20.073782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 16:44:20.074348 ==
2534 16:44:20.077139 [Gating] SW mode calibration
2535 16:44:20.084457 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 16:44:20.090285 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 16:44:20.093365 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2538 16:44:20.096933 0 15 4 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
2539 16:44:20.103556 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 16:44:20.107277 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 16:44:20.110142 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 16:44:20.113798 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 16:44:20.120737 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2544 16:44:20.123877 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2545 16:44:20.127073 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2546 16:44:20.134291 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 16:44:20.137135 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 16:44:20.140000 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 16:44:20.147406 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 16:44:20.150041 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 16:44:20.153843 1 0 24 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2552 16:44:20.160409 1 0 28 | B1->B0 | 2626 4646 | 1 0 | (0 0) (0 0)
2553 16:44:20.164079 1 1 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2554 16:44:20.166545 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 16:44:20.173299 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 16:44:20.177204 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 16:44:20.179921 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 16:44:20.186905 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 16:44:20.190173 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2560 16:44:20.193746 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2561 16:44:20.200172 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2562 16:44:20.203417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 16:44:20.206795 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 16:44:20.213135 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 16:44:20.217055 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 16:44:20.219926 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 16:44:20.226570 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 16:44:20.229704 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 16:44:20.233042 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 16:44:20.239704 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 16:44:20.243145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 16:44:20.246870 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 16:44:20.252986 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 16:44:20.256035 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 16:44:20.259772 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2576 16:44:20.263047 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2577 16:44:20.269768 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2578 16:44:20.273589 Total UI for P1: 0, mck2ui 16
2579 16:44:20.276050 best dqsien dly found for B0: ( 1, 3, 26)
2580 16:44:20.279926 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2581 16:44:20.283027 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 16:44:20.286313 Total UI for P1: 0, mck2ui 16
2583 16:44:20.289665 best dqsien dly found for B1: ( 1, 4, 2)
2584 16:44:20.292971 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2585 16:44:20.295966 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2586 16:44:20.296436
2587 16:44:20.303112 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2588 16:44:20.306054 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2589 16:44:20.309512 [Gating] SW calibration Done
2590 16:44:20.310265 ==
2591 16:44:20.313465 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 16:44:20.316063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 16:44:20.316537 ==
2594 16:44:20.316907 RX Vref Scan: 0
2595 16:44:20.317254
2596 16:44:20.320202 RX Vref 0 -> 0, step: 1
2597 16:44:20.320767
2598 16:44:20.322587 RX Delay -40 -> 252, step: 8
2599 16:44:20.325967 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2600 16:44:20.329958 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2601 16:44:20.336220 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2602 16:44:20.339713 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2603 16:44:20.343057 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2604 16:44:20.346650 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2605 16:44:20.349432 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2606 16:44:20.352897 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2607 16:44:20.359366 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2608 16:44:20.362818 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2609 16:44:20.365769 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2610 16:44:20.369578 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2611 16:44:20.373201 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2612 16:44:20.379170 iDelay=208, Bit 13, Center 111 (48 ~ 175) 128
2613 16:44:20.382612 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2614 16:44:20.386505 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2615 16:44:20.387075 ==
2616 16:44:20.389076 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 16:44:20.392745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 16:44:20.396828 ==
2619 16:44:20.397399 DQS Delay:
2620 16:44:20.397771 DQS0 = 0, DQS1 = 0
2621 16:44:20.399302 DQM Delay:
2622 16:44:20.399776 DQM0 = 123, DQM1 = 109
2623 16:44:20.402482 DQ Delay:
2624 16:44:20.405811 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2625 16:44:20.409311 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2626 16:44:20.412986 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2627 16:44:20.415567 DQ12 =115, DQ13 =111, DQ14 =123, DQ15 =115
2628 16:44:20.416039
2629 16:44:20.416408
2630 16:44:20.416823 ==
2631 16:44:20.419191 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 16:44:20.422323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 16:44:20.422940 ==
2634 16:44:20.423439
2635 16:44:20.425660
2636 16:44:20.426221 TX Vref Scan disable
2637 16:44:20.429098 == TX Byte 0 ==
2638 16:44:20.432791 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2639 16:44:20.435368 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2640 16:44:20.439208 == TX Byte 1 ==
2641 16:44:20.442402 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2642 16:44:20.446088 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2643 16:44:20.446687 ==
2644 16:44:20.448933 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 16:44:20.455656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 16:44:20.456226 ==
2647 16:44:20.466062 TX Vref=22, minBit 0, minWin=23, winSum=393
2648 16:44:20.469650 TX Vref=24, minBit 0, minWin=24, winSum=396
2649 16:44:20.473461 TX Vref=26, minBit 0, minWin=24, winSum=413
2650 16:44:20.476067 TX Vref=28, minBit 1, minWin=24, winSum=411
2651 16:44:20.479327 TX Vref=30, minBit 1, minWin=25, winSum=414
2652 16:44:20.485971 TX Vref=32, minBit 2, minWin=25, winSum=414
2653 16:44:20.489442 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 30
2654 16:44:20.489983
2655 16:44:20.492807 Final TX Range 1 Vref 30
2656 16:44:20.493395
2657 16:44:20.493828 ==
2658 16:44:20.496225 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 16:44:20.499218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 16:44:20.499692 ==
2661 16:44:20.502330
2662 16:44:20.502820
2663 16:44:20.503186 TX Vref Scan disable
2664 16:44:20.505919 == TX Byte 0 ==
2665 16:44:20.508944 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2666 16:44:20.512513 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2667 16:44:20.515727 == TX Byte 1 ==
2668 16:44:20.519518 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2669 16:44:20.522411 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2670 16:44:20.525668
2671 16:44:20.526136 [DATLAT]
2672 16:44:20.526538 Freq=1200, CH0 RK0
2673 16:44:20.526889
2674 16:44:20.529600 DATLAT Default: 0xd
2675 16:44:20.530162 0, 0xFFFF, sum = 0
2676 16:44:20.532914 1, 0xFFFF, sum = 0
2677 16:44:20.535756 2, 0xFFFF, sum = 0
2678 16:44:20.536324 3, 0xFFFF, sum = 0
2679 16:44:20.539229 4, 0xFFFF, sum = 0
2680 16:44:20.539806 5, 0xFFFF, sum = 0
2681 16:44:20.542033 6, 0xFFFF, sum = 0
2682 16:44:20.542540 7, 0xFFFF, sum = 0
2683 16:44:20.545588 8, 0xFFFF, sum = 0
2684 16:44:20.546154 9, 0xFFFF, sum = 0
2685 16:44:20.549099 10, 0xFFFF, sum = 0
2686 16:44:20.549671 11, 0xFFFF, sum = 0
2687 16:44:20.552451 12, 0x0, sum = 1
2688 16:44:20.553024 13, 0x0, sum = 2
2689 16:44:20.555729 14, 0x0, sum = 3
2690 16:44:20.556302 15, 0x0, sum = 4
2691 16:44:20.559256 best_step = 13
2692 16:44:20.559817
2693 16:44:20.560189 ==
2694 16:44:20.562246 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 16:44:20.565539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 16:44:20.566025 ==
2697 16:44:20.566670 RX Vref Scan: 1
2698 16:44:20.568701
2699 16:44:20.569165 Set Vref Range= 32 -> 127
2700 16:44:20.569533
2701 16:44:20.572047 RX Vref 32 -> 127, step: 1
2702 16:44:20.572517
2703 16:44:20.575362 RX Delay -13 -> 252, step: 4
2704 16:44:20.575919
2705 16:44:20.578718 Set Vref, RX VrefLevel [Byte0]: 32
2706 16:44:20.581955 [Byte1]: 32
2707 16:44:20.582454
2708 16:44:20.585931 Set Vref, RX VrefLevel [Byte0]: 33
2709 16:44:20.588664 [Byte1]: 33
2710 16:44:20.592241
2711 16:44:20.592796 Set Vref, RX VrefLevel [Byte0]: 34
2712 16:44:20.595343 [Byte1]: 34
2713 16:44:20.600479
2714 16:44:20.601038 Set Vref, RX VrefLevel [Byte0]: 35
2715 16:44:20.603696 [Byte1]: 35
2716 16:44:20.607872
2717 16:44:20.610919 Set Vref, RX VrefLevel [Byte0]: 36
2718 16:44:20.614421 [Byte1]: 36
2719 16:44:20.614992
2720 16:44:20.617800 Set Vref, RX VrefLevel [Byte0]: 37
2721 16:44:20.621079 [Byte1]: 37
2722 16:44:20.621639
2723 16:44:20.624923 Set Vref, RX VrefLevel [Byte0]: 38
2724 16:44:20.627840 [Byte1]: 38
2725 16:44:20.631596
2726 16:44:20.632153 Set Vref, RX VrefLevel [Byte0]: 39
2727 16:44:20.634885 [Byte1]: 39
2728 16:44:20.639502
2729 16:44:20.640065 Set Vref, RX VrefLevel [Byte0]: 40
2730 16:44:20.643116 [Byte1]: 40
2731 16:44:20.648849
2732 16:44:20.649418 Set Vref, RX VrefLevel [Byte0]: 41
2733 16:44:20.650800 [Byte1]: 41
2734 16:44:20.655129
2735 16:44:20.655597 Set Vref, RX VrefLevel [Byte0]: 42
2736 16:44:20.658528 [Byte1]: 42
2737 16:44:20.663728
2738 16:44:20.664291 Set Vref, RX VrefLevel [Byte0]: 43
2739 16:44:20.667181 [Byte1]: 43
2740 16:44:20.670993
2741 16:44:20.671460 Set Vref, RX VrefLevel [Byte0]: 44
2742 16:44:20.674278 [Byte1]: 44
2743 16:44:20.679080
2744 16:44:20.679660 Set Vref, RX VrefLevel [Byte0]: 45
2745 16:44:20.682185 [Byte1]: 45
2746 16:44:20.686890
2747 16:44:20.687461 Set Vref, RX VrefLevel [Byte0]: 46
2748 16:44:20.689925 [Byte1]: 46
2749 16:44:20.695065
2750 16:44:20.695614 Set Vref, RX VrefLevel [Byte0]: 47
2751 16:44:20.697956 [Byte1]: 47
2752 16:44:20.702518
2753 16:44:20.703083 Set Vref, RX VrefLevel [Byte0]: 48
2754 16:44:20.705974 [Byte1]: 48
2755 16:44:20.710656
2756 16:44:20.711286 Set Vref, RX VrefLevel [Byte0]: 49
2757 16:44:20.714589 [Byte1]: 49
2758 16:44:20.718465
2759 16:44:20.719018 Set Vref, RX VrefLevel [Byte0]: 50
2760 16:44:20.721434 [Byte1]: 50
2761 16:44:20.726343
2762 16:44:20.726951 Set Vref, RX VrefLevel [Byte0]: 51
2763 16:44:20.729604 [Byte1]: 51
2764 16:44:20.734284
2765 16:44:20.734896 Set Vref, RX VrefLevel [Byte0]: 52
2766 16:44:20.737529 [Byte1]: 52
2767 16:44:20.742547
2768 16:44:20.743105 Set Vref, RX VrefLevel [Byte0]: 53
2769 16:44:20.745551 [Byte1]: 53
2770 16:44:20.750180
2771 16:44:20.750803 Set Vref, RX VrefLevel [Byte0]: 54
2772 16:44:20.753137 [Byte1]: 54
2773 16:44:20.758214
2774 16:44:20.758815 Set Vref, RX VrefLevel [Byte0]: 55
2775 16:44:20.761173 [Byte1]: 55
2776 16:44:20.765797
2777 16:44:20.766406 Set Vref, RX VrefLevel [Byte0]: 56
2778 16:44:20.768965 [Byte1]: 56
2779 16:44:20.773634
2780 16:44:20.777234 Set Vref, RX VrefLevel [Byte0]: 57
2781 16:44:20.777800 [Byte1]: 57
2782 16:44:20.781449
2783 16:44:20.781911 Set Vref, RX VrefLevel [Byte0]: 58
2784 16:44:20.785019 [Byte1]: 58
2785 16:44:20.789709
2786 16:44:20.790273 Set Vref, RX VrefLevel [Byte0]: 59
2787 16:44:20.792970 [Byte1]: 59
2788 16:44:20.797591
2789 16:44:20.798154 Set Vref, RX VrefLevel [Byte0]: 60
2790 16:44:20.800939 [Byte1]: 60
2791 16:44:20.805254
2792 16:44:20.805817 Set Vref, RX VrefLevel [Byte0]: 61
2793 16:44:20.810900 [Byte1]: 61
2794 16:44:20.813017
2795 16:44:20.813479 Set Vref, RX VrefLevel [Byte0]: 62
2796 16:44:20.816743 [Byte1]: 62
2797 16:44:20.820943
2798 16:44:20.821492 Set Vref, RX VrefLevel [Byte0]: 63
2799 16:44:20.824135 [Byte1]: 63
2800 16:44:20.828659
2801 16:44:20.829173 Set Vref, RX VrefLevel [Byte0]: 64
2802 16:44:20.832370 [Byte1]: 64
2803 16:44:20.836608
2804 16:44:20.837173 Set Vref, RX VrefLevel [Byte0]: 65
2805 16:44:20.843323 [Byte1]: 65
2806 16:44:20.843872
2807 16:44:20.846439 Set Vref, RX VrefLevel [Byte0]: 66
2808 16:44:20.849824 [Byte1]: 66
2809 16:44:20.850423
2810 16:44:20.853520 Set Vref, RX VrefLevel [Byte0]: 67
2811 16:44:20.856733 [Byte1]: 67
2812 16:44:20.860609
2813 16:44:20.861356 Set Vref, RX VrefLevel [Byte0]: 68
2814 16:44:20.863807 [Byte1]: 68
2815 16:44:20.868342
2816 16:44:20.868899 Set Vref, RX VrefLevel [Byte0]: 69
2817 16:44:20.872022 [Byte1]: 69
2818 16:44:20.877480
2819 16:44:20.878041 Final RX Vref Byte 0 = 59 to rank0
2820 16:44:20.879344 Final RX Vref Byte 1 = 49 to rank0
2821 16:44:20.882697 Final RX Vref Byte 0 = 59 to rank1
2822 16:44:20.886548 Final RX Vref Byte 1 = 49 to rank1==
2823 16:44:20.889489 Dram Type= 6, Freq= 0, CH_0, rank 0
2824 16:44:20.896284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 16:44:20.896846 ==
2826 16:44:20.897219 DQS Delay:
2827 16:44:20.897562 DQS0 = 0, DQS1 = 0
2828 16:44:20.899361 DQM Delay:
2829 16:44:20.899849 DQM0 = 122, DQM1 = 109
2830 16:44:20.902961 DQ Delay:
2831 16:44:20.906620 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2832 16:44:20.910313 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2833 16:44:20.913126 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =108
2834 16:44:20.916182 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =118
2835 16:44:20.916745
2836 16:44:20.917112
2837 16:44:20.922732 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2838 16:44:20.925857 CH0 RK0: MR19=404, MR18=804
2839 16:44:20.932927 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2840 16:44:20.933501
2841 16:44:20.935984 ----->DramcWriteLeveling(PI) begin...
2842 16:44:20.936459 ==
2843 16:44:20.940098 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 16:44:20.942635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 16:44:20.946483 ==
2846 16:44:20.947045 Write leveling (Byte 0): 34 => 34
2847 16:44:20.949596 Write leveling (Byte 1): 29 => 29
2848 16:44:20.952446 DramcWriteLeveling(PI) end<-----
2849 16:44:20.952915
2850 16:44:20.953284 ==
2851 16:44:20.956804 Dram Type= 6, Freq= 0, CH_0, rank 1
2852 16:44:20.963196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2853 16:44:20.963832 ==
2854 16:44:20.964208 [Gating] SW mode calibration
2855 16:44:20.972171 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2856 16:44:20.975780 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2857 16:44:20.982222 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2858 16:44:20.985640 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 16:44:20.990036 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 16:44:20.995624 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 16:44:20.999037 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 16:44:21.002799 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 16:44:21.005808 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2864 16:44:21.012034 0 15 28 | B1->B0 | 2d2d 2a2a | 0 0 | (0 1) (0 1)
2865 16:44:21.015662 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 16:44:21.018986 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 16:44:21.025416 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 16:44:21.029011 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 16:44:21.032704 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 16:44:21.038641 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 16:44:21.041718 1 0 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
2872 16:44:21.045192 1 0 28 | B1->B0 | 3737 3d3d | 1 0 | (0 0) (0 0)
2873 16:44:21.051939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 16:44:21.055499 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 16:44:21.058877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 16:44:21.065542 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 16:44:21.069079 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 16:44:21.072334 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 16:44:21.079069 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2880 16:44:21.081864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 16:44:21.085610 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2882 16:44:21.092235 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 16:44:21.095194 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 16:44:21.099200 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 16:44:21.105245 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 16:44:21.108731 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 16:44:21.112061 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 16:44:21.118721 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 16:44:21.121970 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 16:44:21.125597 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 16:44:21.131694 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 16:44:21.135257 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 16:44:21.138326 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 16:44:21.141617 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 16:44:21.148342 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2896 16:44:21.151998 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2897 16:44:21.154873 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 16:44:21.158229 Total UI for P1: 0, mck2ui 16
2899 16:44:21.161974 best dqsien dly found for B0: ( 1, 3, 26)
2900 16:44:21.165683 Total UI for P1: 0, mck2ui 16
2901 16:44:21.168350 best dqsien dly found for B1: ( 1, 3, 28)
2902 16:44:21.171410 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2903 16:44:21.178145 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2904 16:44:21.178660
2905 16:44:21.181736 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2906 16:44:21.184878 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2907 16:44:21.188454 [Gating] SW calibration Done
2908 16:44:21.188919 ==
2909 16:44:21.192166 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 16:44:21.195003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 16:44:21.195584 ==
2912 16:44:21.196007 RX Vref Scan: 0
2913 16:44:21.199090
2914 16:44:21.199663 RX Vref 0 -> 0, step: 1
2915 16:44:21.200038
2916 16:44:21.201429 RX Delay -40 -> 252, step: 8
2917 16:44:21.205011 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2918 16:44:21.208158 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2919 16:44:21.215132 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2920 16:44:21.218462 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2921 16:44:21.221610 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2922 16:44:21.224594 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2923 16:44:21.227786 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2924 16:44:21.234474 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2925 16:44:21.238502 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2926 16:44:21.241161 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2927 16:44:21.244721 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2928 16:44:21.247808 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2929 16:44:21.254519 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2930 16:44:21.257794 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2931 16:44:21.261120 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2932 16:44:21.264242 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2933 16:44:21.264708 ==
2934 16:44:21.268036 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 16:44:21.274138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 16:44:21.274774 ==
2937 16:44:21.275155 DQS Delay:
2938 16:44:21.277687 DQS0 = 0, DQS1 = 0
2939 16:44:21.278258 DQM Delay:
2940 16:44:21.281527 DQM0 = 120, DQM1 = 108
2941 16:44:21.282098 DQ Delay:
2942 16:44:21.284095 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2943 16:44:21.287653 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2944 16:44:21.291717 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2945 16:44:21.294434 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2946 16:44:21.295004
2947 16:44:21.295374
2948 16:44:21.295720 ==
2949 16:44:21.297471 Dram Type= 6, Freq= 0, CH_0, rank 1
2950 16:44:21.301229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2951 16:44:21.304428 ==
2952 16:44:21.305004
2953 16:44:21.305372
2954 16:44:21.305713 TX Vref Scan disable
2955 16:44:21.307653 == TX Byte 0 ==
2956 16:44:21.311198 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2957 16:44:21.314495 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2958 16:44:21.317758 == TX Byte 1 ==
2959 16:44:21.321263 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2960 16:44:21.324297 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2961 16:44:21.327405 ==
2962 16:44:21.331070 Dram Type= 6, Freq= 0, CH_0, rank 1
2963 16:44:21.334474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2964 16:44:21.335043 ==
2965 16:44:21.345666 TX Vref=22, minBit 3, minWin=23, winSum=399
2966 16:44:21.348670 TX Vref=24, minBit 3, minWin=24, winSum=401
2967 16:44:21.353036 TX Vref=26, minBit 0, minWin=25, winSum=410
2968 16:44:21.355915 TX Vref=28, minBit 1, minWin=25, winSum=415
2969 16:44:21.358794 TX Vref=30, minBit 1, minWin=25, winSum=417
2970 16:44:21.362225 TX Vref=32, minBit 2, minWin=25, winSum=418
2971 16:44:21.368730 [TxChooseVref] Worse bit 2, Min win 25, Win sum 418, Final Vref 32
2972 16:44:21.369308
2973 16:44:21.372531 Final TX Range 1 Vref 32
2974 16:44:21.373102
2975 16:44:21.373469 ==
2976 16:44:21.375353 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 16:44:21.379127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 16:44:21.379597 ==
2979 16:44:21.379964
2980 16:44:21.381936
2981 16:44:21.382437 TX Vref Scan disable
2982 16:44:21.385212 == TX Byte 0 ==
2983 16:44:21.388534 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2984 16:44:21.392261 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2985 16:44:21.395320 == TX Byte 1 ==
2986 16:44:21.398721 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2987 16:44:21.402471 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2988 16:44:21.405412
2989 16:44:21.405981 [DATLAT]
2990 16:44:21.406387 Freq=1200, CH0 RK1
2991 16:44:21.406746
2992 16:44:21.408638 DATLAT Default: 0xd
2993 16:44:21.409207 0, 0xFFFF, sum = 0
2994 16:44:21.411584 1, 0xFFFF, sum = 0
2995 16:44:21.412056 2, 0xFFFF, sum = 0
2996 16:44:21.415220 3, 0xFFFF, sum = 0
2997 16:44:21.418753 4, 0xFFFF, sum = 0
2998 16:44:21.419330 5, 0xFFFF, sum = 0
2999 16:44:21.421958 6, 0xFFFF, sum = 0
3000 16:44:21.422577 7, 0xFFFF, sum = 0
3001 16:44:21.425422 8, 0xFFFF, sum = 0
3002 16:44:21.426064 9, 0xFFFF, sum = 0
3003 16:44:21.428314 10, 0xFFFF, sum = 0
3004 16:44:21.428788 11, 0xFFFF, sum = 0
3005 16:44:21.431913 12, 0x0, sum = 1
3006 16:44:21.432488 13, 0x0, sum = 2
3007 16:44:21.435216 14, 0x0, sum = 3
3008 16:44:21.435793 15, 0x0, sum = 4
3009 16:44:21.438483 best_step = 13
3010 16:44:21.439044
3011 16:44:21.439413 ==
3012 16:44:21.441729 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 16:44:21.445357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 16:44:21.445928 ==
3015 16:44:21.446301 RX Vref Scan: 0
3016 16:44:21.446697
3017 16:44:21.448403 RX Vref 0 -> 0, step: 1
3018 16:44:21.448871
3019 16:44:21.452459 RX Delay -21 -> 252, step: 4
3020 16:44:21.455227 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3021 16:44:21.461722 iDelay=199, Bit 1, Center 122 (55 ~ 190) 136
3022 16:44:21.465132 iDelay=199, Bit 2, Center 118 (51 ~ 186) 136
3023 16:44:21.468217 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3024 16:44:21.471231 iDelay=199, Bit 4, Center 122 (55 ~ 190) 136
3025 16:44:21.474859 iDelay=199, Bit 5, Center 114 (51 ~ 178) 128
3026 16:44:21.481493 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3027 16:44:21.484530 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3028 16:44:21.488207 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3029 16:44:21.491170 iDelay=199, Bit 9, Center 94 (31 ~ 158) 128
3030 16:44:21.494725 iDelay=199, Bit 10, Center 110 (47 ~ 174) 128
3031 16:44:21.502005 iDelay=199, Bit 11, Center 106 (43 ~ 170) 128
3032 16:44:21.504449 iDelay=199, Bit 12, Center 112 (47 ~ 178) 132
3033 16:44:21.507887 iDelay=199, Bit 13, Center 110 (47 ~ 174) 128
3034 16:44:21.511598 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3035 16:44:21.518185 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
3036 16:44:21.518804 ==
3037 16:44:21.521632 Dram Type= 6, Freq= 0, CH_0, rank 1
3038 16:44:21.524774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3039 16:44:21.525343 ==
3040 16:44:21.525719 DQS Delay:
3041 16:44:21.527813 DQS0 = 0, DQS1 = 0
3042 16:44:21.528281 DQM Delay:
3043 16:44:21.531246 DQM0 = 119, DQM1 = 107
3044 16:44:21.531810 DQ Delay:
3045 16:44:21.534463 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =112
3046 16:44:21.537982 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =124
3047 16:44:21.541058 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3048 16:44:21.544781 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3049 16:44:21.545349
3050 16:44:21.545722
3051 16:44:21.554514 [DQSOSCAuto] RK1, (LSB)MR18= 0xff7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3052 16:44:21.557680 CH0 RK1: MR19=403, MR18=FF7
3053 16:44:21.561164 CH0_RK1: MR19=0x403, MR18=0xFF7, DQSOSC=404, MR23=63, INC=40, DEC=26
3054 16:44:21.564353 [RxdqsGatingPostProcess] freq 1200
3055 16:44:21.571240 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3056 16:44:21.574094 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 16:44:21.577433 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 16:44:21.581524 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 16:44:21.584208 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 16:44:21.587799 best DQS0 dly(2T, 0.5T) = (0, 11)
3061 16:44:21.591552 best DQS1 dly(2T, 0.5T) = (0, 11)
3062 16:44:21.594111 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3063 16:44:21.594621 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3064 16:44:21.597285 Pre-setting of DQS Precalculation
3065 16:44:21.604038 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3066 16:44:21.604512 ==
3067 16:44:21.608006 Dram Type= 6, Freq= 0, CH_1, rank 0
3068 16:44:21.610908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 16:44:21.611388 ==
3070 16:44:21.617947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3071 16:44:21.624331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3072 16:44:21.631864 [CA 0] Center 37 (7~68) winsize 62
3073 16:44:21.634705 [CA 1] Center 37 (7~68) winsize 62
3074 16:44:21.638328 [CA 2] Center 35 (5~65) winsize 61
3075 16:44:21.641676 [CA 3] Center 34 (3~65) winsize 63
3076 16:44:21.644467 [CA 4] Center 34 (4~64) winsize 61
3077 16:44:21.648274 [CA 5] Center 33 (3~64) winsize 62
3078 16:44:21.648841
3079 16:44:21.651124 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3080 16:44:21.651596
3081 16:44:21.654855 [CATrainingPosCal] consider 1 rank data
3082 16:44:21.657979 u2DelayCellTimex100 = 270/100 ps
3083 16:44:21.661299 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3084 16:44:21.664847 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3085 16:44:21.671526 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3086 16:44:21.674480 CA3 delay=34 (3~65),Diff = 1 PI (4 cell)
3087 16:44:21.677603 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3088 16:44:21.681486 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 16:44:21.682054
3090 16:44:21.684354 CA PerBit enable=1, Macro0, CA PI delay=33
3091 16:44:21.684827
3092 16:44:21.687673 [CBTSetCACLKResult] CA Dly = 33
3093 16:44:21.688142 CS Dly: 5 (0~36)
3094 16:44:21.691835 ==
3095 16:44:21.692400 Dram Type= 6, Freq= 0, CH_1, rank 1
3096 16:44:21.697636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3097 16:44:21.698113 ==
3098 16:44:21.701292 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3099 16:44:21.707623 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3100 16:44:21.717291 [CA 0] Center 38 (8~68) winsize 61
3101 16:44:21.720266 [CA 1] Center 38 (7~69) winsize 63
3102 16:44:21.724031 [CA 2] Center 35 (5~66) winsize 62
3103 16:44:21.726997 [CA 3] Center 35 (5~65) winsize 61
3104 16:44:21.730241 [CA 4] Center 34 (4~65) winsize 62
3105 16:44:21.733895 [CA 5] Center 34 (4~64) winsize 61
3106 16:44:21.734508
3107 16:44:21.737159 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3108 16:44:21.737726
3109 16:44:21.739952 [CATrainingPosCal] consider 2 rank data
3110 16:44:21.744013 u2DelayCellTimex100 = 270/100 ps
3111 16:44:21.746866 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3112 16:44:21.753610 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3113 16:44:21.756727 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3114 16:44:21.760301 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3115 16:44:21.763272 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3116 16:44:21.767009 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3117 16:44:21.767579
3118 16:44:21.770145 CA PerBit enable=1, Macro0, CA PI delay=34
3119 16:44:21.770652
3120 16:44:21.773085 [CBTSetCACLKResult] CA Dly = 34
3121 16:44:21.773558 CS Dly: 6 (0~39)
3122 16:44:21.773933
3123 16:44:21.777220 ----->DramcWriteLeveling(PI) begin...
3124 16:44:21.780348 ==
3125 16:44:21.783962 Dram Type= 6, Freq= 0, CH_1, rank 0
3126 16:44:21.786590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3127 16:44:21.787062 ==
3128 16:44:21.789917 Write leveling (Byte 0): 26 => 26
3129 16:44:21.793860 Write leveling (Byte 1): 28 => 28
3130 16:44:21.797202 DramcWriteLeveling(PI) end<-----
3131 16:44:21.797696
3132 16:44:21.798066 ==
3133 16:44:21.800410 Dram Type= 6, Freq= 0, CH_1, rank 0
3134 16:44:21.803229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 16:44:21.803709 ==
3136 16:44:21.806554 [Gating] SW mode calibration
3137 16:44:21.813485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3138 16:44:21.820295 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3139 16:44:21.823687 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 16:44:21.826895 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 16:44:21.830713 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 16:44:21.837045 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 16:44:21.840284 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 16:44:21.843742 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3145 16:44:21.850209 0 15 24 | B1->B0 | 2f2f 2b2b | 1 1 | (1 0) (1 0)
3146 16:44:21.853645 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3147 16:44:21.856809 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 16:44:21.863827 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 16:44:21.866333 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 16:44:21.870099 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 16:44:21.876509 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 16:44:21.880269 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 16:44:21.883326 1 0 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3154 16:44:21.890094 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 16:44:21.893138 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 16:44:21.896922 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 16:44:21.903181 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 16:44:21.906706 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 16:44:21.909451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 16:44:21.916572 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3161 16:44:21.919695 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3162 16:44:21.923012 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3163 16:44:21.929905 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 16:44:21.933246 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 16:44:21.936306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 16:44:21.943265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 16:44:21.946472 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 16:44:21.949786 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 16:44:21.956425 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 16:44:21.959550 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 16:44:21.963192 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 16:44:21.969659 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 16:44:21.972780 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 16:44:21.975729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 16:44:21.983245 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 16:44:21.985933 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3177 16:44:21.989051 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3178 16:44:21.992615 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3179 16:44:21.996018 Total UI for P1: 0, mck2ui 16
3180 16:44:21.999652 best dqsien dly found for B0: ( 1, 3, 22)
3181 16:44:22.005905 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3182 16:44:22.009026 Total UI for P1: 0, mck2ui 16
3183 16:44:22.012800 best dqsien dly found for B1: ( 1, 3, 26)
3184 16:44:22.015557 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3185 16:44:22.020432 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3186 16:44:22.020999
3187 16:44:22.022182 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3188 16:44:22.025973 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3189 16:44:22.029064 [Gating] SW calibration Done
3190 16:44:22.029536 ==
3191 16:44:22.032757 Dram Type= 6, Freq= 0, CH_1, rank 0
3192 16:44:22.035877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 16:44:22.036444 ==
3194 16:44:22.039454 RX Vref Scan: 0
3195 16:44:22.040018
3196 16:44:22.040394 RX Vref 0 -> 0, step: 1
3197 16:44:22.042616
3198 16:44:22.043181 RX Delay -40 -> 252, step: 8
3199 16:44:22.049163 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3200 16:44:22.052462 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3201 16:44:22.056355 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3202 16:44:22.059522 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3203 16:44:22.062676 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3204 16:44:22.069179 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3205 16:44:22.072388 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3206 16:44:22.075573 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3207 16:44:22.079118 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3208 16:44:22.082179 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3209 16:44:22.085666 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3210 16:44:22.092118 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3211 16:44:22.095769 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3212 16:44:22.098800 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3213 16:44:22.102014 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3214 16:44:22.109007 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3215 16:44:22.109575 ==
3216 16:44:22.112756 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 16:44:22.115646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 16:44:22.116123 ==
3219 16:44:22.116496 DQS Delay:
3220 16:44:22.118974 DQS0 = 0, DQS1 = 0
3221 16:44:22.119445 DQM Delay:
3222 16:44:22.122275 DQM0 = 119, DQM1 = 112
3223 16:44:22.122775 DQ Delay:
3224 16:44:22.125718 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3225 16:44:22.128868 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3226 16:44:22.133173 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3227 16:44:22.135258 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3228 16:44:22.135731
3229 16:44:22.136099
3230 16:44:22.136444 ==
3231 16:44:22.138951 Dram Type= 6, Freq= 0, CH_1, rank 0
3232 16:44:22.145890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3233 16:44:22.146467 ==
3234 16:44:22.146843
3235 16:44:22.147189
3236 16:44:22.148795 TX Vref Scan disable
3237 16:44:22.149363 == TX Byte 0 ==
3238 16:44:22.152460 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3239 16:44:22.159187 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3240 16:44:22.159750 == TX Byte 1 ==
3241 16:44:22.161929 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 16:44:22.168877 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 16:44:22.169448 ==
3244 16:44:22.171862 Dram Type= 6, Freq= 0, CH_1, rank 0
3245 16:44:22.175225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3246 16:44:22.175814 ==
3247 16:44:22.187053 TX Vref=22, minBit 1, minWin=24, winSum=405
3248 16:44:22.190128 TX Vref=24, minBit 11, minWin=24, winSum=406
3249 16:44:22.193682 TX Vref=26, minBit 3, minWin=25, winSum=411
3250 16:44:22.197070 TX Vref=28, minBit 3, minWin=25, winSum=417
3251 16:44:22.200282 TX Vref=30, minBit 10, minWin=25, winSum=423
3252 16:44:22.207139 TX Vref=32, minBit 10, minWin=25, winSum=423
3253 16:44:22.210413 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 30
3254 16:44:22.210978
3255 16:44:22.213607 Final TX Range 1 Vref 30
3256 16:44:22.214258
3257 16:44:22.214696 ==
3258 16:44:22.216954 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 16:44:22.220218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 16:44:22.223983 ==
3261 16:44:22.224550
3262 16:44:22.224924
3263 16:44:22.225268 TX Vref Scan disable
3264 16:44:22.226561 == TX Byte 0 ==
3265 16:44:22.229925 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3266 16:44:22.233818 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3267 16:44:22.236701 == TX Byte 1 ==
3268 16:44:22.240160 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3269 16:44:22.246731 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3270 16:44:22.247297
3271 16:44:22.247674 [DATLAT]
3272 16:44:22.248021 Freq=1200, CH1 RK0
3273 16:44:22.248356
3274 16:44:22.249699 DATLAT Default: 0xd
3275 16:44:22.250160 0, 0xFFFF, sum = 0
3276 16:44:22.253146 1, 0xFFFF, sum = 0
3277 16:44:22.256734 2, 0xFFFF, sum = 0
3278 16:44:22.257304 3, 0xFFFF, sum = 0
3279 16:44:22.260358 4, 0xFFFF, sum = 0
3280 16:44:22.260929 5, 0xFFFF, sum = 0
3281 16:44:22.263726 6, 0xFFFF, sum = 0
3282 16:44:22.264297 7, 0xFFFF, sum = 0
3283 16:44:22.267134 8, 0xFFFF, sum = 0
3284 16:44:22.267706 9, 0xFFFF, sum = 0
3285 16:44:22.269975 10, 0xFFFF, sum = 0
3286 16:44:22.270495 11, 0xFFFF, sum = 0
3287 16:44:22.273367 12, 0x0, sum = 1
3288 16:44:22.273939 13, 0x0, sum = 2
3289 16:44:22.276332 14, 0x0, sum = 3
3290 16:44:22.276804 15, 0x0, sum = 4
3291 16:44:22.279898 best_step = 13
3292 16:44:22.280462
3293 16:44:22.280831 ==
3294 16:44:22.283210 Dram Type= 6, Freq= 0, CH_1, rank 0
3295 16:44:22.286564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3296 16:44:22.287034 ==
3297 16:44:22.287418 RX Vref Scan: 1
3298 16:44:22.287762
3299 16:44:22.289647 Set Vref Range= 32 -> 127
3300 16:44:22.290375
3301 16:44:22.293605 RX Vref 32 -> 127, step: 1
3302 16:44:22.294173
3303 16:44:22.296972 RX Delay -13 -> 252, step: 4
3304 16:44:22.297535
3305 16:44:22.300146 Set Vref, RX VrefLevel [Byte0]: 32
3306 16:44:22.303326 [Byte1]: 32
3307 16:44:22.303965
3308 16:44:22.306659 Set Vref, RX VrefLevel [Byte0]: 33
3309 16:44:22.310863 [Byte1]: 33
3310 16:44:22.314105
3311 16:44:22.314594 Set Vref, RX VrefLevel [Byte0]: 34
3312 16:44:22.316474 [Byte1]: 34
3313 16:44:22.321074
3314 16:44:22.321521 Set Vref, RX VrefLevel [Byte0]: 35
3315 16:44:22.324516 [Byte1]: 35
3316 16:44:22.328883
3317 16:44:22.329399 Set Vref, RX VrefLevel [Byte0]: 36
3318 16:44:22.332480 [Byte1]: 36
3319 16:44:22.336906
3320 16:44:22.337462 Set Vref, RX VrefLevel [Byte0]: 37
3321 16:44:22.339957 [Byte1]: 37
3322 16:44:22.344824
3323 16:44:22.345398 Set Vref, RX VrefLevel [Byte0]: 38
3324 16:44:22.347978 [Byte1]: 38
3325 16:44:22.352454
3326 16:44:22.352909 Set Vref, RX VrefLevel [Byte0]: 39
3327 16:44:22.355710 [Byte1]: 39
3328 16:44:22.360492
3329 16:44:22.361052 Set Vref, RX VrefLevel [Byte0]: 40
3330 16:44:22.363827 [Byte1]: 40
3331 16:44:22.368358
3332 16:44:22.368924 Set Vref, RX VrefLevel [Byte0]: 41
3333 16:44:22.371721 [Byte1]: 41
3334 16:44:22.376138
3335 16:44:22.376833 Set Vref, RX VrefLevel [Byte0]: 42
3336 16:44:22.379607 [Byte1]: 42
3337 16:44:22.384422
3338 16:44:22.384992 Set Vref, RX VrefLevel [Byte0]: 43
3339 16:44:22.387360 [Byte1]: 43
3340 16:44:22.391929
3341 16:44:22.392384 Set Vref, RX VrefLevel [Byte0]: 44
3342 16:44:22.395586 [Byte1]: 44
3343 16:44:22.399953
3344 16:44:22.400501 Set Vref, RX VrefLevel [Byte0]: 45
3345 16:44:22.403274 [Byte1]: 45
3346 16:44:22.407821
3347 16:44:22.408277 Set Vref, RX VrefLevel [Byte0]: 46
3348 16:44:22.411372 [Byte1]: 46
3349 16:44:22.415599
3350 16:44:22.416154 Set Vref, RX VrefLevel [Byte0]: 47
3351 16:44:22.419742 [Byte1]: 47
3352 16:44:22.423636
3353 16:44:22.424185 Set Vref, RX VrefLevel [Byte0]: 48
3354 16:44:22.426968 [Byte1]: 48
3355 16:44:22.431517
3356 16:44:22.432064 Set Vref, RX VrefLevel [Byte0]: 49
3357 16:44:22.434864 [Byte1]: 49
3358 16:44:22.439464
3359 16:44:22.440006 Set Vref, RX VrefLevel [Byte0]: 50
3360 16:44:22.442487 [Byte1]: 50
3361 16:44:22.447344
3362 16:44:22.447822 Set Vref, RX VrefLevel [Byte0]: 51
3363 16:44:22.450544 [Byte1]: 51
3364 16:44:22.455423
3365 16:44:22.455974 Set Vref, RX VrefLevel [Byte0]: 52
3366 16:44:22.458389 [Byte1]: 52
3367 16:44:22.463257
3368 16:44:22.466526 Set Vref, RX VrefLevel [Byte0]: 53
3369 16:44:22.467080 [Byte1]: 53
3370 16:44:22.471109
3371 16:44:22.471656 Set Vref, RX VrefLevel [Byte0]: 54
3372 16:44:22.474298 [Byte1]: 54
3373 16:44:22.479261
3374 16:44:22.479716 Set Vref, RX VrefLevel [Byte0]: 55
3375 16:44:22.482644 [Byte1]: 55
3376 16:44:22.487705
3377 16:44:22.488252 Set Vref, RX VrefLevel [Byte0]: 56
3378 16:44:22.490182 [Byte1]: 56
3379 16:44:22.494716
3380 16:44:22.495263 Set Vref, RX VrefLevel [Byte0]: 57
3381 16:44:22.498526 [Byte1]: 57
3382 16:44:22.502677
3383 16:44:22.503223 Set Vref, RX VrefLevel [Byte0]: 58
3384 16:44:22.505746 [Byte1]: 58
3385 16:44:22.510596
3386 16:44:22.511158 Set Vref, RX VrefLevel [Byte0]: 59
3387 16:44:22.513898 [Byte1]: 59
3388 16:44:22.518320
3389 16:44:22.518907 Set Vref, RX VrefLevel [Byte0]: 60
3390 16:44:22.522160 [Byte1]: 60
3391 16:44:22.526211
3392 16:44:22.526824 Set Vref, RX VrefLevel [Byte0]: 61
3393 16:44:22.532731 [Byte1]: 61
3394 16:44:22.533283
3395 16:44:22.535736 Set Vref, RX VrefLevel [Byte0]: 62
3396 16:44:22.539046 [Byte1]: 62
3397 16:44:22.539498
3398 16:44:22.542722 Set Vref, RX VrefLevel [Byte0]: 63
3399 16:44:22.545708 [Byte1]: 63
3400 16:44:22.549806
3401 16:44:22.550322 Set Vref, RX VrefLevel [Byte0]: 64
3402 16:44:22.553379 [Byte1]: 64
3403 16:44:22.557632
3404 16:44:22.558111 Set Vref, RX VrefLevel [Byte0]: 65
3405 16:44:22.561814 [Byte1]: 65
3406 16:44:22.565472
3407 16:44:22.566004 Set Vref, RX VrefLevel [Byte0]: 66
3408 16:44:22.568941 [Byte1]: 66
3409 16:44:22.573578
3410 16:44:22.574140 Set Vref, RX VrefLevel [Byte0]: 67
3411 16:44:22.576942 [Byte1]: 67
3412 16:44:22.581667
3413 16:44:22.582227 Final RX Vref Byte 0 = 52 to rank0
3414 16:44:22.584713 Final RX Vref Byte 1 = 52 to rank0
3415 16:44:22.588076 Final RX Vref Byte 0 = 52 to rank1
3416 16:44:22.591554 Final RX Vref Byte 1 = 52 to rank1==
3417 16:44:22.594517 Dram Type= 6, Freq= 0, CH_1, rank 0
3418 16:44:22.601662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 16:44:22.602232 ==
3420 16:44:22.602654 DQS Delay:
3421 16:44:22.602998 DQS0 = 0, DQS1 = 0
3422 16:44:22.604988 DQM Delay:
3423 16:44:22.605446 DQM0 = 119, DQM1 = 112
3424 16:44:22.607950 DQ Delay:
3425 16:44:22.611727 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3426 16:44:22.615216 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3427 16:44:22.618084 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =106
3428 16:44:22.621600 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =118
3429 16:44:22.622166
3430 16:44:22.622592
3431 16:44:22.627964 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3432 16:44:22.631419 CH1 RK0: MR19=404, MR18=114
3433 16:44:22.637779 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3434 16:44:22.638333
3435 16:44:22.641192 ----->DramcWriteLeveling(PI) begin...
3436 16:44:22.641767 ==
3437 16:44:22.644756 Dram Type= 6, Freq= 0, CH_1, rank 1
3438 16:44:22.648114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3439 16:44:22.650905 ==
3440 16:44:22.651392 Write leveling (Byte 0): 24 => 24
3441 16:44:22.654562 Write leveling (Byte 1): 29 => 29
3442 16:44:22.658012 DramcWriteLeveling(PI) end<-----
3443 16:44:22.658612
3444 16:44:22.659023 ==
3445 16:44:22.661009 Dram Type= 6, Freq= 0, CH_1, rank 1
3446 16:44:22.667748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3447 16:44:22.668309 ==
3448 16:44:22.668679 [Gating] SW mode calibration
3449 16:44:22.677589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3450 16:44:22.681178 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3451 16:44:22.687717 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 16:44:22.691338 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 16:44:22.694419 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 16:44:22.701716 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 16:44:22.704633 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3456 16:44:22.708127 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3457 16:44:22.710900 0 15 24 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
3458 16:44:22.717456 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3459 16:44:22.721036 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 16:44:22.724103 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 16:44:22.730711 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 16:44:22.734406 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3463 16:44:22.737738 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3464 16:44:22.744327 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3465 16:44:22.747238 1 0 24 | B1->B0 | 3c3c 2424 | 0 0 | (0 0) (0 0)
3466 16:44:22.750882 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3467 16:44:22.757188 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 16:44:22.760895 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 16:44:22.763737 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 16:44:22.771113 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3471 16:44:22.774121 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3472 16:44:22.777313 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 16:44:22.784208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3474 16:44:22.787060 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3475 16:44:22.790459 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 16:44:22.797593 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 16:44:22.800048 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 16:44:22.803738 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 16:44:22.810694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 16:44:22.813760 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 16:44:22.817777 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 16:44:22.823764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 16:44:22.826988 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 16:44:22.830511 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 16:44:22.836940 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 16:44:22.840416 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 16:44:22.843674 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 16:44:22.850293 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3489 16:44:22.853739 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3490 16:44:22.856666 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3491 16:44:22.863369 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 16:44:22.863956 Total UI for P1: 0, mck2ui 16
3493 16:44:22.869865 best dqsien dly found for B0: ( 1, 3, 26)
3494 16:44:22.870469 Total UI for P1: 0, mck2ui 16
3495 16:44:22.873404 best dqsien dly found for B1: ( 1, 3, 24)
3496 16:44:22.880196 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3497 16:44:22.883730 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3498 16:44:22.884310
3499 16:44:22.886283 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3500 16:44:22.890174 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3501 16:44:22.892911 [Gating] SW calibration Done
3502 16:44:22.893387 ==
3503 16:44:22.897139 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 16:44:22.899484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 16:44:22.900051 ==
3506 16:44:22.903914 RX Vref Scan: 0
3507 16:44:22.904479
3508 16:44:22.904846 RX Vref 0 -> 0, step: 1
3509 16:44:22.905190
3510 16:44:22.906100 RX Delay -40 -> 252, step: 8
3511 16:44:22.910268 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3512 16:44:22.915947 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3513 16:44:22.920546 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3514 16:44:22.923050 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3515 16:44:22.926587 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3516 16:44:22.929817 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3517 16:44:22.936362 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3518 16:44:22.939656 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3519 16:44:22.942722 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3520 16:44:22.945988 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3521 16:44:22.949601 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3522 16:44:22.955735 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3523 16:44:22.959405 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3524 16:44:22.962633 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3525 16:44:22.965493 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3526 16:44:22.972993 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3527 16:44:22.973550 ==
3528 16:44:22.975982 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 16:44:22.978797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 16:44:22.979332 ==
3531 16:44:22.979706 DQS Delay:
3532 16:44:22.982792 DQS0 = 0, DQS1 = 0
3533 16:44:22.983255 DQM Delay:
3534 16:44:22.985481 DQM0 = 120, DQM1 = 112
3535 16:44:22.986038 DQ Delay:
3536 16:44:22.988692 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3537 16:44:22.992205 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3538 16:44:22.995671 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3539 16:44:22.999427 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3540 16:44:22.999890
3541 16:44:23.000365
3542 16:44:23.001590 ==
3543 16:44:23.002053 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 16:44:23.008702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 16:44:23.009271 ==
3546 16:44:23.009638
3547 16:44:23.009974
3548 16:44:23.012190 TX Vref Scan disable
3549 16:44:23.012752 == TX Byte 0 ==
3550 16:44:23.015127 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3551 16:44:23.022122 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3552 16:44:23.022734 == TX Byte 1 ==
3553 16:44:23.025172 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3554 16:44:23.032035 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3555 16:44:23.032598 ==
3556 16:44:23.035274 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 16:44:23.038704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 16:44:23.039271 ==
3559 16:44:23.050860 TX Vref=22, minBit 3, minWin=25, winSum=415
3560 16:44:23.053860 TX Vref=24, minBit 3, minWin=25, winSum=417
3561 16:44:23.057218 TX Vref=26, minBit 1, minWin=25, winSum=421
3562 16:44:23.060847 TX Vref=28, minBit 1, minWin=26, winSum=429
3563 16:44:23.063620 TX Vref=30, minBit 1, minWin=26, winSum=429
3564 16:44:23.070517 TX Vref=32, minBit 0, minWin=26, winSum=427
3565 16:44:23.074622 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3566 16:44:23.075247
3567 16:44:23.077528 Final TX Range 1 Vref 28
3568 16:44:23.078120
3569 16:44:23.078543 ==
3570 16:44:23.080313 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 16:44:23.083734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 16:44:23.086933 ==
3573 16:44:23.087461
3574 16:44:23.087825
3575 16:44:23.088165 TX Vref Scan disable
3576 16:44:23.090019 == TX Byte 0 ==
3577 16:44:23.093345 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3578 16:44:23.096939 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3579 16:44:23.100230 == TX Byte 1 ==
3580 16:44:23.103462 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3581 16:44:23.110465 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3582 16:44:23.111026
3583 16:44:23.111391 [DATLAT]
3584 16:44:23.111728 Freq=1200, CH1 RK1
3585 16:44:23.112052
3586 16:44:23.113290 DATLAT Default: 0xd
3587 16:44:23.113750 0, 0xFFFF, sum = 0
3588 16:44:23.116864 1, 0xFFFF, sum = 0
3589 16:44:23.120179 2, 0xFFFF, sum = 0
3590 16:44:23.120750 3, 0xFFFF, sum = 0
3591 16:44:23.123729 4, 0xFFFF, sum = 0
3592 16:44:23.124305 5, 0xFFFF, sum = 0
3593 16:44:23.126718 6, 0xFFFF, sum = 0
3594 16:44:23.127187 7, 0xFFFF, sum = 0
3595 16:44:23.129856 8, 0xFFFF, sum = 0
3596 16:44:23.130494 9, 0xFFFF, sum = 0
3597 16:44:23.133305 10, 0xFFFF, sum = 0
3598 16:44:23.133881 11, 0xFFFF, sum = 0
3599 16:44:23.136857 12, 0x0, sum = 1
3600 16:44:23.137428 13, 0x0, sum = 2
3601 16:44:23.140180 14, 0x0, sum = 3
3602 16:44:23.140756 15, 0x0, sum = 4
3603 16:44:23.143333 best_step = 13
3604 16:44:23.143894
3605 16:44:23.144262 ==
3606 16:44:23.146695 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 16:44:23.150649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 16:44:23.151218 ==
3609 16:44:23.151587 RX Vref Scan: 0
3610 16:44:23.152911
3611 16:44:23.153373 RX Vref 0 -> 0, step: 1
3612 16:44:23.153740
3613 16:44:23.156802 RX Delay -13 -> 252, step: 4
3614 16:44:23.163422 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3615 16:44:23.166748 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3616 16:44:23.169469 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3617 16:44:23.173081 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3618 16:44:23.176495 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3619 16:44:23.179641 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3620 16:44:23.186521 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3621 16:44:23.189378 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3622 16:44:23.192793 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3623 16:44:23.196455 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3624 16:44:23.202807 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3625 16:44:23.205964 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3626 16:44:23.210012 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3627 16:44:23.212825 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3628 16:44:23.216207 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3629 16:44:23.223100 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3630 16:44:23.223662 ==
3631 16:44:23.226806 Dram Type= 6, Freq= 0, CH_1, rank 1
3632 16:44:23.230146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3633 16:44:23.230762 ==
3634 16:44:23.231231 DQS Delay:
3635 16:44:23.232318 DQS0 = 0, DQS1 = 0
3636 16:44:23.232777 DQM Delay:
3637 16:44:23.236342 DQM0 = 119, DQM1 = 113
3638 16:44:23.236912 DQ Delay:
3639 16:44:23.239198 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3640 16:44:23.242880 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3641 16:44:23.245647 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =108
3642 16:44:23.248931 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3643 16:44:23.249496
3644 16:44:23.252491
3645 16:44:23.259042 [DQSOSCAuto] RK1, (LSB)MR18= 0xbef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3646 16:44:23.262915 CH1 RK1: MR19=403, MR18=BEF
3647 16:44:23.269493 CH1_RK1: MR19=0x403, MR18=0xBEF, DQSOSC=405, MR23=63, INC=39, DEC=26
3648 16:44:23.270061 [RxdqsGatingPostProcess] freq 1200
3649 16:44:23.275328 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3650 16:44:23.279139 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 16:44:23.281773 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 16:44:23.285361 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 16:44:23.288747 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 16:44:23.292020 best DQS0 dly(2T, 0.5T) = (0, 11)
3655 16:44:23.295901 best DQS1 dly(2T, 0.5T) = (0, 11)
3656 16:44:23.298689 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3657 16:44:23.301675 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3658 16:44:23.305207 Pre-setting of DQS Precalculation
3659 16:44:23.308456 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3660 16:44:23.315529 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3661 16:44:23.325115 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3662 16:44:23.325697
3663 16:44:23.326069
3664 16:44:23.328318 [Calibration Summary] 2400 Mbps
3665 16:44:23.328892 CH 0, Rank 0
3666 16:44:23.331510 SW Impedance : PASS
3667 16:44:23.331984 DUTY Scan : NO K
3668 16:44:23.334832 ZQ Calibration : PASS
3669 16:44:23.338113 Jitter Meter : NO K
3670 16:44:23.338733 CBT Training : PASS
3671 16:44:23.341539 Write leveling : PASS
3672 16:44:23.345750 RX DQS gating : PASS
3673 16:44:23.346313 RX DQ/DQS(RDDQC) : PASS
3674 16:44:23.348524 TX DQ/DQS : PASS
3675 16:44:23.349089 RX DATLAT : PASS
3676 16:44:23.351486 RX DQ/DQS(Engine): PASS
3677 16:44:23.355122 TX OE : NO K
3678 16:44:23.355687 All Pass.
3679 16:44:23.356061
3680 16:44:23.356406 CH 0, Rank 1
3681 16:44:23.357929 SW Impedance : PASS
3682 16:44:23.362155 DUTY Scan : NO K
3683 16:44:23.362764 ZQ Calibration : PASS
3684 16:44:23.364983 Jitter Meter : NO K
3685 16:44:23.368357 CBT Training : PASS
3686 16:44:23.368916 Write leveling : PASS
3687 16:44:23.371105 RX DQS gating : PASS
3688 16:44:23.374693 RX DQ/DQS(RDDQC) : PASS
3689 16:44:23.375257 TX DQ/DQS : PASS
3690 16:44:23.377876 RX DATLAT : PASS
3691 16:44:23.381297 RX DQ/DQS(Engine): PASS
3692 16:44:23.381891 TX OE : NO K
3693 16:44:23.384250 All Pass.
3694 16:44:23.384718
3695 16:44:23.385087 CH 1, Rank 0
3696 16:44:23.387819 SW Impedance : PASS
3697 16:44:23.388288 DUTY Scan : NO K
3698 16:44:23.390918 ZQ Calibration : PASS
3699 16:44:23.394336 Jitter Meter : NO K
3700 16:44:23.394847 CBT Training : PASS
3701 16:44:23.398160 Write leveling : PASS
3702 16:44:23.401126 RX DQS gating : PASS
3703 16:44:23.401688 RX DQ/DQS(RDDQC) : PASS
3704 16:44:23.404181 TX DQ/DQS : PASS
3705 16:44:23.404650 RX DATLAT : PASS
3706 16:44:23.407803 RX DQ/DQS(Engine): PASS
3707 16:44:23.411021 TX OE : NO K
3708 16:44:23.411492 All Pass.
3709 16:44:23.411858
3710 16:44:23.412202 CH 1, Rank 1
3711 16:44:23.414068 SW Impedance : PASS
3712 16:44:23.418040 DUTY Scan : NO K
3713 16:44:23.418677 ZQ Calibration : PASS
3714 16:44:23.420877 Jitter Meter : NO K
3715 16:44:23.424382 CBT Training : PASS
3716 16:44:23.424943 Write leveling : PASS
3717 16:44:23.428038 RX DQS gating : PASS
3718 16:44:23.431273 RX DQ/DQS(RDDQC) : PASS
3719 16:44:23.431865 TX DQ/DQS : PASS
3720 16:44:23.434078 RX DATLAT : PASS
3721 16:44:23.437612 RX DQ/DQS(Engine): PASS
3722 16:44:23.438079 TX OE : NO K
3723 16:44:23.440761 All Pass.
3724 16:44:23.441317
3725 16:44:23.441687 DramC Write-DBI off
3726 16:44:23.444575 PER_BANK_REFRESH: Hybrid Mode
3727 16:44:23.445139 TX_TRACKING: ON
3728 16:44:23.454641 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3729 16:44:23.457386 [FAST_K] Save calibration result to emmc
3730 16:44:23.460833 dramc_set_vcore_voltage set vcore to 650000
3731 16:44:23.463978 Read voltage for 600, 5
3732 16:44:23.464447 Vio18 = 0
3733 16:44:23.467215 Vcore = 650000
3734 16:44:23.467772 Vdram = 0
3735 16:44:23.468144 Vddq = 0
3736 16:44:23.470913 Vmddr = 0
3737 16:44:23.473998 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3738 16:44:23.480670 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3739 16:44:23.481231 MEM_TYPE=3, freq_sel=19
3740 16:44:23.484021 sv_algorithm_assistance_LP4_1600
3741 16:44:23.490391 ============ PULL DRAM RESETB DOWN ============
3742 16:44:23.493509 ========== PULL DRAM RESETB DOWN end =========
3743 16:44:23.496803 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3744 16:44:23.500433 ===================================
3745 16:44:23.503360 LPDDR4 DRAM CONFIGURATION
3746 16:44:23.507358 ===================================
3747 16:44:23.510190 EX_ROW_EN[0] = 0x0
3748 16:44:23.510729 EX_ROW_EN[1] = 0x0
3749 16:44:23.513391 LP4Y_EN = 0x0
3750 16:44:23.513810 WORK_FSP = 0x0
3751 16:44:23.517226 WL = 0x2
3752 16:44:23.517769 RL = 0x2
3753 16:44:23.520287 BL = 0x2
3754 16:44:23.520708 RPST = 0x0
3755 16:44:23.523375 RD_PRE = 0x0
3756 16:44:23.523886 WR_PRE = 0x1
3757 16:44:23.526324 WR_PST = 0x0
3758 16:44:23.526775 DBI_WR = 0x0
3759 16:44:23.530279 DBI_RD = 0x0
3760 16:44:23.530835 OTF = 0x1
3761 16:44:23.533203 ===================================
3762 16:44:23.536923 ===================================
3763 16:44:23.540201 ANA top config
3764 16:44:23.543016 ===================================
3765 16:44:23.547189 DLL_ASYNC_EN = 0
3766 16:44:23.547708 ALL_SLAVE_EN = 1
3767 16:44:23.549783 NEW_RANK_MODE = 1
3768 16:44:23.553246 DLL_IDLE_MODE = 1
3769 16:44:23.556452 LP45_APHY_COMB_EN = 1
3770 16:44:23.559543 TX_ODT_DIS = 1
3771 16:44:23.560061 NEW_8X_MODE = 1
3772 16:44:23.562938 ===================================
3773 16:44:23.566429 ===================================
3774 16:44:23.569621 data_rate = 1200
3775 16:44:23.573116 CKR = 1
3776 16:44:23.576087 DQ_P2S_RATIO = 8
3777 16:44:23.580892 ===================================
3778 16:44:23.582660 CA_P2S_RATIO = 8
3779 16:44:23.586051 DQ_CA_OPEN = 0
3780 16:44:23.586599 DQ_SEMI_OPEN = 0
3781 16:44:23.589567 CA_SEMI_OPEN = 0
3782 16:44:23.593271 CA_FULL_RATE = 0
3783 16:44:23.595730 DQ_CKDIV4_EN = 1
3784 16:44:23.599279 CA_CKDIV4_EN = 1
3785 16:44:23.602222 CA_PREDIV_EN = 0
3786 16:44:23.602679 PH8_DLY = 0
3787 16:44:23.605786 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3788 16:44:23.609328 DQ_AAMCK_DIV = 4
3789 16:44:23.612432 CA_AAMCK_DIV = 4
3790 16:44:23.615988 CA_ADMCK_DIV = 4
3791 16:44:23.619405 DQ_TRACK_CA_EN = 0
3792 16:44:23.619830 CA_PICK = 600
3793 16:44:23.622770 CA_MCKIO = 600
3794 16:44:23.625723 MCKIO_SEMI = 0
3795 16:44:23.628986 PLL_FREQ = 2288
3796 16:44:23.631932 DQ_UI_PI_RATIO = 32
3797 16:44:23.635717 CA_UI_PI_RATIO = 0
3798 16:44:23.638892 ===================================
3799 16:44:23.642246 ===================================
3800 16:44:23.642808 memory_type:LPDDR4
3801 16:44:23.645485 GP_NUM : 10
3802 16:44:23.649156 SRAM_EN : 1
3803 16:44:23.649688 MD32_EN : 0
3804 16:44:23.652711 ===================================
3805 16:44:23.655628 [ANA_INIT] >>>>>>>>>>>>>>
3806 16:44:23.658685 <<<<<< [CONFIGURE PHASE]: ANA_TX
3807 16:44:23.662737 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3808 16:44:23.665360 ===================================
3809 16:44:23.668768 data_rate = 1200,PCW = 0X5800
3810 16:44:23.672198 ===================================
3811 16:44:23.675227 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3812 16:44:23.679044 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3813 16:44:23.685042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3814 16:44:23.692476 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3815 16:44:23.695085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3816 16:44:23.698440 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3817 16:44:23.698909 [ANA_INIT] flow start
3818 16:44:23.702011 [ANA_INIT] PLL >>>>>>>>
3819 16:44:23.705570 [ANA_INIT] PLL <<<<<<<<
3820 16:44:23.706033 [ANA_INIT] MIDPI >>>>>>>>
3821 16:44:23.709247 [ANA_INIT] MIDPI <<<<<<<<
3822 16:44:23.711631 [ANA_INIT] DLL >>>>>>>>
3823 16:44:23.712192 [ANA_INIT] flow end
3824 16:44:23.718503 ============ LP4 DIFF to SE enter ============
3825 16:44:23.722039 ============ LP4 DIFF to SE exit ============
3826 16:44:23.722646 [ANA_INIT] <<<<<<<<<<<<<
3827 16:44:23.725024 [Flow] Enable top DCM control >>>>>
3828 16:44:23.728704 [Flow] Enable top DCM control <<<<<
3829 16:44:23.731316 Enable DLL master slave shuffle
3830 16:44:23.738519 ==============================================================
3831 16:44:23.741442 Gating Mode config
3832 16:44:23.744614 ==============================================================
3833 16:44:23.748391 Config description:
3834 16:44:23.758166 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3835 16:44:23.764798 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3836 16:44:23.768030 SELPH_MODE 0: By rank 1: By Phase
3837 16:44:23.774523 ==============================================================
3838 16:44:23.778594 GAT_TRACK_EN = 1
3839 16:44:23.781049 RX_GATING_MODE = 2
3840 16:44:23.784264 RX_GATING_TRACK_MODE = 2
3841 16:44:23.784733 SELPH_MODE = 1
3842 16:44:23.787676 PICG_EARLY_EN = 1
3843 16:44:23.791754 VALID_LAT_VALUE = 1
3844 16:44:23.798275 ==============================================================
3845 16:44:23.801008 Enter into Gating configuration >>>>
3846 16:44:23.804354 Exit from Gating configuration <<<<
3847 16:44:23.807505 Enter into DVFS_PRE_config >>>>>
3848 16:44:23.817534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3849 16:44:23.820947 Exit from DVFS_PRE_config <<<<<
3850 16:44:23.823789 Enter into PICG configuration >>>>
3851 16:44:23.827090 Exit from PICG configuration <<<<
3852 16:44:23.830873 [RX_INPUT] configuration >>>>>
3853 16:44:23.833645 [RX_INPUT] configuration <<<<<
3854 16:44:23.837458 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3855 16:44:23.844027 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3856 16:44:23.850550 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 16:44:23.857420 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 16:44:23.864046 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3859 16:44:23.870425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3860 16:44:23.873579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3861 16:44:23.877366 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3862 16:44:23.880465 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3863 16:44:23.886729 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3864 16:44:23.890467 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3865 16:44:23.893910 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3866 16:44:23.896539 ===================================
3867 16:44:23.900016 LPDDR4 DRAM CONFIGURATION
3868 16:44:23.903647 ===================================
3869 16:44:23.904210 EX_ROW_EN[0] = 0x0
3870 16:44:23.906815 EX_ROW_EN[1] = 0x0
3871 16:44:23.910386 LP4Y_EN = 0x0
3872 16:44:23.910947 WORK_FSP = 0x0
3873 16:44:23.913578 WL = 0x2
3874 16:44:23.914144 RL = 0x2
3875 16:44:23.916405 BL = 0x2
3876 16:44:23.916967 RPST = 0x0
3877 16:44:23.919442 RD_PRE = 0x0
3878 16:44:23.919904 WR_PRE = 0x1
3879 16:44:23.922700 WR_PST = 0x0
3880 16:44:23.923158 DBI_WR = 0x0
3881 16:44:23.926502 DBI_RD = 0x0
3882 16:44:23.927049 OTF = 0x1
3883 16:44:23.929710 ===================================
3884 16:44:23.932858 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3885 16:44:23.939311 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3886 16:44:23.942903 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3887 16:44:23.946329 ===================================
3888 16:44:23.949775 LPDDR4 DRAM CONFIGURATION
3889 16:44:23.952829 ===================================
3890 16:44:23.953403 EX_ROW_EN[0] = 0x10
3891 16:44:23.956177 EX_ROW_EN[1] = 0x0
3892 16:44:23.959776 LP4Y_EN = 0x0
3893 16:44:23.960342 WORK_FSP = 0x0
3894 16:44:23.962940 WL = 0x2
3895 16:44:23.963502 RL = 0x2
3896 16:44:23.965758 BL = 0x2
3897 16:44:23.966324 RPST = 0x0
3898 16:44:23.969214 RD_PRE = 0x0
3899 16:44:23.969775 WR_PRE = 0x1
3900 16:44:23.973011 WR_PST = 0x0
3901 16:44:23.973572 DBI_WR = 0x0
3902 16:44:23.975685 DBI_RD = 0x0
3903 16:44:23.976154 OTF = 0x1
3904 16:44:23.979231 ===================================
3905 16:44:23.985722 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3906 16:44:23.989987 nWR fixed to 30
3907 16:44:23.993841 [ModeRegInit_LP4] CH0 RK0
3908 16:44:23.994448 [ModeRegInit_LP4] CH0 RK1
3909 16:44:23.996774 [ModeRegInit_LP4] CH1 RK0
3910 16:44:23.999982 [ModeRegInit_LP4] CH1 RK1
3911 16:44:24.000545 match AC timing 17
3912 16:44:24.006926 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3913 16:44:24.010040 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3914 16:44:24.013790 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3915 16:44:24.019871 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3916 16:44:24.022871 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3917 16:44:24.023337 ==
3918 16:44:24.026288 Dram Type= 6, Freq= 0, CH_0, rank 0
3919 16:44:24.029838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3920 16:44:24.030429 ==
3921 16:44:24.036374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3922 16:44:24.042937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3923 16:44:24.046305 [CA 0] Center 36 (5~67) winsize 63
3924 16:44:24.049723 [CA 1] Center 36 (6~67) winsize 62
3925 16:44:24.052816 [CA 2] Center 34 (4~65) winsize 62
3926 16:44:24.055827 [CA 3] Center 34 (3~65) winsize 63
3927 16:44:24.059836 [CA 4] Center 33 (3~64) winsize 62
3928 16:44:24.062978 [CA 5] Center 33 (3~64) winsize 62
3929 16:44:24.063549
3930 16:44:24.065926 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3931 16:44:24.066520
3932 16:44:24.069667 [CATrainingPosCal] consider 1 rank data
3933 16:44:24.072982 u2DelayCellTimex100 = 270/100 ps
3934 16:44:24.075709 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3935 16:44:24.079695 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3936 16:44:24.082853 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3937 16:44:24.085872 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3938 16:44:24.093357 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3939 16:44:24.095682 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3940 16:44:24.096149
3941 16:44:24.099012 CA PerBit enable=1, Macro0, CA PI delay=33
3942 16:44:24.099481
3943 16:44:24.102781 [CBTSetCACLKResult] CA Dly = 33
3944 16:44:24.103348 CS Dly: 5 (0~36)
3945 16:44:24.103718 ==
3946 16:44:24.105986 Dram Type= 6, Freq= 0, CH_0, rank 1
3947 16:44:24.112469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 16:44:24.113039 ==
3949 16:44:24.115718 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3950 16:44:24.122760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3951 16:44:24.125699 [CA 0] Center 36 (6~67) winsize 62
3952 16:44:24.128872 [CA 1] Center 36 (6~67) winsize 62
3953 16:44:24.132094 [CA 2] Center 35 (5~65) winsize 61
3954 16:44:24.135579 [CA 3] Center 34 (4~65) winsize 62
3955 16:44:24.139094 [CA 4] Center 33 (3~64) winsize 62
3956 16:44:24.142073 [CA 5] Center 33 (3~64) winsize 62
3957 16:44:24.142694
3958 16:44:24.145604 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3959 16:44:24.146164
3960 16:44:24.148786 [CATrainingPosCal] consider 2 rank data
3961 16:44:24.151669 u2DelayCellTimex100 = 270/100 ps
3962 16:44:24.155223 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3963 16:44:24.162247 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3964 16:44:24.165751 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3965 16:44:24.168537 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3966 16:44:24.171619 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3967 16:44:24.175545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3968 16:44:24.176119
3969 16:44:24.179009 CA PerBit enable=1, Macro0, CA PI delay=33
3970 16:44:24.179576
3971 16:44:24.181565 [CBTSetCACLKResult] CA Dly = 33
3972 16:44:24.185198 CS Dly: 6 (0~38)
3973 16:44:24.185760
3974 16:44:24.188250 ----->DramcWriteLeveling(PI) begin...
3975 16:44:24.188721 ==
3976 16:44:24.191621 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 16:44:24.194630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3978 16:44:24.195095 ==
3979 16:44:24.198045 Write leveling (Byte 0): 35 => 35
3980 16:44:24.202415 Write leveling (Byte 1): 32 => 32
3981 16:44:24.205131 DramcWriteLeveling(PI) end<-----
3982 16:44:24.205697
3983 16:44:24.206061 ==
3984 16:44:24.207868 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 16:44:24.211434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 16:44:24.211998 ==
3987 16:44:24.215040 [Gating] SW mode calibration
3988 16:44:24.221195 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3989 16:44:24.228297 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3990 16:44:24.230681 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 16:44:24.234226 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3992 16:44:24.240729 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3993 16:44:24.244065 0 9 12 | B1->B0 | 3434 2424 | 1 0 | (0 0) (0 0)
3994 16:44:24.247122 0 9 16 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3995 16:44:24.254104 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3996 16:44:24.257797 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 16:44:24.260419 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 16:44:24.267180 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 16:44:24.271047 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4000 16:44:24.274246 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4001 16:44:24.280444 0 10 12 | B1->B0 | 2424 3e3e | 1 1 | (0 0) (0 0)
4002 16:44:24.284410 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
4003 16:44:24.287367 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 16:44:24.294136 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 16:44:24.297350 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 16:44:24.300704 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 16:44:24.306850 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 16:44:24.310185 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 16:44:24.313793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4010 16:44:24.320244 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4011 16:44:24.323495 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 16:44:24.327042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 16:44:24.333474 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 16:44:24.336665 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 16:44:24.339964 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 16:44:24.347184 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 16:44:24.350167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 16:44:24.353010 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 16:44:24.359524 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 16:44:24.363744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 16:44:24.366588 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 16:44:24.373122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 16:44:24.376634 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 16:44:24.379783 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 16:44:24.386293 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4026 16:44:24.389341 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4027 16:44:24.393178 Total UI for P1: 0, mck2ui 16
4028 16:44:24.395702 best dqsien dly found for B0: ( 0, 13, 12)
4029 16:44:24.399631 Total UI for P1: 0, mck2ui 16
4030 16:44:24.403088 best dqsien dly found for B1: ( 0, 13, 14)
4031 16:44:24.406423 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4032 16:44:24.409604 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4033 16:44:24.410182
4034 16:44:24.412781 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4035 16:44:24.415887 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4036 16:44:24.419269 [Gating] SW calibration Done
4037 16:44:24.419847 ==
4038 16:44:24.422305 Dram Type= 6, Freq= 0, CH_0, rank 0
4039 16:44:24.429099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4040 16:44:24.429682 ==
4041 16:44:24.430055 RX Vref Scan: 0
4042 16:44:24.430458
4043 16:44:24.432276 RX Vref 0 -> 0, step: 1
4044 16:44:24.432849
4045 16:44:24.435651 RX Delay -230 -> 252, step: 16
4046 16:44:24.439537 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4047 16:44:24.442758 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4048 16:44:24.445441 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4049 16:44:24.452030 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4050 16:44:24.455580 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4051 16:44:24.458617 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4052 16:44:24.462133 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4053 16:44:24.468861 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4054 16:44:24.472004 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4055 16:44:24.475642 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4056 16:44:24.478735 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4057 16:44:24.484823 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4058 16:44:24.488198 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4059 16:44:24.492287 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4060 16:44:24.495027 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4061 16:44:24.501776 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4062 16:44:24.502347 ==
4063 16:44:24.504847 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 16:44:24.508373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 16:44:24.508839 ==
4066 16:44:24.509203 DQS Delay:
4067 16:44:24.511669 DQS0 = 0, DQS1 = 0
4068 16:44:24.512230 DQM Delay:
4069 16:44:24.514929 DQM0 = 51, DQM1 = 39
4070 16:44:24.515391 DQ Delay:
4071 16:44:24.518760 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4072 16:44:24.521224 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4073 16:44:24.524716 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4074 16:44:24.528734 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4075 16:44:24.529304
4076 16:44:24.529671
4077 16:44:24.530011 ==
4078 16:44:24.531861 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 16:44:24.534313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 16:44:24.534839 ==
4081 16:44:24.535208
4082 16:44:24.538085
4083 16:44:24.538686 TX Vref Scan disable
4084 16:44:24.541323 == TX Byte 0 ==
4085 16:44:24.544761 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4086 16:44:24.548664 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4087 16:44:24.551630 == TX Byte 1 ==
4088 16:44:24.554684 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 16:44:24.558006 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 16:44:24.560963 ==
4091 16:44:24.561522 Dram Type= 6, Freq= 0, CH_0, rank 0
4092 16:44:24.567686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4093 16:44:24.568267 ==
4094 16:44:24.568646
4095 16:44:24.568983
4096 16:44:24.570974 TX Vref Scan disable
4097 16:44:24.571438 == TX Byte 0 ==
4098 16:44:24.577654 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4099 16:44:24.581141 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4100 16:44:24.581712 == TX Byte 1 ==
4101 16:44:24.587370 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4102 16:44:24.590873 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4103 16:44:24.591336
4104 16:44:24.591697 [DATLAT]
4105 16:44:24.594034 Freq=600, CH0 RK0
4106 16:44:24.594670
4107 16:44:24.595374 DATLAT Default: 0x9
4108 16:44:24.597584 0, 0xFFFF, sum = 0
4109 16:44:24.598174 1, 0xFFFF, sum = 0
4110 16:44:24.600254 2, 0xFFFF, sum = 0
4111 16:44:24.604184 3, 0xFFFF, sum = 0
4112 16:44:24.604691 4, 0xFFFF, sum = 0
4113 16:44:24.607331 5, 0xFFFF, sum = 0
4114 16:44:24.607805 6, 0xFFFF, sum = 0
4115 16:44:24.610985 7, 0xFFFF, sum = 0
4116 16:44:24.611454 8, 0x0, sum = 1
4117 16:44:24.613730 9, 0x0, sum = 2
4118 16:44:24.614157 10, 0x0, sum = 3
4119 16:44:24.614529 11, 0x0, sum = 4
4120 16:44:24.616711 best_step = 9
4121 16:44:24.617129
4122 16:44:24.617463 ==
4123 16:44:24.620275 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 16:44:24.623742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 16:44:24.624182 ==
4126 16:44:24.626788 RX Vref Scan: 1
4127 16:44:24.627225
4128 16:44:24.627659 RX Vref 0 -> 0, step: 1
4129 16:44:24.628072
4130 16:44:24.630564 RX Delay -179 -> 252, step: 8
4131 16:44:24.631016
4132 16:44:24.633856 Set Vref, RX VrefLevel [Byte0]: 59
4133 16:44:24.637004 [Byte1]: 49
4134 16:44:24.641428
4135 16:44:24.641950 Final RX Vref Byte 0 = 59 to rank0
4136 16:44:24.645493 Final RX Vref Byte 1 = 49 to rank0
4137 16:44:24.648111 Final RX Vref Byte 0 = 59 to rank1
4138 16:44:24.651538 Final RX Vref Byte 1 = 49 to rank1==
4139 16:44:24.654455 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 16:44:24.661663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 16:44:24.662234 ==
4142 16:44:24.662755 DQS Delay:
4143 16:44:24.664371 DQS0 = 0, DQS1 = 0
4144 16:44:24.664935 DQM Delay:
4145 16:44:24.665310 DQM0 = 49, DQM1 = 37
4146 16:44:24.667254 DQ Delay:
4147 16:44:24.670798 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4148 16:44:24.674303 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4149 16:44:24.677459 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4150 16:44:24.680474 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4151 16:44:24.681037
4152 16:44:24.681408
4153 16:44:24.687547 [DQSOSCAuto] RK0, (LSB)MR18= 0x5953, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4154 16:44:24.690415 CH0 RK0: MR19=808, MR18=5953
4155 16:44:24.697071 CH0_RK0: MR19=0x808, MR18=0x5953, DQSOSC=393, MR23=63, INC=169, DEC=113
4156 16:44:24.697673
4157 16:44:24.700223 ----->DramcWriteLeveling(PI) begin...
4158 16:44:24.700714 ==
4159 16:44:24.703580 Dram Type= 6, Freq= 0, CH_0, rank 1
4160 16:44:24.706920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 16:44:24.707388 ==
4162 16:44:24.711011 Write leveling (Byte 0): 36 => 36
4163 16:44:24.714469 Write leveling (Byte 1): 31 => 31
4164 16:44:24.717363 DramcWriteLeveling(PI) end<-----
4165 16:44:24.717932
4166 16:44:24.718301 ==
4167 16:44:24.720909 Dram Type= 6, Freq= 0, CH_0, rank 1
4168 16:44:24.726863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 16:44:24.727425 ==
4170 16:44:24.727795 [Gating] SW mode calibration
4171 16:44:24.737029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4172 16:44:24.740433 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4173 16:44:24.743712 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 16:44:24.750688 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 16:44:24.753601 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4176 16:44:24.757308 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (0 0) (0 0)
4177 16:44:24.763899 0 9 16 | B1->B0 | 2b2b 2525 | 0 0 | (0 0) (0 0)
4178 16:44:24.766593 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 16:44:24.770215 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 16:44:24.777107 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 16:44:24.779931 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 16:44:24.783102 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 16:44:24.789683 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4184 16:44:24.792786 0 10 12 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
4185 16:44:24.796373 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4186 16:44:24.802690 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 16:44:24.806028 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 16:44:24.809576 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 16:44:24.816206 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 16:44:24.819144 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 16:44:24.822549 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 16:44:24.829571 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4193 16:44:24.832862 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4194 16:44:24.835986 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 16:44:24.842947 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 16:44:24.845930 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 16:44:24.849639 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 16:44:24.856506 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 16:44:24.859615 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 16:44:24.862667 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 16:44:24.869236 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 16:44:24.872755 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 16:44:24.876454 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 16:44:24.882559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 16:44:24.885842 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 16:44:24.889478 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 16:44:24.895867 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 16:44:24.899032 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4209 16:44:24.902198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4210 16:44:24.905481 Total UI for P1: 0, mck2ui 16
4211 16:44:24.909011 best dqsien dly found for B0: ( 0, 13, 12)
4212 16:44:24.912204 Total UI for P1: 0, mck2ui 16
4213 16:44:24.916049 best dqsien dly found for B1: ( 0, 13, 14)
4214 16:44:24.918778 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4215 16:44:24.921671 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4216 16:44:24.922130
4217 16:44:24.928867 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4218 16:44:24.932205 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4219 16:44:24.932765 [Gating] SW calibration Done
4220 16:44:24.935495 ==
4221 16:44:24.939272 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 16:44:24.941947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 16:44:24.942566 ==
4224 16:44:24.943057 RX Vref Scan: 0
4225 16:44:24.943519
4226 16:44:24.945078 RX Vref 0 -> 0, step: 1
4227 16:44:24.945576
4228 16:44:24.948562 RX Delay -230 -> 252, step: 16
4229 16:44:24.951987 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4230 16:44:24.955282 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4231 16:44:24.962148 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4232 16:44:24.965241 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4233 16:44:24.968827 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4234 16:44:24.972196 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4235 16:44:24.978243 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4236 16:44:24.981714 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4237 16:44:24.984632 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4238 16:44:24.988312 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4239 16:44:24.991641 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4240 16:44:24.997807 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4241 16:44:25.001332 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4242 16:44:25.004393 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4243 16:44:25.007756 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4244 16:44:25.014864 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4245 16:44:25.015460 ==
4246 16:44:25.017854 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 16:44:25.021315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 16:44:25.021822 ==
4249 16:44:25.022250 DQS Delay:
4250 16:44:25.024838 DQS0 = 0, DQS1 = 0
4251 16:44:25.025415 DQM Delay:
4252 16:44:25.027566 DQM0 = 50, DQM1 = 43
4253 16:44:25.028037 DQ Delay:
4254 16:44:25.031132 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4255 16:44:25.034292 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4256 16:44:25.037857 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4257 16:44:25.040795 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4258 16:44:25.041361
4259 16:44:25.041730
4260 16:44:25.042071 ==
4261 16:44:25.044413 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 16:44:25.050826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 16:44:25.051395 ==
4264 16:44:25.051773
4265 16:44:25.052121
4266 16:44:25.052454 TX Vref Scan disable
4267 16:44:25.054855 == TX Byte 0 ==
4268 16:44:25.057954 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4269 16:44:25.064383 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4270 16:44:25.064967 == TX Byte 1 ==
4271 16:44:25.067708 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4272 16:44:25.074434 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4273 16:44:25.075002 ==
4274 16:44:25.077695 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 16:44:25.081083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 16:44:25.081650 ==
4277 16:44:25.082020
4278 16:44:25.082391
4279 16:44:25.083891 TX Vref Scan disable
4280 16:44:25.087491 == TX Byte 0 ==
4281 16:44:25.090474 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4282 16:44:25.094211 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4283 16:44:25.097101 == TX Byte 1 ==
4284 16:44:25.100696 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4285 16:44:25.103749 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4286 16:44:25.104262
4287 16:44:25.104874 [DATLAT]
4288 16:44:25.107377 Freq=600, CH0 RK1
4289 16:44:25.107921
4290 16:44:25.110926 DATLAT Default: 0x9
4291 16:44:25.111394 0, 0xFFFF, sum = 0
4292 16:44:25.113833 1, 0xFFFF, sum = 0
4293 16:44:25.114308 2, 0xFFFF, sum = 0
4294 16:44:25.117430 3, 0xFFFF, sum = 0
4295 16:44:25.118031 4, 0xFFFF, sum = 0
4296 16:44:25.120665 5, 0xFFFF, sum = 0
4297 16:44:25.121247 6, 0xFFFF, sum = 0
4298 16:44:25.123487 7, 0xFFFF, sum = 0
4299 16:44:25.123976 8, 0x0, sum = 1
4300 16:44:25.127009 9, 0x0, sum = 2
4301 16:44:25.127500 10, 0x0, sum = 3
4302 16:44:25.130478 11, 0x0, sum = 4
4303 16:44:25.131060 best_step = 9
4304 16:44:25.131542
4305 16:44:25.131993 ==
4306 16:44:25.133446 Dram Type= 6, Freq= 0, CH_0, rank 1
4307 16:44:25.136899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4308 16:44:25.137382 ==
4309 16:44:25.140253 RX Vref Scan: 0
4310 16:44:25.140790
4311 16:44:25.143487 RX Vref 0 -> 0, step: 1
4312 16:44:25.143988
4313 16:44:25.144432 RX Delay -163 -> 252, step: 8
4314 16:44:25.151092 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4315 16:44:25.154663 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4316 16:44:25.157757 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4317 16:44:25.161198 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4318 16:44:25.164872 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4319 16:44:25.171116 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4320 16:44:25.174380 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4321 16:44:25.177933 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4322 16:44:25.180893 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4323 16:44:25.187953 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4324 16:44:25.190928 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4325 16:44:25.194441 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4326 16:44:25.196970 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4327 16:44:25.204134 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4328 16:44:25.207140 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4329 16:44:25.210605 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4330 16:44:25.210921 ==
4331 16:44:25.213962 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 16:44:25.217228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 16:44:25.217735 ==
4334 16:44:25.221107 DQS Delay:
4335 16:44:25.221661 DQS0 = 0, DQS1 = 0
4336 16:44:25.224169 DQM Delay:
4337 16:44:25.224625 DQM0 = 48, DQM1 = 42
4338 16:44:25.224983 DQ Delay:
4339 16:44:25.226947 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4340 16:44:25.231130 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =56
4341 16:44:25.233754 DQ8 =36, DQ9 =28, DQ10 =40, DQ11 =32
4342 16:44:25.237104 DQ12 =48, DQ13 =48, DQ14 =52, DQ15 =52
4343 16:44:25.237562
4344 16:44:25.237921
4345 16:44:25.248153 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f2d, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
4346 16:44:25.250701 CH0 RK1: MR19=808, MR18=5F2D
4347 16:44:25.257957 CH0_RK1: MR19=0x808, MR18=0x5F2D, DQSOSC=391, MR23=63, INC=171, DEC=114
4348 16:44:25.258554 [RxdqsGatingPostProcess] freq 600
4349 16:44:25.263620 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4350 16:44:25.267561 Pre-setting of DQS Precalculation
4351 16:44:25.270782 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4352 16:44:25.273667 ==
4353 16:44:25.277209 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 16:44:25.280547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 16:44:25.281103 ==
4356 16:44:25.283759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 16:44:25.290266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4358 16:44:25.293844 [CA 0] Center 36 (6~66) winsize 61
4359 16:44:25.297663 [CA 1] Center 35 (5~66) winsize 62
4360 16:44:25.300842 [CA 2] Center 34 (4~65) winsize 62
4361 16:44:25.303935 [CA 3] Center 34 (3~65) winsize 63
4362 16:44:25.307088 [CA 4] Center 34 (4~65) winsize 62
4363 16:44:25.310686 [CA 5] Center 33 (3~64) winsize 62
4364 16:44:25.311145
4365 16:44:25.313765 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4366 16:44:25.314318
4367 16:44:25.316978 [CATrainingPosCal] consider 1 rank data
4368 16:44:25.320659 u2DelayCellTimex100 = 270/100 ps
4369 16:44:25.323801 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4370 16:44:25.330242 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4371 16:44:25.333634 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4372 16:44:25.336887 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4373 16:44:25.340125 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 16:44:25.343582 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 16:44:25.344138
4376 16:44:25.346695 CA PerBit enable=1, Macro0, CA PI delay=33
4377 16:44:25.347153
4378 16:44:25.350286 [CBTSetCACLKResult] CA Dly = 33
4379 16:44:25.353460 CS Dly: 4 (0~35)
4380 16:44:25.354038 ==
4381 16:44:25.357054 Dram Type= 6, Freq= 0, CH_1, rank 1
4382 16:44:25.360353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 16:44:25.360908 ==
4384 16:44:25.367603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4385 16:44:25.369821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4386 16:44:25.374179 [CA 0] Center 35 (5~66) winsize 62
4387 16:44:25.377505 [CA 1] Center 35 (5~66) winsize 62
4388 16:44:25.380631 [CA 2] Center 34 (4~65) winsize 62
4389 16:44:25.384660 [CA 3] Center 34 (4~65) winsize 62
4390 16:44:25.386903 [CA 4] Center 34 (4~65) winsize 62
4391 16:44:25.390506 [CA 5] Center 33 (3~64) winsize 62
4392 16:44:25.391060
4393 16:44:25.393850 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4394 16:44:25.394451
4395 16:44:25.397143 [CATrainingPosCal] consider 2 rank data
4396 16:44:25.400327 u2DelayCellTimex100 = 270/100 ps
4397 16:44:25.403921 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4398 16:44:25.410772 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4399 16:44:25.413963 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4400 16:44:25.417171 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4401 16:44:25.420678 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4402 16:44:25.423290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4403 16:44:25.423848
4404 16:44:25.426802 CA PerBit enable=1, Macro0, CA PI delay=33
4405 16:44:25.427285
4406 16:44:25.429992 [CBTSetCACLKResult] CA Dly = 33
4407 16:44:25.433817 CS Dly: 4 (0~36)
4408 16:44:25.434430
4409 16:44:25.436435 ----->DramcWriteLeveling(PI) begin...
4410 16:44:25.436926 ==
4411 16:44:25.439962 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 16:44:25.443586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 16:44:25.444177 ==
4414 16:44:25.446881 Write leveling (Byte 0): 30 => 30
4415 16:44:25.450392 Write leveling (Byte 1): 30 => 30
4416 16:44:25.454124 DramcWriteLeveling(PI) end<-----
4417 16:44:25.454749
4418 16:44:25.455235 ==
4419 16:44:25.456315 Dram Type= 6, Freq= 0, CH_1, rank 0
4420 16:44:25.459815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 16:44:25.460395 ==
4422 16:44:25.463387 [Gating] SW mode calibration
4423 16:44:25.469767 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4424 16:44:25.476556 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4425 16:44:25.480031 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 16:44:25.483255 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 16:44:25.489716 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4428 16:44:25.492998 0 9 12 | B1->B0 | 2d2d 2c2c | 1 0 | (1 0) (0 0)
4429 16:44:25.496381 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 16:44:25.502978 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 16:44:25.505921 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 16:44:25.510339 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 16:44:25.516436 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 16:44:25.520030 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 16:44:25.522686 0 10 8 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
4436 16:44:25.529211 0 10 12 | B1->B0 | 3838 3c3c | 1 0 | (0 0) (0 0)
4437 16:44:25.532681 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 16:44:25.536043 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 16:44:25.542782 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 16:44:25.545747 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 16:44:25.549059 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 16:44:25.555488 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 16:44:25.559556 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4444 16:44:25.562585 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4445 16:44:25.568923 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 16:44:25.572313 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 16:44:25.575219 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 16:44:25.582199 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 16:44:25.584972 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 16:44:25.589092 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 16:44:25.595538 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 16:44:25.598253 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 16:44:25.601917 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 16:44:25.608125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 16:44:25.611537 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 16:44:25.615050 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 16:44:25.621511 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 16:44:25.624770 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 16:44:25.628173 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 16:44:25.634794 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4461 16:44:25.637720 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4462 16:44:25.641294 Total UI for P1: 0, mck2ui 16
4463 16:44:25.644262 best dqsien dly found for B0: ( 0, 13, 12)
4464 16:44:25.647775 Total UI for P1: 0, mck2ui 16
4465 16:44:25.651310 best dqsien dly found for B1: ( 0, 13, 14)
4466 16:44:25.654641 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4467 16:44:25.657691 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4468 16:44:25.658264
4469 16:44:25.661286 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4470 16:44:25.664323 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4471 16:44:25.668351 [Gating] SW calibration Done
4472 16:44:25.668931 ==
4473 16:44:25.670721 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 16:44:25.677696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 16:44:25.678277 ==
4476 16:44:25.678804 RX Vref Scan: 0
4477 16:44:25.679259
4478 16:44:25.680455 RX Vref 0 -> 0, step: 1
4479 16:44:25.680936
4480 16:44:25.684201 RX Delay -230 -> 252, step: 16
4481 16:44:25.687638 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4482 16:44:25.690777 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4483 16:44:25.694680 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4484 16:44:25.700806 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4485 16:44:25.704473 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4486 16:44:25.707281 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4487 16:44:25.710959 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4488 16:44:25.717672 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4489 16:44:25.720597 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4490 16:44:25.723596 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4491 16:44:25.727810 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4492 16:44:25.733697 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4493 16:44:25.736817 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4494 16:44:25.740601 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4495 16:44:25.744339 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4496 16:44:25.750078 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4497 16:44:25.750784 ==
4498 16:44:25.753307 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 16:44:25.756799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 16:44:25.757360 ==
4501 16:44:25.757729 DQS Delay:
4502 16:44:25.759839 DQS0 = 0, DQS1 = 0
4503 16:44:25.760406 DQM Delay:
4504 16:44:25.762699 DQM0 = 51, DQM1 = 42
4505 16:44:25.763167 DQ Delay:
4506 16:44:25.766894 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4507 16:44:25.769908 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4508 16:44:25.772796 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4509 16:44:25.775944 DQ12 =57, DQ13 =49, DQ14 =41, DQ15 =49
4510 16:44:25.776463
4511 16:44:25.776831
4512 16:44:25.777173 ==
4513 16:44:25.779430 Dram Type= 6, Freq= 0, CH_1, rank 0
4514 16:44:25.783018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4515 16:44:25.786174 ==
4516 16:44:25.786672
4517 16:44:25.787041
4518 16:44:25.787386 TX Vref Scan disable
4519 16:44:25.789231 == TX Byte 0 ==
4520 16:44:25.792273 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 16:44:25.799017 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 16:44:25.799488 == TX Byte 1 ==
4523 16:44:25.802719 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 16:44:25.805638 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 16:44:25.809151 ==
4526 16:44:25.812598 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 16:44:25.815921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 16:44:25.816485 ==
4529 16:44:25.816858
4530 16:44:25.817197
4531 16:44:25.819199 TX Vref Scan disable
4532 16:44:25.819668 == TX Byte 0 ==
4533 16:44:25.826014 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4534 16:44:25.829249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4535 16:44:25.832095 == TX Byte 1 ==
4536 16:44:25.835552 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 16:44:25.838825 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 16:44:25.839293
4539 16:44:25.839662 [DATLAT]
4540 16:44:25.842503 Freq=600, CH1 RK0
4541 16:44:25.843062
4542 16:44:25.843430 DATLAT Default: 0x9
4543 16:44:25.845752 0, 0xFFFF, sum = 0
4544 16:44:25.848880 1, 0xFFFF, sum = 0
4545 16:44:25.849452 2, 0xFFFF, sum = 0
4546 16:44:25.852297 3, 0xFFFF, sum = 0
4547 16:44:25.852884 4, 0xFFFF, sum = 0
4548 16:44:25.855408 5, 0xFFFF, sum = 0
4549 16:44:25.855887 6, 0xFFFF, sum = 0
4550 16:44:25.858951 7, 0xFFFF, sum = 0
4551 16:44:25.859648 8, 0x0, sum = 1
4552 16:44:25.860034 9, 0x0, sum = 2
4553 16:44:25.861977 10, 0x0, sum = 3
4554 16:44:25.862479 11, 0x0, sum = 4
4555 16:44:25.865850 best_step = 9
4556 16:44:25.866439
4557 16:44:25.866810 ==
4558 16:44:25.869267 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 16:44:25.871890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 16:44:25.872364 ==
4561 16:44:25.875402 RX Vref Scan: 1
4562 16:44:25.875962
4563 16:44:25.876333 RX Vref 0 -> 0, step: 1
4564 16:44:25.878774
4565 16:44:25.879331 RX Delay -179 -> 252, step: 8
4566 16:44:25.879761
4567 16:44:25.881907 Set Vref, RX VrefLevel [Byte0]: 52
4568 16:44:25.885353 [Byte1]: 52
4569 16:44:25.889632
4570 16:44:25.890193 Final RX Vref Byte 0 = 52 to rank0
4571 16:44:25.893163 Final RX Vref Byte 1 = 52 to rank0
4572 16:44:25.896753 Final RX Vref Byte 0 = 52 to rank1
4573 16:44:25.899644 Final RX Vref Byte 1 = 52 to rank1==
4574 16:44:25.903030 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 16:44:25.909532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 16:44:25.910095 ==
4577 16:44:25.910529 DQS Delay:
4578 16:44:25.912554 DQS0 = 0, DQS1 = 0
4579 16:44:25.913122 DQM Delay:
4580 16:44:25.913493 DQM0 = 49, DQM1 = 42
4581 16:44:25.915920 DQ Delay:
4582 16:44:25.919026 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4583 16:44:25.923515 DQ4 =52, DQ5 =60, DQ6 =60, DQ7 =44
4584 16:44:25.926136 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =36
4585 16:44:25.929335 DQ12 =56, DQ13 =48, DQ14 =52, DQ15 =48
4586 16:44:25.929895
4587 16:44:25.930262
4588 16:44:25.935924 [DQSOSCAuto] RK0, (LSB)MR18= 0x476e, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4589 16:44:25.939161 CH1 RK0: MR19=808, MR18=476E
4590 16:44:25.945539 CH1_RK0: MR19=0x808, MR18=0x476E, DQSOSC=389, MR23=63, INC=173, DEC=115
4591 16:44:25.946106
4592 16:44:25.949241 ----->DramcWriteLeveling(PI) begin...
4593 16:44:25.949826 ==
4594 16:44:25.952119 Dram Type= 6, Freq= 0, CH_1, rank 1
4595 16:44:25.955079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 16:44:25.955550 ==
4597 16:44:25.958909 Write leveling (Byte 0): 29 => 29
4598 16:44:25.962074 Write leveling (Byte 1): 32 => 32
4599 16:44:25.965352 DramcWriteLeveling(PI) end<-----
4600 16:44:25.965891
4601 16:44:25.966257 ==
4602 16:44:25.968897 Dram Type= 6, Freq= 0, CH_1, rank 1
4603 16:44:25.975373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 16:44:25.975929 ==
4605 16:44:25.976303 [Gating] SW mode calibration
4606 16:44:25.985103 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4607 16:44:25.988242 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4608 16:44:25.991568 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 16:44:25.998095 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4610 16:44:26.001906 0 9 8 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 0)
4611 16:44:26.004878 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (1 0) (1 0)
4612 16:44:26.011399 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 16:44:26.014262 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 16:44:26.017838 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 16:44:26.024913 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 16:44:26.027883 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 16:44:26.031236 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4618 16:44:26.037916 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
4619 16:44:26.041369 0 10 12 | B1->B0 | 3939 2f2f | 0 0 | (0 0) (0 0)
4620 16:44:26.044562 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 16:44:26.050991 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 16:44:26.054395 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 16:44:26.058298 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 16:44:26.064553 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 16:44:26.068035 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 16:44:26.070827 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4627 16:44:26.077471 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4628 16:44:26.080621 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 16:44:26.083941 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 16:44:26.090721 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 16:44:26.094320 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 16:44:26.097006 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 16:44:26.104159 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 16:44:26.107059 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 16:44:26.110305 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 16:44:26.116882 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 16:44:26.120759 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 16:44:26.123898 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 16:44:26.130167 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 16:44:26.133996 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 16:44:26.136678 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 16:44:26.143247 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 16:44:26.146795 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4644 16:44:26.150124 Total UI for P1: 0, mck2ui 16
4645 16:44:26.153470 best dqsien dly found for B0: ( 0, 13, 10)
4646 16:44:26.156532 Total UI for P1: 0, mck2ui 16
4647 16:44:26.159518 best dqsien dly found for B1: ( 0, 13, 10)
4648 16:44:26.163119 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4649 16:44:26.166940 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4650 16:44:26.167504
4651 16:44:26.170148 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4652 16:44:26.176399 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4653 16:44:26.176992 [Gating] SW calibration Done
4654 16:44:26.177365 ==
4655 16:44:26.179713 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 16:44:26.185958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 16:44:26.186570 ==
4658 16:44:26.186951 RX Vref Scan: 0
4659 16:44:26.187295
4660 16:44:26.189535 RX Vref 0 -> 0, step: 1
4661 16:44:26.190110
4662 16:44:26.192519 RX Delay -230 -> 252, step: 16
4663 16:44:26.195836 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4664 16:44:26.199008 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4665 16:44:26.205816 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4666 16:44:26.209377 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4667 16:44:26.212401 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4668 16:44:26.215820 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4669 16:44:26.219006 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4670 16:44:26.225764 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4671 16:44:26.229585 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4672 16:44:26.232270 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4673 16:44:26.235643 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4674 16:44:26.243239 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4675 16:44:26.245657 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4676 16:44:26.249184 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4677 16:44:26.252217 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4678 16:44:26.258939 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4679 16:44:26.259519 ==
4680 16:44:26.261900 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 16:44:26.265768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 16:44:26.266346 ==
4683 16:44:26.266760 DQS Delay:
4684 16:44:26.268640 DQS0 = 0, DQS1 = 0
4685 16:44:26.269210 DQM Delay:
4686 16:44:26.271592 DQM0 = 52, DQM1 = 46
4687 16:44:26.272060 DQ Delay:
4688 16:44:26.275475 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4689 16:44:26.278612 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4690 16:44:26.282224 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4691 16:44:26.285109 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4692 16:44:26.285679
4693 16:44:26.286054
4694 16:44:26.286434 ==
4695 16:44:26.288554 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 16:44:26.292169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 16:44:26.292746 ==
4698 16:44:26.295652
4699 16:44:26.296145
4700 16:44:26.296525 TX Vref Scan disable
4701 16:44:26.298777 == TX Byte 0 ==
4702 16:44:26.301483 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 16:44:26.304836 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 16:44:26.308302 == TX Byte 1 ==
4705 16:44:26.311348 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4706 16:44:26.314951 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4707 16:44:26.317881 ==
4708 16:44:26.318413 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 16:44:26.324843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 16:44:26.325428 ==
4711 16:44:26.325802
4712 16:44:26.326249
4713 16:44:26.327781 TX Vref Scan disable
4714 16:44:26.328250 == TX Byte 0 ==
4715 16:44:26.335163 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 16:44:26.337957 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 16:44:26.338462 == TX Byte 1 ==
4718 16:44:26.344639 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4719 16:44:26.347965 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4720 16:44:26.348537
4721 16:44:26.348908 [DATLAT]
4722 16:44:26.351152 Freq=600, CH1 RK1
4723 16:44:26.351625
4724 16:44:26.351991 DATLAT Default: 0x9
4725 16:44:26.354328 0, 0xFFFF, sum = 0
4726 16:44:26.354833 1, 0xFFFF, sum = 0
4727 16:44:26.357959 2, 0xFFFF, sum = 0
4728 16:44:26.361178 3, 0xFFFF, sum = 0
4729 16:44:26.361758 4, 0xFFFF, sum = 0
4730 16:44:26.364861 5, 0xFFFF, sum = 0
4731 16:44:26.365442 6, 0xFFFF, sum = 0
4732 16:44:26.368084 7, 0xFFFF, sum = 0
4733 16:44:26.368678 8, 0x0, sum = 1
4734 16:44:26.369062 9, 0x0, sum = 2
4735 16:44:26.371075 10, 0x0, sum = 3
4736 16:44:26.371552 11, 0x0, sum = 4
4737 16:44:26.374447 best_step = 9
4738 16:44:26.375021
4739 16:44:26.375393 ==
4740 16:44:26.377928 Dram Type= 6, Freq= 0, CH_1, rank 1
4741 16:44:26.381011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4742 16:44:26.381590 ==
4743 16:44:26.384588 RX Vref Scan: 0
4744 16:44:26.385161
4745 16:44:26.385539 RX Vref 0 -> 0, step: 1
4746 16:44:26.385890
4747 16:44:26.387874 RX Delay -163 -> 252, step: 8
4748 16:44:26.394996 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4749 16:44:26.398408 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4750 16:44:26.401846 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4751 16:44:26.404721 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4752 16:44:26.411614 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4753 16:44:26.414392 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4754 16:44:26.418096 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4755 16:44:26.422323 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4756 16:44:26.424986 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4757 16:44:26.431223 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4758 16:44:26.434458 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4759 16:44:26.438649 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4760 16:44:26.440837 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4761 16:44:26.447716 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4762 16:44:26.450792 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4763 16:44:26.454994 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4764 16:44:26.455569 ==
4765 16:44:26.458057 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 16:44:26.461015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 16:44:26.461591 ==
4768 16:44:26.464429 DQS Delay:
4769 16:44:26.464899 DQS0 = 0, DQS1 = 0
4770 16:44:26.467497 DQM Delay:
4771 16:44:26.468066 DQM0 = 48, DQM1 = 43
4772 16:44:26.468442 DQ Delay:
4773 16:44:26.470812 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =48
4774 16:44:26.473592 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =44
4775 16:44:26.477353 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4776 16:44:26.480341 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4777 16:44:26.480499
4778 16:44:26.480572
4779 16:44:26.490145 [DQSOSCAuto] RK1, (LSB)MR18= 0x581d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4780 16:44:26.493716 CH1 RK1: MR19=808, MR18=581D
4781 16:44:26.500322 CH1_RK1: MR19=0x808, MR18=0x581D, DQSOSC=393, MR23=63, INC=169, DEC=113
4782 16:44:26.503959 [RxdqsGatingPostProcess] freq 600
4783 16:44:26.506655 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4784 16:44:26.510085 Pre-setting of DQS Precalculation
4785 16:44:26.516780 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4786 16:44:26.523593 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4787 16:44:26.529914 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4788 16:44:26.530232
4789 16:44:26.530455
4790 16:44:26.533555 [Calibration Summary] 1200 Mbps
4791 16:44:26.533943 CH 0, Rank 0
4792 16:44:26.536469 SW Impedance : PASS
4793 16:44:26.539841 DUTY Scan : NO K
4794 16:44:26.540204 ZQ Calibration : PASS
4795 16:44:26.543480 Jitter Meter : NO K
4796 16:44:26.544156 CBT Training : PASS
4797 16:44:26.546873 Write leveling : PASS
4798 16:44:26.549970 RX DQS gating : PASS
4799 16:44:26.550606 RX DQ/DQS(RDDQC) : PASS
4800 16:44:26.553434 TX DQ/DQS : PASS
4801 16:44:26.556798 RX DATLAT : PASS
4802 16:44:26.557375 RX DQ/DQS(Engine): PASS
4803 16:44:26.559978 TX OE : NO K
4804 16:44:26.560558 All Pass.
4805 16:44:26.560931
4806 16:44:26.563102 CH 0, Rank 1
4807 16:44:26.563572 SW Impedance : PASS
4808 16:44:26.567250 DUTY Scan : NO K
4809 16:44:26.570327 ZQ Calibration : PASS
4810 16:44:26.570936 Jitter Meter : NO K
4811 16:44:26.573564 CBT Training : PASS
4812 16:44:26.576840 Write leveling : PASS
4813 16:44:26.577419 RX DQS gating : PASS
4814 16:44:26.579929 RX DQ/DQS(RDDQC) : PASS
4815 16:44:26.582940 TX DQ/DQS : PASS
4816 16:44:26.583517 RX DATLAT : PASS
4817 16:44:26.586439 RX DQ/DQS(Engine): PASS
4818 16:44:26.589658 TX OE : NO K
4819 16:44:26.590235 All Pass.
4820 16:44:26.590645
4821 16:44:26.590991 CH 1, Rank 0
4822 16:44:26.592933 SW Impedance : PASS
4823 16:44:26.596248 DUTY Scan : NO K
4824 16:44:26.596826 ZQ Calibration : PASS
4825 16:44:26.599280 Jitter Meter : NO K
4826 16:44:26.603000 CBT Training : PASS
4827 16:44:26.603470 Write leveling : PASS
4828 16:44:26.606072 RX DQS gating : PASS
4829 16:44:26.609422 RX DQ/DQS(RDDQC) : PASS
4830 16:44:26.610014 TX DQ/DQS : PASS
4831 16:44:26.612441 RX DATLAT : PASS
4832 16:44:26.615724 RX DQ/DQS(Engine): PASS
4833 16:44:26.616193 TX OE : NO K
4834 16:44:26.616566 All Pass.
4835 16:44:26.619012
4836 16:44:26.619479 CH 1, Rank 1
4837 16:44:26.622468 SW Impedance : PASS
4838 16:44:26.623036 DUTY Scan : NO K
4839 16:44:26.625449 ZQ Calibration : PASS
4840 16:44:26.625918 Jitter Meter : NO K
4841 16:44:26.629412 CBT Training : PASS
4842 16:44:26.632164 Write leveling : PASS
4843 16:44:26.632739 RX DQS gating : PASS
4844 16:44:26.635692 RX DQ/DQS(RDDQC) : PASS
4845 16:44:26.639019 TX DQ/DQS : PASS
4846 16:44:26.639596 RX DATLAT : PASS
4847 16:44:26.641910 RX DQ/DQS(Engine): PASS
4848 16:44:26.645429 TX OE : NO K
4849 16:44:26.645914 All Pass.
4850 16:44:26.646287
4851 16:44:26.650898 DramC Write-DBI off
4852 16:44:26.651470 PER_BANK_REFRESH: Hybrid Mode
4853 16:44:26.652259 TX_TRACKING: ON
4854 16:44:26.659006 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4855 16:44:26.665453 [FAST_K] Save calibration result to emmc
4856 16:44:26.669143 dramc_set_vcore_voltage set vcore to 662500
4857 16:44:26.669709 Read voltage for 933, 3
4858 16:44:26.672204 Vio18 = 0
4859 16:44:26.672769 Vcore = 662500
4860 16:44:26.673137 Vdram = 0
4861 16:44:26.674979 Vddq = 0
4862 16:44:26.675444 Vmddr = 0
4863 16:44:26.678713 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4864 16:44:26.685440 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4865 16:44:26.688213 MEM_TYPE=3, freq_sel=17
4866 16:44:26.691617 sv_algorithm_assistance_LP4_1600
4867 16:44:26.694948 ============ PULL DRAM RESETB DOWN ============
4868 16:44:26.698460 ========== PULL DRAM RESETB DOWN end =========
4869 16:44:26.705748 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4870 16:44:26.708245 ===================================
4871 16:44:26.708809 LPDDR4 DRAM CONFIGURATION
4872 16:44:26.711226 ===================================
4873 16:44:26.714515 EX_ROW_EN[0] = 0x0
4874 16:44:26.718316 EX_ROW_EN[1] = 0x0
4875 16:44:26.718922 LP4Y_EN = 0x0
4876 16:44:26.721480 WORK_FSP = 0x0
4877 16:44:26.722036 WL = 0x3
4878 16:44:26.724769 RL = 0x3
4879 16:44:26.725338 BL = 0x2
4880 16:44:26.728437 RPST = 0x0
4881 16:44:26.728902 RD_PRE = 0x0
4882 16:44:26.731218 WR_PRE = 0x1
4883 16:44:26.731684 WR_PST = 0x0
4884 16:44:26.734535 DBI_WR = 0x0
4885 16:44:26.735000 DBI_RD = 0x0
4886 16:44:26.738196 OTF = 0x1
4887 16:44:26.741638 ===================================
4888 16:44:26.744801 ===================================
4889 16:44:26.745376 ANA top config
4890 16:44:26.748165 ===================================
4891 16:44:26.751012 DLL_ASYNC_EN = 0
4892 16:44:26.754762 ALL_SLAVE_EN = 1
4893 16:44:26.758217 NEW_RANK_MODE = 1
4894 16:44:26.758892 DLL_IDLE_MODE = 1
4895 16:44:26.761355 LP45_APHY_COMB_EN = 1
4896 16:44:26.764303 TX_ODT_DIS = 1
4897 16:44:26.767835 NEW_8X_MODE = 1
4898 16:44:26.771244 ===================================
4899 16:44:26.774794 ===================================
4900 16:44:26.777830 data_rate = 1866
4901 16:44:26.778424 CKR = 1
4902 16:44:26.781076 DQ_P2S_RATIO = 8
4903 16:44:26.784096 ===================================
4904 16:44:26.787314 CA_P2S_RATIO = 8
4905 16:44:26.790682 DQ_CA_OPEN = 0
4906 16:44:26.794529 DQ_SEMI_OPEN = 0
4907 16:44:26.797627 CA_SEMI_OPEN = 0
4908 16:44:26.798186 CA_FULL_RATE = 0
4909 16:44:26.800412 DQ_CKDIV4_EN = 1
4910 16:44:26.803970 CA_CKDIV4_EN = 1
4911 16:44:26.807832 CA_PREDIV_EN = 0
4912 16:44:26.810779 PH8_DLY = 0
4913 16:44:26.814200 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4914 16:44:26.814744 DQ_AAMCK_DIV = 4
4915 16:44:26.817374 CA_AAMCK_DIV = 4
4916 16:44:26.820965 CA_ADMCK_DIV = 4
4917 16:44:26.824025 DQ_TRACK_CA_EN = 0
4918 16:44:26.826901 CA_PICK = 933
4919 16:44:26.830623 CA_MCKIO = 933
4920 16:44:26.831183 MCKIO_SEMI = 0
4921 16:44:26.833831 PLL_FREQ = 3732
4922 16:44:26.837838 DQ_UI_PI_RATIO = 32
4923 16:44:26.840472 CA_UI_PI_RATIO = 0
4924 16:44:26.843688 ===================================
4925 16:44:26.847786 ===================================
4926 16:44:26.850613 memory_type:LPDDR4
4927 16:44:26.851175 GP_NUM : 10
4928 16:44:26.853702 SRAM_EN : 1
4929 16:44:26.857292 MD32_EN : 0
4930 16:44:26.860301 ===================================
4931 16:44:26.860871 [ANA_INIT] >>>>>>>>>>>>>>
4932 16:44:26.863952 <<<<<< [CONFIGURE PHASE]: ANA_TX
4933 16:44:26.866744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4934 16:44:26.869871 ===================================
4935 16:44:26.873700 data_rate = 1866,PCW = 0X8f00
4936 16:44:26.876708 ===================================
4937 16:44:26.879907 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4938 16:44:26.886510 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 16:44:26.894111 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4940 16:44:26.896658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4941 16:44:26.899991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4942 16:44:26.902887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4943 16:44:26.906467 [ANA_INIT] flow start
4944 16:44:26.906936 [ANA_INIT] PLL >>>>>>>>
4945 16:44:26.909683 [ANA_INIT] PLL <<<<<<<<
4946 16:44:26.913479 [ANA_INIT] MIDPI >>>>>>>>
4947 16:44:26.913951 [ANA_INIT] MIDPI <<<<<<<<
4948 16:44:26.916022 [ANA_INIT] DLL >>>>>>>>
4949 16:44:26.919596 [ANA_INIT] flow end
4950 16:44:26.923039 ============ LP4 DIFF to SE enter ============
4951 16:44:26.926805 ============ LP4 DIFF to SE exit ============
4952 16:44:26.929486 [ANA_INIT] <<<<<<<<<<<<<
4953 16:44:26.932914 [Flow] Enable top DCM control >>>>>
4954 16:44:26.936185 [Flow] Enable top DCM control <<<<<
4955 16:44:26.939530 Enable DLL master slave shuffle
4956 16:44:26.942541 ==============================================================
4957 16:44:26.946519 Gating Mode config
4958 16:44:26.952423 ==============================================================
4959 16:44:26.953005 Config description:
4960 16:44:26.962553 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4961 16:44:26.968885 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4962 16:44:26.975952 SELPH_MODE 0: By rank 1: By Phase
4963 16:44:26.978841 ==============================================================
4964 16:44:26.982639 GAT_TRACK_EN = 1
4965 16:44:26.985415 RX_GATING_MODE = 2
4966 16:44:26.988912 RX_GATING_TRACK_MODE = 2
4967 16:44:26.992820 SELPH_MODE = 1
4968 16:44:26.995490 PICG_EARLY_EN = 1
4969 16:44:26.999250 VALID_LAT_VALUE = 1
4970 16:44:27.002684 ==============================================================
4971 16:44:27.005079 Enter into Gating configuration >>>>
4972 16:44:27.009236 Exit from Gating configuration <<<<
4973 16:44:27.011766 Enter into DVFS_PRE_config >>>>>
4974 16:44:27.025628 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4975 16:44:27.028916 Exit from DVFS_PRE_config <<<<<
4976 16:44:27.032317 Enter into PICG configuration >>>>
4977 16:44:27.036406 Exit from PICG configuration <<<<
4978 16:44:27.036983 [RX_INPUT] configuration >>>>>
4979 16:44:27.038435 [RX_INPUT] configuration <<<<<
4980 16:44:27.045434 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4981 16:44:27.048716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4982 16:44:27.055459 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4983 16:44:27.061700 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4984 16:44:27.068528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4985 16:44:27.075272 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4986 16:44:27.078522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4987 16:44:27.081639 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4988 16:44:27.088015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4989 16:44:27.091292 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4990 16:44:27.094933 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4991 16:44:27.100999 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4992 16:44:27.101585 ===================================
4993 16:44:27.104740 LPDDR4 DRAM CONFIGURATION
4994 16:44:27.107794 ===================================
4995 16:44:27.111434 EX_ROW_EN[0] = 0x0
4996 16:44:27.112009 EX_ROW_EN[1] = 0x0
4997 16:44:27.114237 LP4Y_EN = 0x0
4998 16:44:27.114952 WORK_FSP = 0x0
4999 16:44:27.117793 WL = 0x3
5000 16:44:27.118399 RL = 0x3
5001 16:44:27.121057 BL = 0x2
5002 16:44:27.124720 RPST = 0x0
5003 16:44:27.125295 RD_PRE = 0x0
5004 16:44:27.127369 WR_PRE = 0x1
5005 16:44:27.127853 WR_PST = 0x0
5006 16:44:27.130925 DBI_WR = 0x0
5007 16:44:27.131403 DBI_RD = 0x0
5008 16:44:27.134235 OTF = 0x1
5009 16:44:27.137697 ===================================
5010 16:44:27.141116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5011 16:44:27.144293 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5012 16:44:27.150928 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5013 16:44:27.154085 ===================================
5014 16:44:27.154698 LPDDR4 DRAM CONFIGURATION
5015 16:44:27.157531 ===================================
5016 16:44:27.160905 EX_ROW_EN[0] = 0x10
5017 16:44:27.161719 EX_ROW_EN[1] = 0x0
5018 16:44:27.163737 LP4Y_EN = 0x0
5019 16:44:27.167250 WORK_FSP = 0x0
5020 16:44:27.167833 WL = 0x3
5021 16:44:27.171163 RL = 0x3
5022 16:44:27.171743 BL = 0x2
5023 16:44:27.174671 RPST = 0x0
5024 16:44:27.175244 RD_PRE = 0x0
5025 16:44:27.177191 WR_PRE = 0x1
5026 16:44:27.177670 WR_PST = 0x0
5027 16:44:27.179943 DBI_WR = 0x0
5028 16:44:27.180427 DBI_RD = 0x0
5029 16:44:27.183293 OTF = 0x1
5030 16:44:27.186812 ===================================
5031 16:44:27.193373 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5032 16:44:27.196588 nWR fixed to 30
5033 16:44:27.197077 [ModeRegInit_LP4] CH0 RK0
5034 16:44:27.199939 [ModeRegInit_LP4] CH0 RK1
5035 16:44:27.203026 [ModeRegInit_LP4] CH1 RK0
5036 16:44:27.206709 [ModeRegInit_LP4] CH1 RK1
5037 16:44:27.207292 match AC timing 9
5038 16:44:27.210323 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5039 16:44:27.216445 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5040 16:44:27.219999 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5041 16:44:27.226618 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5042 16:44:27.229800 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5043 16:44:27.230412 ==
5044 16:44:27.233239 Dram Type= 6, Freq= 0, CH_0, rank 0
5045 16:44:27.236524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5046 16:44:27.237099 ==
5047 16:44:27.243026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5048 16:44:27.249649 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5049 16:44:27.253097 [CA 0] Center 37 (7~68) winsize 62
5050 16:44:27.256265 [CA 1] Center 38 (8~69) winsize 62
5051 16:44:27.259460 [CA 2] Center 35 (5~66) winsize 62
5052 16:44:27.262996 [CA 3] Center 35 (4~66) winsize 63
5053 16:44:27.265919 [CA 4] Center 34 (4~65) winsize 62
5054 16:44:27.269864 [CA 5] Center 33 (3~64) winsize 62
5055 16:44:27.270482
5056 16:44:27.272922 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5057 16:44:27.273497
5058 16:44:27.276271 [CATrainingPosCal] consider 1 rank data
5059 16:44:27.279496 u2DelayCellTimex100 = 270/100 ps
5060 16:44:27.282815 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5061 16:44:27.286204 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 16:44:27.289479 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5063 16:44:27.293148 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5064 16:44:27.295795 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5065 16:44:27.299317 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 16:44:27.299800
5067 16:44:27.305828 CA PerBit enable=1, Macro0, CA PI delay=33
5068 16:44:27.306425
5069 16:44:27.306810 [CBTSetCACLKResult] CA Dly = 33
5070 16:44:27.309336 CS Dly: 6 (0~37)
5071 16:44:27.309898 ==
5072 16:44:27.312913 Dram Type= 6, Freq= 0, CH_0, rank 1
5073 16:44:27.315772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5074 16:44:27.316246 ==
5075 16:44:27.322644 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5076 16:44:27.329312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5077 16:44:27.332688 [CA 0] Center 38 (8~69) winsize 62
5078 16:44:27.335583 [CA 1] Center 38 (8~69) winsize 62
5079 16:44:27.339264 [CA 2] Center 36 (6~66) winsize 61
5080 16:44:27.342400 [CA 3] Center 35 (5~66) winsize 62
5081 16:44:27.345561 [CA 4] Center 34 (4~65) winsize 62
5082 16:44:27.349081 [CA 5] Center 34 (4~65) winsize 62
5083 16:44:27.349648
5084 16:44:27.352427 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5085 16:44:27.352988
5086 16:44:27.355024 [CATrainingPosCal] consider 2 rank data
5087 16:44:27.358689 u2DelayCellTimex100 = 270/100 ps
5088 16:44:27.362784 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5089 16:44:27.365508 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5090 16:44:27.369127 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5091 16:44:27.372087 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5092 16:44:27.378717 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5093 16:44:27.381735 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5094 16:44:27.382295
5095 16:44:27.385114 CA PerBit enable=1, Macro0, CA PI delay=34
5096 16:44:27.385678
5097 16:44:27.388588 [CBTSetCACLKResult] CA Dly = 34
5098 16:44:27.389156 CS Dly: 7 (0~39)
5099 16:44:27.389536
5100 16:44:27.391904 ----->DramcWriteLeveling(PI) begin...
5101 16:44:27.392381 ==
5102 16:44:27.394869 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 16:44:27.402032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 16:44:27.402540 ==
5105 16:44:27.404762 Write leveling (Byte 0): 34 => 34
5106 16:44:27.408187 Write leveling (Byte 1): 30 => 30
5107 16:44:27.408659 DramcWriteLeveling(PI) end<-----
5108 16:44:27.409031
5109 16:44:27.411318 ==
5110 16:44:27.414775 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 16:44:27.418098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 16:44:27.418629 ==
5113 16:44:27.422287 [Gating] SW mode calibration
5114 16:44:27.427970 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5115 16:44:27.431570 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5116 16:44:27.437994 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5117 16:44:27.441274 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 16:44:27.445122 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 16:44:27.451303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 16:44:27.454445 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 16:44:27.457975 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5122 16:44:27.464603 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5123 16:44:27.468168 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
5124 16:44:27.471299 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
5125 16:44:27.477918 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 16:44:27.481162 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 16:44:27.484345 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 16:44:27.491252 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 16:44:27.493781 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5130 16:44:27.497286 0 15 24 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
5131 16:44:27.503816 0 15 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
5132 16:44:27.507056 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5133 16:44:27.510568 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 16:44:27.517114 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 16:44:27.520561 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 16:44:27.524149 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 16:44:27.530024 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5138 16:44:27.533863 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5139 16:44:27.537156 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 16:44:27.543591 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 16:44:27.546781 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 16:44:27.550330 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 16:44:27.556740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 16:44:27.559887 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 16:44:27.563295 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 16:44:27.569874 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 16:44:27.573155 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 16:44:27.576654 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 16:44:27.583716 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 16:44:27.586738 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 16:44:27.589932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 16:44:27.596574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 16:44:27.599959 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 16:44:27.603166 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 16:44:27.609796 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5156 16:44:27.613139 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5157 16:44:27.617254 Total UI for P1: 0, mck2ui 16
5158 16:44:27.619959 best dqsien dly found for B0: ( 1, 2, 28)
5159 16:44:27.622919 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5160 16:44:27.626452 Total UI for P1: 0, mck2ui 16
5161 16:44:27.630002 best dqsien dly found for B1: ( 1, 3, 0)
5162 16:44:27.633197 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5163 16:44:27.636820 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5164 16:44:27.637401
5165 16:44:27.639462 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5166 16:44:27.646252 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5167 16:44:27.646853 [Gating] SW calibration Done
5168 16:44:27.647226 ==
5169 16:44:27.649932 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 16:44:27.656158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 16:44:27.656735 ==
5172 16:44:27.657105 RX Vref Scan: 0
5173 16:44:27.657449
5174 16:44:27.659611 RX Vref 0 -> 0, step: 1
5175 16:44:27.660178
5176 16:44:27.663023 RX Delay -80 -> 252, step: 8
5177 16:44:27.666442 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5178 16:44:27.669445 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5179 16:44:27.672981 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5180 16:44:27.679378 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5181 16:44:27.682986 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5182 16:44:27.686117 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5183 16:44:27.689735 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5184 16:44:27.693116 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5185 16:44:27.696135 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5186 16:44:27.702650 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5187 16:44:27.706089 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5188 16:44:27.708783 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5189 16:44:27.712489 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5190 16:44:27.715680 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5191 16:44:27.719036 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5192 16:44:27.725741 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5193 16:44:27.726314 ==
5194 16:44:27.728739 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 16:44:27.732321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 16:44:27.732810 ==
5197 16:44:27.733180 DQS Delay:
5198 16:44:27.735466 DQS0 = 0, DQS1 = 0
5199 16:44:27.735935 DQM Delay:
5200 16:44:27.738521 DQM0 = 105, DQM1 = 90
5201 16:44:27.738993 DQ Delay:
5202 16:44:27.742519 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5203 16:44:27.745362 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5204 16:44:27.748866 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5205 16:44:27.752499 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5206 16:44:27.753073
5207 16:44:27.753445
5208 16:44:27.753791 ==
5209 16:44:27.754961 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 16:44:27.761892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 16:44:27.762502 ==
5212 16:44:27.762887
5213 16:44:27.763234
5214 16:44:27.763564 TX Vref Scan disable
5215 16:44:27.765475 == TX Byte 0 ==
5216 16:44:27.768969 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5217 16:44:27.775382 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5218 16:44:27.775968 == TX Byte 1 ==
5219 16:44:27.779016 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5220 16:44:27.784934 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5221 16:44:27.785513 ==
5222 16:44:27.788567 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 16:44:27.791807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 16:44:27.792385 ==
5225 16:44:27.792759
5226 16:44:27.793099
5227 16:44:27.795142 TX Vref Scan disable
5228 16:44:27.799083 == TX Byte 0 ==
5229 16:44:27.801568 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5230 16:44:27.804968 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5231 16:44:27.808155 == TX Byte 1 ==
5232 16:44:27.812089 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5233 16:44:27.814878 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5234 16:44:27.815351
5235 16:44:27.815720 [DATLAT]
5236 16:44:27.818578 Freq=933, CH0 RK0
5237 16:44:27.819155
5238 16:44:27.819528 DATLAT Default: 0xd
5239 16:44:27.821631 0, 0xFFFF, sum = 0
5240 16:44:27.824892 1, 0xFFFF, sum = 0
5241 16:44:27.825472 2, 0xFFFF, sum = 0
5242 16:44:27.828547 3, 0xFFFF, sum = 0
5243 16:44:27.829135 4, 0xFFFF, sum = 0
5244 16:44:27.831470 5, 0xFFFF, sum = 0
5245 16:44:27.831946 6, 0xFFFF, sum = 0
5246 16:44:27.834371 7, 0xFFFF, sum = 0
5247 16:44:27.834856 8, 0xFFFF, sum = 0
5248 16:44:27.837999 9, 0xFFFF, sum = 0
5249 16:44:27.838618 10, 0x0, sum = 1
5250 16:44:27.841572 11, 0x0, sum = 2
5251 16:44:27.842049 12, 0x0, sum = 3
5252 16:44:27.844647 13, 0x0, sum = 4
5253 16:44:27.845124 best_step = 11
5254 16:44:27.845495
5255 16:44:27.845839 ==
5256 16:44:27.848372 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 16:44:27.851349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 16:44:27.851822 ==
5259 16:44:27.855050 RX Vref Scan: 1
5260 16:44:27.855623
5261 16:44:27.857735 RX Vref 0 -> 0, step: 1
5262 16:44:27.858204
5263 16:44:27.858625 RX Delay -53 -> 252, step: 4
5264 16:44:27.858977
5265 16:44:27.861099 Set Vref, RX VrefLevel [Byte0]: 59
5266 16:44:27.865210 [Byte1]: 49
5267 16:44:27.869449
5268 16:44:27.870016 Final RX Vref Byte 0 = 59 to rank0
5269 16:44:27.872702 Final RX Vref Byte 1 = 49 to rank0
5270 16:44:27.876169 Final RX Vref Byte 0 = 59 to rank1
5271 16:44:27.879390 Final RX Vref Byte 1 = 49 to rank1==
5272 16:44:27.882851 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 16:44:27.889672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 16:44:27.890242 ==
5275 16:44:27.890645 DQS Delay:
5276 16:44:27.890997 DQS0 = 0, DQS1 = 0
5277 16:44:27.892793 DQM Delay:
5278 16:44:27.893368 DQM0 = 107, DQM1 = 92
5279 16:44:27.896001 DQ Delay:
5280 16:44:27.899390 DQ0 =108, DQ1 =108, DQ2 =104, DQ3 =106
5281 16:44:27.902618 DQ4 =106, DQ5 =98, DQ6 =118, DQ7 =114
5282 16:44:27.905846 DQ8 =86, DQ9 =78, DQ10 =92, DQ11 =90
5283 16:44:27.909121 DQ12 =96, DQ13 =94, DQ14 =104, DQ15 =98
5284 16:44:27.909799
5285 16:44:27.910178
5286 16:44:27.915491 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5287 16:44:27.918558 CH0 RK0: MR19=505, MR18=231F
5288 16:44:27.925490 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5289 16:44:27.926066
5290 16:44:27.928406 ----->DramcWriteLeveling(PI) begin...
5291 16:44:27.928904 ==
5292 16:44:27.932051 Dram Type= 6, Freq= 0, CH_0, rank 1
5293 16:44:27.935404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 16:44:27.939107 ==
5295 16:44:27.939677 Write leveling (Byte 0): 31 => 31
5296 16:44:27.941521 Write leveling (Byte 1): 29 => 29
5297 16:44:27.944993 DramcWriteLeveling(PI) end<-----
5298 16:44:27.945469
5299 16:44:27.945839 ==
5300 16:44:27.948758 Dram Type= 6, Freq= 0, CH_0, rank 1
5301 16:44:27.955637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 16:44:27.956207 ==
5303 16:44:27.958785 [Gating] SW mode calibration
5304 16:44:27.965752 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5305 16:44:27.968527 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5306 16:44:27.975169 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 16:44:27.978728 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 16:44:27.981518 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 16:44:27.988207 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 16:44:27.991233 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 16:44:27.994578 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5312 16:44:28.001637 0 14 24 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
5313 16:44:28.004616 0 14 28 | B1->B0 | 2f2f 2727 | 0 0 | (1 1) (0 0)
5314 16:44:28.007745 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 16:44:28.014386 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 16:44:28.017937 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 16:44:28.021374 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 16:44:28.027911 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5319 16:44:28.030979 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5320 16:44:28.034281 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5321 16:44:28.040796 0 15 28 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
5322 16:44:28.044189 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 16:44:28.047781 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 16:44:28.054436 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 16:44:28.058176 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 16:44:28.061297 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 16:44:28.066987 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5328 16:44:28.070442 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5329 16:44:28.073715 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5330 16:44:28.080869 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 16:44:28.083749 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 16:44:28.087122 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 16:44:28.093829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 16:44:28.096754 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 16:44:28.100623 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 16:44:28.107316 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 16:44:28.110198 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 16:44:28.113666 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 16:44:28.120119 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 16:44:28.123817 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 16:44:28.126519 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 16:44:28.133488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 16:44:28.136877 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 16:44:28.140048 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 16:44:28.146602 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5346 16:44:28.147150 Total UI for P1: 0, mck2ui 16
5347 16:44:28.149900 best dqsien dly found for B0: ( 1, 2, 26)
5348 16:44:28.156413 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 16:44:28.159977 Total UI for P1: 0, mck2ui 16
5350 16:44:28.162731 best dqsien dly found for B1: ( 1, 2, 28)
5351 16:44:28.167051 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5352 16:44:28.169481 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5353 16:44:28.170044
5354 16:44:28.172720 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5355 16:44:28.176255 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5356 16:44:28.179341 [Gating] SW calibration Done
5357 16:44:28.179814 ==
5358 16:44:28.182766 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 16:44:28.186168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 16:44:28.186780 ==
5361 16:44:28.190187 RX Vref Scan: 0
5362 16:44:28.190802
5363 16:44:28.192602 RX Vref 0 -> 0, step: 1
5364 16:44:28.193072
5365 16:44:28.193441 RX Delay -80 -> 252, step: 8
5366 16:44:28.199577 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5367 16:44:28.202711 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5368 16:44:28.206099 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5369 16:44:28.209157 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5370 16:44:28.212820 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5371 16:44:28.219246 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5372 16:44:28.222493 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5373 16:44:28.225825 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5374 16:44:28.229077 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5375 16:44:28.232388 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5376 16:44:28.235957 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5377 16:44:28.242021 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5378 16:44:28.245406 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5379 16:44:28.249284 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5380 16:44:28.252062 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5381 16:44:28.255798 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5382 16:44:28.256376 ==
5383 16:44:28.258973 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 16:44:28.265644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 16:44:28.266214 ==
5386 16:44:28.266648 DQS Delay:
5387 16:44:28.268994 DQS0 = 0, DQS1 = 0
5388 16:44:28.269629 DQM Delay:
5389 16:44:28.270007 DQM0 = 104, DQM1 = 90
5390 16:44:28.272500 DQ Delay:
5391 16:44:28.275150 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5392 16:44:28.279114 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5393 16:44:28.281829 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5394 16:44:28.284947 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5395 16:44:28.285418
5396 16:44:28.285786
5397 16:44:28.286128 ==
5398 16:44:28.288547 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 16:44:28.291775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 16:44:28.292264 ==
5401 16:44:28.292640
5402 16:44:28.292985
5403 16:44:28.295022 TX Vref Scan disable
5404 16:44:28.298810 == TX Byte 0 ==
5405 16:44:28.302224 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5406 16:44:28.305277 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5407 16:44:28.308086 == TX Byte 1 ==
5408 16:44:28.312103 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5409 16:44:28.314999 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5410 16:44:28.315567 ==
5411 16:44:28.318317 Dram Type= 6, Freq= 0, CH_0, rank 1
5412 16:44:28.325082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5413 16:44:28.325650 ==
5414 16:44:28.326023
5415 16:44:28.326415
5416 16:44:28.326762 TX Vref Scan disable
5417 16:44:28.328981 == TX Byte 0 ==
5418 16:44:28.332879 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5419 16:44:28.339094 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5420 16:44:28.339660 == TX Byte 1 ==
5421 16:44:28.342624 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5422 16:44:28.348727 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5423 16:44:28.349297
5424 16:44:28.349673 [DATLAT]
5425 16:44:28.350021 Freq=933, CH0 RK1
5426 16:44:28.350378
5427 16:44:28.352146 DATLAT Default: 0xb
5428 16:44:28.355130 0, 0xFFFF, sum = 0
5429 16:44:28.355705 1, 0xFFFF, sum = 0
5430 16:44:28.359050 2, 0xFFFF, sum = 0
5431 16:44:28.359624 3, 0xFFFF, sum = 0
5432 16:44:28.361566 4, 0xFFFF, sum = 0
5433 16:44:28.362136 5, 0xFFFF, sum = 0
5434 16:44:28.364966 6, 0xFFFF, sum = 0
5435 16:44:28.365535 7, 0xFFFF, sum = 0
5436 16:44:28.368830 8, 0xFFFF, sum = 0
5437 16:44:28.369401 9, 0xFFFF, sum = 0
5438 16:44:28.371500 10, 0x0, sum = 1
5439 16:44:28.372074 11, 0x0, sum = 2
5440 16:44:28.375033 12, 0x0, sum = 3
5441 16:44:28.375607 13, 0x0, sum = 4
5442 16:44:28.378066 best_step = 11
5443 16:44:28.378657
5444 16:44:28.379033 ==
5445 16:44:28.381180 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 16:44:28.384707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 16:44:28.385279 ==
5448 16:44:28.385654 RX Vref Scan: 0
5449 16:44:28.388373
5450 16:44:28.388934 RX Vref 0 -> 0, step: 1
5451 16:44:28.389310
5452 16:44:28.391269 RX Delay -53 -> 252, step: 4
5453 16:44:28.397883 iDelay=203, Bit 0, Center 102 (15 ~ 190) 176
5454 16:44:28.400832 iDelay=203, Bit 1, Center 106 (19 ~ 194) 176
5455 16:44:28.404733 iDelay=203, Bit 2, Center 102 (15 ~ 190) 176
5456 16:44:28.407645 iDelay=203, Bit 3, Center 98 (15 ~ 182) 168
5457 16:44:28.411452 iDelay=203, Bit 4, Center 104 (19 ~ 190) 172
5458 16:44:28.418562 iDelay=203, Bit 5, Center 98 (11 ~ 186) 176
5459 16:44:28.421223 iDelay=203, Bit 6, Center 114 (27 ~ 202) 176
5460 16:44:28.424307 iDelay=203, Bit 7, Center 112 (27 ~ 198) 172
5461 16:44:28.427326 iDelay=203, Bit 8, Center 86 (3 ~ 170) 168
5462 16:44:28.430850 iDelay=203, Bit 9, Center 80 (-1 ~ 162) 164
5463 16:44:28.437698 iDelay=203, Bit 10, Center 94 (11 ~ 178) 168
5464 16:44:28.440718 iDelay=203, Bit 11, Center 92 (11 ~ 174) 164
5465 16:44:28.444900 iDelay=203, Bit 12, Center 96 (11 ~ 182) 172
5466 16:44:28.447834 iDelay=203, Bit 13, Center 94 (11 ~ 178) 168
5467 16:44:28.450607 iDelay=203, Bit 14, Center 100 (15 ~ 186) 172
5468 16:44:28.457471 iDelay=203, Bit 15, Center 100 (19 ~ 182) 164
5469 16:44:28.458043 ==
5470 16:44:28.460805 Dram Type= 6, Freq= 0, CH_0, rank 1
5471 16:44:28.463698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5472 16:44:28.464267 ==
5473 16:44:28.464643 DQS Delay:
5474 16:44:28.467513 DQS0 = 0, DQS1 = 0
5475 16:44:28.467982 DQM Delay:
5476 16:44:28.470478 DQM0 = 104, DQM1 = 92
5477 16:44:28.470950 DQ Delay:
5478 16:44:28.474189 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =98
5479 16:44:28.477439 DQ4 =104, DQ5 =98, DQ6 =114, DQ7 =112
5480 16:44:28.480623 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5481 16:44:28.483597 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =100
5482 16:44:28.484164
5483 16:44:28.484584
5484 16:44:28.493408 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 407 ps
5485 16:44:28.496678 CH0 RK1: MR19=505, MR18=2E0E
5486 16:44:28.499981 CH0_RK1: MR19=0x505, MR18=0x2E0E, DQSOSC=407, MR23=63, INC=65, DEC=43
5487 16:44:28.503078 [RxdqsGatingPostProcess] freq 933
5488 16:44:28.510134 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5489 16:44:28.513853 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 16:44:28.516536 best DQS1 dly(2T, 0.5T) = (0, 11)
5491 16:44:28.519742 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 16:44:28.524047 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5493 16:44:28.526487 best DQS0 dly(2T, 0.5T) = (0, 10)
5494 16:44:28.529897 best DQS1 dly(2T, 0.5T) = (0, 10)
5495 16:44:28.533171 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5496 16:44:28.536269 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5497 16:44:28.539700 Pre-setting of DQS Precalculation
5498 16:44:28.543806 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5499 16:44:28.544385 ==
5500 16:44:28.546642 Dram Type= 6, Freq= 0, CH_1, rank 0
5501 16:44:28.549735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 16:44:28.550306 ==
5503 16:44:28.556285 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5504 16:44:28.563336 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5505 16:44:28.566327 [CA 0] Center 37 (7~68) winsize 62
5506 16:44:28.569907 [CA 1] Center 37 (7~68) winsize 62
5507 16:44:28.572937 [CA 2] Center 35 (5~66) winsize 62
5508 16:44:28.576186 [CA 3] Center 34 (4~65) winsize 62
5509 16:44:28.580000 [CA 4] Center 35 (5~66) winsize 62
5510 16:44:28.582730 [CA 5] Center 34 (4~65) winsize 62
5511 16:44:28.583299
5512 16:44:28.586119 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5513 16:44:28.586712
5514 16:44:28.589524 [CATrainingPosCal] consider 1 rank data
5515 16:44:28.592862 u2DelayCellTimex100 = 270/100 ps
5516 16:44:28.596094 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5517 16:44:28.599073 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5518 16:44:28.603000 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5519 16:44:28.605917 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5520 16:44:28.612581 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5521 16:44:28.615794 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5522 16:44:28.616264
5523 16:44:28.619126 CA PerBit enable=1, Macro0, CA PI delay=34
5524 16:44:28.619638
5525 16:44:28.622861 [CBTSetCACLKResult] CA Dly = 34
5526 16:44:28.623509 CS Dly: 6 (0~37)
5527 16:44:28.624039 ==
5528 16:44:28.625330 Dram Type= 6, Freq= 0, CH_1, rank 1
5529 16:44:28.631912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 16:44:28.632473 ==
5531 16:44:28.635772 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5532 16:44:28.642655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5533 16:44:28.645683 [CA 0] Center 38 (8~69) winsize 62
5534 16:44:28.648715 [CA 1] Center 38 (8~69) winsize 62
5535 16:44:28.652262 [CA 2] Center 36 (6~66) winsize 61
5536 16:44:28.655319 [CA 3] Center 35 (5~65) winsize 61
5537 16:44:28.658560 [CA 4] Center 35 (5~66) winsize 62
5538 16:44:28.661858 [CA 5] Center 35 (5~65) winsize 61
5539 16:44:28.662467
5540 16:44:28.665356 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5541 16:44:28.665914
5542 16:44:28.668747 [CATrainingPosCal] consider 2 rank data
5543 16:44:28.672139 u2DelayCellTimex100 = 270/100 ps
5544 16:44:28.675475 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5545 16:44:28.678519 CA1 delay=38 (8~68),Diff = 3 PI (18 cell)
5546 16:44:28.685390 CA2 delay=36 (6~66),Diff = 1 PI (6 cell)
5547 16:44:28.688687 CA3 delay=35 (5~65),Diff = 0 PI (0 cell)
5548 16:44:28.691989 CA4 delay=35 (5~66),Diff = 0 PI (0 cell)
5549 16:44:28.695462 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5550 16:44:28.696019
5551 16:44:28.698528 CA PerBit enable=1, Macro0, CA PI delay=35
5552 16:44:28.699097
5553 16:44:28.701698 [CBTSetCACLKResult] CA Dly = 35
5554 16:44:28.702165 CS Dly: 7 (0~39)
5555 16:44:28.702589
5556 16:44:28.705074 ----->DramcWriteLeveling(PI) begin...
5557 16:44:28.708216 ==
5558 16:44:28.711731 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 16:44:28.714936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 16:44:28.715499 ==
5561 16:44:28.717806 Write leveling (Byte 0): 25 => 25
5562 16:44:28.721580 Write leveling (Byte 1): 27 => 27
5563 16:44:28.724519 DramcWriteLeveling(PI) end<-----
5564 16:44:28.724982
5565 16:44:28.725347 ==
5566 16:44:28.727734 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 16:44:28.730982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 16:44:28.731450 ==
5569 16:44:28.734414 [Gating] SW mode calibration
5570 16:44:28.741213 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5571 16:44:28.747851 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5572 16:44:28.751169 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 16:44:28.754635 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 16:44:28.761009 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 16:44:28.764234 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 16:44:28.768296 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5577 16:44:28.774253 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5578 16:44:28.777612 0 14 24 | B1->B0 | 3131 3131 | 0 0 | (0 1) (0 1)
5579 16:44:28.780853 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5580 16:44:28.787573 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 16:44:28.790886 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 16:44:28.794190 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 16:44:28.800875 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 16:44:28.804056 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5585 16:44:28.808096 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5586 16:44:28.813825 0 15 24 | B1->B0 | 2727 2c2c | 0 0 | (0 0) (0 0)
5587 16:44:28.817219 0 15 28 | B1->B0 | 4141 4343 | 0 0 | (0 0) (0 0)
5588 16:44:28.820169 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 16:44:28.828181 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 16:44:28.829980 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 16:44:28.833825 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 16:44:28.840397 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5593 16:44:28.843918 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5594 16:44:28.846947 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5595 16:44:28.854169 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 16:44:28.856848 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 16:44:28.860331 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 16:44:28.866700 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 16:44:28.870080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 16:44:28.873600 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 16:44:28.880056 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 16:44:28.883524 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 16:44:28.886174 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 16:44:28.893156 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 16:44:28.896559 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 16:44:28.899812 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 16:44:28.906339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 16:44:28.909585 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 16:44:28.912545 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5610 16:44:28.919504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5611 16:44:28.922829 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5612 16:44:28.926126 Total UI for P1: 0, mck2ui 16
5613 16:44:28.929449 best dqsien dly found for B0: ( 1, 2, 22)
5614 16:44:28.933233 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5615 16:44:28.936052 Total UI for P1: 0, mck2ui 16
5616 16:44:28.939199 best dqsien dly found for B1: ( 1, 2, 26)
5617 16:44:28.942550 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5618 16:44:28.946224 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5619 16:44:28.946718
5620 16:44:28.948872 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5621 16:44:28.955762 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5622 16:44:28.956340 [Gating] SW calibration Done
5623 16:44:28.956714 ==
5624 16:44:28.958959 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 16:44:28.965828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 16:44:28.966422 ==
5627 16:44:28.966800 RX Vref Scan: 0
5628 16:44:28.967149
5629 16:44:28.969841 RX Vref 0 -> 0, step: 1
5630 16:44:28.970311
5631 16:44:28.972477 RX Delay -80 -> 252, step: 8
5632 16:44:28.975714 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5633 16:44:28.978551 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5634 16:44:28.982059 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5635 16:44:28.989131 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5636 16:44:28.992316 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5637 16:44:28.995204 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5638 16:44:28.998788 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5639 16:44:29.002021 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5640 16:44:29.005002 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5641 16:44:29.011836 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5642 16:44:29.015037 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5643 16:44:29.019208 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5644 16:44:29.022229 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5645 16:44:29.025291 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5646 16:44:29.031334 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5647 16:44:29.035041 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5648 16:44:29.035507 ==
5649 16:44:29.037916 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 16:44:29.041721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 16:44:29.042208 ==
5652 16:44:29.044800 DQS Delay:
5653 16:44:29.045366 DQS0 = 0, DQS1 = 0
5654 16:44:29.045737 DQM Delay:
5655 16:44:29.047798 DQM0 = 102, DQM1 = 95
5656 16:44:29.048338 DQ Delay:
5657 16:44:29.051016 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5658 16:44:29.054692 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5659 16:44:29.058006 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5660 16:44:29.061260 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5661 16:44:29.061833
5662 16:44:29.062207
5663 16:44:29.064159 ==
5664 16:44:29.067892 Dram Type= 6, Freq= 0, CH_1, rank 0
5665 16:44:29.071074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5666 16:44:29.071550 ==
5667 16:44:29.071920
5668 16:44:29.072261
5669 16:44:29.074114 TX Vref Scan disable
5670 16:44:29.074630 == TX Byte 0 ==
5671 16:44:29.081009 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5672 16:44:29.084376 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5673 16:44:29.084952 == TX Byte 1 ==
5674 16:44:29.090948 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5675 16:44:29.094347 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5676 16:44:29.094948 ==
5677 16:44:29.097712 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 16:44:29.100835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 16:44:29.101414 ==
5680 16:44:29.101789
5681 16:44:29.102133
5682 16:44:29.104087 TX Vref Scan disable
5683 16:44:29.107805 == TX Byte 0 ==
5684 16:44:29.110446 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5685 16:44:29.113885 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5686 16:44:29.117619 == TX Byte 1 ==
5687 16:44:29.120748 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5688 16:44:29.123645 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5689 16:44:29.124117
5690 16:44:29.127034 [DATLAT]
5691 16:44:29.127504 Freq=933, CH1 RK0
5692 16:44:29.127874
5693 16:44:29.130458 DATLAT Default: 0xd
5694 16:44:29.130953 0, 0xFFFF, sum = 0
5695 16:44:29.133922 1, 0xFFFF, sum = 0
5696 16:44:29.134547 2, 0xFFFF, sum = 0
5697 16:44:29.137233 3, 0xFFFF, sum = 0
5698 16:44:29.137803 4, 0xFFFF, sum = 0
5699 16:44:29.140166 5, 0xFFFF, sum = 0
5700 16:44:29.140644 6, 0xFFFF, sum = 0
5701 16:44:29.143580 7, 0xFFFF, sum = 0
5702 16:44:29.144058 8, 0xFFFF, sum = 0
5703 16:44:29.146806 9, 0xFFFF, sum = 0
5704 16:44:29.147285 10, 0x0, sum = 1
5705 16:44:29.150129 11, 0x0, sum = 2
5706 16:44:29.150651 12, 0x0, sum = 3
5707 16:44:29.153632 13, 0x0, sum = 4
5708 16:44:29.154216 best_step = 11
5709 16:44:29.154667
5710 16:44:29.155021 ==
5711 16:44:29.157002 Dram Type= 6, Freq= 0, CH_1, rank 0
5712 16:44:29.163468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5713 16:44:29.164026 ==
5714 16:44:29.164417 RX Vref Scan: 1
5715 16:44:29.164767
5716 16:44:29.166672 RX Vref 0 -> 0, step: 1
5717 16:44:29.167182
5718 16:44:29.169981 RX Delay -53 -> 252, step: 4
5719 16:44:29.170517
5720 16:44:29.173657 Set Vref, RX VrefLevel [Byte0]: 52
5721 16:44:29.176847 [Byte1]: 52
5722 16:44:29.177411
5723 16:44:29.180126 Final RX Vref Byte 0 = 52 to rank0
5724 16:44:29.183091 Final RX Vref Byte 1 = 52 to rank0
5725 16:44:29.187606 Final RX Vref Byte 0 = 52 to rank1
5726 16:44:29.190303 Final RX Vref Byte 1 = 52 to rank1==
5727 16:44:29.193140 Dram Type= 6, Freq= 0, CH_1, rank 0
5728 16:44:29.196324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5729 16:44:29.196896 ==
5730 16:44:29.199569 DQS Delay:
5731 16:44:29.200137 DQS0 = 0, DQS1 = 0
5732 16:44:29.202806 DQM Delay:
5733 16:44:29.203274 DQM0 = 105, DQM1 = 97
5734 16:44:29.206445 DQ Delay:
5735 16:44:29.206864 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5736 16:44:29.213089 DQ4 =104, DQ5 =114, DQ6 =114, DQ7 =104
5737 16:44:29.216033 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =92
5738 16:44:29.219494 DQ12 =108, DQ13 =102, DQ14 =102, DQ15 =104
5739 16:44:29.220059
5740 16:44:29.220425
5741 16:44:29.226618 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5742 16:44:29.230308 CH1 RK0: MR19=505, MR18=1A32
5743 16:44:29.236147 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5744 16:44:29.236711
5745 16:44:29.239074 ----->DramcWriteLeveling(PI) begin...
5746 16:44:29.239545 ==
5747 16:44:29.242518 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 16:44:29.246012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 16:44:29.246622 ==
5750 16:44:29.249234 Write leveling (Byte 0): 29 => 29
5751 16:44:29.252620 Write leveling (Byte 1): 27 => 27
5752 16:44:29.255855 DramcWriteLeveling(PI) end<-----
5753 16:44:29.256419
5754 16:44:29.256785 ==
5755 16:44:29.260875 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 16:44:29.262105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 16:44:29.265503 ==
5758 16:44:29.266104 [Gating] SW mode calibration
5759 16:44:29.275444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5760 16:44:29.278921 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5761 16:44:29.282426 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 16:44:29.288943 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 16:44:29.292072 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 16:44:29.295409 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 16:44:29.302294 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5766 16:44:29.305279 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5767 16:44:29.308683 0 14 24 | B1->B0 | 2f2f 3434 | 0 0 | (0 1) (0 1)
5768 16:44:29.315500 0 14 28 | B1->B0 | 2626 2929 | 0 0 | (0 0) (0 0)
5769 16:44:29.318493 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5770 16:44:29.321935 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 16:44:29.328722 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 16:44:29.331868 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 16:44:29.335257 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5774 16:44:29.341648 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5775 16:44:29.344869 0 15 24 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
5776 16:44:29.348533 0 15 28 | B1->B0 | 3c3c 3b3b | 0 1 | (0 0) (0 0)
5777 16:44:29.354842 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 16:44:29.358497 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 16:44:29.361626 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 16:44:29.368343 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 16:44:29.371202 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5782 16:44:29.374823 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5783 16:44:29.381471 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5784 16:44:29.384540 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5785 16:44:29.387771 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 16:44:29.395170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 16:44:29.398154 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 16:44:29.401741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 16:44:29.408252 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 16:44:29.411228 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 16:44:29.414669 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 16:44:29.421584 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 16:44:29.424571 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 16:44:29.427812 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 16:44:29.434237 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 16:44:29.437668 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 16:44:29.440858 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 16:44:29.447343 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 16:44:29.450460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5800 16:44:29.454088 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5801 16:44:29.457050 Total UI for P1: 0, mck2ui 16
5802 16:44:29.460448 best dqsien dly found for B1: ( 1, 2, 26)
5803 16:44:29.466938 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5804 16:44:29.467496 Total UI for P1: 0, mck2ui 16
5805 16:44:29.473846 best dqsien dly found for B0: ( 1, 2, 26)
5806 16:44:29.476972 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5807 16:44:29.480237 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5808 16:44:29.480705
5809 16:44:29.484136 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5810 16:44:29.487059 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5811 16:44:29.490222 [Gating] SW calibration Done
5812 16:44:29.490725 ==
5813 16:44:29.493438 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 16:44:29.496986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 16:44:29.497457 ==
5816 16:44:29.500363 RX Vref Scan: 0
5817 16:44:29.500828
5818 16:44:29.501195 RX Vref 0 -> 0, step: 1
5819 16:44:29.501571
5820 16:44:29.503552 RX Delay -80 -> 252, step: 8
5821 16:44:29.507117 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5822 16:44:29.513698 iDelay=200, Bit 1, Center 95 (8 ~ 183) 176
5823 16:44:29.517104 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5824 16:44:29.520297 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5825 16:44:29.523417 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5826 16:44:29.526558 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5827 16:44:29.530728 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5828 16:44:29.536454 iDelay=200, Bit 7, Center 99 (8 ~ 191) 184
5829 16:44:29.540370 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5830 16:44:29.543352 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5831 16:44:29.546844 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5832 16:44:29.550431 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5833 16:44:29.556601 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5834 16:44:29.559830 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5835 16:44:29.563052 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5836 16:44:29.566449 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5837 16:44:29.567022 ==
5838 16:44:29.570122 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 16:44:29.573491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 16:44:29.576651 ==
5841 16:44:29.577216 DQS Delay:
5842 16:44:29.577589 DQS0 = 0, DQS1 = 0
5843 16:44:29.579694 DQM Delay:
5844 16:44:29.580312 DQM0 = 101, DQM1 = 95
5845 16:44:29.583326 DQ Delay:
5846 16:44:29.586440 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5847 16:44:29.589714 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5848 16:44:29.592658 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =87
5849 16:44:29.596245 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5850 16:44:29.596711
5851 16:44:29.597076
5852 16:44:29.597418 ==
5853 16:44:29.599059 Dram Type= 6, Freq= 0, CH_1, rank 1
5854 16:44:29.602598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5855 16:44:29.603068 ==
5856 16:44:29.603433
5857 16:44:29.603770
5858 16:44:29.606447 TX Vref Scan disable
5859 16:44:29.609345 == TX Byte 0 ==
5860 16:44:29.612966 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5861 16:44:29.615723 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5862 16:44:29.618945 == TX Byte 1 ==
5863 16:44:29.622584 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5864 16:44:29.625760 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5865 16:44:29.626231 ==
5866 16:44:29.628944 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 16:44:29.632102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 16:44:29.635506 ==
5869 16:44:29.636069
5870 16:44:29.636436
5871 16:44:29.636776 TX Vref Scan disable
5872 16:44:29.639441 == TX Byte 0 ==
5873 16:44:29.643158 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5874 16:44:29.648977 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5875 16:44:29.649447 == TX Byte 1 ==
5876 16:44:29.652726 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 16:44:29.659205 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 16:44:29.659770
5879 16:44:29.660140 [DATLAT]
5880 16:44:29.660482 Freq=933, CH1 RK1
5881 16:44:29.660811
5882 16:44:29.663205 DATLAT Default: 0xb
5883 16:44:29.665658 0, 0xFFFF, sum = 0
5884 16:44:29.666231 1, 0xFFFF, sum = 0
5885 16:44:29.669117 2, 0xFFFF, sum = 0
5886 16:44:29.669683 3, 0xFFFF, sum = 0
5887 16:44:29.672288 4, 0xFFFF, sum = 0
5888 16:44:29.672852 5, 0xFFFF, sum = 0
5889 16:44:29.676017 6, 0xFFFF, sum = 0
5890 16:44:29.676585 7, 0xFFFF, sum = 0
5891 16:44:29.679152 8, 0xFFFF, sum = 0
5892 16:44:29.679722 9, 0xFFFF, sum = 0
5893 16:44:29.682632 10, 0x0, sum = 1
5894 16:44:29.683205 11, 0x0, sum = 2
5895 16:44:29.685553 12, 0x0, sum = 3
5896 16:44:29.686122 13, 0x0, sum = 4
5897 16:44:29.688968 best_step = 11
5898 16:44:29.689531
5899 16:44:29.689899 ==
5900 16:44:29.692150 Dram Type= 6, Freq= 0, CH_1, rank 1
5901 16:44:29.695952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5902 16:44:29.696536 ==
5903 16:44:29.696911 RX Vref Scan: 0
5904 16:44:29.697253
5905 16:44:29.699214 RX Vref 0 -> 0, step: 1
5906 16:44:29.699679
5907 16:44:29.702194 RX Delay -53 -> 252, step: 4
5908 16:44:29.708675 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5909 16:44:29.711778 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5910 16:44:29.715457 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5911 16:44:29.718326 iDelay=199, Bit 3, Center 104 (23 ~ 186) 164
5912 16:44:29.722184 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5913 16:44:29.728703 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5914 16:44:29.731637 iDelay=199, Bit 6, Center 114 (35 ~ 194) 160
5915 16:44:29.735157 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5916 16:44:29.738160 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5917 16:44:29.741769 iDelay=199, Bit 9, Center 88 (3 ~ 174) 172
5918 16:44:29.746316 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5919 16:44:29.751481 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5920 16:44:29.755181 iDelay=199, Bit 12, Center 108 (23 ~ 194) 172
5921 16:44:29.758185 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5922 16:44:29.761386 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5923 16:44:29.767969 iDelay=199, Bit 15, Center 108 (23 ~ 194) 172
5924 16:44:29.768532 ==
5925 16:44:29.771275 Dram Type= 6, Freq= 0, CH_1, rank 1
5926 16:44:29.774954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5927 16:44:29.775521 ==
5928 16:44:29.775892 DQS Delay:
5929 16:44:29.778327 DQS0 = 0, DQS1 = 0
5930 16:44:29.778924 DQM Delay:
5931 16:44:29.781583 DQM0 = 105, DQM1 = 98
5932 16:44:29.782146 DQ Delay:
5933 16:44:29.784679 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =104
5934 16:44:29.787798 DQ4 =106, DQ5 =116, DQ6 =114, DQ7 =102
5935 16:44:29.791293 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5936 16:44:29.794641 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =108
5937 16:44:29.795204
5938 16:44:29.795568
5939 16:44:29.804570 [DQSOSCAuto] RK1, (LSB)MR18= 0x2501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
5940 16:44:29.807759 CH1 RK1: MR19=505, MR18=2501
5941 16:44:29.811121 CH1_RK1: MR19=0x505, MR18=0x2501, DQSOSC=410, MR23=63, INC=64, DEC=42
5942 16:44:29.814469 [RxdqsGatingPostProcess] freq 933
5943 16:44:29.821323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5944 16:44:29.824231 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 16:44:29.827901 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 16:44:29.830547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 16:44:29.834753 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 16:44:29.837366 best DQS0 dly(2T, 0.5T) = (0, 10)
5949 16:44:29.841287 best DQS1 dly(2T, 0.5T) = (0, 10)
5950 16:44:29.844387 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5951 16:44:29.847465 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5952 16:44:29.850563 Pre-setting of DQS Precalculation
5953 16:44:29.854443 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5954 16:44:29.860934 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5955 16:44:29.867494 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5956 16:44:29.868053
5957 16:44:29.868421
5958 16:44:29.870346 [Calibration Summary] 1866 Mbps
5959 16:44:29.873882 CH 0, Rank 0
5960 16:44:29.874479 SW Impedance : PASS
5961 16:44:29.877313 DUTY Scan : NO K
5962 16:44:29.880413 ZQ Calibration : PASS
5963 16:44:29.880987 Jitter Meter : NO K
5964 16:44:29.883681 CBT Training : PASS
5965 16:44:29.887277 Write leveling : PASS
5966 16:44:29.887840 RX DQS gating : PASS
5967 16:44:29.890534 RX DQ/DQS(RDDQC) : PASS
5968 16:44:29.893624 TX DQ/DQS : PASS
5969 16:44:29.894090 RX DATLAT : PASS
5970 16:44:29.896524 RX DQ/DQS(Engine): PASS
5971 16:44:29.900426 TX OE : NO K
5972 16:44:29.901035 All Pass.
5973 16:44:29.901412
5974 16:44:29.901757 CH 0, Rank 1
5975 16:44:29.903474 SW Impedance : PASS
5976 16:44:29.906918 DUTY Scan : NO K
5977 16:44:29.907425 ZQ Calibration : PASS
5978 16:44:29.910060 Jitter Meter : NO K
5979 16:44:29.913326 CBT Training : PASS
5980 16:44:29.913797 Write leveling : PASS
5981 16:44:29.916511 RX DQS gating : PASS
5982 16:44:29.919711 RX DQ/DQS(RDDQC) : PASS
5983 16:44:29.920176 TX DQ/DQS : PASS
5984 16:44:29.923286 RX DATLAT : PASS
5985 16:44:29.926049 RX DQ/DQS(Engine): PASS
5986 16:44:29.926557 TX OE : NO K
5987 16:44:29.926934 All Pass.
5988 16:44:29.929356
5989 16:44:29.930128 CH 1, Rank 0
5990 16:44:29.933353 SW Impedance : PASS
5991 16:44:29.933918 DUTY Scan : NO K
5992 16:44:29.936401 ZQ Calibration : PASS
5993 16:44:29.936970 Jitter Meter : NO K
5994 16:44:29.939838 CBT Training : PASS
5995 16:44:29.942959 Write leveling : PASS
5996 16:44:29.943440 RX DQS gating : PASS
5997 16:44:29.946075 RX DQ/DQS(RDDQC) : PASS
5998 16:44:29.949807 TX DQ/DQS : PASS
5999 16:44:29.950426 RX DATLAT : PASS
6000 16:44:29.953539 RX DQ/DQS(Engine): PASS
6001 16:44:29.956024 TX OE : NO K
6002 16:44:29.956599 All Pass.
6003 16:44:29.956972
6004 16:44:29.957315 CH 1, Rank 1
6005 16:44:29.959547 SW Impedance : PASS
6006 16:44:29.962917 DUTY Scan : NO K
6007 16:44:29.963490 ZQ Calibration : PASS
6008 16:44:29.965687 Jitter Meter : NO K
6009 16:44:29.970314 CBT Training : PASS
6010 16:44:29.970931 Write leveling : PASS
6011 16:44:29.972621 RX DQS gating : PASS
6012 16:44:29.976302 RX DQ/DQS(RDDQC) : PASS
6013 16:44:29.976877 TX DQ/DQS : PASS
6014 16:44:29.979178 RX DATLAT : PASS
6015 16:44:29.982925 RX DQ/DQS(Engine): PASS
6016 16:44:29.983520 TX OE : NO K
6017 16:44:29.985931 All Pass.
6018 16:44:29.986583
6019 16:44:29.986971 DramC Write-DBI off
6020 16:44:29.989122 PER_BANK_REFRESH: Hybrid Mode
6021 16:44:29.989681 TX_TRACKING: ON
6022 16:44:29.999138 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6023 16:44:30.002331 [FAST_K] Save calibration result to emmc
6024 16:44:30.006199 dramc_set_vcore_voltage set vcore to 650000
6025 16:44:30.009031 Read voltage for 400, 6
6026 16:44:30.009602 Vio18 = 0
6027 16:44:30.012478 Vcore = 650000
6028 16:44:30.012970 Vdram = 0
6029 16:44:30.013406 Vddq = 0
6030 16:44:30.015413 Vmddr = 0
6031 16:44:30.019070 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6032 16:44:30.026244 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6033 16:44:30.026868 MEM_TYPE=3, freq_sel=20
6034 16:44:30.028665 sv_algorithm_assistance_LP4_800
6035 16:44:30.031847 ============ PULL DRAM RESETB DOWN ============
6036 16:44:30.038812 ========== PULL DRAM RESETB DOWN end =========
6037 16:44:30.042053 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6038 16:44:30.045195 ===================================
6039 16:44:30.048492 LPDDR4 DRAM CONFIGURATION
6040 16:44:30.051994 ===================================
6041 16:44:30.052464 EX_ROW_EN[0] = 0x0
6042 16:44:30.055542 EX_ROW_EN[1] = 0x0
6043 16:44:30.058790 LP4Y_EN = 0x0
6044 16:44:30.059436 WORK_FSP = 0x0
6045 16:44:30.062391 WL = 0x2
6046 16:44:30.062970 RL = 0x2
6047 16:44:30.065039 BL = 0x2
6048 16:44:30.065508 RPST = 0x0
6049 16:44:30.068624 RD_PRE = 0x0
6050 16:44:30.069197 WR_PRE = 0x1
6051 16:44:30.071654 WR_PST = 0x0
6052 16:44:30.072230 DBI_WR = 0x0
6053 16:44:30.075288 DBI_RD = 0x0
6054 16:44:30.075859 OTF = 0x1
6055 16:44:30.078415 ===================================
6056 16:44:30.081858 ===================================
6057 16:44:30.085442 ANA top config
6058 16:44:30.088644 ===================================
6059 16:44:30.089220 DLL_ASYNC_EN = 0
6060 16:44:30.091215 ALL_SLAVE_EN = 1
6061 16:44:30.094855 NEW_RANK_MODE = 1
6062 16:44:30.098254 DLL_IDLE_MODE = 1
6063 16:44:30.101378 LP45_APHY_COMB_EN = 1
6064 16:44:30.101951 TX_ODT_DIS = 1
6065 16:44:30.104880 NEW_8X_MODE = 1
6066 16:44:30.108215 ===================================
6067 16:44:30.111215 ===================================
6068 16:44:30.114672 data_rate = 800
6069 16:44:30.118082 CKR = 1
6070 16:44:30.121414 DQ_P2S_RATIO = 4
6071 16:44:30.124579 ===================================
6072 16:44:30.128259 CA_P2S_RATIO = 4
6073 16:44:30.128856 DQ_CA_OPEN = 0
6074 16:44:30.131530 DQ_SEMI_OPEN = 1
6075 16:44:30.135176 CA_SEMI_OPEN = 1
6076 16:44:30.137923 CA_FULL_RATE = 0
6077 16:44:30.141270 DQ_CKDIV4_EN = 0
6078 16:44:30.144468 CA_CKDIV4_EN = 1
6079 16:44:30.145031 CA_PREDIV_EN = 0
6080 16:44:30.148031 PH8_DLY = 0
6081 16:44:30.150850 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6082 16:44:30.154311 DQ_AAMCK_DIV = 0
6083 16:44:30.157964 CA_AAMCK_DIV = 0
6084 16:44:30.160700 CA_ADMCK_DIV = 4
6085 16:44:30.161164 DQ_TRACK_CA_EN = 0
6086 16:44:30.164667 CA_PICK = 800
6087 16:44:30.167794 CA_MCKIO = 400
6088 16:44:30.170880 MCKIO_SEMI = 400
6089 16:44:30.174721 PLL_FREQ = 3016
6090 16:44:30.177523 DQ_UI_PI_RATIO = 32
6091 16:44:30.180595 CA_UI_PI_RATIO = 32
6092 16:44:30.184505 ===================================
6093 16:44:30.187761 ===================================
6094 16:44:30.188325 memory_type:LPDDR4
6095 16:44:30.191031 GP_NUM : 10
6096 16:44:30.194310 SRAM_EN : 1
6097 16:44:30.194902 MD32_EN : 0
6098 16:44:30.197568 ===================================
6099 16:44:30.201117 [ANA_INIT] >>>>>>>>>>>>>>
6100 16:44:30.203692 <<<<<< [CONFIGURE PHASE]: ANA_TX
6101 16:44:30.206983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6102 16:44:30.210771 ===================================
6103 16:44:30.213870 data_rate = 800,PCW = 0X7400
6104 16:44:30.217169 ===================================
6105 16:44:30.220566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6106 16:44:30.224104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6107 16:44:30.236905 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6108 16:44:30.240905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6109 16:44:30.243329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6110 16:44:30.246899 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6111 16:44:30.250712 [ANA_INIT] flow start
6112 16:44:30.253658 [ANA_INIT] PLL >>>>>>>>
6113 16:44:30.254223 [ANA_INIT] PLL <<<<<<<<
6114 16:44:30.257093 [ANA_INIT] MIDPI >>>>>>>>
6115 16:44:30.260368 [ANA_INIT] MIDPI <<<<<<<<
6116 16:44:30.260834 [ANA_INIT] DLL >>>>>>>>
6117 16:44:30.263214 [ANA_INIT] flow end
6118 16:44:30.267562 ============ LP4 DIFF to SE enter ============
6119 16:44:30.270686 ============ LP4 DIFF to SE exit ============
6120 16:44:30.273668 [ANA_INIT] <<<<<<<<<<<<<
6121 16:44:30.276502 [Flow] Enable top DCM control >>>>>
6122 16:44:30.280216 [Flow] Enable top DCM control <<<<<
6123 16:44:30.284033 Enable DLL master slave shuffle
6124 16:44:30.289871 ==============================================================
6125 16:44:30.290473 Gating Mode config
6126 16:44:30.296513 ==============================================================
6127 16:44:30.297079 Config description:
6128 16:44:30.306618 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6129 16:44:30.313377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6130 16:44:30.319567 SELPH_MODE 0: By rank 1: By Phase
6131 16:44:30.326629 ==============================================================
6132 16:44:30.327197 GAT_TRACK_EN = 0
6133 16:44:30.329548 RX_GATING_MODE = 2
6134 16:44:30.333125 RX_GATING_TRACK_MODE = 2
6135 16:44:30.336421 SELPH_MODE = 1
6136 16:44:30.339575 PICG_EARLY_EN = 1
6137 16:44:30.343411 VALID_LAT_VALUE = 1
6138 16:44:30.349949 ==============================================================
6139 16:44:30.352618 Enter into Gating configuration >>>>
6140 16:44:30.356402 Exit from Gating configuration <<<<
6141 16:44:30.359195 Enter into DVFS_PRE_config >>>>>
6142 16:44:30.369286 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6143 16:44:30.372431 Exit from DVFS_PRE_config <<<<<
6144 16:44:30.376141 Enter into PICG configuration >>>>
6145 16:44:30.379531 Exit from PICG configuration <<<<
6146 16:44:30.382510 [RX_INPUT] configuration >>>>>
6147 16:44:30.385763 [RX_INPUT] configuration <<<<<
6148 16:44:30.389275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6149 16:44:30.397082 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6150 16:44:30.402405 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6151 16:44:30.405518 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6152 16:44:30.412605 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6153 16:44:30.419120 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6154 16:44:30.422508 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6155 16:44:30.428680 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6156 16:44:30.432053 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6157 16:44:30.436352 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6158 16:44:30.438752 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6159 16:44:30.445153 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6160 16:44:30.448842 ===================================
6161 16:44:30.449405 LPDDR4 DRAM CONFIGURATION
6162 16:44:30.451991 ===================================
6163 16:44:30.455522 EX_ROW_EN[0] = 0x0
6164 16:44:30.458450 EX_ROW_EN[1] = 0x0
6165 16:44:30.458913 LP4Y_EN = 0x0
6166 16:44:30.461410 WORK_FSP = 0x0
6167 16:44:30.461868 WL = 0x2
6168 16:44:30.465012 RL = 0x2
6169 16:44:30.465576 BL = 0x2
6170 16:44:30.468176 RPST = 0x0
6171 16:44:30.468638 RD_PRE = 0x0
6172 16:44:30.471411 WR_PRE = 0x1
6173 16:44:30.472028 WR_PST = 0x0
6174 16:44:30.475509 DBI_WR = 0x0
6175 16:44:30.476081 DBI_RD = 0x0
6176 16:44:30.478442 OTF = 0x1
6177 16:44:30.481651 ===================================
6178 16:44:30.485008 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6179 16:44:30.488560 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6180 16:44:30.494945 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6181 16:44:30.498213 ===================================
6182 16:44:30.498709 LPDDR4 DRAM CONFIGURATION
6183 16:44:30.502111 ===================================
6184 16:44:30.504768 EX_ROW_EN[0] = 0x10
6185 16:44:30.508136 EX_ROW_EN[1] = 0x0
6186 16:44:30.508597 LP4Y_EN = 0x0
6187 16:44:30.511376 WORK_FSP = 0x0
6188 16:44:30.511836 WL = 0x2
6189 16:44:30.514464 RL = 0x2
6190 16:44:30.514924 BL = 0x2
6191 16:44:30.518001 RPST = 0x0
6192 16:44:30.518501 RD_PRE = 0x0
6193 16:44:30.521441 WR_PRE = 0x1
6194 16:44:30.521902 WR_PST = 0x0
6195 16:44:30.524921 DBI_WR = 0x0
6196 16:44:30.525517 DBI_RD = 0x0
6197 16:44:30.528201 OTF = 0x1
6198 16:44:30.531118 ===================================
6199 16:44:30.537627 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6200 16:44:30.541077 nWR fixed to 30
6201 16:44:30.544252 [ModeRegInit_LP4] CH0 RK0
6202 16:44:30.544734 [ModeRegInit_LP4] CH0 RK1
6203 16:44:30.547703 [ModeRegInit_LP4] CH1 RK0
6204 16:44:30.550725 [ModeRegInit_LP4] CH1 RK1
6205 16:44:30.551241 match AC timing 19
6206 16:44:30.557677 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6207 16:44:30.560609 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6208 16:44:30.564685 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6209 16:44:30.570562 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6210 16:44:30.573866 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6211 16:44:30.574332 ==
6212 16:44:30.577472 Dram Type= 6, Freq= 0, CH_0, rank 0
6213 16:44:30.580473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6214 16:44:30.580996 ==
6215 16:44:30.587333 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6216 16:44:30.594057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6217 16:44:30.597253 [CA 0] Center 36 (8~64) winsize 57
6218 16:44:30.600595 [CA 1] Center 36 (8~64) winsize 57
6219 16:44:30.603817 [CA 2] Center 36 (8~64) winsize 57
6220 16:44:30.606938 [CA 3] Center 36 (8~64) winsize 57
6221 16:44:30.607400 [CA 4] Center 36 (8~64) winsize 57
6222 16:44:30.610847 [CA 5] Center 36 (8~64) winsize 57
6223 16:44:30.611409
6224 16:44:30.617114 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6225 16:44:30.617678
6226 16:44:30.620149 [CATrainingPosCal] consider 1 rank data
6227 16:44:30.623581 u2DelayCellTimex100 = 270/100 ps
6228 16:44:30.626953 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 16:44:30.630404 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 16:44:30.633559 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 16:44:30.636769 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 16:44:30.640562 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 16:44:30.643530 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 16:44:30.644092
6235 16:44:30.646840 CA PerBit enable=1, Macro0, CA PI delay=36
6236 16:44:30.647426
6237 16:44:30.650753 [CBTSetCACLKResult] CA Dly = 36
6238 16:44:30.653268 CS Dly: 1 (0~32)
6239 16:44:30.653849 ==
6240 16:44:30.656622 Dram Type= 6, Freq= 0, CH_0, rank 1
6241 16:44:30.660128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6242 16:44:30.660717 ==
6243 16:44:30.666537 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6244 16:44:30.673004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6245 16:44:30.676383 [CA 0] Center 36 (8~64) winsize 57
6246 16:44:30.679957 [CA 1] Center 36 (8~64) winsize 57
6247 16:44:30.680542 [CA 2] Center 36 (8~64) winsize 57
6248 16:44:30.683016 [CA 3] Center 36 (8~64) winsize 57
6249 16:44:30.687548 [CA 4] Center 36 (8~64) winsize 57
6250 16:44:30.689594 [CA 5] Center 36 (8~64) winsize 57
6251 16:44:30.690188
6252 16:44:30.692673 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6253 16:44:30.695883
6254 16:44:30.699002 [CATrainingPosCal] consider 2 rank data
6255 16:44:30.702987 u2DelayCellTimex100 = 270/100 ps
6256 16:44:30.706076 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 16:44:30.709465 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 16:44:30.712344 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 16:44:30.715694 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6260 16:44:30.719122 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6261 16:44:30.722430 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 16:44:30.722902
6263 16:44:30.726265 CA PerBit enable=1, Macro0, CA PI delay=36
6264 16:44:30.726885
6265 16:44:30.729187 [CBTSetCACLKResult] CA Dly = 36
6266 16:44:30.732926 CS Dly: 1 (0~32)
6267 16:44:30.733501
6268 16:44:30.735490 ----->DramcWriteLeveling(PI) begin...
6269 16:44:30.735966 ==
6270 16:44:30.739352 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 16:44:30.742010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 16:44:30.742507 ==
6273 16:44:30.745743 Write leveling (Byte 0): 40 => 8
6274 16:44:30.748610 Write leveling (Byte 1): 32 => 0
6275 16:44:30.752104 DramcWriteLeveling(PI) end<-----
6276 16:44:30.752575
6277 16:44:30.752945 ==
6278 16:44:30.755525 Dram Type= 6, Freq= 0, CH_0, rank 0
6279 16:44:30.759042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6280 16:44:30.759517 ==
6281 16:44:30.761985 [Gating] SW mode calibration
6282 16:44:30.769207 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6283 16:44:30.775780 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6284 16:44:30.778896 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6285 16:44:30.781732 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6286 16:44:30.788774 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6287 16:44:30.791860 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6288 16:44:30.794886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 16:44:30.801484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6290 16:44:30.805407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 16:44:30.808507 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 16:44:30.815028 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6293 16:44:30.818064 Total UI for P1: 0, mck2ui 16
6294 16:44:30.821384 best dqsien dly found for B0: ( 0, 14, 24)
6295 16:44:30.824882 Total UI for P1: 0, mck2ui 16
6296 16:44:30.828703 best dqsien dly found for B1: ( 0, 14, 24)
6297 16:44:30.831158 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6298 16:44:30.834557 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6299 16:44:30.835021
6300 16:44:30.837932 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6301 16:44:30.841539 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6302 16:44:30.844773 [Gating] SW calibration Done
6303 16:44:30.845334 ==
6304 16:44:30.848017 Dram Type= 6, Freq= 0, CH_0, rank 0
6305 16:44:30.851444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 16:44:30.851982 ==
6307 16:44:30.854570 RX Vref Scan: 0
6308 16:44:30.855031
6309 16:44:30.858557 RX Vref 0 -> 0, step: 1
6310 16:44:30.859008
6311 16:44:30.859360 RX Delay -410 -> 252, step: 16
6312 16:44:30.864500 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6313 16:44:30.868066 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6314 16:44:30.871239 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6315 16:44:30.877953 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6316 16:44:30.881648 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6317 16:44:30.884728 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6318 16:44:30.887700 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6319 16:44:30.891466 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6320 16:44:30.897661 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6321 16:44:30.900933 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6322 16:44:30.904135 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6323 16:44:30.911087 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6324 16:44:30.914533 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6325 16:44:30.917893 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6326 16:44:30.920998 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6327 16:44:30.927383 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6328 16:44:30.927831 ==
6329 16:44:30.930901 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 16:44:30.935051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 16:44:30.935504 ==
6332 16:44:30.935859 DQS Delay:
6333 16:44:30.937370 DQS0 = 19, DQS1 = 43
6334 16:44:30.937902 DQM Delay:
6335 16:44:30.941026 DQM0 = 5, DQM1 = 16
6336 16:44:30.941573 DQ Delay:
6337 16:44:30.944160 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6338 16:44:30.947347 DQ4 =8, DQ5 =0, DQ6 =8, DQ7 =16
6339 16:44:30.950971 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6340 16:44:30.954716 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6341 16:44:30.955271
6342 16:44:30.955625
6343 16:44:30.955955 ==
6344 16:44:30.957037 Dram Type= 6, Freq= 0, CH_0, rank 0
6345 16:44:30.960468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6346 16:44:30.961023 ==
6347 16:44:30.961378
6348 16:44:30.961705
6349 16:44:30.963883 TX Vref Scan disable
6350 16:44:30.964431 == TX Byte 0 ==
6351 16:44:30.970559 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 16:44:30.974045 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 16:44:30.974539 == TX Byte 1 ==
6354 16:44:30.980488 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6355 16:44:30.984060 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6356 16:44:30.984633 ==
6357 16:44:30.986986 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 16:44:30.990585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 16:44:30.991142 ==
6360 16:44:30.991498
6361 16:44:30.993880
6362 16:44:30.994478 TX Vref Scan disable
6363 16:44:30.997644 == TX Byte 0 ==
6364 16:44:31.000694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 16:44:31.003508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 16:44:31.007298 == TX Byte 1 ==
6367 16:44:31.010178 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 16:44:31.013526 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 16:44:31.014077
6370 16:44:31.014481 [DATLAT]
6371 16:44:31.017201 Freq=400, CH0 RK0
6372 16:44:31.017790
6373 16:44:31.020211 DATLAT Default: 0xf
6374 16:44:31.020771 0, 0xFFFF, sum = 0
6375 16:44:31.023633 1, 0xFFFF, sum = 0
6376 16:44:31.024089 2, 0xFFFF, sum = 0
6377 16:44:31.026870 3, 0xFFFF, sum = 0
6378 16:44:31.027393 4, 0xFFFF, sum = 0
6379 16:44:31.030218 5, 0xFFFF, sum = 0
6380 16:44:31.030824 6, 0xFFFF, sum = 0
6381 16:44:31.033279 7, 0xFFFF, sum = 0
6382 16:44:31.033788 8, 0xFFFF, sum = 0
6383 16:44:31.036529 9, 0xFFFF, sum = 0
6384 16:44:31.036988 10, 0xFFFF, sum = 0
6385 16:44:31.039859 11, 0xFFFF, sum = 0
6386 16:44:31.040319 12, 0xFFFF, sum = 0
6387 16:44:31.044016 13, 0x0, sum = 1
6388 16:44:31.044587 14, 0x0, sum = 2
6389 16:44:31.046558 15, 0x0, sum = 3
6390 16:44:31.047031 16, 0x0, sum = 4
6391 16:44:31.050200 best_step = 14
6392 16:44:31.050809
6393 16:44:31.051180 ==
6394 16:44:31.052952 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 16:44:31.057114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 16:44:31.057684 ==
6397 16:44:31.060111 RX Vref Scan: 1
6398 16:44:31.060673
6399 16:44:31.061039 RX Vref 0 -> 0, step: 1
6400 16:44:31.061377
6401 16:44:31.063232 RX Delay -327 -> 252, step: 8
6402 16:44:31.063768
6403 16:44:31.066837 Set Vref, RX VrefLevel [Byte0]: 59
6404 16:44:31.069750 [Byte1]: 49
6405 16:44:31.074280
6406 16:44:31.074791 Final RX Vref Byte 0 = 59 to rank0
6407 16:44:31.077708 Final RX Vref Byte 1 = 49 to rank0
6408 16:44:31.080848 Final RX Vref Byte 0 = 59 to rank1
6409 16:44:31.084257 Final RX Vref Byte 1 = 49 to rank1==
6410 16:44:31.087525 Dram Type= 6, Freq= 0, CH_0, rank 0
6411 16:44:31.094534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 16:44:31.095313 ==
6413 16:44:31.095707 DQS Delay:
6414 16:44:31.097981 DQS0 = 28, DQS1 = 48
6415 16:44:31.098624 DQM Delay:
6416 16:44:31.099003 DQM0 = 12, DQM1 = 15
6417 16:44:31.100719 DQ Delay:
6418 16:44:31.104055 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6419 16:44:31.107280 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =20
6420 16:44:31.110641 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6421 16:44:31.113819 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6422 16:44:31.114549
6423 16:44:31.114929
6424 16:44:31.120563 [DQSOSCAuto] RK0, (LSB)MR18= 0xb2aa, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 387 ps
6425 16:44:31.123612 CH0 RK0: MR19=C0C, MR18=B2AA
6426 16:44:31.130611 CH0_RK0: MR19=0xC0C, MR18=0xB2AA, DQSOSC=387, MR23=63, INC=394, DEC=262
6427 16:44:31.131179 ==
6428 16:44:31.133589 Dram Type= 6, Freq= 0, CH_0, rank 1
6429 16:44:31.136714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 16:44:31.137269 ==
6431 16:44:31.140196 [Gating] SW mode calibration
6432 16:44:31.146727 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6433 16:44:31.153410 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6434 16:44:31.156330 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6435 16:44:31.160353 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6436 16:44:31.167045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6437 16:44:31.170068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 16:44:31.173341 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 16:44:31.180278 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6440 16:44:31.183259 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6441 16:44:31.186276 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6442 16:44:31.193143 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6443 16:44:31.193711 Total UI for P1: 0, mck2ui 16
6444 16:44:31.200378 best dqsien dly found for B0: ( 0, 14, 24)
6445 16:44:31.200841 Total UI for P1: 0, mck2ui 16
6446 16:44:31.206315 best dqsien dly found for B1: ( 0, 14, 24)
6447 16:44:31.209645 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6448 16:44:31.213146 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6449 16:44:31.213715
6450 16:44:31.216081 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6451 16:44:31.220071 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6452 16:44:31.222838 [Gating] SW calibration Done
6453 16:44:31.223301 ==
6454 16:44:31.226039 Dram Type= 6, Freq= 0, CH_0, rank 1
6455 16:44:31.229599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 16:44:31.230166 ==
6457 16:44:31.232806 RX Vref Scan: 0
6458 16:44:31.233455
6459 16:44:31.235829 RX Vref 0 -> 0, step: 1
6460 16:44:31.236426
6461 16:44:31.236821 RX Delay -410 -> 252, step: 16
6462 16:44:31.242684 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6463 16:44:31.245807 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6464 16:44:31.249495 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6465 16:44:31.252552 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6466 16:44:31.259020 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6467 16:44:31.262656 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6468 16:44:31.265621 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6469 16:44:31.272469 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6470 16:44:31.275834 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6471 16:44:31.279242 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6472 16:44:31.282857 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6473 16:44:31.289434 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6474 16:44:31.292210 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6475 16:44:31.295408 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6476 16:44:31.298865 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6477 16:44:31.305669 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6478 16:44:31.306254 ==
6479 16:44:31.308661 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 16:44:31.311944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 16:44:31.312521 ==
6482 16:44:31.312895 DQS Delay:
6483 16:44:31.315405 DQS0 = 27, DQS1 = 35
6484 16:44:31.315896 DQM Delay:
6485 16:44:31.318726 DQM0 = 9, DQM1 = 9
6486 16:44:31.319302 DQ Delay:
6487 16:44:31.321979 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6488 16:44:31.325038 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6489 16:44:31.328716 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6490 16:44:31.331788 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6491 16:44:31.332365
6492 16:44:31.332738
6493 16:44:31.333077 ==
6494 16:44:31.334982 Dram Type= 6, Freq= 0, CH_0, rank 1
6495 16:44:31.338482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6496 16:44:31.339057 ==
6497 16:44:31.339432
6498 16:44:31.339826
6499 16:44:31.341392 TX Vref Scan disable
6500 16:44:31.341864 == TX Byte 0 ==
6501 16:44:31.348043 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6502 16:44:31.351708 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6503 16:44:31.352295 == TX Byte 1 ==
6504 16:44:31.358431 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6505 16:44:31.361910 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6506 16:44:31.362521 ==
6507 16:44:31.364846 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 16:44:31.368044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 16:44:31.368624 ==
6510 16:44:31.368998
6511 16:44:31.369342
6512 16:44:31.371440 TX Vref Scan disable
6513 16:44:31.374471 == TX Byte 0 ==
6514 16:44:31.377914 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 16:44:31.381761 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 16:44:31.384702 == TX Byte 1 ==
6517 16:44:31.388331 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6518 16:44:31.391127 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6519 16:44:31.391703
6520 16:44:31.392076 [DATLAT]
6521 16:44:31.394909 Freq=400, CH0 RK1
6522 16:44:31.395627
6523 16:44:31.396012 DATLAT Default: 0xe
6524 16:44:31.398251 0, 0xFFFF, sum = 0
6525 16:44:31.398857 1, 0xFFFF, sum = 0
6526 16:44:31.401085 2, 0xFFFF, sum = 0
6527 16:44:31.405137 3, 0xFFFF, sum = 0
6528 16:44:31.405725 4, 0xFFFF, sum = 0
6529 16:44:31.407607 5, 0xFFFF, sum = 0
6530 16:44:31.408084 6, 0xFFFF, sum = 0
6531 16:44:31.411321 7, 0xFFFF, sum = 0
6532 16:44:31.411981 8, 0xFFFF, sum = 0
6533 16:44:31.414101 9, 0xFFFF, sum = 0
6534 16:44:31.414735 10, 0xFFFF, sum = 0
6535 16:44:31.418286 11, 0xFFFF, sum = 0
6536 16:44:31.418911 12, 0xFFFF, sum = 0
6537 16:44:31.420571 13, 0x0, sum = 1
6538 16:44:31.421150 14, 0x0, sum = 2
6539 16:44:31.425114 15, 0x0, sum = 3
6540 16:44:31.425807 16, 0x0, sum = 4
6541 16:44:31.427539 best_step = 14
6542 16:44:31.428004
6543 16:44:31.428372 ==
6544 16:44:31.430719 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 16:44:31.434431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 16:44:31.435000 ==
6547 16:44:31.437389 RX Vref Scan: 0
6548 16:44:31.437866
6549 16:44:31.438230 RX Vref 0 -> 0, step: 1
6550 16:44:31.438599
6551 16:44:31.440697 RX Delay -311 -> 252, step: 8
6552 16:44:31.447995 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6553 16:44:31.452014 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6554 16:44:31.454727 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6555 16:44:31.458186 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6556 16:44:31.464715 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6557 16:44:31.468165 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6558 16:44:31.471499 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6559 16:44:31.474431 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6560 16:44:31.481326 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6561 16:44:31.485048 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6562 16:44:31.488581 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6563 16:44:31.494690 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6564 16:44:31.497851 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6565 16:44:31.500856 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6566 16:44:31.504649 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6567 16:44:31.511082 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6568 16:44:31.511650 ==
6569 16:44:31.514117 Dram Type= 6, Freq= 0, CH_0, rank 1
6570 16:44:31.517261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 16:44:31.517747 ==
6572 16:44:31.518175 DQS Delay:
6573 16:44:31.521714 DQS0 = 28, DQS1 = 40
6574 16:44:31.522290 DQM Delay:
6575 16:44:31.523814 DQM0 = 11, DQM1 = 12
6576 16:44:31.524478 DQ Delay:
6577 16:44:31.527015 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6578 16:44:31.530232 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6579 16:44:31.533636 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6580 16:44:31.537532 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6581 16:44:31.538003
6582 16:44:31.538422
6583 16:44:31.544054 [DQSOSCAuto] RK1, (LSB)MR18= 0xc276, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6584 16:44:31.547308 CH0 RK1: MR19=C0C, MR18=C276
6585 16:44:31.553906 CH0_RK1: MR19=0xC0C, MR18=0xC276, DQSOSC=385, MR23=63, INC=398, DEC=265
6586 16:44:31.557080 [RxdqsGatingPostProcess] freq 400
6587 16:44:31.563656 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6588 16:44:31.567992 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 16:44:31.570320 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 16:44:31.574018 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 16:44:31.576982 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 16:44:31.577559 best DQS0 dly(2T, 0.5T) = (0, 10)
6593 16:44:31.581060 best DQS1 dly(2T, 0.5T) = (0, 10)
6594 16:44:31.583208 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6595 16:44:31.587049 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6596 16:44:31.590302 Pre-setting of DQS Precalculation
6597 16:44:31.596810 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6598 16:44:31.597377 ==
6599 16:44:31.599722 Dram Type= 6, Freq= 0, CH_1, rank 0
6600 16:44:31.603373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6601 16:44:31.603941 ==
6602 16:44:31.609655 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6603 16:44:31.616368 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6604 16:44:31.619893 [CA 0] Center 36 (8~64) winsize 57
6605 16:44:31.622928 [CA 1] Center 36 (8~64) winsize 57
6606 16:44:31.626548 [CA 2] Center 36 (8~64) winsize 57
6607 16:44:31.627162 [CA 3] Center 36 (8~64) winsize 57
6608 16:44:31.629445 [CA 4] Center 36 (8~64) winsize 57
6609 16:44:31.633053 [CA 5] Center 36 (8~64) winsize 57
6610 16:44:31.633617
6611 16:44:31.639584 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6612 16:44:31.640155
6613 16:44:31.642740 [CATrainingPosCal] consider 1 rank data
6614 16:44:31.646588 u2DelayCellTimex100 = 270/100 ps
6615 16:44:31.649473 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 16:44:31.653642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 16:44:31.655928 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 16:44:31.659592 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 16:44:31.662434 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 16:44:31.666081 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 16:44:31.666683
6622 16:44:31.669155 CA PerBit enable=1, Macro0, CA PI delay=36
6623 16:44:31.669618
6624 16:44:31.672680 [CBTSetCACLKResult] CA Dly = 36
6625 16:44:31.675761 CS Dly: 1 (0~32)
6626 16:44:31.676321 ==
6627 16:44:31.679512 Dram Type= 6, Freq= 0, CH_1, rank 1
6628 16:44:31.682647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6629 16:44:31.683119 ==
6630 16:44:31.688777 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6631 16:44:31.692423 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6632 16:44:31.695856 [CA 0] Center 36 (8~64) winsize 57
6633 16:44:31.699774 [CA 1] Center 36 (8~64) winsize 57
6634 16:44:31.702957 [CA 2] Center 36 (8~64) winsize 57
6635 16:44:31.705570 [CA 3] Center 36 (8~64) winsize 57
6636 16:44:31.708716 [CA 4] Center 36 (8~64) winsize 57
6637 16:44:31.712906 [CA 5] Center 36 (8~64) winsize 57
6638 16:44:31.713471
6639 16:44:31.715327 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6640 16:44:31.715794
6641 16:44:31.718941 [CATrainingPosCal] consider 2 rank data
6642 16:44:31.722316 u2DelayCellTimex100 = 270/100 ps
6643 16:44:31.725710 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 16:44:31.731958 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 16:44:31.734973 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 16:44:31.738164 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6647 16:44:31.742491 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6648 16:44:31.745674 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 16:44:31.746240
6650 16:44:31.748179 CA PerBit enable=1, Macro0, CA PI delay=36
6651 16:44:31.748645
6652 16:44:31.751782 [CBTSetCACLKResult] CA Dly = 36
6653 16:44:31.752344 CS Dly: 1 (0~32)
6654 16:44:31.754745
6655 16:44:31.758450 ----->DramcWriteLeveling(PI) begin...
6656 16:44:31.759019 ==
6657 16:44:31.761868 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 16:44:31.765246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 16:44:31.765813 ==
6660 16:44:31.767871 Write leveling (Byte 0): 40 => 8
6661 16:44:31.771647 Write leveling (Byte 1): 32 => 0
6662 16:44:31.774623 DramcWriteLeveling(PI) end<-----
6663 16:44:31.775089
6664 16:44:31.775453 ==
6665 16:44:31.778750 Dram Type= 6, Freq= 0, CH_1, rank 0
6666 16:44:31.781857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6667 16:44:31.782330 ==
6668 16:44:31.785324 [Gating] SW mode calibration
6669 16:44:31.791639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6670 16:44:31.798035 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6671 16:44:31.801163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6672 16:44:31.804923 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6673 16:44:31.811110 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6674 16:44:31.814669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6675 16:44:31.817503 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 16:44:31.824277 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6677 16:44:31.827514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6678 16:44:31.830876 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6679 16:44:31.837456 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6680 16:44:31.838018 Total UI for P1: 0, mck2ui 16
6681 16:44:31.844177 best dqsien dly found for B0: ( 0, 14, 24)
6682 16:44:31.844742 Total UI for P1: 0, mck2ui 16
6683 16:44:31.850719 best dqsien dly found for B1: ( 0, 14, 24)
6684 16:44:31.853966 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6685 16:44:31.857508 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6686 16:44:31.858067
6687 16:44:31.860522 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6688 16:44:31.864169 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6689 16:44:31.867231 [Gating] SW calibration Done
6690 16:44:31.867797 ==
6691 16:44:31.870520 Dram Type= 6, Freq= 0, CH_1, rank 0
6692 16:44:31.873611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 16:44:31.874174 ==
6694 16:44:31.876811 RX Vref Scan: 0
6695 16:44:31.877276
6696 16:44:31.880048 RX Vref 0 -> 0, step: 1
6697 16:44:31.880516
6698 16:44:31.880877 RX Delay -410 -> 252, step: 16
6699 16:44:31.886786 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6700 16:44:31.890435 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6701 16:44:31.893521 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6702 16:44:31.900243 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6703 16:44:31.902889 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6704 16:44:31.906515 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6705 16:44:31.909966 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6706 16:44:31.916521 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6707 16:44:31.919965 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6708 16:44:31.923294 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6709 16:44:31.926508 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6710 16:44:31.932900 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6711 16:44:31.935959 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6712 16:44:31.939467 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6713 16:44:31.942897 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6714 16:44:31.949601 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6715 16:44:31.950165 ==
6716 16:44:31.953372 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 16:44:31.955766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 16:44:31.956236 ==
6719 16:44:31.956604 DQS Delay:
6720 16:44:31.959200 DQS0 = 27, DQS1 = 43
6721 16:44:31.959684 DQM Delay:
6722 16:44:31.963217 DQM0 = 9, DQM1 = 18
6723 16:44:31.963780 DQ Delay:
6724 16:44:31.967266 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6725 16:44:31.969226 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6726 16:44:31.972766 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6727 16:44:31.975619 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =32
6728 16:44:31.976085
6729 16:44:31.976451
6730 16:44:31.976789 ==
6731 16:44:31.979071 Dram Type= 6, Freq= 0, CH_1, rank 0
6732 16:44:31.982289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6733 16:44:31.982889 ==
6734 16:44:31.983259
6735 16:44:31.985595
6736 16:44:31.986059 TX Vref Scan disable
6737 16:44:31.989013 == TX Byte 0 ==
6738 16:44:31.992222 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 16:44:31.995679 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 16:44:31.998814 == TX Byte 1 ==
6741 16:44:32.002686 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6742 16:44:32.005640 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6743 16:44:32.006168 ==
6744 16:44:32.008616 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 16:44:32.012116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 16:44:32.015505 ==
6747 16:44:32.016070
6748 16:44:32.016438
6749 16:44:32.016777 TX Vref Scan disable
6750 16:44:32.018871 == TX Byte 0 ==
6751 16:44:32.022702 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 16:44:32.025455 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 16:44:32.029074 == TX Byte 1 ==
6754 16:44:32.032087 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6755 16:44:32.035458 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6756 16:44:32.035927
6757 16:44:32.038655 [DATLAT]
6758 16:44:32.039118 Freq=400, CH1 RK0
6759 16:44:32.039490
6760 16:44:32.041694 DATLAT Default: 0xf
6761 16:44:32.042156 0, 0xFFFF, sum = 0
6762 16:44:32.045716 1, 0xFFFF, sum = 0
6763 16:44:32.046293 2, 0xFFFF, sum = 0
6764 16:44:32.048609 3, 0xFFFF, sum = 0
6765 16:44:32.049191 4, 0xFFFF, sum = 0
6766 16:44:32.052081 5, 0xFFFF, sum = 0
6767 16:44:32.052660 6, 0xFFFF, sum = 0
6768 16:44:32.055264 7, 0xFFFF, sum = 0
6769 16:44:32.055790 8, 0xFFFF, sum = 0
6770 16:44:32.058599 9, 0xFFFF, sum = 0
6771 16:44:32.059170 10, 0xFFFF, sum = 0
6772 16:44:32.061955 11, 0xFFFF, sum = 0
6773 16:44:32.065125 12, 0xFFFF, sum = 0
6774 16:44:32.065691 13, 0x0, sum = 1
6775 16:44:32.066068 14, 0x0, sum = 2
6776 16:44:32.068471 15, 0x0, sum = 3
6777 16:44:32.069043 16, 0x0, sum = 4
6778 16:44:32.071960 best_step = 14
6779 16:44:32.072423
6780 16:44:32.072785 ==
6781 16:44:32.075526 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 16:44:32.078716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 16:44:32.079284 ==
6784 16:44:32.081730 RX Vref Scan: 1
6785 16:44:32.082296
6786 16:44:32.082735 RX Vref 0 -> 0, step: 1
6787 16:44:32.085223
6788 16:44:32.085776 RX Delay -327 -> 252, step: 8
6789 16:44:32.086146
6790 16:44:32.089865 Set Vref, RX VrefLevel [Byte0]: 52
6791 16:44:32.091250 [Byte1]: 52
6792 16:44:32.096569
6793 16:44:32.097132 Final RX Vref Byte 0 = 52 to rank0
6794 16:44:32.099650 Final RX Vref Byte 1 = 52 to rank0
6795 16:44:32.103942 Final RX Vref Byte 0 = 52 to rank1
6796 16:44:32.106465 Final RX Vref Byte 1 = 52 to rank1==
6797 16:44:32.110298 Dram Type= 6, Freq= 0, CH_1, rank 0
6798 16:44:32.116382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 16:44:32.116955 ==
6800 16:44:32.117332 DQS Delay:
6801 16:44:32.120112 DQS0 = 32, DQS1 = 40
6802 16:44:32.120681 DQM Delay:
6803 16:44:32.121053 DQM0 = 11, DQM1 = 12
6804 16:44:32.122839 DQ Delay:
6805 16:44:32.126251 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6806 16:44:32.126893 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6807 16:44:32.129393 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6808 16:44:32.132686 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6809 16:44:32.133154
6810 16:44:32.136232
6811 16:44:32.143039 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cd, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6812 16:44:32.146029 CH1 RK0: MR19=C0C, MR18=92CD
6813 16:44:32.152781 CH1_RK0: MR19=0xC0C, MR18=0x92CD, DQSOSC=384, MR23=63, INC=400, DEC=267
6814 16:44:32.153356 ==
6815 16:44:32.156064 Dram Type= 6, Freq= 0, CH_1, rank 1
6816 16:44:32.159265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 16:44:32.159842 ==
6818 16:44:32.162810 [Gating] SW mode calibration
6819 16:44:32.169249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6820 16:44:32.175805 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6821 16:44:32.179309 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6822 16:44:32.182559 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6823 16:44:32.189108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6824 16:44:32.192311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6825 16:44:32.195951 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 16:44:32.202318 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6827 16:44:32.206024 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6828 16:44:32.208928 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6829 16:44:32.214957 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6830 16:44:32.218777 Total UI for P1: 0, mck2ui 16
6831 16:44:32.221883 best dqsien dly found for B0: ( 0, 14, 24)
6832 16:44:32.222490 Total UI for P1: 0, mck2ui 16
6833 16:44:32.228632 best dqsien dly found for B1: ( 0, 14, 24)
6834 16:44:32.231615 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6835 16:44:32.235035 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6836 16:44:32.235506
6837 16:44:32.238139 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6838 16:44:32.241423 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6839 16:44:32.244924 [Gating] SW calibration Done
6840 16:44:32.245500 ==
6841 16:44:32.248233 Dram Type= 6, Freq= 0, CH_1, rank 1
6842 16:44:32.251529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 16:44:32.252106 ==
6844 16:44:32.255003 RX Vref Scan: 0
6845 16:44:32.255478
6846 16:44:32.257897 RX Vref 0 -> 0, step: 1
6847 16:44:32.258404
6848 16:44:32.258905 RX Delay -410 -> 252, step: 16
6849 16:44:32.264915 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6850 16:44:32.268419 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6851 16:44:32.271278 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6852 16:44:32.274742 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6853 16:44:32.281756 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6854 16:44:32.284511 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6855 16:44:32.288228 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6856 16:44:32.291162 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6857 16:44:32.297404 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6858 16:44:32.301157 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6859 16:44:32.304294 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6860 16:44:32.311671 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6861 16:44:32.314408 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6862 16:44:32.317851 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6863 16:44:32.321438 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6864 16:44:32.327222 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6865 16:44:32.327663 ==
6866 16:44:32.330829 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 16:44:32.333891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 16:44:32.334430 ==
6869 16:44:32.334777 DQS Delay:
6870 16:44:32.337519 DQS0 = 27, DQS1 = 43
6871 16:44:32.338046 DQM Delay:
6872 16:44:32.340889 DQM0 = 11, DQM1 = 22
6873 16:44:32.341362 DQ Delay:
6874 16:44:32.344197 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6875 16:44:32.347783 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6876 16:44:32.350834 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =24
6877 16:44:32.354034 DQ12 =32, DQ13 =24, DQ14 =32, DQ15 =32
6878 16:44:32.354644
6879 16:44:32.355018
6880 16:44:32.355362 ==
6881 16:44:32.357363 Dram Type= 6, Freq= 0, CH_1, rank 1
6882 16:44:32.360733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6883 16:44:32.361302 ==
6884 16:44:32.361677
6885 16:44:32.362025
6886 16:44:32.363931 TX Vref Scan disable
6887 16:44:32.367204 == TX Byte 0 ==
6888 16:44:32.370929 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6889 16:44:32.373659 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6890 16:44:32.377917 == TX Byte 1 ==
6891 16:44:32.380719 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6892 16:44:32.383841 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6893 16:44:32.384410 ==
6894 16:44:32.387875 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 16:44:32.390871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 16:44:32.391436 ==
6897 16:44:32.391809
6898 16:44:32.392157
6899 16:44:32.393982 TX Vref Scan disable
6900 16:44:32.397501 == TX Byte 0 ==
6901 16:44:32.400518 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 16:44:32.403456 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 16:44:32.406986 == TX Byte 1 ==
6904 16:44:32.410499 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6905 16:44:32.413514 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6906 16:44:32.414072
6907 16:44:32.414474 [DATLAT]
6908 16:44:32.416856 Freq=400, CH1 RK1
6909 16:44:32.417420
6910 16:44:32.417787 DATLAT Default: 0xe
6911 16:44:32.419819 0, 0xFFFF, sum = 0
6912 16:44:32.423476 1, 0xFFFF, sum = 0
6913 16:44:32.423942 2, 0xFFFF, sum = 0
6914 16:44:32.426531 3, 0xFFFF, sum = 0
6915 16:44:32.427001 4, 0xFFFF, sum = 0
6916 16:44:32.429726 5, 0xFFFF, sum = 0
6917 16:44:32.430165 6, 0xFFFF, sum = 0
6918 16:44:32.433246 7, 0xFFFF, sum = 0
6919 16:44:32.433668 8, 0xFFFF, sum = 0
6920 16:44:32.437227 9, 0xFFFF, sum = 0
6921 16:44:32.437759 10, 0xFFFF, sum = 0
6922 16:44:32.440448 11, 0xFFFF, sum = 0
6923 16:44:32.440870 12, 0xFFFF, sum = 0
6924 16:44:32.443002 13, 0x0, sum = 1
6925 16:44:32.443426 14, 0x0, sum = 2
6926 16:44:32.446591 15, 0x0, sum = 3
6927 16:44:32.447019 16, 0x0, sum = 4
6928 16:44:32.449949 best_step = 14
6929 16:44:32.450395
6930 16:44:32.450737 ==
6931 16:44:32.452928 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 16:44:32.456153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 16:44:32.456576 ==
6934 16:44:32.459828 RX Vref Scan: 0
6935 16:44:32.460340
6936 16:44:32.460667 RX Vref 0 -> 0, step: 1
6937 16:44:32.460972
6938 16:44:32.462823 RX Delay -327 -> 252, step: 8
6939 16:44:32.471175 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6940 16:44:32.473704 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6941 16:44:32.477318 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6942 16:44:32.483925 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6943 16:44:32.487312 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6944 16:44:32.490548 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6945 16:44:32.493783 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
6946 16:44:32.497544 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6947 16:44:32.503776 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6948 16:44:32.506958 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6949 16:44:32.510568 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6950 16:44:32.517020 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6951 16:44:32.520244 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6952 16:44:32.523539 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
6953 16:44:32.527190 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6954 16:44:32.533921 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6955 16:44:32.534511 ==
6956 16:44:32.536796 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 16:44:32.540278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 16:44:32.540848 ==
6959 16:44:32.541278 DQS Delay:
6960 16:44:32.543503 DQS0 = 28, DQS1 = 36
6961 16:44:32.543967 DQM Delay:
6962 16:44:32.546625 DQM0 = 9, DQM1 = 12
6963 16:44:32.547136 DQ Delay:
6964 16:44:32.550148 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =12
6965 16:44:32.553874 DQ4 =12, DQ5 =16, DQ6 =12, DQ7 =8
6966 16:44:32.556781 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6967 16:44:32.560297 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6968 16:44:32.560917
6969 16:44:32.561282
6970 16:44:32.566761 [DQSOSCAuto] RK1, (LSB)MR18= 0xad55, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
6971 16:44:32.570177 CH1 RK1: MR19=C0C, MR18=AD55
6972 16:44:32.576446 CH1_RK1: MR19=0xC0C, MR18=0xAD55, DQSOSC=388, MR23=63, INC=392, DEC=261
6973 16:44:32.579559 [RxdqsGatingPostProcess] freq 400
6974 16:44:32.586693 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6975 16:44:32.589828 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 16:44:32.593189 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 16:44:32.593772 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 16:44:32.597214 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 16:44:32.599550 best DQS0 dly(2T, 0.5T) = (0, 10)
6980 16:44:32.603110 best DQS1 dly(2T, 0.5T) = (0, 10)
6981 16:44:32.606176 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6982 16:44:32.609919 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6983 16:44:32.613036 Pre-setting of DQS Precalculation
6984 16:44:32.619352 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6985 16:44:32.626493 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6986 16:44:32.632572 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6987 16:44:32.633142
6988 16:44:32.633504
6989 16:44:32.636137 [Calibration Summary] 800 Mbps
6990 16:44:32.636708 CH 0, Rank 0
6991 16:44:32.639510 SW Impedance : PASS
6992 16:44:32.642554 DUTY Scan : NO K
6993 16:44:32.643117 ZQ Calibration : PASS
6994 16:44:32.646523 Jitter Meter : NO K
6995 16:44:32.649482 CBT Training : PASS
6996 16:44:32.650060 Write leveling : PASS
6997 16:44:32.653068 RX DQS gating : PASS
6998 16:44:32.656065 RX DQ/DQS(RDDQC) : PASS
6999 16:44:32.656574 TX DQ/DQS : PASS
7000 16:44:32.660158 RX DATLAT : PASS
7001 16:44:32.662590 RX DQ/DQS(Engine): PASS
7002 16:44:32.663168 TX OE : NO K
7003 16:44:32.663543 All Pass.
7004 16:44:32.665702
7005 16:44:32.666164 CH 0, Rank 1
7006 16:44:32.669024 SW Impedance : PASS
7007 16:44:32.669587 DUTY Scan : NO K
7008 16:44:32.672622 ZQ Calibration : PASS
7009 16:44:32.673197 Jitter Meter : NO K
7010 16:44:32.676052 CBT Training : PASS
7011 16:44:32.679691 Write leveling : NO K
7012 16:44:32.680261 RX DQS gating : PASS
7013 16:44:32.682787 RX DQ/DQS(RDDQC) : PASS
7014 16:44:32.685533 TX DQ/DQS : PASS
7015 16:44:32.686109 RX DATLAT : PASS
7016 16:44:32.688785 RX DQ/DQS(Engine): PASS
7017 16:44:32.692732 TX OE : NO K
7018 16:44:32.693304 All Pass.
7019 16:44:32.693674
7020 16:44:32.694017 CH 1, Rank 0
7021 16:44:32.695397 SW Impedance : PASS
7022 16:44:32.699201 DUTY Scan : NO K
7023 16:44:32.699769 ZQ Calibration : PASS
7024 16:44:32.702183 Jitter Meter : NO K
7025 16:44:32.705577 CBT Training : PASS
7026 16:44:32.706145 Write leveling : PASS
7027 16:44:32.709027 RX DQS gating : PASS
7028 16:44:32.712201 RX DQ/DQS(RDDQC) : PASS
7029 16:44:32.712669 TX DQ/DQS : PASS
7030 16:44:32.715342 RX DATLAT : PASS
7031 16:44:32.718814 RX DQ/DQS(Engine): PASS
7032 16:44:32.719386 TX OE : NO K
7033 16:44:32.722451 All Pass.
7034 16:44:32.723014
7035 16:44:32.723384 CH 1, Rank 1
7036 16:44:32.725458 SW Impedance : PASS
7037 16:44:32.725951 DUTY Scan : NO K
7038 16:44:32.728443 ZQ Calibration : PASS
7039 16:44:32.732012 Jitter Meter : NO K
7040 16:44:32.732671 CBT Training : PASS
7041 16:44:32.735400 Write leveling : NO K
7042 16:44:32.738694 RX DQS gating : PASS
7043 16:44:32.739266 RX DQ/DQS(RDDQC) : PASS
7044 16:44:32.741896 TX DQ/DQS : PASS
7045 16:44:32.742589 RX DATLAT : PASS
7046 16:44:32.745066 RX DQ/DQS(Engine): PASS
7047 16:44:32.748689 TX OE : NO K
7048 16:44:32.749261 All Pass.
7049 16:44:32.749634
7050 16:44:32.752425 DramC Write-DBI off
7051 16:44:32.754884 PER_BANK_REFRESH: Hybrid Mode
7052 16:44:32.755354 TX_TRACKING: ON
7053 16:44:32.764899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7054 16:44:32.768788 [FAST_K] Save calibration result to emmc
7055 16:44:32.771766 dramc_set_vcore_voltage set vcore to 725000
7056 16:44:32.774835 Read voltage for 1600, 0
7057 16:44:32.775410 Vio18 = 0
7058 16:44:32.775782 Vcore = 725000
7059 16:44:32.777862 Vdram = 0
7060 16:44:32.778326 Vddq = 0
7061 16:44:32.778725 Vmddr = 0
7062 16:44:32.784796 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7063 16:44:32.788115 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7064 16:44:32.791641 MEM_TYPE=3, freq_sel=13
7065 16:44:32.794661 sv_algorithm_assistance_LP4_3733
7066 16:44:32.798059 ============ PULL DRAM RESETB DOWN ============
7067 16:44:32.802410 ========== PULL DRAM RESETB DOWN end =========
7068 16:44:32.807687 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7069 16:44:32.811062 ===================================
7070 16:44:32.814528 LPDDR4 DRAM CONFIGURATION
7071 16:44:32.817446 ===================================
7072 16:44:32.818012 EX_ROW_EN[0] = 0x0
7073 16:44:32.821251 EX_ROW_EN[1] = 0x0
7074 16:44:32.821818 LP4Y_EN = 0x0
7075 16:44:32.824058 WORK_FSP = 0x1
7076 16:44:32.824522 WL = 0x5
7077 16:44:32.827456 RL = 0x5
7078 16:44:32.828022 BL = 0x2
7079 16:44:32.831006 RPST = 0x0
7080 16:44:32.831574 RD_PRE = 0x0
7081 16:44:32.834162 WR_PRE = 0x1
7082 16:44:32.834657 WR_PST = 0x1
7083 16:44:32.837344 DBI_WR = 0x0
7084 16:44:32.837906 DBI_RD = 0x0
7085 16:44:32.840999 OTF = 0x1
7086 16:44:32.843408 ===================================
7087 16:44:32.847592 ===================================
7088 16:44:32.848156 ANA top config
7089 16:44:32.850443 ===================================
7090 16:44:32.853781 DLL_ASYNC_EN = 0
7091 16:44:32.857253 ALL_SLAVE_EN = 0
7092 16:44:32.860251 NEW_RANK_MODE = 1
7093 16:44:32.863794 DLL_IDLE_MODE = 1
7094 16:44:32.864354 LP45_APHY_COMB_EN = 1
7095 16:44:32.866768 TX_ODT_DIS = 0
7096 16:44:32.870275 NEW_8X_MODE = 1
7097 16:44:32.873873 ===================================
7098 16:44:32.876742 ===================================
7099 16:44:32.879861 data_rate = 3200
7100 16:44:32.883445 CKR = 1
7101 16:44:32.884049 DQ_P2S_RATIO = 8
7102 16:44:32.886346 ===================================
7103 16:44:32.889694 CA_P2S_RATIO = 8
7104 16:44:32.892862 DQ_CA_OPEN = 0
7105 16:44:32.896574 DQ_SEMI_OPEN = 0
7106 16:44:32.899950 CA_SEMI_OPEN = 0
7107 16:44:32.903582 CA_FULL_RATE = 0
7108 16:44:32.906617 DQ_CKDIV4_EN = 0
7109 16:44:32.907149 CA_CKDIV4_EN = 0
7110 16:44:32.909752 CA_PREDIV_EN = 0
7111 16:44:32.912976 PH8_DLY = 12
7112 16:44:32.916399 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7113 16:44:32.919347 DQ_AAMCK_DIV = 4
7114 16:44:32.922817 CA_AAMCK_DIV = 4
7115 16:44:32.923339 CA_ADMCK_DIV = 4
7116 16:44:32.926130 DQ_TRACK_CA_EN = 0
7117 16:44:32.929668 CA_PICK = 1600
7118 16:44:32.933069 CA_MCKIO = 1600
7119 16:44:32.936491 MCKIO_SEMI = 0
7120 16:44:32.939233 PLL_FREQ = 3068
7121 16:44:32.942793 DQ_UI_PI_RATIO = 32
7122 16:44:32.945761 CA_UI_PI_RATIO = 0
7123 16:44:32.949113 ===================================
7124 16:44:32.952764 ===================================
7125 16:44:32.953288 memory_type:LPDDR4
7126 16:44:32.956352 GP_NUM : 10
7127 16:44:32.959065 SRAM_EN : 1
7128 16:44:32.959486 MD32_EN : 0
7129 16:44:32.962378 ===================================
7130 16:44:32.965590 [ANA_INIT] >>>>>>>>>>>>>>
7131 16:44:32.969018 <<<<<< [CONFIGURE PHASE]: ANA_TX
7132 16:44:32.972028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7133 16:44:32.975411 ===================================
7134 16:44:32.979854 data_rate = 3200,PCW = 0X7600
7135 16:44:32.982284 ===================================
7136 16:44:32.985687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7137 16:44:32.988798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7138 16:44:32.995547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7139 16:44:32.998549 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7140 16:44:33.002084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7141 16:44:33.005030 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7142 16:44:33.008819 [ANA_INIT] flow start
7143 16:44:33.011685 [ANA_INIT] PLL >>>>>>>>
7144 16:44:33.012253 [ANA_INIT] PLL <<<<<<<<
7145 16:44:33.014880 [ANA_INIT] MIDPI >>>>>>>>
7146 16:44:33.019225 [ANA_INIT] MIDPI <<<<<<<<
7147 16:44:33.021604 [ANA_INIT] DLL >>>>>>>>
7148 16:44:33.022168 [ANA_INIT] DLL <<<<<<<<
7149 16:44:33.025004 [ANA_INIT] flow end
7150 16:44:33.028189 ============ LP4 DIFF to SE enter ============
7151 16:44:33.031747 ============ LP4 DIFF to SE exit ============
7152 16:44:33.034964 [ANA_INIT] <<<<<<<<<<<<<
7153 16:44:33.038188 [Flow] Enable top DCM control >>>>>
7154 16:44:33.041502 [Flow] Enable top DCM control <<<<<
7155 16:44:33.044804 Enable DLL master slave shuffle
7156 16:44:33.051894 ==============================================================
7157 16:44:33.052461 Gating Mode config
7158 16:44:33.057940 ==============================================================
7159 16:44:33.058663 Config description:
7160 16:44:33.067802 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7161 16:44:33.074505 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7162 16:44:33.081511 SELPH_MODE 0: By rank 1: By Phase
7163 16:44:33.084693 ==============================================================
7164 16:44:33.087869 GAT_TRACK_EN = 1
7165 16:44:33.091008 RX_GATING_MODE = 2
7166 16:44:33.094153 RX_GATING_TRACK_MODE = 2
7167 16:44:33.097538 SELPH_MODE = 1
7168 16:44:33.100874 PICG_EARLY_EN = 1
7169 16:44:33.104154 VALID_LAT_VALUE = 1
7170 16:44:33.110716 ==============================================================
7171 16:44:33.114254 Enter into Gating configuration >>>>
7172 16:44:33.117792 Exit from Gating configuration <<<<
7173 16:44:33.121194 Enter into DVFS_PRE_config >>>>>
7174 16:44:33.130711 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7175 16:44:33.134673 Exit from DVFS_PRE_config <<<<<
7176 16:44:33.137976 Enter into PICG configuration >>>>
7177 16:44:33.140944 Exit from PICG configuration <<<<
7178 16:44:33.143592 [RX_INPUT] configuration >>>>>
7179 16:44:33.144111 [RX_INPUT] configuration <<<<<
7180 16:44:33.150652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7181 16:44:33.157793 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7182 16:44:33.160557 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7183 16:44:33.167637 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7184 16:44:33.173246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7185 16:44:33.180838 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7186 16:44:33.184336 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7187 16:44:33.186983 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7188 16:44:33.193608 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7189 16:44:33.196455 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7190 16:44:33.200655 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7191 16:44:33.206945 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7192 16:44:33.209819 ===================================
7193 16:44:33.210432 LPDDR4 DRAM CONFIGURATION
7194 16:44:33.213059 ===================================
7195 16:44:33.216659 EX_ROW_EN[0] = 0x0
7196 16:44:33.217229 EX_ROW_EN[1] = 0x0
7197 16:44:33.219952 LP4Y_EN = 0x0
7198 16:44:33.223251 WORK_FSP = 0x1
7199 16:44:33.223827 WL = 0x5
7200 16:44:33.226933 RL = 0x5
7201 16:44:33.227511 BL = 0x2
7202 16:44:33.229754 RPST = 0x0
7203 16:44:33.230223 RD_PRE = 0x0
7204 16:44:33.232915 WR_PRE = 0x1
7205 16:44:33.233382 WR_PST = 0x1
7206 16:44:33.236569 DBI_WR = 0x0
7207 16:44:33.237146 DBI_RD = 0x0
7208 16:44:33.239530 OTF = 0x1
7209 16:44:33.242682 ===================================
7210 16:44:33.246107 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7211 16:44:33.249463 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7212 16:44:33.256603 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7213 16:44:33.259197 ===================================
7214 16:44:33.259669 LPDDR4 DRAM CONFIGURATION
7215 16:44:33.263768 ===================================
7216 16:44:33.266324 EX_ROW_EN[0] = 0x10
7217 16:44:33.269166 EX_ROW_EN[1] = 0x0
7218 16:44:33.269635 LP4Y_EN = 0x0
7219 16:44:33.272435 WORK_FSP = 0x1
7220 16:44:33.272947 WL = 0x5
7221 16:44:33.275793 RL = 0x5
7222 16:44:33.276265 BL = 0x2
7223 16:44:33.279315 RPST = 0x0
7224 16:44:33.279782 RD_PRE = 0x0
7225 16:44:33.282343 WR_PRE = 0x1
7226 16:44:33.282802 WR_PST = 0x1
7227 16:44:33.285454 DBI_WR = 0x0
7228 16:44:33.285880 DBI_RD = 0x0
7229 16:44:33.288995 OTF = 0x1
7230 16:44:33.292289 ===================================
7231 16:44:33.298835 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7232 16:44:33.299296 ==
7233 16:44:33.301965 Dram Type= 6, Freq= 0, CH_0, rank 0
7234 16:44:33.305903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7235 16:44:33.306335 ==
7236 16:44:33.308555 [Duty_Offset_Calibration]
7237 16:44:33.308999 B0:2 B1:0 CA:1
7238 16:44:33.309338
7239 16:44:33.312644 [DutyScan_Calibration_Flow] k_type=0
7240 16:44:33.321887
7241 16:44:33.322451 ==CLK 0==
7242 16:44:33.325542 Final CLK duty delay cell = -4
7243 16:44:33.329174 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7244 16:44:33.331862 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7245 16:44:33.335235 [-4] AVG Duty = 4922%(X100)
7246 16:44:33.335935
7247 16:44:33.338665 CH0 CLK Duty spec in!! Max-Min= 218%
7248 16:44:33.341770 [DutyScan_Calibration_Flow] ====Done====
7249 16:44:33.342194
7250 16:44:33.345195 [DutyScan_Calibration_Flow] k_type=1
7251 16:44:33.361639
7252 16:44:33.362203 ==DQS 0 ==
7253 16:44:33.364780 Final DQS duty delay cell = 0
7254 16:44:33.368839 [0] MAX Duty = 5249%(X100), DQS PI = 32
7255 16:44:33.371568 [0] MIN Duty = 4969%(X100), DQS PI = 0
7256 16:44:33.374995 [0] AVG Duty = 5109%(X100)
7257 16:44:33.375560
7258 16:44:33.375934 ==DQS 1 ==
7259 16:44:33.377804 Final DQS duty delay cell = -4
7260 16:44:33.381242 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7261 16:44:33.384639 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7262 16:44:33.388128 [-4] AVG Duty = 5000%(X100)
7263 16:44:33.388694
7264 16:44:33.391005 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7265 16:44:33.391478
7266 16:44:33.394885 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7267 16:44:33.398387 [DutyScan_Calibration_Flow] ====Done====
7268 16:44:33.398961
7269 16:44:33.401125 [DutyScan_Calibration_Flow] k_type=3
7270 16:44:33.418903
7271 16:44:33.419463 ==DQM 0 ==
7272 16:44:33.422724 Final DQM duty delay cell = 0
7273 16:44:33.425463 [0] MAX Duty = 5124%(X100), DQS PI = 26
7274 16:44:33.428706 [0] MIN Duty = 4813%(X100), DQS PI = 50
7275 16:44:33.432384 [0] AVG Duty = 4968%(X100)
7276 16:44:33.432874
7277 16:44:33.433299 ==DQM 1 ==
7278 16:44:33.435470 Final DQM duty delay cell = 0
7279 16:44:33.438305 [0] MAX Duty = 5249%(X100), DQS PI = 44
7280 16:44:33.441864 [0] MIN Duty = 5031%(X100), DQS PI = 20
7281 16:44:33.445603 [0] AVG Duty = 5140%(X100)
7282 16:44:33.446188
7283 16:44:33.448480 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7284 16:44:33.448949
7285 16:44:33.451796 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7286 16:44:33.455664 [DutyScan_Calibration_Flow] ====Done====
7287 16:44:33.456231
7288 16:44:33.458715 [DutyScan_Calibration_Flow] k_type=2
7289 16:44:33.476953
7290 16:44:33.477567 ==DQ 0 ==
7291 16:44:33.481250 Final DQ duty delay cell = 0
7292 16:44:33.483854 [0] MAX Duty = 5156%(X100), DQS PI = 36
7293 16:44:33.487016 [0] MIN Duty = 5000%(X100), DQS PI = 16
7294 16:44:33.487491 [0] AVG Duty = 5078%(X100)
7295 16:44:33.490228
7296 16:44:33.490836 ==DQ 1 ==
7297 16:44:33.493522 Final DQ duty delay cell = 4
7298 16:44:33.496697 [4] MAX Duty = 5125%(X100), DQS PI = 2
7299 16:44:33.499859 [4] MIN Duty = 5062%(X100), DQS PI = 0
7300 16:44:33.500390 [4] AVG Duty = 5093%(X100)
7301 16:44:33.500766
7302 16:44:33.503876 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7303 16:44:33.506756
7304 16:44:33.509745 CH0 DQ 1 Duty spec in!! Max-Min= 63%
7305 16:44:33.514190 [DutyScan_Calibration_Flow] ====Done====
7306 16:44:33.514680 ==
7307 16:44:33.516330 Dram Type= 6, Freq= 0, CH_1, rank 0
7308 16:44:33.519543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7309 16:44:33.520004 ==
7310 16:44:33.522842 [Duty_Offset_Calibration]
7311 16:44:33.523300 B0:0 B1:-1 CA:2
7312 16:44:33.523660
7313 16:44:33.526104 [DutyScan_Calibration_Flow] k_type=0
7314 16:44:33.536913
7315 16:44:33.537448 ==CLK 0==
7316 16:44:33.540056 Final CLK duty delay cell = 0
7317 16:44:33.543237 [0] MAX Duty = 5156%(X100), DQS PI = 40
7318 16:44:33.546765 [0] MIN Duty = 4906%(X100), DQS PI = 14
7319 16:44:33.550117 [0] AVG Duty = 5031%(X100)
7320 16:44:33.550569
7321 16:44:33.553188 CH1 CLK Duty spec in!! Max-Min= 250%
7322 16:44:33.556585 [DutyScan_Calibration_Flow] ====Done====
7323 16:44:33.557004
7324 16:44:33.559649 [DutyScan_Calibration_Flow] k_type=1
7325 16:44:33.576287
7326 16:44:33.576709 ==DQS 0 ==
7327 16:44:33.579802 Final DQS duty delay cell = 0
7328 16:44:33.582937 [0] MAX Duty = 5093%(X100), DQS PI = 10
7329 16:44:33.586619 [0] MIN Duty = 5000%(X100), DQS PI = 0
7330 16:44:33.590065 [0] AVG Duty = 5046%(X100)
7331 16:44:33.590607
7332 16:44:33.590989 ==DQS 1 ==
7333 16:44:33.593321 Final DQS duty delay cell = 0
7334 16:44:33.596966 [0] MAX Duty = 5218%(X100), DQS PI = 32
7335 16:44:33.600119 [0] MIN Duty = 4844%(X100), DQS PI = 0
7336 16:44:33.603537 [0] AVG Duty = 5031%(X100)
7337 16:44:33.604098
7338 16:44:33.606581 CH1 DQS 0 Duty spec in!! Max-Min= 93%
7339 16:44:33.607130
7340 16:44:33.609409 CH1 DQS 1 Duty spec in!! Max-Min= 374%
7341 16:44:33.613033 [DutyScan_Calibration_Flow] ====Done====
7342 16:44:33.613492
7343 16:44:33.616380 [DutyScan_Calibration_Flow] k_type=3
7344 16:44:33.633618
7345 16:44:33.634184 ==DQM 0 ==
7346 16:44:33.637454 Final DQM duty delay cell = 4
7347 16:44:33.639879 [4] MAX Duty = 5156%(X100), DQS PI = 22
7348 16:44:33.643337 [4] MIN Duty = 4969%(X100), DQS PI = 0
7349 16:44:33.646677 [4] AVG Duty = 5062%(X100)
7350 16:44:33.647161
7351 16:44:33.647521 ==DQM 1 ==
7352 16:44:33.649809 Final DQM duty delay cell = -4
7353 16:44:33.653010 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7354 16:44:33.656733 [-4] MIN Duty = 4719%(X100), DQS PI = 0
7355 16:44:33.659420 [-4] AVG Duty = 4844%(X100)
7356 16:44:33.659874
7357 16:44:33.662751 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7358 16:44:33.663206
7359 16:44:33.666118 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7360 16:44:33.669457 [DutyScan_Calibration_Flow] ====Done====
7361 16:44:33.670009
7362 16:44:33.672910 [DutyScan_Calibration_Flow] k_type=2
7363 16:44:33.690731
7364 16:44:33.691280 ==DQ 0 ==
7365 16:44:33.694056 Final DQ duty delay cell = 0
7366 16:44:33.697041 [0] MAX Duty = 5093%(X100), DQS PI = 22
7367 16:44:33.700490 [0] MIN Duty = 4938%(X100), DQS PI = 0
7368 16:44:33.701040 [0] AVG Duty = 5015%(X100)
7369 16:44:33.701402
7370 16:44:33.703747 ==DQ 1 ==
7371 16:44:33.706924 Final DQ duty delay cell = 0
7372 16:44:33.710246 [0] MAX Duty = 5094%(X100), DQS PI = 34
7373 16:44:33.713418 [0] MIN Duty = 4813%(X100), DQS PI = 0
7374 16:44:33.713876 [0] AVG Duty = 4953%(X100)
7375 16:44:33.714237
7376 16:44:33.720263 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7377 16:44:33.720858
7378 16:44:33.723644 CH1 DQ 1 Duty spec in!! Max-Min= 281%
7379 16:44:33.727146 [DutyScan_Calibration_Flow] ====Done====
7380 16:44:33.730045 nWR fixed to 30
7381 16:44:33.730666 [ModeRegInit_LP4] CH0 RK0
7382 16:44:33.733106 [ModeRegInit_LP4] CH0 RK1
7383 16:44:33.737018 [ModeRegInit_LP4] CH1 RK0
7384 16:44:33.740143 [ModeRegInit_LP4] CH1 RK1
7385 16:44:33.740709 match AC timing 5
7386 16:44:33.747152 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7387 16:44:33.749967 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7388 16:44:33.753271 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7389 16:44:33.759510 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7390 16:44:33.762778 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7391 16:44:33.763235 [MiockJmeterHQA]
7392 16:44:33.763593
7393 16:44:33.766522 [DramcMiockJmeter] u1RxGatingPI = 0
7394 16:44:33.769939 0 : 4255, 4029
7395 16:44:33.770552 4 : 4363, 4137
7396 16:44:33.772925 8 : 4255, 4029
7397 16:44:33.773486 12 : 4252, 4027
7398 16:44:33.776645 16 : 4253, 4027
7399 16:44:33.777243 20 : 4252, 4027
7400 16:44:33.777621 24 : 4363, 4138
7401 16:44:33.779094 28 : 4363, 4137
7402 16:44:33.779558 32 : 4252, 4027
7403 16:44:33.782974 36 : 4253, 4027
7404 16:44:33.783533 40 : 4253, 4027
7405 16:44:33.785943 44 : 4252, 4027
7406 16:44:33.786538 48 : 4255, 4030
7407 16:44:33.789386 52 : 4365, 4140
7408 16:44:33.789942 56 : 4252, 4027
7409 16:44:33.790310 60 : 4252, 4027
7410 16:44:33.792732 64 : 4250, 4027
7411 16:44:33.793289 68 : 4252, 4030
7412 16:44:33.795857 72 : 4250, 4027
7413 16:44:33.796538 76 : 4363, 4139
7414 16:44:33.799048 80 : 4361, 4138
7415 16:44:33.799512 84 : 4250, 4027
7416 16:44:33.802742 88 : 4252, 3709
7417 16:44:33.803305 92 : 4250, 0
7418 16:44:33.803671 96 : 4363, 0
7419 16:44:33.805809 100 : 4252, 0
7420 16:44:33.806417 104 : 4250, 0
7421 16:44:33.806825 108 : 4250, 0
7422 16:44:33.809168 112 : 4252, 0
7423 16:44:33.809758 116 : 4250, 0
7424 16:44:33.812379 120 : 4361, 0
7425 16:44:33.812941 124 : 4361, 0
7426 16:44:33.813336 128 : 4250, 0
7427 16:44:33.815600 132 : 4361, 0
7428 16:44:33.816064 136 : 4250, 0
7429 16:44:33.819637 140 : 4250, 0
7430 16:44:33.820194 144 : 4250, 0
7431 16:44:33.820561 148 : 4250, 0
7432 16:44:33.822425 152 : 4250, 0
7433 16:44:33.822891 156 : 4250, 0
7434 16:44:33.825754 160 : 4250, 0
7435 16:44:33.826312 164 : 4253, 0
7436 16:44:33.826742 168 : 4360, 0
7437 16:44:33.828690 172 : 4250, 0
7438 16:44:33.829152 176 : 4361, 0
7439 16:44:33.829655 180 : 4361, 0
7440 16:44:33.832477 184 : 4250, 0
7441 16:44:33.833035 188 : 4250, 0
7442 16:44:33.835457 192 : 4250, 0
7443 16:44:33.836071 196 : 4250, 0
7444 16:44:33.836453 200 : 4250, 15
7445 16:44:33.839227 204 : 4250, 2523
7446 16:44:33.839691 208 : 4250, 4027
7447 16:44:33.842536 212 : 4250, 4027
7448 16:44:33.843096 216 : 4250, 4027
7449 16:44:33.845466 220 : 4360, 4138
7450 16:44:33.845930 224 : 4249, 4027
7451 16:44:33.848525 228 : 4361, 4137
7452 16:44:33.848992 232 : 4360, 4137
7453 16:44:33.852180 236 : 4250, 4027
7454 16:44:33.852655 240 : 4250, 4027
7455 16:44:33.855700 244 : 4363, 4140
7456 16:44:33.856270 248 : 4250, 4027
7457 16:44:33.858475 252 : 4250, 4027
7458 16:44:33.858952 256 : 4250, 4027
7459 16:44:33.861527 260 : 4252, 4030
7460 16:44:33.862002 264 : 4250, 4027
7461 16:44:33.862409 268 : 4250, 4027
7462 16:44:33.865228 272 : 4360, 4138
7463 16:44:33.865796 276 : 4250, 4027
7464 16:44:33.868396 280 : 4250, 4026
7465 16:44:33.868869 284 : 4360, 4138
7466 16:44:33.872236 288 : 4250, 4027
7467 16:44:33.872808 292 : 4250, 4027
7468 16:44:33.875111 296 : 4363, 4139
7469 16:44:33.875587 300 : 4249, 4027
7470 16:44:33.878251 304 : 4250, 4027
7471 16:44:33.878763 308 : 4250, 4027
7472 16:44:33.882318 312 : 4252, 3911
7473 16:44:33.882935 316 : 4250, 2006
7474 16:44:33.883318
7475 16:44:33.885028 MIOCK jitter meter ch=0
7476 16:44:33.885591
7477 16:44:33.888471 1T = (316-92) = 224 dly cells
7478 16:44:33.891532 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7479 16:44:33.892096 ==
7480 16:44:33.895014 Dram Type= 6, Freq= 0, CH_0, rank 0
7481 16:44:33.901537 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7482 16:44:33.902143 ==
7483 16:44:33.904871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7484 16:44:33.911643 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7485 16:44:33.914974 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7486 16:44:33.921945 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7487 16:44:33.929436 [CA 0] Center 42 (12~73) winsize 62
7488 16:44:33.932678 [CA 1] Center 43 (13~73) winsize 61
7489 16:44:33.935950 [CA 2] Center 38 (8~68) winsize 61
7490 16:44:33.939295 [CA 3] Center 37 (8~67) winsize 60
7491 16:44:33.942277 [CA 4] Center 36 (6~66) winsize 61
7492 16:44:33.946109 [CA 5] Center 35 (5~65) winsize 61
7493 16:44:33.946855
7494 16:44:33.949058 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7495 16:44:33.949526
7496 16:44:33.952609 [CATrainingPosCal] consider 1 rank data
7497 16:44:33.955783 u2DelayCellTimex100 = 290/100 ps
7498 16:44:33.959250 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7499 16:44:33.966102 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7500 16:44:33.969672 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7501 16:44:33.972738 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7502 16:44:33.975640 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7503 16:44:33.978803 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7504 16:44:33.979273
7505 16:44:33.982320 CA PerBit enable=1, Macro0, CA PI delay=35
7506 16:44:33.982920
7507 16:44:33.985716 [CBTSetCACLKResult] CA Dly = 35
7508 16:44:33.988896 CS Dly: 9 (0~40)
7509 16:44:33.992504 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7510 16:44:33.995340 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7511 16:44:33.995907 ==
7512 16:44:33.998507 Dram Type= 6, Freq= 0, CH_0, rank 1
7513 16:44:34.005274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7514 16:44:34.005899 ==
7515 16:44:34.008458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7516 16:44:34.015440 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7517 16:44:34.018802 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7518 16:44:34.025364 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7519 16:44:34.032875 [CA 0] Center 43 (13~73) winsize 61
7520 16:44:34.035720 [CA 1] Center 43 (13~73) winsize 61
7521 16:44:34.039010 [CA 2] Center 37 (8~67) winsize 60
7522 16:44:34.042473 [CA 3] Center 38 (8~68) winsize 61
7523 16:44:34.046042 [CA 4] Center 36 (6~66) winsize 61
7524 16:44:34.049089 [CA 5] Center 36 (6~66) winsize 61
7525 16:44:34.049561
7526 16:44:34.052400 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7527 16:44:34.052868
7528 16:44:34.055644 [CATrainingPosCal] consider 2 rank data
7529 16:44:34.059380 u2DelayCellTimex100 = 290/100 ps
7530 16:44:34.062167 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7531 16:44:34.069181 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7532 16:44:34.072894 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7533 16:44:34.076084 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7534 16:44:34.079019 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7535 16:44:34.082756 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7536 16:44:34.083329
7537 16:44:34.085702 CA PerBit enable=1, Macro0, CA PI delay=35
7538 16:44:34.086278
7539 16:44:34.088936 [CBTSetCACLKResult] CA Dly = 35
7540 16:44:34.092368 CS Dly: 10 (0~43)
7541 16:44:34.095681 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7542 16:44:34.098965 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7543 16:44:34.099437
7544 16:44:34.102203 ----->DramcWriteLeveling(PI) begin...
7545 16:44:34.102813 ==
7546 16:44:34.106020 Dram Type= 6, Freq= 0, CH_0, rank 0
7547 16:44:34.111855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7548 16:44:34.112358 ==
7549 16:44:34.115628 Write leveling (Byte 0): 34 => 34
7550 16:44:34.118647 Write leveling (Byte 1): 31 => 31
7551 16:44:34.119223 DramcWriteLeveling(PI) end<-----
7552 16:44:34.119602
7553 16:44:34.122068 ==
7554 16:44:34.125496 Dram Type= 6, Freq= 0, CH_0, rank 0
7555 16:44:34.128631 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7556 16:44:34.129208 ==
7557 16:44:34.132223 [Gating] SW mode calibration
7558 16:44:34.138445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7559 16:44:34.141853 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7560 16:44:34.148043 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7561 16:44:34.151350 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 16:44:34.154976 1 4 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7563 16:44:34.161227 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7564 16:44:34.164827 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
7565 16:44:34.167906 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7566 16:44:34.174233 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7567 16:44:34.178156 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7568 16:44:34.181413 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7569 16:44:34.187794 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 16:44:34.191042 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7571 16:44:34.194221 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7572 16:44:34.201054 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
7573 16:44:34.204824 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7574 16:44:34.207624 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7575 16:44:34.215104 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7576 16:44:34.217883 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7577 16:44:34.221373 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7578 16:44:34.227684 1 6 8 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7579 16:44:34.230728 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7580 16:44:34.234229 1 6 16 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
7581 16:44:34.241708 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7582 16:44:34.244264 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 16:44:34.247323 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 16:44:34.253965 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7585 16:44:34.257957 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 16:44:34.261706 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 16:44:34.267594 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7588 16:44:34.270565 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7589 16:44:34.273863 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7590 16:44:34.280964 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7591 16:44:34.284283 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 16:44:34.286886 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 16:44:34.294522 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 16:44:34.297222 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 16:44:34.300654 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 16:44:34.307276 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 16:44:34.310605 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 16:44:34.314388 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 16:44:34.320714 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 16:44:34.323736 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 16:44:34.326873 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 16:44:34.333676 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7603 16:44:34.337385 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7604 16:44:34.340750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7605 16:44:34.343773 Total UI for P1: 0, mck2ui 16
7606 16:44:34.347032 best dqsien dly found for B0: ( 1, 9, 10)
7607 16:44:34.350420 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 16:44:34.356705 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 16:44:34.359970 Total UI for P1: 0, mck2ui 16
7610 16:44:34.364000 best dqsien dly found for B1: ( 1, 9, 20)
7611 16:44:34.367002 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7612 16:44:34.370097 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7613 16:44:34.370608
7614 16:44:34.373308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7615 16:44:34.377130 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7616 16:44:34.379680 [Gating] SW calibration Done
7617 16:44:34.380160 ==
7618 16:44:34.383133 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 16:44:34.387042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 16:44:34.387505 ==
7621 16:44:34.389651 RX Vref Scan: 0
7622 16:44:34.390115
7623 16:44:34.393734 RX Vref 0 -> 0, step: 1
7624 16:44:34.394301
7625 16:44:34.394719 RX Delay 0 -> 252, step: 8
7626 16:44:34.399938 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7627 16:44:34.403285 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7628 16:44:34.406280 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7629 16:44:34.410033 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7630 16:44:34.413493 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7631 16:44:34.419549 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7632 16:44:34.422916 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7633 16:44:34.425934 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7634 16:44:34.430089 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7635 16:44:34.433557 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7636 16:44:34.439406 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7637 16:44:34.442403 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
7638 16:44:34.445895 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7639 16:44:34.449498 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7640 16:44:34.452498 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7641 16:44:34.459260 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7642 16:44:34.459817 ==
7643 16:44:34.462528 Dram Type= 6, Freq= 0, CH_0, rank 0
7644 16:44:34.465737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7645 16:44:34.466303 ==
7646 16:44:34.466739 DQS Delay:
7647 16:44:34.468952 DQS0 = 0, DQS1 = 0
7648 16:44:34.469412 DQM Delay:
7649 16:44:34.472294 DQM0 = 138, DQM1 = 127
7650 16:44:34.472852 DQ Delay:
7651 16:44:34.475658 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7652 16:44:34.479563 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7653 16:44:34.482344 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =127
7654 16:44:34.485870 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7655 16:44:34.488936
7656 16:44:34.489535
7657 16:44:34.489899 ==
7658 16:44:34.492226 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 16:44:34.495480 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 16:44:34.496042 ==
7661 16:44:34.496412
7662 16:44:34.496753
7663 16:44:34.499454 TX Vref Scan disable
7664 16:44:34.500022 == TX Byte 0 ==
7665 16:44:34.505083 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7666 16:44:34.508306 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7667 16:44:34.508802 == TX Byte 1 ==
7668 16:44:34.515550 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7669 16:44:34.519058 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7670 16:44:34.519618 ==
7671 16:44:34.521900 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 16:44:34.525003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 16:44:34.525566 ==
7674 16:44:34.539020
7675 16:44:34.542690 TX Vref early break, caculate TX vref
7676 16:44:34.545765 TX Vref=16, minBit 5, minWin=22, winSum=374
7677 16:44:34.548639 TX Vref=18, minBit 4, minWin=23, winSum=384
7678 16:44:34.551984 TX Vref=20, minBit 4, minWin=24, winSum=397
7679 16:44:34.555178 TX Vref=22, minBit 0, minWin=25, winSum=405
7680 16:44:34.558608 TX Vref=24, minBit 2, minWin=25, winSum=415
7681 16:44:34.565278 TX Vref=26, minBit 5, minWin=25, winSum=423
7682 16:44:34.568915 TX Vref=28, minBit 0, minWin=26, winSum=432
7683 16:44:34.571772 TX Vref=30, minBit 0, minWin=26, winSum=429
7684 16:44:34.575118 TX Vref=32, minBit 0, minWin=25, winSum=418
7685 16:44:34.578852 TX Vref=34, minBit 1, minWin=25, winSum=408
7686 16:44:34.585347 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
7687 16:44:34.585911
7688 16:44:34.588326 Final TX Range 0 Vref 28
7689 16:44:34.588891
7690 16:44:34.589258 ==
7691 16:44:34.591477 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 16:44:34.595068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 16:44:34.595534 ==
7694 16:44:34.595948
7695 16:44:34.596307
7696 16:44:34.597955 TX Vref Scan disable
7697 16:44:34.605340 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7698 16:44:34.605904 == TX Byte 0 ==
7699 16:44:34.607936 u2DelayCellOfst[0]=16 cells (5 PI)
7700 16:44:34.611378 u2DelayCellOfst[1]=20 cells (6 PI)
7701 16:44:34.614345 u2DelayCellOfst[2]=16 cells (5 PI)
7702 16:44:34.618917 u2DelayCellOfst[3]=16 cells (5 PI)
7703 16:44:34.622618 u2DelayCellOfst[4]=10 cells (3 PI)
7704 16:44:34.624159 u2DelayCellOfst[5]=0 cells (0 PI)
7705 16:44:34.627769 u2DelayCellOfst[6]=20 cells (6 PI)
7706 16:44:34.631525 u2DelayCellOfst[7]=16 cells (5 PI)
7707 16:44:34.634670 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7708 16:44:34.637707 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7709 16:44:34.640880 == TX Byte 1 ==
7710 16:44:34.644291 u2DelayCellOfst[8]=0 cells (0 PI)
7711 16:44:34.647622 u2DelayCellOfst[9]=0 cells (0 PI)
7712 16:44:34.650833 u2DelayCellOfst[10]=6 cells (2 PI)
7713 16:44:34.651296 u2DelayCellOfst[11]=0 cells (0 PI)
7714 16:44:34.653940 u2DelayCellOfst[12]=13 cells (4 PI)
7715 16:44:34.657749 u2DelayCellOfst[13]=10 cells (3 PI)
7716 16:44:34.660953 u2DelayCellOfst[14]=13 cells (4 PI)
7717 16:44:34.664392 u2DelayCellOfst[15]=10 cells (3 PI)
7718 16:44:34.670619 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7719 16:44:34.674046 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7720 16:44:34.674646 DramC Write-DBI on
7721 16:44:34.677098 ==
7722 16:44:34.681458 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 16:44:34.683853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 16:44:34.684384 ==
7725 16:44:34.684751
7726 16:44:34.685088
7727 16:44:34.687000 TX Vref Scan disable
7728 16:44:34.687465 == TX Byte 0 ==
7729 16:44:34.693828 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7730 16:44:34.694408 == TX Byte 1 ==
7731 16:44:34.697479 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7732 16:44:34.700365 DramC Write-DBI off
7733 16:44:34.700932
7734 16:44:34.701299 [DATLAT]
7735 16:44:34.703879 Freq=1600, CH0 RK0
7736 16:44:34.704438
7737 16:44:34.704808 DATLAT Default: 0xf
7738 16:44:34.707266 0, 0xFFFF, sum = 0
7739 16:44:34.707833 1, 0xFFFF, sum = 0
7740 16:44:34.710557 2, 0xFFFF, sum = 0
7741 16:44:34.711026 3, 0xFFFF, sum = 0
7742 16:44:34.713548 4, 0xFFFF, sum = 0
7743 16:44:34.714109 5, 0xFFFF, sum = 0
7744 16:44:34.717382 6, 0xFFFF, sum = 0
7745 16:44:34.717949 7, 0xFFFF, sum = 0
7746 16:44:34.720018 8, 0xFFFF, sum = 0
7747 16:44:34.723576 9, 0xFFFF, sum = 0
7748 16:44:34.724142 10, 0xFFFF, sum = 0
7749 16:44:34.726847 11, 0xFFFF, sum = 0
7750 16:44:34.727413 12, 0xFFFF, sum = 0
7751 16:44:34.730400 13, 0xFFFF, sum = 0
7752 16:44:34.730967 14, 0x0, sum = 1
7753 16:44:34.734107 15, 0x0, sum = 2
7754 16:44:34.734723 16, 0x0, sum = 3
7755 16:44:34.736715 17, 0x0, sum = 4
7756 16:44:34.737183 best_step = 15
7757 16:44:34.737548
7758 16:44:34.737888 ==
7759 16:44:34.740076 Dram Type= 6, Freq= 0, CH_0, rank 0
7760 16:44:34.743097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7761 16:44:34.747216 ==
7762 16:44:34.747685 RX Vref Scan: 1
7763 16:44:34.748051
7764 16:44:34.749718 Set Vref Range= 24 -> 127
7765 16:44:34.750182
7766 16:44:34.750583 RX Vref 24 -> 127, step: 1
7767 16:44:34.752995
7768 16:44:34.753458 RX Delay 19 -> 252, step: 4
7769 16:44:34.753824
7770 16:44:34.756971 Set Vref, RX VrefLevel [Byte0]: 24
7771 16:44:34.759948 [Byte1]: 24
7772 16:44:34.763484
7773 16:44:34.764054 Set Vref, RX VrefLevel [Byte0]: 25
7774 16:44:34.766514 [Byte1]: 25
7775 16:44:34.771406
7776 16:44:34.771976 Set Vref, RX VrefLevel [Byte0]: 26
7777 16:44:34.774306 [Byte1]: 26
7778 16:44:34.779039
7779 16:44:34.779624 Set Vref, RX VrefLevel [Byte0]: 27
7780 16:44:34.782272 [Byte1]: 27
7781 16:44:34.786133
7782 16:44:34.786757 Set Vref, RX VrefLevel [Byte0]: 28
7783 16:44:34.789427 [Byte1]: 28
7784 16:44:34.793903
7785 16:44:34.794507 Set Vref, RX VrefLevel [Byte0]: 29
7786 16:44:34.797154 [Byte1]: 29
7787 16:44:34.801238
7788 16:44:34.801706 Set Vref, RX VrefLevel [Byte0]: 30
7789 16:44:34.804887 [Byte1]: 30
7790 16:44:34.808649
7791 16:44:34.809114 Set Vref, RX VrefLevel [Byte0]: 31
7792 16:44:34.812099 [Byte1]: 31
7793 16:44:34.817008
7794 16:44:34.817470 Set Vref, RX VrefLevel [Byte0]: 32
7795 16:44:34.819832 [Byte1]: 32
7796 16:44:34.824344
7797 16:44:34.824926 Set Vref, RX VrefLevel [Byte0]: 33
7798 16:44:34.827178 [Byte1]: 33
7799 16:44:34.832024
7800 16:44:34.832597 Set Vref, RX VrefLevel [Byte0]: 34
7801 16:44:34.835862 [Byte1]: 34
7802 16:44:34.839164
7803 16:44:34.839633 Set Vref, RX VrefLevel [Byte0]: 35
7804 16:44:34.842642 [Byte1]: 35
7805 16:44:34.846645
7806 16:44:34.847109 Set Vref, RX VrefLevel [Byte0]: 36
7807 16:44:34.850029 [Byte1]: 36
7808 16:44:34.854330
7809 16:44:34.854835 Set Vref, RX VrefLevel [Byte0]: 37
7810 16:44:34.857893 [Byte1]: 37
7811 16:44:34.862194
7812 16:44:34.862804 Set Vref, RX VrefLevel [Byte0]: 38
7813 16:44:34.865059 [Byte1]: 38
7814 16:44:34.869504
7815 16:44:34.870069 Set Vref, RX VrefLevel [Byte0]: 39
7816 16:44:34.873572 [Byte1]: 39
7817 16:44:34.877070
7818 16:44:34.877634 Set Vref, RX VrefLevel [Byte0]: 40
7819 16:44:34.880746 [Byte1]: 40
7820 16:44:34.884902
7821 16:44:34.885465 Set Vref, RX VrefLevel [Byte0]: 41
7822 16:44:34.888041 [Byte1]: 41
7823 16:44:34.892726
7824 16:44:34.893286 Set Vref, RX VrefLevel [Byte0]: 42
7825 16:44:34.895531 [Byte1]: 42
7826 16:44:34.900349
7827 16:44:34.900908 Set Vref, RX VrefLevel [Byte0]: 43
7828 16:44:34.903011 [Byte1]: 43
7829 16:44:34.907327
7830 16:44:34.907888 Set Vref, RX VrefLevel [Byte0]: 44
7831 16:44:34.910515 [Byte1]: 44
7832 16:44:34.914889
7833 16:44:34.915454 Set Vref, RX VrefLevel [Byte0]: 45
7834 16:44:34.918032 [Byte1]: 45
7835 16:44:34.922781
7836 16:44:34.923371 Set Vref, RX VrefLevel [Byte0]: 46
7837 16:44:34.928867 [Byte1]: 46
7838 16:44:34.929390
7839 16:44:34.932099 Set Vref, RX VrefLevel [Byte0]: 47
7840 16:44:34.935894 [Byte1]: 47
7841 16:44:34.936463
7842 16:44:34.938943 Set Vref, RX VrefLevel [Byte0]: 48
7843 16:44:34.942286 [Byte1]: 48
7844 16:44:34.942892
7845 16:44:34.945325 Set Vref, RX VrefLevel [Byte0]: 49
7846 16:44:34.948818 [Byte1]: 49
7847 16:44:34.952969
7848 16:44:34.953536 Set Vref, RX VrefLevel [Byte0]: 50
7849 16:44:34.955897 [Byte1]: 50
7850 16:44:34.960308
7851 16:44:34.960869 Set Vref, RX VrefLevel [Byte0]: 51
7852 16:44:34.963389 [Byte1]: 51
7853 16:44:34.968343
7854 16:44:34.968905 Set Vref, RX VrefLevel [Byte0]: 52
7855 16:44:34.971767 [Byte1]: 52
7856 16:44:34.976138
7857 16:44:34.976745 Set Vref, RX VrefLevel [Byte0]: 53
7858 16:44:34.978512 [Byte1]: 53
7859 16:44:34.983184
7860 16:44:34.983666 Set Vref, RX VrefLevel [Byte0]: 54
7861 16:44:34.986908 [Byte1]: 54
7862 16:44:34.991290
7863 16:44:34.991852 Set Vref, RX VrefLevel [Byte0]: 55
7864 16:44:34.994447 [Byte1]: 55
7865 16:44:34.998153
7866 16:44:34.998765 Set Vref, RX VrefLevel [Byte0]: 56
7867 16:44:35.001506 [Byte1]: 56
7868 16:44:35.005873
7869 16:44:35.006483 Set Vref, RX VrefLevel [Byte0]: 57
7870 16:44:35.011663 [Byte1]: 57
7871 16:44:35.013442
7872 16:44:35.013954 Set Vref, RX VrefLevel [Byte0]: 58
7873 16:44:35.016791 [Byte1]: 58
7874 16:44:35.021142
7875 16:44:35.021703 Set Vref, RX VrefLevel [Byte0]: 59
7876 16:44:35.025897 [Byte1]: 59
7877 16:44:35.028513
7878 16:44:35.029074 Set Vref, RX VrefLevel [Byte0]: 60
7879 16:44:35.032034 [Byte1]: 60
7880 16:44:35.036139
7881 16:44:35.036708 Set Vref, RX VrefLevel [Byte0]: 61
7882 16:44:35.039407 [Byte1]: 61
7883 16:44:35.043433
7884 16:44:35.043993 Set Vref, RX VrefLevel [Byte0]: 62
7885 16:44:35.046960 [Byte1]: 62
7886 16:44:35.051025
7887 16:44:35.051563 Set Vref, RX VrefLevel [Byte0]: 63
7888 16:44:35.054691 [Byte1]: 63
7889 16:44:35.058584
7890 16:44:35.059045 Set Vref, RX VrefLevel [Byte0]: 64
7891 16:44:35.062238 [Byte1]: 64
7892 16:44:35.066587
7893 16:44:35.067150 Set Vref, RX VrefLevel [Byte0]: 65
7894 16:44:35.069570 [Byte1]: 65
7895 16:44:35.074113
7896 16:44:35.074736 Set Vref, RX VrefLevel [Byte0]: 66
7897 16:44:35.077070 [Byte1]: 66
7898 16:44:35.081707
7899 16:44:35.082265 Set Vref, RX VrefLevel [Byte0]: 67
7900 16:44:35.084758 [Byte1]: 67
7901 16:44:35.089151
7902 16:44:35.089717 Set Vref, RX VrefLevel [Byte0]: 68
7903 16:44:35.092490 [Byte1]: 68
7904 16:44:35.096560
7905 16:44:35.097124 Set Vref, RX VrefLevel [Byte0]: 69
7906 16:44:35.099700 [Byte1]: 69
7907 16:44:35.104582
7908 16:44:35.105146 Set Vref, RX VrefLevel [Byte0]: 70
7909 16:44:35.108105 [Byte1]: 70
7910 16:44:35.111628
7911 16:44:35.112085 Set Vref, RX VrefLevel [Byte0]: 71
7912 16:44:35.115168 [Byte1]: 71
7913 16:44:35.119547
7914 16:44:35.120106 Set Vref, RX VrefLevel [Byte0]: 72
7915 16:44:35.122414 [Byte1]: 72
7916 16:44:35.126862
7917 16:44:35.127585 Set Vref, RX VrefLevel [Byte0]: 73
7918 16:44:35.130502 [Byte1]: 73
7919 16:44:35.135117
7920 16:44:35.135676 Set Vref, RX VrefLevel [Byte0]: 74
7921 16:44:35.138083 [Byte1]: 74
7922 16:44:35.141746
7923 16:44:35.142204 Set Vref, RX VrefLevel [Byte0]: 75
7924 16:44:35.145660 [Byte1]: 75
7925 16:44:35.149514
7926 16:44:35.150070 Set Vref, RX VrefLevel [Byte0]: 76
7927 16:44:35.153454 [Byte1]: 76
7928 16:44:35.157070
7929 16:44:35.157530 Set Vref, RX VrefLevel [Byte0]: 77
7930 16:44:35.160729 [Byte1]: 77
7931 16:44:35.164703
7932 16:44:35.165162 Set Vref, RX VrefLevel [Byte0]: 78
7933 16:44:35.167801 [Byte1]: 78
7934 16:44:35.172476
7935 16:44:35.173035 Final RX Vref Byte 0 = 59 to rank0
7936 16:44:35.175509 Final RX Vref Byte 1 = 61 to rank0
7937 16:44:35.178616 Final RX Vref Byte 0 = 59 to rank1
7938 16:44:35.182001 Final RX Vref Byte 1 = 61 to rank1==
7939 16:44:35.185494 Dram Type= 6, Freq= 0, CH_0, rank 0
7940 16:44:35.192405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 16:44:35.192964 ==
7942 16:44:35.193335 DQS Delay:
7943 16:44:35.195114 DQS0 = 0, DQS1 = 0
7944 16:44:35.195576 DQM Delay:
7945 16:44:35.195943 DQM0 = 136, DQM1 = 124
7946 16:44:35.198588 DQ Delay:
7947 16:44:35.201781 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7948 16:44:35.205357 DQ4 =140, DQ5 =126, DQ6 =146, DQ7 =144
7949 16:44:35.209128 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =118
7950 16:44:35.211518 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =134
7951 16:44:35.211986
7952 16:44:35.212355
7953 16:44:35.212762
7954 16:44:35.215226 [DramC_TX_OE_Calibration] TA2
7955 16:44:35.218843 Original DQ_B0 (3 6) =30, OEN = 27
7956 16:44:35.221900 Original DQ_B1 (3 6) =30, OEN = 27
7957 16:44:35.225149 24, 0x0, End_B0=24 End_B1=24
7958 16:44:35.228692 25, 0x0, End_B0=25 End_B1=25
7959 16:44:35.229167 26, 0x0, End_B0=26 End_B1=26
7960 16:44:35.231473 27, 0x0, End_B0=27 End_B1=27
7961 16:44:35.234870 28, 0x0, End_B0=28 End_B1=28
7962 16:44:35.238878 29, 0x0, End_B0=29 End_B1=29
7963 16:44:35.239367 30, 0x0, End_B0=30 End_B1=30
7964 16:44:35.241590 31, 0x4141, End_B0=30 End_B1=30
7965 16:44:35.244672 Byte0 end_step=30 best_step=27
7966 16:44:35.248861 Byte1 end_step=30 best_step=27
7967 16:44:35.251299 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 16:44:35.255001 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 16:44:35.255502
7970 16:44:35.255878
7971 16:44:35.261256 [DQSOSCAuto] RK0, (LSB)MR18= 0x201e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
7972 16:44:35.264477 CH0 RK0: MR19=303, MR18=201E
7973 16:44:35.271454 CH0_RK0: MR19=0x303, MR18=0x201E, DQSOSC=393, MR23=63, INC=23, DEC=15
7974 16:44:35.272023
7975 16:44:35.274592 ----->DramcWriteLeveling(PI) begin...
7976 16:44:35.275060 ==
7977 16:44:35.278167 Dram Type= 6, Freq= 0, CH_0, rank 1
7978 16:44:35.281599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 16:44:35.282164 ==
7980 16:44:35.284313 Write leveling (Byte 0): 35 => 35
7981 16:44:35.287725 Write leveling (Byte 1): 29 => 29
7982 16:44:35.291728 DramcWriteLeveling(PI) end<-----
7983 16:44:35.292294
7984 16:44:35.292657 ==
7985 16:44:35.294255 Dram Type= 6, Freq= 0, CH_0, rank 1
7986 16:44:35.297723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7987 16:44:35.300848 ==
7988 16:44:35.301419 [Gating] SW mode calibration
7989 16:44:35.310606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7990 16:44:35.314040 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7991 16:44:35.318267 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 16:44:35.324004 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 16:44:35.328372 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7994 16:44:35.330623 1 4 12 | B1->B0 | 2424 2e2e | 1 0 | (1 1) (0 0)
7995 16:44:35.337853 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 16:44:35.340955 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 16:44:35.343784 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 16:44:35.350845 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 16:44:35.353421 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8000 16:44:35.356989 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8001 16:44:35.363810 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8002 16:44:35.366891 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8003 16:44:35.370270 1 5 16 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8004 16:44:35.376705 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 16:44:35.380048 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 16:44:35.383388 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 16:44:35.389824 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 16:44:35.393184 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 16:44:35.396567 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8010 16:44:35.403181 1 6 12 | B1->B0 | 2c2c 3f3f | 1 0 | (0 0) (1 1)
8011 16:44:35.406641 1 6 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8012 16:44:35.410205 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 16:44:35.416570 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 16:44:35.420135 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 16:44:35.423321 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 16:44:35.429250 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 16:44:35.433276 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 16:44:35.436533 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8019 16:44:35.442852 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8020 16:44:35.446104 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 16:44:35.449865 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 16:44:35.455778 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 16:44:35.459262 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 16:44:35.462449 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 16:44:35.470011 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 16:44:35.472177 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 16:44:35.475733 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 16:44:35.482233 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 16:44:35.485921 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 16:44:35.488938 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 16:44:35.495736 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 16:44:35.498831 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 16:44:35.502191 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8034 16:44:35.509216 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8035 16:44:35.512012 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8036 16:44:35.515476 Total UI for P1: 0, mck2ui 16
8037 16:44:35.518660 best dqsien dly found for B0: ( 1, 9, 10)
8038 16:44:35.521889 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 16:44:35.525070 Total UI for P1: 0, mck2ui 16
8040 16:44:35.528741 best dqsien dly found for B1: ( 1, 9, 14)
8041 16:44:35.531870 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8042 16:44:35.535278 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8043 16:44:35.535832
8044 16:44:35.542417 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8045 16:44:35.545953 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8046 16:44:35.548919 [Gating] SW calibration Done
8047 16:44:35.549383 ==
8048 16:44:35.551800 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 16:44:35.555255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 16:44:35.555732 ==
8051 16:44:35.556096 RX Vref Scan: 0
8052 16:44:35.556442
8053 16:44:35.558401 RX Vref 0 -> 0, step: 1
8054 16:44:35.558867
8055 16:44:35.561736 RX Delay 0 -> 252, step: 8
8056 16:44:35.565655 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8057 16:44:35.568304 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8058 16:44:35.575004 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8059 16:44:35.578299 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8060 16:44:35.581822 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8061 16:44:35.585287 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8062 16:44:35.588644 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8063 16:44:35.595150 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8064 16:44:35.598573 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8065 16:44:35.601894 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8066 16:44:35.604522 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8067 16:44:35.608307 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8068 16:44:35.615191 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8069 16:44:35.618337 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8070 16:44:35.621304 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8071 16:44:35.624367 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8072 16:44:35.624864 ==
8073 16:44:35.627667 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 16:44:35.634857 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 16:44:35.635418 ==
8076 16:44:35.635789 DQS Delay:
8077 16:44:35.637766 DQS0 = 0, DQS1 = 0
8078 16:44:35.638315 DQM Delay:
8079 16:44:35.638741 DQM0 = 136, DQM1 = 125
8080 16:44:35.641430 DQ Delay:
8081 16:44:35.644838 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8082 16:44:35.647732 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8083 16:44:35.651056 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8084 16:44:35.654766 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8085 16:44:35.655326
8086 16:44:35.655690
8087 16:44:35.656030 ==
8088 16:44:35.657591 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 16:44:35.660901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 16:44:35.664717 ==
8091 16:44:35.665274
8092 16:44:35.665642
8093 16:44:35.666077 TX Vref Scan disable
8094 16:44:35.667803 == TX Byte 0 ==
8095 16:44:35.670889 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8096 16:44:35.674333 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8097 16:44:35.677859 == TX Byte 1 ==
8098 16:44:35.680683 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8099 16:44:35.684828 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8100 16:44:35.687688 ==
8101 16:44:35.690586 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 16:44:35.694179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 16:44:35.694794 ==
8104 16:44:35.707423
8105 16:44:35.710784 TX Vref early break, caculate TX vref
8106 16:44:35.714099 TX Vref=16, minBit 8, minWin=23, winSum=389
8107 16:44:35.717079 TX Vref=18, minBit 8, minWin=23, winSum=399
8108 16:44:35.720438 TX Vref=20, minBit 0, minWin=25, winSum=406
8109 16:44:35.723679 TX Vref=22, minBit 0, minWin=25, winSum=413
8110 16:44:35.727033 TX Vref=24, minBit 3, minWin=25, winSum=422
8111 16:44:35.733262 TX Vref=26, minBit 0, minWin=26, winSum=429
8112 16:44:35.737009 TX Vref=28, minBit 0, minWin=26, winSum=435
8113 16:44:35.739780 TX Vref=30, minBit 2, minWin=25, winSum=431
8114 16:44:35.743965 TX Vref=32, minBit 2, minWin=25, winSum=421
8115 16:44:35.747079 TX Vref=34, minBit 0, minWin=24, winSum=412
8116 16:44:35.753514 [TxChooseVref] Worse bit 0, Min win 26, Win sum 435, Final Vref 28
8117 16:44:35.754081
8118 16:44:35.756947 Final TX Range 0 Vref 28
8119 16:44:35.757511
8120 16:44:35.757879 ==
8121 16:44:35.760885 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 16:44:35.763075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 16:44:35.763544 ==
8124 16:44:35.763914
8125 16:44:35.764254
8126 16:44:35.766288 TX Vref Scan disable
8127 16:44:35.773313 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8128 16:44:35.773879 == TX Byte 0 ==
8129 16:44:35.776374 u2DelayCellOfst[0]=13 cells (4 PI)
8130 16:44:35.779433 u2DelayCellOfst[1]=16 cells (5 PI)
8131 16:44:35.782941 u2DelayCellOfst[2]=13 cells (4 PI)
8132 16:44:35.786015 u2DelayCellOfst[3]=13 cells (4 PI)
8133 16:44:35.789548 u2DelayCellOfst[4]=6 cells (2 PI)
8134 16:44:35.792468 u2DelayCellOfst[5]=0 cells (0 PI)
8135 16:44:35.795893 u2DelayCellOfst[6]=16 cells (5 PI)
8136 16:44:35.799188 u2DelayCellOfst[7]=16 cells (5 PI)
8137 16:44:35.802845 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8138 16:44:35.806189 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8139 16:44:35.809254 == TX Byte 1 ==
8140 16:44:35.812288 u2DelayCellOfst[8]=0 cells (0 PI)
8141 16:44:35.816163 u2DelayCellOfst[9]=0 cells (0 PI)
8142 16:44:35.816725 u2DelayCellOfst[10]=6 cells (2 PI)
8143 16:44:35.820189 u2DelayCellOfst[11]=3 cells (1 PI)
8144 16:44:35.822593 u2DelayCellOfst[12]=10 cells (3 PI)
8145 16:44:35.826088 u2DelayCellOfst[13]=10 cells (3 PI)
8146 16:44:35.829039 u2DelayCellOfst[14]=13 cells (4 PI)
8147 16:44:35.833461 u2DelayCellOfst[15]=10 cells (3 PI)
8148 16:44:35.839123 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8149 16:44:35.843023 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8150 16:44:35.843586 DramC Write-DBI on
8151 16:44:35.843955 ==
8152 16:44:35.846146 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 16:44:35.852456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 16:44:35.853033 ==
8155 16:44:35.853403
8156 16:44:35.853741
8157 16:44:35.854065 TX Vref Scan disable
8158 16:44:35.857032 == TX Byte 0 ==
8159 16:44:35.859405 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8160 16:44:35.863285 == TX Byte 1 ==
8161 16:44:35.866408 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8162 16:44:35.869872 DramC Write-DBI off
8163 16:44:35.870475
8164 16:44:35.870849 [DATLAT]
8165 16:44:35.871191 Freq=1600, CH0 RK1
8166 16:44:35.871753
8167 16:44:35.872880 DATLAT Default: 0xf
8168 16:44:35.873340 0, 0xFFFF, sum = 0
8169 16:44:35.876384 1, 0xFFFF, sum = 0
8170 16:44:35.879682 2, 0xFFFF, sum = 0
8171 16:44:35.880154 3, 0xFFFF, sum = 0
8172 16:44:35.882930 4, 0xFFFF, sum = 0
8173 16:44:35.883482 5, 0xFFFF, sum = 0
8174 16:44:35.886265 6, 0xFFFF, sum = 0
8175 16:44:35.886879 7, 0xFFFF, sum = 0
8176 16:44:35.889430 8, 0xFFFF, sum = 0
8177 16:44:35.889935 9, 0xFFFF, sum = 0
8178 16:44:35.893076 10, 0xFFFF, sum = 0
8179 16:44:35.893690 11, 0xFFFF, sum = 0
8180 16:44:35.896572 12, 0xFFFF, sum = 0
8181 16:44:35.897043 13, 0xFFFF, sum = 0
8182 16:44:35.900084 14, 0x0, sum = 1
8183 16:44:35.900555 15, 0x0, sum = 2
8184 16:44:35.902778 16, 0x0, sum = 3
8185 16:44:35.903354 17, 0x0, sum = 4
8186 16:44:35.906428 best_step = 15
8187 16:44:35.906988
8188 16:44:35.907352 ==
8189 16:44:35.909576 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 16:44:35.912790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 16:44:35.913255 ==
8192 16:44:35.916419 RX Vref Scan: 0
8193 16:44:35.917009
8194 16:44:35.917377 RX Vref 0 -> 0, step: 1
8195 16:44:35.917782
8196 16:44:35.919672 RX Delay 11 -> 252, step: 4
8197 16:44:35.923272 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8198 16:44:35.929844 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8199 16:44:35.933223 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8200 16:44:35.936074 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8201 16:44:35.939175 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8202 16:44:35.942784 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8203 16:44:35.949569 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8204 16:44:35.952833 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8205 16:44:35.956076 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8206 16:44:35.959500 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8207 16:44:35.962454 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8208 16:44:35.969047 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8209 16:44:35.972323 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8210 16:44:35.975532 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8211 16:44:35.978701 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8212 16:44:35.985750 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8213 16:44:35.986317 ==
8214 16:44:35.989133 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 16:44:35.991883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 16:44:35.992449 ==
8217 16:44:35.992824 DQS Delay:
8218 16:44:35.995332 DQS0 = 0, DQS1 = 0
8219 16:44:35.995890 DQM Delay:
8220 16:44:35.998704 DQM0 = 133, DQM1 = 123
8221 16:44:35.999164 DQ Delay:
8222 16:44:36.001840 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8223 16:44:36.005227 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
8224 16:44:36.008743 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8225 16:44:36.011728 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8226 16:44:36.012191
8227 16:44:36.015001
8228 16:44:36.015463
8229 16:44:36.015828 [DramC_TX_OE_Calibration] TA2
8230 16:44:36.018707 Original DQ_B0 (3 6) =30, OEN = 27
8231 16:44:36.021731 Original DQ_B1 (3 6) =30, OEN = 27
8232 16:44:36.025283 24, 0x0, End_B0=24 End_B1=24
8233 16:44:36.028708 25, 0x0, End_B0=25 End_B1=25
8234 16:44:36.031621 26, 0x0, End_B0=26 End_B1=26
8235 16:44:36.032195 27, 0x0, End_B0=27 End_B1=27
8236 16:44:36.035186 28, 0x0, End_B0=28 End_B1=28
8237 16:44:36.038623 29, 0x0, End_B0=29 End_B1=29
8238 16:44:36.041508 30, 0x0, End_B0=30 End_B1=30
8239 16:44:36.044855 31, 0x4141, End_B0=30 End_B1=30
8240 16:44:36.045446 Byte0 end_step=30 best_step=27
8241 16:44:36.047981 Byte1 end_step=30 best_step=27
8242 16:44:36.051538 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 16:44:36.054852 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 16:44:36.055604
8245 16:44:36.055995
8246 16:44:36.064976 [DQSOSCAuto] RK1, (LSB)MR18= 0x2310, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8247 16:44:36.065548 CH0 RK1: MR19=303, MR18=2310
8248 16:44:36.071779 CH0_RK1: MR19=0x303, MR18=0x2310, DQSOSC=392, MR23=63, INC=24, DEC=16
8249 16:44:36.075268 [RxdqsGatingPostProcess] freq 1600
8250 16:44:36.081609 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 16:44:36.084837 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 16:44:36.088607 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 16:44:36.089177 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 16:44:36.091372 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 16:44:36.094602 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 16:44:36.098486 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 16:44:36.101644 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 16:44:36.105109 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 16:44:36.108965 Pre-setting of DQS Precalculation
8260 16:44:36.114970 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 16:44:36.115438 ==
8262 16:44:36.117584 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 16:44:36.121735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 16:44:36.122303 ==
8265 16:44:36.127353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 16:44:36.130936 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 16:44:36.133919 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 16:44:36.141225 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 16:44:36.149517 [CA 0] Center 41 (11~71) winsize 61
8270 16:44:36.152264 [CA 1] Center 41 (11~71) winsize 61
8271 16:44:36.155830 [CA 2] Center 37 (8~66) winsize 59
8272 16:44:36.159365 [CA 3] Center 36 (7~66) winsize 60
8273 16:44:36.162623 [CA 4] Center 37 (7~67) winsize 61
8274 16:44:36.166855 [CA 5] Center 36 (7~66) winsize 60
8275 16:44:36.167425
8276 16:44:36.169483 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 16:44:36.170047
8278 16:44:36.173089 [CATrainingPosCal] consider 1 rank data
8279 16:44:36.176082 u2DelayCellTimex100 = 290/100 ps
8280 16:44:36.179471 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8281 16:44:36.185876 CA1 delay=41 (11~71),Diff = 5 PI (16 cell)
8282 16:44:36.189770 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8283 16:44:36.192885 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8284 16:44:36.195998 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8285 16:44:36.199049 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 16:44:36.199514
8287 16:44:36.203045 CA PerBit enable=1, Macro0, CA PI delay=36
8288 16:44:36.203613
8289 16:44:36.205727 [CBTSetCACLKResult] CA Dly = 36
8290 16:44:36.209441 CS Dly: 9 (0~40)
8291 16:44:36.212854 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 16:44:36.215560 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 16:44:36.216051 ==
8294 16:44:36.219187 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 16:44:36.222385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 16:44:36.225940 ==
8297 16:44:36.229266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 16:44:36.232467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 16:44:36.239176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 16:44:36.244966 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 16:44:36.252529 [CA 0] Center 42 (12~72) winsize 61
8302 16:44:36.255954 [CA 1] Center 42 (12~72) winsize 61
8303 16:44:36.258734 [CA 2] Center 38 (9~68) winsize 60
8304 16:44:36.262901 [CA 3] Center 37 (8~67) winsize 60
8305 16:44:36.266118 [CA 4] Center 38 (9~67) winsize 59
8306 16:44:36.269118 [CA 5] Center 37 (8~67) winsize 60
8307 16:44:36.269680
8308 16:44:36.272076 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 16:44:36.272526
8310 16:44:36.275446 [CATrainingPosCal] consider 2 rank data
8311 16:44:36.279168 u2DelayCellTimex100 = 290/100 ps
8312 16:44:36.285236 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8313 16:44:36.288488 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8314 16:44:36.292015 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8315 16:44:36.295706 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 16:44:36.299237 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8317 16:44:36.302312 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8318 16:44:36.302908
8319 16:44:36.305210 CA PerBit enable=1, Macro0, CA PI delay=37
8320 16:44:36.305659
8321 16:44:36.308876 [CBTSetCACLKResult] CA Dly = 37
8322 16:44:36.311946 CS Dly: 10 (0~42)
8323 16:44:36.315119 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 16:44:36.318835 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 16:44:36.319290
8326 16:44:36.321855 ----->DramcWriteLeveling(PI) begin...
8327 16:44:36.322563 ==
8328 16:44:36.325071 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 16:44:36.331656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 16:44:36.332112 ==
8331 16:44:36.334887 Write leveling (Byte 0): 27 => 27
8332 16:44:36.338125 Write leveling (Byte 1): 28 => 28
8333 16:44:36.338840 DramcWriteLeveling(PI) end<-----
8334 16:44:36.339221
8335 16:44:36.341770 ==
8336 16:44:36.344733 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 16:44:36.348693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 16:44:36.349247 ==
8339 16:44:36.351366 [Gating] SW mode calibration
8340 16:44:36.357777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 16:44:36.360965 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 16:44:36.367771 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 16:44:36.370970 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 16:44:36.374725 1 4 8 | B1->B0 | 2323 2828 | 1 1 | (1 1) (0 0)
8345 16:44:36.380900 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 16:44:36.384244 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 16:44:36.387727 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 16:44:36.394132 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 16:44:36.397539 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 16:44:36.404798 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 16:44:36.407791 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
8352 16:44:36.410508 1 5 8 | B1->B0 | 3131 2b2b | 1 0 | (1 1) (0 1)
8353 16:44:36.416981 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8354 16:44:36.420457 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 16:44:36.423962 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 16:44:36.427581 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 16:44:36.433881 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 16:44:36.437477 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 16:44:36.439974 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8360 16:44:36.447049 1 6 8 | B1->B0 | 2b2b 3f3f | 1 0 | (0 0) (1 1)
8361 16:44:36.450344 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 16:44:36.453390 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 16:44:36.459863 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 16:44:36.463177 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 16:44:36.467380 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 16:44:36.473452 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 16:44:36.476632 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 16:44:36.480180 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8369 16:44:36.487044 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8370 16:44:36.490083 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 16:44:36.493190 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 16:44:36.499674 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 16:44:36.503242 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 16:44:36.506403 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 16:44:36.513112 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 16:44:36.516231 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 16:44:36.519509 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 16:44:36.526597 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 16:44:36.529531 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 16:44:36.533185 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 16:44:36.540639 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 16:44:36.542667 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 16:44:36.546203 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 16:44:36.552669 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8385 16:44:36.555965 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8386 16:44:36.559178 Total UI for P1: 0, mck2ui 16
8387 16:44:36.562548 best dqsien dly found for B0: ( 1, 9, 8)
8388 16:44:36.565851 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 16:44:36.569542 Total UI for P1: 0, mck2ui 16
8390 16:44:36.572679 best dqsien dly found for B1: ( 1, 9, 12)
8391 16:44:36.576230 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8392 16:44:36.578954 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8393 16:44:36.579420
8394 16:44:36.585889 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8395 16:44:36.589710 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8396 16:44:36.592703 [Gating] SW calibration Done
8397 16:44:36.593268 ==
8398 16:44:36.595639 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 16:44:36.599183 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 16:44:36.599760 ==
8401 16:44:36.600135 RX Vref Scan: 0
8402 16:44:36.600479
8403 16:44:36.602180 RX Vref 0 -> 0, step: 1
8404 16:44:36.602784
8405 16:44:36.605377 RX Delay 0 -> 252, step: 8
8406 16:44:36.608879 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8407 16:44:36.612061 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8408 16:44:36.615311 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8409 16:44:36.622152 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8410 16:44:36.625869 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8411 16:44:36.628951 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8412 16:44:36.631911 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8413 16:44:36.636083 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8414 16:44:36.642432 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8415 16:44:36.645670 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8416 16:44:36.648930 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8417 16:44:36.652067 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8418 16:44:36.654895 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8419 16:44:36.661937 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8420 16:44:36.664995 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8421 16:44:36.668253 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8422 16:44:36.668722 ==
8423 16:44:36.671515 Dram Type= 6, Freq= 0, CH_1, rank 0
8424 16:44:36.679014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8425 16:44:36.679590 ==
8426 16:44:36.679960 DQS Delay:
8427 16:44:36.680302 DQS0 = 0, DQS1 = 0
8428 16:44:36.681305 DQM Delay:
8429 16:44:36.681762 DQM0 = 137, DQM1 = 129
8430 16:44:36.684686 DQ Delay:
8431 16:44:36.688154 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8432 16:44:36.691961 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8433 16:44:36.694952 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8434 16:44:36.698701 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8435 16:44:36.699272
8436 16:44:36.699641
8437 16:44:36.700025 ==
8438 16:44:36.701220 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 16:44:36.704933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 16:44:36.705508 ==
8441 16:44:36.707977
8442 16:44:36.708545
8443 16:44:36.708911 TX Vref Scan disable
8444 16:44:36.712007 == TX Byte 0 ==
8445 16:44:36.714672 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8446 16:44:36.718187 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8447 16:44:36.722189 == TX Byte 1 ==
8448 16:44:36.725397 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8449 16:44:36.727923 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8450 16:44:36.728407 ==
8451 16:44:36.731378 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 16:44:36.738058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 16:44:36.738679 ==
8454 16:44:36.750806
8455 16:44:36.753941 TX Vref early break, caculate TX vref
8456 16:44:36.757215 TX Vref=16, minBit 15, minWin=21, winSum=373
8457 16:44:36.760491 TX Vref=18, minBit 9, minWin=22, winSum=382
8458 16:44:36.763680 TX Vref=20, minBit 15, minWin=23, winSum=390
8459 16:44:36.767244 TX Vref=22, minBit 3, minWin=24, winSum=402
8460 16:44:36.770445 TX Vref=24, minBit 15, minWin=24, winSum=416
8461 16:44:36.777181 TX Vref=26, minBit 15, minWin=24, winSum=419
8462 16:44:36.781313 TX Vref=28, minBit 15, minWin=25, winSum=422
8463 16:44:36.783700 TX Vref=30, minBit 13, minWin=25, winSum=422
8464 16:44:36.786825 TX Vref=32, minBit 10, minWin=23, winSum=411
8465 16:44:36.790508 TX Vref=34, minBit 13, minWin=23, winSum=404
8466 16:44:36.796944 TX Vref=36, minBit 10, minWin=22, winSum=394
8467 16:44:36.800043 [TxChooseVref] Worse bit 15, Min win 25, Win sum 422, Final Vref 28
8468 16:44:36.803931
8469 16:44:36.804493 Final TX Range 0 Vref 28
8470 16:44:36.804873
8471 16:44:36.805219 ==
8472 16:44:36.807012 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 16:44:36.813834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 16:44:36.814447 ==
8475 16:44:36.814870
8476 16:44:36.815263
8477 16:44:36.815599 TX Vref Scan disable
8478 16:44:36.820755 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8479 16:44:36.821323 == TX Byte 0 ==
8480 16:44:36.824334 u2DelayCellOfst[0]=13 cells (4 PI)
8481 16:44:36.827323 u2DelayCellOfst[1]=10 cells (3 PI)
8482 16:44:36.830487 u2DelayCellOfst[2]=0 cells (0 PI)
8483 16:44:36.833937 u2DelayCellOfst[3]=3 cells (1 PI)
8484 16:44:36.837276 u2DelayCellOfst[4]=3 cells (1 PI)
8485 16:44:36.840852 u2DelayCellOfst[5]=16 cells (5 PI)
8486 16:44:36.843579 u2DelayCellOfst[6]=16 cells (5 PI)
8487 16:44:36.847115 u2DelayCellOfst[7]=3 cells (1 PI)
8488 16:44:36.850475 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8489 16:44:36.853940 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8490 16:44:36.857484 == TX Byte 1 ==
8491 16:44:36.860568 u2DelayCellOfst[8]=0 cells (0 PI)
8492 16:44:36.863670 u2DelayCellOfst[9]=0 cells (0 PI)
8493 16:44:36.867027 u2DelayCellOfst[10]=6 cells (2 PI)
8494 16:44:36.870448 u2DelayCellOfst[11]=0 cells (0 PI)
8495 16:44:36.871014 u2DelayCellOfst[12]=13 cells (4 PI)
8496 16:44:36.873934 u2DelayCellOfst[13]=13 cells (4 PI)
8497 16:44:36.876678 u2DelayCellOfst[14]=13 cells (4 PI)
8498 16:44:36.879852 u2DelayCellOfst[15]=10 cells (3 PI)
8499 16:44:36.886474 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8500 16:44:36.890478 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 16:44:36.891055 DramC Write-DBI on
8502 16:44:36.893558 ==
8503 16:44:36.896860 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 16:44:36.900211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 16:44:36.900686 ==
8506 16:44:36.901057
8507 16:44:36.901406
8508 16:44:36.903039 TX Vref Scan disable
8509 16:44:36.903513 == TX Byte 0 ==
8510 16:44:36.909988 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8511 16:44:36.910595 == TX Byte 1 ==
8512 16:44:36.913549 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 16:44:36.916364 DramC Write-DBI off
8514 16:44:36.916838
8515 16:44:36.917207 [DATLAT]
8516 16:44:36.919972 Freq=1600, CH1 RK0
8517 16:44:36.920588
8518 16:44:36.920967 DATLAT Default: 0xf
8519 16:44:36.923254 0, 0xFFFF, sum = 0
8520 16:44:36.923830 1, 0xFFFF, sum = 0
8521 16:44:36.926686 2, 0xFFFF, sum = 0
8522 16:44:36.927180 3, 0xFFFF, sum = 0
8523 16:44:36.930021 4, 0xFFFF, sum = 0
8524 16:44:36.930671 5, 0xFFFF, sum = 0
8525 16:44:36.932643 6, 0xFFFF, sum = 0
8526 16:44:36.936886 7, 0xFFFF, sum = 0
8527 16:44:36.937460 8, 0xFFFF, sum = 0
8528 16:44:36.938999 9, 0xFFFF, sum = 0
8529 16:44:36.939477 10, 0xFFFF, sum = 0
8530 16:44:36.942979 11, 0xFFFF, sum = 0
8531 16:44:36.943555 12, 0xFFFF, sum = 0
8532 16:44:36.946453 13, 0xFFFF, sum = 0
8533 16:44:36.947025 14, 0x0, sum = 1
8534 16:44:36.949914 15, 0x0, sum = 2
8535 16:44:36.950518 16, 0x0, sum = 3
8536 16:44:36.952678 17, 0x0, sum = 4
8537 16:44:36.953256 best_step = 15
8538 16:44:36.953633
8539 16:44:36.953984 ==
8540 16:44:36.955915 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 16:44:36.959305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 16:44:36.962516 ==
8543 16:44:36.963083 RX Vref Scan: 1
8544 16:44:36.963461
8545 16:44:36.966231 Set Vref Range= 24 -> 127
8546 16:44:36.966740
8547 16:44:36.969470 RX Vref 24 -> 127, step: 1
8548 16:44:36.970040
8549 16:44:36.970490 RX Delay 19 -> 252, step: 4
8550 16:44:36.970860
8551 16:44:36.972620 Set Vref, RX VrefLevel [Byte0]: 24
8552 16:44:36.975559 [Byte1]: 24
8553 16:44:36.979314
8554 16:44:36.979881 Set Vref, RX VrefLevel [Byte0]: 25
8555 16:44:36.982688 [Byte1]: 25
8556 16:44:36.987717
8557 16:44:36.988283 Set Vref, RX VrefLevel [Byte0]: 26
8558 16:44:36.990813 [Byte1]: 26
8559 16:44:36.995377
8560 16:44:36.995953 Set Vref, RX VrefLevel [Byte0]: 27
8561 16:44:36.997935 [Byte1]: 27
8562 16:44:37.002026
8563 16:44:37.002618 Set Vref, RX VrefLevel [Byte0]: 28
8564 16:44:37.005374 [Byte1]: 28
8565 16:44:37.010163
8566 16:44:37.010767 Set Vref, RX VrefLevel [Byte0]: 29
8567 16:44:37.013273 [Byte1]: 29
8568 16:44:37.017798
8569 16:44:37.018398 Set Vref, RX VrefLevel [Byte0]: 30
8570 16:44:37.021147 [Byte1]: 30
8571 16:44:37.024741
8572 16:44:37.025302 Set Vref, RX VrefLevel [Byte0]: 31
8573 16:44:37.029319 [Byte1]: 31
8574 16:44:37.032773
8575 16:44:37.033333 Set Vref, RX VrefLevel [Byte0]: 32
8576 16:44:37.036127 [Byte1]: 32
8577 16:44:37.040578
8578 16:44:37.041143 Set Vref, RX VrefLevel [Byte0]: 33
8579 16:44:37.043718 [Byte1]: 33
8580 16:44:37.047735
8581 16:44:37.048301 Set Vref, RX VrefLevel [Byte0]: 34
8582 16:44:37.051622 [Byte1]: 34
8583 16:44:37.055080
8584 16:44:37.055641 Set Vref, RX VrefLevel [Byte0]: 35
8585 16:44:37.058547 [Byte1]: 35
8586 16:44:37.062856
8587 16:44:37.063422 Set Vref, RX VrefLevel [Byte0]: 36
8588 16:44:37.066193 [Byte1]: 36
8589 16:44:37.070694
8590 16:44:37.071256 Set Vref, RX VrefLevel [Byte0]: 37
8591 16:44:37.073903 [Byte1]: 37
8592 16:44:37.078175
8593 16:44:37.078803 Set Vref, RX VrefLevel [Byte0]: 38
8594 16:44:37.081088 [Byte1]: 38
8595 16:44:37.085857
8596 16:44:37.086454 Set Vref, RX VrefLevel [Byte0]: 39
8597 16:44:37.088858 [Byte1]: 39
8598 16:44:37.093138
8599 16:44:37.093702 Set Vref, RX VrefLevel [Byte0]: 40
8600 16:44:37.097551 [Byte1]: 40
8601 16:44:37.100721
8602 16:44:37.101290 Set Vref, RX VrefLevel [Byte0]: 41
8603 16:44:37.104259 [Byte1]: 41
8604 16:44:37.109047
8605 16:44:37.109615 Set Vref, RX VrefLevel [Byte0]: 42
8606 16:44:37.111430 [Byte1]: 42
8607 16:44:37.115494
8608 16:44:37.116028 Set Vref, RX VrefLevel [Byte0]: 43
8609 16:44:37.119114 [Byte1]: 43
8610 16:44:37.123417
8611 16:44:37.123982 Set Vref, RX VrefLevel [Byte0]: 44
8612 16:44:37.126985 [Byte1]: 44
8613 16:44:37.130921
8614 16:44:37.131523 Set Vref, RX VrefLevel [Byte0]: 45
8615 16:44:37.134384 [Byte1]: 45
8616 16:44:37.138702
8617 16:44:37.139272 Set Vref, RX VrefLevel [Byte0]: 46
8618 16:44:37.141891 [Byte1]: 46
8619 16:44:37.146056
8620 16:44:37.146715 Set Vref, RX VrefLevel [Byte0]: 47
8621 16:44:37.149630 [Byte1]: 47
8622 16:44:37.154048
8623 16:44:37.154669 Set Vref, RX VrefLevel [Byte0]: 48
8624 16:44:37.157059 [Byte1]: 48
8625 16:44:37.161531
8626 16:44:37.162100 Set Vref, RX VrefLevel [Byte0]: 49
8627 16:44:37.164721 [Byte1]: 49
8628 16:44:37.168842
8629 16:44:37.169430 Set Vref, RX VrefLevel [Byte0]: 50
8630 16:44:37.172080 [Byte1]: 50
8631 16:44:37.176635
8632 16:44:37.177196 Set Vref, RX VrefLevel [Byte0]: 51
8633 16:44:37.180563 [Byte1]: 51
8634 16:44:37.184219
8635 16:44:37.184785 Set Vref, RX VrefLevel [Byte0]: 52
8636 16:44:37.187035 [Byte1]: 52
8637 16:44:37.191391
8638 16:44:37.191954 Set Vref, RX VrefLevel [Byte0]: 53
8639 16:44:37.194921 [Byte1]: 53
8640 16:44:37.199289
8641 16:44:37.199760 Set Vref, RX VrefLevel [Byte0]: 54
8642 16:44:37.202752 [Byte1]: 54
8643 16:44:37.206760
8644 16:44:37.207322 Set Vref, RX VrefLevel [Byte0]: 55
8645 16:44:37.210072 [Byte1]: 55
8646 16:44:37.214397
8647 16:44:37.214871 Set Vref, RX VrefLevel [Byte0]: 56
8648 16:44:37.217452 [Byte1]: 56
8649 16:44:37.221707
8650 16:44:37.222177 Set Vref, RX VrefLevel [Byte0]: 57
8651 16:44:37.225166 [Byte1]: 57
8652 16:44:37.229179
8653 16:44:37.229648 Set Vref, RX VrefLevel [Byte0]: 58
8654 16:44:37.232725 [Byte1]: 58
8655 16:44:37.237073
8656 16:44:37.237646 Set Vref, RX VrefLevel [Byte0]: 59
8657 16:44:37.240319 [Byte1]: 59
8658 16:44:37.244650
8659 16:44:37.245216 Set Vref, RX VrefLevel [Byte0]: 60
8660 16:44:37.247907 [Byte1]: 60
8661 16:44:37.252568
8662 16:44:37.253135 Set Vref, RX VrefLevel [Byte0]: 61
8663 16:44:37.255266 [Byte1]: 61
8664 16:44:37.259598
8665 16:44:37.260154 Set Vref, RX VrefLevel [Byte0]: 62
8666 16:44:37.263174 [Byte1]: 62
8667 16:44:37.268271
8668 16:44:37.268830 Set Vref, RX VrefLevel [Byte0]: 63
8669 16:44:37.270958 [Byte1]: 63
8670 16:44:37.275112
8671 16:44:37.275674 Set Vref, RX VrefLevel [Byte0]: 64
8672 16:44:37.278212 [Byte1]: 64
8673 16:44:37.282777
8674 16:44:37.283339 Set Vref, RX VrefLevel [Byte0]: 65
8675 16:44:37.285806 [Byte1]: 65
8676 16:44:37.290332
8677 16:44:37.290934 Set Vref, RX VrefLevel [Byte0]: 66
8678 16:44:37.293453 [Byte1]: 66
8679 16:44:37.297821
8680 16:44:37.298415 Set Vref, RX VrefLevel [Byte0]: 67
8681 16:44:37.301527 [Byte1]: 67
8682 16:44:37.305256
8683 16:44:37.308896 Set Vref, RX VrefLevel [Byte0]: 68
8684 16:44:37.309461 [Byte1]: 68
8685 16:44:37.312518
8686 16:44:37.313005 Set Vref, RX VrefLevel [Byte0]: 69
8687 16:44:37.315667 [Byte1]: 69
8688 16:44:37.320585
8689 16:44:37.321183 Set Vref, RX VrefLevel [Byte0]: 70
8690 16:44:37.323524 [Byte1]: 70
8691 16:44:37.327468
8692 16:44:37.327940 Set Vref, RX VrefLevel [Byte0]: 71
8693 16:44:37.331176 [Byte1]: 71
8694 16:44:37.335801
8695 16:44:37.336370 Set Vref, RX VrefLevel [Byte0]: 72
8696 16:44:37.338488 [Byte1]: 72
8697 16:44:37.342905
8698 16:44:37.343463 Set Vref, RX VrefLevel [Byte0]: 73
8699 16:44:37.346932 [Byte1]: 73
8700 16:44:37.350864
8701 16:44:37.351439 Set Vref, RX VrefLevel [Byte0]: 74
8702 16:44:37.353960 [Byte1]: 74
8703 16:44:37.358582
8704 16:44:37.359179 Final RX Vref Byte 0 = 60 to rank0
8705 16:44:37.361915 Final RX Vref Byte 1 = 61 to rank0
8706 16:44:37.365293 Final RX Vref Byte 0 = 60 to rank1
8707 16:44:37.367688 Final RX Vref Byte 1 = 61 to rank1==
8708 16:44:37.371139 Dram Type= 6, Freq= 0, CH_1, rank 0
8709 16:44:37.378085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 16:44:37.378694 ==
8711 16:44:37.379074 DQS Delay:
8712 16:44:37.381822 DQS0 = 0, DQS1 = 0
8713 16:44:37.382458 DQM Delay:
8714 16:44:37.382852 DQM0 = 135, DQM1 = 128
8715 16:44:37.384185 DQ Delay:
8716 16:44:37.387960 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =134
8717 16:44:37.391033 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =132
8718 16:44:37.394786 DQ8 =114, DQ9 =116, DQ10 =132, DQ11 =122
8719 16:44:37.398327 DQ12 =138, DQ13 =134, DQ14 =136, DQ15 =136
8720 16:44:37.398943
8721 16:44:37.399316
8722 16:44:37.399666
8723 16:44:37.400690 [DramC_TX_OE_Calibration] TA2
8724 16:44:37.404561 Original DQ_B0 (3 6) =30, OEN = 27
8725 16:44:37.407785 Original DQ_B1 (3 6) =30, OEN = 27
8726 16:44:37.411329 24, 0x0, End_B0=24 End_B1=24
8727 16:44:37.411902 25, 0x0, End_B0=25 End_B1=25
8728 16:44:37.414579 26, 0x0, End_B0=26 End_B1=26
8729 16:44:37.418314 27, 0x0, End_B0=27 End_B1=27
8730 16:44:37.420617 28, 0x0, End_B0=28 End_B1=28
8731 16:44:37.424184 29, 0x0, End_B0=29 End_B1=29
8732 16:44:37.424760 30, 0x0, End_B0=30 End_B1=30
8733 16:44:37.428193 31, 0x4141, End_B0=30 End_B1=30
8734 16:44:37.430970 Byte0 end_step=30 best_step=27
8735 16:44:37.434056 Byte1 end_step=30 best_step=27
8736 16:44:37.437213 Byte0 TX OE(2T, 0.5T) = (3, 3)
8737 16:44:37.440928 Byte1 TX OE(2T, 0.5T) = (3, 3)
8738 16:44:37.441494
8739 16:44:37.441866
8740 16:44:37.447142 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8741 16:44:37.450459 CH1 RK0: MR19=303, MR18=1927
8742 16:44:37.457213 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8743 16:44:37.457769
8744 16:44:37.460407 ----->DramcWriteLeveling(PI) begin...
8745 16:44:37.460885 ==
8746 16:44:37.463941 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 16:44:37.467089 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 16:44:37.467566 ==
8749 16:44:37.470717 Write leveling (Byte 0): 24 => 24
8750 16:44:37.473855 Write leveling (Byte 1): 28 => 28
8751 16:44:37.477197 DramcWriteLeveling(PI) end<-----
8752 16:44:37.477760
8753 16:44:37.478134 ==
8754 16:44:37.480554 Dram Type= 6, Freq= 0, CH_1, rank 1
8755 16:44:37.484263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8756 16:44:37.484830 ==
8757 16:44:37.487034 [Gating] SW mode calibration
8758 16:44:37.493770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8759 16:44:37.500706 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8760 16:44:37.503595 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 16:44:37.510400 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 16:44:37.513522 1 4 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
8763 16:44:37.517188 1 4 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
8764 16:44:37.523121 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 16:44:37.526479 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 16:44:37.530172 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8767 16:44:37.536441 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8768 16:44:37.539669 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8769 16:44:37.542904 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8770 16:44:37.549534 1 5 8 | B1->B0 | 2d2d 3434 | 0 1 | (1 0) (1 0)
8771 16:44:37.552886 1 5 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 0)
8772 16:44:37.556043 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8773 16:44:37.563038 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 16:44:37.565878 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8775 16:44:37.569779 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8776 16:44:37.575927 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 16:44:37.579287 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 16:44:37.582646 1 6 8 | B1->B0 | 3938 2424 | 1 0 | (0 0) (0 0)
8779 16:44:37.589104 1 6 12 | B1->B0 | 4646 2f2f | 0 0 | (0 0) (0 0)
8780 16:44:37.592678 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 16:44:37.595787 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 16:44:37.602604 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 16:44:37.605628 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8784 16:44:37.609112 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8785 16:44:37.616049 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8786 16:44:37.618797 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8787 16:44:37.622392 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8788 16:44:37.628912 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 16:44:37.631634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 16:44:37.635211 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 16:44:37.642347 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 16:44:37.645700 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 16:44:37.648829 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 16:44:37.655290 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 16:44:37.658324 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 16:44:37.661661 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 16:44:37.668649 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 16:44:37.672460 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 16:44:37.674905 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 16:44:37.681761 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 16:44:37.686105 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 16:44:37.688388 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8803 16:44:37.695077 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8804 16:44:37.695643 Total UI for P1: 0, mck2ui 16
8805 16:44:37.701596 best dqsien dly found for B0: ( 1, 9, 8)
8806 16:44:37.705336 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 16:44:37.708237 Total UI for P1: 0, mck2ui 16
8808 16:44:37.711111 best dqsien dly found for B1: ( 1, 9, 10)
8809 16:44:37.714550 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8810 16:44:37.717918 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8811 16:44:37.718524
8812 16:44:37.721505 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8813 16:44:37.724465 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8814 16:44:37.727980 [Gating] SW calibration Done
8815 16:44:37.728545 ==
8816 16:44:37.730893 Dram Type= 6, Freq= 0, CH_1, rank 1
8817 16:44:37.737540 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8818 16:44:37.738111 ==
8819 16:44:37.738532 RX Vref Scan: 0
8820 16:44:37.738890
8821 16:44:37.740551 RX Vref 0 -> 0, step: 1
8822 16:44:37.741016
8823 16:44:37.744288 RX Delay 0 -> 252, step: 8
8824 16:44:37.747760 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8825 16:44:37.750966 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8826 16:44:37.754232 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8827 16:44:37.757181 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8828 16:44:37.763934 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8829 16:44:37.767435 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8830 16:44:37.770550 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8831 16:44:37.774514 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8832 16:44:37.777382 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8833 16:44:37.783795 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8834 16:44:37.787293 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8835 16:44:37.791032 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8836 16:44:37.794168 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8837 16:44:37.797397 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8838 16:44:37.804054 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8839 16:44:37.806802 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8840 16:44:37.807278 ==
8841 16:44:37.810627 Dram Type= 6, Freq= 0, CH_1, rank 1
8842 16:44:37.813277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8843 16:44:37.813743 ==
8844 16:44:37.816911 DQS Delay:
8845 16:44:37.817514 DQS0 = 0, DQS1 = 0
8846 16:44:37.818022 DQM Delay:
8847 16:44:37.820197 DQM0 = 138, DQM1 = 130
8848 16:44:37.820756 DQ Delay:
8849 16:44:37.824070 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =139
8850 16:44:37.826708 DQ4 =139, DQ5 =151, DQ6 =147, DQ7 =135
8851 16:44:37.833625 DQ8 =111, DQ9 =119, DQ10 =131, DQ11 =127
8852 16:44:37.836496 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8853 16:44:37.837055
8854 16:44:37.837422
8855 16:44:37.837761 ==
8856 16:44:37.839729 Dram Type= 6, Freq= 0, CH_1, rank 1
8857 16:44:37.843197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8858 16:44:37.843758 ==
8859 16:44:37.844127
8860 16:44:37.844464
8861 16:44:37.846326 TX Vref Scan disable
8862 16:44:37.849769 == TX Byte 0 ==
8863 16:44:37.853195 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8864 16:44:37.856579 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8865 16:44:37.860226 == TX Byte 1 ==
8866 16:44:37.863295 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8867 16:44:37.866650 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8868 16:44:37.867113 ==
8869 16:44:37.870112 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 16:44:37.873212 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 16:44:37.875969 ==
8872 16:44:37.888736
8873 16:44:37.891783 TX Vref early break, caculate TX vref
8874 16:44:37.896071 TX Vref=16, minBit 15, minWin=21, winSum=386
8875 16:44:37.898442 TX Vref=18, minBit 9, minWin=23, winSum=395
8876 16:44:37.902476 TX Vref=20, minBit 9, minWin=24, winSum=409
8877 16:44:37.905694 TX Vref=22, minBit 13, minWin=24, winSum=412
8878 16:44:37.909081 TX Vref=24, minBit 9, minWin=25, winSum=419
8879 16:44:37.915059 TX Vref=26, minBit 9, minWin=25, winSum=427
8880 16:44:37.918719 TX Vref=28, minBit 10, minWin=25, winSum=428
8881 16:44:37.921757 TX Vref=30, minBit 9, minWin=25, winSum=424
8882 16:44:37.925079 TX Vref=32, minBit 2, minWin=25, winSum=416
8883 16:44:37.928745 TX Vref=34, minBit 10, minWin=24, winSum=406
8884 16:44:37.934849 TX Vref=36, minBit 0, minWin=24, winSum=398
8885 16:44:37.938427 [TxChooseVref] Worse bit 10, Min win 25, Win sum 428, Final Vref 28
8886 16:44:37.938996
8887 16:44:37.941370 Final TX Range 0 Vref 28
8888 16:44:37.941935
8889 16:44:37.942304 ==
8890 16:44:37.944787 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 16:44:37.948460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 16:44:37.951753 ==
8893 16:44:37.952323
8894 16:44:37.952688
8895 16:44:37.953025 TX Vref Scan disable
8896 16:44:37.958554 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8897 16:44:37.959123 == TX Byte 0 ==
8898 16:44:37.961474 u2DelayCellOfst[0]=16 cells (5 PI)
8899 16:44:37.965039 u2DelayCellOfst[1]=13 cells (4 PI)
8900 16:44:37.968134 u2DelayCellOfst[2]=0 cells (0 PI)
8901 16:44:37.972087 u2DelayCellOfst[3]=6 cells (2 PI)
8902 16:44:37.974766 u2DelayCellOfst[4]=10 cells (3 PI)
8903 16:44:37.977956 u2DelayCellOfst[5]=20 cells (6 PI)
8904 16:44:37.981418 u2DelayCellOfst[6]=20 cells (6 PI)
8905 16:44:37.984919 u2DelayCellOfst[7]=6 cells (2 PI)
8906 16:44:37.988422 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8907 16:44:37.991215 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8908 16:44:37.994901 == TX Byte 1 ==
8909 16:44:37.998184 u2DelayCellOfst[8]=0 cells (0 PI)
8910 16:44:38.001245 u2DelayCellOfst[9]=3 cells (1 PI)
8911 16:44:38.004805 u2DelayCellOfst[10]=6 cells (2 PI)
8912 16:44:38.005398 u2DelayCellOfst[11]=3 cells (1 PI)
8913 16:44:38.007926 u2DelayCellOfst[12]=13 cells (4 PI)
8914 16:44:38.011428 u2DelayCellOfst[13]=13 cells (4 PI)
8915 16:44:38.014429 u2DelayCellOfst[14]=13 cells (4 PI)
8916 16:44:38.017929 u2DelayCellOfst[15]=13 cells (4 PI)
8917 16:44:38.024130 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8918 16:44:38.028090 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8919 16:44:38.028652 DramC Write-DBI on
8920 16:44:38.031368 ==
8921 16:44:38.031926 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 16:44:38.037787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 16:44:38.038348 ==
8924 16:44:38.038771
8925 16:44:38.039115
8926 16:44:38.041378 TX Vref Scan disable
8927 16:44:38.041933 == TX Byte 0 ==
8928 16:44:38.047967 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8929 16:44:38.048525 == TX Byte 1 ==
8930 16:44:38.050966 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8931 16:44:38.054739 DramC Write-DBI off
8932 16:44:38.055295
8933 16:44:38.055663 [DATLAT]
8934 16:44:38.057520 Freq=1600, CH1 RK1
8935 16:44:38.058079
8936 16:44:38.058506 DATLAT Default: 0xf
8937 16:44:38.061287 0, 0xFFFF, sum = 0
8938 16:44:38.061856 1, 0xFFFF, sum = 0
8939 16:44:38.063889 2, 0xFFFF, sum = 0
8940 16:44:38.064427 3, 0xFFFF, sum = 0
8941 16:44:38.067448 4, 0xFFFF, sum = 0
8942 16:44:38.068015 5, 0xFFFF, sum = 0
8943 16:44:38.070468 6, 0xFFFF, sum = 0
8944 16:44:38.074457 7, 0xFFFF, sum = 0
8945 16:44:38.075050 8, 0xFFFF, sum = 0
8946 16:44:38.077621 9, 0xFFFF, sum = 0
8947 16:44:38.078213 10, 0xFFFF, sum = 0
8948 16:44:38.080830 11, 0xFFFF, sum = 0
8949 16:44:38.081450 12, 0xFFFF, sum = 0
8950 16:44:38.083650 13, 0xFFFF, sum = 0
8951 16:44:38.084139 14, 0x0, sum = 1
8952 16:44:38.087162 15, 0x0, sum = 2
8953 16:44:38.087753 16, 0x0, sum = 3
8954 16:44:38.090472 17, 0x0, sum = 4
8955 16:44:38.090981 best_step = 15
8956 16:44:38.091455
8957 16:44:38.091903 ==
8958 16:44:38.093593 Dram Type= 6, Freq= 0, CH_1, rank 1
8959 16:44:38.096982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8960 16:44:38.097582 ==
8961 16:44:38.100578 RX Vref Scan: 0
8962 16:44:38.101183
8963 16:44:38.103555 RX Vref 0 -> 0, step: 1
8964 16:44:38.104031
8965 16:44:38.104404 RX Delay 11 -> 252, step: 4
8966 16:44:38.111117 iDelay=195, Bit 0, Center 138 (95 ~ 182) 88
8967 16:44:38.114522 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8968 16:44:38.117746 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8969 16:44:38.120939 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8970 16:44:38.123993 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8971 16:44:38.130815 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8972 16:44:38.134176 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8973 16:44:38.137410 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8974 16:44:38.140752 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8975 16:44:38.143947 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8976 16:44:38.150807 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8977 16:44:38.154219 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8978 16:44:38.157009 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8979 16:44:38.160728 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8980 16:44:38.167028 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8981 16:44:38.170203 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8982 16:44:38.170821 ==
8983 16:44:38.174116 Dram Type= 6, Freq= 0, CH_1, rank 1
8984 16:44:38.177112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8985 16:44:38.177592 ==
8986 16:44:38.177967 DQS Delay:
8987 16:44:38.180291 DQS0 = 0, DQS1 = 0
8988 16:44:38.180868 DQM Delay:
8989 16:44:38.183784 DQM0 = 134, DQM1 = 129
8990 16:44:38.184362 DQ Delay:
8991 16:44:38.186802 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
8992 16:44:38.190530 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8993 16:44:38.193812 DQ8 =112, DQ9 =118, DQ10 =130, DQ11 =124
8994 16:44:38.199824 DQ12 =136, DQ13 =138, DQ14 =136, DQ15 =140
8995 16:44:38.200389
8996 16:44:38.200759
8997 16:44:38.201103
8998 16:44:38.203274 [DramC_TX_OE_Calibration] TA2
8999 16:44:38.203744 Original DQ_B0 (3 6) =30, OEN = 27
9000 16:44:38.207015 Original DQ_B1 (3 6) =30, OEN = 27
9001 16:44:38.210526 24, 0x0, End_B0=24 End_B1=24
9002 16:44:38.213437 25, 0x0, End_B0=25 End_B1=25
9003 16:44:38.216529 26, 0x0, End_B0=26 End_B1=26
9004 16:44:38.219855 27, 0x0, End_B0=27 End_B1=27
9005 16:44:38.220341 28, 0x0, End_B0=28 End_B1=28
9006 16:44:38.223009 29, 0x0, End_B0=29 End_B1=29
9007 16:44:38.226545 30, 0x0, End_B0=30 End_B1=30
9008 16:44:38.229439 31, 0x4141, End_B0=30 End_B1=30
9009 16:44:38.232791 Byte0 end_step=30 best_step=27
9010 16:44:38.233260 Byte1 end_step=30 best_step=27
9011 16:44:38.236389 Byte0 TX OE(2T, 0.5T) = (3, 3)
9012 16:44:38.239623 Byte1 TX OE(2T, 0.5T) = (3, 3)
9013 16:44:38.240205
9014 16:44:38.240576
9015 16:44:38.249920 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9016 16:44:38.250521 CH1 RK1: MR19=303, MR18=1C07
9017 16:44:38.256312 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9018 16:44:38.259979 [RxdqsGatingPostProcess] freq 1600
9019 16:44:38.266040 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9020 16:44:38.269652 best DQS0 dly(2T, 0.5T) = (1, 1)
9021 16:44:38.272839 best DQS1 dly(2T, 0.5T) = (1, 1)
9022 16:44:38.276026 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9023 16:44:38.279958 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9024 16:44:38.282665 best DQS0 dly(2T, 0.5T) = (1, 1)
9025 16:44:38.283135 best DQS1 dly(2T, 0.5T) = (1, 1)
9026 16:44:38.286168 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9027 16:44:38.289568 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9028 16:44:38.292962 Pre-setting of DQS Precalculation
9029 16:44:38.299291 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9030 16:44:38.306008 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9031 16:44:38.312469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9032 16:44:38.313049
9033 16:44:38.313423
9034 16:44:38.315268 [Calibration Summary] 3200 Mbps
9035 16:44:38.318830 CH 0, Rank 0
9036 16:44:38.319408 SW Impedance : PASS
9037 16:44:38.321975 DUTY Scan : NO K
9038 16:44:38.322471 ZQ Calibration : PASS
9039 16:44:38.325329 Jitter Meter : NO K
9040 16:44:38.329060 CBT Training : PASS
9041 16:44:38.329626 Write leveling : PASS
9042 16:44:38.332074 RX DQS gating : PASS
9043 16:44:38.335292 RX DQ/DQS(RDDQC) : PASS
9044 16:44:38.335860 TX DQ/DQS : PASS
9045 16:44:38.339269 RX DATLAT : PASS
9046 16:44:38.341812 RX DQ/DQS(Engine): PASS
9047 16:44:38.342409 TX OE : PASS
9048 16:44:38.345166 All Pass.
9049 16:44:38.345729
9050 16:44:38.346098 CH 0, Rank 1
9051 16:44:38.348503 SW Impedance : PASS
9052 16:44:38.349071 DUTY Scan : NO K
9053 16:44:38.352139 ZQ Calibration : PASS
9054 16:44:38.355222 Jitter Meter : NO K
9055 16:44:38.355797 CBT Training : PASS
9056 16:44:38.358511 Write leveling : PASS
9057 16:44:38.362128 RX DQS gating : PASS
9058 16:44:38.362741 RX DQ/DQS(RDDQC) : PASS
9059 16:44:38.364983 TX DQ/DQS : PASS
9060 16:44:38.368680 RX DATLAT : PASS
9061 16:44:38.369245 RX DQ/DQS(Engine): PASS
9062 16:44:38.372074 TX OE : PASS
9063 16:44:38.372548 All Pass.
9064 16:44:38.372914
9065 16:44:38.375019 CH 1, Rank 0
9066 16:44:38.375479 SW Impedance : PASS
9067 16:44:38.378575 DUTY Scan : NO K
9068 16:44:38.382032 ZQ Calibration : PASS
9069 16:44:38.382623 Jitter Meter : NO K
9070 16:44:38.385516 CBT Training : PASS
9071 16:44:38.386096 Write leveling : PASS
9072 16:44:38.388356 RX DQS gating : PASS
9073 16:44:38.391850 RX DQ/DQS(RDDQC) : PASS
9074 16:44:38.392419 TX DQ/DQS : PASS
9075 16:44:38.394845 RX DATLAT : PASS
9076 16:44:38.398324 RX DQ/DQS(Engine): PASS
9077 16:44:38.398933 TX OE : PASS
9078 16:44:38.401474 All Pass.
9079 16:44:38.402034
9080 16:44:38.402441 CH 1, Rank 1
9081 16:44:38.404805 SW Impedance : PASS
9082 16:44:38.405269 DUTY Scan : NO K
9083 16:44:38.407990 ZQ Calibration : PASS
9084 16:44:38.411284 Jitter Meter : NO K
9085 16:44:38.412000 CBT Training : PASS
9086 16:44:38.415463 Write leveling : PASS
9087 16:44:38.418414 RX DQS gating : PASS
9088 16:44:38.419074 RX DQ/DQS(RDDQC) : PASS
9089 16:44:38.421259 TX DQ/DQS : PASS
9090 16:44:38.424724 RX DATLAT : PASS
9091 16:44:38.425185 RX DQ/DQS(Engine): PASS
9092 16:44:38.428175 TX OE : PASS
9093 16:44:38.428750 All Pass.
9094 16:44:38.429119
9095 16:44:38.430985 DramC Write-DBI on
9096 16:44:38.434868 PER_BANK_REFRESH: Hybrid Mode
9097 16:44:38.435346 TX_TRACKING: ON
9098 16:44:38.444511 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9099 16:44:38.451218 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9100 16:44:38.458050 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9101 16:44:38.461298 [FAST_K] Save calibration result to emmc
9102 16:44:38.464126 sync common calibartion params.
9103 16:44:38.467663 sync cbt_mode0:1, 1:1
9104 16:44:38.470680 dram_init: ddr_geometry: 2
9105 16:44:38.471146 dram_init: ddr_geometry: 2
9106 16:44:38.474186 dram_init: ddr_geometry: 2
9107 16:44:38.477553 0:dram_rank_size:100000000
9108 16:44:38.480958 1:dram_rank_size:100000000
9109 16:44:38.484082 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9110 16:44:38.487327 DFS_SHUFFLE_HW_MODE: ON
9111 16:44:38.490929 dramc_set_vcore_voltage set vcore to 725000
9112 16:44:38.494970 Read voltage for 1600, 0
9113 16:44:38.495542 Vio18 = 0
9114 16:44:38.495916 Vcore = 725000
9115 16:44:38.498132 Vdram = 0
9116 16:44:38.498634 Vddq = 0
9117 16:44:38.499008 Vmddr = 0
9118 16:44:38.500476 switch to 3200 Mbps bootup
9119 16:44:38.504637 [DramcRunTimeConfig]
9120 16:44:38.505211 PHYPLL
9121 16:44:38.505587 DPM_CONTROL_AFTERK: ON
9122 16:44:38.507478 PER_BANK_REFRESH: ON
9123 16:44:38.510797 REFRESH_OVERHEAD_REDUCTION: ON
9124 16:44:38.511367 CMD_PICG_NEW_MODE: OFF
9125 16:44:38.514107 XRTWTW_NEW_MODE: ON
9126 16:44:38.517442 XRTRTR_NEW_MODE: ON
9127 16:44:38.518006 TX_TRACKING: ON
9128 16:44:38.520640 RDSEL_TRACKING: OFF
9129 16:44:38.521109 DQS Precalculation for DVFS: ON
9130 16:44:38.523630 RX_TRACKING: OFF
9131 16:44:38.524098 HW_GATING DBG: ON
9132 16:44:38.527360 ZQCS_ENABLE_LP4: ON
9133 16:44:38.527825 RX_PICG_NEW_MODE: ON
9134 16:44:38.530906 TX_PICG_NEW_MODE: ON
9135 16:44:38.533804 ENABLE_RX_DCM_DPHY: ON
9136 16:44:38.537810 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9137 16:44:38.538488 DUMMY_READ_FOR_TRACKING: OFF
9138 16:44:38.540641 !!! SPM_CONTROL_AFTERK: OFF
9139 16:44:38.543939 !!! SPM could not control APHY
9140 16:44:38.547412 IMPEDANCE_TRACKING: ON
9141 16:44:38.547982 TEMP_SENSOR: ON
9142 16:44:38.550527 HW_SAVE_FOR_SR: OFF
9143 16:44:38.551102 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9144 16:44:38.556821 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9145 16:44:38.557383 Read ODT Tracking: ON
9146 16:44:38.560219 Refresh Rate DeBounce: ON
9147 16:44:38.563449 DFS_NO_QUEUE_FLUSH: ON
9148 16:44:38.567112 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9149 16:44:38.567579 ENABLE_DFS_RUNTIME_MRW: OFF
9150 16:44:38.570080 DDR_RESERVE_NEW_MODE: ON
9151 16:44:38.573123 MR_CBT_SWITCH_FREQ: ON
9152 16:44:38.573595 =========================
9153 16:44:38.593600 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9154 16:44:38.596915 dram_init: ddr_geometry: 2
9155 16:44:38.614933 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9156 16:44:38.617985 dram_init: dram init end (result: 0)
9157 16:44:38.624464 DRAM-K: Full calibration passed in 24480 msecs
9158 16:44:38.627627 MRC: failed to locate region type 0.
9159 16:44:38.628196 DRAM rank0 size:0x100000000,
9160 16:44:38.631005 DRAM rank1 size=0x100000000
9161 16:44:38.640964 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9162 16:44:38.647698 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9163 16:44:38.654027 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9164 16:44:38.664142 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9165 16:44:38.664624 DRAM rank0 size:0x100000000,
9166 16:44:38.667118 DRAM rank1 size=0x100000000
9167 16:44:38.667589 CBMEM:
9168 16:44:38.670446 IMD: root @ 0xfffff000 254 entries.
9169 16:44:38.673979 IMD: root @ 0xffffec00 62 entries.
9170 16:44:38.676904 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9171 16:44:38.684384 WARNING: RO_VPD is uninitialized or empty.
9172 16:44:38.687669 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9173 16:44:38.695367 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9174 16:44:38.707835 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9175 16:44:38.719154 BS: romstage times (exec / console): total (unknown) / 23984 ms
9176 16:44:38.719807
9177 16:44:38.720190
9178 16:44:38.729039 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9179 16:44:38.732428 ARM64: Exception handlers installed.
9180 16:44:38.735353 ARM64: Testing exception
9181 16:44:38.738787 ARM64: Done test exception
9182 16:44:38.739350 Enumerating buses...
9183 16:44:38.742110 Show all devs... Before device enumeration.
9184 16:44:38.745428 Root Device: enabled 1
9185 16:44:38.748430 CPU_CLUSTER: 0: enabled 1
9186 16:44:38.748905 CPU: 00: enabled 1
9187 16:44:38.752708 Compare with tree...
9188 16:44:38.753268 Root Device: enabled 1
9189 16:44:38.755450 CPU_CLUSTER: 0: enabled 1
9190 16:44:38.758298 CPU: 00: enabled 1
9191 16:44:38.758906 Root Device scanning...
9192 16:44:38.761993 scan_static_bus for Root Device
9193 16:44:38.764898 CPU_CLUSTER: 0 enabled
9194 16:44:38.768289 scan_static_bus for Root Device done
9195 16:44:38.772435 scan_bus: bus Root Device finished in 8 msecs
9196 16:44:38.773051 done
9197 16:44:38.779270 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9198 16:44:38.781708 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9199 16:44:38.788792 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9200 16:44:38.791654 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9201 16:44:38.795268 Allocating resources...
9202 16:44:38.797936 Reading resources...
9203 16:44:38.801567 Root Device read_resources bus 0 link: 0
9204 16:44:38.804790 DRAM rank0 size:0x100000000,
9205 16:44:38.805357 DRAM rank1 size=0x100000000
9206 16:44:38.811665 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9207 16:44:38.812229 CPU: 00 missing read_resources
9208 16:44:38.818270 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9209 16:44:38.821204 Root Device read_resources bus 0 link: 0 done
9210 16:44:38.824069 Done reading resources.
9211 16:44:38.828206 Show resources in subtree (Root Device)...After reading.
9212 16:44:38.831236 Root Device child on link 0 CPU_CLUSTER: 0
9213 16:44:38.834290 CPU_CLUSTER: 0 child on link 0 CPU: 00
9214 16:44:38.844364 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9215 16:44:38.844937 CPU: 00
9216 16:44:38.847246 Root Device assign_resources, bus 0 link: 0
9217 16:44:38.850913 CPU_CLUSTER: 0 missing set_resources
9218 16:44:38.857857 Root Device assign_resources, bus 0 link: 0 done
9219 16:44:38.858472 Done setting resources.
9220 16:44:38.864121 Show resources in subtree (Root Device)...After assigning values.
9221 16:44:38.867303 Root Device child on link 0 CPU_CLUSTER: 0
9222 16:44:38.870694 CPU_CLUSTER: 0 child on link 0 CPU: 00
9223 16:44:38.880538 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9224 16:44:38.881017 CPU: 00
9225 16:44:38.883790 Done allocating resources.
9226 16:44:38.890460 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9227 16:44:38.890936 Enabling resources...
9228 16:44:38.893946 done.
9229 16:44:38.897195 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9230 16:44:38.900548 Initializing devices...
9231 16:44:38.901113 Root Device init
9232 16:44:38.903539 init hardware done!
9233 16:44:38.904103 0x00000018: ctrlr->caps
9234 16:44:38.907329 52.000 MHz: ctrlr->f_max
9235 16:44:38.911269 0.400 MHz: ctrlr->f_min
9236 16:44:38.911841 0x40ff8080: ctrlr->voltages
9237 16:44:38.913842 sclk: 390625
9238 16:44:38.914308 Bus Width = 1
9239 16:44:38.917069 sclk: 390625
9240 16:44:38.917537 Bus Width = 1
9241 16:44:38.920431 Early init status = 3
9242 16:44:38.924034 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9243 16:44:38.926860 in-header: 03 fc 00 00 01 00 00 00
9244 16:44:38.930405 in-data: 00
9245 16:44:38.933897 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9246 16:44:38.939189 in-header: 03 fd 00 00 00 00 00 00
9247 16:44:38.942686 in-data:
9248 16:44:38.945628 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9249 16:44:38.950124 in-header: 03 fc 00 00 01 00 00 00
9250 16:44:38.953674 in-data: 00
9251 16:44:38.956773 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9252 16:44:38.962142 in-header: 03 fd 00 00 00 00 00 00
9253 16:44:38.965863 in-data:
9254 16:44:38.969021 [SSUSB] Setting up USB HOST controller...
9255 16:44:38.972595 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9256 16:44:38.975473 [SSUSB] phy power-on done.
9257 16:44:38.978535 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9258 16:44:38.985667 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9259 16:44:38.988550 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9260 16:44:38.994852 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9261 16:44:39.001814 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9262 16:44:39.008667 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9263 16:44:39.015090 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9264 16:44:39.021746 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9265 16:44:39.024824 SPM: binary array size = 0x9dc
9266 16:44:39.028300 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9267 16:44:39.035179 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9268 16:44:39.041438 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9269 16:44:39.047790 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9270 16:44:39.051194 configure_display: Starting display init
9271 16:44:39.086222 anx7625_power_on_init: Init interface.
9272 16:44:39.088579 anx7625_disable_pd_protocol: Disabled PD feature.
9273 16:44:39.092086 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9274 16:44:39.120042 anx7625_start_dp_work: Secure OCM version=00
9275 16:44:39.123479 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9276 16:44:39.137916 sp_tx_get_edid_block: EDID Block = 1
9277 16:44:39.240769 Extracted contents:
9278 16:44:39.243700 header: 00 ff ff ff ff ff ff 00
9279 16:44:39.247543 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9280 16:44:39.250557 version: 01 04
9281 16:44:39.253778 basic params: 95 1f 11 78 0a
9282 16:44:39.257360 chroma info: 76 90 94 55 54 90 27 21 50 54
9283 16:44:39.260370 established: 00 00 00
9284 16:44:39.267190 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9285 16:44:39.271278 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9286 16:44:39.277269 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9287 16:44:39.283524 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9288 16:44:39.290033 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9289 16:44:39.293769 extensions: 00
9290 16:44:39.294341 checksum: fb
9291 16:44:39.294768
9292 16:44:39.296386 Manufacturer: IVO Model 57d Serial Number 0
9293 16:44:39.300079 Made week 0 of 2020
9294 16:44:39.302926 EDID version: 1.4
9295 16:44:39.303398 Digital display
9296 16:44:39.306396 6 bits per primary color channel
9297 16:44:39.306877 DisplayPort interface
9298 16:44:39.309913 Maximum image size: 31 cm x 17 cm
9299 16:44:39.313857 Gamma: 220%
9300 16:44:39.314474 Check DPMS levels
9301 16:44:39.319664 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9302 16:44:39.322786 First detailed timing is preferred timing
9303 16:44:39.323257 Established timings supported:
9304 16:44:39.326175 Standard timings supported:
9305 16:44:39.329598 Detailed timings
9306 16:44:39.332729 Hex of detail: 383680a07038204018303c0035ae10000019
9307 16:44:39.339767 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9308 16:44:39.342583 0780 0798 07c8 0820 hborder 0
9309 16:44:39.346411 0438 043b 0447 0458 vborder 0
9310 16:44:39.349593 -hsync -vsync
9311 16:44:39.350049 Did detailed timing
9312 16:44:39.356033 Hex of detail: 000000000000000000000000000000000000
9313 16:44:39.359331 Manufacturer-specified data, tag 0
9314 16:44:39.362722 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9315 16:44:39.366757 ASCII string: InfoVision
9316 16:44:39.369306 Hex of detail: 000000fe00523134304e574635205248200a
9317 16:44:39.372935 ASCII string: R140NWF5 RH
9318 16:44:39.373496 Checksum
9319 16:44:39.376102 Checksum: 0xfb (valid)
9320 16:44:39.378762 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9321 16:44:39.382382 DSI data_rate: 832800000 bps
9322 16:44:39.389473 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9323 16:44:39.392060 anx7625_parse_edid: pixelclock(138800).
9324 16:44:39.395665 hactive(1920), hsync(48), hfp(24), hbp(88)
9325 16:44:39.398754 vactive(1080), vsync(12), vfp(3), vbp(17)
9326 16:44:39.404091 anx7625_dsi_config: config dsi.
9327 16:44:39.408549 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9328 16:44:39.422295 anx7625_dsi_config: success to config DSI
9329 16:44:39.425974 anx7625_dp_start: MIPI phy setup OK.
9330 16:44:39.429696 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9331 16:44:39.432792 mtk_ddp_mode_set invalid vrefresh 60
9332 16:44:39.435885 main_disp_path_setup
9333 16:44:39.436443 ovl_layer_smi_id_en
9334 16:44:39.438822 ovl_layer_smi_id_en
9335 16:44:39.439379 ccorr_config
9336 16:44:39.439736 aal_config
9337 16:44:39.442481 gamma_config
9338 16:44:39.443045 postmask_config
9339 16:44:39.445531 dither_config
9340 16:44:39.449676 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9341 16:44:39.455982 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9342 16:44:39.459065 Root Device init finished in 554 msecs
9343 16:44:39.462184 CPU_CLUSTER: 0 init
9344 16:44:39.468597 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9345 16:44:39.475332 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9346 16:44:39.475897 APU_MBOX 0x190000b0 = 0x10001
9347 16:44:39.478858 APU_MBOX 0x190001b0 = 0x10001
9348 16:44:39.481949 APU_MBOX 0x190005b0 = 0x10001
9349 16:44:39.485367 APU_MBOX 0x190006b0 = 0x10001
9350 16:44:39.491639 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9351 16:44:39.501892 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9352 16:44:39.513968 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9353 16:44:39.520811 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9354 16:44:39.532260 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9355 16:44:39.541722 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9356 16:44:39.544773 CPU_CLUSTER: 0 init finished in 81 msecs
9357 16:44:39.548050 Devices initialized
9358 16:44:39.551424 Show all devs... After init.
9359 16:44:39.552000 Root Device: enabled 1
9360 16:44:39.554926 CPU_CLUSTER: 0: enabled 1
9361 16:44:39.558557 CPU: 00: enabled 1
9362 16:44:39.561275 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9363 16:44:39.564375 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9364 16:44:39.567621 ELOG: NV offset 0x57f000 size 0x1000
9365 16:44:39.574456 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9366 16:44:39.581690 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9367 16:44:39.584572 ELOG: Event(17) added with size 13 at 2023-06-03 16:44:39 UTC
9368 16:44:39.590970 out: cmd=0x121: 03 db 21 01 00 00 00 00
9369 16:44:39.594620 in-header: 03 40 00 00 2c 00 00 00
9370 16:44:39.604361 in-data: 1f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9371 16:44:39.610930 ELOG: Event(A1) added with size 10 at 2023-06-03 16:44:39 UTC
9372 16:44:39.617454 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9373 16:44:39.624149 ELOG: Event(A0) added with size 9 at 2023-06-03 16:44:39 UTC
9374 16:44:39.627446 elog_add_boot_reason: Logged dev mode boot
9375 16:44:39.633609 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9376 16:44:39.634083 Finalize devices...
9377 16:44:39.636983 Devices finalized
9378 16:44:39.640296 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9379 16:44:39.643878 Writing coreboot table at 0xffe64000
9380 16:44:39.646949 0. 000000000010a000-0000000000113fff: RAMSTAGE
9381 16:44:39.653606 1. 0000000040000000-00000000400fffff: RAM
9382 16:44:39.657726 2. 0000000040100000-000000004032afff: RAMSTAGE
9383 16:44:39.660735 3. 000000004032b000-00000000545fffff: RAM
9384 16:44:39.663771 4. 0000000054600000-000000005465ffff: BL31
9385 16:44:39.667215 5. 0000000054660000-00000000ffe63fff: RAM
9386 16:44:39.674081 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9387 16:44:39.676820 7. 0000000100000000-000000023fffffff: RAM
9388 16:44:39.680220 Passing 5 GPIOs to payload:
9389 16:44:39.683931 NAME | PORT | POLARITY | VALUE
9390 16:44:39.690517 EC in RW | 0x000000aa | low | undefined
9391 16:44:39.693246 EC interrupt | 0x00000005 | low | undefined
9392 16:44:39.696803 TPM interrupt | 0x000000ab | high | undefined
9393 16:44:39.703728 SD card detect | 0x00000011 | high | undefined
9394 16:44:39.706881 speaker enable | 0x00000093 | high | undefined
9395 16:44:39.710063 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9396 16:44:39.713036 in-header: 03 f9 00 00 02 00 00 00
9397 16:44:39.716590 in-data: 02 00
9398 16:44:39.720177 ADC[4]: Raw value=901401 ID=7
9399 16:44:39.720740 ADC[3]: Raw value=213179 ID=1
9400 16:44:39.723063 RAM Code: 0x71
9401 16:44:39.726446 ADC[6]: Raw value=74502 ID=0
9402 16:44:39.727029 ADC[5]: Raw value=212072 ID=1
9403 16:44:39.729495 SKU Code: 0x1
9404 16:44:39.736220 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9405 16:44:39.736791 coreboot table: 964 bytes.
9406 16:44:39.739524 IMD ROOT 0. 0xfffff000 0x00001000
9407 16:44:39.743247 IMD SMALL 1. 0xffffe000 0x00001000
9408 16:44:39.747002 RO MCACHE 2. 0xffffc000 0x00001104
9409 16:44:39.749561 CONSOLE 3. 0xfff7c000 0x00080000
9410 16:44:39.752724 FMAP 4. 0xfff7b000 0x00000452
9411 16:44:39.756080 TIME STAMP 5. 0xfff7a000 0x00000910
9412 16:44:39.759491 VBOOT WORK 6. 0xfff66000 0x00014000
9413 16:44:39.762944 RAMOOPS 7. 0xffe66000 0x00100000
9414 16:44:39.766252 COREBOOT 8. 0xffe64000 0x00002000
9415 16:44:39.769851 IMD small region:
9416 16:44:39.772510 IMD ROOT 0. 0xffffec00 0x00000400
9417 16:44:39.777052 VPD 1. 0xffffeba0 0x0000004c
9418 16:44:39.779599 MMC STATUS 2. 0xffffeb80 0x00000004
9419 16:44:39.782709 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9420 16:44:39.786104 Probing TPM: done!
9421 16:44:39.789812 Connected to device vid:did:rid of 1ae0:0028:00
9422 16:44:39.800144 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9423 16:44:39.803529 Initialized TPM device CR50 revision 0
9424 16:44:39.807195 Checking cr50 for pending updates
9425 16:44:39.810810 Reading cr50 TPM mode
9426 16:44:39.819650 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9427 16:44:39.826077 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9428 16:44:39.866227 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9429 16:44:39.869539 Checking segment from ROM address 0x40100000
9430 16:44:39.873041 Checking segment from ROM address 0x4010001c
9431 16:44:39.879974 Loading segment from ROM address 0x40100000
9432 16:44:39.880532 code (compression=0)
9433 16:44:39.889686 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9434 16:44:39.896115 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9435 16:44:39.896688 it's not compressed!
9436 16:44:39.902922 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9437 16:44:39.909482 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9438 16:44:39.926982 Loading segment from ROM address 0x4010001c
9439 16:44:39.927547 Entry Point 0x80000000
9440 16:44:39.930115 Loaded segments
9441 16:44:39.933352 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9442 16:44:39.939995 Jumping to boot code at 0x80000000(0xffe64000)
9443 16:44:39.946727 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9444 16:44:39.953610 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9445 16:44:39.960975 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9446 16:44:39.964064 Checking segment from ROM address 0x40100000
9447 16:44:39.967502 Checking segment from ROM address 0x4010001c
9448 16:44:39.974461 Loading segment from ROM address 0x40100000
9449 16:44:39.974990 code (compression=1)
9450 16:44:39.981097 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9451 16:44:39.991078 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9452 16:44:39.991639 using LZMA
9453 16:44:39.999610 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9454 16:44:40.006890 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9455 16:44:40.009491 Loading segment from ROM address 0x4010001c
9456 16:44:40.010055 Entry Point 0x54601000
9457 16:44:40.012496 Loaded segments
9458 16:44:40.016544 NOTICE: MT8192 bl31_setup
9459 16:44:40.022955 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9460 16:44:40.026640 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9461 16:44:40.029967 WARNING: region 0:
9462 16:44:40.033484 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 16:44:40.034106 WARNING: region 1:
9464 16:44:40.039579 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9465 16:44:40.043967 WARNING: region 2:
9466 16:44:40.046412 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9467 16:44:40.049644 WARNING: region 3:
9468 16:44:40.052618 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9469 16:44:40.056652 WARNING: region 4:
9470 16:44:40.062845 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9471 16:44:40.063411 WARNING: region 5:
9472 16:44:40.066316 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9473 16:44:40.069712 WARNING: region 6:
9474 16:44:40.072861 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9475 16:44:40.076008 WARNING: region 7:
9476 16:44:40.079674 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 16:44:40.086138 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9478 16:44:40.089172 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9479 16:44:40.095701 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9480 16:44:40.099305 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9481 16:44:40.102734 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9482 16:44:40.109184 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9483 16:44:40.112700 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9484 16:44:40.115466 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9485 16:44:40.122251 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9486 16:44:40.125536 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9487 16:44:40.132291 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9488 16:44:40.135729 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9489 16:44:40.138780 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9490 16:44:40.145598 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9491 16:44:40.149145 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9492 16:44:40.151877 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9493 16:44:40.159093 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9494 16:44:40.162089 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9495 16:44:40.168806 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9496 16:44:40.172237 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9497 16:44:40.174991 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9498 16:44:40.181476 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9499 16:44:40.185041 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9500 16:44:40.191487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9501 16:44:40.195004 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9502 16:44:40.198213 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9503 16:44:40.204993 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9504 16:44:40.208268 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9505 16:44:40.214973 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9506 16:44:40.218282 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9507 16:44:40.221976 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9508 16:44:40.227767 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9509 16:44:40.231716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9510 16:44:40.234637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9511 16:44:40.241319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9512 16:44:40.244801 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9513 16:44:40.247826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9514 16:44:40.251665 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9515 16:44:40.258109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9516 16:44:40.261152 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9517 16:44:40.264565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9518 16:44:40.268033 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9519 16:44:40.274858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9520 16:44:40.278301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9521 16:44:40.281842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9522 16:44:40.284073 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9523 16:44:40.291377 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9524 16:44:40.294521 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9525 16:44:40.298583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9526 16:44:40.304230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9527 16:44:40.307780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9528 16:44:40.314593 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9529 16:44:40.317418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9530 16:44:40.324320 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9531 16:44:40.327423 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9532 16:44:40.331171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9533 16:44:40.337609 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9534 16:44:40.340596 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9535 16:44:40.347443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9536 16:44:40.350694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9537 16:44:40.357262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9538 16:44:40.360804 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9539 16:44:40.367862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9540 16:44:40.370453 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9541 16:44:40.373987 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9542 16:44:40.380687 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9543 16:44:40.383777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9544 16:44:40.390471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9545 16:44:40.393816 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9546 16:44:40.400559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9547 16:44:40.403958 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9548 16:44:40.407007 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9549 16:44:40.414281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9550 16:44:40.417372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9551 16:44:40.423914 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9552 16:44:40.427029 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9553 16:44:40.433348 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9554 16:44:40.437019 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9555 16:44:40.443535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9556 16:44:40.447260 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9557 16:44:40.450208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9558 16:44:40.456984 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9559 16:44:40.460198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9560 16:44:40.466614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9561 16:44:40.470081 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9562 16:44:40.476383 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9563 16:44:40.480112 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9564 16:44:40.483666 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9565 16:44:40.489796 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9566 16:44:40.493117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9567 16:44:40.499703 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9568 16:44:40.503440 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9569 16:44:40.509916 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9570 16:44:40.513289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9571 16:44:40.519499 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9572 16:44:40.522900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9573 16:44:40.526147 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9574 16:44:40.533165 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9575 16:44:40.536645 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9576 16:44:40.539373 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9577 16:44:40.542758 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9578 16:44:40.550089 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9579 16:44:40.553015 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9580 16:44:40.559820 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9581 16:44:40.563037 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9582 16:44:40.565991 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9583 16:44:40.573529 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9584 16:44:40.575855 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9585 16:44:40.583102 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9586 16:44:40.585861 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9587 16:44:40.589551 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9588 16:44:40.596492 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9589 16:44:40.599350 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9590 16:44:40.605735 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9591 16:44:40.609394 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9592 16:44:40.612005 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9593 16:44:40.618613 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9594 16:44:40.622165 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9595 16:44:40.624877 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9596 16:44:40.632161 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9597 16:44:40.635066 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9598 16:44:40.638777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9599 16:44:40.641701 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9600 16:44:40.648527 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9601 16:44:40.651689 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9602 16:44:40.654798 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9603 16:44:40.662481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9604 16:44:40.665300 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9605 16:44:40.672414 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9606 16:44:40.675201 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9607 16:44:40.678047 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9608 16:44:40.685859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9609 16:44:40.688153 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9610 16:44:40.694917 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9611 16:44:40.697967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9612 16:44:40.701802 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9613 16:44:40.708592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9614 16:44:40.711116 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9615 16:44:40.715050 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9616 16:44:40.721659 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9617 16:44:40.725130 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9618 16:44:40.731746 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9619 16:44:40.735378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9620 16:44:40.741318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9621 16:44:40.745082 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9622 16:44:40.747827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9623 16:44:40.755045 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9624 16:44:40.758271 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9625 16:44:40.762048 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9626 16:44:40.768099 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9627 16:44:40.771611 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9628 16:44:40.777796 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9629 16:44:40.781394 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9630 16:44:40.785399 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9631 16:44:40.791894 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9632 16:44:40.794550 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9633 16:44:40.801593 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9634 16:44:40.804979 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9635 16:44:40.807559 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9636 16:44:40.814681 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9637 16:44:40.817940 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9638 16:44:40.824456 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9639 16:44:40.827447 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9640 16:44:40.831001 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9641 16:44:40.837871 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9642 16:44:40.841581 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9643 16:44:40.844502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9644 16:44:40.850815 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9645 16:44:40.853946 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9646 16:44:40.860682 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9647 16:44:40.863930 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9648 16:44:40.867246 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9649 16:44:40.874151 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9650 16:44:40.877667 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9651 16:44:40.884568 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9652 16:44:40.886911 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9653 16:44:40.890898 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9654 16:44:40.897052 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9655 16:44:40.900361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9656 16:44:40.907049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9657 16:44:40.910708 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9658 16:44:40.913915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9659 16:44:40.920569 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9660 16:44:40.923567 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9661 16:44:40.930253 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9662 16:44:40.933783 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9663 16:44:40.936585 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9664 16:44:40.943607 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9665 16:44:40.946561 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9666 16:44:40.953558 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9667 16:44:40.956449 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9668 16:44:40.963360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9669 16:44:40.966332 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9670 16:44:40.970058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9671 16:44:40.976600 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9672 16:44:40.979597 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9673 16:44:40.986344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9674 16:44:40.989587 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9675 16:44:40.996547 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9676 16:44:40.999681 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9677 16:44:41.002795 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9678 16:44:41.009739 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9679 16:44:41.012604 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9680 16:44:41.019438 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9681 16:44:41.022672 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9682 16:44:41.026116 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9683 16:44:41.032916 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9684 16:44:41.035770 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9685 16:44:41.043060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9686 16:44:41.045704 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9687 16:44:41.052221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9688 16:44:41.055317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9689 16:44:41.058893 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9690 16:44:41.065954 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9691 16:44:41.069311 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9692 16:44:41.075295 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9693 16:44:41.079422 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9694 16:44:41.085390 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9695 16:44:41.088355 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9696 16:44:41.091795 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9697 16:44:41.098797 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9698 16:44:41.101806 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9699 16:44:41.109039 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9700 16:44:41.112327 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9701 16:44:41.118268 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9702 16:44:41.121784 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9703 16:44:41.125020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9704 16:44:41.131298 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9705 16:44:41.135020 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9706 16:44:41.141361 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9707 16:44:41.144666 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9708 16:44:41.147316 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9709 16:44:41.150922 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9710 16:44:41.155187 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9711 16:44:41.161240 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9712 16:44:41.164153 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9713 16:44:41.170815 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9714 16:44:41.174014 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9715 16:44:41.177403 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9716 16:44:41.184292 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9717 16:44:41.187378 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9718 16:44:41.193932 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9719 16:44:41.197361 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9720 16:44:41.200764 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9721 16:44:41.207311 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9722 16:44:41.210704 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9723 16:44:41.213771 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9724 16:44:41.220628 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9725 16:44:41.223770 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9726 16:44:41.226858 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9727 16:44:41.233779 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9728 16:44:41.237047 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9729 16:44:41.243813 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9730 16:44:41.247245 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9731 16:44:41.250132 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9732 16:44:41.256519 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9733 16:44:41.259801 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9734 16:44:41.266873 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9735 16:44:41.269772 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9736 16:44:41.273123 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9737 16:44:41.279869 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9738 16:44:41.282631 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9739 16:44:41.286334 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9740 16:44:41.292933 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9741 16:44:41.296344 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9742 16:44:41.299670 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9743 16:44:41.306698 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9744 16:44:41.310037 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9745 16:44:41.315932 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9746 16:44:41.320288 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9747 16:44:41.322606 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9748 16:44:41.325578 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9749 16:44:41.328963 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9750 16:44:41.335579 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9751 16:44:41.339298 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9752 16:44:41.342480 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9753 16:44:41.346055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9754 16:44:41.352413 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9755 16:44:41.355494 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9756 16:44:41.359243 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9757 16:44:41.365282 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9758 16:44:41.368357 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9759 16:44:41.371992 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9760 16:44:41.378582 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9761 16:44:41.381677 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9762 16:44:41.388110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9763 16:44:41.391386 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9764 16:44:41.398517 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9765 16:44:41.401493 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9766 16:44:41.404902 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9767 16:44:41.411765 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9768 16:44:41.414736 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9769 16:44:41.421630 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9770 16:44:41.425008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9771 16:44:41.427605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9772 16:44:41.434495 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9773 16:44:41.437662 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9774 16:44:41.444604 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9775 16:44:41.447783 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9776 16:44:41.451282 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9777 16:44:41.457563 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9778 16:44:41.460921 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9779 16:44:41.467132 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9780 16:44:41.470931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9781 16:44:41.477672 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9782 16:44:41.480644 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9783 16:44:41.483976 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9784 16:44:41.490305 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9785 16:44:41.493870 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9786 16:44:41.501334 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9787 16:44:41.504117 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9788 16:44:41.507808 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9789 16:44:41.514306 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9790 16:44:41.517643 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9791 16:44:41.524632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9792 16:44:41.527164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9793 16:44:41.530388 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9794 16:44:41.536943 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9795 16:44:41.540577 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9796 16:44:41.547244 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9797 16:44:41.550551 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9798 16:44:41.553973 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9799 16:44:41.560353 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9800 16:44:41.563836 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9801 16:44:41.570181 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9802 16:44:41.573414 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9803 16:44:41.580086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9804 16:44:41.583354 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9805 16:44:41.589673 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9806 16:44:41.593083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9807 16:44:41.596439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9808 16:44:41.602836 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9809 16:44:41.606464 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9810 16:44:41.613397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9811 16:44:41.616251 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9812 16:44:41.619558 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9813 16:44:41.626601 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9814 16:44:41.629697 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9815 16:44:41.635944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9816 16:44:41.639411 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9817 16:44:41.642809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9818 16:44:41.649221 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9819 16:44:41.652823 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9820 16:44:41.659226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9821 16:44:41.663183 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9822 16:44:41.669009 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9823 16:44:41.672232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9824 16:44:41.675378 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9825 16:44:41.682159 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9826 16:44:41.685257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9827 16:44:41.692149 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9828 16:44:41.695069 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9829 16:44:41.701814 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9830 16:44:41.705197 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9831 16:44:41.708358 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9832 16:44:41.715942 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9833 16:44:41.718286 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9834 16:44:41.725284 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9835 16:44:41.728180 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9836 16:44:41.735034 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9837 16:44:41.738282 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9838 16:44:41.741786 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9839 16:44:41.748563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9840 16:44:41.751345 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9841 16:44:41.758500 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9842 16:44:41.761878 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9843 16:44:41.768106 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9844 16:44:41.771252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9845 16:44:41.778770 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9846 16:44:41.781417 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9847 16:44:41.784491 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9848 16:44:41.791268 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9849 16:44:41.794841 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9850 16:44:41.801114 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9851 16:44:41.804451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9852 16:44:41.810826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9853 16:44:41.814109 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9854 16:44:41.817571 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9855 16:44:41.824440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9856 16:44:41.827379 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9857 16:44:41.834183 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9858 16:44:41.837346 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9859 16:44:41.843854 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9860 16:44:41.847154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9861 16:44:41.853748 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9862 16:44:41.856985 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9863 16:44:41.863848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9864 16:44:41.867233 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9865 16:44:41.870224 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9866 16:44:41.876891 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9867 16:44:41.879981 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9868 16:44:41.886684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9869 16:44:41.890032 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9870 16:44:41.896229 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9871 16:44:41.899966 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9872 16:44:41.906245 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9873 16:44:41.910158 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9874 16:44:41.913151 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9875 16:44:41.919329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9876 16:44:41.922844 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9877 16:44:41.929569 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9878 16:44:41.932726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9879 16:44:41.936494 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9880 16:44:41.942655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9881 16:44:41.945920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9882 16:44:41.952613 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9883 16:44:41.955888 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9884 16:44:41.962913 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9885 16:44:41.966173 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9886 16:44:41.972837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9887 16:44:41.975771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9888 16:44:41.982332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9889 16:44:41.985723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9890 16:44:41.992002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9891 16:44:41.995741 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9892 16:44:42.002142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9893 16:44:42.005919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9894 16:44:42.012452 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9895 16:44:42.015325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9896 16:44:42.022668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9897 16:44:42.025712 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9898 16:44:42.032393 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9899 16:44:42.035489 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9900 16:44:42.041808 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9901 16:44:42.045607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9902 16:44:42.052019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9903 16:44:42.055501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9904 16:44:42.061998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9905 16:44:42.064973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9906 16:44:42.071849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9907 16:44:42.075083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9908 16:44:42.081789 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9909 16:44:42.084536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9910 16:44:42.091254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9911 16:44:42.094538 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9912 16:44:42.098698 INFO: [APUAPC] vio 0
9913 16:44:42.101778 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9914 16:44:42.108049 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9915 16:44:42.110927 INFO: [APUAPC] D0_APC_0: 0x400510
9916 16:44:42.114339 INFO: [APUAPC] D0_APC_1: 0x0
9917 16:44:42.114853 INFO: [APUAPC] D0_APC_2: 0x1540
9918 16:44:42.117584 INFO: [APUAPC] D0_APC_3: 0x0
9919 16:44:42.121185 INFO: [APUAPC] D1_APC_0: 0xffffffff
9920 16:44:42.124393 INFO: [APUAPC] D1_APC_1: 0xffffffff
9921 16:44:42.127503 INFO: [APUAPC] D1_APC_2: 0x3fffff
9922 16:44:42.130949 INFO: [APUAPC] D1_APC_3: 0x0
9923 16:44:42.134418 INFO: [APUAPC] D2_APC_0: 0xffffffff
9924 16:44:42.137577 INFO: [APUAPC] D2_APC_1: 0xffffffff
9925 16:44:42.141242 INFO: [APUAPC] D2_APC_2: 0x3fffff
9926 16:44:42.144313 INFO: [APUAPC] D2_APC_3: 0x0
9927 16:44:42.147398 INFO: [APUAPC] D3_APC_0: 0xffffffff
9928 16:44:42.151179 INFO: [APUAPC] D3_APC_1: 0xffffffff
9929 16:44:42.154124 INFO: [APUAPC] D3_APC_2: 0x3fffff
9930 16:44:42.157600 INFO: [APUAPC] D3_APC_3: 0x0
9931 16:44:42.160963 INFO: [APUAPC] D4_APC_0: 0xffffffff
9932 16:44:42.164242 INFO: [APUAPC] D4_APC_1: 0xffffffff
9933 16:44:42.167708 INFO: [APUAPC] D4_APC_2: 0x3fffff
9934 16:44:42.170476 INFO: [APUAPC] D4_APC_3: 0x0
9935 16:44:42.174205 INFO: [APUAPC] D5_APC_0: 0xffffffff
9936 16:44:42.177380 INFO: [APUAPC] D5_APC_1: 0xffffffff
9937 16:44:42.181423 INFO: [APUAPC] D5_APC_2: 0x3fffff
9938 16:44:42.184030 INFO: [APUAPC] D5_APC_3: 0x0
9939 16:44:42.187595 INFO: [APUAPC] D6_APC_0: 0xffffffff
9940 16:44:42.190210 INFO: [APUAPC] D6_APC_1: 0xffffffff
9941 16:44:42.194524 INFO: [APUAPC] D6_APC_2: 0x3fffff
9942 16:44:42.197599 INFO: [APUAPC] D6_APC_3: 0x0
9943 16:44:42.200837 INFO: [APUAPC] D7_APC_0: 0xffffffff
9944 16:44:42.204730 INFO: [APUAPC] D7_APC_1: 0xffffffff
9945 16:44:42.206977 INFO: [APUAPC] D7_APC_2: 0x3fffff
9946 16:44:42.210614 INFO: [APUAPC] D7_APC_3: 0x0
9947 16:44:42.214027 INFO: [APUAPC] D8_APC_0: 0xffffffff
9948 16:44:42.217241 INFO: [APUAPC] D8_APC_1: 0xffffffff
9949 16:44:42.220739 INFO: [APUAPC] D8_APC_2: 0x3fffff
9950 16:44:42.223672 INFO: [APUAPC] D8_APC_3: 0x0
9951 16:44:42.227109 INFO: [APUAPC] D9_APC_0: 0xffffffff
9952 16:44:42.230525 INFO: [APUAPC] D9_APC_1: 0xffffffff
9953 16:44:42.233434 INFO: [APUAPC] D9_APC_2: 0x3fffff
9954 16:44:42.237073 INFO: [APUAPC] D9_APC_3: 0x0
9955 16:44:42.240371 INFO: [APUAPC] D10_APC_0: 0xffffffff
9956 16:44:42.243625 INFO: [APUAPC] D10_APC_1: 0xffffffff
9957 16:44:42.247127 INFO: [APUAPC] D10_APC_2: 0x3fffff
9958 16:44:42.250376 INFO: [APUAPC] D10_APC_3: 0x0
9959 16:44:42.253503 INFO: [APUAPC] D11_APC_0: 0xffffffff
9960 16:44:42.257165 INFO: [APUAPC] D11_APC_1: 0xffffffff
9961 16:44:42.260501 INFO: [APUAPC] D11_APC_2: 0x3fffff
9962 16:44:42.263793 INFO: [APUAPC] D11_APC_3: 0x0
9963 16:44:42.266977 INFO: [APUAPC] D12_APC_0: 0xffffffff
9964 16:44:42.270062 INFO: [APUAPC] D12_APC_1: 0xffffffff
9965 16:44:42.274059 INFO: [APUAPC] D12_APC_2: 0x3fffff
9966 16:44:42.277188 INFO: [APUAPC] D12_APC_3: 0x0
9967 16:44:42.280370 INFO: [APUAPC] D13_APC_0: 0xffffffff
9968 16:44:42.283303 INFO: [APUAPC] D13_APC_1: 0xffffffff
9969 16:44:42.286816 INFO: [APUAPC] D13_APC_2: 0x3fffff
9970 16:44:42.290109 INFO: [APUAPC] D13_APC_3: 0x0
9971 16:44:42.293436 INFO: [APUAPC] D14_APC_0: 0xffffffff
9972 16:44:42.296505 INFO: [APUAPC] D14_APC_1: 0xffffffff
9973 16:44:42.299954 INFO: [APUAPC] D14_APC_2: 0x3fffff
9974 16:44:42.303250 INFO: [APUAPC] D14_APC_3: 0x0
9975 16:44:42.306336 INFO: [APUAPC] D15_APC_0: 0xffffffff
9976 16:44:42.310292 INFO: [APUAPC] D15_APC_1: 0xffffffff
9977 16:44:42.313496 INFO: [APUAPC] D15_APC_2: 0x3fffff
9978 16:44:42.316768 INFO: [APUAPC] D15_APC_3: 0x0
9979 16:44:42.320135 INFO: [APUAPC] APC_CON: 0x4
9980 16:44:42.323039 INFO: [NOCDAPC] D0_APC_0: 0x0
9981 16:44:42.323529 INFO: [NOCDAPC] D0_APC_1: 0x0
9982 16:44:42.326449 INFO: [NOCDAPC] D1_APC_0: 0x0
9983 16:44:42.329911 INFO: [NOCDAPC] D1_APC_1: 0xfff
9984 16:44:42.332855 INFO: [NOCDAPC] D2_APC_0: 0x0
9985 16:44:42.336683 INFO: [NOCDAPC] D2_APC_1: 0xfff
9986 16:44:42.339397 INFO: [NOCDAPC] D3_APC_0: 0x0
9987 16:44:42.342849 INFO: [NOCDAPC] D3_APC_1: 0xfff
9988 16:44:42.346309 INFO: [NOCDAPC] D4_APC_0: 0x0
9989 16:44:42.349450 INFO: [NOCDAPC] D4_APC_1: 0xfff
9990 16:44:42.352707 INFO: [NOCDAPC] D5_APC_0: 0x0
9991 16:44:42.356421 INFO: [NOCDAPC] D5_APC_1: 0xfff
9992 16:44:42.356897 INFO: [NOCDAPC] D6_APC_0: 0x0
9993 16:44:42.359195 INFO: [NOCDAPC] D6_APC_1: 0xfff
9994 16:44:42.362998 INFO: [NOCDAPC] D7_APC_0: 0x0
9995 16:44:42.366408 INFO: [NOCDAPC] D7_APC_1: 0xfff
9996 16:44:42.369410 INFO: [NOCDAPC] D8_APC_0: 0x0
9997 16:44:42.372763 INFO: [NOCDAPC] D8_APC_1: 0xfff
9998 16:44:42.376138 INFO: [NOCDAPC] D9_APC_0: 0x0
9999 16:44:42.379269 INFO: [NOCDAPC] D9_APC_1: 0xfff
10000 16:44:42.383068 INFO: [NOCDAPC] D10_APC_0: 0x0
10001 16:44:42.385961 INFO: [NOCDAPC] D10_APC_1: 0xfff
10002 16:44:42.389339 INFO: [NOCDAPC] D11_APC_0: 0x0
10003 16:44:42.392555 INFO: [NOCDAPC] D11_APC_1: 0xfff
10004 16:44:42.395477 INFO: [NOCDAPC] D12_APC_0: 0x0
10005 16:44:42.398955 INFO: [NOCDAPC] D12_APC_1: 0xfff
10006 16:44:42.399527 INFO: [NOCDAPC] D13_APC_0: 0x0
10007 16:44:42.401984 INFO: [NOCDAPC] D13_APC_1: 0xfff
10008 16:44:42.405592 INFO: [NOCDAPC] D14_APC_0: 0x0
10009 16:44:42.408972 INFO: [NOCDAPC] D14_APC_1: 0xfff
10010 16:44:42.412304 INFO: [NOCDAPC] D15_APC_0: 0x0
10011 16:44:42.415365 INFO: [NOCDAPC] D15_APC_1: 0xfff
10012 16:44:42.418957 INFO: [NOCDAPC] APC_CON: 0x4
10013 16:44:42.421866 INFO: [APUAPC] set_apusys_apc done
10014 16:44:42.425915 INFO: [DEVAPC] devapc_init done
10015 16:44:42.428653 INFO: GICv3 without legacy support detected.
10016 16:44:42.431809 INFO: ARM GICv3 driver initialized in EL3
10017 16:44:42.438542 INFO: Maximum SPI INTID supported: 639
10018 16:44:42.442394 INFO: BL31: Initializing runtime services
10019 16:44:42.449542 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10020 16:44:42.450111 INFO: SPM: enable CPC mode
10021 16:44:42.454808 INFO: mcdi ready for mcusys-off-idle and system suspend
10022 16:44:42.458599 INFO: BL31: Preparing for EL3 exit to normal world
10023 16:44:42.464922 INFO: Entry point address = 0x80000000
10024 16:44:42.465496 INFO: SPSR = 0x8
10025 16:44:42.470702
10026 16:44:42.471167
10027 16:44:42.471535
10028 16:44:42.474312 Starting depthcharge on Spherion...
10029 16:44:42.474913
10030 16:44:42.475287 Wipe memory regions:
10031 16:44:42.475634
10032 16:44:42.478075 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10033 16:44:42.478649 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10034 16:44:42.479103 Setting prompt string to ['asurada:']
10035 16:44:42.479534 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10036 16:44:42.480254 [0x00000040000000, 0x00000054600000)
10037 16:44:42.599804
10038 16:44:42.600382 [0x00000054660000, 0x00000080000000)
10039 16:44:42.860833
10040 16:44:42.861422 [0x000000821a7280, 0x000000ffe64000)
10041 16:44:43.605413
10042 16:44:43.605991 [0x00000100000000, 0x00000240000000)
10043 16:44:45.495649
10044 16:44:45.498764 Initializing XHCI USB controller at 0x11200000.
10045 16:44:46.536965
10046 16:44:46.540519 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10047 16:44:46.541094
10048 16:44:46.541470
10049 16:44:46.541820
10050 16:44:46.542705 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10052 16:44:46.644071 asurada: tftpboot 192.168.201.1 10576340/tftp-deploy-enr8th00/kernel/image.itb 10576340/tftp-deploy-enr8th00/kernel/cmdline
10053 16:44:46.644749 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10054 16:44:46.645314 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10055 16:44:46.649878 tftpboot 192.168.201.1 10576340/tftp-deploy-enr8th00/kernel/image.itp-deploy-enr8th00/kernel/cmdline
10056 16:44:46.650387
10057 16:44:46.650773 Waiting for link
10058 16:44:46.808289
10059 16:44:46.808876 R8152: Initializing
10060 16:44:46.809257
10061 16:44:46.810975 Version 9 (ocp_data = 6010)
10062 16:44:46.811443
10063 16:44:46.814325 R8152: Done initializing
10064 16:44:46.814843
10065 16:44:46.815214 Adding net device
10066 16:44:48.685075
10067 16:44:48.685641 done.
10068 16:44:48.686019
10069 16:44:48.686412 MAC: 00:e0:4c:72:2d:d6
10070 16:44:48.686764
10071 16:44:48.688319 Sending DHCP discover... done.
10072 16:44:48.688788
10073 16:44:48.691469 Waiting for reply... done.
10074 16:44:48.691939
10075 16:44:48.694799 Sending DHCP request... done.
10076 16:44:48.695265
10077 16:44:48.695635 Waiting for reply... done.
10078 16:44:48.695982
10079 16:44:48.698598 My ip is 192.168.201.21
10080 16:44:48.699064
10081 16:44:48.701555 The DHCP server ip is 192.168.201.1
10082 16:44:48.702027
10083 16:44:48.705018 TFTP server IP predefined by user: 192.168.201.1
10084 16:44:48.705487
10085 16:44:48.711302 Bootfile predefined by user: 10576340/tftp-deploy-enr8th00/kernel/image.itb
10086 16:44:48.711776
10087 16:44:48.714540 Sending tftp read request... done.
10088 16:44:48.715014
10089 16:44:48.721524 Waiting for the transfer...
10090 16:44:48.722115
10091 16:44:49.132305 00000000 ################################################################
10092 16:44:49.132857
10093 16:44:49.516080 00080000 ################################################################
10094 16:44:49.516583
10095 16:44:49.925316 00100000 ################################################################
10096 16:44:49.925828
10097 16:44:50.303174 00180000 ################################################################
10098 16:44:50.303698
10099 16:44:50.685850 00200000 ################################################################
10100 16:44:50.686385
10101 16:44:51.072719 00280000 ################################################################
10102 16:44:51.073227
10103 16:44:51.454842 00300000 ################################################################
10104 16:44:51.455366
10105 16:44:51.775645 00380000 ################################################################
10106 16:44:51.775779
10107 16:44:52.076441 00400000 ################################################################
10108 16:44:52.076575
10109 16:44:52.459302 00480000 ################################################################
10110 16:44:52.459808
10111 16:44:52.840976 00500000 ################################################################
10112 16:44:52.841491
10113 16:44:53.224588 00580000 ################################################################
10114 16:44:53.225268
10115 16:44:53.589817 00600000 ################################################################
10116 16:44:53.589956
10117 16:44:53.874649 00680000 ################################################################
10118 16:44:53.874789
10119 16:44:54.163461 00700000 ################################################################
10120 16:44:54.163597
10121 16:44:54.459684 00780000 ################################################################
10122 16:44:54.459818
10123 16:44:54.756044 00800000 ################################################################
10124 16:44:54.756176
10125 16:44:55.053817 00880000 ################################################################
10126 16:44:55.053949
10127 16:44:55.350941 00900000 ################################################################
10128 16:44:55.351069
10129 16:44:55.626907 00980000 ################################################################
10130 16:44:55.627034
10131 16:44:55.876447 00a00000 ################################################################
10132 16:44:55.876577
10133 16:44:56.126046 00a80000 ################################################################
10134 16:44:56.126179
10135 16:44:56.375632 00b00000 ################################################################
10136 16:44:56.375761
10137 16:44:56.625253 00b80000 ################################################################
10138 16:44:56.625381
10139 16:44:56.874999 00c00000 ################################################################
10140 16:44:56.875128
10141 16:44:57.124584 00c80000 ################################################################
10142 16:44:57.124709
10143 16:44:57.413041 00d00000 ################################################################
10144 16:44:57.413174
10145 16:44:57.705451 00d80000 ################################################################
10146 16:44:57.705583
10147 16:44:57.996556 00e00000 ################################################################
10148 16:44:57.996712
10149 16:44:58.291853 00e80000 ################################################################
10150 16:44:58.291987
10151 16:44:58.587979 00f00000 ################################################################
10152 16:44:58.588109
10153 16:44:58.837053 00f80000 ################################################################
10154 16:44:58.837178
10155 16:44:59.086724 01000000 ################################################################
10156 16:44:59.086850
10157 16:44:59.338185 01080000 ################################################################
10158 16:44:59.338322
10159 16:44:59.596427 01100000 ################################################################
10160 16:44:59.596553
10161 16:44:59.889303 01180000 ################################################################
10162 16:44:59.889435
10163 16:45:00.153544 01200000 ################################################################
10164 16:45:00.153671
10165 16:45:00.450591 01280000 ################################################################
10166 16:45:00.450746
10167 16:45:00.747338 01300000 ################################################################
10168 16:45:00.747482
10169 16:45:01.039751 01380000 ################################################################
10170 16:45:01.039887
10171 16:45:01.328661 01400000 ################################################################
10172 16:45:01.328799
10173 16:45:01.619524 01480000 ################################################################
10174 16:45:01.619656
10175 16:45:01.907760 01500000 ################################################################
10176 16:45:01.907901
10177 16:45:02.209648 01580000 ################################################################
10178 16:45:02.209781
10179 16:45:02.509611 01600000 ################################################################
10180 16:45:02.509745
10181 16:45:02.818176 01680000 ################################################################
10182 16:45:02.818771
10183 16:45:03.161292 01700000 ################################################################
10184 16:45:03.161433
10185 16:45:03.459335 01780000 ################################################################
10186 16:45:03.459474
10187 16:45:03.750532 01800000 ################################################################
10188 16:45:03.750661
10189 16:45:04.047554 01880000 ################################################################
10190 16:45:04.047710
10191 16:45:04.317650 01900000 ################################################################
10192 16:45:04.317804
10193 16:45:04.566242 01980000 ################################################################
10194 16:45:04.566425
10195 16:45:04.815895 01a00000 ################################################################
10196 16:45:04.816041
10197 16:45:05.066182 01a80000 ################################################################
10198 16:45:05.066329
10199 16:45:05.315830 01b00000 ################################################################
10200 16:45:05.315952
10201 16:45:05.565256 01b80000 ################################################################
10202 16:45:05.565402
10203 16:45:05.814755 01c00000 ################################################################
10204 16:45:05.814879
10205 16:45:06.064523 01c80000 ################################################################
10206 16:45:06.064669
10207 16:45:06.314364 01d00000 ################################################################
10208 16:45:06.314492
10209 16:45:06.516656 01d80000 ##################################################### done.
10210 16:45:06.516808
10211 16:45:06.520217 The bootfile was 31363990 bytes long.
10212 16:45:06.520294
10213 16:45:06.523645 Sending tftp read request... done.
10214 16:45:06.523733
10215 16:45:06.527477 Waiting for the transfer...
10216 16:45:06.527663
10217 16:45:06.530258 00000000 # done.
10218 16:45:06.530417
10219 16:45:06.536720 Command line loaded dynamically from TFTP file: 10576340/tftp-deploy-enr8th00/kernel/cmdline
10220 16:45:06.536834
10221 16:45:06.546792 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10222 16:45:06.547003
10223 16:45:06.550307 Loading FIT.
10224 16:45:06.550546
10225 16:45:06.554665 Image ramdisk-1 has 21231557 bytes.
10226 16:45:06.554902
10227 16:45:06.557015 Image fdt-1 has 46924 bytes.
10228 16:45:06.557174
10229 16:45:06.557294 Image kernel-1 has 10083474 bytes.
10230 16:45:06.557406
10231 16:45:06.567111 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10232 16:45:06.567314
10233 16:45:06.586686 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10234 16:45:06.587190
10235 16:45:06.589843 Choosing best match conf-1 for compat google,spherion-rev2.
10236 16:45:06.594883
10237 16:45:06.598793 Connected to device vid:did:rid of 1ae0:0028:00
10238 16:45:06.606460
10239 16:45:06.609614 tpm_get_response: command 0x17b, return code 0x0
10240 16:45:06.610193
10241 16:45:06.612442 ec_init: CrosEC protocol v3 supported (256, 248)
10242 16:45:06.617743
10243 16:45:06.621900 tpm_cleanup: add release locality here.
10244 16:45:06.622533
10245 16:45:06.622924 Shutting down all USB controllers.
10246 16:45:06.624601
10247 16:45:06.625070 Removing current net device
10248 16:45:06.625444
10249 16:45:06.631287 Exiting depthcharge with code 4 at timestamp: 53443753
10250 16:45:06.631848
10251 16:45:06.635048 LZMA decompressing kernel-1 to 0x821a6718
10252 16:45:06.635522
10253 16:45:06.638290 LZMA decompressing kernel-1 to 0x40000000
10254 16:45:07.903491
10255 16:45:07.904061 jumping to kernel
10256 16:45:07.905507 end: 2.2.4 bootloader-commands (duration 00:00:25) [common]
10257 16:45:07.906049 start: 2.2.5 auto-login-action (timeout 00:04:00) [common]
10258 16:45:07.906503 Setting prompt string to ['Linux version [0-9]']
10259 16:45:07.906898 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10260 16:45:07.907290 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10261 16:45:07.986345
10262 16:45:07.989939 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10263 16:45:07.993981 start: 2.2.5.1 login-action (timeout 00:04:00) [common]
10264 16:45:07.994608 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10265 16:45:07.995100 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10266 16:45:07.995533 Using line separator: #'\n'#
10267 16:45:07.996051 No login prompt set.
10268 16:45:07.996432 Parsing kernel messages
10269 16:45:07.996768 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10270 16:45:07.997371 [login-action] Waiting for messages, (timeout 00:04:00)
10271 16:45:08.012400 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10272 16:45:08.015605 [ 0.000000] random: crng init done
10273 16:45:08.022402 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10274 16:45:08.022586 [ 0.000000] efi: UEFI not found.
10275 16:45:08.032250 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10276 16:45:08.039254 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10277 16:45:08.048763 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10278 16:45:08.059087 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10279 16:45:08.065520 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10280 16:45:08.072284 [ 0.000000] printk: bootconsole [mtk8250] enabled
10281 16:45:08.079123 [ 0.000000] NUMA: No NUMA configuration found
10282 16:45:08.085134 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10283 16:45:08.088814 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10284 16:45:08.093218 [ 0.000000] Zone ranges:
10285 16:45:08.098185 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10286 16:45:08.101902 [ 0.000000] DMA32 empty
10287 16:45:08.108193 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10288 16:45:08.111712 [ 0.000000] Movable zone start for each node
10289 16:45:08.114816 [ 0.000000] Early memory node ranges
10290 16:45:08.121790 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10291 16:45:08.128177 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10292 16:45:08.134738 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10293 16:45:08.141419 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10294 16:45:08.148066 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10295 16:45:08.154933 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10296 16:45:08.210519 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10297 16:45:08.216863 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10298 16:45:08.223176 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10299 16:45:08.226634 [ 0.000000] psci: probing for conduit method from DT.
10300 16:45:08.233274 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10301 16:45:08.236257 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10302 16:45:08.243196 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10303 16:45:08.246522 [ 0.000000] psci: SMC Calling Convention v1.2
10304 16:45:08.252927 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10305 16:45:08.256316 [ 0.000000] Detected VIPT I-cache on CPU0
10306 16:45:08.262999 [ 0.000000] CPU features: detected: GIC system register CPU interface
10307 16:45:08.269546 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10308 16:45:08.275821 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10309 16:45:08.282845 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10310 16:45:08.292585 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10311 16:45:08.298961 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10312 16:45:08.302458 [ 0.000000] alternatives: applying boot alternatives
10313 16:45:08.309043 [ 0.000000] Fallback order for Node 0: 0
10314 16:45:08.315893 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10315 16:45:08.319215 [ 0.000000] Policy zone: Normal
10316 16:45:08.331793 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10317 16:45:08.342239 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10318 16:45:08.351898 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10319 16:45:08.362087 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10320 16:45:08.368696 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10321 16:45:08.371559 <6>[ 0.000000] software IO TLB: area num 8.
10322 16:45:08.428388 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10323 16:45:08.577822 <6>[ 0.000000] Memory: 7952208K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400560K reserved, 32768K cma-reserved)
10324 16:45:08.584419 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10325 16:45:08.590773 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10326 16:45:08.594527 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10327 16:45:08.600919 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10328 16:45:08.607346 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10329 16:45:08.610402 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10330 16:45:08.620669 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10331 16:45:08.627410 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10332 16:45:08.633892 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10333 16:45:08.640405 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10334 16:45:08.643801 <6>[ 0.000000] GICv3: 608 SPIs implemented
10335 16:45:08.646600 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10336 16:45:08.653480 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10337 16:45:08.656834 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10338 16:45:08.663683 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10339 16:45:08.676990 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10340 16:45:08.689962 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10341 16:45:08.696345 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10342 16:45:08.704107 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10343 16:45:08.717597 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10344 16:45:08.724595 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10345 16:45:08.730687 <6>[ 0.009177] Console: colour dummy device 80x25
10346 16:45:08.740470 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10347 16:45:08.747381 <6>[ 0.024376] pid_max: default: 32768 minimum: 301
10348 16:45:08.750710 <6>[ 0.029250] LSM: Security Framework initializing
10349 16:45:08.756987 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10350 16:45:08.767251 <6>[ 0.042001] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10351 16:45:08.776926 <6>[ 0.051427] cblist_init_generic: Setting adjustable number of callback queues.
10352 16:45:08.780368 <6>[ 0.058881] cblist_init_generic: Setting shift to 3 and lim to 1.
10353 16:45:08.786898 <6>[ 0.065218] cblist_init_generic: Setting shift to 3 and lim to 1.
10354 16:45:08.793472 <6>[ 0.071626] rcu: Hierarchical SRCU implementation.
10355 16:45:08.799925 <6>[ 0.076670] rcu: Max phase no-delay instances is 1000.
10356 16:45:08.803615 <6>[ 0.083691] EFI services will not be available.
10357 16:45:08.810744 <6>[ 0.088667] smp: Bringing up secondary CPUs ...
10358 16:45:08.817686 <6>[ 0.093720] Detected VIPT I-cache on CPU1
10359 16:45:08.823931 <6>[ 0.093793] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10360 16:45:08.830825 <6>[ 0.093821] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10361 16:45:08.834153 <6>[ 0.094161] Detected VIPT I-cache on CPU2
10362 16:45:08.840867 <6>[ 0.094212] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10363 16:45:08.850568 <6>[ 0.094227] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10364 16:45:08.854212 <6>[ 0.094486] Detected VIPT I-cache on CPU3
10365 16:45:08.860371 <6>[ 0.094534] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10366 16:45:08.867722 <6>[ 0.094548] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10367 16:45:08.870403 <6>[ 0.094857] CPU features: detected: Spectre-v4
10368 16:45:08.876890 <6>[ 0.094863] CPU features: detected: Spectre-BHB
10369 16:45:08.880072 <6>[ 0.094868] Detected PIPT I-cache on CPU4
10370 16:45:08.887695 <6>[ 0.094927] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10371 16:45:08.893752 <6>[ 0.094945] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10372 16:45:08.900765 <6>[ 0.095243] Detected PIPT I-cache on CPU5
10373 16:45:08.907026 <6>[ 0.095305] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10374 16:45:08.913595 <6>[ 0.095322] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10375 16:45:08.916610 <6>[ 0.095606] Detected PIPT I-cache on CPU6
10376 16:45:08.923241 <6>[ 0.095672] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10377 16:45:08.930270 <6>[ 0.095688] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10378 16:45:08.936748 <6>[ 0.095986] Detected PIPT I-cache on CPU7
10379 16:45:08.943855 <6>[ 0.096051] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10380 16:45:08.949744 <6>[ 0.096067] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10381 16:45:08.953257 <6>[ 0.096117] smp: Brought up 1 node, 8 CPUs
10382 16:45:08.959597 <6>[ 0.237388] SMP: Total of 8 processors activated.
10383 16:45:08.962672 <6>[ 0.242340] CPU features: detected: 32-bit EL0 Support
10384 16:45:08.972719 <6>[ 0.247736] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10385 16:45:08.979386 <6>[ 0.256536] CPU features: detected: Common not Private translations
10386 16:45:08.985697 <6>[ 0.263012] CPU features: detected: CRC32 instructions
10387 16:45:08.989113 <6>[ 0.268364] CPU features: detected: RCpc load-acquire (LDAPR)
10388 16:45:08.995881 <6>[ 0.274323] CPU features: detected: LSE atomic instructions
10389 16:45:09.002597 <6>[ 0.280140] CPU features: detected: Privileged Access Never
10390 16:45:09.009292 <6>[ 0.285920] CPU features: detected: RAS Extension Support
10391 16:45:09.015964 <6>[ 0.291529] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10392 16:45:09.019041 <6>[ 0.298793] CPU: All CPU(s) started at EL2
10393 16:45:09.025747 <6>[ 0.303109] alternatives: applying system-wide alternatives
10394 16:45:09.035123 <6>[ 0.313779] devtmpfs: initialized
10395 16:45:09.050950 <6>[ 0.322657] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10396 16:45:09.057808 <6>[ 0.332619] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10397 16:45:09.064006 <6>[ 0.340649] pinctrl core: initialized pinctrl subsystem
10398 16:45:09.067177 <6>[ 0.347287] DMI not present or invalid.
10399 16:45:09.073624 <6>[ 0.351698] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10400 16:45:09.083711 <6>[ 0.358561] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10401 16:45:09.090267 <6>[ 0.366141] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10402 16:45:09.099993 <6>[ 0.374360] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10403 16:45:09.103145 <6>[ 0.382601] audit: initializing netlink subsys (disabled)
10404 16:45:09.113214 <5>[ 0.388298] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10405 16:45:09.119631 <6>[ 0.388995] thermal_sys: Registered thermal governor 'step_wise'
10406 16:45:09.126796 <6>[ 0.396265] thermal_sys: Registered thermal governor 'power_allocator'
10407 16:45:09.130595 <6>[ 0.402519] cpuidle: using governor menu
10408 16:45:09.136665 <6>[ 0.413481] NET: Registered PF_QIPCRTR protocol family
10409 16:45:09.142812 <6>[ 0.418956] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10410 16:45:09.149823 <6>[ 0.426060] ASID allocator initialised with 32768 entries
10411 16:45:09.153039 <6>[ 0.432622] Serial: AMBA PL011 UART driver
10412 16:45:09.162636 <4>[ 0.441229] Trying to register duplicate clock ID: 134
10413 16:45:09.217061 <6>[ 0.498556] KASLR enabled
10414 16:45:09.231063 <6>[ 0.506291] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10415 16:45:09.237440 <6>[ 0.513305] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10416 16:45:09.244109 <6>[ 0.519795] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10417 16:45:09.250787 <6>[ 0.526801] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10418 16:45:09.256848 <6>[ 0.533289] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10419 16:45:09.263708 <6>[ 0.540294] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10420 16:45:09.270272 <6>[ 0.546782] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10421 16:45:09.277315 <6>[ 0.553787] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10422 16:45:09.280096 <6>[ 0.561205] ACPI: Interpreter disabled.
10423 16:45:09.289295 <6>[ 0.567644] iommu: Default domain type: Translated
10424 16:45:09.295891 <6>[ 0.572757] iommu: DMA domain TLB invalidation policy: strict mode
10425 16:45:09.298862 <5>[ 0.579423] SCSI subsystem initialized
10426 16:45:09.305259 <6>[ 0.583660] usbcore: registered new interface driver usbfs
10427 16:45:09.312103 <6>[ 0.589391] usbcore: registered new interface driver hub
10428 16:45:09.314960 <6>[ 0.594946] usbcore: registered new device driver usb
10429 16:45:09.322151 <6>[ 0.601047] pps_core: LinuxPPS API ver. 1 registered
10430 16:45:09.332592 <6>[ 0.606242] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10431 16:45:09.335946 <6>[ 0.615588] PTP clock support registered
10432 16:45:09.338977 <6>[ 0.619827] EDAC MC: Ver: 3.0.0
10433 16:45:09.346504 <6>[ 0.625010] FPGA manager framework
10434 16:45:09.352845 <6>[ 0.628687] Advanced Linux Sound Architecture Driver Initialized.
10435 16:45:09.356139 <6>[ 0.635452] vgaarb: loaded
10436 16:45:09.362947 <6>[ 0.638608] clocksource: Switched to clocksource arch_sys_counter
10437 16:45:09.365920 <5>[ 0.645045] VFS: Disk quotas dquot_6.6.0
10438 16:45:09.373097 <6>[ 0.649232] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10439 16:45:09.375585 <6>[ 0.656426] pnp: PnP ACPI: disabled
10440 16:45:09.384444 <6>[ 0.663092] NET: Registered PF_INET protocol family
10441 16:45:09.394513 <6>[ 0.668676] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10442 16:45:09.405691 <6>[ 0.680989] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10443 16:45:09.415395 <6>[ 0.689807] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10444 16:45:09.422176 <6>[ 0.697776] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10445 16:45:09.432081 <6>[ 0.706478] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10446 16:45:09.438827 <6>[ 0.716221] TCP: Hash tables configured (established 65536 bind 65536)
10447 16:45:09.445917 <6>[ 0.723079] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10448 16:45:09.455233 <6>[ 0.730277] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10449 16:45:09.461863 <6>[ 0.737980] NET: Registered PF_UNIX/PF_LOCAL protocol family
10450 16:45:09.468664 <6>[ 0.744148] RPC: Registered named UNIX socket transport module.
10451 16:45:09.472045 <6>[ 0.750302] RPC: Registered udp transport module.
10452 16:45:09.478113 <6>[ 0.755236] RPC: Registered tcp transport module.
10453 16:45:09.484710 <6>[ 0.760169] RPC: Registered tcp NFSv4.1 backchannel transport module.
10454 16:45:09.488136 <6>[ 0.766839] PCI: CLS 0 bytes, default 64
10455 16:45:09.491024 <6>[ 0.771237] Unpacking initramfs...
10456 16:45:09.507996 <6>[ 0.783239] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10457 16:45:09.517785 <6>[ 0.791907] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10458 16:45:09.521417 <6>[ 0.800753] kvm [1]: IPA Size Limit: 40 bits
10459 16:45:09.527707 <6>[ 0.805284] kvm [1]: GICv3: no GICV resource entry
10460 16:45:09.530823 <6>[ 0.810306] kvm [1]: disabling GICv2 emulation
10461 16:45:09.538166 <6>[ 0.814993] kvm [1]: GIC system register CPU interface enabled
10462 16:45:09.540834 <6>[ 0.821163] kvm [1]: vgic interrupt IRQ18
10463 16:45:09.548596 <6>[ 0.826705] kvm [1]: VHE mode initialized successfully
10464 16:45:09.554732 <5>[ 0.833136] Initialise system trusted keyrings
10465 16:45:09.562423 <6>[ 0.837925] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10466 16:45:09.570033 <6>[ 0.848208] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10467 16:45:09.576285 <5>[ 0.854617] NFS: Registering the id_resolver key type
10468 16:45:09.579357 <5>[ 0.859917] Key type id_resolver registered
10469 16:45:09.586428 <5>[ 0.864335] Key type id_legacy registered
10470 16:45:09.593352 <6>[ 0.868622] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10471 16:45:09.599330 <6>[ 0.875546] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10472 16:45:09.605934 <6>[ 0.883287] 9p: Installing v9fs 9p2000 file system support
10473 16:45:09.642943 <5>[ 0.921413] Key type asymmetric registered
10474 16:45:09.645778 <5>[ 0.925749] Asymmetric key parser 'x509' registered
10475 16:45:09.655827 <6>[ 0.930903] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10476 16:45:09.658869 <6>[ 0.938520] io scheduler mq-deadline registered
10477 16:45:09.663004 <6>[ 0.943297] io scheduler kyber registered
10478 16:45:09.681381 <6>[ 0.960128] EINJ: ACPI disabled.
10479 16:45:09.714880 <4>[ 0.985676] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10480 16:45:09.723861 <4>[ 0.996347] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10481 16:45:09.738984 <6>[ 1.017171] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10482 16:45:09.746965 <6>[ 1.025162] printk: console [ttyS0] disabled
10483 16:45:09.774513 <6>[ 1.049811] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10484 16:45:09.780789 <6>[ 1.059309] printk: console [ttyS0] enabled
10485 16:45:09.785126 <6>[ 1.059309] printk: console [ttyS0] enabled
10486 16:45:09.790967 <6>[ 1.068205] printk: bootconsole [mtk8250] disabled
10487 16:45:09.794573 <6>[ 1.068205] printk: bootconsole [mtk8250] disabled
10488 16:45:09.801423 <6>[ 1.079471] SuperH (H)SCI(F) driver initialized
10489 16:45:09.804492 <6>[ 1.084788] msm_serial: driver initialized
10490 16:45:09.818952 <6>[ 1.093846] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10491 16:45:09.828288 <6>[ 1.102404] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10492 16:45:09.834978 <6>[ 1.110948] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10493 16:45:09.845151 <6>[ 1.119578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10494 16:45:09.854847 <6>[ 1.128283] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10495 16:45:09.861167 <6>[ 1.137009] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10496 16:45:09.871477 <6>[ 1.145552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10497 16:45:09.877694 <6>[ 1.154358] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10498 16:45:09.887302 <6>[ 1.162904] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10499 16:45:09.899943 <6>[ 1.178689] loop: module loaded
10500 16:45:09.906651 <6>[ 1.184738] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10501 16:45:09.929626 <4>[ 1.208238] mtk-pmic-keys: Failed to locate of_node [id: -1]
10502 16:45:09.936382 <6>[ 1.215005] megasas: 07.719.03.00-rc1
10503 16:45:09.946455 <6>[ 1.224860] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10504 16:45:09.959592 <6>[ 1.237995] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10505 16:45:09.975911 <6>[ 1.254700] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10506 16:45:10.036912 <6>[ 1.309064] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10507 16:45:10.381612 <6>[ 1.660491] Freeing initrd memory: 20728K
10508 16:45:10.397187 <6>[ 1.676097] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10509 16:45:10.408080 <6>[ 1.687128] tun: Universal TUN/TAP device driver, 1.6
10510 16:45:10.411692 <6>[ 1.693196] thunder_xcv, ver 1.0
10511 16:45:10.415252 <6>[ 1.696703] thunder_bgx, ver 1.0
10512 16:45:10.418036 <6>[ 1.700198] nicpf, ver 1.0
10513 16:45:10.428554 <6>[ 1.704231] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10514 16:45:10.432312 <6>[ 1.711707] hns3: Copyright (c) 2017 Huawei Corporation.
10515 16:45:10.439116 <6>[ 1.717293] hclge is initializing
10516 16:45:10.442761 <6>[ 1.720874] e1000: Intel(R) PRO/1000 Network Driver
10517 16:45:10.448869 <6>[ 1.726002] e1000: Copyright (c) 1999-2006 Intel Corporation.
10518 16:45:10.452144 <6>[ 1.732016] e1000e: Intel(R) PRO/1000 Network Driver
10519 16:45:10.459266 <6>[ 1.737231] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10520 16:45:10.465513 <6>[ 1.743420] igb: Intel(R) Gigabit Ethernet Network Driver
10521 16:45:10.472180 <6>[ 1.749069] igb: Copyright (c) 2007-2014 Intel Corporation.
10522 16:45:10.478398 <6>[ 1.754907] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10523 16:45:10.484838 <6>[ 1.761425] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10524 16:45:10.489256 <6>[ 1.767886] sky2: driver version 1.30
10525 16:45:10.495111 <6>[ 1.772868] VFIO - User Level meta-driver version: 0.3
10526 16:45:10.502253 <6>[ 1.781054] usbcore: registered new interface driver usb-storage
10527 16:45:10.508963 <6>[ 1.787503] usbcore: registered new device driver onboard-usb-hub
10528 16:45:10.517629 <6>[ 1.796585] mt6397-rtc mt6359-rtc: registered as rtc0
10529 16:45:10.527879 <6>[ 1.802057] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:45:10 UTC (1685810710)
10530 16:45:10.531285 <6>[ 1.811619] i2c_dev: i2c /dev entries driver
10531 16:45:10.547536 <6>[ 1.823249] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10532 16:45:10.554806 <6>[ 1.833504] sdhci: Secure Digital Host Controller Interface driver
10533 16:45:10.561565 <6>[ 1.839944] sdhci: Copyright(c) Pierre Ossman
10534 16:45:10.568011 <6>[ 1.845361] Synopsys Designware Multimedia Card Interface Driver
10535 16:45:10.571211 <6>[ 1.851972] mmc0: CQHCI version 5.10
10536 16:45:10.577930 <6>[ 1.852515] sdhci-pltfm: SDHCI platform and OF driver helper
10537 16:45:10.585301 <6>[ 1.863823] ledtrig-cpu: registered to indicate activity on CPUs
10538 16:45:10.596012 <6>[ 1.871174] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10539 16:45:10.598953 <6>[ 1.878562] usbcore: registered new interface driver usbhid
10540 16:45:10.606235 <6>[ 1.884388] usbhid: USB HID core driver
10541 16:45:10.612282 <6>[ 1.888631] spi_master spi0: will run message pump with realtime priority
10542 16:45:10.655758 <6>[ 1.928009] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10543 16:45:10.675223 <6>[ 1.943516] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10544 16:45:10.678204 <6>[ 1.957078] mmc0: Command Queue Engine enabled
10545 16:45:10.684799 <6>[ 1.961816] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10546 16:45:10.691638 <6>[ 1.968831] cros-ec-spi spi0.0: Chrome EC device registered
10547 16:45:10.694527 <6>[ 1.968945] mmcblk0: mmc0:0001 DA4128 116 GiB
10548 16:45:10.705744 <6>[ 1.984366] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10549 16:45:10.714173 <6>[ 1.992079] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10550 16:45:10.720629 <6>[ 1.998034] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10551 16:45:10.726541 <6>[ 2.004191] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10552 16:45:10.745063 <6>[ 2.019556] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10553 16:45:10.752064 <6>[ 2.031011] NET: Registered PF_PACKET protocol family
10554 16:45:10.759291 <6>[ 2.036462] 9pnet: Installing 9P2000 support
10555 16:45:10.762684 <5>[ 2.041049] Key type dns_resolver registered
10556 16:45:10.765449 <6>[ 2.046229] registered taskstats version 1
10557 16:45:10.772318 <5>[ 2.050663] Loading compiled-in X.509 certificates
10558 16:45:10.807225 <4>[ 2.079255] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10559 16:45:10.817161 <4>[ 2.089953] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10560 16:45:10.827189 <3>[ 2.102508] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10561 16:45:10.839091 <6>[ 2.117939] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10562 16:45:10.846512 <6>[ 2.124696] xhci-mtk 11200000.usb: xHCI Host Controller
10563 16:45:10.852441 <6>[ 2.130196] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10564 16:45:10.862920 <6>[ 2.138044] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10565 16:45:10.869833 <6>[ 2.147481] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10566 16:45:10.876202 <6>[ 2.153577] xhci-mtk 11200000.usb: xHCI Host Controller
10567 16:45:10.882633 <6>[ 2.159224] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10568 16:45:10.889145 <6>[ 2.166922] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10569 16:45:10.896172 <6>[ 2.174836] hub 1-0:1.0: USB hub found
10570 16:45:10.899946 <6>[ 2.178878] hub 1-0:1.0: 1 port detected
10571 16:45:10.909498 <6>[ 2.183232] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10572 16:45:10.912559 <6>[ 2.192040] hub 2-0:1.0: USB hub found
10573 16:45:10.916267 <6>[ 2.196082] hub 2-0:1.0: 1 port detected
10574 16:45:10.924473 <6>[ 2.203259] mtk-msdc 11f70000.mmc: Got CD GPIO
10575 16:45:10.941965 <6>[ 2.217219] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10576 16:45:10.949307 <6>[ 2.225253] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10577 16:45:10.958544 <4>[ 2.233240] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10578 16:45:10.968389 <6>[ 2.242895] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10579 16:45:10.974836 <6>[ 2.250977] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10580 16:45:10.981149 <6>[ 2.259003] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10581 16:45:10.991689 <6>[ 2.266920] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10582 16:45:10.998220 <6>[ 2.274741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10583 16:45:11.007858 <6>[ 2.282563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10584 16:45:11.018221 <6>[ 2.293264] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10585 16:45:11.024861 <6>[ 2.301637] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10586 16:45:11.034984 <6>[ 2.309995] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10587 16:45:11.044266 <6>[ 2.318338] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10588 16:45:11.052137 <6>[ 2.326682] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10589 16:45:11.061196 <6>[ 2.335025] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10590 16:45:11.067612 <6>[ 2.343368] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10591 16:45:11.077513 <6>[ 2.351711] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10592 16:45:11.084086 <6>[ 2.360054] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10593 16:45:11.094512 <6>[ 2.368398] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10594 16:45:11.100394 <6>[ 2.376741] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10595 16:45:11.110753 <6>[ 2.385084] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10596 16:45:11.116991 <6>[ 2.393431] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10597 16:45:11.127215 <6>[ 2.401775] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10598 16:45:11.133786 <6>[ 2.410121] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10599 16:45:11.140049 <6>[ 2.419044] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10600 16:45:11.147749 <6>[ 2.426474] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10601 16:45:11.154686 <6>[ 2.433523] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10602 16:45:11.165646 <6>[ 2.440621] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10603 16:45:11.171866 <6>[ 2.447909] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10604 16:45:11.181229 <6>[ 2.454751] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10605 16:45:11.187883 <6>[ 2.463889] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10606 16:45:11.197941 <6>[ 2.473015] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10607 16:45:11.208422 <6>[ 2.482318] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10608 16:45:11.218433 <6>[ 2.491797] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10609 16:45:11.227737 <6>[ 2.501295] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10610 16:45:11.237704 <6>[ 2.510422] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10611 16:45:11.244253 <6>[ 2.519895] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10612 16:45:11.254232 <6>[ 2.529022] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10613 16:45:11.264343 <6>[ 2.538323] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10614 16:45:11.274281 <6>[ 2.548488] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10615 16:45:11.284313 <6>[ 2.559909] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10616 16:45:11.307140 <6>[ 2.582860] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10617 16:45:11.335046 <6>[ 2.613436] hub 2-1:1.0: USB hub found
10618 16:45:11.337758 <6>[ 2.617838] hub 2-1:1.0: 3 ports detected
10619 16:45:11.458884 <6>[ 2.734881] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10620 16:45:11.613832 <6>[ 2.892580] hub 1-1:1.0: USB hub found
10621 16:45:11.617235 <6>[ 2.897007] hub 1-1:1.0: 4 ports detected
10622 16:45:11.695641 <6>[ 2.971133] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10623 16:45:11.938890 <6>[ 3.214894] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10624 16:45:12.072446 <6>[ 3.351158] hub 1-1.4:1.0: USB hub found
10625 16:45:12.075565 <6>[ 3.355814] hub 1-1.4:1.0: 2 ports detected
10626 16:45:12.375094 <6>[ 3.650886] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10627 16:45:12.567433 <6>[ 3.842885] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10628 16:45:23.575672 <6>[ 14.859476] ALSA device list:
10629 16:45:23.582388 <6>[ 14.862730] No soundcards found.
10630 16:45:23.595549 <6>[ 14.874996] Freeing unused kernel memory: 8384K
10631 16:45:23.597856 <6>[ 14.879904] Run /init as init process
10632 16:45:23.623659 Starting syslogd: OK
10633 16:45:23.627754 Starting klogd: OK
10634 16:45:23.636700 Running sysctl: OK
10635 16:45:23.643617 Populating /dev using udev: <30>[ 14.925095] udevd[186]: starting version 3.2.9
10636 16:45:23.652614 <27>[ 14.933012] udevd[186]: specified user 'tss' unknown
10637 16:45:23.659166 <27>[ 14.938382] udevd[186]: specified group 'tss' unknown
10638 16:45:23.663043 <30>[ 14.944883] udevd[187]: starting eudev-3.2.9
10639 16:45:23.694878 <27>[ 14.975017] udevd[187]: specified user 'tss' unknown
10640 16:45:23.701299 <27>[ 14.980407] udevd[187]: specified group 'tss' unknown
10641 16:45:23.892454 <6>[ 15.169130] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10642 16:45:23.900162 <6>[ 15.180390] remoteproc remoteproc0: scp is available
10643 16:45:23.910260 <4>[ 15.186528] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10644 16:45:23.916514 <6>[ 15.196405] remoteproc remoteproc0: powering up scp
10645 16:45:23.923191 <6>[ 15.197306] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10646 16:45:23.933123 <4>[ 15.206695] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10647 16:45:23.943148 <6>[ 15.209177] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10648 16:45:23.950289 <3>[ 15.218974] remoteproc remoteproc0: request_firmware failed: -2
10649 16:45:23.956482 <6>[ 15.227661] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10650 16:45:23.962871 <6>[ 15.243018] mc: Linux media interface: v0.10
10651 16:45:23.973508 <4>[ 15.250665] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10652 16:45:23.979899 <4>[ 15.258780] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10653 16:45:23.990873 <3>[ 15.267286] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 16:45:23.996708 <6>[ 15.269162] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10655 16:45:24.006912 <3>[ 15.275496] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 16:45:24.010232 <6>[ 15.283799] usbcore: registered new interface driver r8152
10657 16:45:24.020966 <3>[ 15.291415] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10658 16:45:24.029914 <3>[ 15.305669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10659 16:45:24.036794 <3>[ 15.314563] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10660 16:45:24.047020 <3>[ 15.323181] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10661 16:45:24.060403 <3>[ 15.336902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10662 16:45:24.069992 <4>[ 15.338420] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10663 16:45:24.073291 <4>[ 15.338420] Fallback method does not support PEC.
10664 16:45:24.083832 <3>[ 15.345294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 16:45:24.086465 <6>[ 15.359561] videodev: Linux video capture interface: v2.00
10666 16:45:24.093013 <6>[ 15.364242] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10667 16:45:24.100120 <6>[ 15.364250] pci_bus 0000:00: root bus resource [bus 00-ff]
10668 16:45:24.106615 <6>[ 15.364256] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10669 16:45:24.116329 <6>[ 15.364266] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10670 16:45:24.123342 <6>[ 15.364299] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10671 16:45:24.129747 <6>[ 15.364318] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10672 16:45:24.136894 <6>[ 15.364485] pci 0000:00:00.0: supports D1 D2
10673 16:45:24.143266 <6>[ 15.364490] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10674 16:45:24.150385 <3>[ 15.367066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 16:45:24.159637 <6>[ 15.367134] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10676 16:45:24.166573 <6>[ 15.367399] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10677 16:45:24.172742 <6>[ 15.367436] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10678 16:45:24.179017 <6>[ 15.367490] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10679 16:45:24.185861 <6>[ 15.367513] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10680 16:45:24.192601 <6>[ 15.367716] pci 0000:01:00.0: supports D1 D2
10681 16:45:24.199108 <6>[ 15.367721] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10682 16:45:24.208825 <3>[ 15.375709] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10683 16:45:24.215442 <6>[ 15.378731] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10684 16:45:24.222903 <6>[ 15.378834] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10685 16:45:24.229120 <6>[ 15.378847] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10686 16:45:24.238883 <6>[ 15.378867] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10687 16:45:24.245522 <6>[ 15.378883] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10688 16:45:24.255225 <6>[ 15.378899] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10689 16:45:24.259013 <6>[ 15.378915] pci 0000:00:00.0: PCI bridge to [bus 01]
10690 16:45:24.268490 <6>[ 15.378924] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10691 16:45:24.274822 <6>[ 15.379646] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10692 16:45:24.281511 <3>[ 15.379732] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 16:45:24.287917 <6>[ 15.382626] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10694 16:45:24.294725 <6>[ 15.383822] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10695 16:45:24.301568 <3>[ 15.387072] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10696 16:45:24.307998 <3>[ 15.392553] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 16:45:24.318798 <6>[ 15.401073] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10698 16:45:24.327828 <6>[ 15.401755] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10699 16:45:24.334506 <6>[ 15.402963] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10700 16:45:24.344350 <3>[ 15.408715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10701 16:45:24.351417 <3>[ 15.410029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 16:45:24.361169 <4>[ 15.442020] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10703 16:45:24.367833 <3>[ 15.443965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 16:45:24.377741 <4>[ 15.450178] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10705 16:45:24.384144 <3>[ 15.457641] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10706 16:45:24.390886 <3>[ 15.511182] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10707 16:45:24.400651 <3>[ 15.515682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10708 16:45:24.403716 <6>[ 15.522827] r8152 2-1.3:1.0 eth0: v1.12.13
10709 16:45:24.410235 <3>[ 15.623253] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10710 16:45:24.417339 <3>[ 15.628103] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 16:45:24.423711 <3>[ 15.637581] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10712 16:45:24.433351 <3>[ 15.645924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 16:45:24.440278 <3>[ 15.645976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 16:45:24.450121 <6>[ 15.654145] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10715 16:45:24.466007 <6>[ 15.746128] usbcore: registered new interface driver cdc_ether
10716 16:45:24.475648 <6>[ 15.756062] usbcore: registered new interface driver r8153_ecm
10717 16:45:24.488506 <5>[ 15.765474] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10718 16:45:24.491769 <6>[ 15.765518] Bluetooth: Core ver 2.22
10719 16:45:24.498266 <6>[ 15.766475] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10720 16:45:24.511441 <6>[ 15.767855] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10721 16:45:24.518578 <6>[ 15.768045] usbcore: registered new interface driver uvcvideo
10722 16:45:24.524780 <6>[ 15.785362] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10723 16:45:24.528162 <6>[ 15.796908] NET: Registered PF_BLUETOOTH protocol family
10724 16:45:24.538489 <5>[ 15.798110] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10725 16:45:24.544718 <4>[ 15.798181] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10726 16:45:24.551223 <6>[ 15.798190] cfg80211: failed to load regulatory.db
10727 16:45:24.555868 <6>[ 15.813417] remoteproc remoteproc0: powering up scp
10728 16:45:24.561102 <6>[ 15.815056] Bluetooth: HCI device and connection manager initialized
10729 16:45:24.571107 <4>[ 15.821774] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10730 16:45:24.577486 <6>[ 15.830665] Bluetooth: HCI socket layer initialized
10731 16:45:24.581371 <6>[ 15.830680] Bluetooth: L2CAP socket layer initialized
10732 16:45:24.587416 <6>[ 15.830713] Bluetooth: SCO socket layer initialized
10733 16:45:24.594634 <3>[ 15.872979] remoteproc remoteproc0: request_firmware failed: -2
10734 16:45:24.601007 <3>[ 15.879458] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10735 16:45:24.606974 <6>[ 15.880843] usbcore: registered new interface driver btusb
10736 16:45:24.617479 <4>[ 15.881741] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10737 16:45:24.623746 <3>[ 15.881756] Bluetooth: hci0: Failed to load firmware file (-2)
10738 16:45:24.630796 <3>[ 15.881760] Bluetooth: hci0: Failed to set up firmware (-2)
10739 16:45:24.640503 <4>[ 15.881763] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10740 16:45:24.646997 <6>[ 15.901349] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10741 16:45:24.653743 <6>[ 15.933309] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10742 16:45:24.679020 <6>[ 15.958902] mt7921e 0000:01:00.0: ASIC revision: 79610010
10743 16:45:24.784865 <4>[ 16.058546] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10744 16:45:24.785452 done
10745 16:45:24.805104 Saving random seed: OK
10746 16:45:24.820859 Starting network: OK
10747 16:45:24.861165 Starting dropbear sshd: <6>[ 16.141732] NET: Registered PF_INET6 protocol family
10748 16:45:24.868351 <6>[ 16.148513] Segment Routing with IPv6
10749 16:45:24.871353 <6>[ 16.152506] In-situ OAM (IOAM) with IPv6
10750 16:45:24.874656 OK
10751 16:45:24.885908 /bin/sh: can't access tty; job control turned off
10752 16:45:24.887101 Matched prompt #10: / #
10754 16:45:24.888218 Setting prompt string to ['/ #']
10755 16:45:24.888691 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10757 16:45:24.889773 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10758 16:45:24.890249 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
10759 16:45:24.890696 Setting prompt string to ['/ #']
10760 16:45:24.891050 Forcing a shell prompt, looking for ['/ #']
10762 16:45:24.941915 / #
10763 16:45:24.942620 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10764 16:45:24.943065 Waiting using forced prompt support (timeout 00:02:30)
10765 16:45:24.943581 <4>[ 16.181420] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 16:45:24.948829
10767 16:45:24.949770 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10768 16:45:24.950317 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
10769 16:45:24.950867 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10770 16:45:24.951343 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
10771 16:45:24.951820 end: 2 depthcharge-action (duration 00:01:17) [common]
10772 16:45:24.952288 start: 3 lava-test-retry (timeout 00:01:00) [common]
10773 16:45:24.952768 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10774 16:45:24.953210 Using namespace: common
10776 16:45:25.054517 / # #
10777 16:45:25.055177 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10778 16:45:25.055760 #<4>[ 16.301454] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 16:45:25.060880
10780 16:45:25.061752 Using /lava-10576340
10782 16:45:25.163099 / # export SHELL=/bin/sh
10783 16:45:25.163937 export SHELL=/bin/sh<4>[ 16.421096] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 16:45:25.170215
10786 16:45:25.271907 / # . /lava-10576340/environment
10787 16:45:25.272701 . /lava-10576340/environment<4>[ 16.541175] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 16:45:25.278998
10790 16:45:25.380716 / # /lava-10576340/bin/lava-test-runner /lava-10576340/0
10791 16:45:25.381350 Test shell timeout: 10s (minimum of the action and connection timeout)
10792 16:45:25.430917 /lava-10576340/bin/lava-test-runner /lava-10576340/0<4>[ 16.661023] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10793 16:45:25.431504
10794 16:45:25.431884 + export 'TESTRUN_ID=0_dmesg'
10795 16:45:25.432238 +<8>[ 16.701700] <LAVA_SIGNAL_STARTRUN 0_dmesg 10576340_1.5.2.3.1>
10796 16:45:25.432586 cd /lava-10576340/0/tests/0_dmesg
10797 16:45:25.432916 + cat uuid
10798 16:45:25.433243 + UUID=10576340_1.5.2.3.1
10799 16:45:25.433565 + set +x
10800 16:45:25.434150 Received signal: <STARTRUN> 0_dmesg 10576340_1.5.2.3.1
10801 16:45:25.434558 Starting test lava.0_dmesg (10576340_1.5.2.3.1)
10802 16:45:25.434981 Skipping test definition patterns.
10803 16:45:25.435544 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10804 16:45:25.442729 <8>[ 16.721038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10805 16:45:25.443579 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10807 16:45:25.464156 <8>[ 16.741121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10808 16:45:25.464996 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10810 16:45:25.485283 <8>[ 16.761708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10811 16:45:25.486130 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10813 16:45:25.488637 + set +x
10814 16:45:25.492675 Received signal: <ENDRUN> 0_dmesg 10576340_1.5.2.3.1
10815 16:45:25.493198 Ending use of test pattern.
10816 16:45:25.493561 Ending test lava.0_dmesg (10576340_1.5.2.3.1), duration 0.06
10818 16:45:25.495293 <8>[ 16.772765] <LAVA_SIGNAL_ENDRUN 0_dmesg 10576340_1.5.2.3.1>
10819 16:45:25.508583 <LAVA_TEST_RUNNE<4>[ 16.781501] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 16:45:25.509159 R EXIT>
10821 16:45:25.627206 / # <4>[ 16.901211] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10822 16:45:25.747254 <4>[ 17.021235] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 16:45:25.867750 <4>[ 17.141213] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 16:45:25.978475 <3>[ 17.259065] mt7921e 0000:01:00.0: hardware init failed
10825 16:45:54.867980 <6>[ 46.154949] vpu: disabling
10826 16:45:54.870780 <6>[ 46.158005] vproc2: disabling
10827 16:45:54.874230 <6>[ 46.161285] vproc1: disabling
10828 16:45:54.877983 <6>[ 46.164546] vaud18: disabling
10829 16:45:54.883935 <6>[ 46.167960] vsram_others: disabling
10830 16:45:54.887044 <6>[ 46.171830] va09: disabling
10831 16:45:54.890536 <6>[ 46.174938] vsram_md: disabling
10832 16:45:54.893543 <6>[ 46.178422] Vgpu: disabling
10834 16:46:24.953760 end: 3.1 lava-test-shell (duration 00:01:00) [common]
10836 16:46:24.954853 lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10838 16:46:24.955909 end: 3 lava-test-retry (duration 00:01:00) [common]
10840 16:46:24.957197 Cleaning after the job
10841 16:46:24.957666 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/ramdisk
10842 16:46:24.960932 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/kernel
10843 16:46:24.969998 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/dtb
10844 16:46:24.970212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576340/tftp-deploy-enr8th00/modules
10845 16:46:24.975638 start: 5.1 power-off (timeout 00:00:30) [common]
10846 16:46:24.975820 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
10847 16:46:25.056018 >> Command sent successfully.
10848 16:46:25.067553 Returned 0 in 0 seconds
10849 16:46:25.168819 end: 5.1 power-off (duration 00:00:00) [common]
10851 16:46:25.170394 start: 5.2 read-feedback (timeout 00:10:00) [common]
10852 16:46:25.171644 Listened to connection for namespace 'common' for up to 1s
10853 16:46:26.172291 Finalising connection for namespace 'common'
10854 16:46:26.172969 Disconnecting from shell: Finalise
10855 16:46:26.274136 end: 5.2 read-feedback (duration 00:00:01) [common]
10856 16:46:26.274787 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576340
10857 16:46:26.354127 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576340
10858 16:46:26.354315 TestError: A test failed to run, look at the error message.