Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 16:43:05.547370 lava-dispatcher, installed at version: 2023.03
2 16:43:05.547595 start: 0 validate
3 16:43:05.547749 Start time: 2023-06-03 16:43:05.547741+00:00 (UTC)
4 16:43:05.547872 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:43:05.548000 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 16:43:05.841641 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:43:05.841828 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:43:17.664550 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:43:17.664773 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:43:17.950673 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:43:17.950895 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:43:18.241150 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:43:18.241367 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:43:23.242389 validate duration: 17.69
16 16:43:23.242657 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:43:23.242755 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:43:23.242841 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:43:23.242961 Not decompressing ramdisk as can be used compressed.
20 16:43:23.243047 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/initrd.cpio.gz
21 16:43:23.243111 saving as /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/ramdisk/initrd.cpio.gz
22 16:43:23.243172 total size: 4665395 (4MB)
23 16:43:23.244341 progress 0% (0MB)
24 16:43:23.245767 progress 5% (0MB)
25 16:43:23.247006 progress 10% (0MB)
26 16:43:23.248262 progress 15% (0MB)
27 16:43:23.249496 progress 20% (0MB)
28 16:43:23.250725 progress 25% (1MB)
29 16:43:23.251981 progress 30% (1MB)
30 16:43:23.253197 progress 35% (1MB)
31 16:43:23.254402 progress 40% (1MB)
32 16:43:23.255783 progress 45% (2MB)
33 16:43:23.256996 progress 50% (2MB)
34 16:43:23.258202 progress 55% (2MB)
35 16:43:23.259405 progress 60% (2MB)
36 16:43:23.260671 progress 65% (2MB)
37 16:43:23.261885 progress 70% (3MB)
38 16:43:23.263090 progress 75% (3MB)
39 16:43:23.264330 progress 80% (3MB)
40 16:43:23.265701 progress 85% (3MB)
41 16:43:23.266959 progress 90% (4MB)
42 16:43:23.268230 progress 95% (4MB)
43 16:43:23.269455 progress 100% (4MB)
44 16:43:23.269610 4MB downloaded in 0.03s (168.31MB/s)
45 16:43:23.269757 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:43:23.270009 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:43:23.270098 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:43:23.270184 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:43:23.270313 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:43:23.270386 saving as /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/kernel/Image
52 16:43:23.270449 total size: 45746688 (43MB)
53 16:43:23.270511 No compression specified
54 16:43:23.271683 progress 0% (0MB)
55 16:43:23.283189 progress 5% (2MB)
56 16:43:23.295167 progress 10% (4MB)
57 16:43:23.307119 progress 15% (6MB)
58 16:43:23.318861 progress 20% (8MB)
59 16:43:23.330665 progress 25% (10MB)
60 16:43:23.342457 progress 30% (13MB)
61 16:43:23.354397 progress 35% (15MB)
62 16:43:23.366731 progress 40% (17MB)
63 16:43:23.378500 progress 45% (19MB)
64 16:43:23.390227 progress 50% (21MB)
65 16:43:23.401881 progress 55% (24MB)
66 16:43:23.413899 progress 60% (26MB)
67 16:43:23.426002 progress 65% (28MB)
68 16:43:23.438169 progress 70% (30MB)
69 16:43:23.450290 progress 75% (32MB)
70 16:43:23.462083 progress 80% (34MB)
71 16:43:23.474074 progress 85% (37MB)
72 16:43:23.486025 progress 90% (39MB)
73 16:43:23.497799 progress 95% (41MB)
74 16:43:23.509878 progress 100% (43MB)
75 16:43:23.510095 43MB downloaded in 0.24s (182.07MB/s)
76 16:43:23.510292 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:43:23.510538 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:43:23.510628 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:43:23.510761 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:43:23.510899 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:43:23.510974 saving as /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/dtb/mt8192-asurada-spherion-r0.dtb
83 16:43:23.511039 total size: 46924 (0MB)
84 16:43:23.511102 No compression specified
85 16:43:23.512342 progress 69% (0MB)
86 16:43:23.512617 progress 100% (0MB)
87 16:43:23.512772 0MB downloaded in 0.00s (25.86MB/s)
88 16:43:23.512895 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:43:23.513143 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:43:23.513233 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:43:23.513317 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:43:23.513433 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230527.0/arm64/full.rootfs.tar.xz
94 16:43:23.513503 saving as /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/nfsrootfs/full.rootfs.tar
95 16:43:23.513566 total size: 125267308 (119MB)
96 16:43:23.513628 Using unxz to decompress xz
97 16:43:23.517486 progress 0% (0MB)
98 16:43:23.842272 progress 5% (6MB)
99 16:43:24.173631 progress 10% (11MB)
100 16:43:24.500641 progress 15% (17MB)
101 16:43:24.684549 progress 20% (23MB)
102 16:43:24.866599 progress 25% (29MB)
103 16:43:25.224404 progress 30% (35MB)
104 16:43:25.648594 progress 35% (41MB)
105 16:43:26.033993 progress 40% (47MB)
106 16:43:26.422671 progress 45% (53MB)
107 16:43:27.097764 progress 50% (59MB)
108 16:43:27.502746 progress 55% (65MB)
109 16:43:27.905506 progress 60% (71MB)
110 16:43:28.283432 progress 65% (77MB)
111 16:43:28.690460 progress 70% (83MB)
112 16:43:29.119387 progress 75% (89MB)
113 16:43:29.574020 progress 80% (95MB)
114 16:43:30.021455 progress 85% (101MB)
115 16:43:30.279250 progress 90% (107MB)
116 16:43:30.648925 progress 95% (113MB)
117 16:43:31.040376 progress 100% (119MB)
118 16:43:31.046669 119MB downloaded in 7.53s (15.86MB/s)
119 16:43:31.047096 end: 1.4.1 http-download (duration 00:00:08) [common]
121 16:43:31.047529 end: 1.4 download-retry (duration 00:00:08) [common]
122 16:43:31.047682 start: 1.5 download-retry (timeout 00:09:52) [common]
123 16:43:31.047827 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 16:43:31.048040 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:43:31.048159 saving as /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/modules/modules.tar
126 16:43:31.048267 total size: 8545664 (8MB)
127 16:43:31.048382 Using unxz to decompress xz
128 16:43:31.053109 progress 0% (0MB)
129 16:43:31.075384 progress 5% (0MB)
130 16:43:31.100977 progress 10% (0MB)
131 16:43:31.128177 progress 15% (1MB)
132 16:43:31.154080 progress 20% (1MB)
133 16:43:31.181137 progress 25% (2MB)
134 16:43:31.207946 progress 30% (2MB)
135 16:43:31.235005 progress 35% (2MB)
136 16:43:31.261858 progress 40% (3MB)
137 16:43:31.287874 progress 45% (3MB)
138 16:43:31.312661 progress 50% (4MB)
139 16:43:31.337021 progress 55% (4MB)
140 16:43:31.362384 progress 60% (4MB)
141 16:43:31.387956 progress 65% (5MB)
142 16:43:31.416210 progress 70% (5MB)
143 16:43:31.445935 progress 75% (6MB)
144 16:43:31.476531 progress 80% (6MB)
145 16:43:31.499784 progress 85% (6MB)
146 16:43:31.525699 progress 90% (7MB)
147 16:43:31.549846 progress 95% (7MB)
148 16:43:31.575865 progress 100% (8MB)
149 16:43:31.582104 8MB downloaded in 0.53s (15.27MB/s)
150 16:43:31.582425 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:43:31.582706 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:43:31.582803 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 16:43:31.582970 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 16:43:33.769049 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu
156 16:43:33.769303 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 16:43:33.769452 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 16:43:33.769689 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl
159 16:43:33.769860 makedir: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin
160 16:43:33.770009 makedir: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/tests
161 16:43:33.770147 makedir: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/results
162 16:43:33.770296 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-add-keys
163 16:43:33.770485 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-add-sources
164 16:43:33.770647 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-background-process-start
165 16:43:33.770813 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-background-process-stop
166 16:43:33.770958 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-common-functions
167 16:43:33.771126 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-echo-ipv4
168 16:43:33.771286 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-install-packages
169 16:43:33.771446 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-installed-packages
170 16:43:33.771836 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-os-build
171 16:43:33.772009 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-probe-channel
172 16:43:33.772175 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-probe-ip
173 16:43:33.772351 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-target-ip
174 16:43:33.772529 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-target-mac
175 16:43:33.772691 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-target-storage
176 16:43:33.772868 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-case
177 16:43:33.773036 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-event
178 16:43:33.773202 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-feedback
179 16:43:33.773369 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-raise
180 16:43:33.773531 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-reference
181 16:43:33.773705 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-runner
182 16:43:33.773876 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-set
183 16:43:33.774059 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-test-shell
184 16:43:33.774225 Updating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-install-packages (oe)
185 16:43:33.774413 Updating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/bin/lava-installed-packages (oe)
186 16:43:33.774567 Creating /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/environment
187 16:43:33.774700 LAVA metadata
188 16:43:33.774804 - LAVA_JOB_ID=10576281
189 16:43:33.774902 - LAVA_DISPATCHER_IP=192.168.201.1
190 16:43:33.775057 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
191 16:43:33.775157 skipped lava-vland-overlay
192 16:43:33.775270 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 16:43:33.775385 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
194 16:43:33.775477 skipped lava-multinode-overlay
195 16:43:33.775596 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 16:43:33.775712 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
197 16:43:33.775823 Loading test definitions
198 16:43:33.775956 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
199 16:43:33.776060 Using /lava-10576281 at stage 0
200 16:43:33.776496 uuid=10576281_1.6.2.3.1 testdef=None
201 16:43:33.776620 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 16:43:33.776739 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
203 16:43:33.777481 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 16:43:33.777845 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
206 16:43:33.778796 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 16:43:33.779183 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
209 16:43:33.779968 runner path: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/0/tests/0_dmesg test_uuid 10576281_1.6.2.3.1
210 16:43:33.780127 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 16:43:33.780360 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:49) [common]
213 16:43:33.780436 Using /lava-10576281 at stage 1
214 16:43:33.780739 uuid=10576281_1.6.2.3.5 testdef=None
215 16:43:33.780830 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 16:43:33.780917 start: 1.6.2.3.6 test-overlay (timeout 00:09:49) [common]
217 16:43:33.781385 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 16:43:33.781606 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:49) [common]
220 16:43:33.782260 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 16:43:33.782496 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:49) [common]
223 16:43:33.783119 runner path: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/1/tests/1_bootrr test_uuid 10576281_1.6.2.3.5
224 16:43:33.783271 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 16:43:33.783483 Creating lava-test-runner.conf files
227 16:43:33.783546 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/0 for stage 0
228 16:43:33.783896 - 0_dmesg
229 16:43:33.783981 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576281/lava-overlay-f40c86gl/lava-10576281/1 for stage 1
230 16:43:33.784074 - 1_bootrr
231 16:43:33.784188 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 16:43:33.784282 start: 1.6.2.4 compress-overlay (timeout 00:09:49) [common]
233 16:43:33.791914 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 16:43:33.792081 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:49) [common]
235 16:43:33.792185 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 16:43:33.792276 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 16:43:33.792362 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:49) [common]
238 16:43:33.910910 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 16:43:33.911295 start: 1.6.4 extract-modules (timeout 00:09:49) [common]
240 16:43:33.911419 extracting modules file /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu
241 16:43:34.126712 extracting modules file /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576281/extract-overlay-ramdisk-gl0u4y58/ramdisk
242 16:43:34.340987 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 16:43:34.341174 start: 1.6.5 apply-overlay-tftp (timeout 00:09:49) [common]
244 16:43:34.341283 [common] Applying overlay to NFS
245 16:43:34.341361 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576281/compress-overlay-h8wv6my9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu
246 16:43:34.349349 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 16:43:34.349514 start: 1.6.6 configure-preseed-file (timeout 00:09:49) [common]
248 16:43:34.349620 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 16:43:34.349714 start: 1.6.7 compress-ramdisk (timeout 00:09:49) [common]
250 16:43:34.349804 Building ramdisk /var/lib/lava/dispatcher/tmp/10576281/extract-overlay-ramdisk-gl0u4y58/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576281/extract-overlay-ramdisk-gl0u4y58/ramdisk
251 16:43:34.666345 >> 117799 blocks
252 16:43:36.645959 rename /var/lib/lava/dispatcher/tmp/10576281/extract-overlay-ramdisk-gl0u4y58/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/ramdisk/ramdisk.cpio.gz
253 16:43:36.646507 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 16:43:36.646689 start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
255 16:43:36.646838 start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
256 16:43:36.646993 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/kernel/Image'
257 16:43:49.650850 Returned 0 in 13 seconds
258 16:43:49.751532 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/kernel/image.itb
259 16:43:50.070956 output: FIT description: Kernel Image image with one or more FDT blobs
260 16:43:50.071373 output: Created: Sat Jun 3 17:43:50 2023
261 16:43:50.071489 output: Image 0 (kernel-1)
262 16:43:50.071603 output: Description:
263 16:43:50.071704 output: Created: Sat Jun 3 17:43:50 2023
264 16:43:50.071803 output: Type: Kernel Image
265 16:43:50.071870 output: Compression: lzma compressed
266 16:43:50.071933 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
267 16:43:50.071996 output: Architecture: AArch64
268 16:43:50.072082 output: OS: Linux
269 16:43:50.072149 output: Load Address: 0x00000000
270 16:43:50.072217 output: Entry Point: 0x00000000
271 16:43:50.072281 output: Hash algo: crc32
272 16:43:50.072341 output: Hash value: b48eba69
273 16:43:50.072399 output: Image 1 (fdt-1)
274 16:43:50.072456 output: Description: mt8192-asurada-spherion-r0
275 16:43:50.072513 output: Created: Sat Jun 3 17:43:50 2023
276 16:43:50.072570 output: Type: Flat Device Tree
277 16:43:50.072626 output: Compression: uncompressed
278 16:43:50.072682 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
279 16:43:50.072739 output: Architecture: AArch64
280 16:43:50.072795 output: Hash algo: crc32
281 16:43:50.072850 output: Hash value: 1df858fa
282 16:43:50.072906 output: Image 2 (ramdisk-1)
283 16:43:50.072969 output: Description: unavailable
284 16:43:50.073026 output: Created: Sat Jun 3 17:43:50 2023
285 16:43:50.073088 output: Type: RAMDisk Image
286 16:43:50.073145 output: Compression: Unknown Compression
287 16:43:50.073202 output: Data Size: 17643100 Bytes = 17229.59 KiB = 16.83 MiB
288 16:43:50.073258 output: Architecture: AArch64
289 16:43:50.073314 output: OS: Linux
290 16:43:50.073392 output: Load Address: unavailable
291 16:43:50.073479 output: Entry Point: unavailable
292 16:43:50.073565 output: Hash algo: crc32
293 16:43:50.073651 output: Hash value: 64c1b1f3
294 16:43:50.073738 output: Default Configuration: 'conf-1'
295 16:43:50.073824 output: Configuration 0 (conf-1)
296 16:43:50.073910 output: Description: mt8192-asurada-spherion-r0
297 16:43:50.073996 output: Kernel: kernel-1
298 16:43:50.074082 output: Init Ramdisk: ramdisk-1
299 16:43:50.074171 output: FDT: fdt-1
300 16:43:50.074258 output: Loadables: kernel-1
301 16:43:50.074348 output:
302 16:43:50.074591 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
303 16:43:50.074722 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
304 16:43:50.074863 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
305 16:43:50.074995 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:33) [common]
306 16:43:50.075110 No LXC device requested
307 16:43:50.075225 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
308 16:43:50.075344 start: 1.8 deploy-device-env (timeout 00:09:33) [common]
309 16:43:50.075460 end: 1.8 deploy-device-env (duration 00:00:00) [common]
310 16:43:50.075562 Checking files for TFTP limit of 4294967296 bytes.
311 16:43:50.076109 end: 1 tftp-deploy (duration 00:00:27) [common]
312 16:43:50.076216 start: 2 depthcharge-action (timeout 00:05:00) [common]
313 16:43:50.076314 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
314 16:43:50.076443 substitutions:
315 16:43:50.076513 - {DTB}: 10576281/tftp-deploy-522scxlt/dtb/mt8192-asurada-spherion-r0.dtb
316 16:43:50.076583 - {INITRD}: 10576281/tftp-deploy-522scxlt/ramdisk/ramdisk.cpio.gz
317 16:43:50.076646 - {KERNEL}: 10576281/tftp-deploy-522scxlt/kernel/Image
318 16:43:50.076707 - {LAVA_MAC}: None
319 16:43:50.076766 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu
320 16:43:50.076830 - {NFS_SERVER_IP}: 192.168.201.1
321 16:43:50.076891 - {PRESEED_CONFIG}: None
322 16:43:50.076949 - {PRESEED_LOCAL}: None
323 16:43:50.077006 - {RAMDISK}: 10576281/tftp-deploy-522scxlt/ramdisk/ramdisk.cpio.gz
324 16:43:50.077063 - {ROOT_PART}: None
325 16:43:50.077128 - {ROOT}: None
326 16:43:50.077185 - {SERVER_IP}: 192.168.201.1
327 16:43:50.077242 - {TEE}: None
328 16:43:50.077297 Parsed boot commands:
329 16:43:50.077353 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
330 16:43:50.077532 Parsed boot commands: tftpboot 192.168.201.1 10576281/tftp-deploy-522scxlt/kernel/image.itb 10576281/tftp-deploy-522scxlt/kernel/cmdline
331 16:43:50.077624 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
332 16:43:50.077714 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
333 16:43:50.077810 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
334 16:43:50.077908 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
335 16:43:50.077982 Not connected, no need to disconnect.
336 16:43:50.078059 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
337 16:43:50.078149 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
338 16:43:50.078249 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
339 16:43:50.081955 Setting prompt string to ['lava-test: # ']
340 16:43:50.082364 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
341 16:43:50.082512 end: 2.2.1 reset-connection (duration 00:00:00) [common]
342 16:43:50.082647 start: 2.2.2 reset-device (timeout 00:05:00) [common]
343 16:43:50.082777 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
344 16:43:50.082989 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
345 16:43:55.222584 >> Command sent successfully.
346 16:43:55.225474 Returned 0 in 5 seconds
347 16:43:55.325853 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
349 16:43:55.326317 end: 2.2.2 reset-device (duration 00:00:05) [common]
350 16:43:55.326451 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
351 16:43:55.326579 Setting prompt string to 'Starting depthcharge on Spherion...'
352 16:43:55.326682 Changing prompt to 'Starting depthcharge on Spherion...'
353 16:43:55.326783 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
354 16:43:55.327164 [Enter `^Ec?' for help]
355 16:43:55.498301
356 16:43:55.498810
357 16:43:55.499162 F0: 102B 0000
358 16:43:55.499473
359 16:43:55.499818 F3: 1001 0000 [0200]
360 16:43:55.501682
361 16:43:55.502080 F3: 1001 0000
362 16:43:55.502404
363 16:43:55.502700 F7: 102D 0000
364 16:43:55.502988
365 16:43:55.505141 F1: 0000 0000
366 16:43:55.505546
367 16:43:55.505867 V0: 0000 0000 [0001]
368 16:43:55.506176
369 16:43:55.508375 00: 0007 8000
370 16:43:55.508790
371 16:43:55.509140 01: 0000 0000
372 16:43:55.509481
373 16:43:55.511454 BP: 0C00 0209 [0000]
374 16:43:55.511899
375 16:43:55.512219 G0: 1182 0000
376 16:43:55.512519
377 16:43:55.515557 EC: 0000 0021 [4000]
378 16:43:55.516021
379 16:43:55.516389 S7: 0000 0000 [0000]
380 16:43:55.516731
381 16:43:55.518983 CC: 0000 0000 [0001]
382 16:43:55.519385
383 16:43:55.519745 T0: 0000 0040 [010F]
384 16:43:55.520052
385 16:43:55.520350 Jump to BL
386 16:43:55.522444
387 16:43:55.545984
388 16:43:55.546408
389 16:43:55.546738
390 16:43:55.552692 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
391 16:43:55.556351 ARM64: Exception handlers installed.
392 16:43:55.559522 ARM64: Testing exception
393 16:43:55.562921 ARM64: Done test exception
394 16:43:55.569418 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
395 16:43:55.579227 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
396 16:43:55.585998 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
397 16:43:55.595789 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
398 16:43:55.602205 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
399 16:43:55.612602 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
400 16:43:55.623596 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
401 16:43:55.630115 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
402 16:43:55.648158 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
403 16:43:55.651167 WDT: Last reset was cold boot
404 16:43:55.654844 SPI1(PAD0) initialized at 2873684 Hz
405 16:43:55.657900 SPI5(PAD0) initialized at 992727 Hz
406 16:43:55.661568 VBOOT: Loading verstage.
407 16:43:55.667840 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
408 16:43:55.671314 FMAP: Found "FLASH" version 1.1 at 0x20000.
409 16:43:55.674668 FMAP: base = 0x0 size = 0x800000 #areas = 25
410 16:43:55.678087 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
411 16:43:55.685336 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
412 16:43:55.691772 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
413 16:43:55.703245 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
414 16:43:55.703352
415 16:43:55.703421
416 16:43:55.713015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
417 16:43:55.715928 ARM64: Exception handlers installed.
418 16:43:55.719667 ARM64: Testing exception
419 16:43:55.719747 ARM64: Done test exception
420 16:43:55.727642 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
421 16:43:55.730348 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 16:43:55.743899 Probing TPM: . done!
423 16:43:55.743992 TPM ready after 0 ms
424 16:43:55.751154 Connected to device vid:did:rid of 1ae0:0028:00
425 16:43:55.757926 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
426 16:43:55.799497 Initialized TPM device CR50 revision 0
427 16:43:55.810653 tlcl_send_startup: Startup return code is 0
428 16:43:55.810770 TPM: setup succeeded
429 16:43:55.822087 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
430 16:43:55.830666 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 16:43:55.842587 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
432 16:43:55.851544 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
433 16:43:55.855150 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
434 16:43:55.858952 in-header: 03 07 00 00 08 00 00 00
435 16:43:55.862754 in-data: aa e4 47 04 13 02 00 00
436 16:43:55.865961 Chrome EC: UHEPI supported
437 16:43:55.873402 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
438 16:43:55.876892 in-header: 03 9d 00 00 08 00 00 00
439 16:43:55.880222 in-data: 10 20 20 08 00 00 00 00
440 16:43:55.880348 Phase 1
441 16:43:55.883940 FMAP: area GBB found @ 3f5000 (12032 bytes)
442 16:43:55.891410 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
443 16:43:55.894953 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
444 16:43:55.898668 Recovery requested (1009000e)
445 16:43:55.901651 TPM: Extending digest for VBOOT: boot mode into PCR 0
446 16:43:55.911204 tlcl_extend: response is 0
447 16:43:55.919563 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
448 16:43:55.924877 tlcl_extend: response is 0
449 16:43:55.930867 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
450 16:43:55.952301 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
451 16:43:55.959132 BS: bootblock times (exec / console): total (unknown) / 148 ms
452 16:43:55.959227
453 16:43:55.959298
454 16:43:55.969678 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
455 16:43:55.973461 ARM64: Exception handlers installed.
456 16:43:55.973551 ARM64: Testing exception
457 16:43:55.976528 ARM64: Done test exception
458 16:43:55.997836 pmic_efuse_setting: Set efuses in 11 msecs
459 16:43:56.000732 pmwrap_interface_init: Select PMIF_VLD_RDY
460 16:43:56.008205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
461 16:43:56.011881 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
462 16:43:56.015548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
463 16:43:56.022962 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
464 16:43:56.026643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
465 16:43:56.030046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
466 16:43:56.033862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
467 16:43:56.040980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
468 16:43:56.044575 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
469 16:43:56.051251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
470 16:43:56.054237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
471 16:43:56.057907 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
472 16:43:56.064185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
473 16:43:56.070984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
474 16:43:56.074118 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
475 16:43:56.080967 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
476 16:43:56.087506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
477 16:43:56.091201 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
478 16:43:56.098142 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
479 16:43:56.104547 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
480 16:43:56.107858 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
481 16:43:56.114447 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
482 16:43:56.121411 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
483 16:43:56.124340 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
484 16:43:56.131420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
485 16:43:56.138217 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
486 16:43:56.142046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
487 16:43:56.145806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
488 16:43:56.152821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
489 16:43:56.156452 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
490 16:43:56.163332 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
491 16:43:56.166925 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
492 16:43:56.170206 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
493 16:43:56.177705 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
494 16:43:56.181528 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
495 16:43:56.185114 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
496 16:43:56.191665 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
497 16:43:56.194791 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
498 16:43:56.201962 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
499 16:43:56.205074 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
500 16:43:56.208043 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
501 16:43:56.215370 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
502 16:43:56.218624 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
503 16:43:56.221488 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
504 16:43:56.228413 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
505 16:43:56.231519 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
506 16:43:56.234820 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
507 16:43:56.238439 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
508 16:43:56.244959 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
509 16:43:56.248157 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
510 16:43:56.251705 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
511 16:43:56.261620 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
512 16:43:56.268209 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
513 16:43:56.274986 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
514 16:43:56.281564 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
515 16:43:56.291386 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
516 16:43:56.294166 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
517 16:43:56.297830 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 16:43:56.304452 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
519 16:43:56.311353 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x20
520 16:43:56.314322 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
521 16:43:56.321846 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
522 16:43:56.325357 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
523 16:43:56.334534 [RTC]rtc_get_frequency_meter,154: input=15, output=793
524 16:43:56.338127 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
525 16:43:56.344677 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
526 16:43:56.348091 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
527 16:43:56.351068 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
528 16:43:56.354249 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
529 16:43:56.357934 ADC[4]: Raw value=895561 ID=7
530 16:43:56.361494 ADC[3]: Raw value=212700 ID=1
531 16:43:56.364889 RAM Code: 0x71
532 16:43:56.368040 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
533 16:43:56.371532 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
534 16:43:56.381056 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
535 16:43:56.388987 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
536 16:43:56.392055 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
537 16:43:56.395141 in-header: 03 07 00 00 08 00 00 00
538 16:43:56.398729 in-data: aa e4 47 04 13 02 00 00
539 16:43:56.401692 Chrome EC: UHEPI supported
540 16:43:56.408691 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
541 16:43:56.412522 in-header: 03 d5 00 00 08 00 00 00
542 16:43:56.412618 in-data: 98 20 60 08 00 00 00 00
543 16:43:56.415652 MRC: failed to locate region type 0.
544 16:43:56.423321 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
545 16:43:56.426940 DRAM-K: Running full calibration
546 16:43:56.433599 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
547 16:43:56.433684 header.status = 0x0
548 16:43:56.436868 header.version = 0x6 (expected: 0x6)
549 16:43:56.439982 header.size = 0xd00 (expected: 0xd00)
550 16:43:56.443440 header.flags = 0x0
551 16:43:56.450351 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
552 16:43:56.466793 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
553 16:43:56.473384 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
554 16:43:56.476477 dram_init: ddr_geometry: 2
555 16:43:56.480341 [EMI] MDL number = 2
556 16:43:56.480431 [EMI] Get MDL freq = 0
557 16:43:56.482965 dram_init: ddr_type: 0
558 16:43:56.483054 is_discrete_lpddr4: 1
559 16:43:56.486662 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
560 16:43:56.486772
561 16:43:56.486869
562 16:43:56.489958 [Bian_co] ETT version 0.0.0.1
563 16:43:56.497073 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
564 16:43:56.497158
565 16:43:56.500110 dramc_set_vcore_voltage set vcore to 650000
566 16:43:56.500191 Read voltage for 800, 4
567 16:43:56.503541 Vio18 = 0
568 16:43:56.503653 Vcore = 650000
569 16:43:56.503725 Vdram = 0
570 16:43:56.507129 Vddq = 0
571 16:43:56.507217 Vmddr = 0
572 16:43:56.510843 dram_init: config_dvfs: 1
573 16:43:56.514600 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
574 16:43:56.518363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
575 16:43:56.521599 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
576 16:43:56.528903 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
577 16:43:56.531905 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
578 16:43:56.535634 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
579 16:43:56.535724 MEM_TYPE=3, freq_sel=18
580 16:43:56.539041 sv_algorithm_assistance_LP4_1600
581 16:43:56.542864 ============ PULL DRAM RESETB DOWN ============
582 16:43:56.546904 ========== PULL DRAM RESETB DOWN end =========
583 16:43:56.554494 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
584 16:43:56.557641 ===================================
585 16:43:56.557772 LPDDR4 DRAM CONFIGURATION
586 16:43:56.561737 ===================================
587 16:43:56.564871 EX_ROW_EN[0] = 0x0
588 16:43:56.564990 EX_ROW_EN[1] = 0x0
589 16:43:56.568738 LP4Y_EN = 0x0
590 16:43:56.568854 WORK_FSP = 0x0
591 16:43:56.572123 WL = 0x2
592 16:43:56.572253 RL = 0x2
593 16:43:56.576291 BL = 0x2
594 16:43:56.576415 RPST = 0x0
595 16:43:56.576534 RD_PRE = 0x0
596 16:43:56.579524 WR_PRE = 0x1
597 16:43:56.579644 WR_PST = 0x0
598 16:43:56.583274 DBI_WR = 0x0
599 16:43:56.583394 DBI_RD = 0x0
600 16:43:56.586939 OTF = 0x1
601 16:43:56.590456 ===================================
602 16:43:56.594089 ===================================
603 16:43:56.594203 ANA top config
604 16:43:56.596918 ===================================
605 16:43:56.600670 DLL_ASYNC_EN = 0
606 16:43:56.603694 ALL_SLAVE_EN = 1
607 16:43:56.603804 NEW_RANK_MODE = 1
608 16:43:56.606807 DLL_IDLE_MODE = 1
609 16:43:56.610315 LP45_APHY_COMB_EN = 1
610 16:43:56.613969 TX_ODT_DIS = 1
611 16:43:56.617051 NEW_8X_MODE = 1
612 16:43:56.620167 ===================================
613 16:43:56.623782 ===================================
614 16:43:56.623863 data_rate = 1600
615 16:43:56.626861 CKR = 1
616 16:43:56.630431 DQ_P2S_RATIO = 8
617 16:43:56.633640 ===================================
618 16:43:56.637360 CA_P2S_RATIO = 8
619 16:43:56.640359 DQ_CA_OPEN = 0
620 16:43:56.643477 DQ_SEMI_OPEN = 0
621 16:43:56.643594 CA_SEMI_OPEN = 0
622 16:43:56.646891 CA_FULL_RATE = 0
623 16:43:56.650024 DQ_CKDIV4_EN = 1
624 16:43:56.653630 CA_CKDIV4_EN = 1
625 16:43:56.656527 CA_PREDIV_EN = 0
626 16:43:56.660039 PH8_DLY = 0
627 16:43:56.660168 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
628 16:43:56.663154 DQ_AAMCK_DIV = 4
629 16:43:56.666627 CA_AAMCK_DIV = 4
630 16:43:56.669880 CA_ADMCK_DIV = 4
631 16:43:56.673019 DQ_TRACK_CA_EN = 0
632 16:43:56.676483 CA_PICK = 800
633 16:43:56.679918 CA_MCKIO = 800
634 16:43:56.680028 MCKIO_SEMI = 0
635 16:43:56.683199 PLL_FREQ = 3068
636 16:43:56.686375 DQ_UI_PI_RATIO = 32
637 16:43:56.689695 CA_UI_PI_RATIO = 0
638 16:43:56.693342 ===================================
639 16:43:56.696458 ===================================
640 16:43:56.699836 memory_type:LPDDR4
641 16:43:56.699926 GP_NUM : 10
642 16:43:56.703177 SRAM_EN : 1
643 16:43:56.706800 MD32_EN : 0
644 16:43:56.706879 ===================================
645 16:43:56.709879 [ANA_INIT] >>>>>>>>>>>>>>
646 16:43:56.713427 <<<<<< [CONFIGURE PHASE]: ANA_TX
647 16:43:56.716366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
648 16:43:56.719966 ===================================
649 16:43:56.723177 data_rate = 1600,PCW = 0X7600
650 16:43:56.726385 ===================================
651 16:43:56.730074 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
652 16:43:56.736339 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
653 16:43:56.739427 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
654 16:43:56.746393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
655 16:43:56.749690 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
656 16:43:56.753255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
657 16:43:56.753346 [ANA_INIT] flow start
658 16:43:56.756880 [ANA_INIT] PLL >>>>>>>>
659 16:43:56.756968 [ANA_INIT] PLL <<<<<<<<
660 16:43:56.760856 [ANA_INIT] MIDPI >>>>>>>>
661 16:43:56.764211 [ANA_INIT] MIDPI <<<<<<<<
662 16:43:56.764337 [ANA_INIT] DLL >>>>>>>>
663 16:43:56.767724 [ANA_INIT] flow end
664 16:43:56.771803 ============ LP4 DIFF to SE enter ============
665 16:43:56.775022 ============ LP4 DIFF to SE exit ============
666 16:43:56.778691 [ANA_INIT] <<<<<<<<<<<<<
667 16:43:56.782637 [Flow] Enable top DCM control >>>>>
668 16:43:56.786066 [Flow] Enable top DCM control <<<<<
669 16:43:56.786154 Enable DLL master slave shuffle
670 16:43:56.793049 ==============================================================
671 16:43:56.796088 Gating Mode config
672 16:43:56.799768 ==============================================================
673 16:43:56.802674 Config description:
674 16:43:56.812909 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
675 16:43:56.819235 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
676 16:43:56.822889 SELPH_MODE 0: By rank 1: By Phase
677 16:43:56.829080 ==============================================================
678 16:43:56.832781 GAT_TRACK_EN = 1
679 16:43:56.835889 RX_GATING_MODE = 2
680 16:43:56.839054 RX_GATING_TRACK_MODE = 2
681 16:43:56.842280 SELPH_MODE = 1
682 16:43:56.842368 PICG_EARLY_EN = 1
683 16:43:56.845888 VALID_LAT_VALUE = 1
684 16:43:56.852159 ==============================================================
685 16:43:56.856004 Enter into Gating configuration >>>>
686 16:43:56.858865 Exit from Gating configuration <<<<
687 16:43:56.862432 Enter into DVFS_PRE_config >>>>>
688 16:43:56.872438 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
689 16:43:56.875922 Exit from DVFS_PRE_config <<<<<
690 16:43:56.878720 Enter into PICG configuration >>>>
691 16:43:56.881978 Exit from PICG configuration <<<<
692 16:43:56.885557 [RX_INPUT] configuration >>>>>
693 16:43:56.888683 [RX_INPUT] configuration <<<<<
694 16:43:56.892146 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
695 16:43:56.898952 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
696 16:43:56.905648 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
697 16:43:56.912513 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
698 16:43:56.918899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
699 16:43:56.922245 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
700 16:43:56.928907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
701 16:43:56.932049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
702 16:43:56.935276 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
703 16:43:56.938717 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
704 16:43:56.945560 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
705 16:43:56.948648 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
706 16:43:56.952314 ===================================
707 16:43:56.955545 LPDDR4 DRAM CONFIGURATION
708 16:43:56.958912 ===================================
709 16:43:56.959013 EX_ROW_EN[0] = 0x0
710 16:43:56.961964 EX_ROW_EN[1] = 0x0
711 16:43:56.962081 LP4Y_EN = 0x0
712 16:43:56.965555 WORK_FSP = 0x0
713 16:43:56.965656 WL = 0x2
714 16:43:56.969041 RL = 0x2
715 16:43:56.969139 BL = 0x2
716 16:43:56.972818 RPST = 0x0
717 16:43:56.972906 RD_PRE = 0x0
718 16:43:56.976520 WR_PRE = 0x1
719 16:43:56.976607 WR_PST = 0x0
720 16:43:56.980079 DBI_WR = 0x0
721 16:43:56.980166 DBI_RD = 0x0
722 16:43:56.983357 OTF = 0x1
723 16:43:56.987166 ===================================
724 16:43:56.990681 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
725 16:43:56.994521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
726 16:43:56.998402 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 16:43:57.001443 ===================================
728 16:43:57.004947 LPDDR4 DRAM CONFIGURATION
729 16:43:57.008003 ===================================
730 16:43:57.008090 EX_ROW_EN[0] = 0x10
731 16:43:57.011903 EX_ROW_EN[1] = 0x0
732 16:43:57.011990 LP4Y_EN = 0x0
733 16:43:57.014809 WORK_FSP = 0x0
734 16:43:57.014926 WL = 0x2
735 16:43:57.018765 RL = 0x2
736 16:43:57.018939 BL = 0x2
737 16:43:57.022291 RPST = 0x0
738 16:43:57.022376 RD_PRE = 0x0
739 16:43:57.025705 WR_PRE = 0x1
740 16:43:57.025820 WR_PST = 0x0
741 16:43:57.029603 DBI_WR = 0x0
742 16:43:57.029780 DBI_RD = 0x0
743 16:43:57.033436 OTF = 0x1
744 16:43:57.036668 ===================================
745 16:43:57.040435 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
746 16:43:57.045418 nWR fixed to 40
747 16:43:57.045509 [ModeRegInit_LP4] CH0 RK0
748 16:43:57.049069 [ModeRegInit_LP4] CH0 RK1
749 16:43:57.052848 [ModeRegInit_LP4] CH1 RK0
750 16:43:57.052937 [ModeRegInit_LP4] CH1 RK1
751 16:43:57.055943 match AC timing 13
752 16:43:57.059503 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
753 16:43:57.063309 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
754 16:43:57.070648 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
755 16:43:57.074535 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
756 16:43:57.077587 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
757 16:43:57.081286 [EMI DOE] emi_dcm 0
758 16:43:57.084573 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
759 16:43:57.084717 ==
760 16:43:57.088577 Dram Type= 6, Freq= 0, CH_0, rank 0
761 16:43:57.091909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
762 16:43:57.092038 ==
763 16:43:57.099572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
764 16:43:57.103005 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
765 16:43:57.112865 [CA 0] Center 38 (7~69) winsize 63
766 16:43:57.116626 [CA 1] Center 37 (7~68) winsize 62
767 16:43:57.120226 [CA 2] Center 35 (5~66) winsize 62
768 16:43:57.123957 [CA 3] Center 35 (5~66) winsize 62
769 16:43:57.127775 [CA 4] Center 34 (4~65) winsize 62
770 16:43:57.131496 [CA 5] Center 34 (4~64) winsize 61
771 16:43:57.131620
772 16:43:57.134906 [CmdBusTrainingLP45] Vref(ca) range 1: 34
773 16:43:57.135015
774 16:43:57.138994 [CATrainingPosCal] consider 1 rank data
775 16:43:57.139110 u2DelayCellTimex100 = 270/100 ps
776 16:43:57.142327 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
777 16:43:57.146109 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
778 16:43:57.149910 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
779 16:43:57.153617 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
780 16:43:57.157316 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
781 16:43:57.161385 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
782 16:43:57.161487
783 16:43:57.164952 CA PerBit enable=1, Macro0, CA PI delay=34
784 16:43:57.165041
785 16:43:57.168148 [CBTSetCACLKResult] CA Dly = 34
786 16:43:57.171914 CS Dly: 6 (0~37)
787 16:43:57.172000 ==
788 16:43:57.175574 Dram Type= 6, Freq= 0, CH_0, rank 1
789 16:43:57.179149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 16:43:57.179266 ==
791 16:43:57.182981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
792 16:43:57.189639 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
793 16:43:57.199604 [CA 0] Center 38 (7~69) winsize 63
794 16:43:57.202980 [CA 1] Center 37 (7~68) winsize 62
795 16:43:57.206747 [CA 2] Center 35 (5~66) winsize 62
796 16:43:57.210266 [CA 3] Center 35 (5~66) winsize 62
797 16:43:57.214084 [CA 4] Center 34 (4~65) winsize 62
798 16:43:57.217698 [CA 5] Center 34 (4~65) winsize 62
799 16:43:57.217828
800 16:43:57.221310 [CmdBusTrainingLP45] Vref(ca) range 1: 32
801 16:43:57.221440
802 16:43:57.224947 [CATrainingPosCal] consider 2 rank data
803 16:43:57.225067 u2DelayCellTimex100 = 270/100 ps
804 16:43:57.228988 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
805 16:43:57.232630 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
806 16:43:57.235765 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
807 16:43:57.239786 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
808 16:43:57.243208 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
809 16:43:57.246362 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
810 16:43:57.249776
811 16:43:57.253136 CA PerBit enable=1, Macro0, CA PI delay=34
812 16:43:57.253262
813 16:43:57.256801 [CBTSetCACLKResult] CA Dly = 34
814 16:43:57.256939 CS Dly: 6 (0~37)
815 16:43:57.257038
816 16:43:57.259951 ----->DramcWriteLeveling(PI) begin...
817 16:43:57.260035 ==
818 16:43:57.262993 Dram Type= 6, Freq= 0, CH_0, rank 0
819 16:43:57.266233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
820 16:43:57.269535 ==
821 16:43:57.272686 Write leveling (Byte 0): 30 => 30
822 16:43:57.272770 Write leveling (Byte 1): 29 => 29
823 16:43:57.276305 DramcWriteLeveling(PI) end<-----
824 16:43:57.276418
825 16:43:57.276523 ==
826 16:43:57.279245 Dram Type= 6, Freq= 0, CH_0, rank 0
827 16:43:57.286007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
828 16:43:57.286143 ==
829 16:43:57.289363 [Gating] SW mode calibration
830 16:43:57.296187 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
831 16:43:57.299192 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
832 16:43:57.305972 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
833 16:43:57.309736 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
834 16:43:57.312677 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
835 16:43:57.319324 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
836 16:43:57.322573 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 16:43:57.325798 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 16:43:57.332272 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 16:43:57.336003 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 16:43:57.339161 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 16:43:57.342849 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 16:43:57.350301 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 16:43:57.353867 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 16:43:57.357245 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 16:43:57.360395 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 16:43:57.367525 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 16:43:57.370798 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
848 16:43:57.374285 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
849 16:43:57.381016 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
850 16:43:57.383968 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
851 16:43:57.387815 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
852 16:43:57.394476 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 16:43:57.397382 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 16:43:57.400467 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 16:43:57.404177 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 16:43:57.410408 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:43:57.414056 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:43:57.417121 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
859 16:43:57.423792 0 9 12 | B1->B0 | 2525 3030 | 0 1 | (0 0) (1 1)
860 16:43:57.427237 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
861 16:43:57.430934 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
862 16:43:57.437188 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
863 16:43:57.440445 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
864 16:43:57.443533 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
865 16:43:57.450535 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
866 16:43:57.453916 0 10 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
867 16:43:57.457137 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
868 16:43:57.463293 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
869 16:43:57.466854 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 16:43:57.469964 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 16:43:57.476728 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 16:43:57.480406 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:43:57.483426 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:43:57.489954 0 11 8 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
875 16:43:57.493611 0 11 12 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
876 16:43:57.496704 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
877 16:43:57.503358 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
878 16:43:57.506686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
879 16:43:57.509730 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
880 16:43:57.516770 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
881 16:43:57.519687 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
882 16:43:57.523349 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
883 16:43:57.529787 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 16:43:57.533499 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 16:43:57.536637 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 16:43:57.543286 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 16:43:57.546279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
888 16:43:57.549755 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
889 16:43:57.556191 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
890 16:43:57.559365 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
891 16:43:57.562892 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
892 16:43:57.569499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
893 16:43:57.572912 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
894 16:43:57.576001 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
895 16:43:57.582757 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
896 16:43:57.586402 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
897 16:43:57.589324 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
898 16:43:57.595958 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
899 16:43:57.599699 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
900 16:43:57.602859 Total UI for P1: 0, mck2ui 16
901 16:43:57.605956 best dqsien dly found for B0: ( 0, 14, 8)
902 16:43:57.609683 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 16:43:57.613213 Total UI for P1: 0, mck2ui 16
904 16:43:57.615868 best dqsien dly found for B1: ( 0, 14, 10)
905 16:43:57.619731 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
906 16:43:57.622866 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
907 16:43:57.622954
908 16:43:57.625969 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
909 16:43:57.632597 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
910 16:43:57.632687 [Gating] SW calibration Done
911 16:43:57.632757 ==
912 16:43:57.635914 Dram Type= 6, Freq= 0, CH_0, rank 0
913 16:43:57.642736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 16:43:57.642827 ==
915 16:43:57.642897 RX Vref Scan: 0
916 16:43:57.642963
917 16:43:57.645823 RX Vref 0 -> 0, step: 1
918 16:43:57.645909
919 16:43:57.649661 RX Delay -130 -> 252, step: 16
920 16:43:57.652510 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
921 16:43:57.656215 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
922 16:43:57.659559 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
923 16:43:57.666106 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
924 16:43:57.669108 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
925 16:43:57.672911 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
926 16:43:57.675675 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
927 16:43:57.679381 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
928 16:43:57.682901 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
929 16:43:57.689182 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
930 16:43:57.692282 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
931 16:43:57.696094 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
932 16:43:57.699082 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
933 16:43:57.705756 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
934 16:43:57.709157 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
935 16:43:57.712231 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
936 16:43:57.712318 ==
937 16:43:57.715426 Dram Type= 6, Freq= 0, CH_0, rank 0
938 16:43:57.718983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
939 16:43:57.719098 ==
940 16:43:57.722626 DQS Delay:
941 16:43:57.722738 DQS0 = 0, DQS1 = 0
942 16:43:57.725488 DQM Delay:
943 16:43:57.725574 DQM0 = 80, DQM1 = 70
944 16:43:57.725681 DQ Delay:
945 16:43:57.729263 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
946 16:43:57.732460 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
947 16:43:57.735525 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
948 16:43:57.738948 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
949 16:43:57.739044
950 16:43:57.739197
951 16:43:57.742526 ==
952 16:43:57.746083 Dram Type= 6, Freq= 0, CH_0, rank 0
953 16:43:57.749437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
954 16:43:57.749541 ==
955 16:43:57.749651
956 16:43:57.749775
957 16:43:57.749894 TX Vref Scan disable
958 16:43:57.753196 == TX Byte 0 ==
959 16:43:57.756551 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
960 16:43:57.762710 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
961 16:43:57.762802 == TX Byte 1 ==
962 16:43:57.766126 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
963 16:43:57.772540 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
964 16:43:57.772662 ==
965 16:43:57.776297 Dram Type= 6, Freq= 0, CH_0, rank 0
966 16:43:57.779400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 16:43:57.779488 ==
968 16:43:57.791627 TX Vref=22, minBit 11, minWin=26, winSum=434
969 16:43:57.794816 TX Vref=24, minBit 11, minWin=26, winSum=437
970 16:43:57.798426 TX Vref=26, minBit 5, minWin=26, winSum=440
971 16:43:57.801548 TX Vref=28, minBit 1, minWin=27, winSum=441
972 16:43:57.805055 TX Vref=30, minBit 11, minWin=27, winSum=445
973 16:43:57.811883 TX Vref=32, minBit 10, minWin=26, winSum=437
974 16:43:57.815157 [TxChooseVref] Worse bit 11, Min win 27, Win sum 445, Final Vref 30
975 16:43:57.818188
976 16:43:57.818284 Final TX Range 1 Vref 30
977 16:43:57.818368
978 16:43:57.818456 ==
979 16:43:57.821352 Dram Type= 6, Freq= 0, CH_0, rank 0
980 16:43:57.828182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
981 16:43:57.828272 ==
982 16:43:57.828362
983 16:43:57.828430
984 16:43:57.828492 TX Vref Scan disable
985 16:43:57.832389 == TX Byte 0 ==
986 16:43:57.835599 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
987 16:43:57.842160 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
988 16:43:57.842268 == TX Byte 1 ==
989 16:43:57.845570 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
990 16:43:57.852186 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
991 16:43:57.852277
992 16:43:57.852346 [DATLAT]
993 16:43:57.852410 Freq=800, CH0 RK0
994 16:43:57.852472
995 16:43:57.855707 DATLAT Default: 0xa
996 16:43:57.855794 0, 0xFFFF, sum = 0
997 16:43:57.858940 1, 0xFFFF, sum = 0
998 16:43:57.862181 2, 0xFFFF, sum = 0
999 16:43:57.862270 3, 0xFFFF, sum = 0
1000 16:43:57.865166 4, 0xFFFF, sum = 0
1001 16:43:57.865289 5, 0xFFFF, sum = 0
1002 16:43:57.869009 6, 0xFFFF, sum = 0
1003 16:43:57.869111 7, 0xFFFF, sum = 0
1004 16:43:57.871901 8, 0xFFFF, sum = 0
1005 16:43:57.872011 9, 0x0, sum = 1
1006 16:43:57.875169 10, 0x0, sum = 2
1007 16:43:57.875287 11, 0x0, sum = 3
1008 16:43:57.875400 12, 0x0, sum = 4
1009 16:43:57.878687 best_step = 10
1010 16:43:57.878813
1011 16:43:57.878918 ==
1012 16:43:57.882115 Dram Type= 6, Freq= 0, CH_0, rank 0
1013 16:43:57.885300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1014 16:43:57.885413 ==
1015 16:43:57.888275 RX Vref Scan: 1
1016 16:43:57.888360
1017 16:43:57.891886 Set Vref Range= 32 -> 127
1018 16:43:57.891976
1019 16:43:57.892061 RX Vref 32 -> 127, step: 1
1020 16:43:57.892134
1021 16:43:57.895063 RX Delay -111 -> 252, step: 8
1022 16:43:57.895154
1023 16:43:57.898715 Set Vref, RX VrefLevel [Byte0]: 32
1024 16:43:57.901861 [Byte1]: 32
1025 16:43:57.905360
1026 16:43:57.905470 Set Vref, RX VrefLevel [Byte0]: 33
1027 16:43:57.908611 [Byte1]: 33
1028 16:43:57.912910
1029 16:43:57.912988 Set Vref, RX VrefLevel [Byte0]: 34
1030 16:43:57.916107 [Byte1]: 34
1031 16:43:57.920467
1032 16:43:57.920549 Set Vref, RX VrefLevel [Byte0]: 35
1033 16:43:57.923794 [Byte1]: 35
1034 16:43:57.927971
1035 16:43:57.928062 Set Vref, RX VrefLevel [Byte0]: 36
1036 16:43:57.931634 [Byte1]: 36
1037 16:43:57.935924
1038 16:43:57.936055 Set Vref, RX VrefLevel [Byte0]: 37
1039 16:43:57.939063 [Byte1]: 37
1040 16:43:57.943604
1041 16:43:57.943693 Set Vref, RX VrefLevel [Byte0]: 38
1042 16:43:57.946792 [Byte1]: 38
1043 16:43:57.950840
1044 16:43:57.950949 Set Vref, RX VrefLevel [Byte0]: 39
1045 16:43:57.954300 [Byte1]: 39
1046 16:43:57.958568
1047 16:43:57.958678 Set Vref, RX VrefLevel [Byte0]: 40
1048 16:43:57.962419 [Byte1]: 40
1049 16:43:57.966394
1050 16:43:57.966516 Set Vref, RX VrefLevel [Byte0]: 41
1051 16:43:57.969350 [Byte1]: 41
1052 16:43:57.974279
1053 16:43:57.974381 Set Vref, RX VrefLevel [Byte0]: 42
1054 16:43:57.977459 [Byte1]: 42
1055 16:43:57.981600
1056 16:43:57.981706 Set Vref, RX VrefLevel [Byte0]: 43
1057 16:43:57.985046 [Byte1]: 43
1058 16:43:57.989034
1059 16:43:57.989127 Set Vref, RX VrefLevel [Byte0]: 44
1060 16:43:57.992583 [Byte1]: 44
1061 16:43:57.996756
1062 16:43:57.996871 Set Vref, RX VrefLevel [Byte0]: 45
1063 16:43:58.000274 [Byte1]: 45
1064 16:43:58.004643
1065 16:43:58.004722 Set Vref, RX VrefLevel [Byte0]: 46
1066 16:43:58.008311 [Byte1]: 46
1067 16:43:58.012493
1068 16:43:58.012572 Set Vref, RX VrefLevel [Byte0]: 47
1069 16:43:58.016065 [Byte1]: 47
1070 16:43:58.019837
1071 16:43:58.019928 Set Vref, RX VrefLevel [Byte0]: 48
1072 16:43:58.023548 [Byte1]: 48
1073 16:43:58.027594
1074 16:43:58.027678 Set Vref, RX VrefLevel [Byte0]: 49
1075 16:43:58.031221 [Byte1]: 49
1076 16:43:58.035069
1077 16:43:58.035158 Set Vref, RX VrefLevel [Byte0]: 50
1078 16:43:58.038623 [Byte1]: 50
1079 16:43:58.043191
1080 16:43:58.043308 Set Vref, RX VrefLevel [Byte0]: 51
1081 16:43:58.046090 [Byte1]: 51
1082 16:43:58.050345
1083 16:43:58.050430 Set Vref, RX VrefLevel [Byte0]: 52
1084 16:43:58.053368 [Byte1]: 52
1085 16:43:58.057832
1086 16:43:58.057946 Set Vref, RX VrefLevel [Byte0]: 53
1087 16:43:58.061062 [Byte1]: 53
1088 16:43:58.065709
1089 16:43:58.065797 Set Vref, RX VrefLevel [Byte0]: 54
1090 16:43:58.069292 [Byte1]: 54
1091 16:43:58.073278
1092 16:43:58.073388 Set Vref, RX VrefLevel [Byte0]: 55
1093 16:43:58.076607 [Byte1]: 55
1094 16:43:58.080788
1095 16:43:58.080880 Set Vref, RX VrefLevel [Byte0]: 56
1096 16:43:58.083987 [Byte1]: 56
1097 16:43:58.088626
1098 16:43:58.088720 Set Vref, RX VrefLevel [Byte0]: 57
1099 16:43:58.091584 [Byte1]: 57
1100 16:43:58.096285
1101 16:43:58.096367 Set Vref, RX VrefLevel [Byte0]: 58
1102 16:43:58.099355 [Byte1]: 58
1103 16:43:58.103527
1104 16:43:58.103649 Set Vref, RX VrefLevel [Byte0]: 59
1105 16:43:58.107137 [Byte1]: 59
1106 16:43:58.111389
1107 16:43:58.111507 Set Vref, RX VrefLevel [Byte0]: 60
1108 16:43:58.115019 [Byte1]: 60
1109 16:43:58.119310
1110 16:43:58.119392 Set Vref, RX VrefLevel [Byte0]: 61
1111 16:43:58.125613 [Byte1]: 61
1112 16:43:58.125721
1113 16:43:58.128996 Set Vref, RX VrefLevel [Byte0]: 62
1114 16:43:58.132093 [Byte1]: 62
1115 16:43:58.132177
1116 16:43:58.135191 Set Vref, RX VrefLevel [Byte0]: 63
1117 16:43:58.138516 [Byte1]: 63
1118 16:43:58.141950
1119 16:43:58.142063 Set Vref, RX VrefLevel [Byte0]: 64
1120 16:43:58.145592 [Byte1]: 64
1121 16:43:58.149887
1122 16:43:58.149974 Set Vref, RX VrefLevel [Byte0]: 65
1123 16:43:58.153316 [Byte1]: 65
1124 16:43:58.157714
1125 16:43:58.157847 Set Vref, RX VrefLevel [Byte0]: 66
1126 16:43:58.160922 [Byte1]: 66
1127 16:43:58.165084
1128 16:43:58.165203 Set Vref, RX VrefLevel [Byte0]: 67
1129 16:43:58.168027 [Byte1]: 67
1130 16:43:58.172775
1131 16:43:58.172892 Set Vref, RX VrefLevel [Byte0]: 68
1132 16:43:58.176007 [Byte1]: 68
1133 16:43:58.180519
1134 16:43:58.180601 Set Vref, RX VrefLevel [Byte0]: 69
1135 16:43:58.183543 [Byte1]: 69
1136 16:43:58.188044
1137 16:43:58.188155 Set Vref, RX VrefLevel [Byte0]: 70
1138 16:43:58.191092 [Byte1]: 70
1139 16:43:58.195743
1140 16:43:58.195829 Set Vref, RX VrefLevel [Byte0]: 71
1141 16:43:58.198694 [Byte1]: 71
1142 16:43:58.203415
1143 16:43:58.203505 Set Vref, RX VrefLevel [Byte0]: 72
1144 16:43:58.206540 [Byte1]: 72
1145 16:43:58.210673
1146 16:43:58.210764 Set Vref, RX VrefLevel [Byte0]: 73
1147 16:43:58.214183 [Byte1]: 73
1148 16:43:58.218342
1149 16:43:58.218422 Set Vref, RX VrefLevel [Byte0]: 74
1150 16:43:58.222069 [Byte1]: 74
1151 16:43:58.226080
1152 16:43:58.226178 Set Vref, RX VrefLevel [Byte0]: 75
1153 16:43:58.229626 [Byte1]: 75
1154 16:43:58.233857
1155 16:43:58.233932 Set Vref, RX VrefLevel [Byte0]: 76
1156 16:43:58.236976 [Byte1]: 76
1157 16:43:58.241319
1158 16:43:58.241397 Set Vref, RX VrefLevel [Byte0]: 77
1159 16:43:58.245182 [Byte1]: 77
1160 16:43:58.249142
1161 16:43:58.249242 Set Vref, RX VrefLevel [Byte0]: 78
1162 16:43:58.252530 [Byte1]: 78
1163 16:43:58.256586
1164 16:43:58.256661 Set Vref, RX VrefLevel [Byte0]: 79
1165 16:43:58.259846 [Byte1]: 79
1166 16:43:58.264150
1167 16:43:58.264231 Set Vref, RX VrefLevel [Byte0]: 80
1168 16:43:58.267947 [Byte1]: 80
1169 16:43:58.271836
1170 16:43:58.271917 Final RX Vref Byte 0 = 60 to rank0
1171 16:43:58.275678 Final RX Vref Byte 1 = 58 to rank0
1172 16:43:58.278542 Final RX Vref Byte 0 = 60 to rank1
1173 16:43:58.281785 Final RX Vref Byte 1 = 58 to rank1==
1174 16:43:58.285114 Dram Type= 6, Freq= 0, CH_0, rank 0
1175 16:43:58.291859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1176 16:43:58.291965 ==
1177 16:43:58.292079 DQS Delay:
1178 16:43:58.292171 DQS0 = 0, DQS1 = 0
1179 16:43:58.295388 DQM Delay:
1180 16:43:58.295523 DQM0 = 82, DQM1 = 68
1181 16:43:58.298404 DQ Delay:
1182 16:43:58.301952 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1183 16:43:58.305139 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1184 16:43:58.308682 DQ8 =64, DQ9 =56, DQ10 =68, DQ11 =60
1185 16:43:58.311661 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1186 16:43:58.311747
1187 16:43:58.311835
1188 16:43:58.318819 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1189 16:43:58.321710 CH0 RK0: MR19=606, MR18=2323
1190 16:43:58.328482 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1191 16:43:58.328569
1192 16:43:58.331547 ----->DramcWriteLeveling(PI) begin...
1193 16:43:58.331657 ==
1194 16:43:58.334705 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 16:43:58.338430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 16:43:58.338515 ==
1197 16:43:58.341606 Write leveling (Byte 0): 31 => 31
1198 16:43:58.345023 Write leveling (Byte 1): 30 => 30
1199 16:43:58.348135 DramcWriteLeveling(PI) end<-----
1200 16:43:58.348218
1201 16:43:58.348284 ==
1202 16:43:58.351683 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 16:43:58.354635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 16:43:58.354718 ==
1205 16:43:58.358434 [Gating] SW mode calibration
1206 16:43:58.364755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1207 16:43:58.371464 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1208 16:43:58.374988 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1209 16:43:58.381445 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1210 16:43:58.384621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 16:43:58.388313 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1212 16:43:58.394680 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 16:43:58.398090 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 16:43:58.401665 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 16:43:58.404442 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 16:43:58.411254 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 16:43:58.414495 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 16:43:58.417684 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 16:43:58.462631 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 16:43:58.462771 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 16:43:58.463062 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 16:43:58.463148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 16:43:58.463240 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:43:58.463894 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1225 16:43:58.463978 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:43:58.464224 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1227 16:43:58.464292 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:43:58.468893 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:43:58.472652 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:43:58.472739 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:43:58.475585 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:43:58.479125 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:43:58.485752 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:43:58.489375 0 9 8 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
1235 16:43:58.492222 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1236 16:43:58.499222 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1237 16:43:58.501981 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 16:43:58.505425 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 16:43:58.512362 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 16:43:58.515554 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 16:43:58.518716 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (1 0)
1242 16:43:58.525720 0 10 8 | B1->B0 | 3030 2a2a | 1 0 | (1 1) (1 0)
1243 16:43:58.529085 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 16:43:58.532047 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 16:43:58.538988 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 16:43:58.542005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 16:43:58.545218 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 16:43:58.552094 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 16:43:58.555158 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1250 16:43:58.558826 0 11 8 | B1->B0 | 3232 3f3f | 0 0 | (0 0) (0 0)
1251 16:43:58.565195 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1252 16:43:58.568207 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1253 16:43:58.571971 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 16:43:58.578598 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 16:43:58.582198 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 16:43:58.585649 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 16:43:58.590001 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1258 16:43:58.596882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1259 16:43:58.599751 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 16:43:58.603201 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 16:43:58.606781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 16:43:58.613631 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 16:43:58.616988 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 16:43:58.620042 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 16:43:58.626854 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 16:43:58.630145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 16:43:58.633815 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 16:43:58.640088 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 16:43:58.643383 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 16:43:58.647016 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 16:43:58.653338 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 16:43:58.657054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 16:43:58.660107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 16:43:58.666592 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1275 16:43:58.670244 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 16:43:58.673324 Total UI for P1: 0, mck2ui 16
1277 16:43:58.676294 best dqsien dly found for B0: ( 0, 14, 8)
1278 16:43:58.680001 Total UI for P1: 0, mck2ui 16
1279 16:43:58.683038 best dqsien dly found for B1: ( 0, 14, 8)
1280 16:43:58.686707 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1281 16:43:58.689624 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1282 16:43:58.689714
1283 16:43:58.693075 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1284 16:43:58.696942 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1285 16:43:58.699884 [Gating] SW calibration Done
1286 16:43:58.699975 ==
1287 16:43:58.703560 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 16:43:58.706628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 16:43:58.706715 ==
1290 16:43:58.710100 RX Vref Scan: 0
1291 16:43:58.710184
1292 16:43:58.713368 RX Vref 0 -> 0, step: 1
1293 16:43:58.713500
1294 16:43:58.713585 RX Delay -130 -> 252, step: 16
1295 16:43:58.719726 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1296 16:43:58.723067 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1297 16:43:58.726325 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1298 16:43:58.729437 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1299 16:43:58.736450 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1300 16:43:58.739464 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1301 16:43:58.742811 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1302 16:43:58.746372 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1303 16:43:58.749595 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1304 16:43:58.756231 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1305 16:43:58.759246 iDelay=222, Bit 10, Center 61 (-66 ~ 189) 256
1306 16:43:58.762344 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1307 16:43:58.765961 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1308 16:43:58.768923 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1309 16:43:58.775607 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1310 16:43:58.779129 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1311 16:43:58.779209 ==
1312 16:43:58.782843 Dram Type= 6, Freq= 0, CH_0, rank 1
1313 16:43:58.785871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1314 16:43:58.785957 ==
1315 16:43:58.788985 DQS Delay:
1316 16:43:58.789070 DQS0 = 0, DQS1 = 0
1317 16:43:58.789139 DQM Delay:
1318 16:43:58.792560 DQM0 = 76, DQM1 = 68
1319 16:43:58.792641 DQ Delay:
1320 16:43:58.795946 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1321 16:43:58.798958 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1322 16:43:58.802430 DQ8 =61, DQ9 =53, DQ10 =61, DQ11 =61
1323 16:43:58.805409 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1324 16:43:58.805524
1325 16:43:58.805618
1326 16:43:58.805700 ==
1327 16:43:58.809131 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 16:43:58.815717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 16:43:58.815803 ==
1330 16:43:58.815871
1331 16:43:58.815933
1332 16:43:58.815993 TX Vref Scan disable
1333 16:43:58.819303 == TX Byte 0 ==
1334 16:43:58.822386 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1335 16:43:58.828929 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1336 16:43:58.829019 == TX Byte 1 ==
1337 16:43:58.832309 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1338 16:43:58.838884 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1339 16:43:58.838999 ==
1340 16:43:58.842181 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 16:43:58.845848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 16:43:58.845934 ==
1343 16:43:58.858017 TX Vref=22, minBit 11, minWin=26, winSum=437
1344 16:43:58.861540 TX Vref=24, minBit 11, minWin=26, winSum=440
1345 16:43:58.864586 TX Vref=26, minBit 1, minWin=27, winSum=441
1346 16:43:58.868255 TX Vref=28, minBit 1, minWin=27, winSum=444
1347 16:43:58.871370 TX Vref=30, minBit 1, minWin=27, winSum=443
1348 16:43:58.878009 TX Vref=32, minBit 1, minWin=27, winSum=442
1349 16:43:58.881757 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 28
1350 16:43:58.881841
1351 16:43:58.884908 Final TX Range 1 Vref 28
1352 16:43:58.884991
1353 16:43:58.885057 ==
1354 16:43:58.887946 Dram Type= 6, Freq= 0, CH_0, rank 1
1355 16:43:58.891527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1356 16:43:58.894562 ==
1357 16:43:58.894646
1358 16:43:58.894711
1359 16:43:58.894773 TX Vref Scan disable
1360 16:43:58.898624 == TX Byte 0 ==
1361 16:43:58.901372 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1362 16:43:58.907867 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1363 16:43:58.907950 == TX Byte 1 ==
1364 16:43:58.911563 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1365 16:43:58.918266 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1366 16:43:58.918363
1367 16:43:58.918442 [DATLAT]
1368 16:43:58.918503 Freq=800, CH0 RK1
1369 16:43:58.918562
1370 16:43:58.921115 DATLAT Default: 0xa
1371 16:43:58.921197 0, 0xFFFF, sum = 0
1372 16:43:58.924813 1, 0xFFFF, sum = 0
1373 16:43:58.927894 2, 0xFFFF, sum = 0
1374 16:43:58.927978 3, 0xFFFF, sum = 0
1375 16:43:58.931388 4, 0xFFFF, sum = 0
1376 16:43:58.931499 5, 0xFFFF, sum = 0
1377 16:43:58.934562 6, 0xFFFF, sum = 0
1378 16:43:58.934646 7, 0xFFFF, sum = 0
1379 16:43:58.938015 8, 0xFFFF, sum = 0
1380 16:43:58.938089 9, 0x0, sum = 1
1381 16:43:58.941368 10, 0x0, sum = 2
1382 16:43:58.941441 11, 0x0, sum = 3
1383 16:43:58.941503 12, 0x0, sum = 4
1384 16:43:58.944684 best_step = 10
1385 16:43:58.944762
1386 16:43:58.944823 ==
1387 16:43:58.947763 Dram Type= 6, Freq= 0, CH_0, rank 1
1388 16:43:58.951306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1389 16:43:58.951382 ==
1390 16:43:58.954361 RX Vref Scan: 0
1391 16:43:58.954431
1392 16:43:58.954510 RX Vref 0 -> 0, step: 1
1393 16:43:58.957897
1394 16:43:58.957967 RX Delay -111 -> 252, step: 8
1395 16:43:58.965043 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1396 16:43:58.968256 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1397 16:43:58.971391 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1398 16:43:58.974987 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1399 16:43:58.981324 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1400 16:43:58.985063 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1401 16:43:58.987983 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1402 16:43:58.991179 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1403 16:43:58.994754 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1404 16:43:58.998306 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1405 16:43:59.004693 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1406 16:43:59.008321 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1407 16:43:59.011446 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1408 16:43:59.014507 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1409 16:43:59.021284 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1410 16:43:59.024872 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1411 16:43:59.024955 ==
1412 16:43:59.027940 Dram Type= 6, Freq= 0, CH_0, rank 1
1413 16:43:59.030959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1414 16:43:59.031035 ==
1415 16:43:59.034667 DQS Delay:
1416 16:43:59.034743 DQS0 = 0, DQS1 = 0
1417 16:43:59.034805 DQM Delay:
1418 16:43:59.037751 DQM0 = 79, DQM1 = 71
1419 16:43:59.037820 DQ Delay:
1420 16:43:59.041232 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1421 16:43:59.044184 DQ4 =80, DQ5 =64, DQ6 =92, DQ7 =92
1422 16:43:59.047599 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1423 16:43:59.051231 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =80
1424 16:43:59.051313
1425 16:43:59.051379
1426 16:43:59.060664 [DQSOSCAuto] RK1, (LSB)MR18= 0x4c27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
1427 16:43:59.060752 CH0 RK1: MR19=606, MR18=4C27
1428 16:43:59.067429 CH0_RK1: MR19=0x606, MR18=0x4C27, DQSOSC=390, MR23=63, INC=97, DEC=64
1429 16:43:59.070866 [RxdqsGatingPostProcess] freq 800
1430 16:43:59.077195 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1431 16:43:59.080548 Pre-setting of DQS Precalculation
1432 16:43:59.084256 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1433 16:43:59.084331 ==
1434 16:43:59.087531 Dram Type= 6, Freq= 0, CH_1, rank 0
1435 16:43:59.094202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1436 16:43:59.094305 ==
1437 16:43:59.097268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1438 16:43:59.103861 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1439 16:43:59.113609 [CA 0] Center 36 (6~67) winsize 62
1440 16:43:59.116787 [CA 1] Center 36 (6~67) winsize 62
1441 16:43:59.120107 [CA 2] Center 34 (5~64) winsize 60
1442 16:43:59.123826 [CA 3] Center 34 (4~64) winsize 61
1443 16:43:59.126617 [CA 4] Center 35 (5~65) winsize 61
1444 16:43:59.130329 [CA 5] Center 34 (4~64) winsize 61
1445 16:43:59.130438
1446 16:43:59.133420 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1447 16:43:59.133525
1448 16:43:59.136457 [CATrainingPosCal] consider 1 rank data
1449 16:43:59.139728 u2DelayCellTimex100 = 270/100 ps
1450 16:43:59.143370 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1451 16:43:59.149764 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1452 16:43:59.153140 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1453 16:43:59.156562 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1454 16:43:59.159933 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1455 16:43:59.162750 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1456 16:43:59.162855
1457 16:43:59.166610 CA PerBit enable=1, Macro0, CA PI delay=34
1458 16:43:59.166688
1459 16:43:59.169672 [CBTSetCACLKResult] CA Dly = 34
1460 16:43:59.169750 CS Dly: 5 (0~36)
1461 16:43:59.173176 ==
1462 16:43:59.176067 Dram Type= 6, Freq= 0, CH_1, rank 1
1463 16:43:59.179231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1464 16:43:59.179307 ==
1465 16:43:59.182778 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1466 16:43:59.189713 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1467 16:43:59.199363 [CA 0] Center 37 (7~67) winsize 61
1468 16:43:59.203035 [CA 1] Center 37 (7~67) winsize 61
1469 16:43:59.206010 [CA 2] Center 35 (5~65) winsize 61
1470 16:43:59.209628 [CA 3] Center 33 (3~64) winsize 62
1471 16:43:59.213177 [CA 4] Center 34 (4~65) winsize 62
1472 16:43:59.215852 [CA 5] Center 33 (3~64) winsize 62
1473 16:43:59.215935
1474 16:43:59.219658 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1475 16:43:59.219741
1476 16:43:59.222572 [CATrainingPosCal] consider 2 rank data
1477 16:43:59.225726 u2DelayCellTimex100 = 270/100 ps
1478 16:43:59.229283 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1479 16:43:59.235985 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1480 16:43:59.239680 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1481 16:43:59.243198 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1482 16:43:59.246724 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1483 16:43:59.250303 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1484 16:43:59.250377
1485 16:43:59.253961 CA PerBit enable=1, Macro0, CA PI delay=34
1486 16:43:59.254031
1487 16:43:59.257579 [CBTSetCACLKResult] CA Dly = 34
1488 16:43:59.257651 CS Dly: 6 (0~38)
1489 16:43:59.257713
1490 16:43:59.261068 ----->DramcWriteLeveling(PI) begin...
1491 16:43:59.261149 ==
1492 16:43:59.264514 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 16:43:59.267938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 16:43:59.268022 ==
1495 16:43:59.271426 Write leveling (Byte 0): 28 => 28
1496 16:43:59.275133 Write leveling (Byte 1): 30 => 30
1497 16:43:59.278656 DramcWriteLeveling(PI) end<-----
1498 16:43:59.278783
1499 16:43:59.278868 ==
1500 16:43:59.281540 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 16:43:59.285180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 16:43:59.285285 ==
1503 16:43:59.288295 [Gating] SW mode calibration
1504 16:43:59.295058 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1505 16:43:59.301637 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1506 16:43:59.305371 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1507 16:43:59.308433 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1508 16:43:59.314769 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1509 16:43:59.318200 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 16:43:59.321938 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 16:43:59.328734 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 16:43:59.331793 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 16:43:59.335352 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 16:43:59.342052 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 16:43:59.344987 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 16:43:59.348524 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 16:43:59.355083 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 16:43:59.358217 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 16:43:59.361766 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 16:43:59.368323 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 16:43:59.371154 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:43:59.374723 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:43:59.381790 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1524 16:43:59.384663 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1525 16:43:59.388088 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:43:59.394841 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:43:59.398038 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:43:59.401441 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:43:59.404821 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:43:59.411477 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 16:43:59.414384 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 16:43:59.418024 0 9 8 | B1->B0 | 2929 2d2d | 1 0 | (1 1) (0 0)
1533 16:43:59.424953 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1534 16:43:59.427927 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1535 16:43:59.431687 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 16:43:59.437672 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 16:43:59.441139 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 16:43:59.444364 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 16:43:59.450930 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (0 0) (0 0)
1540 16:43:59.454510 0 10 8 | B1->B0 | 2b2b 2f2f | 0 0 | (1 0) (0 0)
1541 16:43:59.457524 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 16:43:59.464184 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 16:43:59.467873 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 16:43:59.470878 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 16:43:59.477383 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 16:43:59.481163 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 16:43:59.484706 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1548 16:43:59.490753 0 11 8 | B1->B0 | 3535 3737 | 1 0 | (0 0) (0 0)
1549 16:43:59.494251 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1550 16:43:59.497317 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 16:43:59.504062 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 16:43:59.507028 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 16:43:59.510512 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 16:43:59.517547 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 16:43:59.520448 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1556 16:43:59.523877 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 16:43:59.530593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 16:43:59.533684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 16:43:59.536951 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 16:43:59.543763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 16:43:59.546681 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 16:43:59.550326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 16:43:59.556986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 16:43:59.559957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 16:43:59.563549 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 16:43:59.570159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 16:43:59.573323 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:43:59.576949 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 16:43:59.583261 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 16:43:59.587030 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 16:43:59.590168 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 16:43:59.596334 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1573 16:43:59.599901 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 16:43:59.603557 Total UI for P1: 0, mck2ui 16
1575 16:43:59.606759 best dqsien dly found for B0: ( 0, 14, 8)
1576 16:43:59.609708 Total UI for P1: 0, mck2ui 16
1577 16:43:59.613127 best dqsien dly found for B1: ( 0, 14, 8)
1578 16:43:59.616226 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1579 16:43:59.619762 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1580 16:43:59.619859
1581 16:43:59.623029 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1582 16:43:59.626210 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1583 16:43:59.629755 [Gating] SW calibration Done
1584 16:43:59.629865 ==
1585 16:43:59.632995 Dram Type= 6, Freq= 0, CH_1, rank 0
1586 16:43:59.636083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1587 16:43:59.636187 ==
1588 16:43:59.639741 RX Vref Scan: 0
1589 16:43:59.639817
1590 16:43:59.642759 RX Vref 0 -> 0, step: 1
1591 16:43:59.642832
1592 16:43:59.642893 RX Delay -130 -> 252, step: 16
1593 16:43:59.649362 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1594 16:43:59.653161 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1595 16:43:59.656175 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1596 16:43:59.659293 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1597 16:43:59.662699 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1598 16:43:59.669240 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1599 16:43:59.672977 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1600 16:43:59.676058 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1601 16:43:59.679802 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1602 16:43:59.682701 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1603 16:43:59.689344 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1604 16:43:59.692768 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1605 16:43:59.695757 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1606 16:43:59.699477 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1607 16:43:59.706149 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1608 16:43:59.709202 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1609 16:43:59.709314 ==
1610 16:43:59.712749 Dram Type= 6, Freq= 0, CH_1, rank 0
1611 16:43:59.715767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1612 16:43:59.715852 ==
1613 16:43:59.719284 DQS Delay:
1614 16:43:59.719367 DQS0 = 0, DQS1 = 0
1615 16:43:59.719434 DQM Delay:
1616 16:43:59.722309 DQM0 = 82, DQM1 = 74
1617 16:43:59.722392 DQ Delay:
1618 16:43:59.725857 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1619 16:43:59.729003 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1620 16:43:59.732449 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1621 16:43:59.735522 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1622 16:43:59.735631
1623 16:43:59.735698
1624 16:43:59.735760 ==
1625 16:43:59.739042 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 16:43:59.745876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 16:43:59.745961 ==
1628 16:43:59.746027
1629 16:43:59.746088
1630 16:43:59.746165 TX Vref Scan disable
1631 16:43:59.748950 == TX Byte 0 ==
1632 16:43:59.752451 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1633 16:43:59.758933 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1634 16:43:59.759016 == TX Byte 1 ==
1635 16:43:59.762057 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1636 16:43:59.768945 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1637 16:43:59.769089 ==
1638 16:43:59.772056 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 16:43:59.775686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 16:43:59.775772 ==
1641 16:43:59.788295 TX Vref=22, minBit 1, minWin=26, winSum=436
1642 16:43:59.791208 TX Vref=24, minBit 0, minWin=27, winSum=441
1643 16:43:59.794843 TX Vref=26, minBit 1, minWin=27, winSum=441
1644 16:43:59.797912 TX Vref=28, minBit 1, minWin=27, winSum=443
1645 16:43:59.801509 TX Vref=30, minBit 5, minWin=27, winSum=447
1646 16:43:59.804886 TX Vref=32, minBit 0, minWin=27, winSum=445
1647 16:43:59.811156 [TxChooseVref] Worse bit 5, Min win 27, Win sum 447, Final Vref 30
1648 16:43:59.811241
1649 16:43:59.814754 Final TX Range 1 Vref 30
1650 16:43:59.814839
1651 16:43:59.814905 ==
1652 16:43:59.818291 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 16:43:59.821678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 16:43:59.821764 ==
1655 16:43:59.821830
1656 16:43:59.821892
1657 16:43:59.824757 TX Vref Scan disable
1658 16:43:59.827915 == TX Byte 0 ==
1659 16:43:59.831442 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1660 16:43:59.835040 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1661 16:43:59.838282 == TX Byte 1 ==
1662 16:43:59.841130 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1663 16:43:59.844629 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1664 16:43:59.848414
1665 16:43:59.848497 [DATLAT]
1666 16:43:59.848564 Freq=800, CH1 RK0
1667 16:43:59.848626
1668 16:43:59.851300 DATLAT Default: 0xa
1669 16:43:59.851383 0, 0xFFFF, sum = 0
1670 16:43:59.854505 1, 0xFFFF, sum = 0
1671 16:43:59.854590 2, 0xFFFF, sum = 0
1672 16:43:59.857921 3, 0xFFFF, sum = 0
1673 16:43:59.858013 4, 0xFFFF, sum = 0
1674 16:43:59.860935 5, 0xFFFF, sum = 0
1675 16:43:59.864593 6, 0xFFFF, sum = 0
1676 16:43:59.864677 7, 0xFFFF, sum = 0
1677 16:43:59.867702 8, 0xFFFF, sum = 0
1678 16:43:59.867786 9, 0x0, sum = 1
1679 16:43:59.867853 10, 0x0, sum = 2
1680 16:43:59.871031 11, 0x0, sum = 3
1681 16:43:59.871133 12, 0x0, sum = 4
1682 16:43:59.874149 best_step = 10
1683 16:43:59.874279
1684 16:43:59.874374 ==
1685 16:43:59.877732 Dram Type= 6, Freq= 0, CH_1, rank 0
1686 16:43:59.880809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1687 16:43:59.880887 ==
1688 16:43:59.884658 RX Vref Scan: 1
1689 16:43:59.884735
1690 16:43:59.887511 Set Vref Range= 32 -> 127
1691 16:43:59.887609
1692 16:43:59.887675 RX Vref 32 -> 127, step: 1
1693 16:43:59.887735
1694 16:43:59.890772 RX Delay -111 -> 252, step: 8
1695 16:43:59.890901
1696 16:43:59.894163 Set Vref, RX VrefLevel [Byte0]: 32
1697 16:43:59.897357 [Byte1]: 32
1698 16:43:59.900885
1699 16:43:59.901000 Set Vref, RX VrefLevel [Byte0]: 33
1700 16:43:59.903985 [Byte1]: 33
1701 16:43:59.908641
1702 16:43:59.908736 Set Vref, RX VrefLevel [Byte0]: 34
1703 16:43:59.911748 [Byte1]: 34
1704 16:43:59.915766
1705 16:43:59.915877 Set Vref, RX VrefLevel [Byte0]: 35
1706 16:43:59.919544 [Byte1]: 35
1707 16:43:59.923567
1708 16:43:59.923712 Set Vref, RX VrefLevel [Byte0]: 36
1709 16:43:59.926969 [Byte1]: 36
1710 16:43:59.931063
1711 16:43:59.931174 Set Vref, RX VrefLevel [Byte0]: 37
1712 16:43:59.934685 [Byte1]: 37
1713 16:43:59.939029
1714 16:43:59.939108 Set Vref, RX VrefLevel [Byte0]: 38
1715 16:43:59.942019 [Byte1]: 38
1716 16:43:59.946367
1717 16:43:59.946488 Set Vref, RX VrefLevel [Byte0]: 39
1718 16:43:59.949704 [Byte1]: 39
1719 16:43:59.954529
1720 16:43:59.954615 Set Vref, RX VrefLevel [Byte0]: 40
1721 16:43:59.957489 [Byte1]: 40
1722 16:43:59.961740
1723 16:43:59.961839 Set Vref, RX VrefLevel [Byte0]: 41
1724 16:43:59.965296 [Byte1]: 41
1725 16:43:59.969653
1726 16:43:59.969753 Set Vref, RX VrefLevel [Byte0]: 42
1727 16:43:59.972783 [Byte1]: 42
1728 16:43:59.976912
1729 16:43:59.976997 Set Vref, RX VrefLevel [Byte0]: 43
1730 16:43:59.980562 [Byte1]: 43
1731 16:43:59.984957
1732 16:43:59.985046 Set Vref, RX VrefLevel [Byte0]: 44
1733 16:43:59.987885 [Byte1]: 44
1734 16:43:59.992273
1735 16:43:59.992370 Set Vref, RX VrefLevel [Byte0]: 45
1736 16:43:59.996050 [Byte1]: 45
1737 16:44:00.000120
1738 16:44:00.000234 Set Vref, RX VrefLevel [Byte0]: 46
1739 16:44:00.003164 [Byte1]: 46
1740 16:44:00.007709
1741 16:44:00.007822 Set Vref, RX VrefLevel [Byte0]: 47
1742 16:44:00.011088 [Byte1]: 47
1743 16:44:00.015350
1744 16:44:00.015464 Set Vref, RX VrefLevel [Byte0]: 48
1745 16:44:00.018785 [Byte1]: 48
1746 16:44:00.022969
1747 16:44:00.023072 Set Vref, RX VrefLevel [Byte0]: 49
1748 16:44:00.026404 [Byte1]: 49
1749 16:44:00.030946
1750 16:44:00.031060 Set Vref, RX VrefLevel [Byte0]: 50
1751 16:44:00.034008 [Byte1]: 50
1752 16:44:00.038453
1753 16:44:00.038563 Set Vref, RX VrefLevel [Byte0]: 51
1754 16:44:00.041974 [Byte1]: 51
1755 16:44:00.046161
1756 16:44:00.046270 Set Vref, RX VrefLevel [Byte0]: 52
1757 16:44:00.049203 [Byte1]: 52
1758 16:44:00.053804
1759 16:44:00.053910 Set Vref, RX VrefLevel [Byte0]: 53
1760 16:44:00.060036 [Byte1]: 53
1761 16:44:00.060145
1762 16:44:00.063539 Set Vref, RX VrefLevel [Byte0]: 54
1763 16:44:00.066996 [Byte1]: 54
1764 16:44:00.067111
1765 16:44:00.069999 Set Vref, RX VrefLevel [Byte0]: 55
1766 16:44:00.073123 [Byte1]: 55
1767 16:44:00.076655
1768 16:44:00.076764 Set Vref, RX VrefLevel [Byte0]: 56
1769 16:44:00.079749 [Byte1]: 56
1770 16:44:00.084511
1771 16:44:00.084616 Set Vref, RX VrefLevel [Byte0]: 57
1772 16:44:00.087617 [Byte1]: 57
1773 16:44:00.091968
1774 16:44:00.092061 Set Vref, RX VrefLevel [Byte0]: 58
1775 16:44:00.095007 [Byte1]: 58
1776 16:44:00.099353
1777 16:44:00.099467 Set Vref, RX VrefLevel [Byte0]: 59
1778 16:44:00.103184 [Byte1]: 59
1779 16:44:00.107654
1780 16:44:00.107730 Set Vref, RX VrefLevel [Byte0]: 60
1781 16:44:00.110679 [Byte1]: 60
1782 16:44:00.114977
1783 16:44:00.115052 Set Vref, RX VrefLevel [Byte0]: 61
1784 16:44:00.117958 [Byte1]: 61
1785 16:44:00.122638
1786 16:44:00.122752 Set Vref, RX VrefLevel [Byte0]: 62
1787 16:44:00.125503 [Byte1]: 62
1788 16:44:00.130026
1789 16:44:00.130117 Set Vref, RX VrefLevel [Byte0]: 63
1790 16:44:00.133218 [Byte1]: 63
1791 16:44:00.137587
1792 16:44:00.137698 Set Vref, RX VrefLevel [Byte0]: 64
1793 16:44:00.140871 [Byte1]: 64
1794 16:44:00.145209
1795 16:44:00.145295 Set Vref, RX VrefLevel [Byte0]: 65
1796 16:44:00.148489 [Byte1]: 65
1797 16:44:00.153492
1798 16:44:00.153581 Set Vref, RX VrefLevel [Byte0]: 66
1799 16:44:00.159871 [Byte1]: 66
1800 16:44:00.159962
1801 16:44:00.162777 Set Vref, RX VrefLevel [Byte0]: 67
1802 16:44:00.166140 [Byte1]: 67
1803 16:44:00.166216
1804 16:44:00.169355 Set Vref, RX VrefLevel [Byte0]: 68
1805 16:44:00.173140 [Byte1]: 68
1806 16:44:00.173231
1807 16:44:00.176430 Set Vref, RX VrefLevel [Byte0]: 69
1808 16:44:00.179417 [Byte1]: 69
1809 16:44:00.183491
1810 16:44:00.183619 Set Vref, RX VrefLevel [Byte0]: 70
1811 16:44:00.187013 [Byte1]: 70
1812 16:44:00.191400
1813 16:44:00.191489 Set Vref, RX VrefLevel [Byte0]: 71
1814 16:44:00.194629 [Byte1]: 71
1815 16:44:00.199088
1816 16:44:00.199176 Set Vref, RX VrefLevel [Byte0]: 72
1817 16:44:00.202225 [Byte1]: 72
1818 16:44:00.206678
1819 16:44:00.206768 Set Vref, RX VrefLevel [Byte0]: 73
1820 16:44:00.210093 [Byte1]: 73
1821 16:44:00.214304
1822 16:44:00.214424 Final RX Vref Byte 0 = 59 to rank0
1823 16:44:00.217574 Final RX Vref Byte 1 = 57 to rank0
1824 16:44:00.220672 Final RX Vref Byte 0 = 59 to rank1
1825 16:44:00.224224 Final RX Vref Byte 1 = 57 to rank1==
1826 16:44:00.227791 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 16:44:00.234481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 16:44:00.234613 ==
1829 16:44:00.234688 DQS Delay:
1830 16:44:00.234755 DQS0 = 0, DQS1 = 0
1831 16:44:00.237354 DQM Delay:
1832 16:44:00.237468 DQM0 = 80, DQM1 = 70
1833 16:44:00.240971 DQ Delay:
1834 16:44:00.244146 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1835 16:44:00.247800 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1836 16:44:00.247909 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =64
1837 16:44:00.254063 DQ12 =76, DQ13 =76, DQ14 =76, DQ15 =76
1838 16:44:00.254172
1839 16:44:00.254285
1840 16:44:00.260954 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1841 16:44:00.263964 CH1 RK0: MR19=606, MR18=151F
1842 16:44:00.270596 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1843 16:44:00.270695
1844 16:44:00.273931 ----->DramcWriteLeveling(PI) begin...
1845 16:44:00.274064 ==
1846 16:44:00.277513 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 16:44:00.280770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 16:44:00.280895 ==
1849 16:44:00.283952 Write leveling (Byte 0): 27 => 27
1850 16:44:00.287061 Write leveling (Byte 1): 29 => 29
1851 16:44:00.290481 DramcWriteLeveling(PI) end<-----
1852 16:44:00.290602
1853 16:44:00.290707 ==
1854 16:44:00.293658 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 16:44:00.297318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 16:44:00.297404 ==
1857 16:44:00.300337 [Gating] SW mode calibration
1858 16:44:00.307111 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 16:44:00.313829 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 16:44:00.316862 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 16:44:00.323621 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1862 16:44:00.327203 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1863 16:44:00.330230 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 16:44:00.333350 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 16:44:00.340032 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 16:44:00.343282 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 16:44:00.346512 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 16:44:00.353233 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 16:44:00.356871 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 16:44:00.360260 0 7 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1871 16:44:00.366761 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 16:44:00.369898 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 16:44:00.373544 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 16:44:00.380072 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 16:44:00.383087 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 16:44:00.386577 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 16:44:00.393422 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1878 16:44:00.396238 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1879 16:44:00.399895 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 16:44:00.406659 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 16:44:00.409735 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:44:00.412798 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:44:00.419754 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:44:00.423299 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:44:00.426438 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1886 16:44:00.432652 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1887 16:44:00.436368 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 16:44:00.439409 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 16:44:00.445997 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 16:44:00.449688 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 16:44:00.452951 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 16:44:00.459385 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 16:44:00.462799 0 10 4 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 1)
1894 16:44:00.465945 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
1895 16:44:00.472634 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:44:00.476000 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 16:44:00.479909 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 16:44:00.486387 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 16:44:00.489549 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 16:44:00.492601 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1901 16:44:00.499346 0 11 4 | B1->B0 | 2d2d 3838 | 0 1 | (1 1) (0 0)
1902 16:44:00.502892 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1903 16:44:00.506168 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 16:44:00.512830 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 16:44:00.516149 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 16:44:00.519366 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 16:44:00.522654 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 16:44:00.529389 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 16:44:00.532429 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1910 16:44:00.536139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 16:44:00.542464 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 16:44:00.546432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 16:44:00.549282 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 16:44:00.555835 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 16:44:00.558936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 16:44:00.562481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 16:44:00.568831 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 16:44:00.572023 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 16:44:00.575732 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 16:44:00.582113 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 16:44:00.585360 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 16:44:00.588733 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 16:44:00.595495 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 16:44:00.598488 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 16:44:00.602040 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1926 16:44:00.608535 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 16:44:00.608644 Total UI for P1: 0, mck2ui 16
1928 16:44:00.615367 best dqsien dly found for B0: ( 0, 14, 4)
1929 16:44:00.615482 Total UI for P1: 0, mck2ui 16
1930 16:44:00.622103 best dqsien dly found for B1: ( 0, 14, 6)
1931 16:44:00.625187 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1932 16:44:00.628830 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1933 16:44:00.628932
1934 16:44:00.631938 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1935 16:44:00.635022 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1936 16:44:00.638524 [Gating] SW calibration Done
1937 16:44:00.638632 ==
1938 16:44:00.641707 Dram Type= 6, Freq= 0, CH_1, rank 1
1939 16:44:00.645243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1940 16:44:00.645339 ==
1941 16:44:00.648417 RX Vref Scan: 0
1942 16:44:00.648511
1943 16:44:00.648608 RX Vref 0 -> 0, step: 1
1944 16:44:00.648701
1945 16:44:00.651446 RX Delay -130 -> 252, step: 16
1946 16:44:00.654971 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1947 16:44:00.661557 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1948 16:44:00.665199 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1949 16:44:00.668062 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1950 16:44:00.671511 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1951 16:44:00.675080 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1952 16:44:00.681522 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1953 16:44:00.685127 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1954 16:44:00.688419 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1955 16:44:00.691515 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1956 16:44:00.695041 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1957 16:44:00.701536 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1958 16:44:00.704723 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1959 16:44:00.708175 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1960 16:44:00.711176 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1961 16:44:00.718314 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1962 16:44:00.718418 ==
1963 16:44:00.721130 Dram Type= 6, Freq= 0, CH_1, rank 1
1964 16:44:00.724614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1965 16:44:00.724716 ==
1966 16:44:00.724838 DQS Delay:
1967 16:44:00.728074 DQS0 = 0, DQS1 = 0
1968 16:44:00.728175 DQM Delay:
1969 16:44:00.731337 DQM0 = 77, DQM1 = 73
1970 16:44:00.731438 DQ Delay:
1971 16:44:00.734364 DQ0 =77, DQ1 =69, DQ2 =61, DQ3 =77
1972 16:44:00.738124 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1973 16:44:00.741056 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1974 16:44:00.744309 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1975 16:44:00.744410
1976 16:44:00.744539
1977 16:44:00.744642 ==
1978 16:44:00.747533 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 16:44:00.751067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 16:44:00.751154 ==
1981 16:44:00.751223
1982 16:44:00.754285
1983 16:44:00.754370 TX Vref Scan disable
1984 16:44:00.758073 == TX Byte 0 ==
1985 16:44:00.760803 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1986 16:44:00.764097 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1987 16:44:00.767754 == TX Byte 1 ==
1988 16:44:00.770954 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1989 16:44:00.774005 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1990 16:44:00.774094 ==
1991 16:44:00.777360 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 16:44:00.784174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 16:44:00.784263 ==
1994 16:44:00.796251 TX Vref=22, minBit 1, minWin=27, winSum=450
1995 16:44:00.799234 TX Vref=24, minBit 1, minWin=27, winSum=452
1996 16:44:00.802771 TX Vref=26, minBit 0, minWin=28, winSum=456
1997 16:44:00.805758 TX Vref=28, minBit 5, minWin=27, winSum=456
1998 16:44:00.809520 TX Vref=30, minBit 1, minWin=27, winSum=459
1999 16:44:00.816026 TX Vref=32, minBit 5, minWin=27, winSum=463
2000 16:44:00.819299 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
2001 16:44:00.819386
2002 16:44:00.822750 Final TX Range 1 Vref 26
2003 16:44:00.822837
2004 16:44:00.822906 ==
2005 16:44:00.825812 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 16:44:00.829266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 16:44:00.832350 ==
2008 16:44:00.832436
2009 16:44:00.832506
2010 16:44:00.832569 TX Vref Scan disable
2011 16:44:00.836279 == TX Byte 0 ==
2012 16:44:00.839380 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2013 16:44:00.846094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2014 16:44:00.846179 == TX Byte 1 ==
2015 16:44:00.849122 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2016 16:44:00.855889 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2017 16:44:00.855973
2018 16:44:00.856040 [DATLAT]
2019 16:44:00.856103 Freq=800, CH1 RK1
2020 16:44:00.856163
2021 16:44:00.858880 DATLAT Default: 0xa
2022 16:44:00.862627 0, 0xFFFF, sum = 0
2023 16:44:00.862742 1, 0xFFFF, sum = 0
2024 16:44:00.865501 2, 0xFFFF, sum = 0
2025 16:44:00.865586 3, 0xFFFF, sum = 0
2026 16:44:00.869035 4, 0xFFFF, sum = 0
2027 16:44:00.869120 5, 0xFFFF, sum = 0
2028 16:44:00.872004 6, 0xFFFF, sum = 0
2029 16:44:00.872091 7, 0xFFFF, sum = 0
2030 16:44:00.875879 8, 0xFFFF, sum = 0
2031 16:44:00.875966 9, 0x0, sum = 1
2032 16:44:00.878981 10, 0x0, sum = 2
2033 16:44:00.879082 11, 0x0, sum = 3
2034 16:44:00.882133 12, 0x0, sum = 4
2035 16:44:00.882218 best_step = 10
2036 16:44:00.882284
2037 16:44:00.882347 ==
2038 16:44:00.885599 Dram Type= 6, Freq= 0, CH_1, rank 1
2039 16:44:00.889012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2040 16:44:00.889096 ==
2041 16:44:00.892355 RX Vref Scan: 0
2042 16:44:00.892440
2043 16:44:00.895290 RX Vref 0 -> 0, step: 1
2044 16:44:00.895405
2045 16:44:00.895473 RX Delay -111 -> 252, step: 8
2046 16:44:00.903158 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
2047 16:44:00.906320 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2048 16:44:00.909365 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2049 16:44:00.912722 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2050 16:44:00.916399 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2051 16:44:00.922896 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2052 16:44:00.926219 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2053 16:44:00.929723 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2054 16:44:00.933047 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2055 16:44:00.936482 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2056 16:44:00.943007 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2057 16:44:00.946056 iDelay=209, Bit 11, Center 72 (-47 ~ 192) 240
2058 16:44:00.949156 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2059 16:44:00.952932 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2060 16:44:00.959489 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2061 16:44:00.962744 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2062 16:44:00.962823 ==
2063 16:44:00.965671 Dram Type= 6, Freq= 0, CH_1, rank 1
2064 16:44:00.969161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2065 16:44:00.969245 ==
2066 16:44:00.972633 DQS Delay:
2067 16:44:00.972718 DQS0 = 0, DQS1 = 0
2068 16:44:00.972785 DQM Delay:
2069 16:44:00.975574 DQM0 = 78, DQM1 = 74
2070 16:44:00.975702 DQ Delay:
2071 16:44:00.978828 DQ0 =80, DQ1 =72, DQ2 =68, DQ3 =76
2072 16:44:00.982308 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2073 16:44:00.986098 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =72
2074 16:44:00.988996 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2075 16:44:00.989074
2076 16:44:00.989144
2077 16:44:00.999397 [DQSOSCAuto] RK1, (LSB)MR18= 0x243c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2078 16:44:00.999490 CH1 RK1: MR19=606, MR18=243C
2079 16:44:01.005884 CH1_RK1: MR19=0x606, MR18=0x243C, DQSOSC=394, MR23=63, INC=95, DEC=63
2080 16:44:01.008891 [RxdqsGatingPostProcess] freq 800
2081 16:44:01.015511 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2082 16:44:01.019145 Pre-setting of DQS Precalculation
2083 16:44:01.022312 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2084 16:44:01.028900 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2085 16:44:01.038641 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2086 16:44:01.038808
2087 16:44:01.038908
2088 16:44:01.041982 [Calibration Summary] 1600 Mbps
2089 16:44:01.042064 CH 0, Rank 0
2090 16:44:01.045479 SW Impedance : PASS
2091 16:44:01.045561 DUTY Scan : NO K
2092 16:44:01.048297 ZQ Calibration : PASS
2093 16:44:01.051986 Jitter Meter : NO K
2094 16:44:01.052066 CBT Training : PASS
2095 16:44:01.055131 Write leveling : PASS
2096 16:44:01.058633 RX DQS gating : PASS
2097 16:44:01.058712 RX DQ/DQS(RDDQC) : PASS
2098 16:44:01.061864 TX DQ/DQS : PASS
2099 16:44:01.061945 RX DATLAT : PASS
2100 16:44:01.065110 RX DQ/DQS(Engine): PASS
2101 16:44:01.068726 TX OE : NO K
2102 16:44:01.068805 All Pass.
2103 16:44:01.068873
2104 16:44:01.068942 CH 0, Rank 1
2105 16:44:01.071733 SW Impedance : PASS
2106 16:44:01.075115 DUTY Scan : NO K
2107 16:44:01.075204 ZQ Calibration : PASS
2108 16:44:01.078357 Jitter Meter : NO K
2109 16:44:01.081481 CBT Training : PASS
2110 16:44:01.081567 Write leveling : PASS
2111 16:44:01.085348 RX DQS gating : PASS
2112 16:44:01.088424 RX DQ/DQS(RDDQC) : PASS
2113 16:44:01.088509 TX DQ/DQS : PASS
2114 16:44:01.091474 RX DATLAT : PASS
2115 16:44:01.095087 RX DQ/DQS(Engine): PASS
2116 16:44:01.095173 TX OE : NO K
2117 16:44:01.098035 All Pass.
2118 16:44:01.098121
2119 16:44:01.098190 CH 1, Rank 0
2120 16:44:01.101718 SW Impedance : PASS
2121 16:44:01.101825 DUTY Scan : NO K
2122 16:44:01.104647 ZQ Calibration : PASS
2123 16:44:01.108464 Jitter Meter : NO K
2124 16:44:01.108550 CBT Training : PASS
2125 16:44:01.111257 Write leveling : PASS
2126 16:44:01.114796 RX DQS gating : PASS
2127 16:44:01.114882 RX DQ/DQS(RDDQC) : PASS
2128 16:44:01.118432 TX DQ/DQS : PASS
2129 16:44:01.118534 RX DATLAT : PASS
2130 16:44:01.121285 RX DQ/DQS(Engine): PASS
2131 16:44:01.124904 TX OE : NO K
2132 16:44:01.124992 All Pass.
2133 16:44:01.125097
2134 16:44:01.125196 CH 1, Rank 1
2135 16:44:01.128043 SW Impedance : PASS
2136 16:44:01.131566 DUTY Scan : NO K
2137 16:44:01.131660 ZQ Calibration : PASS
2138 16:44:01.134625 Jitter Meter : NO K
2139 16:44:01.137842 CBT Training : PASS
2140 16:44:01.137959 Write leveling : PASS
2141 16:44:01.141595 RX DQS gating : PASS
2142 16:44:01.144427 RX DQ/DQS(RDDQC) : PASS
2143 16:44:01.144512 TX DQ/DQS : PASS
2144 16:44:01.147854 RX DATLAT : PASS
2145 16:44:01.151474 RX DQ/DQS(Engine): PASS
2146 16:44:01.151574 TX OE : NO K
2147 16:44:01.154478 All Pass.
2148 16:44:01.154564
2149 16:44:01.154633 DramC Write-DBI off
2150 16:44:01.158291 PER_BANK_REFRESH: Hybrid Mode
2151 16:44:01.158377 TX_TRACKING: ON
2152 16:44:01.161156 [GetDramInforAfterCalByMRR] Vendor 6.
2153 16:44:01.168004 [GetDramInforAfterCalByMRR] Revision 606.
2154 16:44:01.170962 [GetDramInforAfterCalByMRR] Revision 2 0.
2155 16:44:01.171048 MR0 0x3b3b
2156 16:44:01.171116 MR8 0x5151
2157 16:44:01.174721 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2158 16:44:01.174837
2159 16:44:01.177794 MR0 0x3b3b
2160 16:44:01.177879 MR8 0x5151
2161 16:44:01.181175 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2162 16:44:01.181261
2163 16:44:01.191194 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2164 16:44:01.194193 [FAST_K] Save calibration result to emmc
2165 16:44:01.197721 [FAST_K] Save calibration result to emmc
2166 16:44:01.200632 dram_init: config_dvfs: 1
2167 16:44:01.204066 dramc_set_vcore_voltage set vcore to 662500
2168 16:44:01.207261 Read voltage for 1200, 2
2169 16:44:01.207347 Vio18 = 0
2170 16:44:01.207416 Vcore = 662500
2171 16:44:01.211027 Vdram = 0
2172 16:44:01.211113 Vddq = 0
2173 16:44:01.211183 Vmddr = 0
2174 16:44:01.217045 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2175 16:44:01.220547 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2176 16:44:01.223969 MEM_TYPE=3, freq_sel=15
2177 16:44:01.227763 sv_algorithm_assistance_LP4_1600
2178 16:44:01.230663 ============ PULL DRAM RESETB DOWN ============
2179 16:44:01.236909 ========== PULL DRAM RESETB DOWN end =========
2180 16:44:01.240461 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2181 16:44:01.243821 ===================================
2182 16:44:01.246711 LPDDR4 DRAM CONFIGURATION
2183 16:44:01.250069 ===================================
2184 16:44:01.250183 EX_ROW_EN[0] = 0x0
2185 16:44:01.253464 EX_ROW_EN[1] = 0x0
2186 16:44:01.253570 LP4Y_EN = 0x0
2187 16:44:01.257114 WORK_FSP = 0x0
2188 16:44:01.257193 WL = 0x4
2189 16:44:01.260488 RL = 0x4
2190 16:44:01.260574 BL = 0x2
2191 16:44:01.263540 RPST = 0x0
2192 16:44:01.263659 RD_PRE = 0x0
2193 16:44:01.266672 WR_PRE = 0x1
2194 16:44:01.270363 WR_PST = 0x0
2195 16:44:01.270477 DBI_WR = 0x0
2196 16:44:01.273400 DBI_RD = 0x0
2197 16:44:01.273487 OTF = 0x1
2198 16:44:01.276421 ===================================
2199 16:44:01.280206 ===================================
2200 16:44:01.280288 ANA top config
2201 16:44:01.283046 ===================================
2202 16:44:01.286380 DLL_ASYNC_EN = 0
2203 16:44:01.290169 ALL_SLAVE_EN = 0
2204 16:44:01.293338 NEW_RANK_MODE = 1
2205 16:44:01.296361 DLL_IDLE_MODE = 1
2206 16:44:01.296440 LP45_APHY_COMB_EN = 1
2207 16:44:01.300041 TX_ODT_DIS = 1
2208 16:44:01.303568 NEW_8X_MODE = 1
2209 16:44:01.306477 ===================================
2210 16:44:01.309610 ===================================
2211 16:44:01.313239 data_rate = 2400
2212 16:44:01.316344 CKR = 1
2213 16:44:01.316426 DQ_P2S_RATIO = 8
2214 16:44:01.320022 ===================================
2215 16:44:01.322961 CA_P2S_RATIO = 8
2216 16:44:01.326339 DQ_CA_OPEN = 0
2217 16:44:01.329583 DQ_SEMI_OPEN = 0
2218 16:44:01.333235 CA_SEMI_OPEN = 0
2219 16:44:01.336497 CA_FULL_RATE = 0
2220 16:44:01.336584 DQ_CKDIV4_EN = 0
2221 16:44:01.339701 CA_CKDIV4_EN = 0
2222 16:44:01.342772 CA_PREDIV_EN = 0
2223 16:44:01.346257 PH8_DLY = 17
2224 16:44:01.349751 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2225 16:44:01.353142 DQ_AAMCK_DIV = 4
2226 16:44:01.355855 CA_AAMCK_DIV = 4
2227 16:44:01.355930 CA_ADMCK_DIV = 4
2228 16:44:01.359104 DQ_TRACK_CA_EN = 0
2229 16:44:01.362728 CA_PICK = 1200
2230 16:44:01.366174 CA_MCKIO = 1200
2231 16:44:01.369134 MCKIO_SEMI = 0
2232 16:44:01.372706 PLL_FREQ = 2366
2233 16:44:01.375778 DQ_UI_PI_RATIO = 32
2234 16:44:01.375864 CA_UI_PI_RATIO = 0
2235 16:44:01.379564 ===================================
2236 16:44:01.382640 ===================================
2237 16:44:01.386261 memory_type:LPDDR4
2238 16:44:01.389238 GP_NUM : 10
2239 16:44:01.389323 SRAM_EN : 1
2240 16:44:01.392956 MD32_EN : 0
2241 16:44:01.396051 ===================================
2242 16:44:01.399341 [ANA_INIT] >>>>>>>>>>>>>>
2243 16:44:01.402810 <<<<<< [CONFIGURE PHASE]: ANA_TX
2244 16:44:01.405870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2245 16:44:01.409099 ===================================
2246 16:44:01.409184 data_rate = 2400,PCW = 0X5b00
2247 16:44:01.412799 ===================================
2248 16:44:01.415835 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2249 16:44:01.422533 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2250 16:44:01.429116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 16:44:01.432139 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2252 16:44:01.435866 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2253 16:44:01.439236 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2254 16:44:01.442576 [ANA_INIT] flow start
2255 16:44:01.442679 [ANA_INIT] PLL >>>>>>>>
2256 16:44:01.445748 [ANA_INIT] PLL <<<<<<<<
2257 16:44:01.449251 [ANA_INIT] MIDPI >>>>>>>>
2258 16:44:01.452222 [ANA_INIT] MIDPI <<<<<<<<
2259 16:44:01.452325 [ANA_INIT] DLL >>>>>>>>
2260 16:44:01.456020 [ANA_INIT] DLL <<<<<<<<
2261 16:44:01.459254 [ANA_INIT] flow end
2262 16:44:01.462211 ============ LP4 DIFF to SE enter ============
2263 16:44:01.465807 ============ LP4 DIFF to SE exit ============
2264 16:44:01.468785 [ANA_INIT] <<<<<<<<<<<<<
2265 16:44:01.472446 [Flow] Enable top DCM control >>>>>
2266 16:44:01.475313 [Flow] Enable top DCM control <<<<<
2267 16:44:01.478995 Enable DLL master slave shuffle
2268 16:44:01.482085 ==============================================================
2269 16:44:01.485849 Gating Mode config
2270 16:44:01.488923 ==============================================================
2271 16:44:01.491864 Config description:
2272 16:44:01.502210 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2273 16:44:01.508442 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2274 16:44:01.512043 SELPH_MODE 0: By rank 1: By Phase
2275 16:44:01.518747 ==============================================================
2276 16:44:01.521873 GAT_TRACK_EN = 1
2277 16:44:01.524894 RX_GATING_MODE = 2
2278 16:44:01.528555 RX_GATING_TRACK_MODE = 2
2279 16:44:01.531679 SELPH_MODE = 1
2280 16:44:01.535043 PICG_EARLY_EN = 1
2281 16:44:01.538169 VALID_LAT_VALUE = 1
2282 16:44:01.541790 ==============================================================
2283 16:44:01.544838 Enter into Gating configuration >>>>
2284 16:44:01.548308 Exit from Gating configuration <<<<
2285 16:44:01.551704 Enter into DVFS_PRE_config >>>>>
2286 16:44:01.564864 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2287 16:44:01.564978 Exit from DVFS_PRE_config <<<<<
2288 16:44:01.568320 Enter into PICG configuration >>>>
2289 16:44:01.571247 Exit from PICG configuration <<<<
2290 16:44:01.574933 [RX_INPUT] configuration >>>>>
2291 16:44:01.578036 [RX_INPUT] configuration <<<<<
2292 16:44:01.585131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2293 16:44:01.588275 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2294 16:44:01.594901 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2295 16:44:01.601566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2296 16:44:01.608199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 16:44:01.615037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 16:44:01.617891 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2299 16:44:01.621655 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2300 16:44:01.624648 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2301 16:44:01.631474 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2302 16:44:01.634466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2303 16:44:01.638076 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2304 16:44:01.641174 ===================================
2305 16:44:01.644799 LPDDR4 DRAM CONFIGURATION
2306 16:44:01.648241 ===================================
2307 16:44:01.648322 EX_ROW_EN[0] = 0x0
2308 16:44:01.651210 EX_ROW_EN[1] = 0x0
2309 16:44:01.654193 LP4Y_EN = 0x0
2310 16:44:01.654270 WORK_FSP = 0x0
2311 16:44:01.657819 WL = 0x4
2312 16:44:01.657895 RL = 0x4
2313 16:44:01.661195 BL = 0x2
2314 16:44:01.661273 RPST = 0x0
2315 16:44:01.664739 RD_PRE = 0x0
2316 16:44:01.664816 WR_PRE = 0x1
2317 16:44:01.668094 WR_PST = 0x0
2318 16:44:01.668174 DBI_WR = 0x0
2319 16:44:01.671294 DBI_RD = 0x0
2320 16:44:01.671369 OTF = 0x1
2321 16:44:01.674531 ===================================
2322 16:44:01.677840 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2323 16:44:01.684494 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2324 16:44:01.687365 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2325 16:44:01.691096 ===================================
2326 16:44:01.694131 LPDDR4 DRAM CONFIGURATION
2327 16:44:01.697871 ===================================
2328 16:44:01.697964 EX_ROW_EN[0] = 0x10
2329 16:44:01.700826 EX_ROW_EN[1] = 0x0
2330 16:44:01.700914 LP4Y_EN = 0x0
2331 16:44:01.704467 WORK_FSP = 0x0
2332 16:44:01.707535 WL = 0x4
2333 16:44:01.707634 RL = 0x4
2334 16:44:01.711048 BL = 0x2
2335 16:44:01.711128 RPST = 0x0
2336 16:44:01.714171 RD_PRE = 0x0
2337 16:44:01.714244 WR_PRE = 0x1
2338 16:44:01.717822 WR_PST = 0x0
2339 16:44:01.717899 DBI_WR = 0x0
2340 16:44:01.720923 DBI_RD = 0x0
2341 16:44:01.721015 OTF = 0x1
2342 16:44:01.724385 ===================================
2343 16:44:01.730952 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2344 16:44:01.731035 ==
2345 16:44:01.734082 Dram Type= 6, Freq= 0, CH_0, rank 0
2346 16:44:01.737272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2347 16:44:01.737358 ==
2348 16:44:01.740871 [Duty_Offset_Calibration]
2349 16:44:01.743826 B0:2 B1:0 CA:3
2350 16:44:01.743903
2351 16:44:01.746991 [DutyScan_Calibration_Flow] k_type=0
2352 16:44:01.755480
2353 16:44:01.755596 ==CLK 0==
2354 16:44:01.759128 Final CLK duty delay cell = 0
2355 16:44:01.762289 [0] MAX Duty = 5062%(X100), DQS PI = 20
2356 16:44:01.765632 [0] MIN Duty = 4875%(X100), DQS PI = 58
2357 16:44:01.765708 [0] AVG Duty = 4968%(X100)
2358 16:44:01.768893
2359 16:44:01.772423 CH0 CLK Duty spec in!! Max-Min= 187%
2360 16:44:01.775367 [DutyScan_Calibration_Flow] ====Done====
2361 16:44:01.775486
2362 16:44:01.779257 [DutyScan_Calibration_Flow] k_type=1
2363 16:44:01.793813
2364 16:44:01.793909 ==DQS 0 ==
2365 16:44:01.797179 Final DQS duty delay cell = 0
2366 16:44:01.800972 [0] MAX Duty = 5062%(X100), DQS PI = 12
2367 16:44:01.803813 [0] MIN Duty = 4907%(X100), DQS PI = 46
2368 16:44:01.807403 [0] AVG Duty = 4984%(X100)
2369 16:44:01.807507
2370 16:44:01.807607 ==DQS 1 ==
2371 16:44:01.810929 Final DQS duty delay cell = -4
2372 16:44:01.813830 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2373 16:44:01.816953 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2374 16:44:01.820628 [-4] AVG Duty = 4937%(X100)
2375 16:44:01.820708
2376 16:44:01.823592 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2377 16:44:01.823686
2378 16:44:01.827190 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2379 16:44:01.830563 [DutyScan_Calibration_Flow] ====Done====
2380 16:44:01.830681
2381 16:44:01.833816 [DutyScan_Calibration_Flow] k_type=3
2382 16:44:01.851374
2383 16:44:01.851472 ==DQM 0 ==
2384 16:44:01.855193 Final DQM duty delay cell = 0
2385 16:44:01.858177 [0] MAX Duty = 5124%(X100), DQS PI = 12
2386 16:44:01.861677 [0] MIN Duty = 4876%(X100), DQS PI = 48
2387 16:44:01.864829 [0] AVG Duty = 5000%(X100)
2388 16:44:01.864945
2389 16:44:01.865015 ==DQM 1 ==
2390 16:44:01.868493 Final DQM duty delay cell = 4
2391 16:44:01.871655 [4] MAX Duty = 5124%(X100), DQS PI = 50
2392 16:44:01.874969 [4] MIN Duty = 5000%(X100), DQS PI = 32
2393 16:44:01.878326 [4] AVG Duty = 5062%(X100)
2394 16:44:01.878403
2395 16:44:01.881906 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2396 16:44:01.881983
2397 16:44:01.884665 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2398 16:44:01.888262 [DutyScan_Calibration_Flow] ====Done====
2399 16:44:01.888337
2400 16:44:01.891557 [DutyScan_Calibration_Flow] k_type=2
2401 16:44:01.906455
2402 16:44:01.906549 ==DQ 0 ==
2403 16:44:01.909567 Final DQ duty delay cell = -4
2404 16:44:01.913060 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2405 16:44:01.916676 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2406 16:44:01.919932 [-4] AVG Duty = 4969%(X100)
2407 16:44:01.920016
2408 16:44:01.920102 ==DQ 1 ==
2409 16:44:01.922977 Final DQ duty delay cell = -4
2410 16:44:01.926146 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2411 16:44:01.929725 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2412 16:44:01.933021 [-4] AVG Duty = 4922%(X100)
2413 16:44:01.933102
2414 16:44:01.936594 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2415 16:44:01.936672
2416 16:44:01.939676 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2417 16:44:01.942822 [DutyScan_Calibration_Flow] ====Done====
2418 16:44:01.942906 ==
2419 16:44:01.946565 Dram Type= 6, Freq= 0, CH_1, rank 0
2420 16:44:01.949680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2421 16:44:01.949779 ==
2422 16:44:01.953103 [Duty_Offset_Calibration]
2423 16:44:01.953190 B0:1 B1:-2 CA:0
2424 16:44:01.953258
2425 16:44:01.956286 [DutyScan_Calibration_Flow] k_type=0
2426 16:44:01.967225
2427 16:44:01.967305 ==CLK 0==
2428 16:44:01.970675 Final CLK duty delay cell = 0
2429 16:44:01.973773 [0] MAX Duty = 5031%(X100), DQS PI = 20
2430 16:44:01.976978 [0] MIN Duty = 4844%(X100), DQS PI = 60
2431 16:44:01.977059 [0] AVG Duty = 4937%(X100)
2432 16:44:01.980036
2433 16:44:01.983394 CH1 CLK Duty spec in!! Max-Min= 187%
2434 16:44:01.987149 [DutyScan_Calibration_Flow] ====Done====
2435 16:44:01.987255
2436 16:44:01.990576 [DutyScan_Calibration_Flow] k_type=1
2437 16:44:02.005777
2438 16:44:02.005861 ==DQS 0 ==
2439 16:44:02.009228 Final DQS duty delay cell = -4
2440 16:44:02.012147 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2441 16:44:02.015851 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2442 16:44:02.018801 [-4] AVG Duty = 4969%(X100)
2443 16:44:02.018876
2444 16:44:02.018940 ==DQS 1 ==
2445 16:44:02.022520 Final DQS duty delay cell = 0
2446 16:44:02.025650 [0] MAX Duty = 5093%(X100), DQS PI = 0
2447 16:44:02.028825 [0] MIN Duty = 4875%(X100), DQS PI = 26
2448 16:44:02.031829 [0] AVG Duty = 4984%(X100)
2449 16:44:02.031916
2450 16:44:02.035312 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2451 16:44:02.035399
2452 16:44:02.038691 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2453 16:44:02.041749 [DutyScan_Calibration_Flow] ====Done====
2454 16:44:02.041836
2455 16:44:02.045005 [DutyScan_Calibration_Flow] k_type=3
2456 16:44:02.062850
2457 16:44:02.062935 ==DQM 0 ==
2458 16:44:02.066312 Final DQM duty delay cell = 4
2459 16:44:02.069610 [4] MAX Duty = 5156%(X100), DQS PI = 20
2460 16:44:02.073162 [4] MIN Duty = 5031%(X100), DQS PI = 52
2461 16:44:02.076784 [4] AVG Duty = 5093%(X100)
2462 16:44:02.076918
2463 16:44:02.077028 ==DQM 1 ==
2464 16:44:02.079834 Final DQM duty delay cell = 0
2465 16:44:02.082895 [0] MAX Duty = 5031%(X100), DQS PI = 36
2466 16:44:02.086532 [0] MIN Duty = 4907%(X100), DQS PI = 4
2467 16:44:02.089426 [0] AVG Duty = 4969%(X100)
2468 16:44:02.089605
2469 16:44:02.092897 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2470 16:44:02.092983
2471 16:44:02.096338 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2472 16:44:02.099803 [DutyScan_Calibration_Flow] ====Done====
2473 16:44:02.099889
2474 16:44:02.102532 [DutyScan_Calibration_Flow] k_type=2
2475 16:44:02.119503
2476 16:44:02.119608 ==DQ 0 ==
2477 16:44:02.122788 Final DQ duty delay cell = 0
2478 16:44:02.125879 [0] MAX Duty = 5093%(X100), DQS PI = 28
2479 16:44:02.128949 [0] MIN Duty = 4907%(X100), DQS PI = 54
2480 16:44:02.132774 [0] AVG Duty = 5000%(X100)
2481 16:44:02.132869
2482 16:44:02.132939 ==DQ 1 ==
2483 16:44:02.135762 Final DQ duty delay cell = 0
2484 16:44:02.139350 [0] MAX Duty = 5125%(X100), DQS PI = 36
2485 16:44:02.142264 [0] MIN Duty = 4969%(X100), DQS PI = 26
2486 16:44:02.142352 [0] AVG Duty = 5047%(X100)
2487 16:44:02.145846
2488 16:44:02.148969 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2489 16:44:02.149055
2490 16:44:02.152569 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2491 16:44:02.155781 [DutyScan_Calibration_Flow] ====Done====
2492 16:44:02.159253 nWR fixed to 30
2493 16:44:02.159344 [ModeRegInit_LP4] CH0 RK0
2494 16:44:02.162263 [ModeRegInit_LP4] CH0 RK1
2495 16:44:02.165909 [ModeRegInit_LP4] CH1 RK0
2496 16:44:02.169026 [ModeRegInit_LP4] CH1 RK1
2497 16:44:02.169113 match AC timing 7
2498 16:44:02.175674 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2499 16:44:02.178902 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2500 16:44:02.182095 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2501 16:44:02.188780 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2502 16:44:02.192354 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2503 16:44:02.192442 ==
2504 16:44:02.195388 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 16:44:02.198897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 16:44:02.199008 ==
2507 16:44:02.205355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2508 16:44:02.212055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2509 16:44:02.219485 [CA 0] Center 40 (10~71) winsize 62
2510 16:44:02.222597 [CA 1] Center 39 (9~70) winsize 62
2511 16:44:02.225929 [CA 2] Center 36 (6~66) winsize 61
2512 16:44:02.229145 [CA 3] Center 35 (5~66) winsize 62
2513 16:44:02.232640 [CA 4] Center 34 (4~65) winsize 62
2514 16:44:02.236334 [CA 5] Center 33 (3~63) winsize 61
2515 16:44:02.236448
2516 16:44:02.239297 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2517 16:44:02.239410
2518 16:44:02.242574 [CATrainingPosCal] consider 1 rank data
2519 16:44:02.246092 u2DelayCellTimex100 = 270/100 ps
2520 16:44:02.249566 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2521 16:44:02.255645 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2522 16:44:02.258950 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2523 16:44:02.262344 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2524 16:44:02.266063 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2525 16:44:02.269339 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2526 16:44:02.269458
2527 16:44:02.272368 CA PerBit enable=1, Macro0, CA PI delay=33
2528 16:44:02.272475
2529 16:44:02.275447 [CBTSetCACLKResult] CA Dly = 33
2530 16:44:02.279090 CS Dly: 7 (0~38)
2531 16:44:02.279204 ==
2532 16:44:02.281973 Dram Type= 6, Freq= 0, CH_0, rank 1
2533 16:44:02.285854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 16:44:02.285966 ==
2535 16:44:02.292582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2536 16:44:02.295615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2537 16:44:02.305886 [CA 0] Center 40 (10~70) winsize 61
2538 16:44:02.308831 [CA 1] Center 39 (9~70) winsize 62
2539 16:44:02.311793 [CA 2] Center 35 (5~66) winsize 62
2540 16:44:02.315128 [CA 3] Center 35 (5~66) winsize 62
2541 16:44:02.318876 [CA 4] Center 34 (3~65) winsize 63
2542 16:44:02.322195 [CA 5] Center 33 (3~64) winsize 62
2543 16:44:02.322305
2544 16:44:02.325324 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2545 16:44:02.325439
2546 16:44:02.328522 [CATrainingPosCal] consider 2 rank data
2547 16:44:02.331820 u2DelayCellTimex100 = 270/100 ps
2548 16:44:02.335481 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2549 16:44:02.342187 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 16:44:02.345204 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2551 16:44:02.348839 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 16:44:02.351990 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2553 16:44:02.355482 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2554 16:44:02.355601
2555 16:44:02.358590 CA PerBit enable=1, Macro0, CA PI delay=33
2556 16:44:02.358700
2557 16:44:02.362251 [CBTSetCACLKResult] CA Dly = 33
2558 16:44:02.365167 CS Dly: 8 (0~40)
2559 16:44:02.365278
2560 16:44:02.368636 ----->DramcWriteLeveling(PI) begin...
2561 16:44:02.368746 ==
2562 16:44:02.371591 Dram Type= 6, Freq= 0, CH_0, rank 0
2563 16:44:02.375215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2564 16:44:02.375330 ==
2565 16:44:02.378203 Write leveling (Byte 0): 32 => 32
2566 16:44:02.381905 Write leveling (Byte 1): 30 => 30
2567 16:44:02.384937 DramcWriteLeveling(PI) end<-----
2568 16:44:02.385052
2569 16:44:02.385168 ==
2570 16:44:02.388593 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 16:44:02.391604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 16:44:02.391724 ==
2573 16:44:02.395151 [Gating] SW mode calibration
2574 16:44:02.401339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2575 16:44:02.408498 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2576 16:44:02.411472 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2577 16:44:02.415287 0 15 4 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 1)
2578 16:44:02.421704 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 16:44:02.425025 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2580 16:44:02.428532 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 16:44:02.434795 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 16:44:02.438355 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 16:44:02.441185 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 16:44:02.448241 1 0 0 | B1->B0 | 3232 2828 | 1 0 | (1 1) (0 0)
2585 16:44:02.451551 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2586 16:44:02.454429 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 16:44:02.460988 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 16:44:02.464740 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 16:44:02.467717 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 16:44:02.474709 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 16:44:02.477823 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2592 16:44:02.480867 1 1 0 | B1->B0 | 2b2b 3636 | 0 1 | (0 0) (0 0)
2593 16:44:02.487481 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 16:44:02.491027 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 16:44:02.494064 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 16:44:02.500748 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 16:44:02.504026 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 16:44:02.507640 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 16:44:02.513871 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 16:44:02.517811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2601 16:44:02.520935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2602 16:44:02.527605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 16:44:02.530964 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 16:44:02.534556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 16:44:02.537385 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 16:44:02.544316 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 16:44:02.547306 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 16:44:02.550791 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 16:44:02.557314 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 16:44:02.560843 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 16:44:02.564338 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 16:44:02.570702 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 16:44:02.574324 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 16:44:02.577344 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 16:44:02.584153 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2616 16:44:02.587224 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2617 16:44:02.590810 Total UI for P1: 0, mck2ui 16
2618 16:44:02.593988 best dqsien dly found for B0: ( 1, 3, 28)
2619 16:44:02.596967 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 16:44:02.600740 Total UI for P1: 0, mck2ui 16
2621 16:44:02.603731 best dqsien dly found for B1: ( 1, 4, 0)
2622 16:44:02.607049 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2623 16:44:02.610639 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2624 16:44:02.610752
2625 16:44:02.617066 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2626 16:44:02.620253 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2627 16:44:02.620340 [Gating] SW calibration Done
2628 16:44:02.624033 ==
2629 16:44:02.627100 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 16:44:02.630166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 16:44:02.630273 ==
2632 16:44:02.630369 RX Vref Scan: 0
2633 16:44:02.630461
2634 16:44:02.633565 RX Vref 0 -> 0, step: 1
2635 16:44:02.633664
2636 16:44:02.636748 RX Delay -40 -> 252, step: 8
2637 16:44:02.640348 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2638 16:44:02.643300 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2639 16:44:02.650003 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2640 16:44:02.653270 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2641 16:44:02.656642 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2642 16:44:02.660314 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2643 16:44:02.663258 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2644 16:44:02.670028 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2645 16:44:02.673087 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2646 16:44:02.676674 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2647 16:44:02.679825 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2648 16:44:02.683239 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2649 16:44:02.686564 iDelay=200, Bit 12, Center 103 (32 ~ 175) 144
2650 16:44:02.693150 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2651 16:44:02.696782 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2652 16:44:02.699536 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2653 16:44:02.699668 ==
2654 16:44:02.703286 Dram Type= 6, Freq= 0, CH_0, rank 0
2655 16:44:02.706277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2656 16:44:02.709609 ==
2657 16:44:02.709693 DQS Delay:
2658 16:44:02.709760 DQS0 = 0, DQS1 = 0
2659 16:44:02.713058 DQM Delay:
2660 16:44:02.713142 DQM0 = 112, DQM1 = 101
2661 16:44:02.716853 DQ Delay:
2662 16:44:02.719919 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2663 16:44:02.722874 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2664 16:44:02.726481 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2665 16:44:02.729569 DQ12 =103, DQ13 =107, DQ14 =115, DQ15 =111
2666 16:44:02.729654
2667 16:44:02.729725
2668 16:44:02.729789 ==
2669 16:44:02.733360 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 16:44:02.736508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 16:44:02.736593 ==
2672 16:44:02.736661
2673 16:44:02.736775
2674 16:44:02.739823 TX Vref Scan disable
2675 16:44:02.742860 == TX Byte 0 ==
2676 16:44:02.746380 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2677 16:44:02.749873 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2678 16:44:02.753231 == TX Byte 1 ==
2679 16:44:02.756138 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2680 16:44:02.759607 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2681 16:44:02.759705 ==
2682 16:44:02.762890 Dram Type= 6, Freq= 0, CH_0, rank 0
2683 16:44:02.766220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2684 16:44:02.769456 ==
2685 16:44:02.779830 TX Vref=22, minBit 4, minWin=25, winSum=414
2686 16:44:02.783293 TX Vref=24, minBit 14, minWin=25, winSum=421
2687 16:44:02.786441 TX Vref=26, minBit 7, minWin=26, winSum=430
2688 16:44:02.789817 TX Vref=28, minBit 10, minWin=26, winSum=432
2689 16:44:02.792864 TX Vref=30, minBit 0, minWin=27, winSum=435
2690 16:44:02.799731 TX Vref=32, minBit 2, minWin=26, winSum=429
2691 16:44:02.802789 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 30
2692 16:44:02.802888
2693 16:44:02.806122 Final TX Range 1 Vref 30
2694 16:44:02.806223
2695 16:44:02.806297 ==
2696 16:44:02.809334 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 16:44:02.812835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 16:44:02.816137 ==
2699 16:44:02.816215
2700 16:44:02.816285
2701 16:44:02.816367 TX Vref Scan disable
2702 16:44:02.819727 == TX Byte 0 ==
2703 16:44:02.822866 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2704 16:44:02.829881 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2705 16:44:02.829988 == TX Byte 1 ==
2706 16:44:02.833365 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2707 16:44:02.839485 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2708 16:44:02.839609
2709 16:44:02.839708 [DATLAT]
2710 16:44:02.839812 Freq=1200, CH0 RK0
2711 16:44:02.839907
2712 16:44:02.842987 DATLAT Default: 0xd
2713 16:44:02.843067 0, 0xFFFF, sum = 0
2714 16:44:02.845993 1, 0xFFFF, sum = 0
2715 16:44:02.849592 2, 0xFFFF, sum = 0
2716 16:44:02.849672 3, 0xFFFF, sum = 0
2717 16:44:02.852709 4, 0xFFFF, sum = 0
2718 16:44:02.852783 5, 0xFFFF, sum = 0
2719 16:44:02.856229 6, 0xFFFF, sum = 0
2720 16:44:02.856305 7, 0xFFFF, sum = 0
2721 16:44:02.859537 8, 0xFFFF, sum = 0
2722 16:44:02.859632 9, 0xFFFF, sum = 0
2723 16:44:02.862409 10, 0xFFFF, sum = 0
2724 16:44:02.862483 11, 0xFFFF, sum = 0
2725 16:44:02.865794 12, 0x0, sum = 1
2726 16:44:02.865872 13, 0x0, sum = 2
2727 16:44:02.869038 14, 0x0, sum = 3
2728 16:44:02.869118 15, 0x0, sum = 4
2729 16:44:02.872204 best_step = 13
2730 16:44:02.872282
2731 16:44:02.872374 ==
2732 16:44:02.876027 Dram Type= 6, Freq= 0, CH_0, rank 0
2733 16:44:02.879018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2734 16:44:02.879100 ==
2735 16:44:02.882284 RX Vref Scan: 1
2736 16:44:02.882361
2737 16:44:02.882431 Set Vref Range= 32 -> 127
2738 16:44:02.882495
2739 16:44:02.885623 RX Vref 32 -> 127, step: 1
2740 16:44:02.885703
2741 16:44:02.889111 RX Delay -37 -> 252, step: 4
2742 16:44:02.889190
2743 16:44:02.892072 Set Vref, RX VrefLevel [Byte0]: 32
2744 16:44:02.895576 [Byte1]: 32
2745 16:44:02.895719
2746 16:44:02.899078 Set Vref, RX VrefLevel [Byte0]: 33
2747 16:44:02.902221 [Byte1]: 33
2748 16:44:02.906308
2749 16:44:02.906385 Set Vref, RX VrefLevel [Byte0]: 34
2750 16:44:02.909867 [Byte1]: 34
2751 16:44:02.914294
2752 16:44:02.914375 Set Vref, RX VrefLevel [Byte0]: 35
2753 16:44:02.917877 [Byte1]: 35
2754 16:44:02.922267
2755 16:44:02.922347 Set Vref, RX VrefLevel [Byte0]: 36
2756 16:44:02.925365 [Byte1]: 36
2757 16:44:02.930125
2758 16:44:02.930206 Set Vref, RX VrefLevel [Byte0]: 37
2759 16:44:02.933907 [Byte1]: 37
2760 16:44:02.938169
2761 16:44:02.938249 Set Vref, RX VrefLevel [Byte0]: 38
2762 16:44:02.941917 [Byte1]: 38
2763 16:44:02.946221
2764 16:44:02.946305 Set Vref, RX VrefLevel [Byte0]: 39
2765 16:44:02.949605 [Byte1]: 39
2766 16:44:02.954373
2767 16:44:02.954461 Set Vref, RX VrefLevel [Byte0]: 40
2768 16:44:02.957424 [Byte1]: 40
2769 16:44:02.962408
2770 16:44:02.962499 Set Vref, RX VrefLevel [Byte0]: 41
2771 16:44:02.965856 [Byte1]: 41
2772 16:44:02.970415
2773 16:44:02.970503 Set Vref, RX VrefLevel [Byte0]: 42
2774 16:44:02.973429 [Byte1]: 42
2775 16:44:02.978111
2776 16:44:02.978203 Set Vref, RX VrefLevel [Byte0]: 43
2777 16:44:02.981698 [Byte1]: 43
2778 16:44:02.986255
2779 16:44:02.986346 Set Vref, RX VrefLevel [Byte0]: 44
2780 16:44:02.989894 [Byte1]: 44
2781 16:44:02.994564
2782 16:44:02.994663 Set Vref, RX VrefLevel [Byte0]: 45
2783 16:44:02.997655 [Byte1]: 45
2784 16:44:03.002179
2785 16:44:03.002260 Set Vref, RX VrefLevel [Byte0]: 46
2786 16:44:03.005826 [Byte1]: 46
2787 16:44:03.010662
2788 16:44:03.010743 Set Vref, RX VrefLevel [Byte0]: 47
2789 16:44:03.013783 [Byte1]: 47
2790 16:44:03.018078
2791 16:44:03.018169 Set Vref, RX VrefLevel [Byte0]: 48
2792 16:44:03.021692 [Byte1]: 48
2793 16:44:03.026596
2794 16:44:03.026709 Set Vref, RX VrefLevel [Byte0]: 49
2795 16:44:03.029627 [Byte1]: 49
2796 16:44:03.034411
2797 16:44:03.034490 Set Vref, RX VrefLevel [Byte0]: 50
2798 16:44:03.037397 [Byte1]: 50
2799 16:44:03.042296
2800 16:44:03.042376 Set Vref, RX VrefLevel [Byte0]: 51
2801 16:44:03.045638 [Byte1]: 51
2802 16:44:03.050405
2803 16:44:03.050488 Set Vref, RX VrefLevel [Byte0]: 52
2804 16:44:03.053987 [Byte1]: 52
2805 16:44:03.058243
2806 16:44:03.058324 Set Vref, RX VrefLevel [Byte0]: 53
2807 16:44:03.061499 [Byte1]: 53
2808 16:44:03.066296
2809 16:44:03.066399 Set Vref, RX VrefLevel [Byte0]: 54
2810 16:44:03.069332 [Byte1]: 54
2811 16:44:03.074124
2812 16:44:03.074207 Set Vref, RX VrefLevel [Byte0]: 55
2813 16:44:03.077621 [Byte1]: 55
2814 16:44:03.082041
2815 16:44:03.082127 Set Vref, RX VrefLevel [Byte0]: 56
2816 16:44:03.085398 [Byte1]: 56
2817 16:44:03.090152
2818 16:44:03.090231 Set Vref, RX VrefLevel [Byte0]: 57
2819 16:44:03.093724 [Byte1]: 57
2820 16:44:03.098588
2821 16:44:03.101498 Set Vref, RX VrefLevel [Byte0]: 58
2822 16:44:03.104797 [Byte1]: 58
2823 16:44:03.104878
2824 16:44:03.107730 Set Vref, RX VrefLevel [Byte0]: 59
2825 16:44:03.111188 [Byte1]: 59
2826 16:44:03.111266
2827 16:44:03.115074 Set Vref, RX VrefLevel [Byte0]: 60
2828 16:44:03.118020 [Byte1]: 60
2829 16:44:03.122159
2830 16:44:03.122240 Set Vref, RX VrefLevel [Byte0]: 61
2831 16:44:03.125753 [Byte1]: 61
2832 16:44:03.130460
2833 16:44:03.130546 Set Vref, RX VrefLevel [Byte0]: 62
2834 16:44:03.136717 [Byte1]: 62
2835 16:44:03.136798
2836 16:44:03.140141 Set Vref, RX VrefLevel [Byte0]: 63
2837 16:44:03.143133 [Byte1]: 63
2838 16:44:03.143212
2839 16:44:03.146890 Set Vref, RX VrefLevel [Byte0]: 64
2840 16:44:03.150059 [Byte1]: 64
2841 16:44:03.154302
2842 16:44:03.154484 Set Vref, RX VrefLevel [Byte0]: 65
2843 16:44:03.157814 [Byte1]: 65
2844 16:44:03.162149
2845 16:44:03.162309 Set Vref, RX VrefLevel [Byte0]: 66
2846 16:44:03.165735 [Byte1]: 66
2847 16:44:03.170001
2848 16:44:03.170081 Set Vref, RX VrefLevel [Byte0]: 67
2849 16:44:03.173725 [Byte1]: 67
2850 16:44:03.178577
2851 16:44:03.178663 Set Vref, RX VrefLevel [Byte0]: 68
2852 16:44:03.181466 [Byte1]: 68
2853 16:44:03.186281
2854 16:44:03.186392 Set Vref, RX VrefLevel [Byte0]: 69
2855 16:44:03.189598 [Byte1]: 69
2856 16:44:03.194086
2857 16:44:03.194176 Set Vref, RX VrefLevel [Byte0]: 70
2858 16:44:03.197640 [Byte1]: 70
2859 16:44:03.202765
2860 16:44:03.202854 Set Vref, RX VrefLevel [Byte0]: 71
2861 16:44:03.205410 [Byte1]: 71
2862 16:44:03.210081
2863 16:44:03.210167 Set Vref, RX VrefLevel [Byte0]: 72
2864 16:44:03.213617 [Byte1]: 72
2865 16:44:03.218294
2866 16:44:03.218378 Set Vref, RX VrefLevel [Byte0]: 73
2867 16:44:03.221880 [Byte1]: 73
2868 16:44:03.226650
2869 16:44:03.226759 Set Vref, RX VrefLevel [Byte0]: 74
2870 16:44:03.229614 [Byte1]: 74
2871 16:44:03.234557
2872 16:44:03.234645 Final RX Vref Byte 0 = 60 to rank0
2873 16:44:03.237626 Final RX Vref Byte 1 = 55 to rank0
2874 16:44:03.241400 Final RX Vref Byte 0 = 60 to rank1
2875 16:44:03.244228 Final RX Vref Byte 1 = 55 to rank1==
2876 16:44:03.247775 Dram Type= 6, Freq= 0, CH_0, rank 0
2877 16:44:03.254031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2878 16:44:03.254116 ==
2879 16:44:03.254184 DQS Delay:
2880 16:44:03.257908 DQS0 = 0, DQS1 = 0
2881 16:44:03.257993 DQM Delay:
2882 16:44:03.258060 DQM0 = 112, DQM1 = 102
2883 16:44:03.260794 DQ Delay:
2884 16:44:03.264425 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2885 16:44:03.267381 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =122
2886 16:44:03.271142 DQ8 =94, DQ9 =86, DQ10 =102, DQ11 =94
2887 16:44:03.274042 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2888 16:44:03.274132
2889 16:44:03.274200
2890 16:44:03.283789 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2891 16:44:03.283908 CH0 RK0: MR19=303, MR18=FBFB
2892 16:44:03.290815 CH0_RK0: MR19=0x303, MR18=0xFBFB, DQSOSC=412, MR23=63, INC=38, DEC=25
2893 16:44:03.290909
2894 16:44:03.293681 ----->DramcWriteLeveling(PI) begin...
2895 16:44:03.293771 ==
2896 16:44:03.296963 Dram Type= 6, Freq= 0, CH_0, rank 1
2897 16:44:03.303829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2898 16:44:03.303912 ==
2899 16:44:03.307524 Write leveling (Byte 0): 34 => 34
2900 16:44:03.307628 Write leveling (Byte 1): 29 => 29
2901 16:44:03.310551 DramcWriteLeveling(PI) end<-----
2902 16:44:03.310635
2903 16:44:03.313441 ==
2904 16:44:03.313520 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 16:44:03.320253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 16:44:03.320344 ==
2907 16:44:03.323941 [Gating] SW mode calibration
2908 16:44:03.330030 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2909 16:44:03.333291 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2910 16:44:03.340142 0 15 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
2911 16:44:03.343192 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 16:44:03.346751 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2913 16:44:03.353581 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 16:44:03.356650 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 16:44:03.360344 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 16:44:03.366871 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
2917 16:44:03.369897 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2918 16:44:03.373630 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2919 16:44:03.379884 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 16:44:03.383393 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 16:44:03.386616 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 16:44:03.393065 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 16:44:03.396526 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 16:44:03.399499 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2925 16:44:03.406324 1 0 28 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
2926 16:44:03.409585 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2927 16:44:03.412785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 16:44:03.419756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 16:44:03.423363 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 16:44:03.426106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 16:44:03.432846 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 16:44:03.436449 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 16:44:03.439291 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2934 16:44:03.442990 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2935 16:44:03.449872 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 16:44:03.452944 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 16:44:03.455925 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 16:44:03.462677 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:44:03.466519 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:44:03.469282 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:44:03.476078 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:44:03.479109 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 16:44:03.482682 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 16:44:03.488901 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 16:44:03.492662 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 16:44:03.495787 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 16:44:03.502108 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 16:44:03.505551 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2949 16:44:03.508835 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2950 16:44:03.515748 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2951 16:44:03.518670 Total UI for P1: 0, mck2ui 16
2952 16:44:03.522104 best dqsien dly found for B0: ( 1, 3, 26)
2953 16:44:03.525788 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2954 16:44:03.528650 Total UI for P1: 0, mck2ui 16
2955 16:44:03.532579 best dqsien dly found for B1: ( 1, 4, 0)
2956 16:44:03.535437 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2957 16:44:03.538891 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2958 16:44:03.539002
2959 16:44:03.542260 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2960 16:44:03.545400 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2961 16:44:03.548727 [Gating] SW calibration Done
2962 16:44:03.548835 ==
2963 16:44:03.552375 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 16:44:03.555795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 16:44:03.558827 ==
2966 16:44:03.558914 RX Vref Scan: 0
2967 16:44:03.558999
2968 16:44:03.561799 RX Vref 0 -> 0, step: 1
2969 16:44:03.561902
2970 16:44:03.565555 RX Delay -40 -> 252, step: 8
2971 16:44:03.568605 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2972 16:44:03.572026 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2973 16:44:03.575020 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2974 16:44:03.578542 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2975 16:44:03.585345 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2976 16:44:03.588403 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2977 16:44:03.592238 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2978 16:44:03.595281 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2979 16:44:03.598411 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2980 16:44:03.605106 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2981 16:44:03.608270 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2982 16:44:03.611728 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2983 16:44:03.615226 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2984 16:44:03.618177 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2985 16:44:03.624847 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2986 16:44:03.628103 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2987 16:44:03.628215 ==
2988 16:44:03.631323 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 16:44:03.634873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 16:44:03.634990 ==
2991 16:44:03.638242 DQS Delay:
2992 16:44:03.638346 DQS0 = 0, DQS1 = 0
2993 16:44:03.638444 DQM Delay:
2994 16:44:03.641573 DQM0 = 113, DQM1 = 101
2995 16:44:03.641678 DQ Delay:
2996 16:44:03.645202 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2997 16:44:03.648087 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2998 16:44:03.651123 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2999 16:44:03.657911 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3000 16:44:03.658019
3001 16:44:03.658117
3002 16:44:03.658207 ==
3003 16:44:03.661238 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 16:44:03.664886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 16:44:03.664992 ==
3006 16:44:03.665085
3007 16:44:03.665179
3008 16:44:03.668066 TX Vref Scan disable
3009 16:44:03.668166 == TX Byte 0 ==
3010 16:44:03.674777 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3011 16:44:03.678115 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3012 16:44:03.678229 == TX Byte 1 ==
3013 16:44:03.684742 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3014 16:44:03.687869 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3015 16:44:03.687955 ==
3016 16:44:03.690906 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 16:44:03.694531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 16:44:03.694636 ==
3019 16:44:03.707393 TX Vref=22, minBit 1, minWin=25, winSum=419
3020 16:44:03.711101 TX Vref=24, minBit 0, minWin=26, winSum=424
3021 16:44:03.714441 TX Vref=26, minBit 1, minWin=26, winSum=429
3022 16:44:03.717515 TX Vref=28, minBit 1, minWin=26, winSum=434
3023 16:44:03.721026 TX Vref=30, minBit 1, minWin=26, winSum=440
3024 16:44:03.727618 TX Vref=32, minBit 15, minWin=26, winSum=436
3025 16:44:03.730406 [TxChooseVref] Worse bit 1, Min win 26, Win sum 440, Final Vref 30
3026 16:44:03.730491
3027 16:44:03.734208 Final TX Range 1 Vref 30
3028 16:44:03.734299
3029 16:44:03.734366 ==
3030 16:44:03.737151 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 16:44:03.740714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 16:44:03.743903 ==
3033 16:44:03.743980
3034 16:44:03.744045
3035 16:44:03.744106 TX Vref Scan disable
3036 16:44:03.747370 == TX Byte 0 ==
3037 16:44:03.750859 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3038 16:44:03.757329 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3039 16:44:03.757411 == TX Byte 1 ==
3040 16:44:03.760555 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3041 16:44:03.767560 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3042 16:44:03.767685
3043 16:44:03.767750 [DATLAT]
3044 16:44:03.767811 Freq=1200, CH0 RK1
3045 16:44:03.767870
3046 16:44:03.770813 DATLAT Default: 0xd
3047 16:44:03.770885 0, 0xFFFF, sum = 0
3048 16:44:03.773778 1, 0xFFFF, sum = 0
3049 16:44:03.777065 2, 0xFFFF, sum = 0
3050 16:44:03.777218 3, 0xFFFF, sum = 0
3051 16:44:03.780528 4, 0xFFFF, sum = 0
3052 16:44:03.780620 5, 0xFFFF, sum = 0
3053 16:44:03.783964 6, 0xFFFF, sum = 0
3054 16:44:03.784048 7, 0xFFFF, sum = 0
3055 16:44:03.787640 8, 0xFFFF, sum = 0
3056 16:44:03.787729 9, 0xFFFF, sum = 0
3057 16:44:03.790640 10, 0xFFFF, sum = 0
3058 16:44:03.790730 11, 0xFFFF, sum = 0
3059 16:44:03.793860 12, 0x0, sum = 1
3060 16:44:03.793944 13, 0x0, sum = 2
3061 16:44:03.796929 14, 0x0, sum = 3
3062 16:44:03.797016 15, 0x0, sum = 4
3063 16:44:03.800562 best_step = 13
3064 16:44:03.800636
3065 16:44:03.800711 ==
3066 16:44:03.803826 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 16:44:03.806939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 16:44:03.807014 ==
3069 16:44:03.807076 RX Vref Scan: 0
3070 16:44:03.810861
3071 16:44:03.810940 RX Vref 0 -> 0, step: 1
3072 16:44:03.811009
3073 16:44:03.813661 RX Delay -37 -> 252, step: 4
3074 16:44:03.820241 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3075 16:44:03.823596 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3076 16:44:03.827145 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3077 16:44:03.830060 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3078 16:44:03.833884 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3079 16:44:03.840254 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3080 16:44:03.843264 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3081 16:44:03.846456 iDelay=195, Bit 7, Center 116 (43 ~ 190) 148
3082 16:44:03.850249 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3083 16:44:03.853604 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3084 16:44:03.859938 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3085 16:44:03.863732 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3086 16:44:03.866727 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3087 16:44:03.870246 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3088 16:44:03.873362 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3089 16:44:03.880236 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3090 16:44:03.880324 ==
3091 16:44:03.883003 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 16:44:03.887220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 16:44:03.887306 ==
3094 16:44:03.887463 DQS Delay:
3095 16:44:03.890070 DQS0 = 0, DQS1 = 0
3096 16:44:03.890156 DQM Delay:
3097 16:44:03.893213 DQM0 = 110, DQM1 = 101
3098 16:44:03.893298 DQ Delay:
3099 16:44:03.896382 DQ0 =108, DQ1 =110, DQ2 =110, DQ3 =108
3100 16:44:03.900077 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =116
3101 16:44:03.903146 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3102 16:44:03.906630 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3103 16:44:03.906715
3104 16:44:03.906799
3105 16:44:03.916626 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3106 16:44:03.919565 CH0 RK1: MR19=403, MR18=11F8
3107 16:44:03.922707 CH0_RK1: MR19=0x403, MR18=0x11F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3108 16:44:03.926137 [RxdqsGatingPostProcess] freq 1200
3109 16:44:03.932907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3110 16:44:03.936205 best DQS0 dly(2T, 0.5T) = (0, 11)
3111 16:44:03.939333 best DQS1 dly(2T, 0.5T) = (0, 12)
3112 16:44:03.943187 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3113 16:44:03.946021 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3114 16:44:03.949351 best DQS0 dly(2T, 0.5T) = (0, 11)
3115 16:44:03.953063 best DQS1 dly(2T, 0.5T) = (0, 12)
3116 16:44:03.956110 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3117 16:44:03.959119 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3118 16:44:03.962811 Pre-setting of DQS Precalculation
3119 16:44:03.966040 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3120 16:44:03.966149 ==
3121 16:44:03.969737 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 16:44:03.972660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 16:44:03.972772 ==
3124 16:44:03.979348 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3125 16:44:03.985984 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3126 16:44:03.993739 [CA 0] Center 37 (7~67) winsize 61
3127 16:44:03.997236 [CA 1] Center 37 (7~68) winsize 62
3128 16:44:04.000337 [CA 2] Center 34 (5~64) winsize 60
3129 16:44:04.003425 [CA 3] Center 33 (3~64) winsize 62
3130 16:44:04.007071 [CA 4] Center 34 (4~64) winsize 61
3131 16:44:04.010296 [CA 5] Center 33 (3~63) winsize 61
3132 16:44:04.010404
3133 16:44:04.013358 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3134 16:44:04.013463
3135 16:44:04.016891 [CATrainingPosCal] consider 1 rank data
3136 16:44:04.019905 u2DelayCellTimex100 = 270/100 ps
3137 16:44:04.023685 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3138 16:44:04.029919 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3139 16:44:04.033294 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3140 16:44:04.036232 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3141 16:44:04.039732 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3142 16:44:04.043306 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3143 16:44:04.043391
3144 16:44:04.046505 CA PerBit enable=1, Macro0, CA PI delay=33
3145 16:44:04.046590
3146 16:44:04.049976 [CBTSetCACLKResult] CA Dly = 33
3147 16:44:04.052956 CS Dly: 6 (0~37)
3148 16:44:04.053051 ==
3149 16:44:04.056484 Dram Type= 6, Freq= 0, CH_1, rank 1
3150 16:44:04.059588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3151 16:44:04.059701 ==
3152 16:44:04.066084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3153 16:44:04.069590 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3154 16:44:04.079404 [CA 0] Center 37 (7~67) winsize 61
3155 16:44:04.082237 [CA 1] Center 37 (7~68) winsize 62
3156 16:44:04.085912 [CA 2] Center 34 (4~65) winsize 62
3157 16:44:04.088932 [CA 3] Center 33 (3~64) winsize 62
3158 16:44:04.092237 [CA 4] Center 34 (4~64) winsize 61
3159 16:44:04.095806 [CA 5] Center 32 (2~63) winsize 62
3160 16:44:04.095893
3161 16:44:04.098713 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3162 16:44:04.098797
3163 16:44:04.102166 [CATrainingPosCal] consider 2 rank data
3164 16:44:04.105371 u2DelayCellTimex100 = 270/100 ps
3165 16:44:04.109109 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3166 16:44:04.115789 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3167 16:44:04.118826 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3168 16:44:04.122035 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3169 16:44:04.125607 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 16:44:04.128688 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3171 16:44:04.128767
3172 16:44:04.131797 CA PerBit enable=1, Macro0, CA PI delay=33
3173 16:44:04.131902
3174 16:44:04.135420 [CBTSetCACLKResult] CA Dly = 33
3175 16:44:04.138232 CS Dly: 7 (0~40)
3176 16:44:04.138334
3177 16:44:04.141949 ----->DramcWriteLeveling(PI) begin...
3178 16:44:04.142061 ==
3179 16:44:04.145297 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 16:44:04.148080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 16:44:04.148179 ==
3182 16:44:04.151366 Write leveling (Byte 0): 27 => 27
3183 16:44:04.154890 Write leveling (Byte 1): 30 => 30
3184 16:44:04.158166 DramcWriteLeveling(PI) end<-----
3185 16:44:04.158246
3186 16:44:04.158327 ==
3187 16:44:04.161810 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 16:44:04.164856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 16:44:04.164934 ==
3190 16:44:04.168004 [Gating] SW mode calibration
3191 16:44:04.174844 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3192 16:44:04.181801 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3193 16:44:04.184943 0 15 0 | B1->B0 | 2b2b 2626 | 1 1 | (0 0) (0 0)
3194 16:44:04.188235 0 15 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
3195 16:44:04.194869 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 16:44:04.197982 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 16:44:04.201605 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 16:44:04.208171 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 16:44:04.211176 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 16:44:04.214357 0 15 28 | B1->B0 | 2d2d 2e2e | 0 0 | (1 0) (0 0)
3201 16:44:04.220980 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 16:44:04.224158 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 16:44:04.227816 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 16:44:04.234673 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 16:44:04.237833 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 16:44:04.240771 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 16:44:04.247363 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3208 16:44:04.250896 1 0 28 | B1->B0 | 3f3f 3938 | 1 1 | (0 0) (0 0)
3209 16:44:04.254725 1 1 0 | B1->B0 | 4545 4141 | 0 1 | (0 0) (0 0)
3210 16:44:04.260741 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 16:44:04.264105 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 16:44:04.267228 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 16:44:04.273879 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 16:44:04.277316 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 16:44:04.280583 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 16:44:04.287394 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 16:44:04.290473 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 16:44:04.293899 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 16:44:04.300288 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 16:44:04.303962 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:44:04.307162 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:44:04.313695 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:44:04.317081 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 16:44:04.320255 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 16:44:04.327006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 16:44:04.330201 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 16:44:04.333843 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 16:44:04.339944 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 16:44:04.343486 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 16:44:04.346740 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 16:44:04.353430 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 16:44:04.356428 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3233 16:44:04.359702 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3234 16:44:04.363258 Total UI for P1: 0, mck2ui 16
3235 16:44:04.366582 best dqsien dly found for B1: ( 1, 3, 28)
3236 16:44:04.373527 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3237 16:44:04.373633 Total UI for P1: 0, mck2ui 16
3238 16:44:04.379548 best dqsien dly found for B0: ( 1, 3, 30)
3239 16:44:04.383330 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3240 16:44:04.386507 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3241 16:44:04.386620
3242 16:44:04.389813 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3243 16:44:04.392582 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3244 16:44:04.396005 [Gating] SW calibration Done
3245 16:44:04.396105 ==
3246 16:44:04.399625 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 16:44:04.402863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 16:44:04.402978 ==
3249 16:44:04.405889 RX Vref Scan: 0
3250 16:44:04.406016
3251 16:44:04.406126 RX Vref 0 -> 0, step: 1
3252 16:44:04.406224
3253 16:44:04.409549 RX Delay -40 -> 252, step: 8
3254 16:44:04.412695 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3255 16:44:04.419810 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3256 16:44:04.422628 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3257 16:44:04.426265 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3258 16:44:04.429490 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3259 16:44:04.432755 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3260 16:44:04.439385 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3261 16:44:04.442598 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3262 16:44:04.445960 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
3263 16:44:04.449215 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3264 16:44:04.452654 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3265 16:44:04.458892 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3266 16:44:04.462566 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3267 16:44:04.465725 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3268 16:44:04.469327 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3269 16:44:04.472274 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3270 16:44:04.475777 ==
3271 16:44:04.479122 Dram Type= 6, Freq= 0, CH_1, rank 0
3272 16:44:04.482737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3273 16:44:04.482827 ==
3274 16:44:04.482895 DQS Delay:
3275 16:44:04.485786 DQS0 = 0, DQS1 = 0
3276 16:44:04.485871 DQM Delay:
3277 16:44:04.488802 DQM0 = 113, DQM1 = 104
3278 16:44:04.488892 DQ Delay:
3279 16:44:04.492328 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3280 16:44:04.495910 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3281 16:44:04.499139 DQ8 =91, DQ9 =99, DQ10 =103, DQ11 =99
3282 16:44:04.502031 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3283 16:44:04.502160
3284 16:44:04.502260
3285 16:44:04.502371 ==
3286 16:44:04.505645 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 16:44:04.512094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 16:44:04.512179 ==
3289 16:44:04.512261
3290 16:44:04.512328
3291 16:44:04.512396 TX Vref Scan disable
3292 16:44:04.515852 == TX Byte 0 ==
3293 16:44:04.519009 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3294 16:44:04.525513 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3295 16:44:04.525649 == TX Byte 1 ==
3296 16:44:04.529098 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3297 16:44:04.535365 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3298 16:44:04.535484 ==
3299 16:44:04.538647 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 16:44:04.542031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 16:44:04.542117 ==
3302 16:44:04.553574 TX Vref=22, minBit 11, minWin=24, winSum=415
3303 16:44:04.556774 TX Vref=24, minBit 8, minWin=25, winSum=422
3304 16:44:04.560408 TX Vref=26, minBit 1, minWin=26, winSum=426
3305 16:44:04.563534 TX Vref=28, minBit 1, minWin=26, winSum=428
3306 16:44:04.567197 TX Vref=30, minBit 9, minWin=25, winSum=429
3307 16:44:04.573505 TX Vref=32, minBit 1, minWin=26, winSum=427
3308 16:44:04.576756 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
3309 16:44:04.576843
3310 16:44:04.580414 Final TX Range 1 Vref 28
3311 16:44:04.580512
3312 16:44:04.580588 ==
3313 16:44:04.583662 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 16:44:04.587149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 16:44:04.587243 ==
3316 16:44:04.590043
3317 16:44:04.590128
3318 16:44:04.590199 TX Vref Scan disable
3319 16:44:04.593095 == TX Byte 0 ==
3320 16:44:04.596651 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3321 16:44:04.602977 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3322 16:44:04.603097 == TX Byte 1 ==
3323 16:44:04.606583 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3324 16:44:04.612845 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3325 16:44:04.612938
3326 16:44:04.613013 [DATLAT]
3327 16:44:04.613083 Freq=1200, CH1 RK0
3328 16:44:04.613151
3329 16:44:04.616702 DATLAT Default: 0xd
3330 16:44:04.616782 0, 0xFFFF, sum = 0
3331 16:44:04.619738 1, 0xFFFF, sum = 0
3332 16:44:04.622904 2, 0xFFFF, sum = 0
3333 16:44:04.623024 3, 0xFFFF, sum = 0
3334 16:44:04.626105 4, 0xFFFF, sum = 0
3335 16:44:04.626224 5, 0xFFFF, sum = 0
3336 16:44:04.629659 6, 0xFFFF, sum = 0
3337 16:44:04.629765 7, 0xFFFF, sum = 0
3338 16:44:04.633016 8, 0xFFFF, sum = 0
3339 16:44:04.633121 9, 0xFFFF, sum = 0
3340 16:44:04.636586 10, 0xFFFF, sum = 0
3341 16:44:04.636669 11, 0xFFFF, sum = 0
3342 16:44:04.639765 12, 0x0, sum = 1
3343 16:44:04.639855 13, 0x0, sum = 2
3344 16:44:04.642796 14, 0x0, sum = 3
3345 16:44:04.642886 15, 0x0, sum = 4
3346 16:44:04.646534 best_step = 13
3347 16:44:04.646642
3348 16:44:04.646736 ==
3349 16:44:04.649493 Dram Type= 6, Freq= 0, CH_1, rank 0
3350 16:44:04.652636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3351 16:44:04.652721 ==
3352 16:44:04.652788 RX Vref Scan: 1
3353 16:44:04.656234
3354 16:44:04.656318 Set Vref Range= 32 -> 127
3355 16:44:04.656385
3356 16:44:04.659571 RX Vref 32 -> 127, step: 1
3357 16:44:04.659664
3358 16:44:04.662576 RX Delay -21 -> 252, step: 4
3359 16:44:04.662660
3360 16:44:04.666112 Set Vref, RX VrefLevel [Byte0]: 32
3361 16:44:04.669223 [Byte1]: 32
3362 16:44:04.669308
3363 16:44:04.672856 Set Vref, RX VrefLevel [Byte0]: 33
3364 16:44:04.675962 [Byte1]: 33
3365 16:44:04.680084
3366 16:44:04.680171 Set Vref, RX VrefLevel [Byte0]: 34
3367 16:44:04.682956 [Byte1]: 34
3368 16:44:04.687506
3369 16:44:04.687616 Set Vref, RX VrefLevel [Byte0]: 35
3370 16:44:04.690943 [Byte1]: 35
3371 16:44:04.695871
3372 16:44:04.695962 Set Vref, RX VrefLevel [Byte0]: 36
3373 16:44:04.698922 [Byte1]: 36
3374 16:44:04.703704
3375 16:44:04.703782 Set Vref, RX VrefLevel [Byte0]: 37
3376 16:44:04.706678 [Byte1]: 37
3377 16:44:04.711143
3378 16:44:04.711249 Set Vref, RX VrefLevel [Byte0]: 38
3379 16:44:04.714716 [Byte1]: 38
3380 16:44:04.719409
3381 16:44:04.719514 Set Vref, RX VrefLevel [Byte0]: 39
3382 16:44:04.722792 [Byte1]: 39
3383 16:44:04.727632
3384 16:44:04.727721 Set Vref, RX VrefLevel [Byte0]: 40
3385 16:44:04.730924 [Byte1]: 40
3386 16:44:04.735042
3387 16:44:04.735152 Set Vref, RX VrefLevel [Byte0]: 41
3388 16:44:04.738517 [Byte1]: 41
3389 16:44:04.743328
3390 16:44:04.743440 Set Vref, RX VrefLevel [Byte0]: 42
3391 16:44:04.746253 [Byte1]: 42
3392 16:44:04.751217
3393 16:44:04.751322 Set Vref, RX VrefLevel [Byte0]: 43
3394 16:44:04.757460 [Byte1]: 43
3395 16:44:04.757567
3396 16:44:04.760923 Set Vref, RX VrefLevel [Byte0]: 44
3397 16:44:04.764132 [Byte1]: 44
3398 16:44:04.764234
3399 16:44:04.767196 Set Vref, RX VrefLevel [Byte0]: 45
3400 16:44:04.770863 [Byte1]: 45
3401 16:44:04.775118
3402 16:44:04.775222 Set Vref, RX VrefLevel [Byte0]: 46
3403 16:44:04.778249 [Byte1]: 46
3404 16:44:04.782626
3405 16:44:04.782745 Set Vref, RX VrefLevel [Byte0]: 47
3406 16:44:04.786181 [Byte1]: 47
3407 16:44:04.790877
3408 16:44:04.790988 Set Vref, RX VrefLevel [Byte0]: 48
3409 16:44:04.794165 [Byte1]: 48
3410 16:44:04.798540
3411 16:44:04.798645 Set Vref, RX VrefLevel [Byte0]: 49
3412 16:44:04.801984 [Byte1]: 49
3413 16:44:04.806510
3414 16:44:04.806621 Set Vref, RX VrefLevel [Byte0]: 50
3415 16:44:04.809978 [Byte1]: 50
3416 16:44:04.814811
3417 16:44:04.814892 Set Vref, RX VrefLevel [Byte0]: 51
3418 16:44:04.817752 [Byte1]: 51
3419 16:44:04.822313
3420 16:44:04.822431 Set Vref, RX VrefLevel [Byte0]: 52
3421 16:44:04.825765 [Byte1]: 52
3422 16:44:04.830561
3423 16:44:04.830678 Set Vref, RX VrefLevel [Byte0]: 53
3424 16:44:04.833715 [Byte1]: 53
3425 16:44:04.838135
3426 16:44:04.838243 Set Vref, RX VrefLevel [Byte0]: 54
3427 16:44:04.841248 [Byte1]: 54
3428 16:44:04.845806
3429 16:44:04.845913 Set Vref, RX VrefLevel [Byte0]: 55
3430 16:44:04.849506 [Byte1]: 55
3431 16:44:04.853871
3432 16:44:04.853985 Set Vref, RX VrefLevel [Byte0]: 56
3433 16:44:04.857704 [Byte1]: 56
3434 16:44:04.861831
3435 16:44:04.861940 Set Vref, RX VrefLevel [Byte0]: 57
3436 16:44:04.865456 [Byte1]: 57
3437 16:44:04.869811
3438 16:44:04.869925 Set Vref, RX VrefLevel [Byte0]: 58
3439 16:44:04.872931 [Byte1]: 58
3440 16:44:04.877950
3441 16:44:04.878056 Set Vref, RX VrefLevel [Byte0]: 59
3442 16:44:04.881051 [Byte1]: 59
3443 16:44:04.886154
3444 16:44:04.886241 Set Vref, RX VrefLevel [Byte0]: 60
3445 16:44:04.889228 [Byte1]: 60
3446 16:44:04.893438
3447 16:44:04.893523 Set Vref, RX VrefLevel [Byte0]: 61
3448 16:44:04.897104 [Byte1]: 61
3449 16:44:04.901742
3450 16:44:04.901827 Set Vref, RX VrefLevel [Byte0]: 62
3451 16:44:04.905167 [Byte1]: 62
3452 16:44:04.909860
3453 16:44:04.909945 Set Vref, RX VrefLevel [Byte0]: 63
3454 16:44:04.912563 [Byte1]: 63
3455 16:44:04.917444
3456 16:44:04.917529 Set Vref, RX VrefLevel [Byte0]: 64
3457 16:44:04.920934 [Byte1]: 64
3458 16:44:04.925631
3459 16:44:04.925745 Final RX Vref Byte 0 = 58 to rank0
3460 16:44:04.928557 Final RX Vref Byte 1 = 50 to rank0
3461 16:44:04.932244 Final RX Vref Byte 0 = 58 to rank1
3462 16:44:04.935191 Final RX Vref Byte 1 = 50 to rank1==
3463 16:44:04.938589 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 16:44:04.945204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 16:44:04.945327 ==
3466 16:44:04.945425 DQS Delay:
3467 16:44:04.945492 DQS0 = 0, DQS1 = 0
3468 16:44:04.948411 DQM Delay:
3469 16:44:04.948498 DQM0 = 114, DQM1 = 105
3470 16:44:04.951812 DQ Delay:
3471 16:44:04.955075 DQ0 =116, DQ1 =110, DQ2 =104, DQ3 =112
3472 16:44:04.958718 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3473 16:44:04.961846 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =100
3474 16:44:04.965321 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3475 16:44:04.965443
3476 16:44:04.965550
3477 16:44:04.975133 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3478 16:44:04.975252 CH1 RK0: MR19=303, MR18=ECF3
3479 16:44:04.981371 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3480 16:44:04.981490
3481 16:44:04.984989 ----->DramcWriteLeveling(PI) begin...
3482 16:44:04.985102 ==
3483 16:44:04.988071 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 16:44:04.994793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 16:44:04.994888 ==
3486 16:44:04.998332 Write leveling (Byte 0): 26 => 26
3487 16:44:05.001263 Write leveling (Byte 1): 28 => 28
3488 16:44:05.001377 DramcWriteLeveling(PI) end<-----
3489 16:44:05.001473
3490 16:44:05.004900 ==
3491 16:44:05.008178 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 16:44:05.011562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 16:44:05.011684 ==
3494 16:44:05.014940 [Gating] SW mode calibration
3495 16:44:05.021512 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3496 16:44:05.024351 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3497 16:44:05.030980 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 16:44:05.034622 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 16:44:05.038169 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 16:44:05.044466 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 16:44:05.048298 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 16:44:05.051367 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3503 16:44:05.057960 0 15 24 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 1)
3504 16:44:05.061291 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3505 16:44:05.064877 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 16:44:05.071133 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 16:44:05.074782 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 16:44:05.077720 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 16:44:05.084680 1 0 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3510 16:44:05.087776 1 0 20 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
3511 16:44:05.090886 1 0 24 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3512 16:44:05.097545 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
3513 16:44:05.101177 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 16:44:05.104556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 16:44:05.111350 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 16:44:05.114412 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 16:44:05.117558 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 16:44:05.121018 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 16:44:05.127598 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3520 16:44:05.130812 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3521 16:44:05.134365 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 16:44:05.140922 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 16:44:05.143728 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 16:44:05.147326 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 16:44:05.154102 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 16:44:05.157015 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 16:44:05.160718 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 16:44:05.166812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 16:44:05.170097 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 16:44:05.173605 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:44:05.179915 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:44:05.183393 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:44:05.187125 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:44:05.193488 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3535 16:44:05.196615 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3536 16:44:05.199843 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 16:44:05.203636 Total UI for P1: 0, mck2ui 16
3538 16:44:05.206520 best dqsien dly found for B0: ( 1, 3, 22)
3539 16:44:05.209970 Total UI for P1: 0, mck2ui 16
3540 16:44:05.213120 best dqsien dly found for B1: ( 1, 3, 24)
3541 16:44:05.216328 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3542 16:44:05.223122 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3543 16:44:05.223256
3544 16:44:05.226105 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3545 16:44:05.229552 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3546 16:44:05.232894 [Gating] SW calibration Done
3547 16:44:05.233018 ==
3548 16:44:05.236468 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 16:44:05.239788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 16:44:05.239890 ==
3551 16:44:05.243027 RX Vref Scan: 0
3552 16:44:05.243145
3553 16:44:05.243249 RX Vref 0 -> 0, step: 1
3554 16:44:05.243349
3555 16:44:05.245946 RX Delay -40 -> 252, step: 8
3556 16:44:05.249432 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3557 16:44:05.255717 iDelay=200, Bit 1, Center 107 (40 ~ 175) 136
3558 16:44:05.259071 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3559 16:44:05.262628 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3560 16:44:05.265584 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3561 16:44:05.269107 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3562 16:44:05.275931 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3563 16:44:05.279377 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3564 16:44:05.282516 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3565 16:44:05.285676 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3566 16:44:05.288763 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3567 16:44:05.295727 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3568 16:44:05.298727 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3569 16:44:05.302372 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3570 16:44:05.305558 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3571 16:44:05.309053 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3572 16:44:05.312018 ==
3573 16:44:05.312151 Dram Type= 6, Freq= 0, CH_1, rank 1
3574 16:44:05.318879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3575 16:44:05.319025 ==
3576 16:44:05.319126 DQS Delay:
3577 16:44:05.321987 DQS0 = 0, DQS1 = 0
3578 16:44:05.322094 DQM Delay:
3579 16:44:05.325780 DQM0 = 111, DQM1 = 106
3580 16:44:05.325892 DQ Delay:
3581 16:44:05.328365 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =111
3582 16:44:05.331825 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3583 16:44:05.334985 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3584 16:44:05.338528 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =111
3585 16:44:05.338645
3586 16:44:05.338729
3587 16:44:05.338794 ==
3588 16:44:05.341922 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 16:44:05.348152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 16:44:05.348327 ==
3591 16:44:05.348436
3592 16:44:05.348536
3593 16:44:05.348630 TX Vref Scan disable
3594 16:44:05.351610 == TX Byte 0 ==
3595 16:44:05.355198 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3596 16:44:05.361767 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3597 16:44:05.361938 == TX Byte 1 ==
3598 16:44:05.364821 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3599 16:44:05.371713 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3600 16:44:05.371895 ==
3601 16:44:05.374661 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 16:44:05.378207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 16:44:05.378338 ==
3604 16:44:05.389584 TX Vref=22, minBit 0, minWin=26, winSum=423
3605 16:44:05.392736 TX Vref=24, minBit 3, minWin=26, winSum=432
3606 16:44:05.396420 TX Vref=26, minBit 1, minWin=26, winSum=431
3607 16:44:05.399420 TX Vref=28, minBit 9, minWin=26, winSum=436
3608 16:44:05.402635 TX Vref=30, minBit 2, minWin=26, winSum=436
3609 16:44:05.409339 TX Vref=32, minBit 8, minWin=25, winSum=433
3610 16:44:05.413009 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 28
3611 16:44:05.413125
3612 16:44:05.416086 Final TX Range 1 Vref 28
3613 16:44:05.416171
3614 16:44:05.416238 ==
3615 16:44:05.419839 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 16:44:05.422728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 16:44:05.425939 ==
3618 16:44:05.426052
3619 16:44:05.426163
3620 16:44:05.426260 TX Vref Scan disable
3621 16:44:05.429540 == TX Byte 0 ==
3622 16:44:05.432571 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3623 16:44:05.439392 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3624 16:44:05.439519 == TX Byte 1 ==
3625 16:44:05.442464 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3626 16:44:05.449463 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3627 16:44:05.449587
3628 16:44:05.449701 [DATLAT]
3629 16:44:05.449797 Freq=1200, CH1 RK1
3630 16:44:05.449899
3631 16:44:05.452814 DATLAT Default: 0xd
3632 16:44:05.452917 0, 0xFFFF, sum = 0
3633 16:44:05.455531 1, 0xFFFF, sum = 0
3634 16:44:05.459029 2, 0xFFFF, sum = 0
3635 16:44:05.459164 3, 0xFFFF, sum = 0
3636 16:44:05.462639 4, 0xFFFF, sum = 0
3637 16:44:05.462733 5, 0xFFFF, sum = 0
3638 16:44:05.465601 6, 0xFFFF, sum = 0
3639 16:44:05.465693 7, 0xFFFF, sum = 0
3640 16:44:05.469202 8, 0xFFFF, sum = 0
3641 16:44:05.469315 9, 0xFFFF, sum = 0
3642 16:44:05.472031 10, 0xFFFF, sum = 0
3643 16:44:05.472143 11, 0xFFFF, sum = 0
3644 16:44:05.475692 12, 0x0, sum = 1
3645 16:44:05.475778 13, 0x0, sum = 2
3646 16:44:05.479114 14, 0x0, sum = 3
3647 16:44:05.479237 15, 0x0, sum = 4
3648 16:44:05.481995 best_step = 13
3649 16:44:05.482134
3650 16:44:05.482234 ==
3651 16:44:05.485625 Dram Type= 6, Freq= 0, CH_1, rank 1
3652 16:44:05.489037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3653 16:44:05.489153 ==
3654 16:44:05.491809 RX Vref Scan: 0
3655 16:44:05.491948
3656 16:44:05.492060 RX Vref 0 -> 0, step: 1
3657 16:44:05.492159
3658 16:44:05.495594 RX Delay -21 -> 252, step: 4
3659 16:44:05.501893 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3660 16:44:05.505413 iDelay=195, Bit 1, Center 108 (43 ~ 174) 132
3661 16:44:05.508565 iDelay=195, Bit 2, Center 104 (35 ~ 174) 140
3662 16:44:05.511671 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3663 16:44:05.515226 iDelay=195, Bit 4, Center 106 (35 ~ 178) 144
3664 16:44:05.521915 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3665 16:44:05.525145 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3666 16:44:05.528119 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3667 16:44:05.531203 iDelay=195, Bit 8, Center 96 (35 ~ 158) 124
3668 16:44:05.534827 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3669 16:44:05.541208 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3670 16:44:05.544948 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3671 16:44:05.547995 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3672 16:44:05.551236 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3673 16:44:05.557686 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3674 16:44:05.561154 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3675 16:44:05.561273 ==
3676 16:44:05.564505 Dram Type= 6, Freq= 0, CH_1, rank 1
3677 16:44:05.567384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3678 16:44:05.567471 ==
3679 16:44:05.571122 DQS Delay:
3680 16:44:05.571234 DQS0 = 0, DQS1 = 0
3681 16:44:05.571331 DQM Delay:
3682 16:44:05.574059 DQM0 = 111, DQM1 = 108
3683 16:44:05.574141 DQ Delay:
3684 16:44:05.577772 DQ0 =114, DQ1 =108, DQ2 =104, DQ3 =108
3685 16:44:05.580711 DQ4 =106, DQ5 =120, DQ6 =120, DQ7 =110
3686 16:44:05.587097 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3687 16:44:05.590691 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3688 16:44:05.590816
3689 16:44:05.590916
3690 16:44:05.596995 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3691 16:44:05.600655 CH1 RK1: MR19=304, MR18=F808
3692 16:44:05.607356 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3693 16:44:05.610421 [RxdqsGatingPostProcess] freq 1200
3694 16:44:05.613654 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3695 16:44:05.617455 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 16:44:05.620518 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 16:44:05.623592 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 16:44:05.627090 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 16:44:05.630202 best DQS0 dly(2T, 0.5T) = (0, 11)
3700 16:44:05.633409 best DQS1 dly(2T, 0.5T) = (0, 11)
3701 16:44:05.636892 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3702 16:44:05.640020 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3703 16:44:05.643597 Pre-setting of DQS Precalculation
3704 16:44:05.646645 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3705 16:44:05.656454 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3706 16:44:05.663043 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3707 16:44:05.663191
3708 16:44:05.663320
3709 16:44:05.666596 [Calibration Summary] 2400 Mbps
3710 16:44:05.666729 CH 0, Rank 0
3711 16:44:05.669728 SW Impedance : PASS
3712 16:44:05.673154 DUTY Scan : NO K
3713 16:44:05.673292 ZQ Calibration : PASS
3714 16:44:05.676224 Jitter Meter : NO K
3715 16:44:05.679453 CBT Training : PASS
3716 16:44:05.679563 Write leveling : PASS
3717 16:44:05.683174 RX DQS gating : PASS
3718 16:44:05.683297 RX DQ/DQS(RDDQC) : PASS
3719 16:44:05.686470 TX DQ/DQS : PASS
3720 16:44:05.689856 RX DATLAT : PASS
3721 16:44:05.689986 RX DQ/DQS(Engine): PASS
3722 16:44:05.692757 TX OE : NO K
3723 16:44:05.692873 All Pass.
3724 16:44:05.692962
3725 16:44:05.696005 CH 0, Rank 1
3726 16:44:05.696104 SW Impedance : PASS
3727 16:44:05.699792 DUTY Scan : NO K
3728 16:44:05.702853 ZQ Calibration : PASS
3729 16:44:05.702952 Jitter Meter : NO K
3730 16:44:05.706318 CBT Training : PASS
3731 16:44:05.709325 Write leveling : PASS
3732 16:44:05.709432 RX DQS gating : PASS
3733 16:44:05.712683 RX DQ/DQS(RDDQC) : PASS
3734 16:44:05.715876 TX DQ/DQS : PASS
3735 16:44:05.715966 RX DATLAT : PASS
3736 16:44:05.718917 RX DQ/DQS(Engine): PASS
3737 16:44:05.722539 TX OE : NO K
3738 16:44:05.722645 All Pass.
3739 16:44:05.722742
3740 16:44:05.722834 CH 1, Rank 0
3741 16:44:05.725686 SW Impedance : PASS
3742 16:44:05.729164 DUTY Scan : NO K
3743 16:44:05.729246 ZQ Calibration : PASS
3744 16:44:05.732184 Jitter Meter : NO K
3745 16:44:05.735374 CBT Training : PASS
3746 16:44:05.735509 Write leveling : PASS
3747 16:44:05.739022 RX DQS gating : PASS
3748 16:44:05.742669 RX DQ/DQS(RDDQC) : PASS
3749 16:44:05.742789 TX DQ/DQS : PASS
3750 16:44:05.745803 RX DATLAT : PASS
3751 16:44:05.748778 RX DQ/DQS(Engine): PASS
3752 16:44:05.748875 TX OE : NO K
3753 16:44:05.751874 All Pass.
3754 16:44:05.752004
3755 16:44:05.752109 CH 1, Rank 1
3756 16:44:05.755043 SW Impedance : PASS
3757 16:44:05.755166 DUTY Scan : NO K
3758 16:44:05.758726 ZQ Calibration : PASS
3759 16:44:05.761997 Jitter Meter : NO K
3760 16:44:05.762126 CBT Training : PASS
3761 16:44:05.764965 Write leveling : PASS
3762 16:44:05.768436 RX DQS gating : PASS
3763 16:44:05.768564 RX DQ/DQS(RDDQC) : PASS
3764 16:44:05.771506 TX DQ/DQS : PASS
3765 16:44:05.774912 RX DATLAT : PASS
3766 16:44:05.775039 RX DQ/DQS(Engine): PASS
3767 16:44:05.778502 TX OE : NO K
3768 16:44:05.778622 All Pass.
3769 16:44:05.778723
3770 16:44:05.781771 DramC Write-DBI off
3771 16:44:05.785268 PER_BANK_REFRESH: Hybrid Mode
3772 16:44:05.785408 TX_TRACKING: ON
3773 16:44:05.794911 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3774 16:44:05.798285 [FAST_K] Save calibration result to emmc
3775 16:44:05.801730 dramc_set_vcore_voltage set vcore to 650000
3776 16:44:05.804809 Read voltage for 600, 5
3777 16:44:05.804957 Vio18 = 0
3778 16:44:05.805031 Vcore = 650000
3779 16:44:05.808064 Vdram = 0
3780 16:44:05.808195 Vddq = 0
3781 16:44:05.808310 Vmddr = 0
3782 16:44:05.814653 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3783 16:44:05.817813 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3784 16:44:05.821345 MEM_TYPE=3, freq_sel=19
3785 16:44:05.824528 sv_algorithm_assistance_LP4_1600
3786 16:44:05.827822 ============ PULL DRAM RESETB DOWN ============
3787 16:44:05.831542 ========== PULL DRAM RESETB DOWN end =========
3788 16:44:05.837895 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3789 16:44:05.840966 ===================================
3790 16:44:05.841074 LPDDR4 DRAM CONFIGURATION
3791 16:44:05.844644 ===================================
3792 16:44:05.847606 EX_ROW_EN[0] = 0x0
3793 16:44:05.851360 EX_ROW_EN[1] = 0x0
3794 16:44:05.851484 LP4Y_EN = 0x0
3795 16:44:05.854527 WORK_FSP = 0x0
3796 16:44:05.854622 WL = 0x2
3797 16:44:05.857614 RL = 0x2
3798 16:44:05.857707 BL = 0x2
3799 16:44:05.861401 RPST = 0x0
3800 16:44:05.861494 RD_PRE = 0x0
3801 16:44:05.864441 WR_PRE = 0x1
3802 16:44:05.864556 WR_PST = 0x0
3803 16:44:05.867411 DBI_WR = 0x0
3804 16:44:05.867522 DBI_RD = 0x0
3805 16:44:05.871078 OTF = 0x1
3806 16:44:05.874026 ===================================
3807 16:44:05.877378 ===================================
3808 16:44:05.877508 ANA top config
3809 16:44:05.880775 ===================================
3810 16:44:05.884355 DLL_ASYNC_EN = 0
3811 16:44:05.887478 ALL_SLAVE_EN = 1
3812 16:44:05.890669 NEW_RANK_MODE = 1
3813 16:44:05.890768 DLL_IDLE_MODE = 1
3814 16:44:05.894342 LP45_APHY_COMB_EN = 1
3815 16:44:05.897288 TX_ODT_DIS = 1
3816 16:44:05.900838 NEW_8X_MODE = 1
3817 16:44:05.904157 ===================================
3818 16:44:05.907010 ===================================
3819 16:44:05.910481 data_rate = 1200
3820 16:44:05.910603 CKR = 1
3821 16:44:05.914017 DQ_P2S_RATIO = 8
3822 16:44:05.917398 ===================================
3823 16:44:05.920723 CA_P2S_RATIO = 8
3824 16:44:05.923919 DQ_CA_OPEN = 0
3825 16:44:05.927013 DQ_SEMI_OPEN = 0
3826 16:44:05.930016 CA_SEMI_OPEN = 0
3827 16:44:05.930136 CA_FULL_RATE = 0
3828 16:44:05.933835 DQ_CKDIV4_EN = 1
3829 16:44:05.936841 CA_CKDIV4_EN = 1
3830 16:44:05.940419 CA_PREDIV_EN = 0
3831 16:44:05.943559 PH8_DLY = 0
3832 16:44:05.946572 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3833 16:44:05.950337 DQ_AAMCK_DIV = 4
3834 16:44:05.950463 CA_AAMCK_DIV = 4
3835 16:44:05.953494 CA_ADMCK_DIV = 4
3836 16:44:05.956569 DQ_TRACK_CA_EN = 0
3837 16:44:05.959818 CA_PICK = 600
3838 16:44:05.963524 CA_MCKIO = 600
3839 16:44:05.966472 MCKIO_SEMI = 0
3840 16:44:05.969613 PLL_FREQ = 2288
3841 16:44:05.969714 DQ_UI_PI_RATIO = 32
3842 16:44:05.973210 CA_UI_PI_RATIO = 0
3843 16:44:05.976196 ===================================
3844 16:44:05.979817 ===================================
3845 16:44:05.983042 memory_type:LPDDR4
3846 16:44:05.986452 GP_NUM : 10
3847 16:44:05.986606 SRAM_EN : 1
3848 16:44:05.989643 MD32_EN : 0
3849 16:44:05.992576 ===================================
3850 16:44:05.995790 [ANA_INIT] >>>>>>>>>>>>>>
3851 16:44:05.999600 <<<<<< [CONFIGURE PHASE]: ANA_TX
3852 16:44:06.002433 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3853 16:44:06.005749 ===================================
3854 16:44:06.005851 data_rate = 1200,PCW = 0X5800
3855 16:44:06.009168 ===================================
3856 16:44:06.012149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3857 16:44:06.019025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 16:44:06.025426 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3859 16:44:06.029123 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3860 16:44:06.032545 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3861 16:44:06.035669 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3862 16:44:06.038819 [ANA_INIT] flow start
3863 16:44:06.038962 [ANA_INIT] PLL >>>>>>>>
3864 16:44:06.042491 [ANA_INIT] PLL <<<<<<<<
3865 16:44:06.046009 [ANA_INIT] MIDPI >>>>>>>>
3866 16:44:06.048639 [ANA_INIT] MIDPI <<<<<<<<
3867 16:44:06.048794 [ANA_INIT] DLL >>>>>>>>
3868 16:44:06.052297 [ANA_INIT] flow end
3869 16:44:06.055353 ============ LP4 DIFF to SE enter ============
3870 16:44:06.059081 ============ LP4 DIFF to SE exit ============
3871 16:44:06.062296 [ANA_INIT] <<<<<<<<<<<<<
3872 16:44:06.065365 [Flow] Enable top DCM control >>>>>
3873 16:44:06.069117 [Flow] Enable top DCM control <<<<<
3874 16:44:06.072201 Enable DLL master slave shuffle
3875 16:44:06.078402 ==============================================================
3876 16:44:06.078584 Gating Mode config
3877 16:44:06.085254 ==============================================================
3878 16:44:06.085437 Config description:
3879 16:44:06.095263 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3880 16:44:06.101635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3881 16:44:06.108114 SELPH_MODE 0: By rank 1: By Phase
3882 16:44:06.114859 ==============================================================
3883 16:44:06.115014 GAT_TRACK_EN = 1
3884 16:44:06.118383 RX_GATING_MODE = 2
3885 16:44:06.121319 RX_GATING_TRACK_MODE = 2
3886 16:44:06.124654 SELPH_MODE = 1
3887 16:44:06.128055 PICG_EARLY_EN = 1
3888 16:44:06.131307 VALID_LAT_VALUE = 1
3889 16:44:06.138164 ==============================================================
3890 16:44:06.141484 Enter into Gating configuration >>>>
3891 16:44:06.144563 Exit from Gating configuration <<<<
3892 16:44:06.148120 Enter into DVFS_PRE_config >>>>>
3893 16:44:06.157668 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3894 16:44:06.160710 Exit from DVFS_PRE_config <<<<<
3895 16:44:06.164589 Enter into PICG configuration >>>>
3896 16:44:06.167531 Exit from PICG configuration <<<<
3897 16:44:06.170670 [RX_INPUT] configuration >>>>>
3898 16:44:06.174489 [RX_INPUT] configuration <<<<<
3899 16:44:06.177659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3900 16:44:06.183918 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3901 16:44:06.190781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3902 16:44:06.197364 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3903 16:44:06.200659 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3904 16:44:06.207452 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3905 16:44:06.210379 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3906 16:44:06.217375 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3907 16:44:06.220297 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3908 16:44:06.223877 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3909 16:44:06.226784 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3910 16:44:06.233777 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3911 16:44:06.237237 ===================================
3912 16:44:06.239982 LPDDR4 DRAM CONFIGURATION
3913 16:44:06.243437 ===================================
3914 16:44:06.243610 EX_ROW_EN[0] = 0x0
3915 16:44:06.246375 EX_ROW_EN[1] = 0x0
3916 16:44:06.246517 LP4Y_EN = 0x0
3917 16:44:06.249868 WORK_FSP = 0x0
3918 16:44:06.250020 WL = 0x2
3919 16:44:06.253210 RL = 0x2
3920 16:44:06.253352 BL = 0x2
3921 16:44:06.256835 RPST = 0x0
3922 16:44:06.256981 RD_PRE = 0x0
3923 16:44:06.259899 WR_PRE = 0x1
3924 16:44:06.260038 WR_PST = 0x0
3925 16:44:06.263006 DBI_WR = 0x0
3926 16:44:06.263159 DBI_RD = 0x0
3927 16:44:06.266236 OTF = 0x1
3928 16:44:06.269431 ===================================
3929 16:44:06.272970 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3930 16:44:06.276283 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3931 16:44:06.282887 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 16:44:06.285881 ===================================
3933 16:44:06.289674 LPDDR4 DRAM CONFIGURATION
3934 16:44:06.292687 ===================================
3935 16:44:06.292842 EX_ROW_EN[0] = 0x10
3936 16:44:06.295799 EX_ROW_EN[1] = 0x0
3937 16:44:06.295910 LP4Y_EN = 0x0
3938 16:44:06.299370 WORK_FSP = 0x0
3939 16:44:06.299527 WL = 0x2
3940 16:44:06.302383 RL = 0x2
3941 16:44:06.302549 BL = 0x2
3942 16:44:06.305610 RPST = 0x0
3943 16:44:06.305765 RD_PRE = 0x0
3944 16:44:06.309006 WR_PRE = 0x1
3945 16:44:06.309161 WR_PST = 0x0
3946 16:44:06.312377 DBI_WR = 0x0
3947 16:44:06.312535 DBI_RD = 0x0
3948 16:44:06.315886 OTF = 0x1
3949 16:44:06.319344 ===================================
3950 16:44:06.325769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3951 16:44:06.329401 nWR fixed to 30
3952 16:44:06.332907 [ModeRegInit_LP4] CH0 RK0
3953 16:44:06.333059 [ModeRegInit_LP4] CH0 RK1
3954 16:44:06.335932 [ModeRegInit_LP4] CH1 RK0
3955 16:44:06.339127 [ModeRegInit_LP4] CH1 RK1
3956 16:44:06.339267 match AC timing 17
3957 16:44:06.346341 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3958 16:44:06.349108 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3959 16:44:06.352524 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3960 16:44:06.359189 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3961 16:44:06.362201 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3962 16:44:06.362343 ==
3963 16:44:06.365773 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 16:44:06.368860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 16:44:06.368990 ==
3966 16:44:06.375788 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3967 16:44:06.381873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3968 16:44:06.385520 [CA 0] Center 37 (7~67) winsize 61
3969 16:44:06.388574 [CA 1] Center 37 (7~67) winsize 61
3970 16:44:06.392196 [CA 2] Center 35 (5~65) winsize 61
3971 16:44:06.395238 [CA 3] Center 35 (5~65) winsize 61
3972 16:44:06.398320 [CA 4] Center 34 (4~65) winsize 62
3973 16:44:06.402005 [CA 5] Center 34 (4~64) winsize 61
3974 16:44:06.402165
3975 16:44:06.405070 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3976 16:44:06.405213
3977 16:44:06.408626 [CATrainingPosCal] consider 1 rank data
3978 16:44:06.411803 u2DelayCellTimex100 = 270/100 ps
3979 16:44:06.415316 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3980 16:44:06.418380 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3981 16:44:06.421791 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3982 16:44:06.427972 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3983 16:44:06.431423 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3984 16:44:06.434845 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3985 16:44:06.434984
3986 16:44:06.437905 CA PerBit enable=1, Macro0, CA PI delay=34
3987 16:44:06.438040
3988 16:44:06.441225 [CBTSetCACLKResult] CA Dly = 34
3989 16:44:06.441360 CS Dly: 7 (0~38)
3990 16:44:06.441482 ==
3991 16:44:06.444361 Dram Type= 6, Freq= 0, CH_0, rank 1
3992 16:44:06.451132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 16:44:06.451323 ==
3994 16:44:06.454529 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 16:44:06.460651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3996 16:44:06.464477 [CA 0] Center 37 (7~67) winsize 61
3997 16:44:06.467684 [CA 1] Center 37 (7~67) winsize 61
3998 16:44:06.471194 [CA 2] Center 35 (5~65) winsize 61
3999 16:44:06.474279 [CA 3] Center 34 (4~65) winsize 62
4000 16:44:06.478195 [CA 4] Center 34 (4~65) winsize 62
4001 16:44:06.481297 [CA 5] Center 33 (3~64) winsize 62
4002 16:44:06.481439
4003 16:44:06.484267 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4004 16:44:06.484416
4005 16:44:06.487932 [CATrainingPosCal] consider 2 rank data
4006 16:44:06.491099 u2DelayCellTimex100 = 270/100 ps
4007 16:44:06.494083 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4008 16:44:06.500895 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4009 16:44:06.503969 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4010 16:44:06.507680 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4011 16:44:06.510529 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4012 16:44:06.513982 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4013 16:44:06.514136
4014 16:44:06.517157 CA PerBit enable=1, Macro0, CA PI delay=34
4015 16:44:06.517297
4016 16:44:06.520806 [CBTSetCACLKResult] CA Dly = 34
4017 16:44:06.523946 CS Dly: 7 (0~38)
4018 16:44:06.524097
4019 16:44:06.527401 ----->DramcWriteLeveling(PI) begin...
4020 16:44:06.527540 ==
4021 16:44:06.530208 Dram Type= 6, Freq= 0, CH_0, rank 0
4022 16:44:06.533959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4023 16:44:06.534104 ==
4024 16:44:06.536906 Write leveling (Byte 0): 34 => 34
4025 16:44:06.540070 Write leveling (Byte 1): 30 => 30
4026 16:44:06.543930 DramcWriteLeveling(PI) end<-----
4027 16:44:06.544054
4028 16:44:06.544128 ==
4029 16:44:06.547138 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 16:44:06.550009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 16:44:06.550168 ==
4032 16:44:06.553861 [Gating] SW mode calibration
4033 16:44:06.560112 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4034 16:44:06.566560 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4035 16:44:06.569669 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 16:44:06.573182 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 16:44:06.579810 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4038 16:44:06.583030 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4039 16:44:06.586172 0 9 16 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (1 1)
4040 16:44:06.593169 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 16:44:06.596248 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 16:44:06.602640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 16:44:06.606115 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 16:44:06.609191 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 16:44:06.616200 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 16:44:06.619094 0 10 12 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
4047 16:44:06.622211 0 10 16 | B1->B0 | 3232 4141 | 0 1 | (0 0) (0 0)
4048 16:44:06.629013 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4049 16:44:06.632126 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 16:44:06.635695 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 16:44:06.641958 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 16:44:06.645243 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 16:44:06.648614 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 16:44:06.655124 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4055 16:44:06.658691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4056 16:44:06.662146 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 16:44:06.668525 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 16:44:06.672095 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 16:44:06.675135 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 16:44:06.681736 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 16:44:06.685167 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 16:44:06.688210 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 16:44:06.694922 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 16:44:06.698470 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 16:44:06.701527 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:44:06.708448 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:44:06.711396 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:44:06.714349 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:44:06.720933 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:44:06.724513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 16:44:06.727551 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4072 16:44:06.734494 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 16:44:06.734661 Total UI for P1: 0, mck2ui 16
4074 16:44:06.741076 best dqsien dly found for B0: ( 0, 13, 14)
4075 16:44:06.741239 Total UI for P1: 0, mck2ui 16
4076 16:44:06.747408 best dqsien dly found for B1: ( 0, 13, 18)
4077 16:44:06.750752 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4078 16:44:06.754175 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4079 16:44:06.754326
4080 16:44:06.757576 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4081 16:44:06.760693 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4082 16:44:06.764241 [Gating] SW calibration Done
4083 16:44:06.764356 ==
4084 16:44:06.767676 Dram Type= 6, Freq= 0, CH_0, rank 0
4085 16:44:06.770397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4086 16:44:06.770493 ==
4087 16:44:06.774382 RX Vref Scan: 0
4088 16:44:06.774485
4089 16:44:06.774557 RX Vref 0 -> 0, step: 1
4090 16:44:06.774622
4091 16:44:06.777224 RX Delay -230 -> 252, step: 16
4092 16:44:06.783937 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4093 16:44:06.786834 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4094 16:44:06.790484 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4095 16:44:06.793693 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4096 16:44:06.797223 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4097 16:44:06.803385 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4098 16:44:06.807070 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4099 16:44:06.810204 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4100 16:44:06.813359 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4101 16:44:06.820033 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4102 16:44:06.823807 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4103 16:44:06.826594 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4104 16:44:06.830286 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4105 16:44:06.836353 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4106 16:44:06.840213 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4107 16:44:06.843257 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4108 16:44:06.843367 ==
4109 16:44:06.846835 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 16:44:06.850084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 16:44:06.853101 ==
4112 16:44:06.853212 DQS Delay:
4113 16:44:06.853284 DQS0 = 0, DQS1 = 0
4114 16:44:06.856177 DQM Delay:
4115 16:44:06.856268 DQM0 = 38, DQM1 = 30
4116 16:44:06.859674 DQ Delay:
4117 16:44:06.863098 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4118 16:44:06.866571 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4119 16:44:06.869559 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4120 16:44:06.872917 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4121 16:44:06.873029
4122 16:44:06.873101
4123 16:44:06.873165 ==
4124 16:44:06.876289 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 16:44:06.879114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 16:44:06.879215 ==
4127 16:44:06.879286
4128 16:44:06.879351
4129 16:44:06.882580 TX Vref Scan disable
4130 16:44:06.882670 == TX Byte 0 ==
4131 16:44:06.888909 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4132 16:44:06.892542 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4133 16:44:06.896107 == TX Byte 1 ==
4134 16:44:06.899229 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4135 16:44:06.902656 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4136 16:44:06.902768 ==
4137 16:44:06.905641 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 16:44:06.909279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 16:44:06.912434 ==
4140 16:44:06.912556
4141 16:44:06.912630
4142 16:44:06.912695 TX Vref Scan disable
4143 16:44:06.916129 == TX Byte 0 ==
4144 16:44:06.919209 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4145 16:44:06.925827 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4146 16:44:06.925974 == TX Byte 1 ==
4147 16:44:06.929523 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4148 16:44:06.935985 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4149 16:44:06.936123
4150 16:44:06.936196 [DATLAT]
4151 16:44:06.936262 Freq=600, CH0 RK0
4152 16:44:06.936327
4153 16:44:06.939011 DATLAT Default: 0x9
4154 16:44:06.939113 0, 0xFFFF, sum = 0
4155 16:44:06.942922 1, 0xFFFF, sum = 0
4156 16:44:06.945963 2, 0xFFFF, sum = 0
4157 16:44:06.946103 3, 0xFFFF, sum = 0
4158 16:44:06.948844 4, 0xFFFF, sum = 0
4159 16:44:06.948951 5, 0xFFFF, sum = 0
4160 16:44:06.952328 6, 0xFFFF, sum = 0
4161 16:44:06.952435 7, 0xFFFF, sum = 0
4162 16:44:06.956160 8, 0x0, sum = 1
4163 16:44:06.956270 9, 0x0, sum = 2
4164 16:44:06.959258 10, 0x0, sum = 3
4165 16:44:06.959379 11, 0x0, sum = 4
4166 16:44:06.959454 best_step = 9
4167 16:44:06.959519
4168 16:44:06.962142 ==
4169 16:44:06.965746 Dram Type= 6, Freq= 0, CH_0, rank 0
4170 16:44:06.969101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4171 16:44:06.969209 ==
4172 16:44:06.969284 RX Vref Scan: 1
4173 16:44:06.969354
4174 16:44:06.972425 RX Vref 0 -> 0, step: 1
4175 16:44:06.972528
4176 16:44:06.975813 RX Delay -195 -> 252, step: 8
4177 16:44:06.975966
4178 16:44:06.978794 Set Vref, RX VrefLevel [Byte0]: 60
4179 16:44:06.982118 [Byte1]: 55
4180 16:44:06.982245
4181 16:44:06.985657 Final RX Vref Byte 0 = 60 to rank0
4182 16:44:06.988525 Final RX Vref Byte 1 = 55 to rank0
4183 16:44:06.992067 Final RX Vref Byte 0 = 60 to rank1
4184 16:44:06.995234 Final RX Vref Byte 1 = 55 to rank1==
4185 16:44:06.998467 Dram Type= 6, Freq= 0, CH_0, rank 0
4186 16:44:07.001834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4187 16:44:07.004870 ==
4188 16:44:07.004976 DQS Delay:
4189 16:44:07.005046 DQS0 = 0, DQS1 = 0
4190 16:44:07.008507 DQM Delay:
4191 16:44:07.008608 DQM0 = 35, DQM1 = 29
4192 16:44:07.011553 DQ Delay:
4193 16:44:07.015149 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =32
4194 16:44:07.015248 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =48
4195 16:44:07.018250 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4196 16:44:07.021435 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =36
4197 16:44:07.025107
4198 16:44:07.025208
4199 16:44:07.032099 [DQSOSCAuto] RK0, (LSB)MR18= 0x4342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4200 16:44:07.034941 CH0 RK0: MR19=808, MR18=4342
4201 16:44:07.041084 CH0_RK0: MR19=0x808, MR18=0x4342, DQSOSC=397, MR23=63, INC=166, DEC=110
4202 16:44:07.041215
4203 16:44:07.044808 ----->DramcWriteLeveling(PI) begin...
4204 16:44:07.044903 ==
4205 16:44:07.047816 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 16:44:07.050961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 16:44:07.051066 ==
4208 16:44:07.054628 Write leveling (Byte 0): 32 => 32
4209 16:44:07.057971 Write leveling (Byte 1): 32 => 32
4210 16:44:07.060940 DramcWriteLeveling(PI) end<-----
4211 16:44:07.061044
4212 16:44:07.061118 ==
4213 16:44:07.064735 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 16:44:07.067789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 16:44:07.067881 ==
4216 16:44:07.070837 [Gating] SW mode calibration
4217 16:44:07.077568 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4218 16:44:07.084387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4219 16:44:07.087158 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 16:44:07.094038 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 16:44:07.097165 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4222 16:44:07.100503 0 9 12 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
4223 16:44:07.107120 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
4224 16:44:07.110677 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 16:44:07.113646 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 16:44:07.120629 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 16:44:07.123843 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 16:44:07.126790 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 16:44:07.133579 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 16:44:07.136641 0 10 12 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (0 0)
4231 16:44:07.140245 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (1 1)
4232 16:44:07.147004 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 16:44:07.150136 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 16:44:07.153248 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 16:44:07.159941 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 16:44:07.163436 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 16:44:07.166476 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 16:44:07.173059 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4239 16:44:07.176737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4240 16:44:07.179611 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 16:44:07.186220 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 16:44:07.189708 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 16:44:07.193020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 16:44:07.199611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 16:44:07.203160 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 16:44:07.206454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 16:44:07.212847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 16:44:07.216293 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:44:07.219350 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:44:07.226352 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:44:07.229267 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:44:07.232445 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:44:07.239303 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:44:07.242255 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:44:07.246033 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4256 16:44:07.249165 Total UI for P1: 0, mck2ui 16
4257 16:44:07.252247 best dqsien dly found for B0: ( 0, 13, 14)
4258 16:44:07.258900 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 16:44:07.259063 Total UI for P1: 0, mck2ui 16
4260 16:44:07.265213 best dqsien dly found for B1: ( 0, 13, 16)
4261 16:44:07.268873 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4262 16:44:07.271814 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4263 16:44:07.271942
4264 16:44:07.275038 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4265 16:44:07.278146 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4266 16:44:07.281696 [Gating] SW calibration Done
4267 16:44:07.281836 ==
4268 16:44:07.285123 Dram Type= 6, Freq= 0, CH_0, rank 1
4269 16:44:07.288285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4270 16:44:07.288420 ==
4271 16:44:07.291933 RX Vref Scan: 0
4272 16:44:07.292079
4273 16:44:07.294786 RX Vref 0 -> 0, step: 1
4274 16:44:07.294906
4275 16:44:07.295013 RX Delay -230 -> 252, step: 16
4276 16:44:07.301265 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4277 16:44:07.304871 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4278 16:44:07.308072 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4279 16:44:07.311035 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4280 16:44:07.317812 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4281 16:44:07.320922 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4282 16:44:07.324403 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4283 16:44:07.327371 iDelay=218, Bit 7, Center 41 (-134 ~ 217) 352
4284 16:44:07.333985 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4285 16:44:07.337630 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4286 16:44:07.340631 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4287 16:44:07.343794 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4288 16:44:07.350387 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4289 16:44:07.354045 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4290 16:44:07.357174 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4291 16:44:07.360153 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4292 16:44:07.363395 ==
4293 16:44:07.363526 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 16:44:07.370367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 16:44:07.370503 ==
4296 16:44:07.370611 DQS Delay:
4297 16:44:07.373546 DQS0 = 0, DQS1 = 0
4298 16:44:07.373666 DQM Delay:
4299 16:44:07.376657 DQM0 = 33, DQM1 = 27
4300 16:44:07.376769 DQ Delay:
4301 16:44:07.380132 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4302 16:44:07.383148 DQ4 =33, DQ5 =17, DQ6 =41, DQ7 =41
4303 16:44:07.386786 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4304 16:44:07.389755 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4305 16:44:07.389866
4306 16:44:07.389961
4307 16:44:07.390046 ==
4308 16:44:07.393334 Dram Type= 6, Freq= 0, CH_0, rank 1
4309 16:44:07.396646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4310 16:44:07.396748 ==
4311 16:44:07.396840
4312 16:44:07.396924
4313 16:44:07.400089 TX Vref Scan disable
4314 16:44:07.403209 == TX Byte 0 ==
4315 16:44:07.406719 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4316 16:44:07.409860 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4317 16:44:07.413277 == TX Byte 1 ==
4318 16:44:07.416622 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4319 16:44:07.419575 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4320 16:44:07.419693 ==
4321 16:44:07.422929 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 16:44:07.429390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 16:44:07.429534 ==
4324 16:44:07.429636
4325 16:44:07.429734
4326 16:44:07.429827 TX Vref Scan disable
4327 16:44:07.434039 == TX Byte 0 ==
4328 16:44:07.437499 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4329 16:44:07.444136 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4330 16:44:07.444283 == TX Byte 1 ==
4331 16:44:07.447367 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4332 16:44:07.454017 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4333 16:44:07.454150
4334 16:44:07.454254 [DATLAT]
4335 16:44:07.454345 Freq=600, CH0 RK1
4336 16:44:07.454438
4337 16:44:07.457173 DATLAT Default: 0x9
4338 16:44:07.460195 0, 0xFFFF, sum = 0
4339 16:44:07.460319 1, 0xFFFF, sum = 0
4340 16:44:07.463267 2, 0xFFFF, sum = 0
4341 16:44:07.463382 3, 0xFFFF, sum = 0
4342 16:44:07.466935 4, 0xFFFF, sum = 0
4343 16:44:07.467078 5, 0xFFFF, sum = 0
4344 16:44:07.470153 6, 0xFFFF, sum = 0
4345 16:44:07.470271 7, 0xFFFF, sum = 0
4346 16:44:07.473516 8, 0x0, sum = 1
4347 16:44:07.473643 9, 0x0, sum = 2
4348 16:44:07.476660 10, 0x0, sum = 3
4349 16:44:07.476778 11, 0x0, sum = 4
4350 16:44:07.476883 best_step = 9
4351 16:44:07.476978
4352 16:44:07.479791 ==
4353 16:44:07.483473 Dram Type= 6, Freq= 0, CH_0, rank 1
4354 16:44:07.486636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 16:44:07.486768 ==
4356 16:44:07.486874 RX Vref Scan: 0
4357 16:44:07.486976
4358 16:44:07.489721 RX Vref 0 -> 0, step: 1
4359 16:44:07.489836
4360 16:44:07.493189 RX Delay -195 -> 252, step: 8
4361 16:44:07.499327 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4362 16:44:07.503012 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4363 16:44:07.506134 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4364 16:44:07.509867 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4365 16:44:07.516494 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4366 16:44:07.519213 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4367 16:44:07.522736 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4368 16:44:07.526335 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4369 16:44:07.529618 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4370 16:44:07.535980 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4371 16:44:07.538816 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4372 16:44:07.542306 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4373 16:44:07.545713 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4374 16:44:07.552125 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4375 16:44:07.555654 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4376 16:44:07.558577 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4377 16:44:07.558710 ==
4378 16:44:07.561853 Dram Type= 6, Freq= 0, CH_0, rank 1
4379 16:44:07.568411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 16:44:07.568565 ==
4381 16:44:07.568673 DQS Delay:
4382 16:44:07.571625 DQS0 = 0, DQS1 = 0
4383 16:44:07.571737 DQM Delay:
4384 16:44:07.571836 DQM0 = 33, DQM1 = 28
4385 16:44:07.574800 DQ Delay:
4386 16:44:07.578112 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4387 16:44:07.581804 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4388 16:44:07.584878 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4389 16:44:07.588124 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4390 16:44:07.588255
4391 16:44:07.588362
4392 16:44:07.594763 [DQSOSCAuto] RK1, (LSB)MR18= 0x703f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4393 16:44:07.598195 CH0 RK1: MR19=808, MR18=703F
4394 16:44:07.604938 CH0_RK1: MR19=0x808, MR18=0x703F, DQSOSC=388, MR23=63, INC=174, DEC=116
4395 16:44:07.608159 [RxdqsGatingPostProcess] freq 600
4396 16:44:07.611754 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4397 16:44:07.614876 Pre-setting of DQS Precalculation
4398 16:44:07.621385 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4399 16:44:07.621534 ==
4400 16:44:07.624430 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 16:44:07.627838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 16:44:07.627969 ==
4403 16:44:07.634971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4404 16:44:07.641236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4405 16:44:07.644567 [CA 0] Center 36 (6~66) winsize 61
4406 16:44:07.647571 [CA 1] Center 36 (6~66) winsize 61
4407 16:44:07.651052 [CA 2] Center 34 (4~65) winsize 62
4408 16:44:07.654237 [CA 3] Center 34 (4~65) winsize 62
4409 16:44:07.657619 [CA 4] Center 34 (4~65) winsize 62
4410 16:44:07.660832 [CA 5] Center 33 (3~64) winsize 62
4411 16:44:07.660971
4412 16:44:07.664185 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4413 16:44:07.664312
4414 16:44:07.667404 [CATrainingPosCal] consider 1 rank data
4415 16:44:07.670542 u2DelayCellTimex100 = 270/100 ps
4416 16:44:07.673751 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4417 16:44:07.677410 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4418 16:44:07.680371 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4419 16:44:07.684037 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4420 16:44:07.687226 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4421 16:44:07.693915 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4422 16:44:07.694094
4423 16:44:07.697058 CA PerBit enable=1, Macro0, CA PI delay=33
4424 16:44:07.697165
4425 16:44:07.700093 [CBTSetCACLKResult] CA Dly = 33
4426 16:44:07.700192 CS Dly: 4 (0~35)
4427 16:44:07.700262 ==
4428 16:44:07.703618 Dram Type= 6, Freq= 0, CH_1, rank 1
4429 16:44:07.706787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 16:44:07.710431 ==
4431 16:44:07.713476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 16:44:07.720104 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4433 16:44:07.723090 [CA 0] Center 35 (5~66) winsize 62
4434 16:44:07.726796 [CA 1] Center 36 (6~66) winsize 61
4435 16:44:07.729944 [CA 2] Center 34 (4~65) winsize 62
4436 16:44:07.733365 [CA 3] Center 34 (3~65) winsize 63
4437 16:44:07.736329 [CA 4] Center 34 (4~65) winsize 62
4438 16:44:07.740015 [CA 5] Center 34 (3~65) winsize 63
4439 16:44:07.740154
4440 16:44:07.743202 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4441 16:44:07.743330
4442 16:44:07.746618 [CATrainingPosCal] consider 2 rank data
4443 16:44:07.749502 u2DelayCellTimex100 = 270/100 ps
4444 16:44:07.752985 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 16:44:07.756449 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 16:44:07.763020 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 16:44:07.766662 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 16:44:07.769808 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 16:44:07.772715 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 16:44:07.772843
4451 16:44:07.776554 CA PerBit enable=1, Macro0, CA PI delay=33
4452 16:44:07.776682
4453 16:44:07.779569 [CBTSetCACLKResult] CA Dly = 33
4454 16:44:07.779699 CS Dly: 5 (0~37)
4455 16:44:07.779805
4456 16:44:07.786103 ----->DramcWriteLeveling(PI) begin...
4457 16:44:07.786260 ==
4458 16:44:07.789211 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 16:44:07.793020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 16:44:07.793132 ==
4461 16:44:07.796206 Write leveling (Byte 0): 28 => 28
4462 16:44:07.799122 Write leveling (Byte 1): 32 => 32
4463 16:44:07.802718 DramcWriteLeveling(PI) end<-----
4464 16:44:07.802824
4465 16:44:07.802901 ==
4466 16:44:07.805879 Dram Type= 6, Freq= 0, CH_1, rank 0
4467 16:44:07.808872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4468 16:44:07.808997 ==
4469 16:44:07.812515 [Gating] SW mode calibration
4470 16:44:07.819220 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4471 16:44:07.825821 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4472 16:44:07.828888 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 16:44:07.832059 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 16:44:07.839048 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 16:44:07.842006 0 9 12 | B1->B0 | 3131 3131 | 0 1 | (1 0) (1 0)
4476 16:44:07.845474 0 9 16 | B1->B0 | 2525 2525 | 0 0 | (1 1) (0 0)
4477 16:44:07.851848 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 16:44:07.855429 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 16:44:07.858342 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 16:44:07.864957 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 16:44:07.868148 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 16:44:07.871834 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 16:44:07.878008 0 10 12 | B1->B0 | 2f2f 3131 | 1 0 | (1 1) (0 0)
4484 16:44:07.881752 0 10 16 | B1->B0 | 4141 4040 | 0 0 | (0 0) (0 0)
4485 16:44:07.884942 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 16:44:07.891337 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 16:44:07.894886 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 16:44:07.897828 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 16:44:07.904627 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 16:44:07.907765 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 16:44:07.911247 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4492 16:44:07.917328 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4493 16:44:07.921074 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 16:44:07.924055 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 16:44:07.930876 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 16:44:07.933936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 16:44:07.937607 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 16:44:07.943850 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 16:44:07.947421 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 16:44:07.950301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:44:07.957122 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:44:07.960449 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:44:07.963899 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:44:07.970555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:44:07.973663 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:44:07.977129 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:44:07.983211 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4508 16:44:07.986600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4509 16:44:07.990078 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 16:44:07.993651 Total UI for P1: 0, mck2ui 16
4511 16:44:07.996657 best dqsien dly found for B0: ( 0, 13, 14)
4512 16:44:07.999774 Total UI for P1: 0, mck2ui 16
4513 16:44:08.003300 best dqsien dly found for B1: ( 0, 13, 16)
4514 16:44:08.006484 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4515 16:44:08.013151 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4516 16:44:08.013308
4517 16:44:08.016672 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4518 16:44:08.019794 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4519 16:44:08.022823 [Gating] SW calibration Done
4520 16:44:08.022919 ==
4521 16:44:08.026514 Dram Type= 6, Freq= 0, CH_1, rank 0
4522 16:44:08.029727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4523 16:44:08.029827 ==
4524 16:44:08.033140 RX Vref Scan: 0
4525 16:44:08.033237
4526 16:44:08.033307 RX Vref 0 -> 0, step: 1
4527 16:44:08.033373
4528 16:44:08.036242 RX Delay -230 -> 252, step: 16
4529 16:44:08.039974 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4530 16:44:08.046147 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4531 16:44:08.049128 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4532 16:44:08.052855 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4533 16:44:08.055700 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4534 16:44:08.062563 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4535 16:44:08.065855 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4536 16:44:08.068949 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4537 16:44:08.072380 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4538 16:44:08.075970 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4539 16:44:08.082426 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4540 16:44:08.085879 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4541 16:44:08.088794 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4542 16:44:08.092024 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4543 16:44:08.098923 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4544 16:44:08.102381 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4545 16:44:08.102515 ==
4546 16:44:08.105601 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 16:44:08.108497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 16:44:08.108616 ==
4549 16:44:08.112205 DQS Delay:
4550 16:44:08.112295 DQS0 = 0, DQS1 = 0
4551 16:44:08.115201 DQM Delay:
4552 16:44:08.115289 DQM0 = 39, DQM1 = 29
4553 16:44:08.115371 DQ Delay:
4554 16:44:08.118947 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4555 16:44:08.121850 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4556 16:44:08.125455 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4557 16:44:08.128551 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4558 16:44:08.128665
4559 16:44:08.128737
4560 16:44:08.131757 ==
4561 16:44:08.135458 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 16:44:08.138433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 16:44:08.138564 ==
4564 16:44:08.138638
4565 16:44:08.138702
4566 16:44:08.142025 TX Vref Scan disable
4567 16:44:08.142166 == TX Byte 0 ==
4568 16:44:08.148287 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4569 16:44:08.151940 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4570 16:44:08.152055 == TX Byte 1 ==
4571 16:44:08.158002 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4572 16:44:08.161421 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4573 16:44:08.161540 ==
4574 16:44:08.165033 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 16:44:08.168283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 16:44:08.168396 ==
4577 16:44:08.168468
4578 16:44:08.168532
4579 16:44:08.171753 TX Vref Scan disable
4580 16:44:08.174767 == TX Byte 0 ==
4581 16:44:08.178144 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4582 16:44:08.181084 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4583 16:44:08.184662 == TX Byte 1 ==
4584 16:44:08.187714 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4585 16:44:08.191318 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4586 16:44:08.194351
4587 16:44:08.194493 [DATLAT]
4588 16:44:08.194594 Freq=600, CH1 RK0
4589 16:44:08.194689
4590 16:44:08.198214 DATLAT Default: 0x9
4591 16:44:08.198341 0, 0xFFFF, sum = 0
4592 16:44:08.200876 1, 0xFFFF, sum = 0
4593 16:44:08.201019 2, 0xFFFF, sum = 0
4594 16:44:08.204385 3, 0xFFFF, sum = 0
4595 16:44:08.204509 4, 0xFFFF, sum = 0
4596 16:44:08.207833 5, 0xFFFF, sum = 0
4597 16:44:08.210768 6, 0xFFFF, sum = 0
4598 16:44:08.210930 7, 0xFFFF, sum = 0
4599 16:44:08.214552 8, 0x0, sum = 1
4600 16:44:08.214688 9, 0x0, sum = 2
4601 16:44:08.214793 10, 0x0, sum = 3
4602 16:44:08.217549 11, 0x0, sum = 4
4603 16:44:08.217668 best_step = 9
4604 16:44:08.217766
4605 16:44:08.217861 ==
4606 16:44:08.220747 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 16:44:08.227809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 16:44:08.227975 ==
4609 16:44:08.228087 RX Vref Scan: 1
4610 16:44:08.228182
4611 16:44:08.230871 RX Vref 0 -> 0, step: 1
4612 16:44:08.230986
4613 16:44:08.234037 RX Delay -195 -> 252, step: 8
4614 16:44:08.234155
4615 16:44:08.237073 Set Vref, RX VrefLevel [Byte0]: 58
4616 16:44:08.240752 [Byte1]: 50
4617 16:44:08.240918
4618 16:44:08.243818 Final RX Vref Byte 0 = 58 to rank0
4619 16:44:08.247424 Final RX Vref Byte 1 = 50 to rank0
4620 16:44:08.250543 Final RX Vref Byte 0 = 58 to rank1
4621 16:44:08.253617 Final RX Vref Byte 1 = 50 to rank1==
4622 16:44:08.257284 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 16:44:08.260425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 16:44:08.260580 ==
4625 16:44:08.263918 DQS Delay:
4626 16:44:08.264037 DQS0 = 0, DQS1 = 0
4627 16:44:08.267269 DQM Delay:
4628 16:44:08.267381 DQM0 = 39, DQM1 = 29
4629 16:44:08.267481 DQ Delay:
4630 16:44:08.270182 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =32
4631 16:44:08.273739 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4632 16:44:08.277329 DQ8 =16, DQ9 =16, DQ10 =32, DQ11 =20
4633 16:44:08.280297 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4634 16:44:08.280406
4635 16:44:08.283671
4636 16:44:08.290295 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4637 16:44:08.293178 CH1 RK0: MR19=808, MR18=1E2B
4638 16:44:08.299911 CH1_RK0: MR19=0x808, MR18=0x1E2B, DQSOSC=401, MR23=63, INC=163, DEC=108
4639 16:44:08.300043
4640 16:44:08.303687 ----->DramcWriteLeveling(PI) begin...
4641 16:44:08.303786 ==
4642 16:44:08.306353 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 16:44:08.309858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 16:44:08.309960 ==
4645 16:44:08.313217 Write leveling (Byte 0): 30 => 30
4646 16:44:08.316704 Write leveling (Byte 1): 28 => 28
4647 16:44:08.319673 DramcWriteLeveling(PI) end<-----
4648 16:44:08.319777
4649 16:44:08.319862 ==
4650 16:44:08.322726 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 16:44:08.326358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 16:44:08.326494 ==
4653 16:44:08.329815 [Gating] SW mode calibration
4654 16:44:08.336584 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4655 16:44:08.342942 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4656 16:44:08.346511 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4657 16:44:08.352580 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 16:44:08.356073 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 16:44:08.359164 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
4660 16:44:08.365997 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4661 16:44:08.369135 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 16:44:08.372324 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 16:44:08.379215 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 16:44:08.382959 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 16:44:08.385936 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 16:44:08.392745 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4667 16:44:08.395661 0 10 12 | B1->B0 | 302f 4040 | 1 0 | (0 0) (0 0)
4668 16:44:08.399239 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4669 16:44:08.405805 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 16:44:08.408941 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 16:44:08.412413 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 16:44:08.415843 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 16:44:08.422051 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 16:44:08.425631 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 16:44:08.428845 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 16:44:08.435353 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 16:44:08.438476 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 16:44:08.442026 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 16:44:08.448879 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 16:44:08.451678 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 16:44:08.454787 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 16:44:08.461616 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 16:44:08.465200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:44:08.468399 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:44:08.475030 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:44:08.478464 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:44:08.481361 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:44:08.487882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:44:08.491164 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:44:08.494684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:44:08.501051 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4692 16:44:08.504769 Total UI for P1: 0, mck2ui 16
4693 16:44:08.507680 best dqsien dly found for B0: ( 0, 13, 10)
4694 16:44:08.511357 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 16:44:08.514359 Total UI for P1: 0, mck2ui 16
4696 16:44:08.517876 best dqsien dly found for B1: ( 0, 13, 14)
4697 16:44:08.520771 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4698 16:44:08.523994 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4699 16:44:08.524090
4700 16:44:08.527614 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4701 16:44:08.533940 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4702 16:44:08.534063 [Gating] SW calibration Done
4703 16:44:08.537695 ==
4704 16:44:08.537790 Dram Type= 6, Freq= 0, CH_1, rank 1
4705 16:44:08.544408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4706 16:44:08.544531 ==
4707 16:44:08.544604 RX Vref Scan: 0
4708 16:44:08.544675
4709 16:44:08.547478 RX Vref 0 -> 0, step: 1
4710 16:44:08.547599
4711 16:44:08.550607 RX Delay -230 -> 252, step: 16
4712 16:44:08.554265 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4713 16:44:08.557107 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4714 16:44:08.564010 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4715 16:44:08.567253 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4716 16:44:08.570292 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4717 16:44:08.573921 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4718 16:44:08.577028 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4719 16:44:08.583758 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4720 16:44:08.587001 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4721 16:44:08.589991 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4722 16:44:08.593968 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4723 16:44:08.599976 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4724 16:44:08.603333 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4725 16:44:08.607053 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4726 16:44:08.610004 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4727 16:44:08.616440 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4728 16:44:08.616590 ==
4729 16:44:08.620021 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 16:44:08.623035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 16:44:08.623179 ==
4732 16:44:08.626269 DQS Delay:
4733 16:44:08.626379 DQS0 = 0, DQS1 = 0
4734 16:44:08.626452 DQM Delay:
4735 16:44:08.629831 DQM0 = 35, DQM1 = 29
4736 16:44:08.629941 DQ Delay:
4737 16:44:08.632738 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4738 16:44:08.636039 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4739 16:44:08.639781 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4740 16:44:08.642619 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4741 16:44:08.642759
4742 16:44:08.642860
4743 16:44:08.642977 ==
4744 16:44:08.646330 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 16:44:08.652470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 16:44:08.652626 ==
4747 16:44:08.652737
4748 16:44:08.652844
4749 16:44:08.652935 TX Vref Scan disable
4750 16:44:08.656211 == TX Byte 0 ==
4751 16:44:08.659975 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4752 16:44:08.665905 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4753 16:44:08.666070 == TX Byte 1 ==
4754 16:44:08.669511 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4755 16:44:08.675849 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4756 16:44:08.676031 ==
4757 16:44:08.679643 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 16:44:08.682618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 16:44:08.682761 ==
4760 16:44:08.682858
4761 16:44:08.682982
4762 16:44:08.685768 TX Vref Scan disable
4763 16:44:08.689351 == TX Byte 0 ==
4764 16:44:08.692285 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4765 16:44:08.695652 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4766 16:44:08.699137 == TX Byte 1 ==
4767 16:44:08.701994 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4768 16:44:08.705529 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4769 16:44:08.705664
4770 16:44:08.708998 [DATLAT]
4771 16:44:08.709115 Freq=600, CH1 RK1
4772 16:44:08.709222
4773 16:44:08.711839 DATLAT Default: 0x9
4774 16:44:08.711973 0, 0xFFFF, sum = 0
4775 16:44:08.715489 1, 0xFFFF, sum = 0
4776 16:44:08.715659 2, 0xFFFF, sum = 0
4777 16:44:08.718888 3, 0xFFFF, sum = 0
4778 16:44:08.718997 4, 0xFFFF, sum = 0
4779 16:44:08.721981 5, 0xFFFF, sum = 0
4780 16:44:08.722123 6, 0xFFFF, sum = 0
4781 16:44:08.725160 7, 0xFFFF, sum = 0
4782 16:44:08.725264 8, 0x0, sum = 1
4783 16:44:08.728952 9, 0x0, sum = 2
4784 16:44:08.729110 10, 0x0, sum = 3
4785 16:44:08.731937 11, 0x0, sum = 4
4786 16:44:08.732052 best_step = 9
4787 16:44:08.732186
4788 16:44:08.732285 ==
4789 16:44:08.735117 Dram Type= 6, Freq= 0, CH_1, rank 1
4790 16:44:08.738525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4791 16:44:08.741956 ==
4792 16:44:08.742101 RX Vref Scan: 0
4793 16:44:08.742199
4794 16:44:08.744830 RX Vref 0 -> 0, step: 1
4795 16:44:08.744946
4796 16:44:08.748240 RX Delay -195 -> 252, step: 8
4797 16:44:08.751715 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4798 16:44:08.754772 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4799 16:44:08.761442 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4800 16:44:08.764593 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4801 16:44:08.768344 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4802 16:44:08.771516 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4803 16:44:08.777860 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4804 16:44:08.781432 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4805 16:44:08.784541 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4806 16:44:08.788143 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4807 16:44:08.794248 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4808 16:44:08.797778 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4809 16:44:08.800800 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4810 16:44:08.804372 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4811 16:44:08.810772 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4812 16:44:08.814122 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4813 16:44:08.814250 ==
4814 16:44:08.817407 Dram Type= 6, Freq= 0, CH_1, rank 1
4815 16:44:08.820791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4816 16:44:08.820952 ==
4817 16:44:08.824233 DQS Delay:
4818 16:44:08.824378 DQS0 = 0, DQS1 = 0
4819 16:44:08.824492 DQM Delay:
4820 16:44:08.826967 DQM0 = 35, DQM1 = 29
4821 16:44:08.827095 DQ Delay:
4822 16:44:08.830889 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4823 16:44:08.833775 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =36
4824 16:44:08.837429 DQ8 =16, DQ9 =16, DQ10 =36, DQ11 =20
4825 16:44:08.840580 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4826 16:44:08.840733
4827 16:44:08.840839
4828 16:44:08.850480 [DQSOSCAuto] RK1, (LSB)MR18= 0x3555, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4829 16:44:08.853580 CH1 RK1: MR19=808, MR18=3555
4830 16:44:08.856853 CH1_RK1: MR19=0x808, MR18=0x3555, DQSOSC=393, MR23=63, INC=169, DEC=113
4831 16:44:08.860268 [RxdqsGatingPostProcess] freq 600
4832 16:44:08.866922 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4833 16:44:08.870019 Pre-setting of DQS Precalculation
4834 16:44:08.873660 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4835 16:44:08.883629 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4836 16:44:08.889858 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4837 16:44:08.890013
4838 16:44:08.890127
4839 16:44:08.893447 [Calibration Summary] 1200 Mbps
4840 16:44:08.893545 CH 0, Rank 0
4841 16:44:08.896565 SW Impedance : PASS
4842 16:44:08.896662 DUTY Scan : NO K
4843 16:44:08.899738 ZQ Calibration : PASS
4844 16:44:08.903173 Jitter Meter : NO K
4845 16:44:08.903322 CBT Training : PASS
4846 16:44:08.906307 Write leveling : PASS
4847 16:44:08.909588 RX DQS gating : PASS
4848 16:44:08.909683 RX DQ/DQS(RDDQC) : PASS
4849 16:44:08.913147 TX DQ/DQS : PASS
4850 16:44:08.916672 RX DATLAT : PASS
4851 16:44:08.916777 RX DQ/DQS(Engine): PASS
4852 16:44:08.920014 TX OE : NO K
4853 16:44:08.920153 All Pass.
4854 16:44:08.920256
4855 16:44:08.923303 CH 0, Rank 1
4856 16:44:08.923400 SW Impedance : PASS
4857 16:44:08.926155 DUTY Scan : NO K
4858 16:44:08.929559 ZQ Calibration : PASS
4859 16:44:08.929673 Jitter Meter : NO K
4860 16:44:08.932663 CBT Training : PASS
4861 16:44:08.936167 Write leveling : PASS
4862 16:44:08.936299 RX DQS gating : PASS
4863 16:44:08.939482 RX DQ/DQS(RDDQC) : PASS
4864 16:44:08.942481 TX DQ/DQS : PASS
4865 16:44:08.942584 RX DATLAT : PASS
4866 16:44:08.946146 RX DQ/DQS(Engine): PASS
4867 16:44:08.949464 TX OE : NO K
4868 16:44:08.949598 All Pass.
4869 16:44:08.949706
4870 16:44:08.949817 CH 1, Rank 0
4871 16:44:08.952738 SW Impedance : PASS
4872 16:44:08.955542 DUTY Scan : NO K
4873 16:44:08.955686 ZQ Calibration : PASS
4874 16:44:08.959049 Jitter Meter : NO K
4875 16:44:08.959137 CBT Training : PASS
4876 16:44:08.962551 Write leveling : PASS
4877 16:44:08.965670 RX DQS gating : PASS
4878 16:44:08.965779 RX DQ/DQS(RDDQC) : PASS
4879 16:44:08.968957 TX DQ/DQS : PASS
4880 16:44:08.972765 RX DATLAT : PASS
4881 16:44:08.972868 RX DQ/DQS(Engine): PASS
4882 16:44:08.975631 TX OE : NO K
4883 16:44:08.975755 All Pass.
4884 16:44:08.975829
4885 16:44:08.978615 CH 1, Rank 1
4886 16:44:08.978742 SW Impedance : PASS
4887 16:44:08.982390 DUTY Scan : NO K
4888 16:44:08.985245 ZQ Calibration : PASS
4889 16:44:08.985383 Jitter Meter : NO K
4890 16:44:08.989168 CBT Training : PASS
4891 16:44:08.992391 Write leveling : PASS
4892 16:44:08.992535 RX DQS gating : PASS
4893 16:44:08.995167 RX DQ/DQS(RDDQC) : PASS
4894 16:44:08.998771 TX DQ/DQS : PASS
4895 16:44:08.998947 RX DATLAT : PASS
4896 16:44:09.001825 RX DQ/DQS(Engine): PASS
4897 16:44:09.005704 TX OE : NO K
4898 16:44:09.005901 All Pass.
4899 16:44:09.005994
4900 16:44:09.008674 DramC Write-DBI off
4901 16:44:09.008795 PER_BANK_REFRESH: Hybrid Mode
4902 16:44:09.011631 TX_TRACKING: ON
4903 16:44:09.018845 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4904 16:44:09.025301 [FAST_K] Save calibration result to emmc
4905 16:44:09.028516 dramc_set_vcore_voltage set vcore to 662500
4906 16:44:09.028639 Read voltage for 933, 3
4907 16:44:09.031474 Vio18 = 0
4908 16:44:09.031606 Vcore = 662500
4909 16:44:09.031680 Vdram = 0
4910 16:44:09.035198 Vddq = 0
4911 16:44:09.035317 Vmddr = 0
4912 16:44:09.038152 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4913 16:44:09.044643 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4914 16:44:09.048011 MEM_TYPE=3, freq_sel=17
4915 16:44:09.051109 sv_algorithm_assistance_LP4_1600
4916 16:44:09.054807 ============ PULL DRAM RESETB DOWN ============
4917 16:44:09.057956 ========== PULL DRAM RESETB DOWN end =========
4918 16:44:09.064447 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4919 16:44:09.068199 ===================================
4920 16:44:09.068354 LPDDR4 DRAM CONFIGURATION
4921 16:44:09.071217 ===================================
4922 16:44:09.074409 EX_ROW_EN[0] = 0x0
4923 16:44:09.074529 EX_ROW_EN[1] = 0x0
4924 16:44:09.077851 LP4Y_EN = 0x0
4925 16:44:09.080874 WORK_FSP = 0x0
4926 16:44:09.081015 WL = 0x3
4927 16:44:09.084414 RL = 0x3
4928 16:44:09.084517 BL = 0x2
4929 16:44:09.087440 RPST = 0x0
4930 16:44:09.087595 RD_PRE = 0x0
4931 16:44:09.091095 WR_PRE = 0x1
4932 16:44:09.091229 WR_PST = 0x0
4933 16:44:09.094133 DBI_WR = 0x0
4934 16:44:09.094235 DBI_RD = 0x0
4935 16:44:09.097843 OTF = 0x1
4936 16:44:09.100679 ===================================
4937 16:44:09.103885 ===================================
4938 16:44:09.103987 ANA top config
4939 16:44:09.107614 ===================================
4940 16:44:09.110786 DLL_ASYNC_EN = 0
4941 16:44:09.113878 ALL_SLAVE_EN = 1
4942 16:44:09.117536 NEW_RANK_MODE = 1
4943 16:44:09.117633 DLL_IDLE_MODE = 1
4944 16:44:09.120565 LP45_APHY_COMB_EN = 1
4945 16:44:09.123969 TX_ODT_DIS = 1
4946 16:44:09.127495 NEW_8X_MODE = 1
4947 16:44:09.130482 ===================================
4948 16:44:09.133458 ===================================
4949 16:44:09.136907 data_rate = 1866
4950 16:44:09.137019 CKR = 1
4951 16:44:09.140345 DQ_P2S_RATIO = 8
4952 16:44:09.143287 ===================================
4953 16:44:09.146907 CA_P2S_RATIO = 8
4954 16:44:09.150413 DQ_CA_OPEN = 0
4955 16:44:09.153705 DQ_SEMI_OPEN = 0
4956 16:44:09.156721 CA_SEMI_OPEN = 0
4957 16:44:09.156820 CA_FULL_RATE = 0
4958 16:44:09.160312 DQ_CKDIV4_EN = 1
4959 16:44:09.163313 CA_CKDIV4_EN = 1
4960 16:44:09.166285 CA_PREDIV_EN = 0
4961 16:44:09.170050 PH8_DLY = 0
4962 16:44:09.173124 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4963 16:44:09.173237 DQ_AAMCK_DIV = 4
4964 16:44:09.176816 CA_AAMCK_DIV = 4
4965 16:44:09.179920 CA_ADMCK_DIV = 4
4966 16:44:09.183029 DQ_TRACK_CA_EN = 0
4967 16:44:09.186103 CA_PICK = 933
4968 16:44:09.189705 CA_MCKIO = 933
4969 16:44:09.192856 MCKIO_SEMI = 0
4970 16:44:09.196424 PLL_FREQ = 3732
4971 16:44:09.196552 DQ_UI_PI_RATIO = 32
4972 16:44:09.199376 CA_UI_PI_RATIO = 0
4973 16:44:09.202974 ===================================
4974 16:44:09.206125 ===================================
4975 16:44:09.209851 memory_type:LPDDR4
4976 16:44:09.212887 GP_NUM : 10
4977 16:44:09.213010 SRAM_EN : 1
4978 16:44:09.216163 MD32_EN : 0
4979 16:44:09.219170 ===================================
4980 16:44:09.222238 [ANA_INIT] >>>>>>>>>>>>>>
4981 16:44:09.222333 <<<<<< [CONFIGURE PHASE]: ANA_TX
4982 16:44:09.226047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4983 16:44:09.229016 ===================================
4984 16:44:09.232161 data_rate = 1866,PCW = 0X8f00
4985 16:44:09.235512 ===================================
4986 16:44:09.239081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4987 16:44:09.245527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4988 16:44:09.251996 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 16:44:09.254992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4990 16:44:09.258708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4991 16:44:09.261973 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4992 16:44:09.265045 [ANA_INIT] flow start
4993 16:44:09.268483 [ANA_INIT] PLL >>>>>>>>
4994 16:44:09.268575 [ANA_INIT] PLL <<<<<<<<
4995 16:44:09.271490 [ANA_INIT] MIDPI >>>>>>>>
4996 16:44:09.274677 [ANA_INIT] MIDPI <<<<<<<<
4997 16:44:09.274787 [ANA_INIT] DLL >>>>>>>>
4998 16:44:09.278433 [ANA_INIT] flow end
4999 16:44:09.281291 ============ LP4 DIFF to SE enter ============
5000 16:44:09.285057 ============ LP4 DIFF to SE exit ============
5001 16:44:09.288092 [ANA_INIT] <<<<<<<<<<<<<
5002 16:44:09.291321 [Flow] Enable top DCM control >>>>>
5003 16:44:09.294895 [Flow] Enable top DCM control <<<<<
5004 16:44:09.297934 Enable DLL master slave shuffle
5005 16:44:09.304692 ==============================================================
5006 16:44:09.304810 Gating Mode config
5007 16:44:09.311290 ==============================================================
5008 16:44:09.314449 Config description:
5009 16:44:09.320993 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5010 16:44:09.328103 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5011 16:44:09.334140 SELPH_MODE 0: By rank 1: By Phase
5012 16:44:09.340779 ==============================================================
5013 16:44:09.340869 GAT_TRACK_EN = 1
5014 16:44:09.344324 RX_GATING_MODE = 2
5015 16:44:09.347559 RX_GATING_TRACK_MODE = 2
5016 16:44:09.350606 SELPH_MODE = 1
5017 16:44:09.353992 PICG_EARLY_EN = 1
5018 16:44:09.357278 VALID_LAT_VALUE = 1
5019 16:44:09.363993 ==============================================================
5020 16:44:09.367005 Enter into Gating configuration >>>>
5021 16:44:09.370317 Exit from Gating configuration <<<<
5022 16:44:09.373868 Enter into DVFS_PRE_config >>>>>
5023 16:44:09.383485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5024 16:44:09.387190 Exit from DVFS_PRE_config <<<<<
5025 16:44:09.390102 Enter into PICG configuration >>>>
5026 16:44:09.393938 Exit from PICG configuration <<<<
5027 16:44:09.397052 [RX_INPUT] configuration >>>>>
5028 16:44:09.400355 [RX_INPUT] configuration <<<<<
5029 16:44:09.403380 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5030 16:44:09.409646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5031 16:44:09.416404 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5032 16:44:09.423431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5033 16:44:09.426501 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5034 16:44:09.432650 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5035 16:44:09.439254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5036 16:44:09.442994 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5037 16:44:09.446020 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5038 16:44:09.449555 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5039 16:44:09.455887 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5040 16:44:09.459493 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5041 16:44:09.462314 ===================================
5042 16:44:09.465567 LPDDR4 DRAM CONFIGURATION
5043 16:44:09.468969 ===================================
5044 16:44:09.469083 EX_ROW_EN[0] = 0x0
5045 16:44:09.472431 EX_ROW_EN[1] = 0x0
5046 16:44:09.472510 LP4Y_EN = 0x0
5047 16:44:09.475862 WORK_FSP = 0x0
5048 16:44:09.475941 WL = 0x3
5049 16:44:09.478867 RL = 0x3
5050 16:44:09.478972 BL = 0x2
5051 16:44:09.482070 RPST = 0x0
5052 16:44:09.482169 RD_PRE = 0x0
5053 16:44:09.485631 WR_PRE = 0x1
5054 16:44:09.489145 WR_PST = 0x0
5055 16:44:09.489261 DBI_WR = 0x0
5056 16:44:09.492339 DBI_RD = 0x0
5057 16:44:09.492425 OTF = 0x1
5058 16:44:09.495405 ===================================
5059 16:44:09.498499 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5060 16:44:09.505026 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5061 16:44:09.508407 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5062 16:44:09.511916 ===================================
5063 16:44:09.515483 LPDDR4 DRAM CONFIGURATION
5064 16:44:09.518685 ===================================
5065 16:44:09.518783 EX_ROW_EN[0] = 0x10
5066 16:44:09.521886 EX_ROW_EN[1] = 0x0
5067 16:44:09.521980 LP4Y_EN = 0x0
5068 16:44:09.525035 WORK_FSP = 0x0
5069 16:44:09.525161 WL = 0x3
5070 16:44:09.528706 RL = 0x3
5071 16:44:09.531782 BL = 0x2
5072 16:44:09.531881 RPST = 0x0
5073 16:44:09.534879 RD_PRE = 0x0
5074 16:44:09.534989 WR_PRE = 0x1
5075 16:44:09.538078 WR_PST = 0x0
5076 16:44:09.538198 DBI_WR = 0x0
5077 16:44:09.541275 DBI_RD = 0x0
5078 16:44:09.541362 OTF = 0x1
5079 16:44:09.544865 ===================================
5080 16:44:09.551615 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5081 16:44:09.555101 nWR fixed to 30
5082 16:44:09.558750 [ModeRegInit_LP4] CH0 RK0
5083 16:44:09.558865 [ModeRegInit_LP4] CH0 RK1
5084 16:44:09.562031 [ModeRegInit_LP4] CH1 RK0
5085 16:44:09.565147 [ModeRegInit_LP4] CH1 RK1
5086 16:44:09.565252 match AC timing 9
5087 16:44:09.571909 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5088 16:44:09.575284 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5089 16:44:09.578349 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5090 16:44:09.585044 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5091 16:44:09.588127 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5092 16:44:09.588241 ==
5093 16:44:09.591328 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 16:44:09.594579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 16:44:09.598186 ==
5096 16:44:09.601283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5097 16:44:09.608055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5098 16:44:09.611253 [CA 0] Center 38 (8~69) winsize 62
5099 16:44:09.615201 [CA 1] Center 38 (7~69) winsize 63
5100 16:44:09.618209 [CA 2] Center 35 (5~65) winsize 61
5101 16:44:09.621656 [CA 3] Center 35 (5~65) winsize 61
5102 16:44:09.624640 [CA 4] Center 34 (4~65) winsize 62
5103 16:44:09.627568 [CA 5] Center 33 (3~64) winsize 62
5104 16:44:09.627673
5105 16:44:09.631212 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5106 16:44:09.631320
5107 16:44:09.634461 [CATrainingPosCal] consider 1 rank data
5108 16:44:09.637536 u2DelayCellTimex100 = 270/100 ps
5109 16:44:09.641263 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5110 16:44:09.644330 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5111 16:44:09.647466 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5112 16:44:09.654165 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5113 16:44:09.657221 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5114 16:44:09.660613 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5115 16:44:09.660715
5116 16:44:09.663693 CA PerBit enable=1, Macro0, CA PI delay=33
5117 16:44:09.663785
5118 16:44:09.667321 [CBTSetCACLKResult] CA Dly = 33
5119 16:44:09.667436 CS Dly: 7 (0~38)
5120 16:44:09.667545 ==
5121 16:44:09.671005 Dram Type= 6, Freq= 0, CH_0, rank 1
5122 16:44:09.677706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 16:44:09.677843 ==
5124 16:44:09.680380 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 16:44:09.687168 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 16:44:09.690851 [CA 0] Center 38 (8~69) winsize 62
5127 16:44:09.693696 [CA 1] Center 38 (8~69) winsize 62
5128 16:44:09.697116 [CA 2] Center 35 (5~66) winsize 62
5129 16:44:09.700568 [CA 3] Center 35 (5~66) winsize 62
5130 16:44:09.703870 [CA 4] Center 34 (4~65) winsize 62
5131 16:44:09.706976 [CA 5] Center 34 (4~64) winsize 61
5132 16:44:09.707092
5133 16:44:09.710644 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 16:44:09.710758
5135 16:44:09.713692 [CATrainingPosCal] consider 2 rank data
5136 16:44:09.716818 u2DelayCellTimex100 = 270/100 ps
5137 16:44:09.720387 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5138 16:44:09.726947 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5139 16:44:09.730559 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5140 16:44:09.733164 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5141 16:44:09.737001 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5142 16:44:09.740019 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5143 16:44:09.740108
5144 16:44:09.743261 CA PerBit enable=1, Macro0, CA PI delay=34
5145 16:44:09.743349
5146 16:44:09.746241 [CBTSetCACLKResult] CA Dly = 34
5147 16:44:09.750036 CS Dly: 7 (0~39)
5148 16:44:09.750124
5149 16:44:09.753035 ----->DramcWriteLeveling(PI) begin...
5150 16:44:09.753120 ==
5151 16:44:09.756097 Dram Type= 6, Freq= 0, CH_0, rank 0
5152 16:44:09.759724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5153 16:44:09.759813 ==
5154 16:44:09.762761 Write leveling (Byte 0): 29 => 29
5155 16:44:09.766318 Write leveling (Byte 1): 29 => 29
5156 16:44:09.769532 DramcWriteLeveling(PI) end<-----
5157 16:44:09.769618
5158 16:44:09.769690 ==
5159 16:44:09.773101 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 16:44:09.776481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 16:44:09.776568 ==
5162 16:44:09.779509 [Gating] SW mode calibration
5163 16:44:09.786296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5164 16:44:09.792402 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5165 16:44:09.796267 0 14 0 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
5166 16:44:09.802330 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5167 16:44:09.805874 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 16:44:09.809472 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 16:44:09.815909 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 16:44:09.819443 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 16:44:09.822613 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 16:44:09.825478 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5173 16:44:09.832144 0 15 0 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
5174 16:44:09.835657 0 15 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5175 16:44:09.842136 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 16:44:09.845145 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 16:44:09.848862 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 16:44:09.855111 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 16:44:09.858725 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 16:44:09.861479 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5181 16:44:09.868260 1 0 0 | B1->B0 | 2828 4040 | 0 1 | (1 1) (0 0)
5182 16:44:09.871509 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5183 16:44:09.874532 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 16:44:09.881685 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 16:44:09.884976 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 16:44:09.887953 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 16:44:09.894613 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 16:44:09.897954 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 16:44:09.901097 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5190 16:44:09.907738 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5191 16:44:09.911270 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 16:44:09.914182 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 16:44:09.921118 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 16:44:09.924032 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 16:44:09.927358 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 16:44:09.934150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 16:44:09.937311 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:44:09.940901 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:44:09.947455 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:44:09.950462 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:44:09.954146 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:44:09.960842 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:44:09.963777 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:44:09.966860 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 16:44:09.973483 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5206 16:44:09.973608 Total UI for P1: 0, mck2ui 16
5207 16:44:09.977340 best dqsien dly found for B0: ( 1, 2, 30)
5208 16:44:09.983450 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5209 16:44:09.986897 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 16:44:09.990311 Total UI for P1: 0, mck2ui 16
5211 16:44:09.993378 best dqsien dly found for B1: ( 1, 3, 2)
5212 16:44:09.996743 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5213 16:44:10.000243 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5214 16:44:10.000356
5215 16:44:10.003223 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5216 16:44:10.009956 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5217 16:44:10.010082 [Gating] SW calibration Done
5218 16:44:10.012969 ==
5219 16:44:10.013082 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 16:44:10.019641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 16:44:10.019759 ==
5222 16:44:10.019880 RX Vref Scan: 0
5223 16:44:10.019995
5224 16:44:10.023023 RX Vref 0 -> 0, step: 1
5225 16:44:10.023142
5226 16:44:10.026452 RX Delay -80 -> 252, step: 8
5227 16:44:10.030152 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5228 16:44:10.032973 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5229 16:44:10.036654 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5230 16:44:10.042854 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5231 16:44:10.046539 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5232 16:44:10.049547 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5233 16:44:10.052842 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5234 16:44:10.056001 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5235 16:44:10.059770 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5236 16:44:10.066211 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5237 16:44:10.069305 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5238 16:44:10.072606 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5239 16:44:10.076138 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5240 16:44:10.082842 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5241 16:44:10.085900 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5242 16:44:10.088982 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5243 16:44:10.089093 ==
5244 16:44:10.092008 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 16:44:10.095597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 16:44:10.095687 ==
5247 16:44:10.098949 DQS Delay:
5248 16:44:10.099031 DQS0 = 0, DQS1 = 0
5249 16:44:10.102313 DQM Delay:
5250 16:44:10.102394 DQM0 = 94, DQM1 = 82
5251 16:44:10.102462 DQ Delay:
5252 16:44:10.105596 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5253 16:44:10.108635 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =111
5254 16:44:10.112100 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5255 16:44:10.115716 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =91
5256 16:44:10.118616
5257 16:44:10.118704
5258 16:44:10.118773 ==
5259 16:44:10.122148 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 16:44:10.125248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 16:44:10.125332 ==
5262 16:44:10.125426
5263 16:44:10.125498
5264 16:44:10.128743 TX Vref Scan disable
5265 16:44:10.128830 == TX Byte 0 ==
5266 16:44:10.135101 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5267 16:44:10.138284 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5268 16:44:10.138369 == TX Byte 1 ==
5269 16:44:10.145338 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5270 16:44:10.148338 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5271 16:44:10.148419 ==
5272 16:44:10.151530 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 16:44:10.155362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 16:44:10.155491 ==
5275 16:44:10.155606
5276 16:44:10.155703
5277 16:44:10.158703 TX Vref Scan disable
5278 16:44:10.161542 == TX Byte 0 ==
5279 16:44:10.164542 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5280 16:44:10.168225 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5281 16:44:10.171454 == TX Byte 1 ==
5282 16:44:10.174549 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5283 16:44:10.178241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5284 16:44:10.178337
5285 16:44:10.181205 [DATLAT]
5286 16:44:10.181299 Freq=933, CH0 RK0
5287 16:44:10.181369
5288 16:44:10.184808 DATLAT Default: 0xd
5289 16:44:10.184936 0, 0xFFFF, sum = 0
5290 16:44:10.187954 1, 0xFFFF, sum = 0
5291 16:44:10.188066 2, 0xFFFF, sum = 0
5292 16:44:10.190938 3, 0xFFFF, sum = 0
5293 16:44:10.191059 4, 0xFFFF, sum = 0
5294 16:44:10.194603 5, 0xFFFF, sum = 0
5295 16:44:10.194723 6, 0xFFFF, sum = 0
5296 16:44:10.197679 7, 0xFFFF, sum = 0
5297 16:44:10.201330 8, 0xFFFF, sum = 0
5298 16:44:10.201442 9, 0xFFFF, sum = 0
5299 16:44:10.204488 10, 0x0, sum = 1
5300 16:44:10.204598 11, 0x0, sum = 2
5301 16:44:10.204714 12, 0x0, sum = 3
5302 16:44:10.207704 13, 0x0, sum = 4
5303 16:44:10.207832 best_step = 11
5304 16:44:10.207931
5305 16:44:10.211054 ==
5306 16:44:10.211160 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 16:44:10.217591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 16:44:10.217694 ==
5309 16:44:10.217776 RX Vref Scan: 1
5310 16:44:10.217895
5311 16:44:10.220557 RX Vref 0 -> 0, step: 1
5312 16:44:10.220652
5313 16:44:10.223926 RX Delay -69 -> 252, step: 4
5314 16:44:10.224041
5315 16:44:10.227691 Set Vref, RX VrefLevel [Byte0]: 60
5316 16:44:10.230620 [Byte1]: 55
5317 16:44:10.230728
5318 16:44:10.233633 Final RX Vref Byte 0 = 60 to rank0
5319 16:44:10.237071 Final RX Vref Byte 1 = 55 to rank0
5320 16:44:10.240237 Final RX Vref Byte 0 = 60 to rank1
5321 16:44:10.243787 Final RX Vref Byte 1 = 55 to rank1==
5322 16:44:10.246860 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 16:44:10.253381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 16:44:10.253471 ==
5325 16:44:10.253542 DQS Delay:
5326 16:44:10.253611 DQS0 = 0, DQS1 = 0
5327 16:44:10.257204 DQM Delay:
5328 16:44:10.257288 DQM0 = 95, DQM1 = 83
5329 16:44:10.260192 DQ Delay:
5330 16:44:10.263769 DQ0 =94, DQ1 =94, DQ2 =92, DQ3 =92
5331 16:44:10.266811 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5332 16:44:10.270350 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =78
5333 16:44:10.273326 DQ12 =88, DQ13 =86, DQ14 =94, DQ15 =90
5334 16:44:10.273442
5335 16:44:10.273546
5336 16:44:10.280128 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5337 16:44:10.283297 CH0 RK0: MR19=505, MR18=1414
5338 16:44:10.289837 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5339 16:44:10.289935
5340 16:44:10.292896 ----->DramcWriteLeveling(PI) begin...
5341 16:44:10.292983 ==
5342 16:44:10.296561 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 16:44:10.299689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 16:44:10.299771 ==
5345 16:44:10.302714 Write leveling (Byte 0): 31 => 31
5346 16:44:10.306223 Write leveling (Byte 1): 30 => 30
5347 16:44:10.309673 DramcWriteLeveling(PI) end<-----
5348 16:44:10.309768
5349 16:44:10.309836 ==
5350 16:44:10.312727 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 16:44:10.316066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 16:44:10.319452 ==
5353 16:44:10.319547 [Gating] SW mode calibration
5354 16:44:10.329161 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 16:44:10.333039 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 16:44:10.335948 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5357 16:44:10.342530 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 16:44:10.345606 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 16:44:10.349511 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 16:44:10.355526 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 16:44:10.359001 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 16:44:10.362150 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 16:44:10.368944 0 14 28 | B1->B0 | 3232 2e2e | 0 0 | (1 0) (1 1)
5364 16:44:10.372451 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
5365 16:44:10.375455 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 16:44:10.382189 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 16:44:10.385354 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 16:44:10.388750 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 16:44:10.395020 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 16:44:10.398757 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 16:44:10.401945 0 15 28 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
5372 16:44:10.408767 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5373 16:44:10.411786 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 16:44:10.415057 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 16:44:10.422009 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 16:44:10.424652 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 16:44:10.428020 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:44:10.435019 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5379 16:44:10.438147 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5380 16:44:10.441677 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5381 16:44:10.448251 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 16:44:10.451319 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 16:44:10.454517 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 16:44:10.461100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 16:44:10.464619 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:44:10.467972 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:44:10.474485 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:44:10.478097 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:44:10.481402 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:44:10.487464 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:44:10.491125 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:44:10.494091 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:44:10.500971 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:44:10.504156 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:44:10.507170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 16:44:10.513946 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5397 16:44:10.517475 Total UI for P1: 0, mck2ui 16
5398 16:44:10.520400 best dqsien dly found for B0: ( 1, 2, 30)
5399 16:44:10.523881 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5400 16:44:10.526862 Total UI for P1: 0, mck2ui 16
5401 16:44:10.530113 best dqsien dly found for B1: ( 1, 3, 0)
5402 16:44:10.533508 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5403 16:44:10.536927 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5404 16:44:10.537015
5405 16:44:10.540132 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5406 16:44:10.543823 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5407 16:44:10.546954 [Gating] SW calibration Done
5408 16:44:10.547067 ==
5409 16:44:10.550516 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 16:44:10.556833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 16:44:10.556950 ==
5412 16:44:10.557049 RX Vref Scan: 0
5413 16:44:10.557143
5414 16:44:10.559921 RX Vref 0 -> 0, step: 1
5415 16:44:10.560013
5416 16:44:10.563665 RX Delay -80 -> 252, step: 8
5417 16:44:10.566495 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5418 16:44:10.569984 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5419 16:44:10.573544 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5420 16:44:10.576379 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5421 16:44:10.583189 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5422 16:44:10.586463 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5423 16:44:10.589517 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5424 16:44:10.593286 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5425 16:44:10.596223 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5426 16:44:10.602847 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5427 16:44:10.605953 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5428 16:44:10.609171 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5429 16:44:10.612814 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5430 16:44:10.615937 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5431 16:44:10.622594 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5432 16:44:10.626153 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5433 16:44:10.626263 ==
5434 16:44:10.628995 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 16:44:10.632509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 16:44:10.632654 ==
5437 16:44:10.635808 DQS Delay:
5438 16:44:10.635924 DQS0 = 0, DQS1 = 0
5439 16:44:10.636020 DQM Delay:
5440 16:44:10.639297 DQM0 = 92, DQM1 = 82
5441 16:44:10.639422 DQ Delay:
5442 16:44:10.642181 DQ0 =91, DQ1 =91, DQ2 =91, DQ3 =87
5443 16:44:10.645670 DQ4 =91, DQ5 =75, DQ6 =107, DQ7 =103
5444 16:44:10.648908 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5445 16:44:10.652659 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5446 16:44:10.652748
5447 16:44:10.652815
5448 16:44:10.655437 ==
5449 16:44:10.655551 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 16:44:10.662323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 16:44:10.662445 ==
5452 16:44:10.662554
5453 16:44:10.662664
5454 16:44:10.665327 TX Vref Scan disable
5455 16:44:10.665453 == TX Byte 0 ==
5456 16:44:10.668530 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5457 16:44:10.675118 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5458 16:44:10.675236 == TX Byte 1 ==
5459 16:44:10.681894 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5460 16:44:10.685279 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5461 16:44:10.685387 ==
5462 16:44:10.688324 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 16:44:10.691849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 16:44:10.691978 ==
5465 16:44:10.692078
5466 16:44:10.692176
5467 16:44:10.694930 TX Vref Scan disable
5468 16:44:10.697940 == TX Byte 0 ==
5469 16:44:10.701357 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5470 16:44:10.704893 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5471 16:44:10.708118 == TX Byte 1 ==
5472 16:44:10.711235 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5473 16:44:10.714990 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5474 16:44:10.715105
5475 16:44:10.717997 [DATLAT]
5476 16:44:10.718124 Freq=933, CH0 RK1
5477 16:44:10.718227
5478 16:44:10.721128 DATLAT Default: 0xb
5479 16:44:10.721240 0, 0xFFFF, sum = 0
5480 16:44:10.725094 1, 0xFFFF, sum = 0
5481 16:44:10.725206 2, 0xFFFF, sum = 0
5482 16:44:10.727958 3, 0xFFFF, sum = 0
5483 16:44:10.728067 4, 0xFFFF, sum = 0
5484 16:44:10.731364 5, 0xFFFF, sum = 0
5485 16:44:10.731490 6, 0xFFFF, sum = 0
5486 16:44:10.734356 7, 0xFFFF, sum = 0
5487 16:44:10.734483 8, 0xFFFF, sum = 0
5488 16:44:10.737612 9, 0xFFFF, sum = 0
5489 16:44:10.737738 10, 0x0, sum = 1
5490 16:44:10.741207 11, 0x0, sum = 2
5491 16:44:10.741304 12, 0x0, sum = 3
5492 16:44:10.744599 13, 0x0, sum = 4
5493 16:44:10.744730 best_step = 11
5494 16:44:10.744834
5495 16:44:10.744940 ==
5496 16:44:10.747807 Dram Type= 6, Freq= 0, CH_0, rank 1
5497 16:44:10.754052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 16:44:10.754185 ==
5499 16:44:10.754280 RX Vref Scan: 0
5500 16:44:10.754352
5501 16:44:10.757753 RX Vref 0 -> 0, step: 1
5502 16:44:10.757836
5503 16:44:10.760730 RX Delay -69 -> 252, step: 4
5504 16:44:10.764307 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5505 16:44:10.770486 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5506 16:44:10.774146 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5507 16:44:10.777822 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5508 16:44:10.780619 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5509 16:44:10.784359 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5510 16:44:10.787270 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5511 16:44:10.793789 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5512 16:44:10.797536 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5513 16:44:10.800451 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5514 16:44:10.804040 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5515 16:44:10.807029 iDelay=199, Bit 11, Center 80 (-9 ~ 170) 180
5516 16:44:10.813666 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5517 16:44:10.816924 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5518 16:44:10.820475 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5519 16:44:10.823527 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5520 16:44:10.823630 ==
5521 16:44:10.826562 Dram Type= 6, Freq= 0, CH_0, rank 1
5522 16:44:10.833501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5523 16:44:10.833589 ==
5524 16:44:10.833658 DQS Delay:
5525 16:44:10.836347 DQS0 = 0, DQS1 = 0
5526 16:44:10.836430 DQM Delay:
5527 16:44:10.836498 DQM0 = 92, DQM1 = 84
5528 16:44:10.840020 DQ Delay:
5529 16:44:10.843492 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5530 16:44:10.846784 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5531 16:44:10.850064 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =80
5532 16:44:10.852944 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =92
5533 16:44:10.853049
5534 16:44:10.853150
5535 16:44:10.859842 [DQSOSCAuto] RK1, (LSB)MR18= 0x3113, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5536 16:44:10.863192 CH0 RK1: MR19=505, MR18=3113
5537 16:44:10.869653 CH0_RK1: MR19=0x505, MR18=0x3113, DQSOSC=406, MR23=63, INC=65, DEC=43
5538 16:44:10.872844 [RxdqsGatingPostProcess] freq 933
5539 16:44:10.879192 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5540 16:44:10.879315 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 16:44:10.882620 best DQS1 dly(2T, 0.5T) = (0, 11)
5542 16:44:10.885893 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 16:44:10.889173 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5544 16:44:10.892945 best DQS0 dly(2T, 0.5T) = (0, 10)
5545 16:44:10.895954 best DQS1 dly(2T, 0.5T) = (0, 11)
5546 16:44:10.899437 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5547 16:44:10.902206 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5548 16:44:10.905661 Pre-setting of DQS Precalculation
5549 16:44:10.912674 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5550 16:44:10.912770 ==
5551 16:44:10.915761 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 16:44:10.918750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 16:44:10.918839 ==
5554 16:44:10.925572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5555 16:44:10.928676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5556 16:44:10.933089 [CA 0] Center 37 (7~67) winsize 61
5557 16:44:10.936004 [CA 1] Center 37 (7~67) winsize 61
5558 16:44:10.939640 [CA 2] Center 34 (5~64) winsize 60
5559 16:44:10.943059 [CA 3] Center 34 (4~64) winsize 61
5560 16:44:10.945896 [CA 4] Center 34 (5~64) winsize 60
5561 16:44:10.949740 [CA 5] Center 33 (4~63) winsize 60
5562 16:44:10.949831
5563 16:44:10.952620 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5564 16:44:10.952703
5565 16:44:10.956039 [CATrainingPosCal] consider 1 rank data
5566 16:44:10.959317 u2DelayCellTimex100 = 270/100 ps
5567 16:44:10.962364 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5568 16:44:10.969110 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5569 16:44:10.972540 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5570 16:44:10.975495 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 16:44:10.979078 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5572 16:44:10.982208 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5573 16:44:10.982298
5574 16:44:10.985886 CA PerBit enable=1, Macro0, CA PI delay=33
5575 16:44:10.985975
5576 16:44:10.989522 [CBTSetCACLKResult] CA Dly = 33
5577 16:44:10.992444 CS Dly: 6 (0~37)
5578 16:44:10.992573 ==
5579 16:44:10.995602 Dram Type= 6, Freq= 0, CH_1, rank 1
5580 16:44:10.998693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 16:44:10.998812 ==
5582 16:44:11.005776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 16:44:11.008872 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5584 16:44:11.013145 [CA 0] Center 37 (7~67) winsize 61
5585 16:44:11.016485 [CA 1] Center 37 (7~68) winsize 62
5586 16:44:11.019418 [CA 2] Center 35 (5~65) winsize 61
5587 16:44:11.022995 [CA 3] Center 34 (4~64) winsize 61
5588 16:44:11.026056 [CA 4] Center 34 (4~64) winsize 61
5589 16:44:11.029118 [CA 5] Center 33 (3~64) winsize 62
5590 16:44:11.029227
5591 16:44:11.032809 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5592 16:44:11.032920
5593 16:44:11.035873 [CATrainingPosCal] consider 2 rank data
5594 16:44:11.039551 u2DelayCellTimex100 = 270/100 ps
5595 16:44:11.042577 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 16:44:11.049148 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5597 16:44:11.052624 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5598 16:44:11.056071 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5599 16:44:11.058941 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5600 16:44:11.062396 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5601 16:44:11.062488
5602 16:44:11.065728 CA PerBit enable=1, Macro0, CA PI delay=33
5603 16:44:11.065814
5604 16:44:11.068655 [CBTSetCACLKResult] CA Dly = 33
5605 16:44:11.072178 CS Dly: 7 (0~39)
5606 16:44:11.072292
5607 16:44:11.075503 ----->DramcWriteLeveling(PI) begin...
5608 16:44:11.075604 ==
5609 16:44:11.078868 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 16:44:11.081869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 16:44:11.081957 ==
5612 16:44:11.085602 Write leveling (Byte 0): 24 => 24
5613 16:44:11.088690 Write leveling (Byte 1): 29 => 29
5614 16:44:11.091653 DramcWriteLeveling(PI) end<-----
5615 16:44:11.091742
5616 16:44:11.091811 ==
5617 16:44:11.095373 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 16:44:11.098386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 16:44:11.098526 ==
5620 16:44:11.101521 [Gating] SW mode calibration
5621 16:44:11.108180 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5622 16:44:11.115244 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5623 16:44:11.118286 0 14 0 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5624 16:44:11.124298 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 16:44:11.128055 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 16:44:11.131181 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 16:44:11.138088 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 16:44:11.141226 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 16:44:11.144319 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 16:44:11.151152 0 14 28 | B1->B0 | 2e2e 2e2e | 1 1 | (1 1) (1 1)
5631 16:44:11.154176 0 15 0 | B1->B0 | 2424 2424 | 0 0 | (1 0) (1 0)
5632 16:44:11.157809 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 16:44:11.164591 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 16:44:11.167981 0 15 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5635 16:44:11.170872 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 16:44:11.177494 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 16:44:11.180438 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 16:44:11.183900 0 15 28 | B1->B0 | 3939 3333 | 0 0 | (1 1) (0 0)
5639 16:44:11.190902 1 0 0 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5640 16:44:11.193918 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 16:44:11.197666 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 16:44:11.203685 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 16:44:11.206858 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:44:11.210675 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 16:44:11.217013 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 16:44:11.220011 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5647 16:44:11.223560 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 16:44:11.229983 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 16:44:11.233628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 16:44:11.236766 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 16:44:11.243494 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:44:11.246562 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:44:11.249551 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:44:11.256206 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:44:11.260021 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:44:11.263142 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:44:11.269605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:44:11.273001 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:44:11.275848 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:44:11.282741 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 16:44:11.286085 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 16:44:11.289469 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 16:44:11.296097 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 16:44:11.296194 Total UI for P1: 0, mck2ui 16
5665 16:44:11.302644 best dqsien dly found for B0: ( 1, 2, 30)
5666 16:44:11.302734 Total UI for P1: 0, mck2ui 16
5667 16:44:11.309133 best dqsien dly found for B1: ( 1, 2, 30)
5668 16:44:11.312183 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5669 16:44:11.315834 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5670 16:44:11.315914
5671 16:44:11.318917 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5672 16:44:11.322161 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5673 16:44:11.325624 [Gating] SW calibration Done
5674 16:44:11.325710 ==
5675 16:44:11.328760 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 16:44:11.332610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 16:44:11.332692 ==
5678 16:44:11.335184 RX Vref Scan: 0
5679 16:44:11.335268
5680 16:44:11.335356 RX Vref 0 -> 0, step: 1
5681 16:44:11.335460
5682 16:44:11.338348 RX Delay -80 -> 252, step: 8
5683 16:44:11.341900 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5684 16:44:11.348806 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5685 16:44:11.351838 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5686 16:44:11.354907 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5687 16:44:11.358670 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5688 16:44:11.361808 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5689 16:44:11.367984 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5690 16:44:11.371612 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5691 16:44:11.374618 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5692 16:44:11.377740 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5693 16:44:11.381237 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5694 16:44:11.388139 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5695 16:44:11.390792 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5696 16:44:11.394140 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5697 16:44:11.397730 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5698 16:44:11.400868 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5699 16:44:11.400949 ==
5700 16:44:11.404006 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 16:44:11.410991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 16:44:11.411077 ==
5703 16:44:11.411146 DQS Delay:
5704 16:44:11.413992 DQS0 = 0, DQS1 = 0
5705 16:44:11.414066 DQM Delay:
5706 16:44:11.414130 DQM0 = 95, DQM1 = 89
5707 16:44:11.417587 DQ Delay:
5708 16:44:11.420650 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5709 16:44:11.423834 DQ4 =91, DQ5 =107, DQ6 =103, DQ7 =91
5710 16:44:11.427366 DQ8 =79, DQ9 =83, DQ10 =87, DQ11 =83
5711 16:44:11.430428 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5712 16:44:11.430540
5713 16:44:11.430660
5714 16:44:11.430768 ==
5715 16:44:11.434031 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 16:44:11.437129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 16:44:11.437241 ==
5718 16:44:11.437358
5719 16:44:11.437464
5720 16:44:11.440630 TX Vref Scan disable
5721 16:44:11.444203 == TX Byte 0 ==
5722 16:44:11.447296 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5723 16:44:11.450455 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5724 16:44:11.453521 == TX Byte 1 ==
5725 16:44:11.457292 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5726 16:44:11.460297 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5727 16:44:11.460397 ==
5728 16:44:11.463444 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 16:44:11.470128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 16:44:11.470222 ==
5731 16:44:11.470292
5732 16:44:11.470361
5733 16:44:11.470431 TX Vref Scan disable
5734 16:44:11.473841 == TX Byte 0 ==
5735 16:44:11.477663 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5736 16:44:11.484327 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5737 16:44:11.484446 == TX Byte 1 ==
5738 16:44:11.487550 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5739 16:44:11.494195 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5740 16:44:11.494311
5741 16:44:11.494398 [DATLAT]
5742 16:44:11.494492 Freq=933, CH1 RK0
5743 16:44:11.494584
5744 16:44:11.497269 DATLAT Default: 0xd
5745 16:44:11.497356 0, 0xFFFF, sum = 0
5746 16:44:11.500709 1, 0xFFFF, sum = 0
5747 16:44:11.503837 2, 0xFFFF, sum = 0
5748 16:44:11.503926 3, 0xFFFF, sum = 0
5749 16:44:11.507294 4, 0xFFFF, sum = 0
5750 16:44:11.507392 5, 0xFFFF, sum = 0
5751 16:44:11.510778 6, 0xFFFF, sum = 0
5752 16:44:11.510868 7, 0xFFFF, sum = 0
5753 16:44:11.513895 8, 0xFFFF, sum = 0
5754 16:44:11.513989 9, 0xFFFF, sum = 0
5755 16:44:11.516704 10, 0x0, sum = 1
5756 16:44:11.516795 11, 0x0, sum = 2
5757 16:44:11.520174 12, 0x0, sum = 3
5758 16:44:11.520292 13, 0x0, sum = 4
5759 16:44:11.520392 best_step = 11
5760 16:44:11.523767
5761 16:44:11.523857 ==
5762 16:44:11.526735 Dram Type= 6, Freq= 0, CH_1, rank 0
5763 16:44:11.529938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5764 16:44:11.530056 ==
5765 16:44:11.530170 RX Vref Scan: 1
5766 16:44:11.530279
5767 16:44:11.533632 RX Vref 0 -> 0, step: 1
5768 16:44:11.533755
5769 16:44:11.536466 RX Delay -61 -> 252, step: 4
5770 16:44:11.536548
5771 16:44:11.539812 Set Vref, RX VrefLevel [Byte0]: 58
5772 16:44:11.542991 [Byte1]: 50
5773 16:44:11.546529
5774 16:44:11.546625 Final RX Vref Byte 0 = 58 to rank0
5775 16:44:11.550288 Final RX Vref Byte 1 = 50 to rank0
5776 16:44:11.552964 Final RX Vref Byte 0 = 58 to rank1
5777 16:44:11.556468 Final RX Vref Byte 1 = 50 to rank1==
5778 16:44:11.559615 Dram Type= 6, Freq= 0, CH_1, rank 0
5779 16:44:11.566153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5780 16:44:11.566257 ==
5781 16:44:11.566371 DQS Delay:
5782 16:44:11.569234 DQS0 = 0, DQS1 = 0
5783 16:44:11.569343 DQM Delay:
5784 16:44:11.569454 DQM0 = 95, DQM1 = 87
5785 16:44:11.572827 DQ Delay:
5786 16:44:11.575885 DQ0 =100, DQ1 =90, DQ2 =86, DQ3 =92
5787 16:44:11.579558 DQ4 =92, DQ5 =106, DQ6 =104, DQ7 =92
5788 16:44:11.582666 DQ8 =78, DQ9 =80, DQ10 =88, DQ11 =82
5789 16:44:11.586508 DQ12 =94, DQ13 =92, DQ14 =92, DQ15 =94
5790 16:44:11.586587
5791 16:44:11.586665
5792 16:44:11.592869 [DQSOSCAuto] RK0, (LSB)MR18= 0x8, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5793 16:44:11.595773 CH1 RK0: MR19=505, MR18=8
5794 16:44:11.602710 CH1_RK0: MR19=0x505, MR18=0x8, DQSOSC=419, MR23=63, INC=61, DEC=41
5795 16:44:11.602806
5796 16:44:11.606061 ----->DramcWriteLeveling(PI) begin...
5797 16:44:11.606184 ==
5798 16:44:11.609217 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 16:44:11.612478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 16:44:11.612595 ==
5801 16:44:11.615768 Write leveling (Byte 0): 28 => 28
5802 16:44:11.618708 Write leveling (Byte 1): 27 => 27
5803 16:44:11.622041 DramcWriteLeveling(PI) end<-----
5804 16:44:11.622129
5805 16:44:11.622201 ==
5806 16:44:11.625524 Dram Type= 6, Freq= 0, CH_1, rank 1
5807 16:44:11.628732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5808 16:44:11.628826 ==
5809 16:44:11.632422 [Gating] SW mode calibration
5810 16:44:11.638606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5811 16:44:11.645260 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5812 16:44:11.648280 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5813 16:44:11.655197 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 16:44:11.658563 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 16:44:11.661945 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 16:44:11.668642 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 16:44:11.671777 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 16:44:11.674824 0 14 24 | B1->B0 | 3030 3030 | 1 0 | (1 1) (0 1)
5819 16:44:11.681468 0 14 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5820 16:44:11.684515 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 16:44:11.688260 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 16:44:11.694487 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 16:44:11.698139 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 16:44:11.701222 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 16:44:11.707822 0 15 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
5826 16:44:11.711114 0 15 24 | B1->B0 | 2c2c 3534 | 0 1 | (0 0) (0 0)
5827 16:44:11.714357 0 15 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5828 16:44:11.721049 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 16:44:11.724449 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 16:44:11.727373 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 16:44:11.734148 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 16:44:11.737711 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 16:44:11.740760 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 16:44:11.747415 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5835 16:44:11.751042 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5836 16:44:11.753911 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 16:44:11.760598 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 16:44:11.763718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 16:44:11.767076 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 16:44:11.773654 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:44:11.777296 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:44:11.780407 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:44:11.787264 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:44:11.790518 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:44:11.793562 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:44:11.800296 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:44:11.803491 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:44:11.806857 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 16:44:11.813584 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 16:44:11.817064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5851 16:44:11.820473 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5852 16:44:11.823670 Total UI for P1: 0, mck2ui 16
5853 16:44:11.826965 best dqsien dly found for B0: ( 1, 2, 24)
5854 16:44:11.833112 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 16:44:11.833207 Total UI for P1: 0, mck2ui 16
5856 16:44:11.836319 best dqsien dly found for B1: ( 1, 2, 28)
5857 16:44:11.843359 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5858 16:44:11.846362 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5859 16:44:11.846447
5860 16:44:11.850114 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5861 16:44:11.853164 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5862 16:44:11.856758 [Gating] SW calibration Done
5863 16:44:11.856846 ==
5864 16:44:11.859593 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 16:44:11.863127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 16:44:11.863212 ==
5867 16:44:11.866274 RX Vref Scan: 0
5868 16:44:11.866364
5869 16:44:11.866473 RX Vref 0 -> 0, step: 1
5870 16:44:11.866583
5871 16:44:11.869783 RX Delay -80 -> 252, step: 8
5872 16:44:11.872808 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5873 16:44:11.879930 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5874 16:44:11.883085 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5875 16:44:11.886071 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5876 16:44:11.889712 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5877 16:44:11.892732 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5878 16:44:11.895890 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5879 16:44:11.902589 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5880 16:44:11.905513 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5881 16:44:11.909099 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5882 16:44:11.912199 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5883 16:44:11.915990 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5884 16:44:11.922062 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5885 16:44:11.925634 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5886 16:44:11.929199 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5887 16:44:11.932030 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5888 16:44:11.932124 ==
5889 16:44:11.935486 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 16:44:11.942120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 16:44:11.942219 ==
5892 16:44:11.942315 DQS Delay:
5893 16:44:11.945346 DQS0 = 0, DQS1 = 0
5894 16:44:11.945443 DQM Delay:
5895 16:44:11.945531 DQM0 = 94, DQM1 = 88
5896 16:44:11.948720 DQ Delay:
5897 16:44:11.951705 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5898 16:44:11.955386 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5899 16:44:11.958287 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =87
5900 16:44:11.961604 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5901 16:44:11.961685
5902 16:44:11.961788
5903 16:44:11.961881 ==
5904 16:44:11.965186 Dram Type= 6, Freq= 0, CH_1, rank 1
5905 16:44:11.968616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5906 16:44:11.968728 ==
5907 16:44:11.968799
5908 16:44:11.968864
5909 16:44:11.971556 TX Vref Scan disable
5910 16:44:11.974703 == TX Byte 0 ==
5911 16:44:11.978618 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5912 16:44:11.981730 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5913 16:44:11.984828 == TX Byte 1 ==
5914 16:44:11.987805 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5915 16:44:11.991411 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5916 16:44:11.991525 ==
5917 16:44:11.994483 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 16:44:12.001273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 16:44:12.001408 ==
5920 16:44:12.001479
5921 16:44:12.001543
5922 16:44:12.001605 TX Vref Scan disable
5923 16:44:12.004945 == TX Byte 0 ==
5924 16:44:12.008564 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5925 16:44:12.014683 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5926 16:44:12.014780 == TX Byte 1 ==
5927 16:44:12.018221 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5928 16:44:12.024871 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5929 16:44:12.024981
5930 16:44:12.025081 [DATLAT]
5931 16:44:12.025178 Freq=933, CH1 RK1
5932 16:44:12.025270
5933 16:44:12.027733 DATLAT Default: 0xb
5934 16:44:12.031434 0, 0xFFFF, sum = 0
5935 16:44:12.031545 1, 0xFFFF, sum = 0
5936 16:44:12.034697 2, 0xFFFF, sum = 0
5937 16:44:12.034807 3, 0xFFFF, sum = 0
5938 16:44:12.037917 4, 0xFFFF, sum = 0
5939 16:44:12.038023 5, 0xFFFF, sum = 0
5940 16:44:12.040908 6, 0xFFFF, sum = 0
5941 16:44:12.041013 7, 0xFFFF, sum = 0
5942 16:44:12.044278 8, 0xFFFF, sum = 0
5943 16:44:12.044386 9, 0xFFFF, sum = 0
5944 16:44:12.047612 10, 0x0, sum = 1
5945 16:44:12.047720 11, 0x0, sum = 2
5946 16:44:12.051162 12, 0x0, sum = 3
5947 16:44:12.051274 13, 0x0, sum = 4
5948 16:44:12.051372 best_step = 11
5949 16:44:12.054551
5950 16:44:12.054657 ==
5951 16:44:12.057965 Dram Type= 6, Freq= 0, CH_1, rank 1
5952 16:44:12.060860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5953 16:44:12.060976 ==
5954 16:44:12.061074 RX Vref Scan: 0
5955 16:44:12.061169
5956 16:44:12.064350 RX Vref 0 -> 0, step: 1
5957 16:44:12.064449
5958 16:44:12.067721 RX Delay -69 -> 252, step: 4
5959 16:44:12.074052 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5960 16:44:12.077030 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5961 16:44:12.080795 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5962 16:44:12.083929 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5963 16:44:12.087585 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5964 16:44:12.094183 iDelay=203, Bit 5, Center 104 (7 ~ 202) 196
5965 16:44:12.097266 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5966 16:44:12.100261 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5967 16:44:12.103969 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5968 16:44:12.107132 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5969 16:44:12.113330 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5970 16:44:12.117271 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5971 16:44:12.119940 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5972 16:44:12.123535 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5973 16:44:12.126692 iDelay=203, Bit 14, Center 94 (3 ~ 186) 184
5974 16:44:12.129838 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5975 16:44:12.133371 ==
5976 16:44:12.136603 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 16:44:12.139737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 16:44:12.139846 ==
5979 16:44:12.139941 DQS Delay:
5980 16:44:12.143396 DQS0 = 0, DQS1 = 0
5981 16:44:12.143512 DQM Delay:
5982 16:44:12.146336 DQM0 = 92, DQM1 = 89
5983 16:44:12.146442 DQ Delay:
5984 16:44:12.149738 DQ0 =96, DQ1 =88, DQ2 =82, DQ3 =90
5985 16:44:12.153021 DQ4 =88, DQ5 =104, DQ6 =104, DQ7 =90
5986 16:44:12.156604 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =82
5987 16:44:12.159635 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5988 16:44:12.159743
5989 16:44:12.159842
5990 16:44:12.165882 [DQSOSCAuto] RK1, (LSB)MR18= 0xd22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5991 16:44:12.169374 CH1 RK1: MR19=505, MR18=D22
5992 16:44:12.175950 CH1_RK1: MR19=0x505, MR18=0xD22, DQSOSC=411, MR23=63, INC=64, DEC=42
5993 16:44:12.179795 [RxdqsGatingPostProcess] freq 933
5994 16:44:12.185713 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5995 16:44:12.189425 best DQS0 dly(2T, 0.5T) = (0, 10)
5996 16:44:12.189548 best DQS1 dly(2T, 0.5T) = (0, 10)
5997 16:44:12.192547 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5998 16:44:12.195921 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5999 16:44:12.198822 best DQS0 dly(2T, 0.5T) = (0, 10)
6000 16:44:12.202405 best DQS1 dly(2T, 0.5T) = (0, 10)
6001 16:44:12.205422 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6002 16:44:12.209008 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6003 16:44:12.212302 Pre-setting of DQS Precalculation
6004 16:44:12.218886 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6005 16:44:12.225327 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6006 16:44:12.232076 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6007 16:44:12.232194
6008 16:44:12.232297
6009 16:44:12.235814 [Calibration Summary] 1866 Mbps
6010 16:44:12.235921 CH 0, Rank 0
6011 16:44:12.238967 SW Impedance : PASS
6012 16:44:12.241908 DUTY Scan : NO K
6013 16:44:12.242014 ZQ Calibration : PASS
6014 16:44:12.245175 Jitter Meter : NO K
6015 16:44:12.248860 CBT Training : PASS
6016 16:44:12.248972 Write leveling : PASS
6017 16:44:12.251831 RX DQS gating : PASS
6018 16:44:12.255258 RX DQ/DQS(RDDQC) : PASS
6019 16:44:12.255370 TX DQ/DQS : PASS
6020 16:44:12.258083 RX DATLAT : PASS
6021 16:44:12.261496 RX DQ/DQS(Engine): PASS
6022 16:44:12.261610 TX OE : NO K
6023 16:44:12.264804 All Pass.
6024 16:44:12.264915
6025 16:44:12.265022 CH 0, Rank 1
6026 16:44:12.268038 SW Impedance : PASS
6027 16:44:12.268154 DUTY Scan : NO K
6028 16:44:12.271482 ZQ Calibration : PASS
6029 16:44:12.274937 Jitter Meter : NO K
6030 16:44:12.275048 CBT Training : PASS
6031 16:44:12.277789 Write leveling : PASS
6032 16:44:12.281129 RX DQS gating : PASS
6033 16:44:12.281241 RX DQ/DQS(RDDQC) : PASS
6034 16:44:12.284773 TX DQ/DQS : PASS
6035 16:44:12.287746 RX DATLAT : PASS
6036 16:44:12.287836 RX DQ/DQS(Engine): PASS
6037 16:44:12.291145 TX OE : NO K
6038 16:44:12.291251 All Pass.
6039 16:44:12.291345
6040 16:44:12.294518 CH 1, Rank 0
6041 16:44:12.294628 SW Impedance : PASS
6042 16:44:12.297640 DUTY Scan : NO K
6043 16:44:12.301090 ZQ Calibration : PASS
6044 16:44:12.301203 Jitter Meter : NO K
6045 16:44:12.304665 CBT Training : PASS
6046 16:44:12.307416 Write leveling : PASS
6047 16:44:12.307501 RX DQS gating : PASS
6048 16:44:12.311091 RX DQ/DQS(RDDQC) : PASS
6049 16:44:12.311177 TX DQ/DQS : PASS
6050 16:44:12.314244 RX DATLAT : PASS
6051 16:44:12.317358 RX DQ/DQS(Engine): PASS
6052 16:44:12.317443 TX OE : NO K
6053 16:44:12.321022 All Pass.
6054 16:44:12.321107
6055 16:44:12.321175 CH 1, Rank 1
6056 16:44:12.324225 SW Impedance : PASS
6057 16:44:12.324336 DUTY Scan : NO K
6058 16:44:12.327689 ZQ Calibration : PASS
6059 16:44:12.330532 Jitter Meter : NO K
6060 16:44:12.330616 CBT Training : PASS
6061 16:44:12.334194 Write leveling : PASS
6062 16:44:12.337201 RX DQS gating : PASS
6063 16:44:12.337286 RX DQ/DQS(RDDQC) : PASS
6064 16:44:12.340960 TX DQ/DQS : PASS
6065 16:44:12.344112 RX DATLAT : PASS
6066 16:44:12.344197 RX DQ/DQS(Engine): PASS
6067 16:44:12.347045 TX OE : NO K
6068 16:44:12.347134 All Pass.
6069 16:44:12.347201
6070 16:44:12.350634 DramC Write-DBI off
6071 16:44:12.353774 PER_BANK_REFRESH: Hybrid Mode
6072 16:44:12.353855 TX_TRACKING: ON
6073 16:44:12.363551 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6074 16:44:12.366772 [FAST_K] Save calibration result to emmc
6075 16:44:12.370111 dramc_set_vcore_voltage set vcore to 650000
6076 16:44:12.373489 Read voltage for 400, 6
6077 16:44:12.373571 Vio18 = 0
6078 16:44:12.373639 Vcore = 650000
6079 16:44:12.376964 Vdram = 0
6080 16:44:12.377049 Vddq = 0
6081 16:44:12.377116 Vmddr = 0
6082 16:44:12.383514 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6083 16:44:12.386838 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6084 16:44:12.390236 MEM_TYPE=3, freq_sel=20
6085 16:44:12.393318 sv_algorithm_assistance_LP4_800
6086 16:44:12.396898 ============ PULL DRAM RESETB DOWN ============
6087 16:44:12.403556 ========== PULL DRAM RESETB DOWN end =========
6088 16:44:12.406784 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6089 16:44:12.409973 ===================================
6090 16:44:12.413218 LPDDR4 DRAM CONFIGURATION
6091 16:44:12.416326 ===================================
6092 16:44:12.416412 EX_ROW_EN[0] = 0x0
6093 16:44:12.419883 EX_ROW_EN[1] = 0x0
6094 16:44:12.419969 LP4Y_EN = 0x0
6095 16:44:12.423149 WORK_FSP = 0x0
6096 16:44:12.423227 WL = 0x2
6097 16:44:12.426384 RL = 0x2
6098 16:44:12.426475 BL = 0x2
6099 16:44:12.429966 RPST = 0x0
6100 16:44:12.430052 RD_PRE = 0x0
6101 16:44:12.432975 WR_PRE = 0x1
6102 16:44:12.433062 WR_PST = 0x0
6103 16:44:12.436396 DBI_WR = 0x0
6104 16:44:12.439384 DBI_RD = 0x0
6105 16:44:12.439509 OTF = 0x1
6106 16:44:12.442746 ===================================
6107 16:44:12.446252 ===================================
6108 16:44:12.446346 ANA top config
6109 16:44:12.449601 ===================================
6110 16:44:12.453029 DLL_ASYNC_EN = 0
6111 16:44:12.456235 ALL_SLAVE_EN = 1
6112 16:44:12.459276 NEW_RANK_MODE = 1
6113 16:44:12.462865 DLL_IDLE_MODE = 1
6114 16:44:12.462954 LP45_APHY_COMB_EN = 1
6115 16:44:12.465839 TX_ODT_DIS = 1
6116 16:44:12.468947 NEW_8X_MODE = 1
6117 16:44:12.472601 ===================================
6118 16:44:12.475797 ===================================
6119 16:44:12.479034 data_rate = 800
6120 16:44:12.482442 CKR = 1
6121 16:44:12.485731 DQ_P2S_RATIO = 4
6122 16:44:12.489032 ===================================
6123 16:44:12.489130 CA_P2S_RATIO = 4
6124 16:44:12.491924 DQ_CA_OPEN = 0
6125 16:44:12.495220 DQ_SEMI_OPEN = 1
6126 16:44:12.498750 CA_SEMI_OPEN = 1
6127 16:44:12.502200 CA_FULL_RATE = 0
6128 16:44:12.505126 DQ_CKDIV4_EN = 0
6129 16:44:12.505244 CA_CKDIV4_EN = 1
6130 16:44:12.508671 CA_PREDIV_EN = 0
6131 16:44:12.511928 PH8_DLY = 0
6132 16:44:12.515587 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6133 16:44:12.781420 DQ_AAMCK_DIV = 0
6134 16:44:12.781857 CA_AAMCK_DIV = 0
6135 16:44:12.782003 CA_ADMCK_DIV = 4
6136 16:44:12.782126 DQ_TRACK_CA_EN = 0
6137 16:44:12.782246 CA_PICK = 800
6138 16:44:12.782365 CA_MCKIO = 400
6139 16:44:12.782495 MCKIO_SEMI = 400
6140 16:44:12.782614 PLL_FREQ = 3016
6141 16:44:12.782733 DQ_UI_PI_RATIO = 32
6142 16:44:12.782852 CA_UI_PI_RATIO = 32
6143 16:44:12.782972 ===================================
6144 16:44:12.783091 ===================================
6145 16:44:12.783209 memory_type:LPDDR4
6146 16:44:12.783363 GP_NUM : 10
6147 16:44:12.783459 SRAM_EN : 1
6148 16:44:12.783550 MD32_EN : 0
6149 16:44:12.783674 ===================================
6150 16:44:12.783764 [ANA_INIT] >>>>>>>>>>>>>>
6151 16:44:12.783853 <<<<<< [CONFIGURE PHASE]: ANA_TX
6152 16:44:12.783942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6153 16:44:12.784030 ===================================
6154 16:44:12.784118 data_rate = 800,PCW = 0X7400
6155 16:44:12.784206 ===================================
6156 16:44:12.784294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6157 16:44:12.784383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6158 16:44:12.784474 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6159 16:44:12.784563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6160 16:44:12.784651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6161 16:44:12.784740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6162 16:44:12.784826 [ANA_INIT] flow start
6163 16:44:12.784911 [ANA_INIT] PLL >>>>>>>>
6164 16:44:12.785003 [ANA_INIT] PLL <<<<<<<<
6165 16:44:12.785119 [ANA_INIT] MIDPI >>>>>>>>
6166 16:44:12.785251 [ANA_INIT] MIDPI <<<<<<<<
6167 16:44:12.785381 [ANA_INIT] DLL >>>>>>>>
6168 16:44:12.785496 [ANA_INIT] flow end
6169 16:44:12.785611 ============ LP4 DIFF to SE enter ============
6170 16:44:12.785762 ============ LP4 DIFF to SE exit ============
6171 16:44:12.785861 [ANA_INIT] <<<<<<<<<<<<<
6172 16:44:12.785955 [Flow] Enable top DCM control >>>>>
6173 16:44:12.786046 [Flow] Enable top DCM control <<<<<
6174 16:44:12.786135 Enable DLL master slave shuffle
6175 16:44:12.786222 ==============================================================
6176 16:44:12.786312 Gating Mode config
6177 16:44:12.786422 ==============================================================
6178 16:44:12.786543 Config description:
6179 16:44:12.786639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6180 16:44:12.786746 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6181 16:44:12.786836 SELPH_MODE 0: By rank 1: By Phase
6182 16:44:12.786925 ==============================================================
6183 16:44:12.787029 GAT_TRACK_EN = 0
6184 16:44:12.787155 RX_GATING_MODE = 2
6185 16:44:12.787287 RX_GATING_TRACK_MODE = 2
6186 16:44:12.787376 SELPH_MODE = 1
6187 16:44:12.787462 PICG_EARLY_EN = 1
6188 16:44:12.787550 VALID_LAT_VALUE = 1
6189 16:44:12.787660 ==============================================================
6190 16:44:12.787717 Enter into Gating configuration >>>>
6191 16:44:12.787785 Exit from Gating configuration <<<<
6192 16:44:12.787864 Enter into DVFS_PRE_config >>>>>
6193 16:44:12.787961 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6194 16:44:12.788059 Exit from DVFS_PRE_config <<<<<
6195 16:44:12.788162 Enter into PICG configuration >>>>
6196 16:44:12.788250 Exit from PICG configuration <<<<
6197 16:44:12.788339 [RX_INPUT] configuration >>>>>
6198 16:44:12.788425 [RX_INPUT] configuration <<<<<
6199 16:44:12.788542 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6200 16:44:12.788604 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6201 16:44:12.788666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 16:44:12.788728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 16:44:12.788785 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6204 16:44:12.788858 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6205 16:44:12.788960 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6206 16:44:12.792263 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6207 16:44:12.795293 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6208 16:44:12.798816 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6209 16:44:12.805022 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6210 16:44:12.808614 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6211 16:44:12.811869 ===================================
6212 16:44:12.814841 LPDDR4 DRAM CONFIGURATION
6213 16:44:12.818228 ===================================
6214 16:44:12.818330 EX_ROW_EN[0] = 0x0
6215 16:44:12.821512 EX_ROW_EN[1] = 0x0
6216 16:44:12.821612 LP4Y_EN = 0x0
6217 16:44:12.825400 WORK_FSP = 0x0
6218 16:44:12.825504 WL = 0x2
6219 16:44:12.828270 RL = 0x2
6220 16:44:12.828368 BL = 0x2
6221 16:44:12.831897 RPST = 0x0
6222 16:44:12.834749 RD_PRE = 0x0
6223 16:44:12.834823 WR_PRE = 0x1
6224 16:44:12.838279 WR_PST = 0x0
6225 16:44:12.838379 DBI_WR = 0x0
6226 16:44:12.841199 DBI_RD = 0x0
6227 16:44:12.841306 OTF = 0x1
6228 16:44:12.844542 ===================================
6229 16:44:12.847920 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6230 16:44:12.854553 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6231 16:44:12.857542 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6232 16:44:12.861243 ===================================
6233 16:44:12.864189 LPDDR4 DRAM CONFIGURATION
6234 16:44:12.868014 ===================================
6235 16:44:12.868117 EX_ROW_EN[0] = 0x10
6236 16:44:12.871063 EX_ROW_EN[1] = 0x0
6237 16:44:12.871163 LP4Y_EN = 0x0
6238 16:44:12.874138 WORK_FSP = 0x0
6239 16:44:12.877146 WL = 0x2
6240 16:44:12.877246 RL = 0x2
6241 16:44:12.880954 BL = 0x2
6242 16:44:12.881066 RPST = 0x0
6243 16:44:12.884111 RD_PRE = 0x0
6244 16:44:12.884215 WR_PRE = 0x1
6245 16:44:12.887211 WR_PST = 0x0
6246 16:44:12.887313 DBI_WR = 0x0
6247 16:44:12.890702 DBI_RD = 0x0
6248 16:44:12.890781 OTF = 0x1
6249 16:44:12.894039 ===================================
6250 16:44:12.900114 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6251 16:44:12.904998 nWR fixed to 30
6252 16:44:12.907792 [ModeRegInit_LP4] CH0 RK0
6253 16:44:12.907886 [ModeRegInit_LP4] CH0 RK1
6254 16:44:12.911447 [ModeRegInit_LP4] CH1 RK0
6255 16:44:12.914287 [ModeRegInit_LP4] CH1 RK1
6256 16:44:12.914403 match AC timing 19
6257 16:44:12.921259 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6258 16:44:12.924798 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6259 16:44:12.927522 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6260 16:44:12.934005 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6261 16:44:12.937484 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6262 16:44:12.937562 ==
6263 16:44:12.940863 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 16:44:12.944328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 16:44:12.944404 ==
6266 16:44:12.950768 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6267 16:44:12.957382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6268 16:44:12.960424 [CA 0] Center 36 (8~64) winsize 57
6269 16:44:12.964030 [CA 1] Center 36 (8~64) winsize 57
6270 16:44:12.967177 [CA 2] Center 36 (8~64) winsize 57
6271 16:44:12.971002 [CA 3] Center 36 (8~64) winsize 57
6272 16:44:12.974052 [CA 4] Center 36 (8~64) winsize 57
6273 16:44:12.977120 [CA 5] Center 36 (8~64) winsize 57
6274 16:44:12.977207
6275 16:44:12.980316 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6276 16:44:12.980402
6277 16:44:12.984073 [CATrainingPosCal] consider 1 rank data
6278 16:44:12.987032 u2DelayCellTimex100 = 270/100 ps
6279 16:44:12.990794 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 16:44:12.993750 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 16:44:12.996743 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 16:44:13.000139 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 16:44:13.003762 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 16:44:13.006834 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 16:44:13.006921
6286 16:44:13.009865 CA PerBit enable=1, Macro0, CA PI delay=36
6287 16:44:13.013404
6288 16:44:13.013490 [CBTSetCACLKResult] CA Dly = 36
6289 16:44:13.016858 CS Dly: 1 (0~32)
6290 16:44:13.016944 ==
6291 16:44:13.020377 Dram Type= 6, Freq= 0, CH_0, rank 1
6292 16:44:13.023125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 16:44:13.023215 ==
6294 16:44:13.029717 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6295 16:44:13.036642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6296 16:44:13.040048 [CA 0] Center 36 (8~64) winsize 57
6297 16:44:13.043060 [CA 1] Center 36 (8~64) winsize 57
6298 16:44:13.046212 [CA 2] Center 36 (8~64) winsize 57
6299 16:44:13.049873 [CA 3] Center 36 (8~64) winsize 57
6300 16:44:13.049983 [CA 4] Center 36 (8~64) winsize 57
6301 16:44:13.053160 [CA 5] Center 36 (8~64) winsize 57
6302 16:44:13.053241
6303 16:44:13.059747 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6304 16:44:13.059857
6305 16:44:13.062800 [CATrainingPosCal] consider 2 rank data
6306 16:44:13.066172 u2DelayCellTimex100 = 270/100 ps
6307 16:44:13.069491 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 16:44:13.072750 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 16:44:13.075856 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 16:44:13.079033 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 16:44:13.082756 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 16:44:13.085840 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:44:13.085944
6314 16:44:13.088800 CA PerBit enable=1, Macro0, CA PI delay=36
6315 16:44:13.092388
6316 16:44:13.092491 [CBTSetCACLKResult] CA Dly = 36
6317 16:44:13.095646 CS Dly: 1 (0~32)
6318 16:44:13.095761
6319 16:44:13.098668 ----->DramcWriteLeveling(PI) begin...
6320 16:44:13.098774 ==
6321 16:44:13.102107 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 16:44:13.105625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 16:44:13.105731 ==
6324 16:44:13.108678 Write leveling (Byte 0): 40 => 8
6325 16:44:13.111885 Write leveling (Byte 1): 40 => 8
6326 16:44:13.115650 DramcWriteLeveling(PI) end<-----
6327 16:44:13.115763
6328 16:44:13.115858 ==
6329 16:44:13.118570 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 16:44:13.122010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 16:44:13.122124 ==
6332 16:44:13.125418 [Gating] SW mode calibration
6333 16:44:13.131699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6334 16:44:13.138726 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6335 16:44:13.141585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6336 16:44:13.148740 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6337 16:44:13.151781 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6338 16:44:13.154855 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 16:44:13.161414 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 16:44:13.165178 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 16:44:13.168323 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6342 16:44:13.174536 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 16:44:13.177921 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 16:44:13.181666 Total UI for P1: 0, mck2ui 16
6345 16:44:13.184677 best dqsien dly found for B0: ( 0, 14, 24)
6346 16:44:13.187908 Total UI for P1: 0, mck2ui 16
6347 16:44:13.190971 best dqsien dly found for B1: ( 0, 14, 24)
6348 16:44:13.194750 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6349 16:44:13.197769 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6350 16:44:13.197881
6351 16:44:13.200986 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6352 16:44:13.207867 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6353 16:44:13.207953 [Gating] SW calibration Done
6354 16:44:13.208021 ==
6355 16:44:13.210813 Dram Type= 6, Freq= 0, CH_0, rank 0
6356 16:44:13.217639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6357 16:44:13.217751 ==
6358 16:44:13.217848 RX Vref Scan: 0
6359 16:44:13.217941
6360 16:44:13.220633 RX Vref 0 -> 0, step: 1
6361 16:44:13.220733
6362 16:44:13.224394 RX Delay -410 -> 252, step: 16
6363 16:44:13.227275 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6364 16:44:13.230715 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6365 16:44:13.237633 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6366 16:44:13.240399 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6367 16:44:13.243886 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6368 16:44:13.246941 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6369 16:44:13.253751 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6370 16:44:13.257266 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6371 16:44:13.260524 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6372 16:44:13.263601 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6373 16:44:13.270039 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6374 16:44:13.273244 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6375 16:44:13.276741 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6376 16:44:13.283460 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6377 16:44:13.286517 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6378 16:44:13.289606 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6379 16:44:13.289707 ==
6380 16:44:13.293271 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 16:44:13.296277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 16:44:13.299922 ==
6383 16:44:13.300037 DQS Delay:
6384 16:44:13.300137 DQS0 = 59, DQS1 = 59
6385 16:44:13.303031 DQM Delay:
6386 16:44:13.303114 DQM0 = 18, DQM1 = 9
6387 16:44:13.306336 DQ Delay:
6388 16:44:13.309827 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6389 16:44:13.309912 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6390 16:44:13.312730 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6391 16:44:13.316368 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6392 16:44:13.316452
6393 16:44:13.316518
6394 16:44:13.319425 ==
6395 16:44:13.323037 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 16:44:13.326096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 16:44:13.326182 ==
6398 16:44:13.326282
6399 16:44:13.326385
6400 16:44:13.329089 TX Vref Scan disable
6401 16:44:13.329173 == TX Byte 0 ==
6402 16:44:13.332674 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 16:44:13.338997 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 16:44:13.339120 == TX Byte 1 ==
6405 16:44:13.342535 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 16:44:13.348922 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 16:44:13.349050 ==
6408 16:44:13.352241 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 16:44:13.355389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 16:44:13.355518 ==
6411 16:44:13.355644
6412 16:44:13.355745
6413 16:44:13.359104 TX Vref Scan disable
6414 16:44:13.359205 == TX Byte 0 ==
6415 16:44:13.365594 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 16:44:13.368765 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 16:44:13.368851 == TX Byte 1 ==
6418 16:44:13.372370 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 16:44:13.378981 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 16:44:13.379079
6421 16:44:13.379157 [DATLAT]
6422 16:44:13.381926 Freq=400, CH0 RK0
6423 16:44:13.382011
6424 16:44:13.382086 DATLAT Default: 0xf
6425 16:44:13.385641 0, 0xFFFF, sum = 0
6426 16:44:13.385730 1, 0xFFFF, sum = 0
6427 16:44:13.388799 2, 0xFFFF, sum = 0
6428 16:44:13.388885 3, 0xFFFF, sum = 0
6429 16:44:13.392060 4, 0xFFFF, sum = 0
6430 16:44:13.392145 5, 0xFFFF, sum = 0
6431 16:44:13.395830 6, 0xFFFF, sum = 0
6432 16:44:13.395917 7, 0xFFFF, sum = 0
6433 16:44:13.398759 8, 0xFFFF, sum = 0
6434 16:44:13.398844 9, 0xFFFF, sum = 0
6435 16:44:13.401993 10, 0xFFFF, sum = 0
6436 16:44:13.402079 11, 0xFFFF, sum = 0
6437 16:44:13.405642 12, 0xFFFF, sum = 0
6438 16:44:13.405737 13, 0x0, sum = 1
6439 16:44:13.408358 14, 0x0, sum = 2
6440 16:44:13.408443 15, 0x0, sum = 3
6441 16:44:13.412030 16, 0x0, sum = 4
6442 16:44:13.412115 best_step = 14
6443 16:44:13.412182
6444 16:44:13.412244 ==
6445 16:44:13.415001 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 16:44:13.421714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 16:44:13.421800 ==
6448 16:44:13.421867 RX Vref Scan: 1
6449 16:44:13.421929
6450 16:44:13.424766 RX Vref 0 -> 0, step: 1
6451 16:44:13.424853
6452 16:44:13.428339 RX Delay -359 -> 252, step: 8
6453 16:44:13.428425
6454 16:44:13.431417 Set Vref, RX VrefLevel [Byte0]: 60
6455 16:44:13.435060 [Byte1]: 55
6456 16:44:13.438230
6457 16:44:13.438346 Final RX Vref Byte 0 = 60 to rank0
6458 16:44:13.441911 Final RX Vref Byte 1 = 55 to rank0
6459 16:44:13.444778 Final RX Vref Byte 0 = 60 to rank1
6460 16:44:13.448118 Final RX Vref Byte 1 = 55 to rank1==
6461 16:44:13.451768 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 16:44:13.457902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 16:44:13.458029 ==
6464 16:44:13.458153 DQS Delay:
6465 16:44:13.461380 DQS0 = 60, DQS1 = 68
6466 16:44:13.461468 DQM Delay:
6467 16:44:13.461540 DQM0 = 14, DQM1 = 13
6468 16:44:13.464759 DQ Delay:
6469 16:44:13.467990 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =8
6470 16:44:13.471465 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6471 16:44:13.471588 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6472 16:44:13.474485 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6473 16:44:13.478116
6474 16:44:13.478204
6475 16:44:13.484506 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6476 16:44:13.487994 CH0 RK0: MR19=C0C, MR18=8281
6477 16:44:13.494640 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6478 16:44:13.494727 ==
6479 16:44:13.498102 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 16:44:13.501151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 16:44:13.501239 ==
6482 16:44:13.504186 [Gating] SW mode calibration
6483 16:44:13.510928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6484 16:44:13.517729 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6485 16:44:13.520614 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6486 16:44:13.524292 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6487 16:44:13.530468 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6488 16:44:13.534088 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 16:44:13.537198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 16:44:13.544023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 16:44:13.547054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6492 16:44:13.550740 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 16:44:13.557077 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 16:44:13.560373 Total UI for P1: 0, mck2ui 16
6495 16:44:13.563745 best dqsien dly found for B0: ( 0, 14, 24)
6496 16:44:13.563826 Total UI for P1: 0, mck2ui 16
6497 16:44:13.570542 best dqsien dly found for B1: ( 0, 14, 24)
6498 16:44:13.573351 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6499 16:44:13.576948 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6500 16:44:13.577035
6501 16:44:13.580480 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6502 16:44:13.583532 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6503 16:44:13.586988 [Gating] SW calibration Done
6504 16:44:13.587086 ==
6505 16:44:13.590030 Dram Type= 6, Freq= 0, CH_0, rank 1
6506 16:44:13.593389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6507 16:44:13.593476 ==
6508 16:44:13.596904 RX Vref Scan: 0
6509 16:44:13.596993
6510 16:44:13.597062 RX Vref 0 -> 0, step: 1
6511 16:44:13.599832
6512 16:44:13.599918 RX Delay -410 -> 252, step: 16
6513 16:44:13.606479 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6514 16:44:13.610122 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6515 16:44:13.613262 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6516 16:44:13.619501 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6517 16:44:13.623088 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6518 16:44:13.626674 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6519 16:44:13.629739 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6520 16:44:13.636388 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6521 16:44:13.639500 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6522 16:44:13.642544 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6523 16:44:13.645798 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6524 16:44:13.652679 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6525 16:44:13.655718 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6526 16:44:13.659194 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6527 16:44:13.662406 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6528 16:44:13.669124 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6529 16:44:13.669210 ==
6530 16:44:13.672305 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 16:44:13.675721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 16:44:13.675803 ==
6533 16:44:13.678864 DQS Delay:
6534 16:44:13.678938 DQS0 = 59, DQS1 = 59
6535 16:44:13.679002 DQM Delay:
6536 16:44:13.682288 DQM0 = 17, DQM1 = 10
6537 16:44:13.682389 DQ Delay:
6538 16:44:13.685626 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6539 16:44:13.688572 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6540 16:44:13.692104 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6541 16:44:13.695233 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6542 16:44:13.695354
6543 16:44:13.695467
6544 16:44:13.695567 ==
6545 16:44:13.698865 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 16:44:13.705070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 16:44:13.705184 ==
6548 16:44:13.705283
6549 16:44:13.705375
6550 16:44:13.705441 TX Vref Scan disable
6551 16:44:13.708160 == TX Byte 0 ==
6552 16:44:13.711470 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6553 16:44:13.715144 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6554 16:44:13.718092 == TX Byte 1 ==
6555 16:44:13.721307 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6556 16:44:13.724804 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6557 16:44:13.724935 ==
6558 16:44:13.728512 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 16:44:13.734928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 16:44:13.735043 ==
6561 16:44:13.735155
6562 16:44:13.735257
6563 16:44:13.735355 TX Vref Scan disable
6564 16:44:13.738017 == TX Byte 0 ==
6565 16:44:13.741726 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6566 16:44:13.744687 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6567 16:44:13.747701 == TX Byte 1 ==
6568 16:44:13.751451 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6569 16:44:13.754761 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6570 16:44:13.757720
6571 16:44:13.757833 [DATLAT]
6572 16:44:13.757941 Freq=400, CH0 RK1
6573 16:44:13.758044
6574 16:44:13.761296 DATLAT Default: 0xe
6575 16:44:13.761411 0, 0xFFFF, sum = 0
6576 16:44:13.764453 1, 0xFFFF, sum = 0
6577 16:44:13.764568 2, 0xFFFF, sum = 0
6578 16:44:13.767515 3, 0xFFFF, sum = 0
6579 16:44:13.767642 4, 0xFFFF, sum = 0
6580 16:44:13.771124 5, 0xFFFF, sum = 0
6581 16:44:13.773875 6, 0xFFFF, sum = 0
6582 16:44:13.773991 7, 0xFFFF, sum = 0
6583 16:44:13.777168 8, 0xFFFF, sum = 0
6584 16:44:13.777278 9, 0xFFFF, sum = 0
6585 16:44:13.780667 10, 0xFFFF, sum = 0
6586 16:44:13.780775 11, 0xFFFF, sum = 0
6587 16:44:13.783868 12, 0xFFFF, sum = 0
6588 16:44:13.783981 13, 0x0, sum = 1
6589 16:44:13.787157 14, 0x0, sum = 2
6590 16:44:13.787270 15, 0x0, sum = 3
6591 16:44:13.790655 16, 0x0, sum = 4
6592 16:44:13.790773 best_step = 14
6593 16:44:13.790877
6594 16:44:13.790982 ==
6595 16:44:13.793815 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 16:44:13.797388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 16:44:13.800643 ==
6598 16:44:13.800758 RX Vref Scan: 0
6599 16:44:13.800860
6600 16:44:13.803877 RX Vref 0 -> 0, step: 1
6601 16:44:13.803985
6602 16:44:13.807064 RX Delay -359 -> 252, step: 8
6603 16:44:13.813486 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6604 16:44:13.816752 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6605 16:44:13.820442 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6606 16:44:13.823361 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6607 16:44:13.829894 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6608 16:44:13.833385 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6609 16:44:13.836976 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6610 16:44:13.839959 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6611 16:44:13.846740 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6612 16:44:13.849776 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6613 16:44:13.852909 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6614 16:44:13.856623 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6615 16:44:13.863155 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6616 16:44:13.866065 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6617 16:44:13.869839 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6618 16:44:13.876009 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6619 16:44:13.876096 ==
6620 16:44:13.879552 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 16:44:13.882510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 16:44:13.882624 ==
6623 16:44:13.882730 DQS Delay:
6624 16:44:13.886251 DQS0 = 60, DQS1 = 72
6625 16:44:13.886337 DQM Delay:
6626 16:44:13.889344 DQM0 = 11, DQM1 = 18
6627 16:44:13.889430 DQ Delay:
6628 16:44:13.892542 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6629 16:44:13.895783 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6630 16:44:13.899850 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6631 16:44:13.902516 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6632 16:44:13.902643
6633 16:44:13.902757
6634 16:44:13.909038 [DQSOSCAuto] RK1, (LSB)MR18= 0xca7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6635 16:44:13.912503 CH0 RK1: MR19=C0C, MR18=CA7F
6636 16:44:13.918876 CH0_RK1: MR19=0xC0C, MR18=0xCA7F, DQSOSC=384, MR23=63, INC=400, DEC=267
6637 16:44:13.922545 [RxdqsGatingPostProcess] freq 400
6638 16:44:13.928777 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6639 16:44:13.932500 best DQS0 dly(2T, 0.5T) = (0, 10)
6640 16:44:13.935492 best DQS1 dly(2T, 0.5T) = (0, 10)
6641 16:44:13.935624 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6642 16:44:13.939088 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6643 16:44:13.942115 best DQS0 dly(2T, 0.5T) = (0, 10)
6644 16:44:13.945719 best DQS1 dly(2T, 0.5T) = (0, 10)
6645 16:44:13.948926 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6646 16:44:13.951812 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6647 16:44:13.955798 Pre-setting of DQS Precalculation
6648 16:44:13.961816 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6649 16:44:13.961944 ==
6650 16:44:13.965663 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 16:44:13.968574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 16:44:13.968699 ==
6653 16:44:13.975259 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6654 16:44:13.981907 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6655 16:44:13.984811 [CA 0] Center 36 (8~64) winsize 57
6656 16:44:13.988038 [CA 1] Center 36 (8~64) winsize 57
6657 16:44:13.988165 [CA 2] Center 36 (8~64) winsize 57
6658 16:44:13.991793 [CA 3] Center 36 (8~64) winsize 57
6659 16:44:13.994665 [CA 4] Center 36 (8~64) winsize 57
6660 16:44:13.998128 [CA 5] Center 36 (8~64) winsize 57
6661 16:44:13.998280
6662 16:44:14.001690 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6663 16:44:14.004378
6664 16:44:14.007697 [CATrainingPosCal] consider 1 rank data
6665 16:44:14.011061 u2DelayCellTimex100 = 270/100 ps
6666 16:44:14.014849 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 16:44:14.017642 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 16:44:14.020999 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 16:44:14.024487 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 16:44:14.027724 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 16:44:14.031045 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 16:44:14.031201
6673 16:44:14.034275 CA PerBit enable=1, Macro0, CA PI delay=36
6674 16:44:14.034421
6675 16:44:14.037388 [CBTSetCACLKResult] CA Dly = 36
6676 16:44:14.041177 CS Dly: 1 (0~32)
6677 16:44:14.041317 ==
6678 16:44:14.044097 Dram Type= 6, Freq= 0, CH_1, rank 1
6679 16:44:14.047559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 16:44:14.047714 ==
6681 16:44:14.054195 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6682 16:44:14.060717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6683 16:44:14.063920 [CA 0] Center 36 (8~64) winsize 57
6684 16:44:14.064071 [CA 1] Center 36 (8~64) winsize 57
6685 16:44:14.066876 [CA 2] Center 36 (8~64) winsize 57
6686 16:44:14.070768 [CA 3] Center 36 (8~64) winsize 57
6687 16:44:14.073503 [CA 4] Center 36 (8~64) winsize 57
6688 16:44:14.077233 [CA 5] Center 36 (8~64) winsize 57
6689 16:44:14.077400
6690 16:44:14.080381 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6691 16:44:14.080534
6692 16:44:14.086842 [CATrainingPosCal] consider 2 rank data
6693 16:44:14.087028 u2DelayCellTimex100 = 270/100 ps
6694 16:44:14.093597 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 16:44:14.096636 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 16:44:14.100311 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 16:44:14.103225 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 16:44:14.106918 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 16:44:14.109718 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:44:14.109887
6701 16:44:14.113407 CA PerBit enable=1, Macro0, CA PI delay=36
6702 16:44:14.113572
6703 16:44:14.116431 [CBTSetCACLKResult] CA Dly = 36
6704 16:44:14.120027 CS Dly: 1 (0~32)
6705 16:44:14.120198
6706 16:44:14.123306 ----->DramcWriteLeveling(PI) begin...
6707 16:44:14.123472 ==
6708 16:44:14.126768 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 16:44:14.129821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 16:44:14.129992 ==
6711 16:44:14.132682 Write leveling (Byte 0): 40 => 8
6712 16:44:14.136119 Write leveling (Byte 1): 40 => 8
6713 16:44:14.139570 DramcWriteLeveling(PI) end<-----
6714 16:44:14.139734
6715 16:44:14.139867 ==
6716 16:44:14.142690 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 16:44:14.146334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 16:44:14.146489 ==
6719 16:44:14.149109 [Gating] SW mode calibration
6720 16:44:14.155840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6721 16:44:14.162662 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6722 16:44:14.165660 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6723 16:44:14.168923 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6724 16:44:14.175474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6725 16:44:14.179073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 16:44:14.182675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 16:44:14.188779 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 16:44:14.192371 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6729 16:44:14.195454 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 16:44:14.202171 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 16:44:14.205005 Total UI for P1: 0, mck2ui 16
6732 16:44:14.208599 best dqsien dly found for B0: ( 0, 14, 24)
6733 16:44:14.211872 Total UI for P1: 0, mck2ui 16
6734 16:44:14.215340 best dqsien dly found for B1: ( 0, 14, 24)
6735 16:44:14.218291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6736 16:44:14.221607 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6737 16:44:14.221771
6738 16:44:14.225381 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6739 16:44:14.228861 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6740 16:44:14.232031 [Gating] SW calibration Done
6741 16:44:14.232194 ==
6742 16:44:14.235117 Dram Type= 6, Freq= 0, CH_1, rank 0
6743 16:44:14.238085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6744 16:44:14.241473 ==
6745 16:44:14.241626 RX Vref Scan: 0
6746 16:44:14.241762
6747 16:44:14.244666 RX Vref 0 -> 0, step: 1
6748 16:44:14.244814
6749 16:44:14.248442 RX Delay -410 -> 252, step: 16
6750 16:44:14.251439 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6751 16:44:14.255086 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6752 16:44:14.258045 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6753 16:44:14.264971 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6754 16:44:14.267980 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6755 16:44:14.271175 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6756 16:44:14.274463 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6757 16:44:14.280944 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6758 16:44:14.284528 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6759 16:44:14.287648 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6760 16:44:14.294542 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6761 16:44:14.297356 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6762 16:44:14.300459 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6763 16:44:14.304135 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6764 16:44:14.310764 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6765 16:44:14.314234 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6766 16:44:14.314393 ==
6767 16:44:14.317326 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 16:44:14.320445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 16:44:14.320602 ==
6770 16:44:14.323915 DQS Delay:
6771 16:44:14.324062 DQS0 = 51, DQS1 = 67
6772 16:44:14.327371 DQM Delay:
6773 16:44:14.327523 DQM0 = 13, DQM1 = 18
6774 16:44:14.327671 DQ Delay:
6775 16:44:14.330744 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6776 16:44:14.333702 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6777 16:44:14.336919 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6778 16:44:14.340259 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6779 16:44:14.340416
6780 16:44:14.340552
6781 16:44:14.340688 ==
6782 16:44:14.344068 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 16:44:14.350150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 16:44:14.350298 ==
6785 16:44:14.350430
6786 16:44:14.350562
6787 16:44:14.350686 TX Vref Scan disable
6788 16:44:14.353633 == TX Byte 0 ==
6789 16:44:14.356518 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 16:44:14.360274 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 16:44:14.363300 == TX Byte 1 ==
6792 16:44:14.366888 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 16:44:14.369933 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 16:44:14.370032 ==
6795 16:44:14.373133 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 16:44:14.380010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 16:44:14.380150 ==
6798 16:44:14.380253
6799 16:44:14.380369
6800 16:44:14.382970 TX Vref Scan disable
6801 16:44:14.383056 == TX Byte 0 ==
6802 16:44:14.386507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 16:44:14.393047 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 16:44:14.393137 == TX Byte 1 ==
6805 16:44:14.396159 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 16:44:14.402634 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 16:44:14.402725
6808 16:44:14.402795 [DATLAT]
6809 16:44:14.402865 Freq=400, CH1 RK0
6810 16:44:14.402929
6811 16:44:14.406424 DATLAT Default: 0xf
6812 16:44:14.406529 0, 0xFFFF, sum = 0
6813 16:44:14.409435 1, 0xFFFF, sum = 0
6814 16:44:14.409541 2, 0xFFFF, sum = 0
6815 16:44:14.412483 3, 0xFFFF, sum = 0
6816 16:44:14.416212 4, 0xFFFF, sum = 0
6817 16:44:14.416297 5, 0xFFFF, sum = 0
6818 16:44:14.419275 6, 0xFFFF, sum = 0
6819 16:44:14.419369 7, 0xFFFF, sum = 0
6820 16:44:14.422618 8, 0xFFFF, sum = 0
6821 16:44:14.422725 9, 0xFFFF, sum = 0
6822 16:44:14.426190 10, 0xFFFF, sum = 0
6823 16:44:14.426297 11, 0xFFFF, sum = 0
6824 16:44:14.429176 12, 0xFFFF, sum = 0
6825 16:44:14.429281 13, 0x0, sum = 1
6826 16:44:14.432826 14, 0x0, sum = 2
6827 16:44:14.432940 15, 0x0, sum = 3
6828 16:44:14.435754 16, 0x0, sum = 4
6829 16:44:14.435850 best_step = 14
6830 16:44:14.435948
6831 16:44:14.436042 ==
6832 16:44:14.439182 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 16:44:14.442666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 16:44:14.445483 ==
6835 16:44:14.445573 RX Vref Scan: 1
6836 16:44:14.445641
6837 16:44:14.449225 RX Vref 0 -> 0, step: 1
6838 16:44:14.449313
6839 16:44:14.452500 RX Delay -375 -> 252, step: 8
6840 16:44:14.452602
6841 16:44:14.455922 Set Vref, RX VrefLevel [Byte0]: 58
6842 16:44:14.459001 [Byte1]: 50
6843 16:44:14.459103
6844 16:44:14.462100 Final RX Vref Byte 0 = 58 to rank0
6845 16:44:14.465184 Final RX Vref Byte 1 = 50 to rank0
6846 16:44:14.469209 Final RX Vref Byte 0 = 58 to rank1
6847 16:44:14.471968 Final RX Vref Byte 1 = 50 to rank1==
6848 16:44:14.475987 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 16:44:14.478819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 16:44:14.481854 ==
6851 16:44:14.481968 DQS Delay:
6852 16:44:14.482040 DQS0 = 52, DQS1 = 64
6853 16:44:14.485127 DQM Delay:
6854 16:44:14.485208 DQM0 = 9, DQM1 = 11
6855 16:44:14.489030 DQ Delay:
6856 16:44:14.489130 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6857 16:44:14.491856 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6858 16:44:14.495680 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6859 16:44:14.498301 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6860 16:44:14.498436
6861 16:44:14.498536
6862 16:44:14.508358 [DQSOSCAuto] RK0, (LSB)MR18= 0x5568, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
6863 16:44:14.511493 CH1 RK0: MR19=C0C, MR18=5568
6864 16:44:14.518144 CH1_RK0: MR19=0xC0C, MR18=0x5568, DQSOSC=396, MR23=63, INC=376, DEC=251
6865 16:44:14.518260 ==
6866 16:44:14.521820 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 16:44:14.524942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 16:44:14.525022 ==
6869 16:44:14.527968 [Gating] SW mode calibration
6870 16:44:14.535351 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6871 16:44:14.538361 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6872 16:44:14.544907 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6873 16:44:14.548276 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6874 16:44:14.551268 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6875 16:44:14.557703 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 16:44:14.561326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 16:44:14.567655 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 16:44:14.570754 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6879 16:44:14.574247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 16:44:14.580643 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 16:44:14.580766 Total UI for P1: 0, mck2ui 16
6882 16:44:14.584312 best dqsien dly found for B0: ( 0, 14, 24)
6883 16:44:14.587536 Total UI for P1: 0, mck2ui 16
6884 16:44:14.590638 best dqsien dly found for B1: ( 0, 14, 24)
6885 16:44:14.597557 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6886 16:44:14.600634 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6887 16:44:14.600771
6888 16:44:14.604168 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6889 16:44:14.607473 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6890 16:44:14.610488 [Gating] SW calibration Done
6891 16:44:14.610598 ==
6892 16:44:14.613956 Dram Type= 6, Freq= 0, CH_1, rank 1
6893 16:44:14.617063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6894 16:44:14.617158 ==
6895 16:44:14.620713 RX Vref Scan: 0
6896 16:44:14.620800
6897 16:44:14.620870 RX Vref 0 -> 0, step: 1
6898 16:44:14.620934
6899 16:44:14.623666 RX Delay -410 -> 252, step: 16
6900 16:44:14.630626 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6901 16:44:14.633699 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6902 16:44:14.636724 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6903 16:44:14.640509 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6904 16:44:14.646472 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6905 16:44:14.650139 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6906 16:44:14.653573 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6907 16:44:14.656928 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6908 16:44:14.662991 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6909 16:44:14.666303 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6910 16:44:14.669470 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6911 16:44:14.672942 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6912 16:44:14.679474 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6913 16:44:14.683172 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6914 16:44:14.686417 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6915 16:44:14.692583 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6916 16:44:14.692675 ==
6917 16:44:14.696192 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 16:44:14.699375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 16:44:14.699514 ==
6920 16:44:14.699633 DQS Delay:
6921 16:44:14.702750 DQS0 = 59, DQS1 = 59
6922 16:44:14.702828 DQM Delay:
6923 16:44:14.705941 DQM0 = 19, DQM1 = 13
6924 16:44:14.706045 DQ Delay:
6925 16:44:14.708976 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6926 16:44:14.712605 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6927 16:44:14.715427 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6928 16:44:14.719056 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6929 16:44:14.719164
6930 16:44:14.719261
6931 16:44:14.719354 ==
6932 16:44:14.722059 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 16:44:14.725739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 16:44:14.725837 ==
6935 16:44:14.728631
6936 16:44:14.728717
6937 16:44:14.728786 TX Vref Scan disable
6938 16:44:14.732332 == TX Byte 0 ==
6939 16:44:14.735475 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6940 16:44:14.738563 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6941 16:44:14.742348 == TX Byte 1 ==
6942 16:44:14.745457 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 16:44:14.748533 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 16:44:14.748654 ==
6945 16:44:14.751505 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 16:44:14.758358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 16:44:14.758483 ==
6948 16:44:14.758601
6949 16:44:14.758692
6950 16:44:14.758822 TX Vref Scan disable
6951 16:44:14.761670 == TX Byte 0 ==
6952 16:44:14.764934 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6953 16:44:14.768254 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6954 16:44:14.771404 == TX Byte 1 ==
6955 16:44:14.775098 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6956 16:44:14.778082 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6957 16:44:14.778194
6958 16:44:14.781571 [DATLAT]
6959 16:44:14.781675 Freq=400, CH1 RK1
6960 16:44:14.781768
6961 16:44:14.785046 DATLAT Default: 0xe
6962 16:44:14.785133 0, 0xFFFF, sum = 0
6963 16:44:14.788078 1, 0xFFFF, sum = 0
6964 16:44:14.788157 2, 0xFFFF, sum = 0
6965 16:44:14.791505 3, 0xFFFF, sum = 0
6966 16:44:14.791631 4, 0xFFFF, sum = 0
6967 16:44:14.794613 5, 0xFFFF, sum = 0
6968 16:44:14.794722 6, 0xFFFF, sum = 0
6969 16:44:14.798307 7, 0xFFFF, sum = 0
6970 16:44:14.798429 8, 0xFFFF, sum = 0
6971 16:44:14.801320 9, 0xFFFF, sum = 0
6972 16:44:14.801402 10, 0xFFFF, sum = 0
6973 16:44:14.804479 11, 0xFFFF, sum = 0
6974 16:44:14.807864 12, 0xFFFF, sum = 0
6975 16:44:14.807952 13, 0x0, sum = 1
6976 16:44:14.808019 14, 0x0, sum = 2
6977 16:44:14.811534 15, 0x0, sum = 3
6978 16:44:14.811648 16, 0x0, sum = 4
6979 16:44:14.814528 best_step = 14
6980 16:44:14.814605
6981 16:44:14.814668 ==
6982 16:44:14.817526 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 16:44:14.821107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 16:44:14.821193 ==
6985 16:44:14.824162 RX Vref Scan: 0
6986 16:44:14.824235
6987 16:44:14.827319 RX Vref 0 -> 0, step: 1
6988 16:44:14.827398
6989 16:44:14.827495 RX Delay -359 -> 252, step: 8
6990 16:44:14.835888 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6991 16:44:14.839608 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6992 16:44:14.842629 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6993 16:44:14.849572 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6994 16:44:14.852760 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6995 16:44:14.856274 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6996 16:44:14.859225 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6997 16:44:14.865981 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6998 16:44:14.869316 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6999 16:44:14.872438 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7000 16:44:14.875684 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7001 16:44:14.882398 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7002 16:44:14.885313 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7003 16:44:14.888949 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7004 16:44:14.891917 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7005 16:44:14.898942 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7006 16:44:14.899065 ==
7007 16:44:14.901722 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 16:44:14.905442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 16:44:14.905528 ==
7010 16:44:14.908416 DQS Delay:
7011 16:44:14.908521 DQS0 = 60, DQS1 = 64
7012 16:44:14.908595 DQM Delay:
7013 16:44:14.911932 DQM0 = 13, DQM1 = 10
7014 16:44:14.912023 DQ Delay:
7015 16:44:14.915164 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7016 16:44:14.918137 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
7017 16:44:14.921834 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7018 16:44:14.924741 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7019 16:44:14.924829
7020 16:44:14.924896
7021 16:44:14.934617 [DQSOSCAuto] RK1, (LSB)MR18= 0x77a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
7022 16:44:14.934711 CH1 RK1: MR19=C0C, MR18=77A7
7023 16:44:14.941273 CH1_RK1: MR19=0xC0C, MR18=0x77A7, DQSOSC=389, MR23=63, INC=390, DEC=260
7024 16:44:14.944530 [RxdqsGatingPostProcess] freq 400
7025 16:44:14.951293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7026 16:44:14.954877 best DQS0 dly(2T, 0.5T) = (0, 10)
7027 16:44:14.958277 best DQS1 dly(2T, 0.5T) = (0, 10)
7028 16:44:14.961429 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7029 16:44:14.964419 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7030 16:44:14.967482 best DQS0 dly(2T, 0.5T) = (0, 10)
7031 16:44:14.971107 best DQS1 dly(2T, 0.5T) = (0, 10)
7032 16:44:14.974055 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7033 16:44:14.977428 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7034 16:44:14.981012 Pre-setting of DQS Precalculation
7035 16:44:14.984251 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7036 16:44:14.991133 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7037 16:44:14.997259 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7038 16:44:14.997354
7039 16:44:14.997434
7040 16:44:15.000423 [Calibration Summary] 800 Mbps
7041 16:44:15.003989 CH 0, Rank 0
7042 16:44:15.004082 SW Impedance : PASS
7043 16:44:15.007379 DUTY Scan : NO K
7044 16:44:15.010453 ZQ Calibration : PASS
7045 16:44:15.010542 Jitter Meter : NO K
7046 16:44:15.014065 CBT Training : PASS
7047 16:44:15.017012 Write leveling : PASS
7048 16:44:15.017102 RX DQS gating : PASS
7049 16:44:15.020111 RX DQ/DQS(RDDQC) : PASS
7050 16:44:15.023968 TX DQ/DQS : PASS
7051 16:44:15.024057 RX DATLAT : PASS
7052 16:44:15.026954 RX DQ/DQS(Engine): PASS
7053 16:44:15.030425 TX OE : NO K
7054 16:44:15.030514 All Pass.
7055 16:44:15.030584
7056 16:44:15.030649 CH 0, Rank 1
7057 16:44:15.033611 SW Impedance : PASS
7058 16:44:15.036725 DUTY Scan : NO K
7059 16:44:15.036813 ZQ Calibration : PASS
7060 16:44:15.039812 Jitter Meter : NO K
7061 16:44:15.043377 CBT Training : PASS
7062 16:44:15.043464 Write leveling : NO K
7063 16:44:15.046597 RX DQS gating : PASS
7064 16:44:15.050131 RX DQ/DQS(RDDQC) : PASS
7065 16:44:15.050218 TX DQ/DQS : PASS
7066 16:44:15.053209 RX DATLAT : PASS
7067 16:44:15.053296 RX DQ/DQS(Engine): PASS
7068 16:44:15.056906 TX OE : NO K
7069 16:44:15.056994 All Pass.
7070 16:44:15.057063
7071 16:44:15.059600 CH 1, Rank 0
7072 16:44:15.063256 SW Impedance : PASS
7073 16:44:15.063343 DUTY Scan : NO K
7074 16:44:15.066398 ZQ Calibration : PASS
7075 16:44:15.069579 Jitter Meter : NO K
7076 16:44:15.069681 CBT Training : PASS
7077 16:44:15.073100 Write leveling : PASS
7078 16:44:15.073187 RX DQS gating : PASS
7079 16:44:15.076292 RX DQ/DQS(RDDQC) : PASS
7080 16:44:15.079172 TX DQ/DQS : PASS
7081 16:44:15.079278 RX DATLAT : PASS
7082 16:44:15.082665 RX DQ/DQS(Engine): PASS
7083 16:44:15.086180 TX OE : NO K
7084 16:44:15.086297 All Pass.
7085 16:44:15.086407
7086 16:44:15.086505 CH 1, Rank 1
7087 16:44:15.089241 SW Impedance : PASS
7088 16:44:15.092671 DUTY Scan : NO K
7089 16:44:15.092771 ZQ Calibration : PASS
7090 16:44:15.095681 Jitter Meter : NO K
7091 16:44:15.099204 CBT Training : PASS
7092 16:44:15.099332 Write leveling : NO K
7093 16:44:15.102071 RX DQS gating : PASS
7094 16:44:15.105540 RX DQ/DQS(RDDQC) : PASS
7095 16:44:15.105656 TX DQ/DQS : PASS
7096 16:44:15.108809 RX DATLAT : PASS
7097 16:44:15.112395 RX DQ/DQS(Engine): PASS
7098 16:44:15.112492 TX OE : NO K
7099 16:44:15.115279 All Pass.
7100 16:44:15.115370
7101 16:44:15.115478 DramC Write-DBI off
7102 16:44:15.119010 PER_BANK_REFRESH: Hybrid Mode
7103 16:44:15.119104 TX_TRACKING: ON
7104 16:44:15.129027 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7105 16:44:15.131855 [FAST_K] Save calibration result to emmc
7106 16:44:15.135614 dramc_set_vcore_voltage set vcore to 725000
7107 16:44:15.138813 Read voltage for 1600, 0
7108 16:44:15.138901 Vio18 = 0
7109 16:44:15.141838 Vcore = 725000
7110 16:44:15.141926 Vdram = 0
7111 16:44:15.142018 Vddq = 0
7112 16:44:15.145341 Vmddr = 0
7113 16:44:15.148507 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7114 16:44:15.155336 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7115 16:44:15.155430 MEM_TYPE=3, freq_sel=13
7116 16:44:15.158309 sv_algorithm_assistance_LP4_3733
7117 16:44:15.164641 ============ PULL DRAM RESETB DOWN ============
7118 16:44:15.168434 ========== PULL DRAM RESETB DOWN end =========
7119 16:44:15.171599 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7120 16:44:15.175043 ===================================
7121 16:44:15.178309 LPDDR4 DRAM CONFIGURATION
7122 16:44:15.181259 ===================================
7123 16:44:15.184440 EX_ROW_EN[0] = 0x0
7124 16:44:15.184582 EX_ROW_EN[1] = 0x0
7125 16:44:15.187848 LP4Y_EN = 0x0
7126 16:44:15.187988 WORK_FSP = 0x1
7127 16:44:15.191621 WL = 0x5
7128 16:44:15.191761 RL = 0x5
7129 16:44:15.194324 BL = 0x2
7130 16:44:15.194462 RPST = 0x0
7131 16:44:15.197949 RD_PRE = 0x0
7132 16:44:15.198041 WR_PRE = 0x1
7133 16:44:15.201038 WR_PST = 0x1
7134 16:44:15.201126 DBI_WR = 0x0
7135 16:44:15.204635 DBI_RD = 0x0
7136 16:44:15.207526 OTF = 0x1
7137 16:44:15.210948 ===================================
7138 16:44:15.214170 ===================================
7139 16:44:15.214261 ANA top config
7140 16:44:15.217756 ===================================
7141 16:44:15.221104 DLL_ASYNC_EN = 0
7142 16:44:15.223975 ALL_SLAVE_EN = 0
7143 16:44:15.224070 NEW_RANK_MODE = 1
7144 16:44:15.227242 DLL_IDLE_MODE = 1
7145 16:44:15.230964 LP45_APHY_COMB_EN = 1
7146 16:44:15.233972 TX_ODT_DIS = 0
7147 16:44:15.234100 NEW_8X_MODE = 1
7148 16:44:15.237433 ===================================
7149 16:44:15.240597 ===================================
7150 16:44:15.244182 data_rate = 3200
7151 16:44:15.247254 CKR = 1
7152 16:44:15.250804 DQ_P2S_RATIO = 8
7153 16:44:15.253844 ===================================
7154 16:44:15.257640 CA_P2S_RATIO = 8
7155 16:44:15.260751 DQ_CA_OPEN = 0
7156 16:44:15.260838 DQ_SEMI_OPEN = 0
7157 16:44:15.263782 CA_SEMI_OPEN = 0
7158 16:44:15.267281 CA_FULL_RATE = 0
7159 16:44:15.270617 DQ_CKDIV4_EN = 0
7160 16:44:15.273822 CA_CKDIV4_EN = 0
7161 16:44:15.276903 CA_PREDIV_EN = 0
7162 16:44:15.280668 PH8_DLY = 12
7163 16:44:15.280747 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7164 16:44:15.283783 DQ_AAMCK_DIV = 4
7165 16:44:15.286830 CA_AAMCK_DIV = 4
7166 16:44:15.290404 CA_ADMCK_DIV = 4
7167 16:44:15.293264 DQ_TRACK_CA_EN = 0
7168 16:44:15.296793 CA_PICK = 1600
7169 16:44:15.300261 CA_MCKIO = 1600
7170 16:44:15.300360 MCKIO_SEMI = 0
7171 16:44:15.303127 PLL_FREQ = 3068
7172 16:44:15.306683 DQ_UI_PI_RATIO = 32
7173 16:44:15.310227 CA_UI_PI_RATIO = 0
7174 16:44:15.313112 ===================================
7175 16:44:15.316595 ===================================
7176 16:44:15.319666 memory_type:LPDDR4
7177 16:44:15.319783 GP_NUM : 10
7178 16:44:15.323339 SRAM_EN : 1
7179 16:44:15.326321 MD32_EN : 0
7180 16:44:15.329891 ===================================
7181 16:44:15.330001 [ANA_INIT] >>>>>>>>>>>>>>
7182 16:44:15.333151 <<<<<< [CONFIGURE PHASE]: ANA_TX
7183 16:44:15.336446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7184 16:44:15.339525 ===================================
7185 16:44:15.342965 data_rate = 3200,PCW = 0X7600
7186 16:44:15.346505 ===================================
7187 16:44:15.349500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7188 16:44:15.356153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7189 16:44:15.359249 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7190 16:44:15.365792 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7191 16:44:15.369310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7192 16:44:15.372180 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7193 16:44:15.375815 [ANA_INIT] flow start
7194 16:44:15.375911 [ANA_INIT] PLL >>>>>>>>
7195 16:44:15.378980 [ANA_INIT] PLL <<<<<<<<
7196 16:44:15.382048 [ANA_INIT] MIDPI >>>>>>>>
7197 16:44:15.382163 [ANA_INIT] MIDPI <<<<<<<<
7198 16:44:15.385269 [ANA_INIT] DLL >>>>>>>>
7199 16:44:15.389078 [ANA_INIT] DLL <<<<<<<<
7200 16:44:15.389193 [ANA_INIT] flow end
7201 16:44:15.395502 ============ LP4 DIFF to SE enter ============
7202 16:44:15.398668 ============ LP4 DIFF to SE exit ============
7203 16:44:15.401938 [ANA_INIT] <<<<<<<<<<<<<
7204 16:44:15.405609 [Flow] Enable top DCM control >>>>>
7205 16:44:15.408877 [Flow] Enable top DCM control <<<<<
7206 16:44:15.408994 Enable DLL master slave shuffle
7207 16:44:15.415329 ==============================================================
7208 16:44:15.418729 Gating Mode config
7209 16:44:15.421687 ==============================================================
7210 16:44:15.424940 Config description:
7211 16:44:15.435197 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7212 16:44:15.441814 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7213 16:44:15.444836 SELPH_MODE 0: By rank 1: By Phase
7214 16:44:15.451493 ==============================================================
7215 16:44:15.454450 GAT_TRACK_EN = 1
7216 16:44:15.458167 RX_GATING_MODE = 2
7217 16:44:15.461306 RX_GATING_TRACK_MODE = 2
7218 16:44:15.464497 SELPH_MODE = 1
7219 16:44:15.468067 PICG_EARLY_EN = 1
7220 16:44:15.468155 VALID_LAT_VALUE = 1
7221 16:44:15.474824 ==============================================================
7222 16:44:15.477707 Enter into Gating configuration >>>>
7223 16:44:15.481491 Exit from Gating configuration <<<<
7224 16:44:15.484584 Enter into DVFS_PRE_config >>>>>
7225 16:44:15.494622 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7226 16:44:15.497657 Exit from DVFS_PRE_config <<<<<
7227 16:44:15.501331 Enter into PICG configuration >>>>
7228 16:44:15.504300 Exit from PICG configuration <<<<
7229 16:44:15.507671 [RX_INPUT] configuration >>>>>
7230 16:44:15.510700 [RX_INPUT] configuration <<<<<
7231 16:44:15.517470 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7232 16:44:15.520763 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7233 16:44:15.527281 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 16:44:15.533520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 16:44:15.540201 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7236 16:44:15.547301 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7237 16:44:15.550205 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7238 16:44:15.553362 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7239 16:44:15.557227 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7240 16:44:15.563120 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7241 16:44:15.567116 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7242 16:44:15.570013 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7243 16:44:15.573616 ===================================
7244 16:44:15.576742 LPDDR4 DRAM CONFIGURATION
7245 16:44:15.579938 ===================================
7246 16:44:15.583411 EX_ROW_EN[0] = 0x0
7247 16:44:15.583523 EX_ROW_EN[1] = 0x0
7248 16:44:15.586554 LP4Y_EN = 0x0
7249 16:44:15.586666 WORK_FSP = 0x1
7250 16:44:15.589722 WL = 0x5
7251 16:44:15.589833 RL = 0x5
7252 16:44:15.593220 BL = 0x2
7253 16:44:15.593327 RPST = 0x0
7254 16:44:15.596308 RD_PRE = 0x0
7255 16:44:15.596419 WR_PRE = 0x1
7256 16:44:15.599892 WR_PST = 0x1
7257 16:44:15.600006 DBI_WR = 0x0
7258 16:44:15.603148 DBI_RD = 0x0
7259 16:44:15.603254 OTF = 0x1
7260 16:44:15.606602 ===================================
7261 16:44:15.612642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7262 16:44:15.616107 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7263 16:44:15.619748 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7264 16:44:15.622867 ===================================
7265 16:44:15.626187 LPDDR4 DRAM CONFIGURATION
7266 16:44:15.629360 ===================================
7267 16:44:15.632972 EX_ROW_EN[0] = 0x10
7268 16:44:15.633082 EX_ROW_EN[1] = 0x0
7269 16:44:15.635962 LP4Y_EN = 0x0
7270 16:44:15.636043 WORK_FSP = 0x1
7271 16:44:15.639569 WL = 0x5
7272 16:44:15.639657 RL = 0x5
7273 16:44:15.642739 BL = 0x2
7274 16:44:15.642826 RPST = 0x0
7275 16:44:15.645744 RD_PRE = 0x0
7276 16:44:15.645832 WR_PRE = 0x1
7277 16:44:15.649237 WR_PST = 0x1
7278 16:44:15.649325 DBI_WR = 0x0
7279 16:44:15.652646 DBI_RD = 0x0
7280 16:44:15.655796 OTF = 0x1
7281 16:44:15.658892 ===================================
7282 16:44:15.662332 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7283 16:44:15.662426 ==
7284 16:44:15.665876 Dram Type= 6, Freq= 0, CH_0, rank 0
7285 16:44:15.672238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7286 16:44:15.672338 ==
7287 16:44:15.672409 [Duty_Offset_Calibration]
7288 16:44:15.675815 B0:2 B1:0 CA:3
7289 16:44:15.675897
7290 16:44:15.678775 [DutyScan_Calibration_Flow] k_type=0
7291 16:44:15.688495
7292 16:44:15.688612 ==CLK 0==
7293 16:44:15.692134 Final CLK duty delay cell = 0
7294 16:44:15.695301 [0] MAX Duty = 5031%(X100), DQS PI = 12
7295 16:44:15.698232 [0] MIN Duty = 4907%(X100), DQS PI = 6
7296 16:44:15.698321 [0] AVG Duty = 4969%(X100)
7297 16:44:15.701943
7298 16:44:15.705062 CH0 CLK Duty spec in!! Max-Min= 124%
7299 16:44:15.708105 [DutyScan_Calibration_Flow] ====Done====
7300 16:44:15.708192
7301 16:44:15.711694 [DutyScan_Calibration_Flow] k_type=1
7302 16:44:15.728951
7303 16:44:15.729083 ==DQS 0 ==
7304 16:44:15.731763 Final DQS duty delay cell = 0
7305 16:44:15.735079 [0] MAX Duty = 5094%(X100), DQS PI = 14
7306 16:44:15.738506 [0] MIN Duty = 4906%(X100), DQS PI = 46
7307 16:44:15.741563 [0] AVG Duty = 5000%(X100)
7308 16:44:15.741650
7309 16:44:15.741721 ==DQS 1 ==
7310 16:44:15.745336 Final DQS duty delay cell = 0
7311 16:44:15.748376 [0] MAX Duty = 5156%(X100), DQS PI = 32
7312 16:44:15.751359 [0] MIN Duty = 5031%(X100), DQS PI = 12
7313 16:44:15.754843 [0] AVG Duty = 5093%(X100)
7314 16:44:15.754976
7315 16:44:15.758052 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7316 16:44:15.758141
7317 16:44:15.761240 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7318 16:44:15.764732 [DutyScan_Calibration_Flow] ====Done====
7319 16:44:15.764813
7320 16:44:15.768221 [DutyScan_Calibration_Flow] k_type=3
7321 16:44:15.786324
7322 16:44:15.786433 ==DQM 0 ==
7323 16:44:15.789852 Final DQM duty delay cell = 0
7324 16:44:15.792843 [0] MAX Duty = 5156%(X100), DQS PI = 30
7325 16:44:15.796532 [0] MIN Duty = 4875%(X100), DQS PI = 0
7326 16:44:15.799541 [0] AVG Duty = 5015%(X100)
7327 16:44:15.799676
7328 16:44:15.799743 ==DQM 1 ==
7329 16:44:15.802758 Final DQM duty delay cell = 4
7330 16:44:15.806233 [4] MAX Duty = 5187%(X100), DQS PI = 62
7331 16:44:15.809396 [4] MIN Duty = 5031%(X100), DQS PI = 14
7332 16:44:15.813154 [4] AVG Duty = 5109%(X100)
7333 16:44:15.813241
7334 16:44:15.816289 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7335 16:44:15.816376
7336 16:44:15.819419 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7337 16:44:15.822420 [DutyScan_Calibration_Flow] ====Done====
7338 16:44:15.822505
7339 16:44:15.825792 [DutyScan_Calibration_Flow] k_type=2
7340 16:44:15.843139
7341 16:44:15.843316 ==DQ 0 ==
7342 16:44:15.846360 Final DQ duty delay cell = -4
7343 16:44:15.849478 [-4] MAX Duty = 5031%(X100), DQS PI = 28
7344 16:44:15.852570 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7345 16:44:15.856431 [-4] AVG Duty = 4953%(X100)
7346 16:44:15.856520
7347 16:44:15.856587 ==DQ 1 ==
7348 16:44:15.859300 Final DQ duty delay cell = 0
7349 16:44:15.862726 [0] MAX Duty = 5156%(X100), DQS PI = 58
7350 16:44:15.865954 [0] MIN Duty = 5000%(X100), DQS PI = 16
7351 16:44:15.869002 [0] AVG Duty = 5078%(X100)
7352 16:44:15.869083
7353 16:44:15.872681 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7354 16:44:15.872760
7355 16:44:15.875734 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7356 16:44:15.878807 [DutyScan_Calibration_Flow] ====Done====
7357 16:44:15.878892 ==
7358 16:44:15.882234 Dram Type= 6, Freq= 0, CH_1, rank 0
7359 16:44:15.885263 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7360 16:44:15.885377 ==
7361 16:44:15.888790 [Duty_Offset_Calibration]
7362 16:44:15.888874 B0:1 B1:-2 CA:0
7363 16:44:15.891873
7364 16:44:15.895043 [DutyScan_Calibration_Flow] k_type=0
7365 16:44:15.903529
7366 16:44:15.903638 ==CLK 0==
7367 16:44:15.906623 Final CLK duty delay cell = 0
7368 16:44:15.910484 [0] MAX Duty = 5031%(X100), DQS PI = 50
7369 16:44:15.913555 [0] MIN Duty = 4876%(X100), DQS PI = 26
7370 16:44:15.916470 [0] AVG Duty = 4953%(X100)
7371 16:44:15.916555
7372 16:44:15.920129 CH1 CLK Duty spec in!! Max-Min= 155%
7373 16:44:15.923162 [DutyScan_Calibration_Flow] ====Done====
7374 16:44:15.923247
7375 16:44:15.926204 [DutyScan_Calibration_Flow] k_type=1
7376 16:44:15.942582
7377 16:44:15.942741 ==DQS 0 ==
7378 16:44:15.945529 Final DQS duty delay cell = -4
7379 16:44:15.948853 [-4] MAX Duty = 4969%(X100), DQS PI = 58
7380 16:44:15.952310 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7381 16:44:15.955332 [-4] AVG Duty = 4906%(X100)
7382 16:44:15.955412
7383 16:44:15.955478 ==DQS 1 ==
7384 16:44:15.958610 Final DQS duty delay cell = 0
7385 16:44:15.962350 [0] MAX Duty = 5124%(X100), DQS PI = 28
7386 16:44:15.965382 [0] MIN Duty = 4813%(X100), DQS PI = 58
7387 16:44:15.968733 [0] AVG Duty = 4968%(X100)
7388 16:44:15.968820
7389 16:44:15.972291 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7390 16:44:15.972404
7391 16:44:15.975147 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7392 16:44:15.978639 [DutyScan_Calibration_Flow] ====Done====
7393 16:44:15.978751
7394 16:44:15.981771 [DutyScan_Calibration_Flow] k_type=3
7395 16:44:15.999552
7396 16:44:15.999681 ==DQM 0 ==
7397 16:44:16.003136 Final DQM duty delay cell = 0
7398 16:44:16.006403 [0] MAX Duty = 5031%(X100), DQS PI = 58
7399 16:44:16.009474 [0] MIN Duty = 4844%(X100), DQS PI = 22
7400 16:44:16.012587 [0] AVG Duty = 4937%(X100)
7401 16:44:16.012675
7402 16:44:16.012743 ==DQM 1 ==
7403 16:44:16.016308 Final DQM duty delay cell = 0
7404 16:44:16.019482 [0] MAX Duty = 5062%(X100), DQS PI = 2
7405 16:44:16.022609 [0] MIN Duty = 4875%(X100), DQS PI = 56
7406 16:44:16.026223 [0] AVG Duty = 4968%(X100)
7407 16:44:16.026309
7408 16:44:16.029131 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7409 16:44:16.029215
7410 16:44:16.032892 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7411 16:44:16.035921 [DutyScan_Calibration_Flow] ====Done====
7412 16:44:16.036008
7413 16:44:16.038846 [DutyScan_Calibration_Flow] k_type=2
7414 16:44:16.056675
7415 16:44:16.056786 ==DQ 0 ==
7416 16:44:16.059661 Final DQ duty delay cell = 0
7417 16:44:16.063363 [0] MAX Duty = 5062%(X100), DQS PI = 0
7418 16:44:16.066536 [0] MIN Duty = 4938%(X100), DQS PI = 28
7419 16:44:16.066626 [0] AVG Duty = 5000%(X100)
7420 16:44:16.069527
7421 16:44:16.069615 ==DQ 1 ==
7422 16:44:16.073007 Final DQ duty delay cell = 0
7423 16:44:16.076765 [0] MAX Duty = 5156%(X100), DQS PI = 4
7424 16:44:16.079725 [0] MIN Duty = 4938%(X100), DQS PI = 56
7425 16:44:16.079813 [0] AVG Duty = 5047%(X100)
7426 16:44:16.079883
7427 16:44:16.083265 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7428 16:44:16.086537
7429 16:44:16.089238 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7430 16:44:16.092653 [DutyScan_Calibration_Flow] ====Done====
7431 16:44:16.096251 nWR fixed to 30
7432 16:44:16.096341 [ModeRegInit_LP4] CH0 RK0
7433 16:44:16.099263 [ModeRegInit_LP4] CH0 RK1
7434 16:44:16.102983 [ModeRegInit_LP4] CH1 RK0
7435 16:44:16.106224 [ModeRegInit_LP4] CH1 RK1
7436 16:44:16.106315 match AC timing 5
7437 16:44:16.112740 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7438 16:44:16.116105 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7439 16:44:16.119000 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7440 16:44:16.125885 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7441 16:44:16.128841 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7442 16:44:16.128959 [MiockJmeterHQA]
7443 16:44:16.129082
7444 16:44:16.132625 [DramcMiockJmeter] u1RxGatingPI = 0
7445 16:44:16.135504 0 : 4363, 4137
7446 16:44:16.135629 4 : 4255, 4029
7447 16:44:16.139335 8 : 4363, 4137
7448 16:44:16.139441 12 : 4252, 4027
7449 16:44:16.142276 16 : 4252, 4027
7450 16:44:16.142390 20 : 4363, 4138
7451 16:44:16.142489 24 : 4363, 4137
7452 16:44:16.145402 28 : 4252, 4027
7453 16:44:16.145492 32 : 4252, 4027
7454 16:44:16.148827 36 : 4250, 4026
7455 16:44:16.148916 40 : 4363, 4138
7456 16:44:16.152344 44 : 4250, 4027
7457 16:44:16.152435 48 : 4361, 4137
7458 16:44:16.155184 52 : 4253, 4027
7459 16:44:16.155273 56 : 4250, 4027
7460 16:44:16.155343 60 : 4250, 4027
7461 16:44:16.158622 64 : 4252, 4029
7462 16:44:16.158711 68 : 4360, 4138
7463 16:44:16.162220 72 : 4250, 4027
7464 16:44:16.162309 76 : 4361, 4137
7465 16:44:16.164985 80 : 4250, 4027
7466 16:44:16.165074 84 : 4250, 4026
7467 16:44:16.168710 88 : 4250, 4027
7468 16:44:16.168799 92 : 4360, 4138
7469 16:44:16.168870 96 : 4250, 4027
7470 16:44:16.171938 100 : 4360, 4138
7471 16:44:16.172027 104 : 4360, 3962
7472 16:44:16.175428 108 : 4248, 7
7473 16:44:16.175517 112 : 4250, 0
7474 16:44:16.178369 116 : 4250, 0
7475 16:44:16.178463 120 : 4252, 0
7476 16:44:16.178534 124 : 4250, 0
7477 16:44:16.181507 128 : 4250, 0
7478 16:44:16.181595 132 : 4250, 0
7479 16:44:16.181666 136 : 4361, 0
7480 16:44:16.185165 140 : 4361, 0
7481 16:44:16.185254 144 : 4360, 0
7482 16:44:16.188114 148 : 4250, 0
7483 16:44:16.188204 152 : 4250, 0
7484 16:44:16.188275 156 : 4361, 0
7485 16:44:16.191560 160 : 4250, 0
7486 16:44:16.191657 164 : 4252, 0
7487 16:44:16.194695 168 : 4250, 0
7488 16:44:16.194785 172 : 4250, 0
7489 16:44:16.194862 176 : 4250, 0
7490 16:44:16.198079 180 : 4250, 0
7491 16:44:16.198167 184 : 4250, 0
7492 16:44:16.201497 188 : 4250, 0
7493 16:44:16.201589 192 : 4361, 0
7494 16:44:16.201661 196 : 4361, 0
7495 16:44:16.204999 200 : 4250, 0
7496 16:44:16.205092 204 : 4250, 0
7497 16:44:16.208105 208 : 4250, 0
7498 16:44:16.208194 212 : 4249, 0
7499 16:44:16.208265 216 : 4250, 0
7500 16:44:16.211548 220 : 4250, 0
7501 16:44:16.211646 224 : 4249, 0
7502 16:44:16.211717 228 : 4360, 0
7503 16:44:16.214525 232 : 4250, 1
7504 16:44:16.214614 236 : 4250, 1155
7505 16:44:16.218182 240 : 4250, 4026
7506 16:44:16.218270 244 : 4250, 4027
7507 16:44:16.221820 248 : 4360, 4138
7508 16:44:16.221923 252 : 4249, 4027
7509 16:44:16.224643 256 : 4250, 4026
7510 16:44:16.224737 260 : 4360, 4138
7511 16:44:16.227574 264 : 4360, 4138
7512 16:44:16.227674 268 : 4249, 4027
7513 16:44:16.231387 272 : 4361, 4137
7514 16:44:16.231467 276 : 4360, 4138
7515 16:44:16.234535 280 : 4250, 4027
7516 16:44:16.234661 284 : 4249, 4027
7517 16:44:16.234744 288 : 4250, 4027
7518 16:44:16.237630 292 : 4250, 4027
7519 16:44:16.237710 296 : 4250, 4027
7520 16:44:16.241254 300 : 4250, 4027
7521 16:44:16.241341 304 : 4250, 4027
7522 16:44:16.244215 308 : 4250, 4027
7523 16:44:16.244304 312 : 4249, 4027
7524 16:44:16.247980 316 : 4360, 4138
7525 16:44:16.248066 320 : 4249, 4027
7526 16:44:16.251085 324 : 4360, 4137
7527 16:44:16.251187 328 : 4360, 4138
7528 16:44:16.254008 332 : 4250, 4027
7529 16:44:16.254104 336 : 4250, 4027
7530 16:44:16.257488 340 : 4250, 4027
7531 16:44:16.257575 344 : 4250, 4026
7532 16:44:16.260927 348 : 4250, 4027
7533 16:44:16.261048 352 : 4250, 4012
7534 16:44:16.264376 356 : 4249, 3018
7535 16:44:16.264457 360 : 4250, 9
7536 16:44:16.264534
7537 16:44:16.267543 MIOCK jitter meter ch=0
7538 16:44:16.267642
7539 16:44:16.271090 1T = (360-108) = 252 dly cells
7540 16:44:16.274038 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7541 16:44:16.274121 ==
7542 16:44:16.277148 Dram Type= 6, Freq= 0, CH_0, rank 0
7543 16:44:16.283883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7544 16:44:16.283975 ==
7545 16:44:16.286947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7546 16:44:16.293487 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7547 16:44:16.297072 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7548 16:44:16.303349 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7549 16:44:16.311225 [CA 0] Center 43 (13~74) winsize 62
7550 16:44:16.314819 [CA 1] Center 43 (13~74) winsize 62
7551 16:44:16.317604 [CA 2] Center 39 (10~68) winsize 59
7552 16:44:16.320882 [CA 3] Center 39 (10~68) winsize 59
7553 16:44:16.324775 [CA 4] Center 36 (7~66) winsize 60
7554 16:44:16.327330 [CA 5] Center 36 (7~66) winsize 60
7555 16:44:16.327423
7556 16:44:16.331070 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7557 16:44:16.333919
7558 16:44:16.337556 [CATrainingPosCal] consider 1 rank data
7559 16:44:16.340566 u2DelayCellTimex100 = 258/100 ps
7560 16:44:16.344304 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7561 16:44:16.347534 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7562 16:44:16.350218 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7563 16:44:16.353708 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7564 16:44:16.356929 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7565 16:44:16.360511 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7566 16:44:16.360645
7567 16:44:16.367124 CA PerBit enable=1, Macro0, CA PI delay=36
7568 16:44:16.367290
7569 16:44:16.367412 [CBTSetCACLKResult] CA Dly = 36
7570 16:44:16.370164 CS Dly: 11 (0~42)
7571 16:44:16.373686 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7572 16:44:16.377145 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7573 16:44:16.380179 ==
7574 16:44:16.383294 Dram Type= 6, Freq= 0, CH_0, rank 1
7575 16:44:16.386831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7576 16:44:16.386972 ==
7577 16:44:16.393202 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7578 16:44:16.396898 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7579 16:44:16.400201 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7580 16:44:16.407117 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7581 16:44:16.415334 [CA 0] Center 43 (13~74) winsize 62
7582 16:44:16.418229 [CA 1] Center 43 (13~74) winsize 62
7583 16:44:16.421640 [CA 2] Center 39 (10~68) winsize 59
7584 16:44:16.425057 [CA 3] Center 39 (10~68) winsize 59
7585 16:44:16.428478 [CA 4] Center 36 (6~66) winsize 61
7586 16:44:16.431575 [CA 5] Center 36 (6~66) winsize 61
7587 16:44:16.431762
7588 16:44:16.435193 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7589 16:44:16.435365
7590 16:44:16.441824 [CATrainingPosCal] consider 2 rank data
7591 16:44:16.442020 u2DelayCellTimex100 = 258/100 ps
7592 16:44:16.448146 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7593 16:44:16.451252 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7594 16:44:16.455063 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7595 16:44:16.458209 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7596 16:44:16.461147 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7597 16:44:16.464451 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7598 16:44:16.464628
7599 16:44:16.467995 CA PerBit enable=1, Macro0, CA PI delay=36
7600 16:44:16.468162
7601 16:44:16.471216 [CBTSetCACLKResult] CA Dly = 36
7602 16:44:16.474299 CS Dly: 11 (0~43)
7603 16:44:16.477798 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7604 16:44:16.481156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7605 16:44:16.481328
7606 16:44:16.487463 ----->DramcWriteLeveling(PI) begin...
7607 16:44:16.487684 ==
7608 16:44:16.491101 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 16:44:16.494274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 16:44:16.494417 ==
7611 16:44:16.497462 Write leveling (Byte 0): 34 => 34
7612 16:44:16.500539 Write leveling (Byte 1): 29 => 29
7613 16:44:16.504038 DramcWriteLeveling(PI) end<-----
7614 16:44:16.504182
7615 16:44:16.504310 ==
7616 16:44:16.507672 Dram Type= 6, Freq= 0, CH_0, rank 0
7617 16:44:16.510751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7618 16:44:16.510896 ==
7619 16:44:16.513866 [Gating] SW mode calibration
7620 16:44:16.520758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7621 16:44:16.526882 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7622 16:44:16.530306 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 16:44:16.533989 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 16:44:16.540271 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 16:44:16.543585 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 16:44:16.546874 1 4 16 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7627 16:44:16.553164 1 4 20 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
7628 16:44:16.556847 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7629 16:44:16.560003 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 16:44:16.566255 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 16:44:16.569726 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 16:44:16.573207 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 16:44:16.580029 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7634 16:44:16.582902 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7635 16:44:16.586032 1 5 20 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
7636 16:44:16.592827 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
7637 16:44:16.596374 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 16:44:16.599413 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 16:44:16.606383 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 16:44:16.609137 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 16:44:16.612623 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7642 16:44:16.619566 1 6 16 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
7643 16:44:16.622555 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7644 16:44:16.625606 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 16:44:16.632333 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 16:44:16.635735 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 16:44:16.639233 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 16:44:16.645440 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 16:44:16.648970 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 16:44:16.652078 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7651 16:44:16.658806 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7652 16:44:16.662584 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7653 16:44:16.665748 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 16:44:16.672295 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 16:44:16.675551 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 16:44:16.678672 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 16:44:16.685395 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 16:44:16.688375 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 16:44:16.691726 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 16:44:16.698514 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 16:44:16.701875 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 16:44:16.704855 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 16:44:16.711516 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 16:44:16.714983 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 16:44:16.717993 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7666 16:44:16.724956 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7667 16:44:16.727987 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7668 16:44:16.731704 Total UI for P1: 0, mck2ui 16
7669 16:44:16.734686 best dqsien dly found for B0: ( 1, 9, 14)
7670 16:44:16.737968 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7671 16:44:16.744323 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7672 16:44:16.744482 Total UI for P1: 0, mck2ui 16
7673 16:44:16.751114 best dqsien dly found for B1: ( 1, 9, 22)
7674 16:44:16.754370 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7675 16:44:16.757572 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7676 16:44:16.757723
7677 16:44:16.761315 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7678 16:44:16.764284 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7679 16:44:16.767490 [Gating] SW calibration Done
7680 16:44:16.767624 ==
7681 16:44:16.770638 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 16:44:16.774434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 16:44:16.774560 ==
7684 16:44:16.777664 RX Vref Scan: 0
7685 16:44:16.777779
7686 16:44:16.780645 RX Vref 0 -> 0, step: 1
7687 16:44:16.780756
7688 16:44:16.780866 RX Delay 0 -> 252, step: 8
7689 16:44:16.786834 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7690 16:44:16.790662 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7691 16:44:16.793445 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7692 16:44:16.797107 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7693 16:44:16.800562 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7694 16:44:16.806667 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7695 16:44:16.809953 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7696 16:44:16.813193 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7697 16:44:16.816936 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7698 16:44:16.822884 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7699 16:44:16.826662 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7700 16:44:16.829732 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7701 16:44:16.833365 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7702 16:44:16.836448 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7703 16:44:16.843276 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7704 16:44:16.846204 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7705 16:44:16.846311 ==
7706 16:44:16.849249 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 16:44:16.852942 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 16:44:16.853049 ==
7709 16:44:16.856440 DQS Delay:
7710 16:44:16.856545 DQS0 = 0, DQS1 = 0
7711 16:44:16.856619 DQM Delay:
7712 16:44:16.859328 DQM0 = 129, DQM1 = 124
7713 16:44:16.859409 DQ Delay:
7714 16:44:16.862883 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7715 16:44:16.866338 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =143
7716 16:44:16.872619 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7717 16:44:16.875689 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7718 16:44:16.875829
7719 16:44:16.875935
7720 16:44:16.876037 ==
7721 16:44:16.879455 Dram Type= 6, Freq= 0, CH_0, rank 0
7722 16:44:16.882634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7723 16:44:16.882728 ==
7724 16:44:16.882796
7725 16:44:16.882860
7726 16:44:16.885756 TX Vref Scan disable
7727 16:44:16.888903 == TX Byte 0 ==
7728 16:44:16.892504 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7729 16:44:16.895674 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7730 16:44:16.898769 == TX Byte 1 ==
7731 16:44:16.902565 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7732 16:44:16.905330 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7733 16:44:16.905461 ==
7734 16:44:16.908844 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 16:44:16.915489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 16:44:16.915655 ==
7737 16:44:16.927682
7738 16:44:16.930592 TX Vref early break, caculate TX vref
7739 16:44:16.933744 TX Vref=16, minBit 4, minWin=21, winSum=356
7740 16:44:16.936812 TX Vref=18, minBit 9, minWin=22, winSum=369
7741 16:44:16.940350 TX Vref=20, minBit 11, minWin=22, winSum=376
7742 16:44:16.943571 TX Vref=22, minBit 7, minWin=23, winSum=387
7743 16:44:16.946708 TX Vref=24, minBit 4, minWin=24, winSum=395
7744 16:44:16.953536 TX Vref=26, minBit 8, minWin=24, winSum=405
7745 16:44:16.956747 TX Vref=28, minBit 4, minWin=24, winSum=405
7746 16:44:16.959782 TX Vref=30, minBit 0, minWin=24, winSum=397
7747 16:44:16.963137 TX Vref=32, minBit 0, minWin=23, winSum=388
7748 16:44:16.966521 TX Vref=34, minBit 6, minWin=23, winSum=382
7749 16:44:16.973183 [TxChooseVref] Worse bit 8, Min win 24, Win sum 405, Final Vref 26
7750 16:44:16.973313
7751 16:44:16.976848 Final TX Range 0 Vref 26
7752 16:44:16.976976
7753 16:44:16.977081 ==
7754 16:44:16.979871 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 16:44:16.982889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 16:44:16.982971 ==
7757 16:44:16.983039
7758 16:44:16.986239
7759 16:44:16.986337 TX Vref Scan disable
7760 16:44:16.992945 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7761 16:44:16.993058 == TX Byte 0 ==
7762 16:44:16.996559 u2DelayCellOfst[0]=15 cells (4 PI)
7763 16:44:16.999778 u2DelayCellOfst[1]=18 cells (5 PI)
7764 16:44:17.002839 u2DelayCellOfst[2]=11 cells (3 PI)
7765 16:44:17.005828 u2DelayCellOfst[3]=15 cells (4 PI)
7766 16:44:17.009774 u2DelayCellOfst[4]=11 cells (3 PI)
7767 16:44:17.012547 u2DelayCellOfst[5]=0 cells (0 PI)
7768 16:44:17.015952 u2DelayCellOfst[6]=22 cells (6 PI)
7769 16:44:17.019193 u2DelayCellOfst[7]=22 cells (6 PI)
7770 16:44:17.022290 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7771 16:44:17.025519 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7772 16:44:17.029016 == TX Byte 1 ==
7773 16:44:17.032558 u2DelayCellOfst[8]=0 cells (0 PI)
7774 16:44:17.035469 u2DelayCellOfst[9]=0 cells (0 PI)
7775 16:44:17.038987 u2DelayCellOfst[10]=7 cells (2 PI)
7776 16:44:17.041930 u2DelayCellOfst[11]=7 cells (2 PI)
7777 16:44:17.045571 u2DelayCellOfst[12]=15 cells (4 PI)
7778 16:44:17.048736 u2DelayCellOfst[13]=11 cells (3 PI)
7779 16:44:17.052008 u2DelayCellOfst[14]=15 cells (4 PI)
7780 16:44:17.052101 u2DelayCellOfst[15]=11 cells (3 PI)
7781 16:44:17.058692 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7782 16:44:17.061842 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7783 16:44:17.065427 DramC Write-DBI on
7784 16:44:17.065538 ==
7785 16:44:17.068663 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 16:44:17.072140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 16:44:17.072234 ==
7788 16:44:17.072306
7789 16:44:17.072369
7790 16:44:17.074941 TX Vref Scan disable
7791 16:44:17.075052 == TX Byte 0 ==
7792 16:44:17.081723 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7793 16:44:17.081841 == TX Byte 1 ==
7794 16:44:17.088546 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7795 16:44:17.088666 DramC Write-DBI off
7796 16:44:17.088769
7797 16:44:17.088864 [DATLAT]
7798 16:44:17.091706 Freq=1600, CH0 RK0
7799 16:44:17.091788
7800 16:44:17.091855 DATLAT Default: 0xf
7801 16:44:17.094771 0, 0xFFFF, sum = 0
7802 16:44:17.098306 1, 0xFFFF, sum = 0
7803 16:44:17.098425 2, 0xFFFF, sum = 0
7804 16:44:17.101164 3, 0xFFFF, sum = 0
7805 16:44:17.101287 4, 0xFFFF, sum = 0
7806 16:44:17.104989 5, 0xFFFF, sum = 0
7807 16:44:17.105087 6, 0xFFFF, sum = 0
7808 16:44:17.108109 7, 0xFFFF, sum = 0
7809 16:44:17.108206 8, 0xFFFF, sum = 0
7810 16:44:17.111163 9, 0xFFFF, sum = 0
7811 16:44:17.111267 10, 0xFFFF, sum = 0
7812 16:44:17.114295 11, 0xFFFF, sum = 0
7813 16:44:17.114431 12, 0xFFFF, sum = 0
7814 16:44:17.117893 13, 0xFFFF, sum = 0
7815 16:44:17.117996 14, 0x0, sum = 1
7816 16:44:17.121069 15, 0x0, sum = 2
7817 16:44:17.121168 16, 0x0, sum = 3
7818 16:44:17.124629 17, 0x0, sum = 4
7819 16:44:17.124776 best_step = 15
7820 16:44:17.124896
7821 16:44:17.124999 ==
7822 16:44:17.127439 Dram Type= 6, Freq= 0, CH_0, rank 0
7823 16:44:17.133987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7824 16:44:17.134119 ==
7825 16:44:17.134217 RX Vref Scan: 1
7826 16:44:17.134285
7827 16:44:17.137689 Set Vref Range= 24 -> 127
7828 16:44:17.137797
7829 16:44:17.141041 RX Vref 24 -> 127, step: 1
7830 16:44:17.141148
7831 16:44:17.144040 RX Delay 11 -> 252, step: 4
7832 16:44:17.144169
7833 16:44:17.147894 Set Vref, RX VrefLevel [Byte0]: 24
7834 16:44:17.150759 [Byte1]: 24
7835 16:44:17.150868
7836 16:44:17.153944 Set Vref, RX VrefLevel [Byte0]: 25
7837 16:44:17.157122 [Byte1]: 25
7838 16:44:17.157252
7839 16:44:17.160817 Set Vref, RX VrefLevel [Byte0]: 26
7840 16:44:17.163687 [Byte1]: 26
7841 16:44:17.167386
7842 16:44:17.167551 Set Vref, RX VrefLevel [Byte0]: 27
7843 16:44:17.170575 [Byte1]: 27
7844 16:44:17.174995
7845 16:44:17.175121 Set Vref, RX VrefLevel [Byte0]: 28
7846 16:44:17.178013 [Byte1]: 28
7847 16:44:17.182247
7848 16:44:17.182396 Set Vref, RX VrefLevel [Byte0]: 29
7849 16:44:17.185922 [Byte1]: 29
7850 16:44:17.190011
7851 16:44:17.190125 Set Vref, RX VrefLevel [Byte0]: 30
7852 16:44:17.193008 [Byte1]: 30
7853 16:44:17.197444
7854 16:44:17.197535 Set Vref, RX VrefLevel [Byte0]: 31
7855 16:44:17.200739 [Byte1]: 31
7856 16:44:17.205359
7857 16:44:17.205491 Set Vref, RX VrefLevel [Byte0]: 32
7858 16:44:17.208319 [Byte1]: 32
7859 16:44:17.212807
7860 16:44:17.212910 Set Vref, RX VrefLevel [Byte0]: 33
7861 16:44:17.215933 [Byte1]: 33
7862 16:44:17.220179
7863 16:44:17.220286 Set Vref, RX VrefLevel [Byte0]: 34
7864 16:44:17.223571 [Byte1]: 34
7865 16:44:17.227810
7866 16:44:17.227915 Set Vref, RX VrefLevel [Byte0]: 35
7867 16:44:17.231462 [Byte1]: 35
7868 16:44:17.236090
7869 16:44:17.236202 Set Vref, RX VrefLevel [Byte0]: 36
7870 16:44:17.239007 [Byte1]: 36
7871 16:44:17.243004
7872 16:44:17.246849 Set Vref, RX VrefLevel [Byte0]: 37
7873 16:44:17.249709 [Byte1]: 37
7874 16:44:17.249812
7875 16:44:17.253158 Set Vref, RX VrefLevel [Byte0]: 38
7876 16:44:17.256384 [Byte1]: 38
7877 16:44:17.256483
7878 16:44:17.259997 Set Vref, RX VrefLevel [Byte0]: 39
7879 16:44:17.263037 [Byte1]: 39
7880 16:44:17.266263
7881 16:44:17.266365 Set Vref, RX VrefLevel [Byte0]: 40
7882 16:44:17.269755 [Byte1]: 40
7883 16:44:17.273852
7884 16:44:17.273961 Set Vref, RX VrefLevel [Byte0]: 41
7885 16:44:17.276840 [Byte1]: 41
7886 16:44:17.281207
7887 16:44:17.281319 Set Vref, RX VrefLevel [Byte0]: 42
7888 16:44:17.284738 [Byte1]: 42
7889 16:44:17.288989
7890 16:44:17.289094 Set Vref, RX VrefLevel [Byte0]: 43
7891 16:44:17.292523 [Byte1]: 43
7892 16:44:17.296370
7893 16:44:17.296474 Set Vref, RX VrefLevel [Byte0]: 44
7894 16:44:17.299861 [Byte1]: 44
7895 16:44:17.304368
7896 16:44:17.304484 Set Vref, RX VrefLevel [Byte0]: 45
7897 16:44:17.307381 [Byte1]: 45
7898 16:44:17.311740
7899 16:44:17.311831 Set Vref, RX VrefLevel [Byte0]: 46
7900 16:44:17.315033 [Byte1]: 46
7901 16:44:17.319171
7902 16:44:17.319255 Set Vref, RX VrefLevel [Byte0]: 47
7903 16:44:17.322848 [Byte1]: 47
7904 16:44:17.326935
7905 16:44:17.327031 Set Vref, RX VrefLevel [Byte0]: 48
7906 16:44:17.330133 [Byte1]: 48
7907 16:44:17.334465
7908 16:44:17.334590 Set Vref, RX VrefLevel [Byte0]: 49
7909 16:44:17.337924 [Byte1]: 49
7910 16:44:17.341907
7911 16:44:17.345560 Set Vref, RX VrefLevel [Byte0]: 50
7912 16:44:17.345691 [Byte1]: 50
7913 16:44:17.349868
7914 16:44:17.349965 Set Vref, RX VrefLevel [Byte0]: 51
7915 16:44:17.353154 [Byte1]: 51
7916 16:44:17.357738
7917 16:44:17.357861 Set Vref, RX VrefLevel [Byte0]: 52
7918 16:44:17.360798 [Byte1]: 52
7919 16:44:17.365036
7920 16:44:17.365140 Set Vref, RX VrefLevel [Byte0]: 53
7921 16:44:17.368538 [Byte1]: 53
7922 16:44:17.372988
7923 16:44:17.373099 Set Vref, RX VrefLevel [Byte0]: 54
7924 16:44:17.376107 [Byte1]: 54
7925 16:44:17.380451
7926 16:44:17.380550 Set Vref, RX VrefLevel [Byte0]: 55
7927 16:44:17.383504 [Byte1]: 55
7928 16:44:17.387815
7929 16:44:17.387947 Set Vref, RX VrefLevel [Byte0]: 56
7930 16:44:17.391655 [Byte1]: 56
7931 16:44:17.395871
7932 16:44:17.395997 Set Vref, RX VrefLevel [Byte0]: 57
7933 16:44:17.399061 [Byte1]: 57
7934 16:44:17.403370
7935 16:44:17.403511 Set Vref, RX VrefLevel [Byte0]: 58
7936 16:44:17.406350 [Byte1]: 58
7937 16:44:17.410601
7938 16:44:17.410719 Set Vref, RX VrefLevel [Byte0]: 59
7939 16:44:17.414198 [Byte1]: 59
7940 16:44:17.418651
7941 16:44:17.418773 Set Vref, RX VrefLevel [Byte0]: 60
7942 16:44:17.421974 [Byte1]: 60
7943 16:44:17.426200
7944 16:44:17.426298 Set Vref, RX VrefLevel [Byte0]: 61
7945 16:44:17.429526 [Byte1]: 61
7946 16:44:17.433647
7947 16:44:17.433769 Set Vref, RX VrefLevel [Byte0]: 62
7948 16:44:17.436777 [Byte1]: 62
7949 16:44:17.441606
7950 16:44:17.441698 Set Vref, RX VrefLevel [Byte0]: 63
7951 16:44:17.444395 [Byte1]: 63
7952 16:44:17.449080
7953 16:44:17.449203 Set Vref, RX VrefLevel [Byte0]: 64
7954 16:44:17.451940 [Byte1]: 64
7955 16:44:17.456496
7956 16:44:17.456594 Set Vref, RX VrefLevel [Byte0]: 65
7957 16:44:17.459682 [Byte1]: 65
7958 16:44:17.464128
7959 16:44:17.464235 Set Vref, RX VrefLevel [Byte0]: 66
7960 16:44:17.467518 [Byte1]: 66
7961 16:44:17.471814
7962 16:44:17.471960 Set Vref, RX VrefLevel [Byte0]: 67
7963 16:44:17.474781 [Byte1]: 67
7964 16:44:17.479240
7965 16:44:17.479356 Set Vref, RX VrefLevel [Byte0]: 68
7966 16:44:17.482805 [Byte1]: 68
7967 16:44:17.487078
7968 16:44:17.487185 Set Vref, RX VrefLevel [Byte0]: 69
7969 16:44:17.490201 [Byte1]: 69
7970 16:44:17.494704
7971 16:44:17.494810 Set Vref, RX VrefLevel [Byte0]: 70
7972 16:44:17.497878 [Byte1]: 70
7973 16:44:17.502572
7974 16:44:17.502719 Set Vref, RX VrefLevel [Byte0]: 71
7975 16:44:17.505178 [Byte1]: 71
7976 16:44:17.509862
7977 16:44:17.509999 Set Vref, RX VrefLevel [Byte0]: 72
7978 16:44:17.512986 [Byte1]: 72
7979 16:44:17.517244
7980 16:44:17.517377 Set Vref, RX VrefLevel [Byte0]: 73
7981 16:44:17.520505 [Byte1]: 73
7982 16:44:17.524767
7983 16:44:17.524880 Set Vref, RX VrefLevel [Byte0]: 74
7984 16:44:17.528278 [Byte1]: 74
7985 16:44:17.532678
7986 16:44:17.532789 Set Vref, RX VrefLevel [Byte0]: 75
7987 16:44:17.535701 [Byte1]: 75
7988 16:44:17.539867
7989 16:44:17.543531 Set Vref, RX VrefLevel [Byte0]: 76
7990 16:44:17.543665 [Byte1]: 76
7991 16:44:17.547994
7992 16:44:17.548099 Final RX Vref Byte 0 = 64 to rank0
7993 16:44:17.550928 Final RX Vref Byte 1 = 60 to rank0
7994 16:44:17.554381 Final RX Vref Byte 0 = 64 to rank1
7995 16:44:17.557661 Final RX Vref Byte 1 = 60 to rank1==
7996 16:44:17.561123 Dram Type= 6, Freq= 0, CH_0, rank 0
7997 16:44:17.567352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7998 16:44:17.567500 ==
7999 16:44:17.567616 DQS Delay:
8000 16:44:17.570789 DQS0 = 0, DQS1 = 0
8001 16:44:17.570880 DQM Delay:
8002 16:44:17.570974 DQM0 = 126, DQM1 = 120
8003 16:44:17.574359 DQ Delay:
8004 16:44:17.577283 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8005 16:44:17.580460 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =138
8006 16:44:17.584076 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8007 16:44:17.587200 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8008 16:44:17.587328
8009 16:44:17.587434
8010 16:44:17.587534
8011 16:44:17.590709 [DramC_TX_OE_Calibration] TA2
8012 16:44:17.594097 Original DQ_B0 (3 6) =30, OEN = 27
8013 16:44:17.597208 Original DQ_B1 (3 6) =30, OEN = 27
8014 16:44:17.600228 24, 0x0, End_B0=24 End_B1=24
8015 16:44:17.604302 25, 0x0, End_B0=25 End_B1=25
8016 16:44:17.604438 26, 0x0, End_B0=26 End_B1=26
8017 16:44:17.606607 27, 0x0, End_B0=27 End_B1=27
8018 16:44:17.610243 28, 0x0, End_B0=28 End_B1=28
8019 16:44:17.613260 29, 0x0, End_B0=29 End_B1=29
8020 16:44:17.616944 30, 0x0, End_B0=30 End_B1=30
8021 16:44:17.617057 31, 0x5151, End_B0=30 End_B1=30
8022 16:44:17.619835 Byte0 end_step=30 best_step=27
8023 16:44:17.623605 Byte1 end_step=30 best_step=27
8024 16:44:17.626766 Byte0 TX OE(2T, 0.5T) = (3, 3)
8025 16:44:17.629923 Byte1 TX OE(2T, 0.5T) = (3, 3)
8026 16:44:17.630011
8027 16:44:17.630081
8028 16:44:17.636756 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8029 16:44:17.639916 CH0 RK0: MR19=303, MR18=1515
8030 16:44:17.646467 CH0_RK0: MR19=0x303, MR18=0x1515, DQSOSC=399, MR23=63, INC=23, DEC=15
8031 16:44:17.646566
8032 16:44:17.649710 ----->DramcWriteLeveling(PI) begin...
8033 16:44:17.649802 ==
8034 16:44:17.652889 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 16:44:17.656482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 16:44:17.659453 ==
8037 16:44:17.659596 Write leveling (Byte 0): 34 => 34
8038 16:44:17.662819 Write leveling (Byte 1): 27 => 27
8039 16:44:17.666058 DramcWriteLeveling(PI) end<-----
8040 16:44:17.666151
8041 16:44:17.666221 ==
8042 16:44:17.669482 Dram Type= 6, Freq= 0, CH_0, rank 1
8043 16:44:17.675602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8044 16:44:17.675719 ==
8045 16:44:17.678644 [Gating] SW mode calibration
8046 16:44:17.685644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8047 16:44:17.689047 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8048 16:44:17.695195 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8049 16:44:17.698788 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8050 16:44:17.701919 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8051 16:44:17.708630 1 4 12 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8052 16:44:17.711954 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
8053 16:44:17.715457 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8054 16:44:17.721473 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8055 16:44:17.724980 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8056 16:44:17.728150 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 16:44:17.734744 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 16:44:17.737913 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8059 16:44:17.741640 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8060 16:44:17.748084 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8061 16:44:17.751424 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8062 16:44:17.754305 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8063 16:44:17.760737 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8064 16:44:17.764431 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 16:44:17.767586 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 16:44:17.774194 1 6 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8067 16:44:17.777207 1 6 12 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
8068 16:44:17.780562 1 6 16 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
8069 16:44:17.787619 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 16:44:17.791020 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 16:44:17.793820 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 16:44:17.800535 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 16:44:17.803612 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 16:44:17.807352 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8075 16:44:17.813505 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8076 16:44:17.816950 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8077 16:44:17.820574 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8078 16:44:17.826816 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 16:44:17.830532 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 16:44:17.833607 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 16:44:17.840455 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 16:44:17.843382 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 16:44:17.846498 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 16:44:17.853061 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 16:44:17.856644 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 16:44:17.859806 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 16:44:17.866752 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 16:44:17.869796 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 16:44:17.872984 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 16:44:17.879512 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8091 16:44:17.882814 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8092 16:44:17.886289 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8093 16:44:17.889732 Total UI for P1: 0, mck2ui 16
8094 16:44:17.893106 best dqsien dly found for B0: ( 1, 9, 10)
8095 16:44:17.899201 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 16:44:17.902712 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 16:44:17.906386 Total UI for P1: 0, mck2ui 16
8098 16:44:17.909404 best dqsien dly found for B1: ( 1, 9, 18)
8099 16:44:17.912568 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8100 16:44:17.916333 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8101 16:44:17.916450
8102 16:44:17.919395 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8103 16:44:17.925825 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8104 16:44:17.925965 [Gating] SW calibration Done
8105 16:44:17.926038 ==
8106 16:44:17.929042 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 16:44:17.935971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 16:44:17.936099 ==
8109 16:44:17.936178 RX Vref Scan: 0
8110 16:44:17.936243
8111 16:44:17.938990 RX Vref 0 -> 0, step: 1
8112 16:44:17.939082
8113 16:44:17.942544 RX Delay 0 -> 252, step: 8
8114 16:44:17.945587 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8115 16:44:17.948701 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8116 16:44:17.952655 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8117 16:44:17.958563 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8118 16:44:17.962226 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8119 16:44:17.965453 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8120 16:44:17.968569 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8121 16:44:17.972066 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8122 16:44:17.978873 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8123 16:44:17.981974 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8124 16:44:17.985052 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8125 16:44:17.988501 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8126 16:44:17.992008 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8127 16:44:17.998065 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8128 16:44:18.002171 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8129 16:44:18.004909 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8130 16:44:18.005018 ==
8131 16:44:18.008216 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 16:44:18.011728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 16:44:18.014982 ==
8134 16:44:18.015094 DQS Delay:
8135 16:44:18.015168 DQS0 = 0, DQS1 = 0
8136 16:44:18.017874 DQM Delay:
8137 16:44:18.017968 DQM0 = 127, DQM1 = 122
8138 16:44:18.021526 DQ Delay:
8139 16:44:18.024651 DQ0 =127, DQ1 =127, DQ2 =123, DQ3 =123
8140 16:44:18.027781 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8141 16:44:18.031263 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8142 16:44:18.034675 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8143 16:44:18.034774
8144 16:44:18.034844
8145 16:44:18.034909 ==
8146 16:44:18.038138 Dram Type= 6, Freq= 0, CH_0, rank 1
8147 16:44:18.041494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8148 16:44:18.041591 ==
8149 16:44:18.044814
8150 16:44:18.044909
8151 16:44:18.044978 TX Vref Scan disable
8152 16:44:18.047876 == TX Byte 0 ==
8153 16:44:18.050969 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8154 16:44:18.054698 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8155 16:44:18.057821 == TX Byte 1 ==
8156 16:44:18.061214 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8157 16:44:18.064357 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8158 16:44:18.064460 ==
8159 16:44:18.067948 Dram Type= 6, Freq= 0, CH_0, rank 1
8160 16:44:18.074213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8161 16:44:18.074309 ==
8162 16:44:18.088007
8163 16:44:18.091190 TX Vref early break, caculate TX vref
8164 16:44:18.094709 TX Vref=16, minBit 8, minWin=21, winSum=365
8165 16:44:18.097890 TX Vref=18, minBit 0, minWin=22, winSum=370
8166 16:44:18.101540 TX Vref=20, minBit 8, minWin=22, winSum=380
8167 16:44:18.104875 TX Vref=22, minBit 1, minWin=23, winSum=388
8168 16:44:18.107606 TX Vref=24, minBit 8, minWin=23, winSum=394
8169 16:44:18.114404 TX Vref=26, minBit 9, minWin=24, winSum=406
8170 16:44:18.117982 TX Vref=28, minBit 8, minWin=24, winSum=406
8171 16:44:18.121434 TX Vref=30, minBit 8, minWin=24, winSum=409
8172 16:44:18.124171 TX Vref=32, minBit 8, minWin=23, winSum=399
8173 16:44:18.127759 TX Vref=34, minBit 8, minWin=22, winSum=390
8174 16:44:18.133961 TX Vref=36, minBit 8, minWin=21, winSum=380
8175 16:44:18.137440 [TxChooseVref] Worse bit 8, Min win 24, Win sum 409, Final Vref 30
8176 16:44:18.137532
8177 16:44:18.141001 Final TX Range 0 Vref 30
8178 16:44:18.141087
8179 16:44:18.141154 ==
8180 16:44:18.143898 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 16:44:18.147344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 16:44:18.150766 ==
8183 16:44:18.150860
8184 16:44:18.150929
8185 16:44:18.150994 TX Vref Scan disable
8186 16:44:18.157490 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8187 16:44:18.157584 == TX Byte 0 ==
8188 16:44:18.160729 u2DelayCellOfst[0]=15 cells (4 PI)
8189 16:44:18.163805 u2DelayCellOfst[1]=15 cells (4 PI)
8190 16:44:18.167314 u2DelayCellOfst[2]=11 cells (3 PI)
8191 16:44:18.170577 u2DelayCellOfst[3]=11 cells (3 PI)
8192 16:44:18.174059 u2DelayCellOfst[4]=7 cells (2 PI)
8193 16:44:18.177102 u2DelayCellOfst[5]=0 cells (0 PI)
8194 16:44:18.180316 u2DelayCellOfst[6]=18 cells (5 PI)
8195 16:44:18.183629 u2DelayCellOfst[7]=15 cells (4 PI)
8196 16:44:18.187194 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8197 16:44:18.190388 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8198 16:44:18.193521 == TX Byte 1 ==
8199 16:44:18.197145 u2DelayCellOfst[8]=0 cells (0 PI)
8200 16:44:18.200072 u2DelayCellOfst[9]=3 cells (1 PI)
8201 16:44:18.203338 u2DelayCellOfst[10]=7 cells (2 PI)
8202 16:44:18.206952 u2DelayCellOfst[11]=7 cells (2 PI)
8203 16:44:18.210117 u2DelayCellOfst[12]=15 cells (4 PI)
8204 16:44:18.213513 u2DelayCellOfst[13]=11 cells (3 PI)
8205 16:44:18.216550 u2DelayCellOfst[14]=15 cells (4 PI)
8206 16:44:18.220079 u2DelayCellOfst[15]=15 cells (4 PI)
8207 16:44:18.223282 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8208 16:44:18.226679 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8209 16:44:18.229856 DramC Write-DBI on
8210 16:44:18.229969 ==
8211 16:44:18.233272 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 16:44:18.236295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 16:44:18.236413 ==
8214 16:44:18.236522
8215 16:44:18.236590
8216 16:44:18.240001 TX Vref Scan disable
8217 16:44:18.242911 == TX Byte 0 ==
8218 16:44:18.246184 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8219 16:44:18.246284 == TX Byte 1 ==
8220 16:44:18.252909 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8221 16:44:18.253046 DramC Write-DBI off
8222 16:44:18.253148
8223 16:44:18.253244 [DATLAT]
8224 16:44:18.255920 Freq=1600, CH0 RK1
8225 16:44:18.256014
8226 16:44:18.259293 DATLAT Default: 0xf
8227 16:44:18.259413 0, 0xFFFF, sum = 0
8228 16:44:18.262521 1, 0xFFFF, sum = 0
8229 16:44:18.262623 2, 0xFFFF, sum = 0
8230 16:44:18.266365 3, 0xFFFF, sum = 0
8231 16:44:18.266486 4, 0xFFFF, sum = 0
8232 16:44:18.269103 5, 0xFFFF, sum = 0
8233 16:44:18.269196 6, 0xFFFF, sum = 0
8234 16:44:18.272833 7, 0xFFFF, sum = 0
8235 16:44:18.272928 8, 0xFFFF, sum = 0
8236 16:44:18.276106 9, 0xFFFF, sum = 0
8237 16:44:18.276192 10, 0xFFFF, sum = 0
8238 16:44:18.279071 11, 0xFFFF, sum = 0
8239 16:44:18.279149 12, 0xFFFF, sum = 0
8240 16:44:18.282280 13, 0xCFFF, sum = 0
8241 16:44:18.282372 14, 0x0, sum = 1
8242 16:44:18.285969 15, 0x0, sum = 2
8243 16:44:18.286088 16, 0x0, sum = 3
8244 16:44:18.289305 17, 0x0, sum = 4
8245 16:44:18.289397 best_step = 15
8246 16:44:18.289466
8247 16:44:18.289530 ==
8248 16:44:18.292138 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 16:44:18.299147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 16:44:18.299254 ==
8251 16:44:18.299336 RX Vref Scan: 0
8252 16:44:18.299407
8253 16:44:18.302105 RX Vref 0 -> 0, step: 1
8254 16:44:18.302213
8255 16:44:18.305856 RX Delay 3 -> 252, step: 4
8256 16:44:18.309014 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8257 16:44:18.312102 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8258 16:44:18.318647 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8259 16:44:18.321918 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8260 16:44:18.325622 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8261 16:44:18.328844 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8262 16:44:18.332007 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8263 16:44:18.338320 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8264 16:44:18.342028 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8265 16:44:18.344899 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8266 16:44:18.348513 iDelay=191, Bit 10, Center 118 (63 ~ 174) 112
8267 16:44:18.351995 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8268 16:44:18.358155 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8269 16:44:18.361753 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8270 16:44:18.365099 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8271 16:44:18.368225 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8272 16:44:18.368315 ==
8273 16:44:18.371124 Dram Type= 6, Freq= 0, CH_0, rank 1
8274 16:44:18.377874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8275 16:44:18.377969 ==
8276 16:44:18.378042 DQS Delay:
8277 16:44:18.381495 DQS0 = 0, DQS1 = 0
8278 16:44:18.381616 DQM Delay:
8279 16:44:18.384584 DQM0 = 124, DQM1 = 117
8280 16:44:18.384704 DQ Delay:
8281 16:44:18.387746 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8282 16:44:18.391550 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8283 16:44:18.394490 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8284 16:44:18.397668 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8285 16:44:18.397782
8286 16:44:18.397886
8287 16:44:18.397982
8288 16:44:18.401250 [DramC_TX_OE_Calibration] TA2
8289 16:44:18.404370 Original DQ_B0 (3 6) =30, OEN = 27
8290 16:44:18.407995 Original DQ_B1 (3 6) =30, OEN = 27
8291 16:44:18.411128 24, 0x0, End_B0=24 End_B1=24
8292 16:44:18.414079 25, 0x0, End_B0=25 End_B1=25
8293 16:44:18.414202 26, 0x0, End_B0=26 End_B1=26
8294 16:44:18.417198 27, 0x0, End_B0=27 End_B1=27
8295 16:44:18.420954 28, 0x0, End_B0=28 End_B1=28
8296 16:44:18.424007 29, 0x0, End_B0=29 End_B1=29
8297 16:44:18.427098 30, 0x0, End_B0=30 End_B1=30
8298 16:44:18.427188 31, 0x4141, End_B0=30 End_B1=30
8299 16:44:18.430873 Byte0 end_step=30 best_step=27
8300 16:44:18.433947 Byte1 end_step=30 best_step=27
8301 16:44:18.437289 Byte0 TX OE(2T, 0.5T) = (3, 3)
8302 16:44:18.440991 Byte1 TX OE(2T, 0.5T) = (3, 3)
8303 16:44:18.441105
8304 16:44:18.441213
8305 16:44:18.447085 [DQSOSCAuto] RK1, (LSB)MR18= 0x2311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
8306 16:44:18.450639 CH0 RK1: MR19=303, MR18=2311
8307 16:44:18.456890 CH0_RK1: MR19=0x303, MR18=0x2311, DQSOSC=392, MR23=63, INC=24, DEC=16
8308 16:44:18.460222 [RxdqsGatingPostProcess] freq 1600
8309 16:44:18.467141 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8310 16:44:18.470239 best DQS0 dly(2T, 0.5T) = (1, 1)
8311 16:44:18.470375 best DQS1 dly(2T, 0.5T) = (1, 1)
8312 16:44:18.473426 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8313 16:44:18.476593 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8314 16:44:18.479980 best DQS0 dly(2T, 0.5T) = (1, 1)
8315 16:44:18.483780 best DQS1 dly(2T, 0.5T) = (1, 1)
8316 16:44:18.486927 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8317 16:44:18.490102 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8318 16:44:18.493331 Pre-setting of DQS Precalculation
8319 16:44:18.496326 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8320 16:44:18.500066 ==
8321 16:44:18.503075 Dram Type= 6, Freq= 0, CH_1, rank 0
8322 16:44:18.506146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8323 16:44:18.506241 ==
8324 16:44:18.513090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8325 16:44:18.516000 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8326 16:44:18.519765 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8327 16:44:18.525909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8328 16:44:18.534842 [CA 0] Center 42 (13~71) winsize 59
8329 16:44:18.537717 [CA 1] Center 42 (13~72) winsize 60
8330 16:44:18.541661 [CA 2] Center 38 (9~67) winsize 59
8331 16:44:18.544723 [CA 3] Center 37 (8~67) winsize 60
8332 16:44:18.547600 [CA 4] Center 38 (9~67) winsize 59
8333 16:44:18.551074 [CA 5] Center 36 (7~66) winsize 60
8334 16:44:18.551163
8335 16:44:18.554613 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8336 16:44:18.554707
8337 16:44:18.557881 [CATrainingPosCal] consider 1 rank data
8338 16:44:18.560869 u2DelayCellTimex100 = 258/100 ps
8339 16:44:18.567531 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8340 16:44:18.571075 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8341 16:44:18.573975 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8342 16:44:18.577467 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
8343 16:44:18.581078 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8344 16:44:18.584020 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8345 16:44:18.584109
8346 16:44:18.587143 CA PerBit enable=1, Macro0, CA PI delay=36
8347 16:44:18.587253
8348 16:44:18.590968 [CBTSetCACLKResult] CA Dly = 36
8349 16:44:18.594113 CS Dly: 9 (0~40)
8350 16:44:18.597086 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8351 16:44:18.600670 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8352 16:44:18.600756 ==
8353 16:44:18.603584 Dram Type= 6, Freq= 0, CH_1, rank 1
8354 16:44:18.610490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 16:44:18.610592 ==
8356 16:44:18.613532 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8357 16:44:18.620064 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8358 16:44:18.623789 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8359 16:44:18.629943 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8360 16:44:18.637944 [CA 0] Center 41 (12~71) winsize 60
8361 16:44:18.640868 [CA 1] Center 42 (12~72) winsize 61
8362 16:44:18.644474 [CA 2] Center 37 (8~67) winsize 60
8363 16:44:18.647699 [CA 3] Center 36 (7~66) winsize 60
8364 16:44:18.650772 [CA 4] Center 37 (8~67) winsize 60
8365 16:44:18.653901 [CA 5] Center 36 (6~66) winsize 61
8366 16:44:18.653992
8367 16:44:18.657264 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8368 16:44:18.657346
8369 16:44:18.664139 [CATrainingPosCal] consider 2 rank data
8370 16:44:18.664238 u2DelayCellTimex100 = 258/100 ps
8371 16:44:18.670358 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8372 16:44:18.674030 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8373 16:44:18.677100 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8374 16:44:18.680225 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8375 16:44:18.683616 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8376 16:44:18.686953 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8377 16:44:18.687063
8378 16:44:18.690654 CA PerBit enable=1, Macro0, CA PI delay=36
8379 16:44:18.690746
8380 16:44:18.693533 [CBTSetCACLKResult] CA Dly = 36
8381 16:44:18.696679 CS Dly: 10 (0~43)
8382 16:44:18.699848 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8383 16:44:18.703427 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8384 16:44:18.703536
8385 16:44:18.706486 ----->DramcWriteLeveling(PI) begin...
8386 16:44:18.706602 ==
8387 16:44:18.710124 Dram Type= 6, Freq= 0, CH_1, rank 0
8388 16:44:18.716899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8389 16:44:18.716987 ==
8390 16:44:18.719944 Write leveling (Byte 0): 26 => 26
8391 16:44:18.723449 Write leveling (Byte 1): 29 => 29
8392 16:44:18.726733 DramcWriteLeveling(PI) end<-----
8393 16:44:18.726847
8394 16:44:18.726939 ==
8395 16:44:18.729673 Dram Type= 6, Freq= 0, CH_1, rank 0
8396 16:44:18.732689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8397 16:44:18.732795 ==
8398 16:44:18.736570 [Gating] SW mode calibration
8399 16:44:18.742700 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8400 16:44:18.749296 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8401 16:44:18.752876 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 16:44:18.755924 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 16:44:18.762474 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 16:44:18.766295 1 4 12 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
8405 16:44:18.769319 1 4 16 | B1->B0 | 3232 3434 | 1 0 | (1 1) (0 0)
8406 16:44:18.775735 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8407 16:44:18.778963 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 16:44:18.782526 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 16:44:18.788969 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 16:44:18.792431 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 16:44:18.795985 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 16:44:18.802378 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 16:44:18.805426 1 5 16 | B1->B0 | 2c2c 2525 | 0 0 | (1 0) (1 0)
8414 16:44:18.809181 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8415 16:44:18.815272 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 16:44:18.819021 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 16:44:18.821962 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 16:44:18.828497 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 16:44:18.832057 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 16:44:18.834938 1 6 12 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
8421 16:44:18.841572 1 6 16 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
8422 16:44:18.845023 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 16:44:18.848006 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 16:44:18.855046 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 16:44:18.858232 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 16:44:18.861248 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 16:44:18.867971 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 16:44:18.871161 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 16:44:18.874726 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8430 16:44:18.880982 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 16:44:18.884475 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 16:44:18.888029 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 16:44:18.894345 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 16:44:18.897899 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 16:44:18.901336 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 16:44:18.907599 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 16:44:18.910674 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 16:44:18.914256 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 16:44:18.921108 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 16:44:18.924138 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 16:44:18.927278 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 16:44:18.934309 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 16:44:18.937520 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 16:44:18.940518 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8445 16:44:18.947259 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8446 16:44:18.950796 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8447 16:44:18.953755 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 16:44:18.957320 Total UI for P1: 0, mck2ui 16
8449 16:44:18.960321 best dqsien dly found for B0: ( 1, 9, 16)
8450 16:44:18.963424 Total UI for P1: 0, mck2ui 16
8451 16:44:18.966689 best dqsien dly found for B1: ( 1, 9, 18)
8452 16:44:18.970235 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8453 16:44:18.973309 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8454 16:44:18.973401
8455 16:44:18.979895 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8456 16:44:18.983511 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8457 16:44:18.986929 [Gating] SW calibration Done
8458 16:44:18.987057 ==
8459 16:44:18.989850 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 16:44:18.993175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 16:44:18.993269 ==
8462 16:44:18.993335 RX Vref Scan: 0
8463 16:44:18.993397
8464 16:44:18.996221 RX Vref 0 -> 0, step: 1
8465 16:44:18.996299
8466 16:44:18.999752 RX Delay 0 -> 252, step: 8
8467 16:44:19.003177 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8468 16:44:19.006988 iDelay=208, Bit 1, Center 127 (64 ~ 191) 128
8469 16:44:19.012844 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8470 16:44:19.016615 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8471 16:44:19.019746 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8472 16:44:19.023245 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8473 16:44:19.026309 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8474 16:44:19.033013 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8475 16:44:19.036477 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8476 16:44:19.039505 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8477 16:44:19.042574 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8478 16:44:19.046272 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8479 16:44:19.053059 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8480 16:44:19.056002 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8481 16:44:19.059548 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8482 16:44:19.062711 iDelay=208, Bit 15, Center 131 (72 ~ 191) 120
8483 16:44:19.062806 ==
8484 16:44:19.065793 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 16:44:19.072460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 16:44:19.072577 ==
8487 16:44:19.072647 DQS Delay:
8488 16:44:19.075523 DQS0 = 0, DQS1 = 0
8489 16:44:19.075665 DQM Delay:
8490 16:44:19.079076 DQM0 = 133, DQM1 = 124
8491 16:44:19.079204 DQ Delay:
8492 16:44:19.082815 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =131
8493 16:44:19.085597 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8494 16:44:19.089009 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8495 16:44:19.092329 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =131
8496 16:44:19.092458
8497 16:44:19.092562
8498 16:44:19.092654 ==
8499 16:44:19.095552 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 16:44:19.102123 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 16:44:19.102263 ==
8502 16:44:19.102364
8503 16:44:19.102456
8504 16:44:19.102557 TX Vref Scan disable
8505 16:44:19.105549 == TX Byte 0 ==
8506 16:44:19.109217 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8507 16:44:19.115559 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8508 16:44:19.115699 == TX Byte 1 ==
8509 16:44:19.118596 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8510 16:44:19.125605 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8511 16:44:19.125745 ==
8512 16:44:19.128656 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 16:44:19.131758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 16:44:19.131890 ==
8515 16:44:19.144588
8516 16:44:19.147661 TX Vref early break, caculate TX vref
8517 16:44:19.150681 TX Vref=16, minBit 9, minWin=21, winSum=356
8518 16:44:19.154190 TX Vref=18, minBit 9, minWin=21, winSum=367
8519 16:44:19.157392 TX Vref=20, minBit 9, minWin=23, winSum=381
8520 16:44:19.160976 TX Vref=22, minBit 5, minWin=23, winSum=385
8521 16:44:19.163889 TX Vref=24, minBit 1, minWin=24, winSum=399
8522 16:44:19.170844 TX Vref=26, minBit 11, minWin=24, winSum=406
8523 16:44:19.174032 TX Vref=28, minBit 0, minWin=25, winSum=412
8524 16:44:19.177108 TX Vref=30, minBit 1, minWin=24, winSum=408
8525 16:44:19.180266 TX Vref=32, minBit 1, minWin=24, winSum=401
8526 16:44:19.184161 TX Vref=34, minBit 1, minWin=22, winSum=390
8527 16:44:19.190252 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 28
8528 16:44:19.190357
8529 16:44:19.193746 Final TX Range 0 Vref 28
8530 16:44:19.193870
8531 16:44:19.193978 ==
8532 16:44:19.196845 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 16:44:19.200293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 16:44:19.200422 ==
8535 16:44:19.200530
8536 16:44:19.200600
8537 16:44:19.203800 TX Vref Scan disable
8538 16:44:19.210533 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8539 16:44:19.210684 == TX Byte 0 ==
8540 16:44:19.213446 u2DelayCellOfst[0]=22 cells (6 PI)
8541 16:44:19.216502 u2DelayCellOfst[1]=15 cells (4 PI)
8542 16:44:19.220044 u2DelayCellOfst[2]=0 cells (0 PI)
8543 16:44:19.223163 u2DelayCellOfst[3]=11 cells (3 PI)
8544 16:44:19.226866 u2DelayCellOfst[4]=11 cells (3 PI)
8545 16:44:19.230151 u2DelayCellOfst[5]=22 cells (6 PI)
8546 16:44:19.233591 u2DelayCellOfst[6]=22 cells (6 PI)
8547 16:44:19.236337 u2DelayCellOfst[7]=7 cells (2 PI)
8548 16:44:19.239954 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8549 16:44:19.243034 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8550 16:44:19.246749 == TX Byte 1 ==
8551 16:44:19.249603 u2DelayCellOfst[8]=0 cells (0 PI)
8552 16:44:19.253287 u2DelayCellOfst[9]=7 cells (2 PI)
8553 16:44:19.256301 u2DelayCellOfst[10]=15 cells (4 PI)
8554 16:44:19.259462 u2DelayCellOfst[11]=11 cells (3 PI)
8555 16:44:19.263431 u2DelayCellOfst[12]=18 cells (5 PI)
8556 16:44:19.266217 u2DelayCellOfst[13]=22 cells (6 PI)
8557 16:44:19.266317 u2DelayCellOfst[14]=26 cells (7 PI)
8558 16:44:19.269263 u2DelayCellOfst[15]=22 cells (6 PI)
8559 16:44:19.276083 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8560 16:44:19.279177 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8561 16:44:19.282855 DramC Write-DBI on
8562 16:44:19.282962 ==
8563 16:44:19.285792 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 16:44:19.288916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 16:44:19.289006 ==
8566 16:44:19.289074
8567 16:44:19.289137
8568 16:44:19.292764 TX Vref Scan disable
8569 16:44:19.292884 == TX Byte 0 ==
8570 16:44:19.298908 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8571 16:44:19.299025 == TX Byte 1 ==
8572 16:44:19.302206 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8573 16:44:19.305780 DramC Write-DBI off
8574 16:44:19.305926
8575 16:44:19.306034 [DATLAT]
8576 16:44:19.309111 Freq=1600, CH1 RK0
8577 16:44:19.309214
8578 16:44:19.309293 DATLAT Default: 0xf
8579 16:44:19.312308 0, 0xFFFF, sum = 0
8580 16:44:19.315144 1, 0xFFFF, sum = 0
8581 16:44:19.315250 2, 0xFFFF, sum = 0
8582 16:44:19.318780 3, 0xFFFF, sum = 0
8583 16:44:19.318882 4, 0xFFFF, sum = 0
8584 16:44:19.322122 5, 0xFFFF, sum = 0
8585 16:44:19.322261 6, 0xFFFF, sum = 0
8586 16:44:19.325092 7, 0xFFFF, sum = 0
8587 16:44:19.325187 8, 0xFFFF, sum = 0
8588 16:44:19.328840 9, 0xFFFF, sum = 0
8589 16:44:19.328945 10, 0xFFFF, sum = 0
8590 16:44:19.331829 11, 0xFFFF, sum = 0
8591 16:44:19.331950 12, 0xFFFF, sum = 0
8592 16:44:19.335447 13, 0x8FFF, sum = 0
8593 16:44:19.335568 14, 0x0, sum = 1
8594 16:44:19.338443 15, 0x0, sum = 2
8595 16:44:19.338561 16, 0x0, sum = 3
8596 16:44:19.341917 17, 0x0, sum = 4
8597 16:44:19.342033 best_step = 15
8598 16:44:19.342139
8599 16:44:19.342243 ==
8600 16:44:19.345154 Dram Type= 6, Freq= 0, CH_1, rank 0
8601 16:44:19.351793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8602 16:44:19.351921 ==
8603 16:44:19.352037 RX Vref Scan: 1
8604 16:44:19.352143
8605 16:44:19.354710 Set Vref Range= 24 -> 127
8606 16:44:19.354817
8607 16:44:19.357824 RX Vref 24 -> 127, step: 1
8608 16:44:19.357942
8609 16:44:19.361477 RX Delay 11 -> 252, step: 4
8610 16:44:19.361603
8611 16:44:19.361712 Set Vref, RX VrefLevel [Byte0]: 24
8612 16:44:19.364458 [Byte1]: 24
8613 16:44:19.369114
8614 16:44:19.369204 Set Vref, RX VrefLevel [Byte0]: 25
8615 16:44:19.372714 [Byte1]: 25
8616 16:44:19.376993
8617 16:44:19.377086 Set Vref, RX VrefLevel [Byte0]: 26
8618 16:44:19.380035 [Byte1]: 26
8619 16:44:19.384369
8620 16:44:19.384471 Set Vref, RX VrefLevel [Byte0]: 27
8621 16:44:19.387369 [Byte1]: 27
8622 16:44:19.392239
8623 16:44:19.392371 Set Vref, RX VrefLevel [Byte0]: 28
8624 16:44:19.394966 [Byte1]: 28
8625 16:44:19.399364
8626 16:44:19.399461 Set Vref, RX VrefLevel [Byte0]: 29
8627 16:44:19.403100 [Byte1]: 29
8628 16:44:19.407237
8629 16:44:19.407381 Set Vref, RX VrefLevel [Byte0]: 30
8630 16:44:19.410783 [Byte1]: 30
8631 16:44:19.414810
8632 16:44:19.414903 Set Vref, RX VrefLevel [Byte0]: 31
8633 16:44:19.417802 [Byte1]: 31
8634 16:44:19.422579
8635 16:44:19.422672 Set Vref, RX VrefLevel [Byte0]: 32
8636 16:44:19.425538 [Byte1]: 32
8637 16:44:19.430067
8638 16:44:19.430165 Set Vref, RX VrefLevel [Byte0]: 33
8639 16:44:19.433105 [Byte1]: 33
8640 16:44:19.437455
8641 16:44:19.437550 Set Vref, RX VrefLevel [Byte0]: 34
8642 16:44:19.441244 [Byte1]: 34
8643 16:44:19.445558
8644 16:44:19.445657 Set Vref, RX VrefLevel [Byte0]: 35
8645 16:44:19.448473 [Byte1]: 35
8646 16:44:19.453158
8647 16:44:19.453251 Set Vref, RX VrefLevel [Byte0]: 36
8648 16:44:19.456285 [Byte1]: 36
8649 16:44:19.460445
8650 16:44:19.460541 Set Vref, RX VrefLevel [Byte0]: 37
8651 16:44:19.463495 [Byte1]: 37
8652 16:44:19.467899
8653 16:44:19.468001 Set Vref, RX VrefLevel [Byte0]: 38
8654 16:44:19.471025 [Byte1]: 38
8655 16:44:19.475898
8656 16:44:19.476006 Set Vref, RX VrefLevel [Byte0]: 39
8657 16:44:19.479079 [Byte1]: 39
8658 16:44:19.483513
8659 16:44:19.483657 Set Vref, RX VrefLevel [Byte0]: 40
8660 16:44:19.486725 [Byte1]: 40
8661 16:44:19.491202
8662 16:44:19.491296 Set Vref, RX VrefLevel [Byte0]: 41
8663 16:44:19.493958 [Byte1]: 41
8664 16:44:19.498267
8665 16:44:19.498381 Set Vref, RX VrefLevel [Byte0]: 42
8666 16:44:19.502067 [Byte1]: 42
8667 16:44:19.506244
8668 16:44:19.506384 Set Vref, RX VrefLevel [Byte0]: 43
8669 16:44:19.509473 [Byte1]: 43
8670 16:44:19.513532
8671 16:44:19.513661 Set Vref, RX VrefLevel [Byte0]: 44
8672 16:44:19.517173 [Byte1]: 44
8673 16:44:19.521729
8674 16:44:19.521862 Set Vref, RX VrefLevel [Byte0]: 45
8675 16:44:19.524823 [Byte1]: 45
8676 16:44:19.528857
8677 16:44:19.528969 Set Vref, RX VrefLevel [Byte0]: 46
8678 16:44:19.532282 [Byte1]: 46
8679 16:44:19.536414
8680 16:44:19.536552 Set Vref, RX VrefLevel [Byte0]: 47
8681 16:44:19.539891 [Byte1]: 47
8682 16:44:19.544590
8683 16:44:19.544690 Set Vref, RX VrefLevel [Byte0]: 48
8684 16:44:19.547626 [Byte1]: 48
8685 16:44:19.551689
8686 16:44:19.551784 Set Vref, RX VrefLevel [Byte0]: 49
8687 16:44:19.555114 [Byte1]: 49
8688 16:44:19.559474
8689 16:44:19.559575 Set Vref, RX VrefLevel [Byte0]: 50
8690 16:44:19.562944 [Byte1]: 50
8691 16:44:19.566762
8692 16:44:19.566893 Set Vref, RX VrefLevel [Byte0]: 51
8693 16:44:19.570264 [Byte1]: 51
8694 16:44:19.574849
8695 16:44:19.574956 Set Vref, RX VrefLevel [Byte0]: 52
8696 16:44:19.577841 [Byte1]: 52
8697 16:44:19.582075
8698 16:44:19.582173 Set Vref, RX VrefLevel [Byte0]: 53
8699 16:44:19.585337 [Byte1]: 53
8700 16:44:19.589553
8701 16:44:19.589666 Set Vref, RX VrefLevel [Byte0]: 54
8702 16:44:19.593294 [Byte1]: 54
8703 16:44:19.597590
8704 16:44:19.597693 Set Vref, RX VrefLevel [Byte0]: 55
8705 16:44:19.600796 [Byte1]: 55
8706 16:44:19.605129
8707 16:44:19.605264 Set Vref, RX VrefLevel [Byte0]: 56
8708 16:44:19.608145 [Byte1]: 56
8709 16:44:19.612729
8710 16:44:19.612866 Set Vref, RX VrefLevel [Byte0]: 57
8711 16:44:19.615814 [Byte1]: 57
8712 16:44:19.620186
8713 16:44:19.620318 Set Vref, RX VrefLevel [Byte0]: 58
8714 16:44:19.623616 [Byte1]: 58
8715 16:44:19.628208
8716 16:44:19.628314 Set Vref, RX VrefLevel [Byte0]: 59
8717 16:44:19.631273 [Byte1]: 59
8718 16:44:19.635723
8719 16:44:19.635826 Set Vref, RX VrefLevel [Byte0]: 60
8720 16:44:19.638802 [Byte1]: 60
8721 16:44:19.643495
8722 16:44:19.643623 Set Vref, RX VrefLevel [Byte0]: 61
8723 16:44:19.646289 [Byte1]: 61
8724 16:44:19.650410
8725 16:44:19.650506 Set Vref, RX VrefLevel [Byte0]: 62
8726 16:44:19.657527 [Byte1]: 62
8727 16:44:19.657667
8728 16:44:19.660206 Set Vref, RX VrefLevel [Byte0]: 63
8729 16:44:19.663871 [Byte1]: 63
8730 16:44:19.663984
8731 16:44:19.666840 Set Vref, RX VrefLevel [Byte0]: 64
8732 16:44:19.670448 [Byte1]: 64
8733 16:44:19.673655
8734 16:44:19.673750 Set Vref, RX VrefLevel [Byte0]: 65
8735 16:44:19.676892 [Byte1]: 65
8736 16:44:19.681216
8737 16:44:19.681313 Set Vref, RX VrefLevel [Byte0]: 66
8738 16:44:19.684183 [Byte1]: 66
8739 16:44:19.689022
8740 16:44:19.689133 Set Vref, RX VrefLevel [Byte0]: 67
8741 16:44:19.691903 [Byte1]: 67
8742 16:44:19.696207
8743 16:44:19.696301 Set Vref, RX VrefLevel [Byte0]: 68
8744 16:44:19.699854 [Byte1]: 68
8745 16:44:19.704294
8746 16:44:19.704414 Set Vref, RX VrefLevel [Byte0]: 69
8747 16:44:19.707457 [Byte1]: 69
8748 16:44:19.711629
8749 16:44:19.711753 Set Vref, RX VrefLevel [Byte0]: 70
8750 16:44:19.714787 [Byte1]: 70
8751 16:44:19.719054
8752 16:44:19.719153 Set Vref, RX VrefLevel [Byte0]: 71
8753 16:44:19.722643 [Byte1]: 71
8754 16:44:19.726936
8755 16:44:19.727027 Final RX Vref Byte 0 = 55 to rank0
8756 16:44:19.729859 Final RX Vref Byte 1 = 58 to rank0
8757 16:44:19.733790 Final RX Vref Byte 0 = 55 to rank1
8758 16:44:19.736947 Final RX Vref Byte 1 = 58 to rank1==
8759 16:44:19.740307 Dram Type= 6, Freq= 0, CH_1, rank 0
8760 16:44:19.746881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 16:44:19.747018 ==
8762 16:44:19.747094 DQS Delay:
8763 16:44:19.747168 DQS0 = 0, DQS1 = 0
8764 16:44:19.749943 DQM Delay:
8765 16:44:19.750033 DQM0 = 131, DQM1 = 122
8766 16:44:19.753324 DQ Delay:
8767 16:44:19.756550 DQ0 =138, DQ1 =126, DQ2 =120, DQ3 =128
8768 16:44:19.760243 DQ4 =130, DQ5 =140, DQ6 =142, DQ7 =128
8769 16:44:19.763732 DQ8 =108, DQ9 =110, DQ10 =124, DQ11 =114
8770 16:44:19.766700 DQ12 =132, DQ13 =130, DQ14 =130, DQ15 =130
8771 16:44:19.766833
8772 16:44:19.766939
8773 16:44:19.767008
8774 16:44:19.769672 [DramC_TX_OE_Calibration] TA2
8775 16:44:19.773463 Original DQ_B0 (3 6) =30, OEN = 27
8776 16:44:19.776409 Original DQ_B1 (3 6) =30, OEN = 27
8777 16:44:19.779954 24, 0x0, End_B0=24 End_B1=24
8778 16:44:19.780046 25, 0x0, End_B0=25 End_B1=25
8779 16:44:19.782838 26, 0x0, End_B0=26 End_B1=26
8780 16:44:19.786201 27, 0x0, End_B0=27 End_B1=27
8781 16:44:19.789644 28, 0x0, End_B0=28 End_B1=28
8782 16:44:19.793188 29, 0x0, End_B0=29 End_B1=29
8783 16:44:19.793292 30, 0x0, End_B0=30 End_B1=30
8784 16:44:19.796259 31, 0x4141, End_B0=30 End_B1=30
8785 16:44:19.799976 Byte0 end_step=30 best_step=27
8786 16:44:19.802981 Byte1 end_step=30 best_step=27
8787 16:44:19.806164 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 16:44:19.809792 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 16:44:19.809885
8790 16:44:19.809955
8791 16:44:19.815898 [DQSOSCAuto] RK0, (LSB)MR18= 0xb10, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
8792 16:44:19.819880 CH1 RK0: MR19=303, MR18=B10
8793 16:44:19.826024 CH1_RK0: MR19=0x303, MR18=0xB10, DQSOSC=401, MR23=63, INC=22, DEC=15
8794 16:44:19.826165
8795 16:44:19.829626 ----->DramcWriteLeveling(PI) begin...
8796 16:44:19.829758 ==
8797 16:44:19.832583 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 16:44:19.836233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 16:44:19.836354 ==
8800 16:44:19.839092 Write leveling (Byte 0): 21 => 21
8801 16:44:19.842650 Write leveling (Byte 1): 29 => 29
8802 16:44:19.846000 DramcWriteLeveling(PI) end<-----
8803 16:44:19.846122
8804 16:44:19.846228 ==
8805 16:44:19.848858 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 16:44:19.852166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 16:44:19.852281 ==
8808 16:44:19.855630 [Gating] SW mode calibration
8809 16:44:19.862198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8810 16:44:19.868913 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8811 16:44:19.871931 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 16:44:19.878482 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8813 16:44:19.881905 1 4 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
8814 16:44:19.885400 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8815 16:44:19.891693 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 16:44:19.895520 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
8817 16:44:19.898190 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 16:44:19.905255 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 16:44:19.908636 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 16:44:19.911622 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 16:44:19.918121 1 5 8 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8822 16:44:19.921309 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8823 16:44:19.924932 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8824 16:44:19.931224 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 16:44:19.934939 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 16:44:19.938115 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 16:44:19.944708 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 16:44:19.947553 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 16:44:19.951062 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8830 16:44:19.957419 1 6 12 | B1->B0 | 3d3c 4646 | 1 0 | (0 0) (0 0)
8831 16:44:19.960995 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 16:44:19.964418 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 16:44:19.970856 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 16:44:19.974193 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 16:44:19.977819 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 16:44:19.984226 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 16:44:19.987221 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8838 16:44:19.990466 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8839 16:44:19.997182 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8840 16:44:20.000669 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 16:44:20.003458 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 16:44:20.010417 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 16:44:20.013415 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 16:44:20.016503 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 16:44:20.023458 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 16:44:20.026535 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 16:44:20.029746 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 16:44:20.036506 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 16:44:20.039733 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 16:44:20.043272 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 16:44:20.049794 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 16:44:20.053161 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8853 16:44:20.056877 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8854 16:44:20.063028 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8855 16:44:20.066443 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 16:44:20.069684 Total UI for P1: 0, mck2ui 16
8857 16:44:20.072836 best dqsien dly found for B0: ( 1, 9, 8)
8858 16:44:20.076539 Total UI for P1: 0, mck2ui 16
8859 16:44:20.079345 best dqsien dly found for B1: ( 1, 9, 10)
8860 16:44:20.082585 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8861 16:44:20.085997 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8862 16:44:20.086123
8863 16:44:20.089376 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8864 16:44:20.092781 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8865 16:44:20.095825 [Gating] SW calibration Done
8866 16:44:20.095945 ==
8867 16:44:20.099401 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 16:44:20.105709 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 16:44:20.105852 ==
8870 16:44:20.105960 RX Vref Scan: 0
8871 16:44:20.106059
8872 16:44:20.109360 RX Vref 0 -> 0, step: 1
8873 16:44:20.109490
8874 16:44:20.112681 RX Delay 0 -> 252, step: 8
8875 16:44:20.115897 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8876 16:44:20.119281 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8877 16:44:20.122632 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8878 16:44:20.125836 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8879 16:44:20.132482 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8880 16:44:20.135539 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8881 16:44:20.139307 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8882 16:44:20.142586 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8883 16:44:20.145514 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8884 16:44:20.152139 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8885 16:44:20.155658 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8886 16:44:20.158474 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8887 16:44:20.162181 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8888 16:44:20.168394 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8889 16:44:20.172005 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8890 16:44:20.174982 iDelay=200, Bit 15, Center 135 (72 ~ 199) 128
8891 16:44:20.175106 ==
8892 16:44:20.178334 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 16:44:20.181872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 16:44:20.182001 ==
8895 16:44:20.184836 DQS Delay:
8896 16:44:20.184951 DQS0 = 0, DQS1 = 0
8897 16:44:20.188403 DQM Delay:
8898 16:44:20.188522 DQM0 = 129, DQM1 = 128
8899 16:44:20.191511 DQ Delay:
8900 16:44:20.194850 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8901 16:44:20.198061 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8902 16:44:20.201591 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8903 16:44:20.204598 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =135
8904 16:44:20.204723
8905 16:44:20.204832
8906 16:44:20.204929 ==
8907 16:44:20.208245 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 16:44:20.211114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 16:44:20.211237 ==
8910 16:44:20.211339
8911 16:44:20.214370
8912 16:44:20.214484 TX Vref Scan disable
8913 16:44:20.218154 == TX Byte 0 ==
8914 16:44:20.221451 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8915 16:44:20.224646 Update DQM dly =977 (3 ,6, 17) DQM OEN =(3 ,3)
8916 16:44:20.227924 == TX Byte 1 ==
8917 16:44:20.230855 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8918 16:44:20.234055 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8919 16:44:20.234193 ==
8920 16:44:20.237623 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 16:44:20.244345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 16:44:20.244487 ==
8923 16:44:20.258306
8924 16:44:20.261258 TX Vref early break, caculate TX vref
8925 16:44:20.264867 TX Vref=16, minBit 0, minWin=20, winSum=364
8926 16:44:20.267885 TX Vref=18, minBit 0, minWin=21, winSum=373
8927 16:44:20.270909 TX Vref=20, minBit 0, minWin=21, winSum=381
8928 16:44:20.274562 TX Vref=22, minBit 0, minWin=22, winSum=389
8929 16:44:20.277537 TX Vref=24, minBit 0, minWin=22, winSum=399
8930 16:44:20.284673 TX Vref=26, minBit 0, minWin=22, winSum=411
8931 16:44:20.287588 TX Vref=28, minBit 0, minWin=22, winSum=407
8932 16:44:20.290882 TX Vref=30, minBit 0, minWin=23, winSum=406
8933 16:44:20.294406 TX Vref=32, minBit 0, minWin=23, winSum=400
8934 16:44:20.297830 TX Vref=34, minBit 1, minWin=23, winSum=392
8935 16:44:20.301093 TX Vref=36, minBit 0, minWin=21, winSum=377
8936 16:44:20.307608 [TxChooseVref] Worse bit 0, Min win 23, Win sum 406, Final Vref 30
8937 16:44:20.307776
8938 16:44:20.310553 Final TX Range 0 Vref 30
8939 16:44:20.310672
8940 16:44:20.310772 ==
8941 16:44:20.314005 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 16:44:20.317121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 16:44:20.317245 ==
8944 16:44:20.320908
8945 16:44:20.321027
8946 16:44:20.321128 TX Vref Scan disable
8947 16:44:20.326902 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8948 16:44:20.327035 == TX Byte 0 ==
8949 16:44:20.330272 u2DelayCellOfst[0]=15 cells (4 PI)
8950 16:44:20.333696 u2DelayCellOfst[1]=15 cells (4 PI)
8951 16:44:20.337378 u2DelayCellOfst[2]=0 cells (0 PI)
8952 16:44:20.340425 u2DelayCellOfst[3]=3 cells (1 PI)
8953 16:44:20.343599 u2DelayCellOfst[4]=7 cells (2 PI)
8954 16:44:20.347202 u2DelayCellOfst[5]=22 cells (6 PI)
8955 16:44:20.350306 u2DelayCellOfst[6]=22 cells (6 PI)
8956 16:44:20.353791 u2DelayCellOfst[7]=3 cells (1 PI)
8957 16:44:20.356901 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8958 16:44:20.360697 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8959 16:44:20.363471 == TX Byte 1 ==
8960 16:44:20.367131 u2DelayCellOfst[8]=0 cells (0 PI)
8961 16:44:20.370063 u2DelayCellOfst[9]=7 cells (2 PI)
8962 16:44:20.373825 u2DelayCellOfst[10]=15 cells (4 PI)
8963 16:44:20.376907 u2DelayCellOfst[11]=7 cells (2 PI)
8964 16:44:20.380035 u2DelayCellOfst[12]=18 cells (5 PI)
8965 16:44:20.380126 u2DelayCellOfst[13]=18 cells (5 PI)
8966 16:44:20.383733 u2DelayCellOfst[14]=18 cells (5 PI)
8967 16:44:20.386691 u2DelayCellOfst[15]=18 cells (5 PI)
8968 16:44:20.393474 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8969 16:44:20.396609 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8970 16:44:20.400013 DramC Write-DBI on
8971 16:44:20.400105 ==
8972 16:44:20.402884 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 16:44:20.406318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 16:44:20.406438 ==
8975 16:44:20.406549
8976 16:44:20.406647
8977 16:44:20.409568 TX Vref Scan disable
8978 16:44:20.409691 == TX Byte 0 ==
8979 16:44:20.416352 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
8980 16:44:20.416476 == TX Byte 1 ==
8981 16:44:20.419787 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8982 16:44:20.422673 DramC Write-DBI off
8983 16:44:20.422802
8984 16:44:20.422909 [DATLAT]
8985 16:44:20.426468 Freq=1600, CH1 RK1
8986 16:44:20.426553
8987 16:44:20.426654 DATLAT Default: 0xf
8988 16:44:20.429478 0, 0xFFFF, sum = 0
8989 16:44:20.432400 1, 0xFFFF, sum = 0
8990 16:44:20.432496 2, 0xFFFF, sum = 0
8991 16:44:20.435975 3, 0xFFFF, sum = 0
8992 16:44:20.436073 4, 0xFFFF, sum = 0
8993 16:44:20.439445 5, 0xFFFF, sum = 0
8994 16:44:20.439535 6, 0xFFFF, sum = 0
8995 16:44:20.442861 7, 0xFFFF, sum = 0
8996 16:44:20.442976 8, 0xFFFF, sum = 0
8997 16:44:20.445933 9, 0xFFFF, sum = 0
8998 16:44:20.446027 10, 0xFFFF, sum = 0
8999 16:44:20.449087 11, 0xFFFF, sum = 0
9000 16:44:20.449177 12, 0xFFFF, sum = 0
9001 16:44:20.452381 13, 0x8FFF, sum = 0
9002 16:44:20.452472 14, 0x0, sum = 1
9003 16:44:20.455671 15, 0x0, sum = 2
9004 16:44:20.455761 16, 0x0, sum = 3
9005 16:44:20.459317 17, 0x0, sum = 4
9006 16:44:20.459408 best_step = 15
9007 16:44:20.459478
9008 16:44:20.459542 ==
9009 16:44:20.462519 Dram Type= 6, Freq= 0, CH_1, rank 1
9010 16:44:20.469146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9011 16:44:20.469260 ==
9012 16:44:20.469333 RX Vref Scan: 0
9013 16:44:20.469399
9014 16:44:20.472279 RX Vref 0 -> 0, step: 1
9015 16:44:20.472396
9016 16:44:20.475417 RX Delay 3 -> 252, step: 4
9017 16:44:20.478898 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9018 16:44:20.482026 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9019 16:44:20.485606 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9020 16:44:20.492175 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
9021 16:44:20.495201 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9022 16:44:20.498842 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9023 16:44:20.502350 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9024 16:44:20.505233 iDelay=195, Bit 7, Center 124 (67 ~ 182) 116
9025 16:44:20.511678 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9026 16:44:20.515014 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9027 16:44:20.518324 iDelay=195, Bit 10, Center 128 (71 ~ 186) 116
9028 16:44:20.521714 iDelay=195, Bit 11, Center 120 (63 ~ 178) 116
9029 16:44:20.528529 iDelay=195, Bit 12, Center 134 (79 ~ 190) 112
9030 16:44:20.531710 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
9031 16:44:20.534727 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9032 16:44:20.537905 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9033 16:44:20.538010 ==
9034 16:44:20.541538 Dram Type= 6, Freq= 0, CH_1, rank 1
9035 16:44:20.547796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9036 16:44:20.547902 ==
9037 16:44:20.547985 DQS Delay:
9038 16:44:20.551181 DQS0 = 0, DQS1 = 0
9039 16:44:20.551271 DQM Delay:
9040 16:44:20.554453 DQM0 = 127, DQM1 = 124
9041 16:44:20.554543 DQ Delay:
9042 16:44:20.557939 DQ0 =132, DQ1 =124, DQ2 =114, DQ3 =122
9043 16:44:20.560846 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =124
9044 16:44:20.564097 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
9045 16:44:20.567867 DQ12 =134, DQ13 =130, DQ14 =130, DQ15 =134
9046 16:44:20.567958
9047 16:44:20.568028
9048 16:44:20.568093
9049 16:44:20.570913 [DramC_TX_OE_Calibration] TA2
9050 16:44:20.574320 Original DQ_B0 (3 6) =30, OEN = 27
9051 16:44:20.577319 Original DQ_B1 (3 6) =30, OEN = 27
9052 16:44:20.580483 24, 0x0, End_B0=24 End_B1=24
9053 16:44:20.584035 25, 0x0, End_B0=25 End_B1=25
9054 16:44:20.584135 26, 0x0, End_B0=26 End_B1=26
9055 16:44:20.587065 27, 0x0, End_B0=27 End_B1=27
9056 16:44:20.590691 28, 0x0, End_B0=28 End_B1=28
9057 16:44:20.593614 29, 0x0, End_B0=29 End_B1=29
9058 16:44:20.597314 30, 0x0, End_B0=30 End_B1=30
9059 16:44:20.597416 31, 0x4141, End_B0=30 End_B1=30
9060 16:44:20.600678 Byte0 end_step=30 best_step=27
9061 16:44:20.603492 Byte1 end_step=30 best_step=27
9062 16:44:20.607075 Byte0 TX OE(2T, 0.5T) = (3, 3)
9063 16:44:20.610571 Byte1 TX OE(2T, 0.5T) = (3, 3)
9064 16:44:20.610705
9065 16:44:20.610808
9066 16:44:20.617161 [DQSOSCAuto] RK1, (LSB)MR18= 0x101d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9067 16:44:20.620068 CH1 RK1: MR19=303, MR18=101D
9068 16:44:20.626884 CH1_RK1: MR19=0x303, MR18=0x101D, DQSOSC=395, MR23=63, INC=23, DEC=15
9069 16:44:20.630320 [RxdqsGatingPostProcess] freq 1600
9070 16:44:20.636796 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9071 16:44:20.640010 best DQS0 dly(2T, 0.5T) = (1, 1)
9072 16:44:20.640110 best DQS1 dly(2T, 0.5T) = (1, 1)
9073 16:44:20.642993 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9074 16:44:20.646721 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9075 16:44:20.649567 best DQS0 dly(2T, 0.5T) = (1, 1)
9076 16:44:20.653155 best DQS1 dly(2T, 0.5T) = (1, 1)
9077 16:44:20.656489 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9078 16:44:20.659610 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9079 16:44:20.663159 Pre-setting of DQS Precalculation
9080 16:44:20.666393 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9081 16:44:20.676176 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9082 16:44:20.682784 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9083 16:44:20.682936
9084 16:44:20.683041
9085 16:44:20.686394 [Calibration Summary] 3200 Mbps
9086 16:44:20.686517 CH 0, Rank 0
9087 16:44:20.689478 SW Impedance : PASS
9088 16:44:20.689567 DUTY Scan : NO K
9089 16:44:20.693004 ZQ Calibration : PASS
9090 16:44:20.696211 Jitter Meter : NO K
9091 16:44:20.696308 CBT Training : PASS
9092 16:44:20.699097 Write leveling : PASS
9093 16:44:20.702845 RX DQS gating : PASS
9094 16:44:20.702940 RX DQ/DQS(RDDQC) : PASS
9095 16:44:20.705982 TX DQ/DQS : PASS
9096 16:44:20.709030 RX DATLAT : PASS
9097 16:44:20.709136 RX DQ/DQS(Engine): PASS
9098 16:44:20.712662 TX OE : PASS
9099 16:44:20.712766 All Pass.
9100 16:44:20.712836
9101 16:44:20.715566 CH 0, Rank 1
9102 16:44:20.715667 SW Impedance : PASS
9103 16:44:20.719048 DUTY Scan : NO K
9104 16:44:20.722668 ZQ Calibration : PASS
9105 16:44:20.722768 Jitter Meter : NO K
9106 16:44:20.725574 CBT Training : PASS
9107 16:44:20.729558 Write leveling : PASS
9108 16:44:20.729655 RX DQS gating : PASS
9109 16:44:20.732494 RX DQ/DQS(RDDQC) : PASS
9110 16:44:20.735598 TX DQ/DQS : PASS
9111 16:44:20.735700 RX DATLAT : PASS
9112 16:44:20.738875 RX DQ/DQS(Engine): PASS
9113 16:44:20.742468 TX OE : PASS
9114 16:44:20.742568 All Pass.
9115 16:44:20.742663
9116 16:44:20.742732 CH 1, Rank 0
9117 16:44:20.745242 SW Impedance : PASS
9118 16:44:20.748738 DUTY Scan : NO K
9119 16:44:20.748871 ZQ Calibration : PASS
9120 16:44:20.752406 Jitter Meter : NO K
9121 16:44:20.755419 CBT Training : PASS
9122 16:44:20.755508 Write leveling : PASS
9123 16:44:20.758977 RX DQS gating : PASS
9124 16:44:20.762005 RX DQ/DQS(RDDQC) : PASS
9125 16:44:20.762134 TX DQ/DQS : PASS
9126 16:44:20.765241 RX DATLAT : PASS
9127 16:44:20.768359 RX DQ/DQS(Engine): PASS
9128 16:44:20.768454 TX OE : PASS
9129 16:44:20.768524 All Pass.
9130 16:44:20.772128
9131 16:44:20.772220 CH 1, Rank 1
9132 16:44:20.775010 SW Impedance : PASS
9133 16:44:20.775100 DUTY Scan : NO K
9134 16:44:20.778806 ZQ Calibration : PASS
9135 16:44:20.778925 Jitter Meter : NO K
9136 16:44:20.781768 CBT Training : PASS
9137 16:44:20.785147 Write leveling : PASS
9138 16:44:20.785241 RX DQS gating : PASS
9139 16:44:20.788244 RX DQ/DQS(RDDQC) : PASS
9140 16:44:20.791324 TX DQ/DQS : PASS
9141 16:44:20.791443 RX DATLAT : PASS
9142 16:44:20.795073 RX DQ/DQS(Engine): PASS
9143 16:44:20.797977 TX OE : PASS
9144 16:44:20.798098 All Pass.
9145 16:44:20.798196
9146 16:44:20.801269 DramC Write-DBI on
9147 16:44:20.801385 PER_BANK_REFRESH: Hybrid Mode
9148 16:44:20.805039 TX_TRACKING: ON
9149 16:44:20.814570 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9150 16:44:20.820934 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9151 16:44:20.827566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9152 16:44:20.831270 [FAST_K] Save calibration result to emmc
9153 16:44:20.834362 sync common calibartion params.
9154 16:44:20.837949 sync cbt_mode0:1, 1:1
9155 16:44:20.840991 dram_init: ddr_geometry: 2
9156 16:44:20.841117 dram_init: ddr_geometry: 2
9157 16:44:20.844234 dram_init: ddr_geometry: 2
9158 16:44:20.847510 0:dram_rank_size:100000000
9159 16:44:20.847641 1:dram_rank_size:100000000
9160 16:44:20.853954 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9161 16:44:20.857212 DFS_SHUFFLE_HW_MODE: ON
9162 16:44:20.860899 dramc_set_vcore_voltage set vcore to 725000
9163 16:44:20.863783 Read voltage for 1600, 0
9164 16:44:20.863886 Vio18 = 0
9165 16:44:20.863958 Vcore = 725000
9166 16:44:20.867445 Vdram = 0
9167 16:44:20.867543 Vddq = 0
9168 16:44:20.867626 Vmddr = 0
9169 16:44:20.870264 switch to 3200 Mbps bootup
9170 16:44:20.873457 [DramcRunTimeConfig]
9171 16:44:20.873549 PHYPLL
9172 16:44:20.873624 DPM_CONTROL_AFTERK: ON
9173 16:44:20.876884 PER_BANK_REFRESH: ON
9174 16:44:20.880039 REFRESH_OVERHEAD_REDUCTION: ON
9175 16:44:20.880137 CMD_PICG_NEW_MODE: OFF
9176 16:44:20.883185 XRTWTW_NEW_MODE: ON
9177 16:44:20.886735 XRTRTR_NEW_MODE: ON
9178 16:44:20.886831 TX_TRACKING: ON
9179 16:44:20.890319 RDSEL_TRACKING: OFF
9180 16:44:20.890412 DQS Precalculation for DVFS: ON
9181 16:44:20.893302 RX_TRACKING: OFF
9182 16:44:20.893387 HW_GATING DBG: ON
9183 16:44:20.896582 ZQCS_ENABLE_LP4: ON
9184 16:44:20.899564 RX_PICG_NEW_MODE: ON
9185 16:44:20.899663 TX_PICG_NEW_MODE: ON
9186 16:44:20.903303 ENABLE_RX_DCM_DPHY: ON
9187 16:44:20.906855 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9188 16:44:20.906955 DUMMY_READ_FOR_TRACKING: OFF
9189 16:44:20.909452 !!! SPM_CONTROL_AFTERK: OFF
9190 16:44:20.913018 !!! SPM could not control APHY
9191 16:44:20.916049 IMPEDANCE_TRACKING: ON
9192 16:44:20.916152 TEMP_SENSOR: ON
9193 16:44:20.919533 HW_SAVE_FOR_SR: OFF
9194 16:44:20.922750 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9195 16:44:20.925731 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9196 16:44:20.925823 Read ODT Tracking: ON
9197 16:44:20.929205 Refresh Rate DeBounce: ON
9198 16:44:20.932706 DFS_NO_QUEUE_FLUSH: ON
9199 16:44:20.935669 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9200 16:44:20.935761 ENABLE_DFS_RUNTIME_MRW: OFF
9201 16:44:20.939109 DDR_RESERVE_NEW_MODE: ON
9202 16:44:20.942284 MR_CBT_SWITCH_FREQ: ON
9203 16:44:20.942371 =========================
9204 16:44:20.962515 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9205 16:44:20.965896 dram_init: ddr_geometry: 2
9206 16:44:20.984107 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9207 16:44:20.987672 dram_init: dram init end (result: 0)
9208 16:44:20.993896 DRAM-K: Full calibration passed in 24555 msecs
9209 16:44:20.997426 MRC: failed to locate region type 0.
9210 16:44:20.997559 DRAM rank0 size:0x100000000,
9211 16:44:21.000560 DRAM rank1 size=0x100000000
9212 16:44:21.010871 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9213 16:44:21.017105 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9214 16:44:21.023750 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9215 16:44:21.033519 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9216 16:44:21.033660 DRAM rank0 size:0x100000000,
9217 16:44:21.036956 DRAM rank1 size=0x100000000
9218 16:44:21.037071 CBMEM:
9219 16:44:21.040140 IMD: root @ 0xfffff000 254 entries.
9220 16:44:21.043829 IMD: root @ 0xffffec00 62 entries.
9221 16:44:21.046985 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9222 16:44:21.053861 WARNING: RO_VPD is uninitialized or empty.
9223 16:44:21.056770 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9224 16:44:21.064125 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9225 16:44:21.077363 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9226 16:44:21.088331 BS: romstage times (exec / console): total (unknown) / 24024 ms
9227 16:44:21.088477
9228 16:44:21.088550
9229 16:44:21.098522 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9230 16:44:21.101623 ARM64: Exception handlers installed.
9231 16:44:21.104635 ARM64: Testing exception
9232 16:44:21.108197 ARM64: Done test exception
9233 16:44:21.108294 Enumerating buses...
9234 16:44:21.111958 Show all devs... Before device enumeration.
9235 16:44:21.114755 Root Device: enabled 1
9236 16:44:21.118175 CPU_CLUSTER: 0: enabled 1
9237 16:44:21.118274 CPU: 00: enabled 1
9238 16:44:21.121180 Compare with tree...
9239 16:44:21.121271 Root Device: enabled 1
9240 16:44:21.124708 CPU_CLUSTER: 0: enabled 1
9241 16:44:21.128163 CPU: 00: enabled 1
9242 16:44:21.128262 Root Device scanning...
9243 16:44:21.131210 scan_static_bus for Root Device
9244 16:44:21.134960 CPU_CLUSTER: 0 enabled
9245 16:44:21.138015 scan_static_bus for Root Device done
9246 16:44:21.141639 scan_bus: bus Root Device finished in 8 msecs
9247 16:44:21.141738 done
9248 16:44:21.147831 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9249 16:44:21.151002 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9250 16:44:21.157774 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9251 16:44:21.161440 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9252 16:44:21.164411 Allocating resources...
9253 16:44:21.167954 Reading resources...
9254 16:44:21.170864 Root Device read_resources bus 0 link: 0
9255 16:44:21.174486 DRAM rank0 size:0x100000000,
9256 16:44:21.174617 DRAM rank1 size=0x100000000
9257 16:44:21.177300 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9258 16:44:21.181122 CPU: 00 missing read_resources
9259 16:44:21.187359 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9260 16:44:21.190968 Root Device read_resources bus 0 link: 0 done
9261 16:44:21.194081 Done reading resources.
9262 16:44:21.197126 Show resources in subtree (Root Device)...After reading.
9263 16:44:21.200670 Root Device child on link 0 CPU_CLUSTER: 0
9264 16:44:21.204279 CPU_CLUSTER: 0 child on link 0 CPU: 00
9265 16:44:21.214060 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9266 16:44:21.214211 CPU: 00
9267 16:44:21.217084 Root Device assign_resources, bus 0 link: 0
9268 16:44:21.220799 CPU_CLUSTER: 0 missing set_resources
9269 16:44:21.226956 Root Device assign_resources, bus 0 link: 0 done
9270 16:44:21.227073 Done setting resources.
9271 16:44:21.233399 Show resources in subtree (Root Device)...After assigning values.
9272 16:44:21.237203 Root Device child on link 0 CPU_CLUSTER: 0
9273 16:44:21.240337 CPU_CLUSTER: 0 child on link 0 CPU: 00
9274 16:44:21.250074 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9275 16:44:21.250207 CPU: 00
9276 16:44:21.253588 Done allocating resources.
9277 16:44:21.259955 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9278 16:44:21.260075 Enabling resources...
9279 16:44:21.263008 done.
9280 16:44:21.266222 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9281 16:44:21.270059 Initializing devices...
9282 16:44:21.270158 Root Device init
9283 16:44:21.273115 init hardware done!
9284 16:44:21.273208 0x00000018: ctrlr->caps
9285 16:44:21.276626 52.000 MHz: ctrlr->f_max
9286 16:44:21.279504 0.400 MHz: ctrlr->f_min
9287 16:44:21.279636 0x40ff8080: ctrlr->voltages
9288 16:44:21.283024 sclk: 390625
9289 16:44:21.283110 Bus Width = 1
9290 16:44:21.286550 sclk: 390625
9291 16:44:21.286644 Bus Width = 1
9292 16:44:21.289303 Early init status = 3
9293 16:44:21.292641 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9294 16:44:21.295981 in-header: 03 fc 00 00 01 00 00 00
9295 16:44:21.299778 in-data: 00
9296 16:44:21.302698 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9297 16:44:21.306876 in-header: 03 fd 00 00 00 00 00 00
9298 16:44:21.310663 in-data:
9299 16:44:21.313675 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9300 16:44:21.317353 in-header: 03 fc 00 00 01 00 00 00
9301 16:44:21.320515 in-data: 00
9302 16:44:21.324068 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9303 16:44:21.328336 in-header: 03 fd 00 00 00 00 00 00
9304 16:44:21.331771 in-data:
9305 16:44:21.335183 [SSUSB] Setting up USB HOST controller...
9306 16:44:21.338289 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9307 16:44:21.341506 [SSUSB] phy power-on done.
9308 16:44:21.345010 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9309 16:44:21.351568 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9310 16:44:21.354802 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9311 16:44:21.361357 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9312 16:44:21.368034 read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps
9313 16:44:21.374801 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9314 16:44:21.380945 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9315 16:44:21.387815 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9316 16:44:21.391087 SPM: binary array size = 0x9dc
9317 16:44:21.394152 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9318 16:44:21.401223 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9319 16:44:21.407504 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9320 16:44:21.414519 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9321 16:44:21.417213 configure_display: Starting display init
9322 16:44:21.451833 anx7625_power_on_init: Init interface.
9323 16:44:21.454896 anx7625_disable_pd_protocol: Disabled PD feature.
9324 16:44:21.458021 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9325 16:44:21.485854 anx7625_start_dp_work: Secure OCM version=00
9326 16:44:21.489244 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9327 16:44:21.504123 sp_tx_get_edid_block: EDID Block = 1
9328 16:44:21.606565 Extracted contents:
9329 16:44:21.609975 header: 00 ff ff ff ff ff ff 00
9330 16:44:21.613282 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9331 16:44:21.616554 version: 01 04
9332 16:44:21.619883 basic params: 95 1f 11 78 0a
9333 16:44:21.623267 chroma info: 76 90 94 55 54 90 27 21 50 54
9334 16:44:21.626153 established: 00 00 00
9335 16:44:21.633329 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9336 16:44:21.639808 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9337 16:44:21.642827 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9338 16:44:21.649365 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9339 16:44:21.656001 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9340 16:44:21.659044 extensions: 00
9341 16:44:21.659173 checksum: fb
9342 16:44:21.659286
9343 16:44:21.665834 Manufacturer: IVO Model 57d Serial Number 0
9344 16:44:21.665975 Made week 0 of 2020
9345 16:44:21.668901 EDID version: 1.4
9346 16:44:21.668987 Digital display
9347 16:44:21.672591 6 bits per primary color channel
9348 16:44:21.675488 DisplayPort interface
9349 16:44:21.675618 Maximum image size: 31 cm x 17 cm
9350 16:44:21.679249 Gamma: 220%
9351 16:44:21.679356 Check DPMS levels
9352 16:44:21.685492 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9353 16:44:21.688764 First detailed timing is preferred timing
9354 16:44:21.691897 Established timings supported:
9355 16:44:21.692021 Standard timings supported:
9356 16:44:21.695413 Detailed timings
9357 16:44:21.698393 Hex of detail: 383680a07038204018303c0035ae10000019
9358 16:44:21.705070 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9359 16:44:21.708138 0780 0798 07c8 0820 hborder 0
9360 16:44:21.711888 0438 043b 0447 0458 vborder 0
9361 16:44:21.715153 -hsync -vsync
9362 16:44:21.715259 Did detailed timing
9363 16:44:21.721376 Hex of detail: 000000000000000000000000000000000000
9364 16:44:21.724746 Manufacturer-specified data, tag 0
9365 16:44:21.728038 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9366 16:44:21.731340 ASCII string: InfoVision
9367 16:44:21.735073 Hex of detail: 000000fe00523134304e574635205248200a
9368 16:44:21.738491 ASCII string: R140NWF5 RH
9369 16:44:21.738595 Checksum
9370 16:44:21.741253 Checksum: 0xfb (valid)
9371 16:44:21.744601 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9372 16:44:21.747655 DSI data_rate: 832800000 bps
9373 16:44:21.754594 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9374 16:44:21.757802 anx7625_parse_edid: pixelclock(138800).
9375 16:44:21.760762 hactive(1920), hsync(48), hfp(24), hbp(88)
9376 16:44:21.764529 vactive(1080), vsync(12), vfp(3), vbp(17)
9377 16:44:21.767514 anx7625_dsi_config: config dsi.
9378 16:44:21.774361 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9379 16:44:21.788625 anx7625_dsi_config: success to config DSI
9380 16:44:21.791913 anx7625_dp_start: MIPI phy setup OK.
9381 16:44:21.795531 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9382 16:44:21.798750 mtk_ddp_mode_set invalid vrefresh 60
9383 16:44:21.801595 main_disp_path_setup
9384 16:44:21.801679 ovl_layer_smi_id_en
9385 16:44:21.805142 ovl_layer_smi_id_en
9386 16:44:21.805243 ccorr_config
9387 16:44:21.805311 aal_config
9388 16:44:21.808196 gamma_config
9389 16:44:21.808286 postmask_config
9390 16:44:21.811373 dither_config
9391 16:44:21.815152 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9392 16:44:21.821674 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9393 16:44:21.824553 Root Device init finished in 551 msecs
9394 16:44:21.828148 CPU_CLUSTER: 0 init
9395 16:44:21.834552 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9396 16:44:21.841064 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9397 16:44:21.841223 APU_MBOX 0x190000b0 = 0x10001
9398 16:44:21.844659 APU_MBOX 0x190001b0 = 0x10001
9399 16:44:21.847754 APU_MBOX 0x190005b0 = 0x10001
9400 16:44:21.850982 APU_MBOX 0x190006b0 = 0x10001
9401 16:44:21.857462 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9402 16:44:21.867892 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9403 16:44:21.880225 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9404 16:44:21.886505 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9405 16:44:21.898349 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9406 16:44:21.907640 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9407 16:44:21.910943 CPU_CLUSTER: 0 init finished in 81 msecs
9408 16:44:21.914105 Devices initialized
9409 16:44:21.917044 Show all devs... After init.
9410 16:44:21.917147 Root Device: enabled 1
9411 16:44:21.920795 CPU_CLUSTER: 0: enabled 1
9412 16:44:21.923849 CPU: 00: enabled 1
9413 16:44:21.926892 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9414 16:44:21.930427 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9415 16:44:21.933799 ELOG: NV offset 0x57f000 size 0x1000
9416 16:44:21.940585 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9417 16:44:21.947249 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9418 16:44:21.950133 ELOG: Event(17) added with size 13 at 2023-06-03 16:44:22 UTC
9419 16:44:21.957300 out: cmd=0x121: 03 db 21 01 00 00 00 00
9420 16:44:21.960353 in-header: 03 6c 00 00 2c 00 00 00
9421 16:44:21.973643 in-data: f3 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9422 16:44:21.976609 ELOG: Event(A1) added with size 10 at 2023-06-03 16:44:22 UTC
9423 16:44:21.983519 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9424 16:44:21.989741 ELOG: Event(A0) added with size 9 at 2023-06-03 16:44:22 UTC
9425 16:44:21.993259 elog_add_boot_reason: Logged dev mode boot
9426 16:44:21.999783 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9427 16:44:21.999945 Finalize devices...
9428 16:44:22.002909 Devices finalized
9429 16:44:22.006473 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9430 16:44:22.010145 Writing coreboot table at 0xffe64000
9431 16:44:22.016675 0. 000000000010a000-0000000000113fff: RAMSTAGE
9432 16:44:22.019674 1. 0000000040000000-00000000400fffff: RAM
9433 16:44:22.022597 2. 0000000040100000-000000004032afff: RAMSTAGE
9434 16:44:22.026258 3. 000000004032b000-00000000545fffff: RAM
9435 16:44:22.029444 4. 0000000054600000-000000005465ffff: BL31
9436 16:44:22.036108 5. 0000000054660000-00000000ffe63fff: RAM
9437 16:44:22.038985 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9438 16:44:22.042664 7. 0000000100000000-000000023fffffff: RAM
9439 16:44:22.046072 Passing 5 GPIOs to payload:
9440 16:44:22.052498 NAME | PORT | POLARITY | VALUE
9441 16:44:22.055471 EC in RW | 0x000000aa | low | undefined
9442 16:44:22.059050 EC interrupt | 0x00000005 | low | undefined
9443 16:44:22.065674 TPM interrupt | 0x000000ab | high | undefined
9444 16:44:22.069109 SD card detect | 0x00000011 | high | undefined
9445 16:44:22.075550 speaker enable | 0x00000093 | high | undefined
9446 16:44:22.078521 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9447 16:44:22.082249 in-header: 03 f9 00 00 02 00 00 00
9448 16:44:22.082376 in-data: 02 00
9449 16:44:22.085145 ADC[4]: Raw value=894081 ID=7
9450 16:44:22.088980 ADC[3]: Raw value=213440 ID=1
9451 16:44:22.089084 RAM Code: 0x71
9452 16:44:22.092152 ADC[6]: Raw value=74722 ID=0
9453 16:44:22.094933 ADC[5]: Raw value=211590 ID=1
9454 16:44:22.095030 SKU Code: 0x1
9455 16:44:22.101809 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9456 16:44:22.104726 coreboot table: 964 bytes.
9457 16:44:22.108214 IMD ROOT 0. 0xfffff000 0x00001000
9458 16:44:22.111806 IMD SMALL 1. 0xffffe000 0x00001000
9459 16:44:22.114983 RO MCACHE 2. 0xffffc000 0x00001104
9460 16:44:22.118312 CONSOLE 3. 0xfff7c000 0x00080000
9461 16:44:22.121233 FMAP 4. 0xfff7b000 0x00000452
9462 16:44:22.124935 TIME STAMP 5. 0xfff7a000 0x00000910
9463 16:44:22.127882 VBOOT WORK 6. 0xfff66000 0x00014000
9464 16:44:22.131650 RAMOOPS 7. 0xffe66000 0x00100000
9465 16:44:22.134704 COREBOOT 8. 0xffe64000 0x00002000
9466 16:44:22.134800 IMD small region:
9467 16:44:22.137657 IMD ROOT 0. 0xffffec00 0x00000400
9468 16:44:22.141058 VPD 1. 0xffffeba0 0x0000004c
9469 16:44:22.144241 MMC STATUS 2. 0xffffeb80 0x00000004
9470 16:44:22.151028 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9471 16:44:22.154339 Probing TPM: done!
9472 16:44:22.157861 Connected to device vid:did:rid of 1ae0:0028:00
9473 16:44:22.167860 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9474 16:44:22.171042 Initialized TPM device CR50 revision 0
9475 16:44:22.174586 Checking cr50 for pending updates
9476 16:44:22.177671 Reading cr50 TPM mode
9477 16:44:22.186175 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9478 16:44:22.192837 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9479 16:44:22.233025 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9480 16:44:22.236542 Checking segment from ROM address 0x40100000
9481 16:44:22.239659 Checking segment from ROM address 0x4010001c
9482 16:44:22.246146 Loading segment from ROM address 0x40100000
9483 16:44:22.246313 code (compression=0)
9484 16:44:22.256347 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9485 16:44:22.262494 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9486 16:44:22.262624 it's not compressed!
9487 16:44:22.269276 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9488 16:44:22.275678 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9489 16:44:22.293309 Loading segment from ROM address 0x4010001c
9490 16:44:22.293464 Entry Point 0x80000000
9491 16:44:22.296658 Loaded segments
9492 16:44:22.300311 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9493 16:44:22.307142 Jumping to boot code at 0x80000000(0xffe64000)
9494 16:44:22.313182 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9495 16:44:22.320345 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9496 16:44:22.327828 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9497 16:44:22.331419 Checking segment from ROM address 0x40100000
9498 16:44:22.334550 Checking segment from ROM address 0x4010001c
9499 16:44:22.341240 Loading segment from ROM address 0x40100000
9500 16:44:22.341371 code (compression=1)
9501 16:44:22.347915 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9502 16:44:22.357724 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9503 16:44:22.357874 using LZMA
9504 16:44:22.366629 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9505 16:44:22.372922 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9506 16:44:22.376328 Loading segment from ROM address 0x4010001c
9507 16:44:22.376442 Entry Point 0x54601000
9508 16:44:22.379910 Loaded segments
9509 16:44:22.382668 NOTICE: MT8192 bl31_setup
9510 16:44:22.390198 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9511 16:44:22.393092 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9512 16:44:22.396624 WARNING: region 0:
9513 16:44:22.400165 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9514 16:44:22.400306 WARNING: region 1:
9515 16:44:22.406507 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9516 16:44:22.409509 WARNING: region 2:
9517 16:44:22.413305 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9518 16:44:22.416161 WARNING: region 3:
9519 16:44:22.419894 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9520 16:44:22.422816 WARNING: region 4:
9521 16:44:22.429595 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9522 16:44:22.429752 WARNING: region 5:
9523 16:44:22.433055 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9524 16:44:22.436323 WARNING: region 6:
9525 16:44:22.439405 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9526 16:44:22.442606 WARNING: region 7:
9527 16:44:22.446424 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9528 16:44:22.452797 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9529 16:44:22.456520 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9530 16:44:22.459604 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9531 16:44:22.466449 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9532 16:44:22.469233 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9533 16:44:22.475911 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9534 16:44:22.479235 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9535 16:44:22.482547 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9536 16:44:22.489504 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9537 16:44:22.492756 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9538 16:44:22.496288 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9539 16:44:22.502940 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9540 16:44:22.506142 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9541 16:44:22.512665 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9542 16:44:22.516168 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9543 16:44:22.519184 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9544 16:44:22.525879 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9545 16:44:22.528869 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9546 16:44:22.532617 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9547 16:44:22.538937 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9548 16:44:22.542461 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9549 16:44:22.548960 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9550 16:44:22.552679 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9551 16:44:22.555679 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9552 16:44:22.562182 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9553 16:44:22.565994 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9554 16:44:22.572559 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9555 16:44:22.575767 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9556 16:44:22.579234 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9557 16:44:22.585714 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9558 16:44:22.589042 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9559 16:44:22.595277 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9560 16:44:22.598726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9561 16:44:22.602051 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9562 16:44:22.605484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9563 16:44:22.612091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9564 16:44:22.615274 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9565 16:44:22.618495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9566 16:44:22.622053 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9567 16:44:22.628382 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9568 16:44:22.632074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9569 16:44:22.635222 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9570 16:44:22.638235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9571 16:44:22.644819 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9572 16:44:22.648270 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9573 16:44:22.652111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9574 16:44:22.655108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9575 16:44:22.661684 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9576 16:44:22.664805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9577 16:44:22.671669 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9578 16:44:22.675174 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9579 16:44:22.681645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9580 16:44:22.684693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9581 16:44:22.688086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9582 16:44:22.694755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9583 16:44:22.698472 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9584 16:44:22.704997 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9585 16:44:22.708355 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9586 16:44:22.714619 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9587 16:44:22.718085 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9588 16:44:22.721519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9589 16:44:22.728578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9590 16:44:22.731295 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9591 16:44:22.737951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9592 16:44:22.741644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9593 16:44:22.748278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9594 16:44:22.751359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9595 16:44:22.754590 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9596 16:44:22.761338 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9597 16:44:22.764778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9598 16:44:22.771399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9599 16:44:22.774567 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9600 16:44:22.781083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9601 16:44:22.784252 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9602 16:44:22.791368 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9603 16:44:22.794341 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9604 16:44:22.798073 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9605 16:44:22.803981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9606 16:44:22.807551 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9607 16:44:22.814337 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9608 16:44:22.817980 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9609 16:44:22.824615 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9610 16:44:22.827525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9611 16:44:22.830928 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9612 16:44:22.837521 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9613 16:44:22.841369 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9614 16:44:22.848132 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9615 16:44:22.851035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9616 16:44:22.857195 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9617 16:44:22.861096 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9618 16:44:22.867233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9619 16:44:22.870777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9620 16:44:22.874154 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9621 16:44:22.880541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9622 16:44:22.884262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9623 16:44:22.890858 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9624 16:44:22.893961 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9625 16:44:22.897334 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9626 16:44:22.903507 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9627 16:44:22.907251 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9628 16:44:22.910166 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9629 16:44:22.917200 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9630 16:44:22.920042 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9631 16:44:22.923444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9632 16:44:22.930244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9633 16:44:22.933217 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9634 16:44:22.939833 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9635 16:44:22.943489 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9636 16:44:22.946528 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9637 16:44:22.953405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9638 16:44:22.956664 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9639 16:44:22.963404 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9640 16:44:22.966661 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9641 16:44:22.969625 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9642 16:44:22.976062 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9643 16:44:22.979864 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9644 16:44:22.983263 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9645 16:44:22.989417 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9646 16:44:22.993001 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9647 16:44:22.996131 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9648 16:44:23.003037 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9649 16:44:23.006006 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9650 16:44:23.009821 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9651 16:44:23.012863 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9652 16:44:23.019531 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9653 16:44:23.023044 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9654 16:44:23.029610 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9655 16:44:23.032588 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9656 16:44:23.036075 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9657 16:44:23.042755 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9658 16:44:23.045678 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9659 16:44:23.052803 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9660 16:44:23.055702 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9661 16:44:23.059432 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9662 16:44:23.065627 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9663 16:44:23.069161 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9664 16:44:23.075876 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9665 16:44:23.078887 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9666 16:44:23.082582 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9667 16:44:23.088787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9668 16:44:23.092306 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9669 16:44:23.098908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9670 16:44:23.102642 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9671 16:44:23.105766 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9672 16:44:23.112239 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9673 16:44:23.115884 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9674 16:44:23.119026 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9675 16:44:23.125849 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9676 16:44:23.128671 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9677 16:44:23.135717 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9678 16:44:23.138973 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9679 16:44:23.142145 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9680 16:44:23.149012 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9681 16:44:23.152525 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9682 16:44:23.159101 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9683 16:44:23.162021 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9684 16:44:23.165753 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9685 16:44:23.172002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9686 16:44:23.175216 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9687 16:44:23.181651 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9688 16:44:23.184853 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9689 16:44:23.188451 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9690 16:44:23.194724 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9691 16:44:23.198056 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9692 16:44:23.204866 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9693 16:44:23.208457 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9694 16:44:23.211436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9695 16:44:23.218324 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9696 16:44:23.221492 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9697 16:44:23.228202 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9698 16:44:23.231351 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9699 16:44:23.234424 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9700 16:44:23.241056 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9701 16:44:23.244458 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9702 16:44:23.251031 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9703 16:44:23.253986 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9704 16:44:23.257446 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9705 16:44:23.264268 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9706 16:44:23.267111 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9707 16:44:23.273894 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9708 16:44:23.277044 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9709 16:44:23.280697 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9710 16:44:23.286976 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9711 16:44:23.290700 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9712 16:44:23.296886 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9713 16:44:23.300474 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9714 16:44:23.303948 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9715 16:44:23.310182 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9716 16:44:23.313506 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9717 16:44:23.320245 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9718 16:44:23.323363 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9719 16:44:23.330130 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9720 16:44:23.333223 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9721 16:44:23.336861 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9722 16:44:23.343570 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9723 16:44:23.346560 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9724 16:44:23.353008 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9725 16:44:23.356479 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9726 16:44:23.362802 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9727 16:44:23.366319 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9728 16:44:23.369898 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9729 16:44:23.376011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9730 16:44:23.379686 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9731 16:44:23.385906 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9732 16:44:23.389352 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9733 16:44:23.396295 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9734 16:44:23.399348 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9735 16:44:23.402981 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9736 16:44:23.408953 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9737 16:44:23.412385 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9738 16:44:23.419317 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9739 16:44:23.422724 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9740 16:44:23.425913 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9741 16:44:23.432443 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9742 16:44:23.436015 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9743 16:44:23.442166 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9744 16:44:23.445854 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9745 16:44:23.452356 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9746 16:44:23.455298 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9747 16:44:23.459269 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9748 16:44:23.465796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9749 16:44:23.468679 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9750 16:44:23.475094 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9751 16:44:23.478794 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9752 16:44:23.485078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9753 16:44:23.488732 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9754 16:44:23.491664 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9755 16:44:23.498525 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9756 16:44:23.501683 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9757 16:44:23.505355 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9758 16:44:23.512041 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9759 16:44:23.514908 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9760 16:44:23.518307 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9761 16:44:23.521700 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9762 16:44:23.527940 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9763 16:44:23.531426 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9764 16:44:23.538157 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9765 16:44:23.541150 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9766 16:44:23.544882 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9767 16:44:23.551465 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9768 16:44:23.554509 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9769 16:44:23.557566 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9770 16:44:23.564687 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9771 16:44:23.567565 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9772 16:44:23.571038 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9773 16:44:23.577573 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9774 16:44:23.581028 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9775 16:44:23.587868 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9776 16:44:23.590864 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9777 16:44:23.593879 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9778 16:44:23.600730 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9779 16:44:23.603786 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9780 16:44:23.610330 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9781 16:44:23.613994 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9782 16:44:23.616935 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9783 16:44:23.623542 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9784 16:44:23.626888 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9785 16:44:23.633224 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9786 16:44:23.636918 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9787 16:44:23.639769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9788 16:44:23.646471 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9789 16:44:23.650067 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9790 16:44:23.653089 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9791 16:44:23.659592 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9792 16:44:23.662924 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9793 16:44:23.666553 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9794 16:44:23.672928 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9795 16:44:23.676676 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9796 16:44:23.679704 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9797 16:44:23.686752 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9798 16:44:23.689588 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9799 16:44:23.692962 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9800 16:44:23.695984 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9801 16:44:23.702534 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9802 16:44:23.706312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9803 16:44:23.709313 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9804 16:44:23.713106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9805 16:44:23.719514 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9806 16:44:23.722670 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9807 16:44:23.725671 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9808 16:44:23.732550 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9809 16:44:23.735533 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9810 16:44:23.738809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9811 16:44:23.745287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9812 16:44:23.748712 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9813 16:44:23.755663 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9814 16:44:23.758583 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9815 16:44:23.762035 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9816 16:44:23.768748 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9817 16:44:23.771753 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9818 16:44:23.778480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9819 16:44:23.781707 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9820 16:44:23.785226 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9821 16:44:23.791639 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9822 16:44:23.794756 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9823 16:44:23.801336 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9824 16:44:23.804938 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9825 16:44:23.811180 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9826 16:44:23.814825 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9827 16:44:23.818246 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9828 16:44:23.824879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9829 16:44:23.827802 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9830 16:44:23.834346 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9831 16:44:23.837943 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9832 16:44:23.844103 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9833 16:44:23.847816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9834 16:44:23.850778 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9835 16:44:23.857604 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9836 16:44:23.860963 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9837 16:44:23.867298 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9838 16:44:23.870570 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9839 16:44:23.874104 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9840 16:44:23.880795 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9841 16:44:23.883875 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9842 16:44:23.890663 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9843 16:44:23.893864 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9844 16:44:23.900477 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9845 16:44:23.903447 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9846 16:44:23.906919 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9847 16:44:23.913482 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9848 16:44:23.916590 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9849 16:44:23.923439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9850 16:44:23.926303 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9851 16:44:23.933087 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9852 16:44:23.936246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9853 16:44:23.939795 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9854 16:44:23.946520 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9855 16:44:23.949685 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9856 16:44:23.956246 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9857 16:44:23.959226 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9858 16:44:23.962848 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9859 16:44:23.969245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9860 16:44:23.972554 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9861 16:44:23.979069 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9862 16:44:23.982926 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9863 16:44:23.988918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9864 16:44:23.992326 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9865 16:44:23.995952 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9866 16:44:24.002552 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9867 16:44:24.005572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9868 16:44:24.011986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9869 16:44:24.015570 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9870 16:44:24.021704 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9871 16:44:24.025228 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9872 16:44:24.028821 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9873 16:44:24.035163 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9874 16:44:24.038328 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9875 16:44:24.044894 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9876 16:44:24.048492 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9877 16:44:24.051784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9878 16:44:24.058416 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9879 16:44:24.061572 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9880 16:44:24.068121 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9881 16:44:24.071070 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9882 16:44:24.077984 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9883 16:44:24.081358 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9884 16:44:24.087963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9885 16:44:24.090919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9886 16:44:24.094179 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9887 16:44:24.100870 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9888 16:44:24.104410 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9889 16:44:24.111117 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9890 16:44:24.114190 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9891 16:44:24.120998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9892 16:44:24.123875 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9893 16:44:24.127556 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9894 16:44:24.134194 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9895 16:44:24.137703 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9896 16:44:24.143705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9897 16:44:24.147290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9898 16:44:24.153474 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9899 16:44:24.157248 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9900 16:44:24.163908 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9901 16:44:24.166756 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9902 16:44:24.173785 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9903 16:44:24.177038 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9904 16:44:24.179918 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9905 16:44:24.186631 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9906 16:44:24.189846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9907 16:44:24.196877 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9908 16:44:24.199722 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9909 16:44:24.206566 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9910 16:44:24.209503 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9911 16:44:24.216571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9912 16:44:24.219380 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9913 16:44:24.222989 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9914 16:44:24.229331 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9915 16:44:24.232842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9916 16:44:24.239433 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9917 16:44:24.242346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9918 16:44:24.249133 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9919 16:44:24.252743 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9920 16:44:24.258788 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9921 16:44:24.262484 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9922 16:44:24.265518 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9923 16:44:24.272042 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9924 16:44:24.275651 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9925 16:44:24.281859 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9926 16:44:24.285569 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9927 16:44:24.292107 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9928 16:44:24.295633 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9929 16:44:24.298499 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9930 16:44:24.305249 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9931 16:44:24.308464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9932 16:44:24.315004 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9933 16:44:24.318497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9934 16:44:24.325200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9935 16:44:24.328508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9936 16:44:24.334845 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9937 16:44:24.338194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9938 16:44:24.344614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9939 16:44:24.348246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9940 16:44:24.354769 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9941 16:44:24.357746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9942 16:44:24.364538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9943 16:44:24.367763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9944 16:44:24.374176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9945 16:44:24.377799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9946 16:44:24.384505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9947 16:44:24.387860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9948 16:44:24.394085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9949 16:44:24.397226 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9950 16:44:24.404375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9951 16:44:24.407342 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9952 16:44:24.413822 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9953 16:44:24.417547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9954 16:44:24.423480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9955 16:44:24.427156 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9956 16:44:24.433275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9957 16:44:24.436581 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9958 16:44:24.443132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9959 16:44:24.446729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9960 16:44:24.453268 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9961 16:44:24.456320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9962 16:44:24.462908 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9963 16:44:24.463033 INFO: [APUAPC] vio 0
9964 16:44:24.469629 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9965 16:44:24.473250 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9966 16:44:24.476258 INFO: [APUAPC] D0_APC_0: 0x400510
9967 16:44:24.479894 INFO: [APUAPC] D0_APC_1: 0x0
9968 16:44:24.482966 INFO: [APUAPC] D0_APC_2: 0x1540
9969 16:44:24.486610 INFO: [APUAPC] D0_APC_3: 0x0
9970 16:44:24.489648 INFO: [APUAPC] D1_APC_0: 0xffffffff
9971 16:44:24.492635 INFO: [APUAPC] D1_APC_1: 0xffffffff
9972 16:44:24.496254 INFO: [APUAPC] D1_APC_2: 0x3fffff
9973 16:44:24.499818 INFO: [APUAPC] D1_APC_3: 0x0
9974 16:44:24.502893 INFO: [APUAPC] D2_APC_0: 0xffffffff
9975 16:44:24.505897 INFO: [APUAPC] D2_APC_1: 0xffffffff
9976 16:44:24.509638 INFO: [APUAPC] D2_APC_2: 0x3fffff
9977 16:44:24.512615 INFO: [APUAPC] D2_APC_3: 0x0
9978 16:44:24.516348 INFO: [APUAPC] D3_APC_0: 0xffffffff
9979 16:44:24.519334 INFO: [APUAPC] D3_APC_1: 0xffffffff
9980 16:44:24.522391 INFO: [APUAPC] D3_APC_2: 0x3fffff
9981 16:44:24.526108 INFO: [APUAPC] D3_APC_3: 0x0
9982 16:44:24.529040 INFO: [APUAPC] D4_APC_0: 0xffffffff
9983 16:44:24.532790 INFO: [APUAPC] D4_APC_1: 0xffffffff
9984 16:44:24.535928 INFO: [APUAPC] D4_APC_2: 0x3fffff
9985 16:44:24.539337 INFO: [APUAPC] D4_APC_3: 0x0
9986 16:44:24.542319 INFO: [APUAPC] D5_APC_0: 0xffffffff
9987 16:44:24.545520 INFO: [APUAPC] D5_APC_1: 0xffffffff
9988 16:44:24.548810 INFO: [APUAPC] D5_APC_2: 0x3fffff
9989 16:44:24.552180 INFO: [APUAPC] D5_APC_3: 0x0
9990 16:44:24.555355 INFO: [APUAPC] D6_APC_0: 0xffffffff
9991 16:44:24.558737 INFO: [APUAPC] D6_APC_1: 0xffffffff
9992 16:44:24.561847 INFO: [APUAPC] D6_APC_2: 0x3fffff
9993 16:44:24.561952 INFO: [APUAPC] D6_APC_3: 0x0
9994 16:44:24.568475 INFO: [APUAPC] D7_APC_0: 0xffffffff
9995 16:44:24.571843 INFO: [APUAPC] D7_APC_1: 0xffffffff
9996 16:44:24.574959 INFO: [APUAPC] D7_APC_2: 0x3fffff
9997 16:44:24.575055 INFO: [APUAPC] D7_APC_3: 0x0
9998 16:44:24.578605 INFO: [APUAPC] D8_APC_0: 0xffffffff
9999 16:44:24.584979 INFO: [APUAPC] D8_APC_1: 0xffffffff
10000 16:44:24.588631 INFO: [APUAPC] D8_APC_2: 0x3fffff
10001 16:44:24.588740 INFO: [APUAPC] D8_APC_3: 0x0
10002 16:44:24.591802 INFO: [APUAPC] D9_APC_0: 0xffffffff
10003 16:44:24.595273 INFO: [APUAPC] D9_APC_1: 0xffffffff
10004 16:44:24.598244 INFO: [APUAPC] D9_APC_2: 0x3fffff
10005 16:44:24.601826 INFO: [APUAPC] D9_APC_3: 0x0
10006 16:44:24.604754 INFO: [APUAPC] D10_APC_0: 0xffffffff
10007 16:44:24.608423 INFO: [APUAPC] D10_APC_1: 0xffffffff
10008 16:44:24.614636 INFO: [APUAPC] D10_APC_2: 0x3fffff
10009 16:44:24.614781 INFO: [APUAPC] D10_APC_3: 0x0
10010 16:44:24.618057 INFO: [APUAPC] D11_APC_0: 0xffffffff
10011 16:44:24.624672 INFO: [APUAPC] D11_APC_1: 0xffffffff
10012 16:44:24.627687 INFO: [APUAPC] D11_APC_2: 0x3fffff
10013 16:44:24.627813 INFO: [APUAPC] D11_APC_3: 0x0
10014 16:44:24.634804 INFO: [APUAPC] D12_APC_0: 0xffffffff
10015 16:44:24.637766 INFO: [APUAPC] D12_APC_1: 0xffffffff
10016 16:44:24.641311 INFO: [APUAPC] D12_APC_2: 0x3fffff
10017 16:44:24.644442 INFO: [APUAPC] D12_APC_3: 0x0
10018 16:44:24.647803 INFO: [APUAPC] D13_APC_0: 0xffffffff
10019 16:44:24.650922 INFO: [APUAPC] D13_APC_1: 0xffffffff
10020 16:44:24.654510 INFO: [APUAPC] D13_APC_2: 0x3fffff
10021 16:44:24.657751 INFO: [APUAPC] D13_APC_3: 0x0
10022 16:44:24.661019 INFO: [APUAPC] D14_APC_0: 0xffffffff
10023 16:44:24.663993 INFO: [APUAPC] D14_APC_1: 0xffffffff
10024 16:44:24.667469 INFO: [APUAPC] D14_APC_2: 0x3fffff
10025 16:44:24.670871 INFO: [APUAPC] D14_APC_3: 0x0
10026 16:44:24.673823 INFO: [APUAPC] D15_APC_0: 0xffffffff
10027 16:44:24.676975 INFO: [APUAPC] D15_APC_1: 0xffffffff
10028 16:44:24.680280 INFO: [APUAPC] D15_APC_2: 0x3fffff
10029 16:44:24.683775 INFO: [APUAPC] D15_APC_3: 0x0
10030 16:44:24.687418 INFO: [APUAPC] APC_CON: 0x4
10031 16:44:24.687546 INFO: [NOCDAPC] D0_APC_0: 0x0
10032 16:44:24.690311 INFO: [NOCDAPC] D0_APC_1: 0x0
10033 16:44:24.693951 INFO: [NOCDAPC] D1_APC_0: 0x0
10034 16:44:24.697085 INFO: [NOCDAPC] D1_APC_1: 0xfff
10035 16:44:24.700070 INFO: [NOCDAPC] D2_APC_0: 0x0
10036 16:44:24.703737 INFO: [NOCDAPC] D2_APC_1: 0xfff
10037 16:44:24.706687 INFO: [NOCDAPC] D3_APC_0: 0x0
10038 16:44:24.710144 INFO: [NOCDAPC] D3_APC_1: 0xfff
10039 16:44:24.713210 INFO: [NOCDAPC] D4_APC_0: 0x0
10040 16:44:24.717002 INFO: [NOCDAPC] D4_APC_1: 0xfff
10041 16:44:24.719935 INFO: [NOCDAPC] D5_APC_0: 0x0
10042 16:44:24.720039 INFO: [NOCDAPC] D5_APC_1: 0xfff
10043 16:44:24.723453 INFO: [NOCDAPC] D6_APC_0: 0x0
10044 16:44:24.726636 INFO: [NOCDAPC] D6_APC_1: 0xfff
10045 16:44:24.730467 INFO: [NOCDAPC] D7_APC_0: 0x0
10046 16:44:24.733559 INFO: [NOCDAPC] D7_APC_1: 0xfff
10047 16:44:24.736426 INFO: [NOCDAPC] D8_APC_0: 0x0
10048 16:44:24.740175 INFO: [NOCDAPC] D8_APC_1: 0xfff
10049 16:44:24.743295 INFO: [NOCDAPC] D9_APC_0: 0x0
10050 16:44:24.746159 INFO: [NOCDAPC] D9_APC_1: 0xfff
10051 16:44:24.749990 INFO: [NOCDAPC] D10_APC_0: 0x0
10052 16:44:24.752736 INFO: [NOCDAPC] D10_APC_1: 0xfff
10053 16:44:24.756349 INFO: [NOCDAPC] D11_APC_0: 0x0
10054 16:44:24.759377 INFO: [NOCDAPC] D11_APC_1: 0xfff
10055 16:44:24.763087 INFO: [NOCDAPC] D12_APC_0: 0x0
10056 16:44:24.766162 INFO: [NOCDAPC] D12_APC_1: 0xfff
10057 16:44:24.766261 INFO: [NOCDAPC] D13_APC_0: 0x0
10058 16:44:24.768995 INFO: [NOCDAPC] D13_APC_1: 0xfff
10059 16:44:24.772656 INFO: [NOCDAPC] D14_APC_0: 0x0
10060 16:44:24.775589 INFO: [NOCDAPC] D14_APC_1: 0xfff
10061 16:44:24.778963 INFO: [NOCDAPC] D15_APC_0: 0x0
10062 16:44:24.782593 INFO: [NOCDAPC] D15_APC_1: 0xfff
10063 16:44:24.785726 INFO: [NOCDAPC] APC_CON: 0x4
10064 16:44:24.789007 INFO: [APUAPC] set_apusys_apc done
10065 16:44:24.792428 INFO: [DEVAPC] devapc_init done
10066 16:44:24.796010 INFO: GICv3 without legacy support detected.
10067 16:44:24.799128 INFO: ARM GICv3 driver initialized in EL3
10068 16:44:24.805803 INFO: Maximum SPI INTID supported: 639
10069 16:44:24.808854 INFO: BL31: Initializing runtime services
10070 16:44:24.815314 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10071 16:44:24.815508 INFO: SPM: enable CPC mode
10072 16:44:24.822059 INFO: mcdi ready for mcusys-off-idle and system suspend
10073 16:44:24.825308 INFO: BL31: Preparing for EL3 exit to normal world
10074 16:44:24.828890 INFO: Entry point address = 0x80000000
10075 16:44:24.832119 INFO: SPSR = 0x8
10076 16:44:24.837822
10077 16:44:24.837963
10078 16:44:24.838039
10079 16:44:24.841457 Starting depthcharge on Spherion...
10080 16:44:24.841571
10081 16:44:24.841641 Wipe memory regions:
10082 16:44:24.841728
10083 16:44:24.842616 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10084 16:44:24.842759 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10085 16:44:24.842888 Setting prompt string to ['asurada:']
10086 16:44:24.843295 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10087 16:44:24.844604 [0x00000040000000, 0x00000054600000)
10088 16:44:24.966731
10089 16:44:24.966898 [0x00000054660000, 0x00000080000000)
10090 16:44:25.227392
10091 16:44:25.227558 [0x000000821a7280, 0x000000ffe64000)
10092 16:44:25.972013
10093 16:44:25.972151 [0x00000100000000, 0x00000240000000)
10094 16:44:27.862887
10095 16:44:27.866022 Initializing XHCI USB controller at 0x11200000.
10096 16:44:28.904200
10097 16:44:28.907524 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10098 16:44:28.907657
10099 16:44:28.907727
10100 16:44:28.907791
10101 16:44:28.908075 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10103 16:44:29.008424 asurada: tftpboot 192.168.201.1 10576281/tftp-deploy-522scxlt/kernel/image.itb 10576281/tftp-deploy-522scxlt/kernel/cmdline
10104 16:44:29.008587 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10105 16:44:29.008684 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10106 16:44:29.013420 tftpboot 192.168.201.1 10576281/tftp-deploy-522scxlt/kernel/image.itp-deploy-522scxlt/kernel/cmdline
10107 16:44:29.013514
10108 16:44:29.013582 Waiting for link
10109 16:44:29.173428
10110 16:44:29.173570 R8152: Initializing
10111 16:44:29.173640
10112 16:44:29.176983 Version 6 (ocp_data = 5c30)
10113 16:44:29.177077
10114 16:44:29.180440 R8152: Done initializing
10115 16:44:29.180526
10116 16:44:29.180595 Adding net device
10117 16:44:31.036320
10118 16:44:31.036457 done.
10119 16:44:31.036526
10120 16:44:31.036587 MAC: 00:24:32:30:78:ff
10121 16:44:31.036648
10122 16:44:31.039990 Sending DHCP discover... done.
10123 16:44:31.040075
10124 16:44:31.043100 Waiting for reply... done.
10125 16:44:31.043209
10126 16:44:31.046112 Sending DHCP request... done.
10127 16:44:31.046209
10128 16:44:31.052008 Waiting for reply... done.
10129 16:44:31.052112
10130 16:44:31.052193 My ip is 192.168.201.21
10131 16:44:31.052269
10132 16:44:31.054977 The DHCP server ip is 192.168.201.1
10133 16:44:31.055080
10134 16:44:31.061456 TFTP server IP predefined by user: 192.168.201.1
10135 16:44:31.061581
10136 16:44:31.068422 Bootfile predefined by user: 10576281/tftp-deploy-522scxlt/kernel/image.itb
10137 16:44:31.068569
10138 16:44:31.071548 Sending tftp read request... done.
10139 16:44:31.071726
10140 16:44:31.075642 Waiting for the transfer...
10141 16:44:31.075819
10142 16:44:31.642841 00000000 ################################################################
10143 16:44:31.642979
10144 16:44:32.183525 00080000 ################################################################
10145 16:44:32.183718
10146 16:44:32.738676 00100000 ################################################################
10147 16:44:32.738812
10148 16:44:33.294766 00180000 ################################################################
10149 16:44:33.294910
10150 16:44:33.823544 00200000 ################################################################
10151 16:44:33.823735
10152 16:44:34.356705 00280000 ################################################################
10153 16:44:34.356880
10154 16:44:34.932729 00300000 ################################################################
10155 16:44:34.933312
10156 16:44:35.616773 00380000 ################################################################
10157 16:44:35.617364
10158 16:44:36.270774 00400000 ################################################################
10159 16:44:36.270913
10160 16:44:36.913771 00480000 ################################################################
10161 16:44:36.913942
10162 16:44:37.511422 00500000 ################################################################
10163 16:44:37.511627
10164 16:44:38.064235 00580000 ################################################################
10165 16:44:38.064373
10166 16:44:38.612959 00600000 ################################################################
10167 16:44:38.613142
10168 16:44:39.229270 00680000 ################################################################
10169 16:44:39.229429
10170 16:44:39.784938 00700000 ################################################################
10171 16:44:39.785123
10172 16:44:40.417179 00780000 ################################################################
10173 16:44:40.417837
10174 16:44:41.057622 00800000 ################################################################
10175 16:44:41.058342
10176 16:44:41.721234 00880000 ################################################################
10177 16:44:41.721392
10178 16:44:42.357543 00900000 ################################################################
10179 16:44:42.357697
10180 16:44:42.915122 00980000 ################################################################
10181 16:44:42.915257
10182 16:44:43.489399 00a00000 ################################################################
10183 16:44:43.489995
10184 16:44:44.134684 00a80000 ################################################################
10185 16:44:44.134840
10186 16:44:44.730264 00b00000 ################################################################
10187 16:44:44.730407
10188 16:44:45.287478 00b80000 ################################################################
10189 16:44:45.287667
10190 16:44:45.841223 00c00000 ################################################################
10191 16:44:45.841358
10192 16:44:46.380559 00c80000 ################################################################
10193 16:44:46.380830
10194 16:44:46.980888 00d00000 ################################################################
10195 16:44:46.981582
10196 16:44:47.567620 00d80000 ################################################################
10197 16:44:47.567757
10198 16:44:48.102150 00e00000 ################################################################
10199 16:44:48.102321
10200 16:44:48.636376 00e80000 ################################################################
10201 16:44:48.636537
10202 16:44:49.183721 00f00000 ################################################################
10203 16:44:49.183898
10204 16:44:49.724111 00f80000 ################################################################
10205 16:44:49.724250
10206 16:44:50.251463 01000000 ################################################################
10207 16:44:50.251649
10208 16:44:50.775386 01080000 ################################################################
10209 16:44:50.775556
10210 16:44:51.298922 01100000 ################################################################
10211 16:44:51.299088
10212 16:44:51.917544 01180000 ################################################################
10213 16:44:51.917701
10214 16:44:52.580625 01200000 ################################################################
10215 16:44:52.581525
10216 16:44:53.270249 01280000 ################################################################
10217 16:44:53.270908
10218 16:44:53.972981 01300000 ################################################################
10219 16:44:53.973160
10220 16:44:54.638855 01380000 ################################################################
10221 16:44:54.639400
10222 16:44:55.337061 01400000 ################################################################
10223 16:44:55.337586
10224 16:44:56.009282 01480000 ################################################################
10225 16:44:56.009872
10226 16:44:56.656005 01500000 ################################################################
10227 16:44:56.656595
10228 16:44:57.334179 01580000 ################################################################
10229 16:44:57.334709
10230 16:44:57.992256 01600000 ################################################################
10231 16:44:57.992964
10232 16:44:58.642416 01680000 ################################################################
10233 16:44:58.642931
10234 16:44:59.295766 01700000 ################################################################
10235 16:44:59.295981
10236 16:44:59.919190 01780000 ################################################################
10237 16:44:59.919729
10238 16:45:00.501874 01800000 ################################################################
10239 16:45:00.502447
10240 16:45:01.161557 01880000 ################################################################
10241 16:45:01.162197
10242 16:45:01.777818 01900000 ################################################################
10243 16:45:01.777995
10244 16:45:02.390709 01980000 ################################################################
10245 16:45:02.390849
10246 16:45:03.048125 01a00000 ############################################################### done.
10247 16:45:03.048283
10248 16:45:03.051308 The bootfile was 27775530 bytes long.
10249 16:45:03.051397
10250 16:45:03.054425 Sending tftp read request... done.
10251 16:45:03.054512
10252 16:45:03.054597 Waiting for the transfer...
10253 16:45:03.054678
10254 16:45:03.057960 00000000 # done.
10255 16:45:03.058062
10256 16:45:03.064581 Command line loaded dynamically from TFTP file: 10576281/tftp-deploy-522scxlt/kernel/cmdline
10257 16:45:03.064668
10258 16:45:03.081026 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10259 16:45:03.081121
10260 16:45:03.084615 Loading FIT.
10261 16:45:03.084701
10262 16:45:03.087813 Image ramdisk-1 has 17643100 bytes.
10263 16:45:03.087899
10264 16:45:03.087984 Image fdt-1 has 46924 bytes.
10265 16:45:03.090996
10266 16:45:03.091087 Image kernel-1 has 10083474 bytes.
10267 16:45:03.091178
10268 16:45:03.101268 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10269 16:45:03.101471
10270 16:45:03.117280 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10271 16:45:03.121197
10272 16:45:03.124260 Choosing best match conf-1 for compat google,spherion-rev2.
10273 16:45:03.128642
10274 16:45:03.132417 Connected to device vid:did:rid of 1ae0:0028:00
10275 16:45:03.139551
10276 16:45:03.143213 tpm_get_response: command 0x17b, return code 0x0
10277 16:45:03.143297
10278 16:45:03.146255 ec_init: CrosEC protocol v3 supported (256, 248)
10279 16:45:03.150513
10280 16:45:03.154184 tpm_cleanup: add release locality here.
10281 16:45:03.154269
10282 16:45:03.154336 Shutting down all USB controllers.
10283 16:45:03.157150
10284 16:45:03.157233 Removing current net device
10285 16:45:03.157299
10286 16:45:03.163418 Exiting depthcharge with code 4 at timestamp: 67614808
10287 16:45:03.163502
10288 16:45:03.166990 LZMA decompressing kernel-1 to 0x821a6718
10289 16:45:03.167080
10290 16:45:03.169887 LZMA decompressing kernel-1 to 0x40000000
10291 16:45:04.487762
10292 16:45:04.488395 jumping to kernel
10293 16:45:04.489965 end: 2.2.4 bootloader-commands (duration 00:00:40) [common]
10294 16:45:04.490530 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
10295 16:45:04.490958 Setting prompt string to ['Linux version [0-9]']
10296 16:45:04.491359 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10297 16:45:04.491806 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10298 16:45:04.974206
10299 16:45:04.977749 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10300 16:45:04.981106 start: 2.2.5.1 login-action (timeout 00:03:45) [common]
10301 16:45:04.981201 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10302 16:45:04.981290 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10303 16:45:04.981366 Using line separator: #'\n'#
10304 16:45:04.981428 No login prompt set.
10305 16:45:04.981490 Parsing kernel messages
10306 16:45:04.981546 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10307 16:45:04.981652 [login-action] Waiting for messages, (timeout 00:03:45)
10308 16:45:05.000544 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10309 16:45:05.004481 [ 0.000000] random: crng init done
10310 16:45:05.011072 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10311 16:45:05.014026 [ 0.000000] efi: UEFI not found.
10312 16:45:05.020787 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10313 16:45:05.027372 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10314 16:45:05.037206 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10315 16:45:05.047023 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10316 16:45:05.050644 [ 0.000000] NUMA: No NUMA configuration found
10317 16:45:05.059987 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10318 16:45:05.063627 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10319 16:45:05.066782 [ 0.000000] Zone ranges:
10320 16:45:05.073229 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10321 16:45:05.076565 [ 0.000000] DMA32 empty
10322 16:45:05.083110 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10323 16:45:05.086502 [ 0.000000] Movable zone start for each node
10324 16:45:05.089764 [ 0.000000] Early memory node ranges
10325 16:45:05.096578 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10326 16:45:05.103284 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10327 16:45:05.109764 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10328 16:45:05.116493 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10329 16:45:05.119866 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10330 16:45:05.129465 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10331 16:45:05.132864 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10332 16:45:05.139563 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10333 16:45:05.145917 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10334 16:45:05.149608 [ 0.000000] psci: probing for conduit method from DT.
10335 16:45:05.155731 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10336 16:45:05.159323 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10337 16:45:05.166222 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10338 16:45:05.169248 [ 0.000000] psci: SMC Calling Convention v1.2
10339 16:45:05.175616 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10340 16:45:05.178985 [ 0.000000] Detected VIPT I-cache on CPU0
10341 16:45:05.185459 [ 0.000000] CPU features: detected: GIC system register CPU interface
10342 16:45:05.192280 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10343 16:45:05.198664 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10344 16:45:05.206020 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10345 16:45:05.212069 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10346 16:45:05.222067 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10347 16:45:05.225124 [ 0.000000] alternatives: applying boot alternatives
10348 16:45:05.228331 [ 0.000000] Fallback order for Node 0: 0
10349 16:45:05.235167 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10350 16:45:05.238836 [ 0.000000] Policy zone: Normal
10351 16:45:05.258059 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10352 16:45:05.268267 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10353 16:45:05.274907 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10354 16:45:05.285139 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10355 16:45:05.291558 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10356 16:45:05.294635 [ 0.000000] software IO TLB: area num 8.
10357 16:45:05.301164 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10358 16:45:05.314195 [ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10359 16:45:05.321042 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10360 16:45:05.327830 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10361 16:45:05.331032 [ 0.000000] rcu: RCU event tracing is enabled.
10362 16:45:05.337366 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10363 16:45:05.344098 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10364 16:45:05.347171 [ 0.000000] Tracing variant of Tasks RCU enabled.
10365 16:45:05.357518 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10366 16:45:05.363998 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10367 16:45:05.367547 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10368 16:45:05.373598 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10369 16:45:05.377355 [ 0.000000] GICv3: 608 SPIs implemented
10370 16:45:05.384013 [ 0.000000] GICv3: 0 Extended SPIs implemented
10371 16:45:05.387090 [ 0.000000] Root IRQ handler: gic_handle_irq
10372 16:45:05.390112 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10373 16:45:05.396764 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10374 16:45:05.410102 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10375 16:45:05.420122 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10376 16:45:05.426802 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10377 16:45:05.433602 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10378 16:45:05.446565 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10379 16:45:05.453370 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10380 16:45:05.456289 [ 0.000943] Console: colour dummy device 80x25
10381 16:45:05.466437 [ 0.001011] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10382 16:45:05.472612 [ 0.001019] pid_max: default: 32768 minimum: 301
10383 16:45:05.476009 [ 0.001059] LSM: Security Framework initializing
10384 16:45:05.485792 [ 0.001162] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 16:45:05.492531 [ 0.001215] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 16:45:05.499205 [ 0.002454] cblist_init_generic: Setting adjustable number of callback queues.
10387 16:45:05.505856 [ 0.002465] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 16:45:05.512691 [ 0.002507] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 16:45:05.515527 [ 0.002611] rcu: Hierarchical SRCU implementation.
10390 16:45:05.522175 [ 0.002613] rcu: Max phase no-delay instances is 1000.
10391 16:45:05.525828 [ 0.004241] EFI services will not be available.
10392 16:45:05.532444 [ 0.004462] smp: Bringing up secondary CPUs ...
10393 16:45:05.535454 [ 0.004760] Detected VIPT I-cache on CPU1
10394 16:45:05.542182 [ 0.004832] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 16:45:05.549080 [ 0.004863] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 16:45:05.552231 [ 0.005210] Detected VIPT I-cache on CPU2
10397 16:45:05.558792 [ 0.005263] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 16:45:05.565035 [ 0.005280] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 16:45:05.569151 [ 0.005541] Detected VIPT I-cache on CPU3
10400 16:45:05.578485 [ 0.005589] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 16:45:05.581658 [ 0.005603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 16:45:05.588597 [ 0.005910] CPU features: detected: Spectre-v4
10403 16:45:05.592059 [ 0.005916] CPU features: detected: Spectre-BHB
10404 16:45:05.594918 [ 0.005921] Detected PIPT I-cache on CPU4
10405 16:45:05.605202 [ 0.005978] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 16:45:05.611369 [ 0.005995] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 16:45:05.614773 [ 0.006291] Detected PIPT I-cache on CPU5
10408 16:45:05.621650 [ 0.006355] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 16:45:05.628087 [ 0.006371] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 16:45:05.631417 [ 0.006656] Detected PIPT I-cache on CPU6
10411 16:45:05.637677 [ 0.006722] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 16:45:05.644479 [ 0.006738] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 16:45:05.648310 [ 0.007040] Detected PIPT I-cache on CPU7
10414 16:45:05.654575 [ 0.007105] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 16:45:05.661392 [ 0.007121] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 16:45:05.667525 [ 0.007169] smp: Brought up 1 node, 8 CPUs
10417 16:45:05.671417 [ 0.007174] SMP: Total of 8 processors activated.
10418 16:45:05.677500 [ 0.007177] CPU features: detected: 32-bit EL0 Support
10419 16:45:05.684165 [ 0.007180] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 16:45:05.691101 [ 0.007182] CPU features: detected: Common not Private translations
10421 16:45:05.697552 [ 0.007184] CPU features: detected: CRC32 instructions
10422 16:45:05.700909 [ 0.007187] CPU features: detected: RCpc load-acquire (LDAPR)
10423 16:45:05.707743 [ 0.007189] CPU features: detected: LSE atomic instructions
10424 16:45:05.714351 [ 0.007191] CPU features: detected: Privileged Access Never
10425 16:45:05.717174 [ 0.007192] CPU features: detected: RAS Extension Support
10426 16:45:05.726991 [ 0.007196] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 16:45:05.730471 [ 0.007264] CPU: All CPU(s) started at EL2
10428 16:45:05.733546 [ 0.007266] alternatives: applying system-wide alternatives
10429 16:45:05.736973 [ 0.012225] devtmpfs: initialized
10430 16:45:05.747047 [ 0.017371] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10431 16:45:05.756984 [ 0.017387] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10432 16:45:05.760112 [ 0.018479] pinctrl core: initialized pinctrl subsystem
10433 16:45:05.764092 [ 0.019664] DMI not present or invalid.
10434 16:45:05.770506 [ 0.020015] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10435 16:45:05.776694 [ 0.020766] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10436 16:45:05.786386 [ 0.020994] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10437 16:45:05.793380 [ 0.021175] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10438 16:45:05.799716 [ 0.021209] audit: initializing netlink subsys (disabled)
10439 16:45:05.806524 [ 0.021287] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10440 16:45:05.813412 [ 0.022001] thermal_sys: Registered thermal governor 'step_wise'
10441 16:45:05.819852 [ 0.022005] thermal_sys: Registered thermal governor 'power_allocator'
10442 16:45:05.822959 [ 0.022034] cpuidle: using governor menu
10443 16:45:05.826082 [ 0.022103] NET: Registered PF_QIPCRTR protocol family
10444 16:45:05.836446 [ 0.022252] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10445 16:45:05.839343 [ 0.022345] ASID allocator initialised with 32768 entries
10446 16:45:05.842949 [ 0.023306] Serial: AMBA PL011 UART driver
10447 16:45:05.849097 [ 0.027696] Trying to register duplicate clock ID: 134
10448 16:45:05.852715 [ 0.080000] KASLR enabled
10449 16:45:05.859331 [ 0.084839] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10450 16:45:05.866220 [ 0.084843] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10451 16:45:05.872663 [ 0.084847] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10452 16:45:05.879004 [ 0.084850] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10453 16:45:05.885707 [ 0.084853] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10454 16:45:05.892210 [ 0.084855] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10455 16:45:05.899016 [ 0.084858] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10456 16:45:05.905660 [ 0.084860] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10457 16:45:05.908547 [ 0.085839] ACPI: Interpreter disabled.
10458 16:45:05.912345 [ 0.088167] iommu: Default domain type: Translated
10459 16:45:05.918713 [ 0.088171] iommu: DMA domain TLB invalidation policy: strict mode
10460 16:45:05.921968 [ 0.088348] SCSI subsystem initialized
10461 16:45:05.928433 [ 0.088540] usbcore: registered new interface driver usbfs
10462 16:45:05.932169 [ 0.088557] usbcore: registered new interface driver hub
10463 16:45:05.938283 [ 0.088570] usbcore: registered new device driver usb
10464 16:45:05.941810 [ 0.089387] pps_core: LinuxPPS API ver. 1 registered
10465 16:45:05.951535 [ 0.089390] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10466 16:45:05.954903 [ 0.089396] PTP clock support registered
10467 16:45:05.958307 [ 0.089480] EDAC MC: Ver: 3.0.0
10468 16:45:05.961744 [ 0.091263] FPGA manager framework
10469 16:45:05.968597 [ 0.091303] Advanced Linux Sound Architecture Driver Initialized.
10470 16:45:05.971773 [ 0.091754] vgaarb: loaded
10471 16:45:05.978884 [ 0.091968] clocksource: Switched to clocksource arch_sys_counter
10472 16:45:05.982315 [ 0.092085] VFS: Disk quotas dquot_6.6.0
10473 16:45:05.989246 [ 0.092114] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10474 16:45:05.992121 [ 0.092220] pnp: PnP ACPI: disabled
10475 16:45:05.998192 [ 0.095123] NET: Registered PF_INET protocol family
10476 16:45:06.004955 [ 0.095604] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10477 16:45:06.014597 [ 0.100135] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10478 16:45:06.021494 [ 0.100208] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10479 16:45:06.027868 [ 0.100225] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10480 16:45:06.037848 [ 0.100750] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10481 16:45:06.041547 [ 0.102870] TCP: Hash tables configured (established 65536 bind 65536)
10482 16:45:06.051189 [ 0.102984] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 16:45:06.058048 [ 0.103177] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 16:45:06.061009 [ 0.103439] NET: Registered PF_UNIX/PF_LOCAL protocol family
10485 16:45:06.067761 [ 0.103647] RPC: Registered named UNIX socket transport module.
10486 16:45:06.074370 [ 0.103650] RPC: Registered udp transport module.
10487 16:45:06.077678 [ 0.103652] RPC: Registered tcp transport module.
10488 16:45:06.084239 [ 0.103654] RPC: Registered tcp NFSv4.1 backchannel transport module.
10489 16:45:06.087712 [ 0.103663] PCI: CLS 0 bytes, default 64
10490 16:45:06.091319 [ 0.103856] Unpacking initramfs...
10491 16:45:06.101009 [ 0.104486] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10492 16:45:06.107180 [ 0.104770] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10493 16:45:06.110212 [ 0.105217] kvm [1]: IPA Size Limit: 40 bits
10494 16:45:06.116762 [ 0.105240] kvm [1]: GICv3: no GICV resource entry
10495 16:45:06.120059 [ 0.105245] kvm [1]: disabling GICv2 emulation
10496 16:45:06.126603 [ 0.105257] kvm [1]: GIC system register CPU interface enabled
10497 16:45:06.130213 [ 0.105349] kvm [1]: vgic interrupt IRQ18
10498 16:45:06.136956 [ 0.105451] kvm [1]: VHE mode initialized successfully
10499 16:45:06.139775 [ 0.106357] Initialise system trusted keyrings
10500 16:45:06.146387 [ 0.106456] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10501 16:45:06.152959 [ 0.109784] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10502 16:45:06.156695 [ 0.110110] NFS: Registering the id_resolver key type
10503 16:45:06.162862 [ 0.110127] Key type id_resolver registered
10504 16:45:06.166736 [ 0.110129] Key type id_legacy registered
10505 16:45:06.172865 [ 0.110167] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10506 16:45:06.179658 [ 0.110170] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10507 16:45:06.186391 [ 0.110252] 9p: Installing v9fs 9p2000 file system support
10508 16:45:06.189605 [ 0.142172] Key type asymmetric registered
10509 16:45:06.193281 [ 0.142175] Asymmetric key parser 'x509' registered
10510 16:45:06.202517 [ 0.142214] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10511 16:45:06.206171 [ 0.142219] io scheduler mq-deadline registered
10512 16:45:06.209321 [ 0.142223] io scheduler kyber registered
10513 16:45:06.212511 [ 0.154718] EINJ: ACPI disabled.
10514 16:45:06.222436 [ 0.176842] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 16:45:06.232989 [ 0.176980] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 16:45:06.239385 [ 0.186972] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10517 16:45:06.245642 [ 0.188325] printk: console [ttyS0] disabled
10518 16:45:06.252810 [ 0.208482] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10519 16:45:06.259190 [ 0.874006] Freeing initrd memory: 17224K
10520 16:45:06.262182 [ 0.874575] printk: console [ttyS0] enabled
10521 16:45:06.268640 [ 1.499002] SuperH (H)SCI(F) driver initialized
10522 16:45:06.272501 [ 1.504014] msm_serial: driver initialized
10523 16:45:06.285387 [ 1.512577] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10524 16:45:06.291636 [ 1.520858] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10525 16:45:06.301528 [ 1.529139] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10526 16:45:06.310990 [ 1.537509] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10527 16:45:06.317776 [ 1.545954] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10528 16:45:06.327724 [ 1.554407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10529 16:45:06.334382 [ 1.562692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10530 16:45:06.344634 [ 1.571227] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10531 16:45:06.350950 [ 1.579508] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10532 16:45:06.359805 [ 1.594245] loop: module loaded
10533 16:45:06.368647 [ 1.599862] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10534 16:45:06.391114 [ 1.622429] mtk-pmic-keys: Failed to locate of_node [id: -1]
10535 16:45:06.398311 [ 1.628742] megasas: 07.719.03.00-rc1
10536 16:45:06.406796 [ 1.637958] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10537 16:45:06.417782 [ 1.647339] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10538 16:45:06.423687 [ 1.648926] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10539 16:45:06.433377 [ 1.664412] tun: Universal TUN/TAP device driver, 1.6
10540 16:45:06.440301 [ 1.664974] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10541 16:45:06.444940 [ 1.670198] thunder_xcv, ver 1.0
10542 16:45:06.445040 [ 1.678877] thunder_bgx, ver 1.0
10543 16:45:06.448907 [ 1.682110] nicpf, ver 1.0
10544 16:45:06.457834 [ 1.685857] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10545 16:45:06.474976 [ 1.693073] hns3: Copyright (c) 2017 Huawei Corporation.
10546 16:45:06.475279 [ 1.698400] hclge is initializing
10547 16:45:06.475358 [ 1.701716] e1000: Intel(R) PRO/1000 Network Driver
10548 16:45:06.479803 [ 1.706585] e1000: Copyright (c) 1999-2006 Intel Corporation.
10549 16:45:06.479895 [ 1.712337] e1000e: Intel(R) PRO/1000 Network Driver
10550 16:45:06.491112 [ 1.717291] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10551 16:45:06.495992 [ 1.723219] igb: Intel(R) Gigabit Ethernet Network Driver
10552 16:45:06.499517 [ 1.728608] igb: Copyright (c) 2007-2014 Intel Corporation.
10553 16:45:06.503439 [ 1.734184] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10554 16:45:06.516214 [ 1.734853] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10555 16:45:06.519267 [ 1.740441] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10556 16:45:06.526103 [ 1.740732] sky2: driver version 1.30
10557 16:45:06.529339 [ 1.761845] VFIO - User Level meta-driver version: 0.3
10558 16:45:06.538575 [ 1.769683] usbcore: registered new interface driver usb-storage
10559 16:45:06.544966 [ 1.775866] usbcore: registered new device driver onboard-usb-hub
10560 16:45:06.553684 [ 1.784667] mt6397-rtc mt6359-rtc: registered as rtc0
10561 16:45:06.563735 [ 1.789876] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:45:06 UTC (1685810706)
10562 16:45:06.566811 [ 1.799182] i2c_dev: i2c /dev entries driver
10563 16:45:06.582603 [ 1.810429] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10564 16:45:06.589514 [ 1.820338] sdhci: Secure Digital Host Controller Interface driver
10565 16:45:06.595626 [ 1.826512] sdhci: Copyright(c) Pierre Ossman
10566 16:45:06.602671 [ 1.831669] Synopsys Designware Multimedia Card Interface Driver
10567 16:45:06.606075 [ 1.838120] mmc0: CQHCI version 5.10
10568 16:45:06.612262 [ 1.838555] sdhci-pltfm: SDHCI platform and OF driver helper
10569 16:45:06.619043 [ 1.849431] ledtrig-cpu: registered to indicate activity on CPUs
10570 16:45:06.625897 [ 1.856482] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10571 16:45:06.632428 [ 1.863615] usbcore: registered new interface driver usbhid
10572 16:45:06.636038 [ 1.869181] usbhid: USB HID core driver
10573 16:45:06.642149 [ 1.873186] spi_master spi0: will run message pump with realtime priority
10574 16:45:06.689883 [ 1.914164] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10575 16:45:06.705190 [ 1.929535] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10576 16:45:06.712083 [ 1.942894] mmc0: Command Queue Engine enabled
10577 16:45:06.715765 [ 1.944178] cros-ec-spi spi0.0: Chrome EC device registered
10578 16:45:06.722499 [ 1.947360] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10579 16:45:06.729196 [ 1.960090] mmcblk0: mmc0:0001 DA4128 116 GiB
10580 16:45:06.740376 [ 1.971387] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10581 16:45:06.750292 [ 1.971478] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10582 16:45:06.753605 [ 1.979382] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10583 16:45:06.760242 [ 1.988254] NET: Registered PF_PACKET protocol family
10584 16:45:06.763918 [ 1.992021] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10585 16:45:06.770565 [ 1.996233] 9pnet: Installing 9P2000 support
10586 16:45:06.776866 [ 2.001865] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10587 16:45:06.780454 [ 2.005381] Key type dns_resolver registered
10588 16:45:06.783375 [ 2.016531] registered taskstats version 1
10589 16:45:06.789681 [ 2.020671] Loading compiled-in X.509 certificates
10590 16:45:06.821903 [ 2.046286] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10591 16:45:06.831891 [ 2.056692] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 16:45:06.841299 [ 2.069023] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10593 16:45:06.852050 [ 2.083091] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10594 16:45:06.858525 [ 2.089700] xhci-mtk 11200000.usb: xHCI Host Controller
10595 16:45:06.865557 [ 2.094953] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10596 16:45:06.875214 [ 2.102559] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10597 16:45:06.881711 [ 2.111723] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10598 16:45:06.885295 [ 2.117571] xhci-mtk 11200000.usb: xHCI Host Controller
10599 16:45:06.894759 [ 2.122796] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10600 16:45:06.901769 [ 2.130188] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10601 16:45:06.904900 [ 2.137794] hub 1-0:1.0: USB hub found
10602 16:45:06.908108 [ 2.141566] hub 1-0:1.0: 1 port detected
10603 16:45:06.918220 [ 2.145660] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10604 16:45:06.921744 [ 2.154206] hub 2-0:1.0: USB hub found
10605 16:45:06.924997 [ 2.157979] hub 2-0:1.0: 1 port detected
10606 16:45:06.933801 [ 2.165106] mtk-msdc 11f70000.mmc: Got CD GPIO
10607 16:45:06.955919 [ 2.183802] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10608 16:45:06.963088 [ 2.191589] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10609 16:45:06.972889 [ 2.199419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10610 16:45:06.979023 [ 2.208833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10611 16:45:06.989101 [ 2.216660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10612 16:45:06.995615 [ 2.224422] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10613 16:45:07.002457 [ 2.232076] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10614 16:45:07.012620 [ 2.239636] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10615 16:45:07.018860 [ 2.247197] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10616 16:45:07.029753 [ 2.257682] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10617 16:45:07.036431 [ 2.265792] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10618 16:45:07.046506 [ 2.273888] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10619 16:45:07.053487 [ 2.281972] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10620 16:45:07.063262 [ 2.290054] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10621 16:45:07.069839 [ 2.298138] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10622 16:45:07.079717 [ 2.306220] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10623 16:45:07.085906 [ 2.314302] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10624 16:45:07.092814 [ 2.322385] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10625 16:45:07.102571 [ 2.330468] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10626 16:45:07.109778 [ 2.338551] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10627 16:45:07.119501 [ 2.346635] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10628 16:45:07.125767 [ 2.354718] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10629 16:45:07.135703 [ 2.362801] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10630 16:45:07.142287 [ 2.370884] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10631 16:45:07.148991 [ 2.379511] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10632 16:45:07.155339 [ 2.386664] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10633 16:45:07.162349 [ 2.393445] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10634 16:45:07.168929 [ 2.400294] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10635 16:45:07.176368 [ 2.407329] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10636 16:45:07.186017 [ 2.413964] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10637 16:45:07.195852 [ 2.422842] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10638 16:45:07.206345 [ 2.431715] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10639 16:45:07.213204 [ 2.440758] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10640 16:45:07.223073 [ 2.449972] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10641 16:45:07.233099 [ 2.459189] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10642 16:45:07.242877 [ 2.468055] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10643 16:45:07.249701 [ 2.477268] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10644 16:45:07.259389 [ 2.486134] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10645 16:45:07.269355 [ 2.495176] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10646 16:45:07.278897 [ 2.505081] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10647 16:45:07.289070 [ 2.516256] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10648 16:45:07.295096 [ 2.525917] Trying to probe devices needed for running init ...
10649 16:45:07.313091 [ 2.544446] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10650 16:45:07.343799 [ 2.574696] hub 2-1:1.0: USB hub found
10651 16:45:07.346544 [ 2.578849] hub 2-1:1.0: 3 ports detected
10652 16:45:07.465041 [ 2.696211] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10653 16:45:07.621225 [ 2.852155] hub 1-1:1.0: USB hub found
10654 16:45:07.624714 [ 2.856212] hub 1-1:1.0: 4 ports detected
10655 16:45:07.701048 [ 2.928479] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10656 16:45:07.944141 [ 3.172115] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10657 16:45:08.077003 [ 3.307799] hub 1-1.4:1.0: USB hub found
10658 16:45:08.080528 [ 3.312197] hub 1-1.4:1.0: 2 ports detected
10659 16:45:08.376880 [ 3.604239] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10660 16:45:08.568179 [ 3.796268] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10661 16:45:19.580984 [ 14.816871] ALSA device list:
10662 16:45:19.583913 [ 14.819845] No soundcards found.
10663 16:45:19.599237 [ 14.831988] Freeing unused kernel memory: 8384K
10664 16:45:19.602839 [ 14.836642] Run /init as init process
10665 16:45:19.612469 Loading, please wait...
10666 16:45:19.631074 Starting version 247.3-7+deb11u2
10667 16:45:19.971401 [ 15.200603] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 16:45:19.983293 [ 15.212513] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 16:45:19.986238 [ 15.213529] remoteproc remoteproc0: scp is available
10670 16:45:19.993458 [ 15.226010] mc: Linux media interface: v0.10
10671 16:45:20.003182 [ 15.226566] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10672 16:45:20.009948 [ 15.231746] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 16:45:20.013015 [ 15.239899] remoteproc remoteproc0: powering up scp
10674 16:45:20.023488 [ 15.248139] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10675 16:45:20.029870 [ 15.250263] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10676 16:45:20.039518 [ 15.250278] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10677 16:45:20.049429 [ 15.254912] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10678 16:45:20.056211 [ 15.260118] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 16:45:20.062722 [ 15.268468] remoteproc remoteproc0: request_firmware failed: -2
10680 16:45:20.069087 [ 15.282181] videodev: Linux video capture interface: v2.00
10681 16:45:20.075919 [ 15.291121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 16:45:20.082357 [ 15.292813] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 16:45:20.089328 [ 15.293249] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10684 16:45:20.096488 [ 15.297728] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10685 16:45:20.106674 [ 15.300424] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 16:45:20.109797 [ 15.306408] Bluetooth: Core ver 2.22
10687 16:45:20.116530 [ 15.313595] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 16:45:20.124425 [ 15.320779] NET: Registered PF_BLUETOOTH protocol family
10689 16:45:20.130503 [ 15.322706] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10690 16:45:20.133486 [ 15.322706] Fallback method does not support PEC.
10691 16:45:20.143651 [ 15.327721] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 16:45:20.150018 [ 15.335078] Bluetooth: HCI device and connection manager initialized
10693 16:45:20.156898 [ 15.336429] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10694 16:45:20.163310 [ 15.339500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10695 16:45:20.173305 [ 15.342892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 16:45:20.176567 [ 15.346483] Bluetooth: HCI socket layer initialized
10697 16:45:20.186553 [ 15.354329] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 16:45:20.189792 [ 15.359615] Bluetooth: L2CAP socket layer initialized
10699 16:45:20.199806 [ 15.359769] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10700 16:45:20.206421 [ 15.359781] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10701 16:45:20.215976 [ 15.361784] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 16:45:20.222958 [ 15.372755] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 16:45:20.229608 [ 15.372996] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10704 16:45:20.235898 [ 15.373003] pci_bus 0000:00: root bus resource [bus 00-ff]
10705 16:45:20.242702 [ 15.373011] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10706 16:45:20.252620 [ 15.373017] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10707 16:45:20.259101 [ 15.373050] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10708 16:45:20.265874 [ 15.373068] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 16:45:20.268728 [ 15.373142] pci 0000:00:00.0: supports D1 D2
10710 16:45:20.275507 [ 15.373146] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 16:45:20.285291 [ 15.374864] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10712 16:45:20.288890 [ 15.374962] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10713 16:45:20.298785 [ 15.374991] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10714 16:45:20.305599 [ 15.375009] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10715 16:45:20.311699 [ 15.375027] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10716 16:45:20.315335 [ 15.375138] pci 0000:01:00.0: supports D1 D2
10717 16:45:20.321850 [ 15.375141] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10718 16:45:20.328478 [ 15.380541] Bluetooth: SCO socket layer initialized
10719 16:45:20.334819 [ 15.384149] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10720 16:45:20.341777 [ 15.384177] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10721 16:45:20.348235 [ 15.384184] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10722 16:45:20.358232 [ 15.384197] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10723 16:45:20.364758 [ 15.384213] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10724 16:45:20.371347 [ 15.384229] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10725 16:45:20.378045 [ 15.384244] pci 0000:00:00.0: PCI bridge to [bus 01]
10726 16:45:20.384752 [ 15.384251] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10727 16:45:20.390926 [ 15.384374] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10728 16:45:20.397672 [ 15.385211] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10729 16:45:20.404464 [ 15.385720] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10730 16:45:20.411208 [ 15.386873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 16:45:20.414202 [ 15.404157] r8152 2-1.3:1.0 eth0: v1.12.13
10732 16:45:20.424036 [ 15.407329] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10733 16:45:20.430761 [ 15.410085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 16:45:20.437267 [ 15.415136] usbcore: registered new interface driver r8152
10735 16:45:20.444199 [ 15.422819] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 16:45:20.453600 [ 15.424731] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10737 16:45:20.463698 [ 15.424968] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10738 16:45:20.470253 [ 15.447281] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10739 16:45:20.480012 [ 15.452981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 16:45:20.483714 [ 15.453384] usbcore: registered new interface driver cdc_ether
10741 16:45:20.490299 [ 15.461412] usbcore: registered new interface driver r8153_ecm
10742 16:45:20.500257 [ 15.467454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 16:45:20.506847 [ 15.467486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 16:45:20.513381 [ 15.467501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 16:45:20.523084 [ 15.467570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 16:45:20.526526 [ 15.470385] usbcore: registered new interface driver btusb
10747 16:45:20.533095 [ 15.470615] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10748 16:45:20.543080 [ 15.470732] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10749 16:45:20.549864 [ 15.470745] Bluetooth: hci0: Failed to load firmware file (-2)
10750 16:45:20.556461 [ 15.470750] Bluetooth: hci0: Failed to set up firmware (-2)
10751 16:45:20.566388 [ 15.470753] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10752 16:45:20.579299 [ 15.471928] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10753 16:45:20.582814 [ 15.472107] usbcore: registered new interface driver uvcvideo
10754 16:45:20.589173 [ 15.475154] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10755 16:45:20.595601 [ 15.483543] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10756 16:45:20.602404 [ 15.490553] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10757 16:45:20.647213 [ 15.876716] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10758 16:45:20.653976 [ 15.885383] cfg80211: failed to load regulatory.db
10759 16:45:20.691779 [ 15.921185] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10760 16:45:20.695297 [ 15.928443] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10761 16:45:20.722681 [ 15.955005] mt7921e 0000:01:00.0: ASIC revision: 79610010
10762 16:45:20.831467 [ 16.056903] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 16:45:20.833881 Begin: Loading essential drivers ... done.
10764 16:45:20.840955 Begin: Running /scripts/init-premount ... done.
10765 16:45:20.846928 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10766 16:45:20.857002 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10767 16:45:20.860457 Device /sys/class/net/enx0024323078ff found
10768 16:45:20.860565 done.
10769 16:45:20.926789 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10770 16:45:20.956493 [ 16.182610] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10771 16:45:21.075454 [ 16.301838] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10772 16:45:21.191394 [ 16.417684] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 16:45:21.307439 [ 16.533660] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 16:45:21.423366 [ 16.649577] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 16:45:21.539463 [ 16.765553] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 16:45:21.655570 [ 16.881447] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 16:45:21.771637 [ 16.997501] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 16:45:21.851296 [ 17.084170] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10779 16:45:21.886942 [ 17.113380] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 16:45:21.994186 [ 17.227359] mt7921e 0000:01:00.0: hardware init failed
10781 16:45:22.056943 IP-Config: no response after 2 secs - giving up
10782 16:45:22.086472 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10783 16:45:22.106366 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10784 16:45:22.113068 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10785 16:45:22.119496 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10786 16:45:22.126523 host : mt8192-asurada-spherion-r0-cbg-8
10787 16:45:22.132789 domain : lava-rack
10788 16:45:22.139479 rootserver: 192.168.201.1 rootpath:
10789 16:45:22.139618 filename :
10790 16:45:22.169815 done.
10791 16:45:22.177337 Begin: Running /scripts/nfs-bottom ... done.
10792 16:45:22.196240 Begin: Running /scripts/init-bottom ... done.
10793 16:45:23.321529 [ 18.554368] NET: Registered PF_INET6 protocol family
10794 16:45:23.328042 [ 18.561092] Segment Routing with IPv6
10795 16:45:23.331421 [ 18.564813] In-situ OAM (IOAM) with IPv6
10796 16:45:23.440487 [ 18.657097] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10797 16:45:23.447545 [ 18.680560] systemd[1]: Detected architecture arm64.
10798 16:45:23.465495
10799 16:45:23.468984 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10800 16:45:23.469070
10801 16:45:23.485144 [ 18.718376] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10802 16:45:24.080051 [ 19.310149] systemd[1]: Queued start job for default target Graphical Interface.
10803 16:45:24.100235 [ 19.333308] systemd[1]: Created slice system-getty.slice.
10804 16:45:24.106651 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10805 16:45:24.123806 [ 19.356904] systemd[1]: Created slice system-modprobe.slice.
10806 16:45:24.130391 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10807 16:45:24.148117 [ 19.380827] systemd[1]: Created slice system-serial\x2dgetty.slice.
10808 16:45:24.154357 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10809 16:45:24.172702 [ 19.405296] systemd[1]: Created slice User and Session Slice.
10810 16:45:24.178596 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10811 16:45:24.199666 [ 19.428802] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10812 16:45:24.206473 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10813 16:45:24.223220 [ 19.452331] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10814 16:45:24.229549 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10815 16:45:24.250202 [ 19.476372] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10816 16:45:24.256817 [ 19.488068] systemd[1]: Reached target Local Encrypted Volumes.
10817 16:45:24.263273 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10818 16:45:24.275508 [ 19.508614] systemd[1]: Reached target Paths.
10819 16:45:24.278563 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10820 16:45:24.294974 [ 19.528276] systemd[1]: Reached target Remote File Systems.
10821 16:45:24.301684 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10822 16:45:24.315189 [ 19.548224] systemd[1]: Reached target Slices.
10823 16:45:24.318609 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10824 16:45:24.334872 [ 19.568285] systemd[1]: Reached target Swap.
10825 16:45:24.338564 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10826 16:45:24.355237 [ 19.588625] systemd[1]: Listening on initctl Compatibility Named Pipe.
10827 16:45:24.365634 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10828 16:45:24.372252 [ 19.604000] systemd[1]: Listening on Journal Audit Socket.
10829 16:45:24.378675 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10830 16:45:24.392252 [ 19.625443] systemd[1]: Listening on Journal Socket (/dev/log).
10831 16:45:24.398686 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10832 16:45:24.415899 [ 19.649057] systemd[1]: Listening on Journal Socket.
10833 16:45:24.422394 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10834 16:45:24.436401 [ 19.669704] systemd[1]: Listening on Network Service Netlink Socket.
10835 16:45:24.446310 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10836 16:45:24.462254 [ 19.695204] systemd[1]: Listening on udev Control Socket.
10837 16:45:24.468578 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10838 16:45:24.483299 [ 19.716530] systemd[1]: Listening on udev Kernel Socket.
10839 16:45:24.489862 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10840 16:45:24.538989 [ 19.772393] systemd[1]: Mounting Huge Pages File System...
10841 16:45:24.545742 Mounting [0;1;39mHuge Pages File System[0m...
10842 16:45:24.561448 [ 19.794473] systemd[1]: Mounting POSIX Message Queue File System...
10843 16:45:24.568061 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10844 16:45:24.585607 [ 19.818559] systemd[1]: Mounting Kernel Debug File System...
10845 16:45:24.592014 Mounting [0;1;39mKernel Debug File System[0m...
10846 16:45:24.610526 [ 19.840472] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10847 16:45:24.628957 [ 19.859077] systemd[1]: Starting Create list of static device nodes for the current kernel...
10848 16:45:24.635996 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10849 16:45:24.645761 [ 19.878426] systemd[1]: Starting Load Kernel Module configfs...
10850 16:45:24.652051 Starting [0;1;39mLoad Kernel Module configfs[0m...
10851 16:45:24.669833 [ 19.902719] systemd[1]: Starting Load Kernel Module drm...
10852 16:45:24.675860 Starting [0;1;39mLoad Kernel Module drm[0m...
10853 16:45:24.693480 [ 19.926687] systemd[1]: Starting Load Kernel Module fuse...
10854 16:45:24.699890 Starting [0;1;39mLoad Kernel Module fuse[0m...
10855 16:45:24.732255 [ 19.965492] fuse: init (API version 7.37)
10856 16:45:24.738624 [ 19.967285] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10857 16:45:24.771917 [ 20.004775] systemd[1]: Starting Journal Service...
10858 16:45:24.774923 Starting [0;1;39mJournal Service[0m...
10859 16:45:24.799686 [ 20.032744] systemd[1]: Starting Load Kernel Modules...
10860 16:45:24.806197 Starting [0;1;39mLoad Kernel Modules[0m...
10861 16:45:24.824724 [ 20.054652] systemd[1]: Starting Remount Root and Kernel File Systems...
10862 16:45:24.830969 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10863 16:45:24.846300 [ 20.079368] systemd[1]: Starting Coldplug All udev Devices...
10864 16:45:24.852742 Starting [0;1;39mColdplug All udev Devices[0m...
10865 16:45:24.870281 [ 20.103419] systemd[1]: Mounted Huge Pages File System.
10866 16:45:24.876746 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10867 16:45:24.891338 [ 20.124761] systemd[1]: Mounted POSIX Message Queue File System.
10868 16:45:24.898159 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10869 16:45:24.915424 [ 20.148876] systemd[1]: Mounted Kernel Debug File System.
10870 16:45:24.922458 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10871 16:45:24.936593 [ 20.166539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 16:45:24.946666 [ 20.176443] systemd[1]: Finished Create list of static device nodes for the current kernel.
10873 16:45:24.956465 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10874 16:45:24.967314 [ 20.197358] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 16:45:24.976292 [ 20.209054] systemd[1]: modprobe@configfs.service: Succeeded.
10876 16:45:24.982525 [ 20.215684] systemd[1]: Finished Load Kernel Module configfs.
10877 16:45:24.989109 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10878 16:45:25.004445 [ 20.237269] systemd[1]: modprobe@drm.service: Succeeded.
10879 16:45:25.011539 [ 20.243341] systemd[1]: Finished Load Kernel Module drm.
10880 16:45:25.018129 [ 20.246351] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 16:45:25.024878 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10882 16:45:25.041399 [ 20.273374] systemd[1]: modprobe@fuse.service: Succeeded.
10883 16:45:25.048231 [ 20.279539] systemd[1]: Finished Load Kernel Module fuse.
10884 16:45:25.054304 [ 20.282974] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 16:45:25.061167 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10886 16:45:25.077829 [ 20.309498] systemd[1]: Finished Load Kernel Modules.
10887 16:45:25.090585 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne[ 20.318224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 16:45:25.091071 l Modules[0m.
10889 16:45:25.104965 [ 20.338003] systemd[1]: Finished Remount Root and Kernel File Systems.
10890 16:45:25.115616 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10891 16:45:25.122188 [ 20.353362] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 16:45:25.157585 [ 20.387590] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 16:45:25.163904 [ 20.388677] systemd[1]: Mounting FUSE Control File System...
10894 16:45:25.167283 Mounting [0;1;39mFUSE Control File System[0m...
10895 16:45:25.186314 [ 20.419099] systemd[1]: Mounting Kernel Configuration File System...
10896 16:45:25.195981 [ 20.425597] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 16:45:25.202629 Mounting [0;1;39mKernel Configuration File System[0m...
10898 16:45:25.225981 [ 20.455328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 16:45:25.235311 [ 20.457090] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10900 16:45:25.242434 [ 20.472517] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10901 16:45:25.254807 [ 20.484339] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 16:45:25.261176 [ 20.484483] systemd[1]: Starting Load/Save Random Seed...
10903 16:45:25.264739 Starting [0;1;39mLoad/Save Random Seed[0m...
10904 16:45:25.283793 [ 20.514035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 16:45:25.299570 [ 20.532761] systemd[1]: Starting Apply Kernel Variables...
10906 16:45:25.306225 Starting [0;1;39mApply Kernel Variables[0m...
10907 16:45:25.316317 [ 20.545219] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 16:45:25.323983 [ 20.557297] systemd[1]: Starting Create System Users...
10909 16:45:25.330606 Starting [0;1;39mCreate System Users[0m...
10910 16:45:25.344901 [ 20.574913] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 16:45:25.354768 [ 20.588065] systemd[1]: Mounted FUSE Control File System.
10912 16:45:25.361317 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10913 16:45:25.376036 [ 20.605891] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 16:45:25.382559 [ 20.615252] systemd[1]: Mounted Kernel Configuration File System.
10915 16:45:25.389312 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10916 16:45:25.406921 [ 20.636262] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 16:45:25.413179 [ 20.637203] systemd[1]: Finished Load/Save Random Seed.
10918 16:45:25.416535 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10919 16:45:25.432902 [ 20.666162] systemd[1]: Finished Apply Kernel Variables.
10920 16:45:25.439465 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10921 16:45:25.455878 [ 20.689377] systemd[1]: Finished Create System Users.
10922 16:45:25.462452 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10923 16:45:25.475239 [ 20.708725] systemd[1]: Started Journal Service.
10924 16:45:25.482017 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10925 16:45:25.536156 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10926 16:45:25.558267 [ 20.781877] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10927 16:45:25.564716 [ 20.797297] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10928 16:45:25.575445 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10929 16:45:25.602661 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev[ 20.833529] systemd-journald[294]: Received client request to flush runtime journal.
10930 16:45:25.606249 Devices[0m.
10931 16:45:25.623137 See 'systemctl status systemd-udev-trigger.service' for details.
10932 16:45:26.893292 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10933 16:45:26.911387 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10934 16:45:26.926930 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10935 16:45:26.978739 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10936 16:45:26.995430 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10937 16:45:27.010253 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10938 16:45:27.183813 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10939 16:45:27.243862 Starting [0;1;39mNetwork Service[0m...
10940 16:45:27.380443 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10941 16:45:27.435513 Starting [0;1;39mNetwork Time Synchronization[0m...
10942 16:45:27.453738 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10943 16:45:27.555603 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10944 16:45:27.580690 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10945 16:45:27.601731 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10946 16:45:27.818187 [ 23.051799] remoteproc remoteproc0: powering up scp
10947 16:45:27.859004 [ 23.089220] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10948 16:45:27.865619 [ 23.098971] remoteproc remoteproc0: request_firmware failed: -2
10949 16:45:27.872418 [ 23.104908] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10950 16:45:27.951781 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10951 16:45:27.970989 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10952 16:45:27.987322 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10953 16:45:28.003515 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10954 16:45:28.059523 Starting [0;1;39mNetwork Name Resolution[0m...
10955 16:45:28.078354 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10956 16:45:28.104984 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10957 16:45:28.120055 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10958 16:45:28.135446 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10959 16:45:28.150960 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10960 16:45:28.170272 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10961 16:45:28.182364 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10962 16:45:28.198869 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10963 16:45:28.245541 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10964 16:45:28.274430 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10965 16:45:28.304655 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10966 16:45:28.335819 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10967 16:45:28.350962 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10968 16:45:28.378778 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10969 16:45:28.391040 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10970 16:45:28.407233 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10971 16:45:28.447083 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10972 16:45:28.574771 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10973 16:45:28.687830 Starting [0;1;39mUser Login Management[0m...
10974 16:45:28.741993 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10975 16:45:28.759522 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10976 16:45:28.778224 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10977 16:45:28.807333 Starting [0;1;39mPermit User Sessions[0m...
10978 16:45:28.917355 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10979 16:45:28.975375 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10980 16:45:28.993715 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10981 16:45:29.015262 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10982 16:45:29.036201 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10983 16:45:29.052738 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10984 16:45:29.071973 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10985 16:45:29.086763 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10986 16:45:29.134643 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10987 16:45:29.176928 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10988 16:45:29.294912
10989 16:45:29.295100
10990 16:45:29.298299 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10991 16:45:29.298408
10992 16:45:29.300986 debian-bullseye-arm64 login: root (automatic login)
10993 16:45:29.301091
10994 16:45:29.301185
10995 16:45:29.571458 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
10996 16:45:29.571663
10997 16:45:29.577932 The programs included with the Debian GNU/Linux system are free software;
10998 16:45:29.584325 the exact distribution terms for each program are described in the
10999 16:45:29.587776 individual files in /usr/share/doc/*/copyright.
11000 16:45:29.587853
11001 16:45:29.594177 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11002 16:45:29.597624 permitted by applicable law.
11003 16:45:29.659560 Matched prompt #10: / #
11005 16:45:29.659941 Setting prompt string to ['/ #']
11006 16:45:29.660083 end: 2.2.5.1 login-action (duration 00:00:25) [common]
11008 16:45:29.660400 end: 2.2.5 auto-login-action (duration 00:00:25) [common]
11009 16:45:29.660538 start: 2.2.6 expect-shell-connection (timeout 00:03:20) [common]
11010 16:45:29.660642 Setting prompt string to ['/ #']
11011 16:45:29.660734 Forcing a shell prompt, looking for ['/ #']
11013 16:45:29.711003 / #
11014 16:45:29.711154 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11015 16:45:29.711281 Waiting using forced prompt support (timeout 00:02:30)
11016 16:45:29.715736
11017 16:45:29.716007 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11018 16:45:29.716102 start: 2.2.7 export-device-env (timeout 00:03:20) [common]
11020 16:45:29.816405 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu'
11021 16:45:29.821059 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576281/extract-nfsrootfs-gw18nulu'
11023 16:45:29.921541 / # export NFS_SERVER_IP='192.168.201.1'
11024 16:45:29.926307 export NFS_SERVER_IP='192.168.201.1'
11025 16:45:29.926625 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11026 16:45:29.926753 end: 2.2 depthcharge-retry (duration 00:01:40) [common]
11027 16:45:29.926872 end: 2 depthcharge-action (duration 00:01:40) [common]
11028 16:45:29.926999 start: 3 lava-test-retry (timeout 00:01:00) [common]
11029 16:45:29.927117 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11030 16:45:29.927222 Using namespace: common
11032 16:45:30.027623 / # #
11033 16:45:30.027780 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11034 16:45:30.032380 #
11035 16:45:30.032646 Using /lava-10576281
11037 16:45:30.132955 / # export SHELL=/bin/sh
11038 16:45:30.138001 export SHELL=/bin/sh
11040 16:45:30.238495 / # . /lava-10576281/environment
11041 16:45:30.244007 . /lava-10576281/environment
11043 16:45:30.348665 / # /lava-10576281/bin/lava-test-runner /lava-10576281/0
11044 16:45:30.348879 Test shell timeout: 10s (minimum of the action and connection timeout)
11045 16:45:30.354052 /lava-10576281/bin/lava-test-runner /lava-10576281/0
11046 16:45:30.611032 + export TESTRUN_ID=0_dmesg
11047 16:45:30.614157 + cd /lava-10576281/0/tests/0_dmesg
11048 16:45:30.617615 + cat uuid
11049 16:45:30.628692 + UUID=10576281_1.[ 25.859549] <LAVA_SIGNAL_STARTRUN 0_dmesg 10576281_1.6.2.3.1>
11050 16:45:30.628790 6.2.3.1
11051 16:45:30.628861 + set +x
11052 16:45:30.629109 Received signal: <STARTRUN> 0_dmesg 10576281_1.6.2.3.1
11053 16:45:30.629188 Starting test lava.0_dmesg (10576281_1.6.2.3.1)
11054 16:45:30.629275 Skipping test definition patterns.
11055 16:45:30.635314 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11056 16:45:30.731147 [ 25.961823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11057 16:45:30.731483 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11059 16:45:30.816200 [ 26.046783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11060 16:45:30.816510 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11062 16:45:30.898951 [ 26.129090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11063 16:45:30.899470 + set +x
11064 16:45:30.900189 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11066 16:45:30.905497 [ 26.138082] <LAVA_SIGNAL_ENDRUN 0_dmesg 10576281_1.6.2.3.1>
11067 16:45:30.906516 Received signal: <ENDRUN> 0_dmesg 10576281_1.6.2.3.1
11068 16:45:30.907219 Ending use of test pattern.
11069 16:45:30.907880 Ending test lava.0_dmesg (10576281_1.6.2.3.1), duration 0.28
11071 16:45:30.918496 <LAVA_TEST_RUNNER EXIT>
11072 16:45:30.919397 ok: lava_test_shell seems to have completed
11073 16:45:30.920112 alert: pass
crit: pass
emerg: pass
11074 16:45:30.920606 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11075 16:45:30.921079 end: 3 lava-test-retry (duration 00:00:01) [common]
11076 16:45:30.921567 start: 4 lava-test-retry (timeout 00:01:00) [common]
11077 16:45:30.922041 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11078 16:45:30.922415 Using namespace: common
11080 16:45:31.023451 / # #
11081 16:45:31.023931 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11082 16:45:31.024236 Using /lava-10576281
11084 16:45:31.124864 export SHELL=/bin/sh
11085 16:45:31.125095 #
11087 16:45:31.225663 / # export SHELL=/bin/sh. /lava-10576281/environment
11088 16:45:31.225867
11090 16:45:31.326580 / # . /lava-10576281/environment/lava-10576281/bin/lava-test-runner /lava-10576281/1
11091 16:45:31.327185 Test shell timeout: 10s (minimum of the action and connection timeout)
11092 16:45:31.327829
11093 16:45:31.332743 / # /lava-10576281/bin/lava-test-runner /lava-10576281/1
11094 16:45:31.499646 + export TESTRUN_ID=1_bootrr
11095 16:45:31.503157 + cd /lava-10576281/1/tests/1_bootrr
11096 16:45:31.506151 + cat uuid
11097 16:45:31.521217 + UUID=10576281_1.[ 26.751587] <LAVA_SIGNAL_STARTRUN 1_bootrr 10576281_1.6.2.3.5>
11098 16:45:31.521315 6.2.3.5
11099 16:45:31.521406 + set +x
11100 16:45:31.521648 Received signal: <STARTRUN> 1_bootrr 10576281_1.6.2.3.5
11101 16:45:31.521721 Starting test lava.1_bootrr (10576281_1.6.2.3.5)
11102 16:45:31.521803 Skipping test definition patterns.
11103 16:45:31.534304 + export PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10576281/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11104 16:45:31.537283 + cd /opt/bootrr/libexec/bootrr
11105 16:45:31.537392 + sh helpers/bootrr-auto
11106 16:45:31.613433 /lava-10576281/1/../bin/lava-test-case
11107 16:45:31.652833 [ 26.882859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11108 16:45:31.653670 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11110 16:45:31.702870 /lava-10576281/1/../bin/lava-test-case
11111 16:45:31.739413 [ 26.969469] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
11112 16:45:31.740420 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11114 16:45:31.764992 /lava-10576281/1/../bin/lava-test-case
11115 16:45:31.797573 [ 27.027779] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=skip>
11116 16:45:31.798421 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=skip
11118 16:45:31.865691 /lava-10576281/1/../bin/lava-test-case
11119 16:45:31.898883 [ 27.129344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
11120 16:45:31.899713 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
11122 16:45:31.940318 /lava-10576281/1/../bin/lava-test-case
11123 16:45:31.971190 [ 27.201530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
11124 16:45:31.971947 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
11126 16:45:32.010338 /lava-10576281/1/../bin/lava-test-case
11127 16:45:32.042426 [ 27.272914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
11128 16:45:32.043261 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
11130 16:45:32.082294 /lava-10576281/1/../bin/lava-test-case
11131 16:45:32.113449 [ 27.343629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
11132 16:45:32.114279 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
11134 16:45:32.157307 /lava-10576281/1/../bin/lava-test-case
11135 16:45:32.189803 [ 27.420185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
11136 16:45:32.190753 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
11138 16:45:32.214485 /lava-10576281/1/../bin/lava-test-case
11139 16:45:32.244355 [ 27.474714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
11140 16:45:32.245083 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
11142 16:45:32.289718 /lava-10576281/1/../bin/lava-test-case
11143 16:45:32.323288 [ 27.553671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
11144 16:45:32.324294 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
11146 16:45:32.349021 /lava-10576281/1/../bin/lava-test-case
11147 16:45:32.382127 [ 27.612694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
11148 16:45:32.382608 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
11150 16:45:32.419356 /lava-10576281/1/../bin/lava-test-case
11151 16:45:32.459083 [ 27.689644] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
11152 16:45:32.460098 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
11154 16:45:32.508055 /lava-10576281/1/../bin/lava-test-case
11155 16:45:32.538658 [ 27.769275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
11156 16:45:32.539561 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
11158 16:45:32.582565 /lava-10576281/1/../bin/lava-test-case
11159 16:45:32.620397 [ 27.850863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
11160 16:45:32.621272 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
11162 16:45:32.661264 /lava-10576281/1/../bin/lava-test-case
11163 16:45:32.692430 [ 27.922710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
11164 16:45:32.693273 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
11166 16:45:32.719142 /lava-10576281/1/../bin/lava-test-case
11167 16:45:32.756579 [ 27.987573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
11168 16:45:32.756855 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
11170 16:45:32.793783 /lava-10576281/1/../bin/lava-test-case
11171 16:45:32.821518 [ 28.052458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
11172 16:45:32.821790 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
11174 16:45:32.851535 /lava-10576281/1/../bin/lava-test-case
11175 16:45:32.879788 [ 28.110761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
11176 16:45:32.880068 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
11178 16:45:32.915962 /lava-10576281/1/../bin/lava-test-case
11179 16:45:32.942861 [ 28.173465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
11180 16:45:32.943158 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
11182 16:45:32.968975 /lava-10576281/1/../bin/lava-test-case
11183 16:45:33.002912 [ 28.233078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
11184 16:45:33.004105 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
11186 16:45:33.039563 /lava-10576281/1/../bin/lava-test-case
11187 16:45:33.076622 [ 28.306752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
11188 16:45:33.077897 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
11190 16:45:33.100164 /lava-10576281/1/../bin/lava-test-case
11191 16:45:33.136611 [ 28.366805] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
11192 16:45:33.137519 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
11194 16:45:33.187411 /lava-10576281/1/../bin/lava-test-case
11195 16:45:33.217944 [ 28.448395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
11196 16:45:33.218670 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
11198 16:45:33.242637 /lava-10576281/1/../bin/lava-test-case
11199 16:45:33.269860 [ 28.501072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
11200 16:45:33.270136 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
11202 16:45:33.303215 /lava-10576281/1/../bin/lava-test-case
11203 16:45:33.328459 [ 28.559017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
11204 16:45:33.328799 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
11206 16:45:33.362288 /lava-10576281/1/../bin/lava-test-case
11207 16:45:33.390925 [ 28.621703] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
11208 16:45:33.391204 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
11210 16:45:33.415540 /lava-10576281/1/../bin/lava-test-case
11211 16:45:33.445573 [ 28.676129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
11212 16:45:33.446147 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
11214 16:45:33.489285 /lava-10576281/1/../bin/lava-test-case
11215 16:45:33.522926 [ 28.753339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
11216 16:45:33.523864 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
11218 16:45:33.553447 /lava-10576281/1/../bin/lava-test-case
11219 16:45:33.586181 [ 28.816781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
11220 16:45:33.586981 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
11222 16:45:33.625408 /lava-10576281/1/../bin/lava-test-case
11223 16:45:33.658569 [ 28.888973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
11224 16:45:33.659341 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
11226 16:45:33.699755 /lava-10576281/1/../bin/lava-test-case
11227 16:45:33.737537 [ 28.967894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
11228 16:45:33.738416 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
11230 16:45:33.781717 /lava-10576281/1/../bin/lava-test-case
11231 16:45:33.828611 [ 29.059164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
11232 16:45:33.829419 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
11234 16:45:33.868804 /lava-10576281/1/../bin/lava-test-case
11235 16:45:33.902327 [ 29.132781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
11236 16:45:33.903082 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
11238 16:45:33.935505 /lava-10576281/1/../bin/lava-test-case
11239 16:45:33.966446 [ 29.197132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
11240 16:45:33.967228 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
11242 16:45:34.010667 /lava-10576281/1/../bin/lava-test-case
11243 16:45:34.041407 [ 29.272271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
11244 16:45:34.042166 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
11246 16:45:34.083793 /lava-10576281/1/../bin/lava-test-case
11247 16:45:34.117004 [ 29.347504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
11248 16:45:34.117793 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
11250 16:45:34.142181 /lava-10576281/1/../bin/lava-test-case
11251 16:45:34.176433 [ 29.407289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
11252 16:45:34.177197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
11254 16:45:34.217900 /lava-10576281/1/../bin/lava-test-case
11255 16:45:34.250069 [ 29.480697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
11256 16:45:34.250778 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
11258 16:45:34.282256 /lava-10576281/1/../bin/lava-test-case
11259 16:45:34.317406 [ 29.548005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
11260 16:45:34.318315 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
11262 16:45:34.358364 /lava-10576281/1/../bin/lava-test-case
11263 16:45:34.392868 [ 29.623587] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
11264 16:45:34.393748 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
11266 16:45:34.418264 /lava-10576281/1/../bin/lava-test-case
11267 16:45:34.454655 [ 29.685293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
11268 16:45:34.455457 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
11270 16:45:34.497125 /lava-10576281/1/../bin/lava-test-case
11271 16:45:34.531502 [ 29.762466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
11272 16:45:34.532564 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11274 16:45:34.555425 /lava-10576281/1/../bin/lava-test-case
11275 16:45:34.591473 [ 29.822370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11276 16:45:34.592590 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11278 16:45:34.641962 /lava-10576281/1/../bin/lava-test-case
11279 16:45:34.679166 [ 29.909536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11280 16:45:34.680084 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11282 16:45:34.702925 /lava-10576281/1/../bin/lava-test-case
11283 16:45:34.732019 [ 29.963211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11284 16:45:34.732318 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11286 16:45:34.764817 /lava-10576281/1/../bin/lava-test-case
11287 16:45:34.793447 [ 30.024771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11288 16:45:34.793740 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11290 16:45:34.818807 /lava-10576281/1/../bin/lava-test-case
11291 16:45:34.848404 [ 30.079283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11292 16:45:34.848699 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11294 16:45:34.881562 /lava-10576281/1/../bin/lava-test-case
11295 16:45:34.910305 [ 30.141597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11296 16:45:34.910602 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11298 16:45:34.933271 /lava-10576281/1/../bin/lava-test-case
11299 16:45:34.962221 [ 30.193544] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11300 16:45:34.962522 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11302 16:45:35.006650 /lava-10576281/1/../bin/lava-test-case
11303 16:45:35.037035 [ 30.268151] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11304 16:45:35.037308 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11306 16:45:35.073370 /lava-10576281/1/../bin/lava-test-case
11307 16:45:35.104289 [ 30.334938] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11308 16:45:35.104566 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11310 16:45:36.142684 /lava-10576281/1/../bin/lava-test-case
11311 16:45:36.175371 [ 31.406322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11312 16:45:36.175685 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11314 16:45:37.208253 /lava-10576281/1/../bin/lava-test-case
11315 16:45:37.237185 [ 32.468235] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11316 16:45:37.237459 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11317 16:45:37.237551 Bad test result: blocked
11318 16:45:37.260631 /lava-10576281/1/../bin/lava-test-case
11319 16:45:37.288545 [ 32.519930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11320 16:45:37.288813 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11322 16:45:37.323877 /lava-10576281/1/../bin/lava-test-case
11323 16:45:37.353340 [ 32.584299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11324 16:45:37.353612 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11326 16:45:37.387355 /lava-10576281/1/../bin/lava-test-case
11327 16:45:37.416392 [ 32.647579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11328 16:45:37.416671 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11330 16:45:37.452277 /lava-10576281/1/../bin/lava-test-case
11331 16:45:37.481304 [ 32.712228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11332 16:45:37.481568 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11334 16:45:37.514033 /lava-10576281/1/../bin/lava-test-case
11335 16:45:37.549219 [ 32.780668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11336 16:45:37.549513 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11338 16:45:37.586818 /lava-10576281/1/../bin/lava-test-case
11339 16:45:37.619552 [ 32.851100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11340 16:45:37.619869 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11342 16:45:37.640994 /lava-10576281/1/../bin/lava-test-case
11343 16:45:37.667016 [ 32.898212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11344 16:45:37.667313 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11346 16:45:37.704015 /lava-10576281/1/../bin/lava-test-case
11347 16:45:37.735415 [ 32.966898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11348 16:45:37.735690 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11350 16:45:37.768080 /lava-10576281/1/../bin/lava-test-case
11351 16:45:37.795959 [ 33.027548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11352 16:45:37.796225 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11354 16:45:37.819166 /lava-10576281/1/../bin/lava-test-case
11355 16:45:37.851043 [ 33.082445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11356 16:45:37.851313 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11358 16:45:37.895552 /lava-10576281/1/../bin/lava-test-case
11359 16:45:37.923347 [ 33.154391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11360 16:45:37.923617 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11362 16:45:37.945356 /lava-10576281/1/../bin/lava-test-case
11363 16:45:37.974416 [ 33.205889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11364 16:45:37.974681 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11366 16:45:38.013517 /lava-10576281/1/../bin/lava-test-case
11367 16:45:38.041070 [ 33.272287] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11368 16:45:38.041346 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11370 16:45:38.063295 /lava-10576281/1/../bin/lava-test-case
11371 16:45:38.095477 [ 33.326702] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11372 16:45:38.095747 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11374 16:45:38.133516 /lava-10576281/1/../bin/lava-test-case
11375 16:45:38.162836 [ 33.394260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11376 16:45:38.163102 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11378 16:45:38.196521 /lava-10576281/1/../bin/lava-test-case
11379 16:45:38.226661 [ 33.457827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11380 16:45:38.226967 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11382 16:45:38.273168 /lava-10576281/1/../bin/lava-test-case
11383 16:45:38.306487 [ 33.537901] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11384 16:45:38.306847 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11386 16:45:38.342480 /lava-10576281/1/../bin/lava-test-case
11387 16:45:38.372495 [ 33.603624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11388 16:45:38.372762 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11390 16:45:38.409266 /lava-10576281/1/../bin/lava-test-case
11391 16:45:38.439918 [ 33.671178] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11392 16:45:38.440186 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11394 16:45:38.473045 /lava-10576281/1/../bin/lava-test-case
11395 16:45:38.503211 [ 33.734505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11396 16:45:38.503489 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11398 16:45:38.541877 /lava-10576281/1/../bin/lava-test-case
11399 16:45:38.573993 [ 33.805481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11400 16:45:38.574258 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11402 16:45:38.615639 /lava-10576281/1/../bin/lava-test-case
11403 16:45:38.645330 [ 33.876744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11404 16:45:38.645603 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11406 16:45:38.681406 /lava-10576281/1/../bin/lava-test-case
11407 16:45:38.710042 [ 33.941823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11408 16:45:38.710319 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11410 16:45:38.748778 /lava-10576281/1/../bin/lava-test-case
11411 16:45:38.779182 [ 34.010306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11412 16:45:38.779449 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11414 16:45:38.817514 /lava-10576281/1/../bin/lava-test-case
11415 16:45:38.850112 [ 34.081552] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11416 16:45:38.850389 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11418 16:45:38.882636 /lava-10576281/1/../bin/lava-test-case
11419 16:45:38.911852 [ 34.143295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11420 16:45:38.912130 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11422 16:45:38.952839 /lava-10576281/1/../bin/lava-test-case
11423 16:45:38.980130 [ 34.211761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11424 16:45:38.980398 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11426 16:45:39.019342 /lava-10576281/1/../bin/lava-test-case
11427 16:45:39.053574 [ 34.284928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11428 16:45:39.053854 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11430 16:45:39.088716 /lava-10576281/1/../bin/lava-test-case
11431 16:45:39.115637 [ 34.347284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11432 16:45:39.115926 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11434 16:45:39.140009 /lava-10576281/1/../bin/lava-test-case
11435 16:45:39.170033 [ 34.401370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11436 16:45:39.170302 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11438 16:45:39.205923 /lava-10576281/1/../bin/lava-test-case
11439 16:45:39.239779 [ 34.471439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11440 16:45:39.240051 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11442 16:45:39.269689 /lava-10576281/1/../bin/lava-test-case
11443 16:45:39.299999 [ 34.531616] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11444 16:45:39.300268 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11446 16:45:39.334855 /lava-10576281/1/../bin/lava-test-case
11447 16:45:39.361955 [ 34.593693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11448 16:45:39.362235 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11450 16:45:39.384336 /lava-10576281/1/../bin/lava-test-case
11451 16:45:39.414710 [ 34.646307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11452 16:45:39.414987 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11454 16:45:39.451883 /lava-10576281/1/../bin/lava-test-case
11455 16:45:39.481168 [ 34.712759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11456 16:45:39.481436 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11458 16:45:39.506981 /lava-10576281/1/../bin/lava-test-case
11459 16:45:39.536882 [ 34.768738] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11460 16:45:39.537148 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11462 16:45:39.571614 /lava-10576281/1/../bin/lava-test-case
11463 16:45:39.604218 [ 34.835562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11464 16:45:39.604486 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11466 16:45:39.633821 /lava-10576281/1/../bin/lava-test-case
11467 16:45:39.665024 [ 34.896813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11468 16:45:39.665289 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11470 16:45:39.700430 /lava-10576281/1/../bin/lava-test-case
11471 16:45:39.731488 [ 34.963269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11472 16:45:39.731785 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11474 16:45:39.755301 /lava-10576281/1/../bin/lava-test-case
11475 16:45:39.781439 [ 35.012961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11476 16:45:39.781704 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11478 16:45:39.815308 /lava-10576281/1/../bin/lava-test-case
11479 16:45:39.843261 [ 35.074928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11480 16:45:39.843535 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11482 16:45:39.879033 /lava-10576281/1/../bin/lava-test-case
11483 16:45:39.909438 [ 35.141203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11484 16:45:39.909725 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11486 16:45:39.929814 /lava-10576281/1/../bin/lava-test-case
11487 16:45:39.956793 [ 35.188405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11488 16:45:39.957063 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11490 16:45:39.996420 /lava-10576281/1/../bin/lava-test-case
11491 16:45:40.023374 [ 35.254997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11492 16:45:40.023621 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11494 16:45:40.046408 /lava-10576281/1/../bin/lava-test-case
11495 16:45:40.074120 [ 35.305657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11496 16:45:40.074386 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11498 16:45:40.108189 /lava-10576281/1/../bin/lava-test-case
11499 16:45:40.136660 [ 35.368647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11500 16:45:40.136938 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11502 16:45:40.159789 /lava-10576281/1/../bin/lava-test-case
11503 16:45:40.187409 [ 35.419221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11504 16:45:40.187697 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11506 16:45:41.232522 /lava-10576281/1/../bin/lava-test-case
11507 16:45:41.261973 [ 36.493668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11508 16:45:41.262260 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11510 16:45:41.284257 /lava-10576281/1/../bin/lava-test-case
11511 16:45:41.314774 [ 36.546622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11512 16:45:41.315090 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11514 16:45:42.358606 /lava-10576281/1/../bin/lava-test-case
11515 16:45:42.392291 [ 37.623750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11516 16:45:42.393267 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11518 16:45:42.416790 /lava-10576281/1/../bin/lava-test-case
11519 16:45:42.449120 [ 37.680664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11520 16:45:42.449940 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11522 16:45:43.500603 /lava-10576281/1/../bin/lava-test-case
11523 16:45:43.532182 [ 38.764541] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11524 16:45:43.532503 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11526 16:45:43.554767 /lava-10576281/1/../bin/lava-test-case
11527 16:45:43.588116 [ 38.820505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11528 16:45:43.588429 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11530 16:45:44.634634 /lava-10576281/1/../bin/lava-test-case
11531 16:45:44.669092 [ 39.901227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11532 16:45:44.669458 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11534 16:45:44.690617 /lava-10576281/1/../bin/lava-test-case
11535 16:45:44.719757 [ 39.951895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11536 16:45:44.720020 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11538 16:45:45.764104 /lava-10576281/1/../bin/lava-test-case
11539 16:45:45.796257 [ 41.028948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11540 16:45:45.796539 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11542 16:45:45.819584 /lava-10576281/1/../bin/lava-test-case
11543 16:45:45.851166 [ 41.083535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11544 16:45:45.851532 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11546 16:45:46.899525 /lava-10576281/1/../bin/lava-test-case
11547 16:45:46.934898 [ 42.167474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11548 16:45:46.935198 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11550 16:45:46.956223 /lava-10576281/1/../bin/lava-test-case
11551 16:45:46.986261 [ 42.218726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11552 16:45:46.986541 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11554 16:45:48.034116 /lava-10576281/1/../bin/lava-test-case
11555 16:45:48.066526 [ 43.299215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11556 16:45:48.066864 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11558 16:45:48.088156 /lava-10576281/1/../bin/lava-test-case
11559 16:45:48.119270 [ 43.351789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11560 16:45:48.119620 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11562 16:45:48.143062 /lava-10576281/1/../bin/lava-test-case
11563 16:45:48.170545 [ 43.403017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11564 16:45:48.170873 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11566 16:45:49.217940 /lava-10576281/1/../bin/lava-test-case
11567 16:45:49.252342 [ 44.485035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11568 16:45:49.252710 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11570 16:45:49.274257 /lava-10576281/1/../bin/lava-test-case
11571 16:45:49.304912 [ 44.537657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11572 16:45:49.305265 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11574 16:45:49.342310 /lava-10576281/1/../bin/lava-test-case
11575 16:45:49.373593 [ 44.606628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11576 16:45:49.373950 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11578 16:45:49.393984 /lava-10576281/1/../bin/lava-test-case
11579 16:45:49.421829 [ 44.654190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11580 16:45:49.422177 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11582 16:45:49.459335 /lava-10576281/1/../bin/lava-test-case
11583 16:45:49.490277 [ 44.723284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11584 16:45:49.490620 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11586 16:45:49.528240 /lava-10576281/1/../bin/lava-test-case
11587 16:45:49.552775 [ 44.785411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11588 16:45:49.553205 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11590 16:45:49.588309 /lava-10576281/1/../bin/lava-test-case
11591 16:45:49.619682 [ 44.852510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11592 16:45:49.620014 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11594 16:45:49.642248 /lava-10576281/1/../bin/lava-test-case
11595 16:45:49.668258 [ 44.901191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11596 16:45:49.668581 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11598 16:45:49.702296 /lava-10576281/1/../bin/lava-test-case
11599 16:45:49.734858 [ 44.967737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11600 16:45:49.735166 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11602 16:45:49.770637 /lava-10576281/1/../bin/lava-test-case
11603 16:45:49.798756 [ 45.030845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11604 16:45:49.799052 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11606 16:45:49.823036 /lava-10576281/1/../bin/lava-test-case
11607 16:45:49.851779 [ 45.084686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11608 16:45:49.852120 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11610 16:45:49.895101 /lava-10576281/1/../bin/lava-test-case
11611 16:45:49.922391 [ 45.155021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11612 16:45:49.922711 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11614 16:45:49.943943 /lava-10576281/1/../bin/lava-test-case
11615 16:45:49.970153 [ 45.202960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11616 16:45:49.970471 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11618 16:45:50.004362 /lava-10576281/1/../bin/lava-test-case
11619 16:45:50.038404 [ 45.271253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11620 16:45:50.038770 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11622 16:45:50.063179 /lava-10576281/1/../bin/lava-test-case
11623 16:45:50.093442 [ 45.326027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11624 16:45:50.093757 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11626 16:45:50.129352 /lava-10576281/1/../bin/lava-test-case
11627 16:45:50.159828 [ 45.392727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11628 16:45:50.160146 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11630 16:45:50.180656 /lava-10576281/1/../bin/lava-test-case
11631 16:45:50.213247 [ 45.446041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11632 16:45:50.213558 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11634 16:45:50.256038 /lava-10576281/1/../bin/lava-test-case
11635 16:45:50.283524 [ 45.516380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11636 16:45:50.283847 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11638 16:45:50.306202 /lava-10576281/1/../bin/lava-test-case
11639 16:45:50.338442 [ 45.571555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11640 16:45:50.338784 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11642 16:45:50.370083 /lava-10576281/1/../bin/lava-test-case
11643 16:45:50.398155 [ 45.630884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11644 16:45:50.398441 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11646 16:45:50.418777 /lava-10576281/1/../bin/lava-test-case
11647 16:45:50.450995 [ 45.683912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11648 16:45:50.451323 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11650 16:45:50.761182 [ 46.000259] vpu: disabling
11651 16:45:50.764382 [ 46.003066] vproc2: disabling
11652 16:45:50.767897 [ 46.006069] vproc1: disabling
11653 16:45:50.770546 [ 46.009066] vaud18: disabling
11654 16:45:50.774130 [ 46.012210] vsram_others: disabling
11655 16:45:50.777667 [ 46.015815] va09: disabling
11656 16:45:50.780655 [ 46.018652] vsram_md: disabling
11657 16:45:50.783932 [ 46.021881] Vgpu: disabling
11658 16:45:51.499525 /lava-10576281/1/../bin/lava-test-case
11659 16:45:51.529528 [ 46.762654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11660 16:45:51.529877 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11662 16:45:52.574214 /lava-10576281/1/../bin/lava-test-case
11663 16:45:52.602978 [ 47.835992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11664 16:45:52.603347 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11666 16:45:52.624666 /lava-10576281/1/../bin/lava-test-case
11667 16:45:52.651284 [ 47.884224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11668 16:45:52.651638 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11670 16:45:52.686663 /lava-10576281/1/../bin/lava-test-case
11671 16:45:52.718505 [ 47.951710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11672 16:45:52.718836 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11674 16:45:52.738371 /lava-10576281/1/../bin/lava-test-case
11675 16:45:52.769298 [ 48.002367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11676 16:45:52.769643 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11678 16:45:52.805014 /lava-10576281/1/../bin/lava-test-case
11679 16:45:52.835327 [ 48.068854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11680 16:45:52.835697 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11682 16:45:52.858834 /lava-10576281/1/../bin/lava-test-case
11683 16:45:52.884816 [ 48.118115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11684 16:45:52.885153 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11686 16:45:52.929247 /lava-10576281/1/../bin/lava-test-case
11687 16:45:52.959376 [ 48.192799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11688 16:45:52.959713 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11690 16:45:52.981014 /lava-10576281/1/../bin/lava-test-case
11691 16:45:53.008038 [ 48.241209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11692 16:45:53.008381 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11694 16:45:53.038106 /lava-10576281/1/../bin/lava-test-case
11695 16:45:53.065284 [ 48.298108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11696 16:45:53.065612 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11698 16:45:53.086940 /lava-10576281/1/../bin/lava-test-case
11699 16:45:53.116366 [ 48.349503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11700 16:45:53.116703 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11702 16:45:53.155324 /lava-10576281/1/../bin/lava-test-case
11703 16:45:53.184501 [ 48.417571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11704 16:45:53.184829 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11706 16:45:53.206812 /lava-10576281/1/../bin/lava-test-case
11707 16:45:53.232786 [ 48.465966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11708 16:45:53.233122 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11710 16:45:53.271812 /lava-10576281/1/../bin/lava-test-case
11711 16:45:53.305215 [ 48.538063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11712 16:45:53.305577 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11714 16:45:53.326593 /lava-10576281/1/../bin/lava-test-case
11715 16:45:53.354439 [ 48.587534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11716 16:45:53.354774 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11718 16:45:53.388635 /lava-10576281/1/../bin/lava-test-case
11719 16:45:53.416304 [ 48.649398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11720 16:45:53.416637 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11722 16:45:53.437160 /lava-10576281/1/../bin/lava-test-case
11723 16:45:53.469159 [ 48.702361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11724 16:45:53.469520 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11726 16:45:53.503426 /lava-10576281/1/../bin/lava-test-case
11727 16:45:53.531000 [ 48.763879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11728 16:45:53.531333 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11730 16:45:53.553137 /lava-10576281/1/../bin/lava-test-case
11731 16:45:53.581815 [ 48.814839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11732 16:45:53.582149 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11734 16:45:53.621206 /lava-10576281/1/../bin/lava-test-case
11735 16:45:53.645399 [ 48.878777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11736 16:45:53.645729 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11738 16:45:53.667830 /lava-10576281/1/../bin/lava-test-case
11739 16:45:53.693556 [ 48.926716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11740 16:45:53.693937 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11742 16:45:53.726578 /lava-10576281/1/../bin/lava-test-case
11743 16:45:53.752957 [ 48.986233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11744 16:45:53.753312 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11746 16:45:54.785430 /lava-10576281/1/../bin/lava-test-case
11747 16:45:54.817512 [ 50.050635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11748 16:45:54.817859 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11750 16:45:55.853698 /lava-10576281/1/../bin/lava-test-case
11751 16:45:55.881698 [ 51.115092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11752 16:45:55.882058 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11753 16:45:55.882185 Bad test result: blocked
11754 16:45:55.904799 /lava-10576281/1/../bin/lava-test-case
11755 16:45:55.930474 [ 51.163883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11756 16:45:55.930859 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11758 16:45:56.973009 /lava-10576281/1/../bin/lava-test-case
11759 16:45:57.003520 [ 52.237343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11760 16:45:57.003893 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11762 16:45:57.027431 /lava-10576281/1/../bin/lava-test-case
11763 16:45:57.056623 [ 52.290115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11764 16:45:57.056980 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11766 16:45:57.092042 /lava-10576281/1/../bin/lava-test-case
11767 16:45:57.123073 [ 52.356335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11768 16:45:57.123411 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11770 16:45:57.153991 /lava-10576281/1/../bin/lava-test-case
11771 16:45:57.181618 [ 52.415341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11772 16:45:57.181989 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11774 16:45:57.204602 /lava-10576281/1/../bin/lava-test-case
11775 16:45:57.229602 [ 52.463154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11776 16:45:57.229974 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11778 16:45:57.262434 /lava-10576281/1/../bin/lava-test-case
11779 16:45:57.297556 [ 52.531078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11780 16:45:57.297914 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11782 16:45:57.319205 /lava-10576281/1/../bin/lava-test-case
11783 16:45:57.348313 [ 52.581895] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11784 16:45:57.348650 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11786 16:45:58.392448 /lava-10576281/1/../bin/lava-test-case
11787 16:45:58.423394 [ 53.657130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11788 16:45:58.423750 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11790 16:45:58.444243 /lava-10576281/1/../bin/lava-test-case
11791 16:45:58.474827 [ 53.708522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11792 16:45:58.475161 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11794 16:45:59.527561 /lava-10576281/1/../bin/lava-test-case
11795 16:45:59.558879 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11797 16:45:59.561683 [ 54.795491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11798 16:45:59.587031 /lava-10576281/1/../bin/lava-test-case
11799 16:45:59.615777 [ 54.849591] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11800 16:45:59.616101 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11802 16:46:00.663518 /lava-10576281/1/../bin/lava-test-case
11803 16:46:00.694896 [ 55.929073] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11804 16:46:00.695304 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11806 16:46:00.718515 /lava-10576281/1/../bin/lava-test-case
11807 16:46:00.747290 [ 55.981563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11808 16:46:00.747609 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11810 16:46:01.798395 /lava-10576281/1/../bin/lava-test-case
11811 16:46:01.837443 [ 57.071561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11812 16:46:01.837801 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11814 16:46:01.858422 /lava-10576281/1/../bin/lava-test-case
11815 16:46:01.996686 [ 57.230382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11816 16:46:01.997405 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11818 16:46:02.036330 /lava-10576281/1/../bin/lava-test-case
11819 16:46:02.063619 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11821 16:46:02.066272 [ 57.300624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11822 16:46:02.103223 /lava-10576281/1/../bin/lava-test-case
11823 16:46:02.130092 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11825 16:46:02.133226 [ 57.367436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11826 16:46:02.161905 /lava-10576281/1/../bin/lava-test-case
11827 16:46:02.189097 [ 57.423495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11828 16:46:02.189413 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11830 16:46:02.221955 /lava-10576281/1/../bin/lava-test-case
11831 16:46:02.246096 [ 57.480315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11832 16:46:02.246420 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11834 16:46:02.266881 /lava-10576281/1/../bin/lava-test-case
11835 16:46:02.294609 [ 57.528683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11836 16:46:02.294954 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11838 16:46:02.331203 /lava-10576281/1/../bin/lava-test-case
11839 16:46:02.362286 [ 57.596629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11840 16:46:02.362615 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11842 16:46:02.386869 /lava-10576281/1/../bin/lava-test-case
11843 16:46:02.416636 [ 57.650936] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11844 16:46:02.416957 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11846 16:46:03.466840 /lava-10576281/1/../bin/lava-test-case
11847 16:46:03.500502 [ 58.735139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11848 16:46:03.500855 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11850 16:46:03.506445 + set +x
11851 16:46:03.509928 [ 58.747679] <LAVA_SIGNAL_ENDRUN 1_bootrr 10576281_1.6.2.3.5>
11852 16:46:03.510181 Received signal: <ENDRUN> 1_bootrr 10576281_1.6.2.3.5
11853 16:46:03.510260 Ending use of test pattern.
11854 16:46:03.510323 Ending test lava.1_bootrr (10576281_1.6.2.3.5), duration 31.99
11856 16:46:03.517673 <LAVA_TEST_RUNNER EXIT>
11857 16:46:03.517946 ok: lava_test_shell seems to have completed
11858 16:46:03.518993 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: skip
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11859 16:46:03.519169 end: 4.1 lava-test-shell (duration 00:00:33) [common]
11860 16:46:03.519292 end: 4 lava-test-retry (duration 00:00:33) [common]
11861 16:46:03.519411 start: 5 finalize (timeout 00:07:20) [common]
11862 16:46:03.519532 start: 5.1 power-off (timeout 00:00:30) [common]
11863 16:46:03.519716 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11864 16:46:03.596035 >> Command sent successfully.
11865 16:46:03.598472 Returned 0 in 0 seconds
11866 16:46:03.698923 end: 5.1 power-off (duration 00:00:00) [common]
11868 16:46:03.699280 start: 5.2 read-feedback (timeout 00:07:20) [common]
11869 16:46:03.699551 Listened to connection for namespace 'common' for up to 1s
11870 16:46:04.699703 Finalising connection for namespace 'common'
11871 16:46:04.699886 Disconnecting from shell: Finalise
11872 16:46:04.699969 / #
11873 16:46:04.800306 end: 5.2 read-feedback (duration 00:00:01) [common]
11874 16:46:04.800493 end: 5 finalize (duration 00:00:01) [common]
11875 16:46:04.800618 Cleaning after the job
11876 16:46:04.800719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/ramdisk
11877 16:46:04.802817 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/kernel
11878 16:46:04.811928 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/dtb
11879 16:46:04.812160 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/nfsrootfs
11880 16:46:04.868490 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576281/tftp-deploy-522scxlt/modules
11881 16:46:04.874123 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576281
11882 16:46:05.189812 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576281
11883 16:46:05.190008 Job finished correctly