Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 16:46:47.123876 lava-dispatcher, installed at version: 2023.03
2 16:46:47.124072 start: 0 validate
3 16:46:47.124201 Start time: 2023-06-03 16:46:47.124193+00:00 (UTC)
4 16:46:47.124316 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:46:47.124442 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 16:46:47.419632 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:46:47.420379 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:46:47.714810 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:46:47.715014 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:46:48.002954 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:46:48.003685 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:46:48.299531 validate duration: 1.18
14 16:46:48.300665 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:46:48.301223 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:46:48.301680 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:46:48.302257 Not decompressing ramdisk as can be used compressed.
18 16:46:48.302685 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 16:46:48.303055 saving as /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/ramdisk/rootfs.cpio.gz
20 16:46:48.303422 total size: 43394293 (41MB)
21 16:46:48.309100 progress 0% (0MB)
22 16:46:48.345362 progress 5% (2MB)
23 16:46:48.360652 progress 10% (4MB)
24 16:46:48.372849 progress 15% (6MB)
25 16:46:48.385387 progress 20% (8MB)
26 16:46:48.396842 progress 25% (10MB)
27 16:46:48.408140 progress 30% (12MB)
28 16:46:48.419264 progress 35% (14MB)
29 16:46:48.430593 progress 40% (16MB)
30 16:46:48.441689 progress 45% (18MB)
31 16:46:48.453156 progress 50% (20MB)
32 16:46:48.464390 progress 55% (22MB)
33 16:46:48.475613 progress 60% (24MB)
34 16:46:48.486555 progress 65% (26MB)
35 16:46:48.497792 progress 70% (29MB)
36 16:46:48.508697 progress 75% (31MB)
37 16:46:48.520015 progress 80% (33MB)
38 16:46:48.531019 progress 85% (35MB)
39 16:46:48.542377 progress 90% (37MB)
40 16:46:48.553440 progress 95% (39MB)
41 16:46:48.564232 progress 100% (41MB)
42 16:46:48.564406 41MB downloaded in 0.26s (158.57MB/s)
43 16:46:48.564572 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:46:48.564815 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:46:48.564907 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:46:48.564996 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:46:48.565131 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:46:48.565208 saving as /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/kernel/Image
50 16:46:48.565273 total size: 45746688 (43MB)
51 16:46:48.565335 No compression specified
52 16:46:48.566465 progress 0% (0MB)
53 16:46:48.578120 progress 5% (2MB)
54 16:46:48.589720 progress 10% (4MB)
55 16:46:48.601411 progress 15% (6MB)
56 16:46:48.613023 progress 20% (8MB)
57 16:46:48.624863 progress 25% (10MB)
58 16:46:48.636583 progress 30% (13MB)
59 16:46:48.648609 progress 35% (15MB)
60 16:46:48.660210 progress 40% (17MB)
61 16:46:48.672030 progress 45% (19MB)
62 16:46:48.683774 progress 50% (21MB)
63 16:46:48.695258 progress 55% (24MB)
64 16:46:48.706882 progress 60% (26MB)
65 16:46:48.718550 progress 65% (28MB)
66 16:46:48.730396 progress 70% (30MB)
67 16:46:48.742183 progress 75% (32MB)
68 16:46:48.754060 progress 80% (34MB)
69 16:46:48.765644 progress 85% (37MB)
70 16:46:48.777501 progress 90% (39MB)
71 16:46:48.788991 progress 95% (41MB)
72 16:46:48.800530 progress 100% (43MB)
73 16:46:48.800684 43MB downloaded in 0.24s (185.33MB/s)
74 16:46:48.800841 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:46:48.801083 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:46:48.801264 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:46:48.801381 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:46:48.801515 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:46:48.801613 saving as /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/dtb/mt8192-asurada-spherion-r0.dtb
81 16:46:48.801678 total size: 46924 (0MB)
82 16:46:48.801739 No compression specified
83 16:46:48.802862 progress 69% (0MB)
84 16:46:48.803143 progress 100% (0MB)
85 16:46:48.803339 0MB downloaded in 0.00s (26.99MB/s)
86 16:46:48.803462 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:46:48.803683 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:46:48.803768 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:46:48.803850 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:46:48.803960 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:46:48.804028 saving as /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/modules/modules.tar
93 16:46:48.804089 total size: 8545664 (8MB)
94 16:46:48.804150 Using unxz to decompress xz
95 16:46:48.807847 progress 0% (0MB)
96 16:46:48.830226 progress 5% (0MB)
97 16:46:48.855765 progress 10% (0MB)
98 16:46:48.882880 progress 15% (1MB)
99 16:46:48.907898 progress 20% (1MB)
100 16:46:48.933657 progress 25% (2MB)
101 16:46:48.959228 progress 30% (2MB)
102 16:46:48.985039 progress 35% (2MB)
103 16:46:49.010010 progress 40% (3MB)
104 16:46:49.035254 progress 45% (3MB)
105 16:46:49.059598 progress 50% (4MB)
106 16:46:49.083399 progress 55% (4MB)
107 16:46:49.109415 progress 60% (4MB)
108 16:46:49.136539 progress 65% (5MB)
109 16:46:49.163915 progress 70% (5MB)
110 16:46:49.192708 progress 75% (6MB)
111 16:46:49.224265 progress 80% (6MB)
112 16:46:49.248118 progress 85% (6MB)
113 16:46:49.276385 progress 90% (7MB)
114 16:46:49.301658 progress 95% (7MB)
115 16:46:49.325893 progress 100% (8MB)
116 16:46:49.331754 8MB downloaded in 0.53s (15.45MB/s)
117 16:46:49.332030 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:46:49.332316 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:46:49.332412 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:46:49.332585 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:46:49.332687 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:46:49.332880 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:46:49.333191 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v
125 16:46:49.333368 makedir: /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin
126 16:46:49.333502 makedir: /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/tests
127 16:46:49.333646 makedir: /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/results
128 16:46:49.333836 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-add-keys
129 16:46:49.334009 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-add-sources
130 16:46:49.334202 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-background-process-start
131 16:46:49.334360 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-background-process-stop
132 16:46:49.334539 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-common-functions
133 16:46:49.334691 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-echo-ipv4
134 16:46:49.334842 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-install-packages
135 16:46:49.335025 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-installed-packages
136 16:46:49.335198 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-os-build
137 16:46:49.335334 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-probe-channel
138 16:46:49.335452 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-probe-ip
139 16:46:49.335572 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-target-ip
140 16:46:49.335690 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-target-mac
141 16:46:49.335806 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-target-storage
142 16:46:49.335925 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-case
143 16:46:49.336041 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-event
144 16:46:49.336157 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-feedback
145 16:46:49.336273 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-raise
146 16:46:49.336391 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-reference
147 16:46:49.336508 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-runner
148 16:46:49.336625 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-set
149 16:46:49.336744 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-test-shell
150 16:46:49.336868 Updating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-install-packages (oe)
151 16:46:49.337010 Updating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/bin/lava-installed-packages (oe)
152 16:46:49.337127 Creating /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/environment
153 16:46:49.337225 LAVA metadata
154 16:46:49.337297 - LAVA_JOB_ID=10576298
155 16:46:49.337365 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:46:49.337468 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:46:49.337534 skipped lava-vland-overlay
158 16:46:49.337610 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:46:49.337690 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:46:49.337752 skipped lava-multinode-overlay
161 16:46:49.337825 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:46:49.337926 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:46:49.338002 Loading test definitions
164 16:46:49.338096 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:46:49.338166 Using /lava-10576298 at stage 0
166 16:46:49.338449 uuid=10576298_1.5.2.3.1 testdef=None
167 16:46:49.338535 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:46:49.338621 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:46:49.339283 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:46:49.339504 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:46:49.340102 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:46:49.340377 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:46:49.340975 runner path: /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/0/tests/0_igt-gpu-panfrost test_uuid 10576298_1.5.2.3.1
176 16:46:49.341127 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:46:49.341340 Creating lava-test-runner.conf files
179 16:46:49.341421 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576298/lava-overlay-d64dg23v/lava-10576298/0 for stage 0
180 16:46:49.341518 - 0_igt-gpu-panfrost
181 16:46:49.341616 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:46:49.341709 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:46:49.348347 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:46:49.348464 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:46:49.348580 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:46:49.348695 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:46:49.348809 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:46:50.714800 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 16:46:50.715209 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 16:46:50.715364 extracting modules file /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576298/extract-overlay-ramdisk-1aeixfdi/ramdisk
191 16:46:50.930688 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:46:50.930843 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 16:46:50.930944 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576298/compress-overlay-icwqji38/overlay-1.5.2.4.tar.gz to ramdisk
194 16:46:50.931018 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576298/compress-overlay-icwqji38/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576298/extract-overlay-ramdisk-1aeixfdi/ramdisk
195 16:46:50.937307 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:46:50.937420 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 16:46:50.937513 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:46:50.937602 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 16:46:50.937681 Building ramdisk /var/lib/lava/dispatcher/tmp/10576298/extract-overlay-ramdisk-1aeixfdi/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576298/extract-overlay-ramdisk-1aeixfdi/ramdisk
200 16:46:51.911396 >> 369037 blocks
201 16:46:57.752025 rename /var/lib/lava/dispatcher/tmp/10576298/extract-overlay-ramdisk-1aeixfdi/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/ramdisk/ramdisk.cpio.gz
202 16:46:57.752583 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 16:46:57.752770 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 16:46:57.752929 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 16:46:57.753101 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/kernel/Image'
206 16:47:09.850693 Returned 0 in 12 seconds
207 16:47:09.951373 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/kernel/image.itb
208 16:47:10.704182 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:47:10.704616 output: Created: Sat Jun 3 17:47:10 2023
210 16:47:10.704729 output: Image 0 (kernel-1)
211 16:47:10.704826 output: Description:
212 16:47:10.704920 output: Created: Sat Jun 3 17:47:10 2023
213 16:47:10.705013 output: Type: Kernel Image
214 16:47:10.705104 output: Compression: lzma compressed
215 16:47:10.705195 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
216 16:47:10.705290 output: Architecture: AArch64
217 16:47:10.705380 output: OS: Linux
218 16:47:10.705469 output: Load Address: 0x00000000
219 16:47:10.705562 output: Entry Point: 0x00000000
220 16:47:10.705655 output: Hash algo: crc32
221 16:47:10.705742 output: Hash value: b48eba69
222 16:47:10.705828 output: Image 1 (fdt-1)
223 16:47:10.705914 output: Description: mt8192-asurada-spherion-r0
224 16:47:10.705999 output: Created: Sat Jun 3 17:47:10 2023
225 16:47:10.706084 output: Type: Flat Device Tree
226 16:47:10.706168 output: Compression: uncompressed
227 16:47:10.706252 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 16:47:10.706337 output: Architecture: AArch64
229 16:47:10.706421 output: Hash algo: crc32
230 16:47:10.706504 output: Hash value: 1df858fa
231 16:47:10.706589 output: Image 2 (ramdisk-1)
232 16:47:10.706673 output: Description: unavailable
233 16:47:10.706758 output: Created: Sat Jun 3 17:47:10 2023
234 16:47:10.706843 output: Type: RAMDisk Image
235 16:47:10.706929 output: Compression: Unknown Compression
236 16:47:10.707013 output: Data Size: 56373837 Bytes = 55052.58 KiB = 53.76 MiB
237 16:47:10.707098 output: Architecture: AArch64
238 16:47:10.707190 output: OS: Linux
239 16:47:10.707312 output: Load Address: unavailable
240 16:47:10.707398 output: Entry Point: unavailable
241 16:47:10.707483 output: Hash algo: crc32
242 16:47:10.707566 output: Hash value: b4a1362d
243 16:47:10.707650 output: Default Configuration: 'conf-1'
244 16:47:10.707735 output: Configuration 0 (conf-1)
245 16:47:10.707819 output: Description: mt8192-asurada-spherion-r0
246 16:47:10.707903 output: Kernel: kernel-1
247 16:47:10.707987 output: Init Ramdisk: ramdisk-1
248 16:47:10.708070 output: FDT: fdt-1
249 16:47:10.708154 output: Loadables: kernel-1
250 16:47:10.708238 output:
251 16:47:10.708489 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 16:47:10.708634 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 16:47:10.708784 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 16:47:10.708921 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 16:47:10.709038 No LXC device requested
256 16:47:10.709150 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:47:10.709282 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 16:47:10.709403 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:47:10.709509 Checking files for TFTP limit of 4294967296 bytes.
260 16:47:10.710257 end: 1 tftp-deploy (duration 00:00:22) [common]
261 16:47:10.710399 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:47:10.710526 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:47:10.710699 substitutions:
264 16:47:10.710798 - {DTB}: 10576298/tftp-deploy-pqkgui2f/dtb/mt8192-asurada-spherion-r0.dtb
265 16:47:10.710898 - {INITRD}: 10576298/tftp-deploy-pqkgui2f/ramdisk/ramdisk.cpio.gz
266 16:47:10.710990 - {KERNEL}: 10576298/tftp-deploy-pqkgui2f/kernel/Image
267 16:47:10.711080 - {LAVA_MAC}: None
268 16:47:10.711206 - {PRESEED_CONFIG}: None
269 16:47:10.711364 - {PRESEED_LOCAL}: None
270 16:47:10.711452 - {RAMDISK}: 10576298/tftp-deploy-pqkgui2f/ramdisk/ramdisk.cpio.gz
271 16:47:10.711570 - {ROOT_PART}: None
272 16:47:10.711656 - {ROOT}: None
273 16:47:10.711742 - {SERVER_IP}: 192.168.201.1
274 16:47:10.711829 - {TEE}: None
275 16:47:10.711917 Parsed boot commands:
276 16:47:10.712064 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:47:10.712296 Parsed boot commands: tftpboot 192.168.201.1 10576298/tftp-deploy-pqkgui2f/kernel/image.itb 10576298/tftp-deploy-pqkgui2f/kernel/cmdline
278 16:47:10.712427 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:47:10.712554 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:47:10.712688 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:47:10.712815 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:47:10.712922 Not connected, no need to disconnect.
283 16:47:10.713033 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:47:10.713182 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:47:10.713283 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
286 16:47:10.717354 Setting prompt string to ['lava-test: # ']
287 16:47:10.717782 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:47:10.717931 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:47:10.718067 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:47:10.718198 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:47:10.718537 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 16:47:15.851556 >> Command sent successfully.
293 16:47:15.854058 Returned 0 in 5 seconds
294 16:47:15.954498 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 16:47:15.955084 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 16:47:15.955202 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 16:47:15.955302 Setting prompt string to 'Starting depthcharge on Spherion...'
299 16:47:15.955367 Changing prompt to 'Starting depthcharge on Spherion...'
300 16:47:15.955435 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 16:47:15.955692 [Enter `^Ec?' for help]
302 16:47:16.130492
303 16:47:16.130667
304 16:47:16.130772 F0: 102B 0000
305 16:47:16.130878
306 16:47:16.130980 F3: 1001 0000 [0200]
307 16:47:16.134267
308 16:47:16.134378 F3: 1001 0000
309 16:47:16.134466
310 16:47:16.134529 F7: 102D 0000
311 16:47:16.134588
312 16:47:16.137603 F1: 0000 0000
313 16:47:16.137688
314 16:47:16.137764 V0: 0000 0000 [0001]
315 16:47:16.137829
316 16:47:16.140448 00: 0007 8000
317 16:47:16.140542
318 16:47:16.140610 01: 0000 0000
319 16:47:16.140673
320 16:47:16.144101 BP: 0C00 0209 [0000]
321 16:47:16.144212
322 16:47:16.144334 G0: 1182 0000
323 16:47:16.144484
324 16:47:16.147506 EC: 0000 0021 [4000]
325 16:47:16.147618
326 16:47:16.147714 S7: 0000 0000 [0000]
327 16:47:16.147803
328 16:47:16.151104 CC: 0000 0000 [0001]
329 16:47:16.151267
330 16:47:16.151370 T0: 0000 0040 [010F]
331 16:47:16.151436
332 16:47:16.151497 Jump to BL
333 16:47:16.151555
334 16:47:16.178484
335 16:47:16.178640
336 16:47:16.178729
337 16:47:16.184714 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 16:47:16.187754 ARM64: Exception handlers installed.
339 16:47:16.191803 ARM64: Testing exception
340 16:47:16.195038 ARM64: Done test exception
341 16:47:16.201353 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 16:47:16.211707 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 16:47:16.218185 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 16:47:16.228706 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 16:47:16.235423 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 16:47:16.245398 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 16:47:16.256323 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 16:47:16.262658 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 16:47:16.280891 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 16:47:16.284092 WDT: Last reset was cold boot
351 16:47:16.287520 SPI1(PAD0) initialized at 2873684 Hz
352 16:47:16.290255 SPI5(PAD0) initialized at 992727 Hz
353 16:47:16.294954 VBOOT: Loading verstage.
354 16:47:16.300451 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 16:47:16.303746 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 16:47:16.307296 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 16:47:16.311007 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 16:47:16.317924 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 16:47:16.324543 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 16:47:16.335475 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 16:47:16.335619
362 16:47:16.335693
363 16:47:16.345288 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 16:47:16.348776 ARM64: Exception handlers installed.
365 16:47:16.352023 ARM64: Testing exception
366 16:47:16.352115 ARM64: Done test exception
367 16:47:16.359328 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 16:47:16.362628 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 16:47:16.376353 Probing TPM: . done!
370 16:47:16.376497 TPM ready after 0 ms
371 16:47:16.384536 Connected to device vid:did:rid of 1ae0:0028:00
372 16:47:16.391369 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 16:47:16.449322 Initialized TPM device CR50 revision 0
374 16:47:16.460603 tlcl_send_startup: Startup return code is 0
375 16:47:16.460751 TPM: setup succeeded
376 16:47:16.472899 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 16:47:16.481723 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:47:16.492893 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 16:47:16.503340 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 16:47:16.506589 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 16:47:16.511093 in-header: 03 07 00 00 08 00 00 00
382 16:47:16.514936 in-data: aa e4 47 04 13 02 00 00
383 16:47:16.518293 Chrome EC: UHEPI supported
384 16:47:16.525603 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 16:47:16.528880 in-header: 03 95 00 00 08 00 00 00
386 16:47:16.532705 in-data: 18 20 20 08 00 00 00 00
387 16:47:16.532796 Phase 1
388 16:47:16.536337 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 16:47:16.543296 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 16:47:16.547081 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 16:47:16.551130 Recovery requested (1009000e)
392 16:47:16.559890 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 16:47:16.565232 tlcl_extend: response is 0
394 16:47:16.575046 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 16:47:16.580457 tlcl_extend: response is 0
396 16:47:16.587521 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 16:47:16.607065 read SPI 0x210d4 0x2173b: 15143 us, 9048 KB/s, 72.384 Mbps
398 16:47:16.613690 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 16:47:16.613867
400 16:47:16.613967
401 16:47:16.623413 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 16:47:16.626733 ARM64: Exception handlers installed.
403 16:47:16.630503 ARM64: Testing exception
404 16:47:16.630593 ARM64: Done test exception
405 16:47:16.652679 pmic_efuse_setting: Set efuses in 11 msecs
406 16:47:16.656389 pmwrap_interface_init: Select PMIF_VLD_RDY
407 16:47:16.662585 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 16:47:16.665985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 16:47:16.672617 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 16:47:16.676151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 16:47:16.680006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 16:47:16.687052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 16:47:16.690996 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 16:47:16.694347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 16:47:16.702414 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 16:47:16.705507 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 16:47:16.708976 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 16:47:16.712978 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 16:47:16.719512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 16:47:16.723250 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 16:47:16.730930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 16:47:16.737827 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 16:47:16.741265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 16:47:16.749246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 16:47:16.753736 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 16:47:16.760868 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 16:47:16.764784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 16:47:16.771598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 16:47:16.774701 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 16:47:16.783408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 16:47:16.785920 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 16:47:16.793196 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 16:47:16.797201 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 16:47:16.800706 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 16:47:16.807675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 16:47:16.812278 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 16:47:16.815409 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 16:47:16.822733 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 16:47:16.826618 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 16:47:16.833479 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 16:47:16.837151 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 16:47:16.840540 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 16:47:16.848399 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 16:47:16.852461 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 16:47:16.856001 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 16:47:16.859748 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 16:47:16.866703 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 16:47:16.870614 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 16:47:16.873775 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 16:47:16.877833 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 16:47:16.881461 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 16:47:16.885965 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 16:47:16.892153 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 16:47:16.895806 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 16:47:16.899910 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 16:47:16.903361 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 16:47:16.906817 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 16:47:16.914390 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 16:47:16.925456 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 16:47:16.928594 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 16:47:16.935597 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 16:47:16.946602 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 16:47:16.950595 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 16:47:16.954315 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:47:16.957777 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 16:47:16.966574 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
467 16:47:16.969645 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 16:47:16.977813 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 16:47:16.980924 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 16:47:16.990242 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 16:47:16.999749 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 16:47:17.008922 [RTC]rtc_get_frequency_meter,154: input=11, output=788
473 16:47:17.018411 [RTC]rtc_get_frequency_meter,154: input=13, output=820
474 16:47:17.028129 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 16:47:17.038043 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 16:47:17.047390 [RTC]rtc_get_frequency_meter,154: input=12, output=806
477 16:47:17.051436 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 16:47:17.054652 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 16:47:17.059104 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 16:47:17.065775 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 16:47:17.069654 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 16:47:17.073998 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 16:47:17.077295 ADC[4]: Raw value=904433 ID=7
484 16:47:17.077409 ADC[3]: Raw value=213916 ID=1
485 16:47:17.081299 RAM Code: 0x71
486 16:47:17.085680 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 16:47:17.088133 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 16:47:17.099866 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 16:47:17.103799 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 16:47:17.106724 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 16:47:17.110432 in-header: 03 07 00 00 08 00 00 00
492 16:47:17.114812 in-data: aa e4 47 04 13 02 00 00
493 16:47:17.118148 Chrome EC: UHEPI supported
494 16:47:17.125412 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 16:47:17.128949 in-header: 03 95 00 00 08 00 00 00
496 16:47:17.133290 in-data: 18 20 20 08 00 00 00 00
497 16:47:17.133397 MRC: failed to locate region type 0.
498 16:47:17.139990 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 16:47:17.143971 DRAM-K: Running full calibration
500 16:47:17.151312 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 16:47:17.151440 header.status = 0x0
502 16:47:17.154951 header.version = 0x6 (expected: 0x6)
503 16:47:17.158808 header.size = 0xd00 (expected: 0xd00)
504 16:47:17.158907 header.flags = 0x0
505 16:47:17.165675 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 16:47:17.184305 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
507 16:47:17.192131 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 16:47:17.195473 dram_init: ddr_geometry: 2
509 16:47:17.195623 [EMI] MDL number = 2
510 16:47:17.199318 [EMI] Get MDL freq = 0
511 16:47:17.199415 dram_init: ddr_type: 0
512 16:47:17.203241 is_discrete_lpddr4: 1
513 16:47:17.206977 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 16:47:17.207080
515 16:47:17.207200
516 16:47:17.207279 [Bian_co] ETT version 0.0.0.1
517 16:47:17.213822 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 16:47:17.213930
519 16:47:17.217079 dramc_set_vcore_voltage set vcore to 650000
520 16:47:17.221386 Read voltage for 800, 4
521 16:47:17.221496 Vio18 = 0
522 16:47:17.221564 Vcore = 650000
523 16:47:17.221627 Vdram = 0
524 16:47:17.224551 Vddq = 0
525 16:47:17.224644 Vmddr = 0
526 16:47:17.227929 dram_init: config_dvfs: 1
527 16:47:17.232104 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 16:47:17.235179 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 16:47:17.238908 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 16:47:17.246004 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 16:47:17.248916 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 16:47:17.253004 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 16:47:17.253119 MEM_TYPE=3, freq_sel=18
534 16:47:17.256302 sv_algorithm_assistance_LP4_1600
535 16:47:17.262854 ============ PULL DRAM RESETB DOWN ============
536 16:47:17.266940 ========== PULL DRAM RESETB DOWN end =========
537 16:47:17.270551 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 16:47:17.274189 ===================================
539 16:47:17.277753 LPDDR4 DRAM CONFIGURATION
540 16:47:17.277855 ===================================
541 16:47:17.281468 EX_ROW_EN[0] = 0x0
542 16:47:17.284884 EX_ROW_EN[1] = 0x0
543 16:47:17.284982 LP4Y_EN = 0x0
544 16:47:17.287727 WORK_FSP = 0x0
545 16:47:17.287815 WL = 0x2
546 16:47:17.291486 RL = 0x2
547 16:47:17.291593 BL = 0x2
548 16:47:17.294788 RPST = 0x0
549 16:47:17.294876 RD_PRE = 0x0
550 16:47:17.297566 WR_PRE = 0x1
551 16:47:17.297653 WR_PST = 0x0
552 16:47:17.301261 DBI_WR = 0x0
553 16:47:17.301352 DBI_RD = 0x0
554 16:47:17.304395 OTF = 0x1
555 16:47:17.307563 ===================================
556 16:47:17.310911 ===================================
557 16:47:17.311001 ANA top config
558 16:47:17.314445 ===================================
559 16:47:17.317702 DLL_ASYNC_EN = 0
560 16:47:17.320795 ALL_SLAVE_EN = 1
561 16:47:17.320887 NEW_RANK_MODE = 1
562 16:47:17.324572 DLL_IDLE_MODE = 1
563 16:47:17.327583 LP45_APHY_COMB_EN = 1
564 16:47:17.330943 TX_ODT_DIS = 1
565 16:47:17.333979 NEW_8X_MODE = 1
566 16:47:17.337749 ===================================
567 16:47:17.340955 ===================================
568 16:47:17.341046 data_rate = 1600
569 16:47:17.344250 CKR = 1
570 16:47:17.347560 DQ_P2S_RATIO = 8
571 16:47:17.351287 ===================================
572 16:47:17.354412 CA_P2S_RATIO = 8
573 16:47:17.358188 DQ_CA_OPEN = 0
574 16:47:17.358304 DQ_SEMI_OPEN = 0
575 16:47:17.361343 CA_SEMI_OPEN = 0
576 16:47:17.364959 CA_FULL_RATE = 0
577 16:47:17.367899 DQ_CKDIV4_EN = 1
578 16:47:17.371514 CA_CKDIV4_EN = 1
579 16:47:17.374651 CA_PREDIV_EN = 0
580 16:47:17.374761 PH8_DLY = 0
581 16:47:17.378057 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 16:47:17.381254 DQ_AAMCK_DIV = 4
583 16:47:17.384381 CA_AAMCK_DIV = 4
584 16:47:17.388570 CA_ADMCK_DIV = 4
585 16:47:17.391057 DQ_TRACK_CA_EN = 0
586 16:47:17.394809 CA_PICK = 800
587 16:47:17.394930 CA_MCKIO = 800
588 16:47:17.397891 MCKIO_SEMI = 0
589 16:47:17.401815 PLL_FREQ = 3068
590 16:47:17.405321 DQ_UI_PI_RATIO = 32
591 16:47:17.409198 CA_UI_PI_RATIO = 0
592 16:47:17.409307 ===================================
593 16:47:17.412557 ===================================
594 16:47:17.416291 memory_type:LPDDR4
595 16:47:17.420082 GP_NUM : 10
596 16:47:17.420276 SRAM_EN : 1
597 16:47:17.423683 MD32_EN : 0
598 16:47:17.427735 ===================================
599 16:47:17.427858 [ANA_INIT] >>>>>>>>>>>>>>
600 16:47:17.431201 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 16:47:17.435333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 16:47:17.437956 ===================================
603 16:47:17.440981 data_rate = 1600,PCW = 0X7600
604 16:47:17.444272 ===================================
605 16:47:17.448064 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 16:47:17.450651 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 16:47:17.457393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 16:47:17.464378 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 16:47:17.467332 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 16:47:17.470553 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 16:47:17.470709 [ANA_INIT] flow start
612 16:47:17.473830 [ANA_INIT] PLL >>>>>>>>
613 16:47:17.477121 [ANA_INIT] PLL <<<<<<<<
614 16:47:17.477237 [ANA_INIT] MIDPI >>>>>>>>
615 16:47:17.480800 [ANA_INIT] MIDPI <<<<<<<<
616 16:47:17.483787 [ANA_INIT] DLL >>>>>>>>
617 16:47:17.483886 [ANA_INIT] flow end
618 16:47:17.491005 ============ LP4 DIFF to SE enter ============
619 16:47:17.493781 ============ LP4 DIFF to SE exit ============
620 16:47:17.497652 [ANA_INIT] <<<<<<<<<<<<<
621 16:47:17.497747 [Flow] Enable top DCM control >>>>>
622 16:47:17.500341 [Flow] Enable top DCM control <<<<<
623 16:47:17.504895 Enable DLL master slave shuffle
624 16:47:17.510416 ==============================================================
625 16:47:17.513887 Gating Mode config
626 16:47:17.517001 ==============================================================
627 16:47:17.520280 Config description:
628 16:47:17.530321 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 16:47:17.537282 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 16:47:17.540287 SELPH_MODE 0: By rank 1: By Phase
631 16:47:17.547586 ==============================================================
632 16:47:17.550395 GAT_TRACK_EN = 1
633 16:47:17.553612 RX_GATING_MODE = 2
634 16:47:17.556821 RX_GATING_TRACK_MODE = 2
635 16:47:17.556931 SELPH_MODE = 1
636 16:47:17.561164 PICG_EARLY_EN = 1
637 16:47:17.563680 VALID_LAT_VALUE = 1
638 16:47:17.570325 ==============================================================
639 16:47:17.573637 Enter into Gating configuration >>>>
640 16:47:17.577031 Exit from Gating configuration <<<<
641 16:47:17.580324 Enter into DVFS_PRE_config >>>>>
642 16:47:17.590043 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 16:47:17.593054 Exit from DVFS_PRE_config <<<<<
644 16:47:17.596779 Enter into PICG configuration >>>>
645 16:47:17.600169 Exit from PICG configuration <<<<
646 16:47:17.603102 [RX_INPUT] configuration >>>>>
647 16:47:17.606788 [RX_INPUT] configuration <<<<<
648 16:47:17.610223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 16:47:17.616366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 16:47:17.623500 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 16:47:17.629826 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 16:47:17.636264 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 16:47:17.639476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 16:47:17.646583 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 16:47:17.650370 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 16:47:17.653166 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 16:47:17.656258 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 16:47:17.662911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 16:47:17.666517 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 16:47:17.669846 ===================================
661 16:47:17.673299 LPDDR4 DRAM CONFIGURATION
662 16:47:17.676010 ===================================
663 16:47:17.676097 EX_ROW_EN[0] = 0x0
664 16:47:17.679410 EX_ROW_EN[1] = 0x0
665 16:47:17.679491 LP4Y_EN = 0x0
666 16:47:17.684153 WORK_FSP = 0x0
667 16:47:17.684237 WL = 0x2
668 16:47:17.685910 RL = 0x2
669 16:47:17.685984 BL = 0x2
670 16:47:17.689349 RPST = 0x0
671 16:47:17.689424 RD_PRE = 0x0
672 16:47:17.692670 WR_PRE = 0x1
673 16:47:17.692784 WR_PST = 0x0
674 16:47:17.696236 DBI_WR = 0x0
675 16:47:17.699451 DBI_RD = 0x0
676 16:47:17.699542 OTF = 0x1
677 16:47:17.702582 ===================================
678 16:47:17.706425 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 16:47:17.709282 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 16:47:17.715924 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 16:47:17.719151 ===================================
682 16:47:17.722771 LPDDR4 DRAM CONFIGURATION
683 16:47:17.725904 ===================================
684 16:47:17.726005 EX_ROW_EN[0] = 0x10
685 16:47:17.729486 EX_ROW_EN[1] = 0x0
686 16:47:17.729618 LP4Y_EN = 0x0
687 16:47:17.732563 WORK_FSP = 0x0
688 16:47:17.732653 WL = 0x2
689 16:47:17.735663 RL = 0x2
690 16:47:17.735753 BL = 0x2
691 16:47:17.739647 RPST = 0x0
692 16:47:17.739738 RD_PRE = 0x0
693 16:47:17.742642 WR_PRE = 0x1
694 16:47:17.742729 WR_PST = 0x0
695 16:47:17.745911 DBI_WR = 0x0
696 16:47:17.745998 DBI_RD = 0x0
697 16:47:17.749196 OTF = 0x1
698 16:47:17.752574 ===================================
699 16:47:17.759287 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 16:47:17.762371 nWR fixed to 40
701 16:47:17.765805 [ModeRegInit_LP4] CH0 RK0
702 16:47:17.765901 [ModeRegInit_LP4] CH0 RK1
703 16:47:17.769167 [ModeRegInit_LP4] CH1 RK0
704 16:47:17.772556 [ModeRegInit_LP4] CH1 RK1
705 16:47:17.772645 match AC timing 13
706 16:47:17.779581 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 16:47:17.782378 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 16:47:17.785607 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 16:47:17.792468 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 16:47:17.795970 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 16:47:17.799221 [EMI DOE] emi_dcm 0
712 16:47:17.802037 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 16:47:17.802130 ==
714 16:47:17.805210 Dram Type= 6, Freq= 0, CH_0, rank 0
715 16:47:17.808851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 16:47:17.808948 ==
717 16:47:17.816021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 16:47:17.821949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 16:47:17.830209 [CA 0] Center 38 (7~69) winsize 63
720 16:47:17.833089 [CA 1] Center 37 (7~68) winsize 62
721 16:47:17.836386 [CA 2] Center 34 (4~65) winsize 62
722 16:47:17.839804 [CA 3] Center 35 (4~66) winsize 63
723 16:47:17.843682 [CA 4] Center 34 (3~65) winsize 63
724 16:47:17.847052 [CA 5] Center 33 (3~64) winsize 62
725 16:47:17.847149
726 16:47:17.849666 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 16:47:17.849752
728 16:47:17.853177 [CATrainingPosCal] consider 1 rank data
729 16:47:17.856420 u2DelayCellTimex100 = 270/100 ps
730 16:47:17.859968 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
731 16:47:17.866195 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
732 16:47:17.869900 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 16:47:17.872794 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
734 16:47:17.876233 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 16:47:17.879669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 16:47:17.879768
737 16:47:17.882788 CA PerBit enable=1, Macro0, CA PI delay=33
738 16:47:17.882880
739 16:47:17.886468 [CBTSetCACLKResult] CA Dly = 33
740 16:47:17.889284 CS Dly: 5 (0~36)
741 16:47:17.889367 ==
742 16:47:17.892813 Dram Type= 6, Freq= 0, CH_0, rank 1
743 16:47:17.895923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 16:47:17.896005 ==
745 16:47:17.903353 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 16:47:17.906964 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 16:47:17.916314 [CA 0] Center 38 (7~69) winsize 63
748 16:47:17.919976 [CA 1] Center 37 (7~68) winsize 62
749 16:47:17.922614 [CA 2] Center 35 (4~66) winsize 63
750 16:47:17.926094 [CA 3] Center 35 (4~66) winsize 63
751 16:47:17.929544 [CA 4] Center 34 (3~65) winsize 63
752 16:47:17.932670 [CA 5] Center 33 (3~64) winsize 62
753 16:47:17.932767
754 16:47:17.936106 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 16:47:17.936199
756 16:47:17.939924 [CATrainingPosCal] consider 2 rank data
757 16:47:17.943435 u2DelayCellTimex100 = 270/100 ps
758 16:47:17.945976 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
759 16:47:17.952987 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 16:47:17.956455 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
761 16:47:17.959464 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
762 16:47:17.963461 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 16:47:17.965931 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 16:47:17.966024
765 16:47:17.969316 CA PerBit enable=1, Macro0, CA PI delay=33
766 16:47:17.969405
767 16:47:17.973675 [CBTSetCACLKResult] CA Dly = 33
768 16:47:17.973769 CS Dly: 6 (0~38)
769 16:47:17.976017
770 16:47:17.979624 ----->DramcWriteLeveling(PI) begin...
771 16:47:17.979721 ==
772 16:47:17.979789 Dram Type= 6, Freq= 0, CH_0, rank 0
773 16:47:17.987063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 16:47:17.987233 ==
775 16:47:17.990470 Write leveling (Byte 0): 31 => 31
776 16:47:17.990561 Write leveling (Byte 1): 26 => 26
777 16:47:17.994151 DramcWriteLeveling(PI) end<-----
778 16:47:17.994247
779 16:47:17.994315 ==
780 16:47:17.998117 Dram Type= 6, Freq= 0, CH_0, rank 0
781 16:47:18.000924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 16:47:18.004517 ==
783 16:47:18.004615 [Gating] SW mode calibration
784 16:47:18.011664 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 16:47:18.018237 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 16:47:18.021448 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 16:47:18.028088 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 16:47:18.031474 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 16:47:18.034891 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
790 16:47:18.038039 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:47:18.044815 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:47:18.048304 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:47:18.051452 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:47:18.058534 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:47:18.061875 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:47:18.064613 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 16:47:18.071620 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 16:47:18.075162 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 16:47:18.078231 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 16:47:18.085321 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 16:47:18.088541 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 16:47:18.091435 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 16:47:18.098589 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 16:47:18.101340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:47:18.105342 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
806 16:47:18.112250 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 16:47:18.114709 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 16:47:18.117877 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 16:47:18.124313 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 16:47:18.127993 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 16:47:18.131684 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 16:47:18.137851 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
813 16:47:18.141166 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
814 16:47:18.144747 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 16:47:18.151036 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 16:47:18.154201 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 16:47:18.158265 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 16:47:18.161042 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 16:47:18.167887 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
820 16:47:18.171505 0 10 8 | B1->B0 | 3030 2a2a | 1 0 | (1 0) (1 1)
821 16:47:18.174146 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
822 16:47:18.181041 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 16:47:18.184066 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 16:47:18.191005 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 16:47:18.194189 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 16:47:18.197372 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 16:47:18.200722 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
828 16:47:18.207352 0 11 8 | B1->B0 | 2727 4242 | 0 0 | (0 0) (0 0)
829 16:47:18.210477 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
830 16:47:18.214426 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 16:47:18.220763 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 16:47:18.223691 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 16:47:18.227211 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 16:47:18.233749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 16:47:18.237251 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 16:47:18.240520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 16:47:18.247074 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 16:47:18.250605 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:47:18.253772 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:47:18.260039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:47:18.263484 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:47:18.266889 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:47:18.273256 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:47:18.277300 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:47:18.280084 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 16:47:18.286429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 16:47:18.290295 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 16:47:18.293415 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 16:47:18.299719 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 16:47:18.303404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 16:47:18.306693 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 16:47:18.313762 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
853 16:47:18.316692 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 16:47:18.320985 Total UI for P1: 0, mck2ui 16
855 16:47:18.323526 best dqsien dly found for B0: ( 0, 14, 8)
856 16:47:18.326589 Total UI for P1: 0, mck2ui 16
857 16:47:18.329866 best dqsien dly found for B1: ( 0, 14, 10)
858 16:47:18.332922 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 16:47:18.336207 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 16:47:18.336334
861 16:47:18.340569 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 16:47:18.343101 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 16:47:18.346613 [Gating] SW calibration Done
864 16:47:18.346708 ==
865 16:47:18.349525 Dram Type= 6, Freq= 0, CH_0, rank 0
866 16:47:18.353184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 16:47:18.353284 ==
868 16:47:18.357214 RX Vref Scan: 0
869 16:47:18.357314
870 16:47:18.357386 RX Vref 0 -> 0, step: 1
871 16:47:18.360099
872 16:47:18.360188 RX Delay -130 -> 252, step: 16
873 16:47:18.366847 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 16:47:18.370501 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 16:47:18.373566 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 16:47:18.376974 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 16:47:18.380198 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 16:47:18.386820 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 16:47:18.390167 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 16:47:18.393489 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 16:47:18.397070 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 16:47:18.400081 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 16:47:18.406568 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 16:47:18.410223 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 16:47:18.413512 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 16:47:18.416644 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 16:47:18.423510 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 16:47:18.426981 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 16:47:18.427087 ==
890 16:47:18.429860 Dram Type= 6, Freq= 0, CH_0, rank 0
891 16:47:18.432901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 16:47:18.432986 ==
893 16:47:18.433050 DQS Delay:
894 16:47:18.436146 DQS0 = 0, DQS1 = 0
895 16:47:18.436236 DQM Delay:
896 16:47:18.439571 DQM0 = 88, DQM1 = 75
897 16:47:18.439653 DQ Delay:
898 16:47:18.442960 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 16:47:18.446525 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 16:47:18.449625 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 16:47:18.453605 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 16:47:18.453703
903 16:47:18.453781
904 16:47:18.453845 ==
905 16:47:18.456806 Dram Type= 6, Freq= 0, CH_0, rank 0
906 16:47:18.460668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 16:47:18.463960 ==
908 16:47:18.464056
909 16:47:18.464124
910 16:47:18.464189 TX Vref Scan disable
911 16:47:18.467482 == TX Byte 0 ==
912 16:47:18.469549 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
913 16:47:18.476335 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
914 16:47:18.476501 == TX Byte 1 ==
915 16:47:18.479663 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
916 16:47:18.486293 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
917 16:47:18.486409 ==
918 16:47:18.489890 Dram Type= 6, Freq= 0, CH_0, rank 0
919 16:47:18.492701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 16:47:18.492797 ==
921 16:47:18.505654 TX Vref=22, minBit 0, minWin=26, winSum=436
922 16:47:18.509176 TX Vref=24, minBit 0, minWin=27, winSum=440
923 16:47:18.512552 TX Vref=26, minBit 1, minWin=27, winSum=444
924 16:47:18.515920 TX Vref=28, minBit 1, minWin=27, winSum=449
925 16:47:18.519475 TX Vref=30, minBit 1, minWin=27, winSum=450
926 16:47:18.522797 TX Vref=32, minBit 2, minWin=27, winSum=448
927 16:47:18.529539 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
928 16:47:18.529665
929 16:47:18.532311 Final TX Range 1 Vref 30
930 16:47:18.532402
931 16:47:18.532488 ==
932 16:47:18.536026 Dram Type= 6, Freq= 0, CH_0, rank 0
933 16:47:18.539087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 16:47:18.539241 ==
935 16:47:18.542464
936 16:47:18.542574
937 16:47:18.542663 TX Vref Scan disable
938 16:47:18.546234 == TX Byte 0 ==
939 16:47:18.548962 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
940 16:47:18.552760 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
941 16:47:18.556225 == TX Byte 1 ==
942 16:47:18.559816 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
943 16:47:18.562575 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
944 16:47:18.565811
945 16:47:18.565910 [DATLAT]
946 16:47:18.565980 Freq=800, CH0 RK0
947 16:47:18.566041
948 16:47:18.569090 DATLAT Default: 0xa
949 16:47:18.569177 0, 0xFFFF, sum = 0
950 16:47:18.572803 1, 0xFFFF, sum = 0
951 16:47:18.572901 2, 0xFFFF, sum = 0
952 16:47:18.575584 3, 0xFFFF, sum = 0
953 16:47:18.578808 4, 0xFFFF, sum = 0
954 16:47:18.578911 5, 0xFFFF, sum = 0
955 16:47:18.582471 6, 0xFFFF, sum = 0
956 16:47:18.582570 7, 0xFFFF, sum = 0
957 16:47:18.585898 8, 0xFFFF, sum = 0
958 16:47:18.586019 9, 0x0, sum = 1
959 16:47:18.589084 10, 0x0, sum = 2
960 16:47:18.589176 11, 0x0, sum = 3
961 16:47:18.589244 12, 0x0, sum = 4
962 16:47:18.592099 best_step = 10
963 16:47:18.592186
964 16:47:18.592251 ==
965 16:47:18.595476 Dram Type= 6, Freq= 0, CH_0, rank 0
966 16:47:18.598726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 16:47:18.598819 ==
968 16:47:18.602267 RX Vref Scan: 1
969 16:47:18.602353
970 16:47:18.605572 Set Vref Range= 32 -> 127
971 16:47:18.605693
972 16:47:18.605758 RX Vref 32 -> 127, step: 1
973 16:47:18.605820
974 16:47:18.608967 RX Delay -111 -> 252, step: 8
975 16:47:18.609054
976 16:47:18.612444 Set Vref, RX VrefLevel [Byte0]: 32
977 16:47:18.615717 [Byte1]: 32
978 16:47:18.619011
979 16:47:18.619106 Set Vref, RX VrefLevel [Byte0]: 33
980 16:47:18.622758 [Byte1]: 33
981 16:47:18.626280
982 16:47:18.626389 Set Vref, RX VrefLevel [Byte0]: 34
983 16:47:18.630066 [Byte1]: 34
984 16:47:18.633682
985 16:47:18.633777 Set Vref, RX VrefLevel [Byte0]: 35
986 16:47:18.636997 [Byte1]: 35
987 16:47:18.641463
988 16:47:18.641563 Set Vref, RX VrefLevel [Byte0]: 36
989 16:47:18.645080 [Byte1]: 36
990 16:47:18.649673
991 16:47:18.649779 Set Vref, RX VrefLevel [Byte0]: 37
992 16:47:18.653101 [Byte1]: 37
993 16:47:18.657465
994 16:47:18.657574 Set Vref, RX VrefLevel [Byte0]: 38
995 16:47:18.660612 [Byte1]: 38
996 16:47:18.665221
997 16:47:18.665329 Set Vref, RX VrefLevel [Byte0]: 39
998 16:47:18.667864 [Byte1]: 39
999 16:47:18.672807
1000 16:47:18.672916 Set Vref, RX VrefLevel [Byte0]: 40
1001 16:47:18.675729 [Byte1]: 40
1002 16:47:18.680283
1003 16:47:18.680389 Set Vref, RX VrefLevel [Byte0]: 41
1004 16:47:18.683475 [Byte1]: 41
1005 16:47:18.687403
1006 16:47:18.687509 Set Vref, RX VrefLevel [Byte0]: 42
1007 16:47:18.690591 [Byte1]: 42
1008 16:47:18.695336
1009 16:47:18.695443 Set Vref, RX VrefLevel [Byte0]: 43
1010 16:47:18.698764 [Byte1]: 43
1011 16:47:18.702728
1012 16:47:18.702886 Set Vref, RX VrefLevel [Byte0]: 44
1013 16:47:18.705981 [Byte1]: 44
1014 16:47:18.710159
1015 16:47:18.710355 Set Vref, RX VrefLevel [Byte0]: 45
1016 16:47:18.713639 [Byte1]: 45
1017 16:47:18.718315
1018 16:47:18.718445 Set Vref, RX VrefLevel [Byte0]: 46
1019 16:47:18.721474 [Byte1]: 46
1020 16:47:18.725874
1021 16:47:18.725993 Set Vref, RX VrefLevel [Byte0]: 47
1022 16:47:18.728911 [Byte1]: 47
1023 16:47:18.733501
1024 16:47:18.733604 Set Vref, RX VrefLevel [Byte0]: 48
1025 16:47:18.736631 [Byte1]: 48
1026 16:47:18.740903
1027 16:47:18.741004 Set Vref, RX VrefLevel [Byte0]: 49
1028 16:47:18.744053 [Byte1]: 49
1029 16:47:18.748449
1030 16:47:18.748545 Set Vref, RX VrefLevel [Byte0]: 50
1031 16:47:18.752387 [Byte1]: 50
1032 16:47:18.756381
1033 16:47:18.756487 Set Vref, RX VrefLevel [Byte0]: 51
1034 16:47:18.760125 [Byte1]: 51
1035 16:47:18.763696
1036 16:47:18.763791 Set Vref, RX VrefLevel [Byte0]: 52
1037 16:47:18.767327 [Byte1]: 52
1038 16:47:18.771302
1039 16:47:18.771418 Set Vref, RX VrefLevel [Byte0]: 53
1040 16:47:18.774805 [Byte1]: 53
1041 16:47:18.779524
1042 16:47:18.779623 Set Vref, RX VrefLevel [Byte0]: 54
1043 16:47:18.782285 [Byte1]: 54
1044 16:47:18.787805
1045 16:47:18.787917 Set Vref, RX VrefLevel [Byte0]: 55
1046 16:47:18.790312 [Byte1]: 55
1047 16:47:18.794515
1048 16:47:18.794612 Set Vref, RX VrefLevel [Byte0]: 56
1049 16:47:18.797950 [Byte1]: 56
1050 16:47:18.801951
1051 16:47:18.802040 Set Vref, RX VrefLevel [Byte0]: 57
1052 16:47:18.805260 [Byte1]: 57
1053 16:47:18.810237
1054 16:47:18.810340 Set Vref, RX VrefLevel [Byte0]: 58
1055 16:47:18.813104 [Byte1]: 58
1056 16:47:18.817553
1057 16:47:18.817656 Set Vref, RX VrefLevel [Byte0]: 59
1058 16:47:18.820504 [Byte1]: 59
1059 16:47:18.825079
1060 16:47:18.825249 Set Vref, RX VrefLevel [Byte0]: 60
1061 16:47:18.828290 [Byte1]: 60
1062 16:47:18.832987
1063 16:47:18.833094 Set Vref, RX VrefLevel [Byte0]: 61
1064 16:47:18.836032 [Byte1]: 61
1065 16:47:18.840499
1066 16:47:18.840596 Set Vref, RX VrefLevel [Byte0]: 62
1067 16:47:18.843660 [Byte1]: 62
1068 16:47:18.848166
1069 16:47:18.848263 Set Vref, RX VrefLevel [Byte0]: 63
1070 16:47:18.851145 [Byte1]: 63
1071 16:47:18.855849
1072 16:47:18.855952 Set Vref, RX VrefLevel [Byte0]: 64
1073 16:47:18.858862 [Byte1]: 64
1074 16:47:18.863112
1075 16:47:18.863270 Set Vref, RX VrefLevel [Byte0]: 65
1076 16:47:18.866498 [Byte1]: 65
1077 16:47:18.870955
1078 16:47:18.871050 Set Vref, RX VrefLevel [Byte0]: 66
1079 16:47:18.874635 [Byte1]: 66
1080 16:47:18.878832
1081 16:47:18.878932 Set Vref, RX VrefLevel [Byte0]: 67
1082 16:47:18.881954 [Byte1]: 67
1083 16:47:18.886295
1084 16:47:18.886393 Set Vref, RX VrefLevel [Byte0]: 68
1085 16:47:18.890000 [Byte1]: 68
1086 16:47:18.894138
1087 16:47:18.894240 Set Vref, RX VrefLevel [Byte0]: 69
1088 16:47:18.897281 [Byte1]: 69
1089 16:47:18.901476
1090 16:47:18.901577 Set Vref, RX VrefLevel [Byte0]: 70
1091 16:47:18.905510 [Byte1]: 70
1092 16:47:18.908979
1093 16:47:18.909080 Set Vref, RX VrefLevel [Byte0]: 71
1094 16:47:18.912596 [Byte1]: 71
1095 16:47:18.916808
1096 16:47:18.916914 Set Vref, RX VrefLevel [Byte0]: 72
1097 16:47:18.920295 [Byte1]: 72
1098 16:47:18.924723
1099 16:47:18.924837 Final RX Vref Byte 0 = 57 to rank0
1100 16:47:18.927663 Final RX Vref Byte 1 = 63 to rank0
1101 16:47:18.931986 Final RX Vref Byte 0 = 57 to rank1
1102 16:47:18.934361 Final RX Vref Byte 1 = 63 to rank1==
1103 16:47:18.938639 Dram Type= 6, Freq= 0, CH_0, rank 0
1104 16:47:18.944478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1105 16:47:18.944596 ==
1106 16:47:18.944688 DQS Delay:
1107 16:47:18.944769 DQS0 = 0, DQS1 = 0
1108 16:47:18.947896 DQM Delay:
1109 16:47:18.947984 DQM0 = 88, DQM1 = 76
1110 16:47:18.951050 DQ Delay:
1111 16:47:18.954027 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1112 16:47:18.957478 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1113 16:47:18.960931 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1114 16:47:18.964403 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1115 16:47:18.964520
1116 16:47:18.964618
1117 16:47:18.970894 [DQSOSCAuto] RK0, (LSB)MR18= 0x2822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1118 16:47:18.974103 CH0 RK0: MR19=606, MR18=2822
1119 16:47:18.980688 CH0_RK0: MR19=0x606, MR18=0x2822, DQSOSC=399, MR23=63, INC=92, DEC=61
1120 16:47:18.980801
1121 16:47:18.984092 ----->DramcWriteLeveling(PI) begin...
1122 16:47:18.984187 ==
1123 16:47:18.987100 Dram Type= 6, Freq= 0, CH_0, rank 1
1124 16:47:18.990893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1125 16:47:18.990999 ==
1126 16:47:18.993922 Write leveling (Byte 0): 29 => 29
1127 16:47:18.997343 Write leveling (Byte 1): 28 => 28
1128 16:47:19.000386 DramcWriteLeveling(PI) end<-----
1129 16:47:19.000482
1130 16:47:19.000568 ==
1131 16:47:19.004049 Dram Type= 6, Freq= 0, CH_0, rank 1
1132 16:47:19.007267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1133 16:47:19.007362 ==
1134 16:47:19.010248 [Gating] SW mode calibration
1135 16:47:19.017118 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1136 16:47:19.023561 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1137 16:47:19.027818 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1138 16:47:19.033921 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1139 16:47:19.038044 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1140 16:47:19.040650 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1141 16:47:19.084719 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1142 16:47:19.085044 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1143 16:47:19.085138 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1144 16:47:19.085204 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 16:47:19.085493 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 16:47:19.086194 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 16:47:19.086467 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 16:47:19.086751 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 16:47:19.086824 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 16:47:19.087091 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 16:47:19.128432 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 16:47:19.128786 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 16:47:19.129073 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 16:47:19.129152 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1155 16:47:19.129632 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1156 16:47:19.130675 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 16:47:19.130942 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 16:47:19.131604 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 16:47:19.131687 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 16:47:19.131957 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 16:47:19.134708 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 16:47:19.137737 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 16:47:19.141515 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1164 16:47:19.147972 0 9 12 | B1->B0 | 302f 3434 | 1 1 | (1 1) (1 1)
1165 16:47:19.151677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1166 16:47:19.154885 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1167 16:47:19.161175 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1168 16:47:19.164240 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 16:47:19.167516 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 16:47:19.174291 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
1171 16:47:19.177633 0 10 8 | B1->B0 | 3333 2323 | 0 0 | (1 1) (0 0)
1172 16:47:19.181654 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 16:47:19.187594 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 16:47:19.190617 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 16:47:19.194579 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 16:47:19.200868 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 16:47:19.204831 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 16:47:19.207341 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1179 16:47:19.214254 0 11 8 | B1->B0 | 3636 4444 | 0 0 | (0 0) (0 0)
1180 16:47:19.217245 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1181 16:47:19.220768 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1182 16:47:19.227625 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1183 16:47:19.231151 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1184 16:47:19.235213 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 16:47:19.238763 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1186 16:47:19.242155 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1187 16:47:19.248854 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1188 16:47:19.252287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1189 16:47:19.255847 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1190 16:47:19.259599 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 16:47:19.265468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 16:47:19.268946 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 16:47:19.272180 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 16:47:19.279823 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 16:47:19.282701 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 16:47:19.285368 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 16:47:19.292349 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 16:47:19.295403 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 16:47:19.299206 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 16:47:19.305521 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 16:47:19.308686 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 16:47:19.312091 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1203 16:47:19.318549 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1204 16:47:19.321787 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 16:47:19.325140 Total UI for P1: 0, mck2ui 16
1206 16:47:19.328449 best dqsien dly found for B0: ( 0, 14, 6)
1207 16:47:19.331843 Total UI for P1: 0, mck2ui 16
1208 16:47:19.335358 best dqsien dly found for B1: ( 0, 14, 8)
1209 16:47:19.338885 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1210 16:47:19.341917 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1211 16:47:19.342037
1212 16:47:19.345414 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1213 16:47:19.348493 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1214 16:47:19.351893 [Gating] SW calibration Done
1215 16:47:19.351987 ==
1216 16:47:19.354899 Dram Type= 6, Freq= 0, CH_0, rank 1
1217 16:47:19.358442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1218 16:47:19.361597 ==
1219 16:47:19.361696 RX Vref Scan: 0
1220 16:47:19.361764
1221 16:47:19.364986 RX Vref 0 -> 0, step: 1
1222 16:47:19.365102
1223 16:47:19.367961 RX Delay -130 -> 252, step: 16
1224 16:47:19.372095 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1225 16:47:19.374759 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1226 16:47:19.378241 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1227 16:47:19.381334 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1228 16:47:19.388015 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1229 16:47:19.391676 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1230 16:47:19.394742 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1231 16:47:19.398327 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1232 16:47:19.401344 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1233 16:47:19.408226 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1234 16:47:19.411319 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1235 16:47:19.414165 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1236 16:47:19.418124 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1237 16:47:19.424850 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1238 16:47:19.427850 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1239 16:47:19.431119 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1240 16:47:19.431260 ==
1241 16:47:19.434388 Dram Type= 6, Freq= 0, CH_0, rank 1
1242 16:47:19.437987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1243 16:47:19.438079 ==
1244 16:47:19.440874 DQS Delay:
1245 16:47:19.440963 DQS0 = 0, DQS1 = 0
1246 16:47:19.444264 DQM Delay:
1247 16:47:19.444354 DQM0 = 88, DQM1 = 76
1248 16:47:19.444418 DQ Delay:
1249 16:47:19.447653 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1250 16:47:19.450990 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1251 16:47:19.454257 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1252 16:47:19.457481 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =85
1253 16:47:19.457576
1254 16:47:19.457643
1255 16:47:19.460971 ==
1256 16:47:19.461060 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 16:47:19.468984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 16:47:19.469099 ==
1259 16:47:19.469165
1260 16:47:19.469226
1261 16:47:19.470901 TX Vref Scan disable
1262 16:47:19.470986 == TX Byte 0 ==
1263 16:47:19.473973 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1264 16:47:19.480583 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1265 16:47:19.480694 == TX Byte 1 ==
1266 16:47:19.483725 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1267 16:47:19.490485 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1268 16:47:19.490595 ==
1269 16:47:19.494431 Dram Type= 6, Freq= 0, CH_0, rank 1
1270 16:47:19.497202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1271 16:47:19.497294 ==
1272 16:47:19.510608 TX Vref=22, minBit 0, minWin=27, winSum=439
1273 16:47:19.513945 TX Vref=24, minBit 0, minWin=27, winSum=445
1274 16:47:19.517231 TX Vref=26, minBit 6, minWin=27, winSum=450
1275 16:47:19.520572 TX Vref=28, minBit 2, minWin=27, winSum=447
1276 16:47:19.523941 TX Vref=30, minBit 6, minWin=27, winSum=451
1277 16:47:19.530170 TX Vref=32, minBit 6, minWin=27, winSum=450
1278 16:47:19.533561 [TxChooseVref] Worse bit 6, Min win 27, Win sum 451, Final Vref 30
1279 16:47:19.533660
1280 16:47:19.537409 Final TX Range 1 Vref 30
1281 16:47:19.537500
1282 16:47:19.537567 ==
1283 16:47:19.540902 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 16:47:19.543922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 16:47:19.544035 ==
1286 16:47:19.544128
1287 16:47:19.547508
1288 16:47:19.547597 TX Vref Scan disable
1289 16:47:19.550463 == TX Byte 0 ==
1290 16:47:19.553954 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1291 16:47:19.560298 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1292 16:47:19.560406 == TX Byte 1 ==
1293 16:47:19.563785 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1294 16:47:19.566947 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1295 16:47:19.570140
1296 16:47:19.570242 [DATLAT]
1297 16:47:19.570307 Freq=800, CH0 RK1
1298 16:47:19.570367
1299 16:47:19.573607 DATLAT Default: 0xa
1300 16:47:19.573694 0, 0xFFFF, sum = 0
1301 16:47:19.577086 1, 0xFFFF, sum = 0
1302 16:47:19.577172 2, 0xFFFF, sum = 0
1303 16:47:19.580559 3, 0xFFFF, sum = 0
1304 16:47:19.580643 4, 0xFFFF, sum = 0
1305 16:47:19.583697 5, 0xFFFF, sum = 0
1306 16:47:19.586668 6, 0xFFFF, sum = 0
1307 16:47:19.586757 7, 0xFFFF, sum = 0
1308 16:47:19.590366 8, 0xFFFF, sum = 0
1309 16:47:19.590454 9, 0x0, sum = 1
1310 16:47:19.593342 10, 0x0, sum = 2
1311 16:47:19.593428 11, 0x0, sum = 3
1312 16:47:19.593493 12, 0x0, sum = 4
1313 16:47:19.596408 best_step = 10
1314 16:47:19.596490
1315 16:47:19.596553 ==
1316 16:47:19.599951 Dram Type= 6, Freq= 0, CH_0, rank 1
1317 16:47:19.603142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1318 16:47:19.603272 ==
1319 16:47:19.606535 RX Vref Scan: 0
1320 16:47:19.606623
1321 16:47:19.610486 RX Vref 0 -> 0, step: 1
1322 16:47:19.610570
1323 16:47:19.610634 RX Delay -95 -> 252, step: 8
1324 16:47:19.617003 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1325 16:47:19.620025 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1326 16:47:19.623342 iDelay=209, Bit 2, Center 84 (-23 ~ 192) 216
1327 16:47:19.627063 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1328 16:47:19.630200 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1329 16:47:19.636890 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1330 16:47:19.640214 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1331 16:47:19.643767 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1332 16:47:19.647192 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1333 16:47:19.650926 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1334 16:47:19.656782 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1335 16:47:19.659981 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1336 16:47:19.663523 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1337 16:47:19.666805 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1338 16:47:19.673265 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1339 16:47:19.676972 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1340 16:47:19.677067 ==
1341 16:47:19.679775 Dram Type= 6, Freq= 0, CH_0, rank 1
1342 16:47:19.683329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1343 16:47:19.683411 ==
1344 16:47:19.686395 DQS Delay:
1345 16:47:19.686491 DQS0 = 0, DQS1 = 0
1346 16:47:19.686560 DQM Delay:
1347 16:47:19.689807 DQM0 = 87, DQM1 = 77
1348 16:47:19.689913 DQ Delay:
1349 16:47:19.693494 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1350 16:47:19.696503 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1351 16:47:19.699752 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1352 16:47:19.703077 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =80
1353 16:47:19.703167
1354 16:47:19.703254
1355 16:47:19.712873 [DQSOSCAuto] RK1, (LSB)MR18= 0x2824, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1356 16:47:19.712998 CH0 RK1: MR19=606, MR18=2824
1357 16:47:19.719755 CH0_RK1: MR19=0x606, MR18=0x2824, DQSOSC=399, MR23=63, INC=92, DEC=61
1358 16:47:19.722807 [RxdqsGatingPostProcess] freq 800
1359 16:47:19.729747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1360 16:47:19.733256 Pre-setting of DQS Precalculation
1361 16:47:19.736828 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1362 16:47:19.736929 ==
1363 16:47:19.739645 Dram Type= 6, Freq= 0, CH_1, rank 0
1364 16:47:19.746179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 16:47:19.746284 ==
1366 16:47:19.749631 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1367 16:47:19.756225 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1368 16:47:19.765218 [CA 0] Center 37 (6~68) winsize 63
1369 16:47:19.768673 [CA 1] Center 37 (6~68) winsize 63
1370 16:47:19.772385 [CA 2] Center 35 (5~65) winsize 61
1371 16:47:19.775475 [CA 3] Center 34 (4~65) winsize 62
1372 16:47:19.778714 [CA 4] Center 34 (4~65) winsize 62
1373 16:47:19.781718 [CA 5] Center 34 (3~65) winsize 63
1374 16:47:19.781810
1375 16:47:19.785925 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1376 16:47:19.786021
1377 16:47:19.788706 [CATrainingPosCal] consider 1 rank data
1378 16:47:19.792102 u2DelayCellTimex100 = 270/100 ps
1379 16:47:19.795659 CA0 delay=37 (6~68),Diff = 3 PI (21 cell)
1380 16:47:19.798598 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1381 16:47:19.805083 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1382 16:47:19.808538 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1383 16:47:19.811725 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1384 16:47:19.815196 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1385 16:47:19.815307
1386 16:47:19.818545 CA PerBit enable=1, Macro0, CA PI delay=34
1387 16:47:19.818663
1388 16:47:19.821659 [CBTSetCACLKResult] CA Dly = 34
1389 16:47:19.821745 CS Dly: 4 (0~35)
1390 16:47:19.825352 ==
1391 16:47:19.828176 Dram Type= 6, Freq= 0, CH_1, rank 1
1392 16:47:19.831665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1393 16:47:19.831761 ==
1394 16:47:19.834799 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1395 16:47:19.841668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1396 16:47:19.851587 [CA 0] Center 36 (6~67) winsize 62
1397 16:47:19.854535 [CA 1] Center 36 (6~67) winsize 62
1398 16:47:19.857888 [CA 2] Center 34 (4~65) winsize 62
1399 16:47:19.861301 [CA 3] Center 34 (4~64) winsize 61
1400 16:47:19.864522 [CA 4] Center 34 (3~65) winsize 63
1401 16:47:19.867719 [CA 5] Center 34 (3~65) winsize 63
1402 16:47:19.867812
1403 16:47:19.871523 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1404 16:47:19.871612
1405 16:47:19.874850 [CATrainingPosCal] consider 2 rank data
1406 16:47:19.878057 u2DelayCellTimex100 = 270/100 ps
1407 16:47:19.881675 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1408 16:47:19.887968 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1409 16:47:19.891439 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1410 16:47:19.894819 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1411 16:47:19.898639 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1412 16:47:19.902202 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1413 16:47:19.902337
1414 16:47:19.906480 CA PerBit enable=1, Macro0, CA PI delay=34
1415 16:47:19.906621
1416 16:47:19.909602 [CBTSetCACLKResult] CA Dly = 34
1417 16:47:19.909706 CS Dly: 5 (0~37)
1418 16:47:19.909809
1419 16:47:19.913338 ----->DramcWriteLeveling(PI) begin...
1420 16:47:19.913451 ==
1421 16:47:19.916834 Dram Type= 6, Freq= 0, CH_1, rank 0
1422 16:47:19.920830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 16:47:19.920934 ==
1424 16:47:19.924308 Write leveling (Byte 0): 29 => 29
1425 16:47:19.927892 Write leveling (Byte 1): 26 => 26
1426 16:47:19.931441 DramcWriteLeveling(PI) end<-----
1427 16:47:19.931540
1428 16:47:19.931628 ==
1429 16:47:19.934377 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 16:47:19.937798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 16:47:19.937891 ==
1432 16:47:19.941118 [Gating] SW mode calibration
1433 16:47:19.948053 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1434 16:47:19.951083 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1435 16:47:19.958295 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1436 16:47:19.961113 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1437 16:47:19.964780 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1438 16:47:19.971082 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1439 16:47:19.974567 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1440 16:47:19.977754 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 16:47:19.984685 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 16:47:19.987521 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 16:47:19.991189 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 16:47:19.997628 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 16:47:20.001011 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 16:47:20.003823 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 16:47:20.010667 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 16:47:20.013961 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 16:47:20.017842 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 16:47:20.023819 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 16:47:20.027204 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1452 16:47:20.030486 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1453 16:47:20.037164 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 16:47:20.040516 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 16:47:20.043492 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 16:47:20.050559 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 16:47:20.054246 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 16:47:20.057288 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 16:47:20.064373 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 16:47:20.067142 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 16:47:20.071087 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
1462 16:47:20.077269 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1463 16:47:20.080514 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1464 16:47:20.083867 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1465 16:47:20.090550 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 16:47:20.094014 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 16:47:20.097008 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1468 16:47:20.103590 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1469 16:47:20.107078 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1470 16:47:20.110491 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 16:47:20.117074 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 16:47:20.120246 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 16:47:20.123885 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 16:47:20.126945 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 16:47:20.133327 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 16:47:20.136664 0 11 4 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
1477 16:47:20.140829 0 11 8 | B1->B0 | 3b3b 3c3c | 0 1 | (0 0) (0 0)
1478 16:47:20.146653 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1479 16:47:20.149920 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1480 16:47:20.153151 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1481 16:47:20.160184 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 16:47:20.163424 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 16:47:20.166398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 16:47:20.173124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1485 16:47:20.176317 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1486 16:47:20.180199 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1487 16:47:20.186719 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1488 16:47:20.189612 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 16:47:20.193580 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 16:47:20.199642 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 16:47:20.202976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 16:47:20.206427 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 16:47:20.213717 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 16:47:20.216646 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 16:47:20.219938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 16:47:20.226530 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 16:47:20.229562 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 16:47:20.233144 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 16:47:20.239380 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 16:47:20.242758 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1501 16:47:20.245851 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 16:47:20.249154 Total UI for P1: 0, mck2ui 16
1503 16:47:20.252653 best dqsien dly found for B0: ( 0, 14, 4)
1504 16:47:20.255950 Total UI for P1: 0, mck2ui 16
1505 16:47:20.259092 best dqsien dly found for B1: ( 0, 14, 4)
1506 16:47:20.262970 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1507 16:47:20.265968 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1508 16:47:20.266114
1509 16:47:20.272541 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1510 16:47:20.275638 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1511 16:47:20.275740 [Gating] SW calibration Done
1512 16:47:20.279105 ==
1513 16:47:20.282527 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 16:47:20.285881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 16:47:20.285980 ==
1516 16:47:20.286066 RX Vref Scan: 0
1517 16:47:20.286147
1518 16:47:20.288839 RX Vref 0 -> 0, step: 1
1519 16:47:20.288928
1520 16:47:20.292445 RX Delay -130 -> 252, step: 16
1521 16:47:20.295823 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1522 16:47:20.298771 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1523 16:47:20.305843 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1524 16:47:20.308863 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1525 16:47:20.312814 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1526 16:47:20.316185 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1527 16:47:20.319293 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1528 16:47:20.325342 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1529 16:47:20.328842 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1530 16:47:20.332066 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1531 16:47:20.335638 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1532 16:47:20.338829 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1533 16:47:20.345180 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1534 16:47:20.348461 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1535 16:47:20.351863 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1536 16:47:20.355383 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1537 16:47:20.355500 ==
1538 16:47:20.358534 Dram Type= 6, Freq= 0, CH_1, rank 0
1539 16:47:20.365200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1540 16:47:20.365312 ==
1541 16:47:20.365420 DQS Delay:
1542 16:47:20.368591 DQS0 = 0, DQS1 = 0
1543 16:47:20.368683 DQM Delay:
1544 16:47:20.368750 DQM0 = 86, DQM1 = 80
1545 16:47:20.371763 DQ Delay:
1546 16:47:20.375544 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1547 16:47:20.378273 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =77
1548 16:47:20.381620 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1549 16:47:20.385121 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1550 16:47:20.385213
1551 16:47:20.385277
1552 16:47:20.385337 ==
1553 16:47:20.388184 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 16:47:20.391630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 16:47:20.391749 ==
1556 16:47:20.391844
1557 16:47:20.391932
1558 16:47:20.395304 TX Vref Scan disable
1559 16:47:20.398524 == TX Byte 0 ==
1560 16:47:20.401516 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1561 16:47:20.405154 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1562 16:47:20.408140 == TX Byte 1 ==
1563 16:47:20.412124 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1564 16:47:20.415022 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1565 16:47:20.415112 ==
1566 16:47:20.418051 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 16:47:20.421488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 16:47:20.424704 ==
1569 16:47:20.436734 TX Vref=22, minBit 0, minWin=26, winSum=441
1570 16:47:20.439392 TX Vref=24, minBit 0, minWin=27, winSum=448
1571 16:47:20.443700 TX Vref=26, minBit 1, minWin=27, winSum=450
1572 16:47:20.446074 TX Vref=28, minBit 1, minWin=27, winSum=453
1573 16:47:20.449378 TX Vref=30, minBit 1, minWin=27, winSum=456
1574 16:47:20.456070 TX Vref=32, minBit 1, minWin=27, winSum=455
1575 16:47:20.459237 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 30
1576 16:47:20.459339
1577 16:47:20.462401 Final TX Range 1 Vref 30
1578 16:47:20.462489
1579 16:47:20.462561 ==
1580 16:47:20.466304 Dram Type= 6, Freq= 0, CH_1, rank 0
1581 16:47:20.469761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1582 16:47:20.472806 ==
1583 16:47:20.472892
1584 16:47:20.472956
1585 16:47:20.473015 TX Vref Scan disable
1586 16:47:20.476740 == TX Byte 0 ==
1587 16:47:20.479633 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1588 16:47:20.483222 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1589 16:47:20.486349 == TX Byte 1 ==
1590 16:47:20.489745 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1591 16:47:20.492996 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1592 16:47:20.493088
1593 16:47:20.496468 [DATLAT]
1594 16:47:20.496555 Freq=800, CH1 RK0
1595 16:47:20.496621
1596 16:47:20.499928 DATLAT Default: 0xa
1597 16:47:20.500016 0, 0xFFFF, sum = 0
1598 16:47:20.503911 1, 0xFFFF, sum = 0
1599 16:47:20.504008 2, 0xFFFF, sum = 0
1600 16:47:20.506156 3, 0xFFFF, sum = 0
1601 16:47:20.506247 4, 0xFFFF, sum = 0
1602 16:47:20.509508 5, 0xFFFF, sum = 0
1603 16:47:20.509600 6, 0xFFFF, sum = 0
1604 16:47:20.512821 7, 0xFFFF, sum = 0
1605 16:47:20.516158 8, 0xFFFF, sum = 0
1606 16:47:20.516253 9, 0x0, sum = 1
1607 16:47:20.516322 10, 0x0, sum = 2
1608 16:47:20.519760 11, 0x0, sum = 3
1609 16:47:20.519852 12, 0x0, sum = 4
1610 16:47:20.522525 best_step = 10
1611 16:47:20.522633
1612 16:47:20.522724 ==
1613 16:47:20.526028 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 16:47:20.529618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 16:47:20.529723 ==
1616 16:47:20.532712 RX Vref Scan: 1
1617 16:47:20.532808
1618 16:47:20.532875 Set Vref Range= 32 -> 127
1619 16:47:20.535902
1620 16:47:20.535988 RX Vref 32 -> 127, step: 1
1621 16:47:20.536054
1622 16:47:20.539204 RX Delay -95 -> 252, step: 8
1623 16:47:20.539321
1624 16:47:20.542502 Set Vref, RX VrefLevel [Byte0]: 32
1625 16:47:20.546131 [Byte1]: 32
1626 16:47:20.546252
1627 16:47:20.549489 Set Vref, RX VrefLevel [Byte0]: 33
1628 16:47:20.552878 [Byte1]: 33
1629 16:47:20.556277
1630 16:47:20.556388 Set Vref, RX VrefLevel [Byte0]: 34
1631 16:47:20.560588 [Byte1]: 34
1632 16:47:20.563964
1633 16:47:20.564044 Set Vref, RX VrefLevel [Byte0]: 35
1634 16:47:20.567254 [Byte1]: 35
1635 16:47:20.573058
1636 16:47:20.573178 Set Vref, RX VrefLevel [Byte0]: 36
1637 16:47:20.575384 [Byte1]: 36
1638 16:47:20.579417
1639 16:47:20.579513 Set Vref, RX VrefLevel [Byte0]: 37
1640 16:47:20.582593 [Byte1]: 37
1641 16:47:20.586901
1642 16:47:20.587016 Set Vref, RX VrefLevel [Byte0]: 38
1643 16:47:20.590037 [Byte1]: 38
1644 16:47:20.594730
1645 16:47:20.594838 Set Vref, RX VrefLevel [Byte0]: 39
1646 16:47:20.597813 [Byte1]: 39
1647 16:47:20.602387
1648 16:47:20.602478 Set Vref, RX VrefLevel [Byte0]: 40
1649 16:47:20.605855 [Byte1]: 40
1650 16:47:20.609852
1651 16:47:20.609949 Set Vref, RX VrefLevel [Byte0]: 41
1652 16:47:20.612953 [Byte1]: 41
1653 16:47:20.617292
1654 16:47:20.617393 Set Vref, RX VrefLevel [Byte0]: 42
1655 16:47:20.620818 [Byte1]: 42
1656 16:47:20.624810
1657 16:47:20.624909 Set Vref, RX VrefLevel [Byte0]: 43
1658 16:47:20.628056 [Byte1]: 43
1659 16:47:20.632705
1660 16:47:20.632811 Set Vref, RX VrefLevel [Byte0]: 44
1661 16:47:20.635869 [Byte1]: 44
1662 16:47:20.640182
1663 16:47:20.640284 Set Vref, RX VrefLevel [Byte0]: 45
1664 16:47:20.643119 [Byte1]: 45
1665 16:47:20.647725
1666 16:47:20.647827 Set Vref, RX VrefLevel [Byte0]: 46
1667 16:47:20.650819 [Byte1]: 46
1668 16:47:20.655042
1669 16:47:20.655165 Set Vref, RX VrefLevel [Byte0]: 47
1670 16:47:20.658787 [Byte1]: 47
1671 16:47:20.662615
1672 16:47:20.662737 Set Vref, RX VrefLevel [Byte0]: 48
1673 16:47:20.666041 [Byte1]: 48
1674 16:47:20.670608
1675 16:47:20.670705 Set Vref, RX VrefLevel [Byte0]: 49
1676 16:47:20.674012 [Byte1]: 49
1677 16:47:20.678199
1678 16:47:20.678300 Set Vref, RX VrefLevel [Byte0]: 50
1679 16:47:20.681615 [Byte1]: 50
1680 16:47:20.685471
1681 16:47:20.685570 Set Vref, RX VrefLevel [Byte0]: 51
1682 16:47:20.689219 [Byte1]: 51
1683 16:47:20.693608
1684 16:47:20.693709 Set Vref, RX VrefLevel [Byte0]: 52
1685 16:47:20.696407 [Byte1]: 52
1686 16:47:20.701294
1687 16:47:20.701392 Set Vref, RX VrefLevel [Byte0]: 53
1688 16:47:20.704227 [Byte1]: 53
1689 16:47:20.708864
1690 16:47:20.708961 Set Vref, RX VrefLevel [Byte0]: 54
1691 16:47:20.714894 [Byte1]: 54
1692 16:47:20.714999
1693 16:47:20.718428 Set Vref, RX VrefLevel [Byte0]: 55
1694 16:47:20.721673 [Byte1]: 55
1695 16:47:20.721769
1696 16:47:20.725179 Set Vref, RX VrefLevel [Byte0]: 56
1697 16:47:20.728502 [Byte1]: 56
1698 16:47:20.728605
1699 16:47:20.731528 Set Vref, RX VrefLevel [Byte0]: 57
1700 16:47:20.734666 [Byte1]: 57
1701 16:47:20.738937
1702 16:47:20.739040 Set Vref, RX VrefLevel [Byte0]: 58
1703 16:47:20.741996 [Byte1]: 58
1704 16:47:20.746679
1705 16:47:20.746784 Set Vref, RX VrefLevel [Byte0]: 59
1706 16:47:20.749814 [Byte1]: 59
1707 16:47:20.753952
1708 16:47:20.754078 Set Vref, RX VrefLevel [Byte0]: 60
1709 16:47:20.757432 [Byte1]: 60
1710 16:47:20.761566
1711 16:47:20.761693 Set Vref, RX VrefLevel [Byte0]: 61
1712 16:47:20.765461 [Byte1]: 61
1713 16:47:20.769165
1714 16:47:20.769294 Set Vref, RX VrefLevel [Byte0]: 62
1715 16:47:20.772425 [Byte1]: 62
1716 16:47:20.776834
1717 16:47:20.776936 Set Vref, RX VrefLevel [Byte0]: 63
1718 16:47:20.780348 [Byte1]: 63
1719 16:47:20.785994
1720 16:47:20.786105 Set Vref, RX VrefLevel [Byte0]: 64
1721 16:47:20.788389 [Byte1]: 64
1722 16:47:20.791835
1723 16:47:20.791931 Set Vref, RX VrefLevel [Byte0]: 65
1724 16:47:20.795889 [Byte1]: 65
1725 16:47:20.799791
1726 16:47:20.799887 Set Vref, RX VrefLevel [Byte0]: 66
1727 16:47:20.802704 [Byte1]: 66
1728 16:47:20.807158
1729 16:47:20.807279 Set Vref, RX VrefLevel [Byte0]: 67
1730 16:47:20.810515 [Byte1]: 67
1731 16:47:20.814671
1732 16:47:20.814768 Set Vref, RX VrefLevel [Byte0]: 68
1733 16:47:20.818263 [Byte1]: 68
1734 16:47:20.822452
1735 16:47:20.822550 Set Vref, RX VrefLevel [Byte0]: 69
1736 16:47:20.825777 [Byte1]: 69
1737 16:47:20.830035
1738 16:47:20.830142 Set Vref, RX VrefLevel [Byte0]: 70
1739 16:47:20.833049 [Byte1]: 70
1740 16:47:20.837605
1741 16:47:20.837734 Set Vref, RX VrefLevel [Byte0]: 71
1742 16:47:20.840724 [Byte1]: 71
1743 16:47:20.845507
1744 16:47:20.845650 Set Vref, RX VrefLevel [Byte0]: 72
1745 16:47:20.848601 [Byte1]: 72
1746 16:47:20.852667
1747 16:47:20.852777 Set Vref, RX VrefLevel [Byte0]: 73
1748 16:47:20.855963 [Byte1]: 73
1749 16:47:20.860373
1750 16:47:20.860474 Set Vref, RX VrefLevel [Byte0]: 74
1751 16:47:20.863662 [Byte1]: 74
1752 16:47:20.868151
1753 16:47:20.868250 Set Vref, RX VrefLevel [Byte0]: 75
1754 16:47:20.871161 [Byte1]: 75
1755 16:47:20.875723
1756 16:47:20.875827 Set Vref, RX VrefLevel [Byte0]: 76
1757 16:47:20.879103 [Byte1]: 76
1758 16:47:20.883153
1759 16:47:20.883292 Set Vref, RX VrefLevel [Byte0]: 77
1760 16:47:20.886512 [Byte1]: 77
1761 16:47:20.890604
1762 16:47:20.890702 Final RX Vref Byte 0 = 62 to rank0
1763 16:47:20.893975 Final RX Vref Byte 1 = 54 to rank0
1764 16:47:20.897517 Final RX Vref Byte 0 = 62 to rank1
1765 16:47:20.900598 Final RX Vref Byte 1 = 54 to rank1==
1766 16:47:20.903852 Dram Type= 6, Freq= 0, CH_1, rank 0
1767 16:47:20.910453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1768 16:47:20.910563 ==
1769 16:47:20.910633 DQS Delay:
1770 16:47:20.913901 DQS0 = 0, DQS1 = 0
1771 16:47:20.913988 DQM Delay:
1772 16:47:20.914054 DQM0 = 85, DQM1 = 80
1773 16:47:20.917291 DQ Delay:
1774 16:47:20.920405 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1775 16:47:20.923879 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1776 16:47:20.926970 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1777 16:47:20.930309 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1778 16:47:20.930455
1779 16:47:20.930558
1780 16:47:20.937171 [DQSOSCAuto] RK0, (LSB)MR18= 0x1428, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1781 16:47:20.940329 CH1 RK0: MR19=606, MR18=1428
1782 16:47:20.946976 CH1_RK0: MR19=0x606, MR18=0x1428, DQSOSC=399, MR23=63, INC=92, DEC=61
1783 16:47:20.947113
1784 16:47:20.950840 ----->DramcWriteLeveling(PI) begin...
1785 16:47:20.950959 ==
1786 16:47:20.953634 Dram Type= 6, Freq= 0, CH_1, rank 1
1787 16:47:20.957756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1788 16:47:20.957886 ==
1789 16:47:20.960458 Write leveling (Byte 0): 25 => 25
1790 16:47:20.963532 Write leveling (Byte 1): 29 => 29
1791 16:47:20.966983 DramcWriteLeveling(PI) end<-----
1792 16:47:20.967105
1793 16:47:20.967235 ==
1794 16:47:20.970050 Dram Type= 6, Freq= 0, CH_1, rank 1
1795 16:47:20.973760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1796 16:47:20.973877 ==
1797 16:47:20.976775 [Gating] SW mode calibration
1798 16:47:20.983137 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1799 16:47:20.990109 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1800 16:47:20.993757 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1801 16:47:21.000142 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1802 16:47:21.003410 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 16:47:21.006685 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 16:47:21.013364 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 16:47:21.016532 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 16:47:21.019952 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 16:47:21.026581 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 16:47:21.029725 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 16:47:21.033093 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 16:47:21.036920 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 16:47:21.043256 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 16:47:21.046130 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 16:47:21.049721 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 16:47:21.056212 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 16:47:21.059839 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 16:47:21.063474 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1817 16:47:21.069870 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1818 16:47:21.072898 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1819 16:47:21.076302 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 16:47:21.082869 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 16:47:21.086695 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 16:47:21.089371 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 16:47:21.096273 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 16:47:21.099814 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1825 16:47:21.102944 0 9 4 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1826 16:47:21.109621 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1827 16:47:21.112746 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 16:47:21.115934 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 16:47:21.122419 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 16:47:21.126144 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 16:47:21.129460 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 16:47:21.136311 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1833 16:47:21.139289 0 10 4 | B1->B0 | 3131 2a2a | 0 0 | (0 0) (0 0)
1834 16:47:21.142256 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
1835 16:47:21.148908 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 16:47:21.152396 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 16:47:21.156305 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 16:47:21.162447 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 16:47:21.165374 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 16:47:21.168937 0 11 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1841 16:47:21.175812 0 11 4 | B1->B0 | 2424 4040 | 1 0 | (0 0) (1 1)
1842 16:47:21.178881 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1843 16:47:21.181993 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 16:47:21.188975 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 16:47:21.192448 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 16:47:21.195548 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 16:47:21.202506 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 16:47:21.205337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 16:47:21.209256 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1850 16:47:21.214991 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 16:47:21.218443 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 16:47:21.222133 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 16:47:21.228140 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 16:47:21.231668 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 16:47:21.234890 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 16:47:21.241766 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 16:47:21.244773 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 16:47:21.248836 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 16:47:21.254747 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 16:47:21.258385 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 16:47:21.262657 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 16:47:21.268003 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 16:47:21.271772 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 16:47:21.274893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1865 16:47:21.277959 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1866 16:47:21.281379 Total UI for P1: 0, mck2ui 16
1867 16:47:21.284671 best dqsien dly found for B0: ( 0, 14, 0)
1868 16:47:21.291212 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 16:47:21.295325 Total UI for P1: 0, mck2ui 16
1870 16:47:21.297948 best dqsien dly found for B1: ( 0, 14, 6)
1871 16:47:21.301761 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1872 16:47:21.304728 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1873 16:47:21.304822
1874 16:47:21.307836 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1875 16:47:21.311656 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1876 16:47:21.314891 [Gating] SW calibration Done
1877 16:47:21.314979 ==
1878 16:47:21.317874 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 16:47:21.321250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 16:47:21.321338 ==
1881 16:47:21.324988 RX Vref Scan: 0
1882 16:47:21.325076
1883 16:47:21.327510 RX Vref 0 -> 0, step: 1
1884 16:47:21.327593
1885 16:47:21.327658 RX Delay -130 -> 252, step: 16
1886 16:47:21.334707 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1887 16:47:21.338144 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1888 16:47:21.341203 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1889 16:47:21.344769 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1890 16:47:21.347435 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1891 16:47:21.353868 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1892 16:47:21.357701 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1893 16:47:21.361473 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1894 16:47:21.364139 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1895 16:47:21.367102 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1896 16:47:21.373840 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1897 16:47:21.377227 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1898 16:47:21.381293 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1899 16:47:21.383961 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1900 16:47:21.390416 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1901 16:47:21.394149 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1902 16:47:21.394252 ==
1903 16:47:21.397191 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 16:47:21.400341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 16:47:21.400432 ==
1906 16:47:21.400498 DQS Delay:
1907 16:47:21.404118 DQS0 = 0, DQS1 = 0
1908 16:47:21.404210 DQM Delay:
1909 16:47:21.407035 DQM0 = 83, DQM1 = 83
1910 16:47:21.407145 DQ Delay:
1911 16:47:21.410754 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1912 16:47:21.413676 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1913 16:47:21.417274 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1914 16:47:21.420079 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1915 16:47:21.420171
1916 16:47:21.420238
1917 16:47:21.420299 ==
1918 16:47:21.424207 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 16:47:21.430377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 16:47:21.430494 ==
1921 16:47:21.430592
1922 16:47:21.430655
1923 16:47:21.430714 TX Vref Scan disable
1924 16:47:21.433627 == TX Byte 0 ==
1925 16:47:21.436677 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1926 16:47:21.440675 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1927 16:47:21.443511 == TX Byte 1 ==
1928 16:47:21.447000 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1929 16:47:21.450311 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1930 16:47:21.454014 ==
1931 16:47:21.456897 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 16:47:21.460196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 16:47:21.460291 ==
1934 16:47:21.473127 TX Vref=22, minBit 1, minWin=27, winSum=442
1935 16:47:21.476238 TX Vref=24, minBit 1, minWin=27, winSum=447
1936 16:47:21.479433 TX Vref=26, minBit 1, minWin=27, winSum=452
1937 16:47:21.482667 TX Vref=28, minBit 1, minWin=27, winSum=452
1938 16:47:21.486299 TX Vref=30, minBit 1, minWin=27, winSum=452
1939 16:47:21.492758 TX Vref=32, minBit 3, minWin=27, winSum=454
1940 16:47:21.495974 [TxChooseVref] Worse bit 3, Min win 27, Win sum 454, Final Vref 32
1941 16:47:21.496078
1942 16:47:21.499468 Final TX Range 1 Vref 32
1943 16:47:21.499557
1944 16:47:21.499623 ==
1945 16:47:21.503961 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 16:47:21.506086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 16:47:21.509271 ==
1948 16:47:21.509393
1949 16:47:21.509489
1950 16:47:21.509582 TX Vref Scan disable
1951 16:47:21.512898 == TX Byte 0 ==
1952 16:47:21.516667 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1953 16:47:21.522821 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1954 16:47:21.522953 == TX Byte 1 ==
1955 16:47:21.526005 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1956 16:47:21.532790 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1957 16:47:21.532912
1958 16:47:21.532981 [DATLAT]
1959 16:47:21.533042 Freq=800, CH1 RK1
1960 16:47:21.533102
1961 16:47:21.536052 DATLAT Default: 0xa
1962 16:47:21.536163 0, 0xFFFF, sum = 0
1963 16:47:21.539903 1, 0xFFFF, sum = 0
1964 16:47:21.540018 2, 0xFFFF, sum = 0
1965 16:47:21.542556 3, 0xFFFF, sum = 0
1966 16:47:21.546201 4, 0xFFFF, sum = 0
1967 16:47:21.546317 5, 0xFFFF, sum = 0
1968 16:47:21.549420 6, 0xFFFF, sum = 0
1969 16:47:21.549534 7, 0xFFFF, sum = 0
1970 16:47:21.552333 8, 0xFFFF, sum = 0
1971 16:47:21.552421 9, 0x0, sum = 1
1972 16:47:21.555737 10, 0x0, sum = 2
1973 16:47:21.555827 11, 0x0, sum = 3
1974 16:47:21.555895 12, 0x0, sum = 4
1975 16:47:21.559300 best_step = 10
1976 16:47:21.559389
1977 16:47:21.559457 ==
1978 16:47:21.562180 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 16:47:21.565772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 16:47:21.565870 ==
1981 16:47:21.568962 RX Vref Scan: 0
1982 16:47:21.569048
1983 16:47:21.572429 RX Vref 0 -> 0, step: 1
1984 16:47:21.572535
1985 16:47:21.572608 RX Delay -95 -> 252, step: 8
1986 16:47:21.579485 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1987 16:47:21.583057 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1988 16:47:21.586327 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1989 16:47:21.589692 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1990 16:47:21.596166 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1991 16:47:21.598964 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1992 16:47:21.602500 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1993 16:47:21.606236 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1994 16:47:21.608898 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1995 16:47:21.616141 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
1996 16:47:21.619732 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1997 16:47:21.622263 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1998 16:47:21.625909 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1999 16:47:21.628828 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2000 16:47:21.635725 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2001 16:47:21.639413 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2002 16:47:21.639518 ==
2003 16:47:21.642278 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 16:47:21.645498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 16:47:21.645617 ==
2006 16:47:21.649027 DQS Delay:
2007 16:47:21.649140 DQS0 = 0, DQS1 = 0
2008 16:47:21.649234 DQM Delay:
2009 16:47:21.652442 DQM0 = 87, DQM1 = 81
2010 16:47:21.652529 DQ Delay:
2011 16:47:21.655660 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2012 16:47:21.659058 DQ4 =84, DQ5 =100, DQ6 =96, DQ7 =84
2013 16:47:21.662522 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2014 16:47:21.665932 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
2015 16:47:21.666050
2016 16:47:21.666144
2017 16:47:21.675420 [DQSOSCAuto] RK1, (LSB)MR18= 0x213d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2018 16:47:21.678928 CH1 RK1: MR19=606, MR18=213D
2019 16:47:21.682171 CH1_RK1: MR19=0x606, MR18=0x213D, DQSOSC=394, MR23=63, INC=95, DEC=63
2020 16:47:21.685950 [RxdqsGatingPostProcess] freq 800
2021 16:47:21.692512 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 16:47:21.695118 Pre-setting of DQS Precalculation
2023 16:47:21.698859 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 16:47:21.708855 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 16:47:21.715082 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 16:47:21.715264
2027 16:47:21.715368
2028 16:47:21.718706 [Calibration Summary] 1600 Mbps
2029 16:47:21.718795 CH 0, Rank 0
2030 16:47:21.721748 SW Impedance : PASS
2031 16:47:21.721838 DUTY Scan : NO K
2032 16:47:21.725028 ZQ Calibration : PASS
2033 16:47:21.728338 Jitter Meter : NO K
2034 16:47:21.728435 CBT Training : PASS
2035 16:47:21.731843 Write leveling : PASS
2036 16:47:21.735055 RX DQS gating : PASS
2037 16:47:21.735179 RX DQ/DQS(RDDQC) : PASS
2038 16:47:21.738373 TX DQ/DQS : PASS
2039 16:47:21.741740 RX DATLAT : PASS
2040 16:47:21.741922 RX DQ/DQS(Engine): PASS
2041 16:47:21.744781 TX OE : NO K
2042 16:47:21.744872 All Pass.
2043 16:47:21.744938
2044 16:47:21.748390 CH 0, Rank 1
2045 16:47:21.748477 SW Impedance : PASS
2046 16:47:21.751922 DUTY Scan : NO K
2047 16:47:21.752009 ZQ Calibration : PASS
2048 16:47:21.755590 Jitter Meter : NO K
2049 16:47:21.758528 CBT Training : PASS
2050 16:47:21.758623 Write leveling : PASS
2051 16:47:21.761603 RX DQS gating : PASS
2052 16:47:21.765315 RX DQ/DQS(RDDQC) : PASS
2053 16:47:21.765412 TX DQ/DQS : PASS
2054 16:47:21.768731 RX DATLAT : PASS
2055 16:47:21.771455 RX DQ/DQS(Engine): PASS
2056 16:47:21.771546 TX OE : NO K
2057 16:47:21.774695 All Pass.
2058 16:47:21.774781
2059 16:47:21.774850 CH 1, Rank 0
2060 16:47:21.778069 SW Impedance : PASS
2061 16:47:21.778158 DUTY Scan : NO K
2062 16:47:21.781286 ZQ Calibration : PASS
2063 16:47:21.785160 Jitter Meter : NO K
2064 16:47:21.785252 CBT Training : PASS
2065 16:47:21.788153 Write leveling : PASS
2066 16:47:21.791850 RX DQS gating : PASS
2067 16:47:21.791969 RX DQ/DQS(RDDQC) : PASS
2068 16:47:21.794953 TX DQ/DQS : PASS
2069 16:47:21.795068 RX DATLAT : PASS
2070 16:47:21.798166 RX DQ/DQS(Engine): PASS
2071 16:47:21.801505 TX OE : NO K
2072 16:47:21.801596 All Pass.
2073 16:47:21.801694
2074 16:47:21.801787 CH 1, Rank 1
2075 16:47:21.804689 SW Impedance : PASS
2076 16:47:21.808498 DUTY Scan : NO K
2077 16:47:21.808616 ZQ Calibration : PASS
2078 16:47:21.811621 Jitter Meter : NO K
2079 16:47:21.814863 CBT Training : PASS
2080 16:47:21.814980 Write leveling : PASS
2081 16:47:21.817939 RX DQS gating : PASS
2082 16:47:21.821701 RX DQ/DQS(RDDQC) : PASS
2083 16:47:21.821794 TX DQ/DQS : PASS
2084 16:47:21.824593 RX DATLAT : PASS
2085 16:47:21.828048 RX DQ/DQS(Engine): PASS
2086 16:47:21.828157 TX OE : NO K
2087 16:47:21.831309 All Pass.
2088 16:47:21.831401
2089 16:47:21.831476 DramC Write-DBI off
2090 16:47:21.834289 PER_BANK_REFRESH: Hybrid Mode
2091 16:47:21.834393 TX_TRACKING: ON
2092 16:47:21.838034 [GetDramInforAfterCalByMRR] Vendor 6.
2093 16:47:21.844656 [GetDramInforAfterCalByMRR] Revision 606.
2094 16:47:21.847782 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 16:47:21.847868 MR0 0x3b3b
2096 16:47:21.847934 MR8 0x5151
2097 16:47:21.851268 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 16:47:21.851344
2099 16:47:21.854539 MR0 0x3b3b
2100 16:47:21.854613 MR8 0x5151
2101 16:47:21.857545 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 16:47:21.857650
2103 16:47:21.867714 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 16:47:21.871129 [FAST_K] Save calibration result to emmc
2105 16:47:21.874489 [FAST_K] Save calibration result to emmc
2106 16:47:21.878132 dram_init: config_dvfs: 1
2107 16:47:21.881604 dramc_set_vcore_voltage set vcore to 662500
2108 16:47:21.884165 Read voltage for 1200, 2
2109 16:47:21.884245 Vio18 = 0
2110 16:47:21.884309 Vcore = 662500
2111 16:47:21.887770 Vdram = 0
2112 16:47:21.887871 Vddq = 0
2113 16:47:21.887959 Vmddr = 0
2114 16:47:21.894563 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 16:47:21.897498 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 16:47:21.900919 MEM_TYPE=3, freq_sel=15
2117 16:47:21.904073 sv_algorithm_assistance_LP4_1600
2118 16:47:21.907763 ============ PULL DRAM RESETB DOWN ============
2119 16:47:21.910585 ========== PULL DRAM RESETB DOWN end =========
2120 16:47:21.917344 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 16:47:21.920639 ===================================
2122 16:47:21.924285 LPDDR4 DRAM CONFIGURATION
2123 16:47:21.927670 ===================================
2124 16:47:21.927792 EX_ROW_EN[0] = 0x0
2125 16:47:21.930919 EX_ROW_EN[1] = 0x0
2126 16:47:21.931044 LP4Y_EN = 0x0
2127 16:47:21.933876 WORK_FSP = 0x0
2128 16:47:21.933969 WL = 0x4
2129 16:47:21.937281 RL = 0x4
2130 16:47:21.937370 BL = 0x2
2131 16:47:21.940470 RPST = 0x0
2132 16:47:21.940587 RD_PRE = 0x0
2133 16:47:21.943865 WR_PRE = 0x1
2134 16:47:21.943952 WR_PST = 0x0
2135 16:47:21.947376 DBI_WR = 0x0
2136 16:47:21.947464 DBI_RD = 0x0
2137 16:47:21.950501 OTF = 0x1
2138 16:47:21.954171 ===================================
2139 16:47:21.957156 ===================================
2140 16:47:21.957248 ANA top config
2141 16:47:21.960944 ===================================
2142 16:47:21.963422 DLL_ASYNC_EN = 0
2143 16:47:21.967867 ALL_SLAVE_EN = 0
2144 16:47:21.970510 NEW_RANK_MODE = 1
2145 16:47:21.970626 DLL_IDLE_MODE = 1
2146 16:47:21.973929 LP45_APHY_COMB_EN = 1
2147 16:47:21.977212 TX_ODT_DIS = 1
2148 16:47:21.980069 NEW_8X_MODE = 1
2149 16:47:21.983731 ===================================
2150 16:47:21.986909 ===================================
2151 16:47:21.990276 data_rate = 2400
2152 16:47:21.993674 CKR = 1
2153 16:47:21.993749 DQ_P2S_RATIO = 8
2154 16:47:21.997239 ===================================
2155 16:47:22.000262 CA_P2S_RATIO = 8
2156 16:47:22.003168 DQ_CA_OPEN = 0
2157 16:47:22.006655 DQ_SEMI_OPEN = 0
2158 16:47:22.010225 CA_SEMI_OPEN = 0
2159 16:47:22.013960 CA_FULL_RATE = 0
2160 16:47:22.014044 DQ_CKDIV4_EN = 0
2161 16:47:22.016674 CA_CKDIV4_EN = 0
2162 16:47:22.019885 CA_PREDIV_EN = 0
2163 16:47:22.023178 PH8_DLY = 17
2164 16:47:22.026805 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 16:47:22.030635 DQ_AAMCK_DIV = 4
2166 16:47:22.030748 CA_AAMCK_DIV = 4
2167 16:47:22.034065 CA_ADMCK_DIV = 4
2168 16:47:22.036633 DQ_TRACK_CA_EN = 0
2169 16:47:22.040311 CA_PICK = 1200
2170 16:47:22.043070 CA_MCKIO = 1200
2171 16:47:22.046361 MCKIO_SEMI = 0
2172 16:47:22.049967 PLL_FREQ = 2366
2173 16:47:22.050078 DQ_UI_PI_RATIO = 32
2174 16:47:22.053574 CA_UI_PI_RATIO = 0
2175 16:47:22.056513 ===================================
2176 16:47:22.060198 ===================================
2177 16:47:22.062878 memory_type:LPDDR4
2178 16:47:22.066236 GP_NUM : 10
2179 16:47:22.066318 SRAM_EN : 1
2180 16:47:22.069948 MD32_EN : 0
2181 16:47:22.073094 ===================================
2182 16:47:22.076249 [ANA_INIT] >>>>>>>>>>>>>>
2183 16:47:22.076332 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 16:47:22.079985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 16:47:22.083136 ===================================
2186 16:47:22.086679 data_rate = 2400,PCW = 0X5b00
2187 16:47:22.089282 ===================================
2188 16:47:22.092751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 16:47:22.099480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 16:47:22.106269 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 16:47:22.109361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 16:47:22.112574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 16:47:22.115982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 16:47:22.120291 [ANA_INIT] flow start
2195 16:47:22.120376 [ANA_INIT] PLL >>>>>>>>
2196 16:47:22.123292 [ANA_INIT] PLL <<<<<<<<
2197 16:47:22.125779 [ANA_INIT] MIDPI >>>>>>>>
2198 16:47:22.129007 [ANA_INIT] MIDPI <<<<<<<<
2199 16:47:22.129118 [ANA_INIT] DLL >>>>>>>>
2200 16:47:22.132363 [ANA_INIT] DLL <<<<<<<<
2201 16:47:22.136264 [ANA_INIT] flow end
2202 16:47:22.139158 ============ LP4 DIFF to SE enter ============
2203 16:47:22.142626 ============ LP4 DIFF to SE exit ============
2204 16:47:22.145741 [ANA_INIT] <<<<<<<<<<<<<
2205 16:47:22.149045 [Flow] Enable top DCM control >>>>>
2206 16:47:22.152516 [Flow] Enable top DCM control <<<<<
2207 16:47:22.155555 Enable DLL master slave shuffle
2208 16:47:22.158942 ==============================================================
2209 16:47:22.162500 Gating Mode config
2210 16:47:22.166005 ==============================================================
2211 16:47:22.169244 Config description:
2212 16:47:22.178947 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 16:47:22.185552 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 16:47:22.188697 SELPH_MODE 0: By rank 1: By Phase
2215 16:47:22.195082 ==============================================================
2216 16:47:22.198639 GAT_TRACK_EN = 1
2217 16:47:22.201880 RX_GATING_MODE = 2
2218 16:47:22.205194 RX_GATING_TRACK_MODE = 2
2219 16:47:22.208828 SELPH_MODE = 1
2220 16:47:22.211666 PICG_EARLY_EN = 1
2221 16:47:22.215889 VALID_LAT_VALUE = 1
2222 16:47:22.218408 ==============================================================
2223 16:47:22.222128 Enter into Gating configuration >>>>
2224 16:47:22.225077 Exit from Gating configuration <<<<
2225 16:47:22.228374 Enter into DVFS_PRE_config >>>>>
2226 16:47:22.242378 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 16:47:22.242494 Exit from DVFS_PRE_config <<<<<
2228 16:47:22.244880 Enter into PICG configuration >>>>
2229 16:47:22.248247 Exit from PICG configuration <<<<
2230 16:47:22.251356 [RX_INPUT] configuration >>>>>
2231 16:47:22.254869 [RX_INPUT] configuration <<<<<
2232 16:47:22.261132 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 16:47:22.264488 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 16:47:22.271156 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 16:47:22.278401 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 16:47:22.284441 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 16:47:22.291014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 16:47:22.294402 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 16:47:22.298023 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 16:47:22.301282 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 16:47:22.307919 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 16:47:22.311301 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 16:47:22.314453 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 16:47:22.317630 ===================================
2245 16:47:22.321364 LPDDR4 DRAM CONFIGURATION
2246 16:47:22.324367 ===================================
2247 16:47:22.327655 EX_ROW_EN[0] = 0x0
2248 16:47:22.327740 EX_ROW_EN[1] = 0x0
2249 16:47:22.331583 LP4Y_EN = 0x0
2250 16:47:22.331669 WORK_FSP = 0x0
2251 16:47:22.334492 WL = 0x4
2252 16:47:22.334575 RL = 0x4
2253 16:47:22.337902 BL = 0x2
2254 16:47:22.337984 RPST = 0x0
2255 16:47:22.340968 RD_PRE = 0x0
2256 16:47:22.341051 WR_PRE = 0x1
2257 16:47:22.344275 WR_PST = 0x0
2258 16:47:22.344358 DBI_WR = 0x0
2259 16:47:22.347563 DBI_RD = 0x0
2260 16:47:22.347646 OTF = 0x1
2261 16:47:22.351055 ===================================
2262 16:47:22.354820 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 16:47:22.360901 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 16:47:22.364336 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 16:47:22.367324 ===================================
2266 16:47:22.370683 LPDDR4 DRAM CONFIGURATION
2267 16:47:22.373976 ===================================
2268 16:47:22.374059 EX_ROW_EN[0] = 0x10
2269 16:47:22.377375 EX_ROW_EN[1] = 0x0
2270 16:47:22.380925 LP4Y_EN = 0x0
2271 16:47:22.381009 WORK_FSP = 0x0
2272 16:47:22.384424 WL = 0x4
2273 16:47:22.384506 RL = 0x4
2274 16:47:22.387470 BL = 0x2
2275 16:47:22.387552 RPST = 0x0
2276 16:47:22.390712 RD_PRE = 0x0
2277 16:47:22.390794 WR_PRE = 0x1
2278 16:47:22.394165 WR_PST = 0x0
2279 16:47:22.394246 DBI_WR = 0x0
2280 16:47:22.397159 DBI_RD = 0x0
2281 16:47:22.397240 OTF = 0x1
2282 16:47:22.400820 ===================================
2283 16:47:22.406940 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 16:47:22.407023 ==
2285 16:47:22.410410 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 16:47:22.416763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 16:47:22.416847 ==
2288 16:47:22.416912 [Duty_Offset_Calibration]
2289 16:47:22.420251 B0:2 B1:0 CA:4
2290 16:47:22.420333
2291 16:47:22.423297 [DutyScan_Calibration_Flow] k_type=0
2292 16:47:22.432283
2293 16:47:22.432385 ==CLK 0==
2294 16:47:22.435756 Final CLK duty delay cell = 0
2295 16:47:22.439067 [0] MAX Duty = 5156%(X100), DQS PI = 14
2296 16:47:22.442079 [0] MIN Duty = 4969%(X100), DQS PI = 8
2297 16:47:22.442161 [0] AVG Duty = 5062%(X100)
2298 16:47:22.445460
2299 16:47:22.445542 CH0 CLK Duty spec in!! Max-Min= 187%
2300 16:47:22.452128 [DutyScan_Calibration_Flow] ====Done====
2301 16:47:22.452212
2302 16:47:22.455307 [DutyScan_Calibration_Flow] k_type=1
2303 16:47:22.470851
2304 16:47:22.470945 ==DQS 0 ==
2305 16:47:22.474089 Final DQS duty delay cell = -4
2306 16:47:22.477157 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2307 16:47:22.480573 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2308 16:47:22.483890 [-4] AVG Duty = 4922%(X100)
2309 16:47:22.483973
2310 16:47:22.484038 ==DQS 1 ==
2311 16:47:22.487112 Final DQS duty delay cell = 0
2312 16:47:22.490564 [0] MAX Duty = 5125%(X100), DQS PI = 4
2313 16:47:22.493603 [0] MIN Duty = 4969%(X100), DQS PI = 14
2314 16:47:22.496945 [0] AVG Duty = 5047%(X100)
2315 16:47:22.497026
2316 16:47:22.500616 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2317 16:47:22.500699
2318 16:47:22.503750 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2319 16:47:22.507064 [DutyScan_Calibration_Flow] ====Done====
2320 16:47:22.507145
2321 16:47:22.510121 [DutyScan_Calibration_Flow] k_type=3
2322 16:47:22.527349
2323 16:47:22.527439 ==DQM 0 ==
2324 16:47:22.530883 Final DQM duty delay cell = 0
2325 16:47:22.534308 [0] MAX Duty = 5125%(X100), DQS PI = 20
2326 16:47:22.537322 [0] MIN Duty = 4844%(X100), DQS PI = 52
2327 16:47:22.541208 [0] AVG Duty = 4984%(X100)
2328 16:47:22.541289
2329 16:47:22.541353 ==DQM 1 ==
2330 16:47:22.544734 Final DQM duty delay cell = 0
2331 16:47:22.547153 [0] MAX Duty = 4969%(X100), DQS PI = 2
2332 16:47:22.550568 [0] MIN Duty = 4876%(X100), DQS PI = 20
2333 16:47:22.554003 [0] AVG Duty = 4922%(X100)
2334 16:47:22.554085
2335 16:47:22.557082 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2336 16:47:22.557165
2337 16:47:22.560424 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2338 16:47:22.563808 [DutyScan_Calibration_Flow] ====Done====
2339 16:47:22.563890
2340 16:47:22.567597 [DutyScan_Calibration_Flow] k_type=2
2341 16:47:22.583585
2342 16:47:22.583693 ==DQ 0 ==
2343 16:47:22.587347 Final DQ duty delay cell = 0
2344 16:47:22.590625 [0] MAX Duty = 5125%(X100), DQS PI = 18
2345 16:47:22.593817 [0] MIN Duty = 5000%(X100), DQS PI = 10
2346 16:47:22.593913 [0] AVG Duty = 5062%(X100)
2347 16:47:22.597283
2348 16:47:22.597369 ==DQ 1 ==
2349 16:47:22.600511 Final DQ duty delay cell = 0
2350 16:47:22.603307 [0] MAX Duty = 5156%(X100), DQS PI = 4
2351 16:47:22.606688 [0] MIN Duty = 4938%(X100), DQS PI = 16
2352 16:47:22.606772 [0] AVG Duty = 5047%(X100)
2353 16:47:22.609984
2354 16:47:22.613487 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2355 16:47:22.613571
2356 16:47:22.616842 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2357 16:47:22.619946 [DutyScan_Calibration_Flow] ====Done====
2358 16:47:22.620031 ==
2359 16:47:22.623470 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 16:47:22.626898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 16:47:22.626982 ==
2362 16:47:22.630843 [Duty_Offset_Calibration]
2363 16:47:22.630977 B0:0 B1:-1 CA:3
2364 16:47:22.631046
2365 16:47:22.633238 [DutyScan_Calibration_Flow] k_type=0
2366 16:47:22.642945
2367 16:47:22.643033 ==CLK 0==
2368 16:47:22.646153 Final CLK duty delay cell = -4
2369 16:47:22.649704 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2370 16:47:22.652978 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2371 16:47:22.656247 [-4] AVG Duty = 4938%(X100)
2372 16:47:22.656331
2373 16:47:22.660122 CH1 CLK Duty spec in!! Max-Min= 124%
2374 16:47:22.662858 [DutyScan_Calibration_Flow] ====Done====
2375 16:47:22.662942
2376 16:47:22.666150 [DutyScan_Calibration_Flow] k_type=1
2377 16:47:22.683014
2378 16:47:22.683121 ==DQS 0 ==
2379 16:47:22.686572 Final DQS duty delay cell = 0
2380 16:47:22.689152 [0] MAX Duty = 5187%(X100), DQS PI = 18
2381 16:47:22.692357 [0] MIN Duty = 4907%(X100), DQS PI = 38
2382 16:47:22.695730 [0] AVG Duty = 5047%(X100)
2383 16:47:22.695813
2384 16:47:22.695877 ==DQS 1 ==
2385 16:47:22.699154 Final DQS duty delay cell = 0
2386 16:47:22.702591 [0] MAX Duty = 5156%(X100), DQS PI = 8
2387 16:47:22.705598 [0] MIN Duty = 5000%(X100), DQS PI = 26
2388 16:47:22.705700 [0] AVG Duty = 5078%(X100)
2389 16:47:22.709437
2390 16:47:22.712328 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2391 16:47:22.712410
2392 16:47:22.715998 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2393 16:47:22.719429 [DutyScan_Calibration_Flow] ====Done====
2394 16:47:22.719514
2395 16:47:22.722507 [DutyScan_Calibration_Flow] k_type=3
2396 16:47:22.739061
2397 16:47:22.739179 ==DQM 0 ==
2398 16:47:22.742530 Final DQM duty delay cell = 0
2399 16:47:22.745664 [0] MAX Duty = 5031%(X100), DQS PI = 28
2400 16:47:22.748855 [0] MIN Duty = 4782%(X100), DQS PI = 38
2401 16:47:22.752602 [0] AVG Duty = 4906%(X100)
2402 16:47:22.752684
2403 16:47:22.752748 ==DQM 1 ==
2404 16:47:22.756207 Final DQM duty delay cell = 0
2405 16:47:22.758895 [0] MAX Duty = 5000%(X100), DQS PI = 36
2406 16:47:22.762283 [0] MIN Duty = 4844%(X100), DQS PI = 0
2407 16:47:22.765377 [0] AVG Duty = 4922%(X100)
2408 16:47:22.765460
2409 16:47:22.769654 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2410 16:47:22.769801
2411 16:47:22.772692 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2412 16:47:22.775827 [DutyScan_Calibration_Flow] ====Done====
2413 16:47:22.775910
2414 16:47:22.778497 [DutyScan_Calibration_Flow] k_type=2
2415 16:47:22.794764
2416 16:47:22.794861 ==DQ 0 ==
2417 16:47:22.798181 Final DQ duty delay cell = -4
2418 16:47:22.801269 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2419 16:47:22.804622 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2420 16:47:22.808946 [-4] AVG Duty = 4937%(X100)
2421 16:47:22.809053
2422 16:47:22.809144 ==DQ 1 ==
2423 16:47:22.811422 Final DQ duty delay cell = 0
2424 16:47:22.814514 [0] MAX Duty = 5031%(X100), DQS PI = 34
2425 16:47:22.818114 [0] MIN Duty = 4813%(X100), DQS PI = 62
2426 16:47:22.821114 [0] AVG Duty = 4922%(X100)
2427 16:47:22.821197
2428 16:47:22.824443 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2429 16:47:22.824526
2430 16:47:22.828016 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2431 16:47:22.831009 [DutyScan_Calibration_Flow] ====Done====
2432 16:47:22.834995 nWR fixed to 30
2433 16:47:22.837840 [ModeRegInit_LP4] CH0 RK0
2434 16:47:22.837925 [ModeRegInit_LP4] CH0 RK1
2435 16:47:22.841024 [ModeRegInit_LP4] CH1 RK0
2436 16:47:22.844400 [ModeRegInit_LP4] CH1 RK1
2437 16:47:22.844482 match AC timing 7
2438 16:47:22.850979 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 16:47:22.854565 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 16:47:22.858443 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 16:47:22.864415 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 16:47:22.867921 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 16:47:22.868003 ==
2444 16:47:22.871111 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 16:47:22.874145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 16:47:22.874228 ==
2447 16:47:22.880965 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 16:47:22.887686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 16:47:22.894939 [CA 0] Center 39 (9~70) winsize 62
2450 16:47:22.898539 [CA 1] Center 39 (8~70) winsize 63
2451 16:47:22.901646 [CA 2] Center 35 (5~66) winsize 62
2452 16:47:22.904961 [CA 3] Center 35 (4~66) winsize 63
2453 16:47:22.909035 [CA 4] Center 33 (3~64) winsize 62
2454 16:47:22.911591 [CA 5] Center 33 (3~63) winsize 61
2455 16:47:22.911675
2456 16:47:22.915426 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2457 16:47:22.915510
2458 16:47:22.918322 [CATrainingPosCal] consider 1 rank data
2459 16:47:22.921530 u2DelayCellTimex100 = 270/100 ps
2460 16:47:22.925078 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2461 16:47:22.928271 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2462 16:47:22.934744 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2463 16:47:22.937907 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2464 16:47:22.941400 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2465 16:47:22.945042 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2466 16:47:22.945161
2467 16:47:22.948790 CA PerBit enable=1, Macro0, CA PI delay=33
2468 16:47:22.948877
2469 16:47:22.951521 [CBTSetCACLKResult] CA Dly = 33
2470 16:47:22.951605 CS Dly: 7 (0~38)
2471 16:47:22.955009 ==
2472 16:47:22.955093 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 16:47:22.961682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 16:47:22.961770 ==
2475 16:47:22.965140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 16:47:22.971465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2477 16:47:22.980632 [CA 0] Center 39 (9~70) winsize 62
2478 16:47:22.983862 [CA 1] Center 39 (9~70) winsize 62
2479 16:47:22.988006 [CA 2] Center 35 (5~66) winsize 62
2480 16:47:22.990627 [CA 3] Center 35 (5~66) winsize 62
2481 16:47:22.994253 [CA 4] Center 34 (4~65) winsize 62
2482 16:47:22.997365 [CA 5] Center 33 (3~64) winsize 62
2483 16:47:22.997451
2484 16:47:23.001120 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2485 16:47:23.001207
2486 16:47:23.005515 [CATrainingPosCal] consider 2 rank data
2487 16:47:23.007414 u2DelayCellTimex100 = 270/100 ps
2488 16:47:23.010924 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2489 16:47:23.017374 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2490 16:47:23.020634 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2491 16:47:23.024226 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2492 16:47:23.027066 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2493 16:47:23.030220 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2494 16:47:23.030303
2495 16:47:23.033749 CA PerBit enable=1, Macro0, CA PI delay=33
2496 16:47:23.033840
2497 16:47:23.036869 [CBTSetCACLKResult] CA Dly = 33
2498 16:47:23.036953 CS Dly: 8 (0~41)
2499 16:47:23.040331
2500 16:47:23.043600 ----->DramcWriteLeveling(PI) begin...
2501 16:47:23.043685 ==
2502 16:47:23.047460 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 16:47:23.050659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 16:47:23.050742 ==
2505 16:47:23.053588 Write leveling (Byte 0): 29 => 29
2506 16:47:23.056832 Write leveling (Byte 1): 27 => 27
2507 16:47:23.061150 DramcWriteLeveling(PI) end<-----
2508 16:47:23.061238
2509 16:47:23.061323 ==
2510 16:47:23.063427 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 16:47:23.067067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 16:47:23.067152 ==
2513 16:47:23.069955 [Gating] SW mode calibration
2514 16:47:23.077601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 16:47:23.083464 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 16:47:23.087441 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2517 16:47:23.090144 0 15 4 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
2518 16:47:23.096675 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 16:47:23.100489 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 16:47:23.103357 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 16:47:23.109968 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 16:47:23.113391 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2523 16:47:23.116441 0 15 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
2524 16:47:23.123165 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2525 16:47:23.126560 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 16:47:23.129841 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 16:47:23.136636 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 16:47:23.139795 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 16:47:23.143093 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 16:47:23.149699 1 0 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2531 16:47:23.152958 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2532 16:47:23.156307 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (1 1) (0 0)
2533 16:47:23.159889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 16:47:23.166411 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 16:47:23.169724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 16:47:23.173265 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 16:47:23.179916 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 16:47:23.183035 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 16:47:23.186299 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 16:47:23.193144 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2541 16:47:23.196291 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 16:47:23.199737 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 16:47:23.206460 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 16:47:23.209767 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 16:47:23.213352 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 16:47:23.219411 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 16:47:23.222646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 16:47:23.226148 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 16:47:23.232485 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 16:47:23.235947 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 16:47:23.239134 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 16:47:23.245852 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 16:47:23.249558 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 16:47:23.252630 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2555 16:47:23.259212 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2556 16:47:23.259311 Total UI for P1: 0, mck2ui 16
2557 16:47:23.266330 best dqsien dly found for B0: ( 1, 3, 24)
2558 16:47:23.269043 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2559 16:47:23.272462 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 16:47:23.275901 Total UI for P1: 0, mck2ui 16
2561 16:47:23.279094 best dqsien dly found for B1: ( 1, 3, 30)
2562 16:47:23.282050 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2563 16:47:23.285264 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2564 16:47:23.285347
2565 16:47:23.292146 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2566 16:47:23.295225 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2567 16:47:23.299102 [Gating] SW calibration Done
2568 16:47:23.299192 ==
2569 16:47:23.302194 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 16:47:23.305250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 16:47:23.305354 ==
2572 16:47:23.305451 RX Vref Scan: 0
2573 16:47:23.305528
2574 16:47:23.308581 RX Vref 0 -> 0, step: 1
2575 16:47:23.308664
2576 16:47:23.312147 RX Delay -40 -> 252, step: 8
2577 16:47:23.315561 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 16:47:23.318687 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2579 16:47:23.325569 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 16:47:23.328519 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2581 16:47:23.332238 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2582 16:47:23.334994 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2583 16:47:23.338552 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 16:47:23.345442 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 16:47:23.348914 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2586 16:47:23.351799 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2587 16:47:23.355405 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2588 16:47:23.358816 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2589 16:47:23.362041 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 16:47:23.368161 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2591 16:47:23.371811 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2592 16:47:23.375106 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2593 16:47:23.375249 ==
2594 16:47:23.378326 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 16:47:23.381835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 16:47:23.385373 ==
2597 16:47:23.385459 DQS Delay:
2598 16:47:23.385526 DQS0 = 0, DQS1 = 0
2599 16:47:23.388338 DQM Delay:
2600 16:47:23.388446 DQM0 = 120, DQM1 = 106
2601 16:47:23.391681 DQ Delay:
2602 16:47:23.394979 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2603 16:47:23.398563 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2604 16:47:23.401562 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2605 16:47:23.405375 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2606 16:47:23.405458
2607 16:47:23.405523
2608 16:47:23.405583 ==
2609 16:47:23.407998 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 16:47:23.411733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 16:47:23.411816 ==
2612 16:47:23.411881
2613 16:47:23.415315
2614 16:47:23.415398 TX Vref Scan disable
2615 16:47:23.418367 == TX Byte 0 ==
2616 16:47:23.421910 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2617 16:47:23.424609 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2618 16:47:23.427983 == TX Byte 1 ==
2619 16:47:23.431882 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2620 16:47:23.434929 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2621 16:47:23.435018 ==
2622 16:47:23.438114 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 16:47:23.444746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 16:47:23.444841 ==
2625 16:47:23.455875 TX Vref=22, minBit 0, minWin=25, winSum=411
2626 16:47:23.458652 TX Vref=24, minBit 4, minWin=25, winSum=414
2627 16:47:23.461971 TX Vref=26, minBit 3, minWin=25, winSum=424
2628 16:47:23.465113 TX Vref=28, minBit 1, minWin=26, winSum=426
2629 16:47:23.468459 TX Vref=30, minBit 0, minWin=26, winSum=426
2630 16:47:23.475396 TX Vref=32, minBit 0, minWin=26, winSum=425
2631 16:47:23.478736 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 28
2632 16:47:23.478821
2633 16:47:23.481874 Final TX Range 1 Vref 28
2634 16:47:23.481957
2635 16:47:23.482022 ==
2636 16:47:23.485180 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 16:47:23.488331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 16:47:23.491705 ==
2639 16:47:23.491794
2640 16:47:23.491897
2641 16:47:23.492039 TX Vref Scan disable
2642 16:47:23.495018 == TX Byte 0 ==
2643 16:47:23.498668 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2644 16:47:23.501883 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2645 16:47:23.505010 == TX Byte 1 ==
2646 16:47:23.508393 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2647 16:47:23.514846 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2648 16:47:23.514960
2649 16:47:23.515056 [DATLAT]
2650 16:47:23.515145 Freq=1200, CH0 RK0
2651 16:47:23.515241
2652 16:47:23.518264 DATLAT Default: 0xd
2653 16:47:23.518362 0, 0xFFFF, sum = 0
2654 16:47:23.521642 1, 0xFFFF, sum = 0
2655 16:47:23.525436 2, 0xFFFF, sum = 0
2656 16:47:23.525520 3, 0xFFFF, sum = 0
2657 16:47:23.528153 4, 0xFFFF, sum = 0
2658 16:47:23.528244 5, 0xFFFF, sum = 0
2659 16:47:23.532153 6, 0xFFFF, sum = 0
2660 16:47:23.532243 7, 0xFFFF, sum = 0
2661 16:47:23.534824 8, 0xFFFF, sum = 0
2662 16:47:23.534938 9, 0xFFFF, sum = 0
2663 16:47:23.538504 10, 0xFFFF, sum = 0
2664 16:47:23.538589 11, 0xFFFF, sum = 0
2665 16:47:23.541446 12, 0x0, sum = 1
2666 16:47:23.541557 13, 0x0, sum = 2
2667 16:47:23.544898 14, 0x0, sum = 3
2668 16:47:23.544982 15, 0x0, sum = 4
2669 16:47:23.548151 best_step = 13
2670 16:47:23.548234
2671 16:47:23.548299 ==
2672 16:47:23.551307 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 16:47:23.555071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 16:47:23.555182 ==
2675 16:47:23.555279 RX Vref Scan: 1
2676 16:47:23.558701
2677 16:47:23.558780 Set Vref Range= 32 -> 127
2678 16:47:23.558842
2679 16:47:23.561437 RX Vref 32 -> 127, step: 1
2680 16:47:23.561520
2681 16:47:23.564678 RX Delay -21 -> 252, step: 4
2682 16:47:23.564761
2683 16:47:23.568164 Set Vref, RX VrefLevel [Byte0]: 32
2684 16:47:23.570962 [Byte1]: 32
2685 16:47:23.571046
2686 16:47:23.574645 Set Vref, RX VrefLevel [Byte0]: 33
2687 16:47:23.578029 [Byte1]: 33
2688 16:47:23.581547
2689 16:47:23.581642 Set Vref, RX VrefLevel [Byte0]: 34
2690 16:47:23.585511 [Byte1]: 34
2691 16:47:23.589530
2692 16:47:23.589617 Set Vref, RX VrefLevel [Byte0]: 35
2693 16:47:23.592834 [Byte1]: 35
2694 16:47:23.597619
2695 16:47:23.597703 Set Vref, RX VrefLevel [Byte0]: 36
2696 16:47:23.601618 [Byte1]: 36
2697 16:47:23.605341
2698 16:47:23.605424 Set Vref, RX VrefLevel [Byte0]: 37
2699 16:47:23.608466 [Byte1]: 37
2700 16:47:23.613423
2701 16:47:23.613505 Set Vref, RX VrefLevel [Byte0]: 38
2702 16:47:23.617043 [Byte1]: 38
2703 16:47:23.621457
2704 16:47:23.621539 Set Vref, RX VrefLevel [Byte0]: 39
2705 16:47:23.624482 [Byte1]: 39
2706 16:47:23.629089
2707 16:47:23.629173 Set Vref, RX VrefLevel [Byte0]: 40
2708 16:47:23.632244 [Byte1]: 40
2709 16:47:23.637452
2710 16:47:23.637548 Set Vref, RX VrefLevel [Byte0]: 41
2711 16:47:23.640390 [Byte1]: 41
2712 16:47:23.644845
2713 16:47:23.644930 Set Vref, RX VrefLevel [Byte0]: 42
2714 16:47:23.648084 [Byte1]: 42
2715 16:47:23.653102
2716 16:47:23.653187 Set Vref, RX VrefLevel [Byte0]: 43
2717 16:47:23.656318 [Byte1]: 43
2718 16:47:23.660755
2719 16:47:23.660843 Set Vref, RX VrefLevel [Byte0]: 44
2720 16:47:23.664167 [Byte1]: 44
2721 16:47:23.669358
2722 16:47:23.669453 Set Vref, RX VrefLevel [Byte0]: 45
2723 16:47:23.671964 [Byte1]: 45
2724 16:47:23.676528
2725 16:47:23.676616 Set Vref, RX VrefLevel [Byte0]: 46
2726 16:47:23.680056 [Byte1]: 46
2727 16:47:23.684398
2728 16:47:23.684489 Set Vref, RX VrefLevel [Byte0]: 47
2729 16:47:23.687892 [Byte1]: 47
2730 16:47:23.692630
2731 16:47:23.692717 Set Vref, RX VrefLevel [Byte0]: 48
2732 16:47:23.695623 [Byte1]: 48
2733 16:47:23.700645
2734 16:47:23.700729 Set Vref, RX VrefLevel [Byte0]: 49
2735 16:47:23.703504 [Byte1]: 49
2736 16:47:23.708217
2737 16:47:23.708302 Set Vref, RX VrefLevel [Byte0]: 50
2738 16:47:23.711989 [Byte1]: 50
2739 16:47:23.716542
2740 16:47:23.716626 Set Vref, RX VrefLevel [Byte0]: 51
2741 16:47:23.719777 [Byte1]: 51
2742 16:47:23.724467
2743 16:47:23.724552 Set Vref, RX VrefLevel [Byte0]: 52
2744 16:47:23.727737 [Byte1]: 52
2745 16:47:23.732421
2746 16:47:23.732525 Set Vref, RX VrefLevel [Byte0]: 53
2747 16:47:23.735314 [Byte1]: 53
2748 16:47:23.739905
2749 16:47:23.739997 Set Vref, RX VrefLevel [Byte0]: 54
2750 16:47:23.743912 [Byte1]: 54
2751 16:47:23.748297
2752 16:47:23.748387 Set Vref, RX VrefLevel [Byte0]: 55
2753 16:47:23.751476 [Byte1]: 55
2754 16:47:23.755939
2755 16:47:23.756035 Set Vref, RX VrefLevel [Byte0]: 56
2756 16:47:23.759015 [Byte1]: 56
2757 16:47:23.764266
2758 16:47:23.764361 Set Vref, RX VrefLevel [Byte0]: 57
2759 16:47:23.767041 [Byte1]: 57
2760 16:47:23.771597
2761 16:47:23.771687 Set Vref, RX VrefLevel [Byte0]: 58
2762 16:47:23.775243 [Byte1]: 58
2763 16:47:23.779786
2764 16:47:23.779878 Set Vref, RX VrefLevel [Byte0]: 59
2765 16:47:23.783109 [Byte1]: 59
2766 16:47:23.788143
2767 16:47:23.788234 Set Vref, RX VrefLevel [Byte0]: 60
2768 16:47:23.791168 [Byte1]: 60
2769 16:47:23.796195
2770 16:47:23.796283 Set Vref, RX VrefLevel [Byte0]: 61
2771 16:47:23.798701 [Byte1]: 61
2772 16:47:23.803855
2773 16:47:23.803946 Set Vref, RX VrefLevel [Byte0]: 62
2774 16:47:23.806889 [Byte1]: 62
2775 16:47:23.811664
2776 16:47:23.811748 Set Vref, RX VrefLevel [Byte0]: 63
2777 16:47:23.814762 [Byte1]: 63
2778 16:47:23.819538
2779 16:47:23.819623 Set Vref, RX VrefLevel [Byte0]: 64
2780 16:47:23.822786 [Byte1]: 64
2781 16:47:23.827085
2782 16:47:23.827249 Set Vref, RX VrefLevel [Byte0]: 65
2783 16:47:23.830368 [Byte1]: 65
2784 16:47:23.835008
2785 16:47:23.835129 Set Vref, RX VrefLevel [Byte0]: 66
2786 16:47:23.839024 [Byte1]: 66
2787 16:47:23.844036
2788 16:47:23.844124 Set Vref, RX VrefLevel [Byte0]: 67
2789 16:47:23.846668 [Byte1]: 67
2790 16:47:23.851671
2791 16:47:23.851760 Set Vref, RX VrefLevel [Byte0]: 68
2792 16:47:23.854497 [Byte1]: 68
2793 16:47:23.859120
2794 16:47:23.859263 Final RX Vref Byte 0 = 58 to rank0
2795 16:47:23.862383 Final RX Vref Byte 1 = 49 to rank0
2796 16:47:23.865337 Final RX Vref Byte 0 = 58 to rank1
2797 16:47:23.869067 Final RX Vref Byte 1 = 49 to rank1==
2798 16:47:23.872167 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 16:47:23.878534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 16:47:23.878641 ==
2801 16:47:23.878708 DQS Delay:
2802 16:47:23.882159 DQS0 = 0, DQS1 = 0
2803 16:47:23.882249 DQM Delay:
2804 16:47:23.882316 DQM0 = 119, DQM1 = 105
2805 16:47:23.885503 DQ Delay:
2806 16:47:23.888775 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =114
2807 16:47:23.892253 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2808 16:47:23.895547 DQ8 =94, DQ9 =92, DQ10 =104, DQ11 =100
2809 16:47:23.899070 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2810 16:47:23.899193
2811 16:47:23.899262
2812 16:47:23.909053 [DQSOSCAuto] RK0, (LSB)MR18= 0xfef9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2813 16:47:23.909172 CH0 RK0: MR19=303, MR18=FEF9
2814 16:47:23.915046 CH0_RK0: MR19=0x303, MR18=0xFEF9, DQSOSC=410, MR23=63, INC=39, DEC=26
2815 16:47:23.915144
2816 16:47:23.918817 ----->DramcWriteLeveling(PI) begin...
2817 16:47:23.918914 ==
2818 16:47:23.921965 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 16:47:23.928442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 16:47:23.928545 ==
2821 16:47:23.931733 Write leveling (Byte 0): 33 => 33
2822 16:47:23.931821 Write leveling (Byte 1): 27 => 27
2823 16:47:23.935179 DramcWriteLeveling(PI) end<-----
2824 16:47:23.935286
2825 16:47:23.938187 ==
2826 16:47:23.938296 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 16:47:23.944892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 16:47:23.944982 ==
2829 16:47:23.948646 [Gating] SW mode calibration
2830 16:47:23.955226 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 16:47:23.958511 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 16:47:23.965046 0 15 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
2833 16:47:23.968261 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 16:47:23.971677 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 16:47:23.978094 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 16:47:23.981346 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 16:47:23.984739 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 16:47:23.991251 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2839 16:47:23.994850 0 15 28 | B1->B0 | 3434 2929 | 1 1 | (1 0) (0 0)
2840 16:47:23.998334 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2841 16:47:24.004617 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 16:47:24.008099 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 16:47:24.011251 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 16:47:24.018277 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 16:47:24.022043 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 16:47:24.025138 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2847 16:47:24.028289 1 0 28 | B1->B0 | 2d2d 4545 | 0 0 | (0 0) (0 0)
2848 16:47:24.034822 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2849 16:47:24.037974 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 16:47:24.041108 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 16:47:24.047680 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 16:47:24.051513 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 16:47:24.054451 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 16:47:24.061107 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2855 16:47:24.064552 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2856 16:47:24.067974 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2857 16:47:24.074524 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 16:47:24.078015 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 16:47:24.081141 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 16:47:24.087683 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 16:47:24.091244 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 16:47:24.094523 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 16:47:24.101275 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 16:47:24.104193 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 16:47:24.107744 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 16:47:24.114435 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 16:47:24.117498 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 16:47:24.121016 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 16:47:24.127815 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 16:47:24.131149 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2871 16:47:24.134873 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2872 16:47:24.137875 Total UI for P1: 0, mck2ui 16
2873 16:47:24.140857 best dqsien dly found for B0: ( 1, 3, 24)
2874 16:47:24.144197 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2875 16:47:24.151487 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 16:47:24.154328 Total UI for P1: 0, mck2ui 16
2877 16:47:24.158094 best dqsien dly found for B1: ( 1, 3, 30)
2878 16:47:24.161251 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2879 16:47:24.164024 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2880 16:47:24.164110
2881 16:47:24.167453 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2882 16:47:24.170803 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 16:47:24.174088 [Gating] SW calibration Done
2884 16:47:24.174188 ==
2885 16:47:24.177277 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 16:47:24.180905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 16:47:24.180989 ==
2888 16:47:24.183992 RX Vref Scan: 0
2889 16:47:24.184074
2890 16:47:24.187667 RX Vref 0 -> 0, step: 1
2891 16:47:24.187751
2892 16:47:24.187815 RX Delay -40 -> 252, step: 8
2893 16:47:24.193953 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2894 16:47:24.197357 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2895 16:47:24.200463 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2896 16:47:24.203801 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2897 16:47:24.207530 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2898 16:47:24.214648 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2899 16:47:24.217190 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2900 16:47:24.220799 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2901 16:47:24.223799 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2902 16:47:24.226768 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2903 16:47:24.233933 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2904 16:47:24.236741 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2905 16:47:24.240603 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2906 16:47:24.243737 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2907 16:47:24.250319 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2908 16:47:24.253264 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2909 16:47:24.253349 ==
2910 16:47:24.256747 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 16:47:24.259966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 16:47:24.260049 ==
2913 16:47:24.263661 DQS Delay:
2914 16:47:24.263744 DQS0 = 0, DQS1 = 0
2915 16:47:24.263809 DQM Delay:
2916 16:47:24.266804 DQM0 = 119, DQM1 = 106
2917 16:47:24.266886 DQ Delay:
2918 16:47:24.269793 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2919 16:47:24.273274 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2920 16:47:24.276720 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2921 16:47:24.283689 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2922 16:47:24.283776
2923 16:47:24.283841
2924 16:47:24.283899 ==
2925 16:47:24.286372 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 16:47:24.289793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 16:47:24.289878 ==
2928 16:47:24.289942
2929 16:47:24.290000
2930 16:47:24.292944 TX Vref Scan disable
2931 16:47:24.293056 == TX Byte 0 ==
2932 16:47:24.299859 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2933 16:47:24.303329 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2934 16:47:24.303415 == TX Byte 1 ==
2935 16:47:24.309498 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2936 16:47:24.313031 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2937 16:47:24.313116 ==
2938 16:47:24.316479 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 16:47:24.319628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 16:47:24.319711 ==
2941 16:47:24.333471 TX Vref=22, minBit 3, minWin=25, winSum=413
2942 16:47:24.336719 TX Vref=24, minBit 1, minWin=26, winSum=422
2943 16:47:24.339630 TX Vref=26, minBit 1, minWin=26, winSum=424
2944 16:47:24.343066 TX Vref=28, minBit 10, minWin=26, winSum=428
2945 16:47:24.346579 TX Vref=30, minBit 14, minWin=25, winSum=426
2946 16:47:24.352570 TX Vref=32, minBit 12, minWin=25, winSum=426
2947 16:47:24.356183 [TxChooseVref] Worse bit 10, Min win 26, Win sum 428, Final Vref 28
2948 16:47:24.356265
2949 16:47:24.359380 Final TX Range 1 Vref 28
2950 16:47:24.359461
2951 16:47:24.359526 ==
2952 16:47:24.362627 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 16:47:24.366401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 16:47:24.369258 ==
2955 16:47:24.369341
2956 16:47:24.369503
2957 16:47:24.369583 TX Vref Scan disable
2958 16:47:24.372898 == TX Byte 0 ==
2959 16:47:24.376204 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2960 16:47:24.383158 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2961 16:47:24.383263 == TX Byte 1 ==
2962 16:47:24.387322 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2963 16:47:24.392784 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2964 16:47:24.392890
2965 16:47:24.392983 [DATLAT]
2966 16:47:24.393070 Freq=1200, CH0 RK1
2967 16:47:24.393150
2968 16:47:24.396148 DATLAT Default: 0xd
2969 16:47:24.396229 0, 0xFFFF, sum = 0
2970 16:47:24.400019 1, 0xFFFF, sum = 0
2971 16:47:24.403083 2, 0xFFFF, sum = 0
2972 16:47:24.403194 3, 0xFFFF, sum = 0
2973 16:47:24.406217 4, 0xFFFF, sum = 0
2974 16:47:24.406299 5, 0xFFFF, sum = 0
2975 16:47:24.409416 6, 0xFFFF, sum = 0
2976 16:47:24.409500 7, 0xFFFF, sum = 0
2977 16:47:24.413193 8, 0xFFFF, sum = 0
2978 16:47:24.413275 9, 0xFFFF, sum = 0
2979 16:47:24.416248 10, 0xFFFF, sum = 0
2980 16:47:24.416330 11, 0xFFFF, sum = 0
2981 16:47:24.419580 12, 0x0, sum = 1
2982 16:47:24.419662 13, 0x0, sum = 2
2983 16:47:24.422615 14, 0x0, sum = 3
2984 16:47:24.422697 15, 0x0, sum = 4
2985 16:47:24.426060 best_step = 13
2986 16:47:24.426141
2987 16:47:24.426205 ==
2988 16:47:24.429652 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 16:47:24.432453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 16:47:24.432534 ==
2991 16:47:24.432598 RX Vref Scan: 0
2992 16:47:24.435841
2993 16:47:24.435924 RX Vref 0 -> 0, step: 1
2994 16:47:24.435988
2995 16:47:24.439387 RX Delay -21 -> 252, step: 4
2996 16:47:24.446571 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
2997 16:47:24.449142 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
2998 16:47:24.452248 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
2999 16:47:24.455889 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3000 16:47:24.459102 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3001 16:47:24.462664 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3002 16:47:24.469183 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3003 16:47:24.472734 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3004 16:47:24.475723 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3005 16:47:24.479090 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3006 16:47:24.482742 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3007 16:47:24.489372 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3008 16:47:24.491998 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3009 16:47:24.495894 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3010 16:47:24.499055 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3011 16:47:24.502424 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3012 16:47:24.506291 ==
3013 16:47:24.509179 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 16:47:24.512382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 16:47:24.512465 ==
3016 16:47:24.512531 DQS Delay:
3017 16:47:24.516240 DQS0 = 0, DQS1 = 0
3018 16:47:24.516323 DQM Delay:
3019 16:47:24.518767 DQM0 = 118, DQM1 = 106
3020 16:47:24.518850 DQ Delay:
3021 16:47:24.522085 DQ0 =116, DQ1 =118, DQ2 =114, DQ3 =116
3022 16:47:24.525427 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =122
3023 16:47:24.529093 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3024 16:47:24.532514 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3025 16:47:24.532601
3026 16:47:24.532666
3027 16:47:24.542533 [DQSOSCAuto] RK1, (LSB)MR18= 0xfe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
3028 16:47:24.542639 CH0 RK1: MR19=403, MR18=FE
3029 16:47:24.548835 CH0_RK1: MR19=0x403, MR18=0xFE, DQSOSC=410, MR23=63, INC=39, DEC=26
3030 16:47:24.552024 [RxdqsGatingPostProcess] freq 1200
3031 16:47:24.559207 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3032 16:47:24.562286 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 16:47:24.565186 best DQS1 dly(2T, 0.5T) = (0, 11)
3034 16:47:24.568499 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 16:47:24.572454 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3036 16:47:24.575482 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 16:47:24.575569 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 16:47:24.578447 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 16:47:24.581760 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 16:47:24.585041 Pre-setting of DQS Precalculation
3041 16:47:24.592045 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3042 16:47:24.592137 ==
3043 16:47:24.595176 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 16:47:24.598495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 16:47:24.598579 ==
3046 16:47:24.605918 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3047 16:47:24.611689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3048 16:47:24.618780 [CA 0] Center 38 (8~68) winsize 61
3049 16:47:24.622255 [CA 1] Center 37 (7~68) winsize 62
3050 16:47:24.625651 [CA 2] Center 35 (6~65) winsize 60
3051 16:47:24.628802 [CA 3] Center 34 (4~64) winsize 61
3052 16:47:24.632190 [CA 4] Center 35 (5~65) winsize 61
3053 16:47:24.635334 [CA 5] Center 34 (4~64) winsize 61
3054 16:47:24.635425
3055 16:47:24.638739 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3056 16:47:24.638823
3057 16:47:24.641767 [CATrainingPosCal] consider 1 rank data
3058 16:47:24.645909 u2DelayCellTimex100 = 270/100 ps
3059 16:47:24.648654 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3060 16:47:24.655086 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3061 16:47:24.658453 CA2 delay=35 (6~65),Diff = 1 PI (4 cell)
3062 16:47:24.662125 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3063 16:47:24.665480 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3064 16:47:24.668555 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3065 16:47:24.668638
3066 16:47:24.671772 CA PerBit enable=1, Macro0, CA PI delay=34
3067 16:47:24.671855
3068 16:47:24.675514 [CBTSetCACLKResult] CA Dly = 34
3069 16:47:24.675597 CS Dly: 4 (0~35)
3070 16:47:24.678766 ==
3071 16:47:24.681668 Dram Type= 6, Freq= 0, CH_1, rank 1
3072 16:47:24.685044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 16:47:24.685128 ==
3074 16:47:24.691552 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 16:47:24.694818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3076 16:47:24.704516 [CA 0] Center 38 (8~68) winsize 61
3077 16:47:24.707663 [CA 1] Center 38 (8~68) winsize 61
3078 16:47:24.711401 [CA 2] Center 34 (4~65) winsize 62
3079 16:47:24.715302 [CA 3] Center 33 (3~64) winsize 62
3080 16:47:24.717796 [CA 4] Center 34 (4~64) winsize 61
3081 16:47:24.720895 [CA 5] Center 33 (3~63) winsize 61
3082 16:47:24.720976
3083 16:47:24.724174 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3084 16:47:24.724255
3085 16:47:24.727826 [CATrainingPosCal] consider 2 rank data
3086 16:47:24.730964 u2DelayCellTimex100 = 270/100 ps
3087 16:47:24.734265 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3088 16:47:24.737927 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 16:47:24.744024 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3090 16:47:24.747479 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3091 16:47:24.750882 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3092 16:47:24.754220 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 16:47:24.754307
3094 16:47:24.757832 CA PerBit enable=1, Macro0, CA PI delay=33
3095 16:47:24.757918
3096 16:47:24.760810 [CBTSetCACLKResult] CA Dly = 33
3097 16:47:24.760896 CS Dly: 6 (0~39)
3098 16:47:24.764008
3099 16:47:24.767843 ----->DramcWriteLeveling(PI) begin...
3100 16:47:24.767929 ==
3101 16:47:24.770763 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 16:47:24.773840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 16:47:24.773926 ==
3104 16:47:24.777601 Write leveling (Byte 0): 27 => 27
3105 16:47:24.780558 Write leveling (Byte 1): 27 => 27
3106 16:47:24.783701 DramcWriteLeveling(PI) end<-----
3107 16:47:24.783787
3108 16:47:24.783872 ==
3109 16:47:24.787434 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 16:47:24.790596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 16:47:24.790680 ==
3112 16:47:24.793824 [Gating] SW mode calibration
3113 16:47:24.800582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3114 16:47:24.807495 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3115 16:47:24.810380 0 15 0 | B1->B0 | 3030 3333 | 1 0 | (1 1) (0 0)
3116 16:47:24.815157 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 16:47:24.820730 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 16:47:24.824333 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 16:47:24.827118 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 16:47:24.833621 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 16:47:24.837054 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 1)
3122 16:47:24.840430 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 1) (1 0)
3123 16:47:24.847766 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 16:47:24.850167 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 16:47:24.853782 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 16:47:24.857282 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 16:47:24.863650 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 16:47:24.867521 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 16:47:24.870303 1 0 24 | B1->B0 | 2424 2a29 | 0 1 | (0 0) (0 0)
3130 16:47:24.877038 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3131 16:47:24.880014 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 16:47:24.884140 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 16:47:24.889892 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 16:47:24.893558 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 16:47:24.896601 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 16:47:24.903068 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 16:47:24.906549 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 16:47:24.910013 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3139 16:47:24.916837 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 16:47:24.920590 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 16:47:24.923673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 16:47:24.929626 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 16:47:24.933273 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 16:47:24.936982 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 16:47:24.943338 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 16:47:24.946412 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 16:47:24.949763 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 16:47:24.956702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 16:47:24.959512 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 16:47:24.962774 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 16:47:24.969273 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 16:47:24.973186 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 16:47:24.976382 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 16:47:24.982783 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3155 16:47:24.985776 Total UI for P1: 0, mck2ui 16
3156 16:47:24.989515 best dqsien dly found for B0: ( 1, 3, 26)
3157 16:47:24.992722 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 16:47:24.997014 Total UI for P1: 0, mck2ui 16
3159 16:47:24.999960 best dqsien dly found for B1: ( 1, 3, 28)
3160 16:47:25.002529 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3161 16:47:25.006332 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3162 16:47:25.006415
3163 16:47:25.009408 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3164 16:47:25.012394 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3165 16:47:25.015828 [Gating] SW calibration Done
3166 16:47:25.015911 ==
3167 16:47:25.019416 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 16:47:25.022662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 16:47:25.026667 ==
3170 16:47:25.026749 RX Vref Scan: 0
3171 16:47:25.026815
3172 16:47:25.029031 RX Vref 0 -> 0, step: 1
3173 16:47:25.029114
3174 16:47:25.032289 RX Delay -40 -> 252, step: 8
3175 16:47:25.035656 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3176 16:47:25.039022 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3177 16:47:25.042602 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3178 16:47:25.045985 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3179 16:47:25.052506 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3180 16:47:25.055775 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3181 16:47:25.059513 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3182 16:47:25.063454 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3183 16:47:25.065866 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3184 16:47:25.069415 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3185 16:47:25.075792 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3186 16:47:25.079495 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3187 16:47:25.082643 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3188 16:47:25.086077 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3189 16:47:25.092661 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3190 16:47:25.096040 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3191 16:47:25.096134 ==
3192 16:47:25.099308 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 16:47:25.103030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 16:47:25.103113 ==
3195 16:47:25.105603 DQS Delay:
3196 16:47:25.105685 DQS0 = 0, DQS1 = 0
3197 16:47:25.105751 DQM Delay:
3198 16:47:25.108916 DQM0 = 115, DQM1 = 112
3199 16:47:25.108999 DQ Delay:
3200 16:47:25.112234 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =115
3201 16:47:25.115885 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3202 16:47:25.119393 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3203 16:47:25.125889 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3204 16:47:25.125974
3205 16:47:25.126038
3206 16:47:25.126098 ==
3207 16:47:25.130019 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 16:47:25.132092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 16:47:25.132176 ==
3210 16:47:25.132241
3211 16:47:25.132301
3212 16:47:25.135998 TX Vref Scan disable
3213 16:47:25.136083 == TX Byte 0 ==
3214 16:47:25.142117 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3215 16:47:25.145672 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3216 16:47:25.145782 == TX Byte 1 ==
3217 16:47:25.151933 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3218 16:47:25.155445 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3219 16:47:25.155529 ==
3220 16:47:25.158684 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 16:47:25.161936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 16:47:25.162019 ==
3223 16:47:25.174686 TX Vref=22, minBit 8, minWin=24, winSum=409
3224 16:47:25.177719 TX Vref=24, minBit 1, minWin=25, winSum=412
3225 16:47:25.180904 TX Vref=26, minBit 9, minWin=24, winSum=418
3226 16:47:25.184097 TX Vref=28, minBit 0, minWin=26, winSum=426
3227 16:47:25.187823 TX Vref=30, minBit 0, minWin=26, winSum=424
3228 16:47:25.194689 TX Vref=32, minBit 11, minWin=25, winSum=424
3229 16:47:25.197829 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
3230 16:47:25.197932
3231 16:47:25.201706 Final TX Range 1 Vref 28
3232 16:47:25.201789
3233 16:47:25.201852 ==
3234 16:47:25.204394 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 16:47:25.207525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 16:47:25.207608 ==
3237 16:47:25.210763
3238 16:47:25.210861
3239 16:47:25.210940 TX Vref Scan disable
3240 16:47:25.214069 == TX Byte 0 ==
3241 16:47:25.217801 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3242 16:47:25.224178 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3243 16:47:25.224261 == TX Byte 1 ==
3244 16:47:25.227284 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3245 16:47:25.230821 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3246 16:47:25.234061
3247 16:47:25.234142 [DATLAT]
3248 16:47:25.234207 Freq=1200, CH1 RK0
3249 16:47:25.234267
3250 16:47:25.237434 DATLAT Default: 0xd
3251 16:47:25.237548 0, 0xFFFF, sum = 0
3252 16:47:25.240814 1, 0xFFFF, sum = 0
3253 16:47:25.240897 2, 0xFFFF, sum = 0
3254 16:47:25.243789 3, 0xFFFF, sum = 0
3255 16:47:25.247076 4, 0xFFFF, sum = 0
3256 16:47:25.247223 5, 0xFFFF, sum = 0
3257 16:47:25.250452 6, 0xFFFF, sum = 0
3258 16:47:25.250534 7, 0xFFFF, sum = 0
3259 16:47:25.253741 8, 0xFFFF, sum = 0
3260 16:47:25.253824 9, 0xFFFF, sum = 0
3261 16:47:25.257109 10, 0xFFFF, sum = 0
3262 16:47:25.257202 11, 0xFFFF, sum = 0
3263 16:47:25.260529 12, 0x0, sum = 1
3264 16:47:25.260632 13, 0x0, sum = 2
3265 16:47:25.265001 14, 0x0, sum = 3
3266 16:47:25.265109 15, 0x0, sum = 4
3267 16:47:25.267016 best_step = 13
3268 16:47:25.267102
3269 16:47:25.267168 ==
3270 16:47:25.270353 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 16:47:25.274396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 16:47:25.274519 ==
3273 16:47:25.274616 RX Vref Scan: 1
3274 16:47:25.274704
3275 16:47:25.277372 Set Vref Range= 32 -> 127
3276 16:47:25.277480
3277 16:47:25.281237 RX Vref 32 -> 127, step: 1
3278 16:47:25.281321
3279 16:47:25.284174 RX Delay -13 -> 252, step: 4
3280 16:47:25.284261
3281 16:47:25.286786 Set Vref, RX VrefLevel [Byte0]: 32
3282 16:47:25.290171 [Byte1]: 32
3283 16:47:25.290255
3284 16:47:25.293769 Set Vref, RX VrefLevel [Byte0]: 33
3285 16:47:25.296661 [Byte1]: 33
3286 16:47:25.300355
3287 16:47:25.300437 Set Vref, RX VrefLevel [Byte0]: 34
3288 16:47:25.303596 [Byte1]: 34
3289 16:47:25.309114
3290 16:47:25.309197 Set Vref, RX VrefLevel [Byte0]: 35
3291 16:47:25.311672 [Byte1]: 35
3292 16:47:25.316704
3293 16:47:25.316793 Set Vref, RX VrefLevel [Byte0]: 36
3294 16:47:25.320744 [Byte1]: 36
3295 16:47:25.324026
3296 16:47:25.324110 Set Vref, RX VrefLevel [Byte0]: 37
3297 16:47:25.327700 [Byte1]: 37
3298 16:47:25.332223
3299 16:47:25.332336 Set Vref, RX VrefLevel [Byte0]: 38
3300 16:47:25.335136 [Byte1]: 38
3301 16:47:25.340876
3302 16:47:25.340963 Set Vref, RX VrefLevel [Byte0]: 39
3303 16:47:25.343445 [Byte1]: 39
3304 16:47:25.348230
3305 16:47:25.348311 Set Vref, RX VrefLevel [Byte0]: 40
3306 16:47:25.351004 [Byte1]: 40
3307 16:47:25.355633
3308 16:47:25.355718 Set Vref, RX VrefLevel [Byte0]: 41
3309 16:47:25.358889 [Byte1]: 41
3310 16:47:25.363612
3311 16:47:25.363692 Set Vref, RX VrefLevel [Byte0]: 42
3312 16:47:25.366902 [Byte1]: 42
3313 16:47:25.371612
3314 16:47:25.371692 Set Vref, RX VrefLevel [Byte0]: 43
3315 16:47:25.374664 [Byte1]: 43
3316 16:47:25.379183
3317 16:47:25.379264 Set Vref, RX VrefLevel [Byte0]: 44
3318 16:47:25.383163 [Byte1]: 44
3319 16:47:25.387571
3320 16:47:25.387652 Set Vref, RX VrefLevel [Byte0]: 45
3321 16:47:25.390395 [Byte1]: 45
3322 16:47:25.395058
3323 16:47:25.395164 Set Vref, RX VrefLevel [Byte0]: 46
3324 16:47:25.398308 [Byte1]: 46
3325 16:47:25.402908
3326 16:47:25.402988 Set Vref, RX VrefLevel [Byte0]: 47
3327 16:47:25.406175 [Byte1]: 47
3328 16:47:25.410748
3329 16:47:25.410827 Set Vref, RX VrefLevel [Byte0]: 48
3330 16:47:25.414247 [Byte1]: 48
3331 16:47:25.418738
3332 16:47:25.418818 Set Vref, RX VrefLevel [Byte0]: 49
3333 16:47:25.422092 [Byte1]: 49
3334 16:47:25.426650
3335 16:47:25.426729 Set Vref, RX VrefLevel [Byte0]: 50
3336 16:47:25.430075 [Byte1]: 50
3337 16:47:25.434347
3338 16:47:25.434426 Set Vref, RX VrefLevel [Byte0]: 51
3339 16:47:25.438050 [Byte1]: 51
3340 16:47:25.442688
3341 16:47:25.442771 Set Vref, RX VrefLevel [Byte0]: 52
3342 16:47:25.445845 [Byte1]: 52
3343 16:47:25.450224
3344 16:47:25.450303 Set Vref, RX VrefLevel [Byte0]: 53
3345 16:47:25.453786 [Byte1]: 53
3346 16:47:25.458614
3347 16:47:25.458694 Set Vref, RX VrefLevel [Byte0]: 54
3348 16:47:25.461584 [Byte1]: 54
3349 16:47:25.466301
3350 16:47:25.466382 Set Vref, RX VrefLevel [Byte0]: 55
3351 16:47:25.469541 [Byte1]: 55
3352 16:47:25.474020
3353 16:47:25.474099 Set Vref, RX VrefLevel [Byte0]: 56
3354 16:47:25.477601 [Byte1]: 56
3355 16:47:25.481727
3356 16:47:25.481807 Set Vref, RX VrefLevel [Byte0]: 57
3357 16:47:25.485019 [Byte1]: 57
3358 16:47:25.489589
3359 16:47:25.489670 Set Vref, RX VrefLevel [Byte0]: 58
3360 16:47:25.492864 [Byte1]: 58
3361 16:47:25.497493
3362 16:47:25.497575 Set Vref, RX VrefLevel [Byte0]: 59
3363 16:47:25.501106 [Byte1]: 59
3364 16:47:25.505725
3365 16:47:25.505805 Set Vref, RX VrefLevel [Byte0]: 60
3366 16:47:25.509055 [Byte1]: 60
3367 16:47:25.513645
3368 16:47:25.513725 Set Vref, RX VrefLevel [Byte0]: 61
3369 16:47:25.516720 [Byte1]: 61
3370 16:47:25.521506
3371 16:47:25.521589 Set Vref, RX VrefLevel [Byte0]: 62
3372 16:47:25.524472 [Byte1]: 62
3373 16:47:25.529568
3374 16:47:25.529649 Set Vref, RX VrefLevel [Byte0]: 63
3375 16:47:25.532339 [Byte1]: 63
3376 16:47:25.537223
3377 16:47:25.537307 Set Vref, RX VrefLevel [Byte0]: 64
3378 16:47:25.540241 [Byte1]: 64
3379 16:47:25.545095
3380 16:47:25.545176 Set Vref, RX VrefLevel [Byte0]: 65
3381 16:47:25.548146 [Byte1]: 65
3382 16:47:25.552737
3383 16:47:25.552820 Final RX Vref Byte 0 = 52 to rank0
3384 16:47:25.556050 Final RX Vref Byte 1 = 51 to rank0
3385 16:47:25.559679 Final RX Vref Byte 0 = 52 to rank1
3386 16:47:25.562635 Final RX Vref Byte 1 = 51 to rank1==
3387 16:47:25.566264 Dram Type= 6, Freq= 0, CH_1, rank 0
3388 16:47:25.572549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3389 16:47:25.572633 ==
3390 16:47:25.572698 DQS Delay:
3391 16:47:25.576083 DQS0 = 0, DQS1 = 0
3392 16:47:25.576164 DQM Delay:
3393 16:47:25.576227 DQM0 = 114, DQM1 = 112
3394 16:47:25.579322 DQ Delay:
3395 16:47:25.582275 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3396 16:47:25.585702 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3397 16:47:25.589532 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =106
3398 16:47:25.592446 DQ12 =120, DQ13 =120, DQ14 =118, DQ15 =120
3399 16:47:25.592545
3400 16:47:25.592612
3401 16:47:25.603029 [DQSOSCAuto] RK0, (LSB)MR18= 0xf3ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3402 16:47:25.603156 CH1 RK0: MR19=303, MR18=F3FF
3403 16:47:25.608999 CH1_RK0: MR19=0x303, MR18=0xF3FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3404 16:47:25.609085
3405 16:47:25.612552 ----->DramcWriteLeveling(PI) begin...
3406 16:47:25.612637 ==
3407 16:47:25.615853 Dram Type= 6, Freq= 0, CH_1, rank 1
3408 16:47:25.621888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 16:47:25.621978 ==
3410 16:47:25.625758 Write leveling (Byte 0): 25 => 25
3411 16:47:25.628907 Write leveling (Byte 1): 29 => 29
3412 16:47:25.628990 DramcWriteLeveling(PI) end<-----
3413 16:47:25.629055
3414 16:47:25.632009 ==
3415 16:47:25.635137 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 16:47:25.638915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 16:47:25.639007 ==
3418 16:47:25.642007 [Gating] SW mode calibration
3419 16:47:25.648284 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3420 16:47:25.651884 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3421 16:47:25.658534 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3422 16:47:25.662016 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3423 16:47:25.664937 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3424 16:47:25.671865 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3425 16:47:25.675061 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3426 16:47:25.678322 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3427 16:47:25.684888 0 15 24 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)
3428 16:47:25.688077 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3429 16:47:25.691706 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3430 16:47:25.698185 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3431 16:47:25.701522 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3432 16:47:25.704671 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3433 16:47:25.711515 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3434 16:47:25.714674 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
3435 16:47:25.718245 1 0 24 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
3436 16:47:25.724725 1 0 28 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
3437 16:47:25.728002 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3438 16:47:25.731305 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3439 16:47:25.737810 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3440 16:47:25.741320 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3441 16:47:25.745116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3442 16:47:25.751651 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3443 16:47:25.754244 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3444 16:47:25.757586 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3445 16:47:25.764265 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3446 16:47:25.767883 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3447 16:47:25.770900 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3448 16:47:25.777395 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3449 16:47:25.780464 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3450 16:47:25.783810 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3451 16:47:25.790205 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3452 16:47:25.793963 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3453 16:47:25.797135 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3454 16:47:25.803185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3455 16:47:25.806813 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 16:47:25.809981 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 16:47:25.816750 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 16:47:25.819773 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3459 16:47:25.823060 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3460 16:47:25.829826 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3461 16:47:25.832828 Total UI for P1: 0, mck2ui 16
3462 16:47:25.836324 best dqsien dly found for B0: ( 1, 3, 22)
3463 16:47:25.839615 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 16:47:25.843025 Total UI for P1: 0, mck2ui 16
3465 16:47:25.846257 best dqsien dly found for B1: ( 1, 3, 28)
3466 16:47:25.849483 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3467 16:47:25.853237 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3468 16:47:25.853320
3469 16:47:25.855979 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3470 16:47:25.863064 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3471 16:47:25.863149 [Gating] SW calibration Done
3472 16:47:25.863258 ==
3473 16:47:25.865896 Dram Type= 6, Freq= 0, CH_1, rank 1
3474 16:47:25.872695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 16:47:25.872780 ==
3476 16:47:25.872845 RX Vref Scan: 0
3477 16:47:25.872905
3478 16:47:25.875814 RX Vref 0 -> 0, step: 1
3479 16:47:25.875896
3480 16:47:25.879300 RX Delay -40 -> 252, step: 8
3481 16:47:25.882305 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3482 16:47:25.885634 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3483 16:47:25.889125 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3484 16:47:25.895867 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3485 16:47:25.898993 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3486 16:47:25.902284 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3487 16:47:25.905885 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3488 16:47:25.908613 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3489 16:47:25.915426 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3490 16:47:25.919295 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3491 16:47:25.921784 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3492 16:47:25.924946 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3493 16:47:25.928720 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3494 16:47:25.935103 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3495 16:47:25.938768 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3496 16:47:25.941472 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3497 16:47:25.941557 ==
3498 16:47:25.944934 Dram Type= 6, Freq= 0, CH_1, rank 1
3499 16:47:25.948522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3500 16:47:25.951377 ==
3501 16:47:25.951461 DQS Delay:
3502 16:47:25.951526 DQS0 = 0, DQS1 = 0
3503 16:47:25.954755 DQM Delay:
3504 16:47:25.954836 DQM0 = 115, DQM1 = 111
3505 16:47:25.958203 DQ Delay:
3506 16:47:25.961626 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3507 16:47:25.964891 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3508 16:47:25.967858 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3509 16:47:25.971156 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3510 16:47:25.971247
3511 16:47:25.971312
3512 16:47:25.971371 ==
3513 16:47:25.974663 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 16:47:25.977828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 16:47:25.977913 ==
3516 16:47:25.981560
3517 16:47:25.981643
3518 16:47:25.981707 TX Vref Scan disable
3519 16:47:25.984986 == TX Byte 0 ==
3520 16:47:25.988347 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3521 16:47:25.990976 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3522 16:47:25.994923 == TX Byte 1 ==
3523 16:47:25.997787 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3524 16:47:26.001184 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3525 16:47:26.004768 ==
3526 16:47:26.004852 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 16:47:26.010750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 16:47:26.010836 ==
3529 16:47:26.021925 TX Vref=22, minBit 2, minWin=25, winSum=415
3530 16:47:26.025772 TX Vref=24, minBit 9, minWin=25, winSum=424
3531 16:47:26.028668 TX Vref=26, minBit 3, minWin=25, winSum=429
3532 16:47:26.031766 TX Vref=28, minBit 7, minWin=26, winSum=429
3533 16:47:26.035333 TX Vref=30, minBit 9, minWin=26, winSum=433
3534 16:47:26.041432 TX Vref=32, minBit 9, minWin=26, winSum=432
3535 16:47:26.045006 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 30
3536 16:47:26.045093
3537 16:47:26.048293 Final TX Range 1 Vref 30
3538 16:47:26.048377
3539 16:47:26.048442 ==
3540 16:47:26.051154 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 16:47:26.054718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 16:47:26.058142 ==
3543 16:47:26.058225
3544 16:47:26.058289
3545 16:47:26.058347 TX Vref Scan disable
3546 16:47:26.061689 == TX Byte 0 ==
3547 16:47:26.064824 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3548 16:47:26.071557 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3549 16:47:26.071677 == TX Byte 1 ==
3550 16:47:26.075137 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3551 16:47:26.081221 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3552 16:47:26.081305
3553 16:47:26.081370 [DATLAT]
3554 16:47:26.081430 Freq=1200, CH1 RK1
3555 16:47:26.081488
3556 16:47:26.084722 DATLAT Default: 0xd
3557 16:47:26.088125 0, 0xFFFF, sum = 0
3558 16:47:26.088209 1, 0xFFFF, sum = 0
3559 16:47:26.091220 2, 0xFFFF, sum = 0
3560 16:47:26.091303 3, 0xFFFF, sum = 0
3561 16:47:26.094464 4, 0xFFFF, sum = 0
3562 16:47:26.094548 5, 0xFFFF, sum = 0
3563 16:47:26.097971 6, 0xFFFF, sum = 0
3564 16:47:26.098054 7, 0xFFFF, sum = 0
3565 16:47:26.101128 8, 0xFFFF, sum = 0
3566 16:47:26.101212 9, 0xFFFF, sum = 0
3567 16:47:26.104768 10, 0xFFFF, sum = 0
3568 16:47:26.104851 11, 0xFFFF, sum = 0
3569 16:47:26.107732 12, 0x0, sum = 1
3570 16:47:26.107815 13, 0x0, sum = 2
3571 16:47:26.110962 14, 0x0, sum = 3
3572 16:47:26.111044 15, 0x0, sum = 4
3573 16:47:26.114186 best_step = 13
3574 16:47:26.114267
3575 16:47:26.114330 ==
3576 16:47:26.117887 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 16:47:26.121011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 16:47:26.121094 ==
3579 16:47:26.124463 RX Vref Scan: 0
3580 16:47:26.124545
3581 16:47:26.124609 RX Vref 0 -> 0, step: 1
3582 16:47:26.124669
3583 16:47:26.127571 RX Delay -13 -> 252, step: 4
3584 16:47:26.134045 iDelay=195, Bit 0, Center 116 (47 ~ 186) 140
3585 16:47:26.137323 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3586 16:47:26.140591 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3587 16:47:26.144011 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3588 16:47:26.147161 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3589 16:47:26.153605 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3590 16:47:26.156873 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3591 16:47:26.160481 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3592 16:47:26.163735 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3593 16:47:26.170807 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3594 16:47:26.173237 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3595 16:47:26.177176 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3596 16:47:26.180512 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3597 16:47:26.183630 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3598 16:47:26.189802 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3599 16:47:26.193313 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3600 16:47:26.193397 ==
3601 16:47:26.196888 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 16:47:26.199846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 16:47:26.199931 ==
3604 16:47:26.203383 DQS Delay:
3605 16:47:26.203467 DQS0 = 0, DQS1 = 0
3606 16:47:26.203531 DQM Delay:
3607 16:47:26.206312 DQM0 = 114, DQM1 = 111
3608 16:47:26.206394 DQ Delay:
3609 16:47:26.210357 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =114
3610 16:47:26.213101 DQ4 =116, DQ5 =122, DQ6 =120, DQ7 =112
3611 16:47:26.219354 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3612 16:47:26.222800 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3613 16:47:26.222884
3614 16:47:26.222949
3615 16:47:26.230047 [DQSOSCAuto] RK1, (LSB)MR18= 0xf305, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3616 16:47:26.233073 CH1 RK1: MR19=304, MR18=F305
3617 16:47:26.239318 CH1_RK1: MR19=0x304, MR18=0xF305, DQSOSC=408, MR23=63, INC=39, DEC=26
3618 16:47:26.242523 [RxdqsGatingPostProcess] freq 1200
3619 16:47:26.248894 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3620 16:47:26.252203 best DQS0 dly(2T, 0.5T) = (0, 11)
3621 16:47:26.252289 best DQS1 dly(2T, 0.5T) = (0, 11)
3622 16:47:26.255682 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3623 16:47:26.259146 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3624 16:47:26.261923 best DQS0 dly(2T, 0.5T) = (0, 11)
3625 16:47:26.265217 best DQS1 dly(2T, 0.5T) = (0, 11)
3626 16:47:26.268801 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3627 16:47:26.272645 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3628 16:47:26.276060 Pre-setting of DQS Precalculation
3629 16:47:26.281794 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3630 16:47:26.288536 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3631 16:47:26.295569 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3632 16:47:26.295657
3633 16:47:26.295723
3634 16:47:26.298830 [Calibration Summary] 2400 Mbps
3635 16:47:26.298914 CH 0, Rank 0
3636 16:47:26.301834 SW Impedance : PASS
3637 16:47:26.304789 DUTY Scan : NO K
3638 16:47:26.304898 ZQ Calibration : PASS
3639 16:47:26.308093 Jitter Meter : NO K
3640 16:47:26.311899 CBT Training : PASS
3641 16:47:26.311985 Write leveling : PASS
3642 16:47:26.314766 RX DQS gating : PASS
3643 16:47:26.318359 RX DQ/DQS(RDDQC) : PASS
3644 16:47:26.318445 TX DQ/DQS : PASS
3645 16:47:26.321561 RX DATLAT : PASS
3646 16:47:26.325150 RX DQ/DQS(Engine): PASS
3647 16:47:26.325260 TX OE : NO K
3648 16:47:26.328408 All Pass.
3649 16:47:26.328494
3650 16:47:26.328578 CH 0, Rank 1
3651 16:47:26.331529 SW Impedance : PASS
3652 16:47:26.331638 DUTY Scan : NO K
3653 16:47:26.335649 ZQ Calibration : PASS
3654 16:47:26.338325 Jitter Meter : NO K
3655 16:47:26.338439 CBT Training : PASS
3656 16:47:26.341475 Write leveling : PASS
3657 16:47:26.344341 RX DQS gating : PASS
3658 16:47:26.344428 RX DQ/DQS(RDDQC) : PASS
3659 16:47:26.347698 TX DQ/DQS : PASS
3660 16:47:26.351230 RX DATLAT : PASS
3661 16:47:26.351316 RX DQ/DQS(Engine): PASS
3662 16:47:26.354234 TX OE : NO K
3663 16:47:26.354319 All Pass.
3664 16:47:26.354402
3665 16:47:26.357661 CH 1, Rank 0
3666 16:47:26.357749 SW Impedance : PASS
3667 16:47:26.361299 DUTY Scan : NO K
3668 16:47:26.364243 ZQ Calibration : PASS
3669 16:47:26.364328 Jitter Meter : NO K
3670 16:47:26.367339 CBT Training : PASS
3671 16:47:26.367425 Write leveling : PASS
3672 16:47:26.370678 RX DQS gating : PASS
3673 16:47:26.373952 RX DQ/DQS(RDDQC) : PASS
3674 16:47:26.374037 TX DQ/DQS : PASS
3675 16:47:26.377489 RX DATLAT : PASS
3676 16:47:26.380656 RX DQ/DQS(Engine): PASS
3677 16:47:26.380742 TX OE : NO K
3678 16:47:26.383934 All Pass.
3679 16:47:26.384021
3680 16:47:26.384106 CH 1, Rank 1
3681 16:47:26.387149 SW Impedance : PASS
3682 16:47:26.387274 DUTY Scan : NO K
3683 16:47:26.390201 ZQ Calibration : PASS
3684 16:47:26.393722 Jitter Meter : NO K
3685 16:47:26.393833 CBT Training : PASS
3686 16:47:26.397012 Write leveling : PASS
3687 16:47:26.400329 RX DQS gating : PASS
3688 16:47:26.400426 RX DQ/DQS(RDDQC) : PASS
3689 16:47:26.404121 TX DQ/DQS : PASS
3690 16:47:26.407027 RX DATLAT : PASS
3691 16:47:26.407138 RX DQ/DQS(Engine): PASS
3692 16:47:26.410015 TX OE : NO K
3693 16:47:26.410101 All Pass.
3694 16:47:26.410186
3695 16:47:26.413648 DramC Write-DBI off
3696 16:47:26.416669 PER_BANK_REFRESH: Hybrid Mode
3697 16:47:26.416756 TX_TRACKING: ON
3698 16:47:26.426259 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3699 16:47:26.429551 [FAST_K] Save calibration result to emmc
3700 16:47:26.433479 dramc_set_vcore_voltage set vcore to 650000
3701 16:47:26.436318 Read voltage for 600, 5
3702 16:47:26.436406 Vio18 = 0
3703 16:47:26.439689 Vcore = 650000
3704 16:47:26.439777 Vdram = 0
3705 16:47:26.439862 Vddq = 0
3706 16:47:26.439942 Vmddr = 0
3707 16:47:26.446184 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3708 16:47:26.452835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3709 16:47:26.452929 MEM_TYPE=3, freq_sel=19
3710 16:47:26.455893 sv_algorithm_assistance_LP4_1600
3711 16:47:26.459292 ============ PULL DRAM RESETB DOWN ============
3712 16:47:26.466305 ========== PULL DRAM RESETB DOWN end =========
3713 16:47:26.469480 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3714 16:47:26.472394 ===================================
3715 16:47:26.476036 LPDDR4 DRAM CONFIGURATION
3716 16:47:26.478964 ===================================
3717 16:47:26.479048 EX_ROW_EN[0] = 0x0
3718 16:47:26.482645 EX_ROW_EN[1] = 0x0
3719 16:47:26.485969 LP4Y_EN = 0x0
3720 16:47:26.486051 WORK_FSP = 0x0
3721 16:47:26.489106 WL = 0x2
3722 16:47:26.489189 RL = 0x2
3723 16:47:26.492638 BL = 0x2
3724 16:47:26.492720 RPST = 0x0
3725 16:47:26.495777 RD_PRE = 0x0
3726 16:47:26.495859 WR_PRE = 0x1
3727 16:47:26.498923 WR_PST = 0x0
3728 16:47:26.499004 DBI_WR = 0x0
3729 16:47:26.502343 DBI_RD = 0x0
3730 16:47:26.502424 OTF = 0x1
3731 16:47:26.505411 ===================================
3732 16:47:26.508654 ===================================
3733 16:47:26.512632 ANA top config
3734 16:47:26.515607 ===================================
3735 16:47:26.515715 DLL_ASYNC_EN = 0
3736 16:47:26.518441 ALL_SLAVE_EN = 1
3737 16:47:26.521845 NEW_RANK_MODE = 1
3738 16:47:26.525333 DLL_IDLE_MODE = 1
3739 16:47:26.528637 LP45_APHY_COMB_EN = 1
3740 16:47:26.528719 TX_ODT_DIS = 1
3741 16:47:26.531561 NEW_8X_MODE = 1
3742 16:47:26.535081 ===================================
3743 16:47:26.538906 ===================================
3744 16:47:26.541748 data_rate = 1200
3745 16:47:26.544863 CKR = 1
3746 16:47:26.548246 DQ_P2S_RATIO = 8
3747 16:47:26.551484 ===================================
3748 16:47:26.554781 CA_P2S_RATIO = 8
3749 16:47:26.554889 DQ_CA_OPEN = 0
3750 16:47:26.558154 DQ_SEMI_OPEN = 0
3751 16:47:26.561850 CA_SEMI_OPEN = 0
3752 16:47:26.564617 CA_FULL_RATE = 0
3753 16:47:26.568359 DQ_CKDIV4_EN = 1
3754 16:47:26.571476 CA_CKDIV4_EN = 1
3755 16:47:26.571557 CA_PREDIV_EN = 0
3756 16:47:26.574694 PH8_DLY = 0
3757 16:47:26.577937 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3758 16:47:26.581003 DQ_AAMCK_DIV = 4
3759 16:47:26.584484 CA_AAMCK_DIV = 4
3760 16:47:26.587830 CA_ADMCK_DIV = 4
3761 16:47:26.587913 DQ_TRACK_CA_EN = 0
3762 16:47:26.591131 CA_PICK = 600
3763 16:47:26.594280 CA_MCKIO = 600
3764 16:47:26.597637 MCKIO_SEMI = 0
3765 16:47:26.601121 PLL_FREQ = 2288
3766 16:47:26.604666 DQ_UI_PI_RATIO = 32
3767 16:47:26.607422 CA_UI_PI_RATIO = 0
3768 16:47:26.610922 ===================================
3769 16:47:26.614052 ===================================
3770 16:47:26.614134 memory_type:LPDDR4
3771 16:47:26.617977 GP_NUM : 10
3772 16:47:26.620626 SRAM_EN : 1
3773 16:47:26.620707 MD32_EN : 0
3774 16:47:26.624040 ===================================
3775 16:47:26.627600 [ANA_INIT] >>>>>>>>>>>>>>
3776 16:47:26.630674 <<<<<< [CONFIGURE PHASE]: ANA_TX
3777 16:47:26.633794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3778 16:47:26.637177 ===================================
3779 16:47:26.640264 data_rate = 1200,PCW = 0X5800
3780 16:47:26.643796 ===================================
3781 16:47:26.646982 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3782 16:47:26.650940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3783 16:47:26.656765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3784 16:47:26.663201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3785 16:47:26.666765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3786 16:47:26.669737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3787 16:47:26.669819 [ANA_INIT] flow start
3788 16:47:26.673560 [ANA_INIT] PLL >>>>>>>>
3789 16:47:26.676506 [ANA_INIT] PLL <<<<<<<<
3790 16:47:26.676587 [ANA_INIT] MIDPI >>>>>>>>
3791 16:47:26.679799 [ANA_INIT] MIDPI <<<<<<<<
3792 16:47:26.682900 [ANA_INIT] DLL >>>>>>>>
3793 16:47:26.682981 [ANA_INIT] flow end
3794 16:47:26.689644 ============ LP4 DIFF to SE enter ============
3795 16:47:26.693936 ============ LP4 DIFF to SE exit ============
3796 16:47:26.696415 [ANA_INIT] <<<<<<<<<<<<<
3797 16:47:26.699580 [Flow] Enable top DCM control >>>>>
3798 16:47:26.702835 [Flow] Enable top DCM control <<<<<
3799 16:47:26.702916 Enable DLL master slave shuffle
3800 16:47:26.709324 ==============================================================
3801 16:47:26.712536 Gating Mode config
3802 16:47:26.715889 ==============================================================
3803 16:47:26.718954 Config description:
3804 16:47:26.729690 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3805 16:47:26.735967 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3806 16:47:26.738787 SELPH_MODE 0: By rank 1: By Phase
3807 16:47:26.745699 ==============================================================
3808 16:47:26.749215 GAT_TRACK_EN = 1
3809 16:47:26.751921 RX_GATING_MODE = 2
3810 16:47:26.755576 RX_GATING_TRACK_MODE = 2
3811 16:47:26.758667 SELPH_MODE = 1
3812 16:47:26.761706 PICG_EARLY_EN = 1
3813 16:47:26.765024 VALID_LAT_VALUE = 1
3814 16:47:26.768649 ==============================================================
3815 16:47:26.771745 Enter into Gating configuration >>>>
3816 16:47:26.775092 Exit from Gating configuration <<<<
3817 16:47:26.778659 Enter into DVFS_PRE_config >>>>>
3818 16:47:26.791613 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3819 16:47:26.794997 Exit from DVFS_PRE_config <<<<<
3820 16:47:26.795081 Enter into PICG configuration >>>>
3821 16:47:26.798094 Exit from PICG configuration <<<<
3822 16:47:26.802005 [RX_INPUT] configuration >>>>>
3823 16:47:26.805054 [RX_INPUT] configuration <<<<<
3824 16:47:26.811174 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3825 16:47:26.814908 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3826 16:47:26.820650 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3827 16:47:26.827782 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3828 16:47:26.833780 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3829 16:47:26.840388 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3830 16:47:26.843854 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3831 16:47:26.847855 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3832 16:47:26.853601 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3833 16:47:26.856896 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3834 16:47:26.860572 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3835 16:47:26.866768 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3836 16:47:26.870508 ===================================
3837 16:47:26.870591 LPDDR4 DRAM CONFIGURATION
3838 16:47:26.873228 ===================================
3839 16:47:26.878583 EX_ROW_EN[0] = 0x0
3840 16:47:26.878666 EX_ROW_EN[1] = 0x0
3841 16:47:26.879958 LP4Y_EN = 0x0
3842 16:47:26.880040 WORK_FSP = 0x0
3843 16:47:26.883329 WL = 0x2
3844 16:47:26.886776 RL = 0x2
3845 16:47:26.886905 BL = 0x2
3846 16:47:26.890051 RPST = 0x0
3847 16:47:26.890158 RD_PRE = 0x0
3848 16:47:26.893309 WR_PRE = 0x1
3849 16:47:26.893390 WR_PST = 0x0
3850 16:47:26.896844 DBI_WR = 0x0
3851 16:47:26.896951 DBI_RD = 0x0
3852 16:47:26.899917 OTF = 0x1
3853 16:47:26.903842 ===================================
3854 16:47:26.906815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3855 16:47:26.909643 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3856 16:47:26.916282 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3857 16:47:26.920043 ===================================
3858 16:47:26.920125 LPDDR4 DRAM CONFIGURATION
3859 16:47:26.923293 ===================================
3860 16:47:26.926095 EX_ROW_EN[0] = 0x10
3861 16:47:26.926208 EX_ROW_EN[1] = 0x0
3862 16:47:26.929758 LP4Y_EN = 0x0
3863 16:47:26.932755 WORK_FSP = 0x0
3864 16:47:26.932836 WL = 0x2
3865 16:47:26.936052 RL = 0x2
3866 16:47:26.936134 BL = 0x2
3867 16:47:26.939396 RPST = 0x0
3868 16:47:26.939478 RD_PRE = 0x0
3869 16:47:26.942847 WR_PRE = 0x1
3870 16:47:26.942928 WR_PST = 0x0
3871 16:47:26.945630 DBI_WR = 0x0
3872 16:47:26.945711 DBI_RD = 0x0
3873 16:47:26.949627 OTF = 0x1
3874 16:47:26.952590 ===================================
3875 16:47:26.958993 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3876 16:47:26.962600 nWR fixed to 30
3877 16:47:26.962686 [ModeRegInit_LP4] CH0 RK0
3878 16:47:26.965758 [ModeRegInit_LP4] CH0 RK1
3879 16:47:26.969693 [ModeRegInit_LP4] CH1 RK0
3880 16:47:26.972125 [ModeRegInit_LP4] CH1 RK1
3881 16:47:26.972207 match AC timing 17
3882 16:47:26.978732 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3883 16:47:26.982136 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3884 16:47:26.985445 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3885 16:47:26.992453 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3886 16:47:26.995229 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3887 16:47:26.995381 ==
3888 16:47:26.999068 Dram Type= 6, Freq= 0, CH_0, rank 0
3889 16:47:27.002238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3890 16:47:27.002387 ==
3891 16:47:27.008786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3892 16:47:27.015244 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3893 16:47:27.018924 [CA 0] Center 36 (6~67) winsize 62
3894 16:47:27.022298 [CA 1] Center 36 (5~67) winsize 63
3895 16:47:27.025168 [CA 2] Center 34 (4~65) winsize 62
3896 16:47:27.028187 [CA 3] Center 34 (4~65) winsize 62
3897 16:47:27.031776 [CA 4] Center 33 (3~64) winsize 62
3898 16:47:27.035096 [CA 5] Center 33 (3~64) winsize 62
3899 16:47:27.035227
3900 16:47:27.038401 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3901 16:47:27.038517
3902 16:47:27.041783 [CATrainingPosCal] consider 1 rank data
3903 16:47:27.044866 u2DelayCellTimex100 = 270/100 ps
3904 16:47:27.048419 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3905 16:47:27.051476 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3906 16:47:27.055084 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3907 16:47:27.058950 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3908 16:47:27.061929 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3909 16:47:27.068883 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3910 16:47:27.069350
3911 16:47:27.072070 CA PerBit enable=1, Macro0, CA PI delay=33
3912 16:47:27.072426
3913 16:47:27.074928 [CBTSetCACLKResult] CA Dly = 33
3914 16:47:27.075422 CS Dly: 4 (0~35)
3915 16:47:27.075722 ==
3916 16:47:27.078829 Dram Type= 6, Freq= 0, CH_0, rank 1
3917 16:47:27.081072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 16:47:27.084568 ==
3919 16:47:27.088354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 16:47:27.093958 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3921 16:47:27.097488 [CA 0] Center 36 (6~67) winsize 62
3922 16:47:27.100511 [CA 1] Center 36 (6~67) winsize 62
3923 16:47:27.105007 [CA 2] Center 34 (4~65) winsize 62
3924 16:47:27.107323 [CA 3] Center 34 (4~65) winsize 62
3925 16:47:27.110629 [CA 4] Center 34 (4~65) winsize 62
3926 16:47:27.113859 [CA 5] Center 33 (3~64) winsize 62
3927 16:47:27.113956
3928 16:47:27.116855 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3929 16:47:27.116945
3930 16:47:27.120134 [CATrainingPosCal] consider 2 rank data
3931 16:47:27.123531 u2DelayCellTimex100 = 270/100 ps
3932 16:47:27.126623 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3933 16:47:27.133543 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3934 16:47:27.136955 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3935 16:47:27.140438 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3936 16:47:27.143276 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3937 16:47:27.147071 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3938 16:47:27.147194
3939 16:47:27.150052 CA PerBit enable=1, Macro0, CA PI delay=33
3940 16:47:27.150136
3941 16:47:27.152833 [CBTSetCACLKResult] CA Dly = 33
3942 16:47:27.156444 CS Dly: 5 (0~38)
3943 16:47:27.156528
3944 16:47:27.159467 ----->DramcWriteLeveling(PI) begin...
3945 16:47:27.159551 ==
3946 16:47:27.163004 Dram Type= 6, Freq= 0, CH_0, rank 0
3947 16:47:27.165989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3948 16:47:27.166073 ==
3949 16:47:27.169512 Write leveling (Byte 0): 34 => 34
3950 16:47:27.172513 Write leveling (Byte 1): 30 => 30
3951 16:47:27.176795 DramcWriteLeveling(PI) end<-----
3952 16:47:27.176877
3953 16:47:27.176940 ==
3954 16:47:27.179308 Dram Type= 6, Freq= 0, CH_0, rank 0
3955 16:47:27.182642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 16:47:27.182724 ==
3957 16:47:27.185965 [Gating] SW mode calibration
3958 16:47:27.192539 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3959 16:47:27.198984 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3960 16:47:27.202203 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3961 16:47:27.205397 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3962 16:47:27.211993 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3963 16:47:27.215297 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (0 0) (0 1)
3964 16:47:27.222159 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (1 0) (0 0)
3965 16:47:27.225202 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3966 16:47:27.228472 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3967 16:47:27.235212 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3968 16:47:27.238357 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3969 16:47:27.242472 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3970 16:47:27.248026 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3971 16:47:27.251628 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3972 16:47:27.254689 0 10 16 | B1->B0 | 3939 4545 | 0 0 | (1 1) (0 0)
3973 16:47:27.261406 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3974 16:47:27.265332 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3975 16:47:27.268338 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3976 16:47:27.274961 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3977 16:47:27.277760 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3978 16:47:27.281015 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3979 16:47:27.287842 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3980 16:47:27.290986 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3981 16:47:27.294441 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3982 16:47:27.300802 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3983 16:47:27.304412 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3984 16:47:27.307490 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3985 16:47:27.314078 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3986 16:47:27.317354 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3987 16:47:27.320511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3988 16:47:27.327405 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3989 16:47:27.330840 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3990 16:47:27.333951 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3991 16:47:27.341416 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 16:47:27.343426 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 16:47:27.347274 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 16:47:27.353882 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 16:47:27.356809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 16:47:27.359954 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3997 16:47:27.363411 Total UI for P1: 0, mck2ui 16
3998 16:47:27.366727 best dqsien dly found for B0: ( 0, 13, 14)
3999 16:47:27.372886 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 16:47:27.372983 Total UI for P1: 0, mck2ui 16
4001 16:47:27.379568 best dqsien dly found for B1: ( 0, 13, 16)
4002 16:47:27.383291 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4003 16:47:27.386152 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4004 16:47:27.386235
4005 16:47:27.389570 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4006 16:47:27.392984 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4007 16:47:27.396002 [Gating] SW calibration Done
4008 16:47:27.396084 ==
4009 16:47:27.399920 Dram Type= 6, Freq= 0, CH_0, rank 0
4010 16:47:27.402731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4011 16:47:27.402815 ==
4012 16:47:27.406146 RX Vref Scan: 0
4013 16:47:27.406229
4014 16:47:27.410085 RX Vref 0 -> 0, step: 1
4015 16:47:27.410170
4016 16:47:27.410235 RX Delay -230 -> 252, step: 16
4017 16:47:27.416192 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4018 16:47:27.419044 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4019 16:47:27.422110 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4020 16:47:27.425711 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4021 16:47:27.432371 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4022 16:47:27.435765 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4023 16:47:27.439015 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4024 16:47:27.442573 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4025 16:47:27.449021 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4026 16:47:27.452160 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4027 16:47:27.455901 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4028 16:47:27.458939 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4029 16:47:27.465461 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4030 16:47:27.469297 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4031 16:47:27.472069 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4032 16:47:27.475134 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4033 16:47:27.475269 ==
4034 16:47:27.478732 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 16:47:27.485262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 16:47:27.485449 ==
4037 16:47:27.485545 DQS Delay:
4038 16:47:27.488384 DQS0 = 0, DQS1 = 0
4039 16:47:27.488587 DQM Delay:
4040 16:47:27.488690 DQM0 = 46, DQM1 = 36
4041 16:47:27.491867 DQ Delay:
4042 16:47:27.495015 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4043 16:47:27.498298 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4044 16:47:27.501974 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4045 16:47:27.505247 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4046 16:47:27.505503
4047 16:47:27.505648
4048 16:47:27.505781 ==
4049 16:47:27.508518 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 16:47:27.511879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 16:47:27.512080 ==
4052 16:47:27.512239
4053 16:47:27.512385
4054 16:47:27.515265 TX Vref Scan disable
4055 16:47:27.518153 == TX Byte 0 ==
4056 16:47:27.521958 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4057 16:47:27.525131 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4058 16:47:27.528198 == TX Byte 1 ==
4059 16:47:27.531664 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4060 16:47:27.535153 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4061 16:47:27.535664 ==
4062 16:47:27.538342 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 16:47:27.541565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 16:47:27.544606 ==
4065 16:47:27.544957
4066 16:47:27.545232
4067 16:47:27.545544 TX Vref Scan disable
4068 16:47:27.548625 == TX Byte 0 ==
4069 16:47:27.552319 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4070 16:47:27.558684 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4071 16:47:27.559055 == TX Byte 1 ==
4072 16:47:27.562367 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4073 16:47:27.568398 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4074 16:47:27.568839
4075 16:47:27.569230 [DATLAT]
4076 16:47:27.569606 Freq=600, CH0 RK0
4077 16:47:27.569976
4078 16:47:27.572069 DATLAT Default: 0x9
4079 16:47:27.572424 0, 0xFFFF, sum = 0
4080 16:47:27.575128 1, 0xFFFF, sum = 0
4081 16:47:27.578273 2, 0xFFFF, sum = 0
4082 16:47:27.578627 3, 0xFFFF, sum = 0
4083 16:47:27.581856 4, 0xFFFF, sum = 0
4084 16:47:27.582218 5, 0xFFFF, sum = 0
4085 16:47:27.585571 6, 0xFFFF, sum = 0
4086 16:47:27.585752 7, 0xFFFF, sum = 0
4087 16:47:27.588338 8, 0x0, sum = 1
4088 16:47:27.588427 9, 0x0, sum = 2
4089 16:47:27.591566 10, 0x0, sum = 3
4090 16:47:27.591654 11, 0x0, sum = 4
4091 16:47:27.591723 best_step = 9
4092 16:47:27.591788
4093 16:47:27.594897 ==
4094 16:47:27.594990 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 16:47:27.601692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 16:47:27.601878 ==
4097 16:47:27.601981 RX Vref Scan: 1
4098 16:47:27.602063
4099 16:47:27.604911 RX Vref 0 -> 0, step: 1
4100 16:47:27.605099
4101 16:47:27.608331 RX Delay -179 -> 252, step: 8
4102 16:47:27.608532
4103 16:47:27.611005 Set Vref, RX VrefLevel [Byte0]: 58
4104 16:47:27.614300 [Byte1]: 49
4105 16:47:27.614481
4106 16:47:27.617983 Final RX Vref Byte 0 = 58 to rank0
4107 16:47:27.621417 Final RX Vref Byte 1 = 49 to rank0
4108 16:47:27.624409 Final RX Vref Byte 0 = 58 to rank1
4109 16:47:27.627670 Final RX Vref Byte 1 = 49 to rank1==
4110 16:47:27.631261 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 16:47:27.634299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 16:47:27.637596 ==
4113 16:47:27.637989 DQS Delay:
4114 16:47:27.638231 DQS0 = 0, DQS1 = 0
4115 16:47:27.641118 DQM Delay:
4116 16:47:27.641497 DQM0 = 44, DQM1 = 37
4117 16:47:27.644224 DQ Delay:
4118 16:47:27.647269 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4119 16:47:27.650958 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4120 16:47:27.654178 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =32
4121 16:47:27.657425 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4122 16:47:27.657887
4123 16:47:27.658172
4124 16:47:27.663724 [DQSOSCAuto] RK0, (LSB)MR18= 0x433a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4125 16:47:27.667302 CH0 RK0: MR19=808, MR18=433A
4126 16:47:27.674850 CH0_RK0: MR19=0x808, MR18=0x433A, DQSOSC=397, MR23=63, INC=166, DEC=110
4127 16:47:27.675364
4128 16:47:27.677097 ----->DramcWriteLeveling(PI) begin...
4129 16:47:27.677457 ==
4130 16:47:27.680274 Dram Type= 6, Freq= 0, CH_0, rank 1
4131 16:47:27.684005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 16:47:27.684360 ==
4133 16:47:27.686892 Write leveling (Byte 0): 32 => 32
4134 16:47:27.690254 Write leveling (Byte 1): 29 => 29
4135 16:47:27.693534 DramcWriteLeveling(PI) end<-----
4136 16:47:27.693994
4137 16:47:27.694278 ==
4138 16:47:27.696622 Dram Type= 6, Freq= 0, CH_0, rank 1
4139 16:47:27.700261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 16:47:27.703270 ==
4141 16:47:27.703754 [Gating] SW mode calibration
4142 16:47:27.713197 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4143 16:47:27.716834 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4144 16:47:27.719782 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4145 16:47:27.726521 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4146 16:47:27.730187 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4147 16:47:27.733686 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
4148 16:47:27.739867 0 9 16 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
4149 16:47:27.743044 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4150 16:47:27.747153 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4151 16:47:27.752890 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4152 16:47:27.755898 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4153 16:47:27.759690 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4154 16:47:27.765948 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4155 16:47:27.769617 0 10 12 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
4156 16:47:27.772359 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4157 16:47:27.779323 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4158 16:47:27.782418 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4159 16:47:27.785675 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4160 16:47:27.792291 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4161 16:47:27.795937 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4162 16:47:27.798604 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4163 16:47:27.805486 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4164 16:47:27.808964 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4165 16:47:27.811807 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4166 16:47:27.819057 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4167 16:47:27.821979 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4168 16:47:27.825634 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4169 16:47:27.831699 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4170 16:47:27.835336 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4171 16:47:27.838227 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4172 16:47:27.844976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4173 16:47:27.848212 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4174 16:47:27.851704 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4175 16:47:27.858131 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 16:47:27.861223 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 16:47:27.864344 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 16:47:27.871331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 16:47:27.874630 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4180 16:47:27.877441 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4181 16:47:27.880768 Total UI for P1: 0, mck2ui 16
4182 16:47:27.884787 best dqsien dly found for B0: ( 0, 13, 12)
4183 16:47:27.891133 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 16:47:27.894018 Total UI for P1: 0, mck2ui 16
4185 16:47:27.897769 best dqsien dly found for B1: ( 0, 13, 16)
4186 16:47:27.900768 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4187 16:47:27.904106 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4188 16:47:27.904497
4189 16:47:27.907757 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4190 16:47:27.910863 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4191 16:47:27.913827 [Gating] SW calibration Done
4192 16:47:27.914341 ==
4193 16:47:27.917387 Dram Type= 6, Freq= 0, CH_0, rank 1
4194 16:47:27.920409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 16:47:27.923992 ==
4196 16:47:27.924384 RX Vref Scan: 0
4197 16:47:27.924692
4198 16:47:27.927508 RX Vref 0 -> 0, step: 1
4199 16:47:27.927919
4200 16:47:27.930268 RX Delay -230 -> 252, step: 16
4201 16:47:27.934041 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4202 16:47:27.937313 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4203 16:47:27.940238 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4204 16:47:27.946852 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4205 16:47:27.949971 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4206 16:47:27.953241 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4207 16:47:27.956893 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4208 16:47:27.963512 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4209 16:47:27.966333 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4210 16:47:27.969619 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4211 16:47:27.972845 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4212 16:47:27.976338 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4213 16:47:27.983236 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4214 16:47:27.986052 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4215 16:47:27.989567 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4216 16:47:27.995858 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4217 16:47:27.996330 ==
4218 16:47:27.999342 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 16:47:28.002321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 16:47:28.002807 ==
4221 16:47:28.003122 DQS Delay:
4222 16:47:28.005799 DQS0 = 0, DQS1 = 0
4223 16:47:28.006189 DQM Delay:
4224 16:47:28.009843 DQM0 = 46, DQM1 = 36
4225 16:47:28.010333 DQ Delay:
4226 16:47:28.012443 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4227 16:47:28.015730 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4228 16:47:28.018692 DQ8 =33, DQ9 =17, DQ10 =41, DQ11 =33
4229 16:47:28.022426 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4230 16:47:28.022808
4231 16:47:28.023108
4232 16:47:28.023417 ==
4233 16:47:28.026084 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 16:47:28.028531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 16:47:28.028918 ==
4236 16:47:28.032071
4237 16:47:28.032452
4238 16:47:28.032752 TX Vref Scan disable
4239 16:47:28.035219 == TX Byte 0 ==
4240 16:47:28.039215 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4241 16:47:28.042131 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4242 16:47:28.045437 == TX Byte 1 ==
4243 16:47:28.048602 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4244 16:47:28.051726 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4245 16:47:28.055058 ==
4246 16:47:28.058291 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 16:47:28.061873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 16:47:28.062273 ==
4249 16:47:28.062670
4250 16:47:28.063130
4251 16:47:28.065069 TX Vref Scan disable
4252 16:47:28.068213 == TX Byte 0 ==
4253 16:47:28.071927 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4254 16:47:28.075083 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4255 16:47:28.075653 == TX Byte 1 ==
4256 16:47:28.081943 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4257 16:47:28.085449 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4258 16:47:28.085899
4259 16:47:28.086205 [DATLAT]
4260 16:47:28.088132 Freq=600, CH0 RK1
4261 16:47:28.088517
4262 16:47:28.088818 DATLAT Default: 0x9
4263 16:47:28.091304 0, 0xFFFF, sum = 0
4264 16:47:28.094785 1, 0xFFFF, sum = 0
4265 16:47:28.095324 2, 0xFFFF, sum = 0
4266 16:47:28.098492 3, 0xFFFF, sum = 0
4267 16:47:28.098884 4, 0xFFFF, sum = 0
4268 16:47:28.101941 5, 0xFFFF, sum = 0
4269 16:47:28.102334 6, 0xFFFF, sum = 0
4270 16:47:28.104465 7, 0xFFFF, sum = 0
4271 16:47:28.104855 8, 0x0, sum = 1
4272 16:47:28.109118 9, 0x0, sum = 2
4273 16:47:28.109788 10, 0x0, sum = 3
4274 16:47:28.110324 11, 0x0, sum = 4
4275 16:47:28.111203 best_step = 9
4276 16:47:28.111786
4277 16:47:28.112306 ==
4278 16:47:28.114781 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 16:47:28.117677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 16:47:28.118177 ==
4281 16:47:28.121153 RX Vref Scan: 0
4282 16:47:28.121539
4283 16:47:28.124724 RX Vref 0 -> 0, step: 1
4284 16:47:28.125216
4285 16:47:28.125524 RX Delay -195 -> 252, step: 8
4286 16:47:28.132238 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4287 16:47:28.135546 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4288 16:47:28.138770 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4289 16:47:28.141897 iDelay=205, Bit 3, Center 44 (-107 ~ 196) 304
4290 16:47:28.148409 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4291 16:47:28.152721 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4292 16:47:28.154873 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4293 16:47:28.158668 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4294 16:47:28.164847 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4295 16:47:28.168696 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4296 16:47:28.171531 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4297 16:47:28.175216 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4298 16:47:28.181390 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4299 16:47:28.185160 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4300 16:47:28.188288 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4301 16:47:28.191159 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4302 16:47:28.191607 ==
4303 16:47:28.194476 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 16:47:28.201069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 16:47:28.201569 ==
4306 16:47:28.202011 DQS Delay:
4307 16:47:28.204399 DQS0 = 0, DQS1 = 0
4308 16:47:28.204898 DQM Delay:
4309 16:47:28.205331 DQM0 = 44, DQM1 = 36
4310 16:47:28.207694 DQ Delay:
4311 16:47:28.211514 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =44
4312 16:47:28.214091 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4313 16:47:28.217621 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4314 16:47:28.220966 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4315 16:47:28.221420
4316 16:47:28.221801
4317 16:47:28.227393 [DQSOSCAuto] RK1, (LSB)MR18= 0x403c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4318 16:47:28.230837 CH0 RK1: MR19=808, MR18=403C
4319 16:47:28.237542 CH0_RK1: MR19=0x808, MR18=0x403C, DQSOSC=397, MR23=63, INC=166, DEC=110
4320 16:47:28.240548 [RxdqsGatingPostProcess] freq 600
4321 16:47:28.247259 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4322 16:47:28.247832 Pre-setting of DQS Precalculation
4323 16:47:28.253641 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4324 16:47:28.254111 ==
4325 16:47:28.257096 Dram Type= 6, Freq= 0, CH_1, rank 0
4326 16:47:28.260540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 16:47:28.260924 ==
4328 16:47:28.266685 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4329 16:47:28.273257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4330 16:47:28.276519 [CA 0] Center 36 (6~66) winsize 61
4331 16:47:28.280188 [CA 1] Center 35 (5~66) winsize 62
4332 16:47:28.283110 [CA 2] Center 35 (5~65) winsize 61
4333 16:47:28.286408 [CA 3] Center 34 (4~64) winsize 61
4334 16:47:28.290008 [CA 4] Center 34 (4~65) winsize 62
4335 16:47:28.293346 [CA 5] Center 33 (3~64) winsize 62
4336 16:47:28.293732
4337 16:47:28.296220 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4338 16:47:28.296620
4339 16:47:28.299569 [CATrainingPosCal] consider 1 rank data
4340 16:47:28.303472 u2DelayCellTimex100 = 270/100 ps
4341 16:47:28.306114 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4342 16:47:28.309508 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4343 16:47:28.312671 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4344 16:47:28.316610 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4345 16:47:28.322675 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4346 16:47:28.325909 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4347 16:47:28.326353
4348 16:47:28.329290 CA PerBit enable=1, Macro0, CA PI delay=33
4349 16:47:28.329716
4350 16:47:28.332571 [CBTSetCACLKResult] CA Dly = 33
4351 16:47:28.332953 CS Dly: 4 (0~35)
4352 16:47:28.333259 ==
4353 16:47:28.335884 Dram Type= 6, Freq= 0, CH_1, rank 1
4354 16:47:28.342755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4355 16:47:28.343351 ==
4356 16:47:28.345572 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4357 16:47:28.352618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4358 16:47:28.355463 [CA 0] Center 35 (5~66) winsize 62
4359 16:47:28.358980 [CA 1] Center 36 (6~66) winsize 61
4360 16:47:28.362363 [CA 2] Center 34 (4~65) winsize 62
4361 16:47:28.365816 [CA 3] Center 33 (3~64) winsize 62
4362 16:47:28.368819 [CA 4] Center 34 (4~65) winsize 62
4363 16:47:28.372604 [CA 5] Center 33 (3~64) winsize 62
4364 16:47:28.373104
4365 16:47:28.375592 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4366 16:47:28.376007
4367 16:47:28.378979 [CATrainingPosCal] consider 2 rank data
4368 16:47:28.382458 u2DelayCellTimex100 = 270/100 ps
4369 16:47:28.386001 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4370 16:47:28.391728 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4371 16:47:28.395466 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
4372 16:47:28.398442 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4373 16:47:28.401814 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4374 16:47:28.405071 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4375 16:47:28.405490
4376 16:47:28.409108 CA PerBit enable=1, Macro0, CA PI delay=33
4377 16:47:28.409615
4378 16:47:28.411963 [CBTSetCACLKResult] CA Dly = 33
4379 16:47:28.415094 CS Dly: 5 (0~37)
4380 16:47:28.415581
4381 16:47:28.418222 ----->DramcWriteLeveling(PI) begin...
4382 16:47:28.418854 ==
4383 16:47:28.421795 Dram Type= 6, Freq= 0, CH_1, rank 0
4384 16:47:28.425078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4385 16:47:28.425499 ==
4386 16:47:28.428193 Write leveling (Byte 0): 26 => 26
4387 16:47:28.431309 Write leveling (Byte 1): 30 => 30
4388 16:47:28.435345 DramcWriteLeveling(PI) end<-----
4389 16:47:28.435851
4390 16:47:28.436217 ==
4391 16:47:28.437933 Dram Type= 6, Freq= 0, CH_1, rank 0
4392 16:47:28.441363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4393 16:47:28.441787 ==
4394 16:47:28.444571 [Gating] SW mode calibration
4395 16:47:28.451332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4396 16:47:28.457895 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4397 16:47:28.461174 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4398 16:47:28.464315 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4399 16:47:28.471063 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4400 16:47:28.474717 0 9 12 | B1->B0 | 3232 2f2f | 0 0 | (0 1) (0 0)
4401 16:47:28.477640 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4402 16:47:28.484000 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4403 16:47:28.487673 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4404 16:47:28.490690 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4405 16:47:28.497110 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4406 16:47:28.500483 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 16:47:28.507114 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 16:47:28.510434 0 10 12 | B1->B0 | 2f2f 3636 | 0 1 | (0 0) (0 0)
4409 16:47:28.514118 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4410 16:47:28.519973 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4411 16:47:28.523409 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4412 16:47:28.526592 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4413 16:47:28.533157 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4414 16:47:28.536815 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 16:47:28.540029 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 16:47:28.546430 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 16:47:28.549911 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4418 16:47:28.553018 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4419 16:47:28.559821 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4420 16:47:28.562749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4421 16:47:28.566080 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4422 16:47:28.573488 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 16:47:28.576176 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 16:47:28.579696 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 16:47:28.586121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 16:47:28.589242 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 16:47:28.593029 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 16:47:28.599263 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 16:47:28.602955 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 16:47:28.606043 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 16:47:28.612406 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 16:47:28.616548 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4433 16:47:28.618856 Total UI for P1: 0, mck2ui 16
4434 16:47:28.622419 best dqsien dly found for B0: ( 0, 13, 10)
4435 16:47:28.625432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 16:47:28.628668 Total UI for P1: 0, mck2ui 16
4437 16:47:28.632223 best dqsien dly found for B1: ( 0, 13, 12)
4438 16:47:28.635272 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4439 16:47:28.638906 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4440 16:47:28.639367
4441 16:47:28.645900 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4442 16:47:28.648481 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4443 16:47:28.648922 [Gating] SW calibration Done
4444 16:47:28.652497 ==
4445 16:47:28.655421 Dram Type= 6, Freq= 0, CH_1, rank 0
4446 16:47:28.658761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 16:47:28.659217 ==
4448 16:47:28.659560 RX Vref Scan: 0
4449 16:47:28.659868
4450 16:47:28.661973 RX Vref 0 -> 0, step: 1
4451 16:47:28.662391
4452 16:47:28.665307 RX Delay -230 -> 252, step: 16
4453 16:47:28.668615 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4454 16:47:28.671715 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4455 16:47:28.678789 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4456 16:47:28.682410 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4457 16:47:28.685261 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4458 16:47:28.688780 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4459 16:47:28.695390 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4460 16:47:28.698371 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4461 16:47:28.701378 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4462 16:47:28.704996 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4463 16:47:28.708354 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4464 16:47:28.714378 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4465 16:47:28.718192 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4466 16:47:28.721586 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4467 16:47:28.727858 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4468 16:47:28.731389 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4469 16:47:28.731938 ==
4470 16:47:28.734208 Dram Type= 6, Freq= 0, CH_1, rank 0
4471 16:47:28.737569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4472 16:47:28.737988 ==
4473 16:47:28.740891 DQS Delay:
4474 16:47:28.741422 DQS0 = 0, DQS1 = 0
4475 16:47:28.741758 DQM Delay:
4476 16:47:28.744591 DQM0 = 43, DQM1 = 39
4477 16:47:28.745050 DQ Delay:
4478 16:47:28.747319 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4479 16:47:28.750626 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4480 16:47:28.754092 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4481 16:47:28.757383 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4482 16:47:28.757799
4483 16:47:28.758161
4484 16:47:28.758479 ==
4485 16:47:28.761649 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 16:47:28.767224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 16:47:28.767654 ==
4488 16:47:28.767988
4489 16:47:28.768331
4490 16:47:28.768647 TX Vref Scan disable
4491 16:47:28.770854 == TX Byte 0 ==
4492 16:47:28.773953 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4493 16:47:28.781125 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4494 16:47:28.781645 == TX Byte 1 ==
4495 16:47:28.784132 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4496 16:47:28.790781 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4497 16:47:28.791348 ==
4498 16:47:28.794098 Dram Type= 6, Freq= 0, CH_1, rank 0
4499 16:47:28.797293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4500 16:47:28.797720 ==
4501 16:47:28.798052
4502 16:47:28.798360
4503 16:47:28.800438 TX Vref Scan disable
4504 16:47:28.803969 == TX Byte 0 ==
4505 16:47:28.807561 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4506 16:47:28.810611 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4507 16:47:28.813862 == TX Byte 1 ==
4508 16:47:28.817090 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4509 16:47:28.820614 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4510 16:47:28.821138
4511 16:47:28.823665 [DATLAT]
4512 16:47:28.824181 Freq=600, CH1 RK0
4513 16:47:28.824522
4514 16:47:28.827020 DATLAT Default: 0x9
4515 16:47:28.827579 0, 0xFFFF, sum = 0
4516 16:47:28.830130 1, 0xFFFF, sum = 0
4517 16:47:28.830658 2, 0xFFFF, sum = 0
4518 16:47:28.833357 3, 0xFFFF, sum = 0
4519 16:47:28.833779 4, 0xFFFF, sum = 0
4520 16:47:28.836891 5, 0xFFFF, sum = 0
4521 16:47:28.837334 6, 0xFFFF, sum = 0
4522 16:47:28.840099 7, 0xFFFF, sum = 0
4523 16:47:28.840524 8, 0x0, sum = 1
4524 16:47:28.842961 9, 0x0, sum = 2
4525 16:47:28.843425 10, 0x0, sum = 3
4526 16:47:28.846301 11, 0x0, sum = 4
4527 16:47:28.846766 best_step = 9
4528 16:47:28.847229
4529 16:47:28.847633 ==
4530 16:47:28.849772 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 16:47:28.856393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 16:47:28.856933 ==
4533 16:47:28.857455 RX Vref Scan: 1
4534 16:47:28.857894
4535 16:47:28.859854 RX Vref 0 -> 0, step: 1
4536 16:47:28.860283
4537 16:47:28.862924 RX Delay -179 -> 252, step: 8
4538 16:47:28.863392
4539 16:47:28.866941 Set Vref, RX VrefLevel [Byte0]: 52
4540 16:47:28.869141 [Byte1]: 51
4541 16:47:28.869695
4542 16:47:28.872692 Final RX Vref Byte 0 = 52 to rank0
4543 16:47:28.875843 Final RX Vref Byte 1 = 51 to rank0
4544 16:47:28.878853 Final RX Vref Byte 0 = 52 to rank1
4545 16:47:28.882773 Final RX Vref Byte 1 = 51 to rank1==
4546 16:47:28.885532 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 16:47:28.889185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 16:47:28.889720 ==
4549 16:47:28.892136 DQS Delay:
4550 16:47:28.892684 DQS0 = 0, DQS1 = 0
4551 16:47:28.895680 DQM Delay:
4552 16:47:28.896109 DQM0 = 42, DQM1 = 34
4553 16:47:28.896550 DQ Delay:
4554 16:47:28.898580 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =44
4555 16:47:28.902104 DQ4 =36, DQ5 =52, DQ6 =56, DQ7 =36
4556 16:47:28.905904 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4557 16:47:28.909752 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4558 16:47:28.910249
4559 16:47:28.910654
4560 16:47:28.919036 [DQSOSCAuto] RK0, (LSB)MR18= 0x263f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4561 16:47:28.922054 CH1 RK0: MR19=808, MR18=263F
4562 16:47:28.928634 CH1_RK0: MR19=0x808, MR18=0x263F, DQSOSC=397, MR23=63, INC=166, DEC=110
4563 16:47:28.929134
4564 16:47:28.931888 ----->DramcWriteLeveling(PI) begin...
4565 16:47:28.932401 ==
4566 16:47:28.934840 Dram Type= 6, Freq= 0, CH_1, rank 1
4567 16:47:28.939327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 16:47:28.939825 ==
4569 16:47:28.941655 Write leveling (Byte 0): 28 => 28
4570 16:47:28.944931 Write leveling (Byte 1): 28 => 28
4571 16:47:28.948152 DramcWriteLeveling(PI) end<-----
4572 16:47:28.948550
4573 16:47:28.948960 ==
4574 16:47:28.951414 Dram Type= 6, Freq= 0, CH_1, rank 1
4575 16:47:28.954742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 16:47:28.955301 ==
4577 16:47:28.957908 [Gating] SW mode calibration
4578 16:47:28.964465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4579 16:47:28.970854 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4580 16:47:28.975214 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4581 16:47:28.981491 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4582 16:47:28.985097 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4583 16:47:28.987642 0 9 12 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
4584 16:47:28.994612 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4585 16:47:28.997408 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4586 16:47:29.001239 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4587 16:47:29.007378 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4588 16:47:29.011108 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4589 16:47:29.014043 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4590 16:47:29.020948 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4591 16:47:29.024078 0 10 12 | B1->B0 | 2f2f 4040 | 0 0 | (0 0) (0 0)
4592 16:47:29.027259 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4593 16:47:29.033712 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4594 16:47:29.037264 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4595 16:47:29.040739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4596 16:47:29.047003 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4597 16:47:29.050323 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4598 16:47:29.053678 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4599 16:47:29.061148 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4600 16:47:29.063141 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4601 16:47:29.066794 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4602 16:47:29.073374 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4603 16:47:29.076745 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4604 16:47:29.079613 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4605 16:47:29.086228 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4606 16:47:29.089652 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4607 16:47:29.092951 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4608 16:47:29.099409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4609 16:47:29.102593 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4610 16:47:29.106201 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 16:47:29.112877 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 16:47:29.116298 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 16:47:29.120067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 16:47:29.126176 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 16:47:29.129082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4616 16:47:29.133006 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 16:47:29.136371 Total UI for P1: 0, mck2ui 16
4618 16:47:29.139334 best dqsien dly found for B0: ( 0, 13, 12)
4619 16:47:29.142359 Total UI for P1: 0, mck2ui 16
4620 16:47:29.145692 best dqsien dly found for B1: ( 0, 13, 12)
4621 16:47:29.148945 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4622 16:47:29.152564 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4623 16:47:29.153094
4624 16:47:29.158588 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4625 16:47:29.162848 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4626 16:47:29.165418 [Gating] SW calibration Done
4627 16:47:29.165943 ==
4628 16:47:29.168479 Dram Type= 6, Freq= 0, CH_1, rank 1
4629 16:47:29.171725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 16:47:29.172148 ==
4631 16:47:29.172481 RX Vref Scan: 0
4632 16:47:29.172791
4633 16:47:29.175159 RX Vref 0 -> 0, step: 1
4634 16:47:29.175618
4635 16:47:29.178533 RX Delay -230 -> 252, step: 16
4636 16:47:29.181690 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4637 16:47:29.188346 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4638 16:47:29.191815 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4639 16:47:29.195117 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4640 16:47:29.198018 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4641 16:47:29.201341 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4642 16:47:29.207944 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4643 16:47:29.211570 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4644 16:47:29.214882 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4645 16:47:29.218001 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4646 16:47:29.224598 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4647 16:47:29.228065 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4648 16:47:29.231407 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4649 16:47:29.234987 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4650 16:47:29.241666 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4651 16:47:29.244050 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4652 16:47:29.244478 ==
4653 16:47:29.247489 Dram Type= 6, Freq= 0, CH_1, rank 1
4654 16:47:29.251094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4655 16:47:29.251665 ==
4656 16:47:29.254721 DQS Delay:
4657 16:47:29.255293 DQS0 = 0, DQS1 = 0
4658 16:47:29.257624 DQM Delay:
4659 16:47:29.258044 DQM0 = 41, DQM1 = 38
4660 16:47:29.258372 DQ Delay:
4661 16:47:29.261370 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4662 16:47:29.263937 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4663 16:47:29.267798 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4664 16:47:29.270346 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4665 16:47:29.270769
4666 16:47:29.271101
4667 16:47:29.274437 ==
4668 16:47:29.274954 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 16:47:29.280961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 16:47:29.281486 ==
4671 16:47:29.281825
4672 16:47:29.282135
4673 16:47:29.283528 TX Vref Scan disable
4674 16:47:29.283995 == TX Byte 0 ==
4675 16:47:29.287075 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4676 16:47:29.293779 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4677 16:47:29.294307 == TX Byte 1 ==
4678 16:47:29.296785 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4679 16:47:29.303580 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4680 16:47:29.304001 ==
4681 16:47:29.307295 Dram Type= 6, Freq= 0, CH_1, rank 1
4682 16:47:29.310296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4683 16:47:29.310817 ==
4684 16:47:29.311154
4685 16:47:29.311520
4686 16:47:29.313534 TX Vref Scan disable
4687 16:47:29.316949 == TX Byte 0 ==
4688 16:47:29.319857 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4689 16:47:29.323521 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4690 16:47:29.327216 == TX Byte 1 ==
4691 16:47:29.330780 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4692 16:47:29.333167 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4693 16:47:29.333587
4694 16:47:29.336988 [DATLAT]
4695 16:47:29.337509 Freq=600, CH1 RK1
4696 16:47:29.337843
4697 16:47:29.340591 DATLAT Default: 0x9
4698 16:47:29.341112 0, 0xFFFF, sum = 0
4699 16:47:29.343372 1, 0xFFFF, sum = 0
4700 16:47:29.343916 2, 0xFFFF, sum = 0
4701 16:47:29.346817 3, 0xFFFF, sum = 0
4702 16:47:29.347379 4, 0xFFFF, sum = 0
4703 16:47:29.349483 5, 0xFFFF, sum = 0
4704 16:47:29.349907 6, 0xFFFF, sum = 0
4705 16:47:29.353127 7, 0xFFFF, sum = 0
4706 16:47:29.353649 8, 0x0, sum = 1
4707 16:47:29.356320 9, 0x0, sum = 2
4708 16:47:29.356743 10, 0x0, sum = 3
4709 16:47:29.359848 11, 0x0, sum = 4
4710 16:47:29.360269 best_step = 9
4711 16:47:29.360599
4712 16:47:29.360903 ==
4713 16:47:29.362924 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 16:47:29.369363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 16:47:29.369869 ==
4716 16:47:29.370204 RX Vref Scan: 0
4717 16:47:29.370514
4718 16:47:29.373282 RX Vref 0 -> 0, step: 1
4719 16:47:29.373811
4720 16:47:29.375949 RX Delay -179 -> 252, step: 8
4721 16:47:29.379975 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4722 16:47:29.385902 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4723 16:47:29.389372 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4724 16:47:29.392590 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4725 16:47:29.395785 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4726 16:47:29.402609 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4727 16:47:29.405455 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4728 16:47:29.409198 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4729 16:47:29.412505 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4730 16:47:29.415616 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4731 16:47:29.422319 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4732 16:47:29.425762 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4733 16:47:29.428676 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4734 16:47:29.431852 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4735 16:47:29.438776 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4736 16:47:29.441993 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4737 16:47:29.442511 ==
4738 16:47:29.445674 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 16:47:29.448449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 16:47:29.449012 ==
4741 16:47:29.451821 DQS Delay:
4742 16:47:29.452231 DQS0 = 0, DQS1 = 0
4743 16:47:29.455069 DQM Delay:
4744 16:47:29.455512 DQM0 = 38, DQM1 = 35
4745 16:47:29.455840 DQ Delay:
4746 16:47:29.459271 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4747 16:47:29.461828 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4748 16:47:29.466214 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4749 16:47:29.469032 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4750 16:47:29.469551
4751 16:47:29.469881
4752 16:47:29.478509 [DQSOSCAuto] RK1, (LSB)MR18= 0x375c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4753 16:47:29.481983 CH1 RK1: MR19=808, MR18=375C
4754 16:47:29.488294 CH1_RK1: MR19=0x808, MR18=0x375C, DQSOSC=392, MR23=63, INC=170, DEC=113
4755 16:47:29.491466 [RxdqsGatingPostProcess] freq 600
4756 16:47:29.494881 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4757 16:47:29.497952 Pre-setting of DQS Precalculation
4758 16:47:29.504518 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4759 16:47:29.511010 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4760 16:47:29.517728 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4761 16:47:29.518253
4762 16:47:29.518586
4763 16:47:29.520541 [Calibration Summary] 1200 Mbps
4764 16:47:29.520986 CH 0, Rank 0
4765 16:47:29.524201 SW Impedance : PASS
4766 16:47:29.527416 DUTY Scan : NO K
4767 16:47:29.527835 ZQ Calibration : PASS
4768 16:47:29.530807 Jitter Meter : NO K
4769 16:47:29.533799 CBT Training : PASS
4770 16:47:29.534213 Write leveling : PASS
4771 16:47:29.537645 RX DQS gating : PASS
4772 16:47:29.540440 RX DQ/DQS(RDDQC) : PASS
4773 16:47:29.540856 TX DQ/DQS : PASS
4774 16:47:29.543786 RX DATLAT : PASS
4775 16:47:29.544338 RX DQ/DQS(Engine): PASS
4776 16:47:29.546874 TX OE : NO K
4777 16:47:29.547336 All Pass.
4778 16:47:29.547670
4779 16:47:29.550120 CH 0, Rank 1
4780 16:47:29.553785 SW Impedance : PASS
4781 16:47:29.554312 DUTY Scan : NO K
4782 16:47:29.556925 ZQ Calibration : PASS
4783 16:47:29.557351 Jitter Meter : NO K
4784 16:47:29.561234 CBT Training : PASS
4785 16:47:29.563371 Write leveling : PASS
4786 16:47:29.563799 RX DQS gating : PASS
4787 16:47:29.566911 RX DQ/DQS(RDDQC) : PASS
4788 16:47:29.570563 TX DQ/DQS : PASS
4789 16:47:29.571095 RX DATLAT : PASS
4790 16:47:29.573695 RX DQ/DQS(Engine): PASS
4791 16:47:29.577351 TX OE : NO K
4792 16:47:29.577883 All Pass.
4793 16:47:29.578223
4794 16:47:29.578536 CH 1, Rank 0
4795 16:47:29.579729 SW Impedance : PASS
4796 16:47:29.583269 DUTY Scan : NO K
4797 16:47:29.583799 ZQ Calibration : PASS
4798 16:47:29.586840 Jitter Meter : NO K
4799 16:47:29.589961 CBT Training : PASS
4800 16:47:29.590489 Write leveling : PASS
4801 16:47:29.594190 RX DQS gating : PASS
4802 16:47:29.596843 RX DQ/DQS(RDDQC) : PASS
4803 16:47:29.597378 TX DQ/DQS : PASS
4804 16:47:29.600140 RX DATLAT : PASS
4805 16:47:29.603163 RX DQ/DQS(Engine): PASS
4806 16:47:29.603617 TX OE : NO K
4807 16:47:29.606275 All Pass.
4808 16:47:29.606805
4809 16:47:29.607160 CH 1, Rank 1
4810 16:47:29.609767 SW Impedance : PASS
4811 16:47:29.610296 DUTY Scan : NO K
4812 16:47:29.612603 ZQ Calibration : PASS
4813 16:47:29.616450 Jitter Meter : NO K
4814 16:47:29.616874 CBT Training : PASS
4815 16:47:29.619645 Write leveling : PASS
4816 16:47:29.622703 RX DQS gating : PASS
4817 16:47:29.623334 RX DQ/DQS(RDDQC) : PASS
4818 16:47:29.625967 TX DQ/DQS : PASS
4819 16:47:29.629644 RX DATLAT : PASS
4820 16:47:29.630183 RX DQ/DQS(Engine): PASS
4821 16:47:29.633237 TX OE : NO K
4822 16:47:29.633772 All Pass.
4823 16:47:29.634109
4824 16:47:29.635714 DramC Write-DBI off
4825 16:47:29.639012 PER_BANK_REFRESH: Hybrid Mode
4826 16:47:29.639501 TX_TRACKING: ON
4827 16:47:29.648887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4828 16:47:29.651930 [FAST_K] Save calibration result to emmc
4829 16:47:29.655933 dramc_set_vcore_voltage set vcore to 662500
4830 16:47:29.658747 Read voltage for 933, 3
4831 16:47:29.659202 Vio18 = 0
4832 16:47:29.659556 Vcore = 662500
4833 16:47:29.662101 Vdram = 0
4834 16:47:29.662522 Vddq = 0
4835 16:47:29.662855 Vmddr = 0
4836 16:47:29.668840 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4837 16:47:29.672191 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4838 16:47:29.676031 MEM_TYPE=3, freq_sel=17
4839 16:47:29.678861 sv_algorithm_assistance_LP4_1600
4840 16:47:29.681791 ============ PULL DRAM RESETB DOWN ============
4841 16:47:29.685148 ========== PULL DRAM RESETB DOWN end =========
4842 16:47:29.691804 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4843 16:47:29.695213 ===================================
4844 16:47:29.698350 LPDDR4 DRAM CONFIGURATION
4845 16:47:29.701465 ===================================
4846 16:47:29.701896 EX_ROW_EN[0] = 0x0
4847 16:47:29.704739 EX_ROW_EN[1] = 0x0
4848 16:47:29.705165 LP4Y_EN = 0x0
4849 16:47:29.708044 WORK_FSP = 0x0
4850 16:47:29.708467 WL = 0x3
4851 16:47:29.711301 RL = 0x3
4852 16:47:29.711726 BL = 0x2
4853 16:47:29.714316 RPST = 0x0
4854 16:47:29.714738 RD_PRE = 0x0
4855 16:47:29.717907 WR_PRE = 0x1
4856 16:47:29.721164 WR_PST = 0x0
4857 16:47:29.721612 DBI_WR = 0x0
4858 16:47:29.724254 DBI_RD = 0x0
4859 16:47:29.724680 OTF = 0x1
4860 16:47:29.727594 ===================================
4861 16:47:29.731028 ===================================
4862 16:47:29.734447 ANA top config
4863 16:47:29.738640 ===================================
4864 16:47:29.739169 DLL_ASYNC_EN = 0
4865 16:47:29.741124 ALL_SLAVE_EN = 1
4866 16:47:29.744445 NEW_RANK_MODE = 1
4867 16:47:29.746985 DLL_IDLE_MODE = 1
4868 16:47:29.747461 LP45_APHY_COMB_EN = 1
4869 16:47:29.750586 TX_ODT_DIS = 1
4870 16:47:29.753983 NEW_8X_MODE = 1
4871 16:47:29.756935 ===================================
4872 16:47:29.760802 ===================================
4873 16:47:29.763512 data_rate = 1866
4874 16:47:29.767706 CKR = 1
4875 16:47:29.770789 DQ_P2S_RATIO = 8
4876 16:47:29.773557 ===================================
4877 16:47:29.773987 CA_P2S_RATIO = 8
4878 16:47:29.777276 DQ_CA_OPEN = 0
4879 16:47:29.781948 DQ_SEMI_OPEN = 0
4880 16:47:29.783608 CA_SEMI_OPEN = 0
4881 16:47:29.787071 CA_FULL_RATE = 0
4882 16:47:29.790472 DQ_CKDIV4_EN = 1
4883 16:47:29.790993 CA_CKDIV4_EN = 1
4884 16:47:29.793742 CA_PREDIV_EN = 0
4885 16:47:29.797125 PH8_DLY = 0
4886 16:47:29.800122 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4887 16:47:29.804216 DQ_AAMCK_DIV = 4
4888 16:47:29.807072 CA_AAMCK_DIV = 4
4889 16:47:29.807647 CA_ADMCK_DIV = 4
4890 16:47:29.810218 DQ_TRACK_CA_EN = 0
4891 16:47:29.814033 CA_PICK = 933
4892 16:47:29.816789 CA_MCKIO = 933
4893 16:47:29.820033 MCKIO_SEMI = 0
4894 16:47:29.823306 PLL_FREQ = 3732
4895 16:47:29.826879 DQ_UI_PI_RATIO = 32
4896 16:47:29.829862 CA_UI_PI_RATIO = 0
4897 16:47:29.830376 ===================================
4898 16:47:29.832956 ===================================
4899 16:47:29.836646 memory_type:LPDDR4
4900 16:47:29.839856 GP_NUM : 10
4901 16:47:29.840285 SRAM_EN : 1
4902 16:47:29.843692 MD32_EN : 0
4903 16:47:29.846349 ===================================
4904 16:47:29.849301 [ANA_INIT] >>>>>>>>>>>>>>
4905 16:47:29.853319 <<<<<< [CONFIGURE PHASE]: ANA_TX
4906 16:47:29.856331 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4907 16:47:29.859699 ===================================
4908 16:47:29.862770 data_rate = 1866,PCW = 0X8f00
4909 16:47:29.865882 ===================================
4910 16:47:29.869340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4911 16:47:29.872759 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4912 16:47:29.879337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4913 16:47:29.882669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4914 16:47:29.885675 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4915 16:47:29.892433 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4916 16:47:29.892980 [ANA_INIT] flow start
4917 16:47:29.895695 [ANA_INIT] PLL >>>>>>>>
4918 16:47:29.899262 [ANA_INIT] PLL <<<<<<<<
4919 16:47:29.899780 [ANA_INIT] MIDPI >>>>>>>>
4920 16:47:29.902157 [ANA_INIT] MIDPI <<<<<<<<
4921 16:47:29.905608 [ANA_INIT] DLL >>>>>>>>
4922 16:47:29.906129 [ANA_INIT] flow end
4923 16:47:29.908681 ============ LP4 DIFF to SE enter ============
4924 16:47:29.915568 ============ LP4 DIFF to SE exit ============
4925 16:47:29.916095 [ANA_INIT] <<<<<<<<<<<<<
4926 16:47:29.918938 [Flow] Enable top DCM control >>>>>
4927 16:47:29.921809 [Flow] Enable top DCM control <<<<<
4928 16:47:29.924793 Enable DLL master slave shuffle
4929 16:47:29.931620 ==============================================================
4930 16:47:29.935283 Gating Mode config
4931 16:47:29.938214 ==============================================================
4932 16:47:29.941994 Config description:
4933 16:47:29.952008 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4934 16:47:29.958232 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4935 16:47:29.961277 SELPH_MODE 0: By rank 1: By Phase
4936 16:47:29.968133 ==============================================================
4937 16:47:29.970916 GAT_TRACK_EN = 1
4938 16:47:29.974678 RX_GATING_MODE = 2
4939 16:47:29.978246 RX_GATING_TRACK_MODE = 2
4940 16:47:29.981354 SELPH_MODE = 1
4941 16:47:29.981874 PICG_EARLY_EN = 1
4942 16:47:29.984394 VALID_LAT_VALUE = 1
4943 16:47:29.991017 ==============================================================
4944 16:47:29.994097 Enter into Gating configuration >>>>
4945 16:47:29.997613 Exit from Gating configuration <<<<
4946 16:47:30.000970 Enter into DVFS_PRE_config >>>>>
4947 16:47:30.010759 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4948 16:47:30.014366 Exit from DVFS_PRE_config <<<<<
4949 16:47:30.017462 Enter into PICG configuration >>>>
4950 16:47:30.020585 Exit from PICG configuration <<<<
4951 16:47:30.023749 [RX_INPUT] configuration >>>>>
4952 16:47:30.026887 [RX_INPUT] configuration <<<<<
4953 16:47:30.033707 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4954 16:47:30.037032 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4955 16:47:30.043590 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4956 16:47:30.050639 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4957 16:47:30.056729 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4958 16:47:30.063461 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4959 16:47:30.067446 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4960 16:47:30.069885 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4961 16:47:30.072809 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4962 16:47:30.079726 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4963 16:47:30.083036 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4964 16:47:30.086396 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4965 16:47:30.089769 ===================================
4966 16:47:30.092827 LPDDR4 DRAM CONFIGURATION
4967 16:47:30.096129 ===================================
4968 16:47:30.099245 EX_ROW_EN[0] = 0x0
4969 16:47:30.099665 EX_ROW_EN[1] = 0x0
4970 16:47:30.102595 LP4Y_EN = 0x0
4971 16:47:30.103127 WORK_FSP = 0x0
4972 16:47:30.106174 WL = 0x3
4973 16:47:30.106692 RL = 0x3
4974 16:47:30.109048 BL = 0x2
4975 16:47:30.109465 RPST = 0x0
4976 16:47:30.112410 RD_PRE = 0x0
4977 16:47:30.112929 WR_PRE = 0x1
4978 16:47:30.116055 WR_PST = 0x0
4979 16:47:30.116576 DBI_WR = 0x0
4980 16:47:30.119358 DBI_RD = 0x0
4981 16:47:30.119882 OTF = 0x1
4982 16:47:30.122846 ===================================
4983 16:47:30.129129 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4984 16:47:30.132404 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4985 16:47:30.135496 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 16:47:30.138733 ===================================
4987 16:47:30.141919 LPDDR4 DRAM CONFIGURATION
4988 16:47:30.145260 ===================================
4989 16:47:30.149069 EX_ROW_EN[0] = 0x10
4990 16:47:30.149597 EX_ROW_EN[1] = 0x0
4991 16:47:30.151669 LP4Y_EN = 0x0
4992 16:47:30.152112 WORK_FSP = 0x0
4993 16:47:30.155146 WL = 0x3
4994 16:47:30.155603 RL = 0x3
4995 16:47:30.159053 BL = 0x2
4996 16:47:30.159524 RPST = 0x0
4997 16:47:30.161701 RD_PRE = 0x0
4998 16:47:30.162116 WR_PRE = 0x1
4999 16:47:30.165500 WR_PST = 0x0
5000 16:47:30.166031 DBI_WR = 0x0
5001 16:47:30.168545 DBI_RD = 0x0
5002 16:47:30.171596 OTF = 0x1
5003 16:47:30.174767 ===================================
5004 16:47:30.178080 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5005 16:47:30.183515 nWR fixed to 30
5006 16:47:30.187312 [ModeRegInit_LP4] CH0 RK0
5007 16:47:30.187746 [ModeRegInit_LP4] CH0 RK1
5008 16:47:30.189989 [ModeRegInit_LP4] CH1 RK0
5009 16:47:30.193556 [ModeRegInit_LP4] CH1 RK1
5010 16:47:30.194074 match AC timing 9
5011 16:47:30.200794 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5012 16:47:30.202889 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5013 16:47:30.206778 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5014 16:47:30.213787 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5015 16:47:30.216592 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5016 16:47:30.217112 ==
5017 16:47:30.220340 Dram Type= 6, Freq= 0, CH_0, rank 0
5018 16:47:30.223583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5019 16:47:30.226302 ==
5020 16:47:30.230023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5021 16:47:30.236334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5022 16:47:30.239412 [CA 0] Center 38 (8~69) winsize 62
5023 16:47:30.242605 [CA 1] Center 37 (7~68) winsize 62
5024 16:47:30.246465 [CA 2] Center 34 (4~65) winsize 62
5025 16:47:30.249376 [CA 3] Center 34 (4~65) winsize 62
5026 16:47:30.252814 [CA 4] Center 33 (3~64) winsize 62
5027 16:47:30.255621 [CA 5] Center 32 (2~63) winsize 62
5028 16:47:30.256094
5029 16:47:30.258703 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5030 16:47:30.259117
5031 16:47:30.262258 [CATrainingPosCal] consider 1 rank data
5032 16:47:30.265808 u2DelayCellTimex100 = 270/100 ps
5033 16:47:30.268879 CA0 delay=38 (8~69),Diff = 6 PI (37 cell)
5034 16:47:30.272402 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5035 16:47:30.279009 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5036 16:47:30.282067 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5037 16:47:30.285203 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5038 16:47:30.288506 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5039 16:47:30.288925
5040 16:47:30.291996 CA PerBit enable=1, Macro0, CA PI delay=32
5041 16:47:30.292422
5042 16:47:30.294872 [CBTSetCACLKResult] CA Dly = 32
5043 16:47:30.295351 CS Dly: 6 (0~37)
5044 16:47:30.299356 ==
5045 16:47:30.301446 Dram Type= 6, Freq= 0, CH_0, rank 1
5046 16:47:30.304970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5047 16:47:30.305399 ==
5048 16:47:30.312061 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5049 16:47:30.314897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5050 16:47:30.318831 [CA 0] Center 38 (8~69) winsize 62
5051 16:47:30.322363 [CA 1] Center 37 (7~68) winsize 62
5052 16:47:30.326142 [CA 2] Center 34 (4~65) winsize 62
5053 16:47:30.328645 [CA 3] Center 34 (4~65) winsize 62
5054 16:47:30.331820 [CA 4] Center 33 (3~64) winsize 62
5055 16:47:30.335322 [CA 5] Center 33 (3~63) winsize 61
5056 16:47:30.335842
5057 16:47:30.338743 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5058 16:47:30.339298
5059 16:47:30.341726 [CATrainingPosCal] consider 2 rank data
5060 16:47:30.344988 u2DelayCellTimex100 = 270/100 ps
5061 16:47:30.348340 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5062 16:47:30.354740 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5063 16:47:30.358161 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5064 16:47:30.362082 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5065 16:47:30.364711 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5066 16:47:30.367848 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5067 16:47:30.368274
5068 16:47:30.371077 CA PerBit enable=1, Macro0, CA PI delay=33
5069 16:47:30.371591
5070 16:47:30.374721 [CBTSetCACLKResult] CA Dly = 33
5071 16:47:30.378155 CS Dly: 7 (0~39)
5072 16:47:30.378691
5073 16:47:30.381338 ----->DramcWriteLeveling(PI) begin...
5074 16:47:30.381862 ==
5075 16:47:30.384914 Dram Type= 6, Freq= 0, CH_0, rank 0
5076 16:47:30.387865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5077 16:47:30.388296 ==
5078 16:47:30.391094 Write leveling (Byte 0): 30 => 30
5079 16:47:30.394163 Write leveling (Byte 1): 28 => 28
5080 16:47:30.397906 DramcWriteLeveling(PI) end<-----
5081 16:47:30.398425
5082 16:47:30.398880 ==
5083 16:47:30.401097 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 16:47:30.404199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 16:47:30.404628 ==
5086 16:47:30.407308 [Gating] SW mode calibration
5087 16:47:30.414411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5088 16:47:30.420797 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5089 16:47:30.424547 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5090 16:47:30.430622 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5091 16:47:30.433801 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5092 16:47:30.437158 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5093 16:47:30.443363 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5094 16:47:30.446737 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5095 16:47:30.450108 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5096 16:47:30.456770 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 1)
5097 16:47:30.460226 0 15 0 | B1->B0 | 3030 2424 | 1 0 | (1 1) (1 0)
5098 16:47:30.463743 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5099 16:47:30.469687 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5100 16:47:30.473054 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5101 16:47:30.476210 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5102 16:47:30.482910 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5103 16:47:30.486155 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 16:47:30.489421 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5105 16:47:30.496473 1 0 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
5106 16:47:30.499417 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5107 16:47:30.502670 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5108 16:47:30.509268 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5109 16:47:30.512092 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5110 16:47:30.516010 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5111 16:47:30.522466 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5112 16:47:30.525753 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5113 16:47:30.529363 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5114 16:47:30.535906 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5115 16:47:30.539439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5116 16:47:30.542569 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5117 16:47:30.548404 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5118 16:47:30.551671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5119 16:47:30.555339 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 16:47:30.561848 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 16:47:30.565147 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 16:47:30.568314 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 16:47:30.574378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 16:47:30.577834 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 16:47:30.580924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 16:47:30.588263 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 16:47:30.591162 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 16:47:30.594085 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5129 16:47:30.601047 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5130 16:47:30.604460 Total UI for P1: 0, mck2ui 16
5131 16:47:30.607241 best dqsien dly found for B0: ( 1, 2, 28)
5132 16:47:30.611758 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 16:47:30.613934 Total UI for P1: 0, mck2ui 16
5134 16:47:30.617085 best dqsien dly found for B1: ( 1, 3, 0)
5135 16:47:30.620483 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5136 16:47:30.623877 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5137 16:47:30.624065
5138 16:47:30.626817 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5139 16:47:30.633331 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5140 16:47:30.633475 [Gating] SW calibration Done
5141 16:47:30.633611 ==
5142 16:47:30.637164 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 16:47:30.643679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5144 16:47:30.643805 ==
5145 16:47:30.643913 RX Vref Scan: 0
5146 16:47:30.644012
5147 16:47:30.646671 RX Vref 0 -> 0, step: 1
5148 16:47:30.646778
5149 16:47:30.649920 RX Delay -80 -> 252, step: 8
5150 16:47:30.653308 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5151 16:47:30.656515 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5152 16:47:30.660110 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5153 16:47:30.663091 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5154 16:47:30.669956 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5155 16:47:30.673062 iDelay=200, Bit 5, Center 95 (8 ~ 183) 176
5156 16:47:30.676386 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5157 16:47:30.679760 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5158 16:47:30.682801 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5159 16:47:30.689301 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5160 16:47:30.692720 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5161 16:47:30.696153 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5162 16:47:30.699129 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5163 16:47:30.702463 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5164 16:47:30.708998 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5165 16:47:30.713067 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5166 16:47:30.713159 ==
5167 16:47:30.716335 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 16:47:30.719042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 16:47:30.719133 ==
5170 16:47:30.719254 DQS Delay:
5171 16:47:30.722971 DQS0 = 0, DQS1 = 0
5172 16:47:30.723055 DQM Delay:
5173 16:47:30.725783 DQM0 = 102, DQM1 = 89
5174 16:47:30.725866 DQ Delay:
5175 16:47:30.729264 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5176 16:47:30.732101 DQ4 =103, DQ5 =95, DQ6 =107, DQ7 =107
5177 16:47:30.735765 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5178 16:47:30.739030 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =95
5179 16:47:30.739114
5180 16:47:30.739249
5181 16:47:30.739328 ==
5182 16:47:30.742111 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 16:47:30.748728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 16:47:30.748824 ==
5185 16:47:30.748909
5186 16:47:30.748987
5187 16:47:30.751709 TX Vref Scan disable
5188 16:47:30.751793 == TX Byte 0 ==
5189 16:47:30.756010 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5190 16:47:30.761934 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5191 16:47:30.762058 == TX Byte 1 ==
5192 16:47:30.768078 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5193 16:47:30.771991 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5194 16:47:30.772080 ==
5195 16:47:30.775107 Dram Type= 6, Freq= 0, CH_0, rank 0
5196 16:47:30.778276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5197 16:47:30.778399 ==
5198 16:47:30.778486
5199 16:47:30.778564
5200 16:47:30.781544 TX Vref Scan disable
5201 16:47:30.785028 == TX Byte 0 ==
5202 16:47:30.788675 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5203 16:47:30.791794 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5204 16:47:30.794842 == TX Byte 1 ==
5205 16:47:30.797992 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5206 16:47:30.801679 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5207 16:47:30.801775
5208 16:47:30.804568 [DATLAT]
5209 16:47:30.804674 Freq=933, CH0 RK0
5210 16:47:30.804754
5211 16:47:30.807917 DATLAT Default: 0xd
5212 16:47:30.808026 0, 0xFFFF, sum = 0
5213 16:47:30.811664 1, 0xFFFF, sum = 0
5214 16:47:30.811774 2, 0xFFFF, sum = 0
5215 16:47:30.815010 3, 0xFFFF, sum = 0
5216 16:47:30.815131 4, 0xFFFF, sum = 0
5217 16:47:30.818679 5, 0xFFFF, sum = 0
5218 16:47:30.818816 6, 0xFFFF, sum = 0
5219 16:47:30.821805 7, 0xFFFF, sum = 0
5220 16:47:30.821943 8, 0xFFFF, sum = 0
5221 16:47:30.824317 9, 0xFFFF, sum = 0
5222 16:47:30.824507 10, 0x0, sum = 1
5223 16:47:30.828130 11, 0x0, sum = 2
5224 16:47:30.828265 12, 0x0, sum = 3
5225 16:47:30.830788 13, 0x0, sum = 4
5226 16:47:30.830925 best_step = 11
5227 16:47:30.831031
5228 16:47:30.831131 ==
5229 16:47:30.834143 Dram Type= 6, Freq= 0, CH_0, rank 0
5230 16:47:30.840637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5231 16:47:30.840786 ==
5232 16:47:30.840893 RX Vref Scan: 1
5233 16:47:30.840991
5234 16:47:30.844213 RX Vref 0 -> 0, step: 1
5235 16:47:30.844334
5236 16:47:30.848115 RX Delay -61 -> 252, step: 4
5237 16:47:30.848223
5238 16:47:30.851165 Set Vref, RX VrefLevel [Byte0]: 58
5239 16:47:30.854119 [Byte1]: 49
5240 16:47:30.854224
5241 16:47:30.857106 Final RX Vref Byte 0 = 58 to rank0
5242 16:47:30.860347 Final RX Vref Byte 1 = 49 to rank0
5243 16:47:30.864167 Final RX Vref Byte 0 = 58 to rank1
5244 16:47:30.867343 Final RX Vref Byte 1 = 49 to rank1==
5245 16:47:30.870807 Dram Type= 6, Freq= 0, CH_0, rank 0
5246 16:47:30.874312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5247 16:47:30.874741 ==
5248 16:47:30.877392 DQS Delay:
5249 16:47:30.877815 DQS0 = 0, DQS1 = 0
5250 16:47:30.880870 DQM Delay:
5251 16:47:30.881296 DQM0 = 103, DQM1 = 89
5252 16:47:30.883881 DQ Delay:
5253 16:47:30.886767 DQ0 =102, DQ1 =104, DQ2 =100, DQ3 =100
5254 16:47:30.891021 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5255 16:47:30.893481 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5256 16:47:30.896732 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =98
5257 16:47:30.896909
5258 16:47:30.896999
5259 16:47:30.903308 [DQSOSCAuto] RK0, (LSB)MR18= 0x1610, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5260 16:47:30.906553 CH0 RK0: MR19=505, MR18=1610
5261 16:47:30.913283 CH0_RK0: MR19=0x505, MR18=0x1610, DQSOSC=414, MR23=63, INC=63, DEC=42
5262 16:47:30.913421
5263 16:47:30.916585 ----->DramcWriteLeveling(PI) begin...
5264 16:47:30.916712 ==
5265 16:47:30.919629 Dram Type= 6, Freq= 0, CH_0, rank 1
5266 16:47:30.923373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 16:47:30.923500 ==
5268 16:47:30.926906 Write leveling (Byte 0): 32 => 32
5269 16:47:30.929723 Write leveling (Byte 1): 27 => 27
5270 16:47:30.932972 DramcWriteLeveling(PI) end<-----
5271 16:47:30.933099
5272 16:47:30.933212 ==
5273 16:47:30.936295 Dram Type= 6, Freq= 0, CH_0, rank 1
5274 16:47:30.939598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 16:47:30.942964 ==
5276 16:47:30.943063 [Gating] SW mode calibration
5277 16:47:30.952624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5278 16:47:30.955843 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5279 16:47:30.959141 0 14 0 | B1->B0 | 2929 3434 | 1 0 | (1 1) (1 1)
5280 16:47:30.965778 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5281 16:47:30.969025 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5282 16:47:30.972295 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5283 16:47:30.978919 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5284 16:47:30.982582 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5285 16:47:30.985449 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5286 16:47:30.992074 0 14 28 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
5287 16:47:30.995192 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5288 16:47:30.998615 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5289 16:47:31.005367 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5290 16:47:31.008918 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5291 16:47:31.012360 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5292 16:47:31.018488 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5293 16:47:31.021875 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5294 16:47:31.025596 0 15 28 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
5295 16:47:31.031676 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5296 16:47:31.035000 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5297 16:47:31.038621 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5298 16:47:31.045005 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5299 16:47:31.048173 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5300 16:47:31.055084 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5301 16:47:31.058343 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5302 16:47:31.061639 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5303 16:47:31.068225 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5304 16:47:31.071435 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5305 16:47:31.074764 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5306 16:47:31.081489 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5307 16:47:31.084848 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5308 16:47:31.088090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5309 16:47:31.094744 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5310 16:47:31.097798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5311 16:47:31.101293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5312 16:47:31.107530 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5313 16:47:31.111518 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 16:47:31.114750 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 16:47:31.121001 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 16:47:31.124456 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 16:47:31.127705 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 16:47:31.133907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5319 16:47:31.137376 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5320 16:47:31.141621 Total UI for P1: 0, mck2ui 16
5321 16:47:31.143850 best dqsien dly found for B0: ( 1, 2, 28)
5322 16:47:31.147051 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 16:47:31.150188 Total UI for P1: 0, mck2ui 16
5324 16:47:31.153917 best dqsien dly found for B1: ( 1, 3, 0)
5325 16:47:31.156921 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5326 16:47:31.160022 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5327 16:47:31.160473
5328 16:47:31.167708 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5329 16:47:31.170107 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5330 16:47:31.170628 [Gating] SW calibration Done
5331 16:47:31.173409 ==
5332 16:47:31.176567 Dram Type= 6, Freq= 0, CH_0, rank 1
5333 16:47:31.180127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5334 16:47:31.180648 ==
5335 16:47:31.180977 RX Vref Scan: 0
5336 16:47:31.181282
5337 16:47:31.183220 RX Vref 0 -> 0, step: 1
5338 16:47:31.183641
5339 16:47:31.187147 RX Delay -80 -> 252, step: 8
5340 16:47:31.189954 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5341 16:47:31.193364 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5342 16:47:31.196662 iDelay=200, Bit 2, Center 99 (8 ~ 191) 184
5343 16:47:31.203132 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5344 16:47:31.206159 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5345 16:47:31.209332 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5346 16:47:31.213267 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5347 16:47:31.216503 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5348 16:47:31.219546 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5349 16:47:31.225965 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5350 16:47:31.229308 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5351 16:47:31.232815 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5352 16:47:31.235602 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5353 16:47:31.239222 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5354 16:47:31.246003 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5355 16:47:31.249861 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5356 16:47:31.250407 ==
5357 16:47:31.252565 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 16:47:31.256321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 16:47:31.256738 ==
5360 16:47:31.258627 DQS Delay:
5361 16:47:31.259043 DQS0 = 0, DQS1 = 0
5362 16:47:31.259419 DQM Delay:
5363 16:47:31.261977 DQM0 = 100, DQM1 = 90
5364 16:47:31.262390 DQ Delay:
5365 16:47:31.265478 DQ0 =99, DQ1 =103, DQ2 =99, DQ3 =99
5366 16:47:31.268880 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5367 16:47:31.272283 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5368 16:47:31.275441 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =95
5369 16:47:31.275859
5370 16:47:31.276186
5371 16:47:31.276514 ==
5372 16:47:31.278789 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 16:47:31.285307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 16:47:31.285838 ==
5375 16:47:31.286175
5376 16:47:31.286482
5377 16:47:31.286772 TX Vref Scan disable
5378 16:47:31.289254 == TX Byte 0 ==
5379 16:47:31.292290 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5380 16:47:31.299248 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5381 16:47:31.299771 == TX Byte 1 ==
5382 16:47:31.302664 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5383 16:47:31.309004 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5384 16:47:31.309525 ==
5385 16:47:31.312087 Dram Type= 6, Freq= 0, CH_0, rank 1
5386 16:47:31.316104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5387 16:47:31.316657 ==
5388 16:47:31.317027
5389 16:47:31.317367
5390 16:47:31.318722 TX Vref Scan disable
5391 16:47:31.322151 == TX Byte 0 ==
5392 16:47:31.325315 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5393 16:47:31.328654 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5394 16:47:31.331896 == TX Byte 1 ==
5395 16:47:31.335215 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5396 16:47:31.339005 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5397 16:47:31.339566
5398 16:47:31.339899 [DATLAT]
5399 16:47:31.341884 Freq=933, CH0 RK1
5400 16:47:31.342301
5401 16:47:31.344846 DATLAT Default: 0xb
5402 16:47:31.345261 0, 0xFFFF, sum = 0
5403 16:47:31.348302 1, 0xFFFF, sum = 0
5404 16:47:31.348832 2, 0xFFFF, sum = 0
5405 16:47:31.351318 3, 0xFFFF, sum = 0
5406 16:47:31.351740 4, 0xFFFF, sum = 0
5407 16:47:31.355043 5, 0xFFFF, sum = 0
5408 16:47:31.355489 6, 0xFFFF, sum = 0
5409 16:47:31.358139 7, 0xFFFF, sum = 0
5410 16:47:31.358564 8, 0xFFFF, sum = 0
5411 16:47:31.361105 9, 0xFFFF, sum = 0
5412 16:47:31.361526 10, 0x0, sum = 1
5413 16:47:31.364776 11, 0x0, sum = 2
5414 16:47:31.365298 12, 0x0, sum = 3
5415 16:47:31.367755 13, 0x0, sum = 4
5416 16:47:31.368179 best_step = 11
5417 16:47:31.368541
5418 16:47:31.368873 ==
5419 16:47:31.371335 Dram Type= 6, Freq= 0, CH_0, rank 1
5420 16:47:31.374695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5421 16:47:31.377816 ==
5422 16:47:31.378235 RX Vref Scan: 0
5423 16:47:31.378564
5424 16:47:31.381367 RX Vref 0 -> 0, step: 1
5425 16:47:31.381889
5426 16:47:31.384749 RX Delay -61 -> 252, step: 4
5427 16:47:31.387612 iDelay=199, Bit 0, Center 100 (15 ~ 186) 172
5428 16:47:31.391614 iDelay=199, Bit 1, Center 102 (15 ~ 190) 176
5429 16:47:31.397601 iDelay=199, Bit 2, Center 96 (11 ~ 182) 172
5430 16:47:31.401069 iDelay=199, Bit 3, Center 98 (11 ~ 186) 176
5431 16:47:31.404221 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5432 16:47:31.408092 iDelay=199, Bit 5, Center 92 (7 ~ 178) 172
5433 16:47:31.411595 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5434 16:47:31.418171 iDelay=199, Bit 7, Center 108 (23 ~ 194) 172
5435 16:47:31.420700 iDelay=199, Bit 8, Center 80 (-5 ~ 166) 172
5436 16:47:31.424076 iDelay=199, Bit 9, Center 80 (-5 ~ 166) 172
5437 16:47:31.427360 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5438 16:47:31.430939 iDelay=199, Bit 11, Center 84 (-1 ~ 170) 172
5439 16:47:31.437263 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5440 16:47:31.440325 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5441 16:47:31.443666 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5442 16:47:31.447256 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5443 16:47:31.447769 ==
5444 16:47:31.450145 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 16:47:31.453549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 16:47:31.456794 ==
5447 16:47:31.457216 DQS Delay:
5448 16:47:31.457546 DQS0 = 0, DQS1 = 0
5449 16:47:31.460427 DQM Delay:
5450 16:47:31.460842 DQM0 = 101, DQM1 = 90
5451 16:47:31.463372 DQ Delay:
5452 16:47:31.466716 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5453 16:47:31.469710 DQ4 =104, DQ5 =92, DQ6 =112, DQ7 =108
5454 16:47:31.473286 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
5455 16:47:31.476465 DQ12 =96, DQ13 =94, DQ14 =102, DQ15 =96
5456 16:47:31.476883
5457 16:47:31.477274
5458 16:47:31.483711 [DQSOSCAuto] RK1, (LSB)MR18= 0x1714, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5459 16:47:31.486749 CH0 RK1: MR19=505, MR18=1714
5460 16:47:31.493383 CH0_RK1: MR19=0x505, MR18=0x1714, DQSOSC=414, MR23=63, INC=63, DEC=42
5461 16:47:31.496308 [RxdqsGatingPostProcess] freq 933
5462 16:47:31.503596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5463 16:47:31.504119 best DQS0 dly(2T, 0.5T) = (0, 10)
5464 16:47:31.506385 best DQS1 dly(2T, 0.5T) = (0, 11)
5465 16:47:31.509791 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5466 16:47:31.513330 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5467 16:47:31.516576 best DQS0 dly(2T, 0.5T) = (0, 10)
5468 16:47:31.520064 best DQS1 dly(2T, 0.5T) = (0, 11)
5469 16:47:31.523390 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5470 16:47:31.526240 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5471 16:47:31.529459 Pre-setting of DQS Precalculation
5472 16:47:31.535789 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5473 16:47:31.536348 ==
5474 16:47:31.539775 Dram Type= 6, Freq= 0, CH_1, rank 0
5475 16:47:31.543094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 16:47:31.543696 ==
5477 16:47:31.549274 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5478 16:47:31.552221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5479 16:47:31.556596 [CA 0] Center 36 (6~67) winsize 62
5480 16:47:31.559896 [CA 1] Center 36 (6~67) winsize 62
5481 16:47:31.563022 [CA 2] Center 34 (4~64) winsize 61
5482 16:47:31.566379 [CA 3] Center 34 (4~64) winsize 61
5483 16:47:31.569602 [CA 4] Center 34 (4~64) winsize 61
5484 16:47:31.572780 [CA 5] Center 33 (3~64) winsize 62
5485 16:47:31.573197
5486 16:47:31.576488 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5487 16:47:31.576907
5488 16:47:31.580347 [CATrainingPosCal] consider 1 rank data
5489 16:47:31.582684 u2DelayCellTimex100 = 270/100 ps
5490 16:47:31.586609 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5491 16:47:31.592940 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5492 16:47:31.596298 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5493 16:47:31.599887 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5494 16:47:31.602736 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5495 16:47:31.605860 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5496 16:47:31.606283
5497 16:47:31.609109 CA PerBit enable=1, Macro0, CA PI delay=33
5498 16:47:31.609527
5499 16:47:31.613019 [CBTSetCACLKResult] CA Dly = 33
5500 16:47:31.615873 CS Dly: 5 (0~36)
5501 16:47:31.616392 ==
5502 16:47:31.619504 Dram Type= 6, Freq= 0, CH_1, rank 1
5503 16:47:31.622763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5504 16:47:31.623315 ==
5505 16:47:31.629341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5506 16:47:31.632480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5507 16:47:31.636793 [CA 0] Center 36 (6~66) winsize 61
5508 16:47:31.640001 [CA 1] Center 36 (6~67) winsize 62
5509 16:47:31.643692 [CA 2] Center 34 (4~65) winsize 62
5510 16:47:31.646756 [CA 3] Center 33 (3~64) winsize 62
5511 16:47:31.650566 [CA 4] Center 34 (4~64) winsize 61
5512 16:47:31.652798 [CA 5] Center 33 (3~64) winsize 62
5513 16:47:31.653284
5514 16:47:31.656153 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5515 16:47:31.656624
5516 16:47:31.659285 [CATrainingPosCal] consider 2 rank data
5517 16:47:31.662879 u2DelayCellTimex100 = 270/100 ps
5518 16:47:31.666258 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5519 16:47:31.672349 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5520 16:47:31.675687 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5521 16:47:31.679242 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5522 16:47:31.682296 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5523 16:47:31.685994 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5524 16:47:31.686416
5525 16:47:31.689165 CA PerBit enable=1, Macro0, CA PI delay=33
5526 16:47:31.689583
5527 16:47:31.692430 [CBTSetCACLKResult] CA Dly = 33
5528 16:47:31.695455 CS Dly: 6 (0~38)
5529 16:47:31.696006
5530 16:47:31.699033 ----->DramcWriteLeveling(PI) begin...
5531 16:47:31.699685 ==
5532 16:47:31.702566 Dram Type= 6, Freq= 0, CH_1, rank 0
5533 16:47:31.705494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5534 16:47:31.705912 ==
5535 16:47:31.708756 Write leveling (Byte 0): 23 => 23
5536 16:47:31.712253 Write leveling (Byte 1): 26 => 26
5537 16:47:31.715594 DramcWriteLeveling(PI) end<-----
5538 16:47:31.716113
5539 16:47:31.716442 ==
5540 16:47:31.718991 Dram Type= 6, Freq= 0, CH_1, rank 0
5541 16:47:31.722079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 16:47:31.722601 ==
5543 16:47:31.725712 [Gating] SW mode calibration
5544 16:47:31.732162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5545 16:47:31.739772 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5546 16:47:31.741363 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5547 16:47:31.748345 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5548 16:47:31.751806 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5549 16:47:31.755131 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5550 16:47:31.761345 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5551 16:47:31.765263 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5552 16:47:31.767800 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
5553 16:47:31.774393 0 14 28 | B1->B0 | 2d2d 2828 | 0 0 | (0 0) (0 0)
5554 16:47:31.777912 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5555 16:47:31.781079 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5556 16:47:31.787361 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5557 16:47:31.791108 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5558 16:47:31.794173 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5559 16:47:31.800911 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5560 16:47:31.803911 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5561 16:47:31.807285 0 15 28 | B1->B0 | 3636 4040 | 0 0 | (0 0) (0 0)
5562 16:47:31.813942 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5563 16:47:31.817711 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5564 16:47:31.820733 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5565 16:47:31.827138 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5566 16:47:31.830404 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5567 16:47:31.833922 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 16:47:31.840220 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5569 16:47:31.843662 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5570 16:47:31.846790 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5571 16:47:31.853158 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 16:47:31.856680 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 16:47:31.859789 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 16:47:31.866878 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 16:47:31.870364 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 16:47:31.873227 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5577 16:47:31.879518 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5578 16:47:31.882750 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5579 16:47:31.886436 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5580 16:47:31.893147 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 16:47:31.896542 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 16:47:31.899342 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 16:47:31.906403 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 16:47:31.909783 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5585 16:47:31.912520 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 16:47:31.915566 Total UI for P1: 0, mck2ui 16
5587 16:47:31.918994 best dqsien dly found for B0: ( 1, 2, 24)
5588 16:47:31.922896 Total UI for P1: 0, mck2ui 16
5589 16:47:31.925739 best dqsien dly found for B1: ( 1, 2, 26)
5590 16:47:31.929012 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5591 16:47:31.932454 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5592 16:47:31.936615
5593 16:47:31.938995 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5594 16:47:31.941683 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5595 16:47:31.944853 [Gating] SW calibration Done
5596 16:47:31.945364 ==
5597 16:47:31.948624 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 16:47:31.952134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 16:47:31.952658 ==
5600 16:47:31.952988 RX Vref Scan: 0
5601 16:47:31.954934
5602 16:47:31.955381 RX Vref 0 -> 0, step: 1
5603 16:47:31.955713
5604 16:47:31.958281 RX Delay -80 -> 252, step: 8
5605 16:47:31.961996 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5606 16:47:31.965758 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5607 16:47:31.971630 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5608 16:47:31.974848 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5609 16:47:31.978160 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5610 16:47:31.982594 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5611 16:47:31.984646 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5612 16:47:31.991432 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5613 16:47:31.994634 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5614 16:47:31.998313 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5615 16:47:32.000940 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5616 16:47:32.004411 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5617 16:47:32.008065 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5618 16:47:32.014557 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5619 16:47:32.017596 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5620 16:47:32.020735 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5621 16:47:32.021210 ==
5622 16:47:32.023936 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 16:47:32.027489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 16:47:32.030960 ==
5625 16:47:32.031511 DQS Delay:
5626 16:47:32.031844 DQS0 = 0, DQS1 = 0
5627 16:47:32.034627 DQM Delay:
5628 16:47:32.035041 DQM0 = 98, DQM1 = 95
5629 16:47:32.037312 DQ Delay:
5630 16:47:32.040623 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =99
5631 16:47:32.043660 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5632 16:47:32.047250 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5633 16:47:32.050716 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5634 16:47:32.051263
5635 16:47:32.051602
5636 16:47:32.051918 ==
5637 16:47:32.054041 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 16:47:32.057227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 16:47:32.057755 ==
5640 16:47:32.058090
5641 16:47:32.058402
5642 16:47:32.060675 TX Vref Scan disable
5643 16:47:32.063361 == TX Byte 0 ==
5644 16:47:32.066999 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5645 16:47:32.070727 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5646 16:47:32.073474 == TX Byte 1 ==
5647 16:47:32.076923 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5648 16:47:32.079922 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5649 16:47:32.080343 ==
5650 16:47:32.083547 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 16:47:32.086748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 16:47:32.089758 ==
5653 16:47:32.090175
5654 16:47:32.090500
5655 16:47:32.090806 TX Vref Scan disable
5656 16:47:32.093644 == TX Byte 0 ==
5657 16:47:32.097032 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5658 16:47:32.103668 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5659 16:47:32.104192 == TX Byte 1 ==
5660 16:47:32.106522 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5661 16:47:32.113410 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5662 16:47:32.113929
5663 16:47:32.114260 [DATLAT]
5664 16:47:32.114566 Freq=933, CH1 RK0
5665 16:47:32.114863
5666 16:47:32.117053 DATLAT Default: 0xd
5667 16:47:32.120070 0, 0xFFFF, sum = 0
5668 16:47:32.120609 1, 0xFFFF, sum = 0
5669 16:47:32.123260 2, 0xFFFF, sum = 0
5670 16:47:32.123686 3, 0xFFFF, sum = 0
5671 16:47:32.126636 4, 0xFFFF, sum = 0
5672 16:47:32.127199 5, 0xFFFF, sum = 0
5673 16:47:32.130035 6, 0xFFFF, sum = 0
5674 16:47:32.130461 7, 0xFFFF, sum = 0
5675 16:47:32.133191 8, 0xFFFF, sum = 0
5676 16:47:32.133740 9, 0xFFFF, sum = 0
5677 16:47:32.136372 10, 0x0, sum = 1
5678 16:47:32.136803 11, 0x0, sum = 2
5679 16:47:32.139408 12, 0x0, sum = 3
5680 16:47:32.139835 13, 0x0, sum = 4
5681 16:47:32.142930 best_step = 11
5682 16:47:32.143370
5683 16:47:32.143705 ==
5684 16:47:32.146394 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 16:47:32.149668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 16:47:32.150201 ==
5687 16:47:32.150546 RX Vref Scan: 1
5688 16:47:32.152667
5689 16:47:32.153092 RX Vref 0 -> 0, step: 1
5690 16:47:32.153431
5691 16:47:32.156218 RX Delay -53 -> 252, step: 4
5692 16:47:32.156640
5693 16:47:32.159219 Set Vref, RX VrefLevel [Byte0]: 52
5694 16:47:32.162313 [Byte1]: 51
5695 16:47:32.166271
5696 16:47:32.166811 Final RX Vref Byte 0 = 52 to rank0
5697 16:47:32.169563 Final RX Vref Byte 1 = 51 to rank0
5698 16:47:32.173004 Final RX Vref Byte 0 = 52 to rank1
5699 16:47:32.175968 Final RX Vref Byte 1 = 51 to rank1==
5700 16:47:32.179562 Dram Type= 6, Freq= 0, CH_1, rank 0
5701 16:47:32.185934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5702 16:47:32.186501 ==
5703 16:47:32.186947 DQS Delay:
5704 16:47:32.189130 DQS0 = 0, DQS1 = 0
5705 16:47:32.189558 DQM Delay:
5706 16:47:32.189988 DQM0 = 98, DQM1 = 94
5707 16:47:32.192628 DQ Delay:
5708 16:47:32.195865 DQ0 =104, DQ1 =92, DQ2 =88, DQ3 =98
5709 16:47:32.198909 DQ4 =96, DQ5 =106, DQ6 =108, DQ7 =94
5710 16:47:32.202416 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5711 16:47:32.205341 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5712 16:47:32.205768
5713 16:47:32.206099
5714 16:47:32.211887 [DQSOSCAuto] RK0, (LSB)MR18= 0x616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 420 ps
5715 16:47:32.215273 CH1 RK0: MR19=505, MR18=616
5716 16:47:32.222057 CH1_RK0: MR19=0x505, MR18=0x616, DQSOSC=414, MR23=63, INC=63, DEC=42
5717 16:47:32.222582
5718 16:47:32.225938 ----->DramcWriteLeveling(PI) begin...
5719 16:47:32.226461 ==
5720 16:47:32.229024 Dram Type= 6, Freq= 0, CH_1, rank 1
5721 16:47:32.231684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 16:47:32.232116 ==
5723 16:47:32.235130 Write leveling (Byte 0): 23 => 23
5724 16:47:32.238405 Write leveling (Byte 1): 30 => 30
5725 16:47:32.241486 DramcWriteLeveling(PI) end<-----
5726 16:47:32.241914
5727 16:47:32.242342 ==
5728 16:47:32.244878 Dram Type= 6, Freq= 0, CH_1, rank 1
5729 16:47:32.251986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 16:47:32.252526 ==
5731 16:47:32.252967 [Gating] SW mode calibration
5732 16:47:32.261765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5733 16:47:32.265062 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5734 16:47:32.271416 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5735 16:47:32.275346 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5736 16:47:32.278275 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5737 16:47:32.284500 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5738 16:47:32.288081 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5739 16:47:32.291150 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5740 16:47:32.297806 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (0 0) (0 1)
5741 16:47:32.301131 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5742 16:47:32.304250 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5743 16:47:32.310875 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5744 16:47:32.314500 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5745 16:47:32.317681 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5746 16:47:32.323942 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5747 16:47:32.327145 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5748 16:47:32.330707 0 15 24 | B1->B0 | 2929 3838 | 0 0 | (0 0) (0 0)
5749 16:47:32.337149 0 15 28 | B1->B0 | 3837 4646 | 1 0 | (0 0) (0 0)
5750 16:47:32.340358 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5751 16:47:32.343562 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5752 16:47:32.350206 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5753 16:47:32.353608 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5754 16:47:32.356907 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5755 16:47:32.363653 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5756 16:47:32.367589 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5757 16:47:32.370302 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5758 16:47:32.376752 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5759 16:47:32.379716 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5760 16:47:32.383594 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5761 16:47:32.389980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5762 16:47:32.393335 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5763 16:47:32.396378 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5764 16:47:32.402993 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5765 16:47:32.406322 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5766 16:47:32.409887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5767 16:47:32.416057 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 16:47:32.419390 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 16:47:32.422863 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 16:47:32.429164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 16:47:32.432460 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 16:47:32.435467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5773 16:47:32.442835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5774 16:47:32.446045 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 16:47:32.449517 Total UI for P1: 0, mck2ui 16
5776 16:47:32.452057 best dqsien dly found for B0: ( 1, 2, 26)
5777 16:47:32.455259 Total UI for P1: 0, mck2ui 16
5778 16:47:32.459033 best dqsien dly found for B1: ( 1, 2, 30)
5779 16:47:32.462197 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5780 16:47:32.465977 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5781 16:47:32.466435
5782 16:47:32.468635 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5783 16:47:32.471882 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5784 16:47:32.475131 [Gating] SW calibration Done
5785 16:47:32.475599 ==
5786 16:47:32.478443 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 16:47:32.484961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 16:47:32.485392 ==
5789 16:47:32.485821 RX Vref Scan: 0
5790 16:47:32.486225
5791 16:47:32.487957 RX Vref 0 -> 0, step: 1
5792 16:47:32.488387
5793 16:47:32.491353 RX Delay -80 -> 252, step: 8
5794 16:47:32.495017 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5795 16:47:32.498688 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5796 16:47:32.502688 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5797 16:47:32.504593 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5798 16:47:32.511593 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5799 16:47:32.515025 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5800 16:47:32.518385 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5801 16:47:32.521938 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5802 16:47:32.524448 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5803 16:47:32.527749 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5804 16:47:32.534182 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5805 16:47:32.537544 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5806 16:47:32.540932 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5807 16:47:32.544552 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5808 16:47:32.547697 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5809 16:47:32.554170 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5810 16:47:32.554605 ==
5811 16:47:32.557344 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 16:47:32.560546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 16:47:32.560855 ==
5814 16:47:32.561165 DQS Delay:
5815 16:47:32.563340 DQS0 = 0, DQS1 = 0
5816 16:47:32.563664 DQM Delay:
5817 16:47:32.567543 DQM0 = 97, DQM1 = 94
5818 16:47:32.567782 DQ Delay:
5819 16:47:32.570179 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5820 16:47:32.573362 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5821 16:47:32.576674 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5822 16:47:32.580249 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5823 16:47:32.580435
5824 16:47:32.580613
5825 16:47:32.580691 ==
5826 16:47:32.583015 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 16:47:32.589898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 16:47:32.589982 ==
5829 16:47:32.590065
5830 16:47:32.590144
5831 16:47:32.592917 TX Vref Scan disable
5832 16:47:32.593001 == TX Byte 0 ==
5833 16:47:32.596361 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5834 16:47:32.602827 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5835 16:47:32.602911 == TX Byte 1 ==
5836 16:47:32.606603 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5837 16:47:32.613060 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5838 16:47:32.613153 ==
5839 16:47:32.616027 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 16:47:32.619538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 16:47:32.619621 ==
5842 16:47:32.619686
5843 16:47:32.619744
5844 16:47:32.622611 TX Vref Scan disable
5845 16:47:32.626355 == TX Byte 0 ==
5846 16:47:32.629720 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5847 16:47:32.632844 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5848 16:47:32.636117 == TX Byte 1 ==
5849 16:47:32.639724 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5850 16:47:32.642786 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5851 16:47:32.643233
5852 16:47:32.646624 [DATLAT]
5853 16:47:32.647130 Freq=933, CH1 RK1
5854 16:47:32.647529
5855 16:47:32.650045 DATLAT Default: 0xb
5856 16:47:32.650465 0, 0xFFFF, sum = 0
5857 16:47:32.653112 1, 0xFFFF, sum = 0
5858 16:47:32.653643 2, 0xFFFF, sum = 0
5859 16:47:32.656300 3, 0xFFFF, sum = 0
5860 16:47:32.656731 4, 0xFFFF, sum = 0
5861 16:47:32.659265 5, 0xFFFF, sum = 0
5862 16:47:32.659697 6, 0xFFFF, sum = 0
5863 16:47:32.662748 7, 0xFFFF, sum = 0
5864 16:47:32.663213 8, 0xFFFF, sum = 0
5865 16:47:32.665905 9, 0xFFFF, sum = 0
5866 16:47:32.666352 10, 0x0, sum = 1
5867 16:47:32.670075 11, 0x0, sum = 2
5868 16:47:32.670748 12, 0x0, sum = 3
5869 16:47:32.672486 13, 0x0, sum = 4
5870 16:47:32.672910 best_step = 11
5871 16:47:32.673242
5872 16:47:32.673553 ==
5873 16:47:32.676385 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 16:47:32.682316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 16:47:32.682742 ==
5876 16:47:32.683077 RX Vref Scan: 0
5877 16:47:32.683422
5878 16:47:32.685864 RX Vref 0 -> 0, step: 1
5879 16:47:32.686395
5880 16:47:32.689029 RX Delay -61 -> 252, step: 4
5881 16:47:32.692073 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5882 16:47:32.699122 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5883 16:47:32.702486 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5884 16:47:32.705539 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5885 16:47:32.708612 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5886 16:47:32.712205 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5887 16:47:32.715854 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5888 16:47:32.722053 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5889 16:47:32.725561 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5890 16:47:32.728500 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5891 16:47:32.731754 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5892 16:47:32.735454 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5893 16:47:32.741728 iDelay=199, Bit 12, Center 102 (15 ~ 190) 176
5894 16:47:32.744807 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5895 16:47:32.748488 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5896 16:47:32.751677 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5897 16:47:32.752196 ==
5898 16:47:32.754719 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 16:47:32.761268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 16:47:32.761824 ==
5901 16:47:32.762165 DQS Delay:
5902 16:47:32.765022 DQS0 = 0, DQS1 = 0
5903 16:47:32.765444 DQM Delay:
5904 16:47:32.765903 DQM0 = 97, DQM1 = 92
5905 16:47:32.767655 DQ Delay:
5906 16:47:32.770993 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =92
5907 16:47:32.774849 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5908 16:47:32.777567 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5909 16:47:32.780921 DQ12 =102, DQ13 =100, DQ14 =96, DQ15 =100
5910 16:47:32.781362
5911 16:47:32.781692
5912 16:47:32.788465 [DQSOSCAuto] RK1, (LSB)MR18= 0xf26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 417 ps
5913 16:47:32.790787 CH1 RK1: MR19=505, MR18=F26
5914 16:47:32.797146 CH1_RK1: MR19=0x505, MR18=0xF26, DQSOSC=409, MR23=63, INC=64, DEC=43
5915 16:47:32.800486 [RxdqsGatingPostProcess] freq 933
5916 16:47:32.807615 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5917 16:47:32.808047 best DQS0 dly(2T, 0.5T) = (0, 10)
5918 16:47:32.810453 best DQS1 dly(2T, 0.5T) = (0, 10)
5919 16:47:32.813752 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5920 16:47:32.817181 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5921 16:47:32.820470 best DQS0 dly(2T, 0.5T) = (0, 10)
5922 16:47:32.823992 best DQS1 dly(2T, 0.5T) = (0, 10)
5923 16:47:32.827611 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5924 16:47:32.830448 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5925 16:47:32.833620 Pre-setting of DQS Precalculation
5926 16:47:32.840005 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5927 16:47:32.847309 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5928 16:47:32.853840 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5929 16:47:32.854369
5930 16:47:32.854704
5931 16:47:32.856844 [Calibration Summary] 1866 Mbps
5932 16:47:32.857365 CH 0, Rank 0
5933 16:47:32.859708 SW Impedance : PASS
5934 16:47:32.863345 DUTY Scan : NO K
5935 16:47:32.863764 ZQ Calibration : PASS
5936 16:47:32.866388 Jitter Meter : NO K
5937 16:47:32.869841 CBT Training : PASS
5938 16:47:32.870358 Write leveling : PASS
5939 16:47:32.873463 RX DQS gating : PASS
5940 16:47:32.876168 RX DQ/DQS(RDDQC) : PASS
5941 16:47:32.876591 TX DQ/DQS : PASS
5942 16:47:32.879773 RX DATLAT : PASS
5943 16:47:32.883253 RX DQ/DQS(Engine): PASS
5944 16:47:32.883895 TX OE : NO K
5945 16:47:32.886083 All Pass.
5946 16:47:32.886599
5947 16:47:32.886931 CH 0, Rank 1
5948 16:47:32.889382 SW Impedance : PASS
5949 16:47:32.889803 DUTY Scan : NO K
5950 16:47:32.892548 ZQ Calibration : PASS
5951 16:47:32.895777 Jitter Meter : NO K
5952 16:47:32.896308 CBT Training : PASS
5953 16:47:32.899296 Write leveling : PASS
5954 16:47:32.902694 RX DQS gating : PASS
5955 16:47:32.903253 RX DQ/DQS(RDDQC) : PASS
5956 16:47:32.906079 TX DQ/DQS : PASS
5957 16:47:32.906602 RX DATLAT : PASS
5958 16:47:32.909433 RX DQ/DQS(Engine): PASS
5959 16:47:32.912928 TX OE : NO K
5960 16:47:32.913454 All Pass.
5961 16:47:32.913785
5962 16:47:32.916087 CH 1, Rank 0
5963 16:47:32.916603 SW Impedance : PASS
5964 16:47:32.919404 DUTY Scan : NO K
5965 16:47:32.919928 ZQ Calibration : PASS
5966 16:47:32.923204 Jitter Meter : NO K
5967 16:47:32.925586 CBT Training : PASS
5968 16:47:32.926006 Write leveling : PASS
5969 16:47:32.928853 RX DQS gating : PASS
5970 16:47:32.932512 RX DQ/DQS(RDDQC) : PASS
5971 16:47:32.933034 TX DQ/DQS : PASS
5972 16:47:32.935823 RX DATLAT : PASS
5973 16:47:32.938822 RX DQ/DQS(Engine): PASS
5974 16:47:32.939368 TX OE : NO K
5975 16:47:32.942511 All Pass.
5976 16:47:32.943056
5977 16:47:32.943445 CH 1, Rank 1
5978 16:47:32.945560 SW Impedance : PASS
5979 16:47:32.946081 DUTY Scan : NO K
5980 16:47:32.948528 ZQ Calibration : PASS
5981 16:47:32.952091 Jitter Meter : NO K
5982 16:47:32.952513 CBT Training : PASS
5983 16:47:32.955260 Write leveling : PASS
5984 16:47:32.958334 RX DQS gating : PASS
5985 16:47:32.958752 RX DQ/DQS(RDDQC) : PASS
5986 16:47:32.961859 TX DQ/DQS : PASS
5987 16:47:32.965065 RX DATLAT : PASS
5988 16:47:32.965680 RX DQ/DQS(Engine): PASS
5989 16:47:32.968497 TX OE : NO K
5990 16:47:32.968915 All Pass.
5991 16:47:32.969242
5992 16:47:32.971739 DramC Write-DBI off
5993 16:47:32.975247 PER_BANK_REFRESH: Hybrid Mode
5994 16:47:32.975662 TX_TRACKING: ON
5995 16:47:32.985028 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5996 16:47:32.988908 [FAST_K] Save calibration result to emmc
5997 16:47:32.991776 dramc_set_vcore_voltage set vcore to 650000
5998 16:47:32.994899 Read voltage for 400, 6
5999 16:47:32.995458 Vio18 = 0
6000 16:47:32.995797 Vcore = 650000
6001 16:47:32.998593 Vdram = 0
6002 16:47:32.999008 Vddq = 0
6003 16:47:32.999370 Vmddr = 0
6004 16:47:33.005220 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6005 16:47:33.007995 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6006 16:47:33.011428 MEM_TYPE=3, freq_sel=20
6007 16:47:33.014915 sv_algorithm_assistance_LP4_800
6008 16:47:33.017825 ============ PULL DRAM RESETB DOWN ============
6009 16:47:33.021314 ========== PULL DRAM RESETB DOWN end =========
6010 16:47:33.027790 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6011 16:47:33.031127 ===================================
6012 16:47:33.034168 LPDDR4 DRAM CONFIGURATION
6013 16:47:33.038274 ===================================
6014 16:47:33.038762 EX_ROW_EN[0] = 0x0
6015 16:47:33.040513 EX_ROW_EN[1] = 0x0
6016 16:47:33.041069 LP4Y_EN = 0x0
6017 16:47:33.044045 WORK_FSP = 0x0
6018 16:47:33.044458 WL = 0x2
6019 16:47:33.047297 RL = 0x2
6020 16:47:33.047710 BL = 0x2
6021 16:47:33.050671 RPST = 0x0
6022 16:47:33.051084 RD_PRE = 0x0
6023 16:47:33.053981 WR_PRE = 0x1
6024 16:47:33.057069 WR_PST = 0x0
6025 16:47:33.057569 DBI_WR = 0x0
6026 16:47:33.060816 DBI_RD = 0x0
6027 16:47:33.061409 OTF = 0x1
6028 16:47:33.063628 ===================================
6029 16:47:33.066893 ===================================
6030 16:47:33.070255 ANA top config
6031 16:47:33.073065 ===================================
6032 16:47:33.073605 DLL_ASYNC_EN = 0
6033 16:47:33.076569 ALL_SLAVE_EN = 1
6034 16:47:33.080255 NEW_RANK_MODE = 1
6035 16:47:33.083243 DLL_IDLE_MODE = 1
6036 16:47:33.086776 LP45_APHY_COMB_EN = 1
6037 16:47:33.087372 TX_ODT_DIS = 1
6038 16:47:33.089699 NEW_8X_MODE = 1
6039 16:47:33.093006 ===================================
6040 16:47:33.096305 ===================================
6041 16:47:33.099843 data_rate = 800
6042 16:47:33.103319 CKR = 1
6043 16:47:33.106659 DQ_P2S_RATIO = 4
6044 16:47:33.113930 ===================================
6045 16:47:33.114827 CA_P2S_RATIO = 4
6046 16:47:33.115344 DQ_CA_OPEN = 0
6047 16:47:33.116010 DQ_SEMI_OPEN = 1
6048 16:47:33.119702 CA_SEMI_OPEN = 1
6049 16:47:33.122367 CA_FULL_RATE = 0
6050 16:47:33.125983 DQ_CKDIV4_EN = 0
6051 16:47:33.129253 CA_CKDIV4_EN = 1
6052 16:47:33.129677 CA_PREDIV_EN = 0
6053 16:47:33.132183 PH8_DLY = 0
6054 16:47:33.135572 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6055 16:47:33.138948 DQ_AAMCK_DIV = 0
6056 16:47:33.141955 CA_AAMCK_DIV = 0
6057 16:47:33.145438 CA_ADMCK_DIV = 4
6058 16:47:33.145865 DQ_TRACK_CA_EN = 0
6059 16:47:33.149078 CA_PICK = 800
6060 16:47:33.152494 CA_MCKIO = 400
6061 16:47:33.156051 MCKIO_SEMI = 400
6062 16:47:33.159033 PLL_FREQ = 3016
6063 16:47:33.162112 DQ_UI_PI_RATIO = 32
6064 16:47:33.165187 CA_UI_PI_RATIO = 32
6065 16:47:33.168732 ===================================
6066 16:47:33.171817 ===================================
6067 16:47:33.171901 memory_type:LPDDR4
6068 16:47:33.174928 GP_NUM : 10
6069 16:47:33.178123 SRAM_EN : 1
6070 16:47:33.178205 MD32_EN : 0
6071 16:47:33.181681 ===================================
6072 16:47:33.184729 [ANA_INIT] >>>>>>>>>>>>>>
6073 16:47:33.188459 <<<<<< [CONFIGURE PHASE]: ANA_TX
6074 16:47:33.192271 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6075 16:47:33.195021 ===================================
6076 16:47:33.198134 data_rate = 800,PCW = 0X7400
6077 16:47:33.201925 ===================================
6078 16:47:33.204999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6079 16:47:33.208325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6080 16:47:33.221679 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6081 16:47:33.224994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6082 16:47:33.228220 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6083 16:47:33.231371 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6084 16:47:33.235158 [ANA_INIT] flow start
6085 16:47:33.237690 [ANA_INIT] PLL >>>>>>>>
6086 16:47:33.238144 [ANA_INIT] PLL <<<<<<<<
6087 16:47:33.241511 [ANA_INIT] MIDPI >>>>>>>>
6088 16:47:33.244427 [ANA_INIT] MIDPI <<<<<<<<
6089 16:47:33.248102 [ANA_INIT] DLL >>>>>>>>
6090 16:47:33.248623 [ANA_INIT] flow end
6091 16:47:33.251594 ============ LP4 DIFF to SE enter ============
6092 16:47:33.257556 ============ LP4 DIFF to SE exit ============
6093 16:47:33.257993 [ANA_INIT] <<<<<<<<<<<<<
6094 16:47:33.261221 [Flow] Enable top DCM control >>>>>
6095 16:47:33.264310 [Flow] Enable top DCM control <<<<<
6096 16:47:33.267763 Enable DLL master slave shuffle
6097 16:47:33.274316 ==============================================================
6098 16:47:33.274742 Gating Mode config
6099 16:47:33.281025 ==============================================================
6100 16:47:33.283731 Config description:
6101 16:47:33.294177 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6102 16:47:33.300583 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6103 16:47:33.303793 SELPH_MODE 0: By rank 1: By Phase
6104 16:47:33.310091 ==============================================================
6105 16:47:33.313183 GAT_TRACK_EN = 0
6106 16:47:33.316705 RX_GATING_MODE = 2
6107 16:47:33.320158 RX_GATING_TRACK_MODE = 2
6108 16:47:33.324569 SELPH_MODE = 1
6109 16:47:33.325089 PICG_EARLY_EN = 1
6110 16:47:33.326982 VALID_LAT_VALUE = 1
6111 16:47:33.333424 ==============================================================
6112 16:47:33.336641 Enter into Gating configuration >>>>
6113 16:47:33.340010 Exit from Gating configuration <<<<
6114 16:47:33.342793 Enter into DVFS_PRE_config >>>>>
6115 16:47:33.352524 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6116 16:47:33.355975 Exit from DVFS_PRE_config <<<<<
6117 16:47:33.359446 Enter into PICG configuration >>>>
6118 16:47:33.363007 Exit from PICG configuration <<<<
6119 16:47:33.365810 [RX_INPUT] configuration >>>>>
6120 16:47:33.369540 [RX_INPUT] configuration <<<<<
6121 16:47:33.375762 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6122 16:47:33.379250 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6123 16:47:33.385882 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6124 16:47:33.392431 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6125 16:47:33.398630 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6126 16:47:33.406190 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6127 16:47:33.409014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6128 16:47:33.412149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6129 16:47:33.415606 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6130 16:47:33.421946 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6131 16:47:33.425094 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6132 16:47:33.428446 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6133 16:47:33.431771 ===================================
6134 16:47:33.435483 LPDDR4 DRAM CONFIGURATION
6135 16:47:33.438165 ===================================
6136 16:47:33.442283 EX_ROW_EN[0] = 0x0
6137 16:47:33.442709 EX_ROW_EN[1] = 0x0
6138 16:47:33.445151 LP4Y_EN = 0x0
6139 16:47:33.445575 WORK_FSP = 0x0
6140 16:47:33.448606 WL = 0x2
6141 16:47:33.449130 RL = 0x2
6142 16:47:33.451979 BL = 0x2
6143 16:47:33.452403 RPST = 0x0
6144 16:47:33.454939 RD_PRE = 0x0
6145 16:47:33.455417 WR_PRE = 0x1
6146 16:47:33.458233 WR_PST = 0x0
6147 16:47:33.458658 DBI_WR = 0x0
6148 16:47:33.461663 DBI_RD = 0x0
6149 16:47:33.462087 OTF = 0x1
6150 16:47:33.464473 ===================================
6151 16:47:33.471287 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6152 16:47:33.474824 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6153 16:47:33.478263 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6154 16:47:33.481707 ===================================
6155 16:47:33.484205 LPDDR4 DRAM CONFIGURATION
6156 16:47:33.487686 ===================================
6157 16:47:33.491203 EX_ROW_EN[0] = 0x10
6158 16:47:33.491730 EX_ROW_EN[1] = 0x0
6159 16:47:33.494422 LP4Y_EN = 0x0
6160 16:47:33.494941 WORK_FSP = 0x0
6161 16:47:33.497468 WL = 0x2
6162 16:47:33.497891 RL = 0x2
6163 16:47:33.500707 BL = 0x2
6164 16:47:33.501233 RPST = 0x0
6165 16:47:33.503979 RD_PRE = 0x0
6166 16:47:33.504514 WR_PRE = 0x1
6167 16:47:33.508249 WR_PST = 0x0
6168 16:47:33.508778 DBI_WR = 0x0
6169 16:47:33.510722 DBI_RD = 0x0
6170 16:47:33.514470 OTF = 0x1
6171 16:47:33.517346 ===================================
6172 16:47:33.521084 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6173 16:47:33.525863 nWR fixed to 30
6174 16:47:33.529496 [ModeRegInit_LP4] CH0 RK0
6175 16:47:33.530020 [ModeRegInit_LP4] CH0 RK1
6176 16:47:33.532290 [ModeRegInit_LP4] CH1 RK0
6177 16:47:33.535699 [ModeRegInit_LP4] CH1 RK1
6178 16:47:33.536218 match AC timing 19
6179 16:47:33.542597 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6180 16:47:33.545821 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6181 16:47:33.548740 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6182 16:47:33.555595 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6183 16:47:33.558882 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6184 16:47:33.559441 ==
6185 16:47:33.562170 Dram Type= 6, Freq= 0, CH_0, rank 0
6186 16:47:33.565218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6187 16:47:33.565783 ==
6188 16:47:33.571952 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6189 16:47:33.578564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6190 16:47:33.581829 [CA 0] Center 36 (8~64) winsize 57
6191 16:47:33.585246 [CA 1] Center 36 (8~64) winsize 57
6192 16:47:33.587779 [CA 2] Center 36 (8~64) winsize 57
6193 16:47:33.591360 [CA 3] Center 36 (8~64) winsize 57
6194 16:47:33.594642 [CA 4] Center 36 (8~64) winsize 57
6195 16:47:33.598002 [CA 5] Center 36 (8~64) winsize 57
6196 16:47:33.598417
6197 16:47:33.602134 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6198 16:47:33.602633
6199 16:47:33.604256 [CATrainingPosCal] consider 1 rank data
6200 16:47:33.607518 u2DelayCellTimex100 = 270/100 ps
6201 16:47:33.611088 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6202 16:47:33.615047 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6203 16:47:33.617713 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6204 16:47:33.621466 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6205 16:47:33.623987 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6206 16:47:33.627828 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6207 16:47:33.628350
6208 16:47:33.634221 CA PerBit enable=1, Macro0, CA PI delay=36
6209 16:47:33.634642
6210 16:47:33.636974 [CBTSetCACLKResult] CA Dly = 36
6211 16:47:33.637419 CS Dly: 1 (0~32)
6212 16:47:33.637837 ==
6213 16:47:33.640650 Dram Type= 6, Freq= 0, CH_0, rank 1
6214 16:47:33.643923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6215 16:47:33.644493 ==
6216 16:47:33.650791 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6217 16:47:33.656732 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6218 16:47:33.660293 [CA 0] Center 36 (8~64) winsize 57
6219 16:47:33.663598 [CA 1] Center 36 (8~64) winsize 57
6220 16:47:33.666822 [CA 2] Center 36 (8~64) winsize 57
6221 16:47:33.670321 [CA 3] Center 36 (8~64) winsize 57
6222 16:47:33.673391 [CA 4] Center 36 (8~64) winsize 57
6223 16:47:33.677022 [CA 5] Center 36 (8~64) winsize 57
6224 16:47:33.677442
6225 16:47:33.680058 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6226 16:47:33.680475
6227 16:47:33.683247 [CATrainingPosCal] consider 2 rank data
6228 16:47:33.686905 u2DelayCellTimex100 = 270/100 ps
6229 16:47:33.689788 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 16:47:33.693244 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 16:47:33.696410 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6232 16:47:33.700471 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6233 16:47:33.703280 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6234 16:47:33.706307 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6235 16:47:33.706887
6236 16:47:33.713244 CA PerBit enable=1, Macro0, CA PI delay=36
6237 16:47:33.713810
6238 16:47:33.714171 [CBTSetCACLKResult] CA Dly = 36
6239 16:47:33.716182 CS Dly: 1 (0~32)
6240 16:47:33.716658
6241 16:47:33.719868 ----->DramcWriteLeveling(PI) begin...
6242 16:47:33.720304 ==
6243 16:47:33.723095 Dram Type= 6, Freq= 0, CH_0, rank 0
6244 16:47:33.726263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6245 16:47:33.726689 ==
6246 16:47:33.729757 Write leveling (Byte 0): 40 => 8
6247 16:47:33.732640 Write leveling (Byte 1): 40 => 8
6248 16:47:33.736069 DramcWriteLeveling(PI) end<-----
6249 16:47:33.736625
6250 16:47:33.737078 ==
6251 16:47:33.739569 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 16:47:33.742826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 16:47:33.745533 ==
6254 16:47:33.745614 [Gating] SW mode calibration
6255 16:47:33.755772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6256 16:47:33.758770 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6257 16:47:33.762872 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6258 16:47:33.769273 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6259 16:47:33.772347 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6260 16:47:33.775918 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6261 16:47:33.782268 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6262 16:47:33.785625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6263 16:47:33.788616 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6264 16:47:33.795098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6265 16:47:33.798718 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6266 16:47:33.801552 Total UI for P1: 0, mck2ui 16
6267 16:47:33.805277 best dqsien dly found for B0: ( 0, 14, 24)
6268 16:47:33.808573 Total UI for P1: 0, mck2ui 16
6269 16:47:33.811585 best dqsien dly found for B1: ( 0, 14, 24)
6270 16:47:33.814985 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6271 16:47:33.818590 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6272 16:47:33.818927
6273 16:47:33.821538 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6274 16:47:33.828643 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6275 16:47:33.829236 [Gating] SW calibration Done
6276 16:47:33.829748 ==
6277 16:47:33.831495 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 16:47:33.838168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 16:47:33.838619 ==
6280 16:47:33.838971 RX Vref Scan: 0
6281 16:47:33.839341
6282 16:47:33.841748 RX Vref 0 -> 0, step: 1
6283 16:47:33.842292
6284 16:47:33.844885 RX Delay -410 -> 252, step: 16
6285 16:47:33.847805 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6286 16:47:33.851223 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6287 16:47:33.858305 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6288 16:47:33.861427 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6289 16:47:33.864836 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6290 16:47:33.867790 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6291 16:47:33.874167 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6292 16:47:33.877386 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6293 16:47:33.880770 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6294 16:47:33.887456 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6295 16:47:33.890766 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6296 16:47:33.894265 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6297 16:47:33.897158 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6298 16:47:33.903787 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6299 16:47:33.907454 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6300 16:47:33.910630 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6301 16:47:33.911137 ==
6302 16:47:33.913655 Dram Type= 6, Freq= 0, CH_0, rank 0
6303 16:47:33.920079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6304 16:47:33.920541 ==
6305 16:47:33.920954 DQS Delay:
6306 16:47:33.923621 DQS0 = 35, DQS1 = 51
6307 16:47:33.924195 DQM Delay:
6308 16:47:33.924753 DQM0 = 4, DQM1 = 10
6309 16:47:33.926931 DQ Delay:
6310 16:47:33.930199 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6311 16:47:33.930686 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6312 16:47:33.933971 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6313 16:47:33.937115 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6314 16:47:33.937723
6315 16:47:33.938432
6316 16:47:33.940126 ==
6317 16:47:33.943125 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 16:47:33.946596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 16:47:33.947249 ==
6320 16:47:33.947862
6321 16:47:33.948372
6322 16:47:33.950126 TX Vref Scan disable
6323 16:47:33.950814 == TX Byte 0 ==
6324 16:47:33.953063 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6325 16:47:33.959543 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6326 16:47:33.959657 == TX Byte 1 ==
6327 16:47:33.962616 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6328 16:47:33.969642 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6329 16:47:33.969749 ==
6330 16:47:33.972904 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 16:47:33.975804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 16:47:33.975889 ==
6333 16:47:33.975964
6334 16:47:33.976025
6335 16:47:33.979572 TX Vref Scan disable
6336 16:47:33.979663 == TX Byte 0 ==
6337 16:47:33.985676 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 16:47:33.988988 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 16:47:33.989086 == TX Byte 1 ==
6340 16:47:33.995507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 16:47:33.999053 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 16:47:33.999145
6343 16:47:33.999229 [DATLAT]
6344 16:47:34.002511 Freq=400, CH0 RK0
6345 16:47:34.002623
6346 16:47:34.002699 DATLAT Default: 0xf
6347 16:47:34.005839 0, 0xFFFF, sum = 0
6348 16:47:34.006019 1, 0xFFFF, sum = 0
6349 16:47:34.008995 2, 0xFFFF, sum = 0
6350 16:47:34.009183 3, 0xFFFF, sum = 0
6351 16:47:34.012213 4, 0xFFFF, sum = 0
6352 16:47:34.012381 5, 0xFFFF, sum = 0
6353 16:47:34.015739 6, 0xFFFF, sum = 0
6354 16:47:34.015928 7, 0xFFFF, sum = 0
6355 16:47:34.019015 8, 0xFFFF, sum = 0
6356 16:47:34.019242 9, 0xFFFF, sum = 0
6357 16:47:34.022394 10, 0xFFFF, sum = 0
6358 16:47:34.022629 11, 0xFFFF, sum = 0
6359 16:47:34.025743 12, 0xFFFF, sum = 0
6360 16:47:34.029060 13, 0x0, sum = 1
6361 16:47:34.029319 14, 0x0, sum = 2
6362 16:47:34.029462 15, 0x0, sum = 3
6363 16:47:34.032242 16, 0x0, sum = 4
6364 16:47:34.032592 best_step = 14
6365 16:47:34.032830
6366 16:47:34.035386 ==
6367 16:47:34.035625 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 16:47:34.041968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 16:47:34.042205 ==
6370 16:47:34.042390 RX Vref Scan: 1
6371 16:47:34.042605
6372 16:47:34.045153 RX Vref 0 -> 0, step: 1
6373 16:47:34.045451
6374 16:47:34.048638 RX Delay -343 -> 252, step: 8
6375 16:47:34.049058
6376 16:47:34.052179 Set Vref, RX VrefLevel [Byte0]: 58
6377 16:47:34.054926 [Byte1]: 49
6378 16:47:34.059303
6379 16:47:34.059725 Final RX Vref Byte 0 = 58 to rank0
6380 16:47:34.062266 Final RX Vref Byte 1 = 49 to rank0
6381 16:47:34.065445 Final RX Vref Byte 0 = 58 to rank1
6382 16:47:34.068716 Final RX Vref Byte 1 = 49 to rank1==
6383 16:47:34.071838 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 16:47:34.078737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 16:47:34.079305 ==
6386 16:47:34.079649 DQS Delay:
6387 16:47:34.082398 DQS0 = 44, DQS1 = 56
6388 16:47:34.082948 DQM Delay:
6389 16:47:34.083350 DQM0 = 11, DQM1 = 14
6390 16:47:34.085369 DQ Delay:
6391 16:47:34.088384 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6392 16:47:34.092313 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6393 16:47:34.092866 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6394 16:47:34.098652 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6395 16:47:34.099220
6396 16:47:34.099558
6397 16:47:34.105758 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6398 16:47:34.108321 CH0 RK0: MR19=C0C, MR18=8C80
6399 16:47:34.115063 CH0_RK0: MR19=0xC0C, MR18=0x8C80, DQSOSC=392, MR23=63, INC=384, DEC=256
6400 16:47:34.115627 ==
6401 16:47:34.118467 Dram Type= 6, Freq= 0, CH_0, rank 1
6402 16:47:34.121456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 16:47:34.121987 ==
6404 16:47:34.124768 [Gating] SW mode calibration
6405 16:47:34.131688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6406 16:47:34.137638 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6407 16:47:34.140890 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6408 16:47:34.144571 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6409 16:47:34.152378 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 16:47:34.155085 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6411 16:47:34.157966 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6412 16:47:34.164559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6413 16:47:34.167761 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6414 16:47:34.170441 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6415 16:47:34.177255 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6416 16:47:34.180804 Total UI for P1: 0, mck2ui 16
6417 16:47:34.183702 best dqsien dly found for B0: ( 0, 14, 24)
6418 16:47:34.187515 Total UI for P1: 0, mck2ui 16
6419 16:47:34.191383 best dqsien dly found for B1: ( 0, 14, 24)
6420 16:47:34.194602 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6421 16:47:34.197075 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6422 16:47:34.197668
6423 16:47:34.199862 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6424 16:47:34.203661 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6425 16:47:34.206872 [Gating] SW calibration Done
6426 16:47:34.207488 ==
6427 16:47:34.210347 Dram Type= 6, Freq= 0, CH_0, rank 1
6428 16:47:34.213451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 16:47:34.216472 ==
6430 16:47:34.217046 RX Vref Scan: 0
6431 16:47:34.217423
6432 16:47:34.220111 RX Vref 0 -> 0, step: 1
6433 16:47:34.220694
6434 16:47:34.223240 RX Delay -410 -> 252, step: 16
6435 16:47:34.226901 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6436 16:47:34.229774 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6437 16:47:34.233303 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6438 16:47:34.239684 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6439 16:47:34.243579 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6440 16:47:34.246190 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6441 16:47:34.249866 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6442 16:47:34.256246 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6443 16:47:34.259826 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6444 16:47:34.262898 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6445 16:47:34.266152 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6446 16:47:34.272502 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6447 16:47:34.276557 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6448 16:47:34.280058 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6449 16:47:34.286381 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6450 16:47:34.289346 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6451 16:47:34.289775 ==
6452 16:47:34.292663 Dram Type= 6, Freq= 0, CH_0, rank 1
6453 16:47:34.295835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 16:47:34.296264 ==
6455 16:47:34.299769 DQS Delay:
6456 16:47:34.300302 DQS0 = 35, DQS1 = 59
6457 16:47:34.300640 DQM Delay:
6458 16:47:34.302672 DQM0 = 7, DQM1 = 17
6459 16:47:34.303227 DQ Delay:
6460 16:47:34.306121 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6461 16:47:34.309858 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6462 16:47:34.312758 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6463 16:47:34.316034 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6464 16:47:34.316462
6465 16:47:34.316795
6466 16:47:34.317105 ==
6467 16:47:34.319055 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 16:47:34.322907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 16:47:34.325296 ==
6470 16:47:34.325786
6471 16:47:34.326164
6472 16:47:34.326493 TX Vref Scan disable
6473 16:47:34.328994 == TX Byte 0 ==
6474 16:47:34.331760 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6475 16:47:34.335433 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6476 16:47:34.338464 == TX Byte 1 ==
6477 16:47:34.342212 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6478 16:47:34.345338 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6479 16:47:34.345818 ==
6480 16:47:34.348514 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 16:47:34.354686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 16:47:34.354767 ==
6483 16:47:34.354831
6484 16:47:34.354891
6485 16:47:34.358418 TX Vref Scan disable
6486 16:47:34.358519 == TX Byte 0 ==
6487 16:47:34.361595 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6488 16:47:34.367640 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6489 16:47:34.367721 == TX Byte 1 ==
6490 16:47:34.371357 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6491 16:47:34.377924 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6492 16:47:34.378013
6493 16:47:34.378081 [DATLAT]
6494 16:47:34.378145 Freq=400, CH0 RK1
6495 16:47:34.378206
6496 16:47:34.381269 DATLAT Default: 0xe
6497 16:47:34.384542 0, 0xFFFF, sum = 0
6498 16:47:34.384637 1, 0xFFFF, sum = 0
6499 16:47:34.387778 2, 0xFFFF, sum = 0
6500 16:47:34.387880 3, 0xFFFF, sum = 0
6501 16:47:34.390708 4, 0xFFFF, sum = 0
6502 16:47:34.390809 5, 0xFFFF, sum = 0
6503 16:47:34.394244 6, 0xFFFF, sum = 0
6504 16:47:34.394355 7, 0xFFFF, sum = 0
6505 16:47:34.397700 8, 0xFFFF, sum = 0
6506 16:47:34.397823 9, 0xFFFF, sum = 0
6507 16:47:34.401320 10, 0xFFFF, sum = 0
6508 16:47:34.401442 11, 0xFFFF, sum = 0
6509 16:47:34.404007 12, 0xFFFF, sum = 0
6510 16:47:34.404090 13, 0x0, sum = 1
6511 16:47:34.407650 14, 0x0, sum = 2
6512 16:47:34.407731 15, 0x0, sum = 3
6513 16:47:34.410851 16, 0x0, sum = 4
6514 16:47:34.410933 best_step = 14
6515 16:47:34.410996
6516 16:47:34.411054 ==
6517 16:47:34.414825 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 16:47:34.420475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 16:47:34.420551 ==
6520 16:47:34.420620 RX Vref Scan: 0
6521 16:47:34.420680
6522 16:47:34.424058 RX Vref 0 -> 0, step: 1
6523 16:47:34.424123
6524 16:47:34.427222 RX Delay -359 -> 252, step: 8
6525 16:47:34.434155 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6526 16:47:34.436915 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6527 16:47:34.441164 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6528 16:47:34.443735 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6529 16:47:34.450066 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6530 16:47:34.453443 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6531 16:47:34.457166 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6532 16:47:34.460150 iDelay=217, Bit 7, Center -24 (-263 ~ 216) 480
6533 16:47:34.466777 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6534 16:47:34.470003 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6535 16:47:34.473830 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6536 16:47:34.477133 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6537 16:47:34.483051 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6538 16:47:34.486621 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6539 16:47:34.490036 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6540 16:47:34.496499 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6541 16:47:34.496649 ==
6542 16:47:34.500131 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 16:47:34.503223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 16:47:34.503361 ==
6545 16:47:34.503468 DQS Delay:
6546 16:47:34.506165 DQS0 = 44, DQS1 = 60
6547 16:47:34.506301 DQM Delay:
6548 16:47:34.509409 DQM0 = 10, DQM1 = 15
6549 16:47:34.509563 DQ Delay:
6550 16:47:34.512687 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6551 16:47:34.516465 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6552 16:47:34.519793 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6553 16:47:34.522758 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6554 16:47:34.523001
6555 16:47:34.523213
6556 16:47:34.529545 [DQSOSCAuto] RK1, (LSB)MR18= 0x7e76, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6557 16:47:34.532989 CH0 RK1: MR19=C0C, MR18=7E76
6558 16:47:34.539580 CH0_RK1: MR19=0xC0C, MR18=0x7E76, DQSOSC=393, MR23=63, INC=382, DEC=254
6559 16:47:34.542733 [RxdqsGatingPostProcess] freq 400
6560 16:47:34.549298 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6561 16:47:34.552855 best DQS0 dly(2T, 0.5T) = (0, 10)
6562 16:47:34.556030 best DQS1 dly(2T, 0.5T) = (0, 10)
6563 16:47:34.559517 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6564 16:47:34.562839 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6565 16:47:34.566212 best DQS0 dly(2T, 0.5T) = (0, 10)
6566 16:47:34.566599 best DQS1 dly(2T, 0.5T) = (0, 10)
6567 16:47:34.568704 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6568 16:47:34.572219 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6569 16:47:34.575953 Pre-setting of DQS Precalculation
6570 16:47:34.581997 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6571 16:47:34.582527 ==
6572 16:47:34.585213 Dram Type= 6, Freq= 0, CH_1, rank 0
6573 16:47:34.588362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 16:47:34.588786 ==
6575 16:47:34.595066 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6576 16:47:34.602166 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6577 16:47:34.604918 [CA 0] Center 36 (8~64) winsize 57
6578 16:47:34.608025 [CA 1] Center 36 (8~64) winsize 57
6579 16:47:34.611668 [CA 2] Center 36 (8~64) winsize 57
6580 16:47:34.611742 [CA 3] Center 36 (8~64) winsize 57
6581 16:47:34.614817 [CA 4] Center 36 (8~64) winsize 57
6582 16:47:34.618023 [CA 5] Center 36 (8~64) winsize 57
6583 16:47:34.618095
6584 16:47:34.624623 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6585 16:47:34.624705
6586 16:47:34.627997 [CATrainingPosCal] consider 1 rank data
6587 16:47:34.631204 u2DelayCellTimex100 = 270/100 ps
6588 16:47:34.634827 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6589 16:47:34.638176 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6590 16:47:34.641624 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6591 16:47:34.644187 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6592 16:47:34.647980 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6593 16:47:34.651168 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6594 16:47:34.651286
6595 16:47:34.654399 CA PerBit enable=1, Macro0, CA PI delay=36
6596 16:47:34.654480
6597 16:47:34.657613 [CBTSetCACLKResult] CA Dly = 36
6598 16:47:34.661261 CS Dly: 1 (0~32)
6599 16:47:34.661372 ==
6600 16:47:34.664973 Dram Type= 6, Freq= 0, CH_1, rank 1
6601 16:47:34.667347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 16:47:34.667429 ==
6603 16:47:34.673751 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6604 16:47:34.680559 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6605 16:47:34.683753 [CA 0] Center 36 (8~64) winsize 57
6606 16:47:34.687079 [CA 1] Center 36 (8~64) winsize 57
6607 16:47:34.690955 [CA 2] Center 36 (8~64) winsize 57
6608 16:47:34.691090 [CA 3] Center 36 (8~64) winsize 57
6609 16:47:34.693440 [CA 4] Center 36 (8~64) winsize 57
6610 16:47:34.696988 [CA 5] Center 36 (8~64) winsize 57
6611 16:47:34.697099
6612 16:47:34.703518 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6613 16:47:34.703640
6614 16:47:34.707051 [CATrainingPosCal] consider 2 rank data
6615 16:47:34.710419 u2DelayCellTimex100 = 270/100 ps
6616 16:47:34.713021 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 16:47:34.716864 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 16:47:34.720290 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6619 16:47:34.723033 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6620 16:47:34.726938 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6621 16:47:34.730026 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6622 16:47:34.730266
6623 16:47:34.733237 CA PerBit enable=1, Macro0, CA PI delay=36
6624 16:47:34.733535
6625 16:47:34.736903 [CBTSetCACLKResult] CA Dly = 36
6626 16:47:34.740190 CS Dly: 1 (0~32)
6627 16:47:34.740575
6628 16:47:34.743152 ----->DramcWriteLeveling(PI) begin...
6629 16:47:34.743570 ==
6630 16:47:34.746430 Dram Type= 6, Freq= 0, CH_1, rank 0
6631 16:47:34.749702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6632 16:47:34.750091 ==
6633 16:47:34.753023 Write leveling (Byte 0): 40 => 8
6634 16:47:34.756749 Write leveling (Byte 1): 40 => 8
6635 16:47:34.759891 DramcWriteLeveling(PI) end<-----
6636 16:47:34.760273
6637 16:47:34.760577 ==
6638 16:47:34.763087 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 16:47:34.766508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 16:47:34.766895 ==
6641 16:47:34.770091 [Gating] SW mode calibration
6642 16:47:34.776302 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6643 16:47:34.782822 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6644 16:47:34.786058 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6645 16:47:34.794108 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6646 16:47:34.796030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6647 16:47:34.799572 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6648 16:47:34.806000 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6649 16:47:34.810230 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6650 16:47:34.812637 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6651 16:47:34.819419 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6652 16:47:34.822506 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6653 16:47:34.825926 Total UI for P1: 0, mck2ui 16
6654 16:47:34.829273 best dqsien dly found for B0: ( 0, 14, 24)
6655 16:47:34.832125 Total UI for P1: 0, mck2ui 16
6656 16:47:34.835896 best dqsien dly found for B1: ( 0, 14, 24)
6657 16:47:34.838986 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6658 16:47:34.841873 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6659 16:47:34.842413
6660 16:47:34.845445 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6661 16:47:34.849479 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6662 16:47:34.851527 [Gating] SW calibration Done
6663 16:47:34.852082 ==
6664 16:47:34.855209 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 16:47:34.861854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 16:47:34.862255 ==
6667 16:47:34.862555 RX Vref Scan: 0
6668 16:47:34.862833
6669 16:47:34.864710 RX Vref 0 -> 0, step: 1
6670 16:47:34.865235
6671 16:47:34.868428 RX Delay -410 -> 252, step: 16
6672 16:47:34.871613 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6673 16:47:34.874774 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6674 16:47:34.881457 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6675 16:47:34.885096 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6676 16:47:34.888450 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6677 16:47:34.891358 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6678 16:47:34.898355 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6679 16:47:34.901910 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6680 16:47:34.904880 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6681 16:47:34.908234 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6682 16:47:34.914582 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6683 16:47:34.917500 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6684 16:47:34.921122 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6685 16:47:34.927823 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6686 16:47:34.930655 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6687 16:47:34.934023 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6688 16:47:34.934447 ==
6689 16:47:34.937140 Dram Type= 6, Freq= 0, CH_1, rank 0
6690 16:47:34.940779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6691 16:47:34.944123 ==
6692 16:47:34.944535 DQS Delay:
6693 16:47:34.944864 DQS0 = 35, DQS1 = 51
6694 16:47:34.947168 DQM Delay:
6695 16:47:34.947621 DQM0 = 6, DQM1 = 13
6696 16:47:34.950654 DQ Delay:
6697 16:47:34.951072 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6698 16:47:34.953715 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6699 16:47:34.957793 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6700 16:47:34.960431 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6701 16:47:34.960851
6702 16:47:34.961216
6703 16:47:34.961524 ==
6704 16:47:34.963337 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 16:47:34.970563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 16:47:34.970999 ==
6707 16:47:34.971386
6708 16:47:34.971696
6709 16:47:34.973525 TX Vref Scan disable
6710 16:47:34.973960 == TX Byte 0 ==
6711 16:47:34.976620 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6712 16:47:34.983165 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6713 16:47:34.983625 == TX Byte 1 ==
6714 16:47:34.986988 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6715 16:47:34.993288 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6716 16:47:34.993730 ==
6717 16:47:34.996683 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 16:47:34.999936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 16:47:35.000359 ==
6720 16:47:35.000691
6721 16:47:35.000999
6722 16:47:35.003546 TX Vref Scan disable
6723 16:47:35.003966 == TX Byte 0 ==
6724 16:47:35.006962 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 16:47:35.012920 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 16:47:35.013363 == TX Byte 1 ==
6727 16:47:35.016295 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 16:47:35.023113 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 16:47:35.023698
6730 16:47:35.024038 [DATLAT]
6731 16:47:35.024347 Freq=400, CH1 RK0
6732 16:47:35.026060
6733 16:47:35.026479 DATLAT Default: 0xf
6734 16:47:35.029852 0, 0xFFFF, sum = 0
6735 16:47:35.030277 1, 0xFFFF, sum = 0
6736 16:47:35.033636 2, 0xFFFF, sum = 0
6737 16:47:35.034171 3, 0xFFFF, sum = 0
6738 16:47:35.036523 4, 0xFFFF, sum = 0
6739 16:47:35.036963 5, 0xFFFF, sum = 0
6740 16:47:35.039075 6, 0xFFFF, sum = 0
6741 16:47:35.039557 7, 0xFFFF, sum = 0
6742 16:47:35.042770 8, 0xFFFF, sum = 0
6743 16:47:35.043239 9, 0xFFFF, sum = 0
6744 16:47:35.045816 10, 0xFFFF, sum = 0
6745 16:47:35.046249 11, 0xFFFF, sum = 0
6746 16:47:35.049212 12, 0xFFFF, sum = 0
6747 16:47:35.049645 13, 0x0, sum = 1
6748 16:47:35.052612 14, 0x0, sum = 2
6749 16:47:35.053043 15, 0x0, sum = 3
6750 16:47:35.055518 16, 0x0, sum = 4
6751 16:47:35.055948 best_step = 14
6752 16:47:35.056282
6753 16:47:35.056590 ==
6754 16:47:35.059120 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 16:47:35.065601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 16:47:35.066030 ==
6757 16:47:35.066368 RX Vref Scan: 1
6758 16:47:35.066684
6759 16:47:35.069728 RX Vref 0 -> 0, step: 1
6760 16:47:35.070152
6761 16:47:35.071989 RX Delay -343 -> 252, step: 8
6762 16:47:35.072414
6763 16:47:35.075700 Set Vref, RX VrefLevel [Byte0]: 52
6764 16:47:35.078989 [Byte1]: 51
6765 16:47:35.082077
6766 16:47:35.082497 Final RX Vref Byte 0 = 52 to rank0
6767 16:47:35.085172 Final RX Vref Byte 1 = 51 to rank0
6768 16:47:35.088921 Final RX Vref Byte 0 = 52 to rank1
6769 16:47:35.092046 Final RX Vref Byte 1 = 51 to rank1==
6770 16:47:35.095467 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 16:47:35.102118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 16:47:35.102656 ==
6773 16:47:35.103067 DQS Delay:
6774 16:47:35.105275 DQS0 = 44, DQS1 = 52
6775 16:47:35.105698 DQM Delay:
6776 16:47:35.106035 DQM0 = 9, DQM1 = 10
6777 16:47:35.108679 DQ Delay:
6778 16:47:35.111813 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6779 16:47:35.112277 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6780 16:47:35.115028 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6781 16:47:35.118631 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6782 16:47:35.119097
6783 16:47:35.121717
6784 16:47:35.128877 [DQSOSCAuto] RK0, (LSB)MR18= 0x6288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6785 16:47:35.132107 CH1 RK0: MR19=C0C, MR18=6288
6786 16:47:35.138356 CH1_RK0: MR19=0xC0C, MR18=0x6288, DQSOSC=392, MR23=63, INC=384, DEC=256
6787 16:47:35.138781 ==
6788 16:47:35.141428 Dram Type= 6, Freq= 0, CH_1, rank 1
6789 16:47:35.145073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 16:47:35.145589 ==
6791 16:47:35.148179 [Gating] SW mode calibration
6792 16:47:35.155522 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6793 16:47:35.161112 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6794 16:47:35.164654 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6795 16:47:35.167727 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6796 16:47:35.174303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 16:47:35.177638 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6798 16:47:35.181728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6799 16:47:35.187672 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6800 16:47:35.190730 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6801 16:47:35.194273 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6802 16:47:35.200668 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6803 16:47:35.201176 Total UI for P1: 0, mck2ui 16
6804 16:47:35.207199 best dqsien dly found for B0: ( 0, 14, 24)
6805 16:47:35.207625 Total UI for P1: 0, mck2ui 16
6806 16:47:35.213866 best dqsien dly found for B1: ( 0, 14, 24)
6807 16:47:35.216977 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6808 16:47:35.220096 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6809 16:47:35.220561
6810 16:47:35.223800 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6811 16:47:35.227102 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6812 16:47:35.230953 [Gating] SW calibration Done
6813 16:47:35.231525 ==
6814 16:47:35.233499 Dram Type= 6, Freq= 0, CH_1, rank 1
6815 16:47:35.236825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 16:47:35.237349 ==
6817 16:47:35.240161 RX Vref Scan: 0
6818 16:47:35.240581
6819 16:47:35.242974 RX Vref 0 -> 0, step: 1
6820 16:47:35.243444
6821 16:47:35.243781 RX Delay -410 -> 252, step: 16
6822 16:47:35.250219 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6823 16:47:35.253172 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6824 16:47:35.256959 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6825 16:47:35.263594 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6826 16:47:35.267052 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6827 16:47:35.269499 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6828 16:47:35.273282 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6829 16:47:35.279425 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6830 16:47:35.282836 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6831 16:47:35.286227 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6832 16:47:35.289118 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6833 16:47:35.296706 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6834 16:47:35.299336 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6835 16:47:35.302730 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6836 16:47:35.309592 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6837 16:47:35.312709 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6838 16:47:35.313183 ==
6839 16:47:35.315474 Dram Type= 6, Freq= 0, CH_1, rank 1
6840 16:47:35.319033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 16:47:35.319487 ==
6842 16:47:35.322430 DQS Delay:
6843 16:47:35.322849 DQS0 = 43, DQS1 = 51
6844 16:47:35.323297 DQM Delay:
6845 16:47:35.325884 DQM0 = 9, DQM1 = 15
6846 16:47:35.326395 DQ Delay:
6847 16:47:35.328936 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6848 16:47:35.332707 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6849 16:47:35.335389 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6850 16:47:35.339552 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6851 16:47:35.340075
6852 16:47:35.340409
6853 16:47:35.340711 ==
6854 16:47:35.342133 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 16:47:35.345838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 16:47:35.348937 ==
6857 16:47:35.349359
6858 16:47:35.349692
6859 16:47:35.349998 TX Vref Scan disable
6860 16:47:35.351864 == TX Byte 0 ==
6861 16:47:35.355405 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6862 16:47:35.359095 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6863 16:47:35.362337 == TX Byte 1 ==
6864 16:47:35.365564 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6865 16:47:35.368778 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6866 16:47:35.369192 ==
6867 16:47:35.371619 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 16:47:35.378441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 16:47:35.378872 ==
6870 16:47:35.379399
6871 16:47:35.379843
6872 16:47:35.380238 TX Vref Scan disable
6873 16:47:35.381553 == TX Byte 0 ==
6874 16:47:35.385045 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6875 16:47:35.391518 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6876 16:47:35.391954 == TX Byte 1 ==
6877 16:47:35.394477 Update DQ dly =587 (4 ,2, 11) DQ OEN =(3 ,3)
6878 16:47:35.401410 Update DQM dly =587 (4 ,2, 11) DQM OEN =(3 ,3)
6879 16:47:35.401969
6880 16:47:35.402404 [DATLAT]
6881 16:47:35.402806 Freq=400, CH1 RK1
6882 16:47:35.403334
6883 16:47:35.405129 DATLAT Default: 0xe
6884 16:47:35.408195 0, 0xFFFF, sum = 0
6885 16:47:35.408629 1, 0xFFFF, sum = 0
6886 16:47:35.411023 2, 0xFFFF, sum = 0
6887 16:47:35.411520 3, 0xFFFF, sum = 0
6888 16:47:35.414280 4, 0xFFFF, sum = 0
6889 16:47:35.414713 5, 0xFFFF, sum = 0
6890 16:47:35.417481 6, 0xFFFF, sum = 0
6891 16:47:35.417969 7, 0xFFFF, sum = 0
6892 16:47:35.421419 8, 0xFFFF, sum = 0
6893 16:47:35.421957 9, 0xFFFF, sum = 0
6894 16:47:35.424691 10, 0xFFFF, sum = 0
6895 16:47:35.425236 11, 0xFFFF, sum = 0
6896 16:47:35.427480 12, 0xFFFF, sum = 0
6897 16:47:35.427956 13, 0x0, sum = 1
6898 16:47:35.430753 14, 0x0, sum = 2
6899 16:47:35.431207 15, 0x0, sum = 3
6900 16:47:35.434377 16, 0x0, sum = 4
6901 16:47:35.434915 best_step = 14
6902 16:47:35.435420
6903 16:47:35.435824 ==
6904 16:47:35.437760 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 16:47:35.444199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 16:47:35.444744 ==
6907 16:47:35.445184 RX Vref Scan: 0
6908 16:47:35.445586
6909 16:47:35.447165 RX Vref 0 -> 0, step: 1
6910 16:47:35.447616
6911 16:47:35.451081 RX Delay -343 -> 252, step: 8
6912 16:47:35.457417 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6913 16:47:35.460322 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6914 16:47:35.463986 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6915 16:47:35.466791 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6916 16:47:35.473954 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6917 16:47:35.476765 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6918 16:47:35.479890 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6919 16:47:35.487084 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6920 16:47:35.490352 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6921 16:47:35.493627 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6922 16:47:35.496687 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6923 16:47:35.503081 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6924 16:47:35.506313 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6925 16:47:35.510090 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6926 16:47:35.513491 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6927 16:47:35.519691 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6928 16:47:35.520115 ==
6929 16:47:35.522964 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 16:47:35.526018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 16:47:35.526447 ==
6932 16:47:35.526781 DQS Delay:
6933 16:47:35.529604 DQS0 = 48, DQS1 = 56
6934 16:47:35.530129 DQM Delay:
6935 16:47:35.532841 DQM0 = 10, DQM1 = 14
6936 16:47:35.533364 DQ Delay:
6937 16:47:35.535851 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6938 16:47:35.539633 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6939 16:47:35.542759 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6940 16:47:35.546204 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6941 16:47:35.546731
6942 16:47:35.547065
6943 16:47:35.555903 [DQSOSCAuto] RK1, (LSB)MR18= 0x6da5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6944 16:47:35.556434 CH1 RK1: MR19=C0C, MR18=6DA5
6945 16:47:35.561746 CH1_RK1: MR19=0xC0C, MR18=0x6DA5, DQSOSC=389, MR23=63, INC=390, DEC=260
6946 16:47:35.565395 [RxdqsGatingPostProcess] freq 400
6947 16:47:35.572015 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6948 16:47:35.575695 best DQS0 dly(2T, 0.5T) = (0, 10)
6949 16:47:35.578299 best DQS1 dly(2T, 0.5T) = (0, 10)
6950 16:47:35.581702 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6951 16:47:35.584975 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6952 16:47:35.588540 best DQS0 dly(2T, 0.5T) = (0, 10)
6953 16:47:35.589114 best DQS1 dly(2T, 0.5T) = (0, 10)
6954 16:47:35.591725 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6955 16:47:35.595250 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6956 16:47:35.598276 Pre-setting of DQS Precalculation
6957 16:47:35.605283 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6958 16:47:35.611711 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6959 16:47:35.618095 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6960 16:47:35.618535
6961 16:47:35.618871
6962 16:47:35.621813 [Calibration Summary] 800 Mbps
6963 16:47:35.625275 CH 0, Rank 0
6964 16:47:35.625836 SW Impedance : PASS
6965 16:47:35.628148 DUTY Scan : NO K
6966 16:47:35.631030 ZQ Calibration : PASS
6967 16:47:35.631639 Jitter Meter : NO K
6968 16:47:35.634735 CBT Training : PASS
6969 16:47:35.637580 Write leveling : PASS
6970 16:47:35.638155 RX DQS gating : PASS
6971 16:47:35.640977 RX DQ/DQS(RDDQC) : PASS
6972 16:47:35.644235 TX DQ/DQS : PASS
6973 16:47:35.644817 RX DATLAT : PASS
6974 16:47:35.647439 RX DQ/DQS(Engine): PASS
6975 16:47:35.648039 TX OE : NO K
6976 16:47:35.650802 All Pass.
6977 16:47:35.651329
6978 16:47:35.651736 CH 0, Rank 1
6979 16:47:35.654386 SW Impedance : PASS
6980 16:47:35.654934 DUTY Scan : NO K
6981 16:47:35.657442 ZQ Calibration : PASS
6982 16:47:35.660864 Jitter Meter : NO K
6983 16:47:35.661466 CBT Training : PASS
6984 16:47:35.664011 Write leveling : NO K
6985 16:47:35.667527 RX DQS gating : PASS
6986 16:47:35.668030 RX DQ/DQS(RDDQC) : PASS
6987 16:47:35.670890 TX DQ/DQS : PASS
6988 16:47:35.673950 RX DATLAT : PASS
6989 16:47:35.674331 RX DQ/DQS(Engine): PASS
6990 16:47:35.677893 TX OE : NO K
6991 16:47:35.678381 All Pass.
6992 16:47:35.678804
6993 16:47:35.680659 CH 1, Rank 0
6994 16:47:35.681083 SW Impedance : PASS
6995 16:47:35.684211 DUTY Scan : NO K
6996 16:47:35.687031 ZQ Calibration : PASS
6997 16:47:35.687532 Jitter Meter : NO K
6998 16:47:35.690391 CBT Training : PASS
6999 16:47:35.693666 Write leveling : PASS
7000 16:47:35.694090 RX DQS gating : PASS
7001 16:47:35.697263 RX DQ/DQS(RDDQC) : PASS
7002 16:47:35.700594 TX DQ/DQS : PASS
7003 16:47:35.701070 RX DATLAT : PASS
7004 16:47:35.703626 RX DQ/DQS(Engine): PASS
7005 16:47:35.706998 TX OE : NO K
7006 16:47:35.707454 All Pass.
7007 16:47:35.707823
7008 16:47:35.708142 CH 1, Rank 1
7009 16:47:35.710676 SW Impedance : PASS
7010 16:47:35.713739 DUTY Scan : NO K
7011 16:47:35.714160 ZQ Calibration : PASS
7012 16:47:35.716690 Jitter Meter : NO K
7013 16:47:35.720863 CBT Training : PASS
7014 16:47:35.721434 Write leveling : NO K
7015 16:47:35.723278 RX DQS gating : PASS
7016 16:47:35.727025 RX DQ/DQS(RDDQC) : PASS
7017 16:47:35.727693 TX DQ/DQS : PASS
7018 16:47:35.730033 RX DATLAT : PASS
7019 16:47:35.730453 RX DQ/DQS(Engine): PASS
7020 16:47:35.733441 TX OE : NO K
7021 16:47:35.733862 All Pass.
7022 16:47:35.734192
7023 16:47:35.736466 DramC Write-DBI off
7024 16:47:35.739657 PER_BANK_REFRESH: Hybrid Mode
7025 16:47:35.740078 TX_TRACKING: ON
7026 16:47:35.749455 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7027 16:47:35.753134 [FAST_K] Save calibration result to emmc
7028 16:47:35.756272 dramc_set_vcore_voltage set vcore to 725000
7029 16:47:35.759520 Read voltage for 1600, 0
7030 16:47:35.759940 Vio18 = 0
7031 16:47:35.762810 Vcore = 725000
7032 16:47:35.763286 Vdram = 0
7033 16:47:35.763630 Vddq = 0
7034 16:47:35.763943 Vmddr = 0
7035 16:47:35.770226 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7036 16:47:35.776086 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7037 16:47:35.776509 MEM_TYPE=3, freq_sel=13
7038 16:47:35.779478 sv_algorithm_assistance_LP4_3733
7039 16:47:35.785934 ============ PULL DRAM RESETB DOWN ============
7040 16:47:35.789070 ========== PULL DRAM RESETB DOWN end =========
7041 16:47:35.792242 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7042 16:47:35.795841 ===================================
7043 16:47:35.799017 LPDDR4 DRAM CONFIGURATION
7044 16:47:35.802210 ===================================
7045 16:47:35.805507 EX_ROW_EN[0] = 0x0
7046 16:47:35.805926 EX_ROW_EN[1] = 0x0
7047 16:47:35.808610 LP4Y_EN = 0x0
7048 16:47:35.809028 WORK_FSP = 0x1
7049 16:47:35.812067 WL = 0x5
7050 16:47:35.812483 RL = 0x5
7051 16:47:35.815705 BL = 0x2
7052 16:47:35.816121 RPST = 0x0
7053 16:47:35.818490 RD_PRE = 0x0
7054 16:47:35.818939 WR_PRE = 0x1
7055 16:47:35.821917 WR_PST = 0x1
7056 16:47:35.822333 DBI_WR = 0x0
7057 16:47:35.825043 DBI_RD = 0x0
7058 16:47:35.825582 OTF = 0x1
7059 16:47:35.828894 ===================================
7060 16:47:35.831227 ===================================
7061 16:47:35.834946 ANA top config
7062 16:47:35.838461 ===================================
7063 16:47:35.841678 DLL_ASYNC_EN = 0
7064 16:47:35.842237 ALL_SLAVE_EN = 0
7065 16:47:35.844643 NEW_RANK_MODE = 1
7066 16:47:35.848011 DLL_IDLE_MODE = 1
7067 16:47:35.851010 LP45_APHY_COMB_EN = 1
7068 16:47:35.854744 TX_ODT_DIS = 0
7069 16:47:35.855163 NEW_8X_MODE = 1
7070 16:47:35.857613 ===================================
7071 16:47:35.861163 ===================================
7072 16:47:35.864552 data_rate = 3200
7073 16:47:35.867732 CKR = 1
7074 16:47:35.870839 DQ_P2S_RATIO = 8
7075 16:47:35.874554 ===================================
7076 16:47:35.877520 CA_P2S_RATIO = 8
7077 16:47:35.881298 DQ_CA_OPEN = 0
7078 16:47:35.881811 DQ_SEMI_OPEN = 0
7079 16:47:35.884623 CA_SEMI_OPEN = 0
7080 16:47:35.887600 CA_FULL_RATE = 0
7081 16:47:35.890995 DQ_CKDIV4_EN = 0
7082 16:47:35.894167 CA_CKDIV4_EN = 0
7083 16:47:35.897272 CA_PREDIV_EN = 0
7084 16:47:35.900637 PH8_DLY = 12
7085 16:47:35.901056 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7086 16:47:35.904186 DQ_AAMCK_DIV = 4
7087 16:47:35.907717 CA_AAMCK_DIV = 4
7088 16:47:35.910451 CA_ADMCK_DIV = 4
7089 16:47:35.914053 DQ_TRACK_CA_EN = 0
7090 16:47:35.917274 CA_PICK = 1600
7091 16:47:35.920722 CA_MCKIO = 1600
7092 16:47:35.921139 MCKIO_SEMI = 0
7093 16:47:35.923919 PLL_FREQ = 3068
7094 16:47:35.926932 DQ_UI_PI_RATIO = 32
7095 16:47:35.930478 CA_UI_PI_RATIO = 0
7096 16:47:35.933292 ===================================
7097 16:47:35.936855 ===================================
7098 16:47:35.939980 memory_type:LPDDR4
7099 16:47:35.940399 GP_NUM : 10
7100 16:47:35.943057 SRAM_EN : 1
7101 16:47:35.946777 MD32_EN : 0
7102 16:47:35.949661 ===================================
7103 16:47:35.950077 [ANA_INIT] >>>>>>>>>>>>>>
7104 16:47:35.953467 <<<<<< [CONFIGURE PHASE]: ANA_TX
7105 16:47:35.956292 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7106 16:47:35.960171 ===================================
7107 16:47:35.962878 data_rate = 3200,PCW = 0X7600
7108 16:47:35.966013 ===================================
7109 16:47:35.969344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7110 16:47:35.976357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7111 16:47:35.982765 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7112 16:47:35.986124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7113 16:47:35.989064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7114 16:47:35.992462 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7115 16:47:35.995921 [ANA_INIT] flow start
7116 16:47:35.996379 [ANA_INIT] PLL >>>>>>>>
7117 16:47:35.998926 [ANA_INIT] PLL <<<<<<<<
7118 16:47:36.002947 [ANA_INIT] MIDPI >>>>>>>>
7119 16:47:36.003437 [ANA_INIT] MIDPI <<<<<<<<
7120 16:47:36.006759 [ANA_INIT] DLL >>>>>>>>
7121 16:47:36.009162 [ANA_INIT] DLL <<<<<<<<
7122 16:47:36.009625 [ANA_INIT] flow end
7123 16:47:36.015531 ============ LP4 DIFF to SE enter ============
7124 16:47:36.019040 ============ LP4 DIFF to SE exit ============
7125 16:47:36.021988 [ANA_INIT] <<<<<<<<<<<<<
7126 16:47:36.025878 [Flow] Enable top DCM control >>>>>
7127 16:47:36.028527 [Flow] Enable top DCM control <<<<<
7128 16:47:36.028682 Enable DLL master slave shuffle
7129 16:47:36.034883 ==============================================================
7130 16:47:36.038246 Gating Mode config
7131 16:47:36.041427 ==============================================================
7132 16:47:36.044992 Config description:
7133 16:47:36.055670 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7134 16:47:36.061499 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7135 16:47:36.064720 SELPH_MODE 0: By rank 1: By Phase
7136 16:47:36.071483 ==============================================================
7137 16:47:36.074856 GAT_TRACK_EN = 1
7138 16:47:36.078176 RX_GATING_MODE = 2
7139 16:47:36.081195 RX_GATING_TRACK_MODE = 2
7140 16:47:36.085203 SELPH_MODE = 1
7141 16:47:36.087992 PICG_EARLY_EN = 1
7142 16:47:36.088075 VALID_LAT_VALUE = 1
7143 16:47:36.094399 ==============================================================
7144 16:47:36.098030 Enter into Gating configuration >>>>
7145 16:47:36.100818 Exit from Gating configuration <<<<
7146 16:47:36.104788 Enter into DVFS_PRE_config >>>>>
7147 16:47:36.114007 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7148 16:47:36.117290 Exit from DVFS_PRE_config <<<<<
7149 16:47:36.120791 Enter into PICG configuration >>>>
7150 16:47:36.125157 Exit from PICG configuration <<<<
7151 16:47:36.127704 [RX_INPUT] configuration >>>>>
7152 16:47:36.130534 [RX_INPUT] configuration <<<<<
7153 16:47:36.137023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7154 16:47:36.140929 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7155 16:47:36.146974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7156 16:47:36.153748 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7157 16:47:36.160153 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7158 16:47:36.166544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7159 16:47:36.169976 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7160 16:47:36.173434 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7161 16:47:36.176881 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7162 16:47:36.183435 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7163 16:47:36.186417 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7164 16:47:36.190124 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7165 16:47:36.193881 ===================================
7166 16:47:36.196292 LPDDR4 DRAM CONFIGURATION
7167 16:47:36.199741 ===================================
7168 16:47:36.203618 EX_ROW_EN[0] = 0x0
7169 16:47:36.203700 EX_ROW_EN[1] = 0x0
7170 16:47:36.206379 LP4Y_EN = 0x0
7171 16:47:36.206460 WORK_FSP = 0x1
7172 16:47:36.209794 WL = 0x5
7173 16:47:36.209876 RL = 0x5
7174 16:47:36.213053 BL = 0x2
7175 16:47:36.213134 RPST = 0x0
7176 16:47:36.216124 RD_PRE = 0x0
7177 16:47:36.216206 WR_PRE = 0x1
7178 16:47:36.219718 WR_PST = 0x1
7179 16:47:36.219799 DBI_WR = 0x0
7180 16:47:36.222805 DBI_RD = 0x0
7181 16:47:36.226127 OTF = 0x1
7182 16:47:36.229469 ===================================
7183 16:47:36.232599 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7184 16:47:36.235975 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7185 16:47:36.239667 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 16:47:36.243462 ===================================
7187 16:47:36.246305 LPDDR4 DRAM CONFIGURATION
7188 16:47:36.249353 ===================================
7189 16:47:36.252363 EX_ROW_EN[0] = 0x10
7190 16:47:36.252444 EX_ROW_EN[1] = 0x0
7191 16:47:36.255794 LP4Y_EN = 0x0
7192 16:47:36.255887 WORK_FSP = 0x1
7193 16:47:36.259571 WL = 0x5
7194 16:47:36.259652 RL = 0x5
7195 16:47:36.262640 BL = 0x2
7196 16:47:36.262753 RPST = 0x0
7197 16:47:36.266229 RD_PRE = 0x0
7198 16:47:36.266343 WR_PRE = 0x1
7199 16:47:36.269279 WR_PST = 0x1
7200 16:47:36.269372 DBI_WR = 0x0
7201 16:47:36.272570 DBI_RD = 0x0
7202 16:47:36.276090 OTF = 0x1
7203 16:47:36.279010 ===================================
7204 16:47:36.282408 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7205 16:47:36.282535 ==
7206 16:47:36.286228 Dram Type= 6, Freq= 0, CH_0, rank 0
7207 16:47:36.292361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7208 16:47:36.292498 ==
7209 16:47:36.292637 [Duty_Offset_Calibration]
7210 16:47:36.296247 B0:2 B1:0 CA:4
7211 16:47:36.296424
7212 16:47:36.299218 [DutyScan_Calibration_Flow] k_type=0
7213 16:47:36.307653
7214 16:47:36.307890 ==CLK 0==
7215 16:47:36.311225 Final CLK duty delay cell = -4
7216 16:47:36.314378 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7217 16:47:36.317606 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7218 16:47:36.321013 [-4] AVG Duty = 4937%(X100)
7219 16:47:36.321514
7220 16:47:36.324753 CH0 CLK Duty spec in!! Max-Min= 187%
7221 16:47:36.328139 [DutyScan_Calibration_Flow] ====Done====
7222 16:47:36.328719
7223 16:47:36.331200 [DutyScan_Calibration_Flow] k_type=1
7224 16:47:36.348097
7225 16:47:36.348579 ==DQS 0 ==
7226 16:47:36.351452 Final DQS duty delay cell = 0
7227 16:47:36.354781 [0] MAX Duty = 5249%(X100), DQS PI = 38
7228 16:47:36.357910 [0] MIN Duty = 5093%(X100), DQS PI = 6
7229 16:47:36.361130 [0] AVG Duty = 5171%(X100)
7230 16:47:36.361760
7231 16:47:36.362255 ==DQS 1 ==
7232 16:47:36.364749 Final DQS duty delay cell = 0
7233 16:47:36.368338 [0] MAX Duty = 5156%(X100), DQS PI = 2
7234 16:47:36.371220 [0] MIN Duty = 4969%(X100), DQS PI = 10
7235 16:47:36.374556 [0] AVG Duty = 5062%(X100)
7236 16:47:36.375097
7237 16:47:36.377672 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7238 16:47:36.378216
7239 16:47:36.381207 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7240 16:47:36.384745 [DutyScan_Calibration_Flow] ====Done====
7241 16:47:36.385168
7242 16:47:36.387531 [DutyScan_Calibration_Flow] k_type=3
7243 16:47:36.405455
7244 16:47:36.405870 ==DQM 0 ==
7245 16:47:36.408422 Final DQM duty delay cell = 0
7246 16:47:36.411688 [0] MAX Duty = 5124%(X100), DQS PI = 20
7247 16:47:36.415128 [0] MIN Duty = 4875%(X100), DQS PI = 54
7248 16:47:36.418486 [0] AVG Duty = 4999%(X100)
7249 16:47:36.418903
7250 16:47:36.419270 ==DQM 1 ==
7251 16:47:36.421738 Final DQM duty delay cell = 0
7252 16:47:36.425037 [0] MAX Duty = 4969%(X100), DQS PI = 0
7253 16:47:36.428323 [0] MIN Duty = 4844%(X100), DQS PI = 16
7254 16:47:36.431646 [0] AVG Duty = 4906%(X100)
7255 16:47:36.432061
7256 16:47:36.434799 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7257 16:47:36.435278
7258 16:47:36.437944 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7259 16:47:36.441698 [DutyScan_Calibration_Flow] ====Done====
7260 16:47:36.442113
7261 16:47:36.444696 [DutyScan_Calibration_Flow] k_type=2
7262 16:47:36.461817
7263 16:47:36.461900 ==DQ 0 ==
7264 16:47:36.465298 Final DQ duty delay cell = 0
7265 16:47:36.469356 [0] MAX Duty = 5156%(X100), DQS PI = 22
7266 16:47:36.471940 [0] MIN Duty = 4938%(X100), DQS PI = 12
7267 16:47:36.475017 [0] AVG Duty = 5047%(X100)
7268 16:47:36.475097
7269 16:47:36.475161 ==DQ 1 ==
7270 16:47:36.478401 Final DQ duty delay cell = 0
7271 16:47:36.481778 [0] MAX Duty = 5187%(X100), DQS PI = 2
7272 16:47:36.484980 [0] MIN Duty = 4938%(X100), DQS PI = 12
7273 16:47:36.485062 [0] AVG Duty = 5062%(X100)
7274 16:47:36.488427
7275 16:47:36.491980 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7276 16:47:36.492067
7277 16:47:36.495006 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7278 16:47:36.498117 [DutyScan_Calibration_Flow] ====Done====
7279 16:47:36.498218 ==
7280 16:47:36.501703 Dram Type= 6, Freq= 0, CH_1, rank 0
7281 16:47:36.505308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7282 16:47:36.505419 ==
7283 16:47:36.508363 [Duty_Offset_Calibration]
7284 16:47:36.508483 B0:0 B1:-1 CA:3
7285 16:47:36.508579
7286 16:47:36.511672 [DutyScan_Calibration_Flow] k_type=0
7287 16:47:36.521382
7288 16:47:36.521531 ==CLK 0==
7289 16:47:36.524794 Final CLK duty delay cell = -4
7290 16:47:36.528024 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7291 16:47:36.531532 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7292 16:47:36.534362 [-4] AVG Duty = 4937%(X100)
7293 16:47:36.534669
7294 16:47:36.538682 CH1 CLK Duty spec in!! Max-Min= 187%
7295 16:47:36.541602 [DutyScan_Calibration_Flow] ====Done====
7296 16:47:36.541890
7297 16:47:36.544354 [DutyScan_Calibration_Flow] k_type=1
7298 16:47:36.561321
7299 16:47:36.561695 ==DQS 0 ==
7300 16:47:36.564207 Final DQS duty delay cell = 0
7301 16:47:36.567615 [0] MAX Duty = 5250%(X100), DQS PI = 28
7302 16:47:36.571019 [0] MIN Duty = 4907%(X100), DQS PI = 56
7303 16:47:36.574314 [0] AVG Duty = 5078%(X100)
7304 16:47:36.574725
7305 16:47:36.575048 ==DQS 1 ==
7306 16:47:36.577449 Final DQS duty delay cell = -4
7307 16:47:36.580682 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7308 16:47:36.584026 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7309 16:47:36.587084 [-4] AVG Duty = 4906%(X100)
7310 16:47:36.587581
7311 16:47:36.590393 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7312 16:47:36.590805
7313 16:47:36.593871 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7314 16:47:36.596936 [DutyScan_Calibration_Flow] ====Done====
7315 16:47:36.597350
7316 16:47:36.600372 [DutyScan_Calibration_Flow] k_type=3
7317 16:47:36.618276
7318 16:47:36.618714 ==DQM 0 ==
7319 16:47:36.621458 Final DQM duty delay cell = 0
7320 16:47:36.624758 [0] MAX Duty = 5062%(X100), DQS PI = 32
7321 16:47:36.628133 [0] MIN Duty = 4782%(X100), DQS PI = 40
7322 16:47:36.631482 [0] AVG Duty = 4922%(X100)
7323 16:47:36.631916
7324 16:47:36.632240 ==DQM 1 ==
7325 16:47:36.634960 Final DQM duty delay cell = 0
7326 16:47:36.638728 [0] MAX Duty = 5000%(X100), DQS PI = 30
7327 16:47:36.641670 [0] MIN Duty = 4813%(X100), DQS PI = 0
7328 16:47:36.644584 [0] AVG Duty = 4906%(X100)
7329 16:47:36.645116
7330 16:47:36.648173 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7331 16:47:36.648649
7332 16:47:36.651060 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7333 16:47:36.654604 [DutyScan_Calibration_Flow] ====Done====
7334 16:47:36.655018
7335 16:47:36.658335 [DutyScan_Calibration_Flow] k_type=2
7336 16:47:36.674137
7337 16:47:36.674553 ==DQ 0 ==
7338 16:47:36.677678 Final DQ duty delay cell = -4
7339 16:47:36.680756 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7340 16:47:36.684115 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7341 16:47:36.687691 [-4] AVG Duty = 4891%(X100)
7342 16:47:36.688147
7343 16:47:36.688553 ==DQ 1 ==
7344 16:47:36.690866 Final DQ duty delay cell = 0
7345 16:47:36.694300 [0] MAX Duty = 5031%(X100), DQS PI = 30
7346 16:47:36.697270 [0] MIN Duty = 4875%(X100), DQS PI = 0
7347 16:47:36.700666 [0] AVG Duty = 4953%(X100)
7348 16:47:36.701086
7349 16:47:36.704880 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7350 16:47:36.705287
7351 16:47:36.707434 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7352 16:47:36.710503 [DutyScan_Calibration_Flow] ====Done====
7353 16:47:36.714422 nWR fixed to 30
7354 16:47:36.716967 [ModeRegInit_LP4] CH0 RK0
7355 16:47:36.717384 [ModeRegInit_LP4] CH0 RK1
7356 16:47:36.720379 [ModeRegInit_LP4] CH1 RK0
7357 16:47:36.723767 [ModeRegInit_LP4] CH1 RK1
7358 16:47:36.724271 match AC timing 5
7359 16:47:36.729766 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7360 16:47:36.733420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7361 16:47:36.736730 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7362 16:47:36.743235 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7363 16:47:36.746421 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7364 16:47:36.746493 [MiockJmeterHQA]
7365 16:47:36.749957
7366 16:47:36.750028 [DramcMiockJmeter] u1RxGatingPI = 0
7367 16:47:36.753102 0 : 4257, 4029
7368 16:47:36.753173 4 : 4252, 4027
7369 16:47:36.756451 8 : 4365, 4140
7370 16:47:36.756525 12 : 4252, 4027
7371 16:47:36.759968 16 : 4253, 4027
7372 16:47:36.760041 20 : 4363, 4138
7373 16:47:36.760104 24 : 4252, 4027
7374 16:47:36.763295 28 : 4252, 4026
7375 16:47:36.763366 32 : 4252, 4027
7376 16:47:36.766840 36 : 4253, 4027
7377 16:47:36.766911 40 : 4252, 4027
7378 16:47:36.769673 44 : 4258, 4030
7379 16:47:36.769755 48 : 4252, 4027
7380 16:47:36.772878 52 : 4253, 4027
7381 16:47:36.772958 56 : 4254, 4029
7382 16:47:36.773022 60 : 4252, 4027
7383 16:47:36.776412 64 : 4363, 4137
7384 16:47:36.776494 68 : 4363, 4137
7385 16:47:36.779358 72 : 4252, 4027
7386 16:47:36.779443 76 : 4250, 4027
7387 16:47:36.782545 80 : 4250, 4026
7388 16:47:36.782630 84 : 4250, 4027
7389 16:47:36.786232 88 : 4250, 4027
7390 16:47:36.786309 92 : 4250, 4027
7391 16:47:36.789408 96 : 4250, 3540
7392 16:47:36.789495 100 : 4250, 0
7393 16:47:36.789560 104 : 4253, 0
7394 16:47:36.792645 108 : 4363, 0
7395 16:47:36.792727 112 : 4250, 0
7396 16:47:36.792792 116 : 4361, 0
7397 16:47:36.795764 120 : 4254, 0
7398 16:47:36.795846 124 : 4250, 0
7399 16:47:36.799140 128 : 4250, 0
7400 16:47:36.799270 132 : 4253, 0
7401 16:47:36.799336 136 : 4252, 0
7402 16:47:36.802516 140 : 4250, 0
7403 16:47:36.802598 144 : 4250, 0
7404 16:47:36.805900 148 : 4361, 0
7405 16:47:36.805981 152 : 4250, 0
7406 16:47:36.806045 156 : 4250, 0
7407 16:47:36.809382 160 : 4250, 0
7408 16:47:36.809463 164 : 4361, 0
7409 16:47:36.812854 168 : 4360, 0
7410 16:47:36.812936 172 : 4250, 0
7411 16:47:36.813000 176 : 4250, 0
7412 16:47:36.815970 180 : 4250, 0
7413 16:47:36.816051 184 : 4360, 0
7414 16:47:36.819287 188 : 4250, 0
7415 16:47:36.819369 192 : 4250, 0
7416 16:47:36.819433 196 : 4250, 0
7417 16:47:36.822241 200 : 4363, 0
7418 16:47:36.822323 204 : 4250, 0
7419 16:47:36.825541 208 : 4250, 0
7420 16:47:36.825623 212 : 4250, 0
7421 16:47:36.825687 216 : 4361, 0
7422 16:47:36.828830 220 : 4249, 762
7423 16:47:36.828912 224 : 4250, 3980
7424 16:47:36.832182 228 : 4250, 4027
7425 16:47:36.832266 232 : 4255, 4032
7426 16:47:36.835350 236 : 4249, 4027
7427 16:47:36.835433 240 : 4255, 4029
7428 16:47:36.839332 244 : 4361, 4137
7429 16:47:36.839416 248 : 4250, 4027
7430 16:47:36.842075 252 : 4360, 4138
7431 16:47:36.842158 256 : 4255, 4029
7432 16:47:36.842224 260 : 4250, 4027
7433 16:47:36.845440 264 : 4250, 4027
7434 16:47:36.845522 268 : 4250, 4027
7435 16:47:36.848800 272 : 4250, 4027
7436 16:47:36.848885 276 : 4250, 4026
7437 16:47:36.851716 280 : 4250, 4027
7438 16:47:36.851800 284 : 4252, 4029
7439 16:47:36.855008 288 : 4250, 4027
7440 16:47:36.855118 292 : 4250, 4026
7441 16:47:36.858820 296 : 4361, 4138
7442 16:47:36.858903 300 : 4250, 4027
7443 16:47:36.861624 304 : 4360, 4138
7444 16:47:36.861708 308 : 4250, 4026
7445 16:47:36.865139 312 : 4250, 4027
7446 16:47:36.865222 316 : 4250, 4027
7447 16:47:36.868323 320 : 4250, 4027
7448 16:47:36.868408 324 : 4250, 4027
7449 16:47:36.868473 328 : 4255, 4029
7450 16:47:36.871735 332 : 4255, 3998
7451 16:47:36.871820 336 : 4252, 2156
7452 16:47:36.875293 340 : 4250, 13
7453 16:47:36.875377
7454 16:47:36.878418 MIOCK jitter meter ch=0
7455 16:47:36.878500
7456 16:47:36.878564 1T = (340-100) = 240 dly cells
7457 16:47:36.884909 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7458 16:47:36.884995 ==
7459 16:47:36.888041 Dram Type= 6, Freq= 0, CH_0, rank 0
7460 16:47:36.891086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7461 16:47:36.894492 ==
7462 16:47:36.897900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7463 16:47:36.901357 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7464 16:47:36.908403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7465 16:47:36.914683 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7466 16:47:36.923145 [CA 0] Center 43 (13~74) winsize 62
7467 16:47:36.925393 [CA 1] Center 42 (12~73) winsize 62
7468 16:47:36.928594 [CA 2] Center 37 (8~67) winsize 60
7469 16:47:36.931771 [CA 3] Center 37 (8~67) winsize 60
7470 16:47:36.935530 [CA 4] Center 36 (6~66) winsize 61
7471 16:47:36.938413 [CA 5] Center 35 (5~66) winsize 62
7472 16:47:36.938495
7473 16:47:36.942286 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7474 16:47:36.942368
7475 16:47:36.948216 [CATrainingPosCal] consider 1 rank data
7476 16:47:36.948299 u2DelayCellTimex100 = 271/100 ps
7477 16:47:36.954850 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7478 16:47:36.958018 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7479 16:47:36.961195 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7480 16:47:36.964526 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7481 16:47:36.968149 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7482 16:47:36.971335 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7483 16:47:36.971418
7484 16:47:36.974284 CA PerBit enable=1, Macro0, CA PI delay=35
7485 16:47:36.974366
7486 16:47:36.977886 [CBTSetCACLKResult] CA Dly = 35
7487 16:47:36.980878 CS Dly: 11 (0~42)
7488 16:47:36.984468 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7489 16:47:36.987455 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7490 16:47:36.987537 ==
7491 16:47:36.990821 Dram Type= 6, Freq= 0, CH_0, rank 1
7492 16:47:36.997179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7493 16:47:36.997271 ==
7494 16:47:37.000979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7495 16:47:37.007133 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7496 16:47:37.010472 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7497 16:47:37.016893 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7498 16:47:37.025477 [CA 0] Center 43 (13~74) winsize 62
7499 16:47:37.028552 [CA 1] Center 43 (13~73) winsize 61
7500 16:47:37.031999 [CA 2] Center 38 (9~68) winsize 60
7501 16:47:37.035750 [CA 3] Center 38 (9~68) winsize 60
7502 16:47:37.038297 [CA 4] Center 37 (7~67) winsize 61
7503 16:47:37.041568 [CA 5] Center 36 (6~66) winsize 61
7504 16:47:37.041643
7505 16:47:37.045434 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7506 16:47:37.045512
7507 16:47:37.051451 [CATrainingPosCal] consider 2 rank data
7508 16:47:37.051527 u2DelayCellTimex100 = 271/100 ps
7509 16:47:37.058309 CA0 delay=43 (13~74),Diff = 7 PI (25 cell)
7510 16:47:37.061354 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7511 16:47:37.064615 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7512 16:47:37.067881 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7513 16:47:37.071191 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7514 16:47:37.074558 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7515 16:47:37.074639
7516 16:47:37.077681 CA PerBit enable=1, Macro0, CA PI delay=36
7517 16:47:37.077766
7518 16:47:37.081591 [CBTSetCACLKResult] CA Dly = 36
7519 16:47:37.084514 CS Dly: 12 (0~44)
7520 16:47:37.087960 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7521 16:47:37.091047 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7522 16:47:37.091122
7523 16:47:37.094292 ----->DramcWriteLeveling(PI) begin...
7524 16:47:37.094366 ==
7525 16:47:37.097602 Dram Type= 6, Freq= 0, CH_0, rank 0
7526 16:47:37.104400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7527 16:47:37.104489 ==
7528 16:47:37.107528 Write leveling (Byte 0): 34 => 34
7529 16:47:37.110931 Write leveling (Byte 1): 27 => 27
7530 16:47:37.114027 DramcWriteLeveling(PI) end<-----
7531 16:47:37.114110
7532 16:47:37.114174 ==
7533 16:47:37.117257 Dram Type= 6, Freq= 0, CH_0, rank 0
7534 16:47:37.121400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 16:47:37.121525 ==
7536 16:47:37.123858 [Gating] SW mode calibration
7537 16:47:37.130598 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7538 16:47:37.137198 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7539 16:47:37.140525 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7540 16:47:37.144250 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7541 16:47:37.150138 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7542 16:47:37.153699 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7543 16:47:37.157043 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7544 16:47:37.163695 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7545 16:47:37.167152 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7546 16:47:37.170060 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7547 16:47:37.176889 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7548 16:47:37.180565 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7549 16:47:37.183237 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7550 16:47:37.190137 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
7551 16:47:37.193363 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7552 16:47:37.196608 1 5 20 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
7553 16:47:37.203587 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7554 16:47:37.206550 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 16:47:37.209960 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 16:47:37.216512 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 16:47:37.219183 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7558 16:47:37.222839 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7559 16:47:37.229077 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7560 16:47:37.232340 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7561 16:47:37.235981 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7562 16:47:37.242591 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7563 16:47:37.245495 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 16:47:37.249017 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 16:47:37.255534 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 16:47:37.258899 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7567 16:47:37.262234 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7568 16:47:37.268742 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7569 16:47:37.272329 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7570 16:47:37.275313 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7571 16:47:37.281693 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 16:47:37.285642 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 16:47:37.288515 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 16:47:37.295507 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 16:47:37.298570 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 16:47:37.301561 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 16:47:37.308106 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 16:47:37.311684 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 16:47:37.314565 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 16:47:37.321134 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 16:47:37.324491 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7582 16:47:37.327887 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7583 16:47:37.334478 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7584 16:47:37.337761 Total UI for P1: 0, mck2ui 16
7585 16:47:37.340855 best dqsien dly found for B0: ( 1, 9, 10)
7586 16:47:37.344049 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7587 16:47:37.347628 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 16:47:37.350843 Total UI for P1: 0, mck2ui 16
7589 16:47:37.354004 best dqsien dly found for B1: ( 1, 9, 20)
7590 16:47:37.357347 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7591 16:47:37.360657 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7592 16:47:37.363881
7593 16:47:37.367088 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7594 16:47:37.370328 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7595 16:47:37.373511 [Gating] SW calibration Done
7596 16:47:37.373594 ==
7597 16:47:37.377057 Dram Type= 6, Freq= 0, CH_0, rank 0
7598 16:47:37.380486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7599 16:47:37.380594 ==
7600 16:47:37.383703 RX Vref Scan: 0
7601 16:47:37.383816
7602 16:47:37.383935 RX Vref 0 -> 0, step: 1
7603 16:47:37.384044
7604 16:47:37.386751 RX Delay 0 -> 252, step: 8
7605 16:47:37.390076 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7606 16:47:37.396610 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7607 16:47:37.401113 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7608 16:47:37.403532 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7609 16:47:37.406521 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7610 16:47:37.410017 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7611 16:47:37.416537 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7612 16:47:37.420184 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7613 16:47:37.422870 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7614 16:47:37.426203 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7615 16:47:37.429879 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7616 16:47:37.436242 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7617 16:47:37.439190 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7618 16:47:37.443040 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7619 16:47:37.446308 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7620 16:47:37.452354 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7621 16:47:37.452435 ==
7622 16:47:37.455873 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 16:47:37.459253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 16:47:37.459334 ==
7625 16:47:37.459397 DQS Delay:
7626 16:47:37.462618 DQS0 = 0, DQS1 = 0
7627 16:47:37.462806 DQM Delay:
7628 16:47:37.465420 DQM0 = 132, DQM1 = 127
7629 16:47:37.465501 DQ Delay:
7630 16:47:37.468923 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7631 16:47:37.472342 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7632 16:47:37.475669 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =123
7633 16:47:37.478623 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
7634 16:47:37.478704
7635 16:47:37.481916
7636 16:47:37.482058 ==
7637 16:47:37.485680 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 16:47:37.488647 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 16:47:37.488729 ==
7640 16:47:37.488793
7641 16:47:37.488851
7642 16:47:37.492050 TX Vref Scan disable
7643 16:47:37.492125 == TX Byte 0 ==
7644 16:47:37.498479 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7645 16:47:37.502731 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7646 16:47:37.502812 == TX Byte 1 ==
7647 16:47:37.508724 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7648 16:47:37.512103 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7649 16:47:37.512185 ==
7650 16:47:37.514817 Dram Type= 6, Freq= 0, CH_0, rank 0
7651 16:47:37.518068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7652 16:47:37.518150 ==
7653 16:47:37.532563
7654 16:47:37.535585 TX Vref early break, caculate TX vref
7655 16:47:37.538986 TX Vref=16, minBit 1, minWin=22, winSum=369
7656 16:47:37.542323 TX Vref=18, minBit 8, minWin=22, winSum=383
7657 16:47:37.545464 TX Vref=20, minBit 8, minWin=23, winSum=393
7658 16:47:37.549086 TX Vref=22, minBit 1, minWin=24, winSum=400
7659 16:47:37.552659 TX Vref=24, minBit 1, minWin=25, winSum=416
7660 16:47:37.559121 TX Vref=26, minBit 3, minWin=25, winSum=420
7661 16:47:37.562106 TX Vref=28, minBit 2, minWin=25, winSum=423
7662 16:47:37.565235 TX Vref=30, minBit 2, minWin=25, winSum=419
7663 16:47:37.569353 TX Vref=32, minBit 0, minWin=25, winSum=413
7664 16:47:37.571874 TX Vref=34, minBit 0, minWin=24, winSum=395
7665 16:47:37.578174 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
7666 16:47:37.578282
7667 16:47:37.581787 Final TX Range 0 Vref 28
7668 16:47:37.581902
7669 16:47:37.582007 ==
7670 16:47:37.584943 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 16:47:37.588122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 16:47:37.588205 ==
7673 16:47:37.588270
7674 16:47:37.588333
7675 16:47:37.591532 TX Vref Scan disable
7676 16:47:37.598449 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7677 16:47:37.598533 == TX Byte 0 ==
7678 16:47:37.601371 u2DelayCellOfst[0]=10 cells (3 PI)
7679 16:47:37.604806 u2DelayCellOfst[1]=14 cells (4 PI)
7680 16:47:37.608695 u2DelayCellOfst[2]=10 cells (3 PI)
7681 16:47:37.611137 u2DelayCellOfst[3]=10 cells (3 PI)
7682 16:47:37.614665 u2DelayCellOfst[4]=7 cells (2 PI)
7683 16:47:37.617688 u2DelayCellOfst[5]=0 cells (0 PI)
7684 16:47:37.621257 u2DelayCellOfst[6]=18 cells (5 PI)
7685 16:47:37.624234 u2DelayCellOfst[7]=14 cells (4 PI)
7686 16:47:37.627668 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7687 16:47:37.631336 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7688 16:47:37.634468 == TX Byte 1 ==
7689 16:47:37.637453 u2DelayCellOfst[8]=0 cells (0 PI)
7690 16:47:37.641824 u2DelayCellOfst[9]=0 cells (0 PI)
7691 16:47:37.644227 u2DelayCellOfst[10]=7 cells (2 PI)
7692 16:47:37.647961 u2DelayCellOfst[11]=3 cells (1 PI)
7693 16:47:37.650634 u2DelayCellOfst[12]=10 cells (3 PI)
7694 16:47:37.654558 u2DelayCellOfst[13]=10 cells (3 PI)
7695 16:47:37.654638 u2DelayCellOfst[14]=14 cells (4 PI)
7696 16:47:37.657340 u2DelayCellOfst[15]=10 cells (3 PI)
7697 16:47:37.664077 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7698 16:47:37.667547 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7699 16:47:37.670310 DramC Write-DBI on
7700 16:47:37.670407 ==
7701 16:47:37.673951 Dram Type= 6, Freq= 0, CH_0, rank 0
7702 16:47:37.677830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7703 16:47:37.677934 ==
7704 16:47:37.678022
7705 16:47:37.678107
7706 16:47:37.680204 TX Vref Scan disable
7707 16:47:37.680303 == TX Byte 0 ==
7708 16:47:37.687386 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7709 16:47:37.687510 == TX Byte 1 ==
7710 16:47:37.693459 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7711 16:47:37.693564 DramC Write-DBI off
7712 16:47:37.693656
7713 16:47:37.693797 [DATLAT]
7714 16:47:37.696849 Freq=1600, CH0 RK0
7715 16:47:37.696948
7716 16:47:37.699825 DATLAT Default: 0xf
7717 16:47:37.699926 0, 0xFFFF, sum = 0
7718 16:47:37.703642 1, 0xFFFF, sum = 0
7719 16:47:37.703758 2, 0xFFFF, sum = 0
7720 16:47:37.706668 3, 0xFFFF, sum = 0
7721 16:47:37.706771 4, 0xFFFF, sum = 0
7722 16:47:37.709901 5, 0xFFFF, sum = 0
7723 16:47:37.710009 6, 0xFFFF, sum = 0
7724 16:47:37.713495 7, 0xFFFF, sum = 0
7725 16:47:37.713599 8, 0xFFFF, sum = 0
7726 16:47:37.716339 9, 0xFFFF, sum = 0
7727 16:47:37.716441 10, 0xFFFF, sum = 0
7728 16:47:37.720160 11, 0xFFFF, sum = 0
7729 16:47:37.720265 12, 0xFFFF, sum = 0
7730 16:47:37.723017 13, 0xFFFF, sum = 0
7731 16:47:37.723137 14, 0x0, sum = 1
7732 16:47:37.726614 15, 0x0, sum = 2
7733 16:47:37.726700 16, 0x0, sum = 3
7734 16:47:37.729606 17, 0x0, sum = 4
7735 16:47:37.729683 best_step = 15
7736 16:47:37.729762
7737 16:47:37.729839 ==
7738 16:47:37.732866 Dram Type= 6, Freq= 0, CH_0, rank 0
7739 16:47:37.739519 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7740 16:47:37.739604 ==
7741 16:47:37.739690 RX Vref Scan: 1
7742 16:47:37.739769
7743 16:47:37.742978 Set Vref Range= 24 -> 127
7744 16:47:37.743062
7745 16:47:37.746900 RX Vref 24 -> 127, step: 1
7746 16:47:37.746984
7747 16:47:37.749644 RX Delay 11 -> 252, step: 4
7748 16:47:37.749728
7749 16:47:37.753016 Set Vref, RX VrefLevel [Byte0]: 24
7750 16:47:37.756075 [Byte1]: 24
7751 16:47:37.756159
7752 16:47:37.759057 Set Vref, RX VrefLevel [Byte0]: 25
7753 16:47:37.762592 [Byte1]: 25
7754 16:47:37.762675
7755 16:47:37.765809 Set Vref, RX VrefLevel [Byte0]: 26
7756 16:47:37.768996 [Byte1]: 26
7757 16:47:37.772441
7758 16:47:37.772524 Set Vref, RX VrefLevel [Byte0]: 27
7759 16:47:37.775594 [Byte1]: 27
7760 16:47:37.780230
7761 16:47:37.780346 Set Vref, RX VrefLevel [Byte0]: 28
7762 16:47:37.783338 [Byte1]: 28
7763 16:47:37.787688
7764 16:47:37.787785 Set Vref, RX VrefLevel [Byte0]: 29
7765 16:47:37.790619 [Byte1]: 29
7766 16:47:37.795381
7767 16:47:37.795477 Set Vref, RX VrefLevel [Byte0]: 30
7768 16:47:37.798890 [Byte1]: 30
7769 16:47:37.802699
7770 16:47:37.802775 Set Vref, RX VrefLevel [Byte0]: 31
7771 16:47:37.806287 [Byte1]: 31
7772 16:47:37.810228
7773 16:47:37.810302 Set Vref, RX VrefLevel [Byte0]: 32
7774 16:47:37.813655 [Byte1]: 32
7775 16:47:37.818087
7776 16:47:37.818164 Set Vref, RX VrefLevel [Byte0]: 33
7777 16:47:37.821407 [Byte1]: 33
7778 16:47:37.825903
7779 16:47:37.826007 Set Vref, RX VrefLevel [Byte0]: 34
7780 16:47:37.829074 [Byte1]: 34
7781 16:47:37.833163
7782 16:47:37.833250 Set Vref, RX VrefLevel [Byte0]: 35
7783 16:47:37.836463 [Byte1]: 35
7784 16:47:37.840595
7785 16:47:37.840671 Set Vref, RX VrefLevel [Byte0]: 36
7786 16:47:37.844398 [Byte1]: 36
7787 16:47:37.848539
7788 16:47:37.848643 Set Vref, RX VrefLevel [Byte0]: 37
7789 16:47:37.851610 [Byte1]: 37
7790 16:47:37.855997
7791 16:47:37.856068 Set Vref, RX VrefLevel [Byte0]: 38
7792 16:47:37.859286 [Byte1]: 38
7793 16:47:37.863594
7794 16:47:37.863661 Set Vref, RX VrefLevel [Byte0]: 39
7795 16:47:37.866884 [Byte1]: 39
7796 16:47:37.871826
7797 16:47:37.871895 Set Vref, RX VrefLevel [Byte0]: 40
7798 16:47:37.874562 [Byte1]: 40
7799 16:47:37.878697
7800 16:47:37.878771 Set Vref, RX VrefLevel [Byte0]: 41
7801 16:47:37.883116 [Byte1]: 41
7802 16:47:37.886506
7803 16:47:37.886580 Set Vref, RX VrefLevel [Byte0]: 42
7804 16:47:37.889818 [Byte1]: 42
7805 16:47:37.894465
7806 16:47:37.894539 Set Vref, RX VrefLevel [Byte0]: 43
7807 16:47:37.897486 [Byte1]: 43
7808 16:47:37.901838
7809 16:47:37.904917 Set Vref, RX VrefLevel [Byte0]: 44
7810 16:47:37.908230 [Byte1]: 44
7811 16:47:37.908304
7812 16:47:37.911394 Set Vref, RX VrefLevel [Byte0]: 45
7813 16:47:37.914675 [Byte1]: 45
7814 16:47:37.914745
7815 16:47:37.918747 Set Vref, RX VrefLevel [Byte0]: 46
7816 16:47:37.921700 [Byte1]: 46
7817 16:47:37.924445
7818 16:47:37.924528 Set Vref, RX VrefLevel [Byte0]: 47
7819 16:47:37.927992 [Byte1]: 47
7820 16:47:37.932670
7821 16:47:37.932753 Set Vref, RX VrefLevel [Byte0]: 48
7822 16:47:37.935504 [Byte1]: 48
7823 16:47:37.939751
7824 16:47:37.939834 Set Vref, RX VrefLevel [Byte0]: 49
7825 16:47:37.943090 [Byte1]: 49
7826 16:47:37.947146
7827 16:47:37.947269 Set Vref, RX VrefLevel [Byte0]: 50
7828 16:47:37.951102 [Byte1]: 50
7829 16:47:37.955383
7830 16:47:37.955466 Set Vref, RX VrefLevel [Byte0]: 51
7831 16:47:37.958805 [Byte1]: 51
7832 16:47:37.962552
7833 16:47:37.962636 Set Vref, RX VrefLevel [Byte0]: 52
7834 16:47:37.966494 [Byte1]: 52
7835 16:47:37.970574
7836 16:47:37.970656 Set Vref, RX VrefLevel [Byte0]: 53
7837 16:47:37.973859 [Byte1]: 53
7838 16:47:37.978023
7839 16:47:37.978106 Set Vref, RX VrefLevel [Byte0]: 54
7840 16:47:37.981260 [Byte1]: 54
7841 16:47:37.985881
7842 16:47:37.985967 Set Vref, RX VrefLevel [Byte0]: 55
7843 16:47:37.988853 [Byte1]: 55
7844 16:47:37.992906
7845 16:47:37.992990 Set Vref, RX VrefLevel [Byte0]: 56
7846 16:47:37.996233 [Byte1]: 56
7847 16:47:38.000738
7848 16:47:38.000822 Set Vref, RX VrefLevel [Byte0]: 57
7849 16:47:38.003782 [Byte1]: 57
7850 16:47:38.008530
7851 16:47:38.008613 Set Vref, RX VrefLevel [Byte0]: 58
7852 16:47:38.011776 [Byte1]: 58
7853 16:47:38.015886
7854 16:47:38.015969 Set Vref, RX VrefLevel [Byte0]: 59
7855 16:47:38.019369 [Byte1]: 59
7856 16:47:38.023419
7857 16:47:38.023508 Set Vref, RX VrefLevel [Byte0]: 60
7858 16:47:38.026880 [Byte1]: 60
7859 16:47:38.031709
7860 16:47:38.031805 Set Vref, RX VrefLevel [Byte0]: 61
7861 16:47:38.035265 [Byte1]: 61
7862 16:47:38.038812
7863 16:47:38.038945 Set Vref, RX VrefLevel [Byte0]: 62
7864 16:47:38.042534 [Byte1]: 62
7865 16:47:38.046111
7866 16:47:38.046193 Set Vref, RX VrefLevel [Byte0]: 63
7867 16:47:38.049882 [Byte1]: 63
7868 16:47:38.054431
7869 16:47:38.054545 Set Vref, RX VrefLevel [Byte0]: 64
7870 16:47:38.057262 [Byte1]: 64
7871 16:47:38.061750
7872 16:47:38.061843 Set Vref, RX VrefLevel [Byte0]: 65
7873 16:47:38.064815 [Byte1]: 65
7874 16:47:38.069391
7875 16:47:38.069470 Set Vref, RX VrefLevel [Byte0]: 66
7876 16:47:38.072638 [Byte1]: 66
7877 16:47:38.077012
7878 16:47:38.077090 Set Vref, RX VrefLevel [Byte0]: 67
7879 16:47:38.080172 [Byte1]: 67
7880 16:47:38.084348
7881 16:47:38.084458 Set Vref, RX VrefLevel [Byte0]: 68
7882 16:47:38.087456 [Byte1]: 68
7883 16:47:38.092440
7884 16:47:38.092553 Set Vref, RX VrefLevel [Byte0]: 69
7885 16:47:38.095281 [Byte1]: 69
7886 16:47:38.099650
7887 16:47:38.099747 Set Vref, RX VrefLevel [Byte0]: 70
7888 16:47:38.103310 [Byte1]: 70
7889 16:47:38.107032
7890 16:47:38.107129 Set Vref, RX VrefLevel [Byte0]: 71
7891 16:47:38.110418 [Byte1]: 71
7892 16:47:38.114763
7893 16:47:38.114896 Set Vref, RX VrefLevel [Byte0]: 72
7894 16:47:38.118317 [Byte1]: 72
7895 16:47:38.122547
7896 16:47:38.122626 Set Vref, RX VrefLevel [Byte0]: 73
7897 16:47:38.125616 [Byte1]: 73
7898 16:47:38.130097
7899 16:47:38.130198 Set Vref, RX VrefLevel [Byte0]: 74
7900 16:47:38.133427 [Byte1]: 74
7901 16:47:38.137797
7902 16:47:38.137879 Set Vref, RX VrefLevel [Byte0]: 75
7903 16:47:38.141206 [Byte1]: 75
7904 16:47:38.145960
7905 16:47:38.146041 Set Vref, RX VrefLevel [Byte0]: 76
7906 16:47:38.148973 [Byte1]: 76
7907 16:47:38.153069
7908 16:47:38.153150 Final RX Vref Byte 0 = 56 to rank0
7909 16:47:38.156307 Final RX Vref Byte 1 = 59 to rank0
7910 16:47:38.159861 Final RX Vref Byte 0 = 56 to rank1
7911 16:47:38.162888 Final RX Vref Byte 1 = 59 to rank1==
7912 16:47:38.166315 Dram Type= 6, Freq= 0, CH_0, rank 0
7913 16:47:38.173246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7914 16:47:38.173329 ==
7915 16:47:38.173398 DQS Delay:
7916 16:47:38.175988 DQS0 = 0, DQS1 = 0
7917 16:47:38.176069 DQM Delay:
7918 16:47:38.176147 DQM0 = 129, DQM1 = 123
7919 16:47:38.179385 DQ Delay:
7920 16:47:38.183055 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =126
7921 16:47:38.185536 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7922 16:47:38.189372 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =120
7923 16:47:38.192689 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7924 16:47:38.192775
7925 16:47:38.192860
7926 16:47:38.192939
7927 16:47:38.196407 [DramC_TX_OE_Calibration] TA2
7928 16:47:38.198746 Original DQ_B0 (3 6) =30, OEN = 27
7929 16:47:38.202646 Original DQ_B1 (3 6) =30, OEN = 27
7930 16:47:38.205631 24, 0x0, End_B0=24 End_B1=24
7931 16:47:38.208809 25, 0x0, End_B0=25 End_B1=25
7932 16:47:38.208895 26, 0x0, End_B0=26 End_B1=26
7933 16:47:38.212409 27, 0x0, End_B0=27 End_B1=27
7934 16:47:38.215582 28, 0x0, End_B0=28 End_B1=28
7935 16:47:38.218646 29, 0x0, End_B0=29 End_B1=29
7936 16:47:38.218723 30, 0x0, End_B0=30 End_B1=30
7937 16:47:38.222024 31, 0x4141, End_B0=30 End_B1=30
7938 16:47:38.225430 Byte0 end_step=30 best_step=27
7939 16:47:38.228586 Byte1 end_step=30 best_step=27
7940 16:47:38.231974 Byte0 TX OE(2T, 0.5T) = (3, 3)
7941 16:47:38.235141 Byte1 TX OE(2T, 0.5T) = (3, 3)
7942 16:47:38.235285
7943 16:47:38.235368
7944 16:47:38.241705 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7945 16:47:38.245041 CH0 RK0: MR19=303, MR18=1815
7946 16:47:38.252142 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7947 16:47:38.252226
7948 16:47:38.254962 ----->DramcWriteLeveling(PI) begin...
7949 16:47:38.255034 ==
7950 16:47:38.258396 Dram Type= 6, Freq= 0, CH_0, rank 1
7951 16:47:38.261665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7952 16:47:38.261748 ==
7953 16:47:38.264769 Write leveling (Byte 0): 34 => 34
7954 16:47:38.267901 Write leveling (Byte 1): 26 => 26
7955 16:47:38.271521 DramcWriteLeveling(PI) end<-----
7956 16:47:38.271597
7957 16:47:38.271674 ==
7958 16:47:38.274479 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 16:47:38.281166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 16:47:38.281276 ==
7961 16:47:38.281370 [Gating] SW mode calibration
7962 16:47:38.290745 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7963 16:47:38.294358 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7964 16:47:38.300677 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7965 16:47:38.304188 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7966 16:47:38.307383 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7967 16:47:38.314326 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7968 16:47:38.318420 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7969 16:47:38.320476 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7970 16:47:38.327550 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7971 16:47:38.330690 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7972 16:47:38.333742 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 16:47:38.340508 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7974 16:47:38.343499 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7975 16:47:38.346856 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7976 16:47:38.353286 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7977 16:47:38.356722 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7978 16:47:38.360038 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7979 16:47:38.366684 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7980 16:47:38.370536 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 16:47:38.372980 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 16:47:38.379953 1 6 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
7983 16:47:38.383548 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7984 16:47:38.386570 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
7985 16:47:38.393102 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7986 16:47:38.396210 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7987 16:47:38.399434 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7988 16:47:38.406107 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 16:47:38.409693 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7990 16:47:38.412458 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7991 16:47:38.419584 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7992 16:47:38.422377 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7993 16:47:38.426100 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7994 16:47:38.432908 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7995 16:47:38.435698 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7996 16:47:38.438921 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7997 16:47:38.446079 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 16:47:38.448748 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 16:47:38.452017 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 16:47:38.458370 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 16:47:38.462001 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 16:47:38.465384 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 16:47:38.472138 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 16:47:38.474985 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 16:47:38.478283 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8006 16:47:38.485267 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8007 16:47:38.488343 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8008 16:47:38.491305 Total UI for P1: 0, mck2ui 16
8009 16:47:38.494875 best dqsien dly found for B0: ( 1, 9, 6)
8010 16:47:38.498376 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8011 16:47:38.504899 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8012 16:47:38.508184 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 16:47:38.511498 Total UI for P1: 0, mck2ui 16
8014 16:47:38.514734 best dqsien dly found for B1: ( 1, 9, 18)
8015 16:47:38.518046 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8016 16:47:38.521435 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8017 16:47:38.521535
8018 16:47:38.524388 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8019 16:47:38.527901 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8020 16:47:38.530928 [Gating] SW calibration Done
8021 16:47:38.531044 ==
8022 16:47:38.534075 Dram Type= 6, Freq= 0, CH_0, rank 1
8023 16:47:38.540724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8024 16:47:38.540829 ==
8025 16:47:38.540985 RX Vref Scan: 0
8026 16:47:38.541073
8027 16:47:38.543837 RX Vref 0 -> 0, step: 1
8028 16:47:38.543934
8029 16:47:38.547581 RX Delay 0 -> 252, step: 8
8030 16:47:38.550833 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8031 16:47:38.553900 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8032 16:47:38.557037 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8033 16:47:38.564033 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8034 16:47:38.567624 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8035 16:47:38.570312 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8036 16:47:38.573461 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8037 16:47:38.577038 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8038 16:47:38.583479 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8039 16:47:38.587993 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8040 16:47:38.590074 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8041 16:47:38.593510 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8042 16:47:38.596620 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8043 16:47:38.603167 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8044 16:47:38.606995 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8045 16:47:38.610672 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8046 16:47:38.610776 ==
8047 16:47:38.613207 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 16:47:38.616499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 16:47:38.620415 ==
8050 16:47:38.620516 DQS Delay:
8051 16:47:38.620608 DQS0 = 0, DQS1 = 0
8052 16:47:38.623521 DQM Delay:
8053 16:47:38.623592 DQM0 = 131, DQM1 = 124
8054 16:47:38.626320 DQ Delay:
8055 16:47:38.629590 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8056 16:47:38.633082 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =135
8057 16:47:38.636278 DQ8 =115, DQ9 =111, DQ10 =131, DQ11 =115
8058 16:47:38.639502 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8059 16:47:38.639573
8060 16:47:38.639637
8061 16:47:38.639696 ==
8062 16:47:38.642789 Dram Type= 6, Freq= 0, CH_0, rank 1
8063 16:47:38.646642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8064 16:47:38.649499 ==
8065 16:47:38.649593
8066 16:47:38.649680
8067 16:47:38.649765 TX Vref Scan disable
8068 16:47:38.653003 == TX Byte 0 ==
8069 16:47:38.655891 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8070 16:47:38.659865 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8071 16:47:38.663381 == TX Byte 1 ==
8072 16:47:38.665754 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8073 16:47:38.668984 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8074 16:47:38.672646 ==
8075 16:47:38.675498 Dram Type= 6, Freq= 0, CH_0, rank 1
8076 16:47:38.679610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8077 16:47:38.679706 ==
8078 16:47:38.692082
8079 16:47:38.695967 TX Vref early break, caculate TX vref
8080 16:47:38.698904 TX Vref=16, minBit 1, minWin=23, winSum=380
8081 16:47:38.702419 TX Vref=18, minBit 3, minWin=23, winSum=387
8082 16:47:38.704868 TX Vref=20, minBit 0, minWin=24, winSum=395
8083 16:47:38.708385 TX Vref=22, minBit 8, minWin=24, winSum=404
8084 16:47:38.711949 TX Vref=24, minBit 2, minWin=24, winSum=408
8085 16:47:38.718163 TX Vref=26, minBit 3, minWin=25, winSum=417
8086 16:47:38.721773 TX Vref=28, minBit 10, minWin=25, winSum=421
8087 16:47:38.724948 TX Vref=30, minBit 1, minWin=25, winSum=414
8088 16:47:38.728633 TX Vref=32, minBit 1, minWin=24, winSum=404
8089 16:47:38.731515 TX Vref=34, minBit 0, minWin=24, winSum=398
8090 16:47:38.738011 [TxChooseVref] Worse bit 10, Min win 25, Win sum 421, Final Vref 28
8091 16:47:38.738115
8092 16:47:38.741236 Final TX Range 0 Vref 28
8093 16:47:38.741338
8094 16:47:38.741429 ==
8095 16:47:38.745484 Dram Type= 6, Freq= 0, CH_0, rank 1
8096 16:47:38.748549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8097 16:47:38.748652 ==
8098 16:47:38.748742
8099 16:47:38.748829
8100 16:47:38.751324 TX Vref Scan disable
8101 16:47:38.757769 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8102 16:47:38.757878 == TX Byte 0 ==
8103 16:47:38.761085 u2DelayCellOfst[0]=10 cells (3 PI)
8104 16:47:38.764427 u2DelayCellOfst[1]=14 cells (4 PI)
8105 16:47:38.768041 u2DelayCellOfst[2]=7 cells (2 PI)
8106 16:47:38.770790 u2DelayCellOfst[3]=10 cells (3 PI)
8107 16:47:38.774675 u2DelayCellOfst[4]=7 cells (2 PI)
8108 16:47:38.777700 u2DelayCellOfst[5]=0 cells (0 PI)
8109 16:47:38.780876 u2DelayCellOfst[6]=14 cells (4 PI)
8110 16:47:38.784328 u2DelayCellOfst[7]=14 cells (4 PI)
8111 16:47:38.787984 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8112 16:47:38.790451 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8113 16:47:38.793898 == TX Byte 1 ==
8114 16:47:38.798031 u2DelayCellOfst[8]=0 cells (0 PI)
8115 16:47:38.800807 u2DelayCellOfst[9]=0 cells (0 PI)
8116 16:47:38.803958 u2DelayCellOfst[10]=3 cells (1 PI)
8117 16:47:38.806985 u2DelayCellOfst[11]=0 cells (0 PI)
8118 16:47:38.810711 u2DelayCellOfst[12]=10 cells (3 PI)
8119 16:47:38.810785 u2DelayCellOfst[13]=10 cells (3 PI)
8120 16:47:38.813479 u2DelayCellOfst[14]=18 cells (5 PI)
8121 16:47:38.817337 u2DelayCellOfst[15]=10 cells (3 PI)
8122 16:47:38.823910 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8123 16:47:38.826792 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8124 16:47:38.829838 DramC Write-DBI on
8125 16:47:38.829940 ==
8126 16:47:38.833205 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 16:47:38.836814 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 16:47:38.836937 ==
8129 16:47:38.837030
8130 16:47:38.837119
8131 16:47:38.840109 TX Vref Scan disable
8132 16:47:38.840207 == TX Byte 0 ==
8133 16:47:38.846663 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8134 16:47:38.846771 == TX Byte 1 ==
8135 16:47:38.852885 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8136 16:47:38.852987 DramC Write-DBI off
8137 16:47:38.853070
8138 16:47:38.853130 [DATLAT]
8139 16:47:38.856100 Freq=1600, CH0 RK1
8140 16:47:38.856216
8141 16:47:38.859580 DATLAT Default: 0xf
8142 16:47:38.859655 0, 0xFFFF, sum = 0
8143 16:47:38.863393 1, 0xFFFF, sum = 0
8144 16:47:38.863481 2, 0xFFFF, sum = 0
8145 16:47:38.866068 3, 0xFFFF, sum = 0
8146 16:47:38.866205 4, 0xFFFF, sum = 0
8147 16:47:38.869812 5, 0xFFFF, sum = 0
8148 16:47:38.869969 6, 0xFFFF, sum = 0
8149 16:47:38.872948 7, 0xFFFF, sum = 0
8150 16:47:38.873067 8, 0xFFFF, sum = 0
8151 16:47:38.876041 9, 0xFFFF, sum = 0
8152 16:47:38.876117 10, 0xFFFF, sum = 0
8153 16:47:38.879512 11, 0xFFFF, sum = 0
8154 16:47:38.879643 12, 0xFFFF, sum = 0
8155 16:47:38.882568 13, 0xFFFF, sum = 0
8156 16:47:38.882680 14, 0x0, sum = 1
8157 16:47:38.886033 15, 0x0, sum = 2
8158 16:47:38.886159 16, 0x0, sum = 3
8159 16:47:38.889227 17, 0x0, sum = 4
8160 16:47:38.889330 best_step = 15
8161 16:47:38.889419
8162 16:47:38.889506 ==
8163 16:47:38.892719 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 16:47:38.899005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 16:47:38.899119 ==
8166 16:47:38.899222 RX Vref Scan: 0
8167 16:47:38.899298
8168 16:47:38.902447 RX Vref 0 -> 0, step: 1
8169 16:47:38.902520
8170 16:47:38.905746 RX Delay 11 -> 252, step: 4
8171 16:47:38.908734 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8172 16:47:38.912247 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8173 16:47:38.918808 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8174 16:47:38.922223 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8175 16:47:38.925245 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8176 16:47:38.928799 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8177 16:47:38.932179 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8178 16:47:38.938352 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8179 16:47:38.941900 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8180 16:47:38.945101 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8181 16:47:38.948671 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8182 16:47:38.951883 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8183 16:47:38.958194 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8184 16:47:38.961449 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8185 16:47:38.964680 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8186 16:47:38.967819 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8187 16:47:38.971445 ==
8188 16:47:38.974576 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 16:47:38.977898 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 16:47:38.977996 ==
8191 16:47:38.978084 DQS Delay:
8192 16:47:38.981320 DQS0 = 0, DQS1 = 0
8193 16:47:38.981446 DQM Delay:
8194 16:47:38.984443 DQM0 = 129, DQM1 = 124
8195 16:47:38.984552 DQ Delay:
8196 16:47:38.987635 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8197 16:47:38.991955 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8198 16:47:38.994827 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8199 16:47:38.997555 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8200 16:47:38.997650
8201 16:47:38.997737
8202 16:47:38.997824
8203 16:47:39.000925 [DramC_TX_OE_Calibration] TA2
8204 16:47:39.004148 Original DQ_B0 (3 6) =30, OEN = 27
8205 16:47:39.007496 Original DQ_B1 (3 6) =30, OEN = 27
8206 16:47:39.010753 24, 0x0, End_B0=24 End_B1=24
8207 16:47:39.014264 25, 0x0, End_B0=25 End_B1=25
8208 16:47:39.018125 26, 0x0, End_B0=26 End_B1=26
8209 16:47:39.018229 27, 0x0, End_B0=27 End_B1=27
8210 16:47:39.020385 28, 0x0, End_B0=28 End_B1=28
8211 16:47:39.023862 29, 0x0, End_B0=29 End_B1=29
8212 16:47:39.027180 30, 0x0, End_B0=30 End_B1=30
8213 16:47:39.030249 31, 0x4141, End_B0=30 End_B1=30
8214 16:47:39.030354 Byte0 end_step=30 best_step=27
8215 16:47:39.034512 Byte1 end_step=30 best_step=27
8216 16:47:39.036970 Byte0 TX OE(2T, 0.5T) = (3, 3)
8217 16:47:39.040464 Byte1 TX OE(2T, 0.5T) = (3, 3)
8218 16:47:39.040567
8219 16:47:39.040658
8220 16:47:39.047001 [DQSOSCAuto] RK1, (LSB)MR18= 0x110f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 401 ps
8221 16:47:39.050754 CH0 RK1: MR19=303, MR18=110F
8222 16:47:39.057140 CH0_RK1: MR19=0x303, MR18=0x110F, DQSOSC=401, MR23=63, INC=22, DEC=15
8223 16:47:39.060582 [RxdqsGatingPostProcess] freq 1600
8224 16:47:39.066507 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8225 16:47:39.070700 best DQS0 dly(2T, 0.5T) = (1, 1)
8226 16:47:39.073392 best DQS1 dly(2T, 0.5T) = (1, 1)
8227 16:47:39.076347 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8228 16:47:39.076449 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8229 16:47:39.079687 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 16:47:39.083003 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 16:47:39.086399 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 16:47:39.090075 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 16:47:39.093998 Pre-setting of DQS Precalculation
8234 16:47:39.099394 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8235 16:47:39.099478 ==
8236 16:47:39.102956 Dram Type= 6, Freq= 0, CH_1, rank 0
8237 16:47:39.106475 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 16:47:39.106634 ==
8239 16:47:39.112827 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8240 16:47:39.116144 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8241 16:47:39.119662 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8242 16:47:39.126337 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8243 16:47:39.134535 [CA 0] Center 42 (12~72) winsize 61
8244 16:47:39.137844 [CA 1] Center 42 (13~72) winsize 60
8245 16:47:39.141104 [CA 2] Center 38 (9~68) winsize 60
8246 16:47:39.144721 [CA 3] Center 38 (9~67) winsize 59
8247 16:47:39.148072 [CA 4] Center 38 (9~68) winsize 60
8248 16:47:39.151121 [CA 5] Center 37 (7~67) winsize 61
8249 16:47:39.151256
8250 16:47:39.154842 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8251 16:47:39.154924
8252 16:47:39.161081 [CATrainingPosCal] consider 1 rank data
8253 16:47:39.161199 u2DelayCellTimex100 = 271/100 ps
8254 16:47:39.167738 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8255 16:47:39.171000 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8256 16:47:39.174103 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8257 16:47:39.177612 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8258 16:47:39.180946 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8259 16:47:39.184119 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8260 16:47:39.184203
8261 16:47:39.187407 CA PerBit enable=1, Macro0, CA PI delay=37
8262 16:47:39.187492
8263 16:47:39.190737 [CBTSetCACLKResult] CA Dly = 37
8264 16:47:39.194243 CS Dly: 8 (0~39)
8265 16:47:39.197339 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8266 16:47:39.201192 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8267 16:47:39.201274 ==
8268 16:47:39.204282 Dram Type= 6, Freq= 0, CH_1, rank 1
8269 16:47:39.210927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8270 16:47:39.211036 ==
8271 16:47:39.213638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8272 16:47:39.220549 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8273 16:47:39.224056 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8274 16:47:39.230316 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8275 16:47:39.237969 [CA 0] Center 42 (12~72) winsize 61
8276 16:47:39.241350 [CA 1] Center 42 (13~72) winsize 60
8277 16:47:39.244722 [CA 2] Center 38 (8~68) winsize 61
8278 16:47:39.247832 [CA 3] Center 37 (8~67) winsize 60
8279 16:47:39.250985 [CA 4] Center 37 (8~67) winsize 60
8280 16:47:39.254389 [CA 5] Center 37 (7~67) winsize 61
8281 16:47:39.254474
8282 16:47:39.257517 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8283 16:47:39.257612
8284 16:47:39.264605 [CATrainingPosCal] consider 2 rank data
8285 16:47:39.264689 u2DelayCellTimex100 = 271/100 ps
8286 16:47:39.270688 CA0 delay=42 (12~72),Diff = 5 PI (18 cell)
8287 16:47:39.273985 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8288 16:47:39.277222 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8289 16:47:39.280478 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8290 16:47:39.283700 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8291 16:47:39.287043 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8292 16:47:39.287127
8293 16:47:39.290668 CA PerBit enable=1, Macro0, CA PI delay=37
8294 16:47:39.290741
8295 16:47:39.293777 [CBTSetCACLKResult] CA Dly = 37
8296 16:47:39.297119 CS Dly: 9 (0~42)
8297 16:47:39.300467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8298 16:47:39.303447 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8299 16:47:39.303529
8300 16:47:39.306915 ----->DramcWriteLeveling(PI) begin...
8301 16:47:39.307004 ==
8302 16:47:39.309872 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 16:47:39.316916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 16:47:39.316997 ==
8305 16:47:39.320137 Write leveling (Byte 0): 23 => 23
8306 16:47:39.323451 Write leveling (Byte 1): 26 => 26
8307 16:47:39.326538 DramcWriteLeveling(PI) end<-----
8308 16:47:39.326617
8309 16:47:39.326678 ==
8310 16:47:39.329801 Dram Type= 6, Freq= 0, CH_1, rank 0
8311 16:47:39.333359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 16:47:39.333438 ==
8313 16:47:39.336626 [Gating] SW mode calibration
8314 16:47:39.343273 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8315 16:47:39.349500 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8316 16:47:39.353077 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8317 16:47:39.356489 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 16:47:39.362705 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 16:47:39.366372 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
8320 16:47:39.369658 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8321 16:47:39.376056 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8322 16:47:39.379333 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8323 16:47:39.382655 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 16:47:39.388943 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 16:47:39.392183 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 16:47:39.395868 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8327 16:47:39.402176 1 5 12 | B1->B0 | 3333 2525 | 1 0 | (1 0) (0 0)
8328 16:47:39.405772 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8329 16:47:39.408895 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 16:47:39.415143 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 16:47:39.418932 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 16:47:39.422444 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 16:47:39.428495 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 16:47:39.432226 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8335 16:47:39.435294 1 6 12 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
8336 16:47:39.441915 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8337 16:47:39.445107 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8338 16:47:39.448682 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8339 16:47:39.452254 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 16:47:39.458398 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 16:47:39.462236 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 16:47:39.468964 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8343 16:47:39.472047 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8344 16:47:39.474971 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8345 16:47:39.481561 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 16:47:39.484788 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 16:47:39.487729 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8348 16:47:39.494958 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 16:47:39.497696 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 16:47:39.501275 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 16:47:39.507763 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 16:47:39.510856 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 16:47:39.514195 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 16:47:39.521148 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 16:47:39.523861 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 16:47:39.527769 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 16:47:39.533686 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 16:47:39.537371 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8359 16:47:39.540514 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8360 16:47:39.547128 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8361 16:47:39.547234 Total UI for P1: 0, mck2ui 16
8362 16:47:39.553477 best dqsien dly found for B0: ( 1, 9, 10)
8363 16:47:39.556961 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 16:47:39.560319 Total UI for P1: 0, mck2ui 16
8365 16:47:39.563513 best dqsien dly found for B1: ( 1, 9, 16)
8366 16:47:39.566883 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8367 16:47:39.570231 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8368 16:47:39.570313
8369 16:47:39.573573 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8370 16:47:39.576537 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8371 16:47:39.580309 [Gating] SW calibration Done
8372 16:47:39.580391 ==
8373 16:47:39.583313 Dram Type= 6, Freq= 0, CH_1, rank 0
8374 16:47:39.590171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8375 16:47:39.590267 ==
8376 16:47:39.590333 RX Vref Scan: 0
8377 16:47:39.590393
8378 16:47:39.593571 RX Vref 0 -> 0, step: 1
8379 16:47:39.593659
8380 16:47:39.596275 RX Delay 0 -> 252, step: 8
8381 16:47:39.600251 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8382 16:47:39.603098 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8383 16:47:39.606264 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8384 16:47:39.609357 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8385 16:47:39.615931 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8386 16:47:39.619862 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8387 16:47:39.622855 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8388 16:47:39.625879 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8389 16:47:39.632455 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8390 16:47:39.635897 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8391 16:47:39.639135 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8392 16:47:39.642281 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8393 16:47:39.645582 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8394 16:47:39.652611 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8395 16:47:39.655336 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8396 16:47:39.658630 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8397 16:47:39.658713 ==
8398 16:47:39.662152 Dram Type= 6, Freq= 0, CH_1, rank 0
8399 16:47:39.665148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8400 16:47:39.668666 ==
8401 16:47:39.668749 DQS Delay:
8402 16:47:39.668814 DQS0 = 0, DQS1 = 0
8403 16:47:39.672016 DQM Delay:
8404 16:47:39.672098 DQM0 = 134, DQM1 = 131
8405 16:47:39.675161 DQ Delay:
8406 16:47:39.678600 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8407 16:47:39.681698 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8408 16:47:39.685332 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8409 16:47:39.688633 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8410 16:47:39.688716
8411 16:47:39.688781
8412 16:47:39.688840 ==
8413 16:47:39.691570 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 16:47:39.695101 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 16:47:39.698421 ==
8416 16:47:39.698528
8417 16:47:39.698598
8418 16:47:39.698660 TX Vref Scan disable
8419 16:47:39.701957 == TX Byte 0 ==
8420 16:47:39.705086 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8421 16:47:39.708255 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8422 16:47:39.711341 == TX Byte 1 ==
8423 16:47:39.714783 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8424 16:47:39.718044 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8425 16:47:39.722065 ==
8426 16:47:39.724837 Dram Type= 6, Freq= 0, CH_1, rank 0
8427 16:47:39.728391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8428 16:47:39.728574 ==
8429 16:47:39.740009
8430 16:47:39.743111 TX Vref early break, caculate TX vref
8431 16:47:39.747022 TX Vref=16, minBit 8, minWin=21, winSum=367
8432 16:47:39.750477 TX Vref=18, minBit 9, minWin=21, winSum=374
8433 16:47:39.753043 TX Vref=20, minBit 6, minWin=23, winSum=386
8434 16:47:39.756477 TX Vref=22, minBit 8, minWin=23, winSum=397
8435 16:47:39.759603 TX Vref=24, minBit 9, minWin=24, winSum=407
8436 16:47:39.766288 TX Vref=26, minBit 8, minWin=24, winSum=415
8437 16:47:39.769798 TX Vref=28, minBit 0, minWin=25, winSum=417
8438 16:47:39.773057 TX Vref=30, minBit 14, minWin=25, winSum=421
8439 16:47:39.776162 TX Vref=32, minBit 9, minWin=24, winSum=406
8440 16:47:39.779311 TX Vref=34, minBit 9, minWin=23, winSum=396
8441 16:47:39.785950 [TxChooseVref] Worse bit 14, Min win 25, Win sum 421, Final Vref 30
8442 16:47:39.786072
8443 16:47:39.789085 Final TX Range 0 Vref 30
8444 16:47:39.789196
8445 16:47:39.789291 ==
8446 16:47:39.792610 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 16:47:39.795951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 16:47:39.796053 ==
8449 16:47:39.799753
8450 16:47:39.799857
8451 16:47:39.799946 TX Vref Scan disable
8452 16:47:39.805492 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8453 16:47:39.805593 == TX Byte 0 ==
8454 16:47:39.809143 u2DelayCellOfst[0]=14 cells (4 PI)
8455 16:47:39.812132 u2DelayCellOfst[1]=7 cells (2 PI)
8456 16:47:39.815496 u2DelayCellOfst[2]=0 cells (0 PI)
8457 16:47:39.818732 u2DelayCellOfst[3]=3 cells (1 PI)
8458 16:47:39.822196 u2DelayCellOfst[4]=7 cells (2 PI)
8459 16:47:39.825396 u2DelayCellOfst[5]=14 cells (4 PI)
8460 16:47:39.828740 u2DelayCellOfst[6]=14 cells (4 PI)
8461 16:47:39.831775 u2DelayCellOfst[7]=3 cells (1 PI)
8462 16:47:39.835060 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8463 16:47:39.838428 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8464 16:47:39.841856 == TX Byte 1 ==
8465 16:47:39.845373 u2DelayCellOfst[8]=0 cells (0 PI)
8466 16:47:39.848809 u2DelayCellOfst[9]=3 cells (1 PI)
8467 16:47:39.851931 u2DelayCellOfst[10]=10 cells (3 PI)
8468 16:47:39.855056 u2DelayCellOfst[11]=7 cells (2 PI)
8469 16:47:39.858437 u2DelayCellOfst[12]=14 cells (4 PI)
8470 16:47:39.858548 u2DelayCellOfst[13]=18 cells (5 PI)
8471 16:47:39.861341 u2DelayCellOfst[14]=18 cells (5 PI)
8472 16:47:39.865394 u2DelayCellOfst[15]=18 cells (5 PI)
8473 16:47:39.871319 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8474 16:47:39.875047 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8475 16:47:39.878016 DramC Write-DBI on
8476 16:47:39.878112 ==
8477 16:47:39.881565 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 16:47:39.884506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 16:47:39.884589 ==
8480 16:47:39.884653
8481 16:47:39.884711
8482 16:47:39.888309 TX Vref Scan disable
8483 16:47:39.888392 == TX Byte 0 ==
8484 16:47:39.895105 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8485 16:47:39.895213 == TX Byte 1 ==
8486 16:47:39.898047 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8487 16:47:39.901382 DramC Write-DBI off
8488 16:47:39.901467
8489 16:47:39.901551 [DATLAT]
8490 16:47:39.904336 Freq=1600, CH1 RK0
8491 16:47:39.904422
8492 16:47:39.904506 DATLAT Default: 0xf
8493 16:47:39.907591 0, 0xFFFF, sum = 0
8494 16:47:39.907678 1, 0xFFFF, sum = 0
8495 16:47:39.911151 2, 0xFFFF, sum = 0
8496 16:47:39.914092 3, 0xFFFF, sum = 0
8497 16:47:39.914174 4, 0xFFFF, sum = 0
8498 16:47:39.917473 5, 0xFFFF, sum = 0
8499 16:47:39.917557 6, 0xFFFF, sum = 0
8500 16:47:39.921366 7, 0xFFFF, sum = 0
8501 16:47:39.921449 8, 0xFFFF, sum = 0
8502 16:47:39.924326 9, 0xFFFF, sum = 0
8503 16:47:39.924454 10, 0xFFFF, sum = 0
8504 16:47:39.927304 11, 0xFFFF, sum = 0
8505 16:47:39.927387 12, 0xFFFF, sum = 0
8506 16:47:39.930826 13, 0xFFFF, sum = 0
8507 16:47:39.930909 14, 0x0, sum = 1
8508 16:47:39.933694 15, 0x0, sum = 2
8509 16:47:39.933777 16, 0x0, sum = 3
8510 16:47:39.937015 17, 0x0, sum = 4
8511 16:47:39.937099 best_step = 15
8512 16:47:39.937163
8513 16:47:39.937222 ==
8514 16:47:39.940277 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 16:47:39.946796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 16:47:39.946878 ==
8517 16:47:39.946942 RX Vref Scan: 1
8518 16:47:39.947000
8519 16:47:39.950283 Set Vref Range= 24 -> 127
8520 16:47:39.950365
8521 16:47:39.953557 RX Vref 24 -> 127, step: 1
8522 16:47:39.953642
8523 16:47:39.953706 RX Delay 19 -> 252, step: 4
8524 16:47:39.956948
8525 16:47:39.957058 Set Vref, RX VrefLevel [Byte0]: 24
8526 16:47:39.960087 [Byte1]: 24
8527 16:47:39.964873
8528 16:47:39.964984 Set Vref, RX VrefLevel [Byte0]: 25
8529 16:47:39.967838 [Byte1]: 25
8530 16:47:39.972133
8531 16:47:39.972214 Set Vref, RX VrefLevel [Byte0]: 26
8532 16:47:39.975540 [Byte1]: 26
8533 16:47:39.979511
8534 16:47:39.979594 Set Vref, RX VrefLevel [Byte0]: 27
8535 16:47:39.982895 [Byte1]: 27
8536 16:47:39.987116
8537 16:47:39.987248 Set Vref, RX VrefLevel [Byte0]: 28
8538 16:47:39.990677 [Byte1]: 28
8539 16:47:39.994738
8540 16:47:39.994846 Set Vref, RX VrefLevel [Byte0]: 29
8541 16:47:39.998240 [Byte1]: 29
8542 16:47:40.002462
8543 16:47:40.002570 Set Vref, RX VrefLevel [Byte0]: 30
8544 16:47:40.005702 [Byte1]: 30
8545 16:47:40.009911
8546 16:47:40.010011 Set Vref, RX VrefLevel [Byte0]: 31
8547 16:47:40.013265 [Byte1]: 31
8548 16:47:40.017363
8549 16:47:40.017464 Set Vref, RX VrefLevel [Byte0]: 32
8550 16:47:40.020921 [Byte1]: 32
8551 16:47:40.024861
8552 16:47:40.024973 Set Vref, RX VrefLevel [Byte0]: 33
8553 16:47:40.028083 [Byte1]: 33
8554 16:47:40.033030
8555 16:47:40.033112 Set Vref, RX VrefLevel [Byte0]: 34
8556 16:47:40.036360 [Byte1]: 34
8557 16:47:40.040074
8558 16:47:40.040155 Set Vref, RX VrefLevel [Byte0]: 35
8559 16:47:40.043372 [Byte1]: 35
8560 16:47:40.048053
8561 16:47:40.048136 Set Vref, RX VrefLevel [Byte0]: 36
8562 16:47:40.051401 [Byte1]: 36
8563 16:47:40.055321
8564 16:47:40.055406 Set Vref, RX VrefLevel [Byte0]: 37
8565 16:47:40.058649 [Byte1]: 37
8566 16:47:40.062805
8567 16:47:40.062904 Set Vref, RX VrefLevel [Byte0]: 38
8568 16:47:40.066140 [Byte1]: 38
8569 16:47:40.070526
8570 16:47:40.070613 Set Vref, RX VrefLevel [Byte0]: 39
8571 16:47:40.073863 [Byte1]: 39
8572 16:47:40.078009
8573 16:47:40.078092 Set Vref, RX VrefLevel [Byte0]: 40
8574 16:47:40.081587 [Byte1]: 40
8575 16:47:40.086002
8576 16:47:40.086103 Set Vref, RX VrefLevel [Byte0]: 41
8577 16:47:40.089109 [Byte1]: 41
8578 16:47:40.093315
8579 16:47:40.093398 Set Vref, RX VrefLevel [Byte0]: 42
8580 16:47:40.096335 [Byte1]: 42
8581 16:47:40.100997
8582 16:47:40.101083 Set Vref, RX VrefLevel [Byte0]: 43
8583 16:47:40.104103 [Byte1]: 43
8584 16:47:40.108234
8585 16:47:40.108317 Set Vref, RX VrefLevel [Byte0]: 44
8586 16:47:40.111751 [Byte1]: 44
8587 16:47:40.115810
8588 16:47:40.115895 Set Vref, RX VrefLevel [Byte0]: 45
8589 16:47:40.119563 [Byte1]: 45
8590 16:47:40.124090
8591 16:47:40.124195 Set Vref, RX VrefLevel [Byte0]: 46
8592 16:47:40.126648 [Byte1]: 46
8593 16:47:40.130819
8594 16:47:40.130926 Set Vref, RX VrefLevel [Byte0]: 47
8595 16:47:40.134812 [Byte1]: 47
8596 16:47:40.138681
8597 16:47:40.138783 Set Vref, RX VrefLevel [Byte0]: 48
8598 16:47:40.142046 [Byte1]: 48
8599 16:47:40.146275
8600 16:47:40.146376 Set Vref, RX VrefLevel [Byte0]: 49
8601 16:47:40.149130 [Byte1]: 49
8602 16:47:40.153571
8603 16:47:40.153671 Set Vref, RX VrefLevel [Byte0]: 50
8604 16:47:40.157231 [Byte1]: 50
8605 16:47:40.161494
8606 16:47:40.161596 Set Vref, RX VrefLevel [Byte0]: 51
8607 16:47:40.165024 [Byte1]: 51
8608 16:47:40.169952
8609 16:47:40.170050 Set Vref, RX VrefLevel [Byte0]: 52
8610 16:47:40.172012 [Byte1]: 52
8611 16:47:40.176246
8612 16:47:40.176325 Set Vref, RX VrefLevel [Byte0]: 53
8613 16:47:40.180102 [Byte1]: 53
8614 16:47:40.184236
8615 16:47:40.184335 Set Vref, RX VrefLevel [Byte0]: 54
8616 16:47:40.187345 [Byte1]: 54
8617 16:47:40.191420
8618 16:47:40.191496 Set Vref, RX VrefLevel [Byte0]: 55
8619 16:47:40.195101 [Byte1]: 55
8620 16:47:40.199274
8621 16:47:40.199351 Set Vref, RX VrefLevel [Byte0]: 56
8622 16:47:40.202256 [Byte1]: 56
8623 16:47:40.206545
8624 16:47:40.206642 Set Vref, RX VrefLevel [Byte0]: 57
8625 16:47:40.209960 [Byte1]: 57
8626 16:47:40.214358
8627 16:47:40.214441 Set Vref, RX VrefLevel [Byte0]: 58
8628 16:47:40.217506 [Byte1]: 58
8629 16:47:40.221951
8630 16:47:40.222033 Set Vref, RX VrefLevel [Byte0]: 59
8631 16:47:40.225916 [Byte1]: 59
8632 16:47:40.229780
8633 16:47:40.229862 Set Vref, RX VrefLevel [Byte0]: 60
8634 16:47:40.232802 [Byte1]: 60
8635 16:47:40.237267
8636 16:47:40.237349 Set Vref, RX VrefLevel [Byte0]: 61
8637 16:47:40.240472 [Byte1]: 61
8638 16:47:40.244594
8639 16:47:40.244677 Set Vref, RX VrefLevel [Byte0]: 62
8640 16:47:40.247987 [Byte1]: 62
8641 16:47:40.252333
8642 16:47:40.252415 Set Vref, RX VrefLevel [Byte0]: 63
8643 16:47:40.255368 [Byte1]: 63
8644 16:47:40.259493
8645 16:47:40.259575 Set Vref, RX VrefLevel [Byte0]: 64
8646 16:47:40.263065 [Byte1]: 64
8647 16:47:40.267327
8648 16:47:40.267422 Set Vref, RX VrefLevel [Byte0]: 65
8649 16:47:40.270676 [Byte1]: 65
8650 16:47:40.274831
8651 16:47:40.274943 Set Vref, RX VrefLevel [Byte0]: 66
8652 16:47:40.278553 [Byte1]: 66
8653 16:47:40.282549
8654 16:47:40.282640 Set Vref, RX VrefLevel [Byte0]: 67
8655 16:47:40.285929 [Byte1]: 67
8656 16:47:40.290038
8657 16:47:40.290121 Set Vref, RX VrefLevel [Byte0]: 68
8658 16:47:40.293135 [Byte1]: 68
8659 16:47:40.297972
8660 16:47:40.298056 Set Vref, RX VrefLevel [Byte0]: 69
8661 16:47:40.301440 [Byte1]: 69
8662 16:47:40.305334
8663 16:47:40.305418 Set Vref, RX VrefLevel [Byte0]: 70
8664 16:47:40.308416 [Byte1]: 70
8665 16:47:40.313109
8666 16:47:40.313191 Final RX Vref Byte 0 = 54 to rank0
8667 16:47:40.316273 Final RX Vref Byte 1 = 61 to rank0
8668 16:47:40.319225 Final RX Vref Byte 0 = 54 to rank1
8669 16:47:40.322306 Final RX Vref Byte 1 = 61 to rank1==
8670 16:47:40.325720 Dram Type= 6, Freq= 0, CH_1, rank 0
8671 16:47:40.332598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8672 16:47:40.332695 ==
8673 16:47:40.332807 DQS Delay:
8674 16:47:40.335566 DQS0 = 0, DQS1 = 0
8675 16:47:40.335650 DQM Delay:
8676 16:47:40.338735 DQM0 = 131, DQM1 = 130
8677 16:47:40.338817 DQ Delay:
8678 16:47:40.342432 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8679 16:47:40.345845 DQ4 =126, DQ5 =142, DQ6 =144, DQ7 =126
8680 16:47:40.348733 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8681 16:47:40.352090 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8682 16:47:40.352173
8683 16:47:40.352241
8684 16:47:40.352303
8685 16:47:40.355133 [DramC_TX_OE_Calibration] TA2
8686 16:47:40.358645 Original DQ_B0 (3 6) =30, OEN = 27
8687 16:47:40.362095 Original DQ_B1 (3 6) =30, OEN = 27
8688 16:47:40.365725 24, 0x0, End_B0=24 End_B1=24
8689 16:47:40.368508 25, 0x0, End_B0=25 End_B1=25
8690 16:47:40.368593 26, 0x0, End_B0=26 End_B1=26
8691 16:47:40.371722 27, 0x0, End_B0=27 End_B1=27
8692 16:47:40.375099 28, 0x0, End_B0=28 End_B1=28
8693 16:47:40.378607 29, 0x0, End_B0=29 End_B1=29
8694 16:47:40.381765 30, 0x0, End_B0=30 End_B1=30
8695 16:47:40.381841 31, 0x4141, End_B0=30 End_B1=30
8696 16:47:40.384782 Byte0 end_step=30 best_step=27
8697 16:47:40.388192 Byte1 end_step=30 best_step=27
8698 16:47:40.391301 Byte0 TX OE(2T, 0.5T) = (3, 3)
8699 16:47:40.394671 Byte1 TX OE(2T, 0.5T) = (3, 3)
8700 16:47:40.394760
8701 16:47:40.394864
8702 16:47:40.401124 [DQSOSCAuto] RK0, (LSB)MR18= 0xa13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
8703 16:47:40.404656 CH1 RK0: MR19=303, MR18=A13
8704 16:47:40.411364 CH1_RK0: MR19=0x303, MR18=0xA13, DQSOSC=400, MR23=63, INC=23, DEC=15
8705 16:47:40.411442
8706 16:47:40.414485 ----->DramcWriteLeveling(PI) begin...
8707 16:47:40.414567 ==
8708 16:47:40.417868 Dram Type= 6, Freq= 0, CH_1, rank 1
8709 16:47:40.421418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8710 16:47:40.421493 ==
8711 16:47:40.424388 Write leveling (Byte 0): 23 => 23
8712 16:47:40.427895 Write leveling (Byte 1): 27 => 27
8713 16:47:40.430832 DramcWriteLeveling(PI) end<-----
8714 16:47:40.430922
8715 16:47:40.430986 ==
8716 16:47:40.433993 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 16:47:40.440513 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 16:47:40.440599 ==
8719 16:47:40.440663 [Gating] SW mode calibration
8720 16:47:40.450612 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8721 16:47:40.453894 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8722 16:47:40.460508 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8723 16:47:40.463564 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8724 16:47:40.467103 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8725 16:47:40.473345 1 4 12 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
8726 16:47:40.476832 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8727 16:47:40.480471 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8728 16:47:40.486536 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8729 16:47:40.489986 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8730 16:47:40.493250 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 16:47:40.499639 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 16:47:40.503411 1 5 8 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
8733 16:47:40.506151 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8734 16:47:40.512888 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8735 16:47:40.516440 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 16:47:40.519528 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8737 16:47:40.526155 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8738 16:47:40.529676 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8739 16:47:40.533175 1 6 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8740 16:47:40.539123 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8741 16:47:40.542548 1 6 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8742 16:47:40.546122 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8743 16:47:40.552566 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8744 16:47:40.555993 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8745 16:47:40.559097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8746 16:47:40.565547 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 16:47:40.569203 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8748 16:47:40.572207 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8749 16:47:40.578969 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8750 16:47:40.582260 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8751 16:47:40.585796 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8752 16:47:40.592371 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8753 16:47:40.595507 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8754 16:47:40.599036 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8755 16:47:40.605445 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 16:47:40.608556 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 16:47:40.611609 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 16:47:40.618134 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 16:47:40.621525 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 16:47:40.624766 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 16:47:40.631938 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 16:47:40.634598 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 16:47:40.637795 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8764 16:47:40.644816 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8765 16:47:40.648332 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8766 16:47:40.651349 Total UI for P1: 0, mck2ui 16
8767 16:47:40.654641 best dqsien dly found for B0: ( 1, 9, 6)
8768 16:47:40.657702 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 16:47:40.660781 Total UI for P1: 0, mck2ui 16
8770 16:47:40.664186 best dqsien dly found for B1: ( 1, 9, 12)
8771 16:47:40.668149 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8772 16:47:40.670923 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8773 16:47:40.671006
8774 16:47:40.677484 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8775 16:47:40.680729 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8776 16:47:40.684624 [Gating] SW calibration Done
8777 16:47:40.684703 ==
8778 16:47:40.687419 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 16:47:40.690498 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 16:47:40.690576 ==
8781 16:47:40.690672 RX Vref Scan: 0
8782 16:47:40.694081
8783 16:47:40.694158 RX Vref 0 -> 0, step: 1
8784 16:47:40.694219
8785 16:47:40.697047 RX Delay 0 -> 252, step: 8
8786 16:47:40.700362 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8787 16:47:40.703942 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8788 16:47:40.710634 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8789 16:47:40.713752 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8790 16:47:40.716893 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8791 16:47:40.720763 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8792 16:47:40.723748 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8793 16:47:40.729989 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8794 16:47:40.733622 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8795 16:47:40.736926 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8796 16:47:40.740047 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8797 16:47:40.746679 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8798 16:47:40.749831 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8799 16:47:40.753162 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8800 16:47:40.756592 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8801 16:47:40.759603 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8802 16:47:40.763114 ==
8803 16:47:40.766294 Dram Type= 6, Freq= 0, CH_1, rank 1
8804 16:47:40.769655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8805 16:47:40.769741 ==
8806 16:47:40.769809 DQS Delay:
8807 16:47:40.772549 DQS0 = 0, DQS1 = 0
8808 16:47:40.772629 DQM Delay:
8809 16:47:40.775952 DQM0 = 136, DQM1 = 130
8810 16:47:40.776024 DQ Delay:
8811 16:47:40.779562 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8812 16:47:40.782795 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8813 16:47:40.785659 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8814 16:47:40.789170 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8815 16:47:40.789253
8816 16:47:40.789319
8817 16:47:40.792386 ==
8818 16:47:40.792460 Dram Type= 6, Freq= 0, CH_1, rank 1
8819 16:47:40.799227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8820 16:47:40.799307 ==
8821 16:47:40.799373
8822 16:47:40.799431
8823 16:47:40.802261 TX Vref Scan disable
8824 16:47:40.802339 == TX Byte 0 ==
8825 16:47:40.805634 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8826 16:47:40.813055 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8827 16:47:40.813131 == TX Byte 1 ==
8828 16:47:40.815524 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8829 16:47:40.822007 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8830 16:47:40.822087 ==
8831 16:47:40.825645 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 16:47:40.828773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 16:47:40.828843 ==
8834 16:47:40.844692
8835 16:47:40.847854 TX Vref early break, caculate TX vref
8836 16:47:40.851119 TX Vref=16, minBit 9, minWin=21, winSum=377
8837 16:47:40.854136 TX Vref=18, minBit 9, minWin=22, winSum=389
8838 16:47:40.858609 TX Vref=20, minBit 9, minWin=22, winSum=395
8839 16:47:40.860823 TX Vref=22, minBit 9, minWin=23, winSum=404
8840 16:47:40.864075 TX Vref=24, minBit 9, minWin=24, winSum=408
8841 16:47:40.870877 TX Vref=26, minBit 9, minWin=24, winSum=413
8842 16:47:40.874166 TX Vref=28, minBit 9, minWin=24, winSum=418
8843 16:47:40.877525 TX Vref=30, minBit 9, minWin=24, winSum=415
8844 16:47:40.880492 TX Vref=32, minBit 9, minWin=24, winSum=408
8845 16:47:40.883863 TX Vref=34, minBit 9, minWin=23, winSum=402
8846 16:47:40.887270 TX Vref=36, minBit 9, minWin=23, winSum=397
8847 16:47:40.893829 TX Vref=38, minBit 9, minWin=22, winSum=388
8848 16:47:40.897127 [TxChooseVref] Worse bit 9, Min win 24, Win sum 418, Final Vref 28
8849 16:47:40.897216
8850 16:47:40.900490 Final TX Range 0 Vref 28
8851 16:47:40.900566
8852 16:47:40.900628 ==
8853 16:47:40.903743 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 16:47:40.910200 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 16:47:40.910299 ==
8856 16:47:40.910370
8857 16:47:40.910434
8858 16:47:40.910494 TX Vref Scan disable
8859 16:47:40.917887 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8860 16:47:40.917972 == TX Byte 0 ==
8861 16:47:40.920883 u2DelayCellOfst[0]=10 cells (3 PI)
8862 16:47:40.923796 u2DelayCellOfst[1]=7 cells (2 PI)
8863 16:47:40.927460 u2DelayCellOfst[2]=0 cells (0 PI)
8864 16:47:40.930946 u2DelayCellOfst[3]=3 cells (1 PI)
8865 16:47:40.933822 u2DelayCellOfst[4]=7 cells (2 PI)
8866 16:47:40.936983 u2DelayCellOfst[5]=10 cells (3 PI)
8867 16:47:40.940193 u2DelayCellOfst[6]=14 cells (4 PI)
8868 16:47:40.944017 u2DelayCellOfst[7]=3 cells (1 PI)
8869 16:47:40.946830 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8870 16:47:40.950217 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8871 16:47:40.953624 == TX Byte 1 ==
8872 16:47:40.956804 u2DelayCellOfst[8]=0 cells (0 PI)
8873 16:47:40.960022 u2DelayCellOfst[9]=3 cells (1 PI)
8874 16:47:40.963734 u2DelayCellOfst[10]=10 cells (3 PI)
8875 16:47:40.967745 u2DelayCellOfst[11]=3 cells (1 PI)
8876 16:47:40.969829 u2DelayCellOfst[12]=14 cells (4 PI)
8877 16:47:40.973906 u2DelayCellOfst[13]=14 cells (4 PI)
8878 16:47:40.977087 u2DelayCellOfst[14]=18 cells (5 PI)
8879 16:47:40.979862 u2DelayCellOfst[15]=18 cells (5 PI)
8880 16:47:40.983244 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8881 16:47:40.986581 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8882 16:47:40.989621 DramC Write-DBI on
8883 16:47:40.989710 ==
8884 16:47:40.992868 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 16:47:40.996412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 16:47:40.996503 ==
8887 16:47:40.996580
8888 16:47:40.996641
8889 16:47:40.999589 TX Vref Scan disable
8890 16:47:40.999659 == TX Byte 0 ==
8891 16:47:41.006550 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8892 16:47:41.006626 == TX Byte 1 ==
8893 16:47:41.013562 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8894 16:47:41.013637 DramC Write-DBI off
8895 16:47:41.013699
8896 16:47:41.013756 [DATLAT]
8897 16:47:41.016356 Freq=1600, CH1 RK1
8898 16:47:41.016423
8899 16:47:41.019186 DATLAT Default: 0xf
8900 16:47:41.019272 0, 0xFFFF, sum = 0
8901 16:47:41.022460 1, 0xFFFF, sum = 0
8902 16:47:41.022533 2, 0xFFFF, sum = 0
8903 16:47:41.025905 3, 0xFFFF, sum = 0
8904 16:47:41.025981 4, 0xFFFF, sum = 0
8905 16:47:41.029506 5, 0xFFFF, sum = 0
8906 16:47:41.029603 6, 0xFFFF, sum = 0
8907 16:47:41.032418 7, 0xFFFF, sum = 0
8908 16:47:41.032495 8, 0xFFFF, sum = 0
8909 16:47:41.035801 9, 0xFFFF, sum = 0
8910 16:47:41.035888 10, 0xFFFF, sum = 0
8911 16:47:41.039104 11, 0xFFFF, sum = 0
8912 16:47:41.039209 12, 0xFFFF, sum = 0
8913 16:47:41.042010 13, 0xFFFF, sum = 0
8914 16:47:41.042101 14, 0x0, sum = 1
8915 16:47:41.045509 15, 0x0, sum = 2
8916 16:47:41.045578 16, 0x0, sum = 3
8917 16:47:41.049152 17, 0x0, sum = 4
8918 16:47:41.049236 best_step = 15
8919 16:47:41.049312
8920 16:47:41.049369 ==
8921 16:47:41.052210 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 16:47:41.059068 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 16:47:41.059150 ==
8924 16:47:41.059261 RX Vref Scan: 0
8925 16:47:41.059322
8926 16:47:41.062215 RX Vref 0 -> 0, step: 1
8927 16:47:41.062286
8928 16:47:41.065749 RX Delay 11 -> 252, step: 4
8929 16:47:41.069197 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8930 16:47:41.071677 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8931 16:47:41.078501 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8932 16:47:41.081928 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8933 16:47:41.085040 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8934 16:47:41.088243 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8935 16:47:41.091513 iDelay=195, Bit 6, Center 140 (91 ~ 190) 100
8936 16:47:41.098344 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8937 16:47:41.101680 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8938 16:47:41.104933 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8939 16:47:41.108062 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8940 16:47:41.111506 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8941 16:47:41.118174 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8942 16:47:41.121366 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8943 16:47:41.124598 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8944 16:47:41.128080 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8945 16:47:41.131065 ==
8946 16:47:41.134983 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 16:47:41.137693 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 16:47:41.137851 ==
8949 16:47:41.137959 DQS Delay:
8950 16:47:41.141136 DQS0 = 0, DQS1 = 0
8951 16:47:41.141213 DQM Delay:
8952 16:47:41.144046 DQM0 = 132, DQM1 = 128
8953 16:47:41.144121 DQ Delay:
8954 16:47:41.147940 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8955 16:47:41.150659 DQ4 =132, DQ5 =142, DQ6 =140, DQ7 =130
8956 16:47:41.154441 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8957 16:47:41.157625 DQ12 =136, DQ13 =136, DQ14 =134, DQ15 =138
8958 16:47:41.157701
8959 16:47:41.157767
8960 16:47:41.157827
8961 16:47:41.162176 [DramC_TX_OE_Calibration] TA2
8962 16:47:41.163552 Original DQ_B0 (3 6) =30, OEN = 27
8963 16:47:41.167245 Original DQ_B1 (3 6) =30, OEN = 27
8964 16:47:41.170608 24, 0x0, End_B0=24 End_B1=24
8965 16:47:41.173724 25, 0x0, End_B0=25 End_B1=25
8966 16:47:41.177273 26, 0x0, End_B0=26 End_B1=26
8967 16:47:41.177363 27, 0x0, End_B0=27 End_B1=27
8968 16:47:41.180334 28, 0x0, End_B0=28 End_B1=28
8969 16:47:41.183413 29, 0x0, End_B0=29 End_B1=29
8970 16:47:41.186685 30, 0x0, End_B0=30 End_B1=30
8971 16:47:41.190024 31, 0x4141, End_B0=30 End_B1=30
8972 16:47:41.190106 Byte0 end_step=30 best_step=27
8973 16:47:41.193759 Byte1 end_step=30 best_step=27
8974 16:47:41.196657 Byte0 TX OE(2T, 0.5T) = (3, 3)
8975 16:47:41.200251 Byte1 TX OE(2T, 0.5T) = (3, 3)
8976 16:47:41.200322
8977 16:47:41.200382
8978 16:47:41.206612 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8979 16:47:41.210931 CH1 RK1: MR19=303, MR18=C1B
8980 16:47:41.216923 CH1_RK1: MR19=0x303, MR18=0xC1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8981 16:47:41.220092 [RxdqsGatingPostProcess] freq 1600
8982 16:47:41.226416 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8983 16:47:41.229542 best DQS0 dly(2T, 0.5T) = (1, 1)
8984 16:47:41.233055 best DQS1 dly(2T, 0.5T) = (1, 1)
8985 16:47:41.233128 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8986 16:47:41.236826 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8987 16:47:41.239321 best DQS0 dly(2T, 0.5T) = (1, 1)
8988 16:47:41.242692 best DQS1 dly(2T, 0.5T) = (1, 1)
8989 16:47:41.245942 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8990 16:47:41.249360 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8991 16:47:41.252665 Pre-setting of DQS Precalculation
8992 16:47:41.258987 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8993 16:47:41.265481 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8994 16:47:41.272603 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8995 16:47:41.272717
8996 16:47:41.272818
8997 16:47:41.275929 [Calibration Summary] 3200 Mbps
8998 16:47:41.276062 CH 0, Rank 0
8999 16:47:41.279068 SW Impedance : PASS
9000 16:47:41.282662 DUTY Scan : NO K
9001 16:47:41.282743 ZQ Calibration : PASS
9002 16:47:41.285818 Jitter Meter : NO K
9003 16:47:41.288738 CBT Training : PASS
9004 16:47:41.288821 Write leveling : PASS
9005 16:47:41.292225 RX DQS gating : PASS
9006 16:47:41.295929 RX DQ/DQS(RDDQC) : PASS
9007 16:47:41.296014 TX DQ/DQS : PASS
9008 16:47:41.299114 RX DATLAT : PASS
9009 16:47:41.299248 RX DQ/DQS(Engine): PASS
9010 16:47:41.302758 TX OE : PASS
9011 16:47:41.302863 All Pass.
9012 16:47:41.302957
9013 16:47:41.305358 CH 0, Rank 1
9014 16:47:41.305475 SW Impedance : PASS
9015 16:47:41.308816 DUTY Scan : NO K
9016 16:47:41.311933 ZQ Calibration : PASS
9017 16:47:41.312042 Jitter Meter : NO K
9018 16:47:41.315818 CBT Training : PASS
9019 16:47:41.318455 Write leveling : PASS
9020 16:47:41.318536 RX DQS gating : PASS
9021 16:47:41.322284 RX DQ/DQS(RDDQC) : PASS
9022 16:47:41.325164 TX DQ/DQS : PASS
9023 16:47:41.325246 RX DATLAT : PASS
9024 16:47:41.328534 RX DQ/DQS(Engine): PASS
9025 16:47:41.331976 TX OE : PASS
9026 16:47:41.332058 All Pass.
9027 16:47:41.332123
9028 16:47:41.332182 CH 1, Rank 0
9029 16:47:41.335506 SW Impedance : PASS
9030 16:47:41.338538 DUTY Scan : NO K
9031 16:47:41.338636 ZQ Calibration : PASS
9032 16:47:41.341604 Jitter Meter : NO K
9033 16:47:41.345165 CBT Training : PASS
9034 16:47:41.345246 Write leveling : PASS
9035 16:47:41.348468 RX DQS gating : PASS
9036 16:47:41.351339 RX DQ/DQS(RDDQC) : PASS
9037 16:47:41.351454 TX DQ/DQS : PASS
9038 16:47:41.354691 RX DATLAT : PASS
9039 16:47:41.358279 RX DQ/DQS(Engine): PASS
9040 16:47:41.358361 TX OE : PASS
9041 16:47:41.361616 All Pass.
9042 16:47:41.361697
9043 16:47:41.361772 CH 1, Rank 1
9044 16:47:41.365167 SW Impedance : PASS
9045 16:47:41.365265 DUTY Scan : NO K
9046 16:47:41.367999 ZQ Calibration : PASS
9047 16:47:41.371278 Jitter Meter : NO K
9048 16:47:41.371359 CBT Training : PASS
9049 16:47:41.374359 Write leveling : PASS
9050 16:47:41.377792 RX DQS gating : PASS
9051 16:47:41.377874 RX DQ/DQS(RDDQC) : PASS
9052 16:47:41.381398 TX DQ/DQS : PASS
9053 16:47:41.381494 RX DATLAT : PASS
9054 16:47:41.384316 RX DQ/DQS(Engine): PASS
9055 16:47:41.388063 TX OE : PASS
9056 16:47:41.388181 All Pass.
9057 16:47:41.388248
9058 16:47:41.391007 DramC Write-DBI on
9059 16:47:41.394428 PER_BANK_REFRESH: Hybrid Mode
9060 16:47:41.394550 TX_TRACKING: ON
9061 16:47:41.404195 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9062 16:47:41.410656 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9063 16:47:41.417160 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 16:47:41.420671 [FAST_K] Save calibration result to emmc
9065 16:47:41.424371 sync common calibartion params.
9066 16:47:41.427355 sync cbt_mode0:1, 1:1
9067 16:47:41.430371 dram_init: ddr_geometry: 2
9068 16:47:41.430445 dram_init: ddr_geometry: 2
9069 16:47:41.433959 dram_init: ddr_geometry: 2
9070 16:47:41.437142 0:dram_rank_size:100000000
9071 16:47:41.440396 1:dram_rank_size:100000000
9072 16:47:41.443716 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9073 16:47:41.447003 DFS_SHUFFLE_HW_MODE: ON
9074 16:47:41.450312 dramc_set_vcore_voltage set vcore to 725000
9075 16:47:41.453858 Read voltage for 1600, 0
9076 16:47:41.453967 Vio18 = 0
9077 16:47:41.454063 Vcore = 725000
9078 16:47:41.457026 Vdram = 0
9079 16:47:41.457126 Vddq = 0
9080 16:47:41.457215 Vmddr = 0
9081 16:47:41.460002 switch to 3200 Mbps bootup
9082 16:47:41.463465 [DramcRunTimeConfig]
9083 16:47:41.463543 PHYPLL
9084 16:47:41.463605 DPM_CONTROL_AFTERK: ON
9085 16:47:41.466986 PER_BANK_REFRESH: ON
9086 16:47:41.469899 REFRESH_OVERHEAD_REDUCTION: ON
9087 16:47:41.473232 CMD_PICG_NEW_MODE: OFF
9088 16:47:41.473337 XRTWTW_NEW_MODE: ON
9089 16:47:41.476448 XRTRTR_NEW_MODE: ON
9090 16:47:41.476548 TX_TRACKING: ON
9091 16:47:41.479951 RDSEL_TRACKING: OFF
9092 16:47:41.480051 DQS Precalculation for DVFS: ON
9093 16:47:41.483001 RX_TRACKING: OFF
9094 16:47:41.483105 HW_GATING DBG: ON
9095 16:47:41.486883 ZQCS_ENABLE_LP4: ON
9096 16:47:41.489476 RX_PICG_NEW_MODE: ON
9097 16:47:41.489580 TX_PICG_NEW_MODE: ON
9098 16:47:41.494230 ENABLE_RX_DCM_DPHY: ON
9099 16:47:41.496347 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9100 16:47:41.499335 DUMMY_READ_FOR_TRACKING: OFF
9101 16:47:41.499444 !!! SPM_CONTROL_AFTERK: OFF
9102 16:47:41.502324 !!! SPM could not control APHY
9103 16:47:41.505828 IMPEDANCE_TRACKING: ON
9104 16:47:41.505933 TEMP_SENSOR: ON
9105 16:47:41.509599 HW_SAVE_FOR_SR: OFF
9106 16:47:41.512572 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9107 16:47:41.515761 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9108 16:47:41.515863 Read ODT Tracking: ON
9109 16:47:41.518913 Refresh Rate DeBounce: ON
9110 16:47:41.522710 DFS_NO_QUEUE_FLUSH: ON
9111 16:47:41.525421 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9112 16:47:41.525538 ENABLE_DFS_RUNTIME_MRW: OFF
9113 16:47:41.528977 DDR_RESERVE_NEW_MODE: ON
9114 16:47:41.531985 MR_CBT_SWITCH_FREQ: ON
9115 16:47:41.532087 =========================
9116 16:47:41.552557 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9117 16:47:41.555739 dram_init: ddr_geometry: 2
9118 16:47:41.573907 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9119 16:47:41.577320 dram_init: dram init end (result: 0)
9120 16:47:41.583870 DRAM-K: Full calibration passed in 24428 msecs
9121 16:47:41.587048 MRC: failed to locate region type 0.
9122 16:47:41.587158 DRAM rank0 size:0x100000000,
9123 16:47:41.590624 DRAM rank1 size=0x100000000
9124 16:47:41.600287 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9125 16:47:41.607101 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9126 16:47:41.616543 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9127 16:47:41.623163 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9128 16:47:41.623265 DRAM rank0 size:0x100000000,
9129 16:47:41.626763 DRAM rank1 size=0x100000000
9130 16:47:41.626863 CBMEM:
9131 16:47:41.630109 IMD: root @ 0xfffff000 254 entries.
9132 16:47:41.633124 IMD: root @ 0xffffec00 62 entries.
9133 16:47:41.639565 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9134 16:47:41.642983 WARNING: RO_VPD is uninitialized or empty.
9135 16:47:41.646260 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9136 16:47:41.654167 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9137 16:47:41.666981 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9138 16:47:41.678670 BS: romstage times (exec / console): total (unknown) / 23956 ms
9139 16:47:41.678778
9140 16:47:41.678872
9141 16:47:41.688158 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9142 16:47:41.691635 ARM64: Exception handlers installed.
9143 16:47:41.694904 ARM64: Testing exception
9144 16:47:41.698395 ARM64: Done test exception
9145 16:47:41.698496 Enumerating buses...
9146 16:47:41.701824 Show all devs... Before device enumeration.
9147 16:47:41.704755 Root Device: enabled 1
9148 16:47:41.708043 CPU_CLUSTER: 0: enabled 1
9149 16:47:41.708145 CPU: 00: enabled 1
9150 16:47:41.711072 Compare with tree...
9151 16:47:41.711180 Root Device: enabled 1
9152 16:47:41.714385 CPU_CLUSTER: 0: enabled 1
9153 16:47:41.718015 CPU: 00: enabled 1
9154 16:47:41.718112 Root Device scanning...
9155 16:47:41.721207 scan_static_bus for Root Device
9156 16:47:41.724406 CPU_CLUSTER: 0 enabled
9157 16:47:41.727959 scan_static_bus for Root Device done
9158 16:47:41.731190 scan_bus: bus Root Device finished in 8 msecs
9159 16:47:41.731282 done
9160 16:47:41.737259 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9161 16:47:41.741150 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9162 16:47:41.747778 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9163 16:47:41.754063 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9164 16:47:41.754168 Allocating resources...
9165 16:47:41.757335 Reading resources...
9166 16:47:41.760641 Root Device read_resources bus 0 link: 0
9167 16:47:41.764144 DRAM rank0 size:0x100000000,
9168 16:47:41.764256 DRAM rank1 size=0x100000000
9169 16:47:41.770676 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9170 16:47:41.770777 CPU: 00 missing read_resources
9171 16:47:41.777597 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9172 16:47:41.780621 Root Device read_resources bus 0 link: 0 done
9173 16:47:41.783731 Done reading resources.
9174 16:47:41.787051 Show resources in subtree (Root Device)...After reading.
9175 16:47:41.790524 Root Device child on link 0 CPU_CLUSTER: 0
9176 16:47:41.793901 CPU_CLUSTER: 0 child on link 0 CPU: 00
9177 16:47:41.804798 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9178 16:47:41.804905 CPU: 00
9179 16:47:41.810454 Root Device assign_resources, bus 0 link: 0
9180 16:47:41.813721 CPU_CLUSTER: 0 missing set_resources
9181 16:47:41.817012 Root Device assign_resources, bus 0 link: 0 done
9182 16:47:41.817111 Done setting resources.
9183 16:47:41.823123 Show resources in subtree (Root Device)...After assigning values.
9184 16:47:41.826583 Root Device child on link 0 CPU_CLUSTER: 0
9185 16:47:41.833099 CPU_CLUSTER: 0 child on link 0 CPU: 00
9186 16:47:41.839909 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9187 16:47:41.842962 CPU: 00
9188 16:47:41.843060 Done allocating resources.
9189 16:47:41.849752 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9190 16:47:41.849851 Enabling resources...
9191 16:47:41.852954 done.
9192 16:47:41.856515 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9193 16:47:41.859725 Initializing devices...
9194 16:47:41.859825 Root Device init
9195 16:47:41.862742 init hardware done!
9196 16:47:41.862838 0x00000018: ctrlr->caps
9197 16:47:41.866681 52.000 MHz: ctrlr->f_max
9198 16:47:41.869539 0.400 MHz: ctrlr->f_min
9199 16:47:41.872818 0x40ff8080: ctrlr->voltages
9200 16:47:41.872921 sclk: 390625
9201 16:47:41.873010 Bus Width = 1
9202 16:47:41.876196 sclk: 390625
9203 16:47:41.876292 Bus Width = 1
9204 16:47:41.879072 Early init status = 3
9205 16:47:41.882471 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9206 16:47:41.886658 in-header: 03 fc 00 00 01 00 00 00
9207 16:47:41.890061 in-data: 00
9208 16:47:41.893289 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9209 16:47:41.899511 in-header: 03 fd 00 00 00 00 00 00
9210 16:47:41.902288 in-data:
9211 16:47:41.905556 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9212 16:47:41.910580 in-header: 03 fc 00 00 01 00 00 00
9213 16:47:41.913122 in-data: 00
9214 16:47:41.916622 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9215 16:47:41.922313 in-header: 03 fd 00 00 00 00 00 00
9216 16:47:41.925897 in-data:
9217 16:47:41.929362 [SSUSB] Setting up USB HOST controller...
9218 16:47:41.932254 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9219 16:47:41.935440 [SSUSB] phy power-on done.
9220 16:47:41.938565 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9221 16:47:41.945323 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9222 16:47:41.948437 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9223 16:47:41.955614 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9224 16:47:41.961605 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9225 16:47:41.968463 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9226 16:47:41.974840 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9227 16:47:41.981456 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9228 16:47:41.985147 SPM: binary array size = 0x9dc
9229 16:47:41.988078 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9230 16:47:41.994875 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9231 16:47:42.001934 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9232 16:47:42.008578 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9233 16:47:42.011118 configure_display: Starting display init
9234 16:47:42.045468 anx7625_power_on_init: Init interface.
9235 16:47:42.048579 anx7625_disable_pd_protocol: Disabled PD feature.
9236 16:47:42.052327 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9237 16:47:42.079856 anx7625_start_dp_work: Secure OCM version=00
9238 16:47:42.083285 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9239 16:47:42.097911 sp_tx_get_edid_block: EDID Block = 1
9240 16:47:42.200750 Extracted contents:
9241 16:47:42.204032 header: 00 ff ff ff ff ff ff 00
9242 16:47:42.206965 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9243 16:47:42.210690 version: 01 04
9244 16:47:42.214134 basic params: 95 1f 11 78 0a
9245 16:47:42.217309 chroma info: 76 90 94 55 54 90 27 21 50 54
9246 16:47:42.220674 established: 00 00 00
9247 16:47:42.226616 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9248 16:47:42.233484 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9249 16:47:42.236540 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9250 16:47:42.243197 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9251 16:47:42.249904 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9252 16:47:42.253190 extensions: 00
9253 16:47:42.253280 checksum: fb
9254 16:47:42.253344
9255 16:47:42.259505 Manufacturer: IVO Model 57d Serial Number 0
9256 16:47:42.259620 Made week 0 of 2020
9257 16:47:42.262728 EDID version: 1.4
9258 16:47:42.262811 Digital display
9259 16:47:42.266119 6 bits per primary color channel
9260 16:47:42.270339 DisplayPort interface
9261 16:47:42.270447 Maximum image size: 31 cm x 17 cm
9262 16:47:42.273100 Gamma: 220%
9263 16:47:42.273199 Check DPMS levels
9264 16:47:42.279354 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9265 16:47:42.282629 First detailed timing is preferred timing
9266 16:47:42.286258 Established timings supported:
9267 16:47:42.286339 Standard timings supported:
9268 16:47:42.289535 Detailed timings
9269 16:47:42.292646 Hex of detail: 383680a07038204018303c0035ae10000019
9270 16:47:42.298945 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9271 16:47:42.302284 0780 0798 07c8 0820 hborder 0
9272 16:47:42.305527 0438 043b 0447 0458 vborder 0
9273 16:47:42.308807 -hsync -vsync
9274 16:47:42.308937 Did detailed timing
9275 16:47:42.315462 Hex of detail: 000000000000000000000000000000000000
9276 16:47:42.318754 Manufacturer-specified data, tag 0
9277 16:47:42.322263 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9278 16:47:42.325282 ASCII string: InfoVision
9279 16:47:42.328443 Hex of detail: 000000fe00523134304e574635205248200a
9280 16:47:42.331934 ASCII string: R140NWF5 RH
9281 16:47:42.332014 Checksum
9282 16:47:42.335492 Checksum: 0xfb (valid)
9283 16:47:42.338461 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9284 16:47:42.341661 DSI data_rate: 832800000 bps
9285 16:47:42.348465 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9286 16:47:42.351806 anx7625_parse_edid: pixelclock(138800).
9287 16:47:42.354964 hactive(1920), hsync(48), hfp(24), hbp(88)
9288 16:47:42.358368 vactive(1080), vsync(12), vfp(3), vbp(17)
9289 16:47:42.362092 anx7625_dsi_config: config dsi.
9290 16:47:42.368441 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9291 16:47:42.382534 anx7625_dsi_config: success to config DSI
9292 16:47:42.386391 anx7625_dp_start: MIPI phy setup OK.
9293 16:47:42.389260 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9294 16:47:42.392368 mtk_ddp_mode_set invalid vrefresh 60
9295 16:47:42.395693 main_disp_path_setup
9296 16:47:42.395763 ovl_layer_smi_id_en
9297 16:47:42.399163 ovl_layer_smi_id_en
9298 16:47:42.399256 ccorr_config
9299 16:47:42.399318 aal_config
9300 16:47:42.402145 gamma_config
9301 16:47:42.402210 postmask_config
9302 16:47:42.405507 dither_config
9303 16:47:42.409045 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9304 16:47:42.415691 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9305 16:47:42.418447 Root Device init finished in 555 msecs
9306 16:47:42.421959 CPU_CLUSTER: 0 init
9307 16:47:42.428706 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9308 16:47:42.435332 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9309 16:47:42.435413 APU_MBOX 0x190000b0 = 0x10001
9310 16:47:42.438621 APU_MBOX 0x190001b0 = 0x10001
9311 16:47:42.441791 APU_MBOX 0x190005b0 = 0x10001
9312 16:47:42.445169 APU_MBOX 0x190006b0 = 0x10001
9313 16:47:42.451821 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9314 16:47:42.461379 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9315 16:47:42.474232 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9316 16:47:42.480269 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9317 16:47:42.492352 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9318 16:47:42.501312 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9319 16:47:42.504443 CPU_CLUSTER: 0 init finished in 81 msecs
9320 16:47:42.508162 Devices initialized
9321 16:47:42.511078 Show all devs... After init.
9322 16:47:42.511203 Root Device: enabled 1
9323 16:47:42.514400 CPU_CLUSTER: 0: enabled 1
9324 16:47:42.517539 CPU: 00: enabled 1
9325 16:47:42.521360 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9326 16:47:42.524083 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9327 16:47:42.527304 ELOG: NV offset 0x57f000 size 0x1000
9328 16:47:42.534727 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9329 16:47:42.541222 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9330 16:47:42.544233 ELOG: Event(17) added with size 13 at 2023-06-03 16:47:42 UTC
9331 16:47:42.550982 out: cmd=0x121: 03 db 21 01 00 00 00 00
9332 16:47:42.553964 in-header: 03 23 00 00 2c 00 00 00
9333 16:47:42.564171 in-data: 3c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9334 16:47:42.570849 ELOG: Event(A1) added with size 10 at 2023-06-03 16:47:42 UTC
9335 16:47:42.577271 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9336 16:47:42.583961 ELOG: Event(A0) added with size 9 at 2023-06-03 16:47:42 UTC
9337 16:47:42.587361 elog_add_boot_reason: Logged dev mode boot
9338 16:47:42.594468 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9339 16:47:42.594610 Finalize devices...
9340 16:47:42.597105 Devices finalized
9341 16:47:42.600337 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9342 16:47:42.604074 Writing coreboot table at 0xffe64000
9343 16:47:42.607059 0. 000000000010a000-0000000000113fff: RAMSTAGE
9344 16:47:42.613545 1. 0000000040000000-00000000400fffff: RAM
9345 16:47:42.616885 2. 0000000040100000-000000004032afff: RAMSTAGE
9346 16:47:42.620211 3. 000000004032b000-00000000545fffff: RAM
9347 16:47:42.623471 4. 0000000054600000-000000005465ffff: BL31
9348 16:47:42.626611 5. 0000000054660000-00000000ffe63fff: RAM
9349 16:47:42.633682 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9350 16:47:42.636504 7. 0000000100000000-000000023fffffff: RAM
9351 16:47:42.639795 Passing 5 GPIOs to payload:
9352 16:47:42.643053 NAME | PORT | POLARITY | VALUE
9353 16:47:42.649519 EC in RW | 0x000000aa | low | undefined
9354 16:47:42.653386 EC interrupt | 0x00000005 | low | undefined
9355 16:47:42.659710 TPM interrupt | 0x000000ab | high | undefined
9356 16:47:42.662589 SD card detect | 0x00000011 | high | undefined
9357 16:47:42.666073 speaker enable | 0x00000093 | high | undefined
9358 16:47:42.670319 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9359 16:47:42.673981 in-header: 03 f9 00 00 02 00 00 00
9360 16:47:42.676883 in-data: 02 00
9361 16:47:42.680292 ADC[4]: Raw value=902216 ID=7
9362 16:47:42.683580 ADC[3]: Raw value=213916 ID=1
9363 16:47:42.683658 RAM Code: 0x71
9364 16:47:42.687110 ADC[6]: Raw value=75000 ID=0
9365 16:47:42.689968 ADC[5]: Raw value=213916 ID=1
9366 16:47:42.690041 SKU Code: 0x1
9367 16:47:42.696935 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9368 16:47:42.697019 coreboot table: 964 bytes.
9369 16:47:42.699919 IMD ROOT 0. 0xfffff000 0x00001000
9370 16:47:42.703075 IMD SMALL 1. 0xffffe000 0x00001000
9371 16:47:42.706418 RO MCACHE 2. 0xffffc000 0x00001104
9372 16:47:42.709910 CONSOLE 3. 0xfff7c000 0x00080000
9373 16:47:42.713411 FMAP 4. 0xfff7b000 0x00000452
9374 16:47:42.717100 TIME STAMP 5. 0xfff7a000 0x00000910
9375 16:47:42.719629 VBOOT WORK 6. 0xfff66000 0x00014000
9376 16:47:42.722850 RAMOOPS 7. 0xffe66000 0x00100000
9377 16:47:42.726400 COREBOOT 8. 0xffe64000 0x00002000
9378 16:47:42.729585 IMD small region:
9379 16:47:42.732926 IMD ROOT 0. 0xffffec00 0x00000400
9380 16:47:42.736283 VPD 1. 0xffffeba0 0x0000004c
9381 16:47:42.739791 MMC STATUS 2. 0xffffeb80 0x00000004
9382 16:47:42.746030 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9383 16:47:42.746129 Probing TPM: done!
9384 16:47:42.753200 Connected to device vid:did:rid of 1ae0:0028:00
9385 16:47:42.759689 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9386 16:47:42.763144 Initialized TPM device CR50 revision 0
9387 16:47:42.766524 Checking cr50 for pending updates
9388 16:47:42.771899 Reading cr50 TPM mode
9389 16:47:42.781218 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9390 16:47:42.787565 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9391 16:47:42.827192 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9392 16:47:42.831044 Checking segment from ROM address 0x40100000
9393 16:47:42.833628 Checking segment from ROM address 0x4010001c
9394 16:47:42.840331 Loading segment from ROM address 0x40100000
9395 16:47:42.840412 code (compression=0)
9396 16:47:42.850382 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9397 16:47:42.856751 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9398 16:47:42.856833 it's not compressed!
9399 16:47:42.863625 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9400 16:47:42.870307 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9401 16:47:42.887910 Loading segment from ROM address 0x4010001c
9402 16:47:42.887991 Entry Point 0x80000000
9403 16:47:42.890757 Loaded segments
9404 16:47:42.894481 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9405 16:47:42.900823 Jumping to boot code at 0x80000000(0xffe64000)
9406 16:47:42.907413 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9407 16:47:42.913737 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9408 16:47:42.922305 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9409 16:47:42.925519 Checking segment from ROM address 0x40100000
9410 16:47:42.928640 Checking segment from ROM address 0x4010001c
9411 16:47:42.935345 Loading segment from ROM address 0x40100000
9412 16:47:42.935466 code (compression=1)
9413 16:47:42.941913 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9414 16:47:42.952110 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9415 16:47:42.952210 using LZMA
9416 16:47:42.960521 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9417 16:47:42.966752 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9418 16:47:42.970025 Loading segment from ROM address 0x4010001c
9419 16:47:42.970123 Entry Point 0x54601000
9420 16:47:42.973361 Loaded segments
9421 16:47:42.976866 NOTICE: MT8192 bl31_setup
9422 16:47:42.984168 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9423 16:47:42.987148 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9424 16:47:42.990695 WARNING: region 0:
9425 16:47:42.993926 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9426 16:47:42.994035 WARNING: region 1:
9427 16:47:43.000570 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9428 16:47:43.004531 WARNING: region 2:
9429 16:47:43.008564 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9430 16:47:43.010455 WARNING: region 3:
9431 16:47:43.013979 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9432 16:47:43.017279 WARNING: region 4:
9433 16:47:43.023520 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9434 16:47:43.023605 WARNING: region 5:
9435 16:47:43.026786 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9436 16:47:43.030216 WARNING: region 6:
9437 16:47:43.033391 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9438 16:47:43.037167 WARNING: region 7:
9439 16:47:43.040093 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 16:47:43.046602 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9441 16:47:43.050352 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9442 16:47:43.053590 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9443 16:47:43.059909 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9444 16:47:43.063742 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9445 16:47:43.070662 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9446 16:47:43.073569 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9447 16:47:43.076594 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9448 16:47:43.083633 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9449 16:47:43.087143 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9450 16:47:43.090043 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9451 16:47:43.096881 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9452 16:47:43.100119 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9453 16:47:43.106563 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9454 16:47:43.109845 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9455 16:47:43.113813 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9456 16:47:43.119835 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9457 16:47:43.123261 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9458 16:47:43.129524 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9459 16:47:43.132900 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9460 16:47:43.137717 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9461 16:47:43.142831 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9462 16:47:43.146236 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9463 16:47:43.150248 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9464 16:47:43.156070 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9465 16:47:43.159443 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9466 16:47:43.166803 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9467 16:47:43.170197 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9468 16:47:43.172977 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9469 16:47:43.179326 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9470 16:47:43.182822 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9471 16:47:43.189475 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9472 16:47:43.192966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9473 16:47:43.196465 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9474 16:47:43.200298 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9475 16:47:43.205941 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9476 16:47:43.209568 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9477 16:47:43.212628 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9478 16:47:43.215814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9479 16:47:43.222639 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9480 16:47:43.225960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9481 16:47:43.229246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9482 16:47:43.232945 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9483 16:47:43.239378 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9484 16:47:43.242787 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9485 16:47:43.246225 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9486 16:47:43.249344 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9487 16:47:43.256023 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9488 16:47:43.258844 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9489 16:47:43.265529 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9490 16:47:43.269534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9491 16:47:43.275360 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9492 16:47:43.278894 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9493 16:47:43.282721 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9494 16:47:43.288962 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9495 16:47:43.292226 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9496 16:47:43.298882 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9497 16:47:43.301940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9498 16:47:43.308583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9499 16:47:43.311701 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9500 16:47:43.315330 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9501 16:47:43.322170 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9502 16:47:43.325056 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9503 16:47:43.332492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9504 16:47:43.335174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9505 16:47:43.341997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9506 16:47:43.344935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9507 16:47:43.351899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9508 16:47:43.355263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9509 16:47:43.358422 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9510 16:47:43.364843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9511 16:47:43.368598 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9512 16:47:43.375499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9513 16:47:43.378055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9514 16:47:43.385215 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9515 16:47:43.388389 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9516 16:47:43.395294 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9517 16:47:43.398206 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9518 16:47:43.401673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9519 16:47:43.408266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9520 16:47:43.411370 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9521 16:47:43.418672 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9522 16:47:43.421234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9523 16:47:43.428056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9524 16:47:43.431399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9525 16:47:43.435059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9526 16:47:43.441185 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9527 16:47:43.444548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9528 16:47:43.451107 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9529 16:47:43.454415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9530 16:47:43.461506 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9531 16:47:43.464201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9532 16:47:43.470872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9533 16:47:43.474308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9534 16:47:43.477609 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9535 16:47:43.484181 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9536 16:47:43.487322 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9537 16:47:43.494194 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9538 16:47:43.497166 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9539 16:47:43.500476 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9540 16:47:43.503695 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9541 16:47:43.511071 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9542 16:47:43.514501 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9543 16:47:43.520551 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9544 16:47:43.523554 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9545 16:47:43.527153 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9546 16:47:43.533544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9547 16:47:43.536934 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9548 16:47:43.543613 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9549 16:47:43.546811 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9550 16:47:43.550380 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9551 16:47:43.557195 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9552 16:47:43.560223 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9553 16:47:43.566868 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9554 16:47:43.570215 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9555 16:47:43.573854 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9556 16:47:43.576877 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9557 16:47:43.583640 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9558 16:47:43.587085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9559 16:47:43.589965 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9560 16:47:43.596435 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9561 16:47:43.599929 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9562 16:47:43.603363 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9563 16:47:43.606813 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9564 16:47:43.613327 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9565 16:47:43.616679 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9566 16:47:43.623340 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9567 16:47:43.626247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9568 16:47:43.630019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9569 16:47:43.636544 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9570 16:47:43.639753 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9571 16:47:43.646346 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9572 16:47:43.650148 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9573 16:47:43.653057 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9574 16:47:43.659569 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9575 16:47:43.663094 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9576 16:47:43.669740 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9577 16:47:43.673124 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9578 16:47:43.676889 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9579 16:47:43.683053 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9580 16:47:43.686691 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9581 16:47:43.692989 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9582 16:47:43.696262 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9583 16:47:43.699340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9584 16:47:43.706850 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9585 16:47:43.709575 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9586 16:47:43.712881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9587 16:47:43.719847 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9588 16:47:43.722514 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9589 16:47:43.729184 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9590 16:47:43.733054 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9591 16:47:43.736384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9592 16:47:43.742774 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9593 16:47:43.745838 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9594 16:47:43.753385 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9595 16:47:43.756115 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9596 16:47:43.759356 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9597 16:47:43.766561 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9598 16:47:43.769071 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9599 16:47:43.775961 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9600 16:47:43.779091 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9601 16:47:43.782429 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9602 16:47:43.788961 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9603 16:47:43.792347 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9604 16:47:43.798885 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9605 16:47:43.802820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9606 16:47:43.805255 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9607 16:47:43.811825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9608 16:47:43.815132 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9609 16:47:43.822029 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9610 16:47:43.825090 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9611 16:47:43.828776 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9612 16:47:43.834911 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9613 16:47:43.838321 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9614 16:47:43.845010 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9615 16:47:43.848198 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9616 16:47:43.851478 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9617 16:47:43.857785 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9618 16:47:43.861154 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9619 16:47:43.867912 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9620 16:47:43.870972 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9621 16:47:43.874668 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9622 16:47:43.880973 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9623 16:47:43.884469 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9624 16:47:43.891431 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9625 16:47:43.894275 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9626 16:47:43.897755 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9627 16:47:43.903960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9628 16:47:43.907747 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9629 16:47:43.913784 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9630 16:47:43.917012 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9631 16:47:43.923392 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9632 16:47:43.927335 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9633 16:47:43.933620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9634 16:47:43.936756 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9635 16:47:43.939941 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9636 16:47:43.947295 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9637 16:47:43.950149 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9638 16:47:43.956551 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9639 16:47:43.959711 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9640 16:47:43.966478 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9641 16:47:43.969696 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9642 16:47:43.972865 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9643 16:47:43.980780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9644 16:47:43.983157 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9645 16:47:43.989598 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9646 16:47:43.992480 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9647 16:47:43.999366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9648 16:47:44.003051 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9649 16:47:44.005636 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9650 16:47:44.012830 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9651 16:47:44.015547 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9652 16:47:44.022282 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9653 16:47:44.025377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9654 16:47:44.032190 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9655 16:47:44.035513 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9656 16:47:44.038679 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9657 16:47:44.045118 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9658 16:47:44.048779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9659 16:47:44.055273 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9660 16:47:44.058440 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9661 16:47:44.066209 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9662 16:47:44.068260 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9663 16:47:44.071703 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9664 16:47:44.078344 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9665 16:47:44.081293 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9666 16:47:44.088017 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9667 16:47:44.091444 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9668 16:47:44.098609 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9669 16:47:44.101422 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9670 16:47:44.104534 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9671 16:47:44.107829 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9672 16:47:44.111039 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9673 16:47:44.117873 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9674 16:47:44.121140 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9675 16:47:44.124728 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9676 16:47:44.130814 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9677 16:47:44.134444 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9678 16:47:44.141022 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9679 16:47:44.144450 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9680 16:47:44.147202 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9681 16:47:44.153832 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9682 16:47:44.157241 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9683 16:47:44.160948 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9684 16:47:44.167270 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9685 16:47:44.170473 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9686 16:47:44.176955 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9687 16:47:44.180057 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9688 16:47:44.183645 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9689 16:47:44.189906 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9690 16:47:44.193106 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9691 16:47:44.199775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9692 16:47:44.203391 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9693 16:47:44.206184 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9694 16:47:44.212938 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9695 16:47:44.216269 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9696 16:47:44.222889 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9697 16:47:44.226162 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9698 16:47:44.229259 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9699 16:47:44.236159 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9700 16:47:44.239487 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9701 16:47:44.242963 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9702 16:47:44.249245 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9703 16:47:44.252371 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9704 16:47:44.255745 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9705 16:47:44.262180 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9706 16:47:44.266130 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9707 16:47:44.272160 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9708 16:47:44.275647 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9709 16:47:44.278801 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9710 16:47:44.282234 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9711 16:47:44.288662 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9712 16:47:44.292164 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9713 16:47:44.295355 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9714 16:47:44.298760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9715 16:47:44.305675 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9716 16:47:44.309312 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9717 16:47:44.311768 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9718 16:47:44.315848 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9719 16:47:44.321645 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9720 16:47:44.325828 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9721 16:47:44.328071 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9722 16:47:44.335032 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9723 16:47:44.337859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9724 16:47:44.344545 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9725 16:47:44.348169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9726 16:47:44.354483 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9727 16:47:44.357903 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9728 16:47:44.361225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9729 16:47:44.367631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9730 16:47:44.370657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9731 16:47:44.377770 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9732 16:47:44.381184 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9733 16:47:44.384152 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9734 16:47:44.390621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9735 16:47:44.393923 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9736 16:47:44.400511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9737 16:47:44.403853 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9738 16:47:44.407165 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9739 16:47:44.413649 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9740 16:47:44.417098 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9741 16:47:44.423530 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9742 16:47:44.426971 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9743 16:47:44.433366 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9744 16:47:44.436890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9745 16:47:44.440008 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9746 16:47:44.446540 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9747 16:47:44.449779 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9748 16:47:44.456902 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9749 16:47:44.459909 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9750 16:47:44.466491 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9751 16:47:44.470117 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9752 16:47:44.473377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9753 16:47:44.480492 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9754 16:47:44.483030 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9755 16:47:44.489695 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9756 16:47:44.492920 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9757 16:47:44.496434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9758 16:47:44.502812 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9759 16:47:44.505807 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9760 16:47:44.512455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9761 16:47:44.515746 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9762 16:47:44.522445 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9763 16:47:44.525897 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9764 16:47:44.528967 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9765 16:47:44.535462 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9766 16:47:44.538720 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9767 16:47:44.545326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9768 16:47:44.548674 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9769 16:47:44.552133 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9770 16:47:44.558602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9771 16:47:44.561596 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9772 16:47:44.568396 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9773 16:47:44.571581 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9774 16:47:44.578230 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9775 16:47:44.581365 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9776 16:47:44.588038 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9777 16:47:44.591543 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9778 16:47:44.595339 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9779 16:47:44.601629 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9780 16:47:44.604194 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9781 16:47:44.611007 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9782 16:47:44.614374 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9783 16:47:44.621044 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9784 16:47:44.624201 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9785 16:47:44.627891 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9786 16:47:44.633746 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9787 16:47:44.637409 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9788 16:47:44.643877 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9789 16:47:44.647286 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9790 16:47:44.650507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9791 16:47:44.656931 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9792 16:47:44.660341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9793 16:47:44.666773 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9794 16:47:44.670127 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9795 16:47:44.676901 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9796 16:47:44.680207 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9797 16:47:44.686463 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9798 16:47:44.689831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9799 16:47:44.693011 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9800 16:47:44.699747 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9801 16:47:44.703088 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9802 16:47:44.709640 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9803 16:47:44.712872 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9804 16:47:44.719671 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9805 16:47:44.722613 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9806 16:47:44.729529 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9807 16:47:44.732522 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9808 16:47:44.736431 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9809 16:47:44.743008 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9810 16:47:44.745917 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9811 16:47:44.752643 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9812 16:47:44.755609 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9813 16:47:44.762450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9814 16:47:44.765524 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9815 16:47:44.772484 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9816 16:47:44.775943 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9817 16:47:44.778942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9818 16:47:44.785336 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9819 16:47:44.788660 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9820 16:47:44.795105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9821 16:47:44.798259 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9822 16:47:44.805386 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9823 16:47:44.808335 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9824 16:47:44.815052 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9825 16:47:44.818358 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9826 16:47:44.821562 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9827 16:47:44.828385 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9828 16:47:44.831869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9829 16:47:44.838269 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9830 16:47:44.841242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9831 16:47:44.847682 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9832 16:47:44.851378 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9833 16:47:44.857676 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9834 16:47:44.861269 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9835 16:47:44.864126 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9836 16:47:44.870784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9837 16:47:44.873985 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9838 16:47:44.880665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9839 16:47:44.883987 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9840 16:47:44.890470 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9841 16:47:44.893568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9842 16:47:44.897040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9843 16:47:44.903678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9844 16:47:44.907061 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9845 16:47:44.913660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9846 16:47:44.916890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9847 16:47:44.923760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9848 16:47:44.926715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9849 16:47:44.933871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9850 16:47:44.936863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9851 16:47:44.943351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9852 16:47:44.946866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9853 16:47:44.953072 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9854 16:47:44.956370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9855 16:47:44.963370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9856 16:47:44.966568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9857 16:47:44.972696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9858 16:47:44.976059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9859 16:47:44.982627 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9860 16:47:44.985843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9861 16:47:44.992400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9862 16:47:44.996141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9863 16:47:45.002547 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9864 16:47:45.005649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9865 16:47:45.012154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9866 16:47:45.015418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9867 16:47:45.021857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9868 16:47:45.025605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9869 16:47:45.031752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9870 16:47:45.035363 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9871 16:47:45.041601 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9872 16:47:45.048911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9873 16:47:45.051795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9874 16:47:45.054993 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9875 16:47:45.058106 INFO: [APUAPC] vio 0
9876 16:47:45.061399 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9877 16:47:45.068162 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9878 16:47:45.071393 INFO: [APUAPC] D0_APC_0: 0x400510
9879 16:47:45.074828 INFO: [APUAPC] D0_APC_1: 0x0
9880 16:47:45.078288 INFO: [APUAPC] D0_APC_2: 0x1540
9881 16:47:45.081188 INFO: [APUAPC] D0_APC_3: 0x0
9882 16:47:45.084452 INFO: [APUAPC] D1_APC_0: 0xffffffff
9883 16:47:45.087956 INFO: [APUAPC] D1_APC_1: 0xffffffff
9884 16:47:45.091140 INFO: [APUAPC] D1_APC_2: 0x3fffff
9885 16:47:45.091248 INFO: [APUAPC] D1_APC_3: 0x0
9886 16:47:45.097847 INFO: [APUAPC] D2_APC_0: 0xffffffff
9887 16:47:45.101211 INFO: [APUAPC] D2_APC_1: 0xffffffff
9888 16:47:45.104585 INFO: [APUAPC] D2_APC_2: 0x3fffff
9889 16:47:45.104661 INFO: [APUAPC] D2_APC_3: 0x0
9890 16:47:45.108020 INFO: [APUAPC] D3_APC_0: 0xffffffff
9891 16:47:45.114714 INFO: [APUAPC] D3_APC_1: 0xffffffff
9892 16:47:45.117499 INFO: [APUAPC] D3_APC_2: 0x3fffff
9893 16:47:45.117582 INFO: [APUAPC] D3_APC_3: 0x0
9894 16:47:45.121142 INFO: [APUAPC] D4_APC_0: 0xffffffff
9895 16:47:45.127119 INFO: [APUAPC] D4_APC_1: 0xffffffff
9896 16:47:45.130618 INFO: [APUAPC] D4_APC_2: 0x3fffff
9897 16:47:45.130703 INFO: [APUAPC] D4_APC_3: 0x0
9898 16:47:45.133868 INFO: [APUAPC] D5_APC_0: 0xffffffff
9899 16:47:45.137517 INFO: [APUAPC] D5_APC_1: 0xffffffff
9900 16:47:45.140411 INFO: [APUAPC] D5_APC_2: 0x3fffff
9901 16:47:45.143717 INFO: [APUAPC] D5_APC_3: 0x0
9902 16:47:45.147087 INFO: [APUAPC] D6_APC_0: 0xffffffff
9903 16:47:45.150548 INFO: [APUAPC] D6_APC_1: 0xffffffff
9904 16:47:45.153608 INFO: [APUAPC] D6_APC_2: 0x3fffff
9905 16:47:45.156879 INFO: [APUAPC] D6_APC_3: 0x0
9906 16:47:45.160801 INFO: [APUAPC] D7_APC_0: 0xffffffff
9907 16:47:45.163610 INFO: [APUAPC] D7_APC_1: 0xffffffff
9908 16:47:45.166721 INFO: [APUAPC] D7_APC_2: 0x3fffff
9909 16:47:45.170174 INFO: [APUAPC] D7_APC_3: 0x0
9910 16:47:45.173312 INFO: [APUAPC] D8_APC_0: 0xffffffff
9911 16:47:45.176517 INFO: [APUAPC] D8_APC_1: 0xffffffff
9912 16:47:45.179963 INFO: [APUAPC] D8_APC_2: 0x3fffff
9913 16:47:45.183548 INFO: [APUAPC] D8_APC_3: 0x0
9914 16:47:45.186541 INFO: [APUAPC] D9_APC_0: 0xffffffff
9915 16:47:45.190054 INFO: [APUAPC] D9_APC_1: 0xffffffff
9916 16:47:45.193050 INFO: [APUAPC] D9_APC_2: 0x3fffff
9917 16:47:45.196346 INFO: [APUAPC] D9_APC_3: 0x0
9918 16:47:45.199641 INFO: [APUAPC] D10_APC_0: 0xffffffff
9919 16:47:45.203120 INFO: [APUAPC] D10_APC_1: 0xffffffff
9920 16:47:45.205936 INFO: [APUAPC] D10_APC_2: 0x3fffff
9921 16:47:45.209283 INFO: [APUAPC] D10_APC_3: 0x0
9922 16:47:45.213413 INFO: [APUAPC] D11_APC_0: 0xffffffff
9923 16:47:45.215941 INFO: [APUAPC] D11_APC_1: 0xffffffff
9924 16:47:45.219798 INFO: [APUAPC] D11_APC_2: 0x3fffff
9925 16:47:45.222563 INFO: [APUAPC] D11_APC_3: 0x0
9926 16:47:45.225755 INFO: [APUAPC] D12_APC_0: 0xffffffff
9927 16:47:45.229110 INFO: [APUAPC] D12_APC_1: 0xffffffff
9928 16:47:45.232718 INFO: [APUAPC] D12_APC_2: 0x3fffff
9929 16:47:45.235956 INFO: [APUAPC] D12_APC_3: 0x0
9930 16:47:45.239265 INFO: [APUAPC] D13_APC_0: 0xffffffff
9931 16:47:45.242482 INFO: [APUAPC] D13_APC_1: 0xffffffff
9932 16:47:45.248967 INFO: [APUAPC] D13_APC_2: 0x3fffff
9933 16:47:45.249046 INFO: [APUAPC] D13_APC_3: 0x0
9934 16:47:45.252178 INFO: [APUAPC] D14_APC_0: 0xffffffff
9935 16:47:45.258767 INFO: [APUAPC] D14_APC_1: 0xffffffff
9936 16:47:45.261928 INFO: [APUAPC] D14_APC_2: 0x3fffff
9937 16:47:45.262004 INFO: [APUAPC] D14_APC_3: 0x0
9938 16:47:45.268941 INFO: [APUAPC] D15_APC_0: 0xffffffff
9939 16:47:45.271940 INFO: [APUAPC] D15_APC_1: 0xffffffff
9940 16:47:45.275570 INFO: [APUAPC] D15_APC_2: 0x3fffff
9941 16:47:45.279053 INFO: [APUAPC] D15_APC_3: 0x0
9942 16:47:45.279133 INFO: [APUAPC] APC_CON: 0x4
9943 16:47:45.282344 INFO: [NOCDAPC] D0_APC_0: 0x0
9944 16:47:45.284883 INFO: [NOCDAPC] D0_APC_1: 0x0
9945 16:47:45.288236 INFO: [NOCDAPC] D1_APC_0: 0x0
9946 16:47:45.292087 INFO: [NOCDAPC] D1_APC_1: 0xfff
9947 16:47:45.295244 INFO: [NOCDAPC] D2_APC_0: 0x0
9948 16:47:45.299019 INFO: [NOCDAPC] D2_APC_1: 0xfff
9949 16:47:45.301288 INFO: [NOCDAPC] D3_APC_0: 0x0
9950 16:47:45.304751 INFO: [NOCDAPC] D3_APC_1: 0xfff
9951 16:47:45.308095 INFO: [NOCDAPC] D4_APC_0: 0x0
9952 16:47:45.311672 INFO: [NOCDAPC] D4_APC_1: 0xfff
9953 16:47:45.311753 INFO: [NOCDAPC] D5_APC_0: 0x0
9954 16:47:45.314481 INFO: [NOCDAPC] D5_APC_1: 0xfff
9955 16:47:45.318229 INFO: [NOCDAPC] D6_APC_0: 0x0
9956 16:47:45.321324 INFO: [NOCDAPC] D6_APC_1: 0xfff
9957 16:47:45.324290 INFO: [NOCDAPC] D7_APC_0: 0x0
9958 16:47:45.327663 INFO: [NOCDAPC] D7_APC_1: 0xfff
9959 16:47:45.331695 INFO: [NOCDAPC] D8_APC_0: 0x0
9960 16:47:45.334704 INFO: [NOCDAPC] D8_APC_1: 0xfff
9961 16:47:45.337603 INFO: [NOCDAPC] D9_APC_0: 0x0
9962 16:47:45.341087 INFO: [NOCDAPC] D9_APC_1: 0xfff
9963 16:47:45.344179 INFO: [NOCDAPC] D10_APC_0: 0x0
9964 16:47:45.347812 INFO: [NOCDAPC] D10_APC_1: 0xfff
9965 16:47:45.347884 INFO: [NOCDAPC] D11_APC_0: 0x0
9966 16:47:45.351217 INFO: [NOCDAPC] D11_APC_1: 0xfff
9967 16:47:45.354775 INFO: [NOCDAPC] D12_APC_0: 0x0
9968 16:47:45.357562 INFO: [NOCDAPC] D12_APC_1: 0xfff
9969 16:47:45.360606 INFO: [NOCDAPC] D13_APC_0: 0x0
9970 16:47:45.364070 INFO: [NOCDAPC] D13_APC_1: 0xfff
9971 16:47:45.367701 INFO: [NOCDAPC] D14_APC_0: 0x0
9972 16:47:45.370437 INFO: [NOCDAPC] D14_APC_1: 0xfff
9973 16:47:45.373614 INFO: [NOCDAPC] D15_APC_0: 0x0
9974 16:47:45.377170 INFO: [NOCDAPC] D15_APC_1: 0xfff
9975 16:47:45.380453 INFO: [NOCDAPC] APC_CON: 0x4
9976 16:47:45.383769 INFO: [APUAPC] set_apusys_apc done
9977 16:47:45.386903 INFO: [DEVAPC] devapc_init done
9978 16:47:45.390270 INFO: GICv3 without legacy support detected.
9979 16:47:45.393574 INFO: ARM GICv3 driver initialized in EL3
9980 16:47:45.396874 INFO: Maximum SPI INTID supported: 639
9981 16:47:45.403321 INFO: BL31: Initializing runtime services
9982 16:47:45.406480 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9983 16:47:45.410058 INFO: SPM: enable CPC mode
9984 16:47:45.416687 INFO: mcdi ready for mcusys-off-idle and system suspend
9985 16:47:45.419937 INFO: BL31: Preparing for EL3 exit to normal world
9986 16:47:45.422938 INFO: Entry point address = 0x80000000
9987 16:47:45.426338 INFO: SPSR = 0x8
9988 16:47:45.432118
9989 16:47:45.432283
9990 16:47:45.432382
9991 16:47:45.435041 Starting depthcharge on Spherion...
9992 16:47:45.435123
9993 16:47:45.435220 Wipe memory regions:
9994 16:47:45.435281
9995 16:47:45.435975 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9996 16:47:45.436080 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9997 16:47:45.436162 Setting prompt string to ['asurada:']
9998 16:47:45.436242 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
9999 16:47:45.438608 [0x00000040000000, 0x00000054600000)
10000 16:47:45.561292
10001 16:47:45.561413 [0x00000054660000, 0x00000080000000)
10002 16:47:45.821785
10003 16:47:45.821947 [0x000000821a7280, 0x000000ffe64000)
10004 16:47:46.566269
10005 16:47:46.566412 [0x00000100000000, 0x00000240000000)
10006 16:47:48.456908
10007 16:47:48.460964 Initializing XHCI USB controller at 0x11200000.
10008 16:47:49.498154
10009 16:47:49.501356 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10010 16:47:49.501472
10011 16:47:49.501557
10012 16:47:49.501617
10013 16:47:49.501895 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10015 16:47:49.602260 asurada: tftpboot 192.168.201.1 10576298/tftp-deploy-pqkgui2f/kernel/image.itb 10576298/tftp-deploy-pqkgui2f/kernel/cmdline
10016 16:47:49.602443 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10017 16:47:49.602565 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10018 16:47:49.606533 tftpboot 192.168.201.1 10576298/tftp-deploy-pqkgui2f/kernel/image.itbtp-deploy-pqkgui2f/kernel/cmdline
10019 16:47:49.606628
10020 16:47:49.606693 Waiting for link
10021 16:47:49.767445
10022 16:47:49.767582 R8152: Initializing
10023 16:47:49.767657
10024 16:47:49.770205 Version 6 (ocp_data = 5c30)
10025 16:47:49.770288
10026 16:47:49.773950 R8152: Done initializing
10027 16:47:49.774031
10028 16:47:49.774095 Adding net device
10029 16:47:51.802523
10030 16:47:51.802661 done.
10031 16:47:51.802729
10032 16:47:51.802788 MAC: 00:24:32:30:7c:7b
10033 16:47:51.802847
10034 16:47:51.805322 Sending DHCP discover... done.
10035 16:47:51.805414
10036 16:47:51.809142 Waiting for reply... done.
10037 16:47:51.809229
10038 16:47:51.812318 Sending DHCP request... done.
10039 16:47:51.812403
10040 16:47:51.812487 Waiting for reply... done.
10041 16:47:51.812566
10042 16:47:51.815466 My ip is 192.168.201.14
10043 16:47:51.815549
10044 16:47:51.818992 The DHCP server ip is 192.168.201.1
10045 16:47:51.819077
10046 16:47:51.822271 TFTP server IP predefined by user: 192.168.201.1
10047 16:47:51.822355
10048 16:47:51.828481 Bootfile predefined by user: 10576298/tftp-deploy-pqkgui2f/kernel/image.itb
10049 16:47:51.828572
10050 16:47:51.831948 Sending tftp read request... done.
10051 16:47:51.832037
10052 16:47:51.835083 Waiting for the transfer...
10053 16:47:51.835190
10054 16:47:52.506955 00000000 ################################################################
10055 16:47:52.507131
10056 16:47:53.068703 00080000 ################################################################
10057 16:47:53.069130
10058 16:47:53.599991 00100000 ################################################################
10059 16:47:53.600177
10060 16:47:54.159237 00180000 ################################################################
10061 16:47:54.159749
10062 16:47:54.749493 00200000 ################################################################
10063 16:47:54.750132
10064 16:47:55.394275 00280000 ################################################################
10065 16:47:55.394995
10066 16:47:55.972972 00300000 ################################################################
10067 16:47:55.973106
10068 16:47:56.575884 00380000 ################################################################
10069 16:47:56.576457
10070 16:47:57.244818 00400000 ################################################################
10071 16:47:57.245326
10072 16:47:57.869641 00480000 ################################################################
10073 16:47:57.870163
10074 16:47:58.526827 00500000 ################################################################
10075 16:47:58.527584
10076 16:47:59.178211 00580000 ################################################################
10077 16:47:59.178705
10078 16:47:59.839051 00600000 ################################################################
10079 16:47:59.839236
10080 16:48:00.469898 00680000 ################################################################
10081 16:48:00.470040
10082 16:48:01.044157 00700000 ################################################################
10083 16:48:01.044687
10084 16:48:01.690320 00780000 ################################################################
10085 16:48:01.690893
10086 16:48:02.344269 00800000 ################################################################
10087 16:48:02.344796
10088 16:48:03.013231 00880000 ################################################################
10089 16:48:03.013719
10090 16:48:03.704028 00900000 ################################################################
10091 16:48:03.704546
10092 16:48:04.359632 00980000 ################################################################
10093 16:48:04.359801
10094 16:48:04.952238 00a00000 ################################################################
10095 16:48:04.952426
10096 16:48:05.598644 00a80000 ################################################################
10097 16:48:05.599203
10098 16:48:06.248985 00b00000 ################################################################
10099 16:48:06.249137
10100 16:48:06.854839 00b80000 ################################################################
10101 16:48:06.854973
10102 16:48:07.456739 00c00000 ################################################################
10103 16:48:07.456922
10104 16:48:08.036251 00c80000 ################################################################
10105 16:48:08.036886
10106 16:48:08.674950 00d00000 ################################################################
10107 16:48:08.675580
10108 16:48:09.358185 00d80000 ################################################################
10109 16:48:09.358689
10110 16:48:10.023803 00e00000 ################################################################
10111 16:48:10.023949
10112 16:48:10.630748 00e80000 ################################################################
10113 16:48:10.631292
10114 16:48:11.315321 00f00000 ################################################################
10115 16:48:11.315816
10116 16:48:11.997106 00f80000 ################################################################
10117 16:48:11.997816
10118 16:48:12.621228 01000000 ################################################################
10119 16:48:12.621366
10120 16:48:13.206922 01080000 ################################################################
10121 16:48:13.207077
10122 16:48:13.854051 01100000 ################################################################
10123 16:48:13.854566
10124 16:48:14.545259 01180000 ################################################################
10125 16:48:14.545789
10126 16:48:15.224135 01200000 ################################################################
10127 16:48:15.224632
10128 16:48:15.869079 01280000 ################################################################
10129 16:48:15.869597
10130 16:48:16.501833 01300000 ################################################################
10131 16:48:16.501985
10132 16:48:17.056132 01380000 ################################################################
10133 16:48:17.056269
10134 16:48:17.689156 01400000 ################################################################
10135 16:48:17.689751
10136 16:48:18.303994 01480000 ################################################################
10137 16:48:18.304133
10138 16:48:18.872174 01500000 ################################################################
10139 16:48:18.872313
10140 16:48:19.489887 01580000 ################################################################
10141 16:48:19.490396
10142 16:48:20.160887 01600000 ################################################################
10143 16:48:20.161060
10144 16:48:20.840373 01680000 ################################################################
10145 16:48:20.840530
10146 16:48:21.530602 01700000 ################################################################
10147 16:48:21.531214
10148 16:48:22.226897 01780000 ################################################################
10149 16:48:22.227493
10150 16:48:22.900838 01800000 ################################################################
10151 16:48:22.901421
10152 16:48:23.550426 01880000 ################################################################
10153 16:48:23.550942
10154 16:48:24.248790 01900000 ################################################################
10155 16:48:24.249413
10156 16:48:24.927029 01980000 ################################################################
10157 16:48:24.927235
10158 16:48:25.527133 01a00000 ################################################################
10159 16:48:25.527678
10160 16:48:26.082385 01a80000 ################################################################
10161 16:48:26.082546
10162 16:48:26.622259 01b00000 ################################################################
10163 16:48:26.622422
10164 16:48:27.166907 01b80000 ################################################################
10165 16:48:27.167075
10166 16:48:27.719568 01c00000 ################################################################
10167 16:48:27.719768
10168 16:48:28.318028 01c80000 ################################################################
10169 16:48:28.318669
10170 16:48:28.923920 01d00000 ################################################################
10171 16:48:28.924438
10172 16:48:29.539458 01d80000 ################################################################
10173 16:48:29.539599
10174 16:48:30.129431 01e00000 ################################################################
10175 16:48:30.129606
10176 16:48:30.678836 01e80000 ################################################################
10177 16:48:30.679005
10178 16:48:31.215551 01f00000 ################################################################
10179 16:48:31.215687
10180 16:48:31.752844 01f80000 ################################################################
10181 16:48:31.752977
10182 16:48:32.292661 02000000 ################################################################
10183 16:48:32.292799
10184 16:48:32.905576 02080000 ################################################################
10185 16:48:32.905713
10186 16:48:33.525662 02100000 ################################################################
10187 16:48:33.525797
10188 16:48:34.075648 02180000 ################################################################
10189 16:48:34.075813
10190 16:48:34.619713 02200000 ################################################################
10191 16:48:34.619877
10192 16:48:35.156615 02280000 ################################################################
10193 16:48:35.156776
10194 16:48:35.729000 02300000 ################################################################
10195 16:48:35.729497
10196 16:48:36.390520 02380000 ################################################################
10197 16:48:36.391227
10198 16:48:37.051457 02400000 ################################################################
10199 16:48:37.051981
10200 16:48:37.728468 02480000 ################################################################
10201 16:48:37.728962
10202 16:48:38.401832 02500000 ################################################################
10203 16:48:38.402329
10204 16:48:39.064238 02580000 ################################################################
10205 16:48:39.064443
10206 16:48:39.729366 02600000 ################################################################
10207 16:48:39.729902
10208 16:48:40.420371 02680000 ################################################################
10209 16:48:40.420871
10210 16:48:41.115303 02700000 ################################################################
10211 16:48:41.116064
10212 16:48:41.750811 02780000 ################################################################
10213 16:48:41.751356
10214 16:48:42.437735 02800000 ################################################################
10215 16:48:42.438377
10216 16:48:43.121032 02880000 ################################################################
10217 16:48:43.121610
10218 16:48:43.806032 02900000 ################################################################
10219 16:48:43.806546
10220 16:48:44.431985 02980000 ################################################################
10221 16:48:44.432500
10222 16:48:45.093123 02a00000 ################################################################
10223 16:48:45.093289
10224 16:48:45.725875 02a80000 ################################################################
10225 16:48:45.726012
10226 16:48:46.278073 02b00000 ################################################################
10227 16:48:46.278212
10228 16:48:46.871961 02b80000 ################################################################
10229 16:48:46.872557
10230 16:48:47.438943 02c00000 ################################################################
10231 16:48:47.439094
10232 16:48:48.048614 02c80000 ################################################################
10233 16:48:48.048773
10234 16:48:48.581924 02d00000 ################################################################
10235 16:48:48.582083
10236 16:48:49.151517 02d80000 ################################################################
10237 16:48:49.151676
10238 16:48:49.713882 02e00000 ################################################################
10239 16:48:49.714030
10240 16:48:50.280230 02e80000 ################################################################
10241 16:48:50.280375
10242 16:48:50.875698 02f00000 ################################################################
10243 16:48:50.876243
10244 16:48:51.448434 02f80000 ################################################################
10245 16:48:51.448668
10246 16:48:52.002663 03000000 ################################################################
10247 16:48:52.002793
10248 16:48:52.534051 03080000 ################################################################
10249 16:48:52.534189
10250 16:48:53.065512 03100000 ################################################################
10251 16:48:53.065659
10252 16:48:53.599361 03180000 ################################################################
10253 16:48:53.599498
10254 16:48:54.222954 03200000 ################################################################
10255 16:48:54.223571
10256 16:48:54.781447 03280000 ################################################################
10257 16:48:54.781649
10258 16:48:55.326415 03300000 ################################################################
10259 16:48:55.326554
10260 16:48:55.893786 03380000 ################################################################
10261 16:48:55.893924
10262 16:48:56.501269 03400000 ################################################################
10263 16:48:56.501980
10264 16:48:57.142343 03480000 ################################################################
10265 16:48:57.143119
10266 16:48:57.831419 03500000 ################################################################
10267 16:48:57.831983
10268 16:48:58.438647 03580000 ################################################################
10269 16:48:58.438813
10270 16:48:59.018579 03600000 ################################################################
10271 16:48:59.019105
10272 16:48:59.639159 03680000 ################################################################
10273 16:48:59.639797
10274 16:49:00.290662 03700000 ################################################################
10275 16:49:00.291352
10276 16:49:00.921945 03780000 ################################################################
10277 16:49:00.922076
10278 16:49:01.563037 03800000 ################################################################
10279 16:49:01.563613
10280 16:49:02.189769 03880000 ################################################################
10281 16:49:02.190032
10282 16:49:02.846812 03900000 ################################################################
10283 16:49:02.847345
10284 16:49:03.531433 03980000 ################################################################
10285 16:49:03.531964
10286 16:49:04.202142 03a00000 ################################################################
10287 16:49:04.202284
10288 16:49:04.892959 03a80000 ################################################################
10289 16:49:04.893472
10290 16:49:05.594932 03b00000 ################################################################
10291 16:49:05.595472
10292 16:49:06.282353 03b80000 ################################################################
10293 16:49:06.282907
10294 16:49:06.895083 03c00000 ################################################################
10295 16:49:06.895724
10296 16:49:07.526863 03c80000 ################################################################
10297 16:49:07.527664
10298 16:49:08.211277 03d00000 ################################################################
10299 16:49:08.211818
10300 16:49:08.886535 03d80000 ################################################################
10301 16:49:08.886705
10302 16:49:09.464734 03e00000 ################################################################
10303 16:49:09.464897
10304 16:49:10.031428 03e80000 ################################################################
10305 16:49:10.031594
10306 16:49:10.526489 03f00000 ####################################################### done.
10307 16:49:10.526983
10308 16:49:10.529933 The bootfile was 66506270 bytes long.
10309 16:49:10.530393
10310 16:49:10.533524 Sending tftp read request... done.
10311 16:49:10.533972
10312 16:49:10.536709 Waiting for the transfer...
10313 16:49:10.537130
10314 16:49:10.537462 00000000 # done.
10315 16:49:10.537780
10316 16:49:10.543766 Command line loaded dynamically from TFTP file: 10576298/tftp-deploy-pqkgui2f/kernel/cmdline
10317 16:49:10.546689
10318 16:49:10.556486 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10319 16:49:10.556934
10320 16:49:10.557379 Loading FIT.
10321 16:49:10.557783
10322 16:49:10.559612 Image ramdisk-1 has 56373837 bytes.
10323 16:49:10.560039
10324 16:49:10.563449 Image fdt-1 has 46924 bytes.
10325 16:49:10.564018
10326 16:49:10.566456 Image kernel-1 has 10083474 bytes.
10327 16:49:10.566937
10328 16:49:10.576137 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10329 16:49:10.576698
10330 16:49:10.592790 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10331 16:49:10.593461
10332 16:49:10.599477 Choosing best match conf-1 for compat google,spherion-rev2.
10333 16:49:10.600106
10334 16:49:10.606736 Connected to device vid:did:rid of 1ae0:0028:00
10335 16:49:10.613816
10336 16:49:10.616783 tpm_get_response: command 0x17b, return code 0x0
10337 16:49:10.617208
10338 16:49:10.620848 ec_init: CrosEC protocol v3 supported (256, 248)
10339 16:49:10.624306
10340 16:49:10.627494 tpm_cleanup: add release locality here.
10341 16:49:10.627929
10342 16:49:10.628259 Shutting down all USB controllers.
10343 16:49:10.630801
10344 16:49:10.631242 Removing current net device
10345 16:49:10.631582
10346 16:49:10.637472 Exiting depthcharge with code 4 at timestamp: 114455806
10347 16:49:10.638010
10348 16:49:10.640591 LZMA decompressing kernel-1 to 0x821a6718
10349 16:49:10.641006
10350 16:49:10.644121 LZMA decompressing kernel-1 to 0x40000000
10351 16:49:11.910887
10352 16:49:11.911484 jumping to kernel
10353 16:49:11.912965 end: 2.2.4 bootloader-commands (duration 00:01:26) [common]
10354 16:49:11.913509 start: 2.2.5 auto-login-action (timeout 00:02:59) [common]
10355 16:49:11.914005 Setting prompt string to ['Linux version [0-9]']
10356 16:49:11.914368 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10357 16:49:11.914937 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10358 16:49:11.992550
10359 16:49:11.995909 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10360 16:49:12.000051 start: 2.2.5.1 login-action (timeout 00:02:59) [common]
10361 16:49:12.000677 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10362 16:49:12.001417 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10363 16:49:12.001903 Using line separator: #'\n'#
10364 16:49:12.002413 No login prompt set.
10365 16:49:12.002786 Parsing kernel messages
10366 16:49:12.003562 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10367 16:49:12.004429 [login-action] Waiting for messages, (timeout 00:02:59)
10368 16:49:12.019298 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10369 16:49:12.022184 [ 0.000000] random: crng init done
10370 16:49:12.028847 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10371 16:49:12.029424 [ 0.000000] efi: UEFI not found.
10372 16:49:12.038573 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10373 16:49:12.045502 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10374 16:49:12.055113 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10375 16:49:12.065302 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10376 16:49:12.071640 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10377 16:49:12.078365 [ 0.000000] printk: bootconsole [mtk8250] enabled
10378 16:49:12.084810 [ 0.000000] NUMA: No NUMA configuration found
10379 16:49:12.091453 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10380 16:49:12.094929 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10381 16:49:12.098202 [ 0.000000] Zone ranges:
10382 16:49:12.104438 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10383 16:49:12.107570 [ 0.000000] DMA32 empty
10384 16:49:12.114150 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10385 16:49:12.117294 [ 0.000000] Movable zone start for each node
10386 16:49:12.121317 [ 0.000000] Early memory node ranges
10387 16:49:12.127915 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10388 16:49:12.133855 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10389 16:49:12.140814 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10390 16:49:12.147327 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10391 16:49:12.153888 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10392 16:49:12.160763 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10393 16:49:12.216712 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10394 16:49:12.222959 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10395 16:49:12.229380 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10396 16:49:12.233000 [ 0.000000] psci: probing for conduit method from DT.
10397 16:49:12.239033 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10398 16:49:12.242453 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10399 16:49:12.248781 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10400 16:49:12.251726 [ 0.000000] psci: SMC Calling Convention v1.2
10401 16:49:12.258188 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10402 16:49:12.261946 [ 0.000000] Detected VIPT I-cache on CPU0
10403 16:49:12.268297 [ 0.000000] CPU features: detected: GIC system register CPU interface
10404 16:49:12.274877 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10405 16:49:12.281488 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10406 16:49:12.288311 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10407 16:49:12.298119 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10408 16:49:12.304265 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10409 16:49:12.307756 [ 0.000000] alternatives: applying boot alternatives
10410 16:49:12.314985 [ 0.000000] Fallback order for Node 0: 0
10411 16:49:12.321701 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10412 16:49:12.324772 [ 0.000000] Policy zone: Normal
10413 16:49:12.337600 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10414 16:49:12.347215 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10415 16:49:12.358155 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10416 16:49:12.367520 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10417 16:49:12.374748 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10418 16:49:12.377276 <6>[ 0.000000] software IO TLB: area num 8.
10419 16:49:12.435501 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10420 16:49:12.585010 <6>[ 0.000000] Memory: 7917884K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434884K reserved, 32768K cma-reserved)
10421 16:49:12.591544 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10422 16:49:12.597845 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10423 16:49:12.601122 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10424 16:49:12.608125 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10425 16:49:12.614047 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10426 16:49:12.621129 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10427 16:49:12.627270 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10428 16:49:12.633821 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10429 16:49:12.640176 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10430 16:49:12.646910 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10431 16:49:12.650599 <6>[ 0.000000] GICv3: 608 SPIs implemented
10432 16:49:12.653988 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10433 16:49:12.660485 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10434 16:49:12.664228 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10435 16:49:12.670265 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10436 16:49:12.683858 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10437 16:49:12.696422 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10438 16:49:12.703388 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10439 16:49:12.711950 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10440 16:49:12.724568 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10441 16:49:12.731277 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10442 16:49:12.737852 <6>[ 0.009180] Console: colour dummy device 80x25
10443 16:49:12.747943 <6>[ 0.013939] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10444 16:49:12.754622 <6>[ 0.024446] pid_max: default: 32768 minimum: 301
10445 16:49:12.758433 <6>[ 0.029320] LSM: Security Framework initializing
10446 16:49:12.764313 <6>[ 0.034257] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10447 16:49:12.774131 <6>[ 0.042119] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10448 16:49:12.784137 <6>[ 0.051534] cblist_init_generic: Setting adjustable number of callback queues.
10449 16:49:12.790765 <6>[ 0.058989] cblist_init_generic: Setting shift to 3 and lim to 1.
10450 16:49:12.794293 <6>[ 0.065327] cblist_init_generic: Setting shift to 3 and lim to 1.
10451 16:49:12.800580 <6>[ 0.071771] rcu: Hierarchical SRCU implementation.
10452 16:49:12.807025 <6>[ 0.076785] rcu: Max phase no-delay instances is 1000.
10453 16:49:12.813618 <6>[ 0.083839] EFI services will not be available.
10454 16:49:12.817129 <6>[ 0.088830] smp: Bringing up secondary CPUs ...
10455 16:49:12.825600 <6>[ 0.093881] Detected VIPT I-cache on CPU1
10456 16:49:12.831876 <6>[ 0.093951] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10457 16:49:12.838135 <6>[ 0.093983] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10458 16:49:12.841570 <6>[ 0.094316] Detected VIPT I-cache on CPU2
10459 16:49:12.851451 <6>[ 0.094367] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10460 16:49:12.858591 <6>[ 0.094383] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10461 16:49:12.861494 <6>[ 0.094646] Detected VIPT I-cache on CPU3
10462 16:49:12.867717 <6>[ 0.094693] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10463 16:49:12.874770 <6>[ 0.094707] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10464 16:49:12.881161 <6>[ 0.095012] CPU features: detected: Spectre-v4
10465 16:49:12.884025 <6>[ 0.095018] CPU features: detected: Spectre-BHB
10466 16:49:12.887460 <6>[ 0.095024] Detected PIPT I-cache on CPU4
10467 16:49:12.894745 <6>[ 0.095083] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10468 16:49:12.901321 <6>[ 0.095100] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10469 16:49:12.907481 <6>[ 0.095395] Detected PIPT I-cache on CPU5
10470 16:49:12.914168 <6>[ 0.095460] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10471 16:49:12.921406 <6>[ 0.095476] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10472 16:49:12.924080 <6>[ 0.095761] Detected PIPT I-cache on CPU6
10473 16:49:12.930642 <6>[ 0.095826] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10474 16:49:12.940170 <6>[ 0.095842] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10475 16:49:12.944126 <6>[ 0.096142] Detected PIPT I-cache on CPU7
10476 16:49:12.949957 <6>[ 0.096208] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10477 16:49:12.956479 <6>[ 0.096224] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10478 16:49:12.960450 <6>[ 0.096272] smp: Brought up 1 node, 8 CPUs
10479 16:49:12.966412 <6>[ 0.237551] SMP: Total of 8 processors activated.
10480 16:49:12.969943 <6>[ 0.242473] CPU features: detected: 32-bit EL0 Support
10481 16:49:12.980056 <6>[ 0.247835] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10482 16:49:12.986362 <6>[ 0.256690] CPU features: detected: Common not Private translations
10483 16:49:12.993289 <6>[ 0.263166] CPU features: detected: CRC32 instructions
10484 16:49:12.999648 <6>[ 0.268517] CPU features: detected: RCpc load-acquire (LDAPR)
10485 16:49:13.002911 <6>[ 0.274476] CPU features: detected: LSE atomic instructions
10486 16:49:13.009623 <6>[ 0.280294] CPU features: detected: Privileged Access Never
10487 16:49:13.016111 <6>[ 0.286109] CPU features: detected: RAS Extension Support
10488 16:49:13.022687 <6>[ 0.291718] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10489 16:49:13.026453 <6>[ 0.298935] CPU: All CPU(s) started at EL2
10490 16:49:13.032810 <6>[ 0.303252] alternatives: applying system-wide alternatives
10491 16:49:13.042987 <6>[ 0.313957] devtmpfs: initialized
10492 16:49:13.058175 <6>[ 0.322858] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10493 16:49:13.065081 <6>[ 0.332823] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10494 16:49:13.071815 <6>[ 0.340935] pinctrl core: initialized pinctrl subsystem
10495 16:49:13.074999 <6>[ 0.347741] DMI not present or invalid.
10496 16:49:13.081440 <6>[ 0.352163] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10497 16:49:13.091381 <6>[ 0.359050] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10498 16:49:13.098203 <6>[ 0.366629] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10499 16:49:13.107850 <6>[ 0.374842] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10500 16:49:13.111114 <6>[ 0.383094] audit: initializing netlink subsys (disabled)
10501 16:49:13.121060 <5>[ 0.388796] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10502 16:49:13.127533 <6>[ 0.389557] thermal_sys: Registered thermal governor 'step_wise'
10503 16:49:13.134049 <6>[ 0.396762] thermal_sys: Registered thermal governor 'power_allocator'
10504 16:49:13.137141 <6>[ 0.403018] cpuidle: using governor menu
10505 16:49:13.143915 <6>[ 0.413983] NET: Registered PF_QIPCRTR protocol family
10506 16:49:13.150691 <6>[ 0.419499] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10507 16:49:13.157196 <6>[ 0.426604] ASID allocator initialised with 32768 entries
10508 16:49:13.160492 <6>[ 0.433254] Serial: AMBA PL011 UART driver
10509 16:49:13.171109 <4>[ 0.442247] Trying to register duplicate clock ID: 134
10510 16:49:13.227780 <6>[ 0.502283] KASLR enabled
10511 16:49:13.242175 <6>[ 0.510066] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10512 16:49:13.248716 <6>[ 0.517078] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10513 16:49:13.255302 <6>[ 0.523566] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10514 16:49:13.261971 <6>[ 0.530572] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10515 16:49:13.268625 <6>[ 0.537061] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10516 16:49:13.275202 <6>[ 0.544068] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10517 16:49:13.281821 <6>[ 0.550558] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10518 16:49:13.288621 <6>[ 0.557564] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10519 16:49:13.291872 <6>[ 0.565101] ACPI: Interpreter disabled.
10520 16:49:13.300563 <6>[ 0.571574] iommu: Default domain type: Translated
10521 16:49:13.307053 <6>[ 0.576691] iommu: DMA domain TLB invalidation policy: strict mode
10522 16:49:13.310347 <5>[ 0.583343] SCSI subsystem initialized
10523 16:49:13.316754 <6>[ 0.587513] usbcore: registered new interface driver usbfs
10524 16:49:13.324029 <6>[ 0.593247] usbcore: registered new interface driver hub
10525 16:49:13.327151 <6>[ 0.598800] usbcore: registered new device driver usb
10526 16:49:13.334297 <6>[ 0.604931] pps_core: LinuxPPS API ver. 1 registered
10527 16:49:13.343616 <6>[ 0.610125] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10528 16:49:13.346625 <6>[ 0.619472] PTP clock support registered
10529 16:49:13.350046 <6>[ 0.623714] EDAC MC: Ver: 3.0.0
10530 16:49:13.357655 <6>[ 0.628913] FPGA manager framework
10531 16:49:13.364363 <6>[ 0.632592] Advanced Linux Sound Architecture Driver Initialized.
10532 16:49:13.367813 <6>[ 0.639375] vgaarb: loaded
10533 16:49:13.374135 <6>[ 0.642518] clocksource: Switched to clocksource arch_sys_counter
10534 16:49:13.377549 <5>[ 0.648956] VFS: Disk quotas dquot_6.6.0
10535 16:49:13.384512 <6>[ 0.653139] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10536 16:49:13.387262 <6>[ 0.660329] pnp: PnP ACPI: disabled
10537 16:49:13.396357 <6>[ 0.667037] NET: Registered PF_INET protocol family
10538 16:49:13.405773 <6>[ 0.672620] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10539 16:49:13.417006 <6>[ 0.684924] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10540 16:49:13.426668 <6>[ 0.693739] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10541 16:49:13.433788 <6>[ 0.701712] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10542 16:49:13.443679 <6>[ 0.710416] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10543 16:49:13.450161 <6>[ 0.720160] TCP: Hash tables configured (established 65536 bind 65536)
10544 16:49:13.456682 <6>[ 0.727020] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10545 16:49:13.466933 <6>[ 0.734217] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10546 16:49:13.472845 <6>[ 0.741923] NET: Registered PF_UNIX/PF_LOCAL protocol family
10547 16:49:13.479622 <6>[ 0.748095] RPC: Registered named UNIX socket transport module.
10548 16:49:13.483000 <6>[ 0.754251] RPC: Registered udp transport module.
10549 16:49:13.486278 <6>[ 0.759185] RPC: Registered tcp transport module.
10550 16:49:13.496111 <6>[ 0.764117] RPC: Registered tcp NFSv4.1 backchannel transport module.
10551 16:49:13.499365 <6>[ 0.770787] PCI: CLS 0 bytes, default 64
10552 16:49:13.502969 <6>[ 0.775140] Unpacking initramfs...
10553 16:49:13.512732 <6>[ 0.779276] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10554 16:49:13.519148 <6>[ 0.787957] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10555 16:49:13.526114 <6>[ 0.796851] kvm [1]: IPA Size Limit: 40 bits
10556 16:49:13.528973 <6>[ 0.801376] kvm [1]: GICv3: no GICV resource entry
10557 16:49:13.535547 <6>[ 0.806398] kvm [1]: disabling GICv2 emulation
10558 16:49:13.541837 <6>[ 0.811086] kvm [1]: GIC system register CPU interface enabled
10559 16:49:13.545196 <6>[ 0.817251] kvm [1]: vgic interrupt IRQ18
10560 16:49:13.551481 <6>[ 0.821609] kvm [1]: VHE mode initialized successfully
10561 16:49:13.555163 <5>[ 0.827943] Initialise system trusted keyrings
10562 16:49:13.561346 <6>[ 0.832758] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10563 16:49:13.571050 <6>[ 0.842841] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10564 16:49:13.577799 <5>[ 0.849282] NFS: Registering the id_resolver key type
10565 16:49:13.581066 <5>[ 0.854587] Key type id_resolver registered
10566 16:49:13.587820 <5>[ 0.859002] Key type id_legacy registered
10567 16:49:13.594377 <6>[ 0.863280] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10568 16:49:13.601053 <6>[ 0.870199] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10569 16:49:13.607328 <6>[ 0.877931] 9p: Installing v9fs 9p2000 file system support
10570 16:49:13.644144 <5>[ 0.915943] Key type asymmetric registered
10571 16:49:13.647975 <5>[ 0.920276] Asymmetric key parser 'x509' registered
10572 16:49:13.657423 <6>[ 0.925421] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10573 16:49:13.660994 <6>[ 0.933036] io scheduler mq-deadline registered
10574 16:49:13.664077 <6>[ 0.937797] io scheduler kyber registered
10575 16:49:13.683933 <6>[ 0.955253] EINJ: ACPI disabled.
10576 16:49:13.716514 <4>[ 0.981213] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 16:49:13.726104 <4>[ 0.991883] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10578 16:49:13.742648 <6>[ 1.013082] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10579 16:49:13.749789 <6>[ 1.021235] printk: console [ttyS0] disabled
10580 16:49:13.778042 <6>[ 1.045884] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10581 16:49:13.784453 <6>[ 1.055357] printk: console [ttyS0] enabled
10582 16:49:13.787743 <6>[ 1.055357] printk: console [ttyS0] enabled
10583 16:49:13.794945 <6>[ 1.064253] printk: bootconsole [mtk8250] disabled
10584 16:49:13.797758 <6>[ 1.064253] printk: bootconsole [mtk8250] disabled
10585 16:49:13.804486 <6>[ 1.075644] SuperH (H)SCI(F) driver initialized
10586 16:49:13.807617 <6>[ 1.080947] msm_serial: driver initialized
10587 16:49:13.823211 <6>[ 1.090021] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10588 16:49:13.832492 <6>[ 1.098573] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10589 16:49:13.839011 <6>[ 1.107118] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10590 16:49:13.848542 <6>[ 1.115750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10591 16:49:13.855151 <6>[ 1.124455] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10592 16:49:13.865382 <6>[ 1.133171] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10593 16:49:13.875583 <6>[ 1.141712] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10594 16:49:13.881701 <6>[ 1.150528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10595 16:49:13.891401 <6>[ 1.159073] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10596 16:49:13.903781 <6>[ 1.175045] loop: module loaded
10597 16:49:13.910789 <6>[ 1.180933] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10598 16:49:13.933788 <4>[ 1.204447] mtk-pmic-keys: Failed to locate of_node [id: -1]
10599 16:49:13.940326 <6>[ 1.211433] megasas: 07.719.03.00-rc1
10600 16:49:13.949922 <6>[ 1.221333] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10601 16:49:13.958547 <6>[ 1.229921] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10602 16:49:13.975147 <6>[ 1.246666] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10603 16:49:14.032057 <6>[ 1.297034] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10604 16:49:15.942654 <6>[ 3.213659] Freeing initrd memory: 55048K
10605 16:49:15.952191 <6>[ 3.223845] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10606 16:49:15.963195 <6>[ 3.234815] tun: Universal TUN/TAP device driver, 1.6
10607 16:49:15.966720 <6>[ 3.240874] thunder_xcv, ver 1.0
10608 16:49:15.969876 <6>[ 3.244381] thunder_bgx, ver 1.0
10609 16:49:15.973757 <6>[ 3.247878] nicpf, ver 1.0
10610 16:49:15.983818 <6>[ 3.251926] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10611 16:49:15.986769 <6>[ 3.259402] hns3: Copyright (c) 2017 Huawei Corporation.
10612 16:49:15.993894 <6>[ 3.264990] hclge is initializing
10613 16:49:15.997313 <6>[ 3.268570] e1000: Intel(R) PRO/1000 Network Driver
10614 16:49:16.003673 <6>[ 3.273699] e1000: Copyright (c) 1999-2006 Intel Corporation.
10615 16:49:16.006750 <6>[ 3.279712] e1000e: Intel(R) PRO/1000 Network Driver
10616 16:49:16.013719 <6>[ 3.284927] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10617 16:49:16.020573 <6>[ 3.291112] igb: Intel(R) Gigabit Ethernet Network Driver
10618 16:49:16.026955 <6>[ 3.296766] igb: Copyright (c) 2007-2014 Intel Corporation.
10619 16:49:16.033199 <6>[ 3.302603] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10620 16:49:16.040719 <6>[ 3.309120] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10621 16:49:16.043241 <6>[ 3.315585] sky2: driver version 1.30
10622 16:49:16.049696 <6>[ 3.320620] VFIO - User Level meta-driver version: 0.3
10623 16:49:16.057496 <6>[ 3.328838] usbcore: registered new interface driver usb-storage
10624 16:49:16.064288 <6>[ 3.335281] usbcore: registered new device driver onboard-usb-hub
10625 16:49:16.073286 <6>[ 3.344352] mt6397-rtc mt6359-rtc: registered as rtc0
10626 16:49:16.082929 <6>[ 3.349822] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:49:16 UTC (1685810956)
10627 16:49:16.085995 <6>[ 3.359407] i2c_dev: i2c /dev entries driver
10628 16:49:16.102786 <6>[ 3.371215] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10629 16:49:16.109895 <6>[ 3.381430] sdhci: Secure Digital Host Controller Interface driver
10630 16:49:16.116664 <6>[ 3.387868] sdhci: Copyright(c) Pierre Ossman
10631 16:49:16.123299 <6>[ 3.393291] Synopsys Designware Multimedia Card Interface Driver
10632 16:49:16.127242 <6>[ 3.399943] mmc0: CQHCI version 5.10
10633 16:49:16.133876 <6>[ 3.400472] sdhci-pltfm: SDHCI platform and OF driver helper
10634 16:49:16.140416 <6>[ 3.411953] ledtrig-cpu: registered to indicate activity on CPUs
10635 16:49:16.151422 <6>[ 3.419313] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10636 16:49:16.158248 <6>[ 3.426716] usbcore: registered new interface driver usbhid
10637 16:49:16.161336 <6>[ 3.432543] usbhid: USB HID core driver
10638 16:49:16.167728 <6>[ 3.436784] spi_master spi0: will run message pump with realtime priority
10639 16:49:16.210957 <6>[ 3.475562] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10640 16:49:16.229617 <6>[ 3.491237] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10641 16:49:16.234391 <6>[ 3.504809] mmc0: Command Queue Engine enabled
10642 16:49:16.240019 <6>[ 3.509553] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10643 16:49:16.247350 <6>[ 3.516528] cros-ec-spi spi0.0: Chrome EC device registered
10644 16:49:16.250317 <6>[ 3.516878] mmcblk0: mmc0:0001 DA4128 116 GiB
10645 16:49:16.260129 <6>[ 3.531648] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10646 16:49:16.267638 <6>[ 3.538971] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10647 16:49:16.274894 <6>[ 3.544862] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10648 16:49:16.280318 <6>[ 3.550851] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10649 16:49:16.297789 <6>[ 3.565916] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10650 16:49:16.306299 <6>[ 3.577342] NET: Registered PF_PACKET protocol family
10651 16:49:16.312466 <6>[ 3.582825] 9pnet: Installing 9P2000 support
10652 16:49:16.315815 <5>[ 3.587401] Key type dns_resolver registered
10653 16:49:16.318882 <6>[ 3.592301] registered taskstats version 1
10654 16:49:16.325767 <5>[ 3.596707] Loading compiled-in X.509 certificates
10655 16:49:16.359123 <4>[ 3.623594] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10656 16:49:16.368948 <4>[ 3.634321] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10657 16:49:16.378932 <3>[ 3.647330] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10658 16:49:16.392112 <6>[ 3.663275] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10659 16:49:16.399081 <6>[ 3.670031] xhci-mtk 11200000.usb: xHCI Host Controller
10660 16:49:16.405063 <6>[ 3.675537] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10661 16:49:16.415452 <6>[ 3.683402] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10662 16:49:16.421636 <6>[ 3.692830] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10663 16:49:16.428346 <6>[ 3.698931] xhci-mtk 11200000.usb: xHCI Host Controller
10664 16:49:16.435202 <6>[ 3.704539] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10665 16:49:16.441438 <6>[ 3.712201] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10666 16:49:16.448760 <6>[ 3.720091] hub 1-0:1.0: USB hub found
10667 16:49:16.451491 <6>[ 3.724152] hub 1-0:1.0: 1 port detected
10668 16:49:16.461666 <6>[ 3.728507] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10669 16:49:16.465406 <6>[ 3.737347] hub 2-0:1.0: USB hub found
10670 16:49:16.468115 <6>[ 3.741387] hub 2-0:1.0: 1 port detected
10671 16:49:16.476914 <6>[ 3.748634] mtk-msdc 11f70000.mmc: Got CD GPIO
10672 16:49:16.493387 <6>[ 3.762106] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10673 16:49:16.500010 <6>[ 3.770175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10674 16:49:16.509806 <4>[ 3.778146] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10675 16:49:16.520336 <6>[ 3.787803] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10676 16:49:16.526644 <6>[ 3.795885] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10677 16:49:16.536586 <6>[ 3.803913] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10678 16:49:16.542783 <6>[ 3.811833] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10679 16:49:16.549821 <6>[ 3.819655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10680 16:49:16.560126 <6>[ 3.827485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10681 16:49:16.570033 <6>[ 3.838207] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10682 16:49:16.579704 <6>[ 3.846614] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10683 16:49:16.586281 <6>[ 3.854971] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10684 16:49:16.596146 <6>[ 3.863315] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10685 16:49:16.603463 <6>[ 3.871659] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10686 16:49:16.612378 <6>[ 3.880001] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10687 16:49:16.619250 <6>[ 3.888344] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10688 16:49:16.629426 <6>[ 3.896686] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10689 16:49:16.635743 <6>[ 3.905030] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10690 16:49:16.645909 <6>[ 3.913374] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10691 16:49:16.652061 <6>[ 3.921717] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10692 16:49:16.662086 <6>[ 3.930065] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10693 16:49:16.668965 <6>[ 3.938408] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10694 16:49:16.679295 <6>[ 3.946752] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10695 16:49:16.685608 <6>[ 3.955099] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10696 16:49:16.692738 <6>[ 3.964063] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10697 16:49:16.700296 <6>[ 3.971503] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10698 16:49:16.707119 <6>[ 3.978578] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10699 16:49:16.717500 <6>[ 3.985708] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10700 16:49:16.723947 <6>[ 3.993011] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10701 16:49:16.733898 <6>[ 3.999929] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10702 16:49:16.740546 <6>[ 4.009070] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10703 16:49:16.750319 <6>[ 4.018197] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10704 16:49:16.760274 <6>[ 4.027499] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10705 16:49:16.769998 <6>[ 4.036978] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10706 16:49:16.780308 <6>[ 4.046451] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10707 16:49:16.790054 <6>[ 4.055578] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10708 16:49:16.796947 <6>[ 4.065052] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10709 16:49:16.806586 <6>[ 4.074178] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10710 16:49:16.816445 <6>[ 4.083488] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10711 16:49:16.826326 <6>[ 4.093655] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10712 16:49:16.836890 <6>[ 4.105148] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10713 16:49:16.858204 <6>[ 4.126848] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10714 16:49:16.886130 <6>[ 4.157334] hub 2-1:1.0: USB hub found
10715 16:49:16.888771 <6>[ 4.161740] hub 2-1:1.0: 3 ports detected
10716 16:49:17.010737 <6>[ 4.278794] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10717 16:49:17.165002 <6>[ 4.436328] hub 1-1:1.0: USB hub found
10718 16:49:17.168296 <6>[ 4.440790] hub 1-1:1.0: 4 ports detected
10719 16:49:17.247091 <6>[ 4.515051] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10720 16:49:17.490034 <6>[ 4.758803] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10721 16:49:17.622898 <6>[ 4.894379] hub 1-1.4:1.0: USB hub found
10722 16:49:17.626193 <6>[ 4.899006] hub 1-1.4:1.0: 2 ports detected
10723 16:49:17.922541 <6>[ 5.190799] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10724 16:49:18.114557 <6>[ 5.382797] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10725 16:49:29.119311 <6>[ 16.395470] ALSA device list:
10726 16:49:29.125607 <6>[ 16.398789] No soundcards found.
10727 16:49:29.139001 <6>[ 16.411359] Freeing unused kernel memory: 8384K
10728 16:49:29.141561 <6>[ 16.416289] Run /init as init process
10729 16:49:29.172231 <6>[ 16.444694] NET: Registered PF_INET6 protocol family
10730 16:49:29.178413 <6>[ 16.451050] Segment Routing with IPv6
10731 16:49:29.181325 <6>[ 16.455090] In-situ OAM (IOAM) with IPv6
10732 16:49:29.216338 <30>[ 16.469644] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10733 16:49:29.219711 <30>[ 16.493669] systemd[1]: Detected architecture arm64.
10734 16:49:29.223091
10735 16:49:29.226286 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10736 16:49:29.226704
10737 16:49:29.242093 <30>[ 16.515000] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10738 16:49:29.375460 <30>[ 16.644814] systemd[1]: Queued start job for default target Graphical Interface.
10739 16:49:29.403085 <30>[ 16.675963] systemd[1]: Created slice system-getty.slice.
10740 16:49:29.409468 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10741 16:49:29.426401 <30>[ 16.699379] systemd[1]: Created slice system-modprobe.slice.
10742 16:49:29.433268 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10743 16:49:29.451384 <30>[ 16.723910] systemd[1]: Created slice system-serial\x2dgetty.slice.
10744 16:49:29.460859 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10745 16:49:29.474445 <30>[ 16.747294] systemd[1]: Created slice User and Session Slice.
10746 16:49:29.481144 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10747 16:49:29.502417 <30>[ 16.771348] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10748 16:49:29.511960 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10749 16:49:29.529767 <30>[ 16.798967] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10750 16:49:29.536154 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10751 16:49:29.556607 <30>[ 16.822880] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10752 16:49:29.563853 <30>[ 16.834918] systemd[1]: Reached target Local Encrypted Volumes.
10753 16:49:29.570176 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10754 16:49:29.586058 <30>[ 16.859166] systemd[1]: Reached target Paths.
10755 16:49:29.589306 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10756 16:49:29.605747 <30>[ 16.878838] systemd[1]: Reached target Remote File Systems.
10757 16:49:29.612659 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10758 16:49:29.630624 <30>[ 16.903079] systemd[1]: Reached target Slices.
10759 16:49:29.636983 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10760 16:49:29.649927 <30>[ 16.922856] systemd[1]: Reached target Swap.
10761 16:49:29.653208 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10762 16:49:29.673203 <30>[ 16.943115] systemd[1]: Listening on initctl Compatibility Named Pipe.
10763 16:49:29.680421 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10764 16:49:29.686998 <30>[ 16.957780] systemd[1]: Listening on Journal Audit Socket.
10765 16:49:29.692812 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10766 16:49:29.705898 <30>[ 16.979059] systemd[1]: Listening on Journal Socket (/dev/log).
10767 16:49:29.712293 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10768 16:49:29.730211 <30>[ 17.003573] systemd[1]: Listening on Journal Socket.
10769 16:49:29.736526 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10770 16:49:29.749608 <30>[ 17.023139] systemd[1]: Listening on udev Control Socket.
10771 16:49:29.756234 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10772 16:49:29.774210 <30>[ 17.047464] systemd[1]: Listening on udev Kernel Socket.
10773 16:49:29.780521 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10774 16:49:29.825552 <30>[ 17.099032] systemd[1]: Mounting Huge Pages File System...
10775 16:49:29.832341 Mounting [0;1;39mHuge Pages File System[0m...
10776 16:49:29.847756 <30>[ 17.120877] systemd[1]: Mounting POSIX Message Queue File System...
10777 16:49:29.854646 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10778 16:49:29.901752 <30>[ 17.175057] systemd[1]: Mounting Kernel Debug File System...
10779 16:49:29.908042 Mounting [0;1;39mKernel Debug File System[0m...
10780 16:49:29.925413 <30>[ 17.195081] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10781 16:49:29.935913 <30>[ 17.205884] systemd[1]: Starting Create list of static device nodes for the current kernel...
10782 16:49:29.942657 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10783 16:49:29.959986 <30>[ 17.232990] systemd[1]: Starting Load Kernel Module configfs...
10784 16:49:29.965994 Starting [0;1;39mLoad Kernel Module configfs[0m...
10785 16:49:29.983422 <30>[ 17.256926] systemd[1]: Starting Load Kernel Module drm...
10786 16:49:29.990148 Starting [0;1;39mLoad Kernel Module drm[0m...
10787 16:49:30.008594 <30>[ 17.278970] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10788 16:49:30.019601 <30>[ 17.292597] systemd[1]: Starting Journal Service...
10789 16:49:30.022564 Starting [0;1;39mJournal Service[0m...
10790 16:49:30.039673 <30>[ 17.313380] systemd[1]: Starting Load Kernel Modules...
10791 16:49:30.046504 Starting [0;1;39mLoad Kernel Modules[0m...
10792 16:49:30.105771 <30>[ 17.375624] systemd[1]: Starting Remount Root and Kernel File Systems...
10793 16:49:30.112498 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10794 16:49:30.128343 <30>[ 17.401359] systemd[1]: Starting Coldplug All udev Devices...
10795 16:49:30.135124 Starting [0;1;39mColdplug All udev Devices[0m...
10796 16:49:30.152163 <30>[ 17.425373] systemd[1]: Started Journal Service.
10797 16:49:30.158764 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10798 16:49:30.175453 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10799 16:49:30.190641 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10800 16:49:30.206397 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10801 16:49:30.226216 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10802 16:49:30.243428 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10803 16:49:30.263569 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10804 16:49:30.279148 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10805 16:49:30.299017 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10806 16:49:30.317582 See 'systemctl status systemd-remount-fs.service' for details.
10807 16:49:30.361972 Mounting [0;1;39mKernel Configuration File System[0m...
10808 16:49:30.385008 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10809 16:49:30.401357 <46>[ 17.671372] systemd-journald[173]: Received client request to flush runtime journal.
10810 16:49:30.410971 Starting [0;1;39mLoad/Save Random Seed[0m...
10811 16:49:30.429348 Starting [0;1;39mApply Kernel Variables[0m...
10812 16:49:30.448703 Starting [0;1;39mCreate System Users[0m...
10813 16:49:30.464347 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10814 16:49:30.486075 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10815 16:49:30.499001 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10816 16:49:30.514935 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10817 16:49:30.535134 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10818 16:49:30.555155 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10819 16:49:30.614172 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10820 16:49:30.638316 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10821 16:49:30.651036 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10822 16:49:30.665740 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10823 16:49:30.714153 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10824 16:49:30.741036 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10825 16:49:30.761902 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10826 16:49:30.781790 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10827 16:49:30.826516 Starting [0;1;39mNetwork Time Synchronization[0m...
10828 16:49:30.845434 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10829 16:49:30.881288 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10830 16:49:30.945530 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m<6>[ 18.214233] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10831 16:49:30.946015 .
10832 16:49:30.956992 <6>[ 18.229965] remoteproc remoteproc0: scp is available
10833 16:49:30.969584 <4>[ 18.239317] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10834 16:49:30.976503 <6>[ 18.249415] remoteproc remoteproc0: powering up scp
10835 16:49:30.986236 <4>[ 18.254658] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10836 16:49:30.993054 <3>[ 18.265246] remoteproc remoteproc0: request_firmware failed: -2
10837 16:49:31.013093 <3>[ 18.283044] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10838 16:49:31.019625 <6>[ 18.284287] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10839 16:49:31.029644 <3>[ 18.291765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10840 16:49:31.036902 <6>[ 18.298924] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10841 16:49:31.046858 <3>[ 18.306995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10842 16:49:31.056698 <6>[ 18.323920] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10843 16:49:31.062576 Startin<3>[ 18.333284] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10844 16:49:31.072806 g [0;1;39mLoad/<3>[ 18.342798] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10845 16:49:31.082904 Save Screen …o<3>[ 18.351794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10846 16:49:31.089233 f leds:white:kbd<6>[ 18.355971] usbcore: registered new interface driver r8152
10847 16:49:31.098972 _backlight[0m..<3>[ 18.361276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10848 16:49:31.099584 .
10849 16:49:31.105730 <6>[ 18.365652] mc: Linux media interface: v0.10
10850 16:49:31.112652 <3>[ 18.382778] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10851 16:49:31.119113 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10852 16:49:31.133430 <3>[ 18.403042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10853 16:49:31.140201 <3>[ 18.411322] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10854 16:49:31.150071 <3>[ 18.419445] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10855 16:49:31.156478 <6>[ 18.422590] videodev: Linux video capture interface: v2.00
10856 16:49:31.163091 <3>[ 18.427548] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10857 16:49:31.169550 <4>[ 18.428305] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10858 16:49:31.179713 <3>[ 18.443131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10859 16:49:31.186714 <3>[ 18.456995] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 16:49:31.196296 <3>[ 18.457006] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 16:49:31.202972 <4>[ 18.462831] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10862 16:49:31.209140 <6>[ 18.478767] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10863 16:49:31.215405 <3>[ 18.480487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10864 16:49:31.222387 <6>[ 18.487361] pci_bus 0000:00: root bus resource [bus 00-ff]
10865 16:49:31.232016 [[0;32m OK [<3>[ 18.495432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10866 16:49:31.241914 0m] Finished [0<6>[ 18.496710] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10867 16:49:31.252078 ;1;39mLoad/Save <6>[ 18.498309] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10868 16:49:31.262295 Screen …s of l<6>[ 18.499096] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10869 16:49:31.272762 eds:white:kbd_ba<6>[ 18.499263] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10870 16:49:31.272855 cklight[0m.
10871 16:49:31.279126 <6>[ 18.501181] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10872 16:49:31.289275 <3>[ 18.511116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10873 16:49:31.296175 <4>[ 18.518057] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10874 16:49:31.305609 <4>[ 18.518067] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10875 16:49:31.315924 <6>[ 18.519166] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10876 16:49:31.323057 <6>[ 18.519265] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10877 16:49:31.330297 <4>[ 18.523894] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10878 16:49:31.336393 <4>[ 18.523894] Fallback method does not support PEC.
10879 16:49:31.342912 <3>[ 18.545793] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 16:49:31.353257 <6>[ 18.550229] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10881 16:49:31.356413 <6>[ 18.550408] pci 0000:00:00.0: supports D1 D2
10882 16:49:31.366344 <6>[ 18.580427] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10883 16:49:31.372713 <6>[ 18.583823] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10884 16:49:31.376195 <6>[ 18.622755] r8152 2-1.3:1.0 eth0: v1.12.13
10885 16:49:31.379509 <6>[ 18.623884] Bluetooth: Core ver 2.22
10886 16:49:31.386117 <6>[ 18.624098] NET: Registered PF_BLUETOOTH protocol family
10887 16:49:31.392875 <6>[ 18.624103] Bluetooth: HCI device and connection manager initialized
10888 16:49:31.399399 <6>[ 18.624126] Bluetooth: HCI socket layer initialized
10889 16:49:31.402601 <6>[ 18.624134] Bluetooth: L2CAP socket layer initialized
10890 16:49:31.409524 <6>[ 18.624157] Bluetooth: SCO socket layer initialized
10891 16:49:31.416022 <6>[ 18.631240] usbcore: registered new interface driver cdc_ether
10892 16:49:31.423101 <6>[ 18.633518] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10893 16:49:31.429482 <6>[ 18.633668] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10894 16:49:31.436743 <6>[ 18.633700] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10895 16:49:31.444139 <6>[ 18.633723] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10896 16:49:31.450496 <6>[ 18.633741] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10897 16:49:31.457102 <6>[ 18.633858] pci 0000:01:00.0: supports D1 D2
10898 16:49:31.463655 <6>[ 18.633862] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10899 16:49:31.470225 <3>[ 18.634661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 16:49:31.477246 <6>[ 18.646618] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10901 16:49:31.483424 <6>[ 18.651147] usbcore: registered new interface driver r8153_ecm
10902 16:49:31.493141 <6>[ 18.655309] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10903 16:49:31.500176 <6>[ 18.666250] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10904 16:49:31.506440 <6>[ 18.666612] usbcore: registered new interface driver btusb
10905 16:49:31.516744 <4>[ 18.667301] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10906 16:49:31.523115 <3>[ 18.667314] Bluetooth: hci0: Failed to load firmware file (-2)
10907 16:49:31.526666 <3>[ 18.667318] Bluetooth: hci0: Failed to set up firmware (-2)
10908 16:49:31.539955 <4>[ 18.667323] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10909 16:49:31.546846 <6>[ 18.671250] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10910 16:49:31.553120 <6>[ 18.671269] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10911 16:49:31.563279 <6>[ 18.671286] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10912 16:49:31.569917 <6>[ 18.673880] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10913 16:49:31.579891 <6>[ 18.678325] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10914 16:49:31.589777 <6>[ 18.681750] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10915 16:49:31.596166 <6>[ 18.682501] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10916 16:49:31.600033 <6>[ 18.686427] remoteproc remoteproc0: powering up scp
10917 16:49:31.609902 <4>[ 18.686473] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10918 16:49:31.616446 <3>[ 18.686482] remoteproc remoteproc0: request_firmware failed: -2
10919 16:49:31.623905 <3>[ 18.686485] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10920 16:49:31.630143 <6>[ 18.687216] usbcore: registered new interface driver uvcvideo
10921 16:49:31.636835 <6>[ 18.692969] pci 0000:00:00.0: PCI bridge to [bus 01]
10922 16:49:31.643687 <6>[ 18.692977] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10923 16:49:31.653192 <3>[ 18.721653] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 16:49:31.659436 <3>[ 18.722454] power_supply sbs-5-000b: driver failed to report `current_now' property: -6
10925 16:49:31.666196 <6>[ 18.722662] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10926 16:49:31.672782 <6>[ 18.723555] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10927 16:49:31.679661 <6>[ 18.723913] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10928 16:49:31.689344 <3>[ 18.731608] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 16:49:31.696429 <5>[ 18.745720] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10930 16:49:31.706670 <3>[ 18.939095] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10931 16:49:31.712995 <5>[ 18.956374] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10932 16:49:31.719860 <3>[ 18.984661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 16:49:31.730248 <4>[ 18.989980] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10934 16:49:31.733114 <6>[ 19.007474] cfg80211: failed to load regulatory.db
10935 16:49:31.739795 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10936 16:49:31.749999 <3>[ 19.020220] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10937 16:49:31.783995 <3>[ 19.054150] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 16:49:31.790785 <6>[ 19.058024] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10939 16:49:31.797564 <6>[ 19.070443] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10940 16:49:31.814333 <3>[ 19.084389] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 16:49:31.823800 <6>[ 19.097204] mt7921e 0000:01:00.0: ASIC revision: 79610010
10942 16:49:31.931410 [[0;32m OK [<4>[ 19.198333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10943 16:49:31.937630 0m] Reached target [0;1;39mBluetooth[0m.
10944 16:49:31.952108 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10945 16:49:31.969324 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10946 16:49:31.981887 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10947 16:49:31.997522 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10948 16:49:32.018046 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10949 16:49:32.029424 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10950 16:49:32.053720 [[0;32m OK [<4>[ 19.321333] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10951 16:49:32.060945 0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10952 16:49:32.074918 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10953 16:49:32.089558 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10954 16:49:32.108919 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10955 16:49:32.142216 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10956 16:49:32.176523 <4>[ 19.443221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 16:49:32.186826 Starting [0;1;39mUser Login Management[0m...
10958 16:49:32.203748 Starting [0;1;39mPermit User Sessions[0m...
10959 16:49:32.221839 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10960 16:49:32.238149 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10961 16:49:32.255128 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10962 16:49:32.275662 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10963 16:49:32.299767 <4>[ 19.566280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10964 16:49:32.305847 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10965 16:49:32.313324 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10966 16:49:32.331200 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10967 16:49:32.350702 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10968 16:49:32.370104 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10969 16:49:32.417938 <4>[ 19.685023] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10970 16:49:32.427403 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10971 16:49:32.454288 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10972 16:49:32.498228
10973 16:49:32.498359
10974 16:49:32.501216 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10975 16:49:32.501291
10976 16:49:32.504849 debian-bullseye-arm64 login: root (automatic login)
10977 16:49:32.504951
10978 16:49:32.505044
10979 16:49:32.521194 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
10980 16:49:32.521297
10981 16:49:32.527927 The programs included with the Debian GNU/Linux system are free software;
10982 16:49:32.541063 the exact d<4>[ 19.807054] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 16:49:32.544705 istribution terms for each program are described in the
10984 16:49:32.551699 individual files in /usr/share/doc/*/copyright.
10985 16:49:32.551778
10986 16:49:32.554406 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10987 16:49:32.557280 permitted by applicable law.
10988 16:49:32.557872 Matched prompt #10: / #
10990 16:49:32.558214 Setting prompt string to ['/ #']
10991 16:49:32.558338 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10993 16:49:32.558635 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10994 16:49:32.558752 start: 2.2.6 expect-shell-connection (timeout 00:02:38) [common]
10995 16:49:32.558913 Setting prompt string to ['/ #']
10996 16:49:32.559009 Forcing a shell prompt, looking for ['/ #']
10998 16:49:32.609300 / #
10999 16:49:32.609590 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11000 16:49:32.609808 Waiting using forced prompt support (timeout 00:02:30)
11001 16:49:32.614726
11002 16:49:32.615219 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11003 16:49:32.615435 start: 2.2.7 export-device-env (timeout 00:02:38) [common]
11004 16:49:32.615751 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11005 16:49:32.616047 end: 2.2 depthcharge-retry (duration 00:02:22) [common]
11006 16:49:32.616350 end: 2 depthcharge-action (duration 00:02:22) [common]
11007 16:49:32.616653 start: 3 lava-test-retry (timeout 00:07:16) [common]
11008 16:49:32.616960 start: 3.1 lava-test-shell (timeout 00:07:16) [common]
11009 16:49:32.617223 Using namespace: common
11011 16:49:32.718004 / # #
11012 16:49:32.718384 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11013 16:49:32.718770 <4>[ 19.929027] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11014 16:49:32.723552 #
11015 16:49:32.724069 Using /lava-10576298
11017 16:49:32.824908 / # export SHELL=/bin/sh
11018 16:49:32.825147 <4>[ 20.048876] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11019 16:49:32.830292 export SHELL=/bin/sh
11021 16:49:32.930796 / # . /lava-10576298/environment
11022 16:49:32.930995 . /lava-10576298/environment<4>[ 20.168615] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11023 16:49:32.935807
11025 16:49:33.036410 / # /lava-10576298/bin/lava-test-runner /lava-10576298/0
11026 16:49:33.037114 Test shell timeout: 10s (minimum of the action and connection timeout)
11027 16:49:33.039359 /lava-10576298/bin/lava-test-runner /lava-10576298/0<4>[ 20.288386] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11028 16:49:33.042239
11029 16:49:33.083313 + export TESTRUN_ID=0_igt-gpu-panf<8>[ 20.341062] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10576298_1.5.2.3.1>
11030 16:49:33.083426 rost
11031 16:49:33.083493 + cd /lava-10576298/0/tests/0_igt-gpu-panfrost
11032 16:49:33.083555 + cat uuid
11033 16:49:33.083614 + UUID=10576298_1.5.2.3.1
11034 16:49:33.083672 + set +x
11035 16:49:33.083914 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10576298_1.5.2.3.1
11036 16:49:33.083986 Starting test lava.0_igt-gpu-panfrost (10576298_1.5.2.3.1)
11037 16:49:33.084065 Skipping test definition patterns.
11038 16:49:33.088406 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11039 16:49:33.098618 <8>[ 20.372217] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11040 16:49:33.098872 Received signal: <TESTSET> START panfrost_gem_new
11041 16:49:33.098945 Starting test_set panfrost_gem_new
11042 16:49:33.128322 <14>[ 20.401458] [IGT] panfrost_gem_new: executing
11043 16:49:33.134616 <3>[ 20.404659] mt7921e 0000:01:00.0: hardware init failed
11044 16:49:33.141204 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.415322] [IGT] panfrost_gem_new: exiting, ret=77
11045 16:49:33.144300 .1.31 aarch64)
11046 16:49:33.157197 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.427523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11047 16:49:33.157357 b/drmtest.c:621:
11048 16:49:33.157669 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11050 16:49:33.161194 Test requirement: !(fd<0)
11051 16:49:33.164451 No known gpu found for chipset flags 0x32 (panfrost)
11052 16:49:33.167422 Last errno: 2, No such file or directory
11053 16:49:33.174102 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11054 16:49:33.177840 <14>[ 20.452753] [IGT] panfrost_gem_new: executing
11055 16:49:33.187162 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.460870] [IGT] panfrost_gem_new: exiting, ret=77
11056 16:49:33.190498 .1.31 aarch64)
11057 16:49:33.201016 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11059 16:49:33.204145 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.472926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11060 16:49:33.204611 b/drmtest.c:621:
11061 16:49:33.207160 Test requirement: !(fd<0)
11062 16:49:33.210544 No known gpu found for chipset flags 0x32 (panfrost)
11063 16:49:33.213858 Last errno: 2, No such file or directory
11064 16:49:33.217388 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11065 16:49:33.224857 <14>[ 20.497788] [IGT] panfrost_gem_new: executing
11066 16:49:33.234105 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.505894] [IGT] panfrost_gem_new: exiting, ret=77
11067 16:49:33.234550 .1.31 aarch64)
11068 16:49:33.249208 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.518094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11069 16:49:33.249959 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11071 16:49:33.251316 b/drmtest.c:621:
11072 16:49:33.254180 Test requireme<8>[ 20.527886] <LAVA_SIGNAL_TESTSET STOP>
11073 16:49:33.254849 Received signal: <TESTSET> STOP
11074 16:49:33.255249 Closing test_set panfrost_gem_new
11075 16:49:33.257380 nt: !(fd<0)
11076 16:49:33.260354 No known gpu found for chipset flags 0x32 (panfrost)
11077 16:49:33.264132 Last errno: 2, No such file or directory
11078 16:49:33.267056 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11079 16:49:33.280342 <8>[ 20.553550] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11080 16:49:33.281082 Received signal: <TESTSET> START panfrost_get_param
11081 16:49:33.281498 Starting test_set panfrost_get_param
11082 16:49:33.304376 <14>[ 20.577394] [IGT] panfrost_get_param: executing
11083 16:49:33.313933 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.585940] [IGT] panfrost_get_param: exiting, ret=77
11084 16:49:33.314429 .1.31 aarch64)
11085 16:49:33.327537 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.597844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11086 16:49:33.328222 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11088 16:49:33.330149 b/drmtest.c:621:
11089 16:49:33.330571 Test requirement: !(fd<0)
11090 16:49:33.337482 No known gpu found for chipset flags 0x32 (panfrost)
11091 16:49:33.340904 Last errno: 2, No such file or directory
11092 16:49:33.343901 [1mSubtest base-params: SKIP (0.000s)[0m
11093 16:49:33.351007 <14>[ 20.624560] [IGT] panfrost_get_param: executing
11094 16:49:33.360920 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.633018] [IGT] panfrost_get_param: exiting, ret=77
11095 16:49:33.361347 .1.31 aarch64)
11096 16:49:33.374056 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.644934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11097 16:49:33.374766 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11099 16:49:33.378080 b/drmtest.c:621:
11100 16:49:33.378506 Test requirement: !(fd<0)
11101 16:49:33.383739 No known gpu found for chipset flags 0x32 (panfrost)
11102 16:49:33.386963 Last errno: 2, No such file or directory
11103 16:49:33.390463 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11104 16:49:33.397417 <14>[ 20.670572] [IGT] panfrost_get_param: executing
11105 16:49:33.407075 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.678782] [IGT] panfrost_get_param: exiting, ret=77
11106 16:49:33.407646 .1.31 aarch64)
11107 16:49:33.419846 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.691056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11108 16:49:33.420594 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11110 16:49:33.423229 b/drmtest.c:621:
11111 16:49:33.427263 Test requireme<8>[ 20.700949] <LAVA_SIGNAL_TESTSET STOP>
11112 16:49:33.427989 Received signal: <TESTSET> STOP
11113 16:49:33.428433 Closing test_set panfrost_get_param
11114 16:49:33.430805 nt: !(fd<0)
11115 16:49:33.433561 No known gpu found for chipset flags 0x32 (panfrost)
11116 16:49:33.437303 Last errno: 2, No such file or directory
11117 16:49:33.439839 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11118 16:49:33.455236 <8>[ 20.727609] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11119 16:49:33.455909 Received signal: <TESTSET> START panfrost_prime
11120 16:49:33.456259 Starting test_set panfrost_prime
11121 16:49:33.478082 <14>[ 20.751269] [IGT] panfrost_prime: executing
11122 16:49:33.487457 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.759408] [IGT] panfrost_prime: exiting, ret=77
11123 16:49:33.487890 .1.31 aarch64)
11124 16:49:33.500912 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.771017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11125 16:49:33.501611 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11127 16:49:33.504350 b/drmtest.c:621:
11128 16:49:33.507945 Test requireme<8>[ 20.781110] <LAVA_SIGNAL_TESTSET STOP>
11129 16:49:33.508368 nt: !(fd<0)
11130 16:49:33.508943 Received signal: <TESTSET> STOP
11131 16:49:33.509273 Closing test_set panfrost_prime
11132 16:49:33.513927 No known gpu found for chipset flags 0x32 (panfrost)
11133 16:49:33.517903 Last errno: 2, No such file or directory
11134 16:49:33.520855 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11135 16:49:33.532623 <8>[ 20.806356] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11136 16:49:33.533305 Received signal: <TESTSET> START panfrost_submit
11137 16:49:33.533736 Starting test_set panfrost_submit
11138 16:49:33.555706 <14>[ 20.828964] [IGT] panfrost_submit: executing
11139 16:49:33.565356 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.837140] [IGT] panfrost_submit: exiting, ret=77
11140 16:49:33.565793 .1.31 aarch64)
11141 16:49:33.579006 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.849101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11142 16:49:33.579631 b/drmtest.c:621:
11143 16:49:33.580285 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11145 16:49:33.581974 Test requirement: !(fd<0)
11146 16:49:33.588427 No known gpu found for chipset flags 0x32 (panfrost)
11147 16:49:33.591449 Last errno: 2, No such file or directory
11148 16:49:33.594778 [1mSubtest pan-submit: SKIP (0.000s)[0m
11149 16:49:33.601722 <14>[ 20.874047] [IGT] panfrost_submit: executing
11150 16:49:33.608668 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.882037] [IGT] panfrost_submit: exiting, ret=77
11151 16:49:33.611379 .1.31 aarch64)
11152 16:49:33.624483 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.893815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11153 16:49:33.625087 b/drmtest.c:621:
11154 16:49:33.625994 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11156 16:49:33.628148 Test requirement: !(fd<0)
11157 16:49:33.634462 No known gpu found for chipset flags 0x32 (panfrost)
11158 16:49:33.637613 Last errno: 2, No such file or directory
11159 16:49:33.641323 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11160 16:49:33.647943 <14>[ 20.921142] [IGT] panfrost_submit: executing
11161 16:49:33.657579 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.929431] [IGT] panfrost_submit: exiting, ret=77
11162 16:49:33.658012 .1.31 aarch64)
11163 16:49:33.671125 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.941202] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11164 16:49:33.671900 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11166 16:49:33.674133 b/drmtest.c:621:
11167 16:49:33.677671 Test requirement: !(fd<0)
11168 16:49:33.680715 No known gpu found for chipset flags 0x32 (panfrost)
11169 16:49:33.683794 Last errno: 2, No such file or directory
11170 16:49:33.690616 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11171 16:49:33.693756 <14>[ 20.968067] [IGT] panfrost_submit: executing
11172 16:49:33.703788 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.976457] [IGT] panfrost_submit: exiting, ret=77
11173 16:49:33.707023 .1.31 aarch64)
11174 16:49:33.720426 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.988602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11175 16:49:33.720925 b/drmtest.c:621:
11176 16:49:33.721644 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11178 16:49:33.723861 Test requirement: !(fd<0)
11179 16:49:33.727004 No known gpu found for chipset flags 0x32 (panfrost)
11180 16:49:33.733194 Last errno: 2, No such file or directory
11181 16:49:33.736620 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11182 16:49:33.744020 <14>[ 21.016497] [IGT] panfrost_submit: executing
11183 16:49:33.752946 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.024800] [IGT] panfrost_submit: exiting, ret=77
11184 16:49:33.753032 .1.31 aarch64)
11185 16:49:33.766462 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.036728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11186 16:49:33.766757 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11188 16:49:33.769303 b/drmtest.c:621:
11189 16:49:33.773039 Test requirement: !(fd<0)
11190 16:49:33.776310 No known gpu found for chipset flags 0x32 (panfrost)
11191 16:49:33.778988 Last errno: 2, No such file or directory
11192 16:49:33.785983 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11193 16:49:33.792519 <14>[ 21.065155] [IGT] panfrost_submit: executing
11194 16:49:33.798943 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.073502] [IGT] panfrost_submit: exiting, ret=77
11195 16:49:33.802571 .1.31 aarch64)
11196 16:49:33.815698 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.085398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11197 16:49:33.815984 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11199 16:49:33.818715 b/drmtest.c:621:
11200 16:49:33.818823 Test requirement: !(fd<0)
11201 16:49:33.825892 No known gpu found for chipset flags 0x32 (panfrost)
11202 16:49:33.828543 Last errno: 2, No such file or directory
11203 16:49:33.832041 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11204 16:49:33.838940 <14>[ 21.111992] [IGT] panfrost_submit: executing
11205 16:49:33.848574 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.120390] [IGT] panfrost_submit: exiting, ret=77
11206 16:49:33.848663 .1.31 aarch64)
11207 16:49:33.861660 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.132343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11208 16:49:33.861774 b/drmtest.c:621:
11209 16:49:33.862044 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11211 16:49:33.865519 Test requirement: !(fd<0)
11212 16:49:33.868489 No known gpu found for chipset flags 0x32 (panfrost)
11213 16:49:33.874757 Last errno: 2, No such file or directory
11214 16:49:33.878397 [1mSubtest pan-reset: SKIP (0.000s)[0m
11215 16:49:33.884965 <14>[ 21.158319] [IGT] panfrost_submit: executing
11216 16:49:33.894818 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.166394] [IGT] panfrost_submit: exiting, ret=77
11217 16:49:33.894924 .1.31 aarch64)
11218 16:49:33.907913 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.178504] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11219 16:49:33.908184 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11221 16:49:33.910980 b/drmtest.c:621:
11222 16:49:33.911083 Test requirement: !(fd<0)
11223 16:49:33.917908 No known gpu found for chipset flags 0x32 (panfrost)
11224 16:49:33.920930 Last errno: 2, No such file or directory
11225 16:49:33.924524 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11226 16:49:33.931161 <14>[ 21.204299] [IGT] panfrost_submit: executing
11227 16:49:33.940928 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.212370] [IGT] panfrost_submit: exiting, ret=77
11228 16:49:33.941022 .1.31 aarch64)
11229 16:49:33.953826 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.224152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11230 16:49:33.954090 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11232 16:49:33.957033 b/drmtest.c:621:
11233 16:49:33.960661 Test requireme<8>[ 21.234830] <LAVA_SIGNAL_TESTSET STOP>
11234 16:49:33.960961 Received signal: <TESTSET> STOP
11235 16:49:33.961073 Closing test_set panfrost_submit
11236 16:49:33.963844 nt: !(fd<0)
11237 16:49:33.970861 No <8>[ 21.240773] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10576298_1.5.2.3.1>
11238 16:49:33.971207 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10576298_1.5.2.3.1
11239 16:49:33.971330 Ending use of test pattern.
11240 16:49:33.971415 Ending test lava.0_igt-gpu-panfrost (10576298_1.5.2.3.1), duration 0.89
11242 16:49:33.974101 known gpu found for chipset flags 0x32 (panfrost)
11243 16:49:33.977059 Last errno: 2, No such file or directory
11244 16:49:33.983743 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11245 16:49:33.983879 + set +x
11246 16:49:33.987081 <LAVA_TEST_RUNNER EXIT>
11247 16:49:33.987485 ok: lava_test_shell seems to have completed
11248 16:49:33.988116 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11249 16:49:33.988309 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11250 16:49:33.988473 end: 3 lava-test-retry (duration 00:00:01) [common]
11251 16:49:33.988674 start: 4 finalize (timeout 00:07:14) [common]
11252 16:49:33.988835 start: 4.1 power-off (timeout 00:00:30) [common]
11253 16:49:33.989182 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11254 16:49:34.097289 >> Command sent successfully.
11255 16:49:34.100581 Returned 0 in 0 seconds
11256 16:49:34.201377 end: 4.1 power-off (duration 00:00:00) [common]
11258 16:49:34.202819 start: 4.2 read-feedback (timeout 00:07:14) [common]
11259 16:49:34.204318 Listened to connection for namespace 'common' for up to 1s
11260 16:49:35.204897 Finalising connection for namespace 'common'
11261 16:49:35.205704 Disconnecting from shell: Finalise
11262 16:49:35.206289 / #
11263 16:49:35.307485 end: 4.2 read-feedback (duration 00:00:01) [common]
11264 16:49:35.308166 end: 4 finalize (duration 00:00:01) [common]
11265 16:49:35.308808 Cleaning after the job
11266 16:49:35.309327 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/ramdisk
11267 16:49:35.337830 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/kernel
11268 16:49:35.351644 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/dtb
11269 16:49:35.351950 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576298/tftp-deploy-pqkgui2f/modules
11270 16:49:35.360328 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576298
11271 16:49:35.462375 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576298
11272 16:49:35.462551 Job finished correctly