Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 19
1 16:52:45.821895 lava-dispatcher, installed at version: 2023.03
2 16:52:45.822101 start: 0 validate
3 16:52:45.822234 Start time: 2023-06-03 16:52:45.822227+00:00 (UTC)
4 16:52:45.822359 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:52:45.822491 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 16:52:46.119009 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:52:46.119873 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:52:46.415088 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:52:46.415267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:52:46.704179 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:52:46.704390 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 16:52:46.992021 validate duration: 1.17
14 16:52:46.992296 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:52:46.992396 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:52:46.992487 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:52:46.992613 Not decompressing ramdisk as can be used compressed.
18 16:52:46.992704 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 16:52:46.992774 saving as /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/ramdisk/rootfs.cpio.gz
20 16:52:46.992836 total size: 43394293 (41MB)
21 16:52:46.993865 progress 0% (0MB)
22 16:52:47.005292 progress 5% (2MB)
23 16:52:47.016400 progress 10% (4MB)
24 16:52:47.027517 progress 15% (6MB)
25 16:52:47.038720 progress 20% (8MB)
26 16:52:47.049953 progress 25% (10MB)
27 16:52:47.061243 progress 30% (12MB)
28 16:52:47.072423 progress 35% (14MB)
29 16:52:47.083517 progress 40% (16MB)
30 16:52:47.094632 progress 45% (18MB)
31 16:52:47.106095 progress 50% (20MB)
32 16:52:47.117159 progress 55% (22MB)
33 16:52:47.128245 progress 60% (24MB)
34 16:52:47.139273 progress 65% (26MB)
35 16:52:47.150719 progress 70% (29MB)
36 16:52:47.161970 progress 75% (31MB)
37 16:52:47.172992 progress 80% (33MB)
38 16:52:47.184171 progress 85% (35MB)
39 16:52:47.195083 progress 90% (37MB)
40 16:52:47.206148 progress 95% (39MB)
41 16:52:47.217341 progress 100% (41MB)
42 16:52:47.217527 41MB downloaded in 0.22s (184.19MB/s)
43 16:52:47.217692 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:52:47.217941 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:52:47.218028 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:52:47.218112 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:52:47.218247 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 16:52:47.218320 saving as /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/kernel/Image
50 16:52:47.218383 total size: 45746688 (43MB)
51 16:52:47.218444 No compression specified
52 16:52:47.219552 progress 0% (0MB)
53 16:52:47.231496 progress 5% (2MB)
54 16:52:47.244326 progress 10% (4MB)
55 16:52:47.257986 progress 15% (6MB)
56 16:52:47.270531 progress 20% (8MB)
57 16:52:47.283408 progress 25% (10MB)
58 16:52:47.295978 progress 30% (13MB)
59 16:52:47.308254 progress 35% (15MB)
60 16:52:47.321251 progress 40% (17MB)
61 16:52:47.334410 progress 45% (19MB)
62 16:52:47.347002 progress 50% (21MB)
63 16:52:47.358646 progress 55% (24MB)
64 16:52:47.370648 progress 60% (26MB)
65 16:52:47.382591 progress 65% (28MB)
66 16:52:47.394546 progress 70% (30MB)
67 16:52:47.406442 progress 75% (32MB)
68 16:52:47.418341 progress 80% (34MB)
69 16:52:47.430119 progress 85% (37MB)
70 16:52:47.441960 progress 90% (39MB)
71 16:52:47.453684 progress 95% (41MB)
72 16:52:47.466271 progress 100% (43MB)
73 16:52:47.466467 43MB downloaded in 0.25s (175.86MB/s)
74 16:52:47.466702 end: 1.2.1 http-download (duration 00:00:00) [common]
76 16:52:47.466959 end: 1.2 download-retry (duration 00:00:00) [common]
77 16:52:47.467055 start: 1.3 download-retry (timeout 00:10:00) [common]
78 16:52:47.467141 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 16:52:47.467290 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 16:52:47.467389 saving as /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/dtb/mt8192-asurada-spherion-r0.dtb
81 16:52:47.467484 total size: 46924 (0MB)
82 16:52:47.467588 No compression specified
83 16:52:47.468890 progress 69% (0MB)
84 16:52:47.469214 progress 100% (0MB)
85 16:52:47.469405 0MB downloaded in 0.00s (23.33MB/s)
86 16:52:47.469546 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:52:47.469783 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:52:47.469887 start: 1.4 download-retry (timeout 00:10:00) [common]
90 16:52:47.470013 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 16:52:47.470165 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 16:52:47.470266 saving as /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/modules/modules.tar
93 16:52:47.470360 total size: 8545664 (8MB)
94 16:52:47.470456 Using unxz to decompress xz
95 16:52:47.474305 progress 0% (0MB)
96 16:52:47.496295 progress 5% (0MB)
97 16:52:47.521335 progress 10% (0MB)
98 16:52:47.547467 progress 15% (1MB)
99 16:52:47.572709 progress 20% (1MB)
100 16:52:47.598649 progress 25% (2MB)
101 16:52:47.623317 progress 30% (2MB)
102 16:52:47.648986 progress 35% (2MB)
103 16:52:47.674641 progress 40% (3MB)
104 16:52:47.700719 progress 45% (3MB)
105 16:52:47.725911 progress 50% (4MB)
106 16:52:47.750197 progress 55% (4MB)
107 16:52:47.775462 progress 60% (4MB)
108 16:52:47.800899 progress 65% (5MB)
109 16:52:47.826655 progress 70% (5MB)
110 16:52:47.853744 progress 75% (6MB)
111 16:52:47.883426 progress 80% (6MB)
112 16:52:47.906162 progress 85% (6MB)
113 16:52:47.931542 progress 90% (7MB)
114 16:52:47.955303 progress 95% (7MB)
115 16:52:47.979564 progress 100% (8MB)
116 16:52:47.985542 8MB downloaded in 0.52s (15.82MB/s)
117 16:52:47.985847 end: 1.4.1 http-download (duration 00:00:01) [common]
119 16:52:47.986127 end: 1.4 download-retry (duration 00:00:01) [common]
120 16:52:47.986238 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 16:52:47.986336 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 16:52:47.986435 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:52:47.986524 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 16:52:47.986762 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87
125 16:52:47.986902 makedir: /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin
126 16:52:47.987019 makedir: /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/tests
127 16:52:47.987126 makedir: /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/results
128 16:52:47.987244 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-add-keys
129 16:52:47.987402 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-add-sources
130 16:52:47.987542 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-background-process-start
131 16:52:47.987689 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-background-process-stop
132 16:52:47.987816 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-common-functions
133 16:52:47.987946 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-echo-ipv4
134 16:52:47.988080 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-install-packages
135 16:52:47.988203 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-installed-packages
136 16:52:47.988333 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-os-build
137 16:52:47.988462 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-probe-channel
138 16:52:47.988586 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-probe-ip
139 16:52:47.988714 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-target-ip
140 16:52:47.988849 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-target-mac
141 16:52:47.988970 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-target-storage
142 16:52:47.989103 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-case
143 16:52:47.989233 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-event
144 16:52:47.989362 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-feedback
145 16:52:47.989484 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-raise
146 16:52:47.989617 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-reference
147 16:52:47.989754 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-runner
148 16:52:47.989877 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-set
149 16:52:47.990009 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-test-shell
150 16:52:47.990141 Updating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-install-packages (oe)
151 16:52:47.990312 Updating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/bin/lava-installed-packages (oe)
152 16:52:47.990441 Creating /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/environment
153 16:52:47.990546 LAVA metadata
154 16:52:47.990644 - LAVA_JOB_ID=10576339
155 16:52:47.990719 - LAVA_DISPATCHER_IP=192.168.201.1
156 16:52:47.990826 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 16:52:47.990904 skipped lava-vland-overlay
158 16:52:47.990983 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 16:52:47.991080 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 16:52:47.991150 skipped lava-multinode-overlay
161 16:52:47.991229 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 16:52:47.991320 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 16:52:47.991409 Loading test definitions
164 16:52:47.991511 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 16:52:47.991594 Using /lava-10576339 at stage 0
166 16:52:47.991917 uuid=10576339_1.5.2.3.1 testdef=None
167 16:52:47.992021 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 16:52:47.992108 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 16:52:47.992658 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 16:52:47.992904 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 16:52:47.993556 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 16:52:47.993800 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 16:52:47.994448 runner path: /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/0/tests/0_igt-kms-mediatek test_uuid 10576339_1.5.2.3.1
176 16:52:47.994617 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 16:52:47.994834 Creating lava-test-runner.conf files
179 16:52:47.994899 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576339/lava-overlay-wgze4u87/lava-10576339/0 for stage 0
180 16:52:47.994988 - 0_igt-kms-mediatek
181 16:52:47.995100 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 16:52:47.995187 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 16:52:48.002254 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 16:52:48.002382 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 16:52:48.002477 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 16:52:48.002565 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 16:52:48.002652 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 16:52:49.369705 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 16:52:49.370101 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 16:52:49.370231 extracting modules file /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576339/extract-overlay-ramdisk-t_5su1fw/ramdisk
191 16:52:49.586245 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 16:52:49.586419 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 16:52:49.586518 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576339/compress-overlay-dxbm7dml/overlay-1.5.2.4.tar.gz to ramdisk
194 16:52:49.586591 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576339/compress-overlay-dxbm7dml/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576339/extract-overlay-ramdisk-t_5su1fw/ramdisk
195 16:52:49.593507 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 16:52:49.593652 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 16:52:49.593777 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 16:52:49.593904 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 16:52:49.594023 Building ramdisk /var/lib/lava/dispatcher/tmp/10576339/extract-overlay-ramdisk-t_5su1fw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576339/extract-overlay-ramdisk-t_5su1fw/ramdisk
200 16:52:50.737350 >> 369037 blocks
201 16:52:56.613107 rename /var/lib/lava/dispatcher/tmp/10576339/extract-overlay-ramdisk-t_5su1fw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/ramdisk/ramdisk.cpio.gz
202 16:52:56.613539 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 16:52:56.613664 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 16:52:56.613767 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 16:52:56.613870 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/kernel/Image'
206 16:53:08.293776 Returned 0 in 11 seconds
207 16:53:08.394726 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/kernel/image.itb
208 16:53:09.140701 output: FIT description: Kernel Image image with one or more FDT blobs
209 16:53:09.141062 output: Created: Sat Jun 3 17:53:08 2023
210 16:53:09.141134 output: Image 0 (kernel-1)
211 16:53:09.141199 output: Description:
212 16:53:09.141266 output: Created: Sat Jun 3 17:53:08 2023
213 16:53:09.141329 output: Type: Kernel Image
214 16:53:09.141391 output: Compression: lzma compressed
215 16:53:09.141452 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
216 16:53:09.141552 output: Architecture: AArch64
217 16:53:09.141623 output: OS: Linux
218 16:53:09.141692 output: Load Address: 0x00000000
219 16:53:09.141781 output: Entry Point: 0x00000000
220 16:53:09.141844 output: Hash algo: crc32
221 16:53:09.141902 output: Hash value: b48eba69
222 16:53:09.141957 output: Image 1 (fdt-1)
223 16:53:09.142011 output: Description: mt8192-asurada-spherion-r0
224 16:53:09.142065 output: Created: Sat Jun 3 17:53:08 2023
225 16:53:09.142119 output: Type: Flat Device Tree
226 16:53:09.142173 output: Compression: uncompressed
227 16:53:09.142226 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 16:53:09.142280 output: Architecture: AArch64
229 16:53:09.142333 output: Hash algo: crc32
230 16:53:09.142386 output: Hash value: 1df858fa
231 16:53:09.142452 output: Image 2 (ramdisk-1)
232 16:53:09.142506 output: Description: unavailable
233 16:53:09.142560 output: Created: Sat Jun 3 17:53:08 2023
234 16:53:09.142614 output: Type: RAMDisk Image
235 16:53:09.142668 output: Compression: Unknown Compression
236 16:53:09.142721 output: Data Size: 56352471 Bytes = 55031.71 KiB = 53.74 MiB
237 16:53:09.142775 output: Architecture: AArch64
238 16:53:09.142829 output: OS: Linux
239 16:53:09.142882 output: Load Address: unavailable
240 16:53:09.142936 output: Entry Point: unavailable
241 16:53:09.142990 output: Hash algo: crc32
242 16:53:09.143043 output: Hash value: 80a81c55
243 16:53:09.143096 output: Default Configuration: 'conf-1'
244 16:53:09.143149 output: Configuration 0 (conf-1)
245 16:53:09.143203 output: Description: mt8192-asurada-spherion-r0
246 16:53:09.143257 output: Kernel: kernel-1
247 16:53:09.143310 output: Init Ramdisk: ramdisk-1
248 16:53:09.143363 output: FDT: fdt-1
249 16:53:09.143416 output: Loadables: kernel-1
250 16:53:09.143469 output:
251 16:53:09.143702 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 16:53:09.143803 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 16:53:09.143907 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 16:53:09.143999 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 16:53:09.144078 No LXC device requested
256 16:53:09.144157 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 16:53:09.144241 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 16:53:09.144318 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 16:53:09.144389 Checking files for TFTP limit of 4294967296 bytes.
260 16:53:09.144892 end: 1 tftp-deploy (duration 00:00:22) [common]
261 16:53:09.144995 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 16:53:09.145086 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 16:53:09.145206 substitutions:
264 16:53:09.145273 - {DTB}: 10576339/tftp-deploy-7o0p90sc/dtb/mt8192-asurada-spherion-r0.dtb
265 16:53:09.145345 - {INITRD}: 10576339/tftp-deploy-7o0p90sc/ramdisk/ramdisk.cpio.gz
266 16:53:09.145404 - {KERNEL}: 10576339/tftp-deploy-7o0p90sc/kernel/Image
267 16:53:09.145463 - {LAVA_MAC}: None
268 16:53:09.145519 - {PRESEED_CONFIG}: None
269 16:53:09.145575 - {PRESEED_LOCAL}: None
270 16:53:09.145629 - {RAMDISK}: 10576339/tftp-deploy-7o0p90sc/ramdisk/ramdisk.cpio.gz
271 16:53:09.145685 - {ROOT_PART}: None
272 16:53:09.145739 - {ROOT}: None
273 16:53:09.145794 - {SERVER_IP}: 192.168.201.1
274 16:53:09.145848 - {TEE}: None
275 16:53:09.145903 Parsed boot commands:
276 16:53:09.145979 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 16:53:09.146160 Parsed boot commands: tftpboot 192.168.201.1 10576339/tftp-deploy-7o0p90sc/kernel/image.itb 10576339/tftp-deploy-7o0p90sc/kernel/cmdline
278 16:53:09.146253 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 16:53:09.146337 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 16:53:09.146433 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 16:53:09.146537 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 16:53:09.146612 Not connected, no need to disconnect.
283 16:53:09.146688 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 16:53:09.146770 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 16:53:09.146836 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 16:53:09.150252 Setting prompt string to ['lava-test: # ']
287 16:53:09.150586 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 16:53:09.150697 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 16:53:09.150795 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 16:53:09.150888 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 16:53:09.151087 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 16:53:14.298665 >> Command sent successfully.
293 16:53:14.308926 Returned 0 in 5 seconds
294 16:53:14.410138 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 16:53:14.412919 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 16:53:14.413635 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 16:53:14.414247 Setting prompt string to 'Starting depthcharge on Spherion...'
299 16:53:14.414776 Changing prompt to 'Starting depthcharge on Spherion...'
300 16:53:14.415162 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 16:53:14.416486 [Enter `^Ec?' for help]
302 16:53:14.572366
303 16:53:14.572900
304 16:53:14.573246 F0: 102B 0000
305 16:53:14.573576
306 16:53:14.574017 F3: 1001 0000 [0200]
307 16:53:14.574401
308 16:53:14.575822 F3: 1001 0000
309 16:53:14.576260
310 16:53:14.576609 F7: 102D 0000
311 16:53:14.577002
312 16:53:14.577349 F1: 0000 0000
313 16:53:14.580108
314 16:53:14.580539 V0: 0000 0000 [0001]
315 16:53:14.580894
316 16:53:14.581328 00: 0007 8000
317 16:53:14.581745
318 16:53:14.583846 01: 0000 0000
319 16:53:14.584290
320 16:53:14.584687 BP: 0C00 0209 [0000]
321 16:53:14.585189
322 16:53:14.585547 G0: 1182 0000
323 16:53:14.586937
324 16:53:14.587366 EC: 0000 0021 [4000]
325 16:53:14.587762
326 16:53:14.590988 S7: 0000 0000 [0000]
327 16:53:14.591424
328 16:53:14.591886 CC: 0000 0000 [0001]
329 16:53:14.592229
330 16:53:14.593737 T0: 0000 0040 [010F]
331 16:53:14.594202
332 16:53:14.594639 Jump to BL
333 16:53:14.594976
334 16:53:14.618860
335 16:53:14.619549
336 16:53:14.619986
337 16:53:14.626143 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 16:53:14.630019 ARM64: Exception handlers installed.
339 16:53:14.633702 ARM64: Testing exception
340 16:53:14.637700 ARM64: Done test exception
341 16:53:14.644442 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 16:53:14.655636 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 16:53:14.662265 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 16:53:14.672423 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 16:53:14.678706 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 16:53:14.684915 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 16:53:14.695836 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 16:53:14.702508 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 16:53:14.721954 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 16:53:14.725342 WDT: Last reset was cold boot
351 16:53:14.728524 SPI1(PAD0) initialized at 2873684 Hz
352 16:53:14.731868 SPI5(PAD0) initialized at 992727 Hz
353 16:53:14.735265 VBOOT: Loading verstage.
354 16:53:14.741606 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 16:53:14.745033 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 16:53:14.748472 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 16:53:14.751833 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 16:53:14.759328 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 16:53:14.766050 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 16:53:14.777086 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 16:53:14.777519
362 16:53:14.777861
363 16:53:14.786881 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 16:53:14.790063 ARM64: Exception handlers installed.
365 16:53:14.793776 ARM64: Testing exception
366 16:53:14.794206 ARM64: Done test exception
367 16:53:14.799919 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 16:53:14.803754 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 16:53:14.818028 Probing TPM: . done!
370 16:53:14.818566 TPM ready after 0 ms
371 16:53:14.824783 Connected to device vid:did:rid of 1ae0:0028:00
372 16:53:14.834601 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 16:53:14.875395 Initialized TPM device CR50 revision 0
374 16:53:14.886156 tlcl_send_startup: Startup return code is 0
375 16:53:14.886660 TPM: setup succeeded
376 16:53:14.897170 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 16:53:14.906256 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 16:53:14.917913 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 16:53:14.927224 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 16:53:14.930738 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 16:53:14.934531 in-header: 03 07 00 00 08 00 00 00
382 16:53:14.937952 in-data: aa e4 47 04 13 02 00 00
383 16:53:14.941068 Chrome EC: UHEPI supported
384 16:53:14.947928 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 16:53:14.951837 in-header: 03 9d 00 00 08 00 00 00
386 16:53:14.955349 in-data: 10 20 20 08 00 00 00 00
387 16:53:14.955834 Phase 1
388 16:53:14.959127 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 16:53:14.966260 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 16:53:14.973914 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 16:53:14.974358 Recovery requested (1009000e)
392 16:53:14.982225 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 16:53:14.987830 tlcl_extend: response is 0
394 16:53:14.995564 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 16:53:15.001020 tlcl_extend: response is 0
396 16:53:15.007704 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 16:53:15.028863 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
398 16:53:15.036246 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 16:53:15.036711
400 16:53:15.037059
401 16:53:15.043541 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 16:53:15.046819 ARM64: Exception handlers installed.
403 16:53:15.050824 ARM64: Testing exception
404 16:53:15.054035 ARM64: Done test exception
405 16:53:15.074257 pmic_efuse_setting: Set efuses in 11 msecs
406 16:53:15.077685 pmwrap_interface_init: Select PMIF_VLD_RDY
407 16:53:15.084695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 16:53:15.088491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 16:53:15.092096 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 16:53:15.095885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 16:53:15.103270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 16:53:15.106471 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 16:53:15.113638 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 16:53:15.116754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 16:53:15.120646 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 16:53:15.126724 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 16:53:15.130583 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 16:53:15.136773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 16:53:15.139971 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 16:53:15.147068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 16:53:15.153587 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 16:53:15.156568 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 16:53:15.163213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 16:53:15.170072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 16:53:15.173070 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 16:53:15.180505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 16:53:15.187621 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 16:53:15.190721 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 16:53:15.197454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 16:53:15.201553 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 16:53:15.208538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 16:53:15.215126 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 16:53:15.218081 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 16:53:15.221929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 16:53:15.228046 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 16:53:15.231808 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 16:53:15.239272 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 16:53:15.242401 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 16:53:15.246290 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 16:53:15.253277 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 16:53:15.257223 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 16:53:15.264912 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 16:53:15.268278 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 16:53:15.271269 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 16:53:15.277929 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 16:53:15.281516 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 16:53:15.284487 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 16:53:15.290992 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 16:53:15.294743 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 16:53:15.297698 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 16:53:15.304458 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 16:53:15.308086 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 16:53:15.310803 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 16:53:15.317999 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 16:53:15.321236 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 16:53:15.324250 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 16:53:15.327987 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 16:53:15.337889 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 16:53:15.344015 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 16:53:15.350732 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 16:53:15.357667 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 16:53:15.367655 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 16:53:15.371045 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 16:53:15.374411 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 16:53:15.380787 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 16:53:15.387619 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x20
467 16:53:15.390759 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 16:53:15.398309 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 16:53:15.401618 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 16:53:15.411070 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 16:53:15.414660 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 16:53:15.421131 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 16:53:15.424561 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 16:53:15.427710 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 16:53:15.430726 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 16:53:15.434257 ADC[4]: Raw value=897780 ID=7
477 16:53:15.437932 ADC[3]: Raw value=213070 ID=1
478 16:53:15.440956 RAM Code: 0x71
479 16:53:15.444038 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 16:53:15.447832 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 16:53:15.458244 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 16:53:15.465008 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 16:53:15.468163 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 16:53:15.471675 in-header: 03 07 00 00 08 00 00 00
485 16:53:15.474835 in-data: aa e4 47 04 13 02 00 00
486 16:53:15.478124 Chrome EC: UHEPI supported
487 16:53:15.481575 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 16:53:15.485812 in-header: 03 d5 00 00 08 00 00 00
489 16:53:15.489693 in-data: 98 20 60 08 00 00 00 00
490 16:53:15.492834 MRC: failed to locate region type 0.
491 16:53:15.500364 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 16:53:15.504078 DRAM-K: Running full calibration
493 16:53:15.510226 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 16:53:15.510823 header.status = 0x0
495 16:53:15.513779 header.version = 0x6 (expected: 0x6)
496 16:53:15.516988 header.size = 0xd00 (expected: 0xd00)
497 16:53:15.520105 header.flags = 0x0
498 16:53:15.527833 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 16:53:15.542903 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
500 16:53:15.549680 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 16:53:15.552874 dram_init: ddr_geometry: 2
502 16:53:15.556564 [EMI] MDL number = 2
503 16:53:15.557007 [EMI] Get MDL freq = 0
504 16:53:15.559664 dram_init: ddr_type: 0
505 16:53:15.560098 is_discrete_lpddr4: 1
506 16:53:15.562978 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 16:53:15.563403
508 16:53:15.563807
509 16:53:15.566085 [Bian_co] ETT version 0.0.0.1
510 16:53:15.573018 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 16:53:15.573552
512 16:53:15.576129 dramc_set_vcore_voltage set vcore to 650000
513 16:53:15.579244 Read voltage for 800, 4
514 16:53:15.579717 Vio18 = 0
515 16:53:15.580065 Vcore = 650000
516 16:53:15.583082 Vdram = 0
517 16:53:15.583544 Vddq = 0
518 16:53:15.584104 Vmddr = 0
519 16:53:15.585986 dram_init: config_dvfs: 1
520 16:53:15.589117 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 16:53:15.596060 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 16:53:15.599286 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 16:53:15.603164 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 16:53:15.606057 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 16:53:15.609696 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 16:53:15.612843 MEM_TYPE=3, freq_sel=18
527 16:53:15.616099 sv_algorithm_assistance_LP4_1600
528 16:53:15.619555 ============ PULL DRAM RESETB DOWN ============
529 16:53:15.626239 ========== PULL DRAM RESETB DOWN end =========
530 16:53:15.629317 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 16:53:15.632605 ===================================
532 16:53:15.635974 LPDDR4 DRAM CONFIGURATION
533 16:53:15.639132 ===================================
534 16:53:15.639569 EX_ROW_EN[0] = 0x0
535 16:53:15.642588 EX_ROW_EN[1] = 0x0
536 16:53:15.643022 LP4Y_EN = 0x0
537 16:53:15.645872 WORK_FSP = 0x0
538 16:53:15.646308 WL = 0x2
539 16:53:15.649454 RL = 0x2
540 16:53:15.649891 BL = 0x2
541 16:53:15.652960 RPST = 0x0
542 16:53:15.653395 RD_PRE = 0x0
543 16:53:15.655935 WR_PRE = 0x1
544 16:53:15.659129 WR_PST = 0x0
545 16:53:15.659686 DBI_WR = 0x0
546 16:53:15.662959 DBI_RD = 0x0
547 16:53:15.663393 OTF = 0x1
548 16:53:15.665906 ===================================
549 16:53:15.669041 ===================================
550 16:53:15.669476 ANA top config
551 16:53:15.672735 ===================================
552 16:53:15.676006 DLL_ASYNC_EN = 0
553 16:53:15.679064 ALL_SLAVE_EN = 1
554 16:53:15.682904 NEW_RANK_MODE = 1
555 16:53:15.685849 DLL_IDLE_MODE = 1
556 16:53:15.686394 LP45_APHY_COMB_EN = 1
557 16:53:15.689659 TX_ODT_DIS = 1
558 16:53:15.692666 NEW_8X_MODE = 1
559 16:53:15.696005 ===================================
560 16:53:15.699056 ===================================
561 16:53:15.702345 data_rate = 1600
562 16:53:15.705848 CKR = 1
563 16:53:15.706283 DQ_P2S_RATIO = 8
564 16:53:15.708888 ===================================
565 16:53:15.712532 CA_P2S_RATIO = 8
566 16:53:15.715626 DQ_CA_OPEN = 0
567 16:53:15.718733 DQ_SEMI_OPEN = 0
568 16:53:15.722459 CA_SEMI_OPEN = 0
569 16:53:15.725607 CA_FULL_RATE = 0
570 16:53:15.726043 DQ_CKDIV4_EN = 1
571 16:53:15.728881 CA_CKDIV4_EN = 1
572 16:53:15.732247 CA_PREDIV_EN = 0
573 16:53:15.735814 PH8_DLY = 0
574 16:53:15.738823 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 16:53:15.742334 DQ_AAMCK_DIV = 4
576 16:53:15.742768 CA_AAMCK_DIV = 4
577 16:53:15.745434 CA_ADMCK_DIV = 4
578 16:53:15.748610 DQ_TRACK_CA_EN = 0
579 16:53:15.752298 CA_PICK = 800
580 16:53:15.755211 CA_MCKIO = 800
581 16:53:15.758989 MCKIO_SEMI = 0
582 16:53:15.759558 PLL_FREQ = 3068
583 16:53:15.762588 DQ_UI_PI_RATIO = 32
584 16:53:15.766339 CA_UI_PI_RATIO = 0
585 16:53:15.769982 ===================================
586 16:53:15.773130 ===================================
587 16:53:15.776860 memory_type:LPDDR4
588 16:53:15.777302 GP_NUM : 10
589 16:53:15.780584 SRAM_EN : 1
590 16:53:15.781036 MD32_EN : 0
591 16:53:15.784312 ===================================
592 16:53:15.787868 [ANA_INIT] >>>>>>>>>>>>>>
593 16:53:15.791912 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 16:53:15.792374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 16:53:15.795074 ===================================
596 16:53:15.798919 data_rate = 1600,PCW = 0X7600
597 16:53:15.802786 ===================================
598 16:53:15.805784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 16:53:15.809625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 16:53:15.817315 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 16:53:15.821230 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 16:53:15.824984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 16:53:15.828923 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 16:53:15.832521 [ANA_INIT] flow start
605 16:53:15.833058 [ANA_INIT] PLL >>>>>>>>
606 16:53:15.836163 [ANA_INIT] PLL <<<<<<<<
607 16:53:15.839679 [ANA_INIT] MIDPI >>>>>>>>
608 16:53:15.840128 [ANA_INIT] MIDPI <<<<<<<<
609 16:53:15.843488 [ANA_INIT] DLL >>>>>>>>
610 16:53:15.843966 [ANA_INIT] flow end
611 16:53:15.846895 ============ LP4 DIFF to SE enter ============
612 16:53:15.853913 ============ LP4 DIFF to SE exit ============
613 16:53:15.854347 [ANA_INIT] <<<<<<<<<<<<<
614 16:53:15.857579 [Flow] Enable top DCM control >>>>>
615 16:53:15.861272 [Flow] Enable top DCM control <<<<<
616 16:53:15.865163 Enable DLL master slave shuffle
617 16:53:15.868637 ==============================================================
618 16:53:15.872898 Gating Mode config
619 16:53:15.876429 ==============================================================
620 16:53:15.879718 Config description:
621 16:53:15.887365 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 16:53:15.895270 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 16:53:15.901457 SELPH_MODE 0: By rank 1: By Phase
624 16:53:15.904530 ==============================================================
625 16:53:15.907733 GAT_TRACK_EN = 1
626 16:53:15.911606 RX_GATING_MODE = 2
627 16:53:15.914493 RX_GATING_TRACK_MODE = 2
628 16:53:15.918099 SELPH_MODE = 1
629 16:53:15.921737 PICG_EARLY_EN = 1
630 16:53:15.924263 VALID_LAT_VALUE = 1
631 16:53:15.927945 ==============================================================
632 16:53:15.930977 Enter into Gating configuration >>>>
633 16:53:15.934101 Exit from Gating configuration <<<<
634 16:53:15.937888 Enter into DVFS_PRE_config >>>>>
635 16:53:15.951294 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 16:53:15.954600 Exit from DVFS_PRE_config <<<<<
637 16:53:15.958149 Enter into PICG configuration >>>>
638 16:53:15.958609 Exit from PICG configuration <<<<
639 16:53:15.961214 [RX_INPUT] configuration >>>>>
640 16:53:15.964567 [RX_INPUT] configuration <<<<<
641 16:53:15.970958 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 16:53:15.974522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 16:53:15.980830 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 16:53:15.987833 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 16:53:15.994097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 16:53:16.000829 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 16:53:16.004018 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 16:53:16.007109 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 16:53:16.010949 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 16:53:16.017275 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 16:53:16.020893 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 16:53:16.024515 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 16:53:16.028284 ===================================
654 16:53:16.031692 LPDDR4 DRAM CONFIGURATION
655 16:53:16.035223 ===================================
656 16:53:16.035821 EX_ROW_EN[0] = 0x0
657 16:53:16.038562 EX_ROW_EN[1] = 0x0
658 16:53:16.038997 LP4Y_EN = 0x0
659 16:53:16.042402 WORK_FSP = 0x0
660 16:53:16.042845 WL = 0x2
661 16:53:16.045661 RL = 0x2
662 16:53:16.046097 BL = 0x2
663 16:53:16.049853 RPST = 0x0
664 16:53:16.050291 RD_PRE = 0x0
665 16:53:16.053450 WR_PRE = 0x1
666 16:53:16.053886 WR_PST = 0x0
667 16:53:16.057114 DBI_WR = 0x0
668 16:53:16.057549 DBI_RD = 0x0
669 16:53:16.060349 OTF = 0x1
670 16:53:16.060798 ===================================
671 16:53:16.064207 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 16:53:16.071241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 16:53:16.075185 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 16:53:16.078892 ===================================
675 16:53:16.079341 LPDDR4 DRAM CONFIGURATION
676 16:53:16.082466 ===================================
677 16:53:16.085939 EX_ROW_EN[0] = 0x10
678 16:53:16.086513 EX_ROW_EN[1] = 0x0
679 16:53:16.089215 LP4Y_EN = 0x0
680 16:53:16.089303 WORK_FSP = 0x0
681 16:53:16.093034 WL = 0x2
682 16:53:16.093121 RL = 0x2
683 16:53:16.096638 BL = 0x2
684 16:53:16.096725 RPST = 0x0
685 16:53:16.100325 RD_PRE = 0x0
686 16:53:16.100412 WR_PRE = 0x1
687 16:53:16.103879 WR_PST = 0x0
688 16:53:16.103965 DBI_WR = 0x0
689 16:53:16.107170 DBI_RD = 0x0
690 16:53:16.107258 OTF = 0x1
691 16:53:16.110818 ===================================
692 16:53:16.117797 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 16:53:16.121534 nWR fixed to 40
694 16:53:16.125318 [ModeRegInit_LP4] CH0 RK0
695 16:53:16.125404 [ModeRegInit_LP4] CH0 RK1
696 16:53:16.128980 [ModeRegInit_LP4] CH1 RK0
697 16:53:16.129098 [ModeRegInit_LP4] CH1 RK1
698 16:53:16.132869 match AC timing 13
699 16:53:16.136592 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 16:53:16.139420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 16:53:16.147200 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 16:53:16.150909 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 16:53:16.154731 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 16:53:16.154814 [EMI DOE] emi_dcm 0
705 16:53:16.161939 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 16:53:16.162022 ==
707 16:53:16.165774 Dram Type= 6, Freq= 0, CH_0, rank 0
708 16:53:16.169327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 16:53:16.169411 ==
710 16:53:16.172825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 16:53:16.179572 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 16:53:16.188894 [CA 0] Center 38 (7~69) winsize 63
713 16:53:16.192576 [CA 1] Center 38 (7~69) winsize 63
714 16:53:16.195583 [CA 2] Center 35 (5~66) winsize 62
715 16:53:16.199381 [CA 3] Center 35 (5~66) winsize 62
716 16:53:16.203178 [CA 4] Center 34 (4~65) winsize 62
717 16:53:16.206735 [CA 5] Center 34 (4~64) winsize 61
718 16:53:16.206818
719 16:53:16.210411 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 16:53:16.210494
721 16:53:16.213691 [CATrainingPosCal] consider 1 rank data
722 16:53:16.217417 u2DelayCellTimex100 = 270/100 ps
723 16:53:16.220444 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 16:53:16.224168 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
725 16:53:16.227892 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 16:53:16.231602 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 16:53:16.235413 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 16:53:16.239092 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
729 16:53:16.239178
730 16:53:16.242932 CA PerBit enable=1, Macro0, CA PI delay=34
731 16:53:16.243052
732 16:53:16.246883 [CBTSetCACLKResult] CA Dly = 34
733 16:53:16.247319 CS Dly: 6 (0~37)
734 16:53:16.247698 ==
735 16:53:16.250772 Dram Type= 6, Freq= 0, CH_0, rank 1
736 16:53:16.254288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 16:53:16.254770 ==
738 16:53:16.261531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 16:53:16.265370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 16:53:16.275551 [CA 0] Center 38 (7~69) winsize 63
741 16:53:16.279151 [CA 1] Center 38 (7~69) winsize 63
742 16:53:16.283264 [CA 2] Center 35 (5~66) winsize 62
743 16:53:16.287222 [CA 3] Center 35 (5~66) winsize 62
744 16:53:16.290522 [CA 4] Center 34 (4~65) winsize 62
745 16:53:16.294232 [CA 5] Center 34 (4~64) winsize 61
746 16:53:16.294721
747 16:53:16.298186 [CmdBusTrainingLP45] Vref(ca) range 1: 30
748 16:53:16.298626
749 16:53:16.301693 [CATrainingPosCal] consider 2 rank data
750 16:53:16.302129 u2DelayCellTimex100 = 270/100 ps
751 16:53:16.305162 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 16:53:16.308873 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
753 16:53:16.312341 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 16:53:16.316074 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 16:53:16.319370 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 16:53:16.323163 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
757 16:53:16.323731
758 16:53:16.329998 CA PerBit enable=1, Macro0, CA PI delay=34
759 16:53:16.330528
760 16:53:16.333472 [CBTSetCACLKResult] CA Dly = 34
761 16:53:16.333917 CS Dly: 6 (0~38)
762 16:53:16.334257
763 16:53:16.336344 ----->DramcWriteLeveling(PI) begin...
764 16:53:16.336792 ==
765 16:53:16.340159 Dram Type= 6, Freq= 0, CH_0, rank 0
766 16:53:16.343302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 16:53:16.343773 ==
768 16:53:16.346480 Write leveling (Byte 0): 33 => 33
769 16:53:16.349600 Write leveling (Byte 1): 30 => 30
770 16:53:16.352863 DramcWriteLeveling(PI) end<-----
771 16:53:16.353294
772 16:53:16.353635 ==
773 16:53:16.356715 Dram Type= 6, Freq= 0, CH_0, rank 0
774 16:53:16.363162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 16:53:16.363635 ==
776 16:53:16.363993 [Gating] SW mode calibration
777 16:53:16.372945 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 16:53:16.376132 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 16:53:16.379527 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 16:53:16.386239 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 16:53:16.389722 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
782 16:53:16.392638 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
783 16:53:16.399733 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 16:53:16.402796 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 16:53:16.406221 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 16:53:16.413393 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 16:53:16.417328 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 16:53:16.420638 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 16:53:16.424433 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 16:53:16.427852 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 16:53:16.434745 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 16:53:16.437990 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 16:53:16.441058 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 16:53:16.448352 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 16:53:16.451461 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 16:53:16.455135 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 16:53:16.461322 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
798 16:53:16.464806 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
799 16:53:16.468487 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 16:53:16.474704 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 16:53:16.478418 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 16:53:16.481770 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 16:53:16.488219 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 16:53:16.491344 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 16:53:16.494893 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
806 16:53:16.497898 0 9 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
807 16:53:16.504849 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 16:53:16.508005 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 16:53:16.511788 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 16:53:16.518306 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 16:53:16.521313 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 16:53:16.524874 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 16:53:16.531703 0 10 8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
814 16:53:16.534743 0 10 12 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
815 16:53:16.538048 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 16:53:16.544982 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 16:53:16.548546 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 16:53:16.551780 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 16:53:16.558006 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 16:53:16.561661 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 16:53:16.564986 0 11 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
822 16:53:16.571325 0 11 12 | B1->B0 | 3c3c 4444 | 1 0 | (0 0) (0 0)
823 16:53:16.574482 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 16:53:16.578046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 16:53:16.584701 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 16:53:16.587817 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 16:53:16.590983 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 16:53:16.598256 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 16:53:16.601405 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 16:53:16.604342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 16:53:16.611851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 16:53:16.614438 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 16:53:16.617911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 16:53:16.620780 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 16:53:16.627413 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 16:53:16.631059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 16:53:16.634100 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 16:53:16.641157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 16:53:16.644241 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 16:53:16.647462 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 16:53:16.654161 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 16:53:16.657983 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 16:53:16.661121 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 16:53:16.667930 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 16:53:16.671353 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
846 16:53:16.674378 Total UI for P1: 0, mck2ui 16
847 16:53:16.677421 best dqsien dly found for B0: ( 0, 14, 6)
848 16:53:16.681193 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
849 16:53:16.687654 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 16:53:16.688254 Total UI for P1: 0, mck2ui 16
851 16:53:16.694557 best dqsien dly found for B1: ( 0, 14, 10)
852 16:53:16.697842 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
853 16:53:16.700796 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
854 16:53:16.701289
855 16:53:16.704468 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
856 16:53:16.707669 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
857 16:53:16.710837 [Gating] SW calibration Done
858 16:53:16.711355 ==
859 16:53:16.714028 Dram Type= 6, Freq= 0, CH_0, rank 0
860 16:53:16.717654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 16:53:16.718189 ==
862 16:53:16.720878 RX Vref Scan: 0
863 16:53:16.721311
864 16:53:16.721658 RX Vref 0 -> 0, step: 1
865 16:53:16.721981
866 16:53:16.724219 RX Delay -130 -> 252, step: 16
867 16:53:16.727236 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 16:53:16.733930 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
869 16:53:16.737505 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 16:53:16.740467 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 16:53:16.744238 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
872 16:53:16.747254 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 16:53:16.754014 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 16:53:16.757100 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 16:53:16.760779 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 16:53:16.763837 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 16:53:16.766950 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 16:53:16.773799 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 16:53:16.777655 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 16:53:16.780803 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 16:53:16.783716 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 16:53:16.790498 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 16:53:16.790987 ==
884 16:53:16.793662 Dram Type= 6, Freq= 0, CH_0, rank 0
885 16:53:16.796893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 16:53:16.797497 ==
887 16:53:16.797893 DQS Delay:
888 16:53:16.800038 DQS0 = 0, DQS1 = 0
889 16:53:16.800648 DQM Delay:
890 16:53:16.803670 DQM0 = 79, DQM1 = 69
891 16:53:16.804086 DQ Delay:
892 16:53:16.806814 DQ0 =77, DQ1 =77, DQ2 =77, DQ3 =77
893 16:53:16.810561 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
894 16:53:16.813805 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 16:53:16.817067 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 16:53:16.817625
897 16:53:16.818037
898 16:53:16.818360 ==
899 16:53:16.820466 Dram Type= 6, Freq= 0, CH_0, rank 0
900 16:53:16.823899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 16:53:16.824385 ==
902 16:53:16.824728
903 16:53:16.825048
904 16:53:16.827504 TX Vref Scan disable
905 16:53:16.831131 == TX Byte 0 ==
906 16:53:16.834176 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
907 16:53:16.837812 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
908 16:53:16.840887 == TX Byte 1 ==
909 16:53:16.844372 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
910 16:53:16.847749 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
911 16:53:16.848261 ==
912 16:53:16.851136 Dram Type= 6, Freq= 0, CH_0, rank 0
913 16:53:16.854211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 16:53:16.854637 ==
915 16:53:16.868585 TX Vref=22, minBit 0, minWin=27, winSum=435
916 16:53:16.872184 TX Vref=24, minBit 11, minWin=25, winSum=435
917 16:53:16.875521 TX Vref=26, minBit 7, minWin=27, winSum=443
918 16:53:16.878708 TX Vref=28, minBit 4, minWin=27, winSum=441
919 16:53:16.881727 TX Vref=30, minBit 5, minWin=27, winSum=443
920 16:53:16.888848 TX Vref=32, minBit 10, minWin=26, winSum=436
921 16:53:16.892039 [TxChooseVref] Worse bit 7, Min win 27, Win sum 443, Final Vref 26
922 16:53:16.892548
923 16:53:16.895266 Final TX Range 1 Vref 26
924 16:53:16.895731
925 16:53:16.896159 ==
926 16:53:16.898974 Dram Type= 6, Freq= 0, CH_0, rank 0
927 16:53:16.901817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 16:53:16.905385 ==
929 16:53:16.905832
930 16:53:16.906256
931 16:53:16.906597 TX Vref Scan disable
932 16:53:16.908968 == TX Byte 0 ==
933 16:53:16.911994 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
934 16:53:16.915541 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
935 16:53:16.918639 == TX Byte 1 ==
936 16:53:16.921829 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
937 16:53:16.928427 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
938 16:53:16.928995
939 16:53:16.929510 [DATLAT]
940 16:53:16.930009 Freq=800, CH0 RK0
941 16:53:16.930487
942 16:53:16.931936 DATLAT Default: 0xa
943 16:53:16.932500 0, 0xFFFF, sum = 0
944 16:53:16.935616 1, 0xFFFF, sum = 0
945 16:53:16.936263 2, 0xFFFF, sum = 0
946 16:53:16.938533 3, 0xFFFF, sum = 0
947 16:53:16.941747 4, 0xFFFF, sum = 0
948 16:53:16.942367 5, 0xFFFF, sum = 0
949 16:53:16.945553 6, 0xFFFF, sum = 0
950 16:53:16.946035 7, 0xFFFF, sum = 0
951 16:53:16.949248 8, 0xFFFF, sum = 0
952 16:53:16.949742 9, 0x0, sum = 1
953 16:53:16.950295 10, 0x0, sum = 2
954 16:53:16.952055 11, 0x0, sum = 3
955 16:53:16.952676 12, 0x0, sum = 4
956 16:53:16.955124 best_step = 10
957 16:53:16.955568
958 16:53:16.956049 ==
959 16:53:16.958511 Dram Type= 6, Freq= 0, CH_0, rank 0
960 16:53:16.962248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 16:53:16.962825 ==
962 16:53:16.965071 RX Vref Scan: 1
963 16:53:16.965514
964 16:53:16.965955 Set Vref Range= 32 -> 127
965 16:53:16.968717
966 16:53:16.969156 RX Vref 32 -> 127, step: 1
967 16:53:16.969603
968 16:53:16.972165 RX Delay -111 -> 252, step: 8
969 16:53:16.972609
970 16:53:16.975104 Set Vref, RX VrefLevel [Byte0]: 32
971 16:53:16.978745 [Byte1]: 32
972 16:53:16.979190
973 16:53:16.982337 Set Vref, RX VrefLevel [Byte0]: 33
974 16:53:16.985310 [Byte1]: 33
975 16:53:16.989169
976 16:53:16.989591 Set Vref, RX VrefLevel [Byte0]: 34
977 16:53:16.992350 [Byte1]: 34
978 16:53:16.996917
979 16:53:16.997336 Set Vref, RX VrefLevel [Byte0]: 35
980 16:53:17.000723 [Byte1]: 35
981 16:53:17.004424
982 16:53:17.004855 Set Vref, RX VrefLevel [Byte0]: 36
983 16:53:17.007951 [Byte1]: 36
984 16:53:17.012171
985 16:53:17.012608 Set Vref, RX VrefLevel [Byte0]: 37
986 16:53:17.015608 [Byte1]: 37
987 16:53:17.020054
988 16:53:17.020475 Set Vref, RX VrefLevel [Byte0]: 38
989 16:53:17.023130 [Byte1]: 38
990 16:53:17.027460
991 16:53:17.028049 Set Vref, RX VrefLevel [Byte0]: 39
992 16:53:17.030771 [Byte1]: 39
993 16:53:17.035111
994 16:53:17.035575 Set Vref, RX VrefLevel [Byte0]: 40
995 16:53:17.038615 [Byte1]: 40
996 16:53:17.042968
997 16:53:17.043525 Set Vref, RX VrefLevel [Byte0]: 41
998 16:53:17.046571 [Byte1]: 41
999 16:53:17.050468
1000 16:53:17.050961 Set Vref, RX VrefLevel [Byte0]: 42
1001 16:53:17.054224 [Byte1]: 42
1002 16:53:17.058375
1003 16:53:17.058999 Set Vref, RX VrefLevel [Byte0]: 43
1004 16:53:17.061266 [Byte1]: 43
1005 16:53:17.066262
1006 16:53:17.066764 Set Vref, RX VrefLevel [Byte0]: 44
1007 16:53:17.072572 [Byte1]: 44
1008 16:53:17.072999
1009 16:53:17.076183 Set Vref, RX VrefLevel [Byte0]: 45
1010 16:53:17.079546 [Byte1]: 45
1011 16:53:17.079998
1012 16:53:17.083179 Set Vref, RX VrefLevel [Byte0]: 46
1013 16:53:17.086217 [Byte1]: 46
1014 16:53:17.086646
1015 16:53:17.089957 Set Vref, RX VrefLevel [Byte0]: 47
1016 16:53:17.093656 [Byte1]: 47
1017 16:53:17.094089
1018 16:53:17.097550 Set Vref, RX VrefLevel [Byte0]: 48
1019 16:53:17.100652 [Byte1]: 48
1020 16:53:17.104504
1021 16:53:17.104927 Set Vref, RX VrefLevel [Byte0]: 49
1022 16:53:17.107665 [Byte1]: 49
1023 16:53:17.112151
1024 16:53:17.112632 Set Vref, RX VrefLevel [Byte0]: 50
1025 16:53:17.115166 [Byte1]: 50
1026 16:53:17.119386
1027 16:53:17.119856 Set Vref, RX VrefLevel [Byte0]: 51
1028 16:53:17.122498 [Byte1]: 51
1029 16:53:17.127040
1030 16:53:17.127464 Set Vref, RX VrefLevel [Byte0]: 52
1031 16:53:17.130315 [Byte1]: 52
1032 16:53:17.134534
1033 16:53:17.134961 Set Vref, RX VrefLevel [Byte0]: 53
1034 16:53:17.137652 [Byte1]: 53
1035 16:53:17.142478
1036 16:53:17.142905 Set Vref, RX VrefLevel [Byte0]: 54
1037 16:53:17.145562 [Byte1]: 54
1038 16:53:17.149754
1039 16:53:17.150175 Set Vref, RX VrefLevel [Byte0]: 55
1040 16:53:17.152912 [Byte1]: 55
1041 16:53:17.157423
1042 16:53:17.157962 Set Vref, RX VrefLevel [Byte0]: 56
1043 16:53:17.160893 [Byte1]: 56
1044 16:53:17.164947
1045 16:53:17.165546 Set Vref, RX VrefLevel [Byte0]: 57
1046 16:53:17.168806 [Byte1]: 57
1047 16:53:17.173098
1048 16:53:17.173522 Set Vref, RX VrefLevel [Byte0]: 58
1049 16:53:17.176297 [Byte1]: 58
1050 16:53:17.180564
1051 16:53:17.180984 Set Vref, RX VrefLevel [Byte0]: 59
1052 16:53:17.183647 [Byte1]: 59
1053 16:53:17.187760
1054 16:53:17.188205 Set Vref, RX VrefLevel [Byte0]: 60
1055 16:53:17.191493 [Byte1]: 60
1056 16:53:17.195865
1057 16:53:17.196284 Set Vref, RX VrefLevel [Byte0]: 61
1058 16:53:17.199187 [Byte1]: 61
1059 16:53:17.203309
1060 16:53:17.203801 Set Vref, RX VrefLevel [Byte0]: 62
1061 16:53:17.206481 [Byte1]: 62
1062 16:53:17.210928
1063 16:53:17.211349 Set Vref, RX VrefLevel [Byte0]: 63
1064 16:53:17.214170 [Byte1]: 63
1065 16:53:17.219065
1066 16:53:17.219523 Set Vref, RX VrefLevel [Byte0]: 64
1067 16:53:17.222024 [Byte1]: 64
1068 16:53:17.226340
1069 16:53:17.226786 Set Vref, RX VrefLevel [Byte0]: 65
1070 16:53:17.229827 [Byte1]: 65
1071 16:53:17.233823
1072 16:53:17.234244 Set Vref, RX VrefLevel [Byte0]: 66
1073 16:53:17.237311 [Byte1]: 66
1074 16:53:17.241737
1075 16:53:17.242159 Set Vref, RX VrefLevel [Byte0]: 67
1076 16:53:17.245323 [Byte1]: 67
1077 16:53:17.249963
1078 16:53:17.250485 Set Vref, RX VrefLevel [Byte0]: 68
1079 16:53:17.253254 [Byte1]: 68
1080 16:53:17.257331
1081 16:53:17.257772 Set Vref, RX VrefLevel [Byte0]: 69
1082 16:53:17.260560 [Byte1]: 69
1083 16:53:17.264798
1084 16:53:17.265303 Set Vref, RX VrefLevel [Byte0]: 70
1085 16:53:17.271422 [Byte1]: 70
1086 16:53:17.272085
1087 16:53:17.274615 Set Vref, RX VrefLevel [Byte0]: 71
1088 16:53:17.278134 [Byte1]: 71
1089 16:53:17.278802
1090 16:53:17.281149 Set Vref, RX VrefLevel [Byte0]: 72
1091 16:53:17.284376 [Byte1]: 72
1092 16:53:17.287536
1093 16:53:17.287996 Set Vref, RX VrefLevel [Byte0]: 73
1094 16:53:17.290781 [Byte1]: 73
1095 16:53:17.295271
1096 16:53:17.295736 Set Vref, RX VrefLevel [Byte0]: 74
1097 16:53:17.299333 [Byte1]: 74
1098 16:53:17.302630
1099 16:53:17.303053 Set Vref, RX VrefLevel [Byte0]: 75
1100 16:53:17.305870 [Byte1]: 75
1101 16:53:17.311020
1102 16:53:17.311439 Set Vref, RX VrefLevel [Byte0]: 76
1103 16:53:17.313907 [Byte1]: 76
1104 16:53:17.317945
1105 16:53:17.318382 Set Vref, RX VrefLevel [Byte0]: 77
1106 16:53:17.321769 [Byte1]: 77
1107 16:53:17.325964
1108 16:53:17.326512 Set Vref, RX VrefLevel [Byte0]: 78
1109 16:53:17.329212 [Byte1]: 78
1110 16:53:17.333504
1111 16:53:17.333933 Final RX Vref Byte 0 = 54 to rank0
1112 16:53:17.336436 Final RX Vref Byte 1 = 62 to rank0
1113 16:53:17.340129 Final RX Vref Byte 0 = 54 to rank1
1114 16:53:17.343217 Final RX Vref Byte 1 = 62 to rank1==
1115 16:53:17.346566 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 16:53:17.352958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 16:53:17.353428 ==
1118 16:53:17.353804 DQS Delay:
1119 16:53:17.356840 DQS0 = 0, DQS1 = 0
1120 16:53:17.357291 DQM Delay:
1121 16:53:17.357633 DQM0 = 82, DQM1 = 68
1122 16:53:17.359940 DQ Delay:
1123 16:53:17.363284 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1124 16:53:17.366702 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1125 16:53:17.369549 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1126 16:53:17.373351 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1127 16:53:17.373778
1128 16:53:17.374117
1129 16:53:17.380079 [DQSOSCAuto] RK0, (LSB)MR18= 0x2423, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1130 16:53:17.382806 CH0 RK0: MR19=606, MR18=2423
1131 16:53:17.389749 CH0_RK0: MR19=0x606, MR18=0x2423, DQSOSC=400, MR23=63, INC=92, DEC=61
1132 16:53:17.390199
1133 16:53:17.392565 ----->DramcWriteLeveling(PI) begin...
1134 16:53:17.393039 ==
1135 16:53:17.396104 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 16:53:17.399324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 16:53:17.399797 ==
1138 16:53:17.403079 Write leveling (Byte 0): 31 => 31
1139 16:53:17.405979 Write leveling (Byte 1): 32 => 32
1140 16:53:17.409129 DramcWriteLeveling(PI) end<-----
1141 16:53:17.409592
1142 16:53:17.409947 ==
1143 16:53:17.412930 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 16:53:17.416197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 16:53:17.416631 ==
1146 16:53:17.419293 [Gating] SW mode calibration
1147 16:53:17.425771 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 16:53:17.432475 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 16:53:17.435766 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 16:53:17.442592 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 16:53:17.446128 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 16:53:17.449071 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1153 16:53:17.455725 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 16:53:17.459490 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 16:53:17.462438 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 16:53:17.468872 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 16:53:17.472613 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 16:53:17.475849 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 16:53:17.482181 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 16:53:17.486210 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 16:53:17.489224 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 16:53:17.492156 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 16:53:17.539491 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 16:53:17.540070 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 16:53:17.540413 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 16:53:17.540728 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1167 16:53:17.541349 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 16:53:17.541674 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 16:53:17.541988 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 16:53:17.542290 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 16:53:17.542577 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 16:53:17.542863 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 16:53:17.543668 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 16:53:17.547726 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 16:53:17.550717 0 9 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1176 16:53:17.554370 0 9 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
1177 16:53:17.560441 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 16:53:17.563848 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 16:53:17.567524 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 16:53:17.573469 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 16:53:17.576752 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 16:53:17.583743 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1183 16:53:17.586944 0 10 8 | B1->B0 | 3131 2626 | 0 1 | (0 1) (1 0)
1184 16:53:17.589892 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1185 16:53:17.596380 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 16:53:17.600182 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 16:53:17.603368 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 16:53:17.606361 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 16:53:17.613574 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 16:53:17.616526 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 16:53:17.619723 0 11 8 | B1->B0 | 2f2f 3838 | 0 0 | (1 1) (0 0)
1192 16:53:17.627051 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1193 16:53:17.629971 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 16:53:17.632917 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 16:53:17.639686 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 16:53:17.642996 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 16:53:17.646680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 16:53:17.653296 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 16:53:17.656891 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1200 16:53:17.660043 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1201 16:53:17.663476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 16:53:17.670069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 16:53:17.673861 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 16:53:17.677357 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 16:53:17.684026 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 16:53:17.687697 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 16:53:17.690929 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 16:53:17.697713 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 16:53:17.700809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 16:53:17.704540 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 16:53:17.710922 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 16:53:17.714263 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 16:53:17.717287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 16:53:17.724185 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 16:53:17.727383 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 16:53:17.730440 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 16:53:17.734016 Total UI for P1: 0, mck2ui 16
1218 16:53:17.737841 best dqsien dly found for B0: ( 0, 14, 8)
1219 16:53:17.740622 Total UI for P1: 0, mck2ui 16
1220 16:53:17.743604 best dqsien dly found for B1: ( 0, 14, 10)
1221 16:53:17.747296 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1222 16:53:17.750395 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1223 16:53:17.750817
1224 16:53:17.754419 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 16:53:17.760870 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1226 16:53:17.761408 [Gating] SW calibration Done
1227 16:53:17.761774 ==
1228 16:53:17.763652 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 16:53:17.770710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 16:53:17.771224 ==
1231 16:53:17.771565 RX Vref Scan: 0
1232 16:53:17.771938
1233 16:53:17.773953 RX Vref 0 -> 0, step: 1
1234 16:53:17.774478
1235 16:53:17.777706 RX Delay -130 -> 252, step: 16
1236 16:53:17.780234 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1237 16:53:17.784096 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1238 16:53:17.787288 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1239 16:53:17.793912 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1240 16:53:17.797029 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1241 16:53:17.800327 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1242 16:53:17.803735 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1243 16:53:17.806903 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1244 16:53:17.813344 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1245 16:53:17.816717 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1246 16:53:17.820054 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1247 16:53:17.824237 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1248 16:53:17.827044 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1249 16:53:17.833694 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1250 16:53:17.837094 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1251 16:53:17.840227 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1252 16:53:17.840835 ==
1253 16:53:17.843320 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 16:53:17.846734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 16:53:17.847259 ==
1256 16:53:17.850285 DQS Delay:
1257 16:53:17.850703 DQS0 = 0, DQS1 = 0
1258 16:53:17.853072 DQM Delay:
1259 16:53:17.853490 DQM0 = 82, DQM1 = 73
1260 16:53:17.857273 DQ Delay:
1261 16:53:17.857822 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1262 16:53:17.860215 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
1263 16:53:17.863342 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1264 16:53:17.866610 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1265 16:53:17.867213
1266 16:53:17.870188
1267 16:53:17.870605 ==
1268 16:53:17.873717 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 16:53:17.876392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 16:53:17.876815 ==
1271 16:53:17.877146
1272 16:53:17.877452
1273 16:53:17.879616 TX Vref Scan disable
1274 16:53:17.880040 == TX Byte 0 ==
1275 16:53:17.886304 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1276 16:53:17.889860 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1277 16:53:17.890278 == TX Byte 1 ==
1278 16:53:17.896396 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1279 16:53:17.899980 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1280 16:53:17.900521 ==
1281 16:53:17.902938 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 16:53:17.906675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 16:53:17.907100 ==
1284 16:53:17.919632 TX Vref=22, minBit 13, minWin=26, winSum=433
1285 16:53:17.923042 TX Vref=24, minBit 11, minWin=26, winSum=437
1286 16:53:17.926564 TX Vref=26, minBit 1, minWin=27, winSum=445
1287 16:53:17.929494 TX Vref=28, minBit 1, minWin=27, winSum=443
1288 16:53:17.932694 TX Vref=30, minBit 1, minWin=27, winSum=441
1289 16:53:17.939473 TX Vref=32, minBit 9, minWin=26, winSum=441
1290 16:53:17.942929 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 26
1291 16:53:17.943351
1292 16:53:17.945833 Final TX Range 1 Vref 26
1293 16:53:17.946241
1294 16:53:17.946561 ==
1295 16:53:17.949563 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 16:53:17.952629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 16:53:17.956302 ==
1298 16:53:17.956723
1299 16:53:17.957239
1300 16:53:17.957575 TX Vref Scan disable
1301 16:53:17.959680 == TX Byte 0 ==
1302 16:53:17.962948 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1303 16:53:17.969542 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1304 16:53:17.969962 == TX Byte 1 ==
1305 16:53:17.972597 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1306 16:53:17.979487 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1307 16:53:17.979944
1308 16:53:17.980269 [DATLAT]
1309 16:53:17.980573 Freq=800, CH0 RK1
1310 16:53:17.980868
1311 16:53:17.982856 DATLAT Default: 0xa
1312 16:53:17.983369 0, 0xFFFF, sum = 0
1313 16:53:17.985875 1, 0xFFFF, sum = 0
1314 16:53:17.989234 2, 0xFFFF, sum = 0
1315 16:53:17.989662 3, 0xFFFF, sum = 0
1316 16:53:17.992410 4, 0xFFFF, sum = 0
1317 16:53:17.992825 5, 0xFFFF, sum = 0
1318 16:53:17.996316 6, 0xFFFF, sum = 0
1319 16:53:17.996731 7, 0xFFFF, sum = 0
1320 16:53:17.999015 8, 0xFFFF, sum = 0
1321 16:53:17.999433 9, 0x0, sum = 1
1322 16:53:18.002938 10, 0x0, sum = 2
1323 16:53:18.003455 11, 0x0, sum = 3
1324 16:53:18.003899 12, 0x0, sum = 4
1325 16:53:18.006387 best_step = 10
1326 16:53:18.006902
1327 16:53:18.007230 ==
1328 16:53:18.009486 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 16:53:18.012291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 16:53:18.012704 ==
1331 16:53:18.016004 RX Vref Scan: 0
1332 16:53:18.016515
1333 16:53:18.019286 RX Vref 0 -> 0, step: 1
1334 16:53:18.019830
1335 16:53:18.020164 RX Delay -111 -> 252, step: 8
1336 16:53:18.026605 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1337 16:53:18.029397 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1338 16:53:18.033008 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1339 16:53:18.036220 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1340 16:53:18.039818 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
1341 16:53:18.046749 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1342 16:53:18.049656 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1343 16:53:18.053014 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1344 16:53:18.056260 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1345 16:53:18.059260 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1346 16:53:18.065890 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1347 16:53:18.069395 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1348 16:53:18.072729 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1349 16:53:18.075688 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1350 16:53:18.082993 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1351 16:53:18.086208 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1352 16:53:18.086743 ==
1353 16:53:18.089031 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 16:53:18.092541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 16:53:18.092955 ==
1356 16:53:18.095566 DQS Delay:
1357 16:53:18.096129 DQS0 = 0, DQS1 = 0
1358 16:53:18.096575 DQM Delay:
1359 16:53:18.099289 DQM0 = 79, DQM1 = 70
1360 16:53:18.099850 DQ Delay:
1361 16:53:18.103015 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1362 16:53:18.106019 DQ4 =76, DQ5 =64, DQ6 =88, DQ7 =92
1363 16:53:18.108789 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =64
1364 16:53:18.112545 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1365 16:53:18.112954
1366 16:53:18.113274
1367 16:53:18.122409 [DQSOSCAuto] RK1, (LSB)MR18= 0x431f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1368 16:53:18.122935 CH0 RK1: MR19=606, MR18=431F
1369 16:53:18.128869 CH0_RK1: MR19=0x606, MR18=0x431F, DQSOSC=393, MR23=63, INC=95, DEC=63
1370 16:53:18.132308 [RxdqsGatingPostProcess] freq 800
1371 16:53:18.138781 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 16:53:18.141832 Pre-setting of DQS Precalculation
1373 16:53:18.145348 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 16:53:18.145762 ==
1375 16:53:18.148465 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 16:53:18.155483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 16:53:18.155993 ==
1378 16:53:18.158352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 16:53:18.164735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 16:53:18.174673 [CA 0] Center 36 (6~67) winsize 62
1381 16:53:18.177916 [CA 1] Center 37 (7~67) winsize 61
1382 16:53:18.180978 [CA 2] Center 34 (4~65) winsize 62
1383 16:53:18.184630 [CA 3] Center 34 (4~64) winsize 61
1384 16:53:18.187464 [CA 4] Center 34 (4~65) winsize 62
1385 16:53:18.190794 [CA 5] Center 34 (4~64) winsize 61
1386 16:53:18.190873
1387 16:53:18.194244 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 16:53:18.194329
1389 16:53:18.197429 [CATrainingPosCal] consider 1 rank data
1390 16:53:18.200848 u2DelayCellTimex100 = 270/100 ps
1391 16:53:18.204045 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1392 16:53:18.210473 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1393 16:53:18.213783 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1394 16:53:18.217329 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1395 16:53:18.220459 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 16:53:18.223816 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 16:53:18.223896
1398 16:53:18.227008 CA PerBit enable=1, Macro0, CA PI delay=34
1399 16:53:18.227088
1400 16:53:18.230835 [CBTSetCACLKResult] CA Dly = 34
1401 16:53:18.230918 CS Dly: 5 (0~36)
1402 16:53:18.234094 ==
1403 16:53:18.237382 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 16:53:18.240402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 16:53:18.240482 ==
1406 16:53:18.246921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 16:53:18.250577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 16:53:18.260686 [CA 0] Center 37 (7~67) winsize 61
1409 16:53:18.263822 [CA 1] Center 36 (6~67) winsize 62
1410 16:53:18.266800 [CA 2] Center 34 (4~65) winsize 62
1411 16:53:18.270141 [CA 3] Center 33 (3~64) winsize 62
1412 16:53:18.273759 [CA 4] Center 34 (4~65) winsize 62
1413 16:53:18.277317 [CA 5] Center 33 (3~64) winsize 62
1414 16:53:18.277466
1415 16:53:18.280350 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 16:53:18.280500
1417 16:53:18.283482 [CATrainingPosCal] consider 2 rank data
1418 16:53:18.287010 u2DelayCellTimex100 = 270/100 ps
1419 16:53:18.290910 CA0 delay=37 (7~67),Diff = 3 PI (21 cell)
1420 16:53:18.297141 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1421 16:53:18.300297 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1422 16:53:18.304193 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1423 16:53:18.307334 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 16:53:18.310412 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 16:53:18.310824
1426 16:53:18.314299 CA PerBit enable=1, Macro0, CA PI delay=34
1427 16:53:18.314745
1428 16:53:18.318074 [CBTSetCACLKResult] CA Dly = 34
1429 16:53:18.318485 CS Dly: 6 (0~38)
1430 16:53:18.318808
1431 16:53:18.321074 ----->DramcWriteLeveling(PI) begin...
1432 16:53:18.321488 ==
1433 16:53:18.324934 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 16:53:18.328864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 16:53:18.332042 ==
1436 16:53:18.332450 Write leveling (Byte 0): 30 => 30
1437 16:53:18.335044 Write leveling (Byte 1): 31 => 31
1438 16:53:18.338749 DramcWriteLeveling(PI) end<-----
1439 16:53:18.339159
1440 16:53:18.339480 ==
1441 16:53:18.342402 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 16:53:18.346155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 16:53:18.346592 ==
1444 16:53:18.349895 [Gating] SW mode calibration
1445 16:53:18.356212 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 16:53:18.363083 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 16:53:18.366485 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 16:53:18.369591 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1449 16:53:18.376595 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1450 16:53:18.379915 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 16:53:18.382999 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 16:53:18.389387 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 16:53:18.392721 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 16:53:18.396162 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 16:53:18.402975 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 16:53:18.405998 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 16:53:18.409488 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 16:53:18.415758 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 16:53:18.419312 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 16:53:18.422368 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 16:53:18.429316 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 16:53:18.431974 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 16:53:18.435467 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 16:53:18.442420 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1465 16:53:18.445702 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1466 16:53:18.448714 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 16:53:18.455289 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 16:53:18.459003 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 16:53:18.461974 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 16:53:18.468978 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 16:53:18.472042 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 16:53:18.475210 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 16:53:18.478714 0 9 8 | B1->B0 | 2a29 2a2a | 1 1 | (1 1) (1 1)
1474 16:53:18.485487 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 16:53:18.489042 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 16:53:18.491780 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 16:53:18.498332 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 16:53:18.502306 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 16:53:18.505419 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 16:53:18.512177 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
1481 16:53:18.515391 0 10 8 | B1->B0 | 2b2b 2b2b | 0 0 | (1 1) (1 1)
1482 16:53:18.518579 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 16:53:18.525593 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 16:53:18.528665 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 16:53:18.531733 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 16:53:18.538449 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 16:53:18.541971 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 16:53:18.544753 0 11 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1489 16:53:18.551734 0 11 8 | B1->B0 | 3737 3939 | 0 0 | (1 1) (0 0)
1490 16:53:18.555373 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 16:53:18.558412 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 16:53:18.564754 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 16:53:18.568477 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 16:53:18.571317 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 16:53:18.578000 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 16:53:18.581399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 16:53:18.584423 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 16:53:18.591191 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 16:53:18.594776 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 16:53:18.598089 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 16:53:18.604781 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 16:53:18.607787 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 16:53:18.611043 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 16:53:18.617889 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 16:53:18.621407 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 16:53:18.624720 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 16:53:18.630916 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 16:53:18.634114 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 16:53:18.637896 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 16:53:18.644115 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 16:53:18.647887 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 16:53:18.650798 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1513 16:53:18.657807 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1514 16:53:18.657889 Total UI for P1: 0, mck2ui 16
1515 16:53:18.664359 best dqsien dly found for B0: ( 0, 14, 6)
1516 16:53:18.667494 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 16:53:18.670514 Total UI for P1: 0, mck2ui 16
1518 16:53:18.674178 best dqsien dly found for B1: ( 0, 14, 6)
1519 16:53:18.677460 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1520 16:53:18.681045 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 16:53:18.681126
1522 16:53:18.683957 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1523 16:53:18.687192 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 16:53:18.690773 [Gating] SW calibration Done
1525 16:53:18.690853 ==
1526 16:53:18.693787 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 16:53:18.697063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 16:53:18.697144 ==
1529 16:53:18.700651 RX Vref Scan: 0
1530 16:53:18.700731
1531 16:53:18.703573 RX Vref 0 -> 0, step: 1
1532 16:53:18.703672
1533 16:53:18.703735 RX Delay -130 -> 252, step: 16
1534 16:53:18.710514 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 16:53:18.713933 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1536 16:53:18.717185 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1537 16:53:18.720141 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1538 16:53:18.726868 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1539 16:53:18.730689 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1540 16:53:18.733700 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1541 16:53:18.736860 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1542 16:53:18.740059 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1543 16:53:18.743727 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1544 16:53:18.750062 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1545 16:53:18.753396 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1546 16:53:18.757071 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1547 16:53:18.759856 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1548 16:53:18.766578 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1549 16:53:18.770236 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1550 16:53:18.770316 ==
1551 16:53:18.773423 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 16:53:18.776501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 16:53:18.776581 ==
1554 16:53:18.779712 DQS Delay:
1555 16:53:18.779792 DQS0 = 0, DQS1 = 0
1556 16:53:18.779855 DQM Delay:
1557 16:53:18.783434 DQM0 = 81, DQM1 = 70
1558 16:53:18.783513 DQ Delay:
1559 16:53:18.786486 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1560 16:53:18.789694 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1561 16:53:18.793084 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1562 16:53:18.796637 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1563 16:53:18.796717
1564 16:53:18.796780
1565 16:53:18.796838 ==
1566 16:53:18.799742 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 16:53:18.805961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 16:53:18.806044 ==
1569 16:53:18.806107
1570 16:53:18.806165
1571 16:53:18.806221 TX Vref Scan disable
1572 16:53:18.809972 == TX Byte 0 ==
1573 16:53:18.813274 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1574 16:53:18.819487 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1575 16:53:18.819567 == TX Byte 1 ==
1576 16:53:18.823203 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1577 16:53:18.829437 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1578 16:53:18.829517 ==
1579 16:53:18.833185 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 16:53:18.836254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 16:53:18.836334 ==
1582 16:53:18.848722 TX Vref=22, minBit 1, minWin=26, winSum=435
1583 16:53:18.852430 TX Vref=24, minBit 1, minWin=27, winSum=440
1584 16:53:18.855485 TX Vref=26, minBit 1, minWin=26, winSum=440
1585 16:53:18.859066 TX Vref=28, minBit 0, minWin=27, winSum=441
1586 16:53:18.862320 TX Vref=30, minBit 4, minWin=27, winSum=447
1587 16:53:18.868684 TX Vref=32, minBit 4, minWin=27, winSum=445
1588 16:53:18.872078 [TxChooseVref] Worse bit 4, Min win 27, Win sum 447, Final Vref 30
1589 16:53:18.872161
1590 16:53:18.875129 Final TX Range 1 Vref 30
1591 16:53:18.875215
1592 16:53:18.875292 ==
1593 16:53:18.879055 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 16:53:18.882048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 16:53:18.882136 ==
1596 16:53:18.885389
1597 16:53:18.885471
1598 16:53:18.885535 TX Vref Scan disable
1599 16:53:18.888935 == TX Byte 0 ==
1600 16:53:18.892632 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1601 16:53:18.895861 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1602 16:53:18.899542 == TX Byte 1 ==
1603 16:53:18.902432 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1604 16:53:18.905544 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1605 16:53:18.905633
1606 16:53:18.909249 [DATLAT]
1607 16:53:18.909331 Freq=800, CH1 RK0
1608 16:53:18.909397
1609 16:53:18.912341 DATLAT Default: 0xa
1610 16:53:18.912423 0, 0xFFFF, sum = 0
1611 16:53:18.915829 1, 0xFFFF, sum = 0
1612 16:53:18.915916 2, 0xFFFF, sum = 0
1613 16:53:18.918823 3, 0xFFFF, sum = 0
1614 16:53:18.918925 4, 0xFFFF, sum = 0
1615 16:53:18.922432 5, 0xFFFF, sum = 0
1616 16:53:18.922535 6, 0xFFFF, sum = 0
1617 16:53:18.925446 7, 0xFFFF, sum = 0
1618 16:53:18.925547 8, 0xFFFF, sum = 0
1619 16:53:18.929057 9, 0x0, sum = 1
1620 16:53:18.929159 10, 0x0, sum = 2
1621 16:53:18.932036 11, 0x0, sum = 3
1622 16:53:18.932137 12, 0x0, sum = 4
1623 16:53:18.936022 best_step = 10
1624 16:53:18.936122
1625 16:53:18.936212 ==
1626 16:53:18.938861 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 16:53:18.942153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 16:53:18.942234 ==
1629 16:53:18.945407 RX Vref Scan: 1
1630 16:53:18.945488
1631 16:53:18.945552 Set Vref Range= 32 -> 127
1632 16:53:18.945612
1633 16:53:18.949175 RX Vref 32 -> 127, step: 1
1634 16:53:18.949256
1635 16:53:18.952258 RX Delay -111 -> 252, step: 8
1636 16:53:18.952339
1637 16:53:18.955443 Set Vref, RX VrefLevel [Byte0]: 32
1638 16:53:18.958706 [Byte1]: 32
1639 16:53:18.958788
1640 16:53:18.962283 Set Vref, RX VrefLevel [Byte0]: 33
1641 16:53:18.965440 [Byte1]: 33
1642 16:53:18.969350
1643 16:53:18.969429 Set Vref, RX VrefLevel [Byte0]: 34
1644 16:53:18.972926 [Byte1]: 34
1645 16:53:18.976825
1646 16:53:18.976905 Set Vref, RX VrefLevel [Byte0]: 35
1647 16:53:18.980490 [Byte1]: 35
1648 16:53:18.984900
1649 16:53:18.984980 Set Vref, RX VrefLevel [Byte0]: 36
1650 16:53:18.987608 [Byte1]: 36
1651 16:53:18.991971
1652 16:53:18.992054 Set Vref, RX VrefLevel [Byte0]: 37
1653 16:53:18.995787 [Byte1]: 37
1654 16:53:19.000070
1655 16:53:19.000154 Set Vref, RX VrefLevel [Byte0]: 38
1656 16:53:19.003188 [Byte1]: 38
1657 16:53:19.007229
1658 16:53:19.007313 Set Vref, RX VrefLevel [Byte0]: 39
1659 16:53:19.010836 [Byte1]: 39
1660 16:53:19.015310
1661 16:53:19.015393 Set Vref, RX VrefLevel [Byte0]: 40
1662 16:53:19.018448 [Byte1]: 40
1663 16:53:19.022574
1664 16:53:19.022658 Set Vref, RX VrefLevel [Byte0]: 41
1665 16:53:19.026043 [Byte1]: 41
1666 16:53:19.030766
1667 16:53:19.030846 Set Vref, RX VrefLevel [Byte0]: 42
1668 16:53:19.033525 [Byte1]: 42
1669 16:53:19.038148
1670 16:53:19.038221 Set Vref, RX VrefLevel [Byte0]: 43
1671 16:53:19.041315 [Byte1]: 43
1672 16:53:19.045615
1673 16:53:19.045700 Set Vref, RX VrefLevel [Byte0]: 44
1674 16:53:19.048863 [Byte1]: 44
1675 16:53:19.053233
1676 16:53:19.053308 Set Vref, RX VrefLevel [Byte0]: 45
1677 16:53:19.057076 [Byte1]: 45
1678 16:53:19.060815
1679 16:53:19.060899 Set Vref, RX VrefLevel [Byte0]: 46
1680 16:53:19.064515 [Byte1]: 46
1681 16:53:19.068849
1682 16:53:19.068932 Set Vref, RX VrefLevel [Byte0]: 47
1683 16:53:19.072111 [Byte1]: 47
1684 16:53:19.076292
1685 16:53:19.076373 Set Vref, RX VrefLevel [Byte0]: 48
1686 16:53:19.079468 [Byte1]: 48
1687 16:53:19.083935
1688 16:53:19.084012 Set Vref, RX VrefLevel [Byte0]: 49
1689 16:53:19.087477 [Byte1]: 49
1690 16:53:19.091365
1691 16:53:19.091473 Set Vref, RX VrefLevel [Byte0]: 50
1692 16:53:19.095073 [Byte1]: 50
1693 16:53:19.099787
1694 16:53:19.099868 Set Vref, RX VrefLevel [Byte0]: 51
1695 16:53:19.102772 [Byte1]: 51
1696 16:53:19.107357
1697 16:53:19.107428 Set Vref, RX VrefLevel [Byte0]: 52
1698 16:53:19.110360 [Byte1]: 52
1699 16:53:19.114451
1700 16:53:19.114531 Set Vref, RX VrefLevel [Byte0]: 53
1701 16:53:19.117982 [Byte1]: 53
1702 16:53:19.122160
1703 16:53:19.122237 Set Vref, RX VrefLevel [Byte0]: 54
1704 16:53:19.125298 [Byte1]: 54
1705 16:53:19.129615
1706 16:53:19.129689 Set Vref, RX VrefLevel [Byte0]: 55
1707 16:53:19.132961 [Byte1]: 55
1708 16:53:19.137506
1709 16:53:19.137579 Set Vref, RX VrefLevel [Byte0]: 56
1710 16:53:19.140440 [Byte1]: 56
1711 16:53:19.144919
1712 16:53:19.145004 Set Vref, RX VrefLevel [Byte0]: 57
1713 16:53:19.148238 [Byte1]: 57
1714 16:53:19.152610
1715 16:53:19.152691 Set Vref, RX VrefLevel [Byte0]: 58
1716 16:53:19.156258 [Byte1]: 58
1717 16:53:19.160740
1718 16:53:19.160813 Set Vref, RX VrefLevel [Byte0]: 59
1719 16:53:19.163865 [Byte1]: 59
1720 16:53:19.168128
1721 16:53:19.168206 Set Vref, RX VrefLevel [Byte0]: 60
1722 16:53:19.171052 [Byte1]: 60
1723 16:53:19.175755
1724 16:53:19.175829 Set Vref, RX VrefLevel [Byte0]: 61
1725 16:53:19.179402 [Byte1]: 61
1726 16:53:19.183208
1727 16:53:19.183284 Set Vref, RX VrefLevel [Byte0]: 62
1728 16:53:19.186681 [Byte1]: 62
1729 16:53:19.190772
1730 16:53:19.190847 Set Vref, RX VrefLevel [Byte0]: 63
1731 16:53:19.194424 [Byte1]: 63
1732 16:53:19.198622
1733 16:53:19.198693 Set Vref, RX VrefLevel [Byte0]: 64
1734 16:53:19.202054 [Byte1]: 64
1735 16:53:19.206287
1736 16:53:19.206367 Set Vref, RX VrefLevel [Byte0]: 65
1737 16:53:19.209451 [Byte1]: 65
1738 16:53:19.213992
1739 16:53:19.214064 Set Vref, RX VrefLevel [Byte0]: 66
1740 16:53:19.217039 [Byte1]: 66
1741 16:53:19.221393
1742 16:53:19.221465 Set Vref, RX VrefLevel [Byte0]: 67
1743 16:53:19.224867 [Byte1]: 67
1744 16:53:19.229366
1745 16:53:19.229443 Set Vref, RX VrefLevel [Byte0]: 68
1746 16:53:19.232391 [Byte1]: 68
1747 16:53:19.236690
1748 16:53:19.236763 Set Vref, RX VrefLevel [Byte0]: 69
1749 16:53:19.240484 [Byte1]: 69
1750 16:53:19.244462
1751 16:53:19.244543 Set Vref, RX VrefLevel [Byte0]: 70
1752 16:53:19.247808 [Byte1]: 70
1753 16:53:19.252285
1754 16:53:19.252361 Set Vref, RX VrefLevel [Byte0]: 71
1755 16:53:19.255560 [Byte1]: 71
1756 16:53:19.259942
1757 16:53:19.260017 Set Vref, RX VrefLevel [Byte0]: 72
1758 16:53:19.266136 [Byte1]: 72
1759 16:53:19.266211
1760 16:53:19.269435 Set Vref, RX VrefLevel [Byte0]: 73
1761 16:53:19.272615 [Byte1]: 73
1762 16:53:19.272690
1763 16:53:19.276368 Set Vref, RX VrefLevel [Byte0]: 74
1764 16:53:19.279412 [Byte1]: 74
1765 16:53:19.282519
1766 16:53:19.282598 Final RX Vref Byte 0 = 60 to rank0
1767 16:53:19.286404 Final RX Vref Byte 1 = 55 to rank0
1768 16:53:19.289494 Final RX Vref Byte 0 = 60 to rank1
1769 16:53:19.292589 Final RX Vref Byte 1 = 55 to rank1==
1770 16:53:19.296112 Dram Type= 6, Freq= 0, CH_1, rank 0
1771 16:53:19.302359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1772 16:53:19.302440 ==
1773 16:53:19.302505 DQS Delay:
1774 16:53:19.306228 DQS0 = 0, DQS1 = 0
1775 16:53:19.306300 DQM Delay:
1776 16:53:19.306369 DQM0 = 81, DQM1 = 71
1777 16:53:19.309188 DQ Delay:
1778 16:53:19.312454 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1779 16:53:19.315583 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1780 16:53:19.318802 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1781 16:53:19.322681 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1782 16:53:19.322753
1783 16:53:19.322814
1784 16:53:19.329096 [DQSOSCAuto] RK0, (LSB)MR18= 0x1019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1785 16:53:19.332118 CH1 RK0: MR19=606, MR18=1019
1786 16:53:19.338742 CH1_RK0: MR19=0x606, MR18=0x1019, DQSOSC=403, MR23=63, INC=90, DEC=60
1787 16:53:19.338820
1788 16:53:19.342379 ----->DramcWriteLeveling(PI) begin...
1789 16:53:19.342461 ==
1790 16:53:19.345573 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 16:53:19.348821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 16:53:19.348906 ==
1793 16:53:19.352342 Write leveling (Byte 0): 28 => 28
1794 16:53:19.355364 Write leveling (Byte 1): 32 => 32
1795 16:53:19.358930 DramcWriteLeveling(PI) end<-----
1796 16:53:19.359014
1797 16:53:19.359098 ==
1798 16:53:19.361939 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 16:53:19.365526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 16:53:19.365610 ==
1801 16:53:19.368698 [Gating] SW mode calibration
1802 16:53:19.375624 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1803 16:53:19.381908 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1804 16:53:19.385135 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1805 16:53:19.391787 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1806 16:53:19.394981 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 16:53:19.398669 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 16:53:19.405071 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 16:53:19.408360 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 16:53:19.411780 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 16:53:19.418411 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 16:53:19.421603 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 16:53:19.424778 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 16:53:19.431518 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 16:53:19.434713 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 16:53:19.437749 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 16:53:19.444584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 16:53:19.447846 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 16:53:19.451374 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 16:53:19.457908 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 16:53:19.460860 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1822 16:53:19.464287 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 16:53:19.471330 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 16:53:19.474486 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 16:53:19.477553 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 16:53:19.484367 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 16:53:19.487454 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 16:53:19.490721 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1829 16:53:19.497684 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1830 16:53:19.500928 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1831 16:53:19.504062 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 16:53:19.510821 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 16:53:19.513791 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 16:53:19.517457 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 16:53:19.523937 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 16:53:19.527146 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 16:53:19.530352 0 10 4 | B1->B0 | 3232 3030 | 0 0 | (0 1) (0 1)
1838 16:53:19.537325 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 16:53:19.540421 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 16:53:19.543704 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 16:53:19.549823 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 16:53:19.553299 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 16:53:19.556834 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 16:53:19.563113 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 16:53:19.566730 0 11 4 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (0 0)
1846 16:53:19.570082 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1847 16:53:19.576408 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 16:53:19.579556 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 16:53:19.583316 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 16:53:19.589896 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 16:53:19.592945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 16:53:19.596143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 16:53:19.603041 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 16:53:19.606307 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 16:53:19.609317 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 16:53:19.616402 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 16:53:19.619751 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 16:53:19.622777 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 16:53:19.626628 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 16:53:19.632717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 16:53:19.636367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 16:53:19.639597 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 16:53:19.646365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 16:53:19.649493 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 16:53:19.653176 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 16:53:19.659161 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 16:53:19.662791 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 16:53:19.666299 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 16:53:19.672790 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1870 16:53:19.675805 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 16:53:19.679256 Total UI for P1: 0, mck2ui 16
1872 16:53:19.682564 best dqsien dly found for B0: ( 0, 14, 4)
1873 16:53:19.685930 Total UI for P1: 0, mck2ui 16
1874 16:53:19.689170 best dqsien dly found for B1: ( 0, 14, 6)
1875 16:53:19.692668 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1876 16:53:19.695929 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1877 16:53:19.696013
1878 16:53:19.699068 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 16:53:19.702887 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1880 16:53:19.705906 [Gating] SW calibration Done
1881 16:53:19.705978 ==
1882 16:53:19.709161 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 16:53:19.712241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 16:53:19.715780 ==
1885 16:53:19.715855 RX Vref Scan: 0
1886 16:53:19.715927
1887 16:53:19.719188 RX Vref 0 -> 0, step: 1
1888 16:53:19.719259
1889 16:53:19.722221 RX Delay -130 -> 252, step: 16
1890 16:53:19.725765 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1891 16:53:19.728848 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1892 16:53:19.732372 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1893 16:53:19.735287 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1894 16:53:19.742613 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1895 16:53:19.745749 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1896 16:53:19.748914 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1897 16:53:19.752177 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1898 16:53:19.755770 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1899 16:53:19.761994 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1900 16:53:19.765551 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1901 16:53:19.768977 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1902 16:53:19.771874 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1903 16:53:19.775651 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1904 16:53:19.782538 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1905 16:53:19.785564 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1906 16:53:19.785642 ==
1907 16:53:19.788587 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 16:53:19.791892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 16:53:19.791975 ==
1910 16:53:19.795300 DQS Delay:
1911 16:53:19.795371 DQS0 = 0, DQS1 = 0
1912 16:53:19.795432 DQM Delay:
1913 16:53:19.798343 DQM0 = 77, DQM1 = 71
1914 16:53:19.798412 DQ Delay:
1915 16:53:19.801871 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1916 16:53:19.805142 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1917 16:53:19.808350 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1918 16:53:19.811496 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1919 16:53:19.811635
1920 16:53:19.811709
1921 16:53:19.811769 ==
1922 16:53:19.815339 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 16:53:19.821551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 16:53:19.821630 ==
1925 16:53:19.821694
1926 16:53:19.821760
1927 16:53:19.821820 TX Vref Scan disable
1928 16:53:19.825814 == TX Byte 0 ==
1929 16:53:19.828604 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1930 16:53:19.835437 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1931 16:53:19.835543 == TX Byte 1 ==
1932 16:53:19.839247 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1933 16:53:19.845609 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1934 16:53:19.845695 ==
1935 16:53:19.848638 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 16:53:19.851754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 16:53:19.851827 ==
1938 16:53:19.864813 TX Vref=22, minBit 5, minWin=27, winSum=451
1939 16:53:19.867872 TX Vref=24, minBit 7, minWin=27, winSum=451
1940 16:53:19.871499 TX Vref=26, minBit 1, minWin=27, winSum=451
1941 16:53:19.875005 TX Vref=28, minBit 5, minWin=27, winSum=453
1942 16:53:19.878031 TX Vref=30, minBit 1, minWin=27, winSum=459
1943 16:53:19.884518 TX Vref=32, minBit 1, minWin=27, winSum=459
1944 16:53:19.887666 [TxChooseVref] Worse bit 1, Min win 27, Win sum 459, Final Vref 30
1945 16:53:19.887741
1946 16:53:19.890965 Final TX Range 1 Vref 30
1947 16:53:19.891034
1948 16:53:19.891093 ==
1949 16:53:19.894459 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 16:53:19.897984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 16:53:19.901367 ==
1952 16:53:19.901445
1953 16:53:19.901508
1954 16:53:19.901569 TX Vref Scan disable
1955 16:53:19.904626 == TX Byte 0 ==
1956 16:53:19.908025 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1957 16:53:19.914523 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1958 16:53:19.914604 == TX Byte 1 ==
1959 16:53:19.918167 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1960 16:53:19.924428 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1961 16:53:19.924506
1962 16:53:19.924572 [DATLAT]
1963 16:53:19.924633 Freq=800, CH1 RK1
1964 16:53:19.924696
1965 16:53:19.927652 DATLAT Default: 0xa
1966 16:53:19.931114 0, 0xFFFF, sum = 0
1967 16:53:19.931191 1, 0xFFFF, sum = 0
1968 16:53:19.934235 2, 0xFFFF, sum = 0
1969 16:53:19.934323 3, 0xFFFF, sum = 0
1970 16:53:19.937828 4, 0xFFFF, sum = 0
1971 16:53:19.937912 5, 0xFFFF, sum = 0
1972 16:53:19.940946 6, 0xFFFF, sum = 0
1973 16:53:19.941022 7, 0xFFFF, sum = 0
1974 16:53:19.944048 8, 0x0, sum = 1
1975 16:53:19.944149 9, 0x0, sum = 2
1976 16:53:19.947878 10, 0x0, sum = 3
1977 16:53:19.947974 11, 0x0, sum = 4
1978 16:53:19.948041 best_step = 9
1979 16:53:19.948102
1980 16:53:19.950807 ==
1981 16:53:19.950890 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 16:53:19.957726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 16:53:19.957808 ==
1984 16:53:19.957873 RX Vref Scan: 0
1985 16:53:19.957934
1986 16:53:19.960830 RX Vref 0 -> 0, step: 1
1987 16:53:19.960898
1988 16:53:19.963862 RX Delay -111 -> 252, step: 8
1989 16:53:19.967584 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1990 16:53:19.973952 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1991 16:53:19.977503 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1992 16:53:19.980489 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1993 16:53:19.984095 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1994 16:53:19.987034 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1995 16:53:19.993793 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1996 16:53:19.997013 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1997 16:53:20.000818 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1998 16:53:20.003756 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1999 16:53:20.007235 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2000 16:53:20.013536 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
2001 16:53:20.017416 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2002 16:53:20.020575 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2003 16:53:20.023566 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2004 16:53:20.026755 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2005 16:53:20.030157 ==
2006 16:53:20.033842 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 16:53:20.036863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 16:53:20.036946 ==
2009 16:53:20.037011 DQS Delay:
2010 16:53:20.040481 DQS0 = 0, DQS1 = 0
2011 16:53:20.040563 DQM Delay:
2012 16:53:20.043761 DQM0 = 78, DQM1 = 74
2013 16:53:20.043842 DQ Delay:
2014 16:53:20.046736 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2015 16:53:20.049926 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2016 16:53:20.053576 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =64
2017 16:53:20.056864 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2018 16:53:20.056946
2019 16:53:20.057011
2020 16:53:20.063606 [DQSOSCAuto] RK1, (LSB)MR18= 0x233c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2021 16:53:20.066777 CH1 RK1: MR19=606, MR18=233C
2022 16:53:20.073120 CH1_RK1: MR19=0x606, MR18=0x233C, DQSOSC=394, MR23=63, INC=95, DEC=63
2023 16:53:20.076779 [RxdqsGatingPostProcess] freq 800
2024 16:53:20.083500 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2025 16:53:20.083606 Pre-setting of DQS Precalculation
2026 16:53:20.089670 [DualRankRxdatlatCal] RK0: 10, RK1: 9, Final_Datlat 10
2027 16:53:20.096739 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2028 16:53:20.103058 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2029 16:53:20.103159
2030 16:53:20.103279
2031 16:53:20.106845 [Calibration Summary] 1600 Mbps
2032 16:53:20.110079 CH 0, Rank 0
2033 16:53:20.110171 SW Impedance : PASS
2034 16:53:20.113055 DUTY Scan : NO K
2035 16:53:20.116510 ZQ Calibration : PASS
2036 16:53:20.116595 Jitter Meter : NO K
2037 16:53:20.119849 CBT Training : PASS
2038 16:53:20.123460 Write leveling : PASS
2039 16:53:20.123557 RX DQS gating : PASS
2040 16:53:20.126432 RX DQ/DQS(RDDQC) : PASS
2041 16:53:20.126514 TX DQ/DQS : PASS
2042 16:53:20.129652 RX DATLAT : PASS
2043 16:53:20.133407 RX DQ/DQS(Engine): PASS
2044 16:53:20.133512 TX OE : NO K
2045 16:53:20.136362 All Pass.
2046 16:53:20.136444
2047 16:53:20.136509 CH 0, Rank 1
2048 16:53:20.139440 SW Impedance : PASS
2049 16:53:20.139522 DUTY Scan : NO K
2050 16:53:20.142929 ZQ Calibration : PASS
2051 16:53:20.146289 Jitter Meter : NO K
2052 16:53:20.146372 CBT Training : PASS
2053 16:53:20.149953 Write leveling : PASS
2054 16:53:20.153087 RX DQS gating : PASS
2055 16:53:20.153169 RX DQ/DQS(RDDQC) : PASS
2056 16:53:20.156684 TX DQ/DQS : PASS
2057 16:53:20.159945 RX DATLAT : PASS
2058 16:53:20.160030 RX DQ/DQS(Engine): PASS
2059 16:53:20.163402 TX OE : NO K
2060 16:53:20.163485 All Pass.
2061 16:53:20.163550
2062 16:53:20.166509 CH 1, Rank 0
2063 16:53:20.166591 SW Impedance : PASS
2064 16:53:20.169702 DUTY Scan : NO K
2065 16:53:20.172806 ZQ Calibration : PASS
2066 16:53:20.172888 Jitter Meter : NO K
2067 16:53:20.176611 CBT Training : PASS
2068 16:53:20.176694 Write leveling : PASS
2069 16:53:20.179819 RX DQS gating : PASS
2070 16:53:20.182845 RX DQ/DQS(RDDQC) : PASS
2071 16:53:20.182928 TX DQ/DQS : PASS
2072 16:53:20.186526 RX DATLAT : PASS
2073 16:53:20.189676 RX DQ/DQS(Engine): PASS
2074 16:53:20.189759 TX OE : NO K
2075 16:53:20.193354 All Pass.
2076 16:53:20.193436
2077 16:53:20.193510 CH 1, Rank 1
2078 16:53:20.196408 SW Impedance : PASS
2079 16:53:20.196490 DUTY Scan : NO K
2080 16:53:20.199811 ZQ Calibration : PASS
2081 16:53:20.202885 Jitter Meter : NO K
2082 16:53:20.202968 CBT Training : PASS
2083 16:53:20.206071 Write leveling : PASS
2084 16:53:20.209203 RX DQS gating : PASS
2085 16:53:20.209288 RX DQ/DQS(RDDQC) : PASS
2086 16:53:20.212465 TX DQ/DQS : PASS
2087 16:53:20.216034 RX DATLAT : PASS
2088 16:53:20.216117 RX DQ/DQS(Engine): PASS
2089 16:53:20.219001 TX OE : NO K
2090 16:53:20.219083 All Pass.
2091 16:53:20.219148
2092 16:53:20.222584 DramC Write-DBI off
2093 16:53:20.225765 PER_BANK_REFRESH: Hybrid Mode
2094 16:53:20.225848 TX_TRACKING: ON
2095 16:53:20.229195 [GetDramInforAfterCalByMRR] Vendor 6.
2096 16:53:20.232729 [GetDramInforAfterCalByMRR] Revision 606.
2097 16:53:20.235522 [GetDramInforAfterCalByMRR] Revision 2 0.
2098 16:53:20.238958 MR0 0x3b3b
2099 16:53:20.239040 MR8 0x5151
2100 16:53:20.242561 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2101 16:53:20.242644
2102 16:53:20.242709 MR0 0x3b3b
2103 16:53:20.245510 MR8 0x5151
2104 16:53:20.249123 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2105 16:53:20.249206
2106 16:53:20.258788 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2107 16:53:20.262542 [FAST_K] Save calibration result to emmc
2108 16:53:20.265603 [FAST_K] Save calibration result to emmc
2109 16:53:20.265686 dram_init: config_dvfs: 1
2110 16:53:20.272317 dramc_set_vcore_voltage set vcore to 662500
2111 16:53:20.272425 Read voltage for 1200, 2
2112 16:53:20.275460 Vio18 = 0
2113 16:53:20.275561 Vcore = 662500
2114 16:53:20.275690 Vdram = 0
2115 16:53:20.278617 Vddq = 0
2116 16:53:20.278699 Vmddr = 0
2117 16:53:20.282276 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2118 16:53:20.288744 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2119 16:53:20.292294 MEM_TYPE=3, freq_sel=15
2120 16:53:20.295384 sv_algorithm_assistance_LP4_1600
2121 16:53:20.298411 ============ PULL DRAM RESETB DOWN ============
2122 16:53:20.301995 ========== PULL DRAM RESETB DOWN end =========
2123 16:53:20.308451 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2124 16:53:20.311940 ===================================
2125 16:53:20.312023 LPDDR4 DRAM CONFIGURATION
2126 16:53:20.315051 ===================================
2127 16:53:20.318292 EX_ROW_EN[0] = 0x0
2128 16:53:20.318374 EX_ROW_EN[1] = 0x0
2129 16:53:20.321910 LP4Y_EN = 0x0
2130 16:53:20.321992 WORK_FSP = 0x0
2131 16:53:20.325059 WL = 0x4
2132 16:53:20.325141 RL = 0x4
2133 16:53:20.328299 BL = 0x2
2134 16:53:20.328382 RPST = 0x0
2135 16:53:20.331486 RD_PRE = 0x0
2136 16:53:20.335075 WR_PRE = 0x1
2137 16:53:20.335157 WR_PST = 0x0
2138 16:53:20.338175 DBI_WR = 0x0
2139 16:53:20.338257 DBI_RD = 0x0
2140 16:53:20.341605 OTF = 0x1
2141 16:53:20.345224 ===================================
2142 16:53:20.348277 ===================================
2143 16:53:20.348359 ANA top config
2144 16:53:20.351688 ===================================
2145 16:53:20.354804 DLL_ASYNC_EN = 0
2146 16:53:20.358292 ALL_SLAVE_EN = 0
2147 16:53:20.358389 NEW_RANK_MODE = 1
2148 16:53:20.361445 DLL_IDLE_MODE = 1
2149 16:53:20.365093 LP45_APHY_COMB_EN = 1
2150 16:53:20.368262 TX_ODT_DIS = 1
2151 16:53:20.368345 NEW_8X_MODE = 1
2152 16:53:20.371459 ===================================
2153 16:53:20.374909 ===================================
2154 16:53:20.378100 data_rate = 2400
2155 16:53:20.381205 CKR = 1
2156 16:53:20.385020 DQ_P2S_RATIO = 8
2157 16:53:20.388016 ===================================
2158 16:53:20.391114 CA_P2S_RATIO = 8
2159 16:53:20.394925 DQ_CA_OPEN = 0
2160 16:53:20.398148 DQ_SEMI_OPEN = 0
2161 16:53:20.398231 CA_SEMI_OPEN = 0
2162 16:53:20.401276 CA_FULL_RATE = 0
2163 16:53:20.404804 DQ_CKDIV4_EN = 0
2164 16:53:20.407935 CA_CKDIV4_EN = 0
2165 16:53:20.411387 CA_PREDIV_EN = 0
2166 16:53:20.414381 PH8_DLY = 17
2167 16:53:20.414495 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2168 16:53:20.417474 DQ_AAMCK_DIV = 4
2169 16:53:20.421169 CA_AAMCK_DIV = 4
2170 16:53:20.424217 CA_ADMCK_DIV = 4
2171 16:53:20.427564 DQ_TRACK_CA_EN = 0
2172 16:53:20.431122 CA_PICK = 1200
2173 16:53:20.434155 CA_MCKIO = 1200
2174 16:53:20.434258 MCKIO_SEMI = 0
2175 16:53:20.437855 PLL_FREQ = 2366
2176 16:53:20.440711 DQ_UI_PI_RATIO = 32
2177 16:53:20.444163 CA_UI_PI_RATIO = 0
2178 16:53:20.447862 ===================================
2179 16:53:20.450793 ===================================
2180 16:53:20.454195 memory_type:LPDDR4
2181 16:53:20.454277 GP_NUM : 10
2182 16:53:20.457229 SRAM_EN : 1
2183 16:53:20.460775 MD32_EN : 0
2184 16:53:20.464007 ===================================
2185 16:53:20.464089 [ANA_INIT] >>>>>>>>>>>>>>
2186 16:53:20.467788 <<<<<< [CONFIGURE PHASE]: ANA_TX
2187 16:53:20.470932 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2188 16:53:20.474033 ===================================
2189 16:53:20.477695 data_rate = 2400,PCW = 0X5b00
2190 16:53:20.480464 ===================================
2191 16:53:20.484145 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2192 16:53:20.490358 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 16:53:20.494158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 16:53:20.500565 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2195 16:53:20.503701 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2196 16:53:20.507450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2197 16:53:20.507532 [ANA_INIT] flow start
2198 16:53:20.510512 [ANA_INIT] PLL >>>>>>>>
2199 16:53:20.513996 [ANA_INIT] PLL <<<<<<<<
2200 16:53:20.514078 [ANA_INIT] MIDPI >>>>>>>>
2201 16:53:20.517002 [ANA_INIT] MIDPI <<<<<<<<
2202 16:53:20.520592 [ANA_INIT] DLL >>>>>>>>
2203 16:53:20.523478 [ANA_INIT] DLL <<<<<<<<
2204 16:53:20.523583 [ANA_INIT] flow end
2205 16:53:20.527039 ============ LP4 DIFF to SE enter ============
2206 16:53:20.533822 ============ LP4 DIFF to SE exit ============
2207 16:53:20.533906 [ANA_INIT] <<<<<<<<<<<<<
2208 16:53:20.536983 [Flow] Enable top DCM control >>>>>
2209 16:53:20.540603 [Flow] Enable top DCM control <<<<<
2210 16:53:20.543549 Enable DLL master slave shuffle
2211 16:53:20.550091 ==============================================================
2212 16:53:20.550183 Gating Mode config
2213 16:53:20.557120 ==============================================================
2214 16:53:20.560135 Config description:
2215 16:53:20.570253 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2216 16:53:20.576840 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2217 16:53:20.580459 SELPH_MODE 0: By rank 1: By Phase
2218 16:53:20.586547 ==============================================================
2219 16:53:20.590052 GAT_TRACK_EN = 1
2220 16:53:20.590125 RX_GATING_MODE = 2
2221 16:53:20.593198 RX_GATING_TRACK_MODE = 2
2222 16:53:20.596398 SELPH_MODE = 1
2223 16:53:20.600030 PICG_EARLY_EN = 1
2224 16:53:20.603084 VALID_LAT_VALUE = 1
2225 16:53:20.610290 ==============================================================
2226 16:53:20.613282 Enter into Gating configuration >>>>
2227 16:53:20.616348 Exit from Gating configuration <<<<
2228 16:53:20.619778 Enter into DVFS_PRE_config >>>>>
2229 16:53:20.629899 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2230 16:53:20.632830 Exit from DVFS_PRE_config <<<<<
2231 16:53:20.636100 Enter into PICG configuration >>>>
2232 16:53:20.639933 Exit from PICG configuration <<<<
2233 16:53:20.643150 [RX_INPUT] configuration >>>>>
2234 16:53:20.646312 [RX_INPUT] configuration <<<<<
2235 16:53:20.649803 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2236 16:53:20.656171 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2237 16:53:20.662974 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2238 16:53:20.669462 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2239 16:53:20.673158 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 16:53:20.679375 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 16:53:20.682979 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2242 16:53:20.689207 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2243 16:53:20.693073 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2244 16:53:20.696128 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2245 16:53:20.699247 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2246 16:53:20.706013 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2247 16:53:20.709258 ===================================
2248 16:53:20.709332 LPDDR4 DRAM CONFIGURATION
2249 16:53:20.712805 ===================================
2250 16:53:20.715996 EX_ROW_EN[0] = 0x0
2251 16:53:20.719280 EX_ROW_EN[1] = 0x0
2252 16:53:20.719351 LP4Y_EN = 0x0
2253 16:53:20.722328 WORK_FSP = 0x0
2254 16:53:20.722402 WL = 0x4
2255 16:53:20.725880 RL = 0x4
2256 16:53:20.725953 BL = 0x2
2257 16:53:20.729137 RPST = 0x0
2258 16:53:20.729218 RD_PRE = 0x0
2259 16:53:20.732883 WR_PRE = 0x1
2260 16:53:20.732958 WR_PST = 0x0
2261 16:53:20.735500 DBI_WR = 0x0
2262 16:53:20.735569 DBI_RD = 0x0
2263 16:53:20.738933 OTF = 0x1
2264 16:53:20.742160 ===================================
2265 16:53:20.745919 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2266 16:53:20.749069 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2267 16:53:20.755924 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2268 16:53:20.758673 ===================================
2269 16:53:20.758748 LPDDR4 DRAM CONFIGURATION
2270 16:53:20.762214 ===================================
2271 16:53:20.765448 EX_ROW_EN[0] = 0x10
2272 16:53:20.769123 EX_ROW_EN[1] = 0x0
2273 16:53:20.769195 LP4Y_EN = 0x0
2274 16:53:20.772567 WORK_FSP = 0x0
2275 16:53:20.772661 WL = 0x4
2276 16:53:20.775569 RL = 0x4
2277 16:53:20.775667 BL = 0x2
2278 16:53:20.778938 RPST = 0x0
2279 16:53:20.779023 RD_PRE = 0x0
2280 16:53:20.781999 WR_PRE = 0x1
2281 16:53:20.782080 WR_PST = 0x0
2282 16:53:20.785284 DBI_WR = 0x0
2283 16:53:20.785367 DBI_RD = 0x0
2284 16:53:20.788902 OTF = 0x1
2285 16:53:20.791942 ===================================
2286 16:53:20.798859 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2287 16:53:20.798938 ==
2288 16:53:20.801738 Dram Type= 6, Freq= 0, CH_0, rank 0
2289 16:53:20.805481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2290 16:53:20.805557 ==
2291 16:53:20.808908 [Duty_Offset_Calibration]
2292 16:53:20.808978 B0:2 B1:0 CA:3
2293 16:53:20.809046
2294 16:53:20.811930 [DutyScan_Calibration_Flow] k_type=0
2295 16:53:20.822765
2296 16:53:20.822839 ==CLK 0==
2297 16:53:20.825786 Final CLK duty delay cell = 0
2298 16:53:20.828940 [0] MAX Duty = 5031%(X100), DQS PI = 20
2299 16:53:20.832082 [0] MIN Duty = 4906%(X100), DQS PI = 54
2300 16:53:20.835304 [0] AVG Duty = 4968%(X100)
2301 16:53:20.835374
2302 16:53:20.838802 CH0 CLK Duty spec in!! Max-Min= 125%
2303 16:53:20.842538 [DutyScan_Calibration_Flow] ====Done====
2304 16:53:20.842611
2305 16:53:20.845533 [DutyScan_Calibration_Flow] k_type=1
2306 16:53:20.860823
2307 16:53:20.860975 ==DQS 0 ==
2308 16:53:20.864601 Final DQS duty delay cell = 0
2309 16:53:20.867568 [0] MAX Duty = 5062%(X100), DQS PI = 10
2310 16:53:20.871002 [0] MIN Duty = 4938%(X100), DQS PI = 0
2311 16:53:20.871074 [0] AVG Duty = 5000%(X100)
2312 16:53:20.874347
2313 16:53:20.874420 ==DQS 1 ==
2314 16:53:20.877345 Final DQS duty delay cell = -4
2315 16:53:20.880920 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2316 16:53:20.883881 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2317 16:53:20.887666 [-4] AVG Duty = 4937%(X100)
2318 16:53:20.887739
2319 16:53:20.890372 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2320 16:53:20.890441
2321 16:53:20.893813 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2322 16:53:20.896951 [DutyScan_Calibration_Flow] ====Done====
2323 16:53:20.897018
2324 16:53:20.900850 [DutyScan_Calibration_Flow] k_type=3
2325 16:53:20.918664
2326 16:53:20.918745 ==DQM 0 ==
2327 16:53:20.921321 Final DQM duty delay cell = 0
2328 16:53:20.925066 [0] MAX Duty = 5093%(X100), DQS PI = 12
2329 16:53:20.928146 [0] MIN Duty = 4876%(X100), DQS PI = 0
2330 16:53:20.931464 [0] AVG Duty = 4984%(X100)
2331 16:53:20.931536
2332 16:53:20.931643 ==DQM 1 ==
2333 16:53:20.935323 Final DQM duty delay cell = 4
2334 16:53:20.938273 [4] MAX Duty = 5124%(X100), DQS PI = 50
2335 16:53:20.941299 [4] MIN Duty = 5000%(X100), DQS PI = 32
2336 16:53:20.944909 [4] AVG Duty = 5062%(X100)
2337 16:53:20.944991
2338 16:53:20.948173 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2339 16:53:20.948260
2340 16:53:20.951777 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2341 16:53:20.954965 [DutyScan_Calibration_Flow] ====Done====
2342 16:53:20.955043
2343 16:53:20.958459 [DutyScan_Calibration_Flow] k_type=2
2344 16:53:20.972945
2345 16:53:20.973032 ==DQ 0 ==
2346 16:53:20.976588 Final DQ duty delay cell = -4
2347 16:53:20.979441 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2348 16:53:20.983390 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2349 16:53:20.986503 [-4] AVG Duty = 4969%(X100)
2350 16:53:20.986576
2351 16:53:20.986644 ==DQ 1 ==
2352 16:53:20.989946 Final DQ duty delay cell = -4
2353 16:53:20.992843 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2354 16:53:20.996619 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2355 16:53:20.999680 [-4] AVG Duty = 4938%(X100)
2356 16:53:20.999754
2357 16:53:21.003032 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2358 16:53:21.003103
2359 16:53:21.006092 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2360 16:53:21.009235 [DutyScan_Calibration_Flow] ====Done====
2361 16:53:21.009316 ==
2362 16:53:21.012810 Dram Type= 6, Freq= 0, CH_1, rank 0
2363 16:53:21.015876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2364 16:53:21.015960 ==
2365 16:53:21.019613 [Duty_Offset_Calibration]
2366 16:53:21.019704 B0:1 B1:-2 CA:0
2367 16:53:21.022682
2368 16:53:21.025855 [DutyScan_Calibration_Flow] k_type=0
2369 16:53:21.033476
2370 16:53:21.033550 ==CLK 0==
2371 16:53:21.037168 Final CLK duty delay cell = 0
2372 16:53:21.040427 [0] MAX Duty = 5031%(X100), DQS PI = 18
2373 16:53:21.043565 [0] MIN Duty = 4875%(X100), DQS PI = 58
2374 16:53:21.043687 [0] AVG Duty = 4953%(X100)
2375 16:53:21.046796
2376 16:53:21.050388 CH1 CLK Duty spec in!! Max-Min= 156%
2377 16:53:21.053438 [DutyScan_Calibration_Flow] ====Done====
2378 16:53:21.053531
2379 16:53:21.056878 [DutyScan_Calibration_Flow] k_type=1
2380 16:53:21.072402
2381 16:53:21.072497 ==DQS 0 ==
2382 16:53:21.075680 Final DQS duty delay cell = -4
2383 16:53:21.078595 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2384 16:53:21.082427 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2385 16:53:21.085431 [-4] AVG Duty = 4969%(X100)
2386 16:53:21.085513
2387 16:53:21.085594 ==DQS 1 ==
2388 16:53:21.088829 Final DQS duty delay cell = 0
2389 16:53:21.092298 [0] MAX Duty = 5062%(X100), DQS PI = 0
2390 16:53:21.095311 [0] MIN Duty = 4875%(X100), DQS PI = 26
2391 16:53:21.098823 [0] AVG Duty = 4968%(X100)
2392 16:53:21.098904
2393 16:53:21.102020 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2394 16:53:21.102102
2395 16:53:21.105184 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2396 16:53:21.108366 [DutyScan_Calibration_Flow] ====Done====
2397 16:53:21.108447
2398 16:53:21.111405 [DutyScan_Calibration_Flow] k_type=3
2399 16:53:21.129283
2400 16:53:21.129371 ==DQM 0 ==
2401 16:53:21.132463 Final DQM duty delay cell = 0
2402 16:53:21.135708 [0] MAX Duty = 5000%(X100), DQS PI = 22
2403 16:53:21.138802 [0] MIN Duty = 4844%(X100), DQS PI = 54
2404 16:53:21.142684 [0] AVG Duty = 4922%(X100)
2405 16:53:21.142766
2406 16:53:21.142831 ==DQM 1 ==
2407 16:53:21.145831 Final DQM duty delay cell = 0
2408 16:53:21.148423 [0] MAX Duty = 5031%(X100), DQS PI = 36
2409 16:53:21.152032 [0] MIN Duty = 4907%(X100), DQS PI = 4
2410 16:53:21.155017 [0] AVG Duty = 4969%(X100)
2411 16:53:21.155098
2412 16:53:21.158321 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2413 16:53:21.158403
2414 16:53:21.161867 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2415 16:53:21.164920 [DutyScan_Calibration_Flow] ====Done====
2416 16:53:21.164996
2417 16:53:21.168403 [DutyScan_Calibration_Flow] k_type=2
2418 16:53:21.185203
2419 16:53:21.185295 ==DQ 0 ==
2420 16:53:21.188535 Final DQ duty delay cell = 0
2421 16:53:21.191986 [0] MAX Duty = 5093%(X100), DQS PI = 18
2422 16:53:21.195074 [0] MIN Duty = 4907%(X100), DQS PI = 56
2423 16:53:21.195155 [0] AVG Duty = 5000%(X100)
2424 16:53:21.198666
2425 16:53:21.198746 ==DQ 1 ==
2426 16:53:21.202173 Final DQ duty delay cell = 0
2427 16:53:21.205108 [0] MAX Duty = 5156%(X100), DQS PI = 36
2428 16:53:21.208555 [0] MIN Duty = 4969%(X100), DQS PI = 26
2429 16:53:21.208630 [0] AVG Duty = 5062%(X100)
2430 16:53:21.212027
2431 16:53:21.215306 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2432 16:53:21.215388
2433 16:53:21.218421 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2434 16:53:21.221655 [DutyScan_Calibration_Flow] ====Done====
2435 16:53:21.224716 nWR fixed to 30
2436 16:53:21.228391 [ModeRegInit_LP4] CH0 RK0
2437 16:53:21.228473 [ModeRegInit_LP4] CH0 RK1
2438 16:53:21.231518 [ModeRegInit_LP4] CH1 RK0
2439 16:53:21.234660 [ModeRegInit_LP4] CH1 RK1
2440 16:53:21.234741 match AC timing 7
2441 16:53:21.241596 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2442 16:53:21.244868 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2443 16:53:21.248047 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2444 16:53:21.254061 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2445 16:53:21.257736 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2446 16:53:21.257818 ==
2447 16:53:21.261043 Dram Type= 6, Freq= 0, CH_0, rank 0
2448 16:53:21.264029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2449 16:53:21.264111 ==
2450 16:53:21.270869 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2451 16:53:21.277577 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2452 16:53:21.285411 [CA 0] Center 40 (10~71) winsize 62
2453 16:53:21.288679 [CA 1] Center 40 (10~70) winsize 61
2454 16:53:21.292202 [CA 2] Center 36 (6~66) winsize 61
2455 16:53:21.295120 [CA 3] Center 35 (5~66) winsize 62
2456 16:53:21.298862 [CA 4] Center 34 (4~65) winsize 62
2457 16:53:21.301827 [CA 5] Center 33 (3~64) winsize 62
2458 16:53:21.301908
2459 16:53:21.305316 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2460 16:53:21.305397
2461 16:53:21.308176 [CATrainingPosCal] consider 1 rank data
2462 16:53:21.312006 u2DelayCellTimex100 = 270/100 ps
2463 16:53:21.318384 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2464 16:53:21.321566 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2465 16:53:21.325412 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2466 16:53:21.328498 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2467 16:53:21.331424 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2468 16:53:21.335011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2469 16:53:21.335092
2470 16:53:21.338267 CA PerBit enable=1, Macro0, CA PI delay=33
2471 16:53:21.338348
2472 16:53:21.341455 [CBTSetCACLKResult] CA Dly = 33
2473 16:53:21.345099 CS Dly: 7 (0~38)
2474 16:53:21.345179 ==
2475 16:53:21.348308 Dram Type= 6, Freq= 0, CH_0, rank 1
2476 16:53:21.351437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2477 16:53:21.351519 ==
2478 16:53:21.358305 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2479 16:53:21.361648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2480 16:53:21.371458 [CA 0] Center 40 (10~70) winsize 61
2481 16:53:21.374704 [CA 1] Center 40 (10~70) winsize 61
2482 16:53:21.378515 [CA 2] Center 35 (5~66) winsize 62
2483 16:53:21.381673 [CA 3] Center 35 (5~66) winsize 62
2484 16:53:21.384934 [CA 4] Center 34 (4~65) winsize 62
2485 16:53:21.388302 [CA 5] Center 33 (3~64) winsize 62
2486 16:53:21.388385
2487 16:53:21.391381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2488 16:53:21.391464
2489 16:53:21.394783 [CATrainingPosCal] consider 2 rank data
2490 16:53:21.398218 u2DelayCellTimex100 = 270/100 ps
2491 16:53:21.401134 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2492 16:53:21.408121 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2493 16:53:21.411184 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2494 16:53:21.414630 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2495 16:53:21.417719 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2496 16:53:21.421301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2497 16:53:21.421404
2498 16:53:21.424379 CA PerBit enable=1, Macro0, CA PI delay=33
2499 16:53:21.424462
2500 16:53:21.427926 [CBTSetCACLKResult] CA Dly = 33
2501 16:53:21.431173 CS Dly: 8 (0~40)
2502 16:53:21.431281
2503 16:53:21.434381 ----->DramcWriteLeveling(PI) begin...
2504 16:53:21.434465 ==
2505 16:53:21.438051 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 16:53:21.441063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 16:53:21.441146 ==
2508 16:53:21.444088 Write leveling (Byte 0): 32 => 32
2509 16:53:21.447375 Write leveling (Byte 1): 30 => 30
2510 16:53:21.451155 DramcWriteLeveling(PI) end<-----
2511 16:53:21.451238
2512 16:53:21.451303 ==
2513 16:53:21.454327 Dram Type= 6, Freq= 0, CH_0, rank 0
2514 16:53:21.457295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2515 16:53:21.457378 ==
2516 16:53:21.461064 [Gating] SW mode calibration
2517 16:53:21.467468 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2518 16:53:21.474022 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2519 16:53:21.477355 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2520 16:53:21.480446 0 15 4 | B1->B0 | 2525 3333 | 1 1 | (0 0) (1 1)
2521 16:53:21.487386 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 16:53:21.490563 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 16:53:21.494052 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 16:53:21.500597 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 16:53:21.504070 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 16:53:21.507761 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2527 16:53:21.513672 1 0 0 | B1->B0 | 3131 2828 | 1 1 | (1 1) (1 0)
2528 16:53:21.517097 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2529 16:53:21.520589 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 16:53:21.526874 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 16:53:21.530300 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 16:53:21.533440 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 16:53:21.540266 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 16:53:21.543479 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 16:53:21.546964 1 1 0 | B1->B0 | 2525 3131 | 0 0 | (0 0) (0 0)
2536 16:53:21.553823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 16:53:21.557006 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 16:53:21.560090 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 16:53:21.567091 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 16:53:21.570309 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 16:53:21.573325 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 16:53:21.580144 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2543 16:53:21.583370 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2544 16:53:21.586608 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2545 16:53:21.593507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 16:53:21.596757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 16:53:21.600227 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 16:53:21.606596 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 16:53:21.609855 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 16:53:21.613432 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 16:53:21.620084 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 16:53:21.623473 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 16:53:21.626483 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 16:53:21.632984 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 16:53:21.636554 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 16:53:21.639763 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 16:53:21.646783 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 16:53:21.649682 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2559 16:53:21.652884 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2560 16:53:21.656322 Total UI for P1: 0, mck2ui 16
2561 16:53:21.659944 best dqsien dly found for B0: ( 1, 3, 28)
2562 16:53:21.663010 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2563 16:53:21.670016 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 16:53:21.672667 Total UI for P1: 0, mck2ui 16
2565 16:53:21.676342 best dqsien dly found for B1: ( 1, 4, 2)
2566 16:53:21.679930 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2567 16:53:21.683105 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2568 16:53:21.683180
2569 16:53:21.685994 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2570 16:53:21.689187 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2571 16:53:21.692980 [Gating] SW calibration Done
2572 16:53:21.693053 ==
2573 16:53:21.695951 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 16:53:21.699845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 16:53:21.699919 ==
2576 16:53:21.702872 RX Vref Scan: 0
2577 16:53:21.702944
2578 16:53:21.703022 RX Vref 0 -> 0, step: 1
2579 16:53:21.705950
2580 16:53:21.706027 RX Delay -40 -> 252, step: 8
2581 16:53:21.712783 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2582 16:53:21.715771 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2583 16:53:21.719494 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2584 16:53:21.722388 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2585 16:53:21.725944 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2586 16:53:21.732539 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2587 16:53:21.736141 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2588 16:53:21.738982 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2589 16:53:21.742482 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2590 16:53:21.745699 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2591 16:53:21.752382 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2592 16:53:21.755533 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2593 16:53:21.758748 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2594 16:53:21.762430 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2595 16:53:21.765341 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2596 16:53:21.772156 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2597 16:53:21.772235 ==
2598 16:53:21.775307 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 16:53:21.778448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 16:53:21.778523 ==
2601 16:53:21.778607 DQS Delay:
2602 16:53:21.782069 DQS0 = 0, DQS1 = 0
2603 16:53:21.782142 DQM Delay:
2604 16:53:21.785056 DQM0 = 112, DQM1 = 102
2605 16:53:21.785135 DQ Delay:
2606 16:53:21.788665 DQ0 =111, DQ1 =111, DQ2 =115, DQ3 =107
2607 16:53:21.791800 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2608 16:53:21.795170 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2609 16:53:21.798967 DQ12 =111, DQ13 =107, DQ14 =115, DQ15 =111
2610 16:53:21.799045
2611 16:53:21.799125
2612 16:53:21.802142 ==
2613 16:53:21.805187 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 16:53:21.808767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 16:53:21.808853 ==
2616 16:53:21.808935
2617 16:53:21.809013
2618 16:53:21.811965 TX Vref Scan disable
2619 16:53:21.812038 == TX Byte 0 ==
2620 16:53:21.815097 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2621 16:53:21.821623 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2622 16:53:21.821720 == TX Byte 1 ==
2623 16:53:21.824987 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2624 16:53:21.831463 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2625 16:53:21.831560 ==
2626 16:53:21.834809 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 16:53:21.838552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 16:53:21.838633 ==
2629 16:53:21.850158 TX Vref=22, minBit 13, minWin=25, winSum=416
2630 16:53:21.853926 TX Vref=24, minBit 1, minWin=26, winSum=421
2631 16:53:21.856936 TX Vref=26, minBit 7, minWin=26, winSum=430
2632 16:53:21.860209 TX Vref=28, minBit 14, minWin=26, winSum=434
2633 16:53:21.863800 TX Vref=30, minBit 10, minWin=25, winSum=429
2634 16:53:21.870377 TX Vref=32, minBit 8, minWin=26, winSum=428
2635 16:53:21.873721 [TxChooseVref] Worse bit 14, Min win 26, Win sum 434, Final Vref 28
2636 16:53:21.873802
2637 16:53:21.876901 Final TX Range 1 Vref 28
2638 16:53:21.876982
2639 16:53:21.877046 ==
2640 16:53:21.879842 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 16:53:21.886675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 16:53:21.886756 ==
2643 16:53:21.886820
2644 16:53:21.886878
2645 16:53:21.886935 TX Vref Scan disable
2646 16:53:21.890436 == TX Byte 0 ==
2647 16:53:21.893640 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2648 16:53:21.900445 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2649 16:53:21.900526 == TX Byte 1 ==
2650 16:53:21.903477 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2651 16:53:21.910413 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2652 16:53:21.910495
2653 16:53:21.910560 [DATLAT]
2654 16:53:21.910620 Freq=1200, CH0 RK0
2655 16:53:21.910677
2656 16:53:21.913497 DATLAT Default: 0xd
2657 16:53:21.913587 0, 0xFFFF, sum = 0
2658 16:53:21.917386 1, 0xFFFF, sum = 0
2659 16:53:21.920509 2, 0xFFFF, sum = 0
2660 16:53:21.920591 3, 0xFFFF, sum = 0
2661 16:53:21.923493 4, 0xFFFF, sum = 0
2662 16:53:21.923637 5, 0xFFFF, sum = 0
2663 16:53:21.926704 6, 0xFFFF, sum = 0
2664 16:53:21.926787 7, 0xFFFF, sum = 0
2665 16:53:21.930052 8, 0xFFFF, sum = 0
2666 16:53:21.930135 9, 0xFFFF, sum = 0
2667 16:53:21.933596 10, 0xFFFF, sum = 0
2668 16:53:21.933710 11, 0xFFFF, sum = 0
2669 16:53:21.936789 12, 0x0, sum = 1
2670 16:53:21.936872 13, 0x0, sum = 2
2671 16:53:21.940385 14, 0x0, sum = 3
2672 16:53:21.940468 15, 0x0, sum = 4
2673 16:53:21.943419 best_step = 13
2674 16:53:21.943500
2675 16:53:21.943590 ==
2676 16:53:21.947124 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 16:53:21.949917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 16:53:21.950008 ==
2679 16:53:21.950091 RX Vref Scan: 1
2680 16:53:21.953444
2681 16:53:21.953528 Set Vref Range= 32 -> 127
2682 16:53:21.953667
2683 16:53:21.956898 RX Vref 32 -> 127, step: 1
2684 16:53:21.956978
2685 16:53:21.960289 RX Delay -37 -> 252, step: 4
2686 16:53:21.960364
2687 16:53:21.963459 Set Vref, RX VrefLevel [Byte0]: 32
2688 16:53:21.966755 [Byte1]: 32
2689 16:53:21.966834
2690 16:53:21.970333 Set Vref, RX VrefLevel [Byte0]: 33
2691 16:53:21.973338 [Byte1]: 33
2692 16:53:21.977006
2693 16:53:21.977084 Set Vref, RX VrefLevel [Byte0]: 34
2694 16:53:21.980129 [Byte1]: 34
2695 16:53:21.984991
2696 16:53:21.985071 Set Vref, RX VrefLevel [Byte0]: 35
2697 16:53:21.988130 [Byte1]: 35
2698 16:53:21.993076
2699 16:53:21.993151 Set Vref, RX VrefLevel [Byte0]: 36
2700 16:53:21.996348 [Byte1]: 36
2701 16:53:22.001439
2702 16:53:22.001519 Set Vref, RX VrefLevel [Byte0]: 37
2703 16:53:22.004607 [Byte1]: 37
2704 16:53:22.009268
2705 16:53:22.009408 Set Vref, RX VrefLevel [Byte0]: 38
2706 16:53:22.012429 [Byte1]: 38
2707 16:53:22.017402
2708 16:53:22.017485 Set Vref, RX VrefLevel [Byte0]: 39
2709 16:53:22.020494 [Byte1]: 39
2710 16:53:22.025428
2711 16:53:22.025513 Set Vref, RX VrefLevel [Byte0]: 40
2712 16:53:22.028659 [Byte1]: 40
2713 16:53:22.032995
2714 16:53:22.033080 Set Vref, RX VrefLevel [Byte0]: 41
2715 16:53:22.036448 [Byte1]: 41
2716 16:53:22.041149
2717 16:53:22.041227 Set Vref, RX VrefLevel [Byte0]: 42
2718 16:53:22.044338 [Byte1]: 42
2719 16:53:22.048869
2720 16:53:22.048947 Set Vref, RX VrefLevel [Byte0]: 43
2721 16:53:22.052646 [Byte1]: 43
2722 16:53:22.056969
2723 16:53:22.057045 Set Vref, RX VrefLevel [Byte0]: 44
2724 16:53:22.060919 [Byte1]: 44
2725 16:53:22.065088
2726 16:53:22.065162 Set Vref, RX VrefLevel [Byte0]: 45
2727 16:53:22.068539 [Byte1]: 45
2728 16:53:22.073464
2729 16:53:22.073547 Set Vref, RX VrefLevel [Byte0]: 46
2730 16:53:22.076594 [Byte1]: 46
2731 16:53:22.081355
2732 16:53:22.081436 Set Vref, RX VrefLevel [Byte0]: 47
2733 16:53:22.084353 [Byte1]: 47
2734 16:53:22.089170
2735 16:53:22.089244 Set Vref, RX VrefLevel [Byte0]: 48
2736 16:53:22.092425 [Byte1]: 48
2737 16:53:22.097329
2738 16:53:22.097404 Set Vref, RX VrefLevel [Byte0]: 49
2739 16:53:22.100466 [Byte1]: 49
2740 16:53:22.105319
2741 16:53:22.105393 Set Vref, RX VrefLevel [Byte0]: 50
2742 16:53:22.108346 [Byte1]: 50
2743 16:53:22.113152
2744 16:53:22.113227 Set Vref, RX VrefLevel [Byte0]: 51
2745 16:53:22.116372 [Byte1]: 51
2746 16:53:22.121005
2747 16:53:22.121080 Set Vref, RX VrefLevel [Byte0]: 52
2748 16:53:22.124428 [Byte1]: 52
2749 16:53:22.129592
2750 16:53:22.129666 Set Vref, RX VrefLevel [Byte0]: 53
2751 16:53:22.132527 [Byte1]: 53
2752 16:53:22.136935
2753 16:53:22.137010 Set Vref, RX VrefLevel [Byte0]: 54
2754 16:53:22.143699 [Byte1]: 54
2755 16:53:22.143782
2756 16:53:22.146652 Set Vref, RX VrefLevel [Byte0]: 55
2757 16:53:22.150227 [Byte1]: 55
2758 16:53:22.150314
2759 16:53:22.153622 Set Vref, RX VrefLevel [Byte0]: 56
2760 16:53:22.157166 [Byte1]: 56
2761 16:53:22.161440
2762 16:53:22.161541 Set Vref, RX VrefLevel [Byte0]: 57
2763 16:53:22.164376 [Byte1]: 57
2764 16:53:22.169176
2765 16:53:22.169259 Set Vref, RX VrefLevel [Byte0]: 58
2766 16:53:22.172285 [Byte1]: 58
2767 16:53:22.176945
2768 16:53:22.177023 Set Vref, RX VrefLevel [Byte0]: 59
2769 16:53:22.180505 [Byte1]: 59
2770 16:53:22.184976
2771 16:53:22.185051 Set Vref, RX VrefLevel [Byte0]: 60
2772 16:53:22.188700 [Byte1]: 60
2773 16:53:22.193226
2774 16:53:22.193301 Set Vref, RX VrefLevel [Byte0]: 61
2775 16:53:22.196342 [Byte1]: 61
2776 16:53:22.201300
2777 16:53:22.201374 Set Vref, RX VrefLevel [Byte0]: 62
2778 16:53:22.204507 [Byte1]: 62
2779 16:53:22.208898
2780 16:53:22.208972 Set Vref, RX VrefLevel [Byte0]: 63
2781 16:53:22.212103 [Byte1]: 63
2782 16:53:22.217213
2783 16:53:22.217296 Set Vref, RX VrefLevel [Byte0]: 64
2784 16:53:22.220216 [Byte1]: 64
2785 16:53:22.225308
2786 16:53:22.225383 Set Vref, RX VrefLevel [Byte0]: 65
2787 16:53:22.228386 [Byte1]: 65
2788 16:53:22.233385
2789 16:53:22.233461 Set Vref, RX VrefLevel [Byte0]: 66
2790 16:53:22.236474 [Byte1]: 66
2791 16:53:22.241444
2792 16:53:22.241550 Set Vref, RX VrefLevel [Byte0]: 67
2793 16:53:22.244532 [Byte1]: 67
2794 16:53:22.249258
2795 16:53:22.249339 Set Vref, RX VrefLevel [Byte0]: 68
2796 16:53:22.252464 [Byte1]: 68
2797 16:53:22.256929
2798 16:53:22.257034 Set Vref, RX VrefLevel [Byte0]: 69
2799 16:53:22.260337 [Byte1]: 69
2800 16:53:22.264878
2801 16:53:22.264953 Set Vref, RX VrefLevel [Byte0]: 70
2802 16:53:22.268463 [Byte1]: 70
2803 16:53:22.273295
2804 16:53:22.273373 Set Vref, RX VrefLevel [Byte0]: 71
2805 16:53:22.276771 [Byte1]: 71
2806 16:53:22.280902
2807 16:53:22.280977 Set Vref, RX VrefLevel [Byte0]: 72
2808 16:53:22.284987 [Byte1]: 72
2809 16:53:22.289016
2810 16:53:22.289094 Set Vref, RX VrefLevel [Byte0]: 73
2811 16:53:22.292227 [Byte1]: 73
2812 16:53:22.296999
2813 16:53:22.297097 Set Vref, RX VrefLevel [Byte0]: 74
2814 16:53:22.300601 [Byte1]: 74
2815 16:53:22.305026
2816 16:53:22.308546 Final RX Vref Byte 0 = 60 to rank0
2817 16:53:22.308618 Final RX Vref Byte 1 = 45 to rank0
2818 16:53:22.311588 Final RX Vref Byte 0 = 60 to rank1
2819 16:53:22.314728 Final RX Vref Byte 1 = 45 to rank1==
2820 16:53:22.318408 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 16:53:22.324708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 16:53:22.324785 ==
2823 16:53:22.324848 DQS Delay:
2824 16:53:22.328504 DQS0 = 0, DQS1 = 0
2825 16:53:22.328576 DQM Delay:
2826 16:53:22.328654 DQM0 = 111, DQM1 = 98
2827 16:53:22.331653 DQ Delay:
2828 16:53:22.334859 DQ0 =112, DQ1 =110, DQ2 =110, DQ3 =108
2829 16:53:22.338407 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2830 16:53:22.341583 DQ8 =90, DQ9 =82, DQ10 =100, DQ11 =90
2831 16:53:22.344749 DQ12 =104, DQ13 =104, DQ14 =112, DQ15 =106
2832 16:53:22.344824
2833 16:53:22.344884
2834 16:53:22.354742 [DQSOSCAuto] RK0, (LSB)MR18= 0xfcfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2835 16:53:22.354826 CH0 RK0: MR19=303, MR18=FCFB
2836 16:53:22.361553 CH0_RK0: MR19=0x303, MR18=0xFCFB, DQSOSC=411, MR23=63, INC=38, DEC=25
2837 16:53:22.361632
2838 16:53:22.364538 ----->DramcWriteLeveling(PI) begin...
2839 16:53:22.364612 ==
2840 16:53:22.368038 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 16:53:22.374314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 16:53:22.374403 ==
2843 16:53:22.378108 Write leveling (Byte 0): 31 => 31
2844 16:53:22.378190 Write leveling (Byte 1): 31 => 31
2845 16:53:22.381142 DramcWriteLeveling(PI) end<-----
2846 16:53:22.381223
2847 16:53:22.384604 ==
2848 16:53:22.384685 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 16:53:22.390799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 16:53:22.390880 ==
2851 16:53:22.394387 [Gating] SW mode calibration
2852 16:53:22.401324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 16:53:22.404080 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 16:53:22.410763 0 15 0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2855 16:53:22.414575 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 16:53:22.417626 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 16:53:22.424661 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 16:53:22.427679 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 16:53:22.430880 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 16:53:22.437627 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2861 16:53:22.440851 0 15 28 | B1->B0 | 3434 2626 | 1 1 | (1 1) (1 0)
2862 16:53:22.444228 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 16:53:22.451020 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 16:53:22.454135 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 16:53:22.457364 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 16:53:22.464165 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 16:53:22.467173 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 16:53:22.470784 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2869 16:53:22.477417 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2870 16:53:22.480919 1 1 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2871 16:53:22.483887 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 16:53:22.490246 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 16:53:22.493794 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 16:53:22.497101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 16:53:22.503468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 16:53:22.506915 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 16:53:22.510081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 16:53:22.516646 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 16:53:22.520245 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 16:53:22.523374 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 16:53:22.527067 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 16:53:22.533414 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 16:53:22.537132 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 16:53:22.540211 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 16:53:22.546559 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 16:53:22.550360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 16:53:22.553582 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 16:53:22.559959 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 16:53:22.563077 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 16:53:22.566661 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 16:53:22.573182 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 16:53:22.576185 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 16:53:22.579863 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 16:53:22.586037 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 16:53:22.589631 Total UI for P1: 0, mck2ui 16
2896 16:53:22.593178 best dqsien dly found for B0: ( 1, 3, 28)
2897 16:53:22.596190 Total UI for P1: 0, mck2ui 16
2898 16:53:22.599329 best dqsien dly found for B1: ( 1, 3, 30)
2899 16:53:22.602982 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2900 16:53:22.606345 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2901 16:53:22.606425
2902 16:53:22.609717 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2903 16:53:22.612518 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2904 16:53:22.615993 [Gating] SW calibration Done
2905 16:53:22.616074 ==
2906 16:53:22.619449 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 16:53:22.622535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 16:53:22.622616 ==
2909 16:53:22.625868 RX Vref Scan: 0
2910 16:53:22.625947
2911 16:53:22.626011 RX Vref 0 -> 0, step: 1
2912 16:53:22.629561
2913 16:53:22.629640 RX Delay -40 -> 252, step: 8
2914 16:53:22.635802 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2915 16:53:22.639527 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2916 16:53:22.642726 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2917 16:53:22.645880 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2918 16:53:22.649094 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2919 16:53:22.655945 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2920 16:53:22.659122 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2921 16:53:22.662171 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2922 16:53:22.665971 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2923 16:53:22.668940 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2924 16:53:22.675824 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2925 16:53:22.678916 iDelay=200, Bit 11, Center 91 (16 ~ 167) 152
2926 16:53:22.681994 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2927 16:53:22.685650 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2928 16:53:22.688704 iDelay=200, Bit 14, Center 107 (32 ~ 183) 152
2929 16:53:22.695504 iDelay=200, Bit 15, Center 107 (40 ~ 175) 136
2930 16:53:22.695607 ==
2931 16:53:22.698924 Dram Type= 6, Freq= 0, CH_0, rank 1
2932 16:53:22.701799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2933 16:53:22.701880 ==
2934 16:53:22.701945 DQS Delay:
2935 16:53:22.705476 DQS0 = 0, DQS1 = 0
2936 16:53:22.705557 DQM Delay:
2937 16:53:22.709369 DQM0 = 112, DQM1 = 99
2938 16:53:22.709449 DQ Delay:
2939 16:53:22.712337 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2940 16:53:22.715330 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2941 16:53:22.718695 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =91
2942 16:53:22.722183 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
2943 16:53:22.722287
2944 16:53:22.722362
2945 16:53:22.722423 ==
2946 16:53:22.725786 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 16:53:22.732148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 16:53:22.732230 ==
2949 16:53:22.732295
2950 16:53:22.732389
2951 16:53:22.732445 TX Vref Scan disable
2952 16:53:22.735906 == TX Byte 0 ==
2953 16:53:22.738805 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2954 16:53:22.745422 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2955 16:53:22.745505 == TX Byte 1 ==
2956 16:53:22.748702 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2957 16:53:22.755387 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2958 16:53:22.755470 ==
2959 16:53:22.759338 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 16:53:22.762403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 16:53:22.762484 ==
2962 16:53:22.773352 TX Vref=22, minBit 0, minWin=26, winSum=422
2963 16:53:22.776867 TX Vref=24, minBit 0, minWin=26, winSum=423
2964 16:53:22.780136 TX Vref=26, minBit 0, minWin=27, winSum=435
2965 16:53:22.783780 TX Vref=28, minBit 1, minWin=27, winSum=442
2966 16:53:22.786915 TX Vref=30, minBit 10, minWin=26, winSum=440
2967 16:53:22.790717 TX Vref=32, minBit 1, minWin=27, winSum=440
2968 16:53:22.797467 [TxChooseVref] Worse bit 1, Min win 27, Win sum 442, Final Vref 28
2969 16:53:22.797549
2970 16:53:22.800409 Final TX Range 1 Vref 28
2971 16:53:22.800505
2972 16:53:22.800569 ==
2973 16:53:22.803759 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 16:53:22.806753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 16:53:22.806836 ==
2976 16:53:22.810231
2977 16:53:22.810312
2978 16:53:22.810376 TX Vref Scan disable
2979 16:53:22.813129 == TX Byte 0 ==
2980 16:53:22.816466 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2981 16:53:22.823184 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2982 16:53:22.823267 == TX Byte 1 ==
2983 16:53:22.826796 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2984 16:53:22.832805 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2985 16:53:22.832888
2986 16:53:22.832952 [DATLAT]
2987 16:53:22.833013 Freq=1200, CH0 RK1
2988 16:53:22.833071
2989 16:53:22.836417 DATLAT Default: 0xd
2990 16:53:22.839611 0, 0xFFFF, sum = 0
2991 16:53:22.839695 1, 0xFFFF, sum = 0
2992 16:53:22.843313 2, 0xFFFF, sum = 0
2993 16:53:22.843396 3, 0xFFFF, sum = 0
2994 16:53:22.846657 4, 0xFFFF, sum = 0
2995 16:53:22.846740 5, 0xFFFF, sum = 0
2996 16:53:22.849892 6, 0xFFFF, sum = 0
2997 16:53:22.849976 7, 0xFFFF, sum = 0
2998 16:53:22.853042 8, 0xFFFF, sum = 0
2999 16:53:22.853126 9, 0xFFFF, sum = 0
3000 16:53:22.856358 10, 0xFFFF, sum = 0
3001 16:53:22.856441 11, 0xFFFF, sum = 0
3002 16:53:22.859366 12, 0x0, sum = 1
3003 16:53:22.859448 13, 0x0, sum = 2
3004 16:53:22.863230 14, 0x0, sum = 3
3005 16:53:22.863314 15, 0x0, sum = 4
3006 16:53:22.866339 best_step = 13
3007 16:53:22.866420
3008 16:53:22.866485 ==
3009 16:53:22.869507 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 16:53:22.872838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 16:53:22.872945 ==
3012 16:53:22.873041 RX Vref Scan: 0
3013 16:53:22.876353
3014 16:53:22.876431 RX Vref 0 -> 0, step: 1
3015 16:53:22.876493
3016 16:53:22.879586 RX Delay -37 -> 252, step: 4
3017 16:53:22.886388 iDelay=195, Bit 0, Center 106 (35 ~ 178) 144
3018 16:53:22.889554 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3019 16:53:22.892748 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3020 16:53:22.895878 iDelay=195, Bit 3, Center 110 (39 ~ 182) 144
3021 16:53:22.899789 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3022 16:53:22.905837 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3023 16:53:22.909417 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3024 16:53:22.912819 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3025 16:53:22.915810 iDelay=195, Bit 8, Center 88 (19 ~ 158) 140
3026 16:53:22.919231 iDelay=195, Bit 9, Center 80 (11 ~ 150) 140
3027 16:53:22.922563 iDelay=195, Bit 10, Center 100 (31 ~ 170) 140
3028 16:53:22.929399 iDelay=195, Bit 11, Center 90 (23 ~ 158) 136
3029 16:53:22.932595 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3030 16:53:22.936126 iDelay=195, Bit 13, Center 106 (35 ~ 178) 144
3031 16:53:22.938943 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3032 16:53:22.945859 iDelay=195, Bit 15, Center 108 (39 ~ 178) 140
3033 16:53:22.945941 ==
3034 16:53:22.949391 Dram Type= 6, Freq= 0, CH_0, rank 1
3035 16:53:22.952342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3036 16:53:22.952426 ==
3037 16:53:22.952492 DQS Delay:
3038 16:53:22.955815 DQS0 = 0, DQS1 = 0
3039 16:53:22.955897 DQM Delay:
3040 16:53:22.958727 DQM0 = 110, DQM1 = 99
3041 16:53:22.958815 DQ Delay:
3042 16:53:22.962621 DQ0 =106, DQ1 =110, DQ2 =108, DQ3 =110
3043 16:53:22.965833 DQ4 =110, DQ5 =102, DQ6 =120, DQ7 =120
3044 16:53:22.968864 DQ8 =88, DQ9 =80, DQ10 =100, DQ11 =90
3045 16:53:22.971968 DQ12 =108, DQ13 =106, DQ14 =112, DQ15 =108
3046 16:53:22.972050
3047 16:53:22.972116
3048 16:53:22.982056 [DQSOSCAuto] RK1, (LSB)MR18= 0xff7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 404 ps
3049 16:53:22.985568 CH0 RK1: MR19=403, MR18=FF7
3050 16:53:22.988807 CH0_RK1: MR19=0x403, MR18=0xFF7, DQSOSC=404, MR23=63, INC=40, DEC=26
3051 16:53:22.991797 [RxdqsGatingPostProcess] freq 1200
3052 16:53:22.998677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3053 16:53:23.002009 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 16:53:23.005541 best DQS1 dly(2T, 0.5T) = (0, 12)
3055 16:53:23.008799 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 16:53:23.011812 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3057 16:53:23.015496 best DQS0 dly(2T, 0.5T) = (0, 11)
3058 16:53:23.018322 best DQS1 dly(2T, 0.5T) = (0, 11)
3059 16:53:23.021919 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3060 16:53:23.025106 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3061 16:53:23.025220 Pre-setting of DQS Precalculation
3062 16:53:23.031767 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3063 16:53:23.031879 ==
3064 16:53:23.035415 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 16:53:23.038374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3066 16:53:23.038494 ==
3067 16:53:23.045072 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3068 16:53:23.051488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3069 16:53:23.059270 [CA 0] Center 37 (7~67) winsize 61
3070 16:53:23.062866 [CA 1] Center 37 (7~68) winsize 62
3071 16:53:23.065753 [CA 2] Center 34 (5~64) winsize 60
3072 16:53:23.068821 [CA 3] Center 33 (3~64) winsize 62
3073 16:53:23.072556 [CA 4] Center 34 (4~64) winsize 61
3074 16:53:23.075900 [CA 5] Center 33 (3~63) winsize 61
3075 16:53:23.075971
3076 16:53:23.078849 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3077 16:53:23.078948
3078 16:53:23.082623 [CATrainingPosCal] consider 1 rank data
3079 16:53:23.085631 u2DelayCellTimex100 = 270/100 ps
3080 16:53:23.088706 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3081 16:53:23.095598 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3082 16:53:23.098697 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3083 16:53:23.101885 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3084 16:53:23.105717 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3085 16:53:23.108733 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3086 16:53:23.108856
3087 16:53:23.111997 CA PerBit enable=1, Macro0, CA PI delay=33
3088 16:53:23.112126
3089 16:53:23.115655 [CBTSetCACLKResult] CA Dly = 33
3090 16:53:23.115726 CS Dly: 6 (0~37)
3091 16:53:23.118916 ==
3092 16:53:23.122259 Dram Type= 6, Freq= 0, CH_1, rank 1
3093 16:53:23.125709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 16:53:23.125809 ==
3095 16:53:23.128608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3096 16:53:23.135326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3097 16:53:23.144707 [CA 0] Center 38 (8~68) winsize 61
3098 16:53:23.147914 [CA 1] Center 37 (7~68) winsize 62
3099 16:53:23.151815 [CA 2] Center 34 (4~65) winsize 62
3100 16:53:23.154915 [CA 3] Center 33 (3~64) winsize 62
3101 16:53:23.157691 [CA 4] Center 34 (4~65) winsize 62
3102 16:53:23.161338 [CA 5] Center 32 (2~63) winsize 62
3103 16:53:23.161445
3104 16:53:23.164436 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3105 16:53:23.164510
3106 16:53:23.167862 [CATrainingPosCal] consider 2 rank data
3107 16:53:23.171435 u2DelayCellTimex100 = 270/100 ps
3108 16:53:23.174566 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3109 16:53:23.181320 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3110 16:53:23.184495 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3111 16:53:23.187488 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3112 16:53:23.191143 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3113 16:53:23.194304 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3114 16:53:23.194450
3115 16:53:23.197469 CA PerBit enable=1, Macro0, CA PI delay=33
3116 16:53:23.197560
3117 16:53:23.201474 [CBTSetCACLKResult] CA Dly = 33
3118 16:53:23.204477 CS Dly: 7 (0~40)
3119 16:53:23.204595
3120 16:53:23.207701 ----->DramcWriteLeveling(PI) begin...
3121 16:53:23.207810 ==
3122 16:53:23.210882 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 16:53:23.213965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 16:53:23.214050 ==
3125 16:53:23.217777 Write leveling (Byte 0): 25 => 25
3126 16:53:23.220913 Write leveling (Byte 1): 28 => 28
3127 16:53:23.223997 DramcWriteLeveling(PI) end<-----
3128 16:53:23.224098
3129 16:53:23.224164 ==
3130 16:53:23.227784 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 16:53:23.230783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 16:53:23.230885 ==
3133 16:53:23.234318 [Gating] SW mode calibration
3134 16:53:23.240732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3135 16:53:23.247287 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3136 16:53:23.250334 0 15 0 | B1->B0 | 2e2e 2827 | 0 1 | (0 0) (0 0)
3137 16:53:23.253971 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 16:53:23.260861 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 16:53:23.263745 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 16:53:23.267366 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 16:53:23.273555 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 16:53:23.276743 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 16:53:23.280152 0 15 28 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
3144 16:53:23.286847 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3145 16:53:23.290079 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 16:53:23.293185 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 16:53:23.300454 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 16:53:23.303690 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 16:53:23.306935 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 16:53:23.313850 1 0 24 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
3151 16:53:23.316959 1 0 28 | B1->B0 | 3d3d 3f3f | 0 0 | (1 1) (0 0)
3152 16:53:23.320122 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3153 16:53:23.326311 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 16:53:23.330061 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 16:53:23.333260 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 16:53:23.339872 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 16:53:23.343633 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 16:53:23.346440 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 16:53:23.353362 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3160 16:53:23.356739 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 16:53:23.359998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 16:53:23.366463 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 16:53:23.369878 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 16:53:23.372743 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 16:53:23.379732 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 16:53:23.383198 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 16:53:23.386085 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 16:53:23.393016 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 16:53:23.396270 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 16:53:23.399132 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 16:53:23.406183 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 16:53:23.409126 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 16:53:23.412228 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 16:53:23.419253 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 16:53:23.422343 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3176 16:53:23.426006 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3177 16:53:23.429239 Total UI for P1: 0, mck2ui 16
3178 16:53:23.432251 best dqsien dly found for B1: ( 1, 3, 28)
3179 16:53:23.436169 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 16:53:23.439318 Total UI for P1: 0, mck2ui 16
3181 16:53:23.442419 best dqsien dly found for B0: ( 1, 3, 30)
3182 16:53:23.449132 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3183 16:53:23.451961 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3184 16:53:23.452046
3185 16:53:23.455543 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3186 16:53:23.458572 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3187 16:53:23.462069 [Gating] SW calibration Done
3188 16:53:23.462151 ==
3189 16:53:23.465621 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 16:53:23.469168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 16:53:23.469250 ==
3192 16:53:23.472077 RX Vref Scan: 0
3193 16:53:23.472157
3194 16:53:23.472221 RX Vref 0 -> 0, step: 1
3195 16:53:23.472280
3196 16:53:23.475320 RX Delay -40 -> 252, step: 8
3197 16:53:23.478731 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3198 16:53:23.485601 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3199 16:53:23.488445 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3200 16:53:23.492286 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3201 16:53:23.495288 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3202 16:53:23.498469 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3203 16:53:23.504875 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3204 16:53:23.508706 iDelay=208, Bit 7, Center 111 (40 ~ 183) 144
3205 16:53:23.511857 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3206 16:53:23.514902 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3207 16:53:23.518135 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
3208 16:53:23.524876 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3209 16:53:23.528096 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3210 16:53:23.531248 iDelay=208, Bit 13, Center 111 (40 ~ 183) 144
3211 16:53:23.535030 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3212 16:53:23.538232 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3213 16:53:23.541612 ==
3214 16:53:23.541694 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 16:53:23.548352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 16:53:23.548436 ==
3217 16:53:23.548502 DQS Delay:
3218 16:53:23.551320 DQS0 = 0, DQS1 = 0
3219 16:53:23.551430 DQM Delay:
3220 16:53:23.555027 DQM0 = 114, DQM1 = 106
3221 16:53:23.555099 DQ Delay:
3222 16:53:23.557976 DQ0 =119, DQ1 =111, DQ2 =99, DQ3 =111
3223 16:53:23.561589 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3224 16:53:23.564387 DQ8 =95, DQ9 =99, DQ10 =107, DQ11 =99
3225 16:53:23.568012 DQ12 =115, DQ13 =111, DQ14 =111, DQ15 =111
3226 16:53:23.568094
3227 16:53:23.568158
3228 16:53:23.568218 ==
3229 16:53:23.571173 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 16:53:23.577698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 16:53:23.577780 ==
3232 16:53:23.577872
3233 16:53:23.577978
3234 16:53:23.578037 TX Vref Scan disable
3235 16:53:23.581271 == TX Byte 0 ==
3236 16:53:23.584376 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3237 16:53:23.591120 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3238 16:53:23.591203 == TX Byte 1 ==
3239 16:53:23.594231 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 16:53:23.601275 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 16:53:23.601379 ==
3242 16:53:23.604407 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 16:53:23.607315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 16:53:23.607416 ==
3245 16:53:23.619059 TX Vref=22, minBit 11, minWin=24, winSum=409
3246 16:53:23.622132 TX Vref=24, minBit 8, minWin=24, winSum=412
3247 16:53:23.625423 TX Vref=26, minBit 9, minWin=25, winSum=417
3248 16:53:23.628951 TX Vref=28, minBit 3, minWin=25, winSum=421
3249 16:53:23.632161 TX Vref=30, minBit 9, minWin=25, winSum=423
3250 16:53:23.638987 TX Vref=32, minBit 9, minWin=24, winSum=422
3251 16:53:23.642146 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 30
3252 16:53:23.642227
3253 16:53:23.645529 Final TX Range 1 Vref 30
3254 16:53:23.645637
3255 16:53:23.645729 ==
3256 16:53:23.648794 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 16:53:23.651802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 16:53:23.655126 ==
3259 16:53:23.655232
3260 16:53:23.655324
3261 16:53:23.655419 TX Vref Scan disable
3262 16:53:23.658767 == TX Byte 0 ==
3263 16:53:23.661874 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3264 16:53:23.668569 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3265 16:53:23.668644 == TX Byte 1 ==
3266 16:53:23.671901 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3267 16:53:23.678731 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3268 16:53:23.678804
3269 16:53:23.678875 [DATLAT]
3270 16:53:23.678936 Freq=1200, CH1 RK0
3271 16:53:23.678992
3272 16:53:23.681702 DATLAT Default: 0xd
3273 16:53:23.681769 0, 0xFFFF, sum = 0
3274 16:53:23.685078 1, 0xFFFF, sum = 0
3275 16:53:23.688384 2, 0xFFFF, sum = 0
3276 16:53:23.688483 3, 0xFFFF, sum = 0
3277 16:53:23.692061 4, 0xFFFF, sum = 0
3278 16:53:23.692162 5, 0xFFFF, sum = 0
3279 16:53:23.695123 6, 0xFFFF, sum = 0
3280 16:53:23.695222 7, 0xFFFF, sum = 0
3281 16:53:23.698858 8, 0xFFFF, sum = 0
3282 16:53:23.698942 9, 0xFFFF, sum = 0
3283 16:53:23.701683 10, 0xFFFF, sum = 0
3284 16:53:23.701783 11, 0xFFFF, sum = 0
3285 16:53:23.705478 12, 0x0, sum = 1
3286 16:53:23.705579 13, 0x0, sum = 2
3287 16:53:23.708389 14, 0x0, sum = 3
3288 16:53:23.708488 15, 0x0, sum = 4
3289 16:53:23.712283 best_step = 13
3290 16:53:23.712358
3291 16:53:23.712417 ==
3292 16:53:23.715268 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 16:53:23.718350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 16:53:23.718424 ==
3295 16:53:23.718484 RX Vref Scan: 1
3296 16:53:23.718542
3297 16:53:23.722308 Set Vref Range= 32 -> 127
3298 16:53:23.722375
3299 16:53:23.725381 RX Vref 32 -> 127, step: 1
3300 16:53:23.725475
3301 16:53:23.728492 RX Delay -21 -> 252, step: 4
3302 16:53:23.728561
3303 16:53:23.732050 Set Vref, RX VrefLevel [Byte0]: 32
3304 16:53:23.735282 [Byte1]: 32
3305 16:53:23.735395
3306 16:53:23.738581 Set Vref, RX VrefLevel [Byte0]: 33
3307 16:53:23.741540 [Byte1]: 33
3308 16:53:23.745367
3309 16:53:23.745462 Set Vref, RX VrefLevel [Byte0]: 34
3310 16:53:23.748519 [Byte1]: 34
3311 16:53:23.753362
3312 16:53:23.753468 Set Vref, RX VrefLevel [Byte0]: 35
3313 16:53:23.756602 [Byte1]: 35
3314 16:53:23.761289
3315 16:53:23.761392 Set Vref, RX VrefLevel [Byte0]: 36
3316 16:53:23.764499 [Byte1]: 36
3317 16:53:23.768851
3318 16:53:23.768949 Set Vref, RX VrefLevel [Byte0]: 37
3319 16:53:23.772564 [Byte1]: 37
3320 16:53:23.777118
3321 16:53:23.777211 Set Vref, RX VrefLevel [Byte0]: 38
3322 16:53:23.780091 [Byte1]: 38
3323 16:53:23.784968
3324 16:53:23.785047 Set Vref, RX VrefLevel [Byte0]: 39
3325 16:53:23.788353 [Byte1]: 39
3326 16:53:23.793062
3327 16:53:23.793162 Set Vref, RX VrefLevel [Byte0]: 40
3328 16:53:23.795988 [Byte1]: 40
3329 16:53:23.800977
3330 16:53:23.801078 Set Vref, RX VrefLevel [Byte0]: 41
3331 16:53:23.803934 [Byte1]: 41
3332 16:53:23.808961
3333 16:53:23.809062 Set Vref, RX VrefLevel [Byte0]: 42
3334 16:53:23.811773 [Byte1]: 42
3335 16:53:23.816543
3336 16:53:23.816618 Set Vref, RX VrefLevel [Byte0]: 43
3337 16:53:23.820044 [Byte1]: 43
3338 16:53:23.824570
3339 16:53:23.824669 Set Vref, RX VrefLevel [Byte0]: 44
3340 16:53:23.827733 [Byte1]: 44
3341 16:53:23.832516
3342 16:53:23.832616 Set Vref, RX VrefLevel [Byte0]: 45
3343 16:53:23.835617 [Byte1]: 45
3344 16:53:23.840106
3345 16:53:23.840205 Set Vref, RX VrefLevel [Byte0]: 46
3346 16:53:23.843985 [Byte1]: 46
3347 16:53:23.848216
3348 16:53:23.848316 Set Vref, RX VrefLevel [Byte0]: 47
3349 16:53:23.851317 [Byte1]: 47
3350 16:53:23.856345
3351 16:53:23.856445 Set Vref, RX VrefLevel [Byte0]: 48
3352 16:53:23.859300 [Byte1]: 48
3353 16:53:23.864097
3354 16:53:23.864174 Set Vref, RX VrefLevel [Byte0]: 49
3355 16:53:23.867159 [Byte1]: 49
3356 16:53:23.872220
3357 16:53:23.872299 Set Vref, RX VrefLevel [Byte0]: 50
3358 16:53:23.875323 [Byte1]: 50
3359 16:53:23.880053
3360 16:53:23.880128 Set Vref, RX VrefLevel [Byte0]: 51
3361 16:53:23.883084 [Byte1]: 51
3362 16:53:23.887734
3363 16:53:23.887814 Set Vref, RX VrefLevel [Byte0]: 52
3364 16:53:23.891013 [Byte1]: 52
3365 16:53:23.895854
3366 16:53:23.895935 Set Vref, RX VrefLevel [Byte0]: 53
3367 16:53:23.899370 [Byte1]: 53
3368 16:53:23.903422
3369 16:53:23.903528 Set Vref, RX VrefLevel [Byte0]: 54
3370 16:53:23.907169 [Byte1]: 54
3371 16:53:23.911390
3372 16:53:23.911466 Set Vref, RX VrefLevel [Byte0]: 55
3373 16:53:23.914964 [Byte1]: 55
3374 16:53:23.919874
3375 16:53:23.919954 Set Vref, RX VrefLevel [Byte0]: 56
3376 16:53:23.922925 [Byte1]: 56
3377 16:53:23.927250
3378 16:53:23.927330 Set Vref, RX VrefLevel [Byte0]: 57
3379 16:53:23.930793 [Byte1]: 57
3380 16:53:23.935319
3381 16:53:23.935399 Set Vref, RX VrefLevel [Byte0]: 58
3382 16:53:23.938399 [Byte1]: 58
3383 16:53:23.943423
3384 16:53:23.943503 Set Vref, RX VrefLevel [Byte0]: 59
3385 16:53:23.946618 [Byte1]: 59
3386 16:53:23.951510
3387 16:53:23.951597 Set Vref, RX VrefLevel [Byte0]: 60
3388 16:53:23.954744 [Byte1]: 60
3389 16:53:23.958998
3390 16:53:23.959078 Set Vref, RX VrefLevel [Byte0]: 61
3391 16:53:23.962201 [Byte1]: 61
3392 16:53:23.966826
3393 16:53:23.966906 Set Vref, RX VrefLevel [Byte0]: 62
3394 16:53:23.970451 [Byte1]: 62
3395 16:53:23.974802
3396 16:53:23.974882 Set Vref, RX VrefLevel [Byte0]: 63
3397 16:53:23.978557 [Byte1]: 63
3398 16:53:23.982866
3399 16:53:23.982946 Final RX Vref Byte 0 = 51 to rank0
3400 16:53:23.985983 Final RX Vref Byte 1 = 50 to rank0
3401 16:53:23.989403 Final RX Vref Byte 0 = 51 to rank1
3402 16:53:23.992750 Final RX Vref Byte 1 = 50 to rank1==
3403 16:53:23.996096 Dram Type= 6, Freq= 0, CH_1, rank 0
3404 16:53:24.002443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3405 16:53:24.002526 ==
3406 16:53:24.002591 DQS Delay:
3407 16:53:24.002650 DQS0 = 0, DQS1 = 0
3408 16:53:24.006052 DQM Delay:
3409 16:53:24.006132 DQM0 = 114, DQM1 = 105
3410 16:53:24.009620 DQ Delay:
3411 16:53:24.012738 DQ0 =120, DQ1 =108, DQ2 =104, DQ3 =112
3412 16:53:24.015785 DQ4 =112, DQ5 =122, DQ6 =126, DQ7 =112
3413 16:53:24.019215 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3414 16:53:24.022688 DQ12 =112, DQ13 =110, DQ14 =116, DQ15 =110
3415 16:53:24.022769
3416 16:53:24.022833
3417 16:53:24.032774 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3418 16:53:24.032862 CH1 RK0: MR19=303, MR18=F0F7
3419 16:53:24.039012 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3420 16:53:24.039094
3421 16:53:24.042292 ----->DramcWriteLeveling(PI) begin...
3422 16:53:24.042374 ==
3423 16:53:24.046170 Dram Type= 6, Freq= 0, CH_1, rank 1
3424 16:53:24.052582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 16:53:24.052664 ==
3426 16:53:24.055756 Write leveling (Byte 0): 25 => 25
3427 16:53:24.055838 Write leveling (Byte 1): 28 => 28
3428 16:53:24.058846 DramcWriteLeveling(PI) end<-----
3429 16:53:24.058926
3430 16:53:24.061988 ==
3431 16:53:24.062068 Dram Type= 6, Freq= 0, CH_1, rank 1
3432 16:53:24.068655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 16:53:24.068750 ==
3434 16:53:24.072101 [Gating] SW mode calibration
3435 16:53:24.079039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3436 16:53:24.082205 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3437 16:53:24.088550 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3438 16:53:24.092451 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 16:53:24.095458 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 16:53:24.101853 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 16:53:24.105136 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 16:53:24.108754 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 16:53:24.115681 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
3444 16:53:24.118454 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
3445 16:53:24.121630 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 16:53:24.128304 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 16:53:24.131413 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 16:53:24.134797 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 16:53:24.141856 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 16:53:24.144912 1 0 20 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3451 16:53:24.148139 1 0 24 | B1->B0 | 2f2f 4545 | 0 0 | (1 1) (0 0)
3452 16:53:24.154999 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 16:53:24.158144 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 16:53:24.161389 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 16:53:24.168325 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 16:53:24.171498 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 16:53:24.174916 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 16:53:24.181718 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 16:53:24.184711 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3460 16:53:24.188423 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3461 16:53:24.194857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 16:53:24.197964 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 16:53:24.201561 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 16:53:24.204783 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 16:53:24.211059 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 16:53:24.214706 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 16:53:24.217651 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 16:53:24.224293 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 16:53:24.228055 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 16:53:24.231181 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 16:53:24.237834 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 16:53:24.241292 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 16:53:24.244123 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 16:53:24.250885 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 16:53:24.254051 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 16:53:24.257166 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3477 16:53:24.261009 Total UI for P1: 0, mck2ui 16
3478 16:53:24.264192 best dqsien dly found for B0: ( 1, 3, 24)
3479 16:53:24.270558 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 16:53:24.273714 Total UI for P1: 0, mck2ui 16
3481 16:53:24.277374 best dqsien dly found for B1: ( 1, 3, 26)
3482 16:53:24.280437 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3483 16:53:24.283945 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3484 16:53:24.284021
3485 16:53:24.287192 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3486 16:53:24.290288 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3487 16:53:24.293466 [Gating] SW calibration Done
3488 16:53:24.293535 ==
3489 16:53:24.297152 Dram Type= 6, Freq= 0, CH_1, rank 1
3490 16:53:24.300273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3491 16:53:24.300347 ==
3492 16:53:24.303444 RX Vref Scan: 0
3493 16:53:24.303540
3494 16:53:24.306996 RX Vref 0 -> 0, step: 1
3495 16:53:24.307066
3496 16:53:24.307126 RX Delay -40 -> 252, step: 8
3497 16:53:24.313151 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3498 16:53:24.316766 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3499 16:53:24.320259 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3500 16:53:24.323102 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3501 16:53:24.326730 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3502 16:53:24.333205 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3503 16:53:24.336563 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3504 16:53:24.339561 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3505 16:53:24.342751 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3506 16:53:24.346157 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3507 16:53:24.353289 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3508 16:53:24.356157 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3509 16:53:24.360047 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3510 16:53:24.363265 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3511 16:53:24.369546 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3512 16:53:24.373174 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3513 16:53:24.373249 ==
3514 16:53:24.376286 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 16:53:24.379427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 16:53:24.379525 ==
3517 16:53:24.379656 DQS Delay:
3518 16:53:24.383151 DQS0 = 0, DQS1 = 0
3519 16:53:24.383221 DQM Delay:
3520 16:53:24.386174 DQM0 = 110, DQM1 = 108
3521 16:53:24.386248 DQ Delay:
3522 16:53:24.389702 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3523 16:53:24.392778 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3524 16:53:24.396053 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3525 16:53:24.402719 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3526 16:53:24.402800
3527 16:53:24.402863
3528 16:53:24.402920 ==
3529 16:53:24.405935 Dram Type= 6, Freq= 0, CH_1, rank 1
3530 16:53:24.409127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3531 16:53:24.409195 ==
3532 16:53:24.409256
3533 16:53:24.409312
3534 16:53:24.412362 TX Vref Scan disable
3535 16:53:24.412432 == TX Byte 0 ==
3536 16:53:24.419371 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 16:53:24.422317 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 16:53:24.422388 == TX Byte 1 ==
3539 16:53:24.429087 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3540 16:53:24.432526 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3541 16:53:24.432596 ==
3542 16:53:24.435646 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 16:53:24.439106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 16:53:24.439207 ==
3545 16:53:24.451898 TX Vref=22, minBit 9, minWin=25, winSum=426
3546 16:53:24.454874 TX Vref=24, minBit 9, minWin=25, winSum=428
3547 16:53:24.458333 TX Vref=26, minBit 8, minWin=26, winSum=432
3548 16:53:24.461494 TX Vref=28, minBit 8, minWin=26, winSum=433
3549 16:53:24.465184 TX Vref=30, minBit 8, minWin=26, winSum=436
3550 16:53:24.471896 TX Vref=32, minBit 8, minWin=25, winSum=430
3551 16:53:24.474900 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 30
3552 16:53:24.474983
3553 16:53:24.478027 Final TX Range 1 Vref 30
3554 16:53:24.478111
3555 16:53:24.478194 ==
3556 16:53:24.481330 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 16:53:24.484365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 16:53:24.488069 ==
3559 16:53:24.488151
3560 16:53:24.488234
3561 16:53:24.488313 TX Vref Scan disable
3562 16:53:24.491688 == TX Byte 0 ==
3563 16:53:24.494759 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 16:53:24.501070 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 16:53:24.501153 == TX Byte 1 ==
3566 16:53:24.504776 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3567 16:53:24.511099 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3568 16:53:24.511182
3569 16:53:24.511269 [DATLAT]
3570 16:53:24.511348 Freq=1200, CH1 RK1
3571 16:53:24.511425
3572 16:53:24.514689 DATLAT Default: 0xd
3573 16:53:24.517839 0, 0xFFFF, sum = 0
3574 16:53:24.517923 1, 0xFFFF, sum = 0
3575 16:53:24.521022 2, 0xFFFF, sum = 0
3576 16:53:24.521106 3, 0xFFFF, sum = 0
3577 16:53:24.524183 4, 0xFFFF, sum = 0
3578 16:53:24.524267 5, 0xFFFF, sum = 0
3579 16:53:24.527744 6, 0xFFFF, sum = 0
3580 16:53:24.527827 7, 0xFFFF, sum = 0
3581 16:53:24.530839 8, 0xFFFF, sum = 0
3582 16:53:24.530923 9, 0xFFFF, sum = 0
3583 16:53:24.534489 10, 0xFFFF, sum = 0
3584 16:53:24.534573 11, 0xFFFF, sum = 0
3585 16:53:24.537440 12, 0x0, sum = 1
3586 16:53:24.537524 13, 0x0, sum = 2
3587 16:53:24.540506 14, 0x0, sum = 3
3588 16:53:24.540590 15, 0x0, sum = 4
3589 16:53:24.544016 best_step = 13
3590 16:53:24.544098
3591 16:53:24.544180 ==
3592 16:53:24.547400 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 16:53:24.550331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 16:53:24.550415 ==
3595 16:53:24.553944 RX Vref Scan: 0
3596 16:53:24.554028
3597 16:53:24.554112 RX Vref 0 -> 0, step: 1
3598 16:53:24.554191
3599 16:53:24.557134 RX Delay -21 -> 252, step: 4
3600 16:53:24.563668 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3601 16:53:24.566974 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3602 16:53:24.570176 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3603 16:53:24.573818 iDelay=195, Bit 3, Center 106 (35 ~ 178) 144
3604 16:53:24.579891 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3605 16:53:24.583745 iDelay=195, Bit 5, Center 118 (47 ~ 190) 144
3606 16:53:24.586919 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3607 16:53:24.589879 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3608 16:53:24.593546 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3609 16:53:24.599759 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3610 16:53:24.603016 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3611 16:53:24.606691 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3612 16:53:24.609624 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3613 16:53:24.613401 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3614 16:53:24.619787 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3615 16:53:24.622883 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3616 16:53:24.622964 ==
3617 16:53:24.626120 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 16:53:24.629810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 16:53:24.629893 ==
3620 16:53:24.632845 DQS Delay:
3621 16:53:24.632925 DQS0 = 0, DQS1 = 0
3622 16:53:24.632989 DQM Delay:
3623 16:53:24.636086 DQM0 = 110, DQM1 = 109
3624 16:53:24.636168 DQ Delay:
3625 16:53:24.639182 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =106
3626 16:53:24.645807 DQ4 =108, DQ5 =118, DQ6 =120, DQ7 =108
3627 16:53:24.649622 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3628 16:53:24.652781 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =116
3629 16:53:24.652863
3630 16:53:24.652927
3631 16:53:24.658976 [DQSOSCAuto] RK1, (LSB)MR18= 0xfa0a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3632 16:53:24.662470 CH1 RK1: MR19=304, MR18=FA0A
3633 16:53:24.668913 CH1_RK1: MR19=0x304, MR18=0xFA0A, DQSOSC=406, MR23=63, INC=39, DEC=26
3634 16:53:24.672781 [RxdqsGatingPostProcess] freq 1200
3635 16:53:24.679042 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3636 16:53:24.681933 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 16:53:24.682015 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 16:53:24.685581 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 16:53:24.688686 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 16:53:24.691810 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 16:53:24.695540 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 16:53:24.698594 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 16:53:24.701714 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 16:53:24.705372 Pre-setting of DQS Precalculation
3645 16:53:24.711517 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3646 16:53:24.718649 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3647 16:53:24.724768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3648 16:53:24.724851
3649 16:53:24.724914
3650 16:53:24.727979 [Calibration Summary] 2400 Mbps
3651 16:53:24.728060 CH 0, Rank 0
3652 16:53:24.731684 SW Impedance : PASS
3653 16:53:24.734629 DUTY Scan : NO K
3654 16:53:24.734713 ZQ Calibration : PASS
3655 16:53:24.738231 Jitter Meter : NO K
3656 16:53:24.741537 CBT Training : PASS
3657 16:53:24.741618 Write leveling : PASS
3658 16:53:24.744653 RX DQS gating : PASS
3659 16:53:24.748292 RX DQ/DQS(RDDQC) : PASS
3660 16:53:24.748374 TX DQ/DQS : PASS
3661 16:53:24.750946 RX DATLAT : PASS
3662 16:53:24.754689 RX DQ/DQS(Engine): PASS
3663 16:53:24.754771 TX OE : NO K
3664 16:53:24.757591 All Pass.
3665 16:53:24.757671
3666 16:53:24.757736 CH 0, Rank 1
3667 16:53:24.760627 SW Impedance : PASS
3668 16:53:24.760709 DUTY Scan : NO K
3669 16:53:24.764145 ZQ Calibration : PASS
3670 16:53:24.767536 Jitter Meter : NO K
3671 16:53:24.767639 CBT Training : PASS
3672 16:53:24.770619 Write leveling : PASS
3673 16:53:24.774056 RX DQS gating : PASS
3674 16:53:24.774138 RX DQ/DQS(RDDQC) : PASS
3675 16:53:24.777631 TX DQ/DQS : PASS
3676 16:53:24.780375 RX DATLAT : PASS
3677 16:53:24.780455 RX DQ/DQS(Engine): PASS
3678 16:53:24.784120 TX OE : NO K
3679 16:53:24.784202 All Pass.
3680 16:53:24.784266
3681 16:53:24.787021 CH 1, Rank 0
3682 16:53:24.787101 SW Impedance : PASS
3683 16:53:24.790495 DUTY Scan : NO K
3684 16:53:24.793696 ZQ Calibration : PASS
3685 16:53:24.793777 Jitter Meter : NO K
3686 16:53:24.797008 CBT Training : PASS
3687 16:53:24.800243 Write leveling : PASS
3688 16:53:24.800324 RX DQS gating : PASS
3689 16:53:24.803942 RX DQ/DQS(RDDQC) : PASS
3690 16:53:24.804024 TX DQ/DQS : PASS
3691 16:53:24.807014 RX DATLAT : PASS
3692 16:53:24.810085 RX DQ/DQS(Engine): PASS
3693 16:53:24.810166 TX OE : NO K
3694 16:53:24.813752 All Pass.
3695 16:53:24.813833
3696 16:53:24.813935 CH 1, Rank 1
3697 16:53:24.816821 SW Impedance : PASS
3698 16:53:24.819984 DUTY Scan : NO K
3699 16:53:24.820065 ZQ Calibration : PASS
3700 16:53:24.823143 Jitter Meter : NO K
3701 16:53:24.826345 CBT Training : PASS
3702 16:53:24.826426 Write leveling : PASS
3703 16:53:24.829454 RX DQS gating : PASS
3704 16:53:24.829535 RX DQ/DQS(RDDQC) : PASS
3705 16:53:24.833188 TX DQ/DQS : PASS
3706 16:53:24.836308 RX DATLAT : PASS
3707 16:53:24.836389 RX DQ/DQS(Engine): PASS
3708 16:53:24.839504 TX OE : NO K
3709 16:53:24.839611 All Pass.
3710 16:53:24.839722
3711 16:53:24.843192 DramC Write-DBI off
3712 16:53:24.846203 PER_BANK_REFRESH: Hybrid Mode
3713 16:53:24.846284 TX_TRACKING: ON
3714 16:53:24.856240 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3715 16:53:24.859346 [FAST_K] Save calibration result to emmc
3716 16:53:24.862571 dramc_set_vcore_voltage set vcore to 650000
3717 16:53:24.866200 Read voltage for 600, 5
3718 16:53:24.866282 Vio18 = 0
3719 16:53:24.869324 Vcore = 650000
3720 16:53:24.869408 Vdram = 0
3721 16:53:24.869512 Vddq = 0
3722 16:53:24.869598 Vmddr = 0
3723 16:53:24.875775 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3724 16:53:24.882766 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3725 16:53:24.882848 MEM_TYPE=3, freq_sel=19
3726 16:53:24.885569 sv_algorithm_assistance_LP4_1600
3727 16:53:24.889312 ============ PULL DRAM RESETB DOWN ============
3728 16:53:24.895724 ========== PULL DRAM RESETB DOWN end =========
3729 16:53:24.898628 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3730 16:53:24.902028 ===================================
3731 16:53:24.905663 LPDDR4 DRAM CONFIGURATION
3732 16:53:24.908557 ===================================
3733 16:53:24.908639 EX_ROW_EN[0] = 0x0
3734 16:53:24.912087 EX_ROW_EN[1] = 0x0
3735 16:53:24.915230 LP4Y_EN = 0x0
3736 16:53:24.915310 WORK_FSP = 0x0
3737 16:53:24.918916 WL = 0x2
3738 16:53:24.918998 RL = 0x2
3739 16:53:24.922188 BL = 0x2
3740 16:53:24.922268 RPST = 0x0
3741 16:53:24.925382 RD_PRE = 0x0
3742 16:53:24.925463 WR_PRE = 0x1
3743 16:53:24.928469 WR_PST = 0x0
3744 16:53:24.928551 DBI_WR = 0x0
3745 16:53:24.931616 DBI_RD = 0x0
3746 16:53:24.931713 OTF = 0x1
3747 16:53:24.934952 ===================================
3748 16:53:24.938542 ===================================
3749 16:53:24.941700 ANA top config
3750 16:53:24.945148 ===================================
3751 16:53:24.945229 DLL_ASYNC_EN = 0
3752 16:53:24.948394 ALL_SLAVE_EN = 1
3753 16:53:24.951477 NEW_RANK_MODE = 1
3754 16:53:24.955129 DLL_IDLE_MODE = 1
3755 16:53:24.958125 LP45_APHY_COMB_EN = 1
3756 16:53:24.958207 TX_ODT_DIS = 1
3757 16:53:24.961280 NEW_8X_MODE = 1
3758 16:53:24.965231 ===================================
3759 16:53:24.968296 ===================================
3760 16:53:24.971425 data_rate = 1200
3761 16:53:24.974349 CKR = 1
3762 16:53:24.978105 DQ_P2S_RATIO = 8
3763 16:53:24.981295 ===================================
3764 16:53:24.984520 CA_P2S_RATIO = 8
3765 16:53:24.984602 DQ_CA_OPEN = 0
3766 16:53:24.987513 DQ_SEMI_OPEN = 0
3767 16:53:24.991382 CA_SEMI_OPEN = 0
3768 16:53:24.994376 CA_FULL_RATE = 0
3769 16:53:24.997769 DQ_CKDIV4_EN = 1
3770 16:53:25.001365 CA_CKDIV4_EN = 1
3771 16:53:25.001448 CA_PREDIV_EN = 0
3772 16:53:25.004347 PH8_DLY = 0
3773 16:53:25.007560 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3774 16:53:25.011099 DQ_AAMCK_DIV = 4
3775 16:53:25.014238 CA_AAMCK_DIV = 4
3776 16:53:25.017439 CA_ADMCK_DIV = 4
3777 16:53:25.017522 DQ_TRACK_CA_EN = 0
3778 16:53:25.020878 CA_PICK = 600
3779 16:53:25.023964 CA_MCKIO = 600
3780 16:53:25.027884 MCKIO_SEMI = 0
3781 16:53:25.030990 PLL_FREQ = 2288
3782 16:53:25.034053 DQ_UI_PI_RATIO = 32
3783 16:53:25.037365 CA_UI_PI_RATIO = 0
3784 16:53:25.040447 ===================================
3785 16:53:25.044180 ===================================
3786 16:53:25.044263 memory_type:LPDDR4
3787 16:53:25.047037 GP_NUM : 10
3788 16:53:25.050832 SRAM_EN : 1
3789 16:53:25.050914 MD32_EN : 0
3790 16:53:25.053795 ===================================
3791 16:53:25.056855 [ANA_INIT] >>>>>>>>>>>>>>
3792 16:53:25.060512 <<<<<< [CONFIGURE PHASE]: ANA_TX
3793 16:53:25.063495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3794 16:53:25.066855 ===================================
3795 16:53:25.070022 data_rate = 1200,PCW = 0X5800
3796 16:53:25.073717 ===================================
3797 16:53:25.076666 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3798 16:53:25.080056 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 16:53:25.086405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 16:53:25.093209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3801 16:53:25.096810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3802 16:53:25.099566 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3803 16:53:25.099687 [ANA_INIT] flow start
3804 16:53:25.102872 [ANA_INIT] PLL >>>>>>>>
3805 16:53:25.106537 [ANA_INIT] PLL <<<<<<<<
3806 16:53:25.106619 [ANA_INIT] MIDPI >>>>>>>>
3807 16:53:25.109438 [ANA_INIT] MIDPI <<<<<<<<
3808 16:53:25.113153 [ANA_INIT] DLL >>>>>>>>
3809 16:53:25.113235 [ANA_INIT] flow end
3810 16:53:25.119544 ============ LP4 DIFF to SE enter ============
3811 16:53:25.122557 ============ LP4 DIFF to SE exit ============
3812 16:53:25.125897 [ANA_INIT] <<<<<<<<<<<<<
3813 16:53:25.129592 [Flow] Enable top DCM control >>>>>
3814 16:53:25.132719 [Flow] Enable top DCM control <<<<<
3815 16:53:25.132802 Enable DLL master slave shuffle
3816 16:53:25.138908 ==============================================================
3817 16:53:25.142687 Gating Mode config
3818 16:53:25.145849 ==============================================================
3819 16:53:25.149139 Config description:
3820 16:53:25.158726 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3821 16:53:25.165496 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3822 16:53:25.168593 SELPH_MODE 0: By rank 1: By Phase
3823 16:53:25.175361 ==============================================================
3824 16:53:25.178650 GAT_TRACK_EN = 1
3825 16:53:25.181698 RX_GATING_MODE = 2
3826 16:53:25.185380 RX_GATING_TRACK_MODE = 2
3827 16:53:25.188565 SELPH_MODE = 1
3828 16:53:25.191743 PICG_EARLY_EN = 1
3829 16:53:25.194881 VALID_LAT_VALUE = 1
3830 16:53:25.198138 ==============================================================
3831 16:53:25.201813 Enter into Gating configuration >>>>
3832 16:53:25.204746 Exit from Gating configuration <<<<
3833 16:53:25.208320 Enter into DVFS_PRE_config >>>>>
3834 16:53:25.221702 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3835 16:53:25.221788 Exit from DVFS_PRE_config <<<<<
3836 16:53:25.224598 Enter into PICG configuration >>>>
3837 16:53:25.228049 Exit from PICG configuration <<<<
3838 16:53:25.231447 [RX_INPUT] configuration >>>>>
3839 16:53:25.234951 [RX_INPUT] configuration <<<<<
3840 16:53:25.241314 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3841 16:53:25.244433 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3842 16:53:25.251330 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 16:53:25.257467 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 16:53:25.264329 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 16:53:25.271293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 16:53:25.274410 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3847 16:53:25.277555 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3848 16:53:25.281201 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3849 16:53:25.287330 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3850 16:53:25.290437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3851 16:53:25.294158 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3852 16:53:25.297281 ===================================
3853 16:53:25.300389 LPDDR4 DRAM CONFIGURATION
3854 16:53:25.304134 ===================================
3855 16:53:25.307290 EX_ROW_EN[0] = 0x0
3856 16:53:25.307372 EX_ROW_EN[1] = 0x0
3857 16:53:25.310383 LP4Y_EN = 0x0
3858 16:53:25.310465 WORK_FSP = 0x0
3859 16:53:25.313806 WL = 0x2
3860 16:53:25.313887 RL = 0x2
3861 16:53:25.316788 BL = 0x2
3862 16:53:25.316869 RPST = 0x0
3863 16:53:25.320223 RD_PRE = 0x0
3864 16:53:25.320304 WR_PRE = 0x1
3865 16:53:25.323724 WR_PST = 0x0
3866 16:53:25.323806 DBI_WR = 0x0
3867 16:53:25.326648 DBI_RD = 0x0
3868 16:53:25.330153 OTF = 0x1
3869 16:53:25.330235 ===================================
3870 16:53:25.336711 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3871 16:53:25.340273 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3872 16:53:25.343465 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3873 16:53:25.346968 ===================================
3874 16:53:25.350124 LPDDR4 DRAM CONFIGURATION
3875 16:53:25.353313 ===================================
3876 16:53:25.356935 EX_ROW_EN[0] = 0x10
3877 16:53:25.357017 EX_ROW_EN[1] = 0x0
3878 16:53:25.359899 LP4Y_EN = 0x0
3879 16:53:25.359980 WORK_FSP = 0x0
3880 16:53:25.362884 WL = 0x2
3881 16:53:25.362966 RL = 0x2
3882 16:53:25.366710 BL = 0x2
3883 16:53:25.366791 RPST = 0x0
3884 16:53:25.369954 RD_PRE = 0x0
3885 16:53:25.370035 WR_PRE = 0x1
3886 16:53:25.373002 WR_PST = 0x0
3887 16:53:25.373084 DBI_WR = 0x0
3888 16:53:25.376254 DBI_RD = 0x0
3889 16:53:25.379999 OTF = 0x1
3890 16:53:25.383146 ===================================
3891 16:53:25.386364 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3892 16:53:25.391237 nWR fixed to 30
3893 16:53:25.394812 [ModeRegInit_LP4] CH0 RK0
3894 16:53:25.394893 [ModeRegInit_LP4] CH0 RK1
3895 16:53:25.397986 [ModeRegInit_LP4] CH1 RK0
3896 16:53:25.401173 [ModeRegInit_LP4] CH1 RK1
3897 16:53:25.401255 match AC timing 17
3898 16:53:25.408054 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3899 16:53:25.411100 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3900 16:53:25.414288 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3901 16:53:25.420823 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3902 16:53:25.424474 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3903 16:53:25.424555 ==
3904 16:53:25.427470 Dram Type= 6, Freq= 0, CH_0, rank 0
3905 16:53:25.431053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3906 16:53:25.434391 ==
3907 16:53:25.437298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3908 16:53:25.443731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3909 16:53:25.447094 [CA 0] Center 37 (7~67) winsize 61
3910 16:53:25.450638 [CA 1] Center 37 (7~67) winsize 61
3911 16:53:25.453676 [CA 2] Center 35 (5~65) winsize 61
3912 16:53:25.457202 [CA 3] Center 35 (5~65) winsize 61
3913 16:53:25.460544 [CA 4] Center 34 (4~64) winsize 61
3914 16:53:25.463422 [CA 5] Center 34 (4~64) winsize 61
3915 16:53:25.463504
3916 16:53:25.466766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3917 16:53:25.466847
3918 16:53:25.470605 [CATrainingPosCal] consider 1 rank data
3919 16:53:25.473762 u2DelayCellTimex100 = 270/100 ps
3920 16:53:25.476726 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3921 16:53:25.479968 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3922 16:53:25.486871 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3923 16:53:25.489932 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3924 16:53:25.492931 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3925 16:53:25.496679 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3926 16:53:25.496761
3927 16:53:25.500324 CA PerBit enable=1, Macro0, CA PI delay=34
3928 16:53:25.500437
3929 16:53:25.503625 [CBTSetCACLKResult] CA Dly = 34
3930 16:53:25.503709 CS Dly: 4 (0~35)
3931 16:53:25.503773 ==
3932 16:53:25.506871 Dram Type= 6, Freq= 0, CH_0, rank 1
3933 16:53:25.513268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 16:53:25.513350 ==
3935 16:53:25.516340 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 16:53:25.523137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3937 16:53:25.526822 [CA 0] Center 37 (7~67) winsize 61
3938 16:53:25.529828 [CA 1] Center 36 (6~67) winsize 62
3939 16:53:25.532999 [CA 2] Center 35 (5~65) winsize 61
3940 16:53:25.536716 [CA 3] Center 35 (5~65) winsize 61
3941 16:53:25.539720 [CA 4] Center 34 (4~65) winsize 62
3942 16:53:25.543250 [CA 5] Center 33 (3~64) winsize 62
3943 16:53:25.543332
3944 16:53:25.546616 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3945 16:53:25.546698
3946 16:53:25.549798 [CATrainingPosCal] consider 2 rank data
3947 16:53:25.552714 u2DelayCellTimex100 = 270/100 ps
3948 16:53:25.559480 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3949 16:53:25.563219 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3950 16:53:25.566026 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3951 16:53:25.569180 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3952 16:53:25.572751 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
3953 16:53:25.575986 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3954 16:53:25.576067
3955 16:53:25.579040 CA PerBit enable=1, Macro0, CA PI delay=34
3956 16:53:25.579122
3957 16:53:25.582621 [CBTSetCACLKResult] CA Dly = 34
3958 16:53:25.585795 CS Dly: 5 (0~38)
3959 16:53:25.585876
3960 16:53:25.588968 ----->DramcWriteLeveling(PI) begin...
3961 16:53:25.589052 ==
3962 16:53:25.592583 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 16:53:25.595867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 16:53:25.595950 ==
3965 16:53:25.598848 Write leveling (Byte 0): 32 => 32
3966 16:53:25.602526 Write leveling (Byte 1): 32 => 32
3967 16:53:25.605682 DramcWriteLeveling(PI) end<-----
3968 16:53:25.605764
3969 16:53:25.605829 ==
3970 16:53:25.608754 Dram Type= 6, Freq= 0, CH_0, rank 0
3971 16:53:25.612017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3972 16:53:25.612098 ==
3973 16:53:25.615652 [Gating] SW mode calibration
3974 16:53:25.621879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3975 16:53:25.628775 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3976 16:53:25.631671 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 16:53:25.638583 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 16:53:25.641760 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 16:53:25.645466 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3980 16:53:25.651541 0 9 16 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 0)
3981 16:53:25.655042 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 16:53:25.658070 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 16:53:25.664828 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 16:53:25.668283 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 16:53:25.671392 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 16:53:25.678112 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 16:53:25.681182 0 10 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3988 16:53:25.685043 0 10 16 | B1->B0 | 3131 3b3b | 0 0 | (1 1) (0 0)
3989 16:53:25.690991 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 16:53:25.694304 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 16:53:25.697921 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 16:53:25.704262 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 16:53:25.707776 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 16:53:25.710966 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 16:53:25.717675 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 16:53:25.720921 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3997 16:53:25.724078 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 16:53:25.731055 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 16:53:25.733988 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 16:53:25.737535 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 16:53:25.743809 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 16:53:25.747522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 16:53:25.750734 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 16:53:25.757319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 16:53:25.760345 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 16:53:25.763883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 16:53:25.770485 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 16:53:25.773789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 16:53:25.777364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 16:53:25.783411 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 16:53:25.786626 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 16:53:25.790068 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4013 16:53:25.796844 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 16:53:25.796951 Total UI for P1: 0, mck2ui 16
4015 16:53:25.800072 best dqsien dly found for B0: ( 0, 13, 16)
4016 16:53:25.803247 Total UI for P1: 0, mck2ui 16
4017 16:53:25.806240 best dqsien dly found for B1: ( 0, 13, 18)
4018 16:53:25.813038 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4019 16:53:25.816100 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4020 16:53:25.816173
4021 16:53:25.819940 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 16:53:25.822994 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4023 16:53:25.826107 [Gating] SW calibration Done
4024 16:53:25.826210 ==
4025 16:53:25.829347 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 16:53:25.833512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 16:53:25.833590 ==
4028 16:53:25.835953 RX Vref Scan: 0
4029 16:53:25.836027
4030 16:53:25.836093 RX Vref 0 -> 0, step: 1
4031 16:53:25.836153
4032 16:53:25.839550 RX Delay -230 -> 252, step: 16
4033 16:53:25.845761 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4034 16:53:25.849329 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4035 16:53:25.852521 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4036 16:53:25.855735 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4037 16:53:25.859394 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4038 16:53:25.865735 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4039 16:53:25.869027 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4040 16:53:25.872054 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4041 16:53:25.875643 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4042 16:53:25.882068 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4043 16:53:25.885471 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4044 16:53:25.889025 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4045 16:53:25.892089 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4046 16:53:25.898949 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4047 16:53:25.902459 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4048 16:53:25.905379 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4049 16:53:25.905478 ==
4050 16:53:25.908614 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 16:53:25.912338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 16:53:25.915149 ==
4053 16:53:25.915229 DQS Delay:
4054 16:53:25.915292 DQS0 = 0, DQS1 = 0
4055 16:53:25.918884 DQM Delay:
4056 16:53:25.918965 DQM0 = 37, DQM1 = 29
4057 16:53:25.922248 DQ Delay:
4058 16:53:25.925291 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4059 16:53:25.925373 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4060 16:53:25.928375 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4061 16:53:25.932094 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4062 16:53:25.935000
4063 16:53:25.935080
4064 16:53:25.935144 ==
4065 16:53:25.938150 Dram Type= 6, Freq= 0, CH_0, rank 0
4066 16:53:25.941949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4067 16:53:25.942032 ==
4068 16:53:25.942096
4069 16:53:25.942156
4070 16:53:25.944879 TX Vref Scan disable
4071 16:53:25.944991 == TX Byte 0 ==
4072 16:53:25.951418 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4073 16:53:25.955257 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4074 16:53:25.955361 == TX Byte 1 ==
4075 16:53:25.961700 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4076 16:53:25.964814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4077 16:53:25.964896 ==
4078 16:53:25.967942 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 16:53:25.971525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 16:53:25.971644 ==
4081 16:53:25.971718
4082 16:53:25.974565
4083 16:53:25.974677 TX Vref Scan disable
4084 16:53:25.978242 == TX Byte 0 ==
4085 16:53:25.981091 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4086 16:53:25.987925 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4087 16:53:25.988007 == TX Byte 1 ==
4088 16:53:25.991278 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4089 16:53:25.997751 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4090 16:53:25.997833
4091 16:53:25.997897 [DATLAT]
4092 16:53:25.997958 Freq=600, CH0 RK0
4093 16:53:25.998016
4094 16:53:26.001504 DATLAT Default: 0x9
4095 16:53:26.004520 0, 0xFFFF, sum = 0
4096 16:53:26.004603 1, 0xFFFF, sum = 0
4097 16:53:26.007468 2, 0xFFFF, sum = 0
4098 16:53:26.007584 3, 0xFFFF, sum = 0
4099 16:53:26.010943 4, 0xFFFF, sum = 0
4100 16:53:26.011025 5, 0xFFFF, sum = 0
4101 16:53:26.014445 6, 0xFFFF, sum = 0
4102 16:53:26.014527 7, 0xFFFF, sum = 0
4103 16:53:26.017501 8, 0x0, sum = 1
4104 16:53:26.017583 9, 0x0, sum = 2
4105 16:53:26.021222 10, 0x0, sum = 3
4106 16:53:26.021308 11, 0x0, sum = 4
4107 16:53:26.021399 best_step = 9
4108 16:53:26.021478
4109 16:53:26.023770 ==
4110 16:53:26.027622 Dram Type= 6, Freq= 0, CH_0, rank 0
4111 16:53:26.030802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4112 16:53:26.030909 ==
4113 16:53:26.031002 RX Vref Scan: 1
4114 16:53:26.031090
4115 16:53:26.033849 RX Vref 0 -> 0, step: 1
4116 16:53:26.033943
4117 16:53:26.037551 RX Delay -195 -> 252, step: 8
4118 16:53:26.037632
4119 16:53:26.040654 Set Vref, RX VrefLevel [Byte0]: 60
4120 16:53:26.043747 [Byte1]: 45
4121 16:53:26.043829
4122 16:53:26.046897 Final RX Vref Byte 0 = 60 to rank0
4123 16:53:26.050439 Final RX Vref Byte 1 = 45 to rank0
4124 16:53:26.054158 Final RX Vref Byte 0 = 60 to rank1
4125 16:53:26.057294 Final RX Vref Byte 1 = 45 to rank1==
4126 16:53:26.060407 Dram Type= 6, Freq= 0, CH_0, rank 0
4127 16:53:26.066823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4128 16:53:26.066905 ==
4129 16:53:26.066970 DQS Delay:
4130 16:53:26.067030 DQS0 = 0, DQS1 = 0
4131 16:53:26.070067 DQM Delay:
4132 16:53:26.070147 DQM0 = 34, DQM1 = 28
4133 16:53:26.073699 DQ Delay:
4134 16:53:26.076839 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4135 16:53:26.080024 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4136 16:53:26.083587 DQ8 =20, DQ9 =16, DQ10 =24, DQ11 =24
4137 16:53:26.086658 DQ12 =32, DQ13 =32, DQ14 =40, DQ15 =40
4138 16:53:26.086739
4139 16:53:26.086802
4140 16:53:26.093079 [DQSOSCAuto] RK0, (LSB)MR18= 0x3b3a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
4141 16:53:26.096480 CH0 RK0: MR19=808, MR18=3B3A
4142 16:53:26.103374 CH0_RK0: MR19=0x808, MR18=0x3B3A, DQSOSC=398, MR23=63, INC=165, DEC=110
4143 16:53:26.103455
4144 16:53:26.106267 ----->DramcWriteLeveling(PI) begin...
4145 16:53:26.106376 ==
4146 16:53:26.109690 Dram Type= 6, Freq= 0, CH_0, rank 1
4147 16:53:26.112790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 16:53:26.112872 ==
4149 16:53:26.116535 Write leveling (Byte 0): 33 => 33
4150 16:53:26.119586 Write leveling (Byte 1): 29 => 29
4151 16:53:26.123174 DramcWriteLeveling(PI) end<-----
4152 16:53:26.123254
4153 16:53:26.123317 ==
4154 16:53:26.125957 Dram Type= 6, Freq= 0, CH_0, rank 1
4155 16:53:26.129561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 16:53:26.132837 ==
4157 16:53:26.132917 [Gating] SW mode calibration
4158 16:53:26.142445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4159 16:53:26.146266 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4160 16:53:26.149372 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 16:53:26.155893 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 16:53:26.159070 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 16:53:26.162849 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
4164 16:53:26.169207 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
4165 16:53:26.172199 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 16:53:26.176003 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 16:53:26.182222 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 16:53:26.185279 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 16:53:26.188935 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 16:53:26.195208 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 16:53:26.198892 0 10 12 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
4172 16:53:26.201848 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4173 16:53:26.208297 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 16:53:26.211790 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 16:53:26.214994 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 16:53:26.221529 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 16:53:26.224980 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 16:53:26.228287 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 16:53:26.234515 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4180 16:53:26.238098 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 16:53:26.241265 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 16:53:26.248042 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 16:53:26.251201 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 16:53:26.254381 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 16:53:26.261079 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 16:53:26.264995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 16:53:26.267884 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 16:53:26.274194 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 16:53:26.277305 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 16:53:26.281212 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 16:53:26.287844 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 16:53:26.291023 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 16:53:26.294583 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 16:53:26.300738 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 16:53:26.304109 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4196 16:53:26.307044 Total UI for P1: 0, mck2ui 16
4197 16:53:26.310735 best dqsien dly found for B0: ( 0, 13, 10)
4198 16:53:26.313727 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4199 16:53:26.320851 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 16:53:26.323723 Total UI for P1: 0, mck2ui 16
4201 16:53:26.327321 best dqsien dly found for B1: ( 0, 13, 16)
4202 16:53:26.330395 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4203 16:53:26.333986 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4204 16:53:26.334068
4205 16:53:26.337003 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4206 16:53:26.339808 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4207 16:53:26.343393 [Gating] SW calibration Done
4208 16:53:26.343475 ==
4209 16:53:26.346742 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 16:53:26.349690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 16:53:26.349772 ==
4212 16:53:26.353101 RX Vref Scan: 0
4213 16:53:26.353183
4214 16:53:26.356192 RX Vref 0 -> 0, step: 1
4215 16:53:26.356273
4216 16:53:26.359870 RX Delay -230 -> 252, step: 16
4217 16:53:26.362884 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4218 16:53:26.366088 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4219 16:53:26.369194 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4220 16:53:26.375966 iDelay=218, Bit 3, Center 25 (-150 ~ 201) 352
4221 16:53:26.379535 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4222 16:53:26.382785 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4223 16:53:26.385758 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4224 16:53:26.389236 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4225 16:53:26.396089 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4226 16:53:26.399333 iDelay=218, Bit 9, Center 9 (-150 ~ 169) 320
4227 16:53:26.402446 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4228 16:53:26.406067 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4229 16:53:26.412144 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4230 16:53:26.415750 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4231 16:53:26.418674 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4232 16:53:26.422362 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4233 16:53:26.425678 ==
4234 16:53:26.428975 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 16:53:26.431943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 16:53:26.432025 ==
4237 16:53:26.432089 DQS Delay:
4238 16:53:26.435473 DQS0 = 0, DQS1 = 0
4239 16:53:26.435569 DQM Delay:
4240 16:53:26.438408 DQM0 = 38, DQM1 = 31
4241 16:53:26.438505 DQ Delay:
4242 16:53:26.441595 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =25
4243 16:53:26.445125 DQ4 =41, DQ5 =17, DQ6 =49, DQ7 =49
4244 16:53:26.448755 DQ8 =17, DQ9 =9, DQ10 =41, DQ11 =17
4245 16:53:26.451704 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4246 16:53:26.451786
4247 16:53:26.451851
4248 16:53:26.451912 ==
4249 16:53:26.455461 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 16:53:26.458123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 16:53:26.458207 ==
4252 16:53:26.458273
4253 16:53:26.458333
4254 16:53:26.461741 TX Vref Scan disable
4255 16:53:26.464850 == TX Byte 0 ==
4256 16:53:26.467952 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4257 16:53:26.471501 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4258 16:53:26.474622 == TX Byte 1 ==
4259 16:53:26.478451 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4260 16:53:26.481550 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4261 16:53:26.481632 ==
4262 16:53:26.484697 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 16:53:26.491018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 16:53:26.491101 ==
4265 16:53:26.491182
4266 16:53:26.491251
4267 16:53:26.491311 TX Vref Scan disable
4268 16:53:26.495836 == TX Byte 0 ==
4269 16:53:26.499146 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4270 16:53:26.505966 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4271 16:53:26.506076 == TX Byte 1 ==
4272 16:53:26.508919 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4273 16:53:26.515568 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4274 16:53:26.515716
4275 16:53:26.515790 [DATLAT]
4276 16:53:26.515852 Freq=600, CH0 RK1
4277 16:53:26.515911
4278 16:53:26.519081 DATLAT Default: 0x9
4279 16:53:26.519170 0, 0xFFFF, sum = 0
4280 16:53:26.522528 1, 0xFFFF, sum = 0
4281 16:53:26.525516 2, 0xFFFF, sum = 0
4282 16:53:26.525612 3, 0xFFFF, sum = 0
4283 16:53:26.528669 4, 0xFFFF, sum = 0
4284 16:53:26.528755 5, 0xFFFF, sum = 0
4285 16:53:26.532334 6, 0xFFFF, sum = 0
4286 16:53:26.532419 7, 0xFFFF, sum = 0
4287 16:53:26.535352 8, 0x0, sum = 1
4288 16:53:26.535436 9, 0x0, sum = 2
4289 16:53:26.538340 10, 0x0, sum = 3
4290 16:53:26.538424 11, 0x0, sum = 4
4291 16:53:26.538496 best_step = 9
4292 16:53:26.538557
4293 16:53:26.541877 ==
4294 16:53:26.545346 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 16:53:26.548379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 16:53:26.548469 ==
4297 16:53:26.548535 RX Vref Scan: 0
4298 16:53:26.548595
4299 16:53:26.551932 RX Vref 0 -> 0, step: 1
4300 16:53:26.552016
4301 16:53:26.554829 RX Delay -195 -> 252, step: 8
4302 16:53:26.561685 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4303 16:53:26.564771 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4304 16:53:26.568485 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4305 16:53:26.571571 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4306 16:53:26.575217 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4307 16:53:26.581455 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4308 16:53:26.584501 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4309 16:53:26.588449 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4310 16:53:26.591479 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4311 16:53:26.597698 iDelay=205, Bit 9, Center 12 (-139 ~ 164) 304
4312 16:53:26.601269 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4313 16:53:26.604445 iDelay=205, Bit 11, Center 16 (-139 ~ 172) 312
4314 16:53:26.607496 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4315 16:53:26.614510 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4316 16:53:26.617593 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4317 16:53:26.620997 iDelay=205, Bit 15, Center 32 (-123 ~ 188) 312
4318 16:53:26.621072 ==
4319 16:53:26.623970 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 16:53:26.631050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 16:53:26.631147 ==
4322 16:53:26.631210 DQS Delay:
4323 16:53:26.631270 DQS0 = 0, DQS1 = 0
4324 16:53:26.634249 DQM Delay:
4325 16:53:26.634353 DQM0 = 34, DQM1 = 27
4326 16:53:26.637290 DQ Delay:
4327 16:53:26.640722 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4328 16:53:26.644263 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4329 16:53:26.647831 DQ8 =16, DQ9 =12, DQ10 =32, DQ11 =16
4330 16:53:26.650691 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =32
4331 16:53:26.650759
4332 16:53:26.650819
4333 16:53:26.657046 [DQSOSCAuto] RK1, (LSB)MR18= 0x6938, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4334 16:53:26.660776 CH0 RK1: MR19=808, MR18=6938
4335 16:53:26.667062 CH0_RK1: MR19=0x808, MR18=0x6938, DQSOSC=390, MR23=63, INC=172, DEC=114
4336 16:53:26.670654 [RxdqsGatingPostProcess] freq 600
4337 16:53:26.673719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 16:53:26.676751 Pre-setting of DQS Precalculation
4339 16:53:26.683539 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 16:53:26.683636 ==
4341 16:53:26.686580 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 16:53:26.690310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 16:53:26.690386 ==
4344 16:53:26.696647 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 16:53:26.703130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4346 16:53:26.707146 [CA 0] Center 36 (6~66) winsize 61
4347 16:53:26.710364 [CA 1] Center 35 (5~66) winsize 62
4348 16:53:26.713474 [CA 2] Center 34 (4~65) winsize 62
4349 16:53:26.716638 [CA 3] Center 34 (4~65) winsize 62
4350 16:53:26.719806 [CA 4] Center 34 (4~65) winsize 62
4351 16:53:26.722891 [CA 5] Center 33 (3~64) winsize 62
4352 16:53:26.722958
4353 16:53:26.726467 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4354 16:53:26.726537
4355 16:53:26.730171 [CATrainingPosCal] consider 1 rank data
4356 16:53:26.733038 u2DelayCellTimex100 = 270/100 ps
4357 16:53:26.736070 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4358 16:53:26.739284 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4359 16:53:26.743065 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 16:53:26.745958 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4361 16:53:26.749146 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 16:53:26.752495 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4363 16:53:26.755933
4364 16:53:26.759362 CA PerBit enable=1, Macro0, CA PI delay=33
4365 16:53:26.759464
4366 16:53:26.762388 [CBTSetCACLKResult] CA Dly = 33
4367 16:53:26.762495 CS Dly: 4 (0~35)
4368 16:53:26.762585 ==
4369 16:53:26.765883 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 16:53:26.769011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 16:53:26.772373 ==
4372 16:53:26.775765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 16:53:26.782133 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4374 16:53:26.785441 [CA 0] Center 36 (6~66) winsize 61
4375 16:53:26.788599 [CA 1] Center 36 (6~66) winsize 61
4376 16:53:26.791931 [CA 2] Center 34 (4~65) winsize 62
4377 16:53:26.795555 [CA 3] Center 34 (3~65) winsize 63
4378 16:53:26.798773 [CA 4] Center 34 (4~65) winsize 62
4379 16:53:26.801785 [CA 5] Center 33 (3~64) winsize 62
4380 16:53:26.801855
4381 16:53:26.805635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4382 16:53:26.805706
4383 16:53:26.808724 [CATrainingPosCal] consider 2 rank data
4384 16:53:26.811720 u2DelayCellTimex100 = 270/100 ps
4385 16:53:26.815027 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4386 16:53:26.818826 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4387 16:53:26.825298 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 16:53:26.828151 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 16:53:26.831738 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 16:53:26.834899 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 16:53:26.834969
4392 16:53:26.838309 CA PerBit enable=1, Macro0, CA PI delay=33
4393 16:53:26.838380
4394 16:53:26.841792 [CBTSetCACLKResult] CA Dly = 33
4395 16:53:26.841860 CS Dly: 4 (0~36)
4396 16:53:26.841927
4397 16:53:26.844863 ----->DramcWriteLeveling(PI) begin...
4398 16:53:26.848116 ==
4399 16:53:26.851566 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 16:53:26.854926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 16:53:26.855011 ==
4402 16:53:26.857842 Write leveling (Byte 0): 27 => 27
4403 16:53:26.861560 Write leveling (Byte 1): 32 => 32
4404 16:53:26.864939 DramcWriteLeveling(PI) end<-----
4405 16:53:26.865019
4406 16:53:26.865080 ==
4407 16:53:26.867747 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 16:53:26.871324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 16:53:26.871403 ==
4410 16:53:26.874433 [Gating] SW mode calibration
4411 16:53:26.881433 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 16:53:26.887616 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 16:53:26.890794 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 16:53:26.894623 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 16:53:26.900912 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 16:53:26.903878 0 9 12 | B1->B0 | 3131 3232 | 0 1 | (0 1) (1 1)
4417 16:53:26.907756 0 9 16 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4418 16:53:26.913727 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 16:53:26.917731 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 16:53:26.920636 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 16:53:26.927153 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 16:53:26.930137 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 16:53:26.933892 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 16:53:26.940092 0 10 12 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
4425 16:53:26.943564 0 10 16 | B1->B0 | 4040 4040 | 0 1 | (0 0) (0 0)
4426 16:53:26.946637 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 16:53:26.953608 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 16:53:26.956710 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 16:53:26.960315 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 16:53:26.966493 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 16:53:26.970008 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 16:53:26.973586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4433 16:53:26.979830 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4434 16:53:26.983859 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 16:53:26.986708 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 16:53:26.993146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 16:53:26.996814 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 16:53:26.999913 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 16:53:27.006736 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 16:53:27.009937 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 16:53:27.013095 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 16:53:27.019379 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 16:53:27.022486 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 16:53:27.025770 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 16:53:27.032563 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 16:53:27.036482 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 16:53:27.039307 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 16:53:27.045715 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4449 16:53:27.049137 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 16:53:27.052660 Total UI for P1: 0, mck2ui 16
4451 16:53:27.055707 best dqsien dly found for B0: ( 0, 13, 12)
4452 16:53:27.058958 Total UI for P1: 0, mck2ui 16
4453 16:53:27.062600 best dqsien dly found for B1: ( 0, 13, 12)
4454 16:53:27.065827 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4455 16:53:27.068973 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 16:53:27.069056
4457 16:53:27.072279 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 16:53:27.075692 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 16:53:27.079059 [Gating] SW calibration Done
4460 16:53:27.079142 ==
4461 16:53:27.081920 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 16:53:27.088773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 16:53:27.088855 ==
4464 16:53:27.088919 RX Vref Scan: 0
4465 16:53:27.088980
4466 16:53:27.092306 RX Vref 0 -> 0, step: 1
4467 16:53:27.092387
4468 16:53:27.095270 RX Delay -230 -> 252, step: 16
4469 16:53:27.098575 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4470 16:53:27.101615 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4471 16:53:27.105256 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4472 16:53:27.111406 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4473 16:53:27.114761 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4474 16:53:27.117898 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4475 16:53:27.121570 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4476 16:53:27.127789 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4477 16:53:27.131322 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4478 16:53:27.134422 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4479 16:53:27.137610 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4480 16:53:27.144553 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4481 16:53:27.147754 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4482 16:53:27.150898 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4483 16:53:27.154681 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4484 16:53:27.160694 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4485 16:53:27.160780 ==
4486 16:53:27.164092 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 16:53:27.167799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 16:53:27.167883 ==
4489 16:53:27.167948 DQS Delay:
4490 16:53:27.170948 DQS0 = 0, DQS1 = 0
4491 16:53:27.171029 DQM Delay:
4492 16:53:27.174121 DQM0 = 38, DQM1 = 28
4493 16:53:27.174230 DQ Delay:
4494 16:53:27.177159 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4495 16:53:27.180554 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4496 16:53:27.184025 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4497 16:53:27.187454 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4498 16:53:27.187536
4499 16:53:27.187665
4500 16:53:27.187742 ==
4501 16:53:27.190787 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 16:53:27.193706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 16:53:27.197066 ==
4504 16:53:27.197148
4505 16:53:27.197214
4506 16:53:27.197274 TX Vref Scan disable
4507 16:53:27.200628 == TX Byte 0 ==
4508 16:53:27.203544 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4509 16:53:27.207110 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4510 16:53:27.210678 == TX Byte 1 ==
4511 16:53:27.214154 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4512 16:53:27.217188 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4513 16:53:27.220488 ==
4514 16:53:27.223606 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 16:53:27.227109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 16:53:27.227211 ==
4517 16:53:27.227313
4518 16:53:27.227412
4519 16:53:27.230288 TX Vref Scan disable
4520 16:53:27.233562 == TX Byte 0 ==
4521 16:53:27.236561 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4522 16:53:27.240269 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4523 16:53:27.243387 == TX Byte 1 ==
4524 16:53:27.246609 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4525 16:53:27.249789 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4526 16:53:27.249889
4527 16:53:27.249996 [DATLAT]
4528 16:53:27.252984 Freq=600, CH1 RK0
4529 16:53:27.253084
4530 16:53:27.256732 DATLAT Default: 0x9
4531 16:53:27.256834 0, 0xFFFF, sum = 0
4532 16:53:27.259924 1, 0xFFFF, sum = 0
4533 16:53:27.260027 2, 0xFFFF, sum = 0
4534 16:53:27.262980 3, 0xFFFF, sum = 0
4535 16:53:27.263082 4, 0xFFFF, sum = 0
4536 16:53:27.266705 5, 0xFFFF, sum = 0
4537 16:53:27.266807 6, 0xFFFF, sum = 0
4538 16:53:27.269537 7, 0xFFFF, sum = 0
4539 16:53:27.269621 8, 0x0, sum = 1
4540 16:53:27.272978 9, 0x0, sum = 2
4541 16:53:27.273060 10, 0x0, sum = 3
4542 16:53:27.276203 11, 0x0, sum = 4
4543 16:53:27.276285 best_step = 9
4544 16:53:27.276349
4545 16:53:27.276408 ==
4546 16:53:27.279337 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 16:53:27.282899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 16:53:27.282981 ==
4549 16:53:27.286042 RX Vref Scan: 1
4550 16:53:27.286122
4551 16:53:27.289221 RX Vref 0 -> 0, step: 1
4552 16:53:27.289302
4553 16:53:27.289365 RX Delay -195 -> 252, step: 8
4554 16:53:27.292755
4555 16:53:27.292838 Set Vref, RX VrefLevel [Byte0]: 51
4556 16:53:27.295712 [Byte1]: 50
4557 16:53:27.300936
4558 16:53:27.301018 Final RX Vref Byte 0 = 51 to rank0
4559 16:53:27.304524 Final RX Vref Byte 1 = 50 to rank0
4560 16:53:27.307493 Final RX Vref Byte 0 = 51 to rank1
4561 16:53:27.311254 Final RX Vref Byte 1 = 50 to rank1==
4562 16:53:27.314208 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 16:53:27.320934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 16:53:27.321016 ==
4565 16:53:27.321080 DQS Delay:
4566 16:53:27.321140 DQS0 = 0, DQS1 = 0
4567 16:53:27.324484 DQM Delay:
4568 16:53:27.324565 DQM0 = 36, DQM1 = 28
4569 16:53:27.327483 DQ Delay:
4570 16:53:27.330606 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =36
4571 16:53:27.333904 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4572 16:53:27.337537 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4573 16:53:27.340635 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4574 16:53:27.340715
4575 16:53:27.340777
4576 16:53:27.347016 [DQSOSCAuto] RK0, (LSB)MR18= 0x222e, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 403 ps
4577 16:53:27.350672 CH1 RK0: MR19=808, MR18=222E
4578 16:53:27.357096 CH1_RK0: MR19=0x808, MR18=0x222E, DQSOSC=401, MR23=63, INC=163, DEC=108
4579 16:53:27.357246
4580 16:53:27.360341 ----->DramcWriteLeveling(PI) begin...
4581 16:53:27.360426 ==
4582 16:53:27.363410 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 16:53:27.366694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 16:53:27.366776 ==
4585 16:53:27.370409 Write leveling (Byte 0): 29 => 29
4586 16:53:27.373293 Write leveling (Byte 1): 29 => 29
4587 16:53:27.376911 DramcWriteLeveling(PI) end<-----
4588 16:53:27.376992
4589 16:53:27.377056 ==
4590 16:53:27.380434 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 16:53:27.383479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 16:53:27.386481 ==
4593 16:53:27.386562 [Gating] SW mode calibration
4594 16:53:27.396507 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 16:53:27.399481 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 16:53:27.403091 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 16:53:27.409750 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 16:53:27.412651 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4599 16:53:27.416290 0 9 12 | B1->B0 | 3030 2a2a | 0 0 | (0 1) (0 0)
4600 16:53:27.423280 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4601 16:53:27.426305 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 16:53:27.429774 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 16:53:27.435951 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 16:53:27.439011 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 16:53:27.442569 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 16:53:27.449502 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4607 16:53:27.452528 0 10 12 | B1->B0 | 3333 4040 | 0 0 | (0 0) (0 0)
4608 16:53:27.455810 0 10 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
4609 16:53:27.462383 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 16:53:27.465470 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 16:53:27.468668 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 16:53:27.475155 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 16:53:27.478653 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 16:53:27.482107 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 16:53:27.488453 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 16:53:27.491926 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4617 16:53:27.495369 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 16:53:27.502165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 16:53:27.505362 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 16:53:27.508836 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 16:53:27.514850 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 16:53:27.518287 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 16:53:27.521800 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 16:53:27.528543 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 16:53:27.531507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 16:53:27.535131 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 16:53:27.541252 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 16:53:27.545053 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 16:53:27.548046 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 16:53:27.554345 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 16:53:27.557724 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4632 16:53:27.561374 Total UI for P1: 0, mck2ui 16
4633 16:53:27.564531 best dqsien dly found for B0: ( 0, 13, 10)
4634 16:53:27.567814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 16:53:27.570787 Total UI for P1: 0, mck2ui 16
4636 16:53:27.574642 best dqsien dly found for B1: ( 0, 13, 14)
4637 16:53:27.577631 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4638 16:53:27.584150 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4639 16:53:27.584232
4640 16:53:27.587243 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 16:53:27.590846 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4642 16:53:27.593814 [Gating] SW calibration Done
4643 16:53:27.593896 ==
4644 16:53:27.597300 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 16:53:27.600618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 16:53:27.600750 ==
4647 16:53:27.604078 RX Vref Scan: 0
4648 16:53:27.604163
4649 16:53:27.604228 RX Vref 0 -> 0, step: 1
4650 16:53:27.604289
4651 16:53:27.607351 RX Delay -230 -> 252, step: 16
4652 16:53:27.610356 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4653 16:53:27.616926 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4654 16:53:27.620520 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4655 16:53:27.623499 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4656 16:53:27.627037 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4657 16:53:27.633731 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4658 16:53:27.636802 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4659 16:53:27.640313 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4660 16:53:27.643520 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4661 16:53:27.650307 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4662 16:53:27.653355 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4663 16:53:27.656471 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4664 16:53:27.660129 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4665 16:53:27.666572 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4666 16:53:27.669565 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4667 16:53:27.672852 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4668 16:53:27.672934 ==
4669 16:53:27.676657 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 16:53:27.679683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 16:53:27.679766 ==
4672 16:53:27.682955 DQS Delay:
4673 16:53:27.683037 DQS0 = 0, DQS1 = 0
4674 16:53:27.686084 DQM Delay:
4675 16:53:27.686165 DQM0 = 36, DQM1 = 29
4676 16:53:27.686229 DQ Delay:
4677 16:53:27.689277 DQ0 =33, DQ1 =33, DQ2 =25, DQ3 =33
4678 16:53:27.692994 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4679 16:53:27.696265 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4680 16:53:27.699214 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4681 16:53:27.699295
4682 16:53:27.702758
4683 16:53:27.702841 ==
4684 16:53:27.706332 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 16:53:27.709286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 16:53:27.709369 ==
4687 16:53:27.709434
4688 16:53:27.709495
4689 16:53:27.712643 TX Vref Scan disable
4690 16:53:27.712725 == TX Byte 0 ==
4691 16:53:27.719486 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4692 16:53:27.722496 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4693 16:53:27.722579 == TX Byte 1 ==
4694 16:53:27.729089 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4695 16:53:27.732543 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4696 16:53:27.732626 ==
4697 16:53:27.736022 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 16:53:27.739008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 16:53:27.739090 ==
4700 16:53:27.739155
4701 16:53:27.739214
4702 16:53:27.742867 TX Vref Scan disable
4703 16:53:27.745873 == TX Byte 0 ==
4704 16:53:27.749074 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4705 16:53:27.752463 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4706 16:53:27.755469 == TX Byte 1 ==
4707 16:53:27.758564 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4708 16:53:27.762429 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4709 16:53:27.765524
4710 16:53:27.765606 [DATLAT]
4711 16:53:27.765670 Freq=600, CH1 RK1
4712 16:53:27.765731
4713 16:53:27.768659 DATLAT Default: 0x9
4714 16:53:27.768741 0, 0xFFFF, sum = 0
4715 16:53:27.772475 1, 0xFFFF, sum = 0
4716 16:53:27.772559 2, 0xFFFF, sum = 0
4717 16:53:27.775744 3, 0xFFFF, sum = 0
4718 16:53:27.778668 4, 0xFFFF, sum = 0
4719 16:53:27.778751 5, 0xFFFF, sum = 0
4720 16:53:27.781798 6, 0xFFFF, sum = 0
4721 16:53:27.781880 7, 0xFFFF, sum = 0
4722 16:53:27.785682 8, 0x0, sum = 1
4723 16:53:27.785764 9, 0x0, sum = 2
4724 16:53:27.785831 10, 0x0, sum = 3
4725 16:53:27.789088 11, 0x0, sum = 4
4726 16:53:27.789171 best_step = 9
4727 16:53:27.789235
4728 16:53:27.789296 ==
4729 16:53:27.792114 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 16:53:27.798568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 16:53:27.798649 ==
4732 16:53:27.798714 RX Vref Scan: 0
4733 16:53:27.798774
4734 16:53:27.801542 RX Vref 0 -> 0, step: 1
4735 16:53:27.801624
4736 16:53:27.805066 RX Delay -195 -> 252, step: 8
4737 16:53:27.808698 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4738 16:53:27.815322 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4739 16:53:27.818288 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4740 16:53:27.821970 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4741 16:53:27.824689 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4742 16:53:27.831550 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4743 16:53:27.834923 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4744 16:53:27.837782 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4745 16:53:27.841031 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4746 16:53:27.847690 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4747 16:53:27.850909 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4748 16:53:27.854485 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4749 16:53:27.857645 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4750 16:53:27.864017 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4751 16:53:27.867745 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4752 16:53:27.871080 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4753 16:53:27.871184 ==
4754 16:53:27.874118 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 16:53:27.877700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 16:53:27.880759 ==
4757 16:53:27.880835 DQS Delay:
4758 16:53:27.880915 DQS0 = 0, DQS1 = 0
4759 16:53:27.883785 DQM Delay:
4760 16:53:27.883861 DQM0 = 35, DQM1 = 30
4761 16:53:27.887507 DQ Delay:
4762 16:53:27.890700 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4763 16:53:27.890774 DQ4 =32, DQ5 =48, DQ6 =44, DQ7 =32
4764 16:53:27.893949 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =20
4765 16:53:27.900738 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =36
4766 16:53:27.900814
4767 16:53:27.900876
4768 16:53:27.907181 [DQSOSCAuto] RK1, (LSB)MR18= 0x3858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4769 16:53:27.910475 CH1 RK1: MR19=808, MR18=3858
4770 16:53:27.916641 CH1_RK1: MR19=0x808, MR18=0x3858, DQSOSC=393, MR23=63, INC=169, DEC=113
4771 16:53:27.920403 [RxdqsGatingPostProcess] freq 600
4772 16:53:27.923714 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4773 16:53:27.926662 Pre-setting of DQS Precalculation
4774 16:53:27.933393 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4775 16:53:27.939849 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4776 16:53:27.946694 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4777 16:53:27.946793
4778 16:53:27.946901
4779 16:53:27.949658 [Calibration Summary] 1200 Mbps
4780 16:53:27.949734 CH 0, Rank 0
4781 16:53:27.953328 SW Impedance : PASS
4782 16:53:27.956371 DUTY Scan : NO K
4783 16:53:27.956444 ZQ Calibration : PASS
4784 16:53:27.959497 Jitter Meter : NO K
4785 16:53:27.963280 CBT Training : PASS
4786 16:53:27.963382 Write leveling : PASS
4787 16:53:27.966797 RX DQS gating : PASS
4788 16:53:27.969839 RX DQ/DQS(RDDQC) : PASS
4789 16:53:27.969940 TX DQ/DQS : PASS
4790 16:53:27.972674 RX DATLAT : PASS
4791 16:53:27.976421 RX DQ/DQS(Engine): PASS
4792 16:53:27.976504 TX OE : NO K
4793 16:53:27.979495 All Pass.
4794 16:53:27.979640
4795 16:53:27.979718 CH 0, Rank 1
4796 16:53:27.982675 SW Impedance : PASS
4797 16:53:27.982784 DUTY Scan : NO K
4798 16:53:27.986294 ZQ Calibration : PASS
4799 16:53:27.989360 Jitter Meter : NO K
4800 16:53:27.989446 CBT Training : PASS
4801 16:53:27.992644 Write leveling : PASS
4802 16:53:27.995647 RX DQS gating : PASS
4803 16:53:27.995729 RX DQ/DQS(RDDQC) : PASS
4804 16:53:27.999387 TX DQ/DQS : PASS
4805 16:53:28.002531 RX DATLAT : PASS
4806 16:53:28.002613 RX DQ/DQS(Engine): PASS
4807 16:53:28.005701 TX OE : NO K
4808 16:53:28.005784 All Pass.
4809 16:53:28.005850
4810 16:53:28.009052 CH 1, Rank 0
4811 16:53:28.009167 SW Impedance : PASS
4812 16:53:28.012609 DUTY Scan : NO K
4813 16:53:28.015430 ZQ Calibration : PASS
4814 16:53:28.015512 Jitter Meter : NO K
4815 16:53:28.018936 CBT Training : PASS
4816 16:53:28.019018 Write leveling : PASS
4817 16:53:28.022027 RX DQS gating : PASS
4818 16:53:28.025621 RX DQ/DQS(RDDQC) : PASS
4819 16:53:28.025704 TX DQ/DQS : PASS
4820 16:53:28.028791 RX DATLAT : PASS
4821 16:53:28.031922 RX DQ/DQS(Engine): PASS
4822 16:53:28.032004 TX OE : NO K
4823 16:53:28.035493 All Pass.
4824 16:53:28.035621
4825 16:53:28.035689 CH 1, Rank 1
4826 16:53:28.038429 SW Impedance : PASS
4827 16:53:28.038511 DUTY Scan : NO K
4828 16:53:28.041817 ZQ Calibration : PASS
4829 16:53:28.045628 Jitter Meter : NO K
4830 16:53:28.045711 CBT Training : PASS
4831 16:53:28.048460 Write leveling : PASS
4832 16:53:28.051458 RX DQS gating : PASS
4833 16:53:28.051540 RX DQ/DQS(RDDQC) : PASS
4834 16:53:28.055418 TX DQ/DQS : PASS
4835 16:53:28.058192 RX DATLAT : PASS
4836 16:53:28.058275 RX DQ/DQS(Engine): PASS
4837 16:53:28.061663 TX OE : NO K
4838 16:53:28.061750 All Pass.
4839 16:53:28.061817
4840 16:53:28.065430 DramC Write-DBI off
4841 16:53:28.068477 PER_BANK_REFRESH: Hybrid Mode
4842 16:53:28.068559 TX_TRACKING: ON
4843 16:53:28.078275 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4844 16:53:28.081790 [FAST_K] Save calibration result to emmc
4845 16:53:28.084908 dramc_set_vcore_voltage set vcore to 662500
4846 16:53:28.087932 Read voltage for 933, 3
4847 16:53:28.088014 Vio18 = 0
4848 16:53:28.088099 Vcore = 662500
4849 16:53:28.091273 Vdram = 0
4850 16:53:28.091355 Vddq = 0
4851 16:53:28.091454 Vmddr = 0
4852 16:53:28.098350 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4853 16:53:28.101582 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4854 16:53:28.104728 MEM_TYPE=3, freq_sel=17
4855 16:53:28.107928 sv_algorithm_assistance_LP4_1600
4856 16:53:28.111082 ============ PULL DRAM RESETB DOWN ============
4857 16:53:28.114666 ========== PULL DRAM RESETB DOWN end =========
4858 16:53:28.121219 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 16:53:28.123985 ===================================
4860 16:53:28.127610 LPDDR4 DRAM CONFIGURATION
4861 16:53:28.130713 ===================================
4862 16:53:28.130796 EX_ROW_EN[0] = 0x0
4863 16:53:28.133934 EX_ROW_EN[1] = 0x0
4864 16:53:28.134016 LP4Y_EN = 0x0
4865 16:53:28.137158 WORK_FSP = 0x0
4866 16:53:28.137240 WL = 0x3
4867 16:53:28.140814 RL = 0x3
4868 16:53:28.140897 BL = 0x2
4869 16:53:28.143923 RPST = 0x0
4870 16:53:28.147512 RD_PRE = 0x0
4871 16:53:28.147618 WR_PRE = 0x1
4872 16:53:28.150489 WR_PST = 0x0
4873 16:53:28.150571 DBI_WR = 0x0
4874 16:53:28.154132 DBI_RD = 0x0
4875 16:53:28.154214 OTF = 0x1
4876 16:53:28.156946 ===================================
4877 16:53:28.160436 ===================================
4878 16:53:28.163573 ANA top config
4879 16:53:28.166889 ===================================
4880 16:53:28.166972 DLL_ASYNC_EN = 0
4881 16:53:28.170321 ALL_SLAVE_EN = 1
4882 16:53:28.173997 NEW_RANK_MODE = 1
4883 16:53:28.177140 DLL_IDLE_MODE = 1
4884 16:53:28.177222 LP45_APHY_COMB_EN = 1
4885 16:53:28.180153 TX_ODT_DIS = 1
4886 16:53:28.183962 NEW_8X_MODE = 1
4887 16:53:28.186766 ===================================
4888 16:53:28.189707 ===================================
4889 16:53:28.192953 data_rate = 1866
4890 16:53:28.196662 CKR = 1
4891 16:53:28.199876 DQ_P2S_RATIO = 8
4892 16:53:28.203083 ===================================
4893 16:53:28.203165 CA_P2S_RATIO = 8
4894 16:53:28.206131 DQ_CA_OPEN = 0
4895 16:53:28.209531 DQ_SEMI_OPEN = 0
4896 16:53:28.212622 CA_SEMI_OPEN = 0
4897 16:53:28.216087 CA_FULL_RATE = 0
4898 16:53:28.219126 DQ_CKDIV4_EN = 1
4899 16:53:28.222658 CA_CKDIV4_EN = 1
4900 16:53:28.222732 CA_PREDIV_EN = 0
4901 16:53:28.225550 PH8_DLY = 0
4902 16:53:28.229036 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4903 16:53:28.232182 DQ_AAMCK_DIV = 4
4904 16:53:28.235890 CA_AAMCK_DIV = 4
4905 16:53:28.239338 CA_ADMCK_DIV = 4
4906 16:53:28.239414 DQ_TRACK_CA_EN = 0
4907 16:53:28.242431 CA_PICK = 933
4908 16:53:28.245469 CA_MCKIO = 933
4909 16:53:28.248672 MCKIO_SEMI = 0
4910 16:53:28.252291 PLL_FREQ = 3732
4911 16:53:28.255185 DQ_UI_PI_RATIO = 32
4912 16:53:28.258826 CA_UI_PI_RATIO = 0
4913 16:53:28.262067 ===================================
4914 16:53:28.265726 ===================================
4915 16:53:28.265831 memory_type:LPDDR4
4916 16:53:28.268642 GP_NUM : 10
4917 16:53:28.272059 SRAM_EN : 1
4918 16:53:28.272136 MD32_EN : 0
4919 16:53:28.274930 ===================================
4920 16:53:28.278365 [ANA_INIT] >>>>>>>>>>>>>>
4921 16:53:28.281981 <<<<<< [CONFIGURE PHASE]: ANA_TX
4922 16:53:28.284993 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4923 16:53:28.288377 ===================================
4924 16:53:28.291760 data_rate = 1866,PCW = 0X8f00
4925 16:53:28.294997 ===================================
4926 16:53:28.298437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4927 16:53:28.301575 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 16:53:28.307880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 16:53:28.314823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4930 16:53:28.317891 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4931 16:53:28.320999 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4932 16:53:28.321083 [ANA_INIT] flow start
4933 16:53:28.324687 [ANA_INIT] PLL >>>>>>>>
4934 16:53:28.327687 [ANA_INIT] PLL <<<<<<<<
4935 16:53:28.327796 [ANA_INIT] MIDPI >>>>>>>>
4936 16:53:28.331367 [ANA_INIT] MIDPI <<<<<<<<
4937 16:53:28.334820 [ANA_INIT] DLL >>>>>>>>
4938 16:53:28.334921 [ANA_INIT] flow end
4939 16:53:28.341024 ============ LP4 DIFF to SE enter ============
4940 16:53:28.344421 ============ LP4 DIFF to SE exit ============
4941 16:53:28.347524 [ANA_INIT] <<<<<<<<<<<<<
4942 16:53:28.351015 [Flow] Enable top DCM control >>>>>
4943 16:53:28.354035 [Flow] Enable top DCM control <<<<<
4944 16:53:28.354141 Enable DLL master slave shuffle
4945 16:53:28.360929 ==============================================================
4946 16:53:28.363791 Gating Mode config
4947 16:53:28.367302 ==============================================================
4948 16:53:28.370887 Config description:
4949 16:53:28.380720 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4950 16:53:28.387210 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4951 16:53:28.390352 SELPH_MODE 0: By rank 1: By Phase
4952 16:53:28.396674 ==============================================================
4953 16:53:28.400192 GAT_TRACK_EN = 1
4954 16:53:28.403227 RX_GATING_MODE = 2
4955 16:53:28.406955 RX_GATING_TRACK_MODE = 2
4956 16:53:28.410133 SELPH_MODE = 1
4957 16:53:28.413369 PICG_EARLY_EN = 1
4958 16:53:28.413439 VALID_LAT_VALUE = 1
4959 16:53:28.420305 ==============================================================
4960 16:53:28.423296 Enter into Gating configuration >>>>
4961 16:53:28.426536 Exit from Gating configuration <<<<
4962 16:53:28.430059 Enter into DVFS_PRE_config >>>>>
4963 16:53:28.439593 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4964 16:53:28.442746 Exit from DVFS_PRE_config <<<<<
4965 16:53:28.446617 Enter into PICG configuration >>>>
4966 16:53:28.449687 Exit from PICG configuration <<<<
4967 16:53:28.452789 [RX_INPUT] configuration >>>>>
4968 16:53:28.456418 [RX_INPUT] configuration <<<<<
4969 16:53:28.462706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4970 16:53:28.465883 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4971 16:53:28.472856 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 16:53:28.478937 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 16:53:28.485814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 16:53:28.492255 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 16:53:28.495830 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4976 16:53:28.498705 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4977 16:53:28.501983 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4978 16:53:28.508708 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4979 16:53:28.511855 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4980 16:53:28.515527 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 16:53:28.518691 ===================================
4982 16:53:28.521785 LPDDR4 DRAM CONFIGURATION
4983 16:53:28.525672 ===================================
4984 16:53:28.528645 EX_ROW_EN[0] = 0x0
4985 16:53:28.528724 EX_ROW_EN[1] = 0x0
4986 16:53:28.531785 LP4Y_EN = 0x0
4987 16:53:28.531859 WORK_FSP = 0x0
4988 16:53:28.535405 WL = 0x3
4989 16:53:28.535500 RL = 0x3
4990 16:53:28.538298 BL = 0x2
4991 16:53:28.538378 RPST = 0x0
4992 16:53:28.541831 RD_PRE = 0x0
4993 16:53:28.541934 WR_PRE = 0x1
4994 16:53:28.544928 WR_PST = 0x0
4995 16:53:28.548293 DBI_WR = 0x0
4996 16:53:28.548377 DBI_RD = 0x0
4997 16:53:28.551479 OTF = 0x1
4998 16:53:28.555243 ===================================
4999 16:53:28.557871 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5000 16:53:28.561592 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5001 16:53:28.564562 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 16:53:28.567713 ===================================
5003 16:53:28.571569 LPDDR4 DRAM CONFIGURATION
5004 16:53:28.574786 ===================================
5005 16:53:28.577814 EX_ROW_EN[0] = 0x10
5006 16:53:28.577937 EX_ROW_EN[1] = 0x0
5007 16:53:28.581060 LP4Y_EN = 0x0
5008 16:53:28.581142 WORK_FSP = 0x0
5009 16:53:28.584359 WL = 0x3
5010 16:53:28.584441 RL = 0x3
5011 16:53:28.587391 BL = 0x2
5012 16:53:28.590848 RPST = 0x0
5013 16:53:28.590929 RD_PRE = 0x0
5014 16:53:28.594417 WR_PRE = 0x1
5015 16:53:28.594499 WR_PST = 0x0
5016 16:53:28.597811 DBI_WR = 0x0
5017 16:53:28.597893 DBI_RD = 0x0
5018 16:53:28.600748 OTF = 0x1
5019 16:53:28.604370 ===================================
5020 16:53:28.610919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5021 16:53:28.613919 nWR fixed to 30
5022 16:53:28.614002 [ModeRegInit_LP4] CH0 RK0
5023 16:53:28.617307 [ModeRegInit_LP4] CH0 RK1
5024 16:53:28.620596 [ModeRegInit_LP4] CH1 RK0
5025 16:53:28.620677 [ModeRegInit_LP4] CH1 RK1
5026 16:53:28.623794 match AC timing 9
5027 16:53:28.626740 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5028 16:53:28.633463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5029 16:53:28.636779 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5030 16:53:28.643438 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5031 16:53:28.646943 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5032 16:53:28.647025 ==
5033 16:53:28.650073 Dram Type= 6, Freq= 0, CH_0, rank 0
5034 16:53:28.653266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5035 16:53:28.653348 ==
5036 16:53:28.660091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5037 16:53:28.666783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5038 16:53:28.670046 [CA 0] Center 38 (8~69) winsize 62
5039 16:53:28.673198 [CA 1] Center 38 (8~69) winsize 62
5040 16:53:28.676157 [CA 2] Center 35 (5~65) winsize 61
5041 16:53:28.679874 [CA 3] Center 35 (5~65) winsize 61
5042 16:53:28.683060 [CA 4] Center 34 (4~64) winsize 61
5043 16:53:28.686252 [CA 5] Center 34 (4~64) winsize 61
5044 16:53:28.686354
5045 16:53:28.689364 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5046 16:53:28.689445
5047 16:53:28.693048 [CATrainingPosCal] consider 1 rank data
5048 16:53:28.696093 u2DelayCellTimex100 = 270/100 ps
5049 16:53:28.699839 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5050 16:53:28.702542 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5051 16:53:28.705848 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5052 16:53:28.709154 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5053 16:53:28.712901 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5054 16:53:28.715715 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5055 16:53:28.715797
5056 16:53:28.722439 CA PerBit enable=1, Macro0, CA PI delay=34
5057 16:53:28.722521
5058 16:53:28.726114 [CBTSetCACLKResult] CA Dly = 34
5059 16:53:28.726207 CS Dly: 7 (0~38)
5060 16:53:28.726272 ==
5061 16:53:28.729297 Dram Type= 6, Freq= 0, CH_0, rank 1
5062 16:53:28.732330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 16:53:28.732412 ==
5064 16:53:28.739421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 16:53:28.745522 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5066 16:53:28.749163 [CA 0] Center 38 (8~69) winsize 62
5067 16:53:28.752173 [CA 1] Center 38 (8~69) winsize 62
5068 16:53:28.755355 [CA 2] Center 35 (5~66) winsize 62
5069 16:53:28.758486 [CA 3] Center 35 (5~66) winsize 62
5070 16:53:28.762406 [CA 4] Center 34 (4~65) winsize 62
5071 16:53:28.765039 [CA 5] Center 34 (4~64) winsize 61
5072 16:53:28.765121
5073 16:53:28.768988 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5074 16:53:28.769069
5075 16:53:28.772308 [CATrainingPosCal] consider 2 rank data
5076 16:53:28.775441 u2DelayCellTimex100 = 270/100 ps
5077 16:53:28.778598 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5078 16:53:28.781728 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5079 16:53:28.785426 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5080 16:53:28.791540 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5081 16:53:28.794857 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5082 16:53:28.798534 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5083 16:53:28.798615
5084 16:53:28.801710 CA PerBit enable=1, Macro0, CA PI delay=34
5085 16:53:28.801791
5086 16:53:28.804820 [CBTSetCACLKResult] CA Dly = 34
5087 16:53:28.804902 CS Dly: 7 (0~38)
5088 16:53:28.804966
5089 16:53:28.808414 ----->DramcWriteLeveling(PI) begin...
5090 16:53:28.811326 ==
5091 16:53:28.811425 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 16:53:28.817633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 16:53:28.817718 ==
5094 16:53:28.821218 Write leveling (Byte 0): 29 => 29
5095 16:53:28.824192 Write leveling (Byte 1): 30 => 30
5096 16:53:28.827720 DramcWriteLeveling(PI) end<-----
5097 16:53:28.827802
5098 16:53:28.827865 ==
5099 16:53:28.831116 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 16:53:28.834264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 16:53:28.834346 ==
5102 16:53:28.837459 [Gating] SW mode calibration
5103 16:53:28.844095 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5104 16:53:28.851208 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5105 16:53:28.854091 0 14 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
5106 16:53:28.857222 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5107 16:53:28.864036 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 16:53:28.867256 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 16:53:28.870385 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 16:53:28.876978 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 16:53:28.880171 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 16:53:28.883455 0 14 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5113 16:53:28.890040 0 15 0 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
5114 16:53:28.893131 0 15 4 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5115 16:53:28.896423 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 16:53:28.903144 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 16:53:28.906609 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 16:53:28.909875 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 16:53:28.916355 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 16:53:28.919440 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 16:53:28.922990 1 0 0 | B1->B0 | 2929 3f3f | 1 1 | (0 0) (0 0)
5122 16:53:28.929631 1 0 4 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
5123 16:53:28.932688 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 16:53:28.935748 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 16:53:28.942783 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 16:53:28.945877 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 16:53:28.949013 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 16:53:28.955869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5129 16:53:28.958836 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5130 16:53:28.962575 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 16:53:28.968752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 16:53:28.971923 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 16:53:28.975051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 16:53:28.981862 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 16:53:28.985593 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 16:53:28.988708 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 16:53:28.995390 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 16:53:28.998429 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 16:53:29.002023 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 16:53:29.008409 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 16:53:29.011415 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 16:53:29.014938 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 16:53:29.021599 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 16:53:29.024855 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 16:53:29.028479 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5146 16:53:29.031458 Total UI for P1: 0, mck2ui 16
5147 16:53:29.034891 best dqsien dly found for B0: ( 1, 2, 30)
5148 16:53:29.041349 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5149 16:53:29.044380 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 16:53:29.047968 Total UI for P1: 0, mck2ui 16
5151 16:53:29.051430 best dqsien dly found for B1: ( 1, 3, 4)
5152 16:53:29.054700 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5153 16:53:29.057861 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5154 16:53:29.057942
5155 16:53:29.061409 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5156 16:53:29.064314 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5157 16:53:29.067469 [Gating] SW calibration Done
5158 16:53:29.067551 ==
5159 16:53:29.070710 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 16:53:29.077557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 16:53:29.077640 ==
5162 16:53:29.077705 RX Vref Scan: 0
5163 16:53:29.077779
5164 16:53:29.080662 RX Vref 0 -> 0, step: 1
5165 16:53:29.080744
5166 16:53:29.084367 RX Delay -80 -> 252, step: 8
5167 16:53:29.087370 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5168 16:53:29.090355 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5169 16:53:29.093591 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5170 16:53:29.097251 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5171 16:53:29.103776 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5172 16:53:29.107312 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5173 16:53:29.110599 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5174 16:53:29.113809 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5175 16:53:29.116754 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5176 16:53:29.123311 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5177 16:53:29.127151 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5178 16:53:29.129794 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5179 16:53:29.133216 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5180 16:53:29.139741 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5181 16:53:29.143444 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5182 16:53:29.146544 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5183 16:53:29.146749 ==
5184 16:53:29.150003 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 16:53:29.153170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 16:53:29.153261 ==
5187 16:53:29.156599 DQS Delay:
5188 16:53:29.156702 DQS0 = 0, DQS1 = 0
5189 16:53:29.160012 DQM Delay:
5190 16:53:29.160119 DQM0 = 94, DQM1 = 81
5191 16:53:29.160211 DQ Delay:
5192 16:53:29.163077 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5193 16:53:29.166097 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =111
5194 16:53:29.169654 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5195 16:53:29.172919 DQ12 =83, DQ13 =87, DQ14 =91, DQ15 =87
5196 16:53:29.173027
5197 16:53:29.176109
5198 16:53:29.176213 ==
5199 16:53:29.179495 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 16:53:29.182461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 16:53:29.182563 ==
5202 16:53:29.182656
5203 16:53:29.182721
5204 16:53:29.186303 TX Vref Scan disable
5205 16:53:29.186402 == TX Byte 0 ==
5206 16:53:29.192586 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5207 16:53:29.195873 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5208 16:53:29.195951 == TX Byte 1 ==
5209 16:53:29.202454 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5210 16:53:29.205609 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5211 16:53:29.205709 ==
5212 16:53:29.208673 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 16:53:29.212562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 16:53:29.212672 ==
5215 16:53:29.212766
5216 16:53:29.212855
5217 16:53:29.215704 TX Vref Scan disable
5218 16:53:29.218759 == TX Byte 0 ==
5219 16:53:29.221963 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5220 16:53:29.225522 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5221 16:53:29.228509 == TX Byte 1 ==
5222 16:53:29.232090 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5223 16:53:29.235440 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5224 16:53:29.235554
5225 16:53:29.238631 [DATLAT]
5226 16:53:29.238717 Freq=933, CH0 RK0
5227 16:53:29.238828
5228 16:53:29.242019 DATLAT Default: 0xd
5229 16:53:29.242180 0, 0xFFFF, sum = 0
5230 16:53:29.245646 1, 0xFFFF, sum = 0
5231 16:53:29.245770 2, 0xFFFF, sum = 0
5232 16:53:29.248527 3, 0xFFFF, sum = 0
5233 16:53:29.248636 4, 0xFFFF, sum = 0
5234 16:53:29.252114 5, 0xFFFF, sum = 0
5235 16:53:29.252224 6, 0xFFFF, sum = 0
5236 16:53:29.255566 7, 0xFFFF, sum = 0
5237 16:53:29.255684 8, 0xFFFF, sum = 0
5238 16:53:29.258589 9, 0xFFFF, sum = 0
5239 16:53:29.258683 10, 0x0, sum = 1
5240 16:53:29.261920 11, 0x0, sum = 2
5241 16:53:29.262028 12, 0x0, sum = 3
5242 16:53:29.265331 13, 0x0, sum = 4
5243 16:53:29.265439 best_step = 11
5244 16:53:29.265538
5245 16:53:29.265629 ==
5246 16:53:29.268492 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 16:53:29.275053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 16:53:29.275169 ==
5249 16:53:29.275265 RX Vref Scan: 1
5250 16:53:29.275363
5251 16:53:29.278211 RX Vref 0 -> 0, step: 1
5252 16:53:29.278316
5253 16:53:29.281602 RX Delay -69 -> 252, step: 4
5254 16:53:29.281705
5255 16:53:29.284700 Set Vref, RX VrefLevel [Byte0]: 60
5256 16:53:29.288435 [Byte1]: 45
5257 16:53:29.288512
5258 16:53:29.291324 Final RX Vref Byte 0 = 60 to rank0
5259 16:53:29.295019 Final RX Vref Byte 1 = 45 to rank0
5260 16:53:29.298295 Final RX Vref Byte 0 = 60 to rank1
5261 16:53:29.301371 Final RX Vref Byte 1 = 45 to rank1==
5262 16:53:29.305152 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 16:53:29.308333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 16:53:29.311303 ==
5265 16:53:29.311413 DQS Delay:
5266 16:53:29.311511 DQS0 = 0, DQS1 = 0
5267 16:53:29.314981 DQM Delay:
5268 16:53:29.315083 DQM0 = 95, DQM1 = 83
5269 16:53:29.318256 DQ Delay:
5270 16:53:29.318362 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5271 16:53:29.321462 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5272 16:53:29.324532 DQ8 =74, DQ9 =70, DQ10 =84, DQ11 =78
5273 16:53:29.327790 DQ12 =86, DQ13 =86, DQ14 =96, DQ15 =90
5274 16:53:29.330945
5275 16:53:29.331018
5276 16:53:29.337991 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5277 16:53:29.341263 CH0 RK0: MR19=505, MR18=1414
5278 16:53:29.347925 CH0_RK0: MR19=0x505, MR18=0x1414, DQSOSC=415, MR23=63, INC=62, DEC=41
5279 16:53:29.348029
5280 16:53:29.350825 ----->DramcWriteLeveling(PI) begin...
5281 16:53:29.350899 ==
5282 16:53:29.354467 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 16:53:29.357429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 16:53:29.357503 ==
5285 16:53:29.360981 Write leveling (Byte 0): 32 => 32
5286 16:53:29.364460 Write leveling (Byte 1): 30 => 30
5287 16:53:29.367803 DramcWriteLeveling(PI) end<-----
5288 16:53:29.367877
5289 16:53:29.367943 ==
5290 16:53:29.371178 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 16:53:29.374000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 16:53:29.374103 ==
5293 16:53:29.377573 [Gating] SW mode calibration
5294 16:53:29.383840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 16:53:29.390238 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 16:53:29.393817 0 14 0 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
5297 16:53:29.400730 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 16:53:29.403855 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 16:53:29.407010 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 16:53:29.413991 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 16:53:29.417166 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 16:53:29.420260 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 16:53:29.426601 0 14 28 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
5304 16:53:29.430239 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
5305 16:53:29.433281 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 16:53:29.440078 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 16:53:29.443633 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 16:53:29.446526 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 16:53:29.452944 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 16:53:29.456615 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 16:53:29.460076 0 15 28 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
5312 16:53:29.466505 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5313 16:53:29.469545 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 16:53:29.473278 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 16:53:29.479904 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 16:53:29.483108 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 16:53:29.486306 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 16:53:29.492542 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 16:53:29.496106 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5320 16:53:29.499234 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5321 16:53:29.506200 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 16:53:29.509565 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 16:53:29.512720 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 16:53:29.519477 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 16:53:29.522550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 16:53:29.525928 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 16:53:29.532822 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 16:53:29.535793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 16:53:29.538909 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 16:53:29.545634 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 16:53:29.549170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 16:53:29.552281 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 16:53:29.558739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 16:53:29.562285 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5335 16:53:29.565332 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5336 16:53:29.571989 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5337 16:53:29.572068 Total UI for P1: 0, mck2ui 16
5338 16:53:29.575716 best dqsien dly found for B0: ( 1, 2, 26)
5339 16:53:29.581716 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 16:53:29.585225 Total UI for P1: 0, mck2ui 16
5341 16:53:29.588484 best dqsien dly found for B1: ( 1, 3, 0)
5342 16:53:29.591590 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5343 16:53:29.594762 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5344 16:53:29.594863
5345 16:53:29.598581 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5346 16:53:29.602033 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5347 16:53:29.605062 [Gating] SW calibration Done
5348 16:53:29.605163 ==
5349 16:53:29.608298 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 16:53:29.611538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 16:53:29.611666 ==
5352 16:53:29.615207 RX Vref Scan: 0
5353 16:53:29.615310
5354 16:53:29.618269 RX Vref 0 -> 0, step: 1
5355 16:53:29.618370
5356 16:53:29.618460 RX Delay -80 -> 252, step: 8
5357 16:53:29.624872 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5358 16:53:29.627969 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5359 16:53:29.631681 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5360 16:53:29.634794 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5361 16:53:29.637969 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5362 16:53:29.644289 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5363 16:53:29.648111 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5364 16:53:29.651094 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5365 16:53:29.654324 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5366 16:53:29.657872 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5367 16:53:29.664011 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5368 16:53:29.667545 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5369 16:53:29.670986 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5370 16:53:29.673801 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5371 16:53:29.677379 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5372 16:53:29.684037 iDelay=208, Bit 15, Center 91 (0 ~ 183) 184
5373 16:53:29.684112 ==
5374 16:53:29.687056 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 16:53:29.690329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 16:53:29.690403 ==
5377 16:53:29.690465 DQS Delay:
5378 16:53:29.693970 DQS0 = 0, DQS1 = 0
5379 16:53:29.694045 DQM Delay:
5380 16:53:29.697219 DQM0 = 91, DQM1 = 82
5381 16:53:29.697324 DQ Delay:
5382 16:53:29.700376 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5383 16:53:29.703976 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5384 16:53:29.706975 DQ8 =71, DQ9 =63, DQ10 =87, DQ11 =71
5385 16:53:29.709934 DQ12 =87, DQ13 =95, DQ14 =95, DQ15 =91
5386 16:53:29.710031
5387 16:53:29.710122
5388 16:53:29.710209 ==
5389 16:53:29.713849 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 16:53:29.716910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 16:53:29.716982 ==
5392 16:53:29.720027
5393 16:53:29.720096
5394 16:53:29.720158 TX Vref Scan disable
5395 16:53:29.723249 == TX Byte 0 ==
5396 16:53:29.726922 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5397 16:53:29.730004 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5398 16:53:29.733234 == TX Byte 1 ==
5399 16:53:29.736731 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5400 16:53:29.739928 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5401 16:53:29.743189 ==
5402 16:53:29.743256 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 16:53:29.750043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 16:53:29.750143 ==
5405 16:53:29.750239
5406 16:53:29.750327
5407 16:53:29.753381 TX Vref Scan disable
5408 16:53:29.753475 == TX Byte 0 ==
5409 16:53:29.759958 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5410 16:53:29.763016 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5411 16:53:29.763117 == TX Byte 1 ==
5412 16:53:29.769566 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5413 16:53:29.772634 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5414 16:53:29.772731
5415 16:53:29.772822 [DATLAT]
5416 16:53:29.776158 Freq=933, CH0 RK1
5417 16:53:29.776255
5418 16:53:29.776346 DATLAT Default: 0xb
5419 16:53:29.779681 0, 0xFFFF, sum = 0
5420 16:53:29.779751 1, 0xFFFF, sum = 0
5421 16:53:29.782511 2, 0xFFFF, sum = 0
5422 16:53:29.782610 3, 0xFFFF, sum = 0
5423 16:53:29.786089 4, 0xFFFF, sum = 0
5424 16:53:29.789533 5, 0xFFFF, sum = 0
5425 16:53:29.789602 6, 0xFFFF, sum = 0
5426 16:53:29.792641 7, 0xFFFF, sum = 0
5427 16:53:29.792710 8, 0xFFFF, sum = 0
5428 16:53:29.795785 9, 0xFFFF, sum = 0
5429 16:53:29.795883 10, 0x0, sum = 1
5430 16:53:29.798851 11, 0x0, sum = 2
5431 16:53:29.798919 12, 0x0, sum = 3
5432 16:53:29.802515 13, 0x0, sum = 4
5433 16:53:29.802588 best_step = 11
5434 16:53:29.802648
5435 16:53:29.802706 ==
5436 16:53:29.805932 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 16:53:29.809113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 16:53:29.809184 ==
5439 16:53:29.811987 RX Vref Scan: 0
5440 16:53:29.812053
5441 16:53:29.815756 RX Vref 0 -> 0, step: 1
5442 16:53:29.815822
5443 16:53:29.815883 RX Delay -77 -> 252, step: 4
5444 16:53:29.823270 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5445 16:53:29.826560 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5446 16:53:29.830056 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5447 16:53:29.833273 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5448 16:53:29.836342 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5449 16:53:29.843262 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5450 16:53:29.846460 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5451 16:53:29.849603 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5452 16:53:29.852894 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5453 16:53:29.856120 iDelay=199, Bit 9, Center 68 (-17 ~ 154) 172
5454 16:53:29.863007 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5455 16:53:29.866012 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5456 16:53:29.869160 iDelay=199, Bit 12, Center 88 (-1 ~ 178) 180
5457 16:53:29.872605 iDelay=199, Bit 13, Center 88 (-1 ~ 178) 180
5458 16:53:29.875642 iDelay=199, Bit 14, Center 94 (7 ~ 182) 176
5459 16:53:29.882284 iDelay=199, Bit 15, Center 90 (3 ~ 178) 176
5460 16:53:29.882388 ==
5461 16:53:29.885846 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 16:53:29.889415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 16:53:29.889516 ==
5464 16:53:29.889609 DQS Delay:
5465 16:53:29.892339 DQS0 = 0, DQS1 = 0
5466 16:53:29.892409 DQM Delay:
5467 16:53:29.895791 DQM0 = 92, DQM1 = 83
5468 16:53:29.895861 DQ Delay:
5469 16:53:29.898823 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5470 16:53:29.902004 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =104
5471 16:53:29.905715 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5472 16:53:29.908846 DQ12 =88, DQ13 =88, DQ14 =94, DQ15 =90
5473 16:53:29.908918
5474 16:53:29.908980
5475 16:53:29.918572 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e10, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 407 ps
5476 16:53:29.918679 CH0 RK1: MR19=505, MR18=2E10
5477 16:53:29.925145 CH0_RK1: MR19=0x505, MR18=0x2E10, DQSOSC=407, MR23=63, INC=65, DEC=43
5478 16:53:29.928794 [RxdqsGatingPostProcess] freq 933
5479 16:53:29.935343 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 16:53:29.938615 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 16:53:29.941611 best DQS1 dly(2T, 0.5T) = (0, 11)
5482 16:53:29.944900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 16:53:29.948780 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5484 16:53:29.951760 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 16:53:29.954976 best DQS1 dly(2T, 0.5T) = (0, 11)
5486 16:53:29.958009 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 16:53:29.961707 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5488 16:53:29.961812 Pre-setting of DQS Precalculation
5489 16:53:29.967907 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 16:53:29.967985 ==
5491 16:53:29.971181 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 16:53:29.974890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 16:53:29.974968 ==
5494 16:53:29.981026 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 16:53:29.988020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5496 16:53:29.991141 [CA 0] Center 36 (7~66) winsize 60
5497 16:53:29.994761 [CA 1] Center 37 (7~67) winsize 61
5498 16:53:29.997592 [CA 2] Center 34 (5~64) winsize 60
5499 16:53:30.001253 [CA 3] Center 34 (4~64) winsize 61
5500 16:53:30.004348 [CA 4] Center 34 (5~64) winsize 60
5501 16:53:30.007921 [CA 5] Center 34 (4~64) winsize 61
5502 16:53:30.007990
5503 16:53:30.011004 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5504 16:53:30.011100
5505 16:53:30.014726 [CATrainingPosCal] consider 1 rank data
5506 16:53:30.017736 u2DelayCellTimex100 = 270/100 ps
5507 16:53:30.021093 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5508 16:53:30.024150 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5509 16:53:30.027773 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5510 16:53:30.030858 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5511 16:53:30.033870 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5512 16:53:30.040667 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5513 16:53:30.040768
5514 16:53:30.043749 CA PerBit enable=1, Macro0, CA PI delay=34
5515 16:53:30.043822
5516 16:53:30.046999 [CBTSetCACLKResult] CA Dly = 34
5517 16:53:30.047075 CS Dly: 5 (0~36)
5518 16:53:30.047165 ==
5519 16:53:30.050602 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 16:53:30.056961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 16:53:30.057057 ==
5522 16:53:30.060077 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 16:53:30.066990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 16:53:30.070036 [CA 0] Center 37 (8~67) winsize 60
5525 16:53:30.073669 [CA 1] Center 37 (7~67) winsize 61
5526 16:53:30.077036 [CA 2] Center 35 (5~65) winsize 61
5527 16:53:30.080057 [CA 3] Center 34 (4~64) winsize 61
5528 16:53:30.083770 [CA 4] Center 35 (5~65) winsize 61
5529 16:53:30.086910 [CA 5] Center 34 (4~64) winsize 61
5530 16:53:30.087004
5531 16:53:30.089891 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 16:53:30.089993
5533 16:53:30.093439 [CATrainingPosCal] consider 2 rank data
5534 16:53:30.097112 u2DelayCellTimex100 = 270/100 ps
5535 16:53:30.100180 CA0 delay=37 (8~66),Diff = 3 PI (18 cell)
5536 16:53:30.102991 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5537 16:53:30.109503 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5538 16:53:30.113132 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5539 16:53:30.116668 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5540 16:53:30.119662 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 16:53:30.119730
5542 16:53:30.122746 CA PerBit enable=1, Macro0, CA PI delay=34
5543 16:53:30.122840
5544 16:53:30.126754 [CBTSetCACLKResult] CA Dly = 34
5545 16:53:30.126848 CS Dly: 6 (0~39)
5546 16:53:30.129839
5547 16:53:30.132732 ----->DramcWriteLeveling(PI) begin...
5548 16:53:30.132805 ==
5549 16:53:30.136524 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 16:53:30.139562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 16:53:30.139693 ==
5552 16:53:30.142638 Write leveling (Byte 0): 27 => 27
5553 16:53:30.146060 Write leveling (Byte 1): 28 => 28
5554 16:53:30.149223 DramcWriteLeveling(PI) end<-----
5555 16:53:30.149321
5556 16:53:30.149409 ==
5557 16:53:30.152518 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 16:53:30.156076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 16:53:30.156145 ==
5560 16:53:30.159215 [Gating] SW mode calibration
5561 16:53:30.165573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 16:53:30.172125 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 16:53:30.176016 0 14 0 | B1->B0 | 3131 3131 | 0 1 | (0 0) (1 1)
5564 16:53:30.178935 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 16:53:30.185662 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 16:53:30.188871 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 16:53:30.192413 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 16:53:30.198722 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 16:53:30.201660 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 16:53:30.205373 0 14 28 | B1->B0 | 3030 3232 | 0 0 | (0 0) (0 1)
5571 16:53:30.211634 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (1 0) (0 0)
5572 16:53:30.214708 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 16:53:30.218345 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 16:53:30.224674 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 16:53:30.227808 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 16:53:30.231706 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 16:53:30.238028 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 16:53:30.240984 0 15 28 | B1->B0 | 3535 3736 | 0 1 | (0 0) (0 0)
5579 16:53:30.244288 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 16:53:30.251437 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 16:53:30.254648 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 16:53:30.257763 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 16:53:30.264260 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 16:53:30.267388 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 16:53:30.271116 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 16:53:30.277153 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5587 16:53:30.280831 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 16:53:30.283991 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 16:53:30.290287 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 16:53:30.293980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 16:53:30.297202 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 16:53:30.304002 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 16:53:30.307007 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 16:53:30.313371 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 16:53:30.316729 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 16:53:30.320219 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 16:53:30.326643 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 16:53:30.329876 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 16:53:30.333433 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 16:53:30.339970 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 16:53:30.343132 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 16:53:30.346566 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5603 16:53:30.353219 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5604 16:53:30.353321 Total UI for P1: 0, mck2ui 16
5605 16:53:30.356133 best dqsien dly found for B1: ( 1, 2, 28)
5606 16:53:30.363165 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 16:53:30.366469 Total UI for P1: 0, mck2ui 16
5608 16:53:30.369427 best dqsien dly found for B0: ( 1, 3, 0)
5609 16:53:30.372877 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5610 16:53:30.375869 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5611 16:53:30.375964
5612 16:53:30.379399 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5613 16:53:30.382959 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5614 16:53:30.385941 [Gating] SW calibration Done
5615 16:53:30.386036 ==
5616 16:53:30.389725 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 16:53:30.392835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 16:53:30.392904 ==
5619 16:53:30.395927 RX Vref Scan: 0
5620 16:53:30.396001
5621 16:53:30.399171 RX Vref 0 -> 0, step: 1
5622 16:53:30.399268
5623 16:53:30.399357 RX Delay -80 -> 252, step: 8
5624 16:53:30.406085 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5625 16:53:30.409254 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5626 16:53:30.412831 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5627 16:53:30.415811 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5628 16:53:30.418964 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5629 16:53:30.422513 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5630 16:53:30.429152 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5631 16:53:30.432225 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5632 16:53:30.435434 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5633 16:53:30.438818 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5634 16:53:30.441881 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5635 16:53:30.448514 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5636 16:53:30.452077 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5637 16:53:30.455038 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5638 16:53:30.458525 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5639 16:53:30.461636 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5640 16:53:30.461731 ==
5641 16:53:30.465357 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 16:53:30.471634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 16:53:30.471725 ==
5644 16:53:30.471788 DQS Delay:
5645 16:53:30.471848 DQS0 = 0, DQS1 = 0
5646 16:53:30.474926 DQM Delay:
5647 16:53:30.474995 DQM0 = 97, DQM1 = 91
5648 16:53:30.478511 DQ Delay:
5649 16:53:30.481548 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5650 16:53:30.485236 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =95
5651 16:53:30.488356 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5652 16:53:30.491266 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5653 16:53:30.491361
5654 16:53:30.491449
5655 16:53:30.491537 ==
5656 16:53:30.494855 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 16:53:30.498003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 16:53:30.498102 ==
5659 16:53:30.498193
5660 16:53:30.498282
5661 16:53:30.501645 TX Vref Scan disable
5662 16:53:30.501742 == TX Byte 0 ==
5663 16:53:30.508242 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5664 16:53:30.511526 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5665 16:53:30.514438 == TX Byte 1 ==
5666 16:53:30.518129 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5667 16:53:30.521050 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5668 16:53:30.521147 ==
5669 16:53:30.524676 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 16:53:30.527740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 16:53:30.527837 ==
5672 16:53:30.531545
5673 16:53:30.531667
5674 16:53:30.531728 TX Vref Scan disable
5675 16:53:30.534546 == TX Byte 0 ==
5676 16:53:30.537959 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5677 16:53:30.544511 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5678 16:53:30.544590 == TX Byte 1 ==
5679 16:53:30.547927 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 16:53:30.554143 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 16:53:30.554241
5682 16:53:30.554333 [DATLAT]
5683 16:53:30.554421 Freq=933, CH1 RK0
5684 16:53:30.554508
5685 16:53:30.557412 DATLAT Default: 0xd
5686 16:53:30.561062 0, 0xFFFF, sum = 0
5687 16:53:30.561167 1, 0xFFFF, sum = 0
5688 16:53:30.563909 2, 0xFFFF, sum = 0
5689 16:53:30.564062 3, 0xFFFF, sum = 0
5690 16:53:30.567233 4, 0xFFFF, sum = 0
5691 16:53:30.567335 5, 0xFFFF, sum = 0
5692 16:53:30.570661 6, 0xFFFF, sum = 0
5693 16:53:30.570734 7, 0xFFFF, sum = 0
5694 16:53:30.574295 8, 0xFFFF, sum = 0
5695 16:53:30.574397 9, 0xFFFF, sum = 0
5696 16:53:30.577274 10, 0x0, sum = 1
5697 16:53:30.577375 11, 0x0, sum = 2
5698 16:53:30.580587 12, 0x0, sum = 3
5699 16:53:30.580688 13, 0x0, sum = 4
5700 16:53:30.583559 best_step = 11
5701 16:53:30.583656
5702 16:53:30.583722 ==
5703 16:53:30.587425 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 16:53:30.590442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 16:53:30.590541 ==
5706 16:53:30.590631 RX Vref Scan: 1
5707 16:53:30.593620
5708 16:53:30.593715 RX Vref 0 -> 0, step: 1
5709 16:53:30.593818
5710 16:53:30.597076 RX Delay -69 -> 252, step: 4
5711 16:53:30.597169
5712 16:53:30.600220 Set Vref, RX VrefLevel [Byte0]: 51
5713 16:53:30.603443 [Byte1]: 50
5714 16:53:30.607159
5715 16:53:30.607233 Final RX Vref Byte 0 = 51 to rank0
5716 16:53:30.610304 Final RX Vref Byte 1 = 50 to rank0
5717 16:53:30.614169 Final RX Vref Byte 0 = 51 to rank1
5718 16:53:30.617453 Final RX Vref Byte 1 = 50 to rank1==
5719 16:53:30.620390 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 16:53:30.627057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 16:53:30.627155 ==
5722 16:53:30.627245 DQS Delay:
5723 16:53:30.627334 DQS0 = 0, DQS1 = 0
5724 16:53:30.630018 DQM Delay:
5725 16:53:30.630114 DQM0 = 95, DQM1 = 88
5726 16:53:30.633753 DQ Delay:
5727 16:53:30.636695 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
5728 16:53:30.640520 DQ4 =92, DQ5 =106, DQ6 =106, DQ7 =92
5729 16:53:30.643530 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5730 16:53:30.646563 DQ12 =98, DQ13 =92, DQ14 =92, DQ15 =96
5731 16:53:30.646661
5732 16:53:30.646748
5733 16:53:30.653040 [DQSOSCAuto] RK0, (LSB)MR18= 0x20b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 421 ps
5734 16:53:30.656556 CH1 RK0: MR19=505, MR18=20B
5735 16:53:30.663441 CH1_RK0: MR19=0x505, MR18=0x20B, DQSOSC=418, MR23=63, INC=62, DEC=41
5736 16:53:30.663555
5737 16:53:30.666713 ----->DramcWriteLeveling(PI) begin...
5738 16:53:30.666806 ==
5739 16:53:30.669765 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 16:53:30.673458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 16:53:30.673560 ==
5742 16:53:30.676261 Write leveling (Byte 0): 25 => 25
5743 16:53:30.679867 Write leveling (Byte 1): 28 => 28
5744 16:53:30.683183 DramcWriteLeveling(PI) end<-----
5745 16:53:30.683285
5746 16:53:30.683376 ==
5747 16:53:30.686383 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 16:53:30.690023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 16:53:30.693105 ==
5750 16:53:30.693179 [Gating] SW mode calibration
5751 16:53:30.702748 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 16:53:30.706340 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 16:53:30.709310 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5754 16:53:30.715876 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 16:53:30.719432 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 16:53:30.722556 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 16:53:30.728787 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 16:53:30.732419 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 16:53:30.735523 0 14 24 | B1->B0 | 3131 2f2f | 1 0 | (1 1) (0 0)
5760 16:53:30.742026 0 14 28 | B1->B0 | 2727 2323 | 1 1 | (1 0) (1 0)
5761 16:53:30.745239 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 16:53:30.748486 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 16:53:30.755463 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 16:53:30.758879 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 16:53:30.761883 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 16:53:30.768495 0 15 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5767 16:53:30.771727 0 15 24 | B1->B0 | 2a2a 3232 | 0 1 | (0 0) (0 0)
5768 16:53:30.775386 0 15 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5769 16:53:30.781685 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 16:53:30.785253 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 16:53:30.788366 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 16:53:30.795066 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 16:53:30.798155 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 16:53:30.801718 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 16:53:30.808261 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 16:53:30.811408 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5777 16:53:30.814504 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 16:53:30.821422 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 16:53:30.824602 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 16:53:30.827802 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 16:53:30.834737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 16:53:30.837760 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 16:53:30.841337 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 16:53:30.848046 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 16:53:30.851030 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 16:53:30.854069 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 16:53:30.860806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 16:53:30.864326 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 16:53:30.867821 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 16:53:30.874134 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 16:53:30.877443 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 16:53:30.880579 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 16:53:30.887370 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 16:53:30.890351 Total UI for P1: 0, mck2ui 16
5795 16:53:30.893669 best dqsien dly found for B0: ( 1, 2, 28)
5796 16:53:30.893771 Total UI for P1: 0, mck2ui 16
5797 16:53:30.900718 best dqsien dly found for B1: ( 1, 2, 28)
5798 16:53:30.903782 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5799 16:53:30.907006 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5800 16:53:30.907111
5801 16:53:30.910518 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5802 16:53:30.913628 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5803 16:53:30.916745 [Gating] SW calibration Done
5804 16:53:30.916845 ==
5805 16:53:30.920003 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 16:53:30.923683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 16:53:30.923757 ==
5808 16:53:30.926818 RX Vref Scan: 0
5809 16:53:30.926917
5810 16:53:30.929974 RX Vref 0 -> 0, step: 1
5811 16:53:30.930048
5812 16:53:30.930109 RX Delay -80 -> 252, step: 8
5813 16:53:30.936306 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5814 16:53:30.939526 iDelay=200, Bit 1, Center 87 (-16 ~ 191) 208
5815 16:53:30.943020 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5816 16:53:30.946609 iDelay=200, Bit 3, Center 87 (-16 ~ 191) 208
5817 16:53:30.949652 iDelay=200, Bit 4, Center 91 (-8 ~ 191) 200
5818 16:53:30.956265 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5819 16:53:30.959390 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5820 16:53:30.963013 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5821 16:53:30.966057 iDelay=200, Bit 8, Center 75 (-24 ~ 175) 200
5822 16:53:30.969612 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5823 16:53:30.976307 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5824 16:53:30.979193 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5825 16:53:30.982318 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5826 16:53:30.985933 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5827 16:53:30.989050 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5828 16:53:30.995757 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5829 16:53:30.995833 ==
5830 16:53:30.998722 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 16:53:31.002354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 16:53:31.002454 ==
5833 16:53:31.002547 DQS Delay:
5834 16:53:31.005334 DQS0 = 0, DQS1 = 0
5835 16:53:31.005432 DQM Delay:
5836 16:53:31.009000 DQM0 = 92, DQM1 = 88
5837 16:53:31.009074 DQ Delay:
5838 16:53:31.011850 DQ0 =99, DQ1 =87, DQ2 =79, DQ3 =87
5839 16:53:31.015355 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5840 16:53:31.018472 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5841 16:53:31.022382 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5842 16:53:31.022457
5843 16:53:31.022522
5844 16:53:31.022581 ==
5845 16:53:31.025470 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 16:53:31.028632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 16:53:31.031886 ==
5848 16:53:31.031958
5849 16:53:31.032019
5850 16:53:31.032077 TX Vref Scan disable
5851 16:53:31.034859 == TX Byte 0 ==
5852 16:53:31.038597 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5853 16:53:31.041682 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5854 16:53:31.044747 == TX Byte 1 ==
5855 16:53:31.047919 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5856 16:53:31.054757 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5857 16:53:31.054866 ==
5858 16:53:31.058381 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 16:53:31.061410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 16:53:31.061488 ==
5861 16:53:31.061574
5862 16:53:31.061665
5863 16:53:31.064447 TX Vref Scan disable
5864 16:53:31.064546 == TX Byte 0 ==
5865 16:53:31.071491 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5866 16:53:31.074552 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5867 16:53:31.074627 == TX Byte 1 ==
5868 16:53:31.081010 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5869 16:53:31.084221 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5870 16:53:31.084375
5871 16:53:31.084515 [DATLAT]
5872 16:53:31.088034 Freq=933, CH1 RK1
5873 16:53:31.088139
5874 16:53:31.088233 DATLAT Default: 0xb
5875 16:53:31.091049 0, 0xFFFF, sum = 0
5876 16:53:31.094059 1, 0xFFFF, sum = 0
5877 16:53:31.094170 2, 0xFFFF, sum = 0
5878 16:53:31.097360 3, 0xFFFF, sum = 0
5879 16:53:31.097474 4, 0xFFFF, sum = 0
5880 16:53:31.100635 5, 0xFFFF, sum = 0
5881 16:53:31.100746 6, 0xFFFF, sum = 0
5882 16:53:31.104247 7, 0xFFFF, sum = 0
5883 16:53:31.104359 8, 0xFFFF, sum = 0
5884 16:53:31.106997 9, 0xFFFF, sum = 0
5885 16:53:31.107073 10, 0x0, sum = 1
5886 16:53:31.110675 11, 0x0, sum = 2
5887 16:53:31.110777 12, 0x0, sum = 3
5888 16:53:31.113974 13, 0x0, sum = 4
5889 16:53:31.114079 best_step = 11
5890 16:53:31.114182
5891 16:53:31.114275 ==
5892 16:53:31.116913 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 16:53:31.120426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 16:53:31.123459 ==
5895 16:53:31.123558 RX Vref Scan: 0
5896 16:53:31.123667
5897 16:53:31.127276 RX Vref 0 -> 0, step: 1
5898 16:53:31.127373
5899 16:53:31.130397 RX Delay -69 -> 252, step: 4
5900 16:53:31.133539 iDelay=203, Bit 0, Center 98 (3 ~ 194) 192
5901 16:53:31.136649 iDelay=203, Bit 1, Center 90 (-5 ~ 186) 192
5902 16:53:31.143573 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5903 16:53:31.146661 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5904 16:53:31.149727 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5905 16:53:31.153302 iDelay=203, Bit 5, Center 104 (11 ~ 198) 188
5906 16:53:31.156401 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5907 16:53:31.159756 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5908 16:53:31.166265 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5909 16:53:31.170043 iDelay=203, Bit 9, Center 78 (-17 ~ 174) 192
5910 16:53:31.173201 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5911 16:53:31.176075 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5912 16:53:31.179566 iDelay=203, Bit 12, Center 94 (-1 ~ 190) 192
5913 16:53:31.186331 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
5914 16:53:31.189317 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5915 16:53:31.192884 iDelay=203, Bit 15, Center 94 (-1 ~ 190) 192
5916 16:53:31.192957 ==
5917 16:53:31.195899 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 16:53:31.199388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 16:53:31.199489 ==
5920 16:53:31.202619 DQS Delay:
5921 16:53:31.202720 DQS0 = 0, DQS1 = 0
5922 16:53:31.206056 DQM Delay:
5923 16:53:31.206153 DQM0 = 93, DQM1 = 88
5924 16:53:31.206241 DQ Delay:
5925 16:53:31.209052 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =88
5926 16:53:31.212509 DQ4 =90, DQ5 =104, DQ6 =104, DQ7 =90
5927 16:53:31.216045 DQ8 =76, DQ9 =78, DQ10 =92, DQ11 =84
5928 16:53:31.219593 DQ12 =94, DQ13 =94, DQ14 =94, DQ15 =94
5929 16:53:31.219670
5930 16:53:31.222447
5931 16:53:31.229196 [DQSOSCAuto] RK1, (LSB)MR18= 0xa1e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5932 16:53:31.232488 CH1 RK1: MR19=505, MR18=A1E
5933 16:53:31.239239 CH1_RK1: MR19=0x505, MR18=0xA1E, DQSOSC=412, MR23=63, INC=63, DEC=42
5934 16:53:31.239343 [RxdqsGatingPostProcess] freq 933
5935 16:53:31.245627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5936 16:53:31.248797 best DQS0 dly(2T, 0.5T) = (0, 11)
5937 16:53:31.252435 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 16:53:31.255598 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5939 16:53:31.258977 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 16:53:31.261918 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 16:53:31.265604 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 16:53:31.268578 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 16:53:31.271946 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 16:53:31.275101 Pre-setting of DQS Precalculation
5945 16:53:31.278896 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5946 16:53:31.285172 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5947 16:53:31.294923 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5948 16:53:31.295002
5949 16:53:31.295103
5950 16:53:31.298478 [Calibration Summary] 1866 Mbps
5951 16:53:31.298552 CH 0, Rank 0
5952 16:53:31.302014 SW Impedance : PASS
5953 16:53:31.302085 DUTY Scan : NO K
5954 16:53:31.305174 ZQ Calibration : PASS
5955 16:53:31.308366 Jitter Meter : NO K
5956 16:53:31.308440 CBT Training : PASS
5957 16:53:31.311617 Write leveling : PASS
5958 16:53:31.314620 RX DQS gating : PASS
5959 16:53:31.314690 RX DQ/DQS(RDDQC) : PASS
5960 16:53:31.318257 TX DQ/DQS : PASS
5961 16:53:31.318330 RX DATLAT : PASS
5962 16:53:31.321089 RX DQ/DQS(Engine): PASS
5963 16:53:31.324503 TX OE : NO K
5964 16:53:31.324571 All Pass.
5965 16:53:31.324631
5966 16:53:31.327619 CH 0, Rank 1
5967 16:53:31.327714 SW Impedance : PASS
5968 16:53:31.331011 DUTY Scan : NO K
5969 16:53:31.331086 ZQ Calibration : PASS
5970 16:53:31.334289 Jitter Meter : NO K
5971 16:53:31.338017 CBT Training : PASS
5972 16:53:31.338084 Write leveling : PASS
5973 16:53:31.341390 RX DQS gating : PASS
5974 16:53:31.344375 RX DQ/DQS(RDDQC) : PASS
5975 16:53:31.344448 TX DQ/DQS : PASS
5976 16:53:31.347735 RX DATLAT : PASS
5977 16:53:31.351270 RX DQ/DQS(Engine): PASS
5978 16:53:31.351338 TX OE : NO K
5979 16:53:31.354432 All Pass.
5980 16:53:31.354504
5981 16:53:31.354564 CH 1, Rank 0
5982 16:53:31.357611 SW Impedance : PASS
5983 16:53:31.357678 DUTY Scan : NO K
5984 16:53:31.360762 ZQ Calibration : PASS
5985 16:53:31.364422 Jitter Meter : NO K
5986 16:53:31.364527 CBT Training : PASS
5987 16:53:31.367576 Write leveling : PASS
5988 16:53:31.370938 RX DQS gating : PASS
5989 16:53:31.371037 RX DQ/DQS(RDDQC) : PASS
5990 16:53:31.373921 TX DQ/DQS : PASS
5991 16:53:31.377308 RX DATLAT : PASS
5992 16:53:31.377405 RX DQ/DQS(Engine): PASS
5993 16:53:31.380868 TX OE : NO K
5994 16:53:31.380967 All Pass.
5995 16:53:31.381057
5996 16:53:31.384014 CH 1, Rank 1
5997 16:53:31.384097 SW Impedance : PASS
5998 16:53:31.387067 DUTY Scan : NO K
5999 16:53:31.390724 ZQ Calibration : PASS
6000 16:53:31.390824 Jitter Meter : NO K
6001 16:53:31.393665 CBT Training : PASS
6002 16:53:31.397171 Write leveling : PASS
6003 16:53:31.397268 RX DQS gating : PASS
6004 16:53:31.400409 RX DQ/DQS(RDDQC) : PASS
6005 16:53:31.400481 TX DQ/DQS : PASS
6006 16:53:31.403667 RX DATLAT : PASS
6007 16:53:31.407102 RX DQ/DQS(Engine): PASS
6008 16:53:31.407199 TX OE : NO K
6009 16:53:31.410145 All Pass.
6010 16:53:31.410242
6011 16:53:31.410336 DramC Write-DBI off
6012 16:53:31.413761 PER_BANK_REFRESH: Hybrid Mode
6013 16:53:31.416965 TX_TRACKING: ON
6014 16:53:31.423338 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6015 16:53:31.426932 [FAST_K] Save calibration result to emmc
6016 16:53:31.433282 dramc_set_vcore_voltage set vcore to 650000
6017 16:53:31.433386 Read voltage for 400, 6
6018 16:53:31.433483 Vio18 = 0
6019 16:53:31.436811 Vcore = 650000
6020 16:53:31.436884 Vdram = 0
6021 16:53:31.436953 Vddq = 0
6022 16:53:31.439842 Vmddr = 0
6023 16:53:31.443684 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6024 16:53:31.449913 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6025 16:53:31.453074 MEM_TYPE=3, freq_sel=20
6026 16:53:31.453153 sv_algorithm_assistance_LP4_800
6027 16:53:31.459922 ============ PULL DRAM RESETB DOWN ============
6028 16:53:31.463032 ========== PULL DRAM RESETB DOWN end =========
6029 16:53:31.466157 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6030 16:53:31.470072 ===================================
6031 16:53:31.473299 LPDDR4 DRAM CONFIGURATION
6032 16:53:31.476429 ===================================
6033 16:53:31.479643 EX_ROW_EN[0] = 0x0
6034 16:53:31.479741 EX_ROW_EN[1] = 0x0
6035 16:53:31.483111 LP4Y_EN = 0x0
6036 16:53:31.483207 WORK_FSP = 0x0
6037 16:53:31.486202 WL = 0x2
6038 16:53:31.486300 RL = 0x2
6039 16:53:31.489669 BL = 0x2
6040 16:53:31.489766 RPST = 0x0
6041 16:53:31.492750 RD_PRE = 0x0
6042 16:53:31.492820 WR_PRE = 0x1
6043 16:53:31.496376 WR_PST = 0x0
6044 16:53:31.499256 DBI_WR = 0x0
6045 16:53:31.499356 DBI_RD = 0x0
6046 16:53:31.502365 OTF = 0x1
6047 16:53:31.505816 ===================================
6048 16:53:31.509168 ===================================
6049 16:53:31.509239 ANA top config
6050 16:53:31.512722 ===================================
6051 16:53:31.516094 DLL_ASYNC_EN = 0
6052 16:53:31.519139 ALL_SLAVE_EN = 1
6053 16:53:31.519209 NEW_RANK_MODE = 1
6054 16:53:31.522257 DLL_IDLE_MODE = 1
6055 16:53:31.525985 LP45_APHY_COMB_EN = 1
6056 16:53:31.529261 TX_ODT_DIS = 1
6057 16:53:31.529339 NEW_8X_MODE = 1
6058 16:53:31.532261 ===================================
6059 16:53:31.535360 ===================================
6060 16:53:31.538813 data_rate = 800
6061 16:53:31.541861 CKR = 1
6062 16:53:31.545550 DQ_P2S_RATIO = 4
6063 16:53:31.548567 ===================================
6064 16:53:31.551783 CA_P2S_RATIO = 4
6065 16:53:31.555534 DQ_CA_OPEN = 0
6066 16:53:31.558651 DQ_SEMI_OPEN = 1
6067 16:53:31.558721 CA_SEMI_OPEN = 1
6068 16:53:31.561888 CA_FULL_RATE = 0
6069 16:53:31.564837 DQ_CKDIV4_EN = 0
6070 16:53:31.568444 CA_CKDIV4_EN = 1
6071 16:53:31.571653 CA_PREDIV_EN = 0
6072 16:53:31.574968 PH8_DLY = 0
6073 16:53:31.575065 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6074 16:53:31.578017 DQ_AAMCK_DIV = 0
6075 16:53:31.581231 CA_AAMCK_DIV = 0
6076 16:53:31.585044 CA_ADMCK_DIV = 4
6077 16:53:31.588004 DQ_TRACK_CA_EN = 0
6078 16:53:31.591669 CA_PICK = 800
6079 16:53:31.594765 CA_MCKIO = 400
6080 16:53:31.594835 MCKIO_SEMI = 400
6081 16:53:31.597740 PLL_FREQ = 3016
6082 16:53:31.601324 DQ_UI_PI_RATIO = 32
6083 16:53:31.604741 CA_UI_PI_RATIO = 32
6084 16:53:31.607778 ===================================
6085 16:53:31.611305 ===================================
6086 16:53:31.614229 memory_type:LPDDR4
6087 16:53:31.614322 GP_NUM : 10
6088 16:53:31.617449 SRAM_EN : 1
6089 16:53:31.621306 MD32_EN : 0
6090 16:53:31.624047 ===================================
6091 16:53:31.624119 [ANA_INIT] >>>>>>>>>>>>>>
6092 16:53:31.627690 <<<<<< [CONFIGURE PHASE]: ANA_TX
6093 16:53:31.630843 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6094 16:53:31.634473 ===================================
6095 16:53:31.637455 data_rate = 800,PCW = 0X7400
6096 16:53:31.640832 ===================================
6097 16:53:31.643873 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6098 16:53:31.650817 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 16:53:31.660331 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 16:53:31.667206 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6101 16:53:31.670181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6102 16:53:31.674013 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6103 16:53:31.674113 [ANA_INIT] flow start
6104 16:53:31.677171 [ANA_INIT] PLL >>>>>>>>
6105 16:53:31.680274 [ANA_INIT] PLL <<<<<<<<
6106 16:53:31.683627 [ANA_INIT] MIDPI >>>>>>>>
6107 16:53:31.683714 [ANA_INIT] MIDPI <<<<<<<<
6108 16:53:31.686757 [ANA_INIT] DLL >>>>>>>>
6109 16:53:31.689859 [ANA_INIT] flow end
6110 16:53:31.693331 ============ LP4 DIFF to SE enter ============
6111 16:53:31.696368 ============ LP4 DIFF to SE exit ============
6112 16:53:31.699978 [ANA_INIT] <<<<<<<<<<<<<
6113 16:53:31.703013 [Flow] Enable top DCM control >>>>>
6114 16:53:31.706632 [Flow] Enable top DCM control <<<<<
6115 16:53:31.709668 Enable DLL master slave shuffle
6116 16:53:31.713255 ==============================================================
6117 16:53:31.716500 Gating Mode config
6118 16:53:31.722908 ==============================================================
6119 16:53:31.723009 Config description:
6120 16:53:31.732844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6121 16:53:31.739510 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6122 16:53:31.742686 SELPH_MODE 0: By rank 1: By Phase
6123 16:53:31.749675 ==============================================================
6124 16:53:31.752536 GAT_TRACK_EN = 0
6125 16:53:31.756009 RX_GATING_MODE = 2
6126 16:53:31.759068 RX_GATING_TRACK_MODE = 2
6127 16:53:31.762553 SELPH_MODE = 1
6128 16:53:31.765547 PICG_EARLY_EN = 1
6129 16:53:31.768767 VALID_LAT_VALUE = 1
6130 16:53:31.772581 ==============================================================
6131 16:53:31.775795 Enter into Gating configuration >>>>
6132 16:53:31.778997 Exit from Gating configuration <<<<
6133 16:53:31.782190 Enter into DVFS_PRE_config >>>>>
6134 16:53:31.795498 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6135 16:53:31.798534 Exit from DVFS_PRE_config <<<<<
6136 16:53:31.802312 Enter into PICG configuration >>>>
6137 16:53:31.805339 Exit from PICG configuration <<<<
6138 16:53:31.805427 [RX_INPUT] configuration >>>>>
6139 16:53:31.808416 [RX_INPUT] configuration <<<<<
6140 16:53:31.815248 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6141 16:53:31.821735 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6142 16:53:31.824689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 16:53:31.831311 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 16:53:31.837730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 16:53:31.844327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 16:53:31.848272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6147 16:53:31.851699 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6148 16:53:31.857737 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6149 16:53:31.860807 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6150 16:53:31.864345 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6151 16:53:31.871107 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6152 16:53:31.874239 ===================================
6153 16:53:31.874319 LPDDR4 DRAM CONFIGURATION
6154 16:53:31.877313 ===================================
6155 16:53:31.880468 EX_ROW_EN[0] = 0x0
6156 16:53:31.884342 EX_ROW_EN[1] = 0x0
6157 16:53:31.884417 LP4Y_EN = 0x0
6158 16:53:31.887639 WORK_FSP = 0x0
6159 16:53:31.887713 WL = 0x2
6160 16:53:31.890641 RL = 0x2
6161 16:53:31.890713 BL = 0x2
6162 16:53:31.893713 RPST = 0x0
6163 16:53:31.893787 RD_PRE = 0x0
6164 16:53:31.897380 WR_PRE = 0x1
6165 16:53:31.897456 WR_PST = 0x0
6166 16:53:31.900507 DBI_WR = 0x0
6167 16:53:31.900584 DBI_RD = 0x0
6168 16:53:31.904168 OTF = 0x1
6169 16:53:31.907202 ===================================
6170 16:53:31.910442 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6171 16:53:31.913576 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6172 16:53:31.920265 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 16:53:31.923452 ===================================
6174 16:53:31.923567 LPDDR4 DRAM CONFIGURATION
6175 16:53:31.926605 ===================================
6176 16:53:31.930047 EX_ROW_EN[0] = 0x10
6177 16:53:31.933110 EX_ROW_EN[1] = 0x0
6178 16:53:31.933220 LP4Y_EN = 0x0
6179 16:53:31.936627 WORK_FSP = 0x0
6180 16:53:31.936704 WL = 0x2
6181 16:53:31.940196 RL = 0x2
6182 16:53:31.940276 BL = 0x2
6183 16:53:31.943209 RPST = 0x0
6184 16:53:31.943285 RD_PRE = 0x0
6185 16:53:31.946768 WR_PRE = 0x1
6186 16:53:31.946846 WR_PST = 0x0
6187 16:53:31.950175 DBI_WR = 0x0
6188 16:53:31.950251 DBI_RD = 0x0
6189 16:53:31.953078 OTF = 0x1
6190 16:53:31.956838 ===================================
6191 16:53:31.963170 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6192 16:53:31.966252 nWR fixed to 30
6193 16:53:31.969328 [ModeRegInit_LP4] CH0 RK0
6194 16:53:31.969404 [ModeRegInit_LP4] CH0 RK1
6195 16:53:31.972944 [ModeRegInit_LP4] CH1 RK0
6196 16:53:31.976082 [ModeRegInit_LP4] CH1 RK1
6197 16:53:31.976161 match AC timing 19
6198 16:53:31.983048 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6199 16:53:31.986161 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6200 16:53:31.989249 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6201 16:53:31.995627 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6202 16:53:31.999306 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6203 16:53:31.999383 ==
6204 16:53:32.002425 Dram Type= 6, Freq= 0, CH_0, rank 0
6205 16:53:32.005672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6206 16:53:32.005761 ==
6207 16:53:32.012305 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6208 16:53:32.018860 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6209 16:53:32.022248 [CA 0] Center 36 (8~64) winsize 57
6210 16:53:32.025281 [CA 1] Center 36 (8~64) winsize 57
6211 16:53:32.029085 [CA 2] Center 36 (8~64) winsize 57
6212 16:53:32.032216 [CA 3] Center 36 (8~64) winsize 57
6213 16:53:32.035284 [CA 4] Center 36 (8~64) winsize 57
6214 16:53:32.035360 [CA 5] Center 36 (8~64) winsize 57
6215 16:53:32.035469
6216 16:53:32.042250 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6217 16:53:32.042359
6218 16:53:32.045237 [CATrainingPosCal] consider 1 rank data
6219 16:53:32.048741 u2DelayCellTimex100 = 270/100 ps
6220 16:53:32.051696 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 16:53:32.055316 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 16:53:32.058744 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 16:53:32.061785 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 16:53:32.064936 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 16:53:32.068186 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 16:53:32.068269
6227 16:53:32.071943 CA PerBit enable=1, Macro0, CA PI delay=36
6228 16:53:32.072062
6229 16:53:32.074835 [CBTSetCACLKResult] CA Dly = 36
6230 16:53:32.078427 CS Dly: 1 (0~32)
6231 16:53:32.078538 ==
6232 16:53:32.081600 Dram Type= 6, Freq= 0, CH_0, rank 1
6233 16:53:32.084774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 16:53:32.084859 ==
6235 16:53:32.091492 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 16:53:32.098209 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6237 16:53:32.101254 [CA 0] Center 36 (8~64) winsize 57
6238 16:53:32.104568 [CA 1] Center 36 (8~64) winsize 57
6239 16:53:32.104651 [CA 2] Center 36 (8~64) winsize 57
6240 16:53:32.108235 [CA 3] Center 36 (8~64) winsize 57
6241 16:53:32.111234 [CA 4] Center 36 (8~64) winsize 57
6242 16:53:32.114379 [CA 5] Center 36 (8~64) winsize 57
6243 16:53:32.114461
6244 16:53:32.118338 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6245 16:53:32.121541
6246 16:53:32.124710 [CATrainingPosCal] consider 2 rank data
6247 16:53:32.127737 u2DelayCellTimex100 = 270/100 ps
6248 16:53:32.131362 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 16:53:32.134338 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 16:53:32.137483 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 16:53:32.141121 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 16:53:32.144763 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 16:53:32.147490 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 16:53:32.147571
6255 16:53:32.150865 CA PerBit enable=1, Macro0, CA PI delay=36
6256 16:53:32.150946
6257 16:53:32.154207 [CBTSetCACLKResult] CA Dly = 36
6258 16:53:32.157597 CS Dly: 1 (0~32)
6259 16:53:32.157678
6260 16:53:32.160941 ----->DramcWriteLeveling(PI) begin...
6261 16:53:32.161022 ==
6262 16:53:32.163931 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 16:53:32.167392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 16:53:32.167475 ==
6265 16:53:32.170604 Write leveling (Byte 0): 40 => 8
6266 16:53:32.174301 Write leveling (Byte 1): 40 => 8
6267 16:53:32.177310 DramcWriteLeveling(PI) end<-----
6268 16:53:32.177391
6269 16:53:32.177455 ==
6270 16:53:32.180978 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 16:53:32.183868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 16:53:32.183950 ==
6273 16:53:32.187612 [Gating] SW mode calibration
6274 16:53:32.193764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6275 16:53:32.200651 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6276 16:53:32.203737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 16:53:32.206888 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 16:53:32.213527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 16:53:32.217242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 16:53:32.220398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 16:53:32.226714 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 16:53:32.230638 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 16:53:32.233541 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 16:53:32.240018 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 16:53:32.243187 Total UI for P1: 0, mck2ui 16
6286 16:53:32.246380 best dqsien dly found for B0: ( 0, 14, 24)
6287 16:53:32.249916 Total UI for P1: 0, mck2ui 16
6288 16:53:32.253030 best dqsien dly found for B1: ( 0, 14, 24)
6289 16:53:32.256467 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6290 16:53:32.260012 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6291 16:53:32.260090
6292 16:53:32.262996 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 16:53:32.266488 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 16:53:32.269742 [Gating] SW calibration Done
6295 16:53:32.269842 ==
6296 16:53:32.273391 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 16:53:32.276291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 16:53:32.279866 ==
6299 16:53:32.279942 RX Vref Scan: 0
6300 16:53:32.280005
6301 16:53:32.282851 RX Vref 0 -> 0, step: 1
6302 16:53:32.282926
6303 16:53:32.285827 RX Delay -410 -> 252, step: 16
6304 16:53:32.289333 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6305 16:53:32.292489 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6306 16:53:32.295730 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6307 16:53:32.302345 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6308 16:53:32.306110 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6309 16:53:32.309157 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6310 16:53:32.312323 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6311 16:53:32.319153 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6312 16:53:32.322304 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6313 16:53:32.325502 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6314 16:53:32.328678 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6315 16:53:32.335538 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6316 16:53:32.338551 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6317 16:53:32.342089 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6318 16:53:32.348477 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6319 16:53:32.351613 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6320 16:53:32.351702 ==
6321 16:53:32.355545 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 16:53:32.358627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 16:53:32.358702 ==
6324 16:53:32.362186 DQS Delay:
6325 16:53:32.362314 DQS0 = 59, DQS1 = 59
6326 16:53:32.365102 DQM Delay:
6327 16:53:32.365178 DQM0 = 18, DQM1 = 10
6328 16:53:32.365245 DQ Delay:
6329 16:53:32.368727 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6330 16:53:32.371612 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6331 16:53:32.375246 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6332 16:53:32.378296 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6333 16:53:32.378395
6334 16:53:32.378484
6335 16:53:32.378572 ==
6336 16:53:32.381796 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 16:53:32.388518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 16:53:32.388621 ==
6339 16:53:32.388711
6340 16:53:32.388798
6341 16:53:32.388885 TX Vref Scan disable
6342 16:53:32.391446 == TX Byte 0 ==
6343 16:53:32.394656 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 16:53:32.398547 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 16:53:32.401625 == TX Byte 1 ==
6346 16:53:32.404661 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 16:53:32.408279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 16:53:32.408355 ==
6349 16:53:32.411428 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 16:53:32.417678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 16:53:32.417754 ==
6352 16:53:32.417819
6353 16:53:32.417877
6354 16:53:32.420847 TX Vref Scan disable
6355 16:53:32.420945 == TX Byte 0 ==
6356 16:53:32.424551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 16:53:32.430808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 16:53:32.430887 == TX Byte 1 ==
6359 16:53:32.434738 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 16:53:32.440808 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 16:53:32.440910
6362 16:53:32.440975 [DATLAT]
6363 16:53:32.441033 Freq=400, CH0 RK0
6364 16:53:32.441090
6365 16:53:32.443929 DATLAT Default: 0xf
6366 16:53:32.443997 0, 0xFFFF, sum = 0
6367 16:53:32.447569 1, 0xFFFF, sum = 0
6368 16:53:32.450498 2, 0xFFFF, sum = 0
6369 16:53:32.450572 3, 0xFFFF, sum = 0
6370 16:53:32.454005 4, 0xFFFF, sum = 0
6371 16:53:32.454109 5, 0xFFFF, sum = 0
6372 16:53:32.457391 6, 0xFFFF, sum = 0
6373 16:53:32.457467 7, 0xFFFF, sum = 0
6374 16:53:32.460511 8, 0xFFFF, sum = 0
6375 16:53:32.460589 9, 0xFFFF, sum = 0
6376 16:53:32.463776 10, 0xFFFF, sum = 0
6377 16:53:32.463879 11, 0xFFFF, sum = 0
6378 16:53:32.467428 12, 0xFFFF, sum = 0
6379 16:53:32.467531 13, 0x0, sum = 1
6380 16:53:32.470658 14, 0x0, sum = 2
6381 16:53:32.470730 15, 0x0, sum = 3
6382 16:53:32.474036 16, 0x0, sum = 4
6383 16:53:32.474141 best_step = 14
6384 16:53:32.474231
6385 16:53:32.474319 ==
6386 16:53:32.477198 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 16:53:32.484106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 16:53:32.484183 ==
6389 16:53:32.484247 RX Vref Scan: 1
6390 16:53:32.484335
6391 16:53:32.486982 RX Vref 0 -> 0, step: 1
6392 16:53:32.487079
6393 16:53:32.490740 RX Delay -359 -> 252, step: 8
6394 16:53:32.490864
6395 16:53:32.493561 Set Vref, RX VrefLevel [Byte0]: 60
6396 16:53:32.496580 [Byte1]: 45
6397 16:53:32.496652
6398 16:53:32.499982 Final RX Vref Byte 0 = 60 to rank0
6399 16:53:32.503668 Final RX Vref Byte 1 = 45 to rank0
6400 16:53:32.506967 Final RX Vref Byte 0 = 60 to rank1
6401 16:53:32.509776 Final RX Vref Byte 1 = 45 to rank1==
6402 16:53:32.513122 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 16:53:32.516420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 16:53:32.520345 ==
6405 16:53:32.520445 DQS Delay:
6406 16:53:32.520538 DQS0 = 60, DQS1 = 68
6407 16:53:32.523384 DQM Delay:
6408 16:53:32.523483 DQM0 = 15, DQM1 = 14
6409 16:53:32.526502 DQ Delay:
6410 16:53:32.529460 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =16
6411 16:53:32.529536 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =28
6412 16:53:32.532766 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6413 16:53:32.536539 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =20
6414 16:53:32.539587
6415 16:53:32.539660
6416 16:53:32.546010 [DQSOSCAuto] RK0, (LSB)MR18= 0x7f7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6417 16:53:32.549703 CH0 RK0: MR19=C0C, MR18=7F7F
6418 16:53:32.555989 CH0_RK0: MR19=0xC0C, MR18=0x7F7F, DQSOSC=393, MR23=63, INC=382, DEC=254
6419 16:53:32.556065 ==
6420 16:53:32.559306 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 16:53:32.562397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 16:53:32.562497 ==
6423 16:53:32.565856 [Gating] SW mode calibration
6424 16:53:32.572316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6425 16:53:32.579032 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6426 16:53:32.582442 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 16:53:32.585941 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 16:53:32.592403 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 16:53:32.595460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 16:53:32.599016 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 16:53:32.605747 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 16:53:32.609128 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 16:53:32.612244 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 16:53:32.618884 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 16:53:32.618977 Total UI for P1: 0, mck2ui 16
6436 16:53:32.625167 best dqsien dly found for B0: ( 0, 14, 24)
6437 16:53:32.625273 Total UI for P1: 0, mck2ui 16
6438 16:53:32.631852 best dqsien dly found for B1: ( 0, 14, 24)
6439 16:53:32.635674 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6440 16:53:32.638764 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6441 16:53:32.638832
6442 16:53:32.641740 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 16:53:32.644783 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 16:53:32.648482 [Gating] SW calibration Done
6445 16:53:32.648566 ==
6446 16:53:32.651964 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 16:53:32.654908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 16:53:32.655008 ==
6449 16:53:32.657910 RX Vref Scan: 0
6450 16:53:32.657987
6451 16:53:32.661646 RX Vref 0 -> 0, step: 1
6452 16:53:32.661717
6453 16:53:32.661777 RX Delay -410 -> 252, step: 16
6454 16:53:32.668422 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6455 16:53:32.671371 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6456 16:53:32.674824 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6457 16:53:32.677827 iDelay=230, Bit 3, Center -51 (-314 ~ 213) 528
6458 16:53:32.684743 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6459 16:53:32.687706 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6460 16:53:32.690870 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6461 16:53:32.697534 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6462 16:53:32.700933 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6463 16:53:32.704669 iDelay=230, Bit 9, Center -67 (-314 ~ 181) 496
6464 16:53:32.707454 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6465 16:53:32.714240 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6466 16:53:32.717418 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6467 16:53:32.720618 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6468 16:53:32.723896 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6469 16:53:32.730549 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6470 16:53:32.730659 ==
6471 16:53:32.734306 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 16:53:32.737095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 16:53:32.737211 ==
6474 16:53:32.737320 DQS Delay:
6475 16:53:32.741024 DQS0 = 59, DQS1 = 67
6476 16:53:32.741097 DQM Delay:
6477 16:53:32.743990 DQM0 = 15, DQM1 = 18
6478 16:53:32.744064 DQ Delay:
6479 16:53:32.747195 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6480 16:53:32.750375 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6481 16:53:32.753730 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6482 16:53:32.757378 DQ12 =24, DQ13 =24, DQ14 =32, DQ15 =24
6483 16:53:32.757451
6484 16:53:32.757513
6485 16:53:32.757571 ==
6486 16:53:32.760661 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 16:53:32.763493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 16:53:32.767287 ==
6489 16:53:32.767392
6490 16:53:32.767484
6491 16:53:32.767601 TX Vref Scan disable
6492 16:53:32.770261 == TX Byte 0 ==
6493 16:53:32.773941 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6494 16:53:32.777079 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6495 16:53:32.779926 == TX Byte 1 ==
6496 16:53:32.783480 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 16:53:32.786623 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 16:53:32.786704 ==
6499 16:53:32.789787 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 16:53:32.797157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 16:53:32.797262 ==
6502 16:53:32.797354
6503 16:53:32.797442
6504 16:53:32.797532 TX Vref Scan disable
6505 16:53:32.799976 == TX Byte 0 ==
6506 16:53:32.803494 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 16:53:32.806518 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 16:53:32.809789 == TX Byte 1 ==
6509 16:53:32.813394 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 16:53:32.816316 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 16:53:32.816460
6512 16:53:32.819865 [DATLAT]
6513 16:53:32.819945 Freq=400, CH0 RK1
6514 16:53:32.820010
6515 16:53:32.822968 DATLAT Default: 0xe
6516 16:53:32.823075 0, 0xFFFF, sum = 0
6517 16:53:32.826974 1, 0xFFFF, sum = 0
6518 16:53:32.827057 2, 0xFFFF, sum = 0
6519 16:53:32.830090 3, 0xFFFF, sum = 0
6520 16:53:32.830173 4, 0xFFFF, sum = 0
6521 16:53:32.832821 5, 0xFFFF, sum = 0
6522 16:53:32.832903 6, 0xFFFF, sum = 0
6523 16:53:32.836661 7, 0xFFFF, sum = 0
6524 16:53:32.836771 8, 0xFFFF, sum = 0
6525 16:53:32.839740 9, 0xFFFF, sum = 0
6526 16:53:32.839823 10, 0xFFFF, sum = 0
6527 16:53:32.842701 11, 0xFFFF, sum = 0
6528 16:53:32.845949 12, 0xFFFF, sum = 0
6529 16:53:32.846048 13, 0x0, sum = 1
6530 16:53:32.849719 14, 0x0, sum = 2
6531 16:53:32.849816 15, 0x0, sum = 3
6532 16:53:32.849906 16, 0x0, sum = 4
6533 16:53:32.852859 best_step = 14
6534 16:53:32.852928
6535 16:53:32.852985 ==
6536 16:53:32.856182 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 16:53:32.859234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 16:53:32.859328 ==
6539 16:53:32.862455 RX Vref Scan: 0
6540 16:53:32.862567
6541 16:53:32.865567 RX Vref 0 -> 0, step: 1
6542 16:53:32.865683
6543 16:53:32.865773 RX Delay -359 -> 252, step: 8
6544 16:53:32.874556 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6545 16:53:32.877742 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6546 16:53:32.881365 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6547 16:53:32.887915 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6548 16:53:32.890975 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6549 16:53:32.894694 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6550 16:53:32.897708 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6551 16:53:32.904366 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6552 16:53:32.907473 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6553 16:53:32.910512 iDelay=217, Bit 9, Center -68 (-311 ~ 176) 488
6554 16:53:32.914142 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6555 16:53:32.920875 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6556 16:53:32.923720 iDelay=217, Bit 12, Center -48 (-295 ~ 200) 496
6557 16:53:32.926970 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6558 16:53:32.930887 iDelay=217, Bit 14, Center -44 (-287 ~ 200) 488
6559 16:53:32.936997 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6560 16:53:32.937098 ==
6561 16:53:32.940253 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 16:53:32.943477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 16:53:32.943576 ==
6564 16:53:32.946593 DQS Delay:
6565 16:53:32.946662 DQS0 = 60, DQS1 = 68
6566 16:53:32.946738 DQM Delay:
6567 16:53:32.950086 DQM0 = 11, DQM1 = 14
6568 16:53:32.950183 DQ Delay:
6569 16:53:32.953363 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6570 16:53:32.956521 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6571 16:53:32.960177 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6572 16:53:32.963476 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6573 16:53:32.963557
6574 16:53:32.963664
6575 16:53:32.972907 [DQSOSCAuto] RK1, (LSB)MR18= 0xc175, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 385 ps
6576 16:53:32.972991 CH0 RK1: MR19=C0C, MR18=C175
6577 16:53:32.979833 CH0_RK1: MR19=0xC0C, MR18=0xC175, DQSOSC=385, MR23=63, INC=398, DEC=265
6578 16:53:32.982772 [RxdqsGatingPostProcess] freq 400
6579 16:53:32.989613 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6580 16:53:32.992883 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 16:53:32.996038 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 16:53:32.999497 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 16:53:33.002390 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 16:53:33.005947 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 16:53:33.009042 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 16:53:33.012722 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 16:53:33.015833 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 16:53:33.015912 Pre-setting of DQS Precalculation
6589 16:53:33.022566 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6590 16:53:33.022673 ==
6591 16:53:33.025792 Dram Type= 6, Freq= 0, CH_1, rank 0
6592 16:53:33.029269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 16:53:33.029370 ==
6594 16:53:33.035709 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6595 16:53:33.042398 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6596 16:53:33.045477 [CA 0] Center 36 (8~64) winsize 57
6597 16:53:33.049070 [CA 1] Center 36 (8~64) winsize 57
6598 16:53:33.052024 [CA 2] Center 36 (8~64) winsize 57
6599 16:53:33.055835 [CA 3] Center 36 (8~64) winsize 57
6600 16:53:33.055923 [CA 4] Center 36 (8~64) winsize 57
6601 16:53:33.059045 [CA 5] Center 36 (8~64) winsize 57
6602 16:53:33.059125
6603 16:53:33.065325 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6604 16:53:33.065407
6605 16:53:33.068955 [CATrainingPosCal] consider 1 rank data
6606 16:53:33.072205 u2DelayCellTimex100 = 270/100 ps
6607 16:53:33.075213 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 16:53:33.079033 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 16:53:33.081975 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 16:53:33.085501 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 16:53:33.088580 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 16:53:33.092366 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 16:53:33.092447
6614 16:53:33.095352 CA PerBit enable=1, Macro0, CA PI delay=36
6615 16:53:33.095433
6616 16:53:33.098654 [CBTSetCACLKResult] CA Dly = 36
6617 16:53:33.101601 CS Dly: 1 (0~32)
6618 16:53:33.101683 ==
6619 16:53:33.105090 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 16:53:33.108674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 16:53:33.108756 ==
6622 16:53:33.114966 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 16:53:33.121345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 16:53:33.125061 [CA 0] Center 36 (8~64) winsize 57
6625 16:53:33.128063 [CA 1] Center 36 (8~64) winsize 57
6626 16:53:33.128144 [CA 2] Center 36 (8~64) winsize 57
6627 16:53:33.131394 [CA 3] Center 36 (8~64) winsize 57
6628 16:53:33.134348 [CA 4] Center 36 (8~64) winsize 57
6629 16:53:33.137660 [CA 5] Center 36 (8~64) winsize 57
6630 16:53:33.137742
6631 16:53:33.144296 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 16:53:33.144381
6633 16:53:33.148269 [CATrainingPosCal] consider 2 rank data
6634 16:53:33.148367 u2DelayCellTimex100 = 270/100 ps
6635 16:53:33.154468 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 16:53:33.157845 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 16:53:33.160987 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 16:53:33.164206 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 16:53:33.167828 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 16:53:33.170920 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 16:53:33.171034
6642 16:53:33.174213 CA PerBit enable=1, Macro0, CA PI delay=36
6643 16:53:33.174295
6644 16:53:33.177827 [CBTSetCACLKResult] CA Dly = 36
6645 16:53:33.181181 CS Dly: 1 (0~32)
6646 16:53:33.181263
6647 16:53:33.184200 ----->DramcWriteLeveling(PI) begin...
6648 16:53:33.184283 ==
6649 16:53:33.187779 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 16:53:33.190787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 16:53:33.190869 ==
6652 16:53:33.194415 Write leveling (Byte 0): 40 => 8
6653 16:53:33.197422 Write leveling (Byte 1): 40 => 8
6654 16:53:33.200607 DramcWriteLeveling(PI) end<-----
6655 16:53:33.200689
6656 16:53:33.200753 ==
6657 16:53:33.204423 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 16:53:33.207507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 16:53:33.207648 ==
6660 16:53:33.210520 [Gating] SW mode calibration
6661 16:53:33.217524 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6662 16:53:33.223781 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6663 16:53:33.227476 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 16:53:33.230493 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 16:53:33.237012 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 16:53:33.240182 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 16:53:33.243775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 16:53:33.250115 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 16:53:33.253267 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 16:53:33.256675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 16:53:33.263608 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 16:53:33.266764 Total UI for P1: 0, mck2ui 16
6673 16:53:33.269992 best dqsien dly found for B0: ( 0, 14, 24)
6674 16:53:33.273280 Total UI for P1: 0, mck2ui 16
6675 16:53:33.276407 best dqsien dly found for B1: ( 0, 14, 24)
6676 16:53:33.279491 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6677 16:53:33.283259 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6678 16:53:33.283341
6679 16:53:33.286274 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 16:53:33.289800 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 16:53:33.293486 [Gating] SW calibration Done
6682 16:53:33.293568 ==
6683 16:53:33.296172 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 16:53:33.299331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 16:53:33.302632 ==
6686 16:53:33.302714 RX Vref Scan: 0
6687 16:53:33.302779
6688 16:53:33.306163 RX Vref 0 -> 0, step: 1
6689 16:53:33.306245
6690 16:53:33.309455 RX Delay -410 -> 252, step: 16
6691 16:53:33.312446 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6692 16:53:33.316188 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6693 16:53:33.319243 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6694 16:53:33.326237 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6695 16:53:33.329203 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6696 16:53:33.332240 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6697 16:53:33.335960 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6698 16:53:33.342668 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6699 16:53:33.345848 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6700 16:53:33.348923 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6701 16:53:33.352035 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6702 16:53:33.359044 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6703 16:53:33.361996 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6704 16:53:33.365391 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6705 16:53:33.371840 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6706 16:53:33.375363 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6707 16:53:33.375440 ==
6708 16:53:33.378729 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 16:53:33.381807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 16:53:33.381884 ==
6711 16:53:33.384993 DQS Delay:
6712 16:53:33.385062 DQS0 = 51, DQS1 = 67
6713 16:53:33.388133 DQM Delay:
6714 16:53:33.388200 DQM0 = 12, DQM1 = 16
6715 16:53:33.388261 DQ Delay:
6716 16:53:33.391801 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6717 16:53:33.394760 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6718 16:53:33.398265 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6719 16:53:33.401335 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6720 16:53:33.401409
6721 16:53:33.401471
6722 16:53:33.401533 ==
6723 16:53:33.405235 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 16:53:33.411417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 16:53:33.411490 ==
6726 16:53:33.411551
6727 16:53:33.411655
6728 16:53:33.411713 TX Vref Scan disable
6729 16:53:33.414656 == TX Byte 0 ==
6730 16:53:33.418462 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 16:53:33.421460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 16:53:33.424717 == TX Byte 1 ==
6733 16:53:33.427762 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 16:53:33.431185 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 16:53:33.431255 ==
6736 16:53:33.434880 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 16:53:33.441271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 16:53:33.441388 ==
6739 16:53:33.441456
6740 16:53:33.441516
6741 16:53:33.444685 TX Vref Scan disable
6742 16:53:33.444755 == TX Byte 0 ==
6743 16:53:33.447855 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 16:53:33.450975 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 16:53:33.454065 == TX Byte 1 ==
6746 16:53:33.457771 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 16:53:33.460643 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 16:53:33.464367
6749 16:53:33.464445 [DATLAT]
6750 16:53:33.464514 Freq=400, CH1 RK0
6751 16:53:33.464576
6752 16:53:33.467673 DATLAT Default: 0xf
6753 16:53:33.467749 0, 0xFFFF, sum = 0
6754 16:53:33.470707 1, 0xFFFF, sum = 0
6755 16:53:33.470787 2, 0xFFFF, sum = 0
6756 16:53:33.473734 3, 0xFFFF, sum = 0
6757 16:53:33.477583 4, 0xFFFF, sum = 0
6758 16:53:33.477661 5, 0xFFFF, sum = 0
6759 16:53:33.481000 6, 0xFFFF, sum = 0
6760 16:53:33.481076 7, 0xFFFF, sum = 0
6761 16:53:33.483968 8, 0xFFFF, sum = 0
6762 16:53:33.484048 9, 0xFFFF, sum = 0
6763 16:53:33.486994 10, 0xFFFF, sum = 0
6764 16:53:33.487066 11, 0xFFFF, sum = 0
6765 16:53:33.490753 12, 0xFFFF, sum = 0
6766 16:53:33.490826 13, 0x0, sum = 1
6767 16:53:33.493957 14, 0x0, sum = 2
6768 16:53:33.494028 15, 0x0, sum = 3
6769 16:53:33.497013 16, 0x0, sum = 4
6770 16:53:33.497084 best_step = 14
6771 16:53:33.497143
6772 16:53:33.497204 ==
6773 16:53:33.500590 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 16:53:33.503472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 16:53:33.506816 ==
6776 16:53:33.506886 RX Vref Scan: 1
6777 16:53:33.506951
6778 16:53:33.510420 RX Vref 0 -> 0, step: 1
6779 16:53:33.510486
6780 16:53:33.513622 RX Delay -375 -> 252, step: 8
6781 16:53:33.513691
6782 16:53:33.516695 Set Vref, RX VrefLevel [Byte0]: 51
6783 16:53:33.520492 [Byte1]: 50
6784 16:53:33.520564
6785 16:53:33.523743 Final RX Vref Byte 0 = 51 to rank0
6786 16:53:33.527000 Final RX Vref Byte 1 = 50 to rank0
6787 16:53:33.530039 Final RX Vref Byte 0 = 51 to rank1
6788 16:53:33.532967 Final RX Vref Byte 1 = 50 to rank1==
6789 16:53:33.536737 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 16:53:33.539671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 16:53:33.543188 ==
6792 16:53:33.543264 DQS Delay:
6793 16:53:33.543325 DQS0 = 56, DQS1 = 68
6794 16:53:33.546352 DQM Delay:
6795 16:53:33.546421 DQM0 = 13, DQM1 = 14
6796 16:53:33.549311 DQ Delay:
6797 16:53:33.552660 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6798 16:53:33.556272 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =12
6799 16:53:33.556346 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6800 16:53:33.559294 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6801 16:53:33.562914
6802 16:53:33.562980
6803 16:53:33.569539 [DQSOSCAuto] RK0, (LSB)MR18= 0x566a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6804 16:53:33.572904 CH1 RK0: MR19=C0C, MR18=566A
6805 16:53:33.579279 CH1_RK0: MR19=0xC0C, MR18=0x566A, DQSOSC=396, MR23=63, INC=376, DEC=251
6806 16:53:33.579362 ==
6807 16:53:33.582746 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 16:53:33.585805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 16:53:33.585879 ==
6810 16:53:33.589458 [Gating] SW mode calibration
6811 16:53:33.595664 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6812 16:53:33.602586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6813 16:53:33.605559 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
6814 16:53:33.608782 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 16:53:33.615550 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 16:53:33.618623 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 16:53:33.621976 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 16:53:33.628949 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 16:53:33.632213 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 16:53:33.635367 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 16:53:33.641986 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 16:53:33.645132 Total UI for P1: 0, mck2ui 16
6823 16:53:33.648222 best dqsien dly found for B0: ( 0, 14, 24)
6824 16:53:33.648323 Total UI for P1: 0, mck2ui 16
6825 16:53:33.654656 best dqsien dly found for B1: ( 0, 14, 24)
6826 16:53:33.658614 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6827 16:53:33.661674 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6828 16:53:33.661750
6829 16:53:33.664639 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 16:53:33.667907 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 16:53:33.671569 [Gating] SW calibration Done
6832 16:53:33.671664 ==
6833 16:53:33.674867 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 16:53:33.677996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 16:53:33.678100 ==
6836 16:53:33.681338 RX Vref Scan: 0
6837 16:53:33.681410
6838 16:53:33.684242 RX Vref 0 -> 0, step: 1
6839 16:53:33.684323
6840 16:53:33.684391 RX Delay -410 -> 252, step: 16
6841 16:53:33.691318 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6842 16:53:33.694627 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6843 16:53:33.698127 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6844 16:53:33.704412 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6845 16:53:33.707971 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6846 16:53:33.711036 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6847 16:53:33.714621 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6848 16:53:33.720793 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6849 16:53:33.723982 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6850 16:53:33.727223 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6851 16:53:33.730963 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6852 16:53:33.737179 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6853 16:53:33.740877 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6854 16:53:33.743957 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6855 16:53:33.747058 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6856 16:53:33.753839 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6857 16:53:33.753921 ==
6858 16:53:33.757404 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 16:53:33.760284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 16:53:33.760389 ==
6861 16:53:33.763370 DQS Delay:
6862 16:53:33.763469 DQS0 = 59, DQS1 = 59
6863 16:53:33.763561 DQM Delay:
6864 16:53:33.767059 DQM0 = 18, DQM1 = 14
6865 16:53:33.767161 DQ Delay:
6866 16:53:33.770697 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6867 16:53:33.773834 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6868 16:53:33.776951 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6869 16:53:33.780079 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6870 16:53:33.780165
6871 16:53:33.780230
6872 16:53:33.780292 ==
6873 16:53:33.783225 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 16:53:33.790277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 16:53:33.790361 ==
6876 16:53:33.790428
6877 16:53:33.790489
6878 16:53:33.790548 TX Vref Scan disable
6879 16:53:33.793148 == TX Byte 0 ==
6880 16:53:33.796499 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6881 16:53:33.799912 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6882 16:53:33.803465 == TX Byte 1 ==
6883 16:53:33.806378 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 16:53:33.809935 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 16:53:33.810020 ==
6886 16:53:33.813089 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 16:53:33.819670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 16:53:33.819754 ==
6889 16:53:33.819820
6890 16:53:33.819881
6891 16:53:33.819939 TX Vref Scan disable
6892 16:53:33.823396 == TX Byte 0 ==
6893 16:53:33.826632 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 16:53:33.829737 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 16:53:33.832957 == TX Byte 1 ==
6896 16:53:33.836231 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 16:53:33.839768 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 16:53:33.839851
6899 16:53:33.842898 [DATLAT]
6900 16:53:33.843010 Freq=400, CH1 RK1
6901 16:53:33.843076
6902 16:53:33.846045 DATLAT Default: 0xe
6903 16:53:33.846157 0, 0xFFFF, sum = 0
6904 16:53:33.849407 1, 0xFFFF, sum = 0
6905 16:53:33.849513 2, 0xFFFF, sum = 0
6906 16:53:33.852533 3, 0xFFFF, sum = 0
6907 16:53:33.852636 4, 0xFFFF, sum = 0
6908 16:53:33.855675 5, 0xFFFF, sum = 0
6909 16:53:33.855776 6, 0xFFFF, sum = 0
6910 16:53:33.858850 7, 0xFFFF, sum = 0
6911 16:53:33.862511 8, 0xFFFF, sum = 0
6912 16:53:33.862611 9, 0xFFFF, sum = 0
6913 16:53:33.865474 10, 0xFFFF, sum = 0
6914 16:53:33.865575 11, 0xFFFF, sum = 0
6915 16:53:33.869269 12, 0xFFFF, sum = 0
6916 16:53:33.869379 13, 0x0, sum = 1
6917 16:53:33.872373 14, 0x0, sum = 2
6918 16:53:33.872477 15, 0x0, sum = 3
6919 16:53:33.876019 16, 0x0, sum = 4
6920 16:53:33.876093 best_step = 14
6921 16:53:33.876155
6922 16:53:33.876243 ==
6923 16:53:33.879338 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 16:53:33.882432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 16:53:33.882533 ==
6926 16:53:33.885540 RX Vref Scan: 0
6927 16:53:33.885638
6928 16:53:33.888665 RX Vref 0 -> 0, step: 1
6929 16:53:33.888764
6930 16:53:33.888859 RX Delay -359 -> 252, step: 8
6931 16:53:33.898036 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6932 16:53:33.901381 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6933 16:53:33.904748 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6934 16:53:33.911272 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6935 16:53:33.914033 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6936 16:53:33.917703 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6937 16:53:33.920516 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6938 16:53:33.927599 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6939 16:53:33.930855 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6940 16:53:33.934089 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6941 16:53:33.937172 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6942 16:53:33.944148 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6943 16:53:33.947269 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6944 16:53:33.950671 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6945 16:53:33.953702 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6946 16:53:33.960646 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6947 16:53:33.960761 ==
6948 16:53:33.963687 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 16:53:33.966972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 16:53:33.967057 ==
6951 16:53:33.970026 DQS Delay:
6952 16:53:33.970110 DQS0 = 60, DQS1 = 64
6953 16:53:33.970177 DQM Delay:
6954 16:53:33.973468 DQM0 = 13, DQM1 = 10
6955 16:53:33.973551 DQ Delay:
6956 16:53:33.976368 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6957 16:53:33.979737 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6958 16:53:33.983443 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6959 16:53:33.986122 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6960 16:53:33.986206
6961 16:53:33.986273
6962 16:53:33.996252 [DQSOSCAuto] RK1, (LSB)MR18= 0x76a5, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 394 ps
6963 16:53:33.996371 CH1 RK1: MR19=C0C, MR18=76A5
6964 16:53:34.002505 CH1_RK1: MR19=0xC0C, MR18=0x76A5, DQSOSC=389, MR23=63, INC=390, DEC=260
6965 16:53:34.006457 [RxdqsGatingPostProcess] freq 400
6966 16:53:34.012590 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6967 16:53:34.015793 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 16:53:34.019401 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 16:53:34.022495 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 16:53:34.026017 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 16:53:34.028710 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 16:53:34.032497 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 16:53:34.035404 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 16:53:34.039272 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 16:53:34.042311 Pre-setting of DQS Precalculation
6976 16:53:34.045483 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6977 16:53:34.051912 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6978 16:53:34.058552 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6979 16:53:34.058637
6980 16:53:34.062269
6981 16:53:34.062358 [Calibration Summary] 800 Mbps
6982 16:53:34.065473 CH 0, Rank 0
6983 16:53:34.065560 SW Impedance : PASS
6984 16:53:34.068708 DUTY Scan : NO K
6985 16:53:34.071801 ZQ Calibration : PASS
6986 16:53:34.071879 Jitter Meter : NO K
6987 16:53:34.075388 CBT Training : PASS
6988 16:53:34.078406 Write leveling : PASS
6989 16:53:34.078483 RX DQS gating : PASS
6990 16:53:34.081907 RX DQ/DQS(RDDQC) : PASS
6991 16:53:34.085038 TX DQ/DQS : PASS
6992 16:53:34.085114 RX DATLAT : PASS
6993 16:53:34.088472 RX DQ/DQS(Engine): PASS
6994 16:53:34.091678 TX OE : NO K
6995 16:53:34.091760 All Pass.
6996 16:53:34.091825
6997 16:53:34.091885 CH 0, Rank 1
6998 16:53:34.095339 SW Impedance : PASS
6999 16:53:34.098387 DUTY Scan : NO K
7000 16:53:34.098468 ZQ Calibration : PASS
7001 16:53:34.101376 Jitter Meter : NO K
7002 16:53:34.104993 CBT Training : PASS
7003 16:53:34.105075 Write leveling : NO K
7004 16:53:34.108333 RX DQS gating : PASS
7005 16:53:34.111525 RX DQ/DQS(RDDQC) : PASS
7006 16:53:34.111663 TX DQ/DQS : PASS
7007 16:53:34.114571 RX DATLAT : PASS
7008 16:53:34.114653 RX DQ/DQS(Engine): PASS
7009 16:53:34.118268 TX OE : NO K
7010 16:53:34.118352 All Pass.
7011 16:53:34.118419
7012 16:53:34.121179 CH 1, Rank 0
7013 16:53:34.121263 SW Impedance : PASS
7014 16:53:34.124757 DUTY Scan : NO K
7015 16:53:34.128004 ZQ Calibration : PASS
7016 16:53:34.128094 Jitter Meter : NO K
7017 16:53:34.131233 CBT Training : PASS
7018 16:53:34.134730 Write leveling : PASS
7019 16:53:34.134823 RX DQS gating : PASS
7020 16:53:34.137716 RX DQ/DQS(RDDQC) : PASS
7021 16:53:34.141157 TX DQ/DQS : PASS
7022 16:53:34.141247 RX DATLAT : PASS
7023 16:53:34.144347 RX DQ/DQS(Engine): PASS
7024 16:53:34.147990 TX OE : NO K
7025 16:53:34.148080 All Pass.
7026 16:53:34.148147
7027 16:53:34.148208 CH 1, Rank 1
7028 16:53:34.151069 SW Impedance : PASS
7029 16:53:34.154424 DUTY Scan : NO K
7030 16:53:34.154505 ZQ Calibration : PASS
7031 16:53:34.157507 Jitter Meter : NO K
7032 16:53:34.161083 CBT Training : PASS
7033 16:53:34.161196 Write leveling : NO K
7034 16:53:34.164380 RX DQS gating : PASS
7035 16:53:34.167405 RX DQ/DQS(RDDQC) : PASS
7036 16:53:34.167498 TX DQ/DQS : PASS
7037 16:53:34.170678 RX DATLAT : PASS
7038 16:53:34.173921 RX DQ/DQS(Engine): PASS
7039 16:53:34.174003 TX OE : NO K
7040 16:53:34.177652 All Pass.
7041 16:53:34.177734
7042 16:53:34.177798 DramC Write-DBI off
7043 16:53:34.180563 PER_BANK_REFRESH: Hybrid Mode
7044 16:53:34.180645 TX_TRACKING: ON
7045 16:53:34.190879 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7046 16:53:34.193969 [FAST_K] Save calibration result to emmc
7047 16:53:34.197395 dramc_set_vcore_voltage set vcore to 725000
7048 16:53:34.200558 Read voltage for 1600, 0
7049 16:53:34.200670 Vio18 = 0
7050 16:53:34.203696 Vcore = 725000
7051 16:53:34.203778 Vdram = 0
7052 16:53:34.203850 Vddq = 0
7053 16:53:34.207274 Vmddr = 0
7054 16:53:34.210477 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7055 16:53:34.216707 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7056 16:53:34.216789 MEM_TYPE=3, freq_sel=13
7057 16:53:34.220589 sv_algorithm_assistance_LP4_3733
7058 16:53:34.226601 ============ PULL DRAM RESETB DOWN ============
7059 16:53:34.230213 ========== PULL DRAM RESETB DOWN end =========
7060 16:53:34.233149 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7061 16:53:34.236940 ===================================
7062 16:53:34.240237 LPDDR4 DRAM CONFIGURATION
7063 16:53:34.243067 ===================================
7064 16:53:34.246732 EX_ROW_EN[0] = 0x0
7065 16:53:34.246813 EX_ROW_EN[1] = 0x0
7066 16:53:34.249828 LP4Y_EN = 0x0
7067 16:53:34.249909 WORK_FSP = 0x1
7068 16:53:34.253154 WL = 0x5
7069 16:53:34.253262 RL = 0x5
7070 16:53:34.256144 BL = 0x2
7071 16:53:34.256225 RPST = 0x0
7072 16:53:34.260290 RD_PRE = 0x0
7073 16:53:34.260371 WR_PRE = 0x1
7074 16:53:34.263107 WR_PST = 0x1
7075 16:53:34.263187 DBI_WR = 0x0
7076 16:53:34.266031 DBI_RD = 0x0
7077 16:53:34.266112 OTF = 0x1
7078 16:53:34.269998 ===================================
7079 16:53:34.273073 ===================================
7080 16:53:34.276213 ANA top config
7081 16:53:34.279335 ===================================
7082 16:53:34.282991 DLL_ASYNC_EN = 0
7083 16:53:34.283072 ALL_SLAVE_EN = 0
7084 16:53:34.286000 NEW_RANK_MODE = 1
7085 16:53:34.289740 DLL_IDLE_MODE = 1
7086 16:53:34.292976 LP45_APHY_COMB_EN = 1
7087 16:53:34.296097 TX_ODT_DIS = 0
7088 16:53:34.296206 NEW_8X_MODE = 1
7089 16:53:34.299155 ===================================
7090 16:53:34.302320 ===================================
7091 16:53:34.305674 data_rate = 3200
7092 16:53:34.309379 CKR = 1
7093 16:53:34.312287 DQ_P2S_RATIO = 8
7094 16:53:34.315866 ===================================
7095 16:53:34.319113 CA_P2S_RATIO = 8
7096 16:53:34.322257 DQ_CA_OPEN = 0
7097 16:53:34.322338 DQ_SEMI_OPEN = 0
7098 16:53:34.325320 CA_SEMI_OPEN = 0
7099 16:53:34.329096 CA_FULL_RATE = 0
7100 16:53:34.332119 DQ_CKDIV4_EN = 0
7101 16:53:34.335147 CA_CKDIV4_EN = 0
7102 16:53:34.338898 CA_PREDIV_EN = 0
7103 16:53:34.338984 PH8_DLY = 12
7104 16:53:34.341990 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7105 16:53:34.345602 DQ_AAMCK_DIV = 4
7106 16:53:34.348621 CA_AAMCK_DIV = 4
7107 16:53:34.351848 CA_ADMCK_DIV = 4
7108 16:53:34.355273 DQ_TRACK_CA_EN = 0
7109 16:53:34.358857 CA_PICK = 1600
7110 16:53:34.358953 CA_MCKIO = 1600
7111 16:53:34.361942 MCKIO_SEMI = 0
7112 16:53:34.365449 PLL_FREQ = 3068
7113 16:53:34.368357 DQ_UI_PI_RATIO = 32
7114 16:53:34.371998 CA_UI_PI_RATIO = 0
7115 16:53:34.375299 ===================================
7116 16:53:34.378470 ===================================
7117 16:53:34.381624 memory_type:LPDDR4
7118 16:53:34.381706 GP_NUM : 10
7119 16:53:34.384697 SRAM_EN : 1
7120 16:53:34.388317 MD32_EN : 0
7121 16:53:34.391318 ===================================
7122 16:53:34.391399 [ANA_INIT] >>>>>>>>>>>>>>
7123 16:53:34.394385 <<<<<< [CONFIGURE PHASE]: ANA_TX
7124 16:53:34.397991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7125 16:53:34.401088 ===================================
7126 16:53:34.404258 data_rate = 3200,PCW = 0X7600
7127 16:53:34.407891 ===================================
7128 16:53:34.410801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7129 16:53:34.417692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 16:53:34.420891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 16:53:34.427511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7132 16:53:34.430710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7133 16:53:34.433869 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7134 16:53:34.437574 [ANA_INIT] flow start
7135 16:53:34.437688 [ANA_INIT] PLL >>>>>>>>
7136 16:53:34.440706 [ANA_INIT] PLL <<<<<<<<
7137 16:53:34.444129 [ANA_INIT] MIDPI >>>>>>>>
7138 16:53:34.444211 [ANA_INIT] MIDPI <<<<<<<<
7139 16:53:34.447355 [ANA_INIT] DLL >>>>>>>>
7140 16:53:34.450497 [ANA_INIT] DLL <<<<<<<<
7141 16:53:34.450578 [ANA_INIT] flow end
7142 16:53:34.456969 ============ LP4 DIFF to SE enter ============
7143 16:53:34.460667 ============ LP4 DIFF to SE exit ============
7144 16:53:34.463804 [ANA_INIT] <<<<<<<<<<<<<
7145 16:53:34.466834 [Flow] Enable top DCM control >>>>>
7146 16:53:34.470473 [Flow] Enable top DCM control <<<<<
7147 16:53:34.470557 Enable DLL master slave shuffle
7148 16:53:34.477198 ==============================================================
7149 16:53:34.480239 Gating Mode config
7150 16:53:34.483463 ==============================================================
7151 16:53:34.486574 Config description:
7152 16:53:34.496551 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7153 16:53:34.503446 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7154 16:53:34.506590 SELPH_MODE 0: By rank 1: By Phase
7155 16:53:34.512815 ==============================================================
7156 16:53:34.516367 GAT_TRACK_EN = 1
7157 16:53:34.519603 RX_GATING_MODE = 2
7158 16:53:34.523134 RX_GATING_TRACK_MODE = 2
7159 16:53:34.526009 SELPH_MODE = 1
7160 16:53:34.529424 PICG_EARLY_EN = 1
7161 16:53:34.529506 VALID_LAT_VALUE = 1
7162 16:53:34.536466 ==============================================================
7163 16:53:34.539541 Enter into Gating configuration >>>>
7164 16:53:34.542662 Exit from Gating configuration <<<<
7165 16:53:34.545960 Enter into DVFS_PRE_config >>>>>
7166 16:53:34.555904 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7167 16:53:34.558984 Exit from DVFS_PRE_config <<<<<
7168 16:53:34.562458 Enter into PICG configuration >>>>
7169 16:53:34.565848 Exit from PICG configuration <<<<
7170 16:53:34.569101 [RX_INPUT] configuration >>>>>
7171 16:53:34.572510 [RX_INPUT] configuration <<<<<
7172 16:53:34.579088 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7173 16:53:34.582383 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7174 16:53:34.589201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 16:53:34.595640 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 16:53:34.602241 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 16:53:34.608636 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 16:53:34.611794 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7179 16:53:34.615520 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7180 16:53:34.618759 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7181 16:53:34.625062 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7182 16:53:34.628610 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7183 16:53:34.631697 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 16:53:34.634751 ===================================
7185 16:53:34.638159 LPDDR4 DRAM CONFIGURATION
7186 16:53:34.641548 ===================================
7187 16:53:34.645052 EX_ROW_EN[0] = 0x0
7188 16:53:34.645129 EX_ROW_EN[1] = 0x0
7189 16:53:34.648048 LP4Y_EN = 0x0
7190 16:53:34.648124 WORK_FSP = 0x1
7191 16:53:34.651471 WL = 0x5
7192 16:53:34.651572 RL = 0x5
7193 16:53:34.654639 BL = 0x2
7194 16:53:34.654738 RPST = 0x0
7195 16:53:34.657901 RD_PRE = 0x0
7196 16:53:34.657999 WR_PRE = 0x1
7197 16:53:34.661063 WR_PST = 0x1
7198 16:53:34.661179 DBI_WR = 0x0
7199 16:53:34.664757 DBI_RD = 0x0
7200 16:53:34.664859 OTF = 0x1
7201 16:53:34.667723 ===================================
7202 16:53:34.674453 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7203 16:53:34.677459 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7204 16:53:34.680919 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 16:53:34.684410 ===================================
7206 16:53:34.687513 LPDDR4 DRAM CONFIGURATION
7207 16:53:34.691215 ===================================
7208 16:53:34.694362 EX_ROW_EN[0] = 0x10
7209 16:53:34.694460 EX_ROW_EN[1] = 0x0
7210 16:53:34.697554 LP4Y_EN = 0x0
7211 16:53:34.697652 WORK_FSP = 0x1
7212 16:53:34.700715 WL = 0x5
7213 16:53:34.700788 RL = 0x5
7214 16:53:34.704181 BL = 0x2
7215 16:53:34.704252 RPST = 0x0
7216 16:53:34.707327 RD_PRE = 0x0
7217 16:53:34.707424 WR_PRE = 0x1
7218 16:53:34.710609 WR_PST = 0x1
7219 16:53:34.710681 DBI_WR = 0x0
7220 16:53:34.713972 DBI_RD = 0x0
7221 16:53:34.714068 OTF = 0x1
7222 16:53:34.717092 ===================================
7223 16:53:34.723787 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7224 16:53:34.723862 ==
7225 16:53:34.726969 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 16:53:34.733600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7227 16:53:34.733704 ==
7228 16:53:34.733800 [Duty_Offset_Calibration]
7229 16:53:34.737507 B0:2 B1:0 CA:3
7230 16:53:34.737607
7231 16:53:34.740557 [DutyScan_Calibration_Flow] k_type=0
7232 16:53:34.750208
7233 16:53:34.750307 ==CLK 0==
7234 16:53:34.753096 Final CLK duty delay cell = 0
7235 16:53:34.756611 [0] MAX Duty = 5031%(X100), DQS PI = 12
7236 16:53:34.760148 [0] MIN Duty = 4907%(X100), DQS PI = 0
7237 16:53:34.760226 [0] AVG Duty = 4969%(X100)
7238 16:53:34.762993
7239 16:53:34.766245 CH0 CLK Duty spec in!! Max-Min= 124%
7240 16:53:34.769928 [DutyScan_Calibration_Flow] ====Done====
7241 16:53:34.770031
7242 16:53:34.772990 [DutyScan_Calibration_Flow] k_type=1
7243 16:53:34.789483
7244 16:53:34.789589 ==DQS 0 ==
7245 16:53:34.792961 Final DQS duty delay cell = 0
7246 16:53:34.796326 [0] MAX Duty = 5094%(X100), DQS PI = 14
7247 16:53:34.799466 [0] MIN Duty = 4875%(X100), DQS PI = 0
7248 16:53:34.803176 [0] AVG Duty = 4984%(X100)
7249 16:53:34.803276
7250 16:53:34.803366 ==DQS 1 ==
7251 16:53:34.806240 Final DQS duty delay cell = 0
7252 16:53:34.809339 [0] MAX Duty = 5156%(X100), DQS PI = 30
7253 16:53:34.813171 [0] MIN Duty = 5031%(X100), DQS PI = 12
7254 16:53:34.816236 [0] AVG Duty = 5093%(X100)
7255 16:53:34.816313
7256 16:53:34.819373 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7257 16:53:34.819470
7258 16:53:34.822318 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7259 16:53:34.825547 [DutyScan_Calibration_Flow] ====Done====
7260 16:53:34.825645
7261 16:53:34.829110 [DutyScan_Calibration_Flow] k_type=3
7262 16:53:34.847705
7263 16:53:34.847781 ==DQM 0 ==
7264 16:53:34.850677 Final DQM duty delay cell = 0
7265 16:53:34.853766 [0] MAX Duty = 5156%(X100), DQS PI = 30
7266 16:53:34.857353 [0] MIN Duty = 4875%(X100), DQS PI = 0
7267 16:53:34.860453 [0] AVG Duty = 5015%(X100)
7268 16:53:34.860533
7269 16:53:34.860597 ==DQM 1 ==
7270 16:53:34.863722 Final DQM duty delay cell = 4
7271 16:53:34.867334 [4] MAX Duty = 5187%(X100), DQS PI = 62
7272 16:53:34.870853 [4] MIN Duty = 5031%(X100), DQS PI = 14
7273 16:53:34.873993 [4] AVG Duty = 5109%(X100)
7274 16:53:34.874097
7275 16:53:34.877006 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7276 16:53:34.877104
7277 16:53:34.880148 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7278 16:53:34.883626 [DutyScan_Calibration_Flow] ====Done====
7279 16:53:34.883703
7280 16:53:34.887304 [DutyScan_Calibration_Flow] k_type=2
7281 16:53:34.903785
7282 16:53:34.903863 ==DQ 0 ==
7283 16:53:34.906833 Final DQ duty delay cell = -4
7284 16:53:34.909955 [-4] MAX Duty = 5000%(X100), DQS PI = 12
7285 16:53:34.913427 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7286 16:53:34.916534 [-4] AVG Duty = 4938%(X100)
7287 16:53:34.916605
7288 16:53:34.916666 ==DQ 1 ==
7289 16:53:34.920463 Final DQ duty delay cell = 0
7290 16:53:34.923489 [0] MAX Duty = 5156%(X100), DQS PI = 58
7291 16:53:34.926704 [0] MIN Duty = 5000%(X100), DQS PI = 16
7292 16:53:34.929763 [0] AVG Duty = 5078%(X100)
7293 16:53:34.929836
7294 16:53:34.933033 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7295 16:53:34.933103
7296 16:53:34.936712 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7297 16:53:34.939706 [DutyScan_Calibration_Flow] ====Done====
7298 16:53:34.939775 ==
7299 16:53:34.943519 Dram Type= 6, Freq= 0, CH_1, rank 0
7300 16:53:34.946568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 16:53:34.946649 ==
7302 16:53:34.949726 [Duty_Offset_Calibration]
7303 16:53:34.949806 B0:1 B1:-2 CA:1
7304 16:53:34.952851
7305 16:53:34.956043 [DutyScan_Calibration_Flow] k_type=0
7306 16:53:34.964384
7307 16:53:34.964463 ==CLK 0==
7308 16:53:34.967471 Final CLK duty delay cell = 0
7309 16:53:34.971047 [0] MAX Duty = 5062%(X100), DQS PI = 20
7310 16:53:34.973870 [0] MIN Duty = 4844%(X100), DQS PI = 0
7311 16:53:34.977460 [0] AVG Duty = 4953%(X100)
7312 16:53:34.977534
7313 16:53:34.980711 CH1 CLK Duty spec in!! Max-Min= 218%
7314 16:53:34.983923 [DutyScan_Calibration_Flow] ====Done====
7315 16:53:34.984003
7316 16:53:34.986961 [DutyScan_Calibration_Flow] k_type=1
7317 16:53:35.003003
7318 16:53:35.003084 ==DQS 0 ==
7319 16:53:35.005999 Final DQS duty delay cell = -4
7320 16:53:35.009258 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7321 16:53:35.012739 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7322 16:53:35.015773 [-4] AVG Duty = 4906%(X100)
7323 16:53:35.015853
7324 16:53:35.015916 ==DQS 1 ==
7325 16:53:35.019476 Final DQS duty delay cell = 0
7326 16:53:35.022586 [0] MAX Duty = 5093%(X100), DQS PI = 60
7327 16:53:35.025724 [0] MIN Duty = 4844%(X100), DQS PI = 24
7328 16:53:35.029498 [0] AVG Duty = 4968%(X100)
7329 16:53:35.029577
7330 16:53:35.032900 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7331 16:53:35.032980
7332 16:53:35.035797 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7333 16:53:35.038860 [DutyScan_Calibration_Flow] ====Done====
7334 16:53:35.038933
7335 16:53:35.041931 [DutyScan_Calibration_Flow] k_type=3
7336 16:53:35.059928
7337 16:53:35.060003 ==DQM 0 ==
7338 16:53:35.063582 Final DQM duty delay cell = 0
7339 16:53:35.066453 [0] MAX Duty = 5031%(X100), DQS PI = 24
7340 16:53:35.070131 [0] MIN Duty = 4813%(X100), DQS PI = 54
7341 16:53:35.073220 [0] AVG Duty = 4922%(X100)
7342 16:53:35.073300
7343 16:53:35.073361 ==DQM 1 ==
7344 16:53:35.076373 Final DQM duty delay cell = 0
7345 16:53:35.079800 [0] MAX Duty = 5093%(X100), DQS PI = 36
7346 16:53:35.083333 [0] MIN Duty = 4875%(X100), DQS PI = 26
7347 16:53:35.086652 [0] AVG Duty = 4984%(X100)
7348 16:53:35.086732
7349 16:53:35.089647 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7350 16:53:35.089726
7351 16:53:35.092825 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7352 16:53:35.095860 [DutyScan_Calibration_Flow] ====Done====
7353 16:53:35.095939
7354 16:53:35.099344 [DutyScan_Calibration_Flow] k_type=2
7355 16:53:35.116634
7356 16:53:35.116741 ==DQ 0 ==
7357 16:53:35.120160 Final DQ duty delay cell = 0
7358 16:53:35.123251 [0] MAX Duty = 5093%(X100), DQS PI = 22
7359 16:53:35.126893 [0] MIN Duty = 4907%(X100), DQS PI = 46
7360 16:53:35.126972 [0] AVG Duty = 5000%(X100)
7361 16:53:35.130100
7362 16:53:35.130179 ==DQ 1 ==
7363 16:53:35.133276 Final DQ duty delay cell = 0
7364 16:53:35.137148 [0] MAX Duty = 5125%(X100), DQS PI = 34
7365 16:53:35.140306 [0] MIN Duty = 4969%(X100), DQS PI = 24
7366 16:53:35.140398 [0] AVG Duty = 5047%(X100)
7367 16:53:35.143263
7368 16:53:35.146365 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7369 16:53:35.146445
7370 16:53:35.149658 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7371 16:53:35.153340 [DutyScan_Calibration_Flow] ====Done====
7372 16:53:35.156416 nWR fixed to 30
7373 16:53:35.159462 [ModeRegInit_LP4] CH0 RK0
7374 16:53:35.159543 [ModeRegInit_LP4] CH0 RK1
7375 16:53:35.162704 [ModeRegInit_LP4] CH1 RK0
7376 16:53:35.165945 [ModeRegInit_LP4] CH1 RK1
7377 16:53:35.166042 match AC timing 5
7378 16:53:35.173080 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7379 16:53:35.176181 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7380 16:53:35.179312 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7381 16:53:35.185904 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7382 16:53:35.189375 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7383 16:53:35.189449 [MiockJmeterHQA]
7384 16:53:35.192403
7385 16:53:35.192488 [DramcMiockJmeter] u1RxGatingPI = 0
7386 16:53:35.195642 0 : 4371, 4142
7387 16:53:35.195721 4 : 4255, 4029
7388 16:53:35.199359 8 : 4257, 4032
7389 16:53:35.199464 12 : 4366, 4139
7390 16:53:35.202512 16 : 4255, 4030
7391 16:53:35.202591 20 : 4258, 4029
7392 16:53:35.202654 24 : 4368, 4140
7393 16:53:35.205547 28 : 4257, 4029
7394 16:53:35.205622 32 : 4257, 4029
7395 16:53:35.208992 36 : 4257, 4030
7396 16:53:35.209067 40 : 4257, 4029
7397 16:53:35.212445 44 : 4366, 4140
7398 16:53:35.212520 48 : 4367, 4140
7399 16:53:35.215427 52 : 4257, 4029
7400 16:53:35.215498 56 : 4252, 4027
7401 16:53:35.215561 60 : 4257, 4029
7402 16:53:35.219184 64 : 4250, 4027
7403 16:53:35.219255 68 : 4257, 4031
7404 16:53:35.222230 72 : 4255, 4029
7405 16:53:35.222301 76 : 4252, 4029
7406 16:53:35.225682 80 : 4255, 4030
7407 16:53:35.225769 84 : 4253, 4029
7408 16:53:35.228574 88 : 4257, 4031
7409 16:53:35.228658 92 : 4255, 4029
7410 16:53:35.228723 96 : 4363, 4140
7411 16:53:35.232266 100 : 4252, 4027
7412 16:53:35.232343 104 : 4255, 3664
7413 16:53:35.235532 108 : 4252, 0
7414 16:53:35.235636 112 : 4255, 0
7415 16:53:35.238483 116 : 4253, 0
7416 16:53:35.238555 120 : 4253, 0
7417 16:53:35.238617 124 : 4366, 0
7418 16:53:35.242264 128 : 4252, 0
7419 16:53:35.242336 132 : 4252, 0
7420 16:53:35.245447 136 : 4361, 0
7421 16:53:35.245519 140 : 4252, 0
7422 16:53:35.245588 144 : 4363, 0
7423 16:53:35.248615 148 : 4363, 0
7424 16:53:35.248688 152 : 4368, 0
7425 16:53:35.248750 156 : 4252, 0
7426 16:53:35.252169 160 : 4255, 0
7427 16:53:35.252241 164 : 4255, 0
7428 16:53:35.255340 168 : 4257, 0
7429 16:53:35.255411 172 : 4252, 0
7430 16:53:35.255479 176 : 4366, 0
7431 16:53:35.258445 180 : 4253, 0
7432 16:53:35.258516 184 : 4252, 0
7433 16:53:35.262247 188 : 4252, 0
7434 16:53:35.262319 192 : 4257, 0
7435 16:53:35.262380 196 : 4363, 0
7436 16:53:35.265344 200 : 4363, 0
7437 16:53:35.265415 204 : 4368, 0
7438 16:53:35.268417 208 : 4255, 0
7439 16:53:35.268495 212 : 4250, 0
7440 16:53:35.268559 216 : 4255, 0
7441 16:53:35.272184 220 : 4257, 0
7442 16:53:35.272260 224 : 4363, 0
7443 16:53:35.274942 228 : 4252, 0
7444 16:53:35.275015 232 : 4252, 0
7445 16:53:35.275077 236 : 4252, 1324
7446 16:53:35.278210 240 : 4257, 4034
7447 16:53:35.278282 244 : 4255, 4029
7448 16:53:35.281780 248 : 4255, 4029
7449 16:53:35.281853 252 : 4253, 4029
7450 16:53:35.284793 256 : 4249, 4027
7451 16:53:35.284871 260 : 4367, 4143
7452 16:53:35.287941 264 : 4255, 4029
7453 16:53:35.288013 268 : 4255, 4029
7454 16:53:35.291698 272 : 4252, 4029
7455 16:53:35.291788 276 : 4257, 4032
7456 16:53:35.294510 280 : 4255, 4029
7457 16:53:35.294582 284 : 4253, 4029
7458 16:53:35.297898 288 : 4253, 4029
7459 16:53:35.297979 292 : 4253, 4029
7460 16:53:35.298043 296 : 4368, 4143
7461 16:53:35.301789 300 : 4255, 4029
7462 16:53:35.301860 304 : 4253, 4029
7463 16:53:35.304786 308 : 4363, 4140
7464 16:53:35.304859 312 : 4365, 4140
7465 16:53:35.307803 316 : 4255, 4029
7466 16:53:35.307881 320 : 4365, 4140
7467 16:53:35.311426 324 : 4363, 4140
7468 16:53:35.311497 328 : 4250, 4026
7469 16:53:35.314308 332 : 4366, 4140
7470 16:53:35.314379 336 : 4366, 4140
7471 16:53:35.317864 340 : 4253, 4029
7472 16:53:35.317940 344 : 4257, 4031
7473 16:53:35.321224 348 : 4255, 4029
7474 16:53:35.321304 352 : 4255, 4026
7475 16:53:35.324545 356 : 4363, 2845
7476 16:53:35.324624 360 : 4252, 1
7477 16:53:35.324685
7478 16:53:35.327464 MIOCK jitter meter ch=0
7479 16:53:35.327533
7480 16:53:35.330886 1T = (360-108) = 252 dly cells
7481 16:53:35.334270 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7482 16:53:35.334346 ==
7483 16:53:35.337338 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 16:53:35.344274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 16:53:35.344355 ==
7486 16:53:35.347334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 16:53:35.354268 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 16:53:35.357357 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 16:53:35.364181 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 16:53:35.372111 [CA 0] Center 44 (14~75) winsize 62
7491 16:53:35.375195 [CA 1] Center 43 (13~74) winsize 62
7492 16:53:35.378409 [CA 2] Center 40 (11~69) winsize 59
7493 16:53:35.382085 [CA 3] Center 39 (10~68) winsize 59
7494 16:53:35.384944 [CA 4] Center 37 (8~67) winsize 60
7495 16:53:35.388875 [CA 5] Center 37 (7~67) winsize 61
7496 16:53:35.389076
7497 16:53:35.391542 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 16:53:35.395553
7499 16:53:35.398501 [CATrainingPosCal] consider 1 rank data
7500 16:53:35.398727 u2DelayCellTimex100 = 258/100 ps
7501 16:53:35.405058 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7502 16:53:35.408164 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7503 16:53:35.412064 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7504 16:53:35.415130 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7505 16:53:35.418310 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7506 16:53:35.421329 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7507 16:53:35.421652
7508 16:53:35.424649 CA PerBit enable=1, Macro0, CA PI delay=37
7509 16:53:35.425044
7510 16:53:35.428112 [CBTSetCACLKResult] CA Dly = 37
7511 16:53:35.431442 CS Dly: 11 (0~42)
7512 16:53:35.435406 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 16:53:35.437899 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 16:53:35.441235 ==
7515 16:53:35.441698 Dram Type= 6, Freq= 0, CH_0, rank 1
7516 16:53:35.447840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 16:53:35.448407 ==
7518 16:53:35.451617 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 16:53:35.458288 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 16:53:35.461604 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 16:53:35.467909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 16:53:35.476245 [CA 0] Center 43 (13~74) winsize 62
7523 16:53:35.479615 [CA 1] Center 43 (13~74) winsize 62
7524 16:53:35.482765 [CA 2] Center 39 (10~68) winsize 59
7525 16:53:35.485838 [CA 3] Center 39 (10~68) winsize 59
7526 16:53:35.489351 [CA 4] Center 36 (7~66) winsize 60
7527 16:53:35.492477 [CA 5] Center 36 (6~66) winsize 61
7528 16:53:35.492942
7529 16:53:35.495771 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7530 16:53:35.499060
7531 16:53:35.503406 [CATrainingPosCal] consider 2 rank data
7532 16:53:35.504018 u2DelayCellTimex100 = 258/100 ps
7533 16:53:35.509229 CA0 delay=44 (14~74),Diff = 8 PI (30 cell)
7534 16:53:35.512228 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7535 16:53:35.515242 CA2 delay=39 (11~68),Diff = 3 PI (11 cell)
7536 16:53:35.518691 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7537 16:53:35.521957 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7538 16:53:35.525646 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7539 16:53:35.526153
7540 16:53:35.531850 CA PerBit enable=1, Macro0, CA PI delay=36
7541 16:53:35.532310
7542 16:53:35.532671 [CBTSetCACLKResult] CA Dly = 36
7543 16:53:35.535655 CS Dly: 11 (0~42)
7544 16:53:35.538510 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 16:53:35.541859 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 16:53:35.545256
7547 16:53:35.548646 ----->DramcWriteLeveling(PI) begin...
7548 16:53:35.549114 ==
7549 16:53:35.551405 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 16:53:35.555035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 16:53:35.555495 ==
7552 16:53:35.558580 Write leveling (Byte 0): 36 => 36
7553 16:53:35.562087 Write leveling (Byte 1): 27 => 27
7554 16:53:35.565198 DramcWriteLeveling(PI) end<-----
7555 16:53:35.565657
7556 16:53:35.566019 ==
7557 16:53:35.568244 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 16:53:35.571486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 16:53:35.572021 ==
7560 16:53:35.575309 [Gating] SW mode calibration
7561 16:53:35.581292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7562 16:53:35.588163 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7563 16:53:35.591152 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 16:53:35.594731 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 16:53:35.600973 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 16:53:35.604423 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 16:53:35.608158 1 4 16 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7568 16:53:35.614120 1 4 20 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7569 16:53:35.617807 1 4 24 | B1->B0 | 2f2e 3434 | 1 1 | (1 1) (1 1)
7570 16:53:35.620969 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 16:53:35.627497 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 16:53:35.631008 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 16:53:35.634118 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 16:53:35.640609 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7575 16:53:35.644290 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7576 16:53:35.647073 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
7577 16:53:35.654000 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7578 16:53:35.656830 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 16:53:35.661103 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 16:53:35.667088 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 16:53:35.670250 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 16:53:35.673589 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 16:53:35.680413 1 6 16 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7584 16:53:35.683736 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7585 16:53:35.686490 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7586 16:53:35.693335 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 16:53:35.696466 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 16:53:35.699770 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 16:53:35.706699 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 16:53:35.709841 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7591 16:53:35.712790 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 16:53:35.720115 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7593 16:53:35.723178 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 16:53:35.726325 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 16:53:35.732787 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 16:53:35.736275 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 16:53:35.739377 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 16:53:35.745731 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 16:53:35.749352 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 16:53:35.755833 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 16:53:35.759142 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 16:53:35.762161 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 16:53:35.765972 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 16:53:35.772133 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 16:53:35.775742 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 16:53:35.779004 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7607 16:53:35.785560 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7608 16:53:35.789192 Total UI for P1: 0, mck2ui 16
7609 16:53:35.791892 best dqsien dly found for B0: ( 1, 9, 14)
7610 16:53:35.795554 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7611 16:53:35.798597 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7612 16:53:35.805703 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 16:53:35.808564 Total UI for P1: 0, mck2ui 16
7614 16:53:35.811970 best dqsien dly found for B1: ( 1, 9, 22)
7615 16:53:35.815690 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7616 16:53:35.818549 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7617 16:53:35.819014
7618 16:53:35.821588 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7619 16:53:35.825481 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7620 16:53:35.828610 [Gating] SW calibration Done
7621 16:53:35.829123 ==
7622 16:53:35.831735 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 16:53:35.834870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 16:53:35.835342 ==
7625 16:53:35.838345 RX Vref Scan: 0
7626 16:53:35.838839
7627 16:53:35.841424 RX Vref 0 -> 0, step: 1
7628 16:53:35.841917
7629 16:53:35.842379 RX Delay 0 -> 252, step: 8
7630 16:53:35.848215 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7631 16:53:35.851030 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7632 16:53:35.854371 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7633 16:53:35.858104 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7634 16:53:35.861197 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7635 16:53:35.867661 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7636 16:53:35.871448 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7637 16:53:35.874435 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7638 16:53:35.877420 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7639 16:53:35.884030 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7640 16:53:35.887517 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7641 16:53:35.890540 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7642 16:53:35.893816 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7643 16:53:35.897509 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7644 16:53:35.903795 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7645 16:53:35.907443 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7646 16:53:35.907957 ==
7647 16:53:35.910484 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 16:53:35.913764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 16:53:35.914254 ==
7650 16:53:35.916881 DQS Delay:
7651 16:53:35.917347 DQS0 = 0, DQS1 = 0
7652 16:53:35.920090 DQM Delay:
7653 16:53:35.920555 DQM0 = 128, DQM1 = 123
7654 16:53:35.920925 DQ Delay:
7655 16:53:35.923853 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7656 16:53:35.930018 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =143
7657 16:53:35.933190 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7658 16:53:35.936977 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7659 16:53:35.937410
7660 16:53:35.937740
7661 16:53:35.938086 ==
7662 16:53:35.940170 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 16:53:35.943118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 16:53:35.943536 ==
7665 16:53:35.943901
7666 16:53:35.944208
7667 16:53:35.947009 TX Vref Scan disable
7668 16:53:35.950107 == TX Byte 0 ==
7669 16:53:35.953389 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7670 16:53:35.956312 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7671 16:53:35.959926 == TX Byte 1 ==
7672 16:53:35.963019 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7673 16:53:35.966888 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7674 16:53:35.967457 ==
7675 16:53:35.969670 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 16:53:35.976156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 16:53:35.976621 ==
7678 16:53:35.988582
7679 16:53:35.992064 TX Vref early break, caculate TX vref
7680 16:53:35.995630 TX Vref=16, minBit 8, minWin=20, winSum=361
7681 16:53:35.999277 TX Vref=18, minBit 8, minWin=22, winSum=375
7682 16:53:36.002327 TX Vref=20, minBit 8, minWin=23, winSum=385
7683 16:53:36.005673 TX Vref=22, minBit 8, minWin=23, winSum=394
7684 16:53:36.008506 TX Vref=24, minBit 8, minWin=23, winSum=402
7685 16:53:36.015426 TX Vref=26, minBit 8, minWin=24, winSum=408
7686 16:53:36.018431 TX Vref=28, minBit 8, minWin=24, winSum=406
7687 16:53:36.021559 TX Vref=30, minBit 8, minWin=24, winSum=399
7688 16:53:36.025647 TX Vref=32, minBit 8, minWin=22, winSum=393
7689 16:53:36.028475 TX Vref=34, minBit 8, minWin=21, winSum=383
7690 16:53:36.034774 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 26
7691 16:53:36.035195
7692 16:53:36.038561 Final TX Range 0 Vref 26
7693 16:53:36.039062
7694 16:53:36.039407 ==
7695 16:53:36.041607 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 16:53:36.044751 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 16:53:36.045173 ==
7698 16:53:36.045506
7699 16:53:36.045810
7700 16:53:36.048545 TX Vref Scan disable
7701 16:53:36.054964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7702 16:53:36.055490 == TX Byte 0 ==
7703 16:53:36.058082 u2DelayCellOfst[0]=15 cells (4 PI)
7704 16:53:36.061697 u2DelayCellOfst[1]=18 cells (5 PI)
7705 16:53:36.064555 u2DelayCellOfst[2]=11 cells (3 PI)
7706 16:53:36.068066 u2DelayCellOfst[3]=15 cells (4 PI)
7707 16:53:36.071258 u2DelayCellOfst[4]=11 cells (3 PI)
7708 16:53:36.074915 u2DelayCellOfst[5]=0 cells (0 PI)
7709 16:53:36.077816 u2DelayCellOfst[6]=22 cells (6 PI)
7710 16:53:36.081512 u2DelayCellOfst[7]=18 cells (5 PI)
7711 16:53:36.085074 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7712 16:53:36.087752 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7713 16:53:36.091520 == TX Byte 1 ==
7714 16:53:36.094487 u2DelayCellOfst[8]=0 cells (0 PI)
7715 16:53:36.098147 u2DelayCellOfst[9]=3 cells (1 PI)
7716 16:53:36.098579 u2DelayCellOfst[10]=7 cells (2 PI)
7717 16:53:36.101153 u2DelayCellOfst[11]=3 cells (1 PI)
7718 16:53:36.104725 u2DelayCellOfst[12]=11 cells (3 PI)
7719 16:53:36.107892 u2DelayCellOfst[13]=11 cells (3 PI)
7720 16:53:36.110993 u2DelayCellOfst[14]=15 cells (4 PI)
7721 16:53:36.114335 u2DelayCellOfst[15]=11 cells (3 PI)
7722 16:53:36.121407 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7723 16:53:36.124008 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7724 16:53:36.124486 DramC Write-DBI on
7725 16:53:36.127534 ==
7726 16:53:36.128146 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 16:53:36.134140 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 16:53:36.134732 ==
7729 16:53:36.135226
7730 16:53:36.135722
7731 16:53:36.137486 TX Vref Scan disable
7732 16:53:36.137961 == TX Byte 0 ==
7733 16:53:36.143928 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7734 16:53:36.144357 == TX Byte 1 ==
7735 16:53:36.146928 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7736 16:53:36.150259 DramC Write-DBI off
7737 16:53:36.150692
7738 16:53:36.151130 [DATLAT]
7739 16:53:36.153785 Freq=1600, CH0 RK0
7740 16:53:36.154218
7741 16:53:36.154649 DATLAT Default: 0xf
7742 16:53:36.156943 0, 0xFFFF, sum = 0
7743 16:53:36.157384 1, 0xFFFF, sum = 0
7744 16:53:36.160225 2, 0xFFFF, sum = 0
7745 16:53:36.160664 3, 0xFFFF, sum = 0
7746 16:53:36.164033 4, 0xFFFF, sum = 0
7747 16:53:36.164596 5, 0xFFFF, sum = 0
7748 16:53:36.167178 6, 0xFFFF, sum = 0
7749 16:53:36.167646 7, 0xFFFF, sum = 0
7750 16:53:36.170116 8, 0xFFFF, sum = 0
7751 16:53:36.173440 9, 0xFFFF, sum = 0
7752 16:53:36.173884 10, 0xFFFF, sum = 0
7753 16:53:36.177008 11, 0xFFFF, sum = 0
7754 16:53:36.177447 12, 0xFFFF, sum = 0
7755 16:53:36.179998 13, 0xEFFF, sum = 0
7756 16:53:36.180436 14, 0x0, sum = 1
7757 16:53:36.183187 15, 0x0, sum = 2
7758 16:53:36.183659 16, 0x0, sum = 3
7759 16:53:36.186558 17, 0x0, sum = 4
7760 16:53:36.186996 best_step = 15
7761 16:53:36.187427
7762 16:53:36.187884 ==
7763 16:53:36.189719 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 16:53:36.193557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 16:53:36.196629 ==
7766 16:53:36.197052 RX Vref Scan: 1
7767 16:53:36.197391
7768 16:53:36.199774 Set Vref Range= 24 -> 127
7769 16:53:36.200199
7770 16:53:36.203389 RX Vref 24 -> 127, step: 1
7771 16:53:36.203960
7772 16:53:36.204313 RX Delay 11 -> 252, step: 4
7773 16:53:36.204633
7774 16:53:36.206354 Set Vref, RX VrefLevel [Byte0]: 24
7775 16:53:36.210006 [Byte1]: 24
7776 16:53:36.213523
7777 16:53:36.213947 Set Vref, RX VrefLevel [Byte0]: 25
7778 16:53:36.217209 [Byte1]: 25
7779 16:53:36.221536
7780 16:53:36.221956 Set Vref, RX VrefLevel [Byte0]: 26
7781 16:53:36.224705 [Byte1]: 26
7782 16:53:36.229316
7783 16:53:36.229835 Set Vref, RX VrefLevel [Byte0]: 27
7784 16:53:36.232188 [Byte1]: 27
7785 16:53:36.236463
7786 16:53:36.236884 Set Vref, RX VrefLevel [Byte0]: 28
7787 16:53:36.239543 [Byte1]: 28
7788 16:53:36.244528
7789 16:53:36.245092 Set Vref, RX VrefLevel [Byte0]: 29
7790 16:53:36.247957 [Byte1]: 29
7791 16:53:36.251827
7792 16:53:36.252380 Set Vref, RX VrefLevel [Byte0]: 30
7793 16:53:36.255670 [Byte1]: 30
7794 16:53:36.259704
7795 16:53:36.260195 Set Vref, RX VrefLevel [Byte0]: 31
7796 16:53:36.262815 [Byte1]: 31
7797 16:53:36.267622
7798 16:53:36.268201 Set Vref, RX VrefLevel [Byte0]: 32
7799 16:53:36.270453 [Byte1]: 32
7800 16:53:36.274681
7801 16:53:36.275156 Set Vref, RX VrefLevel [Byte0]: 33
7802 16:53:36.278007 [Byte1]: 33
7803 16:53:36.282411
7804 16:53:36.282985 Set Vref, RX VrefLevel [Byte0]: 34
7805 16:53:36.285463 [Byte1]: 34
7806 16:53:36.290022
7807 16:53:36.290597 Set Vref, RX VrefLevel [Byte0]: 35
7808 16:53:36.292843 [Byte1]: 35
7809 16:53:36.297219
7810 16:53:36.297791 Set Vref, RX VrefLevel [Byte0]: 36
7811 16:53:36.300495 [Byte1]: 36
7812 16:53:36.305225
7813 16:53:36.305799 Set Vref, RX VrefLevel [Byte0]: 37
7814 16:53:36.308424 [Byte1]: 37
7815 16:53:36.312639
7816 16:53:36.313202 Set Vref, RX VrefLevel [Byte0]: 38
7817 16:53:36.316167 [Byte1]: 38
7818 16:53:36.320222
7819 16:53:36.320687 Set Vref, RX VrefLevel [Byte0]: 39
7820 16:53:36.323325 [Byte1]: 39
7821 16:53:36.328337
7822 16:53:36.328896 Set Vref, RX VrefLevel [Byte0]: 40
7823 16:53:36.331531 [Byte1]: 40
7824 16:53:36.336131
7825 16:53:36.336695 Set Vref, RX VrefLevel [Byte0]: 41
7826 16:53:36.339101 [Byte1]: 41
7827 16:53:36.343533
7828 16:53:36.344161 Set Vref, RX VrefLevel [Byte0]: 42
7829 16:53:36.346540 [Byte1]: 42
7830 16:53:36.350686
7831 16:53:36.351255 Set Vref, RX VrefLevel [Byte0]: 43
7832 16:53:36.353785 [Byte1]: 43
7833 16:53:36.358247
7834 16:53:36.358807 Set Vref, RX VrefLevel [Byte0]: 44
7835 16:53:36.362223 [Byte1]: 44
7836 16:53:36.366448
7837 16:53:36.367009 Set Vref, RX VrefLevel [Byte0]: 45
7838 16:53:36.369549 [Byte1]: 45
7839 16:53:36.373769
7840 16:53:36.374232 Set Vref, RX VrefLevel [Byte0]: 46
7841 16:53:36.376982 [Byte1]: 46
7842 16:53:36.381169
7843 16:53:36.381727 Set Vref, RX VrefLevel [Byte0]: 47
7844 16:53:36.384758 [Byte1]: 47
7845 16:53:36.389117
7846 16:53:36.389678 Set Vref, RX VrefLevel [Byte0]: 48
7847 16:53:36.391960 [Byte1]: 48
7848 16:53:36.396358
7849 16:53:36.396924 Set Vref, RX VrefLevel [Byte0]: 49
7850 16:53:36.399954 [Byte1]: 49
7851 16:53:36.403765
7852 16:53:36.404225 Set Vref, RX VrefLevel [Byte0]: 50
7853 16:53:36.407344 [Byte1]: 50
7854 16:53:36.411484
7855 16:53:36.412000 Set Vref, RX VrefLevel [Byte0]: 51
7856 16:53:36.415067 [Byte1]: 51
7857 16:53:36.419275
7858 16:53:36.419764 Set Vref, RX VrefLevel [Byte0]: 52
7859 16:53:36.422748 [Byte1]: 52
7860 16:53:36.426594
7861 16:53:36.427056 Set Vref, RX VrefLevel [Byte0]: 53
7862 16:53:36.430288 [Byte1]: 53
7863 16:53:36.434319
7864 16:53:36.434776 Set Vref, RX VrefLevel [Byte0]: 54
7865 16:53:36.437540 [Byte1]: 54
7866 16:53:36.442345
7867 16:53:36.442935 Set Vref, RX VrefLevel [Byte0]: 55
7868 16:53:36.445335 [Byte1]: 55
7869 16:53:36.449615
7870 16:53:36.450072 Set Vref, RX VrefLevel [Byte0]: 56
7871 16:53:36.453338 [Byte1]: 56
7872 16:53:36.457175
7873 16:53:36.457589 Set Vref, RX VrefLevel [Byte0]: 57
7874 16:53:36.460254 [Byte1]: 57
7875 16:53:36.465235
7876 16:53:36.465747 Set Vref, RX VrefLevel [Byte0]: 58
7877 16:53:36.468236 [Byte1]: 58
7878 16:53:36.472576
7879 16:53:36.473059 Set Vref, RX VrefLevel [Byte0]: 59
7880 16:53:36.475736 [Byte1]: 59
7881 16:53:36.480330
7882 16:53:36.480893 Set Vref, RX VrefLevel [Byte0]: 60
7883 16:53:36.483422 [Byte1]: 60
7884 16:53:36.488184
7885 16:53:36.488742 Set Vref, RX VrefLevel [Byte0]: 61
7886 16:53:36.491292 [Byte1]: 61
7887 16:53:36.495361
7888 16:53:36.496033 Set Vref, RX VrefLevel [Byte0]: 62
7889 16:53:36.498917 [Byte1]: 62
7890 16:53:36.503373
7891 16:53:36.504018 Set Vref, RX VrefLevel [Byte0]: 63
7892 16:53:36.506419 [Byte1]: 63
7893 16:53:36.511041
7894 16:53:36.511650 Set Vref, RX VrefLevel [Byte0]: 64
7895 16:53:36.513821 [Byte1]: 64
7896 16:53:36.517907
7897 16:53:36.518385 Set Vref, RX VrefLevel [Byte0]: 65
7898 16:53:36.521264 [Byte1]: 65
7899 16:53:36.525668
7900 16:53:36.526078 Set Vref, RX VrefLevel [Byte0]: 66
7901 16:53:36.528902 [Byte1]: 66
7902 16:53:36.533191
7903 16:53:36.533605 Set Vref, RX VrefLevel [Byte0]: 67
7904 16:53:36.536525 [Byte1]: 67
7905 16:53:36.541217
7906 16:53:36.541632 Set Vref, RX VrefLevel [Byte0]: 68
7907 16:53:36.544278 [Byte1]: 68
7908 16:53:36.548576
7909 16:53:36.549092 Set Vref, RX VrefLevel [Byte0]: 69
7910 16:53:36.551613 [Byte1]: 69
7911 16:53:36.556336
7912 16:53:36.556750 Set Vref, RX VrefLevel [Byte0]: 70
7913 16:53:36.559516 [Byte1]: 70
7914 16:53:36.564403
7915 16:53:36.564920 Set Vref, RX VrefLevel [Byte0]: 71
7916 16:53:36.566945 [Byte1]: 71
7917 16:53:36.571241
7918 16:53:36.571683 Set Vref, RX VrefLevel [Byte0]: 72
7919 16:53:36.574999 [Byte1]: 72
7920 16:53:36.578910
7921 16:53:36.579434 Set Vref, RX VrefLevel [Byte0]: 73
7922 16:53:36.582290 [Byte1]: 73
7923 16:53:36.586549
7924 16:53:36.586964 Set Vref, RX VrefLevel [Byte0]: 74
7925 16:53:36.590531 [Byte1]: 74
7926 16:53:36.594733
7927 16:53:36.595149 Set Vref, RX VrefLevel [Byte0]: 75
7928 16:53:36.597673 [Byte1]: 75
7929 16:53:36.601902
7930 16:53:36.602425 Set Vref, RX VrefLevel [Byte0]: 76
7931 16:53:36.605524 [Byte1]: 76
7932 16:53:36.609811
7933 16:53:36.610366 Final RX Vref Byte 0 = 63 to rank0
7934 16:53:36.612662 Final RX Vref Byte 1 = 59 to rank0
7935 16:53:36.615994 Final RX Vref Byte 0 = 63 to rank1
7936 16:53:36.619307 Final RX Vref Byte 1 = 59 to rank1==
7937 16:53:36.622772 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 16:53:36.629522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 16:53:36.630082 ==
7940 16:53:36.630416 DQS Delay:
7941 16:53:36.632252 DQS0 = 0, DQS1 = 0
7942 16:53:36.632791 DQM Delay:
7943 16:53:36.633246 DQM0 = 126, DQM1 = 120
7944 16:53:36.636121 DQ Delay:
7945 16:53:36.639117 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7946 16:53:36.642398 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7947 16:53:36.645994 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7948 16:53:36.648908 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7949 16:53:36.649377
7950 16:53:36.649779
7951 16:53:36.650131
7952 16:53:36.652547 [DramC_TX_OE_Calibration] TA2
7953 16:53:36.655511 Original DQ_B0 (3 6) =30, OEN = 27
7954 16:53:36.658850 Original DQ_B1 (3 6) =30, OEN = 27
7955 16:53:36.661850 24, 0x0, End_B0=24 End_B1=24
7956 16:53:36.665929 25, 0x0, End_B0=25 End_B1=25
7957 16:53:36.666472 26, 0x0, End_B0=26 End_B1=26
7958 16:53:36.668777 27, 0x0, End_B0=27 End_B1=27
7959 16:53:36.671862 28, 0x0, End_B0=28 End_B1=28
7960 16:53:36.675502 29, 0x0, End_B0=29 End_B1=29
7961 16:53:36.675981 30, 0x0, End_B0=30 End_B1=30
7962 16:53:36.678476 31, 0x4141, End_B0=30 End_B1=30
7963 16:53:36.681971 Byte0 end_step=30 best_step=27
7964 16:53:36.685803 Byte1 end_step=30 best_step=27
7965 16:53:36.689047 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 16:53:36.691952 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 16:53:36.692422
7968 16:53:36.692793
7969 16:53:36.698512 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
7970 16:53:36.701575 CH0 RK0: MR19=303, MR18=1010
7971 16:53:36.708271 CH0_RK0: MR19=0x303, MR18=0x1010, DQSOSC=401, MR23=63, INC=22, DEC=15
7972 16:53:36.708800
7973 16:53:36.711147 ----->DramcWriteLeveling(PI) begin...
7974 16:53:36.711637 ==
7975 16:53:36.714266 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 16:53:36.718107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 16:53:36.721006 ==
7978 16:53:36.721429 Write leveling (Byte 0): 33 => 33
7979 16:53:36.724252 Write leveling (Byte 1): 29 => 29
7980 16:53:36.728183 DramcWriteLeveling(PI) end<-----
7981 16:53:36.728709
7982 16:53:36.729046 ==
7983 16:53:36.730860 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 16:53:36.737433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 16:53:36.737860 ==
7986 16:53:36.741260 [Gating] SW mode calibration
7987 16:53:36.748009 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 16:53:36.751105 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 16:53:36.757675 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 16:53:36.760536 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 16:53:36.764089 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 16:53:36.770436 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7993 16:53:36.773443 1 4 16 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7994 16:53:36.777320 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7995 16:53:36.783468 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 16:53:36.787126 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 16:53:36.789979 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 16:53:36.796394 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 16:53:36.799613 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8000 16:53:36.802760 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
8001 16:53:36.809075 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8002 16:53:36.812262 1 5 20 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8003 16:53:36.815738 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 16:53:36.822605 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 16:53:36.825792 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 16:53:36.828990 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 16:53:36.835497 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8008 16:53:36.839252 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8009 16:53:36.842288 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
8010 16:53:36.848853 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 16:53:36.851966 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 16:53:36.855640 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 16:53:36.861698 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 16:53:36.865297 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 16:53:36.868267 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8016 16:53:36.874966 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 16:53:36.878205 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 16:53:36.882029 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 16:53:36.888031 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 16:53:36.891570 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 16:53:36.894827 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 16:53:36.901651 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 16:53:36.904766 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 16:53:36.908040 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 16:53:36.914314 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 16:53:36.917788 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 16:53:36.921076 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 16:53:36.928023 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 16:53:36.931034 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 16:53:36.934039 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 16:53:36.941050 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8032 16:53:36.944261 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 16:53:36.947385 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 16:53:36.950391 Total UI for P1: 0, mck2ui 16
8035 16:53:36.953817 best dqsien dly found for B0: ( 1, 9, 10)
8036 16:53:36.960622 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 16:53:36.963783 Total UI for P1: 0, mck2ui 16
8038 16:53:36.967484 best dqsien dly found for B1: ( 1, 9, 16)
8039 16:53:36.970483 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8040 16:53:36.974296 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8041 16:53:36.974371
8042 16:53:36.977248 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8043 16:53:36.980385 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8044 16:53:36.984274 [Gating] SW calibration Done
8045 16:53:36.984416 ==
8046 16:53:36.987310 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 16:53:36.990572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 16:53:36.990759 ==
8049 16:53:36.994133 RX Vref Scan: 0
8050 16:53:36.994327
8051 16:53:36.997019 RX Vref 0 -> 0, step: 1
8052 16:53:36.997164
8053 16:53:36.997254 RX Delay 0 -> 252, step: 8
8054 16:53:37.003486 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8055 16:53:37.007333 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8056 16:53:37.010799 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8057 16:53:37.013909 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8058 16:53:37.016861 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8059 16:53:37.023816 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8060 16:53:37.027245 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8061 16:53:37.030463 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8062 16:53:37.033479 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8063 16:53:37.036737 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8064 16:53:37.043798 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8065 16:53:37.047233 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8066 16:53:37.049772 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8067 16:53:37.053962 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8068 16:53:37.059916 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8069 16:53:37.063150 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8070 16:53:37.063607 ==
8071 16:53:37.066787 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 16:53:37.069651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 16:53:37.070195 ==
8074 16:53:37.073056 DQS Delay:
8075 16:53:37.073482 DQS0 = 0, DQS1 = 0
8076 16:53:37.073821 DQM Delay:
8077 16:53:37.076252 DQM0 = 128, DQM1 = 121
8078 16:53:37.076708 DQ Delay:
8079 16:53:37.079869 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8080 16:53:37.083263 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8081 16:53:37.090094 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8082 16:53:37.092845 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8083 16:53:37.093270
8084 16:53:37.093607
8085 16:53:37.093918 ==
8086 16:53:37.095877 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 16:53:37.099524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 16:53:37.100005 ==
8089 16:53:37.100340
8090 16:53:37.100650
8091 16:53:37.102661 TX Vref Scan disable
8092 16:53:37.105789 == TX Byte 0 ==
8093 16:53:37.109590 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8094 16:53:37.112739 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8095 16:53:37.115940 == TX Byte 1 ==
8096 16:53:37.119029 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8097 16:53:37.122354 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8098 16:53:37.122774 ==
8099 16:53:37.125766 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 16:53:37.129279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 16:53:37.132491 ==
8102 16:53:37.144136
8103 16:53:37.147198 TX Vref early break, caculate TX vref
8104 16:53:37.150615 TX Vref=16, minBit 9, minWin=21, winSum=367
8105 16:53:37.153821 TX Vref=18, minBit 1, minWin=22, winSum=377
8106 16:53:37.157047 TX Vref=20, minBit 0, minWin=23, winSum=387
8107 16:53:37.160741 TX Vref=22, minBit 8, minWin=23, winSum=393
8108 16:53:37.163267 TX Vref=24, minBit 0, minWin=24, winSum=403
8109 16:53:37.169737 TX Vref=26, minBit 0, minWin=25, winSum=406
8110 16:53:37.173037 TX Vref=28, minBit 1, minWin=25, winSum=412
8111 16:53:37.176483 TX Vref=30, minBit 8, minWin=24, winSum=407
8112 16:53:37.180088 TX Vref=32, minBit 1, minWin=24, winSum=399
8113 16:53:37.183267 TX Vref=34, minBit 8, minWin=23, winSum=390
8114 16:53:37.189628 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 28
8115 16:53:37.190192
8116 16:53:37.192951 Final TX Range 0 Vref 28
8117 16:53:37.193392
8118 16:53:37.193731 ==
8119 16:53:37.196323 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 16:53:37.199306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 16:53:37.199768 ==
8122 16:53:37.200137
8123 16:53:37.202911
8124 16:53:37.203325 TX Vref Scan disable
8125 16:53:37.209170 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8126 16:53:37.209591 == TX Byte 0 ==
8127 16:53:37.212686 u2DelayCellOfst[0]=15 cells (4 PI)
8128 16:53:37.215734 u2DelayCellOfst[1]=18 cells (5 PI)
8129 16:53:37.218978 u2DelayCellOfst[2]=11 cells (3 PI)
8130 16:53:37.222966 u2DelayCellOfst[3]=11 cells (3 PI)
8131 16:53:37.225880 u2DelayCellOfst[4]=7 cells (2 PI)
8132 16:53:37.228979 u2DelayCellOfst[5]=0 cells (0 PI)
8133 16:53:37.232704 u2DelayCellOfst[6]=18 cells (5 PI)
8134 16:53:37.235741 u2DelayCellOfst[7]=18 cells (5 PI)
8135 16:53:37.238854 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8136 16:53:37.241981 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8137 16:53:37.245727 == TX Byte 1 ==
8138 16:53:37.248824 u2DelayCellOfst[8]=0 cells (0 PI)
8139 16:53:37.252037 u2DelayCellOfst[9]=0 cells (0 PI)
8140 16:53:37.255281 u2DelayCellOfst[10]=3 cells (1 PI)
8141 16:53:37.258897 u2DelayCellOfst[11]=3 cells (1 PI)
8142 16:53:37.262022 u2DelayCellOfst[12]=11 cells (3 PI)
8143 16:53:37.265133 u2DelayCellOfst[13]=11 cells (3 PI)
8144 16:53:37.268696 u2DelayCellOfst[14]=11 cells (3 PI)
8145 16:53:37.269121 u2DelayCellOfst[15]=11 cells (3 PI)
8146 16:53:37.275611 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8147 16:53:37.278275 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8148 16:53:37.282039 DramC Write-DBI on
8149 16:53:37.282563 ==
8150 16:53:37.285364 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 16:53:37.288044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 16:53:37.288465 ==
8153 16:53:37.288798
8154 16:53:37.289108
8155 16:53:37.292104 TX Vref Scan disable
8156 16:53:37.292523 == TX Byte 0 ==
8157 16:53:37.298286 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8158 16:53:37.298815 == TX Byte 1 ==
8159 16:53:37.304630 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8160 16:53:37.305147 DramC Write-DBI off
8161 16:53:37.305480
8162 16:53:37.305791 [DATLAT]
8163 16:53:37.308042 Freq=1600, CH0 RK1
8164 16:53:37.308465
8165 16:53:37.311248 DATLAT Default: 0xf
8166 16:53:37.311770 0, 0xFFFF, sum = 0
8167 16:53:37.314820 1, 0xFFFF, sum = 0
8168 16:53:37.315357 2, 0xFFFF, sum = 0
8169 16:53:37.318299 3, 0xFFFF, sum = 0
8170 16:53:37.318832 4, 0xFFFF, sum = 0
8171 16:53:37.321260 5, 0xFFFF, sum = 0
8172 16:53:37.321708 6, 0xFFFF, sum = 0
8173 16:53:37.324574 7, 0xFFFF, sum = 0
8174 16:53:37.325104 8, 0xFFFF, sum = 0
8175 16:53:37.327739 9, 0xFFFF, sum = 0
8176 16:53:37.328263 10, 0xFFFF, sum = 0
8177 16:53:37.331098 11, 0xFFFF, sum = 0
8178 16:53:37.331521 12, 0xFFFF, sum = 0
8179 16:53:37.334966 13, 0xCFFF, sum = 0
8180 16:53:37.335501 14, 0x0, sum = 1
8181 16:53:37.337670 15, 0x0, sum = 2
8182 16:53:37.338109 16, 0x0, sum = 3
8183 16:53:37.340729 17, 0x0, sum = 4
8184 16:53:37.341157 best_step = 15
8185 16:53:37.341490
8186 16:53:37.341798 ==
8187 16:53:37.344360 Dram Type= 6, Freq= 0, CH_0, rank 1
8188 16:53:37.351463 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8189 16:53:37.352051 ==
8190 16:53:37.352390 RX Vref Scan: 0
8191 16:53:37.352702
8192 16:53:37.353794 RX Vref 0 -> 0, step: 1
8193 16:53:37.354212
8194 16:53:37.357424 RX Delay 3 -> 252, step: 4
8195 16:53:37.360762 iDelay=191, Bit 0, Center 122 (67 ~ 178) 112
8196 16:53:37.364222 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8197 16:53:37.370373 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8198 16:53:37.373887 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8199 16:53:37.376976 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8200 16:53:37.381112 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8201 16:53:37.383527 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8202 16:53:37.390647 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8203 16:53:37.394052 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8204 16:53:37.396630 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8205 16:53:37.400250 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8206 16:53:37.403461 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8207 16:53:37.410227 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8208 16:53:37.413215 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8209 16:53:37.416974 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8210 16:53:37.419788 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8211 16:53:37.420206 ==
8212 16:53:37.423214 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 16:53:37.430305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 16:53:37.430864 ==
8215 16:53:37.431237 DQS Delay:
8216 16:53:37.433397 DQS0 = 0, DQS1 = 0
8217 16:53:37.433819 DQM Delay:
8218 16:53:37.436634 DQM0 = 124, DQM1 = 117
8219 16:53:37.437053 DQ Delay:
8220 16:53:37.440009 DQ0 =122, DQ1 =126, DQ2 =122, DQ3 =122
8221 16:53:37.443298 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8222 16:53:37.446563 DQ8 =108, DQ9 =104, DQ10 =120, DQ11 =112
8223 16:53:37.449694 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8224 16:53:37.450226
8225 16:53:37.450562
8226 16:53:37.450872
8227 16:53:37.453220 [DramC_TX_OE_Calibration] TA2
8228 16:53:37.456292 Original DQ_B0 (3 6) =30, OEN = 27
8229 16:53:37.459365 Original DQ_B1 (3 6) =30, OEN = 27
8230 16:53:37.462636 24, 0x0, End_B0=24 End_B1=24
8231 16:53:37.466289 25, 0x0, End_B0=25 End_B1=25
8232 16:53:37.466714 26, 0x0, End_B0=26 End_B1=26
8233 16:53:37.469675 27, 0x0, End_B0=27 End_B1=27
8234 16:53:37.472540 28, 0x0, End_B0=28 End_B1=28
8235 16:53:37.476613 29, 0x0, End_B0=29 End_B1=29
8236 16:53:37.477150 30, 0x0, End_B0=30 End_B1=30
8237 16:53:37.479210 31, 0x4141, End_B0=30 End_B1=30
8238 16:53:37.482901 Byte0 end_step=30 best_step=27
8239 16:53:37.486105 Byte1 end_step=30 best_step=27
8240 16:53:37.489043 Byte0 TX OE(2T, 0.5T) = (3, 3)
8241 16:53:37.493154 Byte1 TX OE(2T, 0.5T) = (3, 3)
8242 16:53:37.493680
8243 16:53:37.494018
8244 16:53:37.498905 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8245 16:53:37.502925 CH0 RK1: MR19=303, MR18=210F
8246 16:53:37.509019 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8247 16:53:37.512537 [RxdqsGatingPostProcess] freq 1600
8248 16:53:37.518935 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8249 16:53:37.519360 best DQS0 dly(2T, 0.5T) = (1, 1)
8250 16:53:37.522097 best DQS1 dly(2T, 0.5T) = (1, 1)
8251 16:53:37.525552 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8252 16:53:37.529015 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8253 16:53:37.532536 best DQS0 dly(2T, 0.5T) = (1, 1)
8254 16:53:37.535765 best DQS1 dly(2T, 0.5T) = (1, 1)
8255 16:53:37.538914 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8256 16:53:37.542161 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8257 16:53:37.545266 Pre-setting of DQS Precalculation
8258 16:53:37.548976 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8259 16:53:37.549396 ==
8260 16:53:37.551729 Dram Type= 6, Freq= 0, CH_1, rank 0
8261 16:53:37.558803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 16:53:37.559343 ==
8263 16:53:37.562001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8264 16:53:37.568993 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8265 16:53:37.572007 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8266 16:53:37.578614 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8267 16:53:37.586218 [CA 0] Center 42 (13~72) winsize 60
8268 16:53:37.589542 [CA 1] Center 42 (13~72) winsize 60
8269 16:53:37.593308 [CA 2] Center 38 (9~67) winsize 59
8270 16:53:37.596306 [CA 3] Center 37 (8~66) winsize 59
8271 16:53:37.599419 [CA 4] Center 37 (8~67) winsize 60
8272 16:53:37.602954 [CA 5] Center 37 (8~66) winsize 59
8273 16:53:37.603492
8274 16:53:37.605874 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8275 16:53:37.606296
8276 16:53:37.612334 [CATrainingPosCal] consider 1 rank data
8277 16:53:37.612760 u2DelayCellTimex100 = 258/100 ps
8278 16:53:37.619320 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8279 16:53:37.622233 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8280 16:53:37.625927 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8281 16:53:37.629429 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8282 16:53:37.632574 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8283 16:53:37.635605 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8284 16:53:37.636035
8285 16:53:37.639110 CA PerBit enable=1, Macro0, CA PI delay=37
8286 16:53:37.639565
8287 16:53:37.641971 [CBTSetCACLKResult] CA Dly = 37
8288 16:53:37.645518 CS Dly: 9 (0~40)
8289 16:53:37.648693 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8290 16:53:37.651846 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8291 16:53:37.652397 ==
8292 16:53:37.655071 Dram Type= 6, Freq= 0, CH_1, rank 1
8293 16:53:37.661790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8294 16:53:37.662198 ==
8295 16:53:37.664892 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8296 16:53:37.671847 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8297 16:53:37.674992 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8298 16:53:37.681652 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8299 16:53:37.689409 [CA 0] Center 41 (12~71) winsize 60
8300 16:53:37.692859 [CA 1] Center 42 (12~72) winsize 61
8301 16:53:37.696070 [CA 2] Center 37 (8~67) winsize 60
8302 16:53:37.699360 [CA 3] Center 36 (7~66) winsize 60
8303 16:53:37.702455 [CA 4] Center 37 (7~67) winsize 61
8304 16:53:37.705532 [CA 5] Center 36 (6~66) winsize 61
8305 16:53:37.705935
8306 16:53:37.709341 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8307 16:53:37.709746
8308 16:53:37.715348 [CATrainingPosCal] consider 2 rank data
8309 16:53:37.715791 u2DelayCellTimex100 = 258/100 ps
8310 16:53:37.721981 CA0 delay=42 (13~71),Diff = 5 PI (18 cell)
8311 16:53:37.725811 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8312 16:53:37.729504 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8313 16:53:37.732307 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8314 16:53:37.735439 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8315 16:53:37.738698 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8316 16:53:37.739102
8317 16:53:37.741913 CA PerBit enable=1, Macro0, CA PI delay=37
8318 16:53:37.742341
8319 16:53:37.745786 [CBTSetCACLKResult] CA Dly = 37
8320 16:53:37.748962 CS Dly: 10 (0~43)
8321 16:53:37.752099 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8322 16:53:37.755096 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8323 16:53:37.755500
8324 16:53:37.758310 ----->DramcWriteLeveling(PI) begin...
8325 16:53:37.758722 ==
8326 16:53:37.765124 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 16:53:37.768141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 16:53:37.768552 ==
8329 16:53:37.771376 Write leveling (Byte 0): 25 => 25
8330 16:53:37.774425 Write leveling (Byte 1): 28 => 28
8331 16:53:37.777720 DramcWriteLeveling(PI) end<-----
8332 16:53:37.778131
8333 16:53:37.778447 ==
8334 16:53:37.781574 Dram Type= 6, Freq= 0, CH_1, rank 0
8335 16:53:37.784595 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 16:53:37.785112 ==
8337 16:53:37.787921 [Gating] SW mode calibration
8338 16:53:37.794338 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8339 16:53:37.801652 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8340 16:53:37.804116 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 16:53:37.807470 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 16:53:37.814304 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 16:53:37.817195 1 4 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8344 16:53:37.820752 1 4 16 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
8345 16:53:37.826947 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8346 16:53:37.830391 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 16:53:37.833411 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 16:53:37.840359 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 16:53:37.843623 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 16:53:37.846616 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 16:53:37.853371 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8352 16:53:37.856389 1 5 16 | B1->B0 | 2525 2525 | 0 0 | (0 1) (0 1)
8353 16:53:37.859814 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8354 16:53:37.866737 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 16:53:37.869738 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 16:53:37.873543 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 16:53:37.879618 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 16:53:37.882839 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 16:53:37.886673 1 6 12 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
8360 16:53:37.892884 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8361 16:53:37.896604 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8362 16:53:37.899756 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 16:53:37.906376 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 16:53:37.909904 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 16:53:37.912816 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 16:53:37.919265 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 16:53:37.922591 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8368 16:53:37.926052 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8369 16:53:37.933190 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8370 16:53:37.936170 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 16:53:37.939257 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 16:53:37.946057 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 16:53:37.949140 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 16:53:37.952351 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 16:53:37.958676 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 16:53:37.962058 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 16:53:37.965363 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 16:53:37.972126 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 16:53:37.975366 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 16:53:37.978318 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 16:53:37.985304 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 16:53:37.988311 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 16:53:37.991473 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 16:53:37.997999 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8385 16:53:38.001281 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 16:53:38.005332 Total UI for P1: 0, mck2ui 16
8387 16:53:38.008328 best dqsien dly found for B0: ( 1, 9, 16)
8388 16:53:38.011529 Total UI for P1: 0, mck2ui 16
8389 16:53:38.014896 best dqsien dly found for B1: ( 1, 9, 16)
8390 16:53:38.017864 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8391 16:53:38.021447 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8392 16:53:38.021883
8393 16:53:38.024484 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8394 16:53:38.030858 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8395 16:53:38.031278 [Gating] SW calibration Done
8396 16:53:38.034654 ==
8397 16:53:38.035191 Dram Type= 6, Freq= 0, CH_1, rank 0
8398 16:53:38.041327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8399 16:53:38.041854 ==
8400 16:53:38.042186 RX Vref Scan: 0
8401 16:53:38.042513
8402 16:53:38.044317 RX Vref 0 -> 0, step: 1
8403 16:53:38.044733
8404 16:53:38.047492 RX Delay 0 -> 252, step: 8
8405 16:53:38.051056 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8406 16:53:38.054059 iDelay=200, Bit 1, Center 127 (64 ~ 191) 128
8407 16:53:38.057663 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8408 16:53:38.063663 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8409 16:53:38.067651 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8410 16:53:38.070704 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8411 16:53:38.074069 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8412 16:53:38.077323 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8413 16:53:38.083956 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8414 16:53:38.087397 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8415 16:53:38.090717 iDelay=200, Bit 10, Center 127 (80 ~ 175) 96
8416 16:53:38.093394 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8417 16:53:38.100251 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8418 16:53:38.103403 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8419 16:53:38.106631 iDelay=200, Bit 14, Center 131 (80 ~ 183) 104
8420 16:53:38.110366 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8421 16:53:38.110781 ==
8422 16:53:38.113617 Dram Type= 6, Freq= 0, CH_1, rank 0
8423 16:53:38.119770 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 16:53:38.120188 ==
8425 16:53:38.120519 DQS Delay:
8426 16:53:38.120824 DQS0 = 0, DQS1 = 0
8427 16:53:38.123644 DQM Delay:
8428 16:53:38.124065 DQM0 = 131, DQM1 = 126
8429 16:53:38.126850 DQ Delay:
8430 16:53:38.129861 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8431 16:53:38.133477 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8432 16:53:38.136635 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =119
8433 16:53:38.140018 DQ12 =135, DQ13 =135, DQ14 =131, DQ15 =135
8434 16:53:38.140438
8435 16:53:38.140766
8436 16:53:38.141073 ==
8437 16:53:38.142962 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 16:53:38.146489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 16:53:38.149818 ==
8440 16:53:38.150341
8441 16:53:38.150676
8442 16:53:38.150983 TX Vref Scan disable
8443 16:53:38.152937 == TX Byte 0 ==
8444 16:53:38.156443 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8445 16:53:38.159558 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8446 16:53:38.163321 == TX Byte 1 ==
8447 16:53:38.166029 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8448 16:53:38.169600 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8449 16:53:38.172682 ==
8450 16:53:38.175818 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 16:53:38.179341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 16:53:38.179793 ==
8453 16:53:38.192854
8454 16:53:38.195648 TX Vref early break, caculate TX vref
8455 16:53:38.199021 TX Vref=16, minBit 9, minWin=21, winSum=359
8456 16:53:38.202941 TX Vref=18, minBit 11, minWin=21, winSum=371
8457 16:53:38.205919 TX Vref=20, minBit 13, minWin=22, winSum=381
8458 16:53:38.209365 TX Vref=22, minBit 11, minWin=23, winSum=389
8459 16:53:38.215558 TX Vref=24, minBit 0, minWin=24, winSum=397
8460 16:53:38.219351 TX Vref=26, minBit 0, minWin=25, winSum=414
8461 16:53:38.222519 TX Vref=28, minBit 0, minWin=25, winSum=413
8462 16:53:38.225958 TX Vref=30, minBit 0, minWin=25, winSum=412
8463 16:53:38.228793 TX Vref=32, minBit 0, minWin=24, winSum=400
8464 16:53:38.232159 TX Vref=34, minBit 1, minWin=23, winSum=393
8465 16:53:38.238711 TX Vref=36, minBit 0, minWin=22, winSum=380
8466 16:53:38.242354 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8467 16:53:38.242891
8468 16:53:38.245459 Final TX Range 0 Vref 26
8469 16:53:38.245984
8470 16:53:38.246317 ==
8471 16:53:38.248776 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 16:53:38.251909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 16:53:38.255350 ==
8474 16:53:38.255815
8475 16:53:38.256154
8476 16:53:38.256464 TX Vref Scan disable
8477 16:53:38.262180 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8478 16:53:38.262697 == TX Byte 0 ==
8479 16:53:38.265419 u2DelayCellOfst[0]=18 cells (5 PI)
8480 16:53:38.268664 u2DelayCellOfst[1]=18 cells (5 PI)
8481 16:53:38.272295 u2DelayCellOfst[2]=0 cells (0 PI)
8482 16:53:38.275190 u2DelayCellOfst[3]=7 cells (2 PI)
8483 16:53:38.278709 u2DelayCellOfst[4]=11 cells (3 PI)
8484 16:53:38.281845 u2DelayCellOfst[5]=22 cells (6 PI)
8485 16:53:38.284855 u2DelayCellOfst[6]=22 cells (6 PI)
8486 16:53:38.288620 u2DelayCellOfst[7]=7 cells (2 PI)
8487 16:53:38.291913 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8488 16:53:38.295189 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8489 16:53:38.298547 == TX Byte 1 ==
8490 16:53:38.301779 u2DelayCellOfst[8]=0 cells (0 PI)
8491 16:53:38.304805 u2DelayCellOfst[9]=3 cells (1 PI)
8492 16:53:38.308032 u2DelayCellOfst[10]=11 cells (3 PI)
8493 16:53:38.311257 u2DelayCellOfst[11]=7 cells (2 PI)
8494 16:53:38.314425 u2DelayCellOfst[12]=15 cells (4 PI)
8495 16:53:38.317729 u2DelayCellOfst[13]=18 cells (5 PI)
8496 16:53:38.321400 u2DelayCellOfst[14]=18 cells (5 PI)
8497 16:53:38.324742 u2DelayCellOfst[15]=18 cells (5 PI)
8498 16:53:38.327753 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8499 16:53:38.330730 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8500 16:53:38.334719 DramC Write-DBI on
8501 16:53:38.335143 ==
8502 16:53:38.337829 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 16:53:38.341025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 16:53:38.341454 ==
8505 16:53:38.341791
8506 16:53:38.342098
8507 16:53:38.344046 TX Vref Scan disable
8508 16:53:38.344471 == TX Byte 0 ==
8509 16:53:38.350766 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8510 16:53:38.351191 == TX Byte 1 ==
8511 16:53:38.357490 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8512 16:53:38.357915 DramC Write-DBI off
8513 16:53:38.358251
8514 16:53:38.358563 [DATLAT]
8515 16:53:38.360512 Freq=1600, CH1 RK0
8516 16:53:38.360937
8517 16:53:38.363801 DATLAT Default: 0xf
8518 16:53:38.364242 0, 0xFFFF, sum = 0
8519 16:53:38.367229 1, 0xFFFF, sum = 0
8520 16:53:38.367709 2, 0xFFFF, sum = 0
8521 16:53:38.370809 3, 0xFFFF, sum = 0
8522 16:53:38.371245 4, 0xFFFF, sum = 0
8523 16:53:38.373860 5, 0xFFFF, sum = 0
8524 16:53:38.374315 6, 0xFFFF, sum = 0
8525 16:53:38.377053 7, 0xFFFF, sum = 0
8526 16:53:38.377489 8, 0xFFFF, sum = 0
8527 16:53:38.380454 9, 0xFFFF, sum = 0
8528 16:53:38.380892 10, 0xFFFF, sum = 0
8529 16:53:38.383651 11, 0xFFFF, sum = 0
8530 16:53:38.384122 12, 0xFFFF, sum = 0
8531 16:53:38.387265 13, 0x8FFF, sum = 0
8532 16:53:38.387935 14, 0x0, sum = 1
8533 16:53:38.390404 15, 0x0, sum = 2
8534 16:53:38.390829 16, 0x0, sum = 3
8535 16:53:38.393677 17, 0x0, sum = 4
8536 16:53:38.394106 best_step = 15
8537 16:53:38.394454
8538 16:53:38.394771 ==
8539 16:53:38.396791 Dram Type= 6, Freq= 0, CH_1, rank 0
8540 16:53:38.403289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8541 16:53:38.403767 ==
8542 16:53:38.404113 RX Vref Scan: 1
8543 16:53:38.404426
8544 16:53:38.406482 Set Vref Range= 24 -> 127
8545 16:53:38.406932
8546 16:53:38.409998 RX Vref 24 -> 127, step: 1
8547 16:53:38.410459
8548 16:53:38.413152 RX Delay 11 -> 252, step: 4
8549 16:53:38.413690
8550 16:53:38.416750 Set Vref, RX VrefLevel [Byte0]: 24
8551 16:53:38.419700 [Byte1]: 24
8552 16:53:38.420123
8553 16:53:38.422935 Set Vref, RX VrefLevel [Byte0]: 25
8554 16:53:38.426199 [Byte1]: 25
8555 16:53:38.426658
8556 16:53:38.430082 Set Vref, RX VrefLevel [Byte0]: 26
8557 16:53:38.433149 [Byte1]: 26
8558 16:53:38.436270
8559 16:53:38.436911 Set Vref, RX VrefLevel [Byte0]: 27
8560 16:53:38.439964 [Byte1]: 27
8561 16:53:38.443804
8562 16:53:38.444219 Set Vref, RX VrefLevel [Byte0]: 28
8563 16:53:38.447422 [Byte1]: 28
8564 16:53:38.451674
8565 16:53:38.452071 Set Vref, RX VrefLevel [Byte0]: 29
8566 16:53:38.457963 [Byte1]: 29
8567 16:53:38.458490
8568 16:53:38.461410 Set Vref, RX VrefLevel [Byte0]: 30
8569 16:53:38.464488 [Byte1]: 30
8570 16:53:38.464921
8571 16:53:38.467693 Set Vref, RX VrefLevel [Byte0]: 31
8572 16:53:38.471104 [Byte1]: 31
8573 16:53:38.474118
8574 16:53:38.474531 Set Vref, RX VrefLevel [Byte0]: 32
8575 16:53:38.477748 [Byte1]: 32
8576 16:53:38.481761
8577 16:53:38.482174 Set Vref, RX VrefLevel [Byte0]: 33
8578 16:53:38.485376 [Byte1]: 33
8579 16:53:38.489959
8580 16:53:38.490391 Set Vref, RX VrefLevel [Byte0]: 34
8581 16:53:38.492995 [Byte1]: 34
8582 16:53:38.497482
8583 16:53:38.497902 Set Vref, RX VrefLevel [Byte0]: 35
8584 16:53:38.500624 [Byte1]: 35
8585 16:53:38.504630
8586 16:53:38.505052 Set Vref, RX VrefLevel [Byte0]: 36
8587 16:53:38.508474 [Byte1]: 36
8588 16:53:38.512816
8589 16:53:38.513238 Set Vref, RX VrefLevel [Byte0]: 37
8590 16:53:38.515780 [Byte1]: 37
8591 16:53:38.519554
8592 16:53:38.519643 Set Vref, RX VrefLevel [Byte0]: 38
8593 16:53:38.522782 [Byte1]: 38
8594 16:53:38.527547
8595 16:53:38.527665 Set Vref, RX VrefLevel [Byte0]: 39
8596 16:53:38.530866 [Byte1]: 39
8597 16:53:38.535470
8598 16:53:38.535654 Set Vref, RX VrefLevel [Byte0]: 40
8599 16:53:38.538517 [Byte1]: 40
8600 16:53:38.542752
8601 16:53:38.542906 Set Vref, RX VrefLevel [Byte0]: 41
8602 16:53:38.546122 [Byte1]: 41
8603 16:53:38.550719
8604 16:53:38.550911 Set Vref, RX VrefLevel [Byte0]: 42
8605 16:53:38.553569 [Byte1]: 42
8606 16:53:38.557796
8607 16:53:38.558019 Set Vref, RX VrefLevel [Byte0]: 43
8608 16:53:38.561247 [Byte1]: 43
8609 16:53:38.565601
8610 16:53:38.565804 Set Vref, RX VrefLevel [Byte0]: 44
8611 16:53:38.569012 [Byte1]: 44
8612 16:53:38.573101
8613 16:53:38.573317 Set Vref, RX VrefLevel [Byte0]: 45
8614 16:53:38.576257 [Byte1]: 45
8615 16:53:38.580504
8616 16:53:38.580586 Set Vref, RX VrefLevel [Byte0]: 46
8617 16:53:38.584028 [Byte1]: 46
8618 16:53:38.588018
8619 16:53:38.588101 Set Vref, RX VrefLevel [Byte0]: 47
8620 16:53:38.591756 [Byte1]: 47
8621 16:53:38.596289
8622 16:53:38.596810 Set Vref, RX VrefLevel [Byte0]: 48
8623 16:53:38.599554 [Byte1]: 48
8624 16:53:38.604145
8625 16:53:38.604566 Set Vref, RX VrefLevel [Byte0]: 49
8626 16:53:38.606964 [Byte1]: 49
8627 16:53:38.611509
8628 16:53:38.611973 Set Vref, RX VrefLevel [Byte0]: 50
8629 16:53:38.615124 [Byte1]: 50
8630 16:53:38.618745
8631 16:53:38.619188 Set Vref, RX VrefLevel [Byte0]: 51
8632 16:53:38.622475 [Byte1]: 51
8633 16:53:38.626906
8634 16:53:38.627437 Set Vref, RX VrefLevel [Byte0]: 52
8635 16:53:38.630283 [Byte1]: 52
8636 16:53:38.634560
8637 16:53:38.634979 Set Vref, RX VrefLevel [Byte0]: 53
8638 16:53:38.637848 [Byte1]: 53
8639 16:53:38.642154
8640 16:53:38.642729 Set Vref, RX VrefLevel [Byte0]: 54
8641 16:53:38.645365 [Byte1]: 54
8642 16:53:38.650018
8643 16:53:38.650432 Set Vref, RX VrefLevel [Byte0]: 55
8644 16:53:38.652951 [Byte1]: 55
8645 16:53:38.657502
8646 16:53:38.658051 Set Vref, RX VrefLevel [Byte0]: 56
8647 16:53:38.660487 [Byte1]: 56
8648 16:53:38.664862
8649 16:53:38.665299 Set Vref, RX VrefLevel [Byte0]: 57
8650 16:53:38.668085 [Byte1]: 57
8651 16:53:38.672247
8652 16:53:38.672664 Set Vref, RX VrefLevel [Byte0]: 58
8653 16:53:38.675370 [Byte1]: 58
8654 16:53:38.680272
8655 16:53:38.680730 Set Vref, RX VrefLevel [Byte0]: 59
8656 16:53:38.683487 [Byte1]: 59
8657 16:53:38.688090
8658 16:53:38.688528 Set Vref, RX VrefLevel [Byte0]: 60
8659 16:53:38.691094 [Byte1]: 60
8660 16:53:38.695217
8661 16:53:38.695789 Set Vref, RX VrefLevel [Byte0]: 61
8662 16:53:38.698682 [Byte1]: 61
8663 16:53:38.702776
8664 16:53:38.703202 Set Vref, RX VrefLevel [Byte0]: 62
8665 16:53:38.706456 [Byte1]: 62
8666 16:53:38.710312
8667 16:53:38.710741 Set Vref, RX VrefLevel [Byte0]: 63
8668 16:53:38.713986 [Byte1]: 63
8669 16:53:38.718097
8670 16:53:38.718524 Set Vref, RX VrefLevel [Byte0]: 64
8671 16:53:38.721516 [Byte1]: 64
8672 16:53:38.725775
8673 16:53:38.726202 Set Vref, RX VrefLevel [Byte0]: 65
8674 16:53:38.728902 [Byte1]: 65
8675 16:53:38.733825
8676 16:53:38.734251 Set Vref, RX VrefLevel [Byte0]: 66
8677 16:53:38.736417 [Byte1]: 66
8678 16:53:38.741025
8679 16:53:38.741442 Set Vref, RX VrefLevel [Byte0]: 67
8680 16:53:38.744211 [Byte1]: 67
8681 16:53:38.748709
8682 16:53:38.749215 Set Vref, RX VrefLevel [Byte0]: 68
8683 16:53:38.751926 [Byte1]: 68
8684 16:53:38.756357
8685 16:53:38.756771 Set Vref, RX VrefLevel [Byte0]: 69
8686 16:53:38.759604 [Byte1]: 69
8687 16:53:38.764177
8688 16:53:38.764707 Set Vref, RX VrefLevel [Byte0]: 70
8689 16:53:38.767255 [Byte1]: 70
8690 16:53:38.771422
8691 16:53:38.771880 Set Vref, RX VrefLevel [Byte0]: 71
8692 16:53:38.774722 [Byte1]: 71
8693 16:53:38.779143
8694 16:53:38.779557 Set Vref, RX VrefLevel [Byte0]: 72
8695 16:53:38.782156 [Byte1]: 72
8696 16:53:38.787014
8697 16:53:38.787434 Final RX Vref Byte 0 = 57 to rank0
8698 16:53:38.790525 Final RX Vref Byte 1 = 54 to rank0
8699 16:53:38.793842 Final RX Vref Byte 0 = 57 to rank1
8700 16:53:38.796686 Final RX Vref Byte 1 = 54 to rank1==
8701 16:53:38.799506 Dram Type= 6, Freq= 0, CH_1, rank 0
8702 16:53:38.805902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8703 16:53:38.806325 ==
8704 16:53:38.806657 DQS Delay:
8705 16:53:38.809374 DQS0 = 0, DQS1 = 0
8706 16:53:38.809791 DQM Delay:
8707 16:53:38.810122 DQM0 = 131, DQM1 = 123
8708 16:53:38.812957 DQ Delay:
8709 16:53:38.815921 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8710 16:53:38.819538 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =128
8711 16:53:38.822613 DQ8 =110, DQ9 =112, DQ10 =122, DQ11 =116
8712 16:53:38.825950 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8713 16:53:38.826578
8714 16:53:38.827143
8715 16:53:38.827668
8716 16:53:38.829136 [DramC_TX_OE_Calibration] TA2
8717 16:53:38.832324 Original DQ_B0 (3 6) =30, OEN = 27
8718 16:53:38.835350 Original DQ_B1 (3 6) =30, OEN = 27
8719 16:53:38.839053 24, 0x0, End_B0=24 End_B1=24
8720 16:53:38.842423 25, 0x0, End_B0=25 End_B1=25
8721 16:53:38.843059 26, 0x0, End_B0=26 End_B1=26
8722 16:53:38.845948 27, 0x0, End_B0=27 End_B1=27
8723 16:53:38.849024 28, 0x0, End_B0=28 End_B1=28
8724 16:53:38.851913 29, 0x0, End_B0=29 End_B1=29
8725 16:53:38.852393 30, 0x0, End_B0=30 End_B1=30
8726 16:53:38.855571 31, 0x5151, End_B0=30 End_B1=30
8727 16:53:38.858650 Byte0 end_step=30 best_step=27
8728 16:53:38.861748 Byte1 end_step=30 best_step=27
8729 16:53:38.865604 Byte0 TX OE(2T, 0.5T) = (3, 3)
8730 16:53:38.868780 Byte1 TX OE(2T, 0.5T) = (3, 3)
8731 16:53:38.869379
8732 16:53:38.869918
8733 16:53:38.874955 [DQSOSCAuto] RK0, (LSB)MR18= 0x50a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 407 ps
8734 16:53:38.878603 CH1 RK0: MR19=303, MR18=50A
8735 16:53:38.884937 CH1_RK0: MR19=0x303, MR18=0x50A, DQSOSC=404, MR23=63, INC=22, DEC=15
8736 16:53:38.885644
8737 16:53:38.888116 ----->DramcWriteLeveling(PI) begin...
8738 16:53:38.888788 ==
8739 16:53:38.891535 Dram Type= 6, Freq= 0, CH_1, rank 1
8740 16:53:38.894732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 16:53:38.895318 ==
8742 16:53:38.897544 Write leveling (Byte 0): 24 => 24
8743 16:53:38.901342 Write leveling (Byte 1): 26 => 26
8744 16:53:38.904299 DramcWriteLeveling(PI) end<-----
8745 16:53:38.904413
8746 16:53:38.904509 ==
8747 16:53:38.908032 Dram Type= 6, Freq= 0, CH_1, rank 1
8748 16:53:38.914141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8749 16:53:38.914251 ==
8750 16:53:38.914349 [Gating] SW mode calibration
8751 16:53:38.924816 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8752 16:53:38.927392 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8753 16:53:38.933979 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 16:53:38.937303 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8755 16:53:38.940257 1 4 8 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
8756 16:53:38.947225 1 4 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8757 16:53:38.950716 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 16:53:38.953801 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 16:53:38.960078 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 16:53:38.963886 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 16:53:38.967207 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 16:53:38.970287 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8763 16:53:38.976896 1 5 8 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 0)
8764 16:53:38.980167 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8765 16:53:38.983269 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 16:53:38.989758 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 16:53:38.993239 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 16:53:38.996290 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 16:53:39.003478 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 16:53:39.006824 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 16:53:39.009785 1 6 8 | B1->B0 | 2626 4646 | 1 0 | (1 1) (0 0)
8772 16:53:39.016670 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8773 16:53:39.019510 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 16:53:39.023303 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 16:53:39.029774 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 16:53:39.032843 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 16:53:39.036602 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 16:53:39.043255 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 16:53:39.046324 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8780 16:53:39.050060 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8781 16:53:39.056572 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8782 16:53:39.059693 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 16:53:39.066198 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 16:53:39.069235 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 16:53:39.072875 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 16:53:39.079730 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 16:53:39.082765 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 16:53:39.085839 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 16:53:39.089644 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 16:53:39.095931 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 16:53:39.099326 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 16:53:39.106057 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 16:53:39.109274 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 16:53:39.112431 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 16:53:39.118800 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8796 16:53:39.121989 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8797 16:53:39.125271 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 16:53:39.128814 Total UI for P1: 0, mck2ui 16
8799 16:53:39.131849 best dqsien dly found for B0: ( 1, 9, 10)
8800 16:53:39.135144 Total UI for P1: 0, mck2ui 16
8801 16:53:39.138296 best dqsien dly found for B1: ( 1, 9, 10)
8802 16:53:39.142026 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8803 16:53:39.145043 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8804 16:53:39.145473
8805 16:53:39.151805 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8806 16:53:39.154710 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8807 16:53:39.158569 [Gating] SW calibration Done
8808 16:53:39.159196 ==
8809 16:53:39.161520 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 16:53:39.164723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 16:53:39.165178 ==
8812 16:53:39.165606 RX Vref Scan: 0
8813 16:53:39.165941
8814 16:53:39.168534 RX Vref 0 -> 0, step: 1
8815 16:53:39.168956
8816 16:53:39.171507 RX Delay 0 -> 252, step: 8
8817 16:53:39.174895 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8818 16:53:39.178064 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8819 16:53:39.184467 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8820 16:53:39.188035 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8821 16:53:39.191247 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8822 16:53:39.194227 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8823 16:53:39.197465 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8824 16:53:39.204233 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8825 16:53:39.207444 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8826 16:53:39.211134 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8827 16:53:39.214245 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8828 16:53:39.217419 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8829 16:53:39.224317 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8830 16:53:39.227292 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8831 16:53:39.230331 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8832 16:53:39.233575 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8833 16:53:39.234014 ==
8834 16:53:39.237120 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 16:53:39.243427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 16:53:39.243933 ==
8837 16:53:39.244388 DQS Delay:
8838 16:53:39.247028 DQS0 = 0, DQS1 = 0
8839 16:53:39.247453 DQM Delay:
8840 16:53:39.250440 DQM0 = 129, DQM1 = 127
8841 16:53:39.250884 DQ Delay:
8842 16:53:39.253361 DQ0 =131, DQ1 =127, DQ2 =115, DQ3 =127
8843 16:53:39.256911 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8844 16:53:39.260114 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8845 16:53:39.263400 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8846 16:53:39.263872
8847 16:53:39.264236
8848 16:53:39.264551 ==
8849 16:53:39.266664 Dram Type= 6, Freq= 0, CH_1, rank 1
8850 16:53:39.273491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8851 16:53:39.273952 ==
8852 16:53:39.274365
8853 16:53:39.274686
8854 16:53:39.274987 TX Vref Scan disable
8855 16:53:39.277289 == TX Byte 0 ==
8856 16:53:39.280281 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8857 16:53:39.286803 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8858 16:53:39.287266 == TX Byte 1 ==
8859 16:53:39.289831 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8860 16:53:39.296950 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8861 16:53:39.297541 ==
8862 16:53:39.300031 Dram Type= 6, Freq= 0, CH_1, rank 1
8863 16:53:39.302999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8864 16:53:39.303426 ==
8865 16:53:39.317816
8866 16:53:39.320165 TX Vref early break, caculate TX vref
8867 16:53:39.323942 TX Vref=16, minBit 0, minWin=23, winSum=385
8868 16:53:39.326953 TX Vref=18, minBit 0, minWin=23, winSum=392
8869 16:53:39.330113 TX Vref=20, minBit 0, minWin=23, winSum=404
8870 16:53:39.333594 TX Vref=22, minBit 0, minWin=24, winSum=407
8871 16:53:39.336749 TX Vref=24, minBit 0, minWin=24, winSum=419
8872 16:53:39.343570 TX Vref=26, minBit 0, minWin=25, winSum=423
8873 16:53:39.346977 TX Vref=28, minBit 0, minWin=25, winSum=424
8874 16:53:39.349828 TX Vref=30, minBit 0, minWin=25, winSum=423
8875 16:53:39.353185 TX Vref=32, minBit 1, minWin=24, winSum=409
8876 16:53:39.356129 TX Vref=34, minBit 1, minWin=23, winSum=405
8877 16:53:39.363134 TX Vref=36, minBit 0, minWin=23, winSum=393
8878 16:53:39.366550 [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28
8879 16:53:39.367076
8880 16:53:39.369364 Final TX Range 0 Vref 28
8881 16:53:39.369839
8882 16:53:39.370206 ==
8883 16:53:39.372785 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 16:53:39.376308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 16:53:39.379660 ==
8886 16:53:39.380098
8887 16:53:39.380453
8888 16:53:39.380764 TX Vref Scan disable
8889 16:53:39.386440 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8890 16:53:39.386968 == TX Byte 0 ==
8891 16:53:39.389450 u2DelayCellOfst[0]=18 cells (5 PI)
8892 16:53:39.392953 u2DelayCellOfst[1]=15 cells (4 PI)
8893 16:53:39.396015 u2DelayCellOfst[2]=0 cells (0 PI)
8894 16:53:39.399249 u2DelayCellOfst[3]=7 cells (2 PI)
8895 16:53:39.402789 u2DelayCellOfst[4]=11 cells (3 PI)
8896 16:53:39.406007 u2DelayCellOfst[5]=22 cells (6 PI)
8897 16:53:39.409144 u2DelayCellOfst[6]=22 cells (6 PI)
8898 16:53:39.412240 u2DelayCellOfst[7]=7 cells (2 PI)
8899 16:53:39.415613 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8900 16:53:39.419451 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8901 16:53:39.422552 == TX Byte 1 ==
8902 16:53:39.425861 u2DelayCellOfst[8]=0 cells (0 PI)
8903 16:53:39.428908 u2DelayCellOfst[9]=7 cells (2 PI)
8904 16:53:39.431913 u2DelayCellOfst[10]=11 cells (3 PI)
8905 16:53:39.436226 u2DelayCellOfst[11]=7 cells (2 PI)
8906 16:53:39.439091 u2DelayCellOfst[12]=15 cells (4 PI)
8907 16:53:39.442278 u2DelayCellOfst[13]=22 cells (6 PI)
8908 16:53:39.445167 u2DelayCellOfst[14]=22 cells (6 PI)
8909 16:53:39.448824 u2DelayCellOfst[15]=22 cells (6 PI)
8910 16:53:39.452239 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8911 16:53:39.455258 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8912 16:53:39.458232 DramC Write-DBI on
8913 16:53:39.458657 ==
8914 16:53:39.461950 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 16:53:39.465309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 16:53:39.465737 ==
8917 16:53:39.466181
8918 16:53:39.466520
8919 16:53:39.468228 TX Vref Scan disable
8920 16:53:39.471521 == TX Byte 0 ==
8921 16:53:39.475100 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8922 16:53:39.475570 == TX Byte 1 ==
8923 16:53:39.481488 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8924 16:53:39.481957 DramC Write-DBI off
8925 16:53:39.482309
8926 16:53:39.482623 [DATLAT]
8927 16:53:39.484827 Freq=1600, CH1 RK1
8928 16:53:39.485252
8929 16:53:39.488209 DATLAT Default: 0xf
8930 16:53:39.488634 0, 0xFFFF, sum = 0
8931 16:53:39.491335 1, 0xFFFF, sum = 0
8932 16:53:39.491809 2, 0xFFFF, sum = 0
8933 16:53:39.494528 3, 0xFFFF, sum = 0
8934 16:53:39.494984 4, 0xFFFF, sum = 0
8935 16:53:39.497903 5, 0xFFFF, sum = 0
8936 16:53:39.498355 6, 0xFFFF, sum = 0
8937 16:53:39.501733 7, 0xFFFF, sum = 0
8938 16:53:39.502216 8, 0xFFFF, sum = 0
8939 16:53:39.504941 9, 0xFFFF, sum = 0
8940 16:53:39.505486 10, 0xFFFF, sum = 0
8941 16:53:39.507794 11, 0xFFFF, sum = 0
8942 16:53:39.508225 12, 0xFFFF, sum = 0
8943 16:53:39.510987 13, 0x8FFF, sum = 0
8944 16:53:39.514125 14, 0x0, sum = 1
8945 16:53:39.514556 15, 0x0, sum = 2
8946 16:53:39.514933 16, 0x0, sum = 3
8947 16:53:39.517865 17, 0x0, sum = 4
8948 16:53:39.518322 best_step = 15
8949 16:53:39.518677
8950 16:53:39.520759 ==
8951 16:53:39.521184 Dram Type= 6, Freq= 0, CH_1, rank 1
8952 16:53:39.527152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8953 16:53:39.527600 ==
8954 16:53:39.527946 RX Vref Scan: 0
8955 16:53:39.528265
8956 16:53:39.530965 RX Vref 0 -> 0, step: 1
8957 16:53:39.531388
8958 16:53:39.533966 RX Delay 3 -> 252, step: 4
8959 16:53:39.537685 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8960 16:53:39.540345 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8961 16:53:39.547100 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8962 16:53:39.550360 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8963 16:53:39.553644 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8964 16:53:39.556714 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8965 16:53:39.560404 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8966 16:53:39.567166 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8967 16:53:39.570205 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8968 16:53:39.573597 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8969 16:53:39.576808 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8970 16:53:39.583013 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8971 16:53:39.586711 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8972 16:53:39.590136 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8973 16:53:39.593391 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8974 16:53:39.596510 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8975 16:53:39.599871 ==
8976 16:53:39.602981 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 16:53:39.606534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 16:53:39.606951 ==
8979 16:53:39.607283 DQS Delay:
8980 16:53:39.609884 DQS0 = 0, DQS1 = 0
8981 16:53:39.610305 DQM Delay:
8982 16:53:39.612834 DQM0 = 127, DQM1 = 125
8983 16:53:39.613276 DQ Delay:
8984 16:53:39.615774 DQ0 =132, DQ1 =126, DQ2 =116, DQ3 =124
8985 16:53:39.619798 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
8986 16:53:39.622743 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
8987 16:53:39.625829 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
8988 16:53:39.626447
8989 16:53:39.626950
8990 16:53:39.629312
8991 16:53:39.629758 [DramC_TX_OE_Calibration] TA2
8992 16:53:39.632359 Original DQ_B0 (3 6) =30, OEN = 27
8993 16:53:39.636196 Original DQ_B1 (3 6) =30, OEN = 27
8994 16:53:39.639193 24, 0x0, End_B0=24 End_B1=24
8995 16:53:39.642304 25, 0x0, End_B0=25 End_B1=25
8996 16:53:39.646103 26, 0x0, End_B0=26 End_B1=26
8997 16:53:39.646536 27, 0x0, End_B0=27 End_B1=27
8998 16:53:39.649319 28, 0x0, End_B0=28 End_B1=28
8999 16:53:39.652491 29, 0x0, End_B0=29 End_B1=29
9000 16:53:39.655656 30, 0x0, End_B0=30 End_B1=30
9001 16:53:39.658725 31, 0x4141, End_B0=30 End_B1=30
9002 16:53:39.659162 Byte0 end_step=30 best_step=27
9003 16:53:39.661976 Byte1 end_step=30 best_step=27
9004 16:53:39.665554 Byte0 TX OE(2T, 0.5T) = (3, 3)
9005 16:53:39.668692 Byte1 TX OE(2T, 0.5T) = (3, 3)
9006 16:53:39.669136
9007 16:53:39.669469
9008 16:53:39.675685 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9009 16:53:39.678725 CH1 RK1: MR19=303, MR18=F1C
9010 16:53:39.685426 CH1_RK1: MR19=0x303, MR18=0xF1C, DQSOSC=395, MR23=63, INC=23, DEC=15
9011 16:53:39.688484 [RxdqsGatingPostProcess] freq 1600
9012 16:53:39.695565 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9013 16:53:39.698768 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 16:53:39.699197 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 16:53:39.701714 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 16:53:39.704953 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 16:53:39.708319 best DQS0 dly(2T, 0.5T) = (1, 1)
9018 16:53:39.711967 best DQS1 dly(2T, 0.5T) = (1, 1)
9019 16:53:39.714819 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9020 16:53:39.718178 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9021 16:53:39.721372 Pre-setting of DQS Precalculation
9022 16:53:39.728485 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9023 16:53:39.734794 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9024 16:53:39.741536 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9025 16:53:39.742079
9026 16:53:39.742425
9027 16:53:39.745006 [Calibration Summary] 3200 Mbps
9028 16:53:39.745434 CH 0, Rank 0
9029 16:53:39.747890 SW Impedance : PASS
9030 16:53:39.751016 DUTY Scan : NO K
9031 16:53:39.751539 ZQ Calibration : PASS
9032 16:53:39.754899 Jitter Meter : NO K
9033 16:53:39.757983 CBT Training : PASS
9034 16:53:39.758520 Write leveling : PASS
9035 16:53:39.761221 RX DQS gating : PASS
9036 16:53:39.764335 RX DQ/DQS(RDDQC) : PASS
9037 16:53:39.764803 TX DQ/DQS : PASS
9038 16:53:39.767987 RX DATLAT : PASS
9039 16:53:39.768412 RX DQ/DQS(Engine): PASS
9040 16:53:39.770971 TX OE : PASS
9041 16:53:39.771493 All Pass.
9042 16:53:39.771910
9043 16:53:39.774118 CH 0, Rank 1
9044 16:53:39.774570 SW Impedance : PASS
9045 16:53:39.777653 DUTY Scan : NO K
9046 16:53:39.780881 ZQ Calibration : PASS
9047 16:53:39.781347 Jitter Meter : NO K
9048 16:53:39.784116 CBT Training : PASS
9049 16:53:39.787686 Write leveling : PASS
9050 16:53:39.788124 RX DQS gating : PASS
9051 16:53:39.790679 RX DQ/DQS(RDDQC) : PASS
9052 16:53:39.794351 TX DQ/DQS : PASS
9053 16:53:39.794839 RX DATLAT : PASS
9054 16:53:39.797656 RX DQ/DQS(Engine): PASS
9055 16:53:39.800644 TX OE : PASS
9056 16:53:39.801144 All Pass.
9057 16:53:39.801486
9058 16:53:39.801801 CH 1, Rank 0
9059 16:53:39.804261 SW Impedance : PASS
9060 16:53:39.807349 DUTY Scan : NO K
9061 16:53:39.807895 ZQ Calibration : PASS
9062 16:53:39.810771 Jitter Meter : NO K
9063 16:53:39.813786 CBT Training : PASS
9064 16:53:39.814310 Write leveling : PASS
9065 16:53:39.817159 RX DQS gating : PASS
9066 16:53:39.820557 RX DQ/DQS(RDDQC) : PASS
9067 16:53:39.820990 TX DQ/DQS : PASS
9068 16:53:39.823772 RX DATLAT : PASS
9069 16:53:39.827219 RX DQ/DQS(Engine): PASS
9070 16:53:39.827752 TX OE : PASS
9071 16:53:39.830439 All Pass.
9072 16:53:39.830853
9073 16:53:39.831185 CH 1, Rank 1
9074 16:53:39.833985 SW Impedance : PASS
9075 16:53:39.834549 DUTY Scan : NO K
9076 16:53:39.837298 ZQ Calibration : PASS
9077 16:53:39.839952 Jitter Meter : NO K
9078 16:53:39.840367 CBT Training : PASS
9079 16:53:39.843757 Write leveling : PASS
9080 16:53:39.846648 RX DQS gating : PASS
9081 16:53:39.847201 RX DQ/DQS(RDDQC) : PASS
9082 16:53:39.849995 TX DQ/DQS : PASS
9083 16:53:39.853407 RX DATLAT : PASS
9084 16:53:39.853950 RX DQ/DQS(Engine): PASS
9085 16:53:39.856919 TX OE : PASS
9086 16:53:39.857337 All Pass.
9087 16:53:39.857667
9088 16:53:39.859898 DramC Write-DBI on
9089 16:53:39.863316 PER_BANK_REFRESH: Hybrid Mode
9090 16:53:39.863755 TX_TRACKING: ON
9091 16:53:39.873565 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9092 16:53:39.879493 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9093 16:53:39.886603 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9094 16:53:39.889341 [FAST_K] Save calibration result to emmc
9095 16:53:39.892552 sync common calibartion params.
9096 16:53:39.896206 sync cbt_mode0:1, 1:1
9097 16:53:39.899281 dram_init: ddr_geometry: 2
9098 16:53:39.899730 dram_init: ddr_geometry: 2
9099 16:53:39.902475 dram_init: ddr_geometry: 2
9100 16:53:39.906324 0:dram_rank_size:100000000
9101 16:53:39.909300 1:dram_rank_size:100000000
9102 16:53:39.912403 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9103 16:53:39.916207 DFS_SHUFFLE_HW_MODE: ON
9104 16:53:39.919405 dramc_set_vcore_voltage set vcore to 725000
9105 16:53:39.922475 Read voltage for 1600, 0
9106 16:53:39.922899 Vio18 = 0
9107 16:53:39.923239 Vcore = 725000
9108 16:53:39.925978 Vdram = 0
9109 16:53:39.926405 Vddq = 0
9110 16:53:39.926745 Vmddr = 0
9111 16:53:39.928826 switch to 3200 Mbps bootup
9112 16:53:39.932412 [DramcRunTimeConfig]
9113 16:53:39.932834 PHYPLL
9114 16:53:39.933171 DPM_CONTROL_AFTERK: ON
9115 16:53:39.935446 PER_BANK_REFRESH: ON
9116 16:53:39.939209 REFRESH_OVERHEAD_REDUCTION: ON
9117 16:53:39.939673 CMD_PICG_NEW_MODE: OFF
9118 16:53:39.942252 XRTWTW_NEW_MODE: ON
9119 16:53:39.945140 XRTRTR_NEW_MODE: ON
9120 16:53:39.945592 TX_TRACKING: ON
9121 16:53:39.949176 RDSEL_TRACKING: OFF
9122 16:53:39.949600 DQS Precalculation for DVFS: ON
9123 16:53:39.952260 RX_TRACKING: OFF
9124 16:53:39.952685 HW_GATING DBG: ON
9125 16:53:39.955361 ZQCS_ENABLE_LP4: ON
9126 16:53:39.958490 RX_PICG_NEW_MODE: ON
9127 16:53:39.958998 TX_PICG_NEW_MODE: ON
9128 16:53:39.962123 ENABLE_RX_DCM_DPHY: ON
9129 16:53:39.965404 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9130 16:53:39.965830 DUMMY_READ_FOR_TRACKING: OFF
9131 16:53:39.968501 !!! SPM_CONTROL_AFTERK: OFF
9132 16:53:39.971751 !!! SPM could not control APHY
9133 16:53:39.975082 IMPEDANCE_TRACKING: ON
9134 16:53:39.975570 TEMP_SENSOR: ON
9135 16:53:39.978032 HW_SAVE_FOR_SR: OFF
9136 16:53:39.981784 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9137 16:53:39.984880 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9138 16:53:39.985332 Read ODT Tracking: ON
9139 16:53:39.987949 Refresh Rate DeBounce: ON
9140 16:53:39.991741 DFS_NO_QUEUE_FLUSH: ON
9141 16:53:39.994881 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9142 16:53:39.995307 ENABLE_DFS_RUNTIME_MRW: OFF
9143 16:53:39.998051 DDR_RESERVE_NEW_MODE: ON
9144 16:53:40.001042 MR_CBT_SWITCH_FREQ: ON
9145 16:53:40.001469 =========================
9146 16:53:40.021196 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9147 16:53:40.024957 dram_init: ddr_geometry: 2
9148 16:53:40.043256 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9149 16:53:40.046299 dram_init: dram init end (result: 0)
9150 16:53:40.053328 DRAM-K: Full calibration passed in 24538 msecs
9151 16:53:40.056480 MRC: failed to locate region type 0.
9152 16:53:40.056898 DRAM rank0 size:0x100000000,
9153 16:53:40.059371 DRAM rank1 size=0x100000000
9154 16:53:40.069098 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9155 16:53:40.076062 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9156 16:53:40.082940 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9157 16:53:40.092723 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9158 16:53:40.093304 DRAM rank0 size:0x100000000,
9159 16:53:40.095730 DRAM rank1 size=0x100000000
9160 16:53:40.096225 CBMEM:
9161 16:53:40.099094 IMD: root @ 0xfffff000 254 entries.
9162 16:53:40.102866 IMD: root @ 0xffffec00 62 entries.
9163 16:53:40.105753 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9164 16:53:40.112251 WARNING: RO_VPD is uninitialized or empty.
9165 16:53:40.115416 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9166 16:53:40.122688 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9167 16:53:40.135691 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9168 16:53:40.147154 BS: romstage times (exec / console): total (unknown) / 24010 ms
9169 16:53:40.147637
9170 16:53:40.147992
9171 16:53:40.156947 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9172 16:53:40.160422 ARM64: Exception handlers installed.
9173 16:53:40.163519 ARM64: Testing exception
9174 16:53:40.166852 ARM64: Done test exception
9175 16:53:40.167301 Enumerating buses...
9176 16:53:40.169928 Show all devs... Before device enumeration.
9177 16:53:40.173792 Root Device: enabled 1
9178 16:53:40.176779 CPU_CLUSTER: 0: enabled 1
9179 16:53:40.177209 CPU: 00: enabled 1
9180 16:53:40.179797 Compare with tree...
9181 16:53:40.180218 Root Device: enabled 1
9182 16:53:40.183111 CPU_CLUSTER: 0: enabled 1
9183 16:53:40.186730 CPU: 00: enabled 1
9184 16:53:40.187159 Root Device scanning...
9185 16:53:40.190024 scan_static_bus for Root Device
9186 16:53:40.192833 CPU_CLUSTER: 0 enabled
9187 16:53:40.196499 scan_static_bus for Root Device done
9188 16:53:40.199810 scan_bus: bus Root Device finished in 8 msecs
9189 16:53:40.200270 done
9190 16:53:40.206028 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9191 16:53:40.209802 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9192 16:53:40.215993 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9193 16:53:40.222793 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9194 16:53:40.223212 Allocating resources...
9195 16:53:40.225737 Reading resources...
9196 16:53:40.229190 Root Device read_resources bus 0 link: 0
9197 16:53:40.233079 DRAM rank0 size:0x100000000,
9198 16:53:40.233496 DRAM rank1 size=0x100000000
9199 16:53:40.239204 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9200 16:53:40.239698 CPU: 00 missing read_resources
9201 16:53:40.246055 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9202 16:53:40.249297 Root Device read_resources bus 0 link: 0 done
9203 16:53:40.252293 Done reading resources.
9204 16:53:40.255332 Show resources in subtree (Root Device)...After reading.
9205 16:53:40.258758 Root Device child on link 0 CPU_CLUSTER: 0
9206 16:53:40.262225 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 16:53:40.271915 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 16:53:40.272360 CPU: 00
9209 16:53:40.279002 Root Device assign_resources, bus 0 link: 0
9210 16:53:40.282118 CPU_CLUSTER: 0 missing set_resources
9211 16:53:40.285420 Root Device assign_resources, bus 0 link: 0 done
9212 16:53:40.288332 Done setting resources.
9213 16:53:40.291519 Show resources in subtree (Root Device)...After assigning values.
9214 16:53:40.298358 Root Device child on link 0 CPU_CLUSTER: 0
9215 16:53:40.301929 CPU_CLUSTER: 0 child on link 0 CPU: 00
9216 16:53:40.308249 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9217 16:53:40.311414 CPU: 00
9218 16:53:40.311911 Done allocating resources.
9219 16:53:40.317950 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9220 16:53:40.321086 Enabling resources...
9221 16:53:40.321677 done.
9222 16:53:40.324630 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9223 16:53:40.327834 Initializing devices...
9224 16:53:40.328431 Root Device init
9225 16:53:40.330890 init hardware done!
9226 16:53:40.334511 0x00000018: ctrlr->caps
9227 16:53:40.334985 52.000 MHz: ctrlr->f_max
9228 16:53:40.338330 0.400 MHz: ctrlr->f_min
9229 16:53:40.341249 0x40ff8080: ctrlr->voltages
9230 16:53:40.341700 sclk: 390625
9231 16:53:40.342145 Bus Width = 1
9232 16:53:40.344323 sclk: 390625
9233 16:53:40.344738 Bus Width = 1
9234 16:53:40.347870 Early init status = 3
9235 16:53:40.351222 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9236 16:53:40.355560 in-header: 03 fc 00 00 01 00 00 00
9237 16:53:40.359289 in-data: 00
9238 16:53:40.362278 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9239 16:53:40.367999 in-header: 03 fd 00 00 00 00 00 00
9240 16:53:40.370959 in-data:
9241 16:53:40.374213 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9242 16:53:40.378733 in-header: 03 fc 00 00 01 00 00 00
9243 16:53:40.381693 in-data: 00
9244 16:53:40.385424 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9245 16:53:40.391111 in-header: 03 fd 00 00 00 00 00 00
9246 16:53:40.394327 in-data:
9247 16:53:40.397496 [SSUSB] Setting up USB HOST controller...
9248 16:53:40.400595 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9249 16:53:40.403908 [SSUSB] phy power-on done.
9250 16:53:40.407363 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9251 16:53:40.414138 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9252 16:53:40.417231 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9253 16:53:40.423975 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9254 16:53:40.430495 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9255 16:53:40.436330 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9256 16:53:40.443002 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9257 16:53:40.450338 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9258 16:53:40.452977 SPM: binary array size = 0x9dc
9259 16:53:40.459861 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9260 16:53:40.463078 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9261 16:53:40.469979 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9262 16:53:40.476533 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9263 16:53:40.479420 configure_display: Starting display init
9264 16:53:40.514385 anx7625_power_on_init: Init interface.
9265 16:53:40.517607 anx7625_disable_pd_protocol: Disabled PD feature.
9266 16:53:40.520720 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9267 16:53:40.548255 anx7625_start_dp_work: Secure OCM version=00
9268 16:53:40.551425 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9269 16:53:40.566389 sp_tx_get_edid_block: EDID Block = 1
9270 16:53:40.668968 Extracted contents:
9271 16:53:40.672639 header: 00 ff ff ff ff ff ff 00
9272 16:53:40.675624 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9273 16:53:40.679216 version: 01 04
9274 16:53:40.682335 basic params: 95 1f 11 78 0a
9275 16:53:40.685528 chroma info: 76 90 94 55 54 90 27 21 50 54
9276 16:53:40.689468 established: 00 00 00
9277 16:53:40.695285 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9278 16:53:40.702115 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9279 16:53:40.705014 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9280 16:53:40.711669 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9281 16:53:40.718301 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9282 16:53:40.721802 extensions: 00
9283 16:53:40.722222 checksum: fb
9284 16:53:40.722584
9285 16:53:40.728058 Manufacturer: IVO Model 57d Serial Number 0
9286 16:53:40.728480 Made week 0 of 2020
9287 16:53:40.731857 EDID version: 1.4
9288 16:53:40.732279 Digital display
9289 16:53:40.735003 6 bits per primary color channel
9290 16:53:40.738094 DisplayPort interface
9291 16:53:40.738510 Maximum image size: 31 cm x 17 cm
9292 16:53:40.741268 Gamma: 220%
9293 16:53:40.741678 Check DPMS levels
9294 16:53:40.748197 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9295 16:53:40.751200 First detailed timing is preferred timing
9296 16:53:40.754960 Established timings supported:
9297 16:53:40.755368 Standard timings supported:
9298 16:53:40.758058 Detailed timings
9299 16:53:40.760995 Hex of detail: 383680a07038204018303c0035ae10000019
9300 16:53:40.768082 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9301 16:53:40.770804 0780 0798 07c8 0820 hborder 0
9302 16:53:40.774217 0438 043b 0447 0458 vborder 0
9303 16:53:40.777893 -hsync -vsync
9304 16:53:40.778316 Did detailed timing
9305 16:53:40.784621 Hex of detail: 000000000000000000000000000000000000
9306 16:53:40.787788 Manufacturer-specified data, tag 0
9307 16:53:40.790898 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9308 16:53:40.794433 ASCII string: InfoVision
9309 16:53:40.797508 Hex of detail: 000000fe00523134304e574635205248200a
9310 16:53:40.800617 ASCII string: R140NWF5 RH
9311 16:53:40.801075 Checksum
9312 16:53:40.804350 Checksum: 0xfb (valid)
9313 16:53:40.807310 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9314 16:53:40.810783 DSI data_rate: 832800000 bps
9315 16:53:40.817389 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9316 16:53:40.820593 anx7625_parse_edid: pixelclock(138800).
9317 16:53:40.824128 hactive(1920), hsync(48), hfp(24), hbp(88)
9318 16:53:40.827078 vactive(1080), vsync(12), vfp(3), vbp(17)
9319 16:53:40.830717 anx7625_dsi_config: config dsi.
9320 16:53:40.836978 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9321 16:53:40.851169 anx7625_dsi_config: success to config DSI
9322 16:53:40.854545 anx7625_dp_start: MIPI phy setup OK.
9323 16:53:40.858143 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9324 16:53:40.861208 mtk_ddp_mode_set invalid vrefresh 60
9325 16:53:40.864450 main_disp_path_setup
9326 16:53:40.864863 ovl_layer_smi_id_en
9327 16:53:40.867544 ovl_layer_smi_id_en
9328 16:53:40.868007 ccorr_config
9329 16:53:40.868338 aal_config
9330 16:53:40.871042 gamma_config
9331 16:53:40.871458 postmask_config
9332 16:53:40.873930 dither_config
9333 16:53:40.877556 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9334 16:53:40.883668 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9335 16:53:40.887441 Root Device init finished in 555 msecs
9336 16:53:40.890582 CPU_CLUSTER: 0 init
9337 16:53:40.897117 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9338 16:53:40.903922 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9339 16:53:40.904338 APU_MBOX 0x190000b0 = 0x10001
9340 16:53:40.907073 APU_MBOX 0x190001b0 = 0x10001
9341 16:53:40.910062 APU_MBOX 0x190005b0 = 0x10001
9342 16:53:40.913586 APU_MBOX 0x190006b0 = 0x10001
9343 16:53:40.920072 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9344 16:53:40.930151 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9345 16:53:40.942277 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9346 16:53:40.949254 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9347 16:53:40.960585 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9348 16:53:40.969917 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9349 16:53:40.973332 CPU_CLUSTER: 0 init finished in 81 msecs
9350 16:53:40.976281 Devices initialized
9351 16:53:40.979710 Show all devs... After init.
9352 16:53:40.980172 Root Device: enabled 1
9353 16:53:40.983404 CPU_CLUSTER: 0: enabled 1
9354 16:53:40.986331 CPU: 00: enabled 1
9355 16:53:40.990102 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9356 16:53:40.992747 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9357 16:53:40.996076 ELOG: NV offset 0x57f000 size 0x1000
9358 16:53:41.002976 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9359 16:53:41.009536 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9360 16:53:41.013237 ELOG: Event(17) added with size 13 at 2023-06-03 16:53:41 UTC
9361 16:53:41.019560 out: cmd=0x121: 03 db 21 01 00 00 00 00
9362 16:53:41.022670 in-header: 03 78 00 00 2c 00 00 00
9363 16:53:41.032745 in-data: e7 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 16:53:41.039234 ELOG: Event(A1) added with size 10 at 2023-06-03 16:53:41 UTC
9365 16:53:41.045645 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9366 16:53:41.052313 ELOG: Event(A0) added with size 9 at 2023-06-03 16:53:41 UTC
9367 16:53:41.056152 elog_add_boot_reason: Logged dev mode boot
9368 16:53:41.062405 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9369 16:53:41.062890 Finalize devices...
9370 16:53:41.065485 Devices finalized
9371 16:53:41.069376 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9372 16:53:41.071940 Writing coreboot table at 0xffe64000
9373 16:53:41.075141 0. 000000000010a000-0000000000113fff: RAMSTAGE
9374 16:53:41.081825 1. 0000000040000000-00000000400fffff: RAM
9375 16:53:41.085770 2. 0000000040100000-000000004032afff: RAMSTAGE
9376 16:53:41.088647 3. 000000004032b000-00000000545fffff: RAM
9377 16:53:41.091696 4. 0000000054600000-000000005465ffff: BL31
9378 16:53:41.095380 5. 0000000054660000-00000000ffe63fff: RAM
9379 16:53:41.102151 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9380 16:53:41.104905 7. 0000000100000000-000000023fffffff: RAM
9381 16:53:41.108983 Passing 5 GPIOs to payload:
9382 16:53:41.111786 NAME | PORT | POLARITY | VALUE
9383 16:53:41.118738 EC in RW | 0x000000aa | low | undefined
9384 16:53:41.121609 EC interrupt | 0x00000005 | low | undefined
9385 16:53:41.128574 TPM interrupt | 0x000000ab | high | undefined
9386 16:53:41.131418 SD card detect | 0x00000011 | high | undefined
9387 16:53:41.134885 speaker enable | 0x00000093 | high | undefined
9388 16:53:41.137818 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9389 16:53:41.141518 in-header: 03 f9 00 00 02 00 00 00
9390 16:53:41.144755 in-data: 02 00
9391 16:53:41.147820 ADC[4]: Raw value=894451 ID=7
9392 16:53:41.151616 ADC[3]: Raw value=213440 ID=1
9393 16:53:41.152149 RAM Code: 0x71
9394 16:53:41.154460 ADC[6]: Raw value=74722 ID=0
9395 16:53:41.157943 ADC[5]: Raw value=211960 ID=1
9396 16:53:41.158583 SKU Code: 0x1
9397 16:53:41.164334 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9398 16:53:41.164755 coreboot table: 964 bytes.
9399 16:53:41.168044 IMD ROOT 0. 0xfffff000 0x00001000
9400 16:53:41.171179 IMD SMALL 1. 0xffffe000 0x00001000
9401 16:53:41.174348 RO MCACHE 2. 0xffffc000 0x00001104
9402 16:53:41.177537 CONSOLE 3. 0xfff7c000 0x00080000
9403 16:53:41.180633 FMAP 4. 0xfff7b000 0x00000452
9404 16:53:41.184298 TIME STAMP 5. 0xfff7a000 0x00000910
9405 16:53:41.187346 VBOOT WORK 6. 0xfff66000 0x00014000
9406 16:53:41.190492 RAMOOPS 7. 0xffe66000 0x00100000
9407 16:53:41.193985 COREBOOT 8. 0xffe64000 0x00002000
9408 16:53:41.197175 IMD small region:
9409 16:53:41.200562 IMD ROOT 0. 0xffffec00 0x00000400
9410 16:53:41.204162 VPD 1. 0xffffeba0 0x0000004c
9411 16:53:41.207161 MMC STATUS 2. 0xffffeb80 0x00000004
9412 16:53:41.213753 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9413 16:53:41.214173 Probing TPM: done!
9414 16:53:41.220162 Connected to device vid:did:rid of 1ae0:0028:00
9415 16:53:41.227099 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9416 16:53:41.230861 Initialized TPM device CR50 revision 0
9417 16:53:41.233828 Checking cr50 for pending updates
9418 16:53:41.239530 Reading cr50 TPM mode
9419 16:53:41.248558 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9420 16:53:41.255163 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9421 16:53:41.294693 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9422 16:53:41.298201 Checking segment from ROM address 0x40100000
9423 16:53:41.304595 Checking segment from ROM address 0x4010001c
9424 16:53:41.307809 Loading segment from ROM address 0x40100000
9425 16:53:41.308226 code (compression=0)
9426 16:53:41.318096 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9427 16:53:41.324524 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9428 16:53:41.325014 it's not compressed!
9429 16:53:41.331141 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9430 16:53:41.337899 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9431 16:53:41.355224 Loading segment from ROM address 0x4010001c
9432 16:53:41.355794 Entry Point 0x80000000
9433 16:53:41.358480 Loaded segments
9434 16:53:41.361620 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9435 16:53:41.368630 Jumping to boot code at 0x80000000(0xffe64000)
9436 16:53:41.375184 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9437 16:53:41.381578 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9438 16:53:41.389662 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9439 16:53:41.392747 Checking segment from ROM address 0x40100000
9440 16:53:41.396258 Checking segment from ROM address 0x4010001c
9441 16:53:41.403036 Loading segment from ROM address 0x40100000
9442 16:53:41.403636 code (compression=1)
9443 16:53:41.409248 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9444 16:53:41.418979 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9445 16:53:41.419403 using LZMA
9446 16:53:41.427950 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9447 16:53:41.434655 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9448 16:53:41.437536 Loading segment from ROM address 0x4010001c
9449 16:53:41.437618 Entry Point 0x54601000
9450 16:53:41.440798 Loaded segments
9451 16:53:41.444410 NOTICE: MT8192 bl31_setup
9452 16:53:41.451380 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9453 16:53:41.454596 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9454 16:53:41.457616 WARNING: region 0:
9455 16:53:41.461261 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9456 16:53:41.461337 WARNING: region 1:
9457 16:53:41.467615 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9458 16:53:41.471205 WARNING: region 2:
9459 16:53:41.474402 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9460 16:53:41.477857 WARNING: region 3:
9461 16:53:41.480785 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9462 16:53:41.484737 WARNING: region 4:
9463 16:53:41.491201 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9464 16:53:41.491296 WARNING: region 5:
9465 16:53:41.494683 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 16:53:41.497612 WARNING: region 6:
9467 16:53:41.500723 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9468 16:53:41.504623 WARNING: region 7:
9469 16:53:41.507773 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9470 16:53:41.514073 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9471 16:53:41.517741 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9472 16:53:41.520768 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9473 16:53:41.527761 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9474 16:53:41.530878 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9475 16:53:41.534038 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9476 16:53:41.541078 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9477 16:53:41.544054 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9478 16:53:41.551121 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9479 16:53:41.554288 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9480 16:53:41.557911 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9481 16:53:41.563992 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9482 16:53:41.567835 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9483 16:53:41.571196 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9484 16:53:41.577945 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9485 16:53:41.580846 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9486 16:53:41.587230 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9487 16:53:41.590927 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9488 16:53:41.594273 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9489 16:53:41.600716 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9490 16:53:41.604385 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9491 16:53:41.610949 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9492 16:53:41.614407 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9493 16:53:41.618053 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9494 16:53:41.623996 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9495 16:53:41.627757 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9496 16:53:41.634416 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9497 16:53:41.637690 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9498 16:53:41.640772 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9499 16:53:41.647078 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9500 16:53:41.650952 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9501 16:53:41.657416 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9502 16:53:41.660927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9503 16:53:41.664125 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9504 16:53:41.667077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9505 16:53:41.673978 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9506 16:53:41.677015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9507 16:53:41.680412 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9508 16:53:41.683844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9509 16:53:41.690923 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9510 16:53:41.694091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9511 16:53:41.697311 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9512 16:53:41.700426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9513 16:53:41.707148 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9514 16:53:41.710257 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9515 16:53:41.713333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9516 16:53:41.717181 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9517 16:53:41.723709 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9518 16:53:41.726892 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9519 16:53:41.733672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9520 16:53:41.736783 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9521 16:53:41.740530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9522 16:53:41.746826 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9523 16:53:41.749874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9524 16:53:41.756460 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9525 16:53:41.759940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9526 16:53:41.766217 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9527 16:53:41.769591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9528 16:53:41.776339 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9529 16:53:41.780088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9530 16:53:41.783568 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9531 16:53:41.789811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9532 16:53:41.793009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9533 16:53:41.799426 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9534 16:53:41.803271 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9535 16:53:41.809455 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9536 16:53:41.813015 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9537 16:53:41.819726 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9538 16:53:41.822926 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9539 16:53:41.826020 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9540 16:53:41.832495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9541 16:53:41.835884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9542 16:53:41.842761 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9543 16:53:41.846258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9544 16:53:41.852546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9545 16:53:41.856885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9546 16:53:41.859811 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9547 16:53:41.866373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9548 16:53:41.869501 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9549 16:53:41.876047 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9550 16:53:41.879664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9551 16:53:41.886248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9552 16:53:41.889321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9553 16:53:41.896245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9554 16:53:41.899083 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9555 16:53:41.902595 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9556 16:53:41.909244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9557 16:53:41.912700 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9558 16:53:41.919239 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9559 16:53:41.922437 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9560 16:53:41.928987 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9561 16:53:41.932159 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9562 16:53:41.939151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9563 16:53:41.942053 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9564 16:53:41.945204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9565 16:53:41.951852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9566 16:53:41.955032 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9567 16:53:41.958905 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9568 16:53:41.965295 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9569 16:53:41.968259 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9570 16:53:41.972011 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9571 16:53:41.978444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9572 16:53:41.981446 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9573 16:53:41.988099 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9574 16:53:41.991556 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9575 16:53:41.995271 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9576 16:53:42.001614 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9577 16:53:42.004682 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9578 16:53:42.011243 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9579 16:53:42.014733 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9580 16:53:42.017663 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9581 16:53:42.024487 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9582 16:53:42.028076 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9583 16:53:42.034913 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9584 16:53:42.037864 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9585 16:53:42.041046 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9586 16:53:42.044616 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9587 16:53:42.050918 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9588 16:53:42.054736 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9589 16:53:42.058155 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9590 16:53:42.064192 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9591 16:53:42.067670 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9592 16:53:42.071617 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9593 16:53:42.074612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9594 16:53:42.081247 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9595 16:53:42.084915 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9596 16:53:42.091234 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9597 16:53:42.094340 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9598 16:53:42.097699 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9599 16:53:42.104014 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9600 16:53:42.107875 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9601 16:53:42.114154 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9602 16:53:42.117815 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9603 16:53:42.120769 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9604 16:53:42.127689 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9605 16:53:42.130658 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9606 16:53:42.137355 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9607 16:53:42.141325 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9608 16:53:42.144208 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9609 16:53:42.151003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9610 16:53:42.154145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9611 16:53:42.160885 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9612 16:53:42.164062 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9613 16:53:42.167328 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9614 16:53:42.174301 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9615 16:53:42.177172 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9616 16:53:42.183879 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9617 16:53:42.187067 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9618 16:53:42.190979 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9619 16:53:42.197051 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9620 16:53:42.200166 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9621 16:53:42.203937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9622 16:53:42.210450 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9623 16:53:42.213713 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9624 16:53:42.220546 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9625 16:53:42.223653 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9626 16:53:42.227471 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9627 16:53:42.233608 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9628 16:53:42.237207 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9629 16:53:42.243726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9630 16:53:42.247084 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9631 16:53:42.250377 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9632 16:53:42.256650 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9633 16:53:42.259688 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9634 16:53:42.266710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9635 16:53:42.270032 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9636 16:53:42.272966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9637 16:53:42.279826 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9638 16:53:42.282848 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9639 16:53:42.290327 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9640 16:53:42.293294 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9641 16:53:42.296200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9642 16:53:42.303255 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9643 16:53:42.306295 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9644 16:53:42.312867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9645 16:53:42.316237 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9646 16:53:42.319468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9647 16:53:42.325510 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9648 16:53:42.329378 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9649 16:53:42.335554 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9650 16:53:42.339341 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9651 16:53:42.342701 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9652 16:53:42.349378 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9653 16:53:42.352129 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9654 16:53:42.358891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9655 16:53:42.362192 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9656 16:53:42.365165 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9657 16:53:42.372116 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9658 16:53:42.375442 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9659 16:53:42.382198 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9660 16:53:42.385225 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9661 16:53:42.391374 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9662 16:53:42.395111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9663 16:53:42.398300 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9664 16:53:42.404812 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9665 16:53:42.408373 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9666 16:53:42.415731 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9667 16:53:42.417813 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9668 16:53:42.424508 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9669 16:53:42.428181 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9670 16:53:42.431269 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9671 16:53:42.437581 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9672 16:53:42.441596 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9673 16:53:42.448072 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9674 16:53:42.450830 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9675 16:53:42.457685 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9676 16:53:42.461414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9677 16:53:42.464272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9678 16:53:42.470986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9679 16:53:42.473936 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9680 16:53:42.480792 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9681 16:53:42.484056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9682 16:53:42.490370 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9683 16:53:42.494055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9684 16:53:42.496791 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9685 16:53:42.503889 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9686 16:53:42.506779 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9687 16:53:42.514036 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9688 16:53:42.517029 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9689 16:53:42.524128 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9690 16:53:42.527361 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9691 16:53:42.530265 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9692 16:53:42.536807 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9693 16:53:42.539907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9694 16:53:42.546879 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9695 16:53:42.549755 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9696 16:53:42.556287 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9697 16:53:42.560091 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9698 16:53:42.562950 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9699 16:53:42.569849 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9700 16:53:42.572951 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9701 16:53:42.576551 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9702 16:53:42.579350 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9703 16:53:42.586258 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9704 16:53:42.589734 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9705 16:53:42.592686 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9706 16:53:42.599527 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9707 16:53:42.602661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9708 16:53:42.605715 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9709 16:53:42.612776 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9710 16:53:42.616275 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9711 16:53:42.622304 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9712 16:53:42.626160 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9713 16:53:42.629042 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9714 16:53:42.635503 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9715 16:53:42.638883 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9716 16:53:42.642008 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9717 16:53:42.648966 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9718 16:53:42.651723 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9719 16:53:42.658776 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9720 16:53:42.662329 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9721 16:53:42.665302 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9722 16:53:42.671641 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9723 16:53:42.675448 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9724 16:53:42.678144 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9725 16:53:42.684603 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9726 16:53:42.688022 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9727 16:53:42.694902 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9728 16:53:42.697657 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9729 16:53:42.701289 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9730 16:53:42.707776 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9731 16:53:42.711213 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9732 16:53:42.718043 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9733 16:53:42.721380 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9734 16:53:42.724374 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9735 16:53:42.730723 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9736 16:53:42.734483 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9737 16:53:42.737369 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9738 16:53:42.743695 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9739 16:53:42.747400 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9740 16:53:42.750465 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9741 16:53:42.753881 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9742 16:53:42.760807 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9743 16:53:42.763550 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9744 16:53:42.766997 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9745 16:53:42.770218 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9746 16:53:42.777122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9747 16:53:42.780338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9748 16:53:42.783268 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9749 16:53:42.786985 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9750 16:53:42.793326 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9751 16:53:42.797076 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9752 16:53:42.800157 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9753 16:53:42.806928 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9754 16:53:42.810083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9755 16:53:42.816683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9756 16:53:42.819996 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9757 16:53:42.826550 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9758 16:53:42.829596 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9759 16:53:42.832760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9760 16:53:42.839364 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9761 16:53:42.842511 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9762 16:53:42.849280 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9763 16:53:42.852458 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9764 16:53:42.859019 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9765 16:53:42.862023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9766 16:53:42.865333 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9767 16:53:42.872033 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9768 16:53:42.875541 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9769 16:53:42.882024 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9770 16:53:42.885270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9771 16:53:42.888353 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9772 16:53:42.895202 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9773 16:53:42.898296 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9774 16:53:42.904913 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9775 16:53:42.908152 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9776 16:53:42.915113 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9777 16:53:42.918088 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9778 16:53:42.921206 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9779 16:53:42.928100 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9780 16:53:42.931115 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9781 16:53:42.938018 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9782 16:53:42.940989 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9783 16:53:42.944712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9784 16:53:42.951146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9785 16:53:42.954391 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9786 16:53:42.961045 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9787 16:53:42.964107 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9788 16:53:42.970681 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9789 16:53:42.974506 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9790 16:53:42.980667 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9791 16:53:42.984387 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9792 16:53:42.988017 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9793 16:53:42.993845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9794 16:53:42.997448 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9795 16:53:43.003758 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9796 16:53:43.007291 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9797 16:53:43.013702 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9798 16:53:43.017416 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9799 16:53:43.020153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9800 16:53:43.027074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9801 16:53:43.030172 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9802 16:53:43.036474 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9803 16:53:43.040260 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9804 16:53:43.043308 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9805 16:53:43.050413 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9806 16:53:43.053569 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9807 16:53:43.059825 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9808 16:53:43.063617 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9809 16:53:43.069723 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9810 16:53:43.072832 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9811 16:53:43.076254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9812 16:53:43.083125 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9813 16:53:43.086246 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9814 16:53:43.092877 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9815 16:53:43.096220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9816 16:53:43.099418 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9817 16:53:43.106454 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9818 16:53:43.109437 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9819 16:53:43.116260 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9820 16:53:43.119232 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9821 16:53:43.126125 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9822 16:53:43.129167 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9823 16:53:43.132648 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9824 16:53:43.138929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9825 16:53:43.142801 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9826 16:53:43.148604 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9827 16:53:43.152182 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9828 16:53:43.158707 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9829 16:53:43.161903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9830 16:53:43.168807 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9831 16:53:43.171761 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9832 16:53:43.175612 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9833 16:53:43.181710 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9834 16:53:43.185182 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9835 16:53:43.191456 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9836 16:53:43.195042 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9837 16:53:43.201340 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9838 16:53:43.204868 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9839 16:53:43.208116 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9840 16:53:43.214891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9841 16:53:43.217632 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9842 16:53:43.224341 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9843 16:53:43.227443 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9844 16:53:43.234503 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9845 16:53:43.237399 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9846 16:53:43.244113 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9847 16:53:43.247084 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9848 16:53:43.254033 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9849 16:53:43.257468 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9850 16:53:43.263763 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9851 16:53:43.267034 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9852 16:53:43.273345 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9853 16:53:43.276963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9854 16:53:43.280051 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9855 16:53:43.287083 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9856 16:53:43.290222 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9857 16:53:43.296416 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9858 16:53:43.300154 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9859 16:53:43.306236 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9860 16:53:43.309430 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9861 16:53:43.316256 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9862 16:53:43.320018 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9863 16:53:43.322771 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9864 16:53:43.329558 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9865 16:53:43.333081 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9866 16:53:43.339742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9867 16:53:43.343066 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9868 16:53:43.349726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9869 16:53:43.352317 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9870 16:53:43.359822 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9871 16:53:43.363016 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9872 16:53:43.365928 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9873 16:53:43.372288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9874 16:53:43.375356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9875 16:53:43.382597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9876 16:53:43.385570 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9877 16:53:43.392483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9878 16:53:43.395749 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9879 16:53:43.402318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9880 16:53:43.405133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9881 16:53:43.411907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9882 16:53:43.415509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9883 16:53:43.421973 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9884 16:53:43.425464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9885 16:53:43.431669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9886 16:53:43.434552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9887 16:53:43.441800 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9888 16:53:43.444958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9889 16:53:43.451299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9890 16:53:43.454752 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9891 16:53:43.462066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9892 16:53:43.464543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9893 16:53:43.471235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9894 16:53:43.474598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9895 16:53:43.480826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9896 16:53:43.484419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9897 16:53:43.491205 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9898 16:53:43.494579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9899 16:53:43.501316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9900 16:53:43.504589 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9901 16:53:43.510488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9902 16:53:43.514413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9903 16:53:43.520378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9904 16:53:43.524208 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9905 16:53:43.527386 INFO: [APUAPC] vio 0
9906 16:53:43.530702 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9907 16:53:43.537176 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9908 16:53:43.540069 INFO: [APUAPC] D0_APC_0: 0x400510
9909 16:53:43.540495 INFO: [APUAPC] D0_APC_1: 0x0
9910 16:53:43.543698 INFO: [APUAPC] D0_APC_2: 0x1540
9911 16:53:43.547309 INFO: [APUAPC] D0_APC_3: 0x0
9912 16:53:43.550821 INFO: [APUAPC] D1_APC_0: 0xffffffff
9913 16:53:43.553372 INFO: [APUAPC] D1_APC_1: 0xffffffff
9914 16:53:43.557117 INFO: [APUAPC] D1_APC_2: 0x3fffff
9915 16:53:43.560192 INFO: [APUAPC] D1_APC_3: 0x0
9916 16:53:43.563652 INFO: [APUAPC] D2_APC_0: 0xffffffff
9917 16:53:43.567087 INFO: [APUAPC] D2_APC_1: 0xffffffff
9918 16:53:43.570102 INFO: [APUAPC] D2_APC_2: 0x3fffff
9919 16:53:43.573202 INFO: [APUAPC] D2_APC_3: 0x0
9920 16:53:43.576318 INFO: [APUAPC] D3_APC_0: 0xffffffff
9921 16:53:43.580161 INFO: [APUAPC] D3_APC_1: 0xffffffff
9922 16:53:43.583375 INFO: [APUAPC] D3_APC_2: 0x3fffff
9923 16:53:43.586761 INFO: [APUAPC] D3_APC_3: 0x0
9924 16:53:43.590310 INFO: [APUAPC] D4_APC_0: 0xffffffff
9925 16:53:43.593292 INFO: [APUAPC] D4_APC_1: 0xffffffff
9926 16:53:43.596691 INFO: [APUAPC] D4_APC_2: 0x3fffff
9927 16:53:43.599744 INFO: [APUAPC] D4_APC_3: 0x0
9928 16:53:43.603074 INFO: [APUAPC] D5_APC_0: 0xffffffff
9929 16:53:43.606073 INFO: [APUAPC] D5_APC_1: 0xffffffff
9930 16:53:43.609306 INFO: [APUAPC] D5_APC_2: 0x3fffff
9931 16:53:43.612961 INFO: [APUAPC] D5_APC_3: 0x0
9932 16:53:43.615919 INFO: [APUAPC] D6_APC_0: 0xffffffff
9933 16:53:43.619248 INFO: [APUAPC] D6_APC_1: 0xffffffff
9934 16:53:43.622345 INFO: [APUAPC] D6_APC_2: 0x3fffff
9935 16:53:43.625878 INFO: [APUAPC] D6_APC_3: 0x0
9936 16:53:43.628866 INFO: [APUAPC] D7_APC_0: 0xffffffff
9937 16:53:43.632829 INFO: [APUAPC] D7_APC_1: 0xffffffff
9938 16:53:43.635951 INFO: [APUAPC] D7_APC_2: 0x3fffff
9939 16:53:43.639314 INFO: [APUAPC] D7_APC_3: 0x0
9940 16:53:43.642622 INFO: [APUAPC] D8_APC_0: 0xffffffff
9941 16:53:43.645981 INFO: [APUAPC] D8_APC_1: 0xffffffff
9942 16:53:43.649152 INFO: [APUAPC] D8_APC_2: 0x3fffff
9943 16:53:43.652407 INFO: [APUAPC] D8_APC_3: 0x0
9944 16:53:43.655332 INFO: [APUAPC] D9_APC_0: 0xffffffff
9945 16:53:43.658758 INFO: [APUAPC] D9_APC_1: 0xffffffff
9946 16:53:43.662143 INFO: [APUAPC] D9_APC_2: 0x3fffff
9947 16:53:43.665596 INFO: [APUAPC] D9_APC_3: 0x0
9948 16:53:43.668484 INFO: [APUAPC] D10_APC_0: 0xffffffff
9949 16:53:43.672358 INFO: [APUAPC] D10_APC_1: 0xffffffff
9950 16:53:43.675811 INFO: [APUAPC] D10_APC_2: 0x3fffff
9951 16:53:43.679003 INFO: [APUAPC] D10_APC_3: 0x0
9952 16:53:43.681695 INFO: [APUAPC] D11_APC_0: 0xffffffff
9953 16:53:43.685264 INFO: [APUAPC] D11_APC_1: 0xffffffff
9954 16:53:43.688500 INFO: [APUAPC] D11_APC_2: 0x3fffff
9955 16:53:43.691658 INFO: [APUAPC] D11_APC_3: 0x0
9956 16:53:43.695564 INFO: [APUAPC] D12_APC_0: 0xffffffff
9957 16:53:43.698219 INFO: [APUAPC] D12_APC_1: 0xffffffff
9958 16:53:43.701701 INFO: [APUAPC] D12_APC_2: 0x3fffff
9959 16:53:43.705311 INFO: [APUAPC] D12_APC_3: 0x0
9960 16:53:43.708131 INFO: [APUAPC] D13_APC_0: 0xffffffff
9961 16:53:43.711423 INFO: [APUAPC] D13_APC_1: 0xffffffff
9962 16:53:43.715266 INFO: [APUAPC] D13_APC_2: 0x3fffff
9963 16:53:43.718200 INFO: [APUAPC] D13_APC_3: 0x0
9964 16:53:43.721500 INFO: [APUAPC] D14_APC_0: 0xffffffff
9965 16:53:43.724718 INFO: [APUAPC] D14_APC_1: 0xffffffff
9966 16:53:43.728147 INFO: [APUAPC] D14_APC_2: 0x3fffff
9967 16:53:43.731098 INFO: [APUAPC] D14_APC_3: 0x0
9968 16:53:43.734954 INFO: [APUAPC] D15_APC_0: 0xffffffff
9969 16:53:43.738220 INFO: [APUAPC] D15_APC_1: 0xffffffff
9970 16:53:43.741021 INFO: [APUAPC] D15_APC_2: 0x3fffff
9971 16:53:43.745115 INFO: [APUAPC] D15_APC_3: 0x0
9972 16:53:43.748025 INFO: [APUAPC] APC_CON: 0x4
9973 16:53:43.751327 INFO: [NOCDAPC] D0_APC_0: 0x0
9974 16:53:43.754458 INFO: [NOCDAPC] D0_APC_1: 0x0
9975 16:53:43.757998 INFO: [NOCDAPC] D1_APC_0: 0x0
9976 16:53:43.761527 INFO: [NOCDAPC] D1_APC_1: 0xfff
9977 16:53:43.762083 INFO: [NOCDAPC] D2_APC_0: 0x0
9978 16:53:43.764080 INFO: [NOCDAPC] D2_APC_1: 0xfff
9979 16:53:43.767640 INFO: [NOCDAPC] D3_APC_0: 0x0
9980 16:53:43.771057 INFO: [NOCDAPC] D3_APC_1: 0xfff
9981 16:53:43.774049 INFO: [NOCDAPC] D4_APC_0: 0x0
9982 16:53:43.777572 INFO: [NOCDAPC] D4_APC_1: 0xfff
9983 16:53:43.780719 INFO: [NOCDAPC] D5_APC_0: 0x0
9984 16:53:43.783896 INFO: [NOCDAPC] D5_APC_1: 0xfff
9985 16:53:43.787028 INFO: [NOCDAPC] D6_APC_0: 0x0
9986 16:53:43.790720 INFO: [NOCDAPC] D6_APC_1: 0xfff
9987 16:53:43.793702 INFO: [NOCDAPC] D7_APC_0: 0x0
9988 16:53:43.797272 INFO: [NOCDAPC] D7_APC_1: 0xfff
9989 16:53:43.797800 INFO: [NOCDAPC] D8_APC_0: 0x0
9990 16:53:43.800682 INFO: [NOCDAPC] D8_APC_1: 0xfff
9991 16:53:43.803903 INFO: [NOCDAPC] D9_APC_0: 0x0
9992 16:53:43.807221 INFO: [NOCDAPC] D9_APC_1: 0xfff
9993 16:53:43.810264 INFO: [NOCDAPC] D10_APC_0: 0x0
9994 16:53:43.813550 INFO: [NOCDAPC] D10_APC_1: 0xfff
9995 16:53:43.817427 INFO: [NOCDAPC] D11_APC_0: 0x0
9996 16:53:43.820367 INFO: [NOCDAPC] D11_APC_1: 0xfff
9997 16:53:43.823680 INFO: [NOCDAPC] D12_APC_0: 0x0
9998 16:53:43.826810 INFO: [NOCDAPC] D12_APC_1: 0xfff
9999 16:53:43.829769 INFO: [NOCDAPC] D13_APC_0: 0x0
10000 16:53:43.832978 INFO: [NOCDAPC] D13_APC_1: 0xfff
10001 16:53:43.836545 INFO: [NOCDAPC] D14_APC_0: 0x0
10002 16:53:43.839763 INFO: [NOCDAPC] D14_APC_1: 0xfff
10003 16:53:43.843177 INFO: [NOCDAPC] D15_APC_0: 0x0
10004 16:53:43.846706 INFO: [NOCDAPC] D15_APC_1: 0xfff
10005 16:53:43.847277 INFO: [NOCDAPC] APC_CON: 0x4
10006 16:53:43.849776 INFO: [APUAPC] set_apusys_apc done
10007 16:53:43.852934 INFO: [DEVAPC] devapc_init done
10008 16:53:43.859777 INFO: GICv3 without legacy support detected.
10009 16:53:43.863222 INFO: ARM GICv3 driver initialized in EL3
10010 16:53:43.866352 INFO: Maximum SPI INTID supported: 639
10011 16:53:43.869592 INFO: BL31: Initializing runtime services
10012 16:53:43.875941 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10013 16:53:43.878860 INFO: SPM: enable CPC mode
10014 16:53:43.882691 INFO: mcdi ready for mcusys-off-idle and system suspend
10015 16:53:43.888846 INFO: BL31: Preparing for EL3 exit to normal world
10016 16:53:43.892032 INFO: Entry point address = 0x80000000
10017 16:53:43.895759 INFO: SPSR = 0x8
10018 16:53:43.900032
10019 16:53:43.900557
10020 16:53:43.900894
10021 16:53:43.903134 Starting depthcharge on Spherion...
10022 16:53:43.903558
10023 16:53:43.903942 Wipe memory regions:
10024 16:53:43.904259
10025 16:53:43.906743 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10026 16:53:43.907267 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10027 16:53:43.907717 Setting prompt string to ['asurada:']
10028 16:53:43.908129 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10029 16:53:43.908784 [0x00000040000000, 0x00000054600000)
10030 16:53:44.029103
10031 16:53:44.029787 [0x00000054660000, 0x00000080000000)
10032 16:53:44.289447
10033 16:53:44.289940 [0x000000821a7280, 0x000000ffe64000)
10034 16:53:45.033616
10035 16:53:45.033775 [0x00000100000000, 0x00000240000000)
10036 16:53:46.924634
10037 16:53:46.928060 Initializing XHCI USB controller at 0x11200000.
10038 16:53:47.965801
10039 16:53:47.969236 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10040 16:53:47.969676
10041 16:53:47.970015
10042 16:53:47.970332
10043 16:53:47.971082 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10045 16:53:48.072322 asurada: tftpboot 192.168.201.1 10576339/tftp-deploy-7o0p90sc/kernel/image.itb 10576339/tftp-deploy-7o0p90sc/kernel/cmdline
10046 16:53:48.072944 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10047 16:53:48.073482 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10048 16:53:48.078032 tftpboot 192.168.201.1 10576339/tftp-deploy-7o0p90sc/kernel/image.itp-deploy-7o0p90sc/kernel/cmdline
10049 16:53:48.078466
10050 16:53:48.078800 Waiting for link
10051 16:53:48.239034
10052 16:53:48.239566 R8152: Initializing
10053 16:53:48.239959
10054 16:53:48.241635 Version 6 (ocp_data = 5c30)
10055 16:53:48.242062
10056 16:53:48.245316 R8152: Done initializing
10057 16:53:48.245743
10058 16:53:48.246077 Adding net device
10059 16:53:50.145661
10060 16:53:50.146192 done.
10061 16:53:50.146535
10062 16:53:50.146852 MAC: 00:24:32:30:78:ff
10063 16:53:50.147209
10064 16:53:50.148447 Sending DHCP discover... done.
10065 16:53:50.148873
10066 16:53:59.310409 Waiting for reply... done.
10067 16:53:59.310576
10068 16:53:59.310674 Sending DHCP request... done.
10069 16:53:59.313227
10070 16:53:59.317955 Waiting for reply... done.
10071 16:53:59.318034
10072 16:53:59.318096 My ip is 192.168.201.21
10073 16:53:59.318156
10074 16:53:59.321015 The DHCP server ip is 192.168.201.1
10075 16:53:59.321127
10076 16:53:59.327970 TFTP server IP predefined by user: 192.168.201.1
10077 16:53:59.328055
10078 16:53:59.334369 Bootfile predefined by user: 10576339/tftp-deploy-7o0p90sc/kernel/image.itb
10079 16:53:59.334484
10080 16:53:59.337594 Sending tftp read request... done.
10081 16:53:59.337672
10082 16:53:59.341314 Waiting for the transfer...
10083 16:53:59.341389
10084 16:53:59.892285 00000000 ################################################################
10085 16:53:59.892460
10086 16:54:00.547898 00080000 ################################################################
10087 16:54:00.548042
10088 16:54:01.164013 00100000 ################################################################
10089 16:54:01.164152
10090 16:54:01.750196 00180000 ################################################################
10091 16:54:01.750336
10092 16:54:02.306310 00200000 ################################################################
10093 16:54:02.306455
10094 16:54:02.872048 00280000 ################################################################
10095 16:54:02.872192
10096 16:54:03.414418 00300000 ################################################################
10097 16:54:03.414563
10098 16:54:03.969752 00380000 ################################################################
10099 16:54:03.969893
10100 16:54:04.545676 00400000 ################################################################
10101 16:54:04.545812
10102 16:54:05.093931 00480000 ################################################################
10103 16:54:05.094062
10104 16:54:05.650998 00500000 ################################################################
10105 16:54:05.651137
10106 16:54:06.199141 00580000 ################################################################
10107 16:54:06.199305
10108 16:54:06.744817 00600000 ################################################################
10109 16:54:06.744956
10110 16:54:07.289687 00680000 ################################################################
10111 16:54:07.289851
10112 16:54:07.866504 00700000 ################################################################
10113 16:54:07.866640
10114 16:54:08.439844 00780000 ################################################################
10115 16:54:08.439978
10116 16:54:09.017042 00800000 ################################################################
10117 16:54:09.017178
10118 16:54:09.562425 00880000 ################################################################
10119 16:54:09.562559
10120 16:54:10.121671 00900000 ################################################################
10121 16:54:10.121835
10122 16:54:10.677595 00980000 ################################################################
10123 16:54:10.677727
10124 16:54:11.223111 00a00000 ################################################################
10125 16:54:11.223253
10126 16:54:11.764368 00a80000 ################################################################
10127 16:54:11.764510
10128 16:54:12.309302 00b00000 ################################################################
10129 16:54:12.309447
10130 16:54:12.870796 00b80000 ################################################################
10131 16:54:12.870928
10132 16:54:13.439286 00c00000 ################################################################
10133 16:54:13.439426
10134 16:54:13.985476 00c80000 ################################################################
10135 16:54:13.985619
10136 16:54:14.528779 00d00000 ################################################################
10137 16:54:14.528923
10138 16:54:15.088071 00d80000 ################################################################
10139 16:54:15.088209
10140 16:54:15.642833 00e00000 ################################################################
10141 16:54:15.642999
10142 16:54:16.168803 00e80000 ################################################################
10143 16:54:16.168945
10144 16:54:16.710424 00f00000 ################################################################
10145 16:54:16.710567
10146 16:54:17.266648 00f80000 ################################################################
10147 16:54:17.266786
10148 16:54:17.892440 01000000 ################################################################
10149 16:54:17.892607
10150 16:54:18.525238 01080000 ################################################################
10151 16:54:18.525795
10152 16:54:19.150601 01100000 ################################################################
10153 16:54:19.150758
10154 16:54:19.780385 01180000 ################################################################
10155 16:54:19.781149
10156 16:54:20.433266 01200000 ################################################################
10157 16:54:20.433782
10158 16:54:21.147046 01280000 ################################################################
10159 16:54:21.147568
10160 16:54:21.882845 01300000 ################################################################
10161 16:54:21.883423
10162 16:54:22.587897 01380000 ################################################################
10163 16:54:22.588515
10164 16:54:23.263325 01400000 ################################################################
10165 16:54:23.263481
10166 16:54:23.906815 01480000 ################################################################
10167 16:54:23.907029
10168 16:54:24.582919 01500000 ################################################################
10169 16:54:24.583062
10170 16:54:25.266030 01580000 ################################################################
10171 16:54:25.266605
10172 16:54:25.985992 01600000 ################################################################
10173 16:54:25.986615
10174 16:54:26.701778 01680000 ################################################################
10175 16:54:26.702392
10176 16:54:27.383076 01700000 ################################################################
10177 16:54:27.383705
10178 16:54:28.051381 01780000 ################################################################
10179 16:54:28.051521
10180 16:54:28.739930 01800000 ################################################################
10181 16:54:28.740071
10182 16:54:29.344090 01880000 ################################################################
10183 16:54:29.344653
10184 16:54:30.054805 01900000 ################################################################
10185 16:54:30.055424
10186 16:54:30.748940 01980000 ################################################################
10187 16:54:30.749528
10188 16:54:31.450948 01a00000 ################################################################
10189 16:54:31.451480
10190 16:54:32.075545 01a80000 ################################################################
10191 16:54:32.076088
10192 16:54:32.779735 01b00000 ################################################################
10193 16:54:32.780277
10194 16:54:33.494775 01b80000 ################################################################
10195 16:54:33.495295
10196 16:54:34.123819 01c00000 ################################################################
10197 16:54:34.124332
10198 16:54:34.777818 01c80000 ################################################################
10199 16:54:34.778390
10200 16:54:35.443273 01d00000 ################################################################
10201 16:54:35.443405
10202 16:54:36.090333 01d80000 ################################################################
10203 16:54:36.090941
10204 16:54:36.758547 01e00000 ################################################################
10205 16:54:36.758700
10206 16:54:37.396005 01e80000 ################################################################
10207 16:54:37.396593
10208 16:54:38.106089 01f00000 ################################################################
10209 16:54:38.106608
10210 16:54:38.767870 01f80000 ################################################################
10211 16:54:38.768519
10212 16:54:39.491219 02000000 ################################################################
10213 16:54:39.491772
10214 16:54:40.189868 02080000 ################################################################
10215 16:54:40.190504
10216 16:54:40.902274 02100000 ################################################################
10217 16:54:40.902800
10218 16:54:41.567240 02180000 ################################################################
10219 16:54:41.567420
10220 16:54:42.159457 02200000 ################################################################
10221 16:54:42.160055
10222 16:54:42.800409 02280000 ################################################################
10223 16:54:42.800933
10224 16:54:43.480719 02300000 ################################################################
10225 16:54:43.481238
10226 16:54:44.183626 02380000 ################################################################
10227 16:54:44.184164
10228 16:54:44.884698 02400000 ################################################################
10229 16:54:44.885368
10230 16:54:45.604727 02480000 ################################################################
10231 16:54:45.605374
10232 16:54:46.238363 02500000 ################################################################
10233 16:54:46.238967
10234 16:54:46.946925 02580000 ################################################################
10235 16:54:46.947526
10236 16:54:47.515425 02600000 ################################################################
10237 16:54:47.515614
10238 16:54:48.100317 02680000 ################################################################
10239 16:54:48.100467
10240 16:54:48.678710 02700000 ################################################################
10241 16:54:48.678863
10242 16:54:49.238191 02780000 ################################################################
10243 16:54:49.238348
10244 16:54:49.786056 02800000 ################################################################
10245 16:54:49.786244
10246 16:54:50.336293 02880000 ################################################################
10247 16:54:50.336490
10248 16:54:50.907069 02900000 ################################################################
10249 16:54:50.907218
10250 16:54:51.463748 02980000 ################################################################
10251 16:54:51.463901
10252 16:54:52.021860 02a00000 ################################################################
10253 16:54:52.022009
10254 16:54:52.598970 02a80000 ################################################################
10255 16:54:52.599112
10256 16:54:53.184930 02b00000 ################################################################
10257 16:54:53.185081
10258 16:54:53.749389 02b80000 ################################################################
10259 16:54:53.749535
10260 16:54:54.315343 02c00000 ################################################################
10261 16:54:54.315510
10262 16:54:54.884868 02c80000 ################################################################
10263 16:54:54.885012
10264 16:54:55.428602 02d00000 ################################################################
10265 16:54:55.428751
10266 16:54:55.996108 02d80000 ################################################################
10267 16:54:55.996334
10268 16:54:56.538047 02e00000 ################################################################
10269 16:54:56.538208
10270 16:54:57.084621 02e80000 ################################################################
10271 16:54:57.084794
10272 16:54:57.640202 02f00000 ################################################################
10273 16:54:57.640353
10274 16:54:58.186973 02f80000 ################################################################
10275 16:54:58.187127
10276 16:54:58.735502 03000000 ################################################################
10277 16:54:58.735674
10278 16:54:59.283517 03080000 ################################################################
10279 16:54:59.283699
10280 16:54:59.839466 03100000 ################################################################
10281 16:54:59.839637
10282 16:55:00.390139 03180000 ################################################################
10283 16:55:00.390300
10284 16:55:00.976538 03200000 ################################################################
10285 16:55:00.976736
10286 16:55:01.570285 03280000 ################################################################
10287 16:55:01.570438
10288 16:55:02.139510 03300000 ################################################################
10289 16:55:02.139698
10290 16:55:02.709568 03380000 ################################################################
10291 16:55:02.709714
10292 16:55:03.272557 03400000 ################################################################
10293 16:55:03.272700
10294 16:55:03.850293 03480000 ################################################################
10295 16:55:03.850435
10296 16:55:04.410740 03500000 ################################################################
10297 16:55:04.410903
10298 16:55:04.965793 03580000 ################################################################
10299 16:55:04.965956
10300 16:55:05.527290 03600000 ################################################################
10301 16:55:05.527435
10302 16:55:06.099875 03680000 ################################################################
10303 16:55:06.100027
10304 16:55:06.684840 03700000 ################################################################
10305 16:55:06.685004
10306 16:55:07.215575 03780000 ################################################################
10307 16:55:07.215764
10308 16:55:07.782875 03800000 ################################################################
10309 16:55:07.783038
10310 16:55:08.347051 03880000 ################################################################
10311 16:55:08.347201
10312 16:55:08.920540 03900000 ################################################################
10313 16:55:08.920683
10314 16:55:09.479038 03980000 ################################################################
10315 16:55:09.479184
10316 16:55:10.045899 03a00000 ################################################################
10317 16:55:10.046051
10318 16:55:10.595923 03a80000 ################################################################
10319 16:55:10.596072
10320 16:55:11.166966 03b00000 ################################################################
10321 16:55:11.167112
10322 16:55:11.743261 03b80000 ################################################################
10323 16:55:11.743416
10324 16:55:12.312774 03c00000 ################################################################
10325 16:55:12.312934
10326 16:55:12.888043 03c80000 ################################################################
10327 16:55:12.888188
10328 16:55:13.462195 03d00000 ################################################################
10329 16:55:13.462341
10330 16:55:14.048336 03d80000 ################################################################
10331 16:55:14.048488
10332 16:55:14.628166 03e00000 ################################################################
10333 16:55:14.628385
10334 16:55:15.344872 03e80000 ################################################################
10335 16:55:15.345413
10336 16:55:15.931352 03f00000 #################################################### done.
10337 16:55:15.931893
10338 16:55:15.934358 The bootfile was 66484902 bytes long.
10339 16:55:15.934796
10340 16:55:15.937636 Sending tftp read request... done.
10341 16:55:15.938063
10342 16:55:15.940467 Waiting for the transfer...
10343 16:55:15.940900
10344 16:55:15.941238 00000000 # done.
10345 16:55:15.941562
10346 16:55:15.947291 Command line loaded dynamically from TFTP file: 10576339/tftp-deploy-7o0p90sc/kernel/cmdline
10347 16:55:15.950387
10348 16:55:15.960995 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10349 16:55:15.961531
10350 16:55:15.961874 Loading FIT.
10351 16:55:15.962192
10352 16:55:15.963678 Image ramdisk-1 has 56352471 bytes.
10353 16:55:15.964065
10354 16:55:15.967385 Image fdt-1 has 46924 bytes.
10355 16:55:15.968026
10356 16:55:15.970365 Image kernel-1 has 10083474 bytes.
10357 16:55:15.970792
10358 16:55:15.980516 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10359 16:55:15.981032
10360 16:55:15.997139 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10361 16:55:15.997695
10362 16:55:16.002931 Choosing best match conf-1 for compat google,spherion-rev2.
10363 16:55:16.003355
10364 16:55:16.010385 Connected to device vid:did:rid of 1ae0:0028:00
10365 16:55:16.017830
10366 16:55:16.020765 tpm_get_response: command 0x17b, return code 0x0
10367 16:55:16.021192
10368 16:55:16.023887 ec_init: CrosEC protocol v3 supported (256, 248)
10369 16:55:16.028388
10370 16:55:16.031683 tpm_cleanup: add release locality here.
10371 16:55:16.032228
10372 16:55:16.032626 Shutting down all USB controllers.
10373 16:55:16.034945
10374 16:55:16.035366 Removing current net device
10375 16:55:16.035751
10376 16:55:16.041354 Exiting depthcharge with code 4 at timestamp: 121418606
10377 16:55:16.041896
10378 16:55:16.044281 LZMA decompressing kernel-1 to 0x821a6718
10379 16:55:16.044728
10380 16:55:16.047961 LZMA decompressing kernel-1 to 0x40000000
10381 16:55:17.314754
10382 16:55:17.315321 jumping to kernel
10383 16:55:17.317365 end: 2.2.4 bootloader-commands (duration 00:01:33) [common]
10384 16:55:17.317862 start: 2.2.5 auto-login-action (timeout 00:02:52) [common]
10385 16:55:17.318323 Setting prompt string to ['Linux version [0-9]']
10386 16:55:17.318701 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10387 16:55:17.319096 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10388 16:55:17.396790
10389 16:55:17.400588 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10390 16:55:17.404178 start: 2.2.5.1 login-action (timeout 00:02:52) [common]
10391 16:55:17.404633 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10392 16:55:17.405083 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10393 16:55:17.405470 Using line separator: #'\n'#
10394 16:55:17.405791 No login prompt set.
10395 16:55:17.406110 Parsing kernel messages
10396 16:55:17.406402 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10397 16:55:17.406929 [login-action] Waiting for messages, (timeout 00:02:52)
10398 16:55:17.423339 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10399 16:55:17.426425 [ 0.000000] random: crng init done
10400 16:55:17.433463 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10401 16:55:17.434030 [ 0.000000] efi: UEFI not found.
10402 16:55:17.443319 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10403 16:55:17.450085 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10404 16:55:17.459673 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10405 16:55:17.469497 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10406 16:55:17.476407 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10407 16:55:17.482412 [ 0.000000] printk: bootconsole [mtk8250] enabled
10408 16:55:17.489056 [ 0.000000] NUMA: No NUMA configuration found
10409 16:55:17.495963 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10410 16:55:17.498824 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcca00-0x23efcefff]
10411 16:55:17.502628 [ 0.000000] Zone ranges:
10412 16:55:17.508814 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10413 16:55:17.512580 [ 0.000000] DMA32 empty
10414 16:55:17.518592 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10415 16:55:17.522212 [ 0.000000] Movable zone start for each node
10416 16:55:17.525275 [ 0.000000] Early memory node ranges
10417 16:55:17.531711 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10418 16:55:17.538719 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10419 16:55:17.545515 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10420 16:55:17.551485 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10421 16:55:17.558605 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10422 16:55:17.565118 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10423 16:55:17.620726 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10424 16:55:17.627409 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10425 16:55:17.634150 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10426 16:55:17.637230 [ 0.000000] psci: probing for conduit method from DT.
10427 16:55:17.643712 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10428 16:55:17.647264 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10429 16:55:17.653412 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10430 16:55:17.657079 [ 0.000000] psci: SMC Calling Convention v1.2
10431 16:55:17.663452 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10432 16:55:17.666840 [ 0.000000] Detected VIPT I-cache on CPU0
10433 16:55:17.673111 [ 0.000000] CPU features: detected: GIC system register CPU interface
10434 16:55:17.679665 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10435 16:55:17.686458 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10436 16:55:17.692893 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10437 16:55:17.702680 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10438 16:55:17.709507 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10439 16:55:17.712517 [ 0.000000] alternatives: applying boot alternatives
10440 16:55:17.719869 [ 0.000000] Fallback order for Node 0: 0
10441 16:55:17.726090 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10442 16:55:17.729931 [ 0.000000] Policy zone: Normal
10443 16:55:17.742963 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10444 16:55:17.752776 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10445 16:55:17.762667 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10446 16:55:17.772852 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10447 16:55:17.778898 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10448 16:55:17.782303 <6>[ 0.000000] software IO TLB: area num 8.
10449 16:55:17.839439 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10450 16:55:17.988635 <6>[ 0.000000] Memory: 7917900K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434868K reserved, 32768K cma-reserved)
10451 16:55:17.995325 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10452 16:55:18.001461 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10453 16:55:18.004787 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10454 16:55:18.011250 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10455 16:55:18.017927 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10456 16:55:18.021151 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10457 16:55:18.031229 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10458 16:55:18.037880 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10459 16:55:18.044142 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10460 16:55:18.050949 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10461 16:55:18.054106 <6>[ 0.000000] GICv3: 608 SPIs implemented
10462 16:55:18.057998 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10463 16:55:18.064288 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10464 16:55:18.067622 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10465 16:55:18.074186 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10466 16:55:18.087210 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10467 16:55:18.100280 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10468 16:55:18.106792 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10469 16:55:18.115136 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10470 16:55:18.128217 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10471 16:55:18.135110 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10472 16:55:18.141787 <6>[ 0.009178] Console: colour dummy device 80x25
10473 16:55:18.151638 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10474 16:55:18.157915 <6>[ 0.024346] pid_max: default: 32768 minimum: 301
10475 16:55:18.161570 <6>[ 0.029219] LSM: Security Framework initializing
10476 16:55:18.167673 <6>[ 0.034188] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10477 16:55:18.177790 <6>[ 0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10478 16:55:18.187838 <6>[ 0.051484] cblist_init_generic: Setting adjustable number of callback queues.
10479 16:55:18.194373 <6>[ 0.058938] cblist_init_generic: Setting shift to 3 and lim to 1.
10480 16:55:18.197806 <6>[ 0.065277] cblist_init_generic: Setting shift to 3 and lim to 1.
10481 16:55:18.204049 <6>[ 0.071684] rcu: Hierarchical SRCU implementation.
10482 16:55:18.210883 <6>[ 0.076697] rcu: Max phase no-delay instances is 1000.
10483 16:55:18.217495 <6>[ 0.083749] EFI services will not be available.
10484 16:55:18.220978 <6>[ 0.088723] smp: Bringing up secondary CPUs ...
10485 16:55:18.228638 <6>[ 0.093776] Detected VIPT I-cache on CPU1
10486 16:55:18.235367 <6>[ 0.093848] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10487 16:55:18.241608 <6>[ 0.093877] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10488 16:55:18.245213 <6>[ 0.094212] Detected VIPT I-cache on CPU2
10489 16:55:18.254919 <6>[ 0.094262] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10490 16:55:18.262098 <6>[ 0.094278] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10491 16:55:18.264933 <6>[ 0.094533] Detected VIPT I-cache on CPU3
10492 16:55:18.271741 <6>[ 0.094580] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10493 16:55:18.277935 <6>[ 0.094594] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10494 16:55:18.281679 <6>[ 0.094898] CPU features: detected: Spectre-v4
10495 16:55:18.287845 <6>[ 0.094904] CPU features: detected: Spectre-BHB
10496 16:55:18.291571 <6>[ 0.094910] Detected PIPT I-cache on CPU4
10497 16:55:18.298123 <6>[ 0.094968] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10498 16:55:18.304255 <6>[ 0.094985] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10499 16:55:18.310915 <6>[ 0.095279] Detected PIPT I-cache on CPU5
10500 16:55:18.317542 <6>[ 0.095345] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10501 16:55:18.324025 <6>[ 0.095362] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10502 16:55:18.327325 <6>[ 0.095643] Detected PIPT I-cache on CPU6
10503 16:55:18.333766 <6>[ 0.095709] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10504 16:55:18.343637 <6>[ 0.095726] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10505 16:55:18.347409 <6>[ 0.096022] Detected PIPT I-cache on CPU7
10506 16:55:18.353945 <6>[ 0.096088] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10507 16:55:18.360087 <6>[ 0.096104] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10508 16:55:18.363762 <6>[ 0.096151] smp: Brought up 1 node, 8 CPUs
10509 16:55:18.370426 <6>[ 0.237473] SMP: Total of 8 processors activated.
10510 16:55:18.376959 <6>[ 0.242394] CPU features: detected: 32-bit EL0 Support
10511 16:55:18.383673 <6>[ 0.247789] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10512 16:55:18.389689 <6>[ 0.256589] CPU features: detected: Common not Private translations
10513 16:55:18.396421 <6>[ 0.263065] CPU features: detected: CRC32 instructions
10514 16:55:18.402803 <6>[ 0.268449] CPU features: detected: RCpc load-acquire (LDAPR)
10515 16:55:18.406255 <6>[ 0.274409] CPU features: detected: LSE atomic instructions
10516 16:55:18.412874 <6>[ 0.280190] CPU features: detected: Privileged Access Never
10517 16:55:18.419510 <6>[ 0.285970] CPU features: detected: RAS Extension Support
10518 16:55:18.426161 <6>[ 0.291578] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10519 16:55:18.429484 <6>[ 0.298798] CPU: All CPU(s) started at EL2
10520 16:55:18.436005 <6>[ 0.303127] alternatives: applying system-wide alternatives
10521 16:55:18.446062 <6>[ 0.313789] devtmpfs: initialized
10522 16:55:18.461884 <6>[ 0.322652] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10523 16:55:18.468189 <6>[ 0.332618] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10524 16:55:18.474882 <6>[ 0.340813] pinctrl core: initialized pinctrl subsystem
10525 16:55:18.478105 <6>[ 0.347605] DMI not present or invalid.
10526 16:55:18.484917 <6>[ 0.352017] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10527 16:55:18.494434 <6>[ 0.358893] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10528 16:55:18.501326 <6>[ 0.366478] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10529 16:55:18.510991 <6>[ 0.374701] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10530 16:55:18.517840 <6>[ 0.382945] audit: initializing netlink subsys (disabled)
10531 16:55:18.524174 <5>[ 0.388637] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10532 16:55:18.530586 <6>[ 0.389376] thermal_sys: Registered thermal governor 'step_wise'
10533 16:55:18.537548 <6>[ 0.396604] thermal_sys: Registered thermal governor 'power_allocator'
10534 16:55:18.541010 <6>[ 0.402859] cpuidle: using governor menu
10535 16:55:18.547376 <6>[ 0.413819] NET: Registered PF_QIPCRTR protocol family
10536 16:55:18.553621 <6>[ 0.419293] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10537 16:55:18.560482 <6>[ 0.426396] ASID allocator initialised with 32768 entries
10538 16:55:18.564042 <6>[ 0.433012] Serial: AMBA PL011 UART driver
10539 16:55:18.574539 <4>[ 0.441948] Trying to register duplicate clock ID: 134
10540 16:55:18.630811 <6>[ 0.501865] KASLR enabled
10541 16:55:18.645358 <6>[ 0.509695] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10542 16:55:18.652001 <6>[ 0.516710] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10543 16:55:18.658269 <6>[ 0.523200] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10544 16:55:18.665119 <6>[ 0.530205] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10545 16:55:18.671857 <6>[ 0.536694] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10546 16:55:18.678098 <6>[ 0.543698] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10547 16:55:18.684795 <6>[ 0.550186] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10548 16:55:18.691664 <6>[ 0.557194] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10549 16:55:18.694799 <6>[ 0.564687] ACPI: Interpreter disabled.
10550 16:55:18.703200 <6>[ 0.571160] iommu: Default domain type: Translated
10551 16:55:18.709977 <6>[ 0.576319] iommu: DMA domain TLB invalidation policy: strict mode
10552 16:55:18.713083 <5>[ 0.582975] SCSI subsystem initialized
10553 16:55:18.720006 <6>[ 0.587217] usbcore: registered new interface driver usbfs
10554 16:55:18.726662 <6>[ 0.592950] usbcore: registered new interface driver hub
10555 16:55:18.730109 <6>[ 0.598504] usbcore: registered new device driver usb
10556 16:55:18.737225 <6>[ 0.604649] pps_core: LinuxPPS API ver. 1 registered
10557 16:55:18.747137 <6>[ 0.609845] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10558 16:55:18.750401 <6>[ 0.619189] PTP clock support registered
10559 16:55:18.753449 <6>[ 0.623432] EDAC MC: Ver: 3.0.0
10560 16:55:18.761334 <6>[ 0.628625] FPGA manager framework
10561 16:55:18.767524 <6>[ 0.632304] Advanced Linux Sound Architecture Driver Initialized.
10562 16:55:18.770853 <6>[ 0.639077] vgaarb: loaded
10563 16:55:18.777099 <6>[ 0.642235] clocksource: Switched to clocksource arch_sys_counter
10564 16:55:18.780476 <5>[ 0.648685] VFS: Disk quotas dquot_6.6.0
10565 16:55:18.787276 <6>[ 0.652871] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10566 16:55:18.790397 <6>[ 0.660063] pnp: PnP ACPI: disabled
10567 16:55:18.799237 <6>[ 0.666745] NET: Registered PF_INET protocol family
10568 16:55:18.808978 <6>[ 0.672331] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10569 16:55:18.820101 <6>[ 0.684638] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10570 16:55:18.830198 <6>[ 0.693454] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10571 16:55:18.836657 <6>[ 0.701429] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10572 16:55:18.846361 <6>[ 0.710130] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10573 16:55:18.852989 <6>[ 0.719879] TCP: Hash tables configured (established 65536 bind 65536)
10574 16:55:18.859278 <6>[ 0.726740] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10575 16:55:18.869332 <6>[ 0.733938] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10576 16:55:18.876303 <6>[ 0.741643] NET: Registered PF_UNIX/PF_LOCAL protocol family
10577 16:55:18.882632 <6>[ 0.747805] RPC: Registered named UNIX socket transport module.
10578 16:55:18.885985 <6>[ 0.753958] RPC: Registered udp transport module.
10579 16:55:18.892559 <6>[ 0.758892] RPC: Registered tcp transport module.
10580 16:55:18.899187 <6>[ 0.763824] RPC: Registered tcp NFSv4.1 backchannel transport module.
10581 16:55:18.902271 <6>[ 0.770493] PCI: CLS 0 bytes, default 64
10582 16:55:18.905340 <6>[ 0.774881] Unpacking initramfs...
10583 16:55:18.929927 <6>[ 0.794372] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10584 16:55:18.939851 <6>[ 0.803040] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10585 16:55:18.943043 <6>[ 0.811906] kvm [1]: IPA Size Limit: 40 bits
10586 16:55:18.949672 <6>[ 0.816435] kvm [1]: GICv3: no GICV resource entry
10587 16:55:18.953170 <6>[ 0.821457] kvm [1]: disabling GICv2 emulation
10588 16:55:18.959632 <6>[ 0.826142] kvm [1]: GIC system register CPU interface enabled
10589 16:55:18.963190 <6>[ 0.832328] kvm [1]: vgic interrupt IRQ18
10590 16:55:18.969734 <6>[ 0.836683] kvm [1]: VHE mode initialized successfully
10591 16:55:18.975830 <5>[ 0.843243] Initialise system trusted keyrings
10592 16:55:18.982496 <6>[ 0.848064] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10593 16:55:18.990599 <6>[ 0.858319] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10594 16:55:18.997265 <5>[ 0.864722] NFS: Registering the id_resolver key type
10595 16:55:19.000815 <5>[ 0.870028] Key type id_resolver registered
10596 16:55:19.006926 <5>[ 0.874445] Key type id_legacy registered
10597 16:55:19.013760 <6>[ 0.878725] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10598 16:55:19.020566 <6>[ 0.885649] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10599 16:55:19.026729 <6>[ 0.893391] 9p: Installing v9fs 9p2000 file system support
10600 16:55:19.062946 <5>[ 0.930840] Key type asymmetric registered
10601 16:55:19.066323 <5>[ 0.935180] Asymmetric key parser 'x509' registered
10602 16:55:19.076506 <6>[ 0.940334] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10603 16:55:19.079809 <6>[ 0.947952] io scheduler mq-deadline registered
10604 16:55:19.083046 <6>[ 0.952711] io scheduler kyber registered
10605 16:55:19.102249 <6>[ 0.970026] EINJ: ACPI disabled.
10606 16:55:19.134635 <4>[ 0.996022] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10607 16:55:19.144312 <4>[ 1.006651] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 16:55:19.159816 <6>[ 1.027751] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10609 16:55:19.167808 <6>[ 1.035802] printk: console [ttyS0] disabled
10610 16:55:19.195686 <6>[ 1.060448] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10611 16:55:19.202254 <6>[ 1.069927] printk: console [ttyS0] enabled
10612 16:55:19.205363 <6>[ 1.069927] printk: console [ttyS0] enabled
10613 16:55:19.212280 <6>[ 1.078820] printk: bootconsole [mtk8250] disabled
10614 16:55:19.215222 <6>[ 1.078820] printk: bootconsole [mtk8250] disabled
10615 16:55:19.222675 <6>[ 1.090072] SuperH (H)SCI(F) driver initialized
10616 16:55:19.225814 <6>[ 1.095362] msm_serial: driver initialized
10617 16:55:19.240160 <6>[ 1.104468] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10618 16:55:19.249951 <6>[ 1.113014] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10619 16:55:19.256868 <6>[ 1.121556] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10620 16:55:19.266404 <6>[ 1.130185] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10621 16:55:19.276380 <6>[ 1.138892] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10622 16:55:19.282895 <6>[ 1.147612] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10623 16:55:19.292752 <6>[ 1.156153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10624 16:55:19.299328 <6>[ 1.164958] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10625 16:55:19.309792 <6>[ 1.173501] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10626 16:55:19.322131 <6>[ 1.189398] loop: module loaded
10627 16:55:19.328502 <6>[ 1.195460] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10628 16:55:19.351254 <4>[ 1.219014] mtk-pmic-keys: Failed to locate of_node [id: -1]
10629 16:55:19.358175 <6>[ 1.225893] megasas: 07.719.03.00-rc1
10630 16:55:19.368050 <6>[ 1.235608] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10631 16:55:19.377833 <6>[ 1.245608] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10632 16:55:19.394835 <6>[ 1.262265] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10633 16:55:19.455217 <6>[ 1.316459] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10634 16:55:21.308014 <6>[ 3.176106] Freeing initrd memory: 55028K
10635 16:55:21.318541 <6>[ 3.186491] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10636 16:55:21.329852 <6>[ 3.197703] tun: Universal TUN/TAP device driver, 1.6
10637 16:55:21.333040 <6>[ 3.203810] thunder_xcv, ver 1.0
10638 16:55:21.336196 <6>[ 3.207316] thunder_bgx, ver 1.0
10639 16:55:21.339883 <6>[ 3.210809] nicpf, ver 1.0
10640 16:55:21.349937 <6>[ 3.214877] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10641 16:55:21.353591 <6>[ 3.222353] hns3: Copyright (c) 2017 Huawei Corporation.
10642 16:55:21.360471 <6>[ 3.227940] hclge is initializing
10643 16:55:21.363551 <6>[ 3.231523] e1000: Intel(R) PRO/1000 Network Driver
10644 16:55:21.370000 <6>[ 3.236653] e1000: Copyright (c) 1999-2006 Intel Corporation.
10645 16:55:21.376391 <6>[ 3.242670] e1000e: Intel(R) PRO/1000 Network Driver
10646 16:55:21.379672 <6>[ 3.247885] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10647 16:55:21.386396 <6>[ 3.254071] igb: Intel(R) Gigabit Ethernet Network Driver
10648 16:55:21.392848 <6>[ 3.259720] igb: Copyright (c) 2007-2014 Intel Corporation.
10649 16:55:21.399489 <6>[ 3.265557] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10650 16:55:21.406298 <6>[ 3.272074] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10651 16:55:21.409778 <6>[ 3.278547] sky2: driver version 1.30
10652 16:55:21.416297 <6>[ 3.283572] VFIO - User Level meta-driver version: 0.3
10653 16:55:21.423832 <6>[ 3.291830] usbcore: registered new interface driver usb-storage
10654 16:55:21.430387 <6>[ 3.298280] usbcore: registered new device driver onboard-usb-hub
10655 16:55:21.439677 <6>[ 3.307416] mt6397-rtc mt6359-rtc: registered as rtc0
10656 16:55:21.449402 <6>[ 3.312883] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:55:21 UTC (1685811321)
10657 16:55:21.452525 <6>[ 3.322475] i2c_dev: i2c /dev entries driver
10658 16:55:21.469563 <6>[ 3.334410] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10659 16:55:21.476844 <6>[ 3.344683] sdhci: Secure Digital Host Controller Interface driver
10660 16:55:21.483621 <6>[ 3.351123] sdhci: Copyright(c) Pierre Ossman
10661 16:55:21.489991 <6>[ 3.356573] Synopsys Designware Multimedia Card Interface Driver
10662 16:55:21.493357 <6>[ 3.363209] mmc0: CQHCI version 5.10
10663 16:55:21.499956 <6>[ 3.363747] sdhci-pltfm: SDHCI platform and OF driver helper
10664 16:55:21.507719 <6>[ 3.375226] ledtrig-cpu: registered to indicate activity on CPUs
10665 16:55:21.517949 <6>[ 3.382617] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10666 16:55:21.521738 <6>[ 3.390006] usbcore: registered new interface driver usbhid
10667 16:55:21.527669 <6>[ 3.395833] usbhid: USB HID core driver
10668 16:55:21.534575 <6>[ 3.400089] spi_master spi0: will run message pump with realtime priority
10669 16:55:21.578269 <6>[ 3.439896] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10670 16:55:21.597271 <6>[ 3.454912] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10671 16:55:21.600807 <6>[ 3.468520] mmc0: Command Queue Engine enabled
10672 16:55:21.607433 <6>[ 3.470173] cros-ec-spi spi0.0: Chrome EC device registered
10673 16:55:21.614411 <6>[ 3.473261] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10674 16:55:21.617506 <6>[ 3.486359] mmcblk0: mmc0:0001 DA4128 116 GiB
10675 16:55:21.627576 <6>[ 3.495230] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10676 16:55:21.637250 <6>[ 3.497356] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10677 16:55:21.643938 <6>[ 3.502401] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10678 16:55:21.647046 <6>[ 3.512550] NET: Registered PF_PACKET protocol family
10679 16:55:21.653837 <6>[ 3.516425] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10680 16:55:21.656787 <6>[ 3.521108] 9pnet: Installing 9P2000 support
10681 16:55:21.663617 <6>[ 3.527024] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10682 16:55:21.670309 <5>[ 3.530803] Key type dns_resolver registered
10683 16:55:21.673318 <6>[ 3.542426] registered taskstats version 1
10684 16:55:21.680390 <5>[ 3.546811] Loading compiled-in X.509 certificates
10685 16:55:21.712664 <4>[ 3.573736] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10686 16:55:21.722083 <4>[ 3.584437] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10687 16:55:21.732208 <3>[ 3.597152] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10688 16:55:21.744645 <6>[ 3.612686] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10689 16:55:21.751541 <6>[ 3.619438] xhci-mtk 11200000.usb: xHCI Host Controller
10690 16:55:21.757845 <6>[ 3.624942] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10691 16:55:21.767773 <6>[ 3.632787] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10692 16:55:21.775009 <6>[ 3.642229] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10693 16:55:21.781180 <6>[ 3.648425] xhci-mtk 11200000.usb: xHCI Host Controller
10694 16:55:21.788277 <6>[ 3.653918] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10695 16:55:21.794452 <6>[ 3.661590] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10696 16:55:21.801219 <6>[ 3.669525] hub 1-0:1.0: USB hub found
10697 16:55:21.804885 <6>[ 3.673567] hub 1-0:1.0: 1 port detected
10698 16:55:21.814382 <6>[ 3.677901] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10699 16:55:21.817840 <6>[ 3.686892] hub 2-0:1.0: USB hub found
10700 16:55:21.821274 <6>[ 3.690943] hub 2-0:1.0: 1 port detected
10701 16:55:21.830078 <6>[ 3.698008] mtk-msdc 11f70000.mmc: Got CD GPIO
10702 16:55:21.846549 <6>[ 3.711735] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10703 16:55:21.853382 <6>[ 3.719769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10704 16:55:21.863094 <4>[ 3.727762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10705 16:55:21.872787 <6>[ 3.737428] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10706 16:55:21.879356 <6>[ 3.745510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10707 16:55:21.889398 <6>[ 3.753535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10708 16:55:21.895981 <6>[ 3.761451] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10709 16:55:21.902623 <6>[ 3.769274] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10710 16:55:21.912765 <6>[ 3.777102] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10711 16:55:21.923154 <6>[ 3.787715] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10712 16:55:21.933425 <6>[ 3.796106] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10713 16:55:21.939691 <6>[ 3.804458] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10714 16:55:21.949639 <6>[ 3.812802] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10715 16:55:21.955974 <6>[ 3.821145] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10716 16:55:21.965401 <6>[ 3.829488] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10717 16:55:21.972114 <6>[ 3.837832] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10718 16:55:21.982304 <6>[ 3.846174] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10719 16:55:21.989015 <6>[ 3.854519] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10720 16:55:21.998393 <6>[ 3.862862] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10721 16:55:22.005202 <6>[ 3.871205] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10722 16:55:22.015009 <6>[ 3.879549] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10723 16:55:22.021554 <6>[ 3.887893] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10724 16:55:22.031372 <6>[ 3.896236] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10725 16:55:22.038319 <6>[ 3.904581] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10726 16:55:22.045734 <6>[ 3.913476] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10727 16:55:22.053072 <6>[ 3.920938] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10728 16:55:22.060031 <6>[ 3.928038] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10729 16:55:22.070438 <6>[ 3.935199] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10730 16:55:22.077653 <6>[ 3.942553] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10731 16:55:22.087181 <6>[ 3.949473] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10732 16:55:22.093906 <6>[ 3.958614] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10733 16:55:22.103451 <6>[ 3.967745] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10734 16:55:22.113327 <6>[ 3.977048] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10735 16:55:22.123655 <6>[ 3.986526] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10736 16:55:22.133429 <6>[ 3.996000] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10737 16:55:22.143002 <6>[ 4.005127] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10738 16:55:22.150260 <6>[ 4.014601] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10739 16:55:22.159750 <6>[ 4.023728] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10740 16:55:22.169662 <6>[ 4.033036] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10741 16:55:22.179307 <6>[ 4.043203] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10742 16:55:22.190423 <6>[ 4.055139] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10743 16:55:22.229909 <6>[ 4.094511] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10744 16:55:22.383913 <6>[ 4.251952] hub 1-1:1.0: USB hub found
10745 16:55:22.387317 <6>[ 4.256425] hub 1-1:1.0: 4 ports detected
10746 16:55:22.691449 <6>[ 4.374704] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10747 16:55:22.692050 <6>[ 4.403036] hub 2-1:1.0: USB hub found
10748 16:55:22.692401 <6>[ 4.407435] hub 2-1:1.0: 3 ports detected
10749 16:55:22.709457 <6>[ 4.574506] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10750 16:55:22.842918 <6>[ 4.710781] hub 1-1.4:1.0: USB hub found
10751 16:55:22.846263 <6>[ 4.715428] hub 1-1.4:1.0: 2 ports detected
10752 16:55:22.921459 <6>[ 4.786760] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10753 16:55:23.141523 <6>[ 5.006508] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10754 16:55:23.333343 <6>[ 5.198506] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10755 16:55:34.490081 <6>[ 16.363087] ALSA device list:
10756 16:55:34.496234 <6>[ 16.366343] No soundcards found.
10757 16:55:34.509196 <6>[ 16.378705] Freeing unused kernel memory: 8384K
10758 16:55:34.512400 <6>[ 16.383619] Run /init as init process
10759 16:55:34.543023 <6>[ 16.412579] NET: Registered PF_INET6 protocol family
10760 16:55:34.549273 <6>[ 16.418683] Segment Routing with IPv6
10761 16:55:34.552929 <6>[ 16.422636] In-situ OAM (IOAM) with IPv6
10762 16:55:34.587456 <30>[ 16.437334] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10763 16:55:34.590378 <30>[ 16.461303] systemd[1]: Detected architecture arm64.
10764 16:55:34.593931
10765 16:55:34.596871 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10766 16:55:34.596955
10767 16:55:34.612897 <30>[ 16.482693] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10768 16:55:34.756098 <30>[ 16.622577] systemd[1]: Queued start job for default target Graphical Interface.
10769 16:55:34.798100 <30>[ 16.667834] systemd[1]: Created slice system-getty.slice.
10770 16:55:34.804365 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10771 16:55:34.821337 <30>[ 16.691067] systemd[1]: Created slice system-modprobe.slice.
10772 16:55:34.828067 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10773 16:55:34.845674 <30>[ 16.715636] systemd[1]: Created slice system-serial\x2dgetty.slice.
10774 16:55:34.855748 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10775 16:55:34.869479 <30>[ 16.739015] systemd[1]: Created slice User and Session Slice.
10776 16:55:34.875652 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10777 16:55:34.896219 <30>[ 16.763059] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10778 16:55:34.906249 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10779 16:55:34.923948 <30>[ 16.790669] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10780 16:55:34.930674 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10781 16:55:34.951659 <30>[ 16.814606] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10782 16:55:34.958142 <30>[ 16.826636] systemd[1]: Reached target Local Encrypted Volumes.
10783 16:55:34.964915 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10784 16:55:34.981273 <30>[ 16.850847] systemd[1]: Reached target Paths.
10785 16:55:34.983989 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10786 16:55:35.000765 <30>[ 16.870548] systemd[1]: Reached target Remote File Systems.
10787 16:55:35.007456 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10788 16:55:35.020798 <30>[ 16.890533] systemd[1]: Reached target Slices.
10789 16:55:35.023767 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10790 16:55:35.040620 <30>[ 16.910541] systemd[1]: Reached target Swap.
10791 16:55:35.044043 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10792 16:55:35.064090 <30>[ 16.930847] systemd[1]: Listening on initctl Compatibility Named Pipe.
10793 16:55:35.070723 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10794 16:55:35.077358 <30>[ 16.945604] systemd[1]: Listening on Journal Audit Socket.
10795 16:55:35.084203 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10796 16:55:35.096855 <30>[ 16.966812] systemd[1]: Listening on Journal Socket (/dev/log).
10797 16:55:35.103397 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10798 16:55:35.120967 <30>[ 16.990813] systemd[1]: Listening on Journal Socket.
10799 16:55:35.127254 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10800 16:55:35.140873 <30>[ 17.010815] systemd[1]: Listening on udev Control Socket.
10801 16:55:35.147428 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10802 16:55:35.165231 <30>[ 17.035161] systemd[1]: Listening on udev Kernel Socket.
10803 16:55:35.172092 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10804 16:55:35.204805 <30>[ 17.074666] systemd[1]: Mounting Huge Pages File System...
10805 16:55:35.211186 Mounting [0;1;39mHuge Pages File System[0m...
10806 16:55:35.230014 <30>[ 17.096753] systemd[1]: Mounting POSIX Message Queue File System...
10807 16:55:35.233660 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10808 16:55:35.251066 <30>[ 17.120741] systemd[1]: Mounting Kernel Debug File System...
10809 16:55:35.257389 Mounting [0;1;39mKernel Debug File System[0m...
10810 16:55:35.276520 <30>[ 17.142852] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10811 16:55:35.312368 <30>[ 17.178815] systemd[1]: Starting Create list of static device nodes for the current kernel...
10812 16:55:35.318746 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10813 16:55:35.339091 <30>[ 17.208899] systemd[1]: Starting Load Kernel Module configfs...
10814 16:55:35.345965 Starting [0;1;39mLoad Kernel Module configfs[0m...
10815 16:55:35.363204 <30>[ 17.233062] systemd[1]: Starting Load Kernel Module drm...
10816 16:55:35.369707 Starting [0;1;39mLoad Kernel Module drm[0m...
10817 16:55:35.388045 <30>[ 17.254715] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10818 16:55:35.398787 <30>[ 17.268476] systemd[1]: Starting Journal Service...
10819 16:55:35.401797 Starting [0;1;39mJournal Service[0m...
10820 16:55:35.419532 <30>[ 17.289364] systemd[1]: Starting Load Kernel Modules...
10821 16:55:35.425911 Starting [0;1;39mLoad Kernel Modules[0m...
10822 16:55:35.446618 <30>[ 17.313010] systemd[1]: Starting Remount Root and Kernel File Systems...
10823 16:55:35.453324 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10824 16:55:35.468077 <30>[ 17.337718] systemd[1]: Starting Coldplug All udev Devices...
10825 16:55:35.474586 Starting [0;1;39mColdplug All udev Devices[0m...
10826 16:55:35.492172 <30>[ 17.361625] systemd[1]: Mounted Huge Pages File System.
10827 16:55:35.498623 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10828 16:55:35.513549 <30>[ 17.383120] systemd[1]: Started Journal Service.
10829 16:55:35.519998 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10830 16:55:35.534767 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10831 16:55:35.553609 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10832 16:55:35.573431 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10833 16:55:35.590626 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10834 16:55:35.606481 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10835 16:55:35.622150 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10836 16:55:35.641852 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10837 16:55:35.656888 See 'systemctl status systemd-remount-fs.service' for details.
10838 16:55:35.709098 Mounting [0;1;39mKernel Configuration File System[0m...
10839 16:55:35.731476 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10840 16:55:35.748973 <46>[ 17.615425] systemd-journald[176]: Received client request to flush runtime journal.
10841 16:55:35.757344 Starting [0;1;39mLoad/Save Random Seed[0m...
10842 16:55:35.779510 Starting [0;1;39mApply Kernel Variables[0m...
10843 16:55:35.799459 Starting [0;1;39mCreate System Users[0m...
10844 16:55:35.821037 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10845 16:55:35.841108 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10846 16:55:35.853453 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10847 16:55:35.869896 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10848 16:55:35.885195 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10849 16:55:35.900960 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10850 16:55:35.945415 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10851 16:55:35.967256 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10852 16:55:35.980858 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10853 16:55:35.996205 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10854 16:55:36.040984 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10855 16:55:36.064197 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10856 16:55:36.081792 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10857 16:55:36.101692 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10858 16:55:36.161951 Starting [0;1;39mNetwork Time Synchronization[0m...
10859 16:55:36.182133 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10860 16:55:36.215951 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10861 16:55:36.270689 [[0;32m OK [0m] Created slice [0;1;39msyste<6>[ 18.137291] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10862 16:55:36.273740 m-systemd\x2dbacklight.slice[0m.
10863 16:55:36.284911 <6>[ 18.155135] remoteproc remoteproc0: scp is available
10864 16:55:36.296504 <4>[ 18.163163] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10865 16:55:36.303546 <6>[ 18.173327] remoteproc remoteproc0: powering up scp
10866 16:55:36.313254 <4>[ 18.179081] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10867 16:55:36.319703 <3>[ 18.188981] remoteproc remoteproc0: request_firmware failed: -2
10868 16:55:36.343855 Starting [0;1;39mLoad/Save Screen …o<3>[ 18.209846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 16:55:36.353791 f leds:white:kbd<3>[ 18.220473] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 16:55:36.363470 _backlight[0m..<3>[ 18.228916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 16:55:36.363586 .
10872 16:55:36.373546 <6>[ 18.239804] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10873 16:55:36.379703 <3>[ 18.241893] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10874 16:55:36.390031 <6>[ 18.247464] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10875 16:55:36.396437 <3>[ 18.255630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 16:55:36.406209 <6>[ 18.264365] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10877 16:55:36.412737 <3>[ 18.272324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 16:55:36.422865 <3>[ 18.272337] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10879 16:55:36.429099 <3>[ 18.272345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10880 16:55:36.439014 <3>[ 18.303143] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 16:55:36.449309 [[0;32m OK [<4>[ 18.314996] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10882 16:55:36.456126 0m] Started [0;<3>[ 18.316998] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 16:55:36.465897 1;39mNetwork Tim<3>[ 18.332549] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10884 16:55:36.475835 e Synchronizatio<3>[ 18.341772] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 16:55:36.475923 n[0m.
10886 16:55:36.485272 <4>[ 18.346660] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10887 16:55:36.492085 <3>[ 18.356131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10888 16:55:36.498703 <6>[ 18.364195] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10889 16:55:36.508489 <3>[ 18.367406] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10890 16:55:36.515008 <3>[ 18.383211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10891 16:55:36.521591 <6>[ 18.384917] mc: Linux media interface: v0.10
10892 16:55:36.531888 <6>[ 18.386938] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10893 16:55:36.541581 [[0;32m OK [<3>[ 18.391307] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 16:55:36.547980 <3>[ 18.391318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10895 16:55:36.557817 <3>[ 18.391437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10896 16:55:36.564618 0m] Finished [0<6>[ 18.392919] usbcore: registered new interface driver r8152
10897 16:55:36.574542 ;1;39mLoad/Save <6>[ 18.393808] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10898 16:55:36.581008 Screen …s of l<6>[ 18.423921] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10899 16:55:36.591246 eds:white:kbd_ba<6>[ 18.457539] pci_bus 0000:00: root bus resource [bus 00-ff]
10900 16:55:36.591332 cklight[0m.
10901 16:55:36.600805 <4>[ 18.460390] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10902 16:55:36.604480 <4>[ 18.460390] Fallback method does not support PEC.
10903 16:55:36.610885 <6>[ 18.464867] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10904 16:55:36.621193 <6>[ 18.486612] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10905 16:55:36.631041 <6>[ 18.490761] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10906 16:55:36.637466 <6>[ 18.497139] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10907 16:55:36.647899 <3>[ 18.499414] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10908 16:55:36.654064 <6>[ 18.518530] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10909 16:55:36.660759 <6>[ 18.521007] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10910 16:55:36.667114 <6>[ 18.521950] videodev: Linux video capture interface: v2.00
10911 16:55:36.673783 <6>[ 18.536405] usbcore: registered new interface driver cdc_ether
10912 16:55:36.677506 <6>[ 18.541459] pci 0000:00:00.0: supports D1 D2
10913 16:55:36.681240 <6>[ 18.542485] Bluetooth: Core ver 2.22
10914 16:55:36.687347 <6>[ 18.542560] NET: Registered PF_BLUETOOTH protocol family
10915 16:55:36.694173 <6>[ 18.542564] Bluetooth: HCI device and connection manager initialized
10916 16:55:36.697646 <6>[ 18.542592] Bluetooth: HCI socket layer initialized
10917 16:55:36.704558 <6>[ 18.542601] Bluetooth: L2CAP socket layer initialized
10918 16:55:36.707686 <6>[ 18.542621] Bluetooth: SCO socket layer initialized
10919 16:55:36.714324 <6>[ 18.556189] usbcore: registered new interface driver r8153_ecm
10920 16:55:36.720806 <6>[ 18.561432] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10921 16:55:36.730747 <4>[ 18.574709] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10922 16:55:36.737331 <6>[ 18.579804] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10923 16:55:36.747449 <6>[ 18.580970] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10924 16:55:36.754023 <6>[ 18.581100] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10925 16:55:36.761026 <6>[ 18.581131] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10926 16:55:36.767694 <6>[ 18.581150] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10927 16:55:36.773741 <6>[ 18.581168] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10928 16:55:36.780783 <6>[ 18.581281] pci 0000:01:00.0: supports D1 D2
10929 16:55:36.787520 <6>[ 18.581285] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10930 16:55:36.794221 <4>[ 18.584605] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10931 16:55:36.800631 <6>[ 18.584671] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10932 16:55:36.807469 <6>[ 18.584781] usbcore: registered new interface driver btusb
10933 16:55:36.817230 <4>[ 18.585710] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10934 16:55:36.824298 <3>[ 18.585723] Bluetooth: hci0: Failed to load firmware file (-2)
10935 16:55:36.827730 <3>[ 18.585728] Bluetooth: hci0: Failed to set up firmware (-2)
10936 16:55:36.840525 <4>[ 18.585735] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10937 16:55:36.843995 <6>[ 18.589834] remoteproc remoteproc0: powering up scp
10938 16:55:36.853870 <4>[ 18.589883] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10939 16:55:36.860968 <6>[ 18.598492] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10940 16:55:36.867380 <3>[ 18.605857] remoteproc remoteproc0: request_firmware failed: -2
10941 16:55:36.874627 <6>[ 18.612902] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10942 16:55:36.884554 <3>[ 18.621173] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10943 16:55:36.891395 <6>[ 18.627415] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10944 16:55:36.898178 <6>[ 18.627429] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10945 16:55:36.907746 <6>[ 18.627445] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10946 16:55:36.921171 <6>[ 18.636760] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10947 16:55:36.927595 <6>[ 18.642455] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10948 16:55:36.934104 <6>[ 18.642472] pci 0000:00:00.0: PCI bridge to [bus 01]
10949 16:55:36.941257 <6>[ 18.642481] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10950 16:55:36.947453 <6>[ 18.642755] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10951 16:55:36.954008 <6>[ 18.650301] usbcore: registered new interface driver uvcvideo
10952 16:55:36.960735 <6>[ 18.655378] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10953 16:55:36.967508 <3>[ 18.672434] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 16:55:36.977028 <3>[ 18.673087] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10955 16:55:36.984034 <6>[ 18.676447] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10956 16:55:36.987135 <6>[ 18.694355] r8152 2-1.3:1.0 eth0: v1.12.13
10957 16:55:36.993881 <5>[ 18.722729] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10958 16:55:37.003502 <3>[ 18.735810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 16:55:37.010193 <3>[ 18.736434] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10960 16:55:37.016705 <6>[ 18.742101] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10961 16:55:37.023437 <5>[ 18.748682] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10962 16:55:37.033121 <3>[ 18.754119] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10963 16:55:37.046262 [[0;32m OK [0m] Found device [0;1;39m/dev/t<4>[ 18.912177] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10964 16:55:37.046403 tyS0[0m.
10965 16:55:37.053250 <6>[ 18.921606] cfg80211: failed to load regulatory.db
10966 16:55:37.063139 <3>[ 18.929712] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 16:55:37.095416 <3>[ 18.962355] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 16:55:37.102288 <6>[ 18.967648] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10969 16:55:37.108926 <6>[ 18.978643] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10970 16:55:37.125378 <3>[ 18.992082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 16:55:37.135248 <6>[ 19.005340] mt7921e 0000:01:00.0: ASIC revision: 79610010
10972 16:55:37.156381 <3>[ 19.023033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 16:55:37.214822 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10974 16:55:37.242383 [[0;32m OK [<4>[ 19.106817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10975 16:55:37.249026 0m] Reached target [0;1;39mSystem Initialization[0m.
10976 16:55:37.267918 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10977 16:55:37.280500 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10978 16:55:37.300729 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10979 16:55:37.320012 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10980 16:55:37.332403 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10981 16:55:37.353663 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10982 16:55:37.366707 <4>[ 19.229316] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10983 16:55:37.370570 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10984 16:55:37.385486 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10985 16:55:37.403989 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10986 16:55:37.453204 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10987 16:55:37.486022 <4>[ 19.349871] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10988 16:55:37.497154 Starting [0;1;39mUser Login Management[0m...
10989 16:55:37.514887 Starting [0;1;39mPermit User Sessions[0m...
10990 16:55:37.532657 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10991 16:55:37.548883 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10992 16:55:37.565960 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10993 16:55:37.575665 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10994 16:55:37.596515 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10995 16:55:37.609499 [[0;32m OK [<4>[ 19.474496] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10996 16:55:37.616451 0m] Reached target [0;1;39mLogin Prompts[0m.
10997 16:55:37.632379 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10998 16:55:37.639242 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10999 16:55:37.656595 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11000 16:55:37.732916 Starting [0;1;39mUpdate UTMP about System Runlevel Cha<4>[ 19.594798] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11001 16:55:37.733138 nges[0m...
11002 16:55:37.763937 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11003 16:55:37.793197
11004 16:55:37.793398
11005 16:55:37.796609 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11006 16:55:37.796748
11007 16:55:37.799249 debian-bullseye-arm64 login: root (automatic login)
11008 16:55:37.799387
11009 16:55:37.799512
11010 16:55:37.816886 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
11011 16:55:37.817065
11012 16:55:37.823103 The programs included with the Debian GNU/Linux system are free software;
11013 16:55:37.829850 the exact distribution terms for each program are described in the
11014 16:55:37.832959 individual files in /usr/share/doc/*/copyright.
11015 16:55:37.833115
11016 16:55:37.839783 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11017 16:55:37.842561 permitted by applicable law.
11018 16:55:37.843057 Matched prompt #10: / #
11020 16:55:37.843456 Setting prompt string to ['/ #']
11021 16:55:37.843634 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11023 16:55:37.844049 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11024 16:55:37.844210 start: 2.2.6 expect-shell-connection (timeout 00:02:31) [common]
11025 16:55:37.844346 Setting prompt string to ['/ #']
11026 16:55:37.844470 Forcing a shell prompt, looking for ['/ #']
11028 16:55:37.894801 / # <4>[ 19.716785] mt7921e 0000:
11029 16:55:37.895043 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11030 16:55:37.895191 Waiting using forced prompt support (timeout 00:02:30)
11031 16:55:37.895374 01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11032 16:55:37.899893
11033 16:55:37.900245 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11034 16:55:37.900407 start: 2.2.7 export-device-env (timeout 00:02:31) [common]
11035 16:55:37.900574 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11036 16:55:37.900732 end: 2.2 depthcharge-retry (duration 00:02:29) [common]
11037 16:55:37.900894 end: 2 depthcharge-action (duration 00:02:29) [common]
11038 16:55:37.901054 start: 3 lava-test-retry (timeout 00:07:09) [common]
11039 16:55:37.901202 start: 3.1 lava-test-shell (timeout 00:07:09) [common]
11040 16:55:37.901341 Using namespace: common
11042 16:55:38.001775 / # #
11043 16:55:38.002021 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11044 16:55:38.002220 #<4>[ 19.836835] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11045 16:55:38.007001
11046 16:55:38.007335 Using /lava-10576339
11048 16:55:38.107777 / # export SHELL=/bin/sh
11049 16:55:38.108074 export SHELL=/bin/sh<4>[ 19.956693] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11050 16:55:38.112838
11052 16:55:38.213492 / # . /lava-10576339/environment
11053 16:55:38.213798 . /lava-10576339/environment<4>[ 20.076670] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11054 16:55:38.218878
11056 16:55:38.360395 / # /lava-10576339/bin/lava-test-runner /lava-10576339/0
11057 16:55:38.360552 Test shell timeout: 10s (minimum of the action and connection timeout)
11058 16:55:38.360871 /lava-10576339/bin/lava-test-runner /lava-10576339/0<4>[ 20.196949] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11059 16:55:38.365953
11060 16:55:38.407754 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.260640] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10576339_1.5.2.3.1>
11061 16:55:38.407848 diatek
11062 16:55:38.407919 + cd /lava-10576339/0/tests/0_igt-kms-mediatek
11063 16:55:38.407984 + cat uuid
11064 16:55:38.408046 + UUID=10576339_1.5.2.3.1
11065 16:55:38.408106 + set +x
11066 16:55:38.408346 Received signal: <STARTRUN> 0_igt-kms-mediatek 10576339_1.5.2.3.1
11067 16:55:38.408417 Starting test lava.0_igt-kms-mediatek (10576339_1.5.2.3.1)
11068 16:55:38.408499 Skipping test definition patterns.
11069 16:55:38.421336 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic km<8>[ 20.291676] <LAVA_SIGNAL_TESTSET START core_auth>
11070 16:55:38.421595 Received signal: <TESTSET> START core_auth
11071 16:55:38.421673 Starting test_set core_auth
11072 16:55:38.427928 s_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11073 16:55:38.442519 <3>[ 20.312662] mt7921e 0000:01:00.0: hardware init failed
11074 16:55:38.453247 <14>[ 20.323213] [IGT] core_auth: executing
11075 16:55:38.459571 IGT-Version: 1.2<14>[ 20.327610] [IGT] core_auth: starting subtest getclient-simple
11076 16:55:38.466165 7.1-g766edf9 (aa<14>[ 20.335377] [IGT] core_auth: exiting, ret=0
11077 16:55:38.469244 rch64) (Linux: 6.1.31 aarch64)
11078 16:55:38.472855 Starting subtest: getclient-simple
11079 16:55:38.479016 Opened devic<8>[ 20.347185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11080 16:55:38.479293 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11082 16:55:38.482610 e: /dev/dri/card0
11083 16:55:38.485807 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11084 16:55:38.502431 <14>[ 20.372680] [IGT] core_auth: executing
11085 16:55:38.509377 IGT-Version: 1.2<14>[ 20.377222] [IGT] core_auth: starting subtest getclient-master-drop
11086 16:55:38.515897 7.1-g766edf9 (aa<14>[ 20.385463] [IGT] core_auth: exiting, ret=0
11087 16:55:38.518866 rch64) (Linux: 6.1.31 aarch64)
11088 16:55:38.522457 Starting subtest: getclient-master-drop
11089 16:55:38.528763 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11091 16:55:38.532308 Opened <8>[ 20.396897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11092 16:55:38.532412 device: /dev/dri/card0
11093 16:55:38.538871 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11094 16:55:38.553961 <14>[ 20.424195] [IGT] core_auth: executing
11095 16:55:38.560782 IGT-Version: 1.2<14>[ 20.428637] [IGT] core_auth: starting subtest basic-auth
11096 16:55:38.567267 7.1-g766edf9 (aa<14>[ 20.436023] [IGT] core_auth: exiting, ret=0
11097 16:55:38.570218 rch64) (Linux: 6.1.31 aarch64)
11098 16:55:38.570319 Opened device: /dev/dri/card0
11099 16:55:38.580166 Starting subtest:<8>[ 20.447516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11100 16:55:38.580250 basic-auth
11101 16:55:38.580486 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11103 16:55:38.583642 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11104 16:55:38.603327 <14>[ 20.473129] [IGT] core_auth: executing
11105 16:55:38.609511 IGT-Version: 1.2<14>[ 20.477725] [IGT] core_auth: starting subtest many-magics
11106 16:55:38.612542 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11107 16:55:38.616376 Opened device: /dev/dri/card0
11108 16:55:38.619387 Starting subtest: many-magics
11109 16:55:38.622926 Reopening device failed after 1020 opens
11110 16:55:38.629056 <14>[ 20.498012] [IGT] core_auth: exiting, ret=0
11111 16:55:38.632058 [1mSubtest many-magics: SUCCESS (0.013s)[0m
11112 16:55:38.642500 <8>[ 20.509344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11113 16:55:38.642781 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11115 16:55:38.645517 <8>[ 20.517785] <LAVA_SIGNAL_TESTSET STOP>
11116 16:55:38.645766 Received signal: <TESTSET> STOP
11117 16:55:38.645837 Closing test_set core_auth
11118 16:55:38.688054 <14>[ 20.558262] [IGT] core_getclient: executing
11119 16:55:38.694688 IGT-Version: 1.2<14>[ 20.563350] [IGT] core_getclient: exiting, ret=0
11120 16:55:38.697948 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11121 16:55:38.701373 Opened device: /dev/dri/card0
11122 16:55:38.707835 S<8>[ 20.575672] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11123 16:55:38.708089 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11125 16:55:38.710765 UCCESS (0.006s)
11126 16:55:38.749704 <14>[ 20.619946] [IGT] core_getstats: executing
11127 16:55:38.756453 IGT-Version: 1.2<14>[ 20.624818] [IGT] core_getstats: exiting, ret=0
11128 16:55:38.759965 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11129 16:55:38.763102 Opened device: /dev/dri/card0
11130 16:55:38.769515 S<8>[ 20.637100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11131 16:55:38.769781 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11133 16:55:38.772579 UCCESS (0.006s)
11134 16:55:38.809931 <14>[ 20.680259] [IGT] core_getversion: executing
11135 16:55:38.816328 IGT-Version: 1.2<14>[ 20.685302] [IGT] core_getversion: exiting, ret=0
11136 16:55:38.819878 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11137 16:55:38.822938 Opened device: /dev/dri/card0
11138 16:55:38.829789 S<8>[ 20.697718] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11139 16:55:38.830042 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11141 16:55:38.832794 UCCESS (0.006s)
11142 16:55:38.870795 <14>[ 20.741148] [IGT] core_setmaster_vs_auth: executing
11143 16:55:38.877268 IGT-Version: 1.2<14>[ 20.746982] [IGT] core_setmaster_vs_auth: exiting, ret=0
11144 16:55:38.883832 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11145 16:55:38.883919 Opened device: /dev/dri/card0
11146 16:55:38.894356 S<8>[ 20.759845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11147 16:55:38.894436 UCCESS (0.007s)
11148 16:55:38.894676 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11150 16:55:38.918774 <8>[ 20.789330] <LAVA_SIGNAL_TESTSET START drm_read>
11151 16:55:38.919122 Received signal: <TESTSET> START drm_read
11152 16:55:38.919256 Starting test_set drm_read
11153 16:55:38.940893 <14>[ 20.811300] [IGT] drm_read: executing
11154 16:55:38.947693 IGT-Version: 1.2<14>[ 20.815893] [IGT] drm_read: exiting, ret=77
11155 16:55:38.950799 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11156 16:55:38.954378 Opened device: /dev/dri/card0
11157 16:55:38.960986 N<8>[ 20.827351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11158 16:55:38.961276 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11160 16:55:38.964170 o KMS driver or no outputs, pipes: 8, outputs: 0
11161 16:55:38.967216 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11162 16:55:38.982286 <14>[ 20.852891] [IGT] drm_read: executing
11163 16:55:38.989271 IGT-Version: 1.2<14>[ 20.857458] [IGT] drm_read: exiting, ret=77
11164 16:55:38.992240 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11165 16:55:38.995532 Opened device: /dev/dri/card0
11166 16:55:39.002385 N<8>[ 20.869049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11167 16:55:39.002664 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11169 16:55:39.005693 o KMS driver or no outputs, pipes: 8, outputs: 0
11170 16:55:39.008963 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11171 16:55:39.023965 <14>[ 20.894511] [IGT] drm_read: executing
11172 16:55:39.031089 IGT-Version: 1.2<14>[ 20.899101] [IGT] drm_read: exiting, ret=77
11173 16:55:39.034175 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11174 16:55:39.037216 Opened device: /dev/dri/card0
11175 16:55:39.043923 N<8>[ 20.910775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11176 16:55:39.044199 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11178 16:55:39.047155 o KMS driver or no outputs, pipes: 8, outputs: 0
11179 16:55:39.050837 [1mSubtest empty-block: SKIP (0.000s)[0m
11180 16:55:39.066253 <14>[ 20.936353] [IGT] drm_read: executing
11181 16:55:39.072629 IGT-Version: 1.2<14>[ 20.940972] [IGT] drm_read: exiting, ret=77
11182 16:55:39.076112 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11183 16:55:39.079472 Opened device: /dev/dri/card0
11184 16:55:39.085564 N<8>[ 20.952626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11185 16:55:39.085820 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11187 16:55:39.089167 o KMS driver or no outputs, pipes: 8, outputs: 0
11188 16:55:39.092553 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11189 16:55:39.108039 <14>[ 20.978091] [IGT] drm_read: executing
11190 16:55:39.114284 IGT-Version: 1.2<14>[ 20.982847] [IGT] drm_read: exiting, ret=77
11191 16:55:39.117722 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11192 16:55:39.120735 Opened device: /dev/dri/card0
11193 16:55:39.127570 N<8>[ 20.994001] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11194 16:55:39.127880 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11196 16:55:39.130586 o KMS driver or no outputs, pipes: 8, outputs: 0
11197 16:55:39.137120 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11198 16:55:39.150081 <14>[ 21.020579] [IGT] drm_read: executing
11199 16:55:39.156614 IGT-Version: 1.2<14>[ 21.025116] [IGT] drm_read: exiting, ret=77
11200 16:55:39.160336 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11201 16:55:39.163510 Opened device: /dev/dri/card0
11202 16:55:39.170224 N<8>[ 21.037251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11203 16:55:39.170508 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11205 16:55:39.173346 o KMS driver or no outputs, pipes: 8, outputs: 0
11206 16:55:39.179707 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11207 16:55:39.192325 <14>[ 21.062572] [IGT] drm_read: executing
11208 16:55:39.199114 IGT-Version: 1.2<14>[ 21.067150] [IGT] drm_read: exiting, ret=77
11209 16:55:39.201882 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11210 16:55:39.205319 Opened device: /dev/dri/card0
11211 16:55:39.212147 N<8>[ 21.079007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11212 16:55:39.212407 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11214 16:55:39.218333 o KMS driver or no outputs, pipe<8>[ 21.088843] <LAVA_SIGNAL_TESTSET STOP>
11215 16:55:39.218589 Received signal: <TESTSET> STOP
11216 16:55:39.218663 Closing test_set drm_read
11217 16:55:39.221944 s: 8, outputs: 0
11218 16:55:39.224907 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11219 16:55:39.244328 <8>[ 21.114477] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11220 16:55:39.244558 Received signal: <TESTSET> START kms_addfb_basic
11221 16:55:39.244713 Starting test_set kms_addfb_basic
11222 16:55:39.266790 <14>[ 21.137027] [IGT] kms_addfb_basic: executing
11223 16:55:39.273065 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11224 16:55:39.279985 <14>[ 21.146499] [IGT] kms_addfb_basic: starting subtest unused-handle
11225 16:55:39.280070 Opened device: /dev/dri/card0
11226 16:55:39.283005 Starting subtest: unused-handle
11227 16:55:39.289556 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11228 16:55:39.293280 Test requiremen<14>[ 21.163829] [IGT] kms_addfb_basic: exiting, ret=0
11229 16:55:39.299753 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11230 16:55:39.309798 Test require<8>[ 21.176573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11231 16:55:39.309886 ment: is_i915_device(fd)
11232 16:55:39.310132 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11234 16:55:39.319470 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11235 16:55:39.323017 Test requirement: is_i915_device(fd)
11236 16:55:39.326343 No KMS driver or no outputs, pipes: 8, outputs: 0
11237 16:55:39.329413 <14>[ 21.201442] [IGT] kms_addfb_basic: executing
11238 16:55:39.335914 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11239 16:55:39.342234 <14>[ 21.211019] [IGT] kms_addfb_basic: starting subtest unused-pitches
11240 16:55:39.345821 Opened device: /dev/dri/card0
11241 16:55:39.348862 Starting subtest: unused-pitches
11242 16:55:39.352650 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11243 16:55:39.358828 Test requirement<14>[ 21.228673] [IGT] kms_addfb_basic: exiting, ret=0
11244 16:55:39.365537 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11245 16:55:39.371905 Test requirem<8>[ 21.241510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11246 16:55:39.372168 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11248 16:55:39.375490 ent: is_i915_device(fd)
11249 16:55:39.382359 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11250 16:55:39.385391 Test requirement: is_i915_device(fd)
11251 16:55:39.391831 No KMS driver or no outputs, pipes: 8, outputs: 0
11252 16:55:39.394865 <14>[ 21.267234] [IGT] kms_addfb_basic: executing
11253 16:55:39.401713 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11254 16:55:39.408304 <14>[ 21.276752] [IGT] kms_addfb_basic: starting subtest unused-offsets
11255 16:55:39.411702 Opened device: /dev/dri/card0
11256 16:55:39.415138 Starting subtest: unused-offsets
11257 16:55:39.418393 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11258 16:55:39.424803 Test requirement<14>[ 21.294372] [IGT] kms_addfb_basic: exiting, ret=0
11259 16:55:39.431563 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11260 16:55:39.438496 Test requirem<8>[ 21.307318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11261 16:55:39.438782 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11263 16:55:39.441559 ent: is_i915_device(fd)
11264 16:55:39.448198 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11265 16:55:39.451128 Test requirement: is_i915_device(fd)
11266 16:55:39.457755 No KMS driver or no outputs, pipes: 8, outputs: 0
11267 16:55:39.460881 <14>[ 21.331877] [IGT] kms_addfb_basic: executing
11268 16:55:39.467640 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11269 16:55:39.474860 <14>[ 21.341252] [IGT] kms_addfb_basic: starting subtest unused-modifier
11270 16:55:39.477890 Opened device: /dev/dri/card0
11271 16:55:39.480827 Starting subtest: unused-modifier
11272 16:55:39.483829 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11273 16:55:39.490776 Test requirement<14>[ 21.359092] [IGT] kms_addfb_basic: exiting, ret=0
11274 16:55:39.497113 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11275 16:55:39.503833 Test requirem<8>[ 21.372033] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11276 16:55:39.504092 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11278 16:55:39.506897 ent: is_i915_device(fd)
11279 16:55:39.513521 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11280 16:55:39.516954 Test requirement: is_i915_device(fd)
11281 16:55:39.519879 No KMS driver or no outputs, pipes: 8, outputs: 0
11282 16:55:39.526693 <14>[ 21.397024] [IGT] kms_addfb_basic: executing
11283 16:55:39.533386 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11284 16:55:39.540034 <14>[ 21.406476] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11285 16:55:39.543092 Opened device: /dev/dri/card0
11286 16:55:39.546381 Starting subtest: clobberred-modifier
11287 16:55:39.556684 Test requirement not met in function igt_require_i915, fil<14>[ 21.424632] [IGT] kms_addfb_basic: exiting, ret=77
11288 16:55:39.556796 e ../lib/drmtest.c:721:
11289 16:55:39.559411 Test requirement: is_i915_device(fd)
11290 16:55:39.569384 [1mSubtest clobb<8>[ 21.437185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11291 16:55:39.569635 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11293 16:55:39.572851 erred-modifier: SKIP (0.000s)[0m
11294 16:55:39.579831 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11295 16:55:39.582520 Test requirement: is_i915_device(fd)
11296 16:55:39.592339 Test requirement not met in function igt_require_i915, file ../lib/d<14>[ 21.463251] [IGT] kms_addfb_basic: executing
11297 16:55:39.595988 rmtest.c:721:
11298 16:55:39.598932 Test requirement: is_i915_device(fd)
11299 16:55:39.605608 No KMS driv<14>[ 21.474400] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11300 16:55:39.612510 er or no outputs, pipes: 8, outputs: 0
11301 16:55:39.615547 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11302 16:55:39.622259 Opened device: /dev/dri/<14>[ 21.492600] [IGT] kms_addfb_basic: exiting, ret=77
11303 16:55:39.625318 card0
11304 16:55:39.628873 Starting subtest: invalid-smem-bo-on-discrete
11305 16:55:39.638515 Test requirement not met i<8>[ 21.505383] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11306 16:55:39.638815 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11308 16:55:39.645050 n function igt_require_intel, file ../lib/drmtest.c:716:
11309 16:55:39.648438 Test requirement: is_intel_device(fd)
11310 16:55:39.651435 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11311 16:55:39.661446 Test requirement not met in function igt_require_i9<14>[ 21.531786] [IGT] kms_addfb_basic: executing
11312 16:55:39.664820 15, file ../lib/drmtest.c:721:
11313 16:55:39.674919 Test requirement: is_i915_device<14>[ 21.541568] [IGT] kms_addfb_basic: starting subtest legacy-format
11314 16:55:39.675000 (fd)
11315 16:55:39.681147 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11316 16:55:39.684829 Test requirement: is_i915_device(fd)
11317 16:55:39.687809 No KMS driver or no outputs, pipes: 8, outputs: 0
11318 16:55:39.694610 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11319 16:55:39.697867 Opened device: /dev/dri/card0
11320 16:55:39.701476 <14>[ 21.571831] [IGT] kms_addfb_basic: exiting, ret=0
11321 16:55:39.701550
11322 16:55:39.704494 Starting subtest: legacy-format
11323 16:55:39.714587 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11325 16:55:39.717950 Successfully fuzzed 10000 {bpp, depth} variati<8>[ 21.583961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11326 16:55:39.718031 ons
11327 16:55:39.721047 [1mSubtest legacy-format: SUCCESS (0.013s)[0m
11328 16:55:39.727870 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11329 16:55:39.730696 Test requirement: is_i915_device(fd)
11330 16:55:39.737281 Test requirement not met in funct<14>[ 21.609076] [IGT] kms_addfb_basic: executing
11331 16:55:39.743959 ion igt_require_i915, file ../lib/drmtest.c:721:
11332 16:55:39.747035 Test requirement: is_i915_device(fd)
11333 16:55:39.753785 No KMS d<14>[ 21.621540] [IGT] kms_addfb_basic: starting subtest no-handle
11334 16:55:39.757372 river or no outputs, pipes: 8, outputs: 0
11335 16:55:39.767154 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31<14>[ 21.636125] [IGT] kms_addfb_basic: exiting, ret=0
11336 16:55:39.767239 aarch64)
11337 16:55:39.770078 Opened device: /dev/dri/card0
11338 16:55:39.773616 Starting subtest: no-handle
11339 16:55:39.780008 [1mSubte<8>[ 21.648386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11340 16:55:39.780268 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11342 16:55:39.783628 st no-handle: SUCCESS (0.000s)[0m
11343 16:55:39.789697 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11344 16:55:39.793294 Test requirement: is_i915_device(fd)
11345 16:55:39.802969 Test requirement not met in function igt_require_i9<14>[ 21.672971] [IGT] kms_addfb_basic: executing
11346 16:55:39.806620 15, file ../lib/drmtest.c:721:
11347 16:55:39.809744 Test requirement: is_i915_device(fd)
11348 16:55:39.816564 No KMS driver or no output<14>[ 21.685845] [IGT] kms_addfb_basic: starting subtest basic
11349 16:55:39.819594 s, pipes: 8, outputs: 0
11350 16:55:39.826456 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11351 16:55:39.829941 Opened <14>[ 21.699979] [IGT] kms_addfb_basic: exiting, ret=0
11352 16:55:39.833079 device: /dev/dri/card0
11353 16:55:39.836181 Starting subtest: basic
11354 16:55:39.842727 [1mSubtest basic: SUCCESS (0.0<8>[ 21.712211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11355 16:55:39.842981 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11357 16:55:39.846175 00s)[0m
11358 16:55:39.852578 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11359 16:55:39.855985 Test requirement: is_i915_device(fd)
11360 16:55:39.865765 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:<14>[ 21.736533] [IGT] kms_addfb_basic: executing
11361 16:55:39.865849 721:
11362 16:55:39.868949 Test requirement: is_i915_device(fd)
11363 16:55:39.875752 No KMS driver or no outputs, pipes: 8, outputs: 0
11364 16:55:39.882473 I<14>[ 21.749377] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11365 16:55:39.885444 GT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11366 16:55:39.889090 Opened device: /dev/dri/card0
11367 16:55:39.895425 St<14>[ 21.764028] [IGT] kms_addfb_basic: exiting, ret=0
11368 16:55:39.895531 arting subtest: bad-pitch-0
11369 16:55:39.901958 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11370 16:55:39.908469 Test<8>[ 21.776291] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11371 16:55:39.908759 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11373 16:55:39.915097 requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11374 16:55:39.918809 Test requirement: is_i915_device(fd)
11375 16:55:39.924917 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11376 16:55:39.931499 Test req<14>[ 21.800981] [IGT] kms_addfb_basic: executing
11377 16:55:39.935316 uirement: is_i915_device(fd)
11378 16:55:39.938382 No KMS driver or no outputs, pipes: 8, outputs: 0
11379 16:55:39.945068 IGT-Version: 1.<14>[ 21.813913] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11380 16:55:39.951792 27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11381 16:55:39.951913 Opened device: /dev/dri/card0
11382 16:55:39.958478 Starting subtest<14>[ 21.828767] [IGT] kms_addfb_basic: exiting, ret=0
11383 16:55:39.961523 : bad-pitch-32
11384 16:55:39.964877 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11385 16:55:39.971308 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11387 16:55:39.974798 Test requirement<8>[ 21.841044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11388 16:55:39.977690 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11389 16:55:39.981374 Test requirement: is_i915_device(fd)
11390 16:55:39.987759 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11391 16:55:39.994304 Test requirement: is<14>[ 21.865664] [IGT] kms_addfb_basic: executing
11392 16:55:39.997931 _i915_device(fd)
11393 16:55:40.001045 No KMS driver or no outputs, pipes: 8, outputs: 0
11394 16:55:40.010667 IGT-Version: 1.27.1-g766edf<14>[ 21.878709] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11395 16:55:40.014181 9 (aarch64) (Linux: 6.1.31 aarch64)
11396 16:55:40.017762 Opened device: /dev/dri/card0
11397 16:55:40.023890 Starting subtest: bad-pitch-<14>[ 21.893389] [IGT] kms_addfb_basic: exiting, ret=0
11398 16:55:40.023993 63
11399 16:55:40.027480 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11400 16:55:40.037067 Test requirement not met in <8>[ 21.905985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11401 16:55:40.037355 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11403 16:55:40.043757 function igt_require_i915, file ../lib/drmtest.c:721:
11404 16:55:40.047301 Test requirement: is_i915_device(fd)
11405 16:55:40.053950 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11406 16:55:40.060635 Test requirement: is_i915_device<14>[ 21.930308] [IGT] kms_addfb_basic: executing
11407 16:55:40.060716 (fd)
11408 16:55:40.066821 No KMS driver or no outputs, pipes: 8, outputs: 0
11409 16:55:40.076780 IGT-Version: 1.27.1-g766edf9 (aarch64) <14>[ 21.943598] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11410 16:55:40.076884 (Linux: 6.1.31 aarch64)
11411 16:55:40.080289 Opened device: /dev/dri/card0
11412 16:55:40.083271 Starting subtest: bad-pitch-128
11413 16:55:40.090019 [1mSub<14>[ 21.958376] [IGT] kms_addfb_basic: exiting, ret=0
11414 16:55:40.093533 test bad-pitch-128: SUCCESS (0.000s)[0m
11415 16:55:40.103138 Test requirement not met in function i<8>[ 21.970726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11416 16:55:40.103398 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11418 16:55:40.106928 gt_require_i915, file ../lib/drmtest.c:721:
11419 16:55:40.109821 Test requirement: is_i915_device(fd)
11420 16:55:40.116312 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11421 16:55:40.119787 Test requirement: is_i915_device(fd)
11422 16:55:40.126533 No K<14>[ 21.995768] [IGT] kms_addfb_basic: executing
11423 16:55:40.129491 MS driver or no outputs, pipes: 8, outputs: 0
11424 16:55:40.139155 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.<14>[ 22.008340] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11425 16:55:40.142942 1.31 aarch64)
11426 16:55:40.145971 Opened device: /dev/dri/card0
11427 16:55:40.146048 Starting subtest: bad-pitch-256
11428 16:55:40.152786 [1mSubtest bad-p<14>[ 22.023312] [IGT] kms_addfb_basic: exiting, ret=0
11429 16:55:40.155813 itch-256: SUCCESS (0.000s)[0m
11430 16:55:40.169038 Test requirement not met in function igt_require<8>[ 22.035752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11431 16:55:40.169295 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11433 16:55:40.172010 _i915, file ../lib/drmtest.c:721:
11434 16:55:40.175764 Test requirement: is_i915_device(fd)
11435 16:55:40.182162 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11436 16:55:40.185674 Test requirement: is_i915_device(fd)
11437 16:55:40.192151 No KMS driver <14>[ 22.060808] [IGT] kms_addfb_basic: executing
11438 16:55:40.195391 or no outputs, pipes: 8, outputs: 0
11439 16:55:40.204938 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch<14>[ 22.073338] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11440 16:55:40.205040 64)
11441 16:55:40.208344 Opened device: /dev/dri/card0
11442 16:55:40.211802 Starting subtest: bad-pitch-1024
11443 16:55:40.218088 [1mSubtest bad-pitch-1024<14>[ 22.088384] [IGT] kms_addfb_basic: exiting, ret=0
11444 16:55:40.221597 : SUCCESS (0.000s)[0m
11445 16:55:40.231351 Test requirement not met in function igt_require_i915, f<8>[ 22.100801] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11446 16:55:40.231639 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11448 16:55:40.234571 ile ../lib/drmtest.c:721:
11449 16:55:40.238097 Test requirement: is_i915_device(fd)
11450 16:55:40.245022 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11451 16:55:40.247875 Test requirement: is_i915_device(fd)
11452 16:55:40.257667 No KMS driver or no outputs, pipes: 8,<14>[ 22.126541] [IGT] kms_addfb_basic: executing
11453 16:55:40.257779 outputs: 0
11454 16:55:40.264325 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11455 16:55:40.270905 Opened device: /<14>[ 22.140084] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11456 16:55:40.274695 dev/dri/card0
11457 16:55:40.274777 Starting subtest: bad-pitch-999
11458 16:55:40.283965 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m<14>[ 22.154478] [IGT] kms_addfb_basic: exiting, ret=0
11459 16:55:40.284074
11460 16:55:40.297308 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<8>[ 22.166834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11461 16:55:40.297598 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11463 16:55:40.300639 21:
11464 16:55:40.304054 Test requirement: is_i915_device(fd)
11465 16:55:40.310318 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11466 16:55:40.313654 Test requirement: is_i915_device(fd)
11467 16:55:40.317146 No KMS driver or no outputs, pipes: 8, outputs: 0
11468 16:55:40.323969 <14>[ 22.192551] [IGT] kms_addfb_basic: executing
11469 16:55:40.327213 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11470 16:55:40.330348 Opened device: /dev/dri/card0
11471 16:55:40.337330 <14>[ 22.205332] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11472 16:55:40.340199 Starting subtest: bad-pitch-65536
11473 16:55:40.343295 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11474 16:55:40.350079 Test requi<14>[ 22.220003] [IGT] kms_addfb_basic: exiting, ret=0
11475 16:55:40.356713 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11476 16:55:40.363536 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11478 16:55:40.366304 Test re<8>[ 22.232485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11479 16:55:40.366387 quirement: is_i915_device(fd)
11480 16:55:40.376480 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11481 16:55:40.379450 Test requirement: is_i915_device(fd)
11482 16:55:40.383130 No KMS driver or no outputs, pipes: 8, outputs: 0
11483 16:55:40.386008 <14>[ 22.257733] [IGT] kms_addfb_basic: executing
11484 16:55:40.392541 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11485 16:55:40.396115 Opened device: /dev/dri/card0
11486 16:55:40.402559 <14>[ 22.272224] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11487 16:55:40.406301 Starting subtest: invalid-get-prop-any
11488 16:55:40.415967 [1mSubtest invalid-get-<14>[ 22.284591] [IGT] kms_addfb_basic: exiting, ret=0
11489 16:55:40.418912 prop-any: SUCCESS (0.000s)[0m
11490 16:55:40.429102 Test requirement not met in function igt_require<8>[ 22.296337] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11491 16:55:40.429361 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11493 16:55:40.432038 _i915, file ../lib/drmtest.c:721:
11494 16:55:40.435586 Test requirement: is_i915_device(fd)
11495 16:55:40.442111 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11496 16:55:40.445587 Test requirement: is_i915_device(fd)
11497 16:55:40.452132 No KMS driver <14>[ 22.321966] [IGT] kms_addfb_basic: executing
11498 16:55:40.455128 or no outputs, pipes: 8, outputs: 0
11499 16:55:40.461979 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11500 16:55:40.468423 Opened device: /dev/dri/car<14>[ 22.337158] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11501 16:55:40.468510 d0
11502 16:55:40.472094 Starting subtest: invalid-get-prop
11503 16:55:40.481793 [1mSubtest invalid-get-prop<14>[ 22.350567] [IGT] kms_addfb_basic: exiting, ret=0
11504 16:55:40.481879 : SUCCESS (0.000s)[0m
11505 16:55:40.494864 Test requirement not met in function igt_require_i915, f<8>[ 22.362816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11506 16:55:40.495125 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11508 16:55:40.497901 ile ../lib/drmtest.c:721:
11509 16:55:40.501596 Test requirement: is_i915_device(fd)
11510 16:55:40.507960 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11511 16:55:40.511292 Test requirement: is_i915_device(fd)
11512 16:55:40.518297 No KMS driver or no ou<14>[ 22.387815] [IGT] kms_addfb_basic: executing
11513 16:55:40.521219 tputs, pipes: 8, outputs: 0
11514 16:55:40.524766 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11515 16:55:40.527518 Opened device: /dev/dri/card0
11516 16:55:40.534259 <14>[ 22.403008] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11517 16:55:40.538062 Starting subtest: invalid-set-prop-any
11518 16:55:40.547514 [1mSubtest invalid-set-<14>[ 22.416375] [IGT] kms_addfb_basic: exiting, ret=0
11519 16:55:40.550944 prop-any: SUCCESS (0.000s)[0m
11520 16:55:40.561110 Test requirement not met in function igt_require<8>[ 22.428231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11521 16:55:40.561374 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11523 16:55:40.564005 _i915, file ../lib/drmtest.c:721:
11524 16:55:40.567141 Test requirement: is_i915_device(fd)
11525 16:55:40.573821 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11526 16:55:40.577231 Test requirement: is_i915_device(fd)
11527 16:55:40.583993 No KMS driver <14>[ 22.453749] [IGT] kms_addfb_basic: executing
11528 16:55:40.587126 or no outputs, pipes: 8, outputs: 0
11529 16:55:40.593952 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11530 16:55:40.600160 Opened device: /dev/dri/car<14>[ 22.468952] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11531 16:55:40.603265 d0
11532 16:55:40.606845 Starting subtest: invalid-set-prop
11533 16:55:40.613146 [1mSubtest invalid-set-prop<14>[ 22.482326] [IGT] kms_addfb_basic: exiting, ret=0
11534 16:55:40.613234 : SUCCESS (0.000s)[0m
11535 16:55:40.626463 Test requirement not met in function igt_require_i915, f<8>[ 22.494540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11536 16:55:40.626724 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11538 16:55:40.630020 ile ../lib/drmtest.c:721:
11539 16:55:40.633089 Test requirement: is_i915_device(fd)
11540 16:55:40.639883 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11541 16:55:40.642897 Test requirement: is_i915_device(fd)
11542 16:55:40.649522 No KMS driver or no ou<14>[ 22.519756] [IGT] kms_addfb_basic: executing
11543 16:55:40.653182 tputs, pipes: 8, outputs: 0
11544 16:55:40.656073 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11545 16:55:40.659510 Opened device: /dev/dri/card0
11546 16:55:40.666517 <14>[ 22.537202] [IGT] kms_addfb_basic: starting subtest master-rmfb
11547 16:55:40.670107 Starting subtest: master-rmfb
11548 16:55:40.676918 [1mSubtest maste<14>[ 22.546528] [IGT] kms_addfb_basic: exiting, ret=0
11549 16:55:40.679993 r-rmfb: SUCCESS (0.000s)[0m
11550 16:55:40.690251 Test requirement not met in function igt_require_i<8>[ 22.559305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11551 16:55:40.690508 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11553 16:55:40.693182 915, file ../lib/drmtest.c:721:
11554 16:55:40.696499 Test requirement: is_i915_device(fd)
11555 16:55:40.703143 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11556 16:55:40.706186 Test requirement: is_i915_device(fd)
11557 16:55:40.712956 No KMS driver or<14>[ 22.584111] [IGT] kms_addfb_basic: executing
11558 16:55:40.716556 no outputs, pipes: 8, outputs: 0
11559 16:55:40.723035 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11560 16:55:40.725918 Opened device: /dev/dri/card0
11561 16:55:40.736330 <14>[ 22.603762] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11562 16:55:40.743391 Starting subtest<14>[ 22.611893] [IGT] kms_addfb_basic: exiting, ret=0
11563 16:55:40.746569 : addfb25-modifier-no-flag
11564 16:55:40.756435 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.624368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11565 16:55:40.756700 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11567 16:55:40.759688 s)[0m
11568 16:55:40.766173 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11569 16:55:40.769680 Test requirement: is_i915_device(fd)
11570 16:55:40.779402 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.650300] [IGT] kms_addfb_basic: executing
11571 16:55:40.779497 1:
11572 16:55:40.782496 Test requirement: is_i915_device(fd)
11573 16:55:40.789120 No KMS driver or no outputs, pipes: 8, outputs: 0
11574 16:55:40.792255 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11575 16:55:40.802468 Opened device: /dev<14>[ 22.669863] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11576 16:55:40.802578 /dri/card0
11577 16:55:40.806007 Starting subtest: addfb25-bad-modifier
11578 16:55:40.818752 (kms_addfb_basic:436) CRITICAL: Test assertion failure function addfb25_<14>[ 22.688011] [IGT] kms_addfb_basic: exiting, ret=98
11579 16:55:40.821897 tests, file ../tests/kms_addfb_basic.c:662:
11580 16:55:40.831729 (kms_addfb_basic:436) CRITICAL: Fai<8>[ 22.700364] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11581 16:55:40.831987 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11583 16:55:40.848591 led assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11584 16:55:40.855179 (kms_addfb_basic:436) CRITICAL: error<14>[ 22.726109] [IGT] kms_addfb_basic: executing
11585 16:55:40.855271 : 0 != -1
11586 16:55:40.858453 Stack trace:
11587 16:55:40.861702 #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11588 16:55:40.864848 #1 [<unknown>+0xb57a47e0]
11589 16:55:40.868222 #2 [<unknown>+0xb57a6278]
11590 16:55:40.868361 #3 [<unknown>+0xb57a167c]
11591 16:55:40.875022 #4 [__libc_st<14>[ 22.746029] [IGT] kms_addfb_basic: exiting, ret=77
11592 16:55:40.878280 art_main+0xe8]
11593 16:55:40.881441 #5 [<unknown>+0xb57a16b4]
11594 16:55:40.881527 #6 [<unknown>+0xb57a16b4]
11595 16:55:40.891486 Subtes<8>[ 22.757997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11596 16:55:40.891770 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11598 16:55:40.894613 t addfb25-bad-modifier failed.
11599 16:55:40.894697 **** DEBUG ****
11600 16:55:40.904517 (kms_addfb_basic:436) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11601 16:55:40.914562 (kms_addfb_basic:436) CRITICAL: Test assertion failure function <14>[ 22.784214] [IGT] kms_addfb_basic: executing
11602 16:55:40.917573 addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11603 16:55:40.934345 (kms_addfb_basic:436) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0<14>[ 22.804796] [IGT] kms_addfb_basic: exiting, ret=77
11604 16:55:40.950610 xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -<8>[ 22.816883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11605 16:55:40.950701 1
11606 16:55:40.950981 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11608 16:55:40.954030 (kms_addfb_basic:436) CRITICAL: error: 0 != -1
11609 16:55:40.957545 (kms_addfb_basic:436) igt_core-INFO: Stack trace:
11610 16:55:40.967254 (kms_addfb_basic:436) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11611 16:55:40.974067 (kms_addfb_basic:436<14>[ 22.842104] [IGT] kms_addfb_basic: executing
11612 16:55:40.976929 ) igt_core-INFO: #1 [<unknown>+0xb57a47e0]
11613 16:55:40.984059 (kms_addfb_basic:436) igt_core-INFO: #2 [<unknown>+0xb57a6278]
11614 16:55:40.993550 (kms_addfb_basic:436) igt_core-INFO: #3 [<unknown>+0xb57a167c]<14>[ 22.862868] [IGT] kms_addfb_basic: exiting, ret=77
11615 16:55:40.993634
11616 16:55:41.000108 (kms_addfb_basic:436) igt_core-INFO: #4 [__libc_start_main+0xe8]
11617 16:55:41.010278 (kms_addfb<8>[ 22.874995] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11618 16:55:41.010533 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11620 16:55:41.013226 _basic:436) igt_core-INFO: #5 [<unknown>+0xb57a16b4]
11621 16:55:41.019870 (kms_addfb_basic:436) igt_core-INFO: #6 [<unknown>+0xb57a16b4]
11622 16:55:41.019952 **** END ****
11623 16:55:41.026611 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11624 16:55:41.029933 Test requirement<14>[ 22.901477] [IGT] kms_addfb_basic: executing
11625 16:55:41.036460 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11626 16:55:41.039433 Test requirement: is_i915_device(fd)
11627 16:55:41.052561 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 22.921536] [IGT] kms_addfb_basic: exiting, ret=77
11628 16:55:41.052667 est.c:721:
11629 16:55:41.056060 Test requirement: is_i915_device(fd)
11630 16:55:41.065872 No KMS driver or no outputs, p<8>[ 22.933601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11631 16:55:41.066159 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11633 16:55:41.069416 ipes: 8, outputs: 0
11634 16:55:41.072270 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11635 16:55:41.076020 Opened device: /dev/dri/card0
11636 16:55:41.082167 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11637 16:55:41.088768 Test requ<14>[ 22.958946] [IGT] kms_addfb_basic: executing
11638 16:55:41.092267 irement: is_i915_device(fd)
11639 16:55:41.095402 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11640 16:55:41.105663 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11641 16:55:41.108735 <14>[ 22.979342] [IGT] kms_addfb_basic: exiting, ret=77
11642 16:55:41.111780 Test requirement: is_i915_device(fd)
11643 16:55:41.125636 No KMS driver or no outputs, pipes: 8, out<8>[ 22.991418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11644 16:55:41.125721 puts: 0
11645 16:55:41.125959 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11647 16:55:41.131593 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11648 16:55:41.135459 Opened device: /dev/dri/card0
11649 16:55:41.142061 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11650 16:55:41.148110 Test requirement: is_<14>[ 23.017430] [IGT] kms_addfb_basic: executing
11651 16:55:41.148197 i915_device(fd)
11652 16:55:41.155034 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11653 16:55:41.161380 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11654 16:55:41.167929 Test requirement: is_<14>[ 23.037438] [IGT] kms_addfb_basic: exiting, ret=77
11655 16:55:41.168013 i915_device(fd)
11656 16:55:41.174734 No KMS driver or no outputs, pipes: 8, outputs: 0
11657 16:55:41.181031 IGT-Version:<8>[ 23.049455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11658 16:55:41.181290 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11660 16:55:41.187724 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11661 16:55:41.187811 Opened device: /dev/dri/card0
11662 16:55:41.197957 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11663 16:55:41.200788 Test requirement: is_i915_device(fd)
11664 16:55:41.204200 [1m<14>[ 23.074980] [IGT] kms_addfb_basic: executing
11665 16:55:41.210724 Subtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11666 16:55:41.217406 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11667 16:55:41.223981 Test requirement: is_i915_devic<14>[ 23.094990] [IGT] kms_addfb_basic: exiting, ret=77
11668 16:55:41.227630 e(fd)
11669 16:55:41.230595 No KMS driver or no outputs, pipes: 8, outputs: 0
11670 16:55:41.240336 IGT-Version: 1.27.1-g7<8>[ 23.107354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11671 16:55:41.240597 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11673 16:55:41.243869 66edf9 (aarch64) (Linux: 6.1.31 aarch64)
11674 16:55:41.246928 Opened device: /dev/dri/card0
11675 16:55:41.253764 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11676 16:55:41.257191 Test requirement: is_i915_device(fd)
11677 16:55:41.263547 Test requireme<14>[ 23.132622] [IGT] kms_addfb_basic: executing
11678 16:55:41.269908 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11679 16:55:41.273255 Test requirement: is_i915_device(fd)
11680 16:55:41.276635 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11681 16:55:41.283410 No KMS driver or<14>[ 23.153055] [IGT] kms_addfb_basic: exiting, ret=77
11682 16:55:41.286474 no outputs, pipes: 8, outputs: 0
11683 16:55:41.296808 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux<8>[ 23.165084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11684 16:55:41.297067 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11686 16:55:41.299727 : 6.1.31 aarch64)
11687 16:55:41.299811 Opened device: /dev/dri/card0
11688 16:55:41.309768 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11689 16:55:41.312731 Test requirement: is_i915_device(fd)
11690 16:55:41.319622 Test requirement not met in function <14>[ 23.189467] [IGT] kms_addfb_basic: executing
11691 16:55:41.322617 igt_require_i915, file ../lib/drmtest.c:721:
11692 16:55:41.326093 Test requirement: is_i915_device(fd)
11693 16:55:41.332768 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11694 16:55:41.338845 No KMS driver or no outputs, pipes<14>[ 23.209578] [IGT] kms_addfb_basic: exiting, ret=77
11695 16:55:41.342623 : 8, outputs: 0
11696 16:55:41.345605 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11697 16:55:41.352356 <8>[ 23.221622] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11698 16:55:41.352449
11699 16:55:41.352733 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11701 16:55:41.355388 Opened device: /dev/dri/card0
11702 16:55:41.362073 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11703 16:55:41.365136 Test requirement: is_i915_device(fd)
11704 16:55:41.375356 Test requirement not met in function igt_require_i915, <14>[ 23.246081] [IGT] kms_addfb_basic: executing
11705 16:55:41.378674 file ../lib/drmtest.c:721:
11706 16:55:41.382045 Test requirement: is_i915_device(fd)
11707 16:55:41.385232 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11708 16:55:41.391426 No KMS driver or no outputs, pipes: 8, outputs: 0
11709 16:55:41.394775 IGT-Ver<14>[ 23.266426] [IGT] kms_addfb_basic: exiting, ret=77
11710 16:55:41.401616 sion: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11711 16:55:41.411380 Opened device: /dev/dri<8>[ 23.278153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11712 16:55:41.411463 /card0
11713 16:55:41.411701 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11715 16:55:41.417897 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11716 16:55:41.421449 Test requirement: is_i915_device(fd)
11717 16:55:41.430962 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 23.302801] [IGT] kms_addfb_basic: executing
11718 16:55:41.434509 1:
11719 16:55:41.437637 Test requirement: is_i915_device(fd)
11720 16:55:41.441385 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11721 16:55:41.444445 No KMS driver or no outputs, pipes: 8, outputs: 0
11722 16:55:41.454196 IGT-Version: 1.27.1-g766edf9 (<14>[ 23.322896] [IGT] kms_addfb_basic: exiting, ret=77
11723 16:55:41.457873 aarch64) (Linux: 6.1.31 aarch64)
11724 16:55:41.457955 Opened device: /dev/dri/card0
11725 16:55:41.467537 Test requiremen<8>[ 23.335175] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11726 16:55:41.467849 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11728 16:55:41.474083 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11729 16:55:41.477623 Test requirement: is_i915_device(fd)
11730 16:55:41.483924 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11731 16:55:41.490359 Test requirement: i<14>[ 23.359954] [IGT] kms_addfb_basic: executing
11732 16:55:41.490455 s_i915_device(fd)
11733 16:55:41.497023 No KMS driver or no outputs, pipes: 8, outputs: 0
11734 16:55:41.500576 [1mSubtest size-max: SKIP (0.000s)[0m
11735 16:55:41.503774 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11736 16:55:41.510291 O<14>[ 23.380122] [IGT] kms_addfb_basic: exiting, ret=77
11737 16:55:41.513294 pened device: /dev/dri/card0
11738 16:55:41.523012 Test requirement not met in function igt_require_i<8>[ 23.392216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11739 16:55:41.523268 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11741 16:55:41.526484 915, file ../lib/drmtest.c:721:
11742 16:55:41.529629 Test requirement: is_i915_device(fd)
11743 16:55:41.536754 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11744 16:55:41.539877 Test requirement: is_i915_device(fd)
11745 16:55:41.546470 No KMS driver or<14>[ 23.416680] [IGT] kms_addfb_basic: executing
11746 16:55:41.549407 no outputs, pipes: 8, outputs: 0
11747 16:55:41.553160 [1mSubtest too-wide: SKIP (0.000s)[0m
11748 16:55:41.559270 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11749 16:55:41.562971 Opened device: /dev/dri/card0
11750 16:55:41.565989 Test <14>[ 23.437039] [IGT] kms_addfb_basic: exiting, ret=77
11751 16:55:41.572488 requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11752 16:55:41.582728 Te<8>[ 23.448943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11753 16:55:41.583023 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11755 16:55:41.585638 st requirement: is_i915_device(fd)
11756 16:55:41.592387 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11757 16:55:41.595848 Test requirement: is_i915_device(fd)
11758 16:55:41.598820 No KMS driver or no outputs, pipes: 8, outputs: 0
11759 16:55:41.605629 <14>[ 23.474866] [IGT] kms_addfb_basic: executing
11760 16:55:41.608508 [1mSubtest too-high: SKIP (0.000s)[0m
11761 16:55:41.615521 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11762 16:55:41.615636 Opened device: /dev/dri/card0
11763 16:55:41.625246 Test requirement not met in function igt<14>[ 23.495234] [IGT] kms_addfb_basic: exiting, ret=77
11764 16:55:41.628608 _require_i915, file ../lib/drmtest.c:721:
11765 16:55:41.632134 Test requirement: is_i915_device(fd)
11766 16:55:41.638496 <8>[ 23.507419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11767 16:55:41.638758 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11769 16:55:41.642103
11770 16:55:41.648334 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11771 16:55:41.651488 Test requirement: is_i915_device(fd)
11772 16:55:41.655182 No KMS driver or no outputs, pipes: 8, outputs: 0
11773 16:55:41.661345 [1mSubtest bo-too-small: SKIP (0.0<14>[ 23.533159] [IGT] kms_addfb_basic: executing
11774 16:55:41.664918 00s)[0m
11775 16:55:41.668115 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11776 16:55:41.671225 Opened device: /dev/dri/card0
11777 16:55:41.684533 Test requirement not met in function igt_require_i915, file ../lib/drmt<14>[ 23.552909] [IGT] kms_addfb_basic: exiting, ret=77
11778 16:55:41.684676 est.c:721:
11779 16:55:41.688145 Test requirement: is_i915_device(fd)
11780 16:55:41.697750 Test requirement not met in fu<8>[ 23.565375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11781 16:55:41.698022 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11783 16:55:41.701341 nction igt_require_i915, file ../lib/drmtest.c:721:
11784 16:55:41.704287 Test requirement: is_i915_device(fd)
11785 16:55:41.710862 No KMS driver or no outputs, pipes: 8, outputs: 0
11786 16:55:41.714371 [1mSubtest small-bo: SKIP (0.000s)[0m
11787 16:55:41.721257 IGT-Version: 1.27.1-g766e<14>[ 23.590929] [IGT] kms_addfb_basic: executing
11788 16:55:41.724228 df9 (aarch64) (Linux: 6.1.31 aarch64)
11789 16:55:41.727325 Opened device: /dev/dri/card0
11790 16:55:41.734420 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11791 16:55:41.740750 Test requirement: is_i9<14>[ 23.611024] [IGT] kms_addfb_basic: exiting, ret=77
11792 16:55:41.744164 15_device(fd)
11793 16:55:41.757261 Test requirement not met in function igt_require_i915, file ../li<8>[ 23.623333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11794 16:55:41.757379 b/drmtest.c:721:
11795 16:55:41.757642 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11797 16:55:41.760453 Test requirement: is_i915_device(fd)
11798 16:55:41.767180 No KMS driver or no outputs, pipes: 8, outputs: 0
11799 16:55:41.770344 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11800 16:55:41.779971 IGT-Version: 1.27.1-g766edf9 (aarch64) (Li<14>[ 23.649612] [IGT] kms_addfb_basic: executing
11801 16:55:41.780053 nux: 6.1.31 aarch64)
11802 16:55:41.783274 Opened device: /dev/dri/card0
11803 16:55:41.789917 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11804 16:55:41.793050 Test requirement: is_i915_device(fd)
11805 16:55:41.800197 Te<14>[ 23.669476] [IGT] kms_addfb_basic: exiting, ret=77
11806 16:55:41.806830 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11807 16:55:41.813178 <8>[ 23.681608] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11808 16:55:41.813268
11809 16:55:41.813511 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11811 16:55:41.819624 Test requirement: is_i915_devic<8>[ 23.691233] <LAVA_SIGNAL_TESTSET STOP>
11812 16:55:41.819706 e(fd)
11813 16:55:41.819950 Received signal: <TESTSET> STOP
11814 16:55:41.820019 Closing test_set kms_addfb_basic
11815 16:55:41.826099 No KMS driver or no outputs, pipes: 8, outputs: 0
11816 16:55:41.829570 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11817 16:55:41.836164 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11818 16:55:41.839800 Opened device: /dev/dri/card0
11819 16:55:41.845740 Test requirement not met in func<8>[ 23.716989] <LAVA_SIGNAL_TESTSET START kms_atomic>
11820 16:55:41.845999 Received signal: <TESTSET> START kms_atomic
11821 16:55:41.846076 Starting test_set kms_atomic
11822 16:55:41.852589 tion igt_require_i915, file ../lib/drmtest.c:721:
11823 16:55:41.856041 Test requirement: is_i915_device(fd)
11824 16:55:41.862696 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11825 16:55:41.869413 Test requirement: is_i915_device(fd)<14>[ 23.739509] [IGT] kms_atomic: executing
11826 16:55:41.869496
11827 16:55:41.875929 No KMS driver <14>[ 23.745048] [IGT] kms_atomic: exiting, ret=77
11828 16:55:41.878817 or no outputs, pipes: 8, outputs: 0
11829 16:55:41.888786 [1mSubtest addfb25-yf-tiled-legacy: SKIP (<8>[ 23.756814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11830 16:55:41.889042 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11832 16:55:41.892424 0.000s)[0m
11833 16:55:41.895434 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11834 16:55:41.898426 Opened device: /dev/dri/card0
11835 16:55:41.905149 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11836 16:55:41.911978 Test requirement:<14>[ 23.782537] [IGT] kms_atomic: executing
11837 16:55:41.918231 is_i915_device(<14>[ 23.788160] [IGT] kms_atomic: exiting, ret=77
11838 16:55:41.918330 fd)
11839 16:55:41.931787 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<8>[ 23.799923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11840 16:55:41.932047 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11842 16:55:41.935220 c:721:
11843 16:55:41.938207 Test requirement: is_i915_device(fd)
11844 16:55:41.941493 No KMS driver or no outputs, pipes: 8, outputs: 0
11845 16:55:41.945018 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11846 16:55:41.954697 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1<14>[ 23.825591] [IGT] kms_atomic: executing
11847 16:55:41.954782 .31 aarch64)
11848 16:55:41.961535 Op<14>[ 23.831131] [IGT] kms_atomic: exiting, ret=77
11849 16:55:41.964557 ened device: /dev/dri/card0
11850 16:55:41.978084 Test requirement not met in function igt_require_i9<8>[ 23.842835] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11851 16:55:41.978359 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11853 16:55:41.981174 15, file ../lib/drmtest.c:721:
11854 16:55:41.984700 Test requirement: is_i915_device(fd)
11855 16:55:41.991377 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11856 16:55:41.994434 Test requirement: is_i915_device(fd)
11857 16:55:41.997551 No KMS driver or <14>[ 23.869858] [IGT] kms_atomic: executing
11858 16:55:42.004150 no outputs, pipe<14>[ 23.875438] [IGT] kms_atomic: exiting, ret=77
11859 16:55:42.007849 s: 8, outputs: 0
11860 16:55:42.010768 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11861 16:55:42.020945 IGT-Version: 1<8>[ 23.887397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11862 16:55:42.021195 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11864 16:55:42.023900 .27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11865 16:55:42.027181 Opened device: /dev/dri/card0
11866 16:55:42.030999 No KMS driver or no outputs, pipes: 8, outputs: 0
11867 16:55:42.037312 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11868 16:55:42.040669 IGT-Version: 1.27.1-g76<14>[ 23.912682] [IGT] kms_atomic: executing
11869 16:55:42.046981 6edf9 (aarch64) <14>[ 23.918515] [IGT] kms_atomic: exiting, ret=77
11870 16:55:42.050474 (Linux: 6.1.31 aarch64)
11871 16:55:42.053422 Opened device: /dev/dri/card0
11872 16:55:42.060472 No KMS driver or no outp<8>[ 23.929844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11873 16:55:42.060725 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11875 16:55:42.064076 uts, pipes: 8, outputs: 0
11876 16:55:42.070341 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11877 16:55:42.073380 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11878 16:55:42.077157 Opened device: /dev/dri/card0
11879 16:55:42.083064 No KMS driver or no outputs, pipe<14>[ 23.954846] [IGT] kms_atomic: executing
11880 16:55:42.090005 s: 8, outputs: 0<14>[ 23.960378] [IGT] kms_atomic: exiting, ret=77
11881 16:55:42.090111
11882 16:55:42.096585 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11883 16:55:42.103527 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11885 16:55:42.106314 IGT-Version<8>[ 23.972048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11886 16:55:42.109926 : 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11887 16:55:42.112946 Opened device: /dev/dri/card0
11888 16:55:42.116241 No KMS driver or no outputs, pipes: 8, outputs: 0
11889 16:55:42.119497 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11890 16:55:42.126251 IGT-Version: 1.27.1-<14>[ 23.997837] [IGT] kms_atomic: executing
11891 16:55:42.133113 g766edf9 (aarch6<14>[ 24.003290] [IGT] kms_atomic: exiting, ret=77
11892 16:55:42.136385 4) (Linux: 6.1.31 aarch64)
11893 16:55:42.139198 Opened device: /dev/dri/card0
11894 16:55:42.148950 No KMS driver or no o<8>[ 24.015097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11895 16:55:42.149038 utputs, pipes: 8, outputs: 0
11896 16:55:42.149277 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11898 16:55:42.152880 [1mSubtest test-only: SKIP (0.000s)[0m
11899 16:55:42.159150 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11900 16:55:42.162678 Opened device: /dev/dri/card0
11901 16:55:42.169472 No KMS driver or no outputs, pipes: 8, ou<14>[ 24.040942] [IGT] kms_atomic: executing
11902 16:55:42.172199 tputs: 0
11903 16:55:42.175869 [1mSu<14>[ 24.046498] [IGT] kms_atomic: exiting, ret=77
11904 16:55:42.178765 btest plane-cursor-legacy: SKIP (0.000s)[0m
11905 16:55:42.192553 IGT-Version: 1.27.1-g766edf9 (aarc<8>[ 24.057932] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11906 16:55:42.192825 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11908 16:55:42.195369 h64) (Linux: 6.1.31 aarch64)
11909 16:55:42.195439 Opened device: /dev/dri/card0
11910 16:55:42.202079 No KMS driver or no outputs, pipes: 8, outputs: 0
11911 16:55:42.205152 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11912 16:55:42.215604 IGT-Version: 1.27.1-g766edf9 (aarch64) (Lin<14>[ 24.084487] [IGT] kms_atomic: executing
11913 16:55:42.218438 ux: 6.1.31 aarch<14>[ 24.089852] [IGT] kms_atomic: exiting, ret=77
11914 16:55:42.222103 64)
11915 16:55:42.222206 Opened device: /dev/dri/card0
11916 16:55:42.235220 No KMS driver or no outputs, pipes: 8, outpu<8>[ 24.101646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11917 16:55:42.235304 ts: 0
11918 16:55:42.235542 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11920 16:55:42.241803 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11921 16:55:42.244960 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11922 16:55:42.248116 Opened device: /dev/dri/card0
11923 16:55:42.258523 No KMS driver or no outputs, pipes: 8, outputs:<14>[ 24.127107] [IGT] kms_atomic: executing
11924 16:55:42.258642 0
11925 16:55:42.261364 [1mSubtest <14>[ 24.132846] [IGT] kms_atomic: exiting, ret=77
11926 16:55:42.264536 crtc-invalid-params: SKIP (0.000s)[0m
11927 16:55:42.278144 IGT-Version: 1.27.1-g766edf9 (aarch64) (<8>[ 24.144600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11928 16:55:42.278401 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11930 16:55:42.281309 Linux: 6.1.31 aarch64)
11931 16:55:42.281391 Opened device: /dev/dri/card0
11932 16:55:42.287875 No KMS driver or no outputs, pipes: 8, outputs: 0
11933 16:55:42.291028 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11934 16:55:42.300150 <14>[ 24.170769] [IGT] kms_atomic: executing
11935 16:55:42.307015 IGT-Version: 1.2<14>[ 24.175515] [IGT] kms_atomic: exiting, ret=77
11936 16:55:42.310191 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11937 16:55:42.313283 Opened device: /dev/dri/card0
11938 16:55:42.319817 N<8>[ 24.187547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11939 16:55:42.320073 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11941 16:55:42.323425 o KMS driver or no outputs, pipes: 8, outputs: 0
11942 16:55:42.329953 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11943 16:55:42.342536 <14>[ 24.213121] [IGT] kms_atomic: executing
11944 16:55:42.349139 IGT-Version: 1.2<14>[ 24.217860] [IGT] kms_atomic: exiting, ret=77
11945 16:55:42.352127 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11946 16:55:42.355882 Opened device: /dev/dri/card0
11947 16:55:42.362523 N<8>[ 24.229750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11948 16:55:42.362781 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11950 16:55:42.368860 o KMS driver or no outputs, pipe<8>[ 24.239995] <LAVA_SIGNAL_TESTSET STOP>
11951 16:55:42.369113 Received signal: <TESTSET> STOP
11952 16:55:42.369183 Closing test_set kms_atomic
11953 16:55:42.372407 s: 8, outputs: 0
11954 16:55:42.375305 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11955 16:55:42.394432 <8>[ 24.265432] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11956 16:55:42.394684 Received signal: <TESTSET> START kms_flip_event_leak
11957 16:55:42.394753 Starting test_set kms_flip_event_leak
11958 16:55:42.417815 <14>[ 24.288528] [IGT] kms_flip_event_leak: executing
11959 16:55:42.424490 IGT-Version: 1.2<14>[ 24.294126] [IGT] kms_flip_event_leak: exiting, ret=77
11960 16:55:42.427506 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11961 16:55:42.430941 Opened device: /dev/dri/card0
11962 16:55:42.437812 N<8>[ 24.306943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11963 16:55:42.438066 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11965 16:55:42.444177 o KMS driver or no outputs, pipe<8>[ 24.315772] <LAVA_SIGNAL_TESTSET STOP>
11966 16:55:42.444429 Received signal: <TESTSET> STOP
11967 16:55:42.444500 Closing test_set kms_flip_event_leak
11968 16:55:42.447419 s: 8, outputs: 0
11969 16:55:42.450910 [1mSubtest basic: SKIP (0.000s)[0m
11970 16:55:42.470422 <8>[ 24.341346] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11971 16:55:42.470730 Received signal: <TESTSET> START kms_prop_blob
11972 16:55:42.470841 Starting test_set kms_prop_blob
11973 16:55:42.492931 <14>[ 24.363916] [IGT] kms_prop_blob: executing
11974 16:55:42.499773 IGT-Version: 1.2<14>[ 24.368766] [IGT] kms_prop_blob: starting subtest basic
11975 16:55:42.506494 7.1-g766edf9 (aa<14>[ 24.375630] [IGT] kms_prop_blob: exiting, ret=0
11976 16:55:42.509401 rch64) (Linux: 6.1.31 aarch64)
11977 16:55:42.513047 Opened device: /dev/dri/card0
11978 16:55:42.519458 Starting subtest:<8>[ 24.388007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11979 16:55:42.519570 basic
11980 16:55:42.519837 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11982 16:55:42.522731 [1mSubtest basic: SUCCESS (0.000s)[0m
11983 16:55:42.541402 <14>[ 24.412398] [IGT] kms_prop_blob: executing
11984 16:55:42.548174 IGT-Version: 1.2<14>[ 24.417338] [IGT] kms_prop_blob: starting subtest blob-prop-core
11985 16:55:42.554808 7.1-g766edf9 (aa<14>[ 24.425011] [IGT] kms_prop_blob: exiting, ret=0
11986 16:55:42.558239 rch64) (Linux: 6.1.31 aarch64)
11987 16:55:42.561186 Opened device: /dev/dri/card0
11988 16:55:42.567800 Starting subtest:<8>[ 24.437583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11989 16:55:42.568057 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11991 16:55:42.571315 blob-prop-core
11992 16:55:42.574400 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11993 16:55:42.592152 <14>[ 24.463158] [IGT] kms_prop_blob: executing
11994 16:55:42.598780 IGT-Version: 1.2<14>[ 24.468084] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11995 16:55:42.605809 7.1-g766edf9 (aa<14>[ 24.476133] [IGT] kms_prop_blob: exiting, ret=0
11996 16:55:42.608814 rch64) (Linux: 6.1.31 aarch64)
11997 16:55:42.611864 Opened device: /dev/dri/card0
11998 16:55:42.621736 Starting subtest:<8>[ 24.488363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11999 16:55:42.621913 blob-prop-validate
12000 16:55:42.622205 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12002 16:55:42.628473 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12003 16:55:42.642898 <14>[ 24.513911] [IGT] kms_prop_blob: executing
12004 16:55:42.649616 IGT-Version: 1.2<14>[ 24.518774] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12005 16:55:42.656303 7.1-g766edf9 (aa<14>[ 24.526821] [IGT] kms_prop_blob: exiting, ret=0
12006 16:55:42.660034 rch64) (Linux: 6.1.31 aarch64)
12007 16:55:42.662829 Opened device: /dev/dri/card0
12008 16:55:42.673086 Starting subtest:<8>[ 24.538774] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12009 16:55:42.673193 blob-prop-lifetime
12010 16:55:42.673460 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12012 16:55:42.679155 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12013 16:55:42.693754 <14>[ 24.564604] [IGT] kms_prop_blob: executing
12014 16:55:42.700577 IGT-Version: 1.2<14>[ 24.569649] [IGT] kms_prop_blob: starting subtest blob-multiple
12015 16:55:42.706980 7.1-g766edf9 (aa<14>[ 24.577352] [IGT] kms_prop_blob: exiting, ret=0
12016 16:55:42.710374 rch64) (Linux: 6.1.31 aarch64)
12017 16:55:42.713743 Opened device: /dev/dri/card0
12018 16:55:42.720053 Starting subtest:<8>[ 24.589596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12019 16:55:42.720306 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12021 16:55:42.723555 blob-multiple
12022 16:55:42.726914 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12023 16:55:42.744147 <14>[ 24.615151] [IGT] kms_prop_blob: executing
12024 16:55:42.750713 IGT-Version: 1.2<14>[ 24.619981] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12025 16:55:42.757846 7.1-g766edf9 (aa<14>[ 24.628339] [IGT] kms_prop_blob: exiting, ret=0
12026 16:55:42.760925 rch64) (Linux: 6.1.31 aarch64)
12027 16:55:42.764109 Opened device: /dev/dri/card0
12028 16:55:42.774398 Starting subtest:<8>[ 24.640597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12029 16:55:42.774490 invalid-get-prop-any
12030 16:55:42.774730 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12032 16:55:42.780358 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12033 16:55:42.795423 <14>[ 24.666284] [IGT] kms_prop_blob: executing
12034 16:55:42.802327 IGT-Version: 1.2<14>[ 24.671114] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12035 16:55:42.808970 7.1-g766edf9 (aa<14>[ 24.678921] [IGT] kms_prop_blob: exiting, ret=0
12036 16:55:42.811843 rch64) (Linux: 6.1.31 aarch64)
12037 16:55:42.815503 Opened device: /dev/dri/card0
12038 16:55:42.821939 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12040 16:55:42.825322 Starting subtest:<8>[ 24.691388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12041 16:55:42.825409 invalid-get-prop
12042 16:55:42.828783 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12043 16:55:42.845742 <14>[ 24.716526] [IGT] kms_prop_blob: executing
12044 16:55:42.852280 IGT-Version: 1.2<14>[ 24.721391] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12045 16:55:42.858919 7.1-g766edf9 (aa<14>[ 24.729533] [IGT] kms_prop_blob: exiting, ret=0
12046 16:55:42.862541 rch64) (Linux: 6.1.31 aarch64)
12047 16:55:42.865511 Opened device: /dev/dri/card0
12048 16:55:42.875536 Starting subtest:<8>[ 24.742053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12049 16:55:42.875677 invalid-set-prop-any
12050 16:55:42.875943 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12052 16:55:42.882291 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12053 16:55:42.896598 <14>[ 24.767529] [IGT] kms_prop_blob: executing
12054 16:55:42.903558 IGT-Version: 1.2<14>[ 24.772498] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12055 16:55:42.910129 7.1-g766edf9 (aa<14>[ 24.780283] [IGT] kms_prop_blob: exiting, ret=0
12056 16:55:42.913482 rch64) (Linux: 6.1.31 aarch64)
12057 16:55:42.916386 Opened device: /dev/dri/card0
12058 16:55:42.926256 Starting subtest:<8>[ 24.792599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12059 16:55:42.926362 invalid-set-prop
12060 16:55:42.926627 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12062 16:55:42.933462 [1mSubtest i<8>[ 24.802550] <LAVA_SIGNAL_TESTSET STOP>
12063 16:55:42.933735 Received signal: <TESTSET> STOP
12064 16:55:42.933813 Closing test_set kms_prop_blob
12065 16:55:42.936273 nvalid-set-prop: SUCCESS (0.000s)[0m
12066 16:55:42.957426 <8>[ 24.828156] <LAVA_SIGNAL_TESTSET START kms_setmode>
12067 16:55:42.957753 Received signal: <TESTSET> START kms_setmode
12068 16:55:42.957841 Starting test_set kms_setmode
12069 16:55:42.979989 <14>[ 24.850417] [IGT] kms_setmode: executing
12070 16:55:42.986433 IGT-Version: 1.2<14>[ 24.855170] [IGT] kms_setmode: starting subtest basic
12071 16:55:42.993271 7.1-g766edf9 (aa<14>[ 24.861798] [IGT] kms_setmode: exiting, ret=77
12072 16:55:42.996398 rch64) (Linux: 6.1.31 aarch64)
12073 16:55:42.996481 Opened device: /dev/dri/card0
12074 16:55:43.005897 Starting subtest:<8>[ 24.874173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12075 16:55:43.005982 basic
12076 16:55:43.006246 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12078 16:55:43.009197 No dynamic tests executed.
12079 16:55:43.012480 [1mSubtest basic: SKIP (0.000s)[0m
12080 16:55:43.027362 <14>[ 24.898198] [IGT] kms_setmode: executing
12081 16:55:43.033959 IGT-Version: 1.2<14>[ 24.902905] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12082 16:55:43.040841 7.1-g766edf9 (aa<14>[ 24.911219] [IGT] kms_setmode: exiting, ret=77
12083 16:55:43.043689 rch64) (Linux: 6.1.31 aarch64)
12084 16:55:43.046904 Opened device: /dev/dri/card0
12085 16:55:43.057000 Starting subtest:<8>[ 24.923561] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12086 16:55:43.057263 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12088 16:55:43.060149 basic-clone-single-crtc
12089 16:55:43.060233 No dynamic tests executed.
12090 16:55:43.066994 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12091 16:55:43.078678 <14>[ 24.949410] [IGT] kms_setmode: executing
12092 16:55:43.085197 IGT-Version: 1.2<14>[ 24.954156] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12093 16:55:43.091810 7.1-g766edf9 (aa<14>[ 24.962523] [IGT] kms_setmode: exiting, ret=77
12094 16:55:43.094941 rch64) (Linux: 6.1.31 aarch64)
12095 16:55:43.098480 Opened device: /dev/dri/card0
12096 16:55:43.108129 Starting subtest:<8>[ 24.974912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12097 16:55:43.108412 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12099 16:55:43.111457 invalid-clone-single-crtc
12100 16:55:43.111599 No dynamic tests executed.
12101 16:55:43.117814 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12102 16:55:43.130435 <14>[ 25.000989] [IGT] kms_setmode: executing
12103 16:55:43.137104 IGT-Version: 1.2<14>[ 25.005706] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12104 16:55:43.143237 7.1-g766edf9 (aa<14>[ 25.014378] [IGT] kms_setmode: exiting, ret=77
12105 16:55:43.146924 rch64) (Linux: 6.1.31 aarch64)
12106 16:55:43.149881 Opened device: /dev/dri/card0
12107 16:55:43.160042 Starting subtest:<8>[ 25.026803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12108 16:55:43.160303 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12110 16:55:43.162957 invalid-clone-exclusive-crtc
12111 16:55:43.166364 No dynamic tests executed.
12112 16:55:43.169406 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12113 16:55:43.181883 <14>[ 25.052753] [IGT] kms_setmode: executing
12114 16:55:43.188271 IGT-Version: 1.2<14>[ 25.057582] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12115 16:55:43.194797 7.1-g766edf9 (aa<14>[ 25.065487] [IGT] kms_setmode: exiting, ret=77
12116 16:55:43.198690 rch64) (Linux: 6.1.31 aarch64)
12117 16:55:43.201813 Opened device: /dev/dri/card0
12118 16:55:43.211545 Starting subtest:<8>[ 25.077826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12119 16:55:43.211666 clone-exclusive-crtc
12120 16:55:43.211905 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12122 16:55:43.214860 No dynamic tests executed.
12123 16:55:43.217982 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12124 16:55:43.232646 <14>[ 25.103481] [IGT] kms_setmode: executing
12125 16:55:43.242766 IGT-Version: 1.2<14>[ 25.108266] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12126 16:55:43.248860 7.1-g766edf9 (aa<14>[ 25.117404] [IGT] kms_setmode: exiting, ret=77
12127 16:55:43.248944 rch64) (Linux: 6.1.31 aarch64)
12128 16:55:43.252630 Opened device: /dev/dri/card0
12129 16:55:43.262462 Starting subtest:<8>[ 25.129763] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12130 16:55:43.262746 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12132 16:55:43.268849 invalid-clone-single-crtc-steal<8>[ 25.141156] <LAVA_SIGNAL_TESTSET STOP>
12133 16:55:43.269099 Received signal: <TESTSET> STOP
12134 16:55:43.269206 Closing test_set kms_setmode
12135 16:55:43.271865 ing
12136 16:55:43.271946 No dynamic tests executed.
12137 16:55:43.278788 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12138 16:55:43.295907 <8>[ 25.167006] <LAVA_SIGNAL_TESTSET START kms_vblank>
12139 16:55:43.296159 Received signal: <TESTSET> START kms_vblank
12140 16:55:43.296227 Starting test_set kms_vblank
12141 16:55:43.318559 <14>[ 25.189351] [IGT] kms_vblank: executing
12142 16:55:43.325002 IGT-Version: 1.2<14>[ 25.194392] [IGT] kms_vblank: exiting, ret=77
12143 16:55:43.328530 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12144 16:55:43.331483 Opened device: /dev/dri/card0
12145 16:55:43.338035 N<8>[ 25.205947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12146 16:55:43.338289 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12148 16:55:43.341508 o KMS driver or no outputs, pipes: 8, outputs: 0
12149 16:55:43.345101 [1mSubtest invalid: SKIP (0.000s)[0m
12150 16:55:43.359858 <14>[ 25.230332] [IGT] kms_vblank: executing
12151 16:55:43.366461 IGT-Version: 1.2<14>[ 25.235288] [IGT] kms_vblank: exiting, ret=77
12152 16:55:43.369239 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12153 16:55:43.373024 Opened device: /dev/dri/card0
12154 16:55:43.379258 N<8>[ 25.247008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12155 16:55:43.379559 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12157 16:55:43.382660 o KMS driver or no outputs, pipes: 8, outputs: 0
12158 16:55:43.385582 [1mSubtest crtc-id: SKIP (0.000s)[0m
12159 16:55:43.400465 <14>[ 25.271395] [IGT] kms_vblank: executing
12160 16:55:43.407242 IGT-Version: 1.2<14>[ 25.276491] [IGT] kms_vblank: exiting, ret=77
12161 16:55:43.410235 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12162 16:55:43.413975 Opened device: /dev/dri/card0
12163 16:55:43.420643 N<8>[ 25.288196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12164 16:55:43.420899 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12166 16:55:43.423795 o KMS driver or no outputs, pipes: 8, outputs: 0
12167 16:55:43.430142 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12168 16:55:43.442953 <14>[ 25.313666] [IGT] kms_vblank: executing
12169 16:55:43.449212 IGT-Version: 1.2<14>[ 25.318850] [IGT] kms_vblank: exiting, ret=77
12170 16:55:43.452921 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12171 16:55:43.455939 Opened device: /dev/dri/card0
12172 16:55:43.462747 N<8>[ 25.330411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12173 16:55:43.463018 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12175 16:55:43.465845 o KMS driver or no outputs, pipes: 8, outputs: 0
12176 16:55:43.472603 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12177 16:55:43.485142 <14>[ 25.355847] [IGT] kms_vblank: executing
12178 16:55:43.491597 IGT-Version: 1.2<14>[ 25.360827] [IGT] kms_vblank: exiting, ret=77
12179 16:55:43.494639 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12180 16:55:43.498144 Opened device: /dev/dri/card0
12181 16:55:43.504572 N<8>[ 25.372421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12182 16:55:43.504835 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12184 16:55:43.508113 o KMS driver or no outputs, pipes: 8, outputs: 0
12185 16:55:43.514898 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12186 16:55:43.527674 <14>[ 25.398264] [IGT] kms_vblank: executing
12187 16:55:43.533783 IGT-Version: 1.2<14>[ 25.403361] [IGT] kms_vblank: exiting, ret=77
12188 16:55:43.537445 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12189 16:55:43.540944 Opened device: /dev/dri/card0
12190 16:55:43.546999 N<8>[ 25.414992] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12191 16:55:43.547262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12193 16:55:43.550672 o KMS driver or no outputs, pipes: 8, outputs: 0
12194 16:55:43.556842 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12195 16:55:43.570799 <14>[ 25.441381] [IGT] kms_vblank: executing
12196 16:55:43.576897 IGT-Version: 1.2<14>[ 25.446322] [IGT] kms_vblank: exiting, ret=77
12197 16:55:43.580736 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12198 16:55:43.583620 Opened device: /dev/dri/card0
12199 16:55:43.590225 N<8>[ 25.457610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12200 16:55:43.590477 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12202 16:55:43.596979 o KMS driver or no outputs, pipes: 8, outputs: 0
12203 16:55:43.600368 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12204 16:55:43.613200 <14>[ 25.483995] [IGT] kms_vblank: executing
12205 16:55:43.620246 IGT-Version: 1.2<14>[ 25.488967] [IGT] kms_vblank: exiting, ret=77
12206 16:55:43.623098 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12207 16:55:43.626858 Opened device: /dev/dri/card0
12208 16:55:43.632880 N<8>[ 25.500045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12209 16:55:43.633124 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12211 16:55:43.636514 o KMS driver or no outputs, pipes: 8, outputs: 0
12212 16:55:43.642601 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12213 16:55:43.655378 <14>[ 25.526005] [IGT] kms_vblank: executing
12214 16:55:43.661625 IGT-Version: 1.2<14>[ 25.531111] [IGT] kms_vblank: exiting, ret=77
12215 16:55:43.664907 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12216 16:55:43.675228 Opened device: /<8>[ 25.541917] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12217 16:55:43.675314 dev/dri/card0
12218 16:55:43.675557 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12220 16:55:43.678335 No KMS driver or no outputs, pipes: 8, outputs: 0
12221 16:55:43.685045 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12222 16:55:43.696959 <14>[ 25.567640] [IGT] kms_vblank: executing
12223 16:55:43.703484 IGT-Version: 1.2<14>[ 25.572614] [IGT] kms_vblank: exiting, ret=77
12224 16:55:43.706544 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12225 16:55:43.709700 Opened device: /dev/dri/card0
12226 16:55:43.716734 N<8>[ 25.583768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12227 16:55:43.716983 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12229 16:55:43.722736 o KMS driver or no outputs, pipes: 8, outputs: 0
12230 16:55:43.726375 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12231 16:55:43.740304 <14>[ 25.611056] [IGT] kms_vblank: executing
12232 16:55:43.746416 IGT-Version: 1.2<14>[ 25.616037] [IGT] kms_vblank: exiting, ret=77
12233 16:55:43.750064 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12234 16:55:43.753005 Opened device: /dev/dri/card0
12235 16:55:43.760171 N<8>[ 25.627295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12236 16:55:43.760441 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12238 16:55:43.766436 o KMS driver or no outputs, pipes: 8, outputs: 0
12239 16:55:43.769700 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12240 16:55:43.783953 <14>[ 25.654962] [IGT] kms_vblank: executing
12241 16:55:43.790804 IGT-Version: 1.2<14>[ 25.659944] [IGT] kms_vblank: exiting, ret=77
12242 16:55:43.793852 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12243 16:55:43.797084 Opened device: /dev/dri/card0
12244 16:55:43.803758 N<8>[ 25.671301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12245 16:55:43.804012 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12247 16:55:43.807382 o KMS driver or no outputs, pipes: 8, outputs: 0
12248 16:55:43.813868 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12249 16:55:43.825918 <14>[ 25.696661] [IGT] kms_vblank: executing
12250 16:55:43.832783 IGT-Version: 1.2<14>[ 25.701690] [IGT] kms_vblank: exiting, ret=77
12251 16:55:43.835747 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12252 16:55:43.838711 Opened device: /dev/dri/card0
12253 16:55:43.845665 N<8>[ 25.712853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12254 16:55:43.845918 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12256 16:55:43.848632 o KMS driver or no outputs, pipes: 8, outputs: 0
12257 16:55:43.855245 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12258 16:55:43.868137 <14>[ 25.739026] [IGT] kms_vblank: executing
12259 16:55:43.874865 IGT-Version: 1.2<14>[ 25.744136] [IGT] kms_vblank: exiting, ret=77
12260 16:55:43.877845 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12261 16:55:43.881410 Opened device: /dev/dri/card0
12262 16:55:43.888154 N<8>[ 25.755236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12263 16:55:43.888409 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12265 16:55:43.891251 o KMS driver or no outputs, pipes: 8, outputs: 0
12266 16:55:43.898012 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12267 16:55:43.910554 <14>[ 25.781065] [IGT] kms_vblank: executing
12268 16:55:43.916619 IGT-Version: 1.2<14>[ 25.786075] [IGT] kms_vblank: exiting, ret=77
12269 16:55:43.920162 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12270 16:55:43.923678 Opened device: /dev/dri/card0
12271 16:55:43.929964 N<8>[ 25.797379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12272 16:55:43.930252 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12274 16:55:43.936555 o KMS driver or no outputs, pipes: 8, outputs: 0
12275 16:55:43.940151 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12276 16:55:43.952844 <14>[ 25.823597] [IGT] kms_vblank: executing
12277 16:55:43.959634 IGT-Version: 1.2<14>[ 25.828648] [IGT] kms_vblank: exiting, ret=77
12278 16:55:43.962490 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12279 16:55:43.972513 Opened device: /<8>[ 25.839563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12280 16:55:43.972596 dev/dri/card0
12281 16:55:43.972855 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12283 16:55:43.976090 No KMS driver or no outputs, pipes: 8, outputs: 0
12284 16:55:43.982509 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12285 16:55:43.993396 <14>[ 25.864048] [IGT] kms_vblank: executing
12286 16:55:43.999852 IGT-Version: 1.2<14>[ 25.869071] [IGT] kms_vblank: exiting, ret=77
12287 16:55:44.002923 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12288 16:55:44.006332 Opened device: /dev/dri/card0
12289 16:55:44.012935 N<8>[ 25.880145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12290 16:55:44.013188 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12292 16:55:44.019201 o KMS driver or no outputs, pipes: 8, outputs: 0
12293 16:55:44.022751 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12294 16:55:44.035795 <14>[ 25.906221] [IGT] kms_vblank: executing
12295 16:55:44.042095 IGT-Version: 1.2<14>[ 25.911474] [IGT] kms_vblank: exiting, ret=77
12296 16:55:44.045504 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12297 16:55:44.048546 Opened device: /dev/dri/card0
12298 16:55:44.055348 N<8>[ 25.922545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12299 16:55:44.055633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12301 16:55:44.058929 o KMS driver or no outputs, pipes: 8, outputs: 0
12302 16:55:44.065310 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12303 16:55:44.078138 <14>[ 25.948767] [IGT] kms_vblank: executing
12304 16:55:44.084413 IGT-Version: 1.2<14>[ 25.953752] [IGT] kms_vblank: exiting, ret=77
12305 16:55:44.088051 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12306 16:55:44.091107 Opened device: /dev/dri/card0
12307 16:55:44.097698 N<8>[ 25.965060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12308 16:55:44.097953 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12310 16:55:44.104278 o KMS driver or no outputs, pipes: 8, outputs: 0
12311 16:55:44.107449 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12312 16:55:44.120809 <14>[ 25.991476] [IGT] kms_vblank: executing
12313 16:55:44.127219 IGT-Version: 1.2<14>[ 25.996607] [IGT] kms_vblank: exiting, ret=77
12314 16:55:44.130794 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12315 16:55:44.133761 Opened device: /dev/dri/card0
12316 16:55:44.140862 N<8>[ 26.007859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12317 16:55:44.141130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12319 16:55:44.147214 o KMS driver or no outputs, pipes: 8, outputs: 0
12320 16:55:44.149973 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12321 16:55:44.163517 <14>[ 26.034551] [IGT] kms_vblank: executing
12322 16:55:44.170244 IGT-Version: 1.2<14>[ 26.039638] [IGT] kms_vblank: exiting, ret=77
12323 16:55:44.173368 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12324 16:55:44.176931 Opened device: /dev/dri/card0
12325 16:55:44.183778 N<8>[ 26.050921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12326 16:55:44.184032 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12328 16:55:44.190327 o KMS driver or no outputs, pipes: 8, outputs: 0
12329 16:55:44.193574 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12330 16:55:44.207150 <14>[ 26.077786] [IGT] kms_vblank: executing
12331 16:55:44.213308 IGT-Version: 1.2<14>[ 26.083000] [IGT] kms_vblank: exiting, ret=77
12332 16:55:44.216799 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12333 16:55:44.219806 Opened device: /dev/dri/card0
12334 16:55:44.226642 N<8>[ 26.093824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12335 16:55:44.226894 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12337 16:55:44.233507 o KMS driver or no outputs, pipes: 8, outputs: 0
12338 16:55:44.236483 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12339 16:55:44.250035 <14>[ 26.120869] [IGT] kms_vblank: executing
12340 16:55:44.256854 IGT-Version: 1.2<14>[ 26.125866] [IGT] kms_vblank: exiting, ret=77
12341 16:55:44.259531 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12342 16:55:44.263237 Opened device: /dev/dri/card0
12343 16:55:44.270110 N<8>[ 26.137105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12344 16:55:44.270364 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12346 16:55:44.276496 o KMS driver or no outputs, pipes: 8, outputs: 0
12347 16:55:44.283146 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12348 16:55:44.293621 <14>[ 26.164394] [IGT] kms_vblank: executing
12349 16:55:44.300060 IGT-Version: 1.2<14>[ 26.169412] [IGT] kms_vblank: exiting, ret=77
12350 16:55:44.303517 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12351 16:55:44.306997 Opened device: /dev/dri/card0
12352 16:55:44.313603 N<8>[ 26.180665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12353 16:55:44.313859 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12355 16:55:44.320266 o KMS driver or no outputs, pipes: 8, outputs: 0
12356 16:55:44.323465 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12357 16:55:44.336678 <14>[ 26.207477] [IGT] kms_vblank: executing
12358 16:55:44.343245 IGT-Version: 1.2<14>[ 26.212455] [IGT] kms_vblank: exiting, ret=77
12359 16:55:44.346359 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12360 16:55:44.350016 Opened device: /dev/dri/card0
12361 16:55:44.356083 N<8>[ 26.223839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12362 16:55:44.356358 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12364 16:55:44.363077 o KMS driver or no outputs, pipes: 8, outputs: 0
12365 16:55:44.366186 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12366 16:55:44.379743 <14>[ 26.250462] [IGT] kms_vblank: executing
12367 16:55:44.385903 IGT-Version: 1.2<14>[ 26.255466] [IGT] kms_vblank: exiting, ret=77
12368 16:55:44.389456 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12369 16:55:44.392694 Opened device: /dev/dri/card0
12370 16:55:44.399206 N<8>[ 26.266750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12371 16:55:44.399477 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12373 16:55:44.405804 o KMS driver or no outputs, pipes: 8, outputs: 0
12374 16:55:44.412338 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12375 16:55:44.422983 <14>[ 26.293775] [IGT] kms_vblank: executing
12376 16:55:44.429142 IGT-Version: 1.2<14>[ 26.298910] [IGT] kms_vblank: exiting, ret=77
12377 16:55:44.432839 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12378 16:55:44.435886 Opened device: /dev/dri/card0
12379 16:55:44.442505 N<8>[ 26.309899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12380 16:55:44.442806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12382 16:55:44.449266 o KMS driver or no outputs, pipes: 8, outputs: 0
12383 16:55:44.455360 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12384 16:55:44.465986 <14>[ 26.337106] [IGT] kms_vblank: executing
12385 16:55:44.472804 IGT-Version: 1.2<14>[ 26.342091] [IGT] kms_vblank: exiting, ret=77
12386 16:55:44.476078 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12387 16:55:44.479419 Opened device: /dev/dri/card0
12388 16:55:44.486055 N<8>[ 26.353564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12389 16:55:44.486330 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12391 16:55:44.489107 o KMS driver or no outputs, pipes: 8, outputs: 0
12392 16:55:44.495327 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12393 16:55:44.508511 <14>[ 26.379146] [IGT] kms_vblank: executing
12394 16:55:44.515052 IGT-Version: 1.2<14>[ 26.384149] [IGT] kms_vblank: exiting, ret=77
12395 16:55:44.518004 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12396 16:55:44.521660 Opened device: /dev/dri/card0
12397 16:55:44.527989 N<8>[ 26.395571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12398 16:55:44.528266 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12400 16:55:44.530907 o KMS driver or no outputs, pipes: 8, outputs: 0
12401 16:55:44.537792 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12402 16:55:44.550320 <14>[ 26.421113] [IGT] kms_vblank: executing
12403 16:55:44.556502 IGT-Version: 1.2<14>[ 26.426122] [IGT] kms_vblank: exiting, ret=77
12404 16:55:44.560061 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12405 16:55:44.563105 Opened device: /dev/dri/card0
12406 16:55:44.569689 N<8>[ 26.437417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12407 16:55:44.569944 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12409 16:55:44.576167 o KMS driver or no outputs, pipes: 8, outputs: 0
12410 16:55:44.579835 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12411 16:55:44.592877 <14>[ 26.463461] [IGT] kms_vblank: executing
12412 16:55:44.599025 IGT-Version: 1.2<14>[ 26.468534] [IGT] kms_vblank: exiting, ret=77
12413 16:55:44.602664 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12414 16:55:44.605573 Opened device: /dev/dri/card0
12415 16:55:44.612044 N<8>[ 26.479829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12416 16:55:44.612295 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12418 16:55:44.615343 o KMS driver or no outputs, pipes: 8, outputs: 0
12419 16:55:44.622303 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12420 16:55:44.634388 <14>[ 26.505502] [IGT] kms_vblank: executing
12421 16:55:44.640884 IGT-Version: 1.2<14>[ 26.510737] [IGT] kms_vblank: exiting, ret=77
12422 16:55:44.644596 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12423 16:55:44.648032 Opened device: /dev/dri/card0
12424 16:55:44.654184 N<8>[ 26.521874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12425 16:55:44.654449 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12427 16:55:44.660799 o KMS driver or no outputs, pipes: 8, outputs: 0
12428 16:55:44.664507 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12429 16:55:44.676973 <14>[ 26.547995] [IGT] kms_vblank: executing
12430 16:55:44.683384 IGT-Version: 1.2<14>[ 26.553099] [IGT] kms_vblank: exiting, ret=77
12431 16:55:44.687122 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12432 16:55:44.690076 Opened device: /dev/dri/card0
12433 16:55:44.696824 N<8>[ 26.564350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12434 16:55:44.697142 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12436 16:55:44.699794 o KMS driver or no outputs, pipes: 8, outputs: 0
12437 16:55:44.706369 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12438 16:55:44.719128 <14>[ 26.589759] [IGT] kms_vblank: executing
12439 16:55:44.725152 IGT-Version: 1.2<14>[ 26.594872] [IGT] kms_vblank: exiting, ret=77
12440 16:55:44.728992 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12441 16:55:44.732044 Opened device: /dev/dri/card0
12442 16:55:44.738866 N<8>[ 26.605993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12443 16:55:44.739115 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12445 16:55:44.741772 o KMS driver or no outputs, pipes: 8, outputs: 0
12446 16:55:44.748254 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12447 16:55:44.761502 <14>[ 26.632182] [IGT] kms_vblank: executing
12448 16:55:44.768211 IGT-Version: 1.2<14>[ 26.637287] [IGT] kms_vblank: exiting, ret=77
12449 16:55:44.771148 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12450 16:55:44.774183 Opened device: /dev/dri/card0
12451 16:55:44.780725 N<8>[ 26.648630] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12452 16:55:44.780988 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12454 16:55:44.787380 o KMS driver or no outputs, pipes: 8, outputs: 0
12455 16:55:44.791047 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12456 16:55:44.803880 <14>[ 26.674740] [IGT] kms_vblank: executing
12457 16:55:44.810277 IGT-Version: 1.2<14>[ 26.679753] [IGT] kms_vblank: exiting, ret=77
12458 16:55:44.814041 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12459 16:55:44.816986 Opened device: /dev/dri/card0
12460 16:55:44.823483 N<8>[ 26.691045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12461 16:55:44.823741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12463 16:55:44.829693 o KMS driver or no outputs, pipes: 8, outputs: 0
12464 16:55:44.833218 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12465 16:55:44.847036 <14>[ 26.717968] [IGT] kms_vblank: executing
12466 16:55:44.853493 IGT-Version: 1.2<14>[ 26.723119] [IGT] kms_vblank: exiting, ret=77
12467 16:55:44.857140 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12468 16:55:44.859987 Opened device: /dev/dri/card0
12469 16:55:44.866626 N<8>[ 26.734378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12470 16:55:44.866898 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12472 16:55:44.870052 o KMS driver or no outputs, pipes: 8, outputs: 0
12473 16:55:44.876622 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12474 16:55:44.889166 <14>[ 26.760011] [IGT] kms_vblank: executing
12475 16:55:44.895709 IGT-Version: 1.2<14>[ 26.765087] [IGT] kms_vblank: exiting, ret=77
12476 16:55:44.898868 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12477 16:55:44.902411 Opened device: /dev/dri/card0
12478 16:55:44.908797 N<8>[ 26.776262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12479 16:55:44.909066 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12481 16:55:44.912046 o KMS driver or no outputs, pipes: 8, outputs: 0
12482 16:55:44.918819 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12483 16:55:44.931237 <14>[ 26.802421] [IGT] kms_vblank: executing
12484 16:55:44.937834 IGT-Version: 1.2<14>[ 26.807429] [IGT] kms_vblank: exiting, ret=77
12485 16:55:44.941634 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12486 16:55:44.944862 Opened device: /dev/dri/card0
12487 16:55:44.951297 N<8>[ 26.818664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12488 16:55:44.951551 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12490 16:55:44.954504 o KMS driver or no outputs, pipes: 8, outputs: 0
12491 16:55:44.961082 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12492 16:55:44.973493 <14>[ 26.844483] [IGT] kms_vblank: executing
12493 16:55:44.980448 IGT-Version: 1.2<14>[ 26.849580] [IGT] kms_vblank: exiting, ret=77
12494 16:55:44.983248 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12495 16:55:44.986450 Opened device: /dev/dri/card0
12496 16:55:44.992971 N<8>[ 26.860782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12497 16:55:44.993227 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12499 16:55:44.999568 o KMS driver or no outputs, pipes: 8, outputs: 0
12500 16:55:45.003108 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12501 16:55:45.015935 <14>[ 26.886971] [IGT] kms_vblank: executing
12502 16:55:45.022984 IGT-Version: 1.2<14>[ 26.892008] [IGT] kms_vblank: exiting, ret=77
12503 16:55:45.025833 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12504 16:55:45.029428 Opened device: /dev/dri/card0
12505 16:55:45.035831 N<8>[ 26.903421] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12506 16:55:45.036084 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12508 16:55:45.038925 o KMS driver or no outputs, pipes: 8, outputs: 0
12509 16:55:45.045486 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12510 16:55:45.057921 <14>[ 26.928978] [IGT] kms_vblank: executing
12511 16:55:45.064648 IGT-Version: 1.2<14>[ 26.934044] [IGT] kms_vblank: exiting, ret=77
12512 16:55:45.067607 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12513 16:55:45.071279 Opened device: /dev/dri/card0
12514 16:55:45.077824 N<8>[ 26.945310] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12515 16:55:45.078079 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12517 16:55:45.080850 o KMS driver or no outputs, pipes: 8, outputs: 0
12518 16:55:45.087442 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12519 16:55:45.100039 <14>[ 26.971213] [IGT] kms_vblank: executing
12520 16:55:45.107259 IGT-Version: 1.2<14>[ 26.976338] [IGT] kms_vblank: exiting, ret=77
12521 16:55:45.110432 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12522 16:55:45.113435 Opened device: /dev/dri/card0
12523 16:55:45.120316 N<8>[ 26.987701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12524 16:55:45.120570 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12526 16:55:45.126318 o KMS driver or no outputs, pipes: 8, outputs: 0
12527 16:55:45.129567 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12528 16:55:45.142591 <14>[ 27.013913] [IGT] kms_vblank: executing
12529 16:55:45.149275 IGT-Version: 1.2<14>[ 27.019140] [IGT] kms_vblank: exiting, ret=77
12530 16:55:45.153066 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12531 16:55:45.156050 Opened device: /dev/dri/card0
12532 16:55:45.162285 N<8>[ 27.030453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12533 16:55:45.162565 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12535 16:55:45.168918 o KMS driver or no outputs, pipes: 8, outputs: 0
12536 16:55:45.172277 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12537 16:55:45.186162 <14>[ 27.057091] [IGT] kms_vblank: executing
12538 16:55:45.192821 IGT-Version: 1.2<14>[ 27.062088] [IGT] kms_vblank: exiting, ret=77
12539 16:55:45.196221 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12540 16:55:45.199373 Opened device: /dev/dri/card0
12541 16:55:45.205856 N<8>[ 27.073426] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12542 16:55:45.206127 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12544 16:55:45.212647 o KMS driver or no outputs, pipes: 8, outputs: 0
12545 16:55:45.215603 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12546 16:55:45.229178 <14>[ 27.099874] [IGT] kms_vblank: executing
12547 16:55:45.235251 IGT-Version: 1.2<14>[ 27.105012] [IGT] kms_vblank: exiting, ret=77
12548 16:55:45.238642 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12549 16:55:45.241979 Opened device: /dev/dri/card0
12550 16:55:45.248581 N<8>[ 27.116283] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12551 16:55:45.248837 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12553 16:55:45.254953 o KMS driver or no outputs, pipes: 8, outputs: 0
12554 16:55:45.258578 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12555 16:55:45.272321 <14>[ 27.143253] [IGT] kms_vblank: executing
12556 16:55:45.278863 IGT-Version: 1.2<14>[ 27.148378] [IGT] kms_vblank: exiting, ret=77
12557 16:55:45.282524 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12558 16:55:45.285178 Opened device: /dev/dri/card0
12559 16:55:45.292086 N<8>[ 27.159775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12560 16:55:45.292363 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12562 16:55:45.298555 o KMS driver or no outputs, pipes: 8, outputs: 0
12563 16:55:45.301663 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12564 16:55:45.315780 <14>[ 27.186741] [IGT] kms_vblank: executing
12565 16:55:45.321923 IGT-Version: 1.2<14>[ 27.191739] [IGT] kms_vblank: exiting, ret=77
12566 16:55:45.325480 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12567 16:55:45.328556 Opened device: /dev/dri/card0
12568 16:55:45.335444 N<8>[ 27.203087] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12569 16:55:45.335721 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12571 16:55:45.341977 o KMS driver or no outputs, pipes: 8, outputs: 0
12572 16:55:45.348268 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12573 16:55:45.359365 <14>[ 27.230661] [IGT] kms_vblank: executing
12574 16:55:45.365932 IGT-Version: 1.2<14>[ 27.235687] [IGT] kms_vblank: exiting, ret=77
12575 16:55:45.369505 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12576 16:55:45.373009 Opened device: /dev/dri/card0
12577 16:55:45.379451 N<8>[ 27.247145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12578 16:55:45.379781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12580 16:55:45.386214 o KMS driver or no outputs, pipes: 8, outputs: 0
12581 16:55:45.389267 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12582 16:55:45.402557 <14>[ 27.273690] [IGT] kms_vblank: executing
12583 16:55:45.409296 IGT-Version: 1.2<14>[ 27.278820] [IGT] kms_vblank: exiting, ret=77
12584 16:55:45.412873 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12585 16:55:45.415731 Opened device: /dev/dri/card0
12586 16:55:45.422346 N<8>[ 27.289866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12587 16:55:45.422621 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12589 16:55:45.429029 o KMS driver or no outputs, pipes: 8, outputs: 0
12590 16:55:45.432160 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12591 16:55:45.445800 <14>[ 27.316758] [IGT] kms_vblank: executing
12592 16:55:45.452495 IGT-Version: 1.2<14>[ 27.321774] [IGT] kms_vblank: exiting, ret=77
12593 16:55:45.455524 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12594 16:55:45.458655 Opened device: /dev/dri/card0
12595 16:55:45.465469 N<8>[ 27.333045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12596 16:55:45.465724 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12598 16:55:45.472295 o KMS driver or no outputs, pipes: 8, outputs: 0
12599 16:55:45.478873 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12600 16:55:45.489296 <14>[ 27.360329] [IGT] kms_vblank: executing
12601 16:55:45.495701 IGT-Version: 1.2<14>[ 27.365333] [IGT] kms_vblank: exiting, ret=77
12602 16:55:45.499246 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12603 16:55:45.502129 Opened device: /dev/dri/card0
12604 16:55:45.508893 N<8>[ 27.376627] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12605 16:55:45.509162 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12607 16:55:45.515374 o KMS driver or no outputs, pipes: 8, outputs: 0
12608 16:55:45.521834 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12609 16:55:45.533006 <14>[ 27.403917] [IGT] kms_vblank: executing
12610 16:55:45.539694 IGT-Version: 1.2<14>[ 27.409005] [IGT] kms_vblank: exiting, ret=77
12611 16:55:45.542931 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12612 16:55:45.545923 Opened device: /dev/dri/card0
12613 16:55:45.552559 N<8>[ 27.420340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12614 16:55:45.552811 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12616 16:55:45.556280 o KMS driver or no outputs, pipes: 8, outputs: 0
12617 16:55:45.563124 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12618 16:55:45.575311 <14>[ 27.446351] [IGT] kms_vblank: executing
12619 16:55:45.581710 IGT-Version: 1.2<14>[ 27.451470] [IGT] kms_vblank: exiting, ret=77
12620 16:55:45.585416 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12621 16:55:45.588940 Opened device: /dev/dri/card0
12622 16:55:45.594768 N<8>[ 27.462894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12623 16:55:45.595021 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12625 16:55:45.598314 o KMS driver or no outputs, pipes: 8, outputs: 0
12626 16:55:45.604853 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12627 16:55:45.617776 <14>[ 27.488659] [IGT] kms_vblank: executing
12628 16:55:45.624415 IGT-Version: 1.2<14>[ 27.493742] [IGT] kms_vblank: exiting, ret=77
12629 16:55:45.627228 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12630 16:55:45.631066 Opened device: /dev/dri/card0
12631 16:55:45.637129 N<8>[ 27.505195] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12632 16:55:45.637385 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12634 16:55:45.643943 o KMS driver or no outputs, pipes: 8, outputs: 0
12635 16:55:45.646999 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12636 16:55:45.660274 <14>[ 27.531313] [IGT] kms_vblank: executing
12637 16:55:45.667199 IGT-Version: 1.2<14>[ 27.536302] [IGT] kms_vblank: exiting, ret=77
12638 16:55:45.670134 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12639 16:55:45.673651 Opened device: /dev/dri/card0
12640 16:55:45.679920 N<8>[ 27.547650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12641 16:55:45.680218 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12643 16:55:45.683472 o KMS driver or no outputs, pipes: 8, outputs: 0
12644 16:55:45.689711 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12645 16:55:45.702725 <14>[ 27.573541] [IGT] kms_vblank: executing
12646 16:55:45.709123 IGT-Version: 1.2<14>[ 27.578565] [IGT] kms_vblank: exiting, ret=77
12647 16:55:45.712278 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12648 16:55:45.715856 Opened device: /dev/dri/card0
12649 16:55:45.722264 N<8>[ 27.589661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12650 16:55:45.722524 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12652 16:55:45.728810 o KMS driver or no outputs, pipes: 8, outputs: 0
12653 16:55:45.731763 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12654 16:55:45.745392 <14>[ 27.616165] [IGT] kms_vblank: executing
12655 16:55:45.751492 IGT-Version: 1.2<14>[ 27.621309] [IGT] kms_vblank: exiting, ret=77
12656 16:55:45.755196 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12657 16:55:45.758246 Opened device: /dev/dri/card0
12658 16:55:45.764896 N<8>[ 27.632599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12659 16:55:45.765152 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12661 16:55:45.767945 o KMS driver or no outputs, pipes: 8, outputs: 0
12662 16:55:45.774737 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12663 16:55:45.787531 <14>[ 27.658465] [IGT] kms_vblank: executing
12664 16:55:45.794080 IGT-Version: 1.2<14>[ 27.663615] [IGT] kms_vblank: exiting, ret=77
12665 16:55:45.797623 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12666 16:55:45.800421 Opened device: /dev/dri/card0
12667 16:55:45.806947 N<8>[ 27.674935] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12668 16:55:45.807202 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12670 16:55:45.813832 o KMS driver or no outputs, pipes: 8, outputs: 0
12671 16:55:45.816746 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12672 16:55:45.829708 <14>[ 27.700889] [IGT] kms_vblank: executing
12673 16:55:45.836388 IGT-Version: 1.2<14>[ 27.705911] [IGT] kms_vblank: exiting, ret=77
12674 16:55:45.839939 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12675 16:55:45.842607 Opened device: /dev/dri/card0
12676 16:55:45.849646 N<8>[ 27.717501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12677 16:55:45.850000 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12679 16:55:45.855977 o KMS driver or no outputs, pipes: 8, outputs: 0
12680 16:55:45.859475 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12681 16:55:45.872403 <14>[ 27.743471] [IGT] kms_vblank: executing
12682 16:55:45.879189 IGT-Version: 1.2<14>[ 27.748425] [IGT] kms_vblank: exiting, ret=77
12683 16:55:45.882304 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12684 16:55:45.885765 Opened device: /dev/dri/card0
12685 16:55:45.892184 N<8>[ 27.759922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12686 16:55:45.892452 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12688 16:55:45.898938 o KMS driver or no outputs, pipes: 8, outputs: 0
12689 16:55:45.901728 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12690 16:55:45.915924 <14>[ 27.786599] [IGT] kms_vblank: executing
12691 16:55:45.921924 IGT-Version: 1.2<14>[ 27.791559] [IGT] kms_vblank: exiting, ret=77
12692 16:55:45.925549 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12693 16:55:45.928432 Opened device: /dev/dri/card0
12694 16:55:45.935559 N<8>[ 27.802826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12695 16:55:45.935852 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12697 16:55:45.938773 o KMS driver or no outputs, pipes: 8, outputs: 0
12698 16:55:45.944849 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12699 16:55:45.957555 <14>[ 27.828384] [IGT] kms_vblank: executing
12700 16:55:45.963608 IGT-Version: 1.2<14>[ 27.833395] [IGT] kms_vblank: exiting, ret=77
12701 16:55:45.967267 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12702 16:55:45.970327 Opened device: /dev/dri/card0
12703 16:55:45.977159 N<8>[ 27.844665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12704 16:55:45.977412 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12706 16:55:45.980348 o KMS driver or no outputs, pipes: 8, outputs: 0
12707 16:55:45.987071 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12708 16:55:45.999435 <14>[ 27.870639] [IGT] kms_vblank: executing
12709 16:55:46.006125 IGT-Version: 1.2<14>[ 27.875746] [IGT] kms_vblank: exiting, ret=77
12710 16:55:46.009276 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12711 16:55:46.012741 Opened device: /dev/dri/card0
12712 16:55:46.019358 N<8>[ 27.887242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12713 16:55:46.019624 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12715 16:55:46.022760 o KMS driver or no outputs, pipes: 8, outputs: 0
12716 16:55:46.028753 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12717 16:55:46.041965 <14>[ 27.912819] [IGT] kms_vblank: executing
12718 16:55:46.048113 IGT-Version: 1.2<14>[ 27.917812] [IGT] kms_vblank: exiting, ret=77
12719 16:55:46.051476 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12720 16:55:46.055200 Opened device: /dev/dri/card0
12721 16:55:46.061606 N<8>[ 27.929060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12722 16:55:46.061920 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12724 16:55:46.064983 o KMS driver or no outputs, pipes: 8, outputs: 0
12725 16:55:46.071623 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12726 16:55:46.084386 <14>[ 27.955321] [IGT] kms_vblank: executing
12727 16:55:46.090554 IGT-Version: 1.2<14>[ 27.960295] [IGT] kms_vblank: exiting, ret=77
12728 16:55:46.094171 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12729 16:55:46.097675 Opened device: /dev/dri/card0
12730 16:55:46.104181 N<8>[ 27.971610] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12731 16:55:46.104436 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12733 16:55:46.107277 o KMS driver or no outputs, pipes: 8, outputs: 0
12734 16:55:46.114269 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12735 16:55:46.126141 <14>[ 27.997058] [IGT] kms_vblank: executing
12736 16:55:46.132318 IGT-Version: 1.2<14>[ 28.002051] [IGT] kms_vblank: exiting, ret=77
12737 16:55:46.135759 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12738 16:55:46.139038 Opened device: /dev/dri/card0
12739 16:55:46.145947 N<8>[ 28.013350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12740 16:55:46.146206 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12742 16:55:46.148813 o KMS driver or no outputs, pipes: 8, outputs: 0
12743 16:55:46.155248 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12744 16:55:46.168194 <14>[ 28.039414] [IGT] kms_vblank: executing
12745 16:55:46.174818 IGT-Version: 1.2<14>[ 28.044397] [IGT] kms_vblank: exiting, ret=77
12746 16:55:46.178022 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12747 16:55:46.181566 Opened device: /dev/dri/card0
12748 16:55:46.187723 N<8>[ 28.055694] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12749 16:55:46.187971 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12751 16:55:46.194599 o KMS driver or no outputs, pipes: 8, outputs: 0
12752 16:55:46.198082 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12753 16:55:46.210734 <14>[ 28.081886] [IGT] kms_vblank: executing
12754 16:55:46.217497 IGT-Version: 1.2<14>[ 28.087174] [IGT] kms_vblank: exiting, ret=77
12755 16:55:46.220485 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12756 16:55:46.224165 Opened device: /dev/dri/card0
12757 16:55:46.230088 N<8>[ 28.098137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12758 16:55:46.230338 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12760 16:55:46.236716 o KMS driver or no outputs, pipes: 8, outputs: 0
12761 16:55:46.240345 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12762 16:55:46.253705 <14>[ 28.124843] [IGT] kms_vblank: executing
12763 16:55:46.260099 IGT-Version: 1.2<14>[ 28.129868] [IGT] kms_vblank: exiting, ret=77
12764 16:55:46.263443 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12765 16:55:46.266720 Opened device: /dev/dri/card0
12766 16:55:46.273198 N<8>[ 28.141273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12767 16:55:46.273455 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12769 16:55:46.280346 o KMS driver or no outputs, pipes: 8, outputs: 0
12770 16:55:46.283409 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12771 16:55:46.296490 <14>[ 28.167776] [IGT] kms_vblank: executing
12772 16:55:46.303203 IGT-Version: 1.2<14>[ 28.172826] [IGT] kms_vblank: exiting, ret=77
12773 16:55:46.306712 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12774 16:55:46.310140 Opened device: /dev/dri/card0
12775 16:55:46.316280 N<8>[ 28.184104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12776 16:55:46.316529 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12778 16:55:46.323123 o KMS driver or no outputs, pipes: 8, outputs: 0
12779 16:55:46.326168 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12780 16:55:46.341261 <14>[ 28.212055] [IGT] kms_vblank: executing
12781 16:55:46.347762 IGT-Version: 1.2<14>[ 28.217275] [IGT] kms_vblank: exiting, ret=77
12782 16:55:46.350636 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12783 16:55:46.354300 Opened device: /dev/dri/card0
12784 16:55:46.360706 N<8>[ 28.228572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12785 16:55:46.361003 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12787 16:55:46.367430 o KMS driver or no outputs, pipes: 8, outputs: 0
12788 16:55:46.370242 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12789 16:55:46.384173 <14>[ 28.255470] [IGT] kms_vblank: executing
12790 16:55:46.390819 IGT-Version: 1.2<14>[ 28.260526] [IGT] kms_vblank: exiting, ret=77
12791 16:55:46.394514 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12792 16:55:46.397647 Opened device: /dev/dri/card0
12793 16:55:46.403870 N<8>[ 28.271979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12794 16:55:46.404158 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12796 16:55:46.410537 o KMS driver or no outputs, pipes: 8, outputs: 0
12797 16:55:46.417094 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12798 16:55:46.428143 <14>[ 28.299165] [IGT] kms_vblank: executing
12799 16:55:46.434646 IGT-Version: 1.2<14>[ 28.304300] [IGT] kms_vblank: exiting, ret=77
12800 16:55:46.437675 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12801 16:55:46.440977 Opened device: /dev/dri/card0
12802 16:55:46.447779 N<8>[ 28.315625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12803 16:55:46.448042 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12805 16:55:46.454252 o KMS driver or no outputs, pipes: 8, outputs: 0
12806 16:55:46.457842 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12807 16:55:46.471175 <14>[ 28.342576] [IGT] kms_vblank: executing
12808 16:55:46.477786 IGT-Version: 1.2<14>[ 28.347563] [IGT] kms_vblank: exiting, ret=77
12809 16:55:46.481137 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12810 16:55:46.484566 Opened device: /dev/dri/card0
12811 16:55:46.490988 N<8>[ 28.358829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12812 16:55:46.491245 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12814 16:55:46.497794 o KMS driver or no outputs, pipes: 8, outputs: 0
12815 16:55:46.500925 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12816 16:55:46.514264 <14>[ 28.385564] [IGT] kms_vblank: executing
12817 16:55:46.521131 IGT-Version: 1.2<14>[ 28.390652] [IGT] kms_vblank: exiting, ret=77
12818 16:55:46.524220 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12819 16:55:46.527324 Opened device: /dev/dri/card0
12820 16:55:46.534163 N<8>[ 28.401728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12821 16:55:46.534447 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12823 16:55:46.540840 o KMS driver or no outputs, pipes: 8, outputs: 0
12824 16:55:46.547029 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12825 16:55:46.557894 <14>[ 28.429092] [IGT] kms_vblank: executing
12826 16:55:46.564297 IGT-Version: 1.2<14>[ 28.434279] [IGT] kms_vblank: exiting, ret=77
12827 16:55:46.567997 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12828 16:55:46.570858 Opened device: /dev/dri/card0
12829 16:55:46.577520 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12831 16:55:46.580874 N<8>[ 28.445489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12832 16:55:46.584535 o KMS driver or no outputs, pipes: 8, outputs: 0
12833 16:55:46.590737 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12834 16:55:46.601745 <14>[ 28.472617] [IGT] kms_vblank: executing
12835 16:55:46.607991 IGT-Version: 1.2<14>[ 28.477606] [IGT] kms_vblank: exiting, ret=77
12836 16:55:46.611061 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12837 16:55:46.614674 Opened device: /dev/dri/card0
12838 16:55:46.621317 N<8>[ 28.488937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12839 16:55:46.621577 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12841 16:55:46.624403 o KMS driver or no outputs, pipes: 8, outputs: 0
12842 16:55:46.631235 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12843 16:55:46.643825 <14>[ 28.514752] [IGT] kms_vblank: executing
12844 16:55:46.650474 IGT-Version: 1.2<14>[ 28.519730] [IGT] kms_vblank: exiting, ret=77
12845 16:55:46.653577 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12846 16:55:46.657112 Opened device: /dev/dri/card0
12847 16:55:46.663409 N<8>[ 28.531170] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12848 16:55:46.663703 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12850 16:55:46.667025 o KMS driver or no outputs, pipes: 8, outputs: 0
12851 16:55:46.673128 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12852 16:55:46.685447 <14>[ 28.556668] [IGT] kms_vblank: executing
12853 16:55:46.692392 IGT-Version: 1.2<14>[ 28.561656] [IGT] kms_vblank: exiting, ret=77
12854 16:55:46.695281 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12855 16:55:46.698781 Opened device: /dev/dri/card0
12856 16:55:46.705388 N<8>[ 28.573088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12857 16:55:46.705706 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12859 16:55:46.708830 o KMS driver or no outputs, pipes: 8, outputs: 0
12860 16:55:46.715049 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12861 16:55:46.728430 <14>[ 28.599187] [IGT] kms_vblank: executing
12862 16:55:46.734547 IGT-Version: 1.2<14>[ 28.604184] [IGT] kms_vblank: exiting, ret=77
12863 16:55:46.738105 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12864 16:55:46.741163 Opened device: /dev/dri/card0
12865 16:55:46.747868 N<8>[ 28.615581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12866 16:55:46.748137 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12868 16:55:46.750978 o KMS driver or no outputs, pipes: 8, outputs: 0
12869 16:55:46.757587 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12870 16:55:46.770334 <14>[ 28.641522] [IGT] kms_vblank: executing
12871 16:55:46.776821 IGT-Version: 1.2<14>[ 28.646581] [IGT] kms_vblank: exiting, ret=77
12872 16:55:46.780243 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12873 16:55:46.783367 Opened device: /dev/dri/card0
12874 16:55:46.790388 N<8>[ 28.657696] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12875 16:55:46.790641 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12877 16:55:46.793663 o KMS driver or no outputs, pipes: 8, outputs: 0
12878 16:55:46.799878 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12879 16:55:46.813115 <14>[ 28.684012] [IGT] kms_vblank: executing
12880 16:55:46.819261 IGT-Version: 1.2<14>[ 28.689001] [IGT] kms_vblank: exiting, ret=77
12881 16:55:46.822919 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12882 16:55:46.825979 Opened device: /dev/dri/card0
12883 16:55:46.832365 N<8>[ 28.700301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12884 16:55:46.832619 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12886 16:55:46.836065 o KMS driver or no outputs, pipes: 8, outputs: 0
12887 16:55:46.842310 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12888 16:55:46.854895 <14>[ 28.726150] [IGT] kms_vblank: executing
12889 16:55:46.861736 IGT-Version: 1.2<14>[ 28.731290] [IGT] kms_vblank: exiting, ret=77
12890 16:55:46.864695 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12891 16:55:46.867940 Opened device: /dev/dri/card0
12892 16:55:46.874538 N<8>[ 28.742489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12893 16:55:46.874797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12895 16:55:46.878103 o KMS driver or no outputs, pipes: 8, outputs: 0
12896 16:55:46.884255 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12897 16:55:46.897808 <14>[ 28.768772] [IGT] kms_vblank: executing
12898 16:55:46.903992 IGT-Version: 1.2<14>[ 28.773748] [IGT] kms_vblank: exiting, ret=77
12899 16:55:46.907457 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12900 16:55:46.910869 Opened device: /dev/dri/card0
12901 16:55:46.917330 N<8>[ 28.785044] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12902 16:55:46.917604 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12904 16:55:46.923730 o KMS driver or no outputs, pipes: 8, outputs: 0
12905 16:55:46.927304 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12906 16:55:46.940039 <14>[ 28.811474] [IGT] kms_vblank: executing
12907 16:55:46.947069 IGT-Version: 1.2<14>[ 28.816493] [IGT] kms_vblank: exiting, ret=77
12908 16:55:46.950179 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12909 16:55:46.953624 Opened device: /dev/dri/card0
12910 16:55:46.959812 N<8>[ 28.827854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12911 16:55:46.960071 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12913 16:55:46.966669 o KMS driver or no outputs, pipes: 8, outputs: 0
12914 16:55:46.969772 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12915 16:55:46.983443 <14>[ 28.854564] [IGT] kms_vblank: executing
12916 16:55:46.990212 IGT-Version: 1.2<14>[ 28.859565] [IGT] kms_vblank: exiting, ret=77
12917 16:55:46.993127 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12918 16:55:46.996767 Opened device: /dev/dri/card0
12919 16:55:47.003411 N<8>[ 28.870978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12920 16:55:47.003694 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12922 16:55:47.006140 o KMS driver or no outputs, pipes: 8, outputs: 0
12923 16:55:47.013299 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12924 16:55:47.025463 <14>[ 28.896549] [IGT] kms_vblank: executing
12925 16:55:47.031799 IGT-Version: 1.2<14>[ 28.901623] [IGT] kms_vblank: exiting, ret=77
12926 16:55:47.035338 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12927 16:55:47.038302 Opened device: /dev/dri/card0
12928 16:55:47.045165 N<8>[ 28.912850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12929 16:55:47.045422 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12931 16:55:47.048295 o KMS driver or no outputs, pipes: 8, outputs: 0
12932 16:55:47.054878 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12933 16:55:47.067525 <14>[ 28.939069] [IGT] kms_vblank: executing
12934 16:55:47.074188 IGT-Version: 1.2<14>[ 28.944079] [IGT] kms_vblank: exiting, ret=77
12935 16:55:47.077854 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12936 16:55:47.080810 Opened device: /dev/dri/card0
12937 16:55:47.087500 N<8>[ 28.955387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12938 16:55:47.087805 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12940 16:55:47.091173 o KMS driver or no outputs, pipes: 8, outputs: 0
12941 16:55:47.097179 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12942 16:55:47.110348 <14>[ 28.981474] [IGT] kms_vblank: executing
12943 16:55:47.116770 IGT-Version: 1.2<14>[ 28.986566] [IGT] kms_vblank: exiting, ret=77
12944 16:55:47.120115 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12945 16:55:47.123802 Opened device: /dev/dri/card0
12946 16:55:47.130301 N<8>[ 28.997647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12947 16:55:47.130607 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12949 16:55:47.136605 o KMS driver or no outputs, pipes: 8, outputs: 0
12950 16:55:47.140056 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12951 16:55:47.152731 <14>[ 29.023980] [IGT] kms_vblank: executing
12952 16:55:47.159471 IGT-Version: 1.2<14>[ 29.029067] [IGT] kms_vblank: exiting, ret=77
12953 16:55:47.162479 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12954 16:55:47.166106 Opened device: /dev/dri/card0
12955 16:55:47.172639 N<8>[ 29.040409] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12956 16:55:47.172895 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12958 16:55:47.175891 o KMS driver or no outputs, pipes: 8, outputs: 0
12959 16:55:47.182466 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12960 16:55:47.194746 <14>[ 29.066090] [IGT] kms_vblank: executing
12961 16:55:47.201372 IGT-Version: 1.2<14>[ 29.071167] [IGT] kms_vblank: exiting, ret=77
12962 16:55:47.204794 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12963 16:55:47.207807 Opened device: /dev/dri/card0
12964 16:55:47.214820 N<8>[ 29.082557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12965 16:55:47.215073 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12967 16:55:47.217869 o KMS driver or no outputs, pipes: 8, outputs: 0
12968 16:55:47.224275 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12969 16:55:47.237373 <14>[ 29.108470] [IGT] kms_vblank: executing
12970 16:55:47.244150 IGT-Version: 1.2<14>[ 29.113610] [IGT] kms_vblank: exiting, ret=77
12971 16:55:47.247376 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12972 16:55:47.250262 Opened device: /dev/dri/card0
12973 16:55:47.257058 N<8>[ 29.124762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12974 16:55:47.257342 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12976 16:55:47.263754 o KMS driver or no outputs, pipes: 8, outputs: 0
12977 16:55:47.266909 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12978 16:55:47.280884 <14>[ 29.152166] [IGT] kms_vblank: executing
12979 16:55:47.287530 IGT-Version: 1.2<14>[ 29.157402] [IGT] kms_vblank: exiting, ret=77
12980 16:55:47.291191 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12981 16:55:47.294029 Opened device: /dev/dri/card0
12982 16:55:47.300704 N<8>[ 29.168815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12983 16:55:47.300964 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12985 16:55:47.307462 o KMS driver or no outputs, pipes: 8, outputs: 0
12986 16:55:47.310508 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12987 16:55:47.324551 <14>[ 29.195641] [IGT] kms_vblank: executing
12988 16:55:47.331082 IGT-Version: 1.2<14>[ 29.200729] [IGT] kms_vblank: exiting, ret=77
12989 16:55:47.333991 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12990 16:55:47.337598 Opened device: /dev/dri/card0
12991 16:55:47.344304 N<8>[ 29.212037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12992 16:55:47.344565 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12994 16:55:47.350870 o KMS driver or no outputs, pipes: 8, outputs: 0
12995 16:55:47.353691 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
12996 16:55:47.367931 <14>[ 29.238676] [IGT] kms_vblank: executing
12997 16:55:47.374013 IGT-Version: 1.2<14>[ 29.243803] [IGT] kms_vblank: exiting, ret=77
12998 16:55:47.377059 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12999 16:55:47.380754 Opened device: /dev/dri/card0
13000 16:55:47.387450 N<8>[ 29.255142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
13001 16:55:47.387711 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13003 16:55:47.393433 o KMS driver or no outputs, pipes: 8, outputs: 0
13004 16:55:47.396959 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13005 16:55:47.411217 <14>[ 29.282052] [IGT] kms_vblank: executing
13006 16:55:47.417521 IGT-Version: 1.2<14>[ 29.287302] [IGT] kms_vblank: exiting, ret=77
13007 16:55:47.420508 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13008 16:55:47.423867 Opened device: /dev/dri/card0
13009 16:55:47.430750 N<8>[ 29.298667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13010 16:55:47.431036 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13012 16:55:47.437184 o KMS driver or no outputs, pipes: 8, outputs: 0
13013 16:55:47.440813 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13014 16:55:47.454384 <14>[ 29.325374] [IGT] kms_vblank: executing
13015 16:55:47.460832 IGT-Version: 1.2<14>[ 29.330472] [IGT] kms_vblank: exiting, ret=77
13016 16:55:47.463782 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13017 16:55:47.467192 Opened device: /dev/dri/card0
13018 16:55:47.473830 N<8>[ 29.341513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13019 16:55:47.474089 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13021 16:55:47.480445 o KMS driver or no outputs, pipes: 8, outputs: 0
13022 16:55:47.487314 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13023 16:55:47.497581 <14>[ 29.368926] [IGT] kms_vblank: executing
13024 16:55:47.504200 IGT-Version: 1.2<14>[ 29.373999] [IGT] kms_vblank: exiting, ret=77
13025 16:55:47.507295 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13026 16:55:47.510917 Opened device: /dev/dri/card0
13027 16:55:47.517753 N<8>[ 29.385430] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13028 16:55:47.518042 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13030 16:55:47.524353 o KMS driver or no outputs, pipes: 8, outputs: 0
13031 16:55:47.527492 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13032 16:55:47.541113 <14>[ 29.412072] [IGT] kms_vblank: executing
13033 16:55:47.547220 IGT-Version: 1.2<14>[ 29.417171] [IGT] kms_vblank: exiting, ret=77
13034 16:55:47.550771 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13035 16:55:47.554236 Opened device: /dev/dri/card0
13036 16:55:47.560819 N<8>[ 29.428443] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13037 16:55:47.561084 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13039 16:55:47.567325 o KMS driver or no outputs, pipes: 8, outputs: 0
13040 16:55:47.570257 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13041 16:55:47.584487 <14>[ 29.455393] [IGT] kms_vblank: executing
13042 16:55:47.590637 IGT-Version: 1.2<14>[ 29.460613] [IGT] kms_vblank: exiting, ret=77
13043 16:55:47.594327 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13044 16:55:47.597355 Opened device: /dev/dri/card0
13045 16:55:47.604041 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13047 16:55:47.607070 N<8>[ 29.471982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13048 16:55:47.610612 o KMS driver or no outputs, pipes: 8, outputs: 0
13049 16:55:47.617226 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13050 16:55:47.628705 <14>[ 29.500292] [IGT] kms_vblank: executing
13051 16:55:47.635501 IGT-Version: 1.2<14>[ 29.505572] [IGT] kms_vblank: exiting, ret=77
13052 16:55:47.638496 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13053 16:55:47.642120 Opened device: /dev/dri/card0
13054 16:55:47.652149 N<8>[ 29.516906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13055 16:55:47.652408 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13057 16:55:47.655085 o KMS driver or no outputs, pipes: 8, outputs: 0
13058 16:55:47.662107 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13059 16:55:47.672676 <14>[ 29.544282] [IGT] kms_vblank: executing
13060 16:55:47.679597 IGT-Version: 1.2<14>[ 29.549284] [IGT] kms_vblank: exiting, ret=77
13061 16:55:47.683172 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13062 16:55:47.685844 Opened device: /dev/dri/card0
13063 16:55:47.692591 N<8>[ 29.560579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13064 16:55:47.692851 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13066 16:55:47.696087 o KMS driver or no outputs, pipes: 8, outputs: 0
13067 16:55:47.702731 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13068 16:55:47.715350 <14>[ 29.586504] [IGT] kms_vblank: executing
13069 16:55:47.721587 IGT-Version: 1.2<14>[ 29.591580] [IGT] kms_vblank: exiting, ret=77
13070 16:55:47.725383 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13071 16:55:47.728145 Opened device: /dev/dri/card0
13072 16:55:47.734807 N<8>[ 29.602933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13073 16:55:47.735094 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13075 16:55:47.738464 o KMS driver or no outputs, pipes: 8, outputs: 0
13076 16:55:47.744731 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13077 16:55:47.757184 <14>[ 29.628466] [IGT] kms_vblank: executing
13078 16:55:47.763462 IGT-Version: 1.2<14>[ 29.633480] [IGT] kms_vblank: exiting, ret=77
13079 16:55:47.766756 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13080 16:55:47.770335 Opened device: /dev/dri/card0
13081 16:55:47.776801 N<8>[ 29.645015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13082 16:55:47.777058 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13084 16:55:47.783386 o KMS driver or no outputs, pipes: 8, outputs: 0
13085 16:55:47.786850 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13086 16:55:47.799853 <14>[ 29.670873] [IGT] kms_vblank: executing
13087 16:55:47.805945 IGT-Version: 1.2<14>[ 29.675984] [IGT] kms_vblank: exiting, ret=77
13088 16:55:47.809745 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13089 16:55:47.812762 Opened device: /dev/dri/card0
13090 16:55:47.819227 N<8>[ 29.687292] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13091 16:55:47.819484 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13093 16:55:47.822792 o KMS driver or no outputs, pipes: 8, outputs: 0
13094 16:55:47.828899 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13095 16:55:47.842292 <14>[ 29.713099] [IGT] kms_vblank: executing
13096 16:55:47.848200 IGT-Version: 1.2<14>[ 29.718113] [IGT] kms_vblank: exiting, ret=77
13097 16:55:47.851790 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13098 16:55:47.854862 Opened device: /dev/dri/card0
13099 16:55:47.861458 N<8>[ 29.729525] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13100 16:55:47.861720 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13102 16:55:47.868065 o KMS driver or no outputs, pipes: 8, outputs: 0
13103 16:55:47.871546 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13104 16:55:47.884551 <14>[ 29.755856] [IGT] kms_vblank: executing
13105 16:55:47.891229 IGT-Version: 1.2<14>[ 29.760878] [IGT] kms_vblank: exiting, ret=77
13106 16:55:47.894782 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13107 16:55:47.897646 Opened device: /dev/dri/card0
13108 16:55:47.904135 N<8>[ 29.772466] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13109 16:55:47.904391 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13111 16:55:47.907617 o KMS driver or no outputs, pipes: 8, outputs: 0
13112 16:55:47.913854 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13113 16:55:47.927219 <14>[ 29.798141] [IGT] kms_vblank: executing
13114 16:55:47.933268 IGT-Version: 1.2<14>[ 29.803284] [IGT] kms_vblank: exiting, ret=77
13115 16:55:47.936791 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13116 16:55:47.939775 Opened device: /dev/dri/card0
13117 16:55:47.946551 N<8>[ 29.814757] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13118 16:55:47.946806 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13120 16:55:47.953471 o KMS driver or no outputs, pipes: 8, outputs: 0
13121 16:55:47.956383 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13122 16:55:47.969535 <14>[ 29.840691] [IGT] kms_vblank: executing
13123 16:55:47.975971 IGT-Version: 1.2<14>[ 29.845675] [IGT] kms_vblank: exiting, ret=77
13124 16:55:47.979339 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13125 16:55:47.982226 Opened device: /dev/dri/card0
13126 16:55:47.989319 N<8>[ 29.857141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13127 16:55:47.989584 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13129 16:55:47.995990 o KMS driver or no outputs, pipes: 8, outputs: 0
13130 16:55:47.998772 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13131 16:55:48.012624 <14>[ 29.884224] [IGT] kms_vblank: executing
13132 16:55:48.019383 IGT-Version: 1.2<14>[ 29.889259] [IGT] kms_vblank: exiting, ret=77
13133 16:55:48.022853 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13134 16:55:48.025881 Opened device: /dev/dri/card0
13135 16:55:48.032847 N<8>[ 29.900811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13136 16:55:48.033103 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13138 16:55:48.039530 o KMS driver or no outputs, pipes: 8, outputs: 0
13139 16:55:48.042545 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13140 16:55:48.057082 <14>[ 29.928498] [IGT] kms_vblank: executing
13141 16:55:48.063586 IGT-Version: 1.2<14>[ 29.933482] [IGT] kms_vblank: exiting, ret=77
13142 16:55:48.067371 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13143 16:55:48.070589 Opened device: /dev/dri/card0
13144 16:55:48.076983 N<8>[ 29.944880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13145 16:55:48.077243 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13147 16:55:48.080514 o KMS driver or no outputs, pipes: 8, outputs: 0
13148 16:55:48.086853 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13149 16:55:48.098847 <14>[ 29.970380] [IGT] kms_vblank: executing
13150 16:55:48.105450 IGT-Version: 1.2<14>[ 29.975374] [IGT] kms_vblank: exiting, ret=77
13151 16:55:48.108995 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13152 16:55:48.118851 Opened device: /<8>[ 29.986350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13153 16:55:48.118936 dev/dri/card0
13154 16:55:48.119173 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13156 16:55:48.122117 No KMS driver or no outputs, pipes: 8, outputs: 0
13157 16:55:48.128462 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13158 16:55:48.141255 <14>[ 30.012429] [IGT] kms_vblank: executing
13159 16:55:48.147782 IGT-Version: 1.2<14>[ 30.017640] [IGT] kms_vblank: exiting, ret=77
13160 16:55:48.150850 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13161 16:55:48.154376 Opened device: /dev/dri/card0
13162 16:55:48.161062 N<8>[ 30.028820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13163 16:55:48.161361 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13165 16:55:48.164167 o KMS driver or no outputs, pipes: 8, outputs: 0
13166 16:55:48.171077 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13167 16:55:48.183574 <14>[ 30.054635] [IGT] kms_vblank: executing
13168 16:55:48.189806 IGT-Version: 1.2<14>[ 30.059637] [IGT] kms_vblank: exiting, ret=77
13169 16:55:48.193243 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13170 16:55:48.196124 Opened device: /dev/dri/card0
13171 16:55:48.202955 N<8>[ 30.070956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13172 16:55:48.203214 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13174 16:55:48.209469 o KMS driver or no outputs, pipes: 8, outputs: 0
13175 16:55:48.213090 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13176 16:55:48.226833 <14>[ 30.098011] [IGT] kms_vblank: executing
13177 16:55:48.233276 IGT-Version: 1.2<14>[ 30.103397] [IGT] kms_vblank: exiting, ret=77
13178 16:55:48.236844 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13179 16:55:48.239855 Opened device: /dev/dri/card0
13180 16:55:48.246533 N<8>[ 30.114746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13181 16:55:48.246820 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13183 16:55:48.249748 o KMS driver or no outputs, pipes: 8, outputs: 0
13184 16:55:48.256170 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13185 16:55:48.269102 <14>[ 30.140512] [IGT] kms_vblank: executing
13186 16:55:48.275654 IGT-Version: 1.2<14>[ 30.145518] [IGT] kms_vblank: exiting, ret=77
13187 16:55:48.278789 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13188 16:55:48.282450 Opened device: /dev/dri/card0
13189 16:55:48.288424 N<8>[ 30.156735] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13190 16:55:48.288675 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13192 16:55:48.295253 o KMS driver or no outputs, pipes: 8, outputs: 0
13193 16:55:48.298347 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13194 16:55:48.311894 <14>[ 30.183101] [IGT] kms_vblank: executing
13195 16:55:48.318249 IGT-Version: 1.2<14>[ 30.188084] [IGT] kms_vblank: exiting, ret=77
13196 16:55:48.321337 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13197 16:55:48.324749 Opened device: /dev/dri/card0
13198 16:55:48.331308 N<8>[ 30.199212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13199 16:55:48.331593 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13201 16:55:48.337751 o KMS driver or no outputs, pipes: 8, outputs: 0
13202 16:55:48.341182 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13203 16:55:48.354397 <14>[ 30.225719] [IGT] kms_vblank: executing
13204 16:55:48.361114 IGT-Version: 1.2<14>[ 30.230967] [IGT] kms_vblank: exiting, ret=77
13205 16:55:48.364101 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13206 16:55:48.367618 Opened device: /dev/dri/card0
13207 16:55:48.374214 N<8>[ 30.242375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13208 16:55:48.374494 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13210 16:55:48.380944 o KMS driver or no outputs, pipes: 8, outputs: 0
13211 16:55:48.384064 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13212 16:55:48.398409 <14>[ 30.269727] [IGT] kms_vblank: executing
13213 16:55:48.404900 IGT-Version: 1.2<14>[ 30.274745] [IGT] kms_vblank: exiting, ret=77
13214 16:55:48.408279 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13215 16:55:48.411770 Opened device: /dev/dri/card0
13216 16:55:48.418182 N<8>[ 30.286768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13217 16:55:48.418440 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13219 16:55:48.424846 o KMS driver or no outputs, pipes: 8, outputs: 0
13220 16:55:48.427790 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13221 16:55:48.441525 <14>[ 30.312863] [IGT] kms_vblank: executing
13222 16:55:48.448189 IGT-Version: 1.2<14>[ 30.317984] [IGT] kms_vblank: exiting, ret=77
13223 16:55:48.451246 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13224 16:55:48.454397 Opened device: /dev/dri/card0
13225 16:55:48.461399 N<8>[ 30.329193] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13226 16:55:48.461699 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13228 16:55:48.467820 o KMS driver or no outputs, pipes: 8, outputs: 0
13229 16:55:48.470838 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13230 16:55:48.485127 <14>[ 30.356274] [IGT] kms_vblank: executing
13231 16:55:48.491696 IGT-Version: 1.2<14>[ 30.361406] [IGT] kms_vblank: exiting, ret=77
13232 16:55:48.495132 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13233 16:55:48.498318 Opened device: /dev/dri/card0
13234 16:55:48.504488 N<8>[ 30.372499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13235 16:55:48.504768 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13237 16:55:48.511294 o KMS driver or no outputs, pipes: 8, outputs: 0
13238 16:55:48.514768 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13239 16:55:48.528252 <14>[ 30.399518] [IGT] kms_vblank: executing
13240 16:55:48.534762 IGT-Version: 1.2<14>[ 30.404543] [IGT] kms_vblank: exiting, ret=77
13241 16:55:48.538220 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13242 16:55:48.541293 Opened device: /dev/dri/card0
13243 16:55:48.547899 N<8>[ 30.415823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13244 16:55:48.548170 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13246 16:55:48.554768 o KMS driver or no outputs, pipes: 8, outputs: 0
13247 16:55:48.560807 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13248 16:55:48.572538 <14>[ 30.443738] [IGT] kms_vblank: executing
13249 16:55:48.578812 IGT-Version: 1.2<14>[ 30.448716] [IGT] kms_vblank: exiting, ret=77
13250 16:55:48.582377 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13251 16:55:48.585368 Opened device: /dev/dri/card0
13252 16:55:48.592361 N<8>[ 30.460869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13253 16:55:48.592625 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13255 16:55:48.598768 o KMS driver or no outputs, pipes: 8, outputs: 0
13256 16:55:48.601790 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13257 16:55:48.616968 <14>[ 30.488239] [IGT] kms_vblank: executing
13258 16:55:48.623352 IGT-Version: 1.2<14>[ 30.493169] [IGT] kms_vblank: exiting, ret=77
13259 16:55:48.626714 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13260 16:55:48.630200 Opened device: /dev/dri/card0
13261 16:55:48.639660 No KMS driver or <8>[ 30.505589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13262 16:55:48.639927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13264 16:55:48.643071 no outputs, pipes: 8, outputs: 0
13265 16:55:48.646060 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13266 16:55:48.661650 <14>[ 30.533014] [IGT] kms_vblank: executing
13267 16:55:48.667977 IGT-Version: 1.2<14>[ 30.538005] [IGT] kms_vblank: exiting, ret=77
13268 16:55:48.671427 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13269 16:55:48.675076 Opened device: /dev/dri/card0
13270 16:55:48.681223 N<8>[ 30.549289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13271 16:55:48.681481 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13273 16:55:48.687930 o KMS driver or no outputs, pipes: 8, outputs: 0
13274 16:55:48.694145 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13275 16:55:48.704777 <14>[ 30.576425] [IGT] kms_vblank: executing
13276 16:55:48.711738 IGT-Version: 1.2<14>[ 30.581566] [IGT] kms_vblank: exiting, ret=77
13277 16:55:48.714840 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13278 16:55:48.718571 Opened device: /dev/dri/card0
13279 16:55:48.724919 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13281 16:55:48.727783 N<8>[ 30.592609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13282 16:55:48.731050 o KMS driver or no outputs, pipes: 8, outputs: 0
13283 16:55:48.737896 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13284 16:55:48.748816 <14>[ 30.620003] [IGT] kms_vblank: executing
13285 16:55:48.755497 IGT-Version: 1.2<14>[ 30.625121] [IGT] kms_vblank: exiting, ret=77
13286 16:55:48.758649 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13287 16:55:48.761609 Opened device: /dev/dri/card0
13288 16:55:48.768414 N<8>[ 30.636208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13289 16:55:48.768697 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13291 16:55:48.771446 o KMS driver or no outputs, pipes: 8, outputs: 0
13292 16:55:48.777990 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13293 16:55:48.791211 <14>[ 30.662414] [IGT] kms_vblank: executing
13294 16:55:48.797311 IGT-Version: 1.2<14>[ 30.667565] [IGT] kms_vblank: exiting, ret=77
13295 16:55:48.801202 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13296 16:55:48.804185 Opened device: /dev/dri/card0
13297 16:55:48.811080 N<8>[ 30.678712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13298 16:55:48.811366 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13300 16:55:48.814102 o KMS driver or no outputs, pipes: 8, outputs: 0
13301 16:55:48.820563 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13302 16:55:48.833399 <14>[ 30.704588] [IGT] kms_vblank: executing
13303 16:55:48.839798 IGT-Version: 1.2<14>[ 30.709610] [IGT] kms_vblank: exiting, ret=77
13304 16:55:48.843266 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13305 16:55:48.846548 Opened device: /dev/dri/card0
13306 16:55:48.852718 N<8>[ 30.720903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13307 16:55:48.852974 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13309 16:55:48.856149 o KMS driver or no outputs, pipes: 8, outputs: 0
13310 16:55:48.862688 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13311 16:55:48.875936 <14>[ 30.747095] [IGT] kms_vblank: executing
13312 16:55:48.882270 IGT-Version: 1.2<14>[ 30.752095] [IGT] kms_vblank: exiting, ret=77
13313 16:55:48.885663 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13314 16:55:48.889148 Opened device: /dev/dri/card0
13315 16:55:48.895255 N<8>[ 30.763882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13316 16:55:48.895539 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13318 16:55:48.898501 o KMS driver or no outputs, pipes: 8, outputs: 0
13319 16:55:48.905104 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13320 16:55:48.918362 <14>[ 30.790204] [IGT] kms_vblank: executing
13321 16:55:48.925556 IGT-Version: 1.2<14>[ 30.795422] [IGT] kms_vblank: exiting, ret=77
13322 16:55:48.928593 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13323 16:55:48.931665 Opened device: /dev/dri/card0
13324 16:55:48.938580 N<8>[ 30.806754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13325 16:55:48.938848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13327 16:55:48.944831 o KMS driver or no outputs, pipes: 8, outputs: 0
13328 16:55:48.948160 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13329 16:55:48.961812 <14>[ 30.833335] [IGT] kms_vblank: executing
13330 16:55:48.968491 IGT-Version: 1.2<14>[ 30.838485] [IGT] kms_vblank: exiting, ret=77
13331 16:55:48.971964 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13332 16:55:48.975092 Opened device: /dev/dri/card0
13333 16:55:48.981805 N<8>[ 30.849405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13334 16:55:48.982080 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13336 16:55:48.984802 o KMS driver or no outputs, pipes: 8, outputs: 0
13337 16:55:48.991452 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13338 16:55:49.004029 <14>[ 30.875563] [IGT] kms_vblank: executing
13339 16:55:49.010850 IGT-Version: 1.2<14>[ 30.880604] [IGT] kms_vblank: exiting, ret=77
13340 16:55:49.013751 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13341 16:55:49.017570 Opened device: /dev/dri/card0
13342 16:55:49.024291 N<8>[ 30.891876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13343 16:55:49.024544 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13345 16:55:49.027429 o KMS driver or no outputs, pipes: 8, outputs: 0
13346 16:55:49.033724 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13347 16:55:49.046607 <14>[ 30.917963] [IGT] kms_vblank: executing
13348 16:55:49.053084 IGT-Version: 1.2<14>[ 30.923256] [IGT] kms_vblank: exiting, ret=77
13349 16:55:49.056325 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13350 16:55:49.059752 Opened device: /dev/dri/card0
13351 16:55:49.066031 N<8>[ 30.934218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13352 16:55:49.066272 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13354 16:55:49.073043 o KMS driver or no outputs, pipes: 8, outputs: 0
13355 16:55:49.076024 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13356 16:55:49.089493 <14>[ 30.960557] [IGT] kms_vblank: executing
13357 16:55:49.095369 IGT-Version: 1.2<14>[ 30.965580] [IGT] kms_vblank: exiting, ret=77
13358 16:55:49.098814 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13359 16:55:49.102348 Opened device: /dev/dri/card0
13360 16:55:49.109049 N<8>[ 30.976799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13361 16:55:49.109332 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13363 16:55:49.115255 o KMS driver or no outputs, pipes: 8, outputs: 0
13364 16:55:49.118861 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13365 16:55:49.132635 <14>[ 31.003724] [IGT] kms_vblank: executing
13366 16:55:49.138921 IGT-Version: 1.2<14>[ 31.008729] [IGT] kms_vblank: exiting, ret=77
13367 16:55:49.142056 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13368 16:55:49.145875 Opened device: /dev/dri/card0
13369 16:55:49.152010 N<8>[ 31.020023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13370 16:55:49.152285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13372 16:55:49.155496 o KMS driver or no outputs, pipes: 8, outputs: 0
13373 16:55:49.161862 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13374 16:55:49.174335 <14>[ 31.045844] [IGT] kms_vblank: executing
13375 16:55:49.181259 IGT-Version: 1.2<14>[ 31.051090] [IGT] kms_vblank: exiting, ret=77
13376 16:55:49.184203 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13377 16:55:49.187753 Opened device: /dev/dri/card0
13378 16:55:49.193846 N<8>[ 31.062203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13379 16:55:49.194091 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13381 16:55:49.197443 o KMS driver or no outputs, pipes: 8, outputs: 0
13382 16:55:49.203968 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13383 16:55:49.216897 <14>[ 31.088527] [IGT] kms_vblank: executing
13384 16:55:49.223465 IGT-Version: 1.2<14>[ 31.093559] [IGT] kms_vblank: exiting, ret=77
13385 16:55:49.227107 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13386 16:55:49.230136 Opened device: /dev/dri/card0
13387 16:55:49.236918 N<8>[ 31.104903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13388 16:55:49.237165 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13390 16:55:49.240050 o KMS driver or no outputs, pipes: 8, outputs: 0
13391 16:55:49.246740 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13392 16:55:49.259326 <14>[ 31.130812] [IGT] kms_vblank: executing
13393 16:55:49.266256 IGT-Version: 1.2<14>[ 31.135823] [IGT] kms_vblank: exiting, ret=77
13394 16:55:49.269338 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13395 16:55:49.272332 Opened device: /dev/dri/card0
13396 16:55:49.279117 N<8>[ 31.147062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13397 16:55:49.279401 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13399 16:55:49.282545 o KMS driver or no outputs, pipes: 8, outputs: 0
13400 16:55:49.288805 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13401 16:55:49.301492 <14>[ 31.173112] [IGT] kms_vblank: executing
13402 16:55:49.308267 IGT-Version: 1.2<14>[ 31.178208] [IGT] kms_vblank: exiting, ret=77
13403 16:55:49.311917 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13404 16:55:49.314602 Opened device: /dev/dri/card0
13405 16:55:49.321411 N<8>[ 31.189369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13406 16:55:49.321660 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13408 16:55:49.325296 o KMS driver or no outputs, pipes: 8, outputs: 0
13409 16:55:49.331256 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13410 16:55:49.344634 <14>[ 31.216091] [IGT] kms_vblank: executing
13411 16:55:49.350999 IGT-Version: 1.2<14>[ 31.221018] [IGT] kms_vblank: exiting, ret=77
13412 16:55:49.354458 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13413 16:55:49.358216 Opened device: /dev/dri/card0
13414 16:55:49.364625 N<8>[ 31.233347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13415 16:55:49.364911 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13417 16:55:49.367714 o KMS driver or no outputs, pipes: 8, outputs: 0
13418 16:55:49.373997 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13419 16:55:49.387911 <14>[ 31.259609] [IGT] kms_vblank: executing
13420 16:55:49.394721 IGT-Version: 1.2<14>[ 31.264531] [IGT] kms_vblank: exiting, ret=77
13421 16:55:49.397999 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13422 16:55:49.401541 Opened device: /dev/dri/card0
13423 16:55:49.411319 No KMS driver or <8>[ 31.277120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13424 16:55:49.411633 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13426 16:55:49.414493 no outputs, pipes: 8, outputs: 0
13427 16:55:49.417487 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13428 16:55:49.432417 <14>[ 31.303710] [IGT] kms_vblank: executing
13429 16:55:49.439138 IGT-Version: 1.2<14>[ 31.308839] [IGT] kms_vblank: exiting, ret=77
13430 16:55:49.442224 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13431 16:55:49.445313 Opened device: /dev/dri/card0
13432 16:55:49.452003 N<8>[ 31.320573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13433 16:55:49.452277 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13435 16:55:49.458786 o KMS driver or no outputs, pipes: 8, outputs: 0
13436 16:55:49.462045 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13437 16:55:49.475489 <14>[ 31.346879] [IGT] kms_vblank: executing
13438 16:55:49.481922 IGT-Version: 1.2<14>[ 31.351975] [IGT] kms_vblank: exiting, ret=77
13439 16:55:49.485204 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13440 16:55:49.488797 Opened device: /dev/dri/card0
13441 16:55:49.495039 N<8>[ 31.363307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13442 16:55:49.495299 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13444 16:55:49.501561 o KMS driver or no outputs, pipes: 8, outputs: 0
13445 16:55:49.505014 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13446 16:55:49.518820 <14>[ 31.389943] [IGT] kms_vblank: executing
13447 16:55:49.524720 IGT-Version: 1.2<14>[ 31.395160] [IGT] kms_vblank: exiting, ret=77
13448 16:55:49.528197 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13449 16:55:49.531850 Opened device: /dev/dri/card0
13450 16:55:49.537901 N<8>[ 31.406370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13451 16:55:49.538183 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13453 16:55:49.544747 o KMS driver or no outputs, pipes: 8, outputs: 0
13454 16:55:49.551485 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13455 16:55:49.561888 <14>[ 31.433388] [IGT] kms_vblank: executing
13456 16:55:49.568292 IGT-Version: 1.2<14>[ 31.438571] [IGT] kms_vblank: exiting, ret=77
13457 16:55:49.571739 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13458 16:55:49.574782 Opened device: /dev/dri/card0
13459 16:55:49.581534 N<8>[ 31.449643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13460 16:55:49.581795 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13462 16:55:49.588081 o KMS driver or no outputs, pipes: 8, outputs: 0
13463 16:55:49.591446 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13464 16:55:49.605442 <14>[ 31.476814] [IGT] kms_vblank: executing
13465 16:55:49.612045 IGT-Version: 1.2<14>[ 31.481807] [IGT] kms_vblank: exiting, ret=77
13466 16:55:49.614951 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13467 16:55:49.618117 Opened device: /dev/dri/card0
13468 16:55:49.625253 N<8>[ 31.493016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13469 16:55:49.625506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13471 16:55:49.631450 o KMS driver or no outputs, pipes: 8, outputs: 0
13472 16:55:49.638274 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13473 16:55:49.648673 <14>[ 31.520272] [IGT] kms_vblank: executing
13474 16:55:49.655186 IGT-Version: 1.2<14>[ 31.525276] [IGT] kms_vblank: exiting, ret=77
13475 16:55:49.658240 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13476 16:55:49.661902 Opened device: /dev/dri/card0
13477 16:55:49.668013 N<8>[ 31.536478] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13478 16:55:49.668281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13480 16:55:49.674763 o KMS driver or no outputs, pipes: 8, outputs: 0
13481 16:55:49.678418 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13482 16:55:49.691753 <14>[ 31.563481] [IGT] kms_vblank: executing
13483 16:55:49.698352 IGT-Version: 1.2<14>[ 31.568494] [IGT] kms_vblank: exiting, ret=77
13484 16:55:49.701728 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13485 16:55:49.705246 Opened device: /dev/dri/card0
13486 16:55:49.711510 N<8>[ 31.579960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13487 16:55:49.711807 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13489 16:55:49.718032 o KMS driver or no outputs, pipes: 8, outputs: 0
13490 16:55:49.721783 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13491 16:55:49.735304 <14>[ 31.606614] [IGT] kms_vblank: executing
13492 16:55:49.741832 IGT-Version: 1.2<14>[ 31.611738] [IGT] kms_vblank: exiting, ret=77
13493 16:55:49.744863 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13494 16:55:49.748576 Opened device: /dev/dri/card0
13495 16:55:49.754850 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13497 16:55:49.758387 N<8>[ 31.623064] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13498 16:55:49.761460 o KMS driver or no outputs, pipes: 8, outputs: 0
13499 16:55:49.768320 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13500 16:55:49.779111 <14>[ 31.650531] [IGT] kms_vblank: executing
13501 16:55:49.785630 IGT-Version: 1.2<14>[ 31.655557] [IGT] kms_vblank: exiting, ret=77
13502 16:55:49.788873 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13503 16:55:49.792302 Opened device: /dev/dri/card0
13504 16:55:49.798775 N<8>[ 31.666851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13505 16:55:49.799031 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13507 16:55:49.805400 o KMS driver or no outputs, pipes: 8, outputs: 0
13508 16:55:49.812029 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13509 16:55:49.822755 <14>[ 31.694056] [IGT] kms_vblank: executing
13510 16:55:49.829286 IGT-Version: 1.2<14>[ 31.699248] [IGT] kms_vblank: exiting, ret=77
13511 16:55:49.832716 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13512 16:55:49.835785 Opened device: /dev/dri/card0
13513 16:55:49.842471 N<8>[ 31.710621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13514 16:55:49.842737 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13516 16:55:49.845377 o KMS driver or no outputs, pipes: 8, outputs: 0
13517 16:55:49.852062 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13518 16:55:49.865422 <14>[ 31.736723] [IGT] kms_vblank: executing
13519 16:55:49.871958 IGT-Version: 1.2<14>[ 31.741764] [IGT] kms_vblank: exiting, ret=77
13520 16:55:49.874835 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13521 16:55:49.878701 Opened device: /dev/dri/card0
13522 16:55:49.885147 N<8>[ 31.753015] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13523 16:55:49.885403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13525 16:55:49.888319 o KMS driver or no outputs, pipes: 8, outputs: 0
13526 16:55:49.894562 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13527 16:55:49.907704 <14>[ 31.778951] [IGT] kms_vblank: executing
13528 16:55:49.914142 IGT-Version: 1.2<14>[ 31.783932] [IGT] kms_vblank: exiting, ret=77
13529 16:55:49.917131 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13530 16:55:49.920763 Opened device: /dev/dri/card0
13531 16:55:49.927264 N<8>[ 31.795158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13532 16:55:49.927547 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13534 16:55:49.930739 o KMS driver or no outputs, pipes: 8, outputs: 0
13535 16:55:49.936684 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13536 16:55:49.949495 <14>[ 31.821324] [IGT] kms_vblank: executing
13537 16:55:49.956636 IGT-Version: 1.2<14>[ 31.826427] [IGT] kms_vblank: exiting, ret=77
13538 16:55:49.959673 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13539 16:55:49.963227 Opened device: /dev/dri/card0
13540 16:55:49.969402 N<8>[ 31.837572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13541 16:55:49.969663 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13543 16:55:49.973247 o KMS driver or no outputs, pipes: 8, outputs: 0
13544 16:55:49.979882 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13545 16:55:49.991902 <14>[ 31.863550] [IGT] kms_vblank: executing
13546 16:55:49.998413 IGT-Version: 1.2<14>[ 31.868554] [IGT] kms_vblank: exiting, ret=77
13547 16:55:50.002056 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13548 16:55:50.005197 Opened device: /dev/dri/card0
13549 16:55:50.012017 N<8>[ 31.879885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13550 16:55:50.012302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13552 16:55:50.018339 o KMS driver or no outputs, pipes: 8, outputs: 0
13553 16:55:50.021375 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13554 16:55:50.034762 <14>[ 31.906310] [IGT] kms_vblank: executing
13555 16:55:50.041442 IGT-Version: 1.2<14>[ 31.911473] [IGT] kms_vblank: exiting, ret=77
13556 16:55:50.044852 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13557 16:55:50.047932 Opened device: /dev/dri/card0
13558 16:55:50.054190 N<8>[ 31.922675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13559 16:55:50.054462 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13561 16:55:50.057912 o KMS driver or no outputs, pipes: 8, outputs: 0
13562 16:55:50.064235 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13563 16:55:50.076454 <14>[ 31.948296] [IGT] kms_vblank: executing
13564 16:55:50.083265 IGT-Version: 1.2<14>[ 31.953347] [IGT] kms_vblank: exiting, ret=77
13565 16:55:50.086834 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13566 16:55:50.089867 Opened device: /dev/dri/card0
13567 16:55:50.096756 N<8>[ 31.964555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13568 16:55:50.097011 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13570 16:55:50.099914 o KMS driver or no outputs, pipes: 8, outputs: 0
13571 16:55:50.106088 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13572 16:55:50.119279 <14>[ 31.990754] [IGT] kms_vblank: executing
13573 16:55:50.125467 IGT-Version: 1.2<14>[ 31.995746] [IGT] kms_vblank: exiting, ret=77
13574 16:55:50.129091 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13575 16:55:50.132560 Opened device: /dev/dri/card0
13576 16:55:50.138610 N<8>[ 32.007047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13577 16:55:50.138882 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13579 16:55:50.145437 o KMS driver or no outputs, pipes: 8, outputs: 0
13580 16:55:50.148794 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13581 16:55:50.162028 <14>[ 32.033465] [IGT] kms_vblank: executing
13582 16:55:50.168601 IGT-Version: 1.2<14>[ 32.038521] [IGT] kms_vblank: exiting, ret=77
13583 16:55:50.172051 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13584 16:55:50.174990 Opened device: /dev/dri/card0
13585 16:55:50.181314 N<8>[ 32.049532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13586 16:55:50.181597 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13588 16:55:50.188125 o KMS driver or no outputs, pipes: 8, outputs: 0
13589 16:55:50.191018 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13590 16:55:50.204843 <14>[ 32.076611] [IGT] kms_vblank: executing
13591 16:55:50.211280 IGT-Version: 1.2<14>[ 32.081711] [IGT] kms_vblank: exiting, ret=77
13592 16:55:50.214726 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13593 16:55:50.218153 Opened device: /dev/dri/card0
13594 16:55:50.224786 N<8>[ 32.092982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13595 16:55:50.225042 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13597 16:55:50.227746 o KMS driver or no outputs, pipes: 8, outputs: 0
13598 16:55:50.234325 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13599 16:55:50.247013 <14>[ 32.118705] [IGT] kms_vblank: executing
13600 16:55:50.254044 IGT-Version: 1.2<14>[ 32.123697] [IGT] kms_vblank: exiting, ret=77
13601 16:55:50.257008 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13602 16:55:50.260179 Opened device: /dev/dri/card0
13603 16:55:50.266950 N<8>[ 32.134916] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13604 16:55:50.267209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13606 16:55:50.270407 o KMS driver or no outputs, pipes: 8, outputs: 0
13607 16:55:50.276714 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13608 16:55:50.289861 <14>[ 32.161211] [IGT] kms_vblank: executing
13609 16:55:50.296483 IGT-Version: 1.2<14>[ 32.166287] [IGT] kms_vblank: exiting, ret=77
13610 16:55:50.299799 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13611 16:55:50.302783 Opened device: /dev/dri/card0
13612 16:55:50.309449 N<8>[ 32.177439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13613 16:55:50.309705 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13615 16:55:50.312599 o KMS driver or no outputs, pipes: 8, outputs: 0
13616 16:55:50.319463 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13617 16:55:50.332017 <14>[ 32.203284] [IGT] kms_vblank: executing
13618 16:55:50.338082 IGT-Version: 1.2<14>[ 32.208326] [IGT] kms_vblank: exiting, ret=77
13619 16:55:50.341701 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13620 16:55:50.344853 Opened device: /dev/dri/card0
13621 16:55:50.351275 N<8>[ 32.219869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13622 16:55:50.351530 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13624 16:55:50.354835 o KMS driver or no outputs, pipes: 8, outputs: 0
13625 16:55:50.361359 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13626 16:55:50.374003 <14>[ 32.245570] [IGT] kms_vblank: executing
13627 16:55:50.380750 IGT-Version: 1.2<14>[ 32.250641] [IGT] kms_vblank: exiting, ret=77
13628 16:55:50.383734 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13629 16:55:50.387175 Opened device: /dev/dri/card0
13630 16:55:50.394005 N<8>[ 32.261836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13631 16:55:50.394262 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13633 16:55:50.397215 o KMS driver or no outputs, pipes: 8, outputs: 0
13634 16:55:50.403774 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13635 16:55:50.416036 <14>[ 32.287436] [IGT] kms_vblank: executing
13636 16:55:50.422552 IGT-Version: 1.2<14>[ 32.292469] [IGT] kms_vblank: exiting, ret=77
13637 16:55:50.425590 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13638 16:55:50.429077 Opened device: /dev/dri/card0
13639 16:55:50.435732 N<8>[ 32.303749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13640 16:55:50.435991 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13642 16:55:50.439075 o KMS driver or no outputs, pipes: 8, outputs: 0
13643 16:55:50.445359 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13644 16:55:50.458114 <14>[ 32.329895] [IGT] kms_vblank: executing
13645 16:55:50.464941 IGT-Version: 1.2<14>[ 32.335040] [IGT] kms_vblank: exiting, ret=77
13646 16:55:50.468685 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13647 16:55:50.471534 Opened device: /dev/dri/card0
13648 16:55:50.478295 N<8>[ 32.345897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13649 16:55:50.478561 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13651 16:55:50.481576 o KMS driver or no outputs, pipes: 8, outputs: 0
13652 16:55:50.487892 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13653 16:55:50.500764 <14>[ 32.372345] [IGT] kms_vblank: executing
13654 16:55:50.507448 IGT-Version: 1.2<14>[ 32.377498] [IGT] kms_vblank: exiting, ret=77
13655 16:55:50.510399 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13656 16:55:50.514171 Opened device: /dev/dri/card0
13657 16:55:50.520957 N<8>[ 32.388746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13658 16:55:50.521214 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13660 16:55:50.527131 o KMS driver or no outputs, pipes: 8, outputs: 0
13661 16:55:50.530138 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13662 16:55:50.543596 <14>[ 32.415338] [IGT] kms_vblank: executing
13663 16:55:50.550212 IGT-Version: 1.2<14>[ 32.420498] [IGT] kms_vblank: exiting, ret=77
13664 16:55:50.553969 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13665 16:55:50.556969 Opened device: /dev/dri/card0
13666 16:55:50.563797 N<8>[ 32.431796] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13667 16:55:50.564114 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13669 16:55:50.569928 o KMS driver or no outputs, pipes: 8, outputs: 0
13670 16:55:50.573539 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13671 16:55:50.586794 <14>[ 32.458384] [IGT] kms_vblank: executing
13672 16:55:50.593513 IGT-Version: 1.2<14>[ 32.463530] [IGT] kms_vblank: exiting, ret=77
13673 16:55:50.597080 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13674 16:55:50.599843 Opened device: /dev/dri/card0
13675 16:55:50.606701 N<8>[ 32.474855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13676 16:55:50.606975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13678 16:55:50.613360 o KMS driver or no outputs, pipes: 8, outputs: 0
13679 16:55:50.616474 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13680 16:55:50.630380 <14>[ 32.501922] [IGT] kms_vblank: executing
13681 16:55:50.636627 IGT-Version: 1.2<14>[ 32.507196] [IGT] kms_vblank: exiting, ret=77
13682 16:55:50.640233 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13683 16:55:50.643726 Opened device: /dev/dri/card0
13684 16:55:50.649905 N<8>[ 32.518293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13685 16:55:50.650168 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13687 16:55:50.656396 o KMS driver or no outputs, pipes: 8, outputs: 0
13688 16:55:50.659999 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13689 16:55:50.673670 <14>[ 32.545408] [IGT] kms_vblank: executing
13690 16:55:50.680174 IGT-Version: 1.2<14>[ 32.550484] [IGT] kms_vblank: exiting, ret=77
13691 16:55:50.683856 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13692 16:55:50.687281 Opened device: /dev/dri/card0
13693 16:55:50.693378 N<8>[ 32.561665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13694 16:55:50.693638 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13696 16:55:50.699793 o KMS driver or no outputs, pipes: 8, outputs: 0
13697 16:55:50.706488 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13698 16:55:50.717270 <14>[ 32.588846] [IGT] kms_vblank: executing
13699 16:55:50.723848 IGT-Version: 1.2<14>[ 32.593990] [IGT] kms_vblank: exiting, ret=77
13700 16:55:50.727044 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13701 16:55:50.737329 Opened device: /<8>[ 32.604952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13702 16:55:50.737445 dev/dri/card0
13703 16:55:50.737692 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13705 16:55:50.743484 No KMS driver or no outputs, pipes: 8, outputs: 0
13706 16:55:50.747148 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13707 16:55:50.759517 <14>[ 32.631334] [IGT] kms_vblank: executing
13708 16:55:50.766287 IGT-Version: 1.2<14>[ 32.636336] [IGT] kms_vblank: exiting, ret=77
13709 16:55:50.769343 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13710 16:55:50.772748 Opened device: /dev/dri/card0
13711 16:55:50.779437 N<8>[ 32.648022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13712 16:55:50.779727 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13714 16:55:50.786118 o KMS driver or no outputs, pipes: 8, outputs: 0
13715 16:55:50.789129 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13716 16:55:50.802677 <14>[ 32.674591] [IGT] kms_vblank: executing
13717 16:55:50.809783 IGT-Version: 1.2<14>[ 32.679592] [IGT] kms_vblank: exiting, ret=77
13718 16:55:50.812590 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13719 16:55:50.816251 Opened device: /dev/dri/card0
13720 16:55:50.822582 N<8>[ 32.690777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13721 16:55:50.822868 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13723 16:55:50.829122 o KMS driver or no outputs, pipes: 8, outputs: 0
13724 16:55:50.835890 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13725 16:55:50.846485 <14>[ 32.718056] [IGT] kms_vblank: executing
13726 16:55:50.853086 IGT-Version: 1.2<14>[ 32.723128] [IGT] kms_vblank: exiting, ret=77
13727 16:55:50.856153 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13728 16:55:50.859778 Opened device: /dev/dri/card0
13729 16:55:50.866153 N<8>[ 32.734173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13730 16:55:50.866470 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13732 16:55:50.872956 o KMS driver or no outputs, pipes: 8, outputs: 0
13733 16:55:50.879472 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13734 16:55:50.890000 <14>[ 32.761724] [IGT] kms_vblank: executing
13735 16:55:50.896507 IGT-Version: 1.2<14>[ 32.766861] [IGT] kms_vblank: exiting, ret=77
13736 16:55:50.900203 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13737 16:55:50.903211 Opened device: /dev/dri/card0
13738 16:55:50.909810 N<8>[ 32.777973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13739 16:55:50.910092 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13741 16:55:50.913461 o KMS driver or no outputs, pipes: 8, outputs: 0
13742 16:55:50.919753 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13743 16:55:50.932098 <14>[ 32.803903] [IGT] kms_vblank: executing
13744 16:55:50.938952 IGT-Version: 1.2<14>[ 32.809020] [IGT] kms_vblank: exiting, ret=77
13745 16:55:50.942036 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13746 16:55:50.945704 Opened device: /dev/dri/card0
13747 16:55:50.951885 N<8>[ 32.820254] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13748 16:55:50.952134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13750 16:55:50.955640 o KMS driver or no outputs, pipes: 8, outputs: 0
13751 16:55:50.961718 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13752 16:55:50.974481 <14>[ 32.846135] [IGT] kms_vblank: executing
13753 16:55:50.981079 IGT-Version: 1.2<14>[ 32.851333] [IGT] kms_vblank: exiting, ret=77
13754 16:55:50.984786 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13755 16:55:50.987848 Opened device: /dev/dri/card0
13756 16:55:50.994021 N<8>[ 32.862659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13757 16:55:50.994296 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13759 16:55:51.001141 o KMS driver or no outputs, pipes: 8, outputs: 0
13760 16:55:51.004092 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13761 16:55:51.017546 <14>[ 32.888887] [IGT] kms_vblank: executing
13762 16:55:51.023931 IGT-Version: 1.2<14>[ 32.893869] [IGT] kms_vblank: exiting, ret=77
13763 16:55:51.026929 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13764 16:55:51.030296 Opened device: /dev/dri/card0
13765 16:55:51.036747 N<8>[ 32.905020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13766 16:55:51.037026 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13768 16:55:51.040090 o KMS driver or no outputs, pipes: 8, outputs: 0
13769 16:55:51.046978 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13770 16:55:51.059187 <14>[ 32.931112] [IGT] kms_vblank: executing
13771 16:55:51.065694 IGT-Version: 1.2<14>[ 32.936243] [IGT] kms_vblank: exiting, ret=77
13772 16:55:51.068994 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13773 16:55:51.072738 Opened device: /dev/dri/card0
13774 16:55:51.079147 N<8>[ 32.947457] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13775 16:55:51.079406 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13777 16:55:51.085513 o KMS driver or no outputs, pipes: 8, outputs: 0
13778 16:55:51.088828 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13779 16:55:51.102286 <14>[ 32.973793] [IGT] kms_vblank: executing
13780 16:55:51.108439 IGT-Version: 1.2<14>[ 32.978880] [IGT] kms_vblank: exiting, ret=77
13781 16:55:51.112075 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13782 16:55:51.115137 Opened device: /dev/dri/card0
13783 16:55:51.121650 N<8>[ 32.989858] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13784 16:55:51.121906 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13786 16:55:51.125322 o KMS driver or no outputs, pipes: 8, outputs: 0
13787 16:55:51.131823 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13788 16:55:51.143890 <14>[ 33.015719] [IGT] kms_vblank: executing
13789 16:55:51.150764 IGT-Version: 1.2<14>[ 33.020696] [IGT] kms_vblank: exiting, ret=77
13790 16:55:51.153894 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13791 16:55:51.156952 Opened device: /dev/dri/card0
13792 16:55:51.163465 N<8>[ 33.031997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13793 16:55:51.163746 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13795 16:55:51.167076 o KMS driver or no outputs, pipes: 8, outputs: 0
13796 16:55:51.173733 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13797 16:55:51.186517 <14>[ 33.058184] [IGT] kms_vblank: executing
13798 16:55:51.192815 IGT-Version: 1.2<14>[ 33.063292] [IGT] kms_vblank: exiting, ret=77
13799 16:55:51.196633 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13800 16:55:51.199787 Opened device: /dev/dri/card0
13801 16:55:51.206228 N<8>[ 33.074351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13802 16:55:51.206483 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13804 16:55:51.212839 o KMS driver or no outputs, pipes: 8, outputs: 0
13805 16:55:51.216004 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13806 16:55:51.229377 <14>[ 33.100861] [IGT] kms_vblank: executing
13807 16:55:51.235586 IGT-Version: 1.2<14>[ 33.105862] [IGT] kms_vblank: exiting, ret=77
13808 16:55:51.238985 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13809 16:55:51.242393 Opened device: /dev/dri/card0
13810 16:55:51.248761 N<8>[ 33.117124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13811 16:55:51.249018 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13813 16:55:51.255614 o KMS driver or no outputs, pipes: 8, outputs: 0
13814 16:55:51.259198 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13815 16:55:51.272532 <14>[ 33.143972] [IGT] kms_vblank: executing
13816 16:55:51.278573 IGT-Version: 1.2<14>[ 33.148959] [IGT] kms_vblank: exiting, ret=77
13817 16:55:51.282333 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13818 16:55:51.285219 Opened device: /dev/dri/card0
13819 16:55:51.291883 N<8>[ 33.160137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13820 16:55:51.292142 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13822 16:55:51.295675 o KMS driver or no outputs, pipes: 8, outputs: 0
13823 16:55:51.301519 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13824 16:55:51.314423 <14>[ 33.186063] [IGT] kms_vblank: executing
13825 16:55:51.320927 IGT-Version: 1.2<14>[ 33.191218] [IGT] kms_vblank: exiting, ret=77
13826 16:55:51.323976 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13827 16:55:51.327287 Opened device: /dev/dri/card0
13828 16:55:51.333933 N<8>[ 33.202296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13829 16:55:51.334190 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13831 16:55:51.337167 o KMS driver or no outputs, pipes: 8, outputs: 0
13832 16:55:51.344153 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13833 16:55:51.356584 <14>[ 33.228399] [IGT] kms_vblank: executing
13834 16:55:51.362946 IGT-Version: 1.2<14>[ 33.233501] [IGT] kms_vblank: exiting, ret=77
13835 16:55:51.366382 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13836 16:55:51.370015 Opened device: /dev/dri/card0
13837 16:55:51.376326 N<8>[ 33.244803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13838 16:55:51.376592 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13840 16:55:51.379479 o KMS driver or no outputs, pipes: 8, outputs: 0
13841 16:55:51.386443 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13842 16:55:51.398961 <14>[ 33.270559] [IGT] kms_vblank: executing
13843 16:55:51.405408 IGT-Version: 1.2<14>[ 33.275660] [IGT] kms_vblank: exiting, ret=77
13844 16:55:51.409269 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13845 16:55:51.412228 Opened device: /dev/dri/card0
13846 16:55:51.418753 N<8>[ 33.286945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13847 16:55:51.419016 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13849 16:55:51.425601 o KMS driver or no outputs, pipes: 8, outputs: 0
13850 16:55:51.428696 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13851 16:55:51.441721 <14>[ 33.313148] [IGT] kms_vblank: executing
13852 16:55:51.448060 IGT-Version: 1.2<14>[ 33.318263] [IGT] kms_vblank: exiting, ret=77
13853 16:55:51.451096 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13854 16:55:51.454713 Opened device: /dev/dri/card0
13855 16:55:51.461432 N<8>[ 33.329429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13856 16:55:51.461723 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13858 16:55:51.464379 o KMS driver or no outputs, pipes: 8, outputs: 0
13859 16:55:51.471187 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13860 16:55:51.484396 <14>[ 33.355969] [IGT] kms_vblank: executing
13861 16:55:51.490936 IGT-Version: 1.2<14>[ 33.360881] [IGT] kms_vblank: exiting, ret=77
13862 16:55:51.494489 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13863 16:55:51.497579 Opened device: /dev/dri/card0
13864 16:55:51.504165 N<8>[ 33.373140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13865 16:55:51.504439 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13867 16:55:51.507523 o KMS driver or no outputs, pipes: 8, outputs: 0
13868 16:55:51.514226 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13869 16:55:51.528196 <14>[ 33.399514] [IGT] kms_vblank: executing
13870 16:55:51.534605 IGT-Version: 1.2<14>[ 33.404438] [IGT] kms_vblank: exiting, ret=77
13871 16:55:51.537699 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13872 16:55:51.540775 Opened device: /dev/dri/card0
13873 16:55:51.547400 N<8>[ 33.416454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13874 16:55:51.547673 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13876 16:55:51.553823 o KMS driver or no outputs, pipes: 8, outputs: 0
13877 16:55:51.557453 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13878 16:55:51.571364 <14>[ 33.443175] [IGT] kms_vblank: executing
13879 16:55:51.578253 IGT-Version: 1.2<14>[ 33.448631] [IGT] kms_vblank: exiting, ret=77
13880 16:55:51.581235 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13881 16:55:51.584464 Opened device: /dev/dri/card0
13882 16:55:51.590904 N<8>[ 33.460571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13883 16:55:51.591165 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13885 16:55:51.597843 o KMS driver or no outputs, pipes: 8, outputs: 0
13886 16:55:51.600698 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13887 16:55:51.615728 <14>[ 33.487416] [IGT] kms_vblank: executing
13888 16:55:51.622467 IGT-Version: 1.2<14>[ 33.492492] [IGT] kms_vblank: exiting, ret=77
13889 16:55:51.625478 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13890 16:55:51.628959 Opened device: /dev/dri/card0
13891 16:55:51.635199 N<8>[ 33.504027] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13892 16:55:51.635459 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13894 16:55:51.641899 o KMS driver or no outputs, pipes: 8, outputs: 0
13895 16:55:51.644973 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13896 16:55:51.658891 <14>[ 33.530679] [IGT] kms_vblank: executing
13897 16:55:51.665499 IGT-Version: 1.2<14>[ 33.535717] [IGT] kms_vblank: exiting, ret=77
13898 16:55:51.668524 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13899 16:55:51.672053 Opened device: /dev/dri/card0
13900 16:55:51.678964 N<8>[ 33.547110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13901 16:55:51.679221 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13903 16:55:51.685254 o KMS driver or no outputs, pipes: 8, outputs: 0
13904 16:55:51.688748 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13905 16:55:51.702704 <14>[ 33.574441] [IGT] kms_vblank: executing
13906 16:55:51.709240 IGT-Version: 1.2<14>[ 33.579468] [IGT] kms_vblank: exiting, ret=77
13907 16:55:51.712822 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13908 16:55:51.715704 Opened device: /dev/dri/card0
13909 16:55:51.722418 N<8>[ 33.590764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13910 16:55:51.722705 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13912 16:55:51.729204 o KMS driver or no outputs, pipes: 8, outputs: 0
13913 16:55:51.732173 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13914 16:55:51.746087 <14>[ 33.617640] [IGT] kms_vblank: executing
13915 16:55:51.752310 IGT-Version: 1.2<14>[ 33.622735] [IGT] kms_vblank: exiting, ret=77
13916 16:55:51.755997 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13917 16:55:51.758969 Opened device: /dev/dri/card0
13918 16:55:51.765464 N<8>[ 33.633714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13919 16:55:51.765769 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13921 16:55:51.772214 o KMS driver or no outputs, pipes: 8, outputs: 0
13922 16:55:51.778783 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13923 16:55:51.789176 <14>[ 33.661070] [IGT] kms_vblank: executing
13924 16:55:51.795763 IGT-Version: 1.2<14>[ 33.666284] [IGT] kms_vblank: exiting, ret=77
13925 16:55:51.798986 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13926 16:55:51.802609 Opened device: /dev/dri/card0
13927 16:55:51.809020 N<8>[ 33.677295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13928 16:55:51.809286 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13930 16:55:51.815486 o KMS driver or no outputs, pipes: 8, outputs: 0
13931 16:55:51.819132 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13932 16:55:51.833222 <14>[ 33.704389] [IGT] kms_vblank: executing
13933 16:55:51.839105 IGT-Version: 1.2<14>[ 33.709512] [IGT] kms_vblank: exiting, ret=77
13934 16:55:51.842894 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13935 16:55:51.845673 Opened device: /dev/dri/card0
13936 16:55:51.852826 N<8>[ 33.720686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13937 16:55:51.853125 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13939 16:55:51.858792 o KMS driver or no outputs, pipes: 8, outputs: 0
13940 16:55:51.862000 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13941 16:55:51.875564 <14>[ 33.747434] [IGT] kms_vblank: executing
13942 16:55:51.882253 IGT-Version: 1.2<14>[ 33.752566] [IGT] kms_vblank: exiting, ret=77
13943 16:55:51.885309 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13944 16:55:51.889044 Opened device: /dev/dri/card0
13945 16:55:51.895651 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13947 16:55:51.898535 N<8>[ 33.763869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13948 16:55:51.902201 o KMS driver or no outputs, pipes: 8, outputs: 0
13949 16:55:51.908838 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13950 16:55:51.919326 <14>[ 33.791303] [IGT] kms_vblank: executing
13951 16:55:51.926320 IGT-Version: 1.2<14>[ 33.796321] [IGT] kms_vblank: exiting, ret=77
13952 16:55:51.929484 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13953 16:55:51.932506 Opened device: /dev/dri/card0
13954 16:55:51.939239 N<8>[ 33.807652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13955 16:55:51.939544 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13957 16:55:51.946000 Received signal: <TESTSET> STOP
13958 16:55:51.946090 Closing test_set kms_vblank
13959 16:55:51.949594 o KMS driver or no outputs, pipe<8>[ 33.819139] <LAVA_SIGNAL_TESTSET STOP>
13960 16:55:51.955942 s: 8, outputs: 0<8>[ 33.825167] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10576339_1.5.2.3.1>
13961 16:55:51.956053
13962 16:55:51.956329 Received signal: <ENDRUN> 0_igt-kms-mediatek 10576339_1.5.2.3.1
13963 16:55:51.956444 Ending use of test pattern.
13964 16:55:51.956511 Ending test lava.0_igt-kms-mediatek (10576339_1.5.2.3.1), duration 13.55
13966 16:55:51.962547 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13967 16:55:51.962633 + set +x
13968 16:55:51.965629 <LAVA_TEST_RUNNER EXIT>
13969 16:55:51.965910 ok: lava_test_shell seems to have completed
13970 16:55:51.973283 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13971 16:55:51.973635 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13972 16:55:51.973751 end: 3 lava-test-retry (duration 00:00:14) [common]
13973 16:55:51.973849 start: 4 finalize (timeout 00:06:55) [common]
13974 16:55:51.973944 start: 4.1 power-off (timeout 00:00:30) [common]
13975 16:55:51.974109 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
13976 16:55:52.049547 >> Command sent successfully.
13977 16:55:52.051932 Returned 0 in 0 seconds
13978 16:55:52.152330 end: 4.1 power-off (duration 00:00:00) [common]
13980 16:55:52.152664 start: 4.2 read-feedback (timeout 00:06:55) [common]
13981 16:55:52.152953 Listened to connection for namespace 'common' for up to 1s
13982 16:55:53.153886 Finalising connection for namespace 'common'
13983 16:55:53.154081 Disconnecting from shell: Finalise
13984 16:55:53.154171 / #
13985 16:55:53.254499 end: 4.2 read-feedback (duration 00:00:01) [common]
13986 16:55:53.254666 end: 4 finalize (duration 00:00:01) [common]
13987 16:55:53.254782 Cleaning after the job
13988 16:55:53.254889 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/ramdisk
13989 16:55:53.260797 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/kernel
13990 16:55:53.266627 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/dtb
13991 16:55:53.266838 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576339/tftp-deploy-7o0p90sc/modules
13992 16:55:53.272047 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576339
13993 16:55:53.368314 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576339
13994 16:55:53.368519 Job finished correctly