Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 29
1 16:54:28.988971 lava-dispatcher, installed at version: 2023.03
2 16:54:28.989174 start: 0 validate
3 16:54:28.989295 Start time: 2023-06-03 16:54:28.989288+00:00 (UTC)
4 16:54:28.989411 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:54:28.989533 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 16:54:29.278876 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:54:29.279697 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:54:29.564671 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:54:29.565480 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:54:29.868881 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:54:29.869695 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:54:30.165634 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:54:30.166434 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:54:30.462688 validate duration: 1.47
16 16:54:30.463978 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:54:30.464528 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:54:30.465007 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:54:30.465646 Not decompressing ramdisk as can be used compressed.
20 16:54:30.466121 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 16:54:30.466523 saving as /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/ramdisk/initrd.cpio.gz
22 16:54:30.466876 total size: 5624321 (5MB)
23 16:54:30.472070 progress 0% (0MB)
24 16:54:30.481132 progress 5% (0MB)
25 16:54:30.488727 progress 10% (0MB)
26 16:54:30.493389 progress 15% (0MB)
27 16:54:30.497465 progress 20% (1MB)
28 16:54:30.500777 progress 25% (1MB)
29 16:54:30.503856 progress 30% (1MB)
30 16:54:30.506644 progress 35% (1MB)
31 16:54:30.508853 progress 40% (2MB)
32 16:54:30.511272 progress 45% (2MB)
33 16:54:30.513219 progress 50% (2MB)
34 16:54:30.515388 progress 55% (2MB)
35 16:54:30.517158 progress 60% (3MB)
36 16:54:30.519109 progress 65% (3MB)
37 16:54:30.521034 progress 70% (3MB)
38 16:54:30.522651 progress 75% (4MB)
39 16:54:30.524387 progress 80% (4MB)
40 16:54:30.525932 progress 85% (4MB)
41 16:54:30.527513 progress 90% (4MB)
42 16:54:30.529128 progress 95% (5MB)
43 16:54:30.530568 progress 100% (5MB)
44 16:54:30.530774 5MB downloaded in 0.06s (83.93MB/s)
45 16:54:30.530917 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:54:30.531148 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:54:30.531232 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:54:30.531314 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:54:30.531436 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:54:30.531509 saving as /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/kernel/Image
52 16:54:30.531570 total size: 45746688 (43MB)
53 16:54:30.531629 No compression specified
54 16:54:30.532702 progress 0% (0MB)
55 16:54:30.543806 progress 5% (2MB)
56 16:54:30.555206 progress 10% (4MB)
57 16:54:30.566559 progress 15% (6MB)
58 16:54:30.577790 progress 20% (8MB)
59 16:54:30.589417 progress 25% (10MB)
60 16:54:30.600771 progress 30% (13MB)
61 16:54:30.612421 progress 35% (15MB)
62 16:54:30.623738 progress 40% (17MB)
63 16:54:30.635070 progress 45% (19MB)
64 16:54:30.646261 progress 50% (21MB)
65 16:54:30.657471 progress 55% (24MB)
66 16:54:30.668818 progress 60% (26MB)
67 16:54:30.679967 progress 65% (28MB)
68 16:54:30.691328 progress 70% (30MB)
69 16:54:30.702827 progress 75% (32MB)
70 16:54:30.714215 progress 80% (34MB)
71 16:54:30.725516 progress 85% (37MB)
72 16:54:30.736890 progress 90% (39MB)
73 16:54:30.748043 progress 95% (41MB)
74 16:54:30.759126 progress 100% (43MB)
75 16:54:30.759239 43MB downloaded in 0.23s (191.63MB/s)
76 16:54:30.759382 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:54:30.759607 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:54:30.759699 start: 1.3 download-retry (timeout 00:10:00) [common]
80 16:54:30.759785 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 16:54:30.759918 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:54:30.759988 saving as /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/dtb/mt8192-asurada-spherion-r0.dtb
83 16:54:30.760048 total size: 46924 (0MB)
84 16:54:30.760107 No compression specified
85 16:54:30.761262 progress 69% (0MB)
86 16:54:30.761529 progress 100% (0MB)
87 16:54:30.761678 0MB downloaded in 0.00s (27.49MB/s)
88 16:54:30.761795 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:54:30.762014 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:54:30.762097 start: 1.4 download-retry (timeout 00:10:00) [common]
92 16:54:30.762176 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 16:54:30.762283 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 16:54:30.762355 saving as /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/nfsrootfs/full.rootfs.tar
95 16:54:30.762448 total size: 195125384 (186MB)
96 16:54:30.762506 Using unxz to decompress xz
97 16:54:30.765942 progress 0% (0MB)
98 16:54:31.301869 progress 5% (9MB)
99 16:54:31.788687 progress 10% (18MB)
100 16:54:32.354360 progress 15% (27MB)
101 16:54:32.623130 progress 20% (37MB)
102 16:54:33.061201 progress 25% (46MB)
103 16:54:33.613491 progress 30% (55MB)
104 16:54:34.149021 progress 35% (65MB)
105 16:54:34.684672 progress 40% (74MB)
106 16:54:35.233307 progress 45% (83MB)
107 16:54:35.816175 progress 50% (93MB)
108 16:54:36.393508 progress 55% (102MB)
109 16:54:37.016879 progress 60% (111MB)
110 16:54:37.397054 progress 65% (120MB)
111 16:54:37.473602 progress 70% (130MB)
112 16:54:37.619960 progress 75% (139MB)
113 16:54:37.690757 progress 80% (148MB)
114 16:54:37.735646 progress 85% (158MB)
115 16:54:37.822701 progress 90% (167MB)
116 16:54:38.182495 progress 95% (176MB)
117 16:54:38.734650 progress 100% (186MB)
118 16:54:38.740751 186MB downloaded in 7.98s (23.32MB/s)
119 16:54:38.741042 end: 1.4.1 http-download (duration 00:00:08) [common]
121 16:54:38.741303 end: 1.4 download-retry (duration 00:00:08) [common]
122 16:54:38.741391 start: 1.5 download-retry (timeout 00:09:52) [common]
123 16:54:38.741479 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 16:54:38.741625 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:54:38.741699 saving as /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/modules/modules.tar
126 16:54:38.741760 total size: 8545664 (8MB)
127 16:54:38.741823 Using unxz to decompress xz
128 16:54:38.745541 progress 0% (0MB)
129 16:54:38.766756 progress 5% (0MB)
130 16:54:38.790871 progress 10% (0MB)
131 16:54:38.816614 progress 15% (1MB)
132 16:54:38.840465 progress 20% (1MB)
133 16:54:38.865750 progress 25% (2MB)
134 16:54:38.889848 progress 30% (2MB)
135 16:54:38.914229 progress 35% (2MB)
136 16:54:38.938070 progress 40% (3MB)
137 16:54:38.962607 progress 45% (3MB)
138 16:54:38.985701 progress 50% (4MB)
139 16:54:39.007717 progress 55% (4MB)
140 16:54:39.031706 progress 60% (4MB)
141 16:54:39.055814 progress 65% (5MB)
142 16:54:39.080677 progress 70% (5MB)
143 16:54:39.106311 progress 75% (6MB)
144 16:54:39.134706 progress 80% (6MB)
145 16:54:39.156458 progress 85% (6MB)
146 16:54:39.181276 progress 90% (7MB)
147 16:54:39.203903 progress 95% (7MB)
148 16:54:39.226978 progress 100% (8MB)
149 16:54:39.232711 8MB downloaded in 0.49s (16.60MB/s)
150 16:54:39.232970 end: 1.5.1 http-download (duration 00:00:00) [common]
152 16:54:39.233238 end: 1.5 download-retry (duration 00:00:00) [common]
153 16:54:39.233330 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 16:54:39.233425 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 16:54:42.473022 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb
156 16:54:42.473227 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 16:54:42.473330 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 16:54:42.473521 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k
159 16:54:42.473647 makedir: /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin
160 16:54:42.473746 makedir: /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/tests
161 16:54:42.473841 makedir: /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/results
162 16:54:42.473943 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-add-keys
163 16:54:42.474084 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-add-sources
164 16:54:42.474208 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-background-process-start
165 16:54:42.474330 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-background-process-stop
166 16:54:42.474591 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-common-functions
167 16:54:42.474713 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-echo-ipv4
168 16:54:42.474836 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-install-packages
169 16:54:42.474956 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-installed-packages
170 16:54:42.475074 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-os-build
171 16:54:42.475194 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-probe-channel
172 16:54:42.475312 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-probe-ip
173 16:54:42.475431 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-target-ip
174 16:54:42.475586 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-target-mac
175 16:54:42.475705 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-target-storage
176 16:54:42.475826 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-case
177 16:54:42.475947 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-event
178 16:54:42.476066 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-feedback
179 16:54:42.476185 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-raise
180 16:54:42.476304 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-reference
181 16:54:42.476423 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-runner
182 16:54:42.476543 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-set
183 16:54:42.476664 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-test-shell
184 16:54:42.476787 Updating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-add-keys (debian)
185 16:54:42.476936 Updating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-add-sources (debian)
186 16:54:42.477071 Updating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-install-packages (debian)
187 16:54:42.477206 Updating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-installed-packages (debian)
188 16:54:42.477340 Updating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/bin/lava-os-build (debian)
189 16:54:42.477458 Creating /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/environment
190 16:54:42.477551 LAVA metadata
191 16:54:42.477623 - LAVA_JOB_ID=10576342
192 16:54:42.477687 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:54:42.477785 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 16:54:42.477851 skipped lava-vland-overlay
195 16:54:42.477925 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:54:42.478004 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 16:54:42.478064 skipped lava-multinode-overlay
198 16:54:42.478136 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:54:42.478237 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 16:54:42.478312 Loading test definitions
201 16:54:42.478451 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 16:54:42.478523 Using /lava-10576342 at stage 0
203 16:54:42.478789 uuid=10576342_1.6.2.3.1 testdef=None
204 16:54:42.478878 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:54:42.478962 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 16:54:42.479399 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:54:42.479708 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 16:54:42.480231 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:54:42.480460 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 16:54:42.480993 runner path: /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/0/tests/0_timesync-off test_uuid 10576342_1.6.2.3.1
213 16:54:42.481143 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:54:42.481367 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 16:54:42.481441 Using /lava-10576342 at stage 0
217 16:54:42.481573 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:54:42.481651 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/0/tests/1_kselftest-alsa'
219 16:54:45.710708 Running '/usr/bin/git checkout kernelci.org
220 16:54:45.851227 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 16:54:45.851922 uuid=10576342_1.6.2.3.5 testdef=None
222 16:54:45.852072 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 16:54:45.852318 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 16:54:45.853037 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:54:45.853267 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 16:54:45.854206 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:54:45.854489 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 16:54:45.855397 runner path: /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/0/tests/1_kselftest-alsa test_uuid 10576342_1.6.2.3.5
232 16:54:45.855488 BOARD='mt8192-asurada-spherion-r0'
233 16:54:45.855554 BRANCH='cip-gitlab'
234 16:54:45.855612 SKIPFILE='/dev/null'
235 16:54:45.855670 SKIP_INSTALL='True'
236 16:54:45.855725 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:54:45.855782 TST_CASENAME=''
238 16:54:45.855837 TST_CMDFILES='alsa'
239 16:54:45.855972 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:54:45.856173 Creating lava-test-runner.conf files
242 16:54:45.856237 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576342/lava-overlay-ekjj298k/lava-10576342/0 for stage 0
243 16:54:45.856327 - 0_timesync-off
244 16:54:45.856396 - 1_kselftest-alsa
245 16:54:45.856490 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 16:54:45.856576 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 16:54:53.184162 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 16:54:53.184328 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 16:54:53.184456 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:54:53.184557 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 16:54:53.184649 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 16:54:53.341085 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:54:53.341450 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 16:54:53.341568 extracting modules file /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb
255 16:54:53.538706 extracting modules file /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576342/extract-overlay-ramdisk-xzikjt14/ramdisk
256 16:54:53.740172 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:54:53.740339 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 16:54:53.740431 [common] Applying overlay to NFS
259 16:54:53.740502 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576342/compress-overlay-ke017bq5/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb
260 16:54:54.615202 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:54:54.615371 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 16:54:54.615465 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:54:54.615555 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 16:54:54.615640 Building ramdisk /var/lib/lava/dispatcher/tmp/10576342/extract-overlay-ramdisk-xzikjt14/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576342/extract-overlay-ramdisk-xzikjt14/ramdisk
265 16:54:54.946261 >> 128921 blocks
266 16:54:56.979455 rename /var/lib/lava/dispatcher/tmp/10576342/extract-overlay-ramdisk-xzikjt14/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/ramdisk/ramdisk.cpio.gz
267 16:54:56.979869 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:54:56.979991 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 16:54:56.980092 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 16:54:56.980191 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/kernel/Image'
271 16:55:08.103201 Returned 0 in 11 seconds
272 16:55:08.204180 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/kernel/image.itb
273 16:55:08.574014 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:55:08.574388 output: Created: Sat Jun 3 17:55:08 2023
275 16:55:08.574482 output: Image 0 (kernel-1)
276 16:55:08.574550 output: Description:
277 16:55:08.574614 output: Created: Sat Jun 3 17:55:08 2023
278 16:55:08.574676 output: Type: Kernel Image
279 16:55:08.574736 output: Compression: lzma compressed
280 16:55:08.574797 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
281 16:55:08.574858 output: Architecture: AArch64
282 16:55:08.574914 output: OS: Linux
283 16:55:08.574971 output: Load Address: 0x00000000
284 16:55:08.575028 output: Entry Point: 0x00000000
285 16:55:08.575085 output: Hash algo: crc32
286 16:55:08.575138 output: Hash value: b48eba69
287 16:55:08.575191 output: Image 1 (fdt-1)
288 16:55:08.575244 output: Description: mt8192-asurada-spherion-r0
289 16:55:08.575296 output: Created: Sat Jun 3 17:55:08 2023
290 16:55:08.575349 output: Type: Flat Device Tree
291 16:55:08.575401 output: Compression: uncompressed
292 16:55:08.575452 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 16:55:08.575504 output: Architecture: AArch64
294 16:55:08.575556 output: Hash algo: crc32
295 16:55:08.575608 output: Hash value: 1df858fa
296 16:55:08.575660 output: Image 2 (ramdisk-1)
297 16:55:08.575712 output: Description: unavailable
298 16:55:08.575764 output: Created: Sat Jun 3 17:55:08 2023
299 16:55:08.575816 output: Type: RAMDisk Image
300 16:55:08.575867 output: Compression: Unknown Compression
301 16:55:08.575920 output: Data Size: 18602210 Bytes = 18166.22 KiB = 17.74 MiB
302 16:55:08.575972 output: Architecture: AArch64
303 16:55:08.576024 output: OS: Linux
304 16:55:08.576076 output: Load Address: unavailable
305 16:55:08.576127 output: Entry Point: unavailable
306 16:55:08.576179 output: Hash algo: crc32
307 16:55:08.576230 output: Hash value: efc51bd1
308 16:55:08.576282 output: Default Configuration: 'conf-1'
309 16:55:08.576333 output: Configuration 0 (conf-1)
310 16:55:08.576385 output: Description: mt8192-asurada-spherion-r0
311 16:55:08.576436 output: Kernel: kernel-1
312 16:55:08.576488 output: Init Ramdisk: ramdisk-1
313 16:55:08.576540 output: FDT: fdt-1
314 16:55:08.576592 output: Loadables: kernel-1
315 16:55:08.576643 output:
316 16:55:08.576826 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 16:55:08.576925 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 16:55:08.577026 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
319 16:55:08.577121 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 16:55:08.577199 No LXC device requested
321 16:55:08.577275 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:55:08.577363 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 16:55:08.577441 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:55:08.577511 Checking files for TFTP limit of 4294967296 bytes.
325 16:55:08.577977 end: 1 tftp-deploy (duration 00:00:38) [common]
326 16:55:08.578082 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:55:08.578174 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:55:08.578297 substitutions:
329 16:55:08.578389 - {DTB}: 10576342/tftp-deploy-a8bjz08n/dtb/mt8192-asurada-spherion-r0.dtb
330 16:55:08.578468 - {INITRD}: 10576342/tftp-deploy-a8bjz08n/ramdisk/ramdisk.cpio.gz
331 16:55:08.578527 - {KERNEL}: 10576342/tftp-deploy-a8bjz08n/kernel/Image
332 16:55:08.578586 - {LAVA_MAC}: None
333 16:55:08.578641 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb
334 16:55:08.578697 - {NFS_SERVER_IP}: 192.168.201.1
335 16:55:08.578752 - {PRESEED_CONFIG}: None
336 16:55:08.578806 - {PRESEED_LOCAL}: None
337 16:55:08.578859 - {RAMDISK}: 10576342/tftp-deploy-a8bjz08n/ramdisk/ramdisk.cpio.gz
338 16:55:08.578913 - {ROOT_PART}: None
339 16:55:08.578966 - {ROOT}: None
340 16:55:08.579020 - {SERVER_IP}: 192.168.201.1
341 16:55:08.579073 - {TEE}: None
342 16:55:08.579126 Parsed boot commands:
343 16:55:08.579179 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:55:08.579348 Parsed boot commands: tftpboot 192.168.201.1 10576342/tftp-deploy-a8bjz08n/kernel/image.itb 10576342/tftp-deploy-a8bjz08n/kernel/cmdline
345 16:55:08.579437 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:55:08.579520 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:55:08.579611 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:55:08.579696 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:55:08.579766 Not connected, no need to disconnect.
350 16:55:08.579839 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:55:08.579919 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:55:08.579985 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
353 16:55:08.583314 Setting prompt string to ['lava-test: # ']
354 16:55:08.583642 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:55:08.583745 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:55:08.583839 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:55:08.583934 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:55:08.584120 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
359 16:55:13.737494 >> Command sent successfully.
360 16:55:13.743287 Returned 0 in 5 seconds
361 16:55:13.844062 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 16:55:13.845587 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 16:55:13.846167 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 16:55:13.846707 Setting prompt string to 'Starting depthcharge on Spherion...'
366 16:55:13.847095 Changing prompt to 'Starting depthcharge on Spherion...'
367 16:55:13.847515 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 16:55:13.848857 [Enter `^Ec?' for help]
369 16:55:14.014450
370 16:55:14.015044
371 16:55:14.015423 F0: 102B 0000
372 16:55:14.015778
373 16:55:14.016114 F3: 1001 0000 [0200]
374 16:55:14.017929
375 16:55:14.018429 F3: 1001 0000
376 16:55:14.018813
377 16:55:14.019161 F7: 102D 0000
378 16:55:14.019495
379 16:55:14.020838 F1: 0000 0000
380 16:55:14.021314
381 16:55:14.021685 V0: 0000 0000 [0001]
382 16:55:14.022028
383 16:55:14.024191 00: 0007 8000
384 16:55:14.024674
385 16:55:14.025044 01: 0000 0000
386 16:55:14.025413
387 16:55:14.027973 BP: 0C00 0209 [0000]
388 16:55:14.028548
389 16:55:14.028926 G0: 1182 0000
390 16:55:14.029271
391 16:55:14.031038 EC: 0000 0021 [4000]
392 16:55:14.031508
393 16:55:14.031877 S7: 0000 0000 [0000]
394 16:55:14.032219
395 16:55:14.034961 CC: 0000 0000 [0001]
396 16:55:14.035458
397 16:55:14.035833 T0: 0000 0040 [010F]
398 16:55:14.036181
399 16:55:14.038341 Jump to BL
400 16:55:14.038869
401 16:55:14.061466
402 16:55:14.062042
403 16:55:14.062480
404 16:55:14.068763 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 16:55:14.072624 ARM64: Exception handlers installed.
406 16:55:14.076066 ARM64: Testing exception
407 16:55:14.079621 ARM64: Done test exception
408 16:55:14.086164 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 16:55:14.096191 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 16:55:14.103387 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 16:55:14.113517 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 16:55:14.120144 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 16:55:14.126196 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 16:55:14.138189 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 16:55:14.145431 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 16:55:14.164214 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 16:55:14.167840 WDT: Last reset was cold boot
418 16:55:14.170871 SPI1(PAD0) initialized at 2873684 Hz
419 16:55:14.174816 SPI5(PAD0) initialized at 992727 Hz
420 16:55:14.177808 VBOOT: Loading verstage.
421 16:55:14.184935 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 16:55:14.187771 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 16:55:14.191080 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 16:55:14.194309 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 16:55:14.202218 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 16:55:14.208422 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 16:55:14.219194 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 16:55:14.219817
429 16:55:14.220200
430 16:55:14.229436 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 16:55:14.232513 ARM64: Exception handlers installed.
432 16:55:14.235934 ARM64: Testing exception
433 16:55:14.236522 ARM64: Done test exception
434 16:55:14.242817 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 16:55:14.246185 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 16:55:14.260463 Probing TPM: . done!
437 16:55:14.261067 TPM ready after 0 ms
438 16:55:14.266787 Connected to device vid:did:rid of 1ae0:0028:00
439 16:55:14.273936 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 16:55:14.277185 Initialized TPM device CR50 revision 0
441 16:55:14.344519 tlcl_send_startup: Startup return code is 0
442 16:55:14.345155 TPM: setup succeeded
443 16:55:14.356159 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 16:55:14.364523 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 16:55:14.371366 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 16:55:14.383767 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 16:55:14.386828 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 16:55:14.394854 in-header: 03 07 00 00 08 00 00 00
449 16:55:14.398099 in-data: aa e4 47 04 13 02 00 00
450 16:55:14.401925 Chrome EC: UHEPI supported
451 16:55:14.409492 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 16:55:14.412284 in-header: 03 ad 00 00 08 00 00 00
453 16:55:14.416163 in-data: 00 20 20 08 00 00 00 00
454 16:55:14.416760 Phase 1
455 16:55:14.419950 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 16:55:14.427087 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 16:55:14.430625 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 16:55:14.434909 Recovery requested (1009000e)
459 16:55:14.444758 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 16:55:14.450668 tlcl_extend: response is 0
461 16:55:14.460203 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 16:55:14.466476 tlcl_extend: response is 0
463 16:55:14.473455 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 16:55:14.493803 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 16:55:14.501058 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 16:55:14.501641
467 16:55:14.502019
468 16:55:14.510667 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 16:55:14.514693 ARM64: Exception handlers installed.
470 16:55:14.515289 ARM64: Testing exception
471 16:55:14.517518 ARM64: Done test exception
472 16:55:14.539278 pmic_efuse_setting: Set efuses in 11 msecs
473 16:55:14.542443 pmwrap_interface_init: Select PMIF_VLD_RDY
474 16:55:14.549546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 16:55:14.552823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 16:55:14.556665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 16:55:14.563038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 16:55:14.566722 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 16:55:14.573582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 16:55:14.578115 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 16:55:14.581281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 16:55:14.585089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 16:55:14.592284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 16:55:14.595963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 16:55:14.598756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 16:55:14.605512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 16:55:14.612284 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 16:55:14.615965 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 16:55:14.622175 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 16:55:14.629555 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 16:55:14.633237 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 16:55:14.640122 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 16:55:14.646521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 16:55:14.650631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 16:55:14.657563 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 16:55:14.663273 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 16:55:14.666975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 16:55:14.673748 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 16:55:14.680189 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 16:55:14.683862 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 16:55:14.686863 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 16:55:14.693759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 16:55:14.696916 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 16:55:14.703809 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 16:55:14.706965 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 16:55:14.713540 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 16:55:14.717229 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 16:55:14.723551 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 16:55:14.726957 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 16:55:14.734116 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 16:55:14.736750 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 16:55:14.743465 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 16:55:14.747231 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 16:55:14.750700 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 16:55:14.754726 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 16:55:14.760767 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 16:55:14.764022 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 16:55:14.767308 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 16:55:14.774382 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 16:55:14.777665 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 16:55:14.780918 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 16:55:14.787568 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 16:55:14.790808 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 16:55:14.794225 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 16:55:14.800880 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 16:55:14.810848 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 16:55:14.814185 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 16:55:14.824122 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 16:55:14.831032 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 16:55:14.837200 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 16:55:14.841036 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:55:14.844107 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 16:55:14.852078 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x30
534 16:55:14.858466 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 16:55:14.861556 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 16:55:14.864988 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 16:55:14.876214 [RTC]rtc_get_frequency_meter,154: input=15, output=771
538 16:55:14.886236 [RTC]rtc_get_frequency_meter,154: input=23, output=957
539 16:55:14.895270 [RTC]rtc_get_frequency_meter,154: input=19, output=863
540 16:55:14.904747 [RTC]rtc_get_frequency_meter,154: input=17, output=819
541 16:55:14.914929 [RTC]rtc_get_frequency_meter,154: input=16, output=796
542 16:55:14.918957 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
543 16:55:14.922486 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
544 16:55:14.929537 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
545 16:55:14.932650 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
546 16:55:14.936757 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
547 16:55:14.940781 ADC[4]: Raw value=902507 ID=7
548 16:55:14.941352 ADC[3]: Raw value=213179 ID=1
549 16:55:14.943499 RAM Code: 0x71
550 16:55:14.947378 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
551 16:55:14.951047 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
552 16:55:14.962012 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
553 16:55:14.965793 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
554 16:55:14.969254 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
555 16:55:14.976312 in-header: 03 07 00 00 08 00 00 00
556 16:55:14.976901 in-data: aa e4 47 04 13 02 00 00
557 16:55:14.979107 Chrome EC: UHEPI supported
558 16:55:14.986270 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
559 16:55:14.989324 in-header: 03 ed 00 00 08 00 00 00
560 16:55:14.992370 in-data: 80 20 60 08 00 00 00 00
561 16:55:14.995908 MRC: failed to locate region type 0.
562 16:55:15.002438 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
563 16:55:15.005952 DRAM-K: Running full calibration
564 16:55:15.012583 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
565 16:55:15.013061 header.status = 0x0
566 16:55:15.015825 header.version = 0x6 (expected: 0x6)
567 16:55:15.019125 header.size = 0xd00 (expected: 0xd00)
568 16:55:15.022623 header.flags = 0x0
569 16:55:15.029446 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
570 16:55:15.046898 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
571 16:55:15.054276 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
572 16:55:15.058165 dram_init: ddr_geometry: 2
573 16:55:15.058682 [EMI] MDL number = 2
574 16:55:15.060775 [EMI] Get MDL freq = 0
575 16:55:15.064124 dram_init: ddr_type: 0
576 16:55:15.064702 is_discrete_lpddr4: 1
577 16:55:15.066839 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
578 16:55:15.067366
579 16:55:15.067747
580 16:55:15.070129 [Bian_co] ETT version 0.0.0.1
581 16:55:15.074592 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
582 16:55:15.075179
583 16:55:15.080271 dramc_set_vcore_voltage set vcore to 650000
584 16:55:15.080749 Read voltage for 800, 4
585 16:55:15.084123 Vio18 = 0
586 16:55:15.084707 Vcore = 650000
587 16:55:15.085088 Vdram = 0
588 16:55:15.085441 Vddq = 0
589 16:55:15.086996 Vmddr = 0
590 16:55:15.087469 dram_init: config_dvfs: 1
591 16:55:15.093722 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
592 16:55:15.100299 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
593 16:55:15.103873 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
594 16:55:15.106743 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
595 16:55:15.110725 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
596 16:55:15.113542 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
597 16:55:15.117280 MEM_TYPE=3, freq_sel=18
598 16:55:15.120794 sv_algorithm_assistance_LP4_1600
599 16:55:15.123766 ============ PULL DRAM RESETB DOWN ============
600 16:55:15.126995 ========== PULL DRAM RESETB DOWN end =========
601 16:55:15.133246 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
602 16:55:15.137090 ===================================
603 16:55:15.137673 LPDDR4 DRAM CONFIGURATION
604 16:55:15.139875 ===================================
605 16:55:15.143708 EX_ROW_EN[0] = 0x0
606 16:55:15.146690 EX_ROW_EN[1] = 0x0
607 16:55:15.147173 LP4Y_EN = 0x0
608 16:55:15.149754 WORK_FSP = 0x0
609 16:55:15.150232 WL = 0x2
610 16:55:15.153212 RL = 0x2
611 16:55:15.153690 BL = 0x2
612 16:55:15.157169 RPST = 0x0
613 16:55:15.157649 RD_PRE = 0x0
614 16:55:15.160248 WR_PRE = 0x1
615 16:55:15.160845 WR_PST = 0x0
616 16:55:15.163052 DBI_WR = 0x0
617 16:55:15.163533 DBI_RD = 0x0
618 16:55:15.166907 OTF = 0x1
619 16:55:15.169748 ===================================
620 16:55:15.173804 ===================================
621 16:55:15.174422 ANA top config
622 16:55:15.176750 ===================================
623 16:55:15.179693 DLL_ASYNC_EN = 0
624 16:55:15.183606 ALL_SLAVE_EN = 1
625 16:55:15.186869 NEW_RANK_MODE = 1
626 16:55:15.187466 DLL_IDLE_MODE = 1
627 16:55:15.190554 LP45_APHY_COMB_EN = 1
628 16:55:15.193800 TX_ODT_DIS = 1
629 16:55:15.196619 NEW_8X_MODE = 1
630 16:55:15.200559 ===================================
631 16:55:15.203198 ===================================
632 16:55:15.203685 data_rate = 1600
633 16:55:15.206456 CKR = 1
634 16:55:15.209902 DQ_P2S_RATIO = 8
635 16:55:15.213211 ===================================
636 16:55:15.216448 CA_P2S_RATIO = 8
637 16:55:15.219457 DQ_CA_OPEN = 0
638 16:55:15.222867 DQ_SEMI_OPEN = 0
639 16:55:15.223438 CA_SEMI_OPEN = 0
640 16:55:15.226413 CA_FULL_RATE = 0
641 16:55:15.229646 DQ_CKDIV4_EN = 1
642 16:55:15.232839 CA_CKDIV4_EN = 1
643 16:55:15.236696 CA_PREDIV_EN = 0
644 16:55:15.239860 PH8_DLY = 0
645 16:55:15.240304 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
646 16:55:15.242801 DQ_AAMCK_DIV = 4
647 16:55:15.246446 CA_AAMCK_DIV = 4
648 16:55:15.249474 CA_ADMCK_DIV = 4
649 16:55:15.252868 DQ_TRACK_CA_EN = 0
650 16:55:15.256459 CA_PICK = 800
651 16:55:15.257042 CA_MCKIO = 800
652 16:55:15.260515 MCKIO_SEMI = 0
653 16:55:15.263444 PLL_FREQ = 3068
654 16:55:15.266700 DQ_UI_PI_RATIO = 32
655 16:55:15.269582 CA_UI_PI_RATIO = 0
656 16:55:15.273258 ===================================
657 16:55:15.276754 ===================================
658 16:55:15.279523 memory_type:LPDDR4
659 16:55:15.279997 GP_NUM : 10
660 16:55:15.282825 SRAM_EN : 1
661 16:55:15.283297 MD32_EN : 0
662 16:55:15.286824 ===================================
663 16:55:15.290521 [ANA_INIT] >>>>>>>>>>>>>>
664 16:55:15.294739 <<<<<< [CONFIGURE PHASE]: ANA_TX
665 16:55:15.297474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
666 16:55:15.301284 ===================================
667 16:55:15.301862 data_rate = 1600,PCW = 0X7600
668 16:55:15.304528 ===================================
669 16:55:15.308308 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
670 16:55:15.315301 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 16:55:15.319232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 16:55:15.326664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
673 16:55:15.329573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
674 16:55:15.332627 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
675 16:55:15.333227 [ANA_INIT] flow start
676 16:55:15.336281 [ANA_INIT] PLL >>>>>>>>
677 16:55:15.339164 [ANA_INIT] PLL <<<<<<<<
678 16:55:15.339638 [ANA_INIT] MIDPI >>>>>>>>
679 16:55:15.342539 [ANA_INIT] MIDPI <<<<<<<<
680 16:55:15.346842 [ANA_INIT] DLL >>>>>>>>
681 16:55:15.347455 [ANA_INIT] flow end
682 16:55:15.352610 ============ LP4 DIFF to SE enter ============
683 16:55:15.356018 ============ LP4 DIFF to SE exit ============
684 16:55:15.356860 [ANA_INIT] <<<<<<<<<<<<<
685 16:55:15.359500 [Flow] Enable top DCM control >>>>>
686 16:55:15.362318 [Flow] Enable top DCM control <<<<<
687 16:55:15.365811 Enable DLL master slave shuffle
688 16:55:15.372692 ==============================================================
689 16:55:15.376210 Gating Mode config
690 16:55:15.379188 ==============================================================
691 16:55:15.382587 Config description:
692 16:55:15.392089 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
693 16:55:15.399210 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
694 16:55:15.402142 SELPH_MODE 0: By rank 1: By Phase
695 16:55:15.408847 ==============================================================
696 16:55:15.411851 GAT_TRACK_EN = 1
697 16:55:15.415726 RX_GATING_MODE = 2
698 16:55:15.418495 RX_GATING_TRACK_MODE = 2
699 16:55:15.418626 SELPH_MODE = 1
700 16:55:15.422335 PICG_EARLY_EN = 1
701 16:55:15.425564 VALID_LAT_VALUE = 1
702 16:55:15.431731 ==============================================================
703 16:55:15.435552 Enter into Gating configuration >>>>
704 16:55:15.438269 Exit from Gating configuration <<<<
705 16:55:15.441575 Enter into DVFS_PRE_config >>>>>
706 16:55:15.451740 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
707 16:55:15.454973 Exit from DVFS_PRE_config <<<<<
708 16:55:15.458230 Enter into PICG configuration >>>>
709 16:55:15.462010 Exit from PICG configuration <<<<
710 16:55:15.464885 [RX_INPUT] configuration >>>>>
711 16:55:15.468131 [RX_INPUT] configuration <<<<<
712 16:55:15.471538 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
713 16:55:15.478299 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
714 16:55:15.484922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
715 16:55:15.491428 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
716 16:55:15.498248 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
717 16:55:15.501429 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
718 16:55:15.508354 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
719 16:55:15.511880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
720 16:55:15.515260 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
721 16:55:15.518802 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
722 16:55:15.522739 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
723 16:55:15.528925 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
724 16:55:15.532311 ===================================
725 16:55:15.532407 LPDDR4 DRAM CONFIGURATION
726 16:55:15.535442 ===================================
727 16:55:15.538559 EX_ROW_EN[0] = 0x0
728 16:55:15.542189 EX_ROW_EN[1] = 0x0
729 16:55:15.542283 LP4Y_EN = 0x0
730 16:55:15.545553 WORK_FSP = 0x0
731 16:55:15.545661 WL = 0x2
732 16:55:15.548978 RL = 0x2
733 16:55:15.549099 BL = 0x2
734 16:55:15.552209 RPST = 0x0
735 16:55:15.552326 RD_PRE = 0x0
736 16:55:15.555545 WR_PRE = 0x1
737 16:55:15.555674 WR_PST = 0x0
738 16:55:15.559309 DBI_WR = 0x0
739 16:55:15.559424 DBI_RD = 0x0
740 16:55:15.563218 OTF = 0x1
741 16:55:15.563304 ===================================
742 16:55:15.566683 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
743 16:55:15.574353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
744 16:55:15.578468 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
745 16:55:15.582124 ===================================
746 16:55:15.582848 LPDDR4 DRAM CONFIGURATION
747 16:55:15.586030 ===================================
748 16:55:15.589389 EX_ROW_EN[0] = 0x10
749 16:55:15.589820 EX_ROW_EN[1] = 0x0
750 16:55:15.592814 LP4Y_EN = 0x0
751 16:55:15.593391 WORK_FSP = 0x0
752 16:55:15.596537 WL = 0x2
753 16:55:15.597106 RL = 0x2
754 16:55:15.600254 BL = 0x2
755 16:55:15.600831 RPST = 0x0
756 16:55:15.603753 RD_PRE = 0x0
757 16:55:15.604206 WR_PRE = 0x1
758 16:55:15.607674 WR_PST = 0x0
759 16:55:15.608100 DBI_WR = 0x0
760 16:55:15.611750 DBI_RD = 0x0
761 16:55:15.612056 OTF = 0x1
762 16:55:15.615409 ===================================
763 16:55:15.621650 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
764 16:55:15.626204 nWR fixed to 40
765 16:55:15.626670 [ModeRegInit_LP4] CH0 RK0
766 16:55:15.629443 [ModeRegInit_LP4] CH0 RK1
767 16:55:15.632716 [ModeRegInit_LP4] CH1 RK0
768 16:55:15.633025 [ModeRegInit_LP4] CH1 RK1
769 16:55:15.636255 match AC timing 13
770 16:55:15.639880 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
771 16:55:15.643828 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
772 16:55:15.647499 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
773 16:55:15.655039 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
774 16:55:15.659005 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
775 16:55:15.659250 [EMI DOE] emi_dcm 0
776 16:55:15.662259 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
777 16:55:15.662507 ==
778 16:55:15.666029 Dram Type= 6, Freq= 0, CH_0, rank 0
779 16:55:15.669480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 16:55:15.673083 ==
781 16:55:15.676904 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 16:55:15.683768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 16:55:15.692379 [CA 0] Center 38 (7~69) winsize 63
784 16:55:15.695972 [CA 1] Center 38 (7~69) winsize 63
785 16:55:15.699134 [CA 2] Center 35 (5~66) winsize 62
786 16:55:15.702647 [CA 3] Center 35 (5~66) winsize 62
787 16:55:15.706460 [CA 4] Center 34 (4~65) winsize 62
788 16:55:15.710285 [CA 5] Center 33 (3~64) winsize 62
789 16:55:15.710492
790 16:55:15.713749 [CmdBusTrainingLP45] Vref(ca) range 1: 34
791 16:55:15.713940
792 16:55:15.716817 [CATrainingPosCal] consider 1 rank data
793 16:55:15.720667 u2DelayCellTimex100 = 270/100 ps
794 16:55:15.724335 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
795 16:55:15.728277 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
796 16:55:15.731554 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
797 16:55:15.735096 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
798 16:55:15.738782 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
799 16:55:15.742331 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 16:55:15.742482
801 16:55:15.745926 CA PerBit enable=1, Macro0, CA PI delay=33
802 16:55:15.746062
803 16:55:15.750214 [CBTSetCACLKResult] CA Dly = 33
804 16:55:15.750361 CS Dly: 5 (0~36)
805 16:55:15.750474 ==
806 16:55:15.754222 Dram Type= 6, Freq= 0, CH_0, rank 1
807 16:55:15.757673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
808 16:55:15.757811 ==
809 16:55:15.765080 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
810 16:55:15.768484 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
811 16:55:15.778299 [CA 0] Center 38 (7~69) winsize 63
812 16:55:15.782247 [CA 1] Center 38 (7~69) winsize 63
813 16:55:15.786624 [CA 2] Center 36 (6~66) winsize 61
814 16:55:15.789775 [CA 3] Center 35 (5~66) winsize 62
815 16:55:15.793277 [CA 4] Center 35 (4~66) winsize 63
816 16:55:15.797441 [CA 5] Center 34 (4~65) winsize 62
817 16:55:15.798022
818 16:55:15.800348 [CmdBusTrainingLP45] Vref(ca) range 1: 32
819 16:55:15.800784
820 16:55:15.804298 [CATrainingPosCal] consider 2 rank data
821 16:55:15.804816 u2DelayCellTimex100 = 270/100 ps
822 16:55:15.808076 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
823 16:55:15.811921 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
824 16:55:15.815338 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
825 16:55:15.822727 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
826 16:55:15.823208 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
827 16:55:15.826502 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
828 16:55:15.826738
829 16:55:15.833766 CA PerBit enable=1, Macro0, CA PI delay=34
830 16:55:15.833971
831 16:55:15.834122 [CBTSetCACLKResult] CA Dly = 34
832 16:55:15.836910 CS Dly: 6 (0~38)
833 16:55:15.837068
834 16:55:15.840830 ----->DramcWriteLeveling(PI) begin...
835 16:55:15.841344 ==
836 16:55:15.844883 Dram Type= 6, Freq= 0, CH_0, rank 0
837 16:55:15.848223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 16:55:15.848765 ==
839 16:55:15.852155 Write leveling (Byte 0): 34 => 34
840 16:55:15.855661 Write leveling (Byte 1): 31 => 31
841 16:55:15.856296 DramcWriteLeveling(PI) end<-----
842 16:55:15.856808
843 16:55:15.858905 ==
844 16:55:15.861912 Dram Type= 6, Freq= 0, CH_0, rank 0
845 16:55:15.865520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 16:55:15.866204 ==
847 16:55:15.869388 [Gating] SW mode calibration
848 16:55:15.877789 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 16:55:15.880648 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 16:55:15.883685 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
851 16:55:15.887013 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
852 16:55:15.893835 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
853 16:55:15.897104 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 16:55:15.900908 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 16:55:15.907429 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 16:55:15.910680 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:55:15.914034 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:55:15.920710 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:55:15.924259 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:55:15.927560 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:55:15.930935 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:55:15.937160 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:55:15.940565 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:55:15.944220 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:55:15.951226 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:55:15.954166 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:55:15.957352 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
868 16:55:15.963633 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
869 16:55:15.967339 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
870 16:55:15.970592 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 16:55:15.976968 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 16:55:15.980549 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:55:15.984090 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:55:15.990486 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:55:15.993854 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
876 16:55:15.997159 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
877 16:55:16.003726 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 16:55:16.007377 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 16:55:16.010675 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 16:55:16.017090 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 16:55:16.020351 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:55:16.023817 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
883 16:55:16.030388 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
884 16:55:16.033885 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
885 16:55:16.037270 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
886 16:55:16.044217 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 16:55:16.047209 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 16:55:16.051145 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 16:55:16.054328 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:55:16.060673 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:55:16.064104 0 11 4 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
892 16:55:16.067198 0 11 8 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
893 16:55:16.074071 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
894 16:55:16.077493 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 16:55:16.080700 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 16:55:16.087292 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 16:55:16.090901 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:55:16.094126 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:55:16.100826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
900 16:55:16.104200 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
901 16:55:16.107110 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 16:55:16.114163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 16:55:16.117693 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 16:55:16.120921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:55:16.126926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:55:16.130786 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:55:16.133844 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:55:16.140318 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:55:16.144464 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:55:16.147647 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:55:16.153964 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:55:16.157480 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:55:16.160191 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:55:16.167047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
915 16:55:16.170220 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
916 16:55:16.173657 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
917 16:55:16.176895 Total UI for P1: 0, mck2ui 16
918 16:55:16.180354 best dqsien dly found for B0: ( 0, 14, 2)
919 16:55:16.186724 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 16:55:16.187307 Total UI for P1: 0, mck2ui 16
921 16:55:16.190268 best dqsien dly found for B1: ( 0, 14, 8)
922 16:55:16.196734 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
923 16:55:16.200041 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
924 16:55:16.200617
925 16:55:16.203531 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
926 16:55:16.206608 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
927 16:55:16.210211 [Gating] SW calibration Done
928 16:55:16.210839 ==
929 16:55:16.214266 Dram Type= 6, Freq= 0, CH_0, rank 0
930 16:55:16.217819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 16:55:16.218303 ==
932 16:55:16.220052 RX Vref Scan: 0
933 16:55:16.220527
934 16:55:16.220905 RX Vref 0 -> 0, step: 1
935 16:55:16.221257
936 16:55:16.223139 RX Delay -130 -> 252, step: 16
937 16:55:16.226605 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
938 16:55:16.233608 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
939 16:55:16.237215 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
940 16:55:16.240352 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
941 16:55:16.243388 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
942 16:55:16.246288 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
943 16:55:16.253098 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
944 16:55:16.257526 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
945 16:55:16.259780 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
946 16:55:16.263040 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
947 16:55:16.267124 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
948 16:55:16.272858 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
949 16:55:16.276604 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
950 16:55:16.280027 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
951 16:55:16.283265 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
952 16:55:16.286630 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
953 16:55:16.290118 ==
954 16:55:16.292575 Dram Type= 6, Freq= 0, CH_0, rank 0
955 16:55:16.296091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
956 16:55:16.296683 ==
957 16:55:16.297076 DQS Delay:
958 16:55:16.299748 DQS0 = 0, DQS1 = 0
959 16:55:16.300325 DQM Delay:
960 16:55:16.303053 DQM0 = 92, DQM1 = 77
961 16:55:16.303635 DQ Delay:
962 16:55:16.306343 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
963 16:55:16.309769 DQ4 =85, DQ5 =85, DQ6 =109, DQ7 =109
964 16:55:16.313059 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
965 16:55:16.316337 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
966 16:55:16.316910
967 16:55:16.317294
968 16:55:16.317642 ==
969 16:55:16.319183 Dram Type= 6, Freq= 0, CH_0, rank 0
970 16:55:16.322916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 16:55:16.323497 ==
972 16:55:16.323880
973 16:55:16.324230
974 16:55:16.325761 TX Vref Scan disable
975 16:55:16.329153 == TX Byte 0 ==
976 16:55:16.332449 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
977 16:55:16.336138 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
978 16:55:16.341046 == TX Byte 1 ==
979 16:55:16.342313 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 16:55:16.345872 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 16:55:16.346492 ==
982 16:55:16.349298 Dram Type= 6, Freq= 0, CH_0, rank 0
983 16:55:16.355733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 16:55:16.356316 ==
985 16:55:16.368229 TX Vref=22, minBit 11, minWin=26, winSum=439
986 16:55:16.371293 TX Vref=24, minBit 6, minWin=27, winSum=440
987 16:55:16.374153 TX Vref=26, minBit 8, minWin=27, winSum=443
988 16:55:16.377965 TX Vref=28, minBit 8, minWin=27, winSum=450
989 16:55:16.381095 TX Vref=30, minBit 8, minWin=27, winSum=447
990 16:55:16.388016 TX Vref=32, minBit 14, minWin=27, winSum=450
991 16:55:16.391127 [TxChooseVref] Worse bit 8, Min win 27, Win sum 450, Final Vref 28
992 16:55:16.391727
993 16:55:16.394211 Final TX Range 1 Vref 28
994 16:55:16.394716
995 16:55:16.395092 ==
996 16:55:16.398005 Dram Type= 6, Freq= 0, CH_0, rank 0
997 16:55:16.401092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
998 16:55:16.401709 ==
999 16:55:16.404101
1000 16:55:16.404608
1001 16:55:16.404985 TX Vref Scan disable
1002 16:55:16.408665 == TX Byte 0 ==
1003 16:55:16.410996 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1004 16:55:16.418229 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1005 16:55:16.418850 == TX Byte 1 ==
1006 16:55:16.421652 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1007 16:55:16.427981 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1008 16:55:16.428560
1009 16:55:16.428943 [DATLAT]
1010 16:55:16.429296 Freq=800, CH0 RK0
1011 16:55:16.429640
1012 16:55:16.431680 DATLAT Default: 0xa
1013 16:55:16.432264 0, 0xFFFF, sum = 0
1014 16:55:16.434160 1, 0xFFFF, sum = 0
1015 16:55:16.434722 2, 0xFFFF, sum = 0
1016 16:55:16.437753 3, 0xFFFF, sum = 0
1017 16:55:16.441302 4, 0xFFFF, sum = 0
1018 16:55:16.441783 5, 0xFFFF, sum = 0
1019 16:55:16.444314 6, 0xFFFF, sum = 0
1020 16:55:16.444800 7, 0xFFFF, sum = 0
1021 16:55:16.447535 8, 0xFFFF, sum = 0
1022 16:55:16.448021 9, 0x0, sum = 1
1023 16:55:16.448406 10, 0x0, sum = 2
1024 16:55:16.451221 11, 0x0, sum = 3
1025 16:55:16.451724 12, 0x0, sum = 4
1026 16:55:16.454920 best_step = 10
1027 16:55:16.455489
1028 16:55:16.455872 ==
1029 16:55:16.458342 Dram Type= 6, Freq= 0, CH_0, rank 0
1030 16:55:16.461111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1031 16:55:16.461578 ==
1032 16:55:16.464336 RX Vref Scan: 1
1033 16:55:16.464801
1034 16:55:16.465170 Set Vref Range= 32 -> 127
1035 16:55:16.467575
1036 16:55:16.468144 RX Vref 32 -> 127, step: 1
1037 16:55:16.468520
1038 16:55:16.470839 RX Delay -95 -> 252, step: 8
1039 16:55:16.471304
1040 16:55:16.474175 Set Vref, RX VrefLevel [Byte0]: 32
1041 16:55:16.478075 [Byte1]: 32
1042 16:55:16.478716
1043 16:55:16.480941 Set Vref, RX VrefLevel [Byte0]: 33
1044 16:55:16.483911 [Byte1]: 33
1045 16:55:16.488359
1046 16:55:16.488932 Set Vref, RX VrefLevel [Byte0]: 34
1047 16:55:16.494436 [Byte1]: 34
1048 16:55:16.494912
1049 16:55:16.498276 Set Vref, RX VrefLevel [Byte0]: 35
1050 16:55:16.501309 [Byte1]: 35
1051 16:55:16.501878
1052 16:55:16.504261 Set Vref, RX VrefLevel [Byte0]: 36
1053 16:55:16.507730 [Byte1]: 36
1054 16:55:16.508308
1055 16:55:16.511018 Set Vref, RX VrefLevel [Byte0]: 37
1056 16:55:16.514856 [Byte1]: 37
1057 16:55:16.518808
1058 16:55:16.519364 Set Vref, RX VrefLevel [Byte0]: 38
1059 16:55:16.522165 [Byte1]: 38
1060 16:55:16.526878
1061 16:55:16.527432 Set Vref, RX VrefLevel [Byte0]: 39
1062 16:55:16.529640 [Byte1]: 39
1063 16:55:16.533657
1064 16:55:16.534130 Set Vref, RX VrefLevel [Byte0]: 40
1065 16:55:16.537370 [Byte1]: 40
1066 16:55:16.541608
1067 16:55:16.542205 Set Vref, RX VrefLevel [Byte0]: 41
1068 16:55:16.544786 [Byte1]: 41
1069 16:55:16.549452
1070 16:55:16.550010 Set Vref, RX VrefLevel [Byte0]: 42
1071 16:55:16.552604 [Byte1]: 42
1072 16:55:16.556994
1073 16:55:16.557557 Set Vref, RX VrefLevel [Byte0]: 43
1074 16:55:16.560353 [Byte1]: 43
1075 16:55:16.564177
1076 16:55:16.564660 Set Vref, RX VrefLevel [Byte0]: 44
1077 16:55:16.567405 [Byte1]: 44
1078 16:55:16.571379
1079 16:55:16.574889 Set Vref, RX VrefLevel [Byte0]: 45
1080 16:55:16.578576 [Byte1]: 45
1081 16:55:16.579139
1082 16:55:16.582098 Set Vref, RX VrefLevel [Byte0]: 46
1083 16:55:16.585042 [Byte1]: 46
1084 16:55:16.585516
1085 16:55:16.588283 Set Vref, RX VrefLevel [Byte0]: 47
1086 16:55:16.591099 [Byte1]: 47
1087 16:55:16.591573
1088 16:55:16.594741 Set Vref, RX VrefLevel [Byte0]: 48
1089 16:55:16.598081 [Byte1]: 48
1090 16:55:16.601852
1091 16:55:16.602318 Set Vref, RX VrefLevel [Byte0]: 49
1092 16:55:16.605419 [Byte1]: 49
1093 16:55:16.609578
1094 16:55:16.610050 Set Vref, RX VrefLevel [Byte0]: 50
1095 16:55:16.613143 [Byte1]: 50
1096 16:55:16.617336
1097 16:55:16.617899 Set Vref, RX VrefLevel [Byte0]: 51
1098 16:55:16.621154 [Byte1]: 51
1099 16:55:16.625140
1100 16:55:16.625718 Set Vref, RX VrefLevel [Byte0]: 52
1101 16:55:16.628207 [Byte1]: 52
1102 16:55:16.632292
1103 16:55:16.632859 Set Vref, RX VrefLevel [Byte0]: 53
1104 16:55:16.635673 [Byte1]: 53
1105 16:55:16.640414
1106 16:55:16.640966 Set Vref, RX VrefLevel [Byte0]: 54
1107 16:55:16.643447 [Byte1]: 54
1108 16:55:16.647966
1109 16:55:16.648520 Set Vref, RX VrefLevel [Byte0]: 55
1110 16:55:16.651254 [Byte1]: 55
1111 16:55:16.655526
1112 16:55:16.656086 Set Vref, RX VrefLevel [Byte0]: 56
1113 16:55:16.658764 [Byte1]: 56
1114 16:55:16.662803
1115 16:55:16.663357 Set Vref, RX VrefLevel [Byte0]: 57
1116 16:55:16.666017 [Byte1]: 57
1117 16:55:16.670574
1118 16:55:16.671190 Set Vref, RX VrefLevel [Byte0]: 58
1119 16:55:16.673996 [Byte1]: 58
1120 16:55:16.678133
1121 16:55:16.678742 Set Vref, RX VrefLevel [Byte0]: 59
1122 16:55:16.681492 [Byte1]: 59
1123 16:55:16.685582
1124 16:55:16.686139 Set Vref, RX VrefLevel [Byte0]: 60
1125 16:55:16.689298 [Byte1]: 60
1126 16:55:16.693106
1127 16:55:16.693577 Set Vref, RX VrefLevel [Byte0]: 61
1128 16:55:16.697123 [Byte1]: 61
1129 16:55:16.700814
1130 16:55:16.701287 Set Vref, RX VrefLevel [Byte0]: 62
1131 16:55:16.704301 [Byte1]: 62
1132 16:55:16.708226
1133 16:55:16.708700 Set Vref, RX VrefLevel [Byte0]: 63
1134 16:55:16.711637 [Byte1]: 63
1135 16:55:16.716044
1136 16:55:16.716514 Set Vref, RX VrefLevel [Byte0]: 64
1137 16:55:16.719461 [Byte1]: 64
1138 16:55:16.723732
1139 16:55:16.726715 Set Vref, RX VrefLevel [Byte0]: 65
1140 16:55:16.727279 [Byte1]: 65
1141 16:55:16.731080
1142 16:55:16.731636 Set Vref, RX VrefLevel [Byte0]: 66
1143 16:55:16.734405 [Byte1]: 66
1144 16:55:16.739273
1145 16:55:16.739826 Set Vref, RX VrefLevel [Byte0]: 67
1146 16:55:16.742275 [Byte1]: 67
1147 16:55:16.746566
1148 16:55:16.747131 Set Vref, RX VrefLevel [Byte0]: 68
1149 16:55:16.749955 [Byte1]: 68
1150 16:55:16.753963
1151 16:55:16.754568 Set Vref, RX VrefLevel [Byte0]: 69
1152 16:55:16.757215 [Byte1]: 69
1153 16:55:16.761438
1154 16:55:16.761907 Set Vref, RX VrefLevel [Byte0]: 70
1155 16:55:16.765089 [Byte1]: 70
1156 16:55:16.769328
1157 16:55:16.769917 Set Vref, RX VrefLevel [Byte0]: 71
1158 16:55:16.772855 [Byte1]: 71
1159 16:55:16.777124
1160 16:55:16.777681 Set Vref, RX VrefLevel [Byte0]: 72
1161 16:55:16.780232 [Byte1]: 72
1162 16:55:16.784279
1163 16:55:16.784877 Set Vref, RX VrefLevel [Byte0]: 73
1164 16:55:16.788026 [Byte1]: 73
1165 16:55:16.792027
1166 16:55:16.792581 Set Vref, RX VrefLevel [Byte0]: 74
1167 16:55:16.795303 [Byte1]: 74
1168 16:55:16.800213
1169 16:55:16.800772 Set Vref, RX VrefLevel [Byte0]: 75
1170 16:55:16.802774 [Byte1]: 75
1171 16:55:16.807162
1172 16:55:16.807711 Set Vref, RX VrefLevel [Byte0]: 76
1173 16:55:16.811255 [Byte1]: 76
1174 16:55:16.814664
1175 16:55:16.815136 Set Vref, RX VrefLevel [Byte0]: 77
1176 16:55:16.818305 [Byte1]: 77
1177 16:55:16.822431
1178 16:55:16.823000 Final RX Vref Byte 0 = 61 to rank0
1179 16:55:16.825900 Final RX Vref Byte 1 = 54 to rank0
1180 16:55:16.829446 Final RX Vref Byte 0 = 61 to rank1
1181 16:55:16.832186 Final RX Vref Byte 1 = 54 to rank1==
1182 16:55:16.835520 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 16:55:16.842550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 16:55:16.843127 ==
1185 16:55:16.843510 DQS Delay:
1186 16:55:16.843859 DQS0 = 0, DQS1 = 0
1187 16:55:16.845880 DQM Delay:
1188 16:55:16.846479 DQM0 = 93, DQM1 = 81
1189 16:55:16.849370 DQ Delay:
1190 16:55:16.852191 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1191 16:55:16.855992 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1192 16:55:16.858867 DQ8 =76, DQ9 =68, DQ10 =80, DQ11 =76
1193 16:55:16.862242 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88
1194 16:55:16.862770
1195 16:55:16.863145
1196 16:55:16.869300 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e39, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
1197 16:55:16.872011 CH0 RK0: MR19=606, MR18=3E39
1198 16:55:16.878992 CH0_RK0: MR19=0x606, MR18=0x3E39, DQSOSC=394, MR23=63, INC=95, DEC=63
1199 16:55:16.879564
1200 16:55:16.882245 ----->DramcWriteLeveling(PI) begin...
1201 16:55:16.882859 ==
1202 16:55:16.885600 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 16:55:16.888939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 16:55:16.889503 ==
1205 16:55:16.892373 Write leveling (Byte 0): 34 => 34
1206 16:55:16.895430 Write leveling (Byte 1): 28 => 28
1207 16:55:16.898794 DramcWriteLeveling(PI) end<-----
1208 16:55:16.899358
1209 16:55:16.899732 ==
1210 16:55:16.902176 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 16:55:16.905519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 16:55:16.906085 ==
1213 16:55:16.908927 [Gating] SW mode calibration
1214 16:55:16.915584 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 16:55:16.922021 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 16:55:16.925555 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 16:55:16.928514 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 16:55:16.935408 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1219 16:55:16.938935 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 16:55:16.983683 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 16:55:16.984297 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 16:55:16.985056 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 16:55:16.985509 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:55:16.985933 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:55:16.986310 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:55:16.986756 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:55:16.987099 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:55:16.987426 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:55:16.987742 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:55:16.989734 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:55:16.992745 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 16:55:16.996117 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 16:55:17.000335 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1234 16:55:17.006229 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 16:55:17.009892 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:55:17.012879 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 16:55:17.019392 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 16:55:17.022509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:55:17.026602 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:55:17.033008 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 16:55:17.036483 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1242 16:55:17.040032 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
1243 16:55:17.045861 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 16:55:17.049390 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 16:55:17.052259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 16:55:17.059443 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 16:55:17.062819 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 16:55:17.066064 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 16:55:17.072315 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (1 0)
1250 16:55:17.076449 0 10 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
1251 16:55:17.079009 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 16:55:17.085729 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 16:55:17.089295 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 16:55:17.092509 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 16:55:17.099199 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 16:55:17.102552 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 16:55:17.105825 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1258 16:55:17.109387 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1259 16:55:17.115697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 16:55:17.119184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 16:55:17.123065 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 16:55:17.126473 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 16:55:17.134431 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 16:55:17.137314 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 16:55:17.140611 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 16:55:17.147761 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 16:55:17.151810 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 16:55:17.154888 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 16:55:17.158215 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 16:55:17.164748 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 16:55:17.167984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 16:55:17.171087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 16:55:17.178220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 16:55:17.181222 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 16:55:17.184909 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 16:55:17.191514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 16:55:17.194842 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 16:55:17.197944 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 16:55:17.201368 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 16:55:17.207861 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 16:55:17.211204 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 16:55:17.215215 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 16:55:17.218089 Total UI for P1: 0, mck2ui 16
1284 16:55:17.221401 best dqsien dly found for B0: ( 0, 14, 4)
1285 16:55:17.228092 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 16:55:17.228750 Total UI for P1: 0, mck2ui 16
1287 16:55:17.234651 best dqsien dly found for B1: ( 0, 14, 6)
1288 16:55:17.237703 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 16:55:17.241416 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1290 16:55:17.242005
1291 16:55:17.244632 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 16:55:17.247605 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1293 16:55:17.250912 [Gating] SW calibration Done
1294 16:55:17.251386 ==
1295 16:55:17.254996 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 16:55:17.258060 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 16:55:17.258583 ==
1298 16:55:17.260940 RX Vref Scan: 0
1299 16:55:17.261409
1300 16:55:17.261785 RX Vref 0 -> 0, step: 1
1301 16:55:17.262136
1302 16:55:17.264305 RX Delay -130 -> 252, step: 16
1303 16:55:17.267834 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1304 16:55:17.274088 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1305 16:55:17.277769 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1306 16:55:17.281305 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1307 16:55:17.284839 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1308 16:55:17.287922 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1309 16:55:17.294586 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1310 16:55:17.298021 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1311 16:55:17.300965 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1312 16:55:17.304239 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1313 16:55:17.308378 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1314 16:55:17.314306 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1315 16:55:17.317503 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1316 16:55:17.320879 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1317 16:55:17.324527 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1318 16:55:17.331168 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1319 16:55:17.331744 ==
1320 16:55:17.333977 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 16:55:17.337486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 16:55:17.338066 ==
1323 16:55:17.338488 DQS Delay:
1324 16:55:17.340579 DQS0 = 0, DQS1 = 0
1325 16:55:17.341049 DQM Delay:
1326 16:55:17.343959 DQM0 = 87, DQM1 = 82
1327 16:55:17.344433 DQ Delay:
1328 16:55:17.347504 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1329 16:55:17.350566 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1330 16:55:17.354042 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1331 16:55:17.357499 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1332 16:55:17.358089
1333 16:55:17.358532
1334 16:55:17.358891 ==
1335 16:55:17.361419 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 16:55:17.364130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 16:55:17.364724 ==
1338 16:55:17.365150
1339 16:55:17.365502
1340 16:55:17.367105 TX Vref Scan disable
1341 16:55:17.370997 == TX Byte 0 ==
1342 16:55:17.373960 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1343 16:55:17.377210 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1344 16:55:17.380763 == TX Byte 1 ==
1345 16:55:17.383939 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1346 16:55:17.387528 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1347 16:55:17.388101 ==
1348 16:55:17.390592 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 16:55:17.397341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 16:55:17.397919 ==
1351 16:55:17.409783 TX Vref=22, minBit 1, minWin=27, winSum=443
1352 16:55:17.412975 TX Vref=24, minBit 6, minWin=27, winSum=444
1353 16:55:17.416828 TX Vref=26, minBit 8, minWin=27, winSum=452
1354 16:55:17.419829 TX Vref=28, minBit 10, minWin=27, winSum=454
1355 16:55:17.423057 TX Vref=30, minBit 10, minWin=27, winSum=456
1356 16:55:17.429465 TX Vref=32, minBit 6, minWin=28, winSum=455
1357 16:55:17.433042 [TxChooseVref] Worse bit 6, Min win 28, Win sum 455, Final Vref 32
1358 16:55:17.433635
1359 16:55:17.436190 Final TX Range 1 Vref 32
1360 16:55:17.436653
1361 16:55:17.437014 ==
1362 16:55:17.439302 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 16:55:17.442643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 16:55:17.445750 ==
1365 16:55:17.446208
1366 16:55:17.446606
1367 16:55:17.446941 TX Vref Scan disable
1368 16:55:17.449818 == TX Byte 0 ==
1369 16:55:17.453861 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1370 16:55:17.456211 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1371 16:55:17.459412 == TX Byte 1 ==
1372 16:55:17.462854 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1373 16:55:17.469976 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1374 16:55:17.470298
1375 16:55:17.470588 [DATLAT]
1376 16:55:17.470825 Freq=800, CH0 RK1
1377 16:55:17.471052
1378 16:55:17.472737 DATLAT Default: 0xa
1379 16:55:17.473057 0, 0xFFFF, sum = 0
1380 16:55:17.475883 1, 0xFFFF, sum = 0
1381 16:55:17.476210 2, 0xFFFF, sum = 0
1382 16:55:17.479603 3, 0xFFFF, sum = 0
1383 16:55:17.482554 4, 0xFFFF, sum = 0
1384 16:55:17.482880 5, 0xFFFF, sum = 0
1385 16:55:17.485754 6, 0xFFFF, sum = 0
1386 16:55:17.486138 7, 0xFFFF, sum = 0
1387 16:55:17.490444 8, 0xFFFF, sum = 0
1388 16:55:17.490865 9, 0x0, sum = 1
1389 16:55:17.492465 10, 0x0, sum = 2
1390 16:55:17.492793 11, 0x0, sum = 3
1391 16:55:17.493054 12, 0x0, sum = 4
1392 16:55:17.495820 best_step = 10
1393 16:55:17.496140
1394 16:55:17.496393 ==
1395 16:55:17.499760 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 16:55:17.503488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 16:55:17.503918 ==
1398 16:55:17.506005 RX Vref Scan: 0
1399 16:55:17.506457
1400 16:55:17.506728 RX Vref 0 -> 0, step: 1
1401 16:55:17.509922
1402 16:55:17.510344 RX Delay -95 -> 252, step: 8
1403 16:55:17.516335 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1404 16:55:17.519997 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1405 16:55:17.522896 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1406 16:55:17.526304 iDelay=209, Bit 3, Center 84 (-23 ~ 192) 216
1407 16:55:17.529752 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1408 16:55:17.536789 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1409 16:55:17.539828 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1410 16:55:17.543274 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1411 16:55:17.546328 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1412 16:55:17.549833 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1413 16:55:17.556143 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1414 16:55:17.559714 iDelay=209, Bit 11, Center 80 (-23 ~ 184) 208
1415 16:55:17.563038 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1416 16:55:17.565643 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1417 16:55:17.572791 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1418 16:55:17.575933 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1419 16:55:17.576391 ==
1420 16:55:17.579058 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 16:55:17.582880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 16:55:17.583462 ==
1423 16:55:17.586132 DQS Delay:
1424 16:55:17.586655 DQS0 = 0, DQS1 = 0
1425 16:55:17.587026 DQM Delay:
1426 16:55:17.589724 DQM0 = 91, DQM1 = 83
1427 16:55:17.590290 DQ Delay:
1428 16:55:17.592776 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =84
1429 16:55:17.595737 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1430 16:55:17.599253 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =80
1431 16:55:17.603156 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1432 16:55:17.603712
1433 16:55:17.604079
1434 16:55:17.612708 [DQSOSCAuto] RK1, (LSB)MR18= 0x411b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
1435 16:55:17.613276 CH0 RK1: MR19=606, MR18=411B
1436 16:55:17.619227 CH0_RK1: MR19=0x606, MR18=0x411B, DQSOSC=393, MR23=63, INC=95, DEC=63
1437 16:55:17.622848 [RxdqsGatingPostProcess] freq 800
1438 16:55:17.629103 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 16:55:17.633684 Pre-setting of DQS Precalculation
1440 16:55:17.635578 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 16:55:17.636056 ==
1442 16:55:17.639258 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 16:55:17.646183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 16:55:17.646846 ==
1445 16:55:17.649315 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 16:55:17.656347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 16:55:17.664928 [CA 0] Center 36 (6~67) winsize 62
1448 16:55:17.668481 [CA 1] Center 36 (6~67) winsize 62
1449 16:55:17.671758 [CA 2] Center 34 (4~65) winsize 62
1450 16:55:17.675148 [CA 3] Center 34 (3~65) winsize 63
1451 16:55:17.678060 [CA 4] Center 34 (4~65) winsize 62
1452 16:55:17.681544 [CA 5] Center 33 (3~64) winsize 62
1453 16:55:17.682281
1454 16:55:17.685803 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1455 16:55:17.686297
1456 16:55:17.688380 [CATrainingPosCal] consider 1 rank data
1457 16:55:17.691552 u2DelayCellTimex100 = 270/100 ps
1458 16:55:17.694771 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 16:55:17.702025 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1460 16:55:17.704716 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1461 16:55:17.708296 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1462 16:55:17.711583 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 16:55:17.714881 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 16:55:17.715455
1465 16:55:17.718009 CA PerBit enable=1, Macro0, CA PI delay=33
1466 16:55:17.718624
1467 16:55:17.721168 [CBTSetCACLKResult] CA Dly = 33
1468 16:55:17.721740 CS Dly: 5 (0~36)
1469 16:55:17.724760 ==
1470 16:55:17.727785 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 16:55:17.731272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 16:55:17.731851 ==
1473 16:55:17.734419 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 16:55:17.740918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 16:55:17.751579 [CA 0] Center 36 (6~67) winsize 62
1476 16:55:17.754235 [CA 1] Center 37 (6~68) winsize 63
1477 16:55:17.757976 [CA 2] Center 35 (4~66) winsize 63
1478 16:55:17.761440 [CA 3] Center 34 (4~65) winsize 62
1479 16:55:17.764384 [CA 4] Center 34 (4~65) winsize 62
1480 16:55:17.767583 [CA 5] Center 34 (3~65) winsize 63
1481 16:55:17.768067
1482 16:55:17.770651 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1483 16:55:17.771123
1484 16:55:17.774088 [CATrainingPosCal] consider 2 rank data
1485 16:55:17.778634 u2DelayCellTimex100 = 270/100 ps
1486 16:55:17.780880 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 16:55:17.787882 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1488 16:55:17.791571 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1489 16:55:17.795256 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1490 16:55:17.795849 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 16:55:17.798843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 16:55:17.799415
1493 16:55:17.802654 CA PerBit enable=1, Macro0, CA PI delay=33
1494 16:55:17.806405
1495 16:55:17.806986 [CBTSetCACLKResult] CA Dly = 33
1496 16:55:17.810180 CS Dly: 6 (0~38)
1497 16:55:17.810830
1498 16:55:17.813829 ----->DramcWriteLeveling(PI) begin...
1499 16:55:17.814307 ==
1500 16:55:17.818222 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 16:55:17.821320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 16:55:17.821927 ==
1503 16:55:17.824758 Write leveling (Byte 0): 29 => 29
1504 16:55:17.827897 Write leveling (Byte 1): 30 => 30
1505 16:55:17.828470 DramcWriteLeveling(PI) end<-----
1506 16:55:17.831237
1507 16:55:17.831812 ==
1508 16:55:17.834831 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 16:55:17.837855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 16:55:17.838332 ==
1511 16:55:17.841035 [Gating] SW mode calibration
1512 16:55:17.847947 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 16:55:17.850880 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 16:55:17.857760 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 16:55:17.861155 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1516 16:55:17.864989 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 16:55:17.871161 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 16:55:17.874244 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 16:55:17.877841 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 16:55:17.884718 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 16:55:17.887482 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:55:17.891122 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:55:17.897668 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:55:17.901336 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:55:17.904374 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:55:17.911104 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:55:17.914088 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:55:17.917659 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 16:55:17.924124 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 16:55:17.927518 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1531 16:55:17.930946 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1532 16:55:17.937567 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 16:55:17.940932 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 16:55:17.944533 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 16:55:17.947350 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:55:17.955007 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:55:17.957657 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 16:55:17.960637 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 16:55:17.967557 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1540 16:55:17.970680 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1541 16:55:17.973972 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 16:55:17.980720 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 16:55:17.983815 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 16:55:17.987326 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 16:55:17.993973 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 16:55:17.997043 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1547 16:55:18.000008 0 10 4 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
1548 16:55:18.006877 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 16:55:18.010092 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 16:55:18.013898 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 16:55:18.020491 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 16:55:18.023767 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 16:55:18.026768 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 16:55:18.033780 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1555 16:55:18.037392 0 11 4 | B1->B0 | 2f2f 3636 | 0 1 | (0 0) (0 0)
1556 16:55:18.040303 0 11 8 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1557 16:55:18.046743 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 16:55:18.050622 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 16:55:18.054411 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 16:55:18.060013 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 16:55:18.063146 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 16:55:18.066977 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 16:55:18.073512 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1564 16:55:18.076722 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 16:55:18.080282 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 16:55:18.086947 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 16:55:18.090206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:55:18.093661 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 16:55:18.099935 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 16:55:18.103530 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 16:55:18.106701 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 16:55:18.113404 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 16:55:18.116520 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 16:55:18.119456 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 16:55:18.126629 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 16:55:18.129881 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 16:55:18.132887 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 16:55:18.139667 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 16:55:18.143146 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1580 16:55:18.146439 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 16:55:18.149624 Total UI for P1: 0, mck2ui 16
1582 16:55:18.153266 best dqsien dly found for B0: ( 0, 14, 4)
1583 16:55:18.156581 Total UI for P1: 0, mck2ui 16
1584 16:55:18.159802 best dqsien dly found for B1: ( 0, 14, 4)
1585 16:55:18.162822 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 16:55:18.166585 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 16:55:18.167162
1588 16:55:18.169317 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 16:55:18.172856 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 16:55:18.176641 [Gating] SW calibration Done
1591 16:55:18.177225 ==
1592 16:55:18.179434 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 16:55:18.185883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 16:55:18.186485 ==
1595 16:55:18.186977 RX Vref Scan: 0
1596 16:55:18.187437
1597 16:55:18.189575 RX Vref 0 -> 0, step: 1
1598 16:55:18.190154
1599 16:55:18.193092 RX Delay -130 -> 252, step: 16
1600 16:55:18.195889 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 16:55:18.199361 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1602 16:55:18.202643 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1603 16:55:18.209791 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1604 16:55:18.212715 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1605 16:55:18.215678 iDelay=222, Bit 5, Center 101 (-2 ~ 205) 208
1606 16:55:18.219274 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1607 16:55:18.222593 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1608 16:55:18.229265 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1609 16:55:18.232580 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1610 16:55:18.235537 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1611 16:55:18.239156 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1612 16:55:18.242069 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1613 16:55:18.249385 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1614 16:55:18.252875 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1615 16:55:18.255710 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1616 16:55:18.256193 ==
1617 16:55:18.259233 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 16:55:18.262549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 16:55:18.263129 ==
1620 16:55:18.265723 DQS Delay:
1621 16:55:18.266302 DQS0 = 0, DQS1 = 0
1622 16:55:18.269096 DQM Delay:
1623 16:55:18.269572 DQM0 = 88, DQM1 = 80
1624 16:55:18.269965 DQ Delay:
1625 16:55:18.272285 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1626 16:55:18.275627 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1627 16:55:18.279012 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1628 16:55:18.282437 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1629 16:55:18.283019
1630 16:55:18.285852
1631 16:55:18.286476 ==
1632 16:55:18.288706 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 16:55:18.292893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 16:55:18.293468 ==
1635 16:55:18.293837
1636 16:55:18.294177
1637 16:55:18.295580 TX Vref Scan disable
1638 16:55:18.296043 == TX Byte 0 ==
1639 16:55:18.302220 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1640 16:55:18.305698 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1641 16:55:18.306337 == TX Byte 1 ==
1642 16:55:18.312009 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1643 16:55:18.315575 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1644 16:55:18.316165 ==
1645 16:55:18.319862 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 16:55:18.321601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 16:55:18.322069 ==
1648 16:55:18.335463 TX Vref=22, minBit 15, minWin=26, winSum=445
1649 16:55:18.338741 TX Vref=24, minBit 8, minWin=27, winSum=450
1650 16:55:18.341872 TX Vref=26, minBit 13, minWin=27, winSum=452
1651 16:55:18.345554 TX Vref=28, minBit 15, minWin=27, winSum=456
1652 16:55:18.348459 TX Vref=30, minBit 15, minWin=27, winSum=456
1653 16:55:18.355012 TX Vref=32, minBit 15, minWin=27, winSum=457
1654 16:55:18.358642 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 32
1655 16:55:18.361626
1656 16:55:18.362089 Final TX Range 1 Vref 32
1657 16:55:18.362511
1658 16:55:18.362866 ==
1659 16:55:18.365187 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 16:55:18.368626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 16:55:18.372216 ==
1662 16:55:18.372785
1663 16:55:18.373209
1664 16:55:18.373553 TX Vref Scan disable
1665 16:55:18.375559 == TX Byte 0 ==
1666 16:55:18.379018 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1667 16:55:18.385976 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1668 16:55:18.386601 == TX Byte 1 ==
1669 16:55:18.388778 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1670 16:55:18.396167 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1671 16:55:18.396738
1672 16:55:18.397114 [DATLAT]
1673 16:55:18.397457 Freq=800, CH1 RK0
1674 16:55:18.397792
1675 16:55:18.399124 DATLAT Default: 0xa
1676 16:55:18.399587 0, 0xFFFF, sum = 0
1677 16:55:18.402545 1, 0xFFFF, sum = 0
1678 16:55:18.403119 2, 0xFFFF, sum = 0
1679 16:55:18.405902 3, 0xFFFF, sum = 0
1680 16:55:18.409481 4, 0xFFFF, sum = 0
1681 16:55:18.410053 5, 0xFFFF, sum = 0
1682 16:55:18.411989 6, 0xFFFF, sum = 0
1683 16:55:18.412463 7, 0xFFFF, sum = 0
1684 16:55:18.415725 8, 0xFFFF, sum = 0
1685 16:55:18.416299 9, 0x0, sum = 1
1686 16:55:18.418943 10, 0x0, sum = 2
1687 16:55:18.419519 11, 0x0, sum = 3
1688 16:55:18.419901 12, 0x0, sum = 4
1689 16:55:18.422556 best_step = 10
1690 16:55:18.423018
1691 16:55:18.423392 ==
1692 16:55:18.425371 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 16:55:18.429687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 16:55:18.430253 ==
1695 16:55:18.432236 RX Vref Scan: 1
1696 16:55:18.432801
1697 16:55:18.435337 Set Vref Range= 32 -> 127
1698 16:55:18.435865
1699 16:55:18.436236 RX Vref 32 -> 127, step: 1
1700 16:55:18.436581
1701 16:55:18.438575 RX Delay -95 -> 252, step: 8
1702 16:55:18.439149
1703 16:55:18.442196 Set Vref, RX VrefLevel [Byte0]: 32
1704 16:55:18.445521 [Byte1]: 32
1705 16:55:18.448355
1706 16:55:18.448822 Set Vref, RX VrefLevel [Byte0]: 33
1707 16:55:18.452093 [Byte1]: 33
1708 16:55:18.456043
1709 16:55:18.456514 Set Vref, RX VrefLevel [Byte0]: 34
1710 16:55:18.459070 [Byte1]: 34
1711 16:55:18.463555
1712 16:55:18.464063 Set Vref, RX VrefLevel [Byte0]: 35
1713 16:55:18.466657 [Byte1]: 35
1714 16:55:18.471028
1715 16:55:18.471503 Set Vref, RX VrefLevel [Byte0]: 36
1716 16:55:18.477811 [Byte1]: 36
1717 16:55:18.478284
1718 16:55:18.481184 Set Vref, RX VrefLevel [Byte0]: 37
1719 16:55:18.484405 [Byte1]: 37
1720 16:55:18.484984
1721 16:55:18.487557 Set Vref, RX VrefLevel [Byte0]: 38
1722 16:55:18.490716 [Byte1]: 38
1723 16:55:18.491192
1724 16:55:18.494116 Set Vref, RX VrefLevel [Byte0]: 39
1725 16:55:18.498164 [Byte1]: 39
1726 16:55:18.502259
1727 16:55:18.502880 Set Vref, RX VrefLevel [Byte0]: 40
1728 16:55:18.504894 [Byte1]: 40
1729 16:55:18.509312
1730 16:55:18.509889 Set Vref, RX VrefLevel [Byte0]: 41
1731 16:55:18.512791 [Byte1]: 41
1732 16:55:18.517106
1733 16:55:18.517669 Set Vref, RX VrefLevel [Byte0]: 42
1734 16:55:18.519977 [Byte1]: 42
1735 16:55:18.524715
1736 16:55:18.525283 Set Vref, RX VrefLevel [Byte0]: 43
1737 16:55:18.528040 [Byte1]: 43
1738 16:55:18.532052
1739 16:55:18.532620 Set Vref, RX VrefLevel [Byte0]: 44
1740 16:55:18.535178 [Byte1]: 44
1741 16:55:18.539807
1742 16:55:18.540408 Set Vref, RX VrefLevel [Byte0]: 45
1743 16:55:18.543259 [Byte1]: 45
1744 16:55:18.547060
1745 16:55:18.547661 Set Vref, RX VrefLevel [Byte0]: 46
1746 16:55:18.550425 [Byte1]: 46
1747 16:55:18.554890
1748 16:55:18.555455 Set Vref, RX VrefLevel [Byte0]: 47
1749 16:55:18.557822 [Byte1]: 47
1750 16:55:18.562217
1751 16:55:18.562717 Set Vref, RX VrefLevel [Byte0]: 48
1752 16:55:18.565921 [Byte1]: 48
1753 16:55:18.570109
1754 16:55:18.570655 Set Vref, RX VrefLevel [Byte0]: 49
1755 16:55:18.573401 [Byte1]: 49
1756 16:55:18.577545
1757 16:55:18.578015 Set Vref, RX VrefLevel [Byte0]: 50
1758 16:55:18.581442 [Byte1]: 50
1759 16:55:18.585287
1760 16:55:18.585848 Set Vref, RX VrefLevel [Byte0]: 51
1761 16:55:18.588551 [Byte1]: 51
1762 16:55:18.592764
1763 16:55:18.593329 Set Vref, RX VrefLevel [Byte0]: 52
1764 16:55:18.596155 [Byte1]: 52
1765 16:55:18.600331
1766 16:55:18.600894 Set Vref, RX VrefLevel [Byte0]: 53
1767 16:55:18.603625 [Byte1]: 53
1768 16:55:18.608020
1769 16:55:18.608587 Set Vref, RX VrefLevel [Byte0]: 54
1770 16:55:18.611388 [Byte1]: 54
1771 16:55:18.615735
1772 16:55:18.616298 Set Vref, RX VrefLevel [Byte0]: 55
1773 16:55:18.619061 [Byte1]: 55
1774 16:55:18.623266
1775 16:55:18.623829 Set Vref, RX VrefLevel [Byte0]: 56
1776 16:55:18.627254 [Byte1]: 56
1777 16:55:18.630794
1778 16:55:18.631360 Set Vref, RX VrefLevel [Byte0]: 57
1779 16:55:18.634886 [Byte1]: 57
1780 16:55:18.638557
1781 16:55:18.639123 Set Vref, RX VrefLevel [Byte0]: 58
1782 16:55:18.642031 [Byte1]: 58
1783 16:55:18.646186
1784 16:55:18.646794 Set Vref, RX VrefLevel [Byte0]: 59
1785 16:55:18.649470 [Byte1]: 59
1786 16:55:18.654717
1787 16:55:18.655279 Set Vref, RX VrefLevel [Byte0]: 60
1788 16:55:18.656612 [Byte1]: 60
1789 16:55:18.661073
1790 16:55:18.661635 Set Vref, RX VrefLevel [Byte0]: 61
1791 16:55:18.664576 [Byte1]: 61
1792 16:55:18.668797
1793 16:55:18.669387 Set Vref, RX VrefLevel [Byte0]: 62
1794 16:55:18.674179 [Byte1]: 62
1795 16:55:18.676239
1796 16:55:18.676709 Set Vref, RX VrefLevel [Byte0]: 63
1797 16:55:18.679630 [Byte1]: 63
1798 16:55:18.684143
1799 16:55:18.684714 Set Vref, RX VrefLevel [Byte0]: 64
1800 16:55:18.687397 [Byte1]: 64
1801 16:55:18.692538
1802 16:55:18.693106 Set Vref, RX VrefLevel [Byte0]: 65
1803 16:55:18.694619 [Byte1]: 65
1804 16:55:18.699322
1805 16:55:18.699894 Set Vref, RX VrefLevel [Byte0]: 66
1806 16:55:18.702454 [Byte1]: 66
1807 16:55:18.707272
1808 16:55:18.707924 Set Vref, RX VrefLevel [Byte0]: 67
1809 16:55:18.709923 [Byte1]: 67
1810 16:55:18.714998
1811 16:55:18.715575 Set Vref, RX VrefLevel [Byte0]: 68
1812 16:55:18.717519 [Byte1]: 68
1813 16:55:18.721903
1814 16:55:18.722508 Set Vref, RX VrefLevel [Byte0]: 69
1815 16:55:18.725296 [Byte1]: 69
1816 16:55:18.729949
1817 16:55:18.730448 Set Vref, RX VrefLevel [Byte0]: 70
1818 16:55:18.733065 [Byte1]: 70
1819 16:55:18.737139
1820 16:55:18.737713 Set Vref, RX VrefLevel [Byte0]: 71
1821 16:55:18.740644 [Byte1]: 71
1822 16:55:18.745450
1823 16:55:18.746050 Set Vref, RX VrefLevel [Byte0]: 72
1824 16:55:18.748383 [Byte1]: 72
1825 16:55:18.752518
1826 16:55:18.753086 Set Vref, RX VrefLevel [Byte0]: 73
1827 16:55:18.755444 [Byte1]: 73
1828 16:55:18.759971
1829 16:55:18.760547 Set Vref, RX VrefLevel [Byte0]: 74
1830 16:55:18.763167 [Byte1]: 74
1831 16:55:18.767965
1832 16:55:18.768536 Set Vref, RX VrefLevel [Byte0]: 75
1833 16:55:18.770794 [Byte1]: 75
1834 16:55:18.775449
1835 16:55:18.775939 Set Vref, RX VrefLevel [Byte0]: 76
1836 16:55:18.779524 [Byte1]: 76
1837 16:55:18.782919
1838 16:55:18.783387 Set Vref, RX VrefLevel [Byte0]: 77
1839 16:55:18.786109 [Byte1]: 77
1840 16:55:18.790513
1841 16:55:18.791086 Final RX Vref Byte 0 = 52 to rank0
1842 16:55:18.793388 Final RX Vref Byte 1 = 63 to rank0
1843 16:55:18.797271 Final RX Vref Byte 0 = 52 to rank1
1844 16:55:18.800022 Final RX Vref Byte 1 = 63 to rank1==
1845 16:55:18.803806 Dram Type= 6, Freq= 0, CH_1, rank 0
1846 16:55:18.810476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1847 16:55:18.811063 ==
1848 16:55:18.811441 DQS Delay:
1849 16:55:18.811929 DQS0 = 0, DQS1 = 0
1850 16:55:18.813816 DQM Delay:
1851 16:55:18.814422 DQM0 = 93, DQM1 = 83
1852 16:55:18.816929 DQ Delay:
1853 16:55:18.820232 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1854 16:55:18.824517 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1855 16:55:18.826566 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1856 16:55:18.830457 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1857 16:55:18.831119
1858 16:55:18.831499
1859 16:55:18.836922 [DQSOSCAuto] RK0, (LSB)MR18= 0x324f, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1860 16:55:18.840011 CH1 RK0: MR19=606, MR18=324F
1861 16:55:18.846762 CH1_RK0: MR19=0x606, MR18=0x324F, DQSOSC=390, MR23=63, INC=97, DEC=64
1862 16:55:18.847340
1863 16:55:18.850072 ----->DramcWriteLeveling(PI) begin...
1864 16:55:18.850734 ==
1865 16:55:18.853777 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 16:55:18.856915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 16:55:18.857506 ==
1868 16:55:18.860138 Write leveling (Byte 0): 28 => 28
1869 16:55:18.863289 Write leveling (Byte 1): 29 => 29
1870 16:55:18.866943 DramcWriteLeveling(PI) end<-----
1871 16:55:18.867417
1872 16:55:18.867789 ==
1873 16:55:18.869636 Dram Type= 6, Freq= 0, CH_1, rank 1
1874 16:55:18.873061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1875 16:55:18.873543 ==
1876 16:55:18.876534 [Gating] SW mode calibration
1877 16:55:18.883181 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1878 16:55:18.890055 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1879 16:55:18.893739 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1880 16:55:18.899725 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1881 16:55:18.903040 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:55:18.906507 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:55:18.913211 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:55:18.916142 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 16:55:18.919796 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 16:55:18.923067 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:55:18.929591 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:55:18.933476 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 16:55:18.936530 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 16:55:18.942544 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 16:55:18.946549 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 16:55:18.949262 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:55:18.956729 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 16:55:18.959666 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 16:55:18.962957 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 16:55:18.969528 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1897 16:55:18.972752 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1898 16:55:18.976337 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 16:55:18.982764 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 16:55:18.986293 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 16:55:18.989298 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 16:55:18.996332 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 16:55:18.999477 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 16:55:19.002679 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1905 16:55:19.009869 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1906 16:55:19.013211 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 16:55:19.016250 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 16:55:19.023053 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 16:55:19.026118 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 16:55:19.029400 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 16:55:19.035792 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 16:55:19.039208 0 10 4 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
1913 16:55:19.042587 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 16:55:19.049154 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 16:55:19.052193 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 16:55:19.055437 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 16:55:19.063253 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 16:55:19.065987 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 16:55:19.069776 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 16:55:19.075540 0 11 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
1921 16:55:19.079071 0 11 8 | B1->B0 | 4444 4343 | 0 0 | (0 0) (0 0)
1922 16:55:19.082323 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 16:55:19.085666 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 16:55:19.092394 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 16:55:19.095467 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 16:55:19.098957 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 16:55:19.105419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 16:55:19.109216 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1929 16:55:19.112518 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1930 16:55:19.118903 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 16:55:19.122164 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 16:55:19.125735 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 16:55:19.132764 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 16:55:19.135684 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 16:55:19.138533 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 16:55:19.145364 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 16:55:19.148517 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 16:55:19.152555 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 16:55:19.158756 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 16:55:19.162488 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 16:55:19.165534 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 16:55:19.171996 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 16:55:19.175085 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 16:55:19.178506 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1945 16:55:19.185139 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1946 16:55:19.185713 Total UI for P1: 0, mck2ui 16
1947 16:55:19.192348 best dqsien dly found for B0: ( 0, 14, 4)
1948 16:55:19.192917 Total UI for P1: 0, mck2ui 16
1949 16:55:19.195404 best dqsien dly found for B1: ( 0, 14, 4)
1950 16:55:19.201882 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1951 16:55:19.204948 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1952 16:55:19.205423
1953 16:55:19.208908 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1954 16:55:19.212683 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 16:55:19.215170 [Gating] SW calibration Done
1956 16:55:19.215646 ==
1957 16:55:19.218453 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 16:55:19.221483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 16:55:19.221963 ==
1960 16:55:19.225323 RX Vref Scan: 0
1961 16:55:19.225901
1962 16:55:19.226281 RX Vref 0 -> 0, step: 1
1963 16:55:19.226666
1964 16:55:19.228123 RX Delay -130 -> 252, step: 16
1965 16:55:19.231359 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1966 16:55:19.239016 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1967 16:55:19.242041 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1968 16:55:19.244911 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1969 16:55:19.247843 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1970 16:55:19.251480 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1971 16:55:19.258094 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1972 16:55:19.261334 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1973 16:55:19.264642 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1974 16:55:19.268125 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1975 16:55:19.272204 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1976 16:55:19.277944 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1977 16:55:19.281407 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1978 16:55:19.285040 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1979 16:55:19.288319 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1980 16:55:19.291243 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1981 16:55:19.295294 ==
1982 16:55:19.295862 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 16:55:19.301146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 16:55:19.301719 ==
1985 16:55:19.302098 DQS Delay:
1986 16:55:19.304736 DQS0 = 0, DQS1 = 0
1987 16:55:19.305300 DQM Delay:
1988 16:55:19.308129 DQM0 = 89, DQM1 = 83
1989 16:55:19.308598 DQ Delay:
1990 16:55:19.311454 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1991 16:55:19.314903 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1992 16:55:19.317682 DQ8 =61, DQ9 =77, DQ10 =85, DQ11 =77
1993 16:55:19.321127 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =93
1994 16:55:19.321598
1995 16:55:19.321969
1996 16:55:19.322311 ==
1997 16:55:19.324797 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 16:55:19.327867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 16:55:19.328347 ==
2000 16:55:19.328721
2001 16:55:19.329069
2002 16:55:19.330861 TX Vref Scan disable
2003 16:55:19.335286 == TX Byte 0 ==
2004 16:55:19.337716 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2005 16:55:19.340830 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2006 16:55:19.344511 == TX Byte 1 ==
2007 16:55:19.347928 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2008 16:55:19.351222 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2009 16:55:19.351707 ==
2010 16:55:19.354314 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 16:55:19.357683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 16:55:19.361123 ==
2013 16:55:19.372281 TX Vref=22, minBit 13, minWin=27, winSum=449
2014 16:55:19.376349 TX Vref=24, minBit 13, minWin=27, winSum=452
2015 16:55:19.379215 TX Vref=26, minBit 8, minWin=28, winSum=456
2016 16:55:19.381989 TX Vref=28, minBit 13, minWin=27, winSum=457
2017 16:55:19.385505 TX Vref=30, minBit 8, minWin=28, winSum=460
2018 16:55:19.392018 TX Vref=32, minBit 8, minWin=28, winSum=457
2019 16:55:19.395145 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 30
2020 16:55:19.395621
2021 16:55:19.398840 Final TX Range 1 Vref 30
2022 16:55:19.399408
2023 16:55:19.399779 ==
2024 16:55:19.401908 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 16:55:19.405781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 16:55:19.408859 ==
2027 16:55:19.409427
2028 16:55:19.409801
2029 16:55:19.410144 TX Vref Scan disable
2030 16:55:19.412219 == TX Byte 0 ==
2031 16:55:19.415789 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2032 16:55:19.422536 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2033 16:55:19.423135 == TX Byte 1 ==
2034 16:55:19.425641 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2035 16:55:19.432114 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2036 16:55:19.432685
2037 16:55:19.433060 [DATLAT]
2038 16:55:19.433403 Freq=800, CH1 RK1
2039 16:55:19.433740
2040 16:55:19.435506 DATLAT Default: 0xa
2041 16:55:19.436075 0, 0xFFFF, sum = 0
2042 16:55:19.439070 1, 0xFFFF, sum = 0
2043 16:55:19.439549 2, 0xFFFF, sum = 0
2044 16:55:19.441987 3, 0xFFFF, sum = 0
2045 16:55:19.445486 4, 0xFFFF, sum = 0
2046 16:55:19.446064 5, 0xFFFF, sum = 0
2047 16:55:19.448914 6, 0xFFFF, sum = 0
2048 16:55:19.449392 7, 0xFFFF, sum = 0
2049 16:55:19.452348 8, 0xFFFF, sum = 0
2050 16:55:19.452918 9, 0x0, sum = 1
2051 16:55:19.453304 10, 0x0, sum = 2
2052 16:55:19.455679 11, 0x0, sum = 3
2053 16:55:19.456255 12, 0x0, sum = 4
2054 16:55:19.458690 best_step = 10
2055 16:55:19.459160
2056 16:55:19.459528 ==
2057 16:55:19.461944 Dram Type= 6, Freq= 0, CH_1, rank 1
2058 16:55:19.465294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2059 16:55:19.465767 ==
2060 16:55:19.468756 RX Vref Scan: 0
2061 16:55:19.469326
2062 16:55:19.469703 RX Vref 0 -> 0, step: 1
2063 16:55:19.470053
2064 16:55:19.472457 RX Delay -95 -> 252, step: 8
2065 16:55:19.478837 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
2066 16:55:19.482482 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2067 16:55:19.486224 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2068 16:55:19.489118 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2069 16:55:19.492205 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2070 16:55:19.499468 iDelay=209, Bit 5, Center 104 (1 ~ 208) 208
2071 16:55:19.502937 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2072 16:55:19.505447 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2073 16:55:19.509007 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2074 16:55:19.512285 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2075 16:55:19.518793 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2076 16:55:19.522206 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2077 16:55:19.525470 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2078 16:55:19.528876 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2079 16:55:19.532319 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2080 16:55:19.538450 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
2081 16:55:19.538944 ==
2082 16:55:19.541696 Dram Type= 6, Freq= 0, CH_1, rank 1
2083 16:55:19.545170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2084 16:55:19.545644 ==
2085 16:55:19.546019 DQS Delay:
2086 16:55:19.548675 DQS0 = 0, DQS1 = 0
2087 16:55:19.549236 DQM Delay:
2088 16:55:19.551891 DQM0 = 91, DQM1 = 84
2089 16:55:19.552359 DQ Delay:
2090 16:55:19.555256 DQ0 =96, DQ1 =88, DQ2 =80, DQ3 =88
2091 16:55:19.558563 DQ4 =92, DQ5 =104, DQ6 =96, DQ7 =88
2092 16:55:19.562226 DQ8 =68, DQ9 =76, DQ10 =88, DQ11 =80
2093 16:55:19.565199 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =92
2094 16:55:19.565754
2095 16:55:19.566126
2096 16:55:19.575257 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2097 16:55:19.575841 CH1 RK1: MR19=606, MR18=3B10
2098 16:55:19.581810 CH1_RK1: MR19=0x606, MR18=0x3B10, DQSOSC=394, MR23=63, INC=95, DEC=63
2099 16:55:19.585275 [RxdqsGatingPostProcess] freq 800
2100 16:55:19.591682 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2101 16:55:19.595040 Pre-setting of DQS Precalculation
2102 16:55:19.599038 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2103 16:55:19.605079 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2104 16:55:19.612235 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2105 16:55:19.615557
2106 16:55:19.616122
2107 16:55:19.616497 [Calibration Summary] 1600 Mbps
2108 16:55:19.618725 CH 0, Rank 0
2109 16:55:19.619286 SW Impedance : PASS
2110 16:55:19.621871 DUTY Scan : NO K
2111 16:55:19.625034 ZQ Calibration : PASS
2112 16:55:19.625599 Jitter Meter : NO K
2113 16:55:19.628425 CBT Training : PASS
2114 16:55:19.632194 Write leveling : PASS
2115 16:55:19.632758 RX DQS gating : PASS
2116 16:55:19.635042 RX DQ/DQS(RDDQC) : PASS
2117 16:55:19.638328 TX DQ/DQS : PASS
2118 16:55:19.638945 RX DATLAT : PASS
2119 16:55:19.641415 RX DQ/DQS(Engine): PASS
2120 16:55:19.644858 TX OE : NO K
2121 16:55:19.645431 All Pass.
2122 16:55:19.645809
2123 16:55:19.646158 CH 0, Rank 1
2124 16:55:19.648328 SW Impedance : PASS
2125 16:55:19.651088 DUTY Scan : NO K
2126 16:55:19.651561 ZQ Calibration : PASS
2127 16:55:19.654798 Jitter Meter : NO K
2128 16:55:19.658178 CBT Training : PASS
2129 16:55:19.658771 Write leveling : PASS
2130 16:55:19.661578 RX DQS gating : PASS
2131 16:55:19.665018 RX DQ/DQS(RDDQC) : PASS
2132 16:55:19.665511 TX DQ/DQS : PASS
2133 16:55:19.667675 RX DATLAT : PASS
2134 16:55:19.668144 RX DQ/DQS(Engine): PASS
2135 16:55:19.671175 TX OE : NO K
2136 16:55:19.671649 All Pass.
2137 16:55:19.672023
2138 16:55:19.674758 CH 1, Rank 0
2139 16:55:19.675226 SW Impedance : PASS
2140 16:55:19.677551 DUTY Scan : NO K
2141 16:55:19.681234 ZQ Calibration : PASS
2142 16:55:19.681801 Jitter Meter : NO K
2143 16:55:19.684795 CBT Training : PASS
2144 16:55:19.688351 Write leveling : PASS
2145 16:55:19.688916 RX DQS gating : PASS
2146 16:55:19.691577 RX DQ/DQS(RDDQC) : PASS
2147 16:55:19.695057 TX DQ/DQS : PASS
2148 16:55:19.695625 RX DATLAT : PASS
2149 16:55:19.697932 RX DQ/DQS(Engine): PASS
2150 16:55:19.701303 TX OE : NO K
2151 16:55:19.701874 All Pass.
2152 16:55:19.702254
2153 16:55:19.702642 CH 1, Rank 1
2154 16:55:19.704957 SW Impedance : PASS
2155 16:55:19.708058 DUTY Scan : NO K
2156 16:55:19.708625 ZQ Calibration : PASS
2157 16:55:19.711372 Jitter Meter : NO K
2158 16:55:19.711936 CBT Training : PASS
2159 16:55:19.715112 Write leveling : PASS
2160 16:55:19.718251 RX DQS gating : PASS
2161 16:55:19.718863 RX DQ/DQS(RDDQC) : PASS
2162 16:55:19.721017 TX DQ/DQS : PASS
2163 16:55:19.724795 RX DATLAT : PASS
2164 16:55:19.725363 RX DQ/DQS(Engine): PASS
2165 16:55:19.728226 TX OE : NO K
2166 16:55:19.728791 All Pass.
2167 16:55:19.729163
2168 16:55:19.731563 DramC Write-DBI off
2169 16:55:19.734703 PER_BANK_REFRESH: Hybrid Mode
2170 16:55:19.735271 TX_TRACKING: ON
2171 16:55:19.738206 [GetDramInforAfterCalByMRR] Vendor 6.
2172 16:55:19.741432 [GetDramInforAfterCalByMRR] Revision 606.
2173 16:55:19.744702 [GetDramInforAfterCalByMRR] Revision 2 0.
2174 16:55:19.748031 MR0 0x3b3b
2175 16:55:19.748630 MR8 0x5151
2176 16:55:19.751149 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2177 16:55:19.751727
2178 16:55:19.754549 MR0 0x3b3b
2179 16:55:19.755023 MR8 0x5151
2180 16:55:19.757725 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2181 16:55:19.758328
2182 16:55:19.767821 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2183 16:55:19.771156 [FAST_K] Save calibration result to emmc
2184 16:55:19.774307 [FAST_K] Save calibration result to emmc
2185 16:55:19.777304 dram_init: config_dvfs: 1
2186 16:55:19.780887 dramc_set_vcore_voltage set vcore to 662500
2187 16:55:19.781470 Read voltage for 1200, 2
2188 16:55:19.784266 Vio18 = 0
2189 16:55:19.784837 Vcore = 662500
2190 16:55:19.785213 Vdram = 0
2191 16:55:19.787606 Vddq = 0
2192 16:55:19.788179 Vmddr = 0
2193 16:55:19.790685 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2194 16:55:19.797696 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2195 16:55:19.801021 MEM_TYPE=3, freq_sel=15
2196 16:55:19.804768 sv_algorithm_assistance_LP4_1600
2197 16:55:19.807871 ============ PULL DRAM RESETB DOWN ============
2198 16:55:19.811216 ========== PULL DRAM RESETB DOWN end =========
2199 16:55:19.817708 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2200 16:55:19.820911 ===================================
2201 16:55:19.821484 LPDDR4 DRAM CONFIGURATION
2202 16:55:19.824428 ===================================
2203 16:55:19.828269 EX_ROW_EN[0] = 0x0
2204 16:55:19.828835 EX_ROW_EN[1] = 0x0
2205 16:55:19.830917 LP4Y_EN = 0x0
2206 16:55:19.831484 WORK_FSP = 0x0
2207 16:55:19.834553 WL = 0x4
2208 16:55:19.835115 RL = 0x4
2209 16:55:19.837772 BL = 0x2
2210 16:55:19.840776 RPST = 0x0
2211 16:55:19.841340 RD_PRE = 0x0
2212 16:55:19.844141 WR_PRE = 0x1
2213 16:55:19.844711 WR_PST = 0x0
2214 16:55:19.848499 DBI_WR = 0x0
2215 16:55:19.849063 DBI_RD = 0x0
2216 16:55:19.850567 OTF = 0x1
2217 16:55:19.854069 ===================================
2218 16:55:19.857919 ===================================
2219 16:55:19.858570 ANA top config
2220 16:55:19.860838 ===================================
2221 16:55:19.864156 DLL_ASYNC_EN = 0
2222 16:55:19.867114 ALL_SLAVE_EN = 0
2223 16:55:19.867589 NEW_RANK_MODE = 1
2224 16:55:19.870533 DLL_IDLE_MODE = 1
2225 16:55:19.874240 LP45_APHY_COMB_EN = 1
2226 16:55:19.877505 TX_ODT_DIS = 1
2227 16:55:19.878285 NEW_8X_MODE = 1
2228 16:55:19.880352 ===================================
2229 16:55:19.884055 ===================================
2230 16:55:19.887223 data_rate = 2400
2231 16:55:19.890598 CKR = 1
2232 16:55:19.894344 DQ_P2S_RATIO = 8
2233 16:55:19.897448 ===================================
2234 16:55:19.900913 CA_P2S_RATIO = 8
2235 16:55:19.903978 DQ_CA_OPEN = 0
2236 16:55:19.904547 DQ_SEMI_OPEN = 0
2237 16:55:19.906956 CA_SEMI_OPEN = 0
2238 16:55:19.910708 CA_FULL_RATE = 0
2239 16:55:19.913951 DQ_CKDIV4_EN = 0
2240 16:55:19.917552 CA_CKDIV4_EN = 0
2241 16:55:19.920542 CA_PREDIV_EN = 0
2242 16:55:19.921033 PH8_DLY = 17
2243 16:55:19.923856 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2244 16:55:19.927133 DQ_AAMCK_DIV = 4
2245 16:55:19.930741 CA_AAMCK_DIV = 4
2246 16:55:19.934256 CA_ADMCK_DIV = 4
2247 16:55:19.937400 DQ_TRACK_CA_EN = 0
2248 16:55:19.940428 CA_PICK = 1200
2249 16:55:19.941028 CA_MCKIO = 1200
2250 16:55:19.943883 MCKIO_SEMI = 0
2251 16:55:19.947070 PLL_FREQ = 2366
2252 16:55:19.950280 DQ_UI_PI_RATIO = 32
2253 16:55:19.953708 CA_UI_PI_RATIO = 0
2254 16:55:19.957828 ===================================
2255 16:55:19.960452 ===================================
2256 16:55:19.963549 memory_type:LPDDR4
2257 16:55:19.964123 GP_NUM : 10
2258 16:55:19.966417 SRAM_EN : 1
2259 16:55:19.966898 MD32_EN : 0
2260 16:55:19.969736 ===================================
2261 16:55:19.973000 [ANA_INIT] >>>>>>>>>>>>>>
2262 16:55:19.976645 <<<<<< [CONFIGURE PHASE]: ANA_TX
2263 16:55:19.979765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2264 16:55:19.983353 ===================================
2265 16:55:19.986731 data_rate = 2400,PCW = 0X5b00
2266 16:55:19.989944 ===================================
2267 16:55:19.993444 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2268 16:55:20.000103 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 16:55:20.003237 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 16:55:20.010269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2271 16:55:20.013747 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2272 16:55:20.017133 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2273 16:55:20.017740 [ANA_INIT] flow start
2274 16:55:20.020044 [ANA_INIT] PLL >>>>>>>>
2275 16:55:20.023070 [ANA_INIT] PLL <<<<<<<<
2276 16:55:20.023545 [ANA_INIT] MIDPI >>>>>>>>
2277 16:55:20.026808 [ANA_INIT] MIDPI <<<<<<<<
2278 16:55:20.030232 [ANA_INIT] DLL >>>>>>>>
2279 16:55:20.030851 [ANA_INIT] DLL <<<<<<<<
2280 16:55:20.033217 [ANA_INIT] flow end
2281 16:55:20.037101 ============ LP4 DIFF to SE enter ============
2282 16:55:20.043016 ============ LP4 DIFF to SE exit ============
2283 16:55:20.043578 [ANA_INIT] <<<<<<<<<<<<<
2284 16:55:20.046578 [Flow] Enable top DCM control >>>>>
2285 16:55:20.049727 [Flow] Enable top DCM control <<<<<
2286 16:55:20.053099 Enable DLL master slave shuffle
2287 16:55:20.059772 ==============================================================
2288 16:55:20.060340 Gating Mode config
2289 16:55:20.066615 ==============================================================
2290 16:55:20.069826 Config description:
2291 16:55:20.076139 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2292 16:55:20.082778 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2293 16:55:20.089318 SELPH_MODE 0: By rank 1: By Phase
2294 16:55:20.095675 ==============================================================
2295 16:55:20.099605 GAT_TRACK_EN = 1
2296 16:55:20.100177 RX_GATING_MODE = 2
2297 16:55:20.102263 RX_GATING_TRACK_MODE = 2
2298 16:55:20.105956 SELPH_MODE = 1
2299 16:55:20.109348 PICG_EARLY_EN = 1
2300 16:55:20.112602 VALID_LAT_VALUE = 1
2301 16:55:20.119876 ==============================================================
2302 16:55:20.122540 Enter into Gating configuration >>>>
2303 16:55:20.125749 Exit from Gating configuration <<<<
2304 16:55:20.129482 Enter into DVFS_PRE_config >>>>>
2305 16:55:20.139007 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2306 16:55:20.142406 Exit from DVFS_PRE_config <<<<<
2307 16:55:20.145880 Enter into PICG configuration >>>>
2308 16:55:20.149139 Exit from PICG configuration <<<<
2309 16:55:20.152304 [RX_INPUT] configuration >>>>>
2310 16:55:20.155775 [RX_INPUT] configuration <<<<<
2311 16:55:20.159300 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2312 16:55:20.165834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2313 16:55:20.172414 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2314 16:55:20.175563 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2315 16:55:20.182628 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2316 16:55:20.189353 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2317 16:55:20.191894 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2318 16:55:20.199172 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2319 16:55:20.202142 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2320 16:55:20.205489 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2321 16:55:20.208832 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2322 16:55:20.216042 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2323 16:55:20.218749 ===================================
2324 16:55:20.219316 LPDDR4 DRAM CONFIGURATION
2325 16:55:20.222236 ===================================
2326 16:55:20.225406 EX_ROW_EN[0] = 0x0
2327 16:55:20.228869 EX_ROW_EN[1] = 0x0
2328 16:55:20.229443 LP4Y_EN = 0x0
2329 16:55:20.231822 WORK_FSP = 0x0
2330 16:55:20.232395 WL = 0x4
2331 16:55:20.235751 RL = 0x4
2332 16:55:20.236318 BL = 0x2
2333 16:55:20.238962 RPST = 0x0
2334 16:55:20.239522 RD_PRE = 0x0
2335 16:55:20.242085 WR_PRE = 0x1
2336 16:55:20.242710 WR_PST = 0x0
2337 16:55:20.245551 DBI_WR = 0x0
2338 16:55:20.246114 DBI_RD = 0x0
2339 16:55:20.248596 OTF = 0x1
2340 16:55:20.252238 ===================================
2341 16:55:20.255004 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2342 16:55:20.258578 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2343 16:55:20.265130 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2344 16:55:20.268527 ===================================
2345 16:55:20.269095 LPDDR4 DRAM CONFIGURATION
2346 16:55:20.271469 ===================================
2347 16:55:20.274990 EX_ROW_EN[0] = 0x10
2348 16:55:20.278240 EX_ROW_EN[1] = 0x0
2349 16:55:20.278857 LP4Y_EN = 0x0
2350 16:55:20.281772 WORK_FSP = 0x0
2351 16:55:20.282341 WL = 0x4
2352 16:55:20.285272 RL = 0x4
2353 16:55:20.285838 BL = 0x2
2354 16:55:20.288245 RPST = 0x0
2355 16:55:20.288808 RD_PRE = 0x0
2356 16:55:20.291406 WR_PRE = 0x1
2357 16:55:20.291878 WR_PST = 0x0
2358 16:55:20.294390 DBI_WR = 0x0
2359 16:55:20.294886 DBI_RD = 0x0
2360 16:55:20.297998 OTF = 0x1
2361 16:55:20.301459 ===================================
2362 16:55:20.308351 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2363 16:55:20.308805 ==
2364 16:55:20.311903 Dram Type= 6, Freq= 0, CH_0, rank 0
2365 16:55:20.314543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 16:55:20.315004 ==
2367 16:55:20.317919 [Duty_Offset_Calibration]
2368 16:55:20.318407 B0:2 B1:0 CA:1
2369 16:55:20.318779
2370 16:55:20.321082 [DutyScan_Calibration_Flow] k_type=0
2371 16:55:20.330536
2372 16:55:20.331080 ==CLK 0==
2373 16:55:20.334177 Final CLK duty delay cell = -4
2374 16:55:20.337296 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2375 16:55:20.340569 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2376 16:55:20.344276 [-4] AVG Duty = 4953%(X100)
2377 16:55:20.344833
2378 16:55:20.347240 CH0 CLK Duty spec in!! Max-Min= 156%
2379 16:55:20.350719 [DutyScan_Calibration_Flow] ====Done====
2380 16:55:20.351174
2381 16:55:20.353562 [DutyScan_Calibration_Flow] k_type=1
2382 16:55:20.369462
2383 16:55:20.370010 ==DQS 0 ==
2384 16:55:20.373273 Final DQS duty delay cell = 0
2385 16:55:20.376167 [0] MAX Duty = 5187%(X100), DQS PI = 30
2386 16:55:20.379321 [0] MIN Duty = 4938%(X100), DQS PI = 0
2387 16:55:20.379777 [0] AVG Duty = 5062%(X100)
2388 16:55:20.382931
2389 16:55:20.383382 ==DQS 1 ==
2390 16:55:20.386564 Final DQS duty delay cell = -4
2391 16:55:20.389708 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2392 16:55:20.392702 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2393 16:55:20.396170 [-4] AVG Duty = 5031%(X100)
2394 16:55:20.396725
2395 16:55:20.399624 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2396 16:55:20.400235
2397 16:55:20.402684 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2398 16:55:20.405982 [DutyScan_Calibration_Flow] ====Done====
2399 16:55:20.406603
2400 16:55:20.409693 [DutyScan_Calibration_Flow] k_type=3
2401 16:55:20.425875
2402 16:55:20.426467 ==DQM 0 ==
2403 16:55:20.428978 Final DQM duty delay cell = 0
2404 16:55:20.432237 [0] MAX Duty = 5062%(X100), DQS PI = 24
2405 16:55:20.435673 [0] MIN Duty = 4813%(X100), DQS PI = 2
2406 16:55:20.438734 [0] AVG Duty = 4937%(X100)
2407 16:55:20.439288
2408 16:55:20.439683 ==DQM 1 ==
2409 16:55:20.441657 Final DQM duty delay cell = -4
2410 16:55:20.445849 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2411 16:55:20.449024 [-4] MIN Duty = 4813%(X100), DQS PI = 12
2412 16:55:20.452157 [-4] AVG Duty = 4906%(X100)
2413 16:55:20.452725
2414 16:55:20.455155 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2415 16:55:20.455612
2416 16:55:20.459013 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2417 16:55:20.462204 [DutyScan_Calibration_Flow] ====Done====
2418 16:55:20.462815
2419 16:55:20.465491 [DutyScan_Calibration_Flow] k_type=2
2420 16:55:20.481578
2421 16:55:20.482167 ==DQ 0 ==
2422 16:55:20.484893 Final DQ duty delay cell = -4
2423 16:55:20.488107 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2424 16:55:20.491557 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2425 16:55:20.495221 [-4] AVG Duty = 4969%(X100)
2426 16:55:20.495800
2427 16:55:20.496178 ==DQ 1 ==
2428 16:55:20.498023 Final DQ duty delay cell = 0
2429 16:55:20.502115 [0] MAX Duty = 4938%(X100), DQS PI = 4
2430 16:55:20.505696 [0] MIN Duty = 4907%(X100), DQS PI = 0
2431 16:55:20.506275 [0] AVG Duty = 4922%(X100)
2432 16:55:20.507862
2433 16:55:20.511191 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2434 16:55:20.511770
2435 16:55:20.514635 CH0 DQ 1 Duty spec in!! Max-Min= 31%
2436 16:55:20.517766 [DutyScan_Calibration_Flow] ====Done====
2437 16:55:20.518339 ==
2438 16:55:20.521200 Dram Type= 6, Freq= 0, CH_1, rank 0
2439 16:55:20.524216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2440 16:55:20.524710 ==
2441 16:55:20.528111 [Duty_Offset_Calibration]
2442 16:55:20.528693 B0:0 B1:-1 CA:2
2443 16:55:20.529077
2444 16:55:20.531059 [DutyScan_Calibration_Flow] k_type=0
2445 16:55:20.541748
2446 16:55:20.542325 ==CLK 0==
2447 16:55:20.545171 Final CLK duty delay cell = 0
2448 16:55:20.548407 [0] MAX Duty = 5156%(X100), DQS PI = 16
2449 16:55:20.552080 [0] MIN Duty = 4969%(X100), DQS PI = 44
2450 16:55:20.552665 [0] AVG Duty = 5062%(X100)
2451 16:55:20.554998
2452 16:55:20.555593 CH1 CLK Duty spec in!! Max-Min= 187%
2453 16:55:20.561696 [DutyScan_Calibration_Flow] ====Done====
2454 16:55:20.562275
2455 16:55:20.565040 [DutyScan_Calibration_Flow] k_type=1
2456 16:55:20.580723
2457 16:55:20.581352 ==DQS 0 ==
2458 16:55:20.584553 Final DQS duty delay cell = 0
2459 16:55:20.587419 [0] MAX Duty = 5093%(X100), DQS PI = 24
2460 16:55:20.590637 [0] MIN Duty = 4969%(X100), DQS PI = 0
2461 16:55:20.594318 [0] AVG Duty = 5031%(X100)
2462 16:55:20.594835
2463 16:55:20.595219 ==DQS 1 ==
2464 16:55:20.597816 Final DQS duty delay cell = 0
2465 16:55:20.601045 [0] MAX Duty = 5156%(X100), DQS PI = 0
2466 16:55:20.604031 [0] MIN Duty = 4844%(X100), DQS PI = 36
2467 16:55:20.607787 [0] AVG Duty = 5000%(X100)
2468 16:55:20.608365
2469 16:55:20.610960 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2470 16:55:20.611539
2471 16:55:20.614325 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2472 16:55:20.617350 [DutyScan_Calibration_Flow] ====Done====
2473 16:55:20.617929
2474 16:55:20.620831 [DutyScan_Calibration_Flow] k_type=3
2475 16:55:20.637261
2476 16:55:20.637833 ==DQM 0 ==
2477 16:55:20.641199 Final DQM duty delay cell = 4
2478 16:55:20.643999 [4] MAX Duty = 5093%(X100), DQS PI = 6
2479 16:55:20.647866 [4] MIN Duty = 4969%(X100), DQS PI = 30
2480 16:55:20.648483 [4] AVG Duty = 5031%(X100)
2481 16:55:20.650658
2482 16:55:20.651236 ==DQM 1 ==
2483 16:55:20.653902 Final DQM duty delay cell = -4
2484 16:55:20.657924 [-4] MAX Duty = 5031%(X100), DQS PI = 60
2485 16:55:20.660590 [-4] MIN Duty = 4751%(X100), DQS PI = 36
2486 16:55:20.663952 [-4] AVG Duty = 4891%(X100)
2487 16:55:20.664535
2488 16:55:20.667358 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2489 16:55:20.667933
2490 16:55:20.670728 CH1 DQM 1 Duty spec in!! Max-Min= 280%
2491 16:55:20.674206 [DutyScan_Calibration_Flow] ====Done====
2492 16:55:20.674824
2493 16:55:20.677391 [DutyScan_Calibration_Flow] k_type=2
2494 16:55:20.694297
2495 16:55:20.694905 ==DQ 0 ==
2496 16:55:20.697987 Final DQ duty delay cell = 0
2497 16:55:20.700981 [0] MAX Duty = 5031%(X100), DQS PI = 14
2498 16:55:20.704456 [0] MIN Duty = 4938%(X100), DQS PI = 46
2499 16:55:20.704944 [0] AVG Duty = 4984%(X100)
2500 16:55:20.707943
2501 16:55:20.708524 ==DQ 1 ==
2502 16:55:20.711049 Final DQ duty delay cell = 0
2503 16:55:20.714213 [0] MAX Duty = 5031%(X100), DQS PI = 2
2504 16:55:20.717579 [0] MIN Duty = 4813%(X100), DQS PI = 36
2505 16:55:20.718154 [0] AVG Duty = 4922%(X100)
2506 16:55:20.718575
2507 16:55:20.721003 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2508 16:55:20.721587
2509 16:55:20.723901 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2510 16:55:20.731274 [DutyScan_Calibration_Flow] ====Done====
2511 16:55:20.733981 nWR fixed to 30
2512 16:55:20.734501 [ModeRegInit_LP4] CH0 RK0
2513 16:55:20.737078 [ModeRegInit_LP4] CH0 RK1
2514 16:55:20.740928 [ModeRegInit_LP4] CH1 RK0
2515 16:55:20.741521 [ModeRegInit_LP4] CH1 RK1
2516 16:55:20.743836 match AC timing 7
2517 16:55:20.747564 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2518 16:55:20.751233 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2519 16:55:20.757275 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2520 16:55:20.760357 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2521 16:55:20.767203 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2522 16:55:20.767788 ==
2523 16:55:20.770998 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 16:55:20.774187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 16:55:20.774818 ==
2526 16:55:20.780362 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2527 16:55:20.786994 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2528 16:55:20.794241 [CA 0] Center 38 (7~69) winsize 63
2529 16:55:20.797450 [CA 1] Center 38 (7~69) winsize 63
2530 16:55:20.800568 [CA 2] Center 34 (4~65) winsize 62
2531 16:55:20.803970 [CA 3] Center 34 (4~65) winsize 62
2532 16:55:20.807278 [CA 4] Center 34 (4~64) winsize 61
2533 16:55:20.810852 [CA 5] Center 32 (2~63) winsize 62
2534 16:55:20.811419
2535 16:55:20.814510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2536 16:55:20.815079
2537 16:55:20.817650 [CATrainingPosCal] consider 1 rank data
2538 16:55:20.820654 u2DelayCellTimex100 = 270/100 ps
2539 16:55:20.823481 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2540 16:55:20.830010 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2541 16:55:20.833398 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2542 16:55:20.837359 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2543 16:55:20.840314 CA4 delay=34 (4~64),Diff = 2 PI (9 cell)
2544 16:55:20.843481 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2545 16:55:20.844130
2546 16:55:20.846828 CA PerBit enable=1, Macro0, CA PI delay=32
2547 16:55:20.847306
2548 16:55:20.850620 [CBTSetCACLKResult] CA Dly = 32
2549 16:55:20.853094 CS Dly: 6 (0~37)
2550 16:55:20.853567 ==
2551 16:55:20.856404 Dram Type= 6, Freq= 0, CH_0, rank 1
2552 16:55:20.860046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2553 16:55:20.860639 ==
2554 16:55:20.863519 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2555 16:55:20.870048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2556 16:55:20.879957 [CA 0] Center 38 (8~69) winsize 62
2557 16:55:20.883018 [CA 1] Center 38 (7~69) winsize 63
2558 16:55:20.886428 [CA 2] Center 35 (5~66) winsize 62
2559 16:55:20.890000 [CA 3] Center 35 (4~66) winsize 63
2560 16:55:20.892709 [CA 4] Center 34 (4~65) winsize 62
2561 16:55:20.896324 [CA 5] Center 33 (3~64) winsize 62
2562 16:55:20.896888
2563 16:55:20.899535 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2564 16:55:20.900100
2565 16:55:20.902758 [CATrainingPosCal] consider 2 rank data
2566 16:55:20.906098 u2DelayCellTimex100 = 270/100 ps
2567 16:55:20.909466 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2568 16:55:20.916263 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2569 16:55:20.920219 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2570 16:55:20.922964 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
2571 16:55:20.925748 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2572 16:55:20.929648 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2573 16:55:20.930217
2574 16:55:20.932861 CA PerBit enable=1, Macro0, CA PI delay=33
2575 16:55:20.933426
2576 16:55:20.936509 [CBTSetCACLKResult] CA Dly = 33
2577 16:55:20.936979 CS Dly: 7 (0~39)
2578 16:55:20.937352
2579 16:55:20.940013 ----->DramcWriteLeveling(PI) begin...
2580 16:55:20.942793 ==
2581 16:55:20.945889 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 16:55:20.949281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 16:55:20.949883 ==
2584 16:55:20.952550 Write leveling (Byte 0): 35 => 35
2585 16:55:20.956340 Write leveling (Byte 1): 31 => 31
2586 16:55:20.960192 DramcWriteLeveling(PI) end<-----
2587 16:55:20.960664
2588 16:55:20.961035 ==
2589 16:55:20.962311 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 16:55:20.965953 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 16:55:20.966620 ==
2592 16:55:20.969392 [Gating] SW mode calibration
2593 16:55:20.976590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2594 16:55:20.983281 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2595 16:55:20.985591 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2596 16:55:20.989373 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2597 16:55:20.995898 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 16:55:20.999478 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 16:55:21.002221 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 16:55:21.005780 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 16:55:21.012261 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2602 16:55:21.016572 0 15 28 | B1->B0 | 3333 2323 | 1 0 | (1 1) (1 0)
2603 16:55:21.019861 1 0 0 | B1->B0 | 3131 2323 | 0 0 | (1 0) (0 0)
2604 16:55:21.025526 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 16:55:21.029882 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 16:55:21.032476 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 16:55:21.038714 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 16:55:21.042726 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 16:55:21.045516 1 0 24 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
2610 16:55:21.051910 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2611 16:55:21.055195 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2612 16:55:21.058774 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 16:55:21.065744 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 16:55:21.069485 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 16:55:21.072470 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 16:55:21.079455 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 16:55:21.082241 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 16:55:21.085467 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2619 16:55:21.092109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2620 16:55:21.095551 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 16:55:21.098829 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 16:55:21.105213 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 16:55:21.108524 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 16:55:21.112202 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 16:55:21.118320 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 16:55:21.121797 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 16:55:21.125252 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 16:55:21.131642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 16:55:21.135842 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 16:55:21.138553 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 16:55:21.145061 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 16:55:21.148266 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 16:55:21.151688 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2634 16:55:21.158378 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2635 16:55:21.161228 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2636 16:55:21.164722 Total UI for P1: 0, mck2ui 16
2637 16:55:21.168697 best dqsien dly found for B0: ( 1, 3, 26)
2638 16:55:21.171646 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2639 16:55:21.177939 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2640 16:55:21.178556 Total UI for P1: 0, mck2ui 16
2641 16:55:21.181135 best dqsien dly found for B1: ( 1, 4, 2)
2642 16:55:21.188724 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2643 16:55:21.191533 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2644 16:55:21.192109
2645 16:55:21.194698 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2646 16:55:21.198525 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2647 16:55:21.201456 [Gating] SW calibration Done
2648 16:55:21.202029 ==
2649 16:55:21.204694 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 16:55:21.208024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 16:55:21.208609 ==
2652 16:55:21.211150 RX Vref Scan: 0
2653 16:55:21.211631
2654 16:55:21.212109 RX Vref 0 -> 0, step: 1
2655 16:55:21.212564
2656 16:55:21.215095 RX Delay -40 -> 252, step: 8
2657 16:55:21.217989 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2658 16:55:21.224803 iDelay=208, Bit 1, Center 119 (48 ~ 191) 144
2659 16:55:21.227642 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2660 16:55:21.231270 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2661 16:55:21.234705 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2662 16:55:21.238563 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2663 16:55:21.241519 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2664 16:55:21.247786 iDelay=208, Bit 7, Center 131 (56 ~ 207) 152
2665 16:55:21.251103 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2666 16:55:21.254621 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2667 16:55:21.257718 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2668 16:55:21.260847 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2669 16:55:21.267381 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2670 16:55:21.271304 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2671 16:55:21.274531 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2672 16:55:21.277900 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2673 16:55:21.278408 ==
2674 16:55:21.281104 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 16:55:21.287080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 16:55:21.287575 ==
2677 16:55:21.287946 DQS Delay:
2678 16:55:21.290596 DQS0 = 0, DQS1 = 0
2679 16:55:21.291066 DQM Delay:
2680 16:55:21.294239 DQM0 = 123, DQM1 = 110
2681 16:55:21.294856 DQ Delay:
2682 16:55:21.297522 DQ0 =123, DQ1 =119, DQ2 =119, DQ3 =119
2683 16:55:21.300795 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =131
2684 16:55:21.303956 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2685 16:55:21.307615 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2686 16:55:21.308189
2687 16:55:21.308560
2688 16:55:21.308901 ==
2689 16:55:21.310578 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 16:55:21.317969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 16:55:21.318582 ==
2692 16:55:21.318965
2693 16:55:21.319306
2694 16:55:21.319632 TX Vref Scan disable
2695 16:55:21.320386 == TX Byte 0 ==
2696 16:55:21.323994 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2697 16:55:21.327619 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2698 16:55:21.331743 == TX Byte 1 ==
2699 16:55:21.333710 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2700 16:55:21.340471 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2701 16:55:21.341051 ==
2702 16:55:21.343889 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 16:55:21.346886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 16:55:21.347464 ==
2705 16:55:21.359248 TX Vref=22, minBit 7, minWin=22, winSum=391
2706 16:55:21.361530 TX Vref=24, minBit 7, minWin=23, winSum=397
2707 16:55:21.365147 TX Vref=26, minBit 0, minWin=24, winSum=403
2708 16:55:21.368561 TX Vref=28, minBit 7, minWin=24, winSum=412
2709 16:55:21.371614 TX Vref=30, minBit 1, minWin=25, winSum=414
2710 16:55:21.378482 TX Vref=32, minBit 1, minWin=25, winSum=413
2711 16:55:21.381281 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 30
2712 16:55:21.381776
2713 16:55:21.384646 Final TX Range 1 Vref 30
2714 16:55:21.385233
2715 16:55:21.385608 ==
2716 16:55:21.387788 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 16:55:21.391104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 16:55:21.394292 ==
2719 16:55:21.394973
2720 16:55:21.395361
2721 16:55:21.395716 TX Vref Scan disable
2722 16:55:21.398033 == TX Byte 0 ==
2723 16:55:21.401715 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2724 16:55:21.408341 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2725 16:55:21.408913 == TX Byte 1 ==
2726 16:55:21.411085 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2727 16:55:21.418036 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2728 16:55:21.418641
2729 16:55:21.419015 [DATLAT]
2730 16:55:21.419493 Freq=1200, CH0 RK0
2731 16:55:21.420022
2732 16:55:21.421698 DATLAT Default: 0xd
2733 16:55:21.422263 0, 0xFFFF, sum = 0
2734 16:55:21.424870 1, 0xFFFF, sum = 0
2735 16:55:21.427893 2, 0xFFFF, sum = 0
2736 16:55:21.428372 3, 0xFFFF, sum = 0
2737 16:55:21.431841 4, 0xFFFF, sum = 0
2738 16:55:21.432413 5, 0xFFFF, sum = 0
2739 16:55:21.434848 6, 0xFFFF, sum = 0
2740 16:55:21.435329 7, 0xFFFF, sum = 0
2741 16:55:21.438217 8, 0xFFFF, sum = 0
2742 16:55:21.438830 9, 0xFFFF, sum = 0
2743 16:55:21.441581 10, 0xFFFF, sum = 0
2744 16:55:21.442155 11, 0xFFFF, sum = 0
2745 16:55:21.444576 12, 0x0, sum = 1
2746 16:55:21.445060 13, 0x0, sum = 2
2747 16:55:21.448173 14, 0x0, sum = 3
2748 16:55:21.448762 15, 0x0, sum = 4
2749 16:55:21.449149 best_step = 13
2750 16:55:21.451062
2751 16:55:21.451534 ==
2752 16:55:21.454829 Dram Type= 6, Freq= 0, CH_0, rank 0
2753 16:55:21.458520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2754 16:55:21.459092 ==
2755 16:55:21.459473 RX Vref Scan: 1
2756 16:55:21.459823
2757 16:55:21.461020 Set Vref Range= 32 -> 127
2758 16:55:21.461491
2759 16:55:21.465054 RX Vref 32 -> 127, step: 1
2760 16:55:21.465618
2761 16:55:21.467997 RX Delay -13 -> 252, step: 4
2762 16:55:21.468561
2763 16:55:21.471247 Set Vref, RX VrefLevel [Byte0]: 32
2764 16:55:21.474674 [Byte1]: 32
2765 16:55:21.475149
2766 16:55:21.477784 Set Vref, RX VrefLevel [Byte0]: 33
2767 16:55:21.481107 [Byte1]: 33
2768 16:55:21.484883
2769 16:55:21.485467 Set Vref, RX VrefLevel [Byte0]: 34
2770 16:55:21.487628 [Byte1]: 34
2771 16:55:21.492256
2772 16:55:21.492726 Set Vref, RX VrefLevel [Byte0]: 35
2773 16:55:21.495920 [Byte1]: 35
2774 16:55:21.500229
2775 16:55:21.500699 Set Vref, RX VrefLevel [Byte0]: 36
2776 16:55:21.503663 [Byte1]: 36
2777 16:55:21.508211
2778 16:55:21.508779 Set Vref, RX VrefLevel [Byte0]: 37
2779 16:55:21.511600 [Byte1]: 37
2780 16:55:21.516228
2781 16:55:21.516798 Set Vref, RX VrefLevel [Byte0]: 38
2782 16:55:21.522754 [Byte1]: 38
2783 16:55:21.523320
2784 16:55:21.525847 Set Vref, RX VrefLevel [Byte0]: 39
2785 16:55:21.530047 [Byte1]: 39
2786 16:55:21.530651
2787 16:55:21.532536 Set Vref, RX VrefLevel [Byte0]: 40
2788 16:55:21.536138 [Byte1]: 40
2789 16:55:21.539965
2790 16:55:21.540532 Set Vref, RX VrefLevel [Byte0]: 41
2791 16:55:21.543007 [Byte1]: 41
2792 16:55:21.547638
2793 16:55:21.548204 Set Vref, RX VrefLevel [Byte0]: 42
2794 16:55:21.550717 [Byte1]: 42
2795 16:55:21.555499
2796 16:55:21.556137 Set Vref, RX VrefLevel [Byte0]: 43
2797 16:55:21.558887 [Byte1]: 43
2798 16:55:21.563278
2799 16:55:21.563845 Set Vref, RX VrefLevel [Byte0]: 44
2800 16:55:21.566982 [Byte1]: 44
2801 16:55:21.571748
2802 16:55:21.572310 Set Vref, RX VrefLevel [Byte0]: 45
2803 16:55:21.574535 [Byte1]: 45
2804 16:55:21.578997
2805 16:55:21.579558 Set Vref, RX VrefLevel [Byte0]: 46
2806 16:55:21.582633 [Byte1]: 46
2807 16:55:21.587920
2808 16:55:21.588497 Set Vref, RX VrefLevel [Byte0]: 47
2809 16:55:21.590064 [Byte1]: 47
2810 16:55:21.595126
2811 16:55:21.595689 Set Vref, RX VrefLevel [Byte0]: 48
2812 16:55:21.598310 [Byte1]: 48
2813 16:55:21.602736
2814 16:55:21.603295 Set Vref, RX VrefLevel [Byte0]: 49
2815 16:55:21.606325 [Byte1]: 49
2816 16:55:21.610976
2817 16:55:21.611540 Set Vref, RX VrefLevel [Byte0]: 50
2818 16:55:21.613963 [Byte1]: 50
2819 16:55:21.618805
2820 16:55:21.619375 Set Vref, RX VrefLevel [Byte0]: 51
2821 16:55:21.622139 [Byte1]: 51
2822 16:55:21.626424
2823 16:55:21.626918 Set Vref, RX VrefLevel [Byte0]: 52
2824 16:55:21.629797 [Byte1]: 52
2825 16:55:21.634829
2826 16:55:21.635393 Set Vref, RX VrefLevel [Byte0]: 53
2827 16:55:21.638142 [Byte1]: 53
2828 16:55:21.642567
2829 16:55:21.643131 Set Vref, RX VrefLevel [Byte0]: 54
2830 16:55:21.645384 [Byte1]: 54
2831 16:55:21.650497
2832 16:55:21.651056 Set Vref, RX VrefLevel [Byte0]: 55
2833 16:55:21.653878 [Byte1]: 55
2834 16:55:21.658210
2835 16:55:21.658817 Set Vref, RX VrefLevel [Byte0]: 56
2836 16:55:21.661594 [Byte1]: 56
2837 16:55:21.666270
2838 16:55:21.666864 Set Vref, RX VrefLevel [Byte0]: 57
2839 16:55:21.669410 [Byte1]: 57
2840 16:55:21.674456
2841 16:55:21.675024 Set Vref, RX VrefLevel [Byte0]: 58
2842 16:55:21.677338 [Byte1]: 58
2843 16:55:21.682476
2844 16:55:21.682948 Set Vref, RX VrefLevel [Byte0]: 59
2845 16:55:21.685208 [Byte1]: 59
2846 16:55:21.689847
2847 16:55:21.690337 Set Vref, RX VrefLevel [Byte0]: 60
2848 16:55:21.692870 [Byte1]: 60
2849 16:55:21.697838
2850 16:55:21.698310 Set Vref, RX VrefLevel [Byte0]: 61
2851 16:55:21.700776 [Byte1]: 61
2852 16:55:21.705908
2853 16:55:21.706510 Set Vref, RX VrefLevel [Byte0]: 62
2854 16:55:21.708679 [Byte1]: 62
2855 16:55:21.713383
2856 16:55:21.713949 Set Vref, RX VrefLevel [Byte0]: 63
2857 16:55:21.716856 [Byte1]: 63
2858 16:55:21.721495
2859 16:55:21.722060 Set Vref, RX VrefLevel [Byte0]: 64
2860 16:55:21.724912 [Byte1]: 64
2861 16:55:21.729282
2862 16:55:21.729846 Set Vref, RX VrefLevel [Byte0]: 65
2863 16:55:21.732500 [Byte1]: 65
2864 16:55:21.737124
2865 16:55:21.737690 Set Vref, RX VrefLevel [Byte0]: 66
2866 16:55:21.740348 [Byte1]: 66
2867 16:55:21.744980
2868 16:55:21.745556 Set Vref, RX VrefLevel [Byte0]: 67
2869 16:55:21.748272 [Byte1]: 67
2870 16:55:21.752909
2871 16:55:21.753477 Set Vref, RX VrefLevel [Byte0]: 68
2872 16:55:21.756730 [Byte1]: 68
2873 16:55:21.760924
2874 16:55:21.761491 Final RX Vref Byte 0 = 57 to rank0
2875 16:55:21.763957 Final RX Vref Byte 1 = 51 to rank0
2876 16:55:21.767736 Final RX Vref Byte 0 = 57 to rank1
2877 16:55:21.771298 Final RX Vref Byte 1 = 51 to rank1==
2878 16:55:21.773953 Dram Type= 6, Freq= 0, CH_0, rank 0
2879 16:55:21.780588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2880 16:55:21.781161 ==
2881 16:55:21.781546 DQS Delay:
2882 16:55:21.781897 DQS0 = 0, DQS1 = 0
2883 16:55:21.784038 DQM Delay:
2884 16:55:21.784507 DQM0 = 122, DQM1 = 109
2885 16:55:21.787330 DQ Delay:
2886 16:55:21.791045 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2887 16:55:21.793980 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2888 16:55:21.797589 DQ8 =102, DQ9 =94, DQ10 =110, DQ11 =106
2889 16:55:21.800761 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2890 16:55:21.801323
2891 16:55:21.801780
2892 16:55:21.807407 [DQSOSCAuto] RK0, (LSB)MR18= 0xb07, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 405 ps
2893 16:55:21.811383 CH0 RK0: MR19=404, MR18=B07
2894 16:55:21.816869 CH0_RK0: MR19=0x404, MR18=0xB07, DQSOSC=405, MR23=63, INC=39, DEC=26
2895 16:55:21.817344
2896 16:55:21.820243 ----->DramcWriteLeveling(PI) begin...
2897 16:55:21.820819 ==
2898 16:55:21.824256 Dram Type= 6, Freq= 0, CH_0, rank 1
2899 16:55:21.827221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2900 16:55:21.830202 ==
2901 16:55:21.830827 Write leveling (Byte 0): 34 => 34
2902 16:55:21.833631 Write leveling (Byte 1): 30 => 30
2903 16:55:21.836875 DramcWriteLeveling(PI) end<-----
2904 16:55:21.837440
2905 16:55:21.837814 ==
2906 16:55:21.840328 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 16:55:21.847394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 16:55:21.847967 ==
2909 16:55:21.850096 [Gating] SW mode calibration
2910 16:55:21.856730 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2911 16:55:21.860693 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2912 16:55:21.866681 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2913 16:55:21.869990 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2914 16:55:21.873895 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2915 16:55:21.879774 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2916 16:55:21.883404 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 16:55:21.886793 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 16:55:21.893185 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 16:55:21.896570 0 15 28 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 1)
2920 16:55:21.899724 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2921 16:55:21.906259 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2922 16:55:21.909858 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2923 16:55:21.913916 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 16:55:21.916120 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 16:55:21.923040 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 16:55:21.926619 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2927 16:55:21.929837 1 0 28 | B1->B0 | 3838 4343 | 1 0 | (0 0) (0 0)
2928 16:55:21.936638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 16:55:21.940520 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2930 16:55:21.943182 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2931 16:55:21.950063 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 16:55:21.954233 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 16:55:21.956527 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 16:55:21.963213 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 16:55:21.966886 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2936 16:55:21.969846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 16:55:21.976437 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 16:55:21.979712 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:55:21.982738 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:55:21.989679 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:55:21.992746 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:55:21.996157 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 16:55:22.002747 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 16:55:22.006344 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 16:55:22.009712 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 16:55:22.016200 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 16:55:22.019536 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 16:55:22.023337 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 16:55:22.029548 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 16:55:22.032655 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2951 16:55:22.036047 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2952 16:55:22.042642 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2953 16:55:22.043214 Total UI for P1: 0, mck2ui 16
2954 16:55:22.045633 best dqsien dly found for B0: ( 1, 3, 26)
2955 16:55:22.049643 Total UI for P1: 0, mck2ui 16
2956 16:55:22.052718 best dqsien dly found for B1: ( 1, 3, 28)
2957 16:55:22.059193 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2958 16:55:22.062950 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2959 16:55:22.063520
2960 16:55:22.065838 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2961 16:55:22.069193 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2962 16:55:22.072585 [Gating] SW calibration Done
2963 16:55:22.073152 ==
2964 16:55:22.075772 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 16:55:22.079408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 16:55:22.079980 ==
2967 16:55:22.082123 RX Vref Scan: 0
2968 16:55:22.082638
2969 16:55:22.083009 RX Vref 0 -> 0, step: 1
2970 16:55:22.083353
2971 16:55:22.085360 RX Delay -40 -> 252, step: 8
2972 16:55:22.089225 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2973 16:55:22.095570 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2974 16:55:22.098896 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2975 16:55:22.102531 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2976 16:55:22.105546 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2977 16:55:22.108556 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2978 16:55:22.115402 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2979 16:55:22.118785 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2980 16:55:22.122033 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2981 16:55:22.125332 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2982 16:55:22.128842 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2983 16:55:22.135002 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2984 16:55:22.138893 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2985 16:55:22.142036 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2986 16:55:22.145279 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2987 16:55:22.148686 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2988 16:55:22.152209 ==
2989 16:55:22.152795 Dram Type= 6, Freq= 0, CH_0, rank 1
2990 16:55:22.158271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2991 16:55:22.158877 ==
2992 16:55:22.159369 DQS Delay:
2993 16:55:22.161618 DQS0 = 0, DQS1 = 0
2994 16:55:22.162201 DQM Delay:
2995 16:55:22.164722 DQM0 = 120, DQM1 = 108
2996 16:55:22.165204 DQ Delay:
2997 16:55:22.168357 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2998 16:55:22.171320 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2999 16:55:22.175223 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3000 16:55:22.178158 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3001 16:55:22.178791
3002 16:55:22.179278
3003 16:55:22.179724 ==
3004 16:55:22.181729 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 16:55:22.188228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 16:55:22.188819 ==
3007 16:55:22.189311
3008 16:55:22.189762
3009 16:55:22.190203 TX Vref Scan disable
3010 16:55:22.191542 == TX Byte 0 ==
3011 16:55:22.195220 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3012 16:55:22.201957 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3013 16:55:22.202599 == TX Byte 1 ==
3014 16:55:22.204970 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3015 16:55:22.211765 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3016 16:55:22.212355 ==
3017 16:55:22.214776 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 16:55:22.218435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 16:55:22.219024 ==
3020 16:55:22.230155 TX Vref=22, minBit 3, minWin=23, winSum=397
3021 16:55:22.233593 TX Vref=24, minBit 1, minWin=24, winSum=405
3022 16:55:22.236753 TX Vref=26, minBit 2, minWin=24, winSum=409
3023 16:55:22.239848 TX Vref=28, minBit 1, minWin=24, winSum=413
3024 16:55:22.243216 TX Vref=30, minBit 1, minWin=25, winSum=417
3025 16:55:22.246372 TX Vref=32, minBit 2, minWin=25, winSum=414
3026 16:55:22.252993 [TxChooseVref] Worse bit 1, Min win 25, Win sum 417, Final Vref 30
3027 16:55:22.253570
3028 16:55:22.256805 Final TX Range 1 Vref 30
3029 16:55:22.257414
3030 16:55:22.257912 ==
3031 16:55:22.259952 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 16:55:22.263283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 16:55:22.263877 ==
3034 16:55:22.264364
3035 16:55:22.266553
3036 16:55:22.267018 TX Vref Scan disable
3037 16:55:22.269749 == TX Byte 0 ==
3038 16:55:22.273316 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3039 16:55:22.276531 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3040 16:55:22.279727 == TX Byte 1 ==
3041 16:55:22.282936 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3042 16:55:22.286213 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3043 16:55:22.289705
3044 16:55:22.290274 [DATLAT]
3045 16:55:22.290705 Freq=1200, CH0 RK1
3046 16:55:22.291059
3047 16:55:22.293100 DATLAT Default: 0xd
3048 16:55:22.293712 0, 0xFFFF, sum = 0
3049 16:55:22.296218 1, 0xFFFF, sum = 0
3050 16:55:22.296698 2, 0xFFFF, sum = 0
3051 16:55:22.299523 3, 0xFFFF, sum = 0
3052 16:55:22.303334 4, 0xFFFF, sum = 0
3053 16:55:22.303912 5, 0xFFFF, sum = 0
3054 16:55:22.306684 6, 0xFFFF, sum = 0
3055 16:55:22.307158 7, 0xFFFF, sum = 0
3056 16:55:22.309622 8, 0xFFFF, sum = 0
3057 16:55:22.310197 9, 0xFFFF, sum = 0
3058 16:55:22.313087 10, 0xFFFF, sum = 0
3059 16:55:22.313668 11, 0xFFFF, sum = 0
3060 16:55:22.316172 12, 0x0, sum = 1
3061 16:55:22.316757 13, 0x0, sum = 2
3062 16:55:22.319520 14, 0x0, sum = 3
3063 16:55:22.320105 15, 0x0, sum = 4
3064 16:55:22.320487 best_step = 13
3065 16:55:22.322665
3066 16:55:22.323133 ==
3067 16:55:22.326573 Dram Type= 6, Freq= 0, CH_0, rank 1
3068 16:55:22.329714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3069 16:55:22.330289 ==
3070 16:55:22.330725 RX Vref Scan: 0
3071 16:55:22.331084
3072 16:55:22.332866 RX Vref 0 -> 0, step: 1
3073 16:55:22.333439
3074 16:55:22.336307 RX Delay -21 -> 252, step: 4
3075 16:55:22.339514 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3076 16:55:22.346118 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3077 16:55:22.349110 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3078 16:55:22.352644 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3079 16:55:22.356315 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3080 16:55:22.359306 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3081 16:55:22.366073 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3082 16:55:22.369647 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3083 16:55:22.372455 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3084 16:55:22.376315 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3085 16:55:22.378996 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3086 16:55:22.386186 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3087 16:55:22.389442 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3088 16:55:22.393011 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3089 16:55:22.395493 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3090 16:55:22.399611 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3091 16:55:22.402622 ==
3092 16:55:22.405632 Dram Type= 6, Freq= 0, CH_0, rank 1
3093 16:55:22.409041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3094 16:55:22.409626 ==
3095 16:55:22.410004 DQS Delay:
3096 16:55:22.412545 DQS0 = 0, DQS1 = 0
3097 16:55:22.413124 DQM Delay:
3098 16:55:22.415907 DQM0 = 119, DQM1 = 107
3099 16:55:22.416486 DQ Delay:
3100 16:55:22.418997 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =114
3101 16:55:22.422813 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =126
3102 16:55:22.425880 DQ8 =98, DQ9 =96, DQ10 =108, DQ11 =104
3103 16:55:22.429129 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3104 16:55:22.429707
3105 16:55:22.430083
3106 16:55:22.438713 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
3107 16:55:22.439318 CH0 RK1: MR19=403, MR18=AF2
3108 16:55:22.446030 CH0_RK1: MR19=0x403, MR18=0xAF2, DQSOSC=406, MR23=63, INC=39, DEC=26
3109 16:55:22.448777 [RxdqsGatingPostProcess] freq 1200
3110 16:55:22.455336 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3111 16:55:22.458751 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 16:55:22.461790 best DQS1 dly(2T, 0.5T) = (0, 12)
3113 16:55:22.465438 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 16:55:22.468782 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3115 16:55:22.472447 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 16:55:22.475224 best DQS1 dly(2T, 0.5T) = (0, 11)
3117 16:55:22.475700 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 16:55:22.478754 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3119 16:55:22.481780 Pre-setting of DQS Precalculation
3120 16:55:22.488408 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3121 16:55:22.488582 ==
3122 16:55:22.491718 Dram Type= 6, Freq= 0, CH_1, rank 0
3123 16:55:22.494788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3124 16:55:22.494956 ==
3125 16:55:22.501968 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3126 16:55:22.508288 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3127 16:55:22.515494 [CA 0] Center 37 (7~67) winsize 61
3128 16:55:22.519635 [CA 1] Center 37 (7~68) winsize 62
3129 16:55:22.522187 [CA 2] Center 34 (4~65) winsize 62
3130 16:55:22.525716 [CA 3] Center 33 (3~64) winsize 62
3131 16:55:22.528968 [CA 4] Center 33 (3~64) winsize 62
3132 16:55:22.532776 [CA 5] Center 33 (3~63) winsize 61
3133 16:55:22.533152
3134 16:55:22.535828 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3135 16:55:22.536205
3136 16:55:22.539496 [CATrainingPosCal] consider 1 rank data
3137 16:55:22.542074 u2DelayCellTimex100 = 270/100 ps
3138 16:55:22.545213 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3139 16:55:22.552148 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3140 16:55:22.555633 CA2 delay=34 (4~65),Diff = 1 PI (4 cell)
3141 16:55:22.558455 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3142 16:55:22.561848 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3143 16:55:22.565195 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3144 16:55:22.565764
3145 16:55:22.568698 CA PerBit enable=1, Macro0, CA PI delay=33
3146 16:55:22.569266
3147 16:55:22.572615 [CBTSetCACLKResult] CA Dly = 33
3148 16:55:22.573203 CS Dly: 4 (0~35)
3149 16:55:22.575131 ==
3150 16:55:22.578266 Dram Type= 6, Freq= 0, CH_1, rank 1
3151 16:55:22.581960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3152 16:55:22.582622 ==
3153 16:55:22.585214 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3154 16:55:22.591780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3155 16:55:22.601316 [CA 0] Center 38 (8~68) winsize 61
3156 16:55:22.605419 [CA 1] Center 37 (7~68) winsize 62
3157 16:55:22.608272 [CA 2] Center 35 (5~66) winsize 62
3158 16:55:22.611526 [CA 3] Center 34 (4~65) winsize 62
3159 16:55:22.614611 [CA 4] Center 34 (4~64) winsize 61
3160 16:55:22.618099 [CA 5] Center 33 (3~64) winsize 62
3161 16:55:22.618725
3162 16:55:22.621565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3163 16:55:22.622134
3164 16:55:22.624303 [CATrainingPosCal] consider 2 rank data
3165 16:55:22.627721 u2DelayCellTimex100 = 270/100 ps
3166 16:55:22.630984 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3167 16:55:22.637403 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3168 16:55:22.641046 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3169 16:55:22.644406 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3170 16:55:22.647602 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3171 16:55:22.650816 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3172 16:55:22.651378
3173 16:55:22.654306 CA PerBit enable=1, Macro0, CA PI delay=33
3174 16:55:22.654910
3175 16:55:22.657326 [CBTSetCACLKResult] CA Dly = 33
3176 16:55:22.660623 CS Dly: 5 (0~38)
3177 16:55:22.661188
3178 16:55:22.664387 ----->DramcWriteLeveling(PI) begin...
3179 16:55:22.664866 ==
3180 16:55:22.667454 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 16:55:22.670736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 16:55:22.671308 ==
3183 16:55:22.674278 Write leveling (Byte 0): 24 => 24
3184 16:55:22.677278 Write leveling (Byte 1): 27 => 27
3185 16:55:22.680671 DramcWriteLeveling(PI) end<-----
3186 16:55:22.681229
3187 16:55:22.681600 ==
3188 16:55:22.683600 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 16:55:22.687027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 16:55:22.687498 ==
3191 16:55:22.690944 [Gating] SW mode calibration
3192 16:55:22.697034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3193 16:55:22.704231 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3194 16:55:22.707267 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3195 16:55:22.710261 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3196 16:55:22.716688 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 16:55:22.720685 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3198 16:55:22.723617 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 16:55:22.730207 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3200 16:55:22.733318 0 15 24 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
3201 16:55:22.736665 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3202 16:55:22.743299 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 16:55:22.746768 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 16:55:22.749740 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3205 16:55:22.756524 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3206 16:55:22.760091 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 16:55:22.762996 1 0 20 | B1->B0 | 2525 2727 | 0 0 | (0 0) (0 0)
3208 16:55:22.770132 1 0 24 | B1->B0 | 3838 3f3f | 0 1 | (0 0) (1 1)
3209 16:55:22.773237 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 16:55:22.777138 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 16:55:22.783580 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 16:55:22.786145 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 16:55:22.789937 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 16:55:22.796248 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 16:55:22.799595 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3216 16:55:22.803543 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3217 16:55:22.809758 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3218 16:55:22.813074 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 16:55:22.816358 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 16:55:22.822877 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:55:22.826123 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:55:22.830096 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:55:22.836370 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 16:55:22.839311 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 16:55:22.842773 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 16:55:22.849267 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 16:55:22.852265 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 16:55:22.856077 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 16:55:22.862522 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 16:55:22.865946 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 16:55:22.869254 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3232 16:55:22.876212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3233 16:55:22.878820 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3234 16:55:22.882223 Total UI for P1: 0, mck2ui 16
3235 16:55:22.885530 best dqsien dly found for B0: ( 1, 3, 22)
3236 16:55:22.888995 Total UI for P1: 0, mck2ui 16
3237 16:55:22.892364 best dqsien dly found for B1: ( 1, 3, 24)
3238 16:55:22.895369 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3239 16:55:22.898549 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3240 16:55:22.899034
3241 16:55:22.901956 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3242 16:55:22.905460 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3243 16:55:22.908893 [Gating] SW calibration Done
3244 16:55:22.909461 ==
3245 16:55:22.911995 Dram Type= 6, Freq= 0, CH_1, rank 0
3246 16:55:22.915704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3247 16:55:22.916280 ==
3248 16:55:22.918427 RX Vref Scan: 0
3249 16:55:22.918892
3250 16:55:22.922092 RX Vref 0 -> 0, step: 1
3251 16:55:22.922712
3252 16:55:22.923092 RX Delay -40 -> 252, step: 8
3253 16:55:22.929085 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3254 16:55:22.932478 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3255 16:55:22.936523 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3256 16:55:22.939046 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3257 16:55:22.942275 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3258 16:55:22.948657 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3259 16:55:22.952114 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3260 16:55:22.955503 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3261 16:55:22.958488 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3262 16:55:22.961861 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3263 16:55:22.968682 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3264 16:55:22.971827 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3265 16:55:22.975110 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3266 16:55:22.978472 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3267 16:55:22.982030 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3268 16:55:22.988828 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3269 16:55:22.989416 ==
3270 16:55:22.991580 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 16:55:22.994740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 16:55:22.995239 ==
3273 16:55:22.995620 DQS Delay:
3274 16:55:22.998316 DQS0 = 0, DQS1 = 0
3275 16:55:22.998861 DQM Delay:
3276 16:55:23.001506 DQM0 = 119, DQM1 = 112
3277 16:55:23.001978 DQ Delay:
3278 16:55:23.005550 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3279 16:55:23.008678 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3280 16:55:23.011936 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3281 16:55:23.014941 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3282 16:55:23.015416
3283 16:55:23.015791
3284 16:55:23.018688 ==
3285 16:55:23.021847 Dram Type= 6, Freq= 0, CH_1, rank 0
3286 16:55:23.025164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3287 16:55:23.025747 ==
3288 16:55:23.026128
3289 16:55:23.026511
3290 16:55:23.028356 TX Vref Scan disable
3291 16:55:23.028929 == TX Byte 0 ==
3292 16:55:23.035047 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3293 16:55:23.038473 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3294 16:55:23.039061 == TX Byte 1 ==
3295 16:55:23.045070 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3296 16:55:23.048113 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3297 16:55:23.048593 ==
3298 16:55:23.051467 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 16:55:23.054774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 16:55:23.055356 ==
3301 16:55:23.067122 TX Vref=22, minBit 8, minWin=23, winSum=399
3302 16:55:23.070184 TX Vref=24, minBit 11, minWin=23, winSum=405
3303 16:55:23.073850 TX Vref=26, minBit 1, minWin=24, winSum=407
3304 16:55:23.077149 TX Vref=28, minBit 3, minWin=25, winSum=414
3305 16:55:23.080201 TX Vref=30, minBit 9, minWin=25, winSum=418
3306 16:55:23.086589 TX Vref=32, minBit 11, minWin=25, winSum=419
3307 16:55:23.090484 [TxChooseVref] Worse bit 11, Min win 25, Win sum 419, Final Vref 32
3308 16:55:23.091054
3309 16:55:23.093351 Final TX Range 1 Vref 32
3310 16:55:23.093824
3311 16:55:23.094199 ==
3312 16:55:23.096643 Dram Type= 6, Freq= 0, CH_1, rank 0
3313 16:55:23.099980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3314 16:55:23.103354 ==
3315 16:55:23.103906
3316 16:55:23.104281
3317 16:55:23.104626 TX Vref Scan disable
3318 16:55:23.106956 == TX Byte 0 ==
3319 16:55:23.110722 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3320 16:55:23.113431 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3321 16:55:23.116722 == TX Byte 1 ==
3322 16:55:23.120442 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3323 16:55:23.126980 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3324 16:55:23.127547
3325 16:55:23.127926 [DATLAT]
3326 16:55:23.128275 Freq=1200, CH1 RK0
3327 16:55:23.128616
3328 16:55:23.129961 DATLAT Default: 0xd
3329 16:55:23.130461 0, 0xFFFF, sum = 0
3330 16:55:23.133715 1, 0xFFFF, sum = 0
3331 16:55:23.137028 2, 0xFFFF, sum = 0
3332 16:55:23.137603 3, 0xFFFF, sum = 0
3333 16:55:23.140643 4, 0xFFFF, sum = 0
3334 16:55:23.141215 5, 0xFFFF, sum = 0
3335 16:55:23.143192 6, 0xFFFF, sum = 0
3336 16:55:23.143674 7, 0xFFFF, sum = 0
3337 16:55:23.146985 8, 0xFFFF, sum = 0
3338 16:55:23.147556 9, 0xFFFF, sum = 0
3339 16:55:23.149903 10, 0xFFFF, sum = 0
3340 16:55:23.150411 11, 0xFFFF, sum = 0
3341 16:55:23.153272 12, 0x0, sum = 1
3342 16:55:23.153845 13, 0x0, sum = 2
3343 16:55:23.156376 14, 0x0, sum = 3
3344 16:55:23.156856 15, 0x0, sum = 4
3345 16:55:23.159949 best_step = 13
3346 16:55:23.160420
3347 16:55:23.160793 ==
3348 16:55:23.163195 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 16:55:23.167013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 16:55:23.167598 ==
3351 16:55:23.167982 RX Vref Scan: 1
3352 16:55:23.168331
3353 16:55:23.169965 Set Vref Range= 32 -> 127
3354 16:55:23.170457
3355 16:55:23.173229 RX Vref 32 -> 127, step: 1
3356 16:55:23.173795
3357 16:55:23.176916 RX Delay -13 -> 252, step: 4
3358 16:55:23.177484
3359 16:55:23.179922 Set Vref, RX VrefLevel [Byte0]: 32
3360 16:55:23.183068 [Byte1]: 32
3361 16:55:23.183564
3362 16:55:23.185913 Set Vref, RX VrefLevel [Byte0]: 33
3363 16:55:23.189383 [Byte1]: 33
3364 16:55:23.193116
3365 16:55:23.193575 Set Vref, RX VrefLevel [Byte0]: 34
3366 16:55:23.196465 [Byte1]: 34
3367 16:55:23.201131
3368 16:55:23.201592 Set Vref, RX VrefLevel [Byte0]: 35
3369 16:55:23.205213 [Byte1]: 35
3370 16:55:23.208810
3371 16:55:23.209138 Set Vref, RX VrefLevel [Byte0]: 36
3372 16:55:23.211962 [Byte1]: 36
3373 16:55:23.216464
3374 16:55:23.216818 Set Vref, RX VrefLevel [Byte0]: 37
3375 16:55:23.220182 [Byte1]: 37
3376 16:55:23.224261
3377 16:55:23.224582 Set Vref, RX VrefLevel [Byte0]: 38
3378 16:55:23.227526 [Byte1]: 38
3379 16:55:23.232731
3380 16:55:23.233280 Set Vref, RX VrefLevel [Byte0]: 39
3381 16:55:23.236253 [Byte1]: 39
3382 16:55:23.240194
3383 16:55:23.240654 Set Vref, RX VrefLevel [Byte0]: 40
3384 16:55:23.243930 [Byte1]: 40
3385 16:55:23.248537
3386 16:55:23.249092 Set Vref, RX VrefLevel [Byte0]: 41
3387 16:55:23.251677 [Byte1]: 41
3388 16:55:23.256177
3389 16:55:23.256724 Set Vref, RX VrefLevel [Byte0]: 42
3390 16:55:23.259986 [Byte1]: 42
3391 16:55:23.264106
3392 16:55:23.264651 Set Vref, RX VrefLevel [Byte0]: 43
3393 16:55:23.268038 [Byte1]: 43
3394 16:55:23.271897
3395 16:55:23.272448 Set Vref, RX VrefLevel [Byte0]: 44
3396 16:55:23.276294 [Byte1]: 44
3397 16:55:23.280352
3398 16:55:23.280903 Set Vref, RX VrefLevel [Byte0]: 45
3399 16:55:23.283378 [Byte1]: 45
3400 16:55:23.287980
3401 16:55:23.288536 Set Vref, RX VrefLevel [Byte0]: 46
3402 16:55:23.292085 [Byte1]: 46
3403 16:55:23.295531
3404 16:55:23.296077 Set Vref, RX VrefLevel [Byte0]: 47
3405 16:55:23.298900 [Byte1]: 47
3406 16:55:23.304338
3407 16:55:23.304897 Set Vref, RX VrefLevel [Byte0]: 48
3408 16:55:23.306678 [Byte1]: 48
3409 16:55:23.311617
3410 16:55:23.312305 Set Vref, RX VrefLevel [Byte0]: 49
3411 16:55:23.314689 [Byte1]: 49
3412 16:55:23.319540
3413 16:55:23.320112 Set Vref, RX VrefLevel [Byte0]: 50
3414 16:55:23.322572 [Byte1]: 50
3415 16:55:23.327157
3416 16:55:23.327707 Set Vref, RX VrefLevel [Byte0]: 51
3417 16:55:23.330408 [Byte1]: 51
3418 16:55:23.335368
3419 16:55:23.335919 Set Vref, RX VrefLevel [Byte0]: 52
3420 16:55:23.338657 [Byte1]: 52
3421 16:55:23.343264
3422 16:55:23.343813 Set Vref, RX VrefLevel [Byte0]: 53
3423 16:55:23.346147 [Byte1]: 53
3424 16:55:23.350616
3425 16:55:23.351094 Set Vref, RX VrefLevel [Byte0]: 54
3426 16:55:23.354395 [Byte1]: 54
3427 16:55:23.359206
3428 16:55:23.359774 Set Vref, RX VrefLevel [Byte0]: 55
3429 16:55:23.362423 [Byte1]: 55
3430 16:55:23.366895
3431 16:55:23.367464 Set Vref, RX VrefLevel [Byte0]: 56
3432 16:55:23.370269 [Byte1]: 56
3433 16:55:23.374819
3434 16:55:23.375386 Set Vref, RX VrefLevel [Byte0]: 57
3435 16:55:23.378036 [Byte1]: 57
3436 16:55:23.382738
3437 16:55:23.383302 Set Vref, RX VrefLevel [Byte0]: 58
3438 16:55:23.386016 [Byte1]: 58
3439 16:55:23.390448
3440 16:55:23.391012 Set Vref, RX VrefLevel [Byte0]: 59
3441 16:55:23.394145 [Byte1]: 59
3442 16:55:23.398271
3443 16:55:23.398897 Set Vref, RX VrefLevel [Byte0]: 60
3444 16:55:23.401262 [Byte1]: 60
3445 16:55:23.405882
3446 16:55:23.406436 Set Vref, RX VrefLevel [Byte0]: 61
3447 16:55:23.409283 [Byte1]: 61
3448 16:55:23.414831
3449 16:55:23.415395 Set Vref, RX VrefLevel [Byte0]: 62
3450 16:55:23.417263 [Byte1]: 62
3451 16:55:23.421756
3452 16:55:23.422318 Set Vref, RX VrefLevel [Byte0]: 63
3453 16:55:23.425301 [Byte1]: 63
3454 16:55:23.429879
3455 16:55:23.430486 Set Vref, RX VrefLevel [Byte0]: 64
3456 16:55:23.433442 [Byte1]: 64
3457 16:55:23.437675
3458 16:55:23.440968 Set Vref, RX VrefLevel [Byte0]: 65
3459 16:55:23.444125 [Byte1]: 65
3460 16:55:23.444695
3461 16:55:23.447259 Set Vref, RX VrefLevel [Byte0]: 66
3462 16:55:23.450627 [Byte1]: 66
3463 16:55:23.451191
3464 16:55:23.453994 Set Vref, RX VrefLevel [Byte0]: 67
3465 16:55:23.457729 [Byte1]: 67
3466 16:55:23.461656
3467 16:55:23.462219 Final RX Vref Byte 0 = 52 to rank0
3468 16:55:23.464917 Final RX Vref Byte 1 = 50 to rank0
3469 16:55:23.467917 Final RX Vref Byte 0 = 52 to rank1
3470 16:55:23.472943 Final RX Vref Byte 1 = 50 to rank1==
3471 16:55:23.474606 Dram Type= 6, Freq= 0, CH_1, rank 0
3472 16:55:23.481647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3473 16:55:23.482237 ==
3474 16:55:23.482677 DQS Delay:
3475 16:55:23.483028 DQS0 = 0, DQS1 = 0
3476 16:55:23.484233 DQM Delay:
3477 16:55:23.484704 DQM0 = 119, DQM1 = 111
3478 16:55:23.488198 DQ Delay:
3479 16:55:23.491271 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =118
3480 16:55:23.494441 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =118
3481 16:55:23.498169 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3482 16:55:23.501536 DQ12 =122, DQ13 =116, DQ14 =118, DQ15 =118
3483 16:55:23.502013
3484 16:55:23.502421
3485 16:55:23.510981 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3486 16:55:23.511575 CH1 RK0: MR19=404, MR18=114
3487 16:55:23.517887 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3488 16:55:23.518508
3489 16:55:23.520636 ----->DramcWriteLeveling(PI) begin...
3490 16:55:23.521142 ==
3491 16:55:23.524392 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 16:55:23.527355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 16:55:23.531205 ==
3494 16:55:23.531675 Write leveling (Byte 0): 23 => 23
3495 16:55:23.534467 Write leveling (Byte 1): 28 => 28
3496 16:55:23.537209 DramcWriteLeveling(PI) end<-----
3497 16:55:23.537685
3498 16:55:23.538055 ==
3499 16:55:23.540907 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 16:55:23.547353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 16:55:23.547917 ==
3502 16:55:23.550930 [Gating] SW mode calibration
3503 16:55:23.557753 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3504 16:55:23.561020 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3505 16:55:23.567777 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 16:55:23.571223 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 16:55:23.574663 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 16:55:23.580476 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 16:55:23.584175 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 16:55:23.587230 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 16:55:23.594719 0 15 24 | B1->B0 | 2c2c 3434 | 1 1 | (1 0) (1 0)
3512 16:55:23.597340 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 1)
3513 16:55:23.600348 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 16:55:23.607256 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 16:55:23.610337 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 16:55:23.613713 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 16:55:23.620372 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 16:55:23.623696 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 16:55:23.626681 1 0 24 | B1->B0 | 4141 2c2c | 0 0 | (0 0) (1 1)
3520 16:55:23.633743 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3521 16:55:23.636751 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:55:23.640475 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 16:55:23.644318 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 16:55:23.650281 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 16:55:23.654047 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 16:55:23.656729 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 16:55:23.663892 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3528 16:55:23.666965 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 16:55:23.670137 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 16:55:23.676838 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:55:23.680555 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:55:23.683510 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:55:23.690137 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:55:23.693575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 16:55:23.696483 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 16:55:23.703537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 16:55:23.706710 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 16:55:23.709794 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 16:55:23.716385 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 16:55:23.719642 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 16:55:23.723013 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 16:55:23.729500 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 16:55:23.732896 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3544 16:55:23.737226 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 16:55:23.739273 Total UI for P1: 0, mck2ui 16
3546 16:55:23.743027 best dqsien dly found for B0: ( 1, 3, 24)
3547 16:55:23.745936 Total UI for P1: 0, mck2ui 16
3548 16:55:23.749290 best dqsien dly found for B1: ( 1, 3, 24)
3549 16:55:23.753028 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3550 16:55:23.755817 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3551 16:55:23.756305
3552 16:55:23.762724 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3553 16:55:23.765791 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3554 16:55:23.769255 [Gating] SW calibration Done
3555 16:55:23.769820 ==
3556 16:55:23.773143 Dram Type= 6, Freq= 0, CH_1, rank 1
3557 16:55:23.776168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3558 16:55:23.776748 ==
3559 16:55:23.777117 RX Vref Scan: 0
3560 16:55:23.777454
3561 16:55:23.779015 RX Vref 0 -> 0, step: 1
3562 16:55:23.779481
3563 16:55:23.782177 RX Delay -40 -> 252, step: 8
3564 16:55:23.785694 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3565 16:55:23.789394 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3566 16:55:23.795388 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3567 16:55:23.798907 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3568 16:55:23.802164 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3569 16:55:23.805989 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3570 16:55:23.808987 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3571 16:55:23.815762 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3572 16:55:23.818803 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3573 16:55:23.822142 iDelay=200, Bit 9, Center 103 (40 ~ 167) 128
3574 16:55:23.825430 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3575 16:55:23.829261 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3576 16:55:23.835280 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3577 16:55:23.838584 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3578 16:55:23.842085 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3579 16:55:23.845437 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3580 16:55:23.846048 ==
3581 16:55:23.848334 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 16:55:23.855146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 16:55:23.855719 ==
3584 16:55:23.856092 DQS Delay:
3585 16:55:23.858324 DQS0 = 0, DQS1 = 0
3586 16:55:23.858867 DQM Delay:
3587 16:55:23.861626 DQM0 = 120, DQM1 = 113
3588 16:55:23.862093 DQ Delay:
3589 16:55:23.865244 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =123
3590 16:55:23.868439 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3591 16:55:23.871878 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
3592 16:55:23.874792 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3593 16:55:23.875259
3594 16:55:23.875626
3595 16:55:23.875962 ==
3596 16:55:23.878474 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 16:55:23.884744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 16:55:23.885461 ==
3599 16:55:23.885855
3600 16:55:23.886202
3601 16:55:23.886605 TX Vref Scan disable
3602 16:55:23.888549 == TX Byte 0 ==
3603 16:55:23.891754 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3604 16:55:23.898131 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3605 16:55:23.898755 == TX Byte 1 ==
3606 16:55:23.901477 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3607 16:55:23.908165 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3608 16:55:23.908747 ==
3609 16:55:23.911207 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 16:55:23.915135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 16:55:23.915718 ==
3612 16:55:23.926575 TX Vref=22, minBit 1, minWin=25, winSum=410
3613 16:55:23.929515 TX Vref=24, minBit 1, minWin=25, winSum=414
3614 16:55:23.933052 TX Vref=26, minBit 1, minWin=25, winSum=418
3615 16:55:23.935851 TX Vref=28, minBit 1, minWin=26, winSum=423
3616 16:55:23.939401 TX Vref=30, minBit 10, minWin=25, winSum=427
3617 16:55:23.946241 TX Vref=32, minBit 10, minWin=25, winSum=424
3618 16:55:23.949561 [TxChooseVref] Worse bit 1, Min win 26, Win sum 423, Final Vref 28
3619 16:55:23.950135
3620 16:55:23.952406 Final TX Range 1 Vref 28
3621 16:55:23.952905
3622 16:55:23.953282 ==
3623 16:55:23.955983 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 16:55:23.959255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 16:55:23.962745 ==
3626 16:55:23.963220
3627 16:55:23.963593
3628 16:55:23.963940 TX Vref Scan disable
3629 16:55:23.965988 == TX Byte 0 ==
3630 16:55:23.969883 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3631 16:55:23.976306 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3632 16:55:23.976891 == TX Byte 1 ==
3633 16:55:23.979169 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3634 16:55:23.986278 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3635 16:55:23.986879
3636 16:55:23.987259 [DATLAT]
3637 16:55:23.987607 Freq=1200, CH1 RK1
3638 16:55:23.987947
3639 16:55:23.989205 DATLAT Default: 0xd
3640 16:55:23.992683 0, 0xFFFF, sum = 0
3641 16:55:23.993270 1, 0xFFFF, sum = 0
3642 16:55:23.996049 2, 0xFFFF, sum = 0
3643 16:55:23.996530 3, 0xFFFF, sum = 0
3644 16:55:23.999062 4, 0xFFFF, sum = 0
3645 16:55:23.999649 5, 0xFFFF, sum = 0
3646 16:55:24.002724 6, 0xFFFF, sum = 0
3647 16:55:24.003206 7, 0xFFFF, sum = 0
3648 16:55:24.005818 8, 0xFFFF, sum = 0
3649 16:55:24.006295 9, 0xFFFF, sum = 0
3650 16:55:24.009581 10, 0xFFFF, sum = 0
3651 16:55:24.010163 11, 0xFFFF, sum = 0
3652 16:55:24.012040 12, 0x0, sum = 1
3653 16:55:24.012519 13, 0x0, sum = 2
3654 16:55:24.015549 14, 0x0, sum = 3
3655 16:55:24.016124 15, 0x0, sum = 4
3656 16:55:24.019150 best_step = 13
3657 16:55:24.019623
3658 16:55:24.019998 ==
3659 16:55:24.021926 Dram Type= 6, Freq= 0, CH_1, rank 1
3660 16:55:24.026391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3661 16:55:24.026975 ==
3662 16:55:24.029399 RX Vref Scan: 0
3663 16:55:24.029869
3664 16:55:24.030243 RX Vref 0 -> 0, step: 1
3665 16:55:24.030649
3666 16:55:24.032016 RX Delay -13 -> 252, step: 4
3667 16:55:24.039275 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3668 16:55:24.042604 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3669 16:55:24.045496 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3670 16:55:24.048734 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3671 16:55:24.051954 iDelay=195, Bit 4, Center 122 (63 ~ 182) 120
3672 16:55:24.058578 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3673 16:55:24.061882 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3674 16:55:24.065217 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3675 16:55:24.069037 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3676 16:55:24.071984 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3677 16:55:24.078170 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3678 16:55:24.081516 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3679 16:55:24.084868 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3680 16:55:24.088459 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3681 16:55:24.092635 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3682 16:55:24.098495 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3683 16:55:24.099072 ==
3684 16:55:24.101782 Dram Type= 6, Freq= 0, CH_1, rank 1
3685 16:55:24.105089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3686 16:55:24.105668 ==
3687 16:55:24.106048 DQS Delay:
3688 16:55:24.108196 DQS0 = 0, DQS1 = 0
3689 16:55:24.108771 DQM Delay:
3690 16:55:24.111512 DQM0 = 119, DQM1 = 113
3691 16:55:24.112094 DQ Delay:
3692 16:55:24.115079 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3693 16:55:24.118574 DQ4 =122, DQ5 =130, DQ6 =126, DQ7 =116
3694 16:55:24.121580 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3695 16:55:24.124867 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =122
3696 16:55:24.128070
3697 16:55:24.128645
3698 16:55:24.135082 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 407 ps
3699 16:55:24.137874 CH1 RK1: MR19=403, MR18=6EA
3700 16:55:24.144354 CH1_RK1: MR19=0x403, MR18=0x6EA, DQSOSC=407, MR23=63, INC=39, DEC=26
3701 16:55:24.147660 [RxdqsGatingPostProcess] freq 1200
3702 16:55:24.151253 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3703 16:55:24.154300 best DQS0 dly(2T, 0.5T) = (0, 11)
3704 16:55:24.157956 best DQS1 dly(2T, 0.5T) = (0, 11)
3705 16:55:24.161221 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3706 16:55:24.164719 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3707 16:55:24.167626 best DQS0 dly(2T, 0.5T) = (0, 11)
3708 16:55:24.170939 best DQS1 dly(2T, 0.5T) = (0, 11)
3709 16:55:24.174660 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3710 16:55:24.177751 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3711 16:55:24.181236 Pre-setting of DQS Precalculation
3712 16:55:24.183961 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3713 16:55:24.190657 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3714 16:55:24.201143 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3715 16:55:24.201745
3716 16:55:24.202122
3717 16:55:24.203751 [Calibration Summary] 2400 Mbps
3718 16:55:24.204228 CH 0, Rank 0
3719 16:55:24.207146 SW Impedance : PASS
3720 16:55:24.207619 DUTY Scan : NO K
3721 16:55:24.210544 ZQ Calibration : PASS
3722 16:55:24.213903 Jitter Meter : NO K
3723 16:55:24.214513 CBT Training : PASS
3724 16:55:24.217146 Write leveling : PASS
3725 16:55:24.220598 RX DQS gating : PASS
3726 16:55:24.221173 RX DQ/DQS(RDDQC) : PASS
3727 16:55:24.224038 TX DQ/DQS : PASS
3728 16:55:24.224625 RX DATLAT : PASS
3729 16:55:24.228505 RX DQ/DQS(Engine): PASS
3730 16:55:24.230523 TX OE : NO K
3731 16:55:24.231098 All Pass.
3732 16:55:24.231477
3733 16:55:24.231824 CH 0, Rank 1
3734 16:55:24.234087 SW Impedance : PASS
3735 16:55:24.237281 DUTY Scan : NO K
3736 16:55:24.237859 ZQ Calibration : PASS
3737 16:55:24.240443 Jitter Meter : NO K
3738 16:55:24.244201 CBT Training : PASS
3739 16:55:24.244890 Write leveling : PASS
3740 16:55:24.246666 RX DQS gating : PASS
3741 16:55:24.250839 RX DQ/DQS(RDDQC) : PASS
3742 16:55:24.251420 TX DQ/DQS : PASS
3743 16:55:24.253518 RX DATLAT : PASS
3744 16:55:24.256970 RX DQ/DQS(Engine): PASS
3745 16:55:24.257548 TX OE : NO K
3746 16:55:24.260319 All Pass.
3747 16:55:24.260896
3748 16:55:24.261272 CH 1, Rank 0
3749 16:55:24.263715 SW Impedance : PASS
3750 16:55:24.264294 DUTY Scan : NO K
3751 16:55:24.266805 ZQ Calibration : PASS
3752 16:55:24.270276 Jitter Meter : NO K
3753 16:55:24.270991 CBT Training : PASS
3754 16:55:24.273590 Write leveling : PASS
3755 16:55:24.276737 RX DQS gating : PASS
3756 16:55:24.277206 RX DQ/DQS(RDDQC) : PASS
3757 16:55:24.279763 TX DQ/DQS : PASS
3758 16:55:24.283202 RX DATLAT : PASS
3759 16:55:24.283669 RX DQ/DQS(Engine): PASS
3760 16:55:24.286801 TX OE : NO K
3761 16:55:24.287277 All Pass.
3762 16:55:24.287648
3763 16:55:24.289849 CH 1, Rank 1
3764 16:55:24.290312 SW Impedance : PASS
3765 16:55:24.293347 DUTY Scan : NO K
3766 16:55:24.293810 ZQ Calibration : PASS
3767 16:55:24.297053 Jitter Meter : NO K
3768 16:55:24.299740 CBT Training : PASS
3769 16:55:24.300218 Write leveling : PASS
3770 16:55:24.303012 RX DQS gating : PASS
3771 16:55:24.306445 RX DQ/DQS(RDDQC) : PASS
3772 16:55:24.306918 TX DQ/DQS : PASS
3773 16:55:24.309977 RX DATLAT : PASS
3774 16:55:24.313018 RX DQ/DQS(Engine): PASS
3775 16:55:24.313491 TX OE : NO K
3776 16:55:24.316281 All Pass.
3777 16:55:24.316750
3778 16:55:24.317121 DramC Write-DBI off
3779 16:55:24.319858 PER_BANK_REFRESH: Hybrid Mode
3780 16:55:24.323160 TX_TRACKING: ON
3781 16:55:24.329436 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3782 16:55:24.333192 [FAST_K] Save calibration result to emmc
3783 16:55:24.336158 dramc_set_vcore_voltage set vcore to 650000
3784 16:55:24.339794 Read voltage for 600, 5
3785 16:55:24.340376 Vio18 = 0
3786 16:55:24.343319 Vcore = 650000
3787 16:55:24.343891 Vdram = 0
3788 16:55:24.344264 Vddq = 0
3789 16:55:24.346434 Vmddr = 0
3790 16:55:24.349661 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3791 16:55:24.356226 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3792 16:55:24.356808 MEM_TYPE=3, freq_sel=19
3793 16:55:24.359107 sv_algorithm_assistance_LP4_1600
3794 16:55:24.366067 ============ PULL DRAM RESETB DOWN ============
3795 16:55:24.369127 ========== PULL DRAM RESETB DOWN end =========
3796 16:55:24.373128 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3797 16:55:24.375739 ===================================
3798 16:55:24.379317 LPDDR4 DRAM CONFIGURATION
3799 16:55:24.382290 ===================================
3800 16:55:24.386086 EX_ROW_EN[0] = 0x0
3801 16:55:24.386757 EX_ROW_EN[1] = 0x0
3802 16:55:24.388884 LP4Y_EN = 0x0
3803 16:55:24.389424 WORK_FSP = 0x0
3804 16:55:24.392654 WL = 0x2
3805 16:55:24.393235 RL = 0x2
3806 16:55:24.395639 BL = 0x2
3807 16:55:24.396236 RPST = 0x0
3808 16:55:24.398879 RD_PRE = 0x0
3809 16:55:24.399458 WR_PRE = 0x1
3810 16:55:24.401956 WR_PST = 0x0
3811 16:55:24.402489 DBI_WR = 0x0
3812 16:55:24.405669 DBI_RD = 0x0
3813 16:55:24.406155 OTF = 0x1
3814 16:55:24.408614 ===================================
3815 16:55:24.412270 ===================================
3816 16:55:24.415663 ANA top config
3817 16:55:24.418934 ===================================
3818 16:55:24.421988 DLL_ASYNC_EN = 0
3819 16:55:24.422481 ALL_SLAVE_EN = 1
3820 16:55:24.425371 NEW_RANK_MODE = 1
3821 16:55:24.429078 DLL_IDLE_MODE = 1
3822 16:55:24.432740 LP45_APHY_COMB_EN = 1
3823 16:55:24.435141 TX_ODT_DIS = 1
3824 16:55:24.435616 NEW_8X_MODE = 1
3825 16:55:24.438305 ===================================
3826 16:55:24.442519 ===================================
3827 16:55:24.445476 data_rate = 1200
3828 16:55:24.448542 CKR = 1
3829 16:55:24.452218 DQ_P2S_RATIO = 8
3830 16:55:24.454907 ===================================
3831 16:55:24.458238 CA_P2S_RATIO = 8
3832 16:55:24.461562 DQ_CA_OPEN = 0
3833 16:55:24.462131 DQ_SEMI_OPEN = 0
3834 16:55:24.465388 CA_SEMI_OPEN = 0
3835 16:55:24.468329 CA_FULL_RATE = 0
3836 16:55:24.471645 DQ_CKDIV4_EN = 1
3837 16:55:24.474887 CA_CKDIV4_EN = 1
3838 16:55:24.478456 CA_PREDIV_EN = 0
3839 16:55:24.479030 PH8_DLY = 0
3840 16:55:24.481590 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3841 16:55:24.485243 DQ_AAMCK_DIV = 4
3842 16:55:24.487974 CA_AAMCK_DIV = 4
3843 16:55:24.491102 CA_ADMCK_DIV = 4
3844 16:55:24.494961 DQ_TRACK_CA_EN = 0
3845 16:55:24.495526 CA_PICK = 600
3846 16:55:24.498332 CA_MCKIO = 600
3847 16:55:24.501457 MCKIO_SEMI = 0
3848 16:55:24.504390 PLL_FREQ = 2288
3849 16:55:24.507698 DQ_UI_PI_RATIO = 32
3850 16:55:24.511059 CA_UI_PI_RATIO = 0
3851 16:55:24.514459 ===================================
3852 16:55:24.517919 ===================================
3853 16:55:24.521521 memory_type:LPDDR4
3854 16:55:24.522090 GP_NUM : 10
3855 16:55:24.524643 SRAM_EN : 1
3856 16:55:24.525223 MD32_EN : 0
3857 16:55:24.528017 ===================================
3858 16:55:24.531066 [ANA_INIT] >>>>>>>>>>>>>>
3859 16:55:24.534843 <<<<<< [CONFIGURE PHASE]: ANA_TX
3860 16:55:24.537957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3861 16:55:24.541808 ===================================
3862 16:55:24.544502 data_rate = 1200,PCW = 0X5800
3863 16:55:24.547709 ===================================
3864 16:55:24.551324 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3865 16:55:24.554221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3866 16:55:24.561252 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3867 16:55:24.567500 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3868 16:55:24.571070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3869 16:55:24.574511 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3870 16:55:24.575078 [ANA_INIT] flow start
3871 16:55:24.577584 [ANA_INIT] PLL >>>>>>>>
3872 16:55:24.581799 [ANA_INIT] PLL <<<<<<<<
3873 16:55:24.582416 [ANA_INIT] MIDPI >>>>>>>>
3874 16:55:24.583767 [ANA_INIT] MIDPI <<<<<<<<
3875 16:55:24.587039 [ANA_INIT] DLL >>>>>>>>
3876 16:55:24.587506 [ANA_INIT] flow end
3877 16:55:24.594154 ============ LP4 DIFF to SE enter ============
3878 16:55:24.597520 ============ LP4 DIFF to SE exit ============
3879 16:55:24.598105 [ANA_INIT] <<<<<<<<<<<<<
3880 16:55:24.600271 [Flow] Enable top DCM control >>>>>
3881 16:55:24.604062 [Flow] Enable top DCM control <<<<<
3882 16:55:24.607211 Enable DLL master slave shuffle
3883 16:55:24.613976 ==============================================================
3884 16:55:24.617159 Gating Mode config
3885 16:55:24.620381 ==============================================================
3886 16:55:24.623660 Config description:
3887 16:55:24.633329 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3888 16:55:24.640229 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3889 16:55:24.643316 SELPH_MODE 0: By rank 1: By Phase
3890 16:55:24.650131 ==============================================================
3891 16:55:24.654145 GAT_TRACK_EN = 1
3892 16:55:24.656933 RX_GATING_MODE = 2
3893 16:55:24.659770 RX_GATING_TRACK_MODE = 2
3894 16:55:24.662914 SELPH_MODE = 1
3895 16:55:24.666718 PICG_EARLY_EN = 1
3896 16:55:24.667291 VALID_LAT_VALUE = 1
3897 16:55:24.673326 ==============================================================
3898 16:55:24.676169 Enter into Gating configuration >>>>
3899 16:55:24.679751 Exit from Gating configuration <<<<
3900 16:55:24.683277 Enter into DVFS_PRE_config >>>>>
3901 16:55:24.693088 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3902 16:55:24.696329 Exit from DVFS_PRE_config <<<<<
3903 16:55:24.699145 Enter into PICG configuration >>>>
3904 16:55:24.702583 Exit from PICG configuration <<<<
3905 16:55:24.706099 [RX_INPUT] configuration >>>>>
3906 16:55:24.709484 [RX_INPUT] configuration <<<<<
3907 16:55:24.716156 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3908 16:55:24.719113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3909 16:55:24.725628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 16:55:24.732294 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 16:55:24.739150 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 16:55:24.745807 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 16:55:24.748789 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3914 16:55:24.752023 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3915 16:55:24.755368 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3916 16:55:24.761964 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3917 16:55:24.765204 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3918 16:55:24.768256 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 16:55:24.771915 ===================================
3920 16:55:24.775352 LPDDR4 DRAM CONFIGURATION
3921 16:55:24.778633 ===================================
3922 16:55:24.782030 EX_ROW_EN[0] = 0x0
3923 16:55:24.782647 EX_ROW_EN[1] = 0x0
3924 16:55:24.785489 LP4Y_EN = 0x0
3925 16:55:24.786061 WORK_FSP = 0x0
3926 16:55:24.788487 WL = 0x2
3927 16:55:24.789061 RL = 0x2
3928 16:55:24.791533 BL = 0x2
3929 16:55:24.792108 RPST = 0x0
3930 16:55:24.794750 RD_PRE = 0x0
3931 16:55:24.795224 WR_PRE = 0x1
3932 16:55:24.798193 WR_PST = 0x0
3933 16:55:24.798719 DBI_WR = 0x0
3934 16:55:24.801887 DBI_RD = 0x0
3935 16:55:24.802488 OTF = 0x1
3936 16:55:24.804839 ===================================
3937 16:55:24.811795 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3938 16:55:24.814710 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3939 16:55:24.818283 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3940 16:55:24.821672 ===================================
3941 16:55:24.824640 LPDDR4 DRAM CONFIGURATION
3942 16:55:24.828968 ===================================
3943 16:55:24.831016 EX_ROW_EN[0] = 0x10
3944 16:55:24.831486 EX_ROW_EN[1] = 0x0
3945 16:55:24.834324 LP4Y_EN = 0x0
3946 16:55:24.834822 WORK_FSP = 0x0
3947 16:55:24.837746 WL = 0x2
3948 16:55:24.838216 RL = 0x2
3949 16:55:24.841826 BL = 0x2
3950 16:55:24.842429 RPST = 0x0
3951 16:55:24.844960 RD_PRE = 0x0
3952 16:55:24.845522 WR_PRE = 0x1
3953 16:55:24.847534 WR_PST = 0x0
3954 16:55:24.848005 DBI_WR = 0x0
3955 16:55:24.851079 DBI_RD = 0x0
3956 16:55:24.851550 OTF = 0x1
3957 16:55:24.854240 ===================================
3958 16:55:24.861028 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3959 16:55:24.865941 nWR fixed to 30
3960 16:55:24.869250 [ModeRegInit_LP4] CH0 RK0
3961 16:55:24.869726 [ModeRegInit_LP4] CH0 RK1
3962 16:55:24.872411 [ModeRegInit_LP4] CH1 RK0
3963 16:55:24.876599 [ModeRegInit_LP4] CH1 RK1
3964 16:55:24.877165 match AC timing 17
3965 16:55:24.882597 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3966 16:55:24.886079 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3967 16:55:24.889610 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3968 16:55:24.895323 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3969 16:55:24.898702 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3970 16:55:24.899269 ==
3971 16:55:24.902477 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 16:55:24.905387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 16:55:24.905960 ==
3974 16:55:24.912081 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3975 16:55:24.919057 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3976 16:55:24.921755 [CA 0] Center 36 (5~67) winsize 63
3977 16:55:24.925264 [CA 1] Center 36 (6~67) winsize 62
3978 16:55:24.928502 [CA 2] Center 34 (4~65) winsize 62
3979 16:55:24.931752 [CA 3] Center 34 (4~65) winsize 62
3980 16:55:24.934748 [CA 4] Center 33 (3~64) winsize 62
3981 16:55:24.938043 [CA 5] Center 33 (3~64) winsize 62
3982 16:55:24.938674
3983 16:55:24.941557 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3984 16:55:24.942122
3985 16:55:24.944656 [CATrainingPosCal] consider 1 rank data
3986 16:55:24.948198 u2DelayCellTimex100 = 270/100 ps
3987 16:55:24.951415 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3988 16:55:24.954487 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3989 16:55:24.957719 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3990 16:55:24.964315 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3991 16:55:24.967745 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3992 16:55:24.971891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3993 16:55:24.972459
3994 16:55:24.974839 CA PerBit enable=1, Macro0, CA PI delay=33
3995 16:55:24.975408
3996 16:55:24.977665 [CBTSetCACLKResult] CA Dly = 33
3997 16:55:24.978250 CS Dly: 6 (0~37)
3998 16:55:24.978681 ==
3999 16:55:24.980955 Dram Type= 6, Freq= 0, CH_0, rank 1
4000 16:55:24.987532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4001 16:55:24.988107 ==
4002 16:55:24.990766 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4003 16:55:24.998125 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4004 16:55:25.001265 [CA 0] Center 36 (6~67) winsize 62
4005 16:55:25.004324 [CA 1] Center 36 (6~67) winsize 62
4006 16:55:25.008090 [CA 2] Center 34 (4~65) winsize 62
4007 16:55:25.010769 [CA 3] Center 34 (4~65) winsize 62
4008 16:55:25.014412 [CA 4] Center 34 (3~65) winsize 63
4009 16:55:25.017724 [CA 5] Center 33 (3~64) winsize 62
4010 16:55:25.018304
4011 16:55:25.020886 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4012 16:55:25.021455
4013 16:55:25.024214 [CATrainingPosCal] consider 2 rank data
4014 16:55:25.027497 u2DelayCellTimex100 = 270/100 ps
4015 16:55:25.030740 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4016 16:55:25.037647 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4017 16:55:25.040930 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4018 16:55:25.043806 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4019 16:55:25.046983 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4020 16:55:25.051459 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4021 16:55:25.052053
4022 16:55:25.054470 CA PerBit enable=1, Macro0, CA PI delay=33
4023 16:55:25.054945
4024 16:55:25.057623 [CBTSetCACLKResult] CA Dly = 33
4025 16:55:25.060452 CS Dly: 5 (0~36)
4026 16:55:25.061028
4027 16:55:25.063361 ----->DramcWriteLeveling(PI) begin...
4028 16:55:25.063836 ==
4029 16:55:25.066903 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 16:55:25.069941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 16:55:25.070473 ==
4032 16:55:25.073380 Write leveling (Byte 0): 32 => 32
4033 16:55:25.076750 Write leveling (Byte 1): 31 => 31
4034 16:55:25.080088 DramcWriteLeveling(PI) end<-----
4035 16:55:25.080681
4036 16:55:25.081059 ==
4037 16:55:25.082948 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 16:55:25.086747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 16:55:25.087396 ==
4040 16:55:25.090049 [Gating] SW mode calibration
4041 16:55:25.096656 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4042 16:55:25.103487 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4043 16:55:25.106484 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 16:55:25.109681 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4045 16:55:25.116771 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 16:55:25.119326 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4047 16:55:25.123051 0 9 16 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
4048 16:55:25.129881 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 16:55:25.133112 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 16:55:25.136006 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 16:55:25.143162 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 16:55:25.146340 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 16:55:25.150312 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 16:55:25.156040 0 10 12 | B1->B0 | 2a2a 3e3d | 0 1 | (0 0) (0 0)
4055 16:55:25.159088 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4056 16:55:25.165820 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 16:55:25.168921 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 16:55:25.172465 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:55:25.175272 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 16:55:25.182476 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 16:55:25.185559 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 16:55:25.188543 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 16:55:25.195287 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4064 16:55:25.198652 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 16:55:25.201815 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:55:25.208488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:55:25.212301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:55:25.218682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:55:25.222077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:55:25.225173 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 16:55:25.232146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 16:55:25.234618 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 16:55:25.238196 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 16:55:25.244975 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 16:55:25.247974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 16:55:25.251808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 16:55:25.258371 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 16:55:25.261308 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 16:55:25.264658 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4080 16:55:25.267760 Total UI for P1: 0, mck2ui 16
4081 16:55:25.270690 best dqsien dly found for B0: ( 0, 13, 14)
4082 16:55:25.274021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 16:55:25.277365 Total UI for P1: 0, mck2ui 16
4084 16:55:25.281042 best dqsien dly found for B1: ( 0, 13, 18)
4085 16:55:25.287606 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4086 16:55:25.290911 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4087 16:55:25.291491
4088 16:55:25.294452 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4089 16:55:25.297583 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4090 16:55:25.300640 [Gating] SW calibration Done
4091 16:55:25.301203 ==
4092 16:55:25.304034 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 16:55:25.307517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 16:55:25.308082 ==
4095 16:55:25.310681 RX Vref Scan: 0
4096 16:55:25.311149
4097 16:55:25.311516 RX Vref 0 -> 0, step: 1
4098 16:55:25.311859
4099 16:55:25.313935 RX Delay -230 -> 252, step: 16
4100 16:55:25.320471 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4101 16:55:25.324348 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4102 16:55:25.326992 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4103 16:55:25.330178 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4104 16:55:25.334103 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4105 16:55:25.340178 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4106 16:55:25.343782 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4107 16:55:25.347609 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4108 16:55:25.350126 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4109 16:55:25.356446 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4110 16:55:25.360280 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4111 16:55:25.363250 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4112 16:55:25.366610 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4113 16:55:25.373194 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4114 16:55:25.376282 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4115 16:55:25.379672 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4116 16:55:25.380299 ==
4117 16:55:25.383059 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 16:55:25.386296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 16:55:25.389288 ==
4120 16:55:25.389903 DQS Delay:
4121 16:55:25.390387 DQS0 = 0, DQS1 = 0
4122 16:55:25.392530 DQM Delay:
4123 16:55:25.393011 DQM0 = 52, DQM1 = 40
4124 16:55:25.396327 DQ Delay:
4125 16:55:25.399309 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =49
4126 16:55:25.399850 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =57
4127 16:55:25.402686 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4128 16:55:25.406401 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =49
4129 16:55:25.409515
4130 16:55:25.410117
4131 16:55:25.410537 ==
4132 16:55:25.412656 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 16:55:25.415937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 16:55:25.416521 ==
4135 16:55:25.416905
4136 16:55:25.417254
4137 16:55:25.419213 TX Vref Scan disable
4138 16:55:25.419690 == TX Byte 0 ==
4139 16:55:25.426295 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4140 16:55:25.429241 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4141 16:55:25.429820 == TX Byte 1 ==
4142 16:55:25.435795 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4143 16:55:25.439070 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4144 16:55:25.439713 ==
4145 16:55:25.442767 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 16:55:25.445726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 16:55:25.446310 ==
4148 16:55:25.446719
4149 16:55:25.447068
4150 16:55:25.449099 TX Vref Scan disable
4151 16:55:25.452729 == TX Byte 0 ==
4152 16:55:25.455779 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4153 16:55:25.462531 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4154 16:55:25.463116 == TX Byte 1 ==
4155 16:55:25.465667 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4156 16:55:25.472317 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4157 16:55:25.472896
4158 16:55:25.473274 [DATLAT]
4159 16:55:25.473623 Freq=600, CH0 RK0
4160 16:55:25.473958
4161 16:55:25.475416 DATLAT Default: 0x9
4162 16:55:25.478883 0, 0xFFFF, sum = 0
4163 16:55:25.479542 1, 0xFFFF, sum = 0
4164 16:55:25.482421 2, 0xFFFF, sum = 0
4165 16:55:25.483009 3, 0xFFFF, sum = 0
4166 16:55:25.485022 4, 0xFFFF, sum = 0
4167 16:55:25.485503 5, 0xFFFF, sum = 0
4168 16:55:25.488847 6, 0xFFFF, sum = 0
4169 16:55:25.489324 7, 0xFFFF, sum = 0
4170 16:55:25.491622 8, 0x0, sum = 1
4171 16:55:25.492140 9, 0x0, sum = 2
4172 16:55:25.495063 10, 0x0, sum = 3
4173 16:55:25.495543 11, 0x0, sum = 4
4174 16:55:25.495926 best_step = 9
4175 16:55:25.496418
4176 16:55:25.498193 ==
4177 16:55:25.498926 Dram Type= 6, Freq= 0, CH_0, rank 0
4178 16:55:25.504962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 16:55:25.505442 ==
4180 16:55:25.505818 RX Vref Scan: 1
4181 16:55:25.506239
4182 16:55:25.508452 RX Vref 0 -> 0, step: 1
4183 16:55:25.508925
4184 16:55:25.511771 RX Delay -179 -> 252, step: 8
4185 16:55:25.512304
4186 16:55:25.515044 Set Vref, RX VrefLevel [Byte0]: 57
4187 16:55:25.518615 [Byte1]: 51
4188 16:55:25.519192
4189 16:55:25.521974 Final RX Vref Byte 0 = 57 to rank0
4190 16:55:25.525286 Final RX Vref Byte 1 = 51 to rank0
4191 16:55:25.529268 Final RX Vref Byte 0 = 57 to rank1
4192 16:55:25.531264 Final RX Vref Byte 1 = 51 to rank1==
4193 16:55:25.535123 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 16:55:25.538575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 16:55:25.541740 ==
4196 16:55:25.542315 DQS Delay:
4197 16:55:25.542793 DQS0 = 0, DQS1 = 0
4198 16:55:25.545327 DQM Delay:
4199 16:55:25.545903 DQM0 = 50, DQM1 = 37
4200 16:55:25.547987 DQ Delay:
4201 16:55:25.548567 DQ0 =48, DQ1 =52, DQ2 =48, DQ3 =48
4202 16:55:25.551218 DQ4 =52, DQ5 =40, DQ6 =56, DQ7 =56
4203 16:55:25.554948 DQ8 =32, DQ9 =24, DQ10 =36, DQ11 =28
4204 16:55:25.558808 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =48
4205 16:55:25.559385
4206 16:55:25.561019
4207 16:55:25.568561 [DQSOSCAuto] RK0, (LSB)MR18= 0x5d57, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
4208 16:55:25.570996 CH0 RK0: MR19=808, MR18=5D57
4209 16:55:25.578168 CH0_RK0: MR19=0x808, MR18=0x5D57, DQSOSC=392, MR23=63, INC=170, DEC=113
4210 16:55:25.578779
4211 16:55:25.581333 ----->DramcWriteLeveling(PI) begin...
4212 16:55:25.581915 ==
4213 16:55:25.584457 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 16:55:25.587464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 16:55:25.587959 ==
4216 16:55:25.590733 Write leveling (Byte 0): 35 => 35
4217 16:55:25.594492 Write leveling (Byte 1): 32 => 32
4218 16:55:25.597640 DramcWriteLeveling(PI) end<-----
4219 16:55:25.598119
4220 16:55:25.598541 ==
4221 16:55:25.600963 Dram Type= 6, Freq= 0, CH_0, rank 1
4222 16:55:25.604042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4223 16:55:25.604560 ==
4224 16:55:25.608076 [Gating] SW mode calibration
4225 16:55:25.614228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4226 16:55:25.621172 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4227 16:55:25.624171 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4228 16:55:25.627427 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4229 16:55:25.634279 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4230 16:55:25.637869 0 9 12 | B1->B0 | 3131 3333 | 0 0 | (0 0) (0 1)
4231 16:55:25.641182 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 16:55:25.647262 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 16:55:25.650470 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 16:55:25.654196 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 16:55:25.660350 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 16:55:25.663683 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 16:55:25.668530 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 16:55:25.673906 0 10 12 | B1->B0 | 2f2f 2d2d | 1 1 | (0 0) (0 0)
4239 16:55:25.677742 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4240 16:55:25.680489 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 16:55:25.686877 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 16:55:25.689838 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 16:55:25.693330 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 16:55:25.700296 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 16:55:25.703316 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 16:55:25.706601 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 16:55:25.713109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4248 16:55:25.716239 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:55:25.720190 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:55:25.726214 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:55:25.729963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:55:25.733806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:55:25.739338 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:55:25.742678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:55:25.749851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 16:55:25.752555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 16:55:25.756641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 16:55:25.762965 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 16:55:25.766056 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 16:55:25.769215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 16:55:25.776043 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 16:55:25.778770 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 16:55:25.782662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 16:55:25.785657 Total UI for P1: 0, mck2ui 16
4265 16:55:25.788735 best dqsien dly found for B0: ( 0, 13, 14)
4266 16:55:25.792155 Total UI for P1: 0, mck2ui 16
4267 16:55:25.795632 best dqsien dly found for B1: ( 0, 13, 14)
4268 16:55:25.799216 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4269 16:55:25.802024 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4270 16:55:25.802724
4271 16:55:25.805310 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4272 16:55:25.812125 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4273 16:55:25.812627 [Gating] SW calibration Done
4274 16:55:25.814988 ==
4275 16:55:25.815459 Dram Type= 6, Freq= 0, CH_0, rank 1
4276 16:55:25.821803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4277 16:55:25.822549 ==
4278 16:55:25.822944 RX Vref Scan: 0
4279 16:55:25.823296
4280 16:55:25.825029 RX Vref 0 -> 0, step: 1
4281 16:55:25.825503
4282 16:55:25.828581 RX Delay -230 -> 252, step: 16
4283 16:55:25.832297 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4284 16:55:25.835038 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4285 16:55:25.841147 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4286 16:55:25.844792 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4287 16:55:25.848473 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4288 16:55:25.851474 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4289 16:55:25.858730 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4290 16:55:25.861897 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4291 16:55:25.864334 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4292 16:55:25.867968 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4293 16:55:25.874726 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4294 16:55:25.878948 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4295 16:55:25.882096 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4296 16:55:25.884493 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4297 16:55:25.887586 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4298 16:55:25.894400 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4299 16:55:25.894970 ==
4300 16:55:25.897664 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 16:55:25.900869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 16:55:25.901455 ==
4303 16:55:25.901837 DQS Delay:
4304 16:55:25.904178 DQS0 = 0, DQS1 = 0
4305 16:55:25.904651 DQM Delay:
4306 16:55:25.907926 DQM0 = 51, DQM1 = 44
4307 16:55:25.908507 DQ Delay:
4308 16:55:25.910611 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4309 16:55:25.913817 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4310 16:55:25.917702 DQ8 =33, DQ9 =25, DQ10 =49, DQ11 =49
4311 16:55:25.920569 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4312 16:55:25.921046
4313 16:55:25.921417
4314 16:55:25.921758 ==
4315 16:55:25.924026 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 16:55:25.930375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 16:55:25.930957 ==
4318 16:55:25.931339
4319 16:55:25.931689
4320 16:55:25.932025 TX Vref Scan disable
4321 16:55:25.934244 == TX Byte 0 ==
4322 16:55:25.937702 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4323 16:55:25.944117 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4324 16:55:25.944695 == TX Byte 1 ==
4325 16:55:25.946985 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4326 16:55:25.954281 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4327 16:55:25.954903 ==
4328 16:55:25.957650 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 16:55:25.960864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 16:55:25.961448 ==
4331 16:55:25.961831
4332 16:55:25.962299
4333 16:55:25.963759 TX Vref Scan disable
4334 16:55:25.966985 == TX Byte 0 ==
4335 16:55:25.970818 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4336 16:55:25.974087 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4337 16:55:25.977445 == TX Byte 1 ==
4338 16:55:25.980527 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4339 16:55:25.984011 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4340 16:55:25.984591
4341 16:55:25.984971 [DATLAT]
4342 16:55:25.986945 Freq=600, CH0 RK1
4343 16:55:25.987420
4344 16:55:25.990280 DATLAT Default: 0x9
4345 16:55:25.990786 0, 0xFFFF, sum = 0
4346 16:55:25.993700 1, 0xFFFF, sum = 0
4347 16:55:25.994284 2, 0xFFFF, sum = 0
4348 16:55:25.997777 3, 0xFFFF, sum = 0
4349 16:55:25.998396 4, 0xFFFF, sum = 0
4350 16:55:26.000218 5, 0xFFFF, sum = 0
4351 16:55:26.000798 6, 0xFFFF, sum = 0
4352 16:55:26.004074 7, 0xFFFF, sum = 0
4353 16:55:26.004556 8, 0x0, sum = 1
4354 16:55:26.006896 9, 0x0, sum = 2
4355 16:55:26.007533 10, 0x0, sum = 3
4356 16:55:26.010490 11, 0x0, sum = 4
4357 16:55:26.011067 best_step = 9
4358 16:55:26.011445
4359 16:55:26.011837 ==
4360 16:55:26.013076 Dram Type= 6, Freq= 0, CH_0, rank 1
4361 16:55:26.016464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4362 16:55:26.016943 ==
4363 16:55:26.019945 RX Vref Scan: 0
4364 16:55:26.020402
4365 16:55:26.022973 RX Vref 0 -> 0, step: 1
4366 16:55:26.023432
4367 16:55:26.023794 RX Delay -179 -> 252, step: 8
4368 16:55:26.031138 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4369 16:55:26.034485 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4370 16:55:26.037600 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4371 16:55:26.041240 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4372 16:55:26.044425 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4373 16:55:26.050805 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4374 16:55:26.054581 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4375 16:55:26.058543 iDelay=205, Bit 7, Center 52 (-91 ~ 196) 288
4376 16:55:26.061028 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4377 16:55:26.067481 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4378 16:55:26.070961 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4379 16:55:26.073864 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4380 16:55:26.077153 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4381 16:55:26.084324 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4382 16:55:26.087068 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4383 16:55:26.090141 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4384 16:55:26.090636 ==
4385 16:55:26.093777 Dram Type= 6, Freq= 0, CH_0, rank 1
4386 16:55:26.097420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4387 16:55:26.097992 ==
4388 16:55:26.100512 DQS Delay:
4389 16:55:26.101072 DQS0 = 0, DQS1 = 0
4390 16:55:26.103865 DQM Delay:
4391 16:55:26.104327 DQM0 = 47, DQM1 = 41
4392 16:55:26.104710 DQ Delay:
4393 16:55:26.106730 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4394 16:55:26.111038 DQ4 =48, DQ5 =40, DQ6 =56, DQ7 =52
4395 16:55:26.113503 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =36
4396 16:55:26.116936 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =52
4397 16:55:26.117497
4398 16:55:26.117859
4399 16:55:26.126755 [DQSOSCAuto] RK1, (LSB)MR18= 0x6532, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4400 16:55:26.130299 CH0 RK1: MR19=808, MR18=6532
4401 16:55:26.136534 CH0_RK1: MR19=0x808, MR18=0x6532, DQSOSC=390, MR23=63, INC=172, DEC=114
4402 16:55:26.139968 [RxdqsGatingPostProcess] freq 600
4403 16:55:26.143288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4404 16:55:26.146599 Pre-setting of DQS Precalculation
4405 16:55:26.153070 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4406 16:55:26.153626 ==
4407 16:55:26.156450 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 16:55:26.159811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 16:55:26.160384 ==
4410 16:55:26.166390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4411 16:55:26.169811 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4412 16:55:26.174090 [CA 0] Center 35 (5~66) winsize 62
4413 16:55:26.177713 [CA 1] Center 35 (5~66) winsize 62
4414 16:55:26.180482 [CA 2] Center 34 (4~65) winsize 62
4415 16:55:26.183473 [CA 3] Center 34 (3~65) winsize 63
4416 16:55:26.187283 [CA 4] Center 34 (3~65) winsize 63
4417 16:55:26.190295 [CA 5] Center 33 (3~64) winsize 62
4418 16:55:26.190810
4419 16:55:26.193926 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4420 16:55:26.194338
4421 16:55:26.196671 [CATrainingPosCal] consider 1 rank data
4422 16:55:26.200570 u2DelayCellTimex100 = 270/100 ps
4423 16:55:26.203681 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4424 16:55:26.210734 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4425 16:55:26.213090 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4426 16:55:26.217113 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4427 16:55:26.220334 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4428 16:55:26.223156 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4429 16:55:26.223617
4430 16:55:26.226805 CA PerBit enable=1, Macro0, CA PI delay=33
4431 16:55:26.227367
4432 16:55:26.230107 [CBTSetCACLKResult] CA Dly = 33
4433 16:55:26.232871 CS Dly: 5 (0~36)
4434 16:55:26.233331 ==
4435 16:55:26.237559 Dram Type= 6, Freq= 0, CH_1, rank 1
4436 16:55:26.239510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4437 16:55:26.239974 ==
4438 16:55:26.245944 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4439 16:55:26.252853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4440 16:55:26.256044 [CA 0] Center 35 (5~66) winsize 62
4441 16:55:26.258894 [CA 1] Center 35 (5~66) winsize 62
4442 16:55:26.262428 [CA 2] Center 34 (4~65) winsize 62
4443 16:55:26.266238 [CA 3] Center 34 (4~65) winsize 62
4444 16:55:26.269441 [CA 4] Center 34 (4~65) winsize 62
4445 16:55:26.272073 [CA 5] Center 34 (3~65) winsize 63
4446 16:55:26.272718
4447 16:55:26.275643 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4448 16:55:26.276317
4449 16:55:26.278943 [CATrainingPosCal] consider 2 rank data
4450 16:55:26.282038 u2DelayCellTimex100 = 270/100 ps
4451 16:55:26.285240 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4452 16:55:26.288723 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4453 16:55:26.291970 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4454 16:55:26.296220 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4455 16:55:26.298393 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 16:55:26.302092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4457 16:55:26.302708
4458 16:55:26.308218 CA PerBit enable=1, Macro0, CA PI delay=33
4459 16:55:26.308770
4460 16:55:26.311650 [CBTSetCACLKResult] CA Dly = 33
4461 16:55:26.312226 CS Dly: 5 (0~37)
4462 16:55:26.312602
4463 16:55:26.314781 ----->DramcWriteLeveling(PI) begin...
4464 16:55:26.315255 ==
4465 16:55:26.318024 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 16:55:26.321714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 16:55:26.324776 ==
4468 16:55:26.325344 Write leveling (Byte 0): 29 => 29
4469 16:55:26.328414 Write leveling (Byte 1): 30 => 30
4470 16:55:26.332174 DramcWriteLeveling(PI) end<-----
4471 16:55:26.332741
4472 16:55:26.333116 ==
4473 16:55:26.334489 Dram Type= 6, Freq= 0, CH_1, rank 0
4474 16:55:26.342321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4475 16:55:26.342932 ==
4476 16:55:26.344612 [Gating] SW mode calibration
4477 16:55:26.351487 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4478 16:55:26.354191 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4479 16:55:26.361381 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4480 16:55:26.364111 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4481 16:55:26.367271 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 1)
4482 16:55:26.374157 0 9 12 | B1->B0 | 2929 2b2b | 1 0 | (1 1) (0 0)
4483 16:55:26.377501 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 16:55:26.380511 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 16:55:26.387053 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4486 16:55:26.390617 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 16:55:26.393959 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 16:55:26.400714 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 16:55:26.404023 0 10 8 | B1->B0 | 2525 2828 | 0 0 | (0 0) (0 0)
4490 16:55:26.406695 0 10 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4491 16:55:26.413340 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 16:55:26.416765 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 16:55:26.419997 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 16:55:26.426610 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 16:55:26.429818 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 16:55:26.433498 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 16:55:26.440147 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 16:55:26.443222 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4499 16:55:26.447186 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 16:55:26.453304 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:55:26.456430 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:55:26.459799 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:55:26.467005 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:55:26.469430 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:55:26.472819 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:55:26.476387 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:55:26.483389 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 16:55:26.486241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 16:55:26.489838 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 16:55:26.496425 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 16:55:26.499981 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 16:55:26.502947 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 16:55:26.509336 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 16:55:26.513208 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 16:55:26.516097 Total UI for P1: 0, mck2ui 16
4516 16:55:26.519783 best dqsien dly found for B0: ( 0, 13, 10)
4517 16:55:26.523036 Total UI for P1: 0, mck2ui 16
4518 16:55:26.526097 best dqsien dly found for B1: ( 0, 13, 10)
4519 16:55:26.529256 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4520 16:55:26.532332 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4521 16:55:26.532495
4522 16:55:26.535820 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4523 16:55:26.542307 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4524 16:55:26.542484 [Gating] SW calibration Done
4525 16:55:26.542613 ==
4526 16:55:26.545530 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 16:55:26.552305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 16:55:26.552496 ==
4529 16:55:26.552645 RX Vref Scan: 0
4530 16:55:26.552782
4531 16:55:26.556022 RX Vref 0 -> 0, step: 1
4532 16:55:26.556450
4533 16:55:26.559609 RX Delay -230 -> 252, step: 16
4534 16:55:26.562989 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4535 16:55:26.565739 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4536 16:55:26.572412 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4537 16:55:26.575499 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4538 16:55:26.579211 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4539 16:55:26.582568 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4540 16:55:26.585767 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4541 16:55:26.592632 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4542 16:55:26.595962 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4543 16:55:26.598872 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4544 16:55:26.602591 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4545 16:55:26.609210 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4546 16:55:26.612676 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4547 16:55:26.615217 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4548 16:55:26.618926 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4549 16:55:26.626125 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4550 16:55:26.626737 ==
4551 16:55:26.628790 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 16:55:26.632399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 16:55:26.632975 ==
4554 16:55:26.633354 DQS Delay:
4555 16:55:26.635489 DQS0 = 0, DQS1 = 0
4556 16:55:26.635961 DQM Delay:
4557 16:55:26.639023 DQM0 = 46, DQM1 = 43
4558 16:55:26.639589 DQ Delay:
4559 16:55:26.642028 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4560 16:55:26.645343 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4561 16:55:26.649614 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4562 16:55:26.652475 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =41
4563 16:55:26.653048
4564 16:55:26.653424
4565 16:55:26.653768 ==
4566 16:55:26.655266 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 16:55:26.658528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 16:55:26.662055 ==
4569 16:55:26.662660
4570 16:55:26.663037
4571 16:55:26.663387 TX Vref Scan disable
4572 16:55:26.665273 == TX Byte 0 ==
4573 16:55:26.668739 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4574 16:55:26.671626 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4575 16:55:26.674958 == TX Byte 1 ==
4576 16:55:26.678481 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4577 16:55:26.681915 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4578 16:55:26.685260 ==
4579 16:55:26.688095 Dram Type= 6, Freq= 0, CH_1, rank 0
4580 16:55:26.691461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4581 16:55:26.691940 ==
4582 16:55:26.692333
4583 16:55:26.692690
4584 16:55:26.695292 TX Vref Scan disable
4585 16:55:26.695767 == TX Byte 0 ==
4586 16:55:26.701617 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4587 16:55:26.704976 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4588 16:55:26.705552 == TX Byte 1 ==
4589 16:55:26.711824 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4590 16:55:26.714801 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4591 16:55:26.715372
4592 16:55:26.715751 [DATLAT]
4593 16:55:26.717815 Freq=600, CH1 RK0
4594 16:55:26.718288
4595 16:55:26.718706 DATLAT Default: 0x9
4596 16:55:26.721176 0, 0xFFFF, sum = 0
4597 16:55:26.721657 1, 0xFFFF, sum = 0
4598 16:55:26.724701 2, 0xFFFF, sum = 0
4599 16:55:26.725275 3, 0xFFFF, sum = 0
4600 16:55:26.727994 4, 0xFFFF, sum = 0
4601 16:55:26.731053 5, 0xFFFF, sum = 0
4602 16:55:26.731533 6, 0xFFFF, sum = 0
4603 16:55:26.735210 7, 0xFFFF, sum = 0
4604 16:55:26.735786 8, 0x0, sum = 1
4605 16:55:26.736167 9, 0x0, sum = 2
4606 16:55:26.737643 10, 0x0, sum = 3
4607 16:55:26.738146 11, 0x0, sum = 4
4608 16:55:26.741774 best_step = 9
4609 16:55:26.742341
4610 16:55:26.742774 ==
4611 16:55:26.744231 Dram Type= 6, Freq= 0, CH_1, rank 0
4612 16:55:26.747710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 16:55:26.748296 ==
4614 16:55:26.751198 RX Vref Scan: 1
4615 16:55:26.751760
4616 16:55:26.752135 RX Vref 0 -> 0, step: 1
4617 16:55:26.752481
4618 16:55:26.754821 RX Delay -163 -> 252, step: 8
4619 16:55:26.755294
4620 16:55:26.757587 Set Vref, RX VrefLevel [Byte0]: 52
4621 16:55:26.760806 [Byte1]: 50
4622 16:55:26.765457
4623 16:55:26.766020 Final RX Vref Byte 0 = 52 to rank0
4624 16:55:26.768834 Final RX Vref Byte 1 = 50 to rank0
4625 16:55:26.771681 Final RX Vref Byte 0 = 52 to rank1
4626 16:55:26.774689 Final RX Vref Byte 1 = 50 to rank1==
4627 16:55:26.778311 Dram Type= 6, Freq= 0, CH_1, rank 0
4628 16:55:26.784656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4629 16:55:26.785223 ==
4630 16:55:26.785595 DQS Delay:
4631 16:55:26.788049 DQS0 = 0, DQS1 = 0
4632 16:55:26.788519 DQM Delay:
4633 16:55:26.788890 DQM0 = 47, DQM1 = 39
4634 16:55:26.791043 DQ Delay:
4635 16:55:26.794537 DQ0 =52, DQ1 =44, DQ2 =32, DQ3 =44
4636 16:55:26.797840 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =44
4637 16:55:26.801009 DQ8 =28, DQ9 =24, DQ10 =44, DQ11 =28
4638 16:55:26.805152 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =44
4639 16:55:26.805619
4640 16:55:26.805989
4641 16:55:26.811800 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4642 16:55:26.814472 CH1 RK0: MR19=808, MR18=4C72
4643 16:55:26.821065 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4644 16:55:26.821633
4645 16:55:26.824430 ----->DramcWriteLeveling(PI) begin...
4646 16:55:26.825004 ==
4647 16:55:26.827635 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 16:55:26.831587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 16:55:26.832157 ==
4650 16:55:26.834477 Write leveling (Byte 0): 30 => 30
4651 16:55:26.837927 Write leveling (Byte 1): 30 => 30
4652 16:55:26.840771 DramcWriteLeveling(PI) end<-----
4653 16:55:26.841334
4654 16:55:26.841708 ==
4655 16:55:26.844609 Dram Type= 6, Freq= 0, CH_1, rank 1
4656 16:55:26.847224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4657 16:55:26.851115 ==
4658 16:55:26.851680 [Gating] SW mode calibration
4659 16:55:26.861285 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4660 16:55:26.864458 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4661 16:55:26.867597 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4662 16:55:26.873784 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4663 16:55:26.876927 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4664 16:55:26.879986 0 9 12 | B1->B0 | 2525 3030 | 0 1 | (0 0) (1 0)
4665 16:55:26.886775 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 16:55:26.890323 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 16:55:26.893179 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 16:55:26.899832 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 16:55:26.903180 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 16:55:26.906598 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 16:55:26.913248 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4672 16:55:26.916288 0 10 12 | B1->B0 | 3e3e 3030 | 0 1 | (0 0) (0 0)
4673 16:55:26.919725 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 16:55:26.926715 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 16:55:26.929765 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 16:55:26.933492 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 16:55:26.939975 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 16:55:26.942909 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 16:55:26.945971 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4680 16:55:26.952721 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4681 16:55:26.957130 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 16:55:26.959205 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 16:55:26.965985 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:55:26.969534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:55:26.973438 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:55:26.979399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:55:26.983173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:55:26.985774 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:55:26.992526 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:55:26.995543 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:55:26.998848 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 16:55:27.005744 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 16:55:27.008875 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 16:55:27.012729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 16:55:27.018805 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 16:55:27.022603 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4697 16:55:27.026158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4698 16:55:27.029279 Total UI for P1: 0, mck2ui 16
4699 16:55:27.032812 best dqsien dly found for B1: ( 0, 13, 12)
4700 16:55:27.039719 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 16:55:27.040305 Total UI for P1: 0, mck2ui 16
4702 16:55:27.045965 best dqsien dly found for B0: ( 0, 13, 14)
4703 16:55:27.049291 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4704 16:55:27.051831 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4705 16:55:27.052307
4706 16:55:27.055276 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4707 16:55:27.059544 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4708 16:55:27.062051 [Gating] SW calibration Done
4709 16:55:27.062779 ==
4710 16:55:27.065320 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 16:55:27.068910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 16:55:27.069511 ==
4713 16:55:27.072286 RX Vref Scan: 0
4714 16:55:27.072862
4715 16:55:27.073238 RX Vref 0 -> 0, step: 1
4716 16:55:27.075215
4717 16:55:27.075805 RX Delay -230 -> 252, step: 16
4718 16:55:27.082164 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4719 16:55:27.085581 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4720 16:55:27.088537 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4721 16:55:27.092500 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4722 16:55:27.095076 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4723 16:55:27.101720 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4724 16:55:27.105508 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4725 16:55:27.108275 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4726 16:55:27.111573 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4727 16:55:27.118402 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4728 16:55:27.121491 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4729 16:55:27.124919 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4730 16:55:27.128090 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4731 16:55:27.135036 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4732 16:55:27.138471 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4733 16:55:27.141539 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4734 16:55:27.142114 ==
4735 16:55:27.145298 Dram Type= 6, Freq= 0, CH_1, rank 1
4736 16:55:27.148330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4737 16:55:27.148911 ==
4738 16:55:27.151809 DQS Delay:
4739 16:55:27.152399 DQS0 = 0, DQS1 = 0
4740 16:55:27.154515 DQM Delay:
4741 16:55:27.155094 DQM0 = 48, DQM1 = 44
4742 16:55:27.158271 DQ Delay:
4743 16:55:27.158883 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4744 16:55:27.160936 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =41
4745 16:55:27.164360 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4746 16:55:27.167321 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4747 16:55:27.167796
4748 16:55:27.170677
4749 16:55:27.171148 ==
4750 16:55:27.174601 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 16:55:27.177791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 16:55:27.178429 ==
4753 16:55:27.178826
4754 16:55:27.179176
4755 16:55:27.181425 TX Vref Scan disable
4756 16:55:27.181997 == TX Byte 0 ==
4757 16:55:27.187185 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4758 16:55:27.190964 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4759 16:55:27.191590 == TX Byte 1 ==
4760 16:55:27.198125 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4761 16:55:27.201039 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4762 16:55:27.201615 ==
4763 16:55:27.203878 Dram Type= 6, Freq= 0, CH_1, rank 1
4764 16:55:27.207312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4765 16:55:27.207898 ==
4766 16:55:27.208277
4767 16:55:27.208621
4768 16:55:27.210592 TX Vref Scan disable
4769 16:55:27.214095 == TX Byte 0 ==
4770 16:55:27.217146 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4771 16:55:27.224112 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4772 16:55:27.224686 == TX Byte 1 ==
4773 16:55:27.226957 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4774 16:55:27.233695 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4775 16:55:27.234290
4776 16:55:27.234727 [DATLAT]
4777 16:55:27.235077 Freq=600, CH1 RK1
4778 16:55:27.235417
4779 16:55:27.237282 DATLAT Default: 0x9
4780 16:55:27.237853 0, 0xFFFF, sum = 0
4781 16:55:27.242378 1, 0xFFFF, sum = 0
4782 16:55:27.242966 2, 0xFFFF, sum = 0
4783 16:55:27.243709 3, 0xFFFF, sum = 0
4784 16:55:27.244175 4, 0xFFFF, sum = 0
4785 16:55:27.247467 5, 0xFFFF, sum = 0
4786 16:55:27.250464 6, 0xFFFF, sum = 0
4787 16:55:27.251046 7, 0xFFFF, sum = 0
4788 16:55:27.253875 8, 0x0, sum = 1
4789 16:55:27.254516 9, 0x0, sum = 2
4790 16:55:27.254920 10, 0x0, sum = 3
4791 16:55:27.257016 11, 0x0, sum = 4
4792 16:55:27.257593 best_step = 9
4793 16:55:27.257973
4794 16:55:27.258317 ==
4795 16:55:27.260205 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 16:55:27.267258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 16:55:27.267838 ==
4798 16:55:27.268221 RX Vref Scan: 0
4799 16:55:27.268568
4800 16:55:27.270082 RX Vref 0 -> 0, step: 1
4801 16:55:27.270603
4802 16:55:27.273033 RX Delay -179 -> 252, step: 8
4803 16:55:27.276325 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4804 16:55:27.283096 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4805 16:55:27.286802 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4806 16:55:27.289871 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4807 16:55:27.293109 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4808 16:55:27.296564 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4809 16:55:27.303569 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4810 16:55:27.306524 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4811 16:55:27.310466 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4812 16:55:27.313312 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4813 16:55:27.319647 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4814 16:55:27.324245 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4815 16:55:27.326481 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4816 16:55:27.329854 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4817 16:55:27.332894 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4818 16:55:27.339867 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4819 16:55:27.340436 ==
4820 16:55:27.342883 Dram Type= 6, Freq= 0, CH_1, rank 1
4821 16:55:27.346206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4822 16:55:27.346827 ==
4823 16:55:27.347217 DQS Delay:
4824 16:55:27.349362 DQS0 = 0, DQS1 = 0
4825 16:55:27.349940 DQM Delay:
4826 16:55:27.352956 DQM0 = 46, DQM1 = 40
4827 16:55:27.353534 DQ Delay:
4828 16:55:27.357187 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4829 16:55:27.359357 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4830 16:55:27.362534 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =32
4831 16:55:27.365859 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =52
4832 16:55:27.366468
4833 16:55:27.366850
4834 16:55:27.375955 [DQSOSCAuto] RK1, (LSB)MR18= 0x531a, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
4835 16:55:27.376687 CH1 RK1: MR19=808, MR18=531A
4836 16:55:27.382288 CH1_RK1: MR19=0x808, MR18=0x531A, DQSOSC=394, MR23=63, INC=168, DEC=112
4837 16:55:27.385908 [RxdqsGatingPostProcess] freq 600
4838 16:55:27.392025 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4839 16:55:27.395375 Pre-setting of DQS Precalculation
4840 16:55:27.399036 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4841 16:55:27.409525 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4842 16:55:27.415652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4843 16:55:27.416224
4844 16:55:27.416600
4845 16:55:27.418569 [Calibration Summary] 1200 Mbps
4846 16:55:27.419138 CH 0, Rank 0
4847 16:55:27.421830 SW Impedance : PASS
4848 16:55:27.422421 DUTY Scan : NO K
4849 16:55:27.425775 ZQ Calibration : PASS
4850 16:55:27.429060 Jitter Meter : NO K
4851 16:55:27.429625 CBT Training : PASS
4852 16:55:27.432033 Write leveling : PASS
4853 16:55:27.434875 RX DQS gating : PASS
4854 16:55:27.435350 RX DQ/DQS(RDDQC) : PASS
4855 16:55:27.438259 TX DQ/DQS : PASS
4856 16:55:27.441419 RX DATLAT : PASS
4857 16:55:27.441891 RX DQ/DQS(Engine): PASS
4858 16:55:27.445024 TX OE : NO K
4859 16:55:27.445627 All Pass.
4860 16:55:27.446012
4861 16:55:27.448509 CH 0, Rank 1
4862 16:55:27.449073 SW Impedance : PASS
4863 16:55:27.451728 DUTY Scan : NO K
4864 16:55:27.452221 ZQ Calibration : PASS
4865 16:55:27.455300 Jitter Meter : NO K
4866 16:55:27.458468 CBT Training : PASS
4867 16:55:27.459035 Write leveling : PASS
4868 16:55:27.461380 RX DQS gating : PASS
4869 16:55:27.465032 RX DQ/DQS(RDDQC) : PASS
4870 16:55:27.465597 TX DQ/DQS : PASS
4871 16:55:27.468209 RX DATLAT : PASS
4872 16:55:27.471082 RX DQ/DQS(Engine): PASS
4873 16:55:27.471557 TX OE : NO K
4874 16:55:27.474967 All Pass.
4875 16:55:27.475529
4876 16:55:27.475904 CH 1, Rank 0
4877 16:55:27.477609 SW Impedance : PASS
4878 16:55:27.478079 DUTY Scan : NO K
4879 16:55:27.480957 ZQ Calibration : PASS
4880 16:55:27.484872 Jitter Meter : NO K
4881 16:55:27.485443 CBT Training : PASS
4882 16:55:27.487862 Write leveling : PASS
4883 16:55:27.491870 RX DQS gating : PASS
4884 16:55:27.492342 RX DQ/DQS(RDDQC) : PASS
4885 16:55:27.494318 TX DQ/DQS : PASS
4886 16:55:27.497836 RX DATLAT : PASS
4887 16:55:27.498448 RX DQ/DQS(Engine): PASS
4888 16:55:27.501323 TX OE : NO K
4889 16:55:27.501888 All Pass.
4890 16:55:27.502258
4891 16:55:27.504391 CH 1, Rank 1
4892 16:55:27.504953 SW Impedance : PASS
4893 16:55:27.507661 DUTY Scan : NO K
4894 16:55:27.511085 ZQ Calibration : PASS
4895 16:55:27.511653 Jitter Meter : NO K
4896 16:55:27.514456 CBT Training : PASS
4897 16:55:27.517346 Write leveling : PASS
4898 16:55:27.517907 RX DQS gating : PASS
4899 16:55:27.520731 RX DQ/DQS(RDDQC) : PASS
4900 16:55:27.521198 TX DQ/DQS : PASS
4901 16:55:27.524559 RX DATLAT : PASS
4902 16:55:27.527500 RX DQ/DQS(Engine): PASS
4903 16:55:27.528085 TX OE : NO K
4904 16:55:27.530562 All Pass.
4905 16:55:27.531032
4906 16:55:27.531403 DramC Write-DBI off
4907 16:55:27.533836 PER_BANK_REFRESH: Hybrid Mode
4908 16:55:27.537488 TX_TRACKING: ON
4909 16:55:27.544041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4910 16:55:27.546916 [FAST_K] Save calibration result to emmc
4911 16:55:27.553936 dramc_set_vcore_voltage set vcore to 662500
4912 16:55:27.554549 Read voltage for 933, 3
4913 16:55:27.554944 Vio18 = 0
4914 16:55:27.557297 Vcore = 662500
4915 16:55:27.557862 Vdram = 0
4916 16:55:27.558239 Vddq = 0
4917 16:55:27.560435 Vmddr = 0
4918 16:55:27.564000 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4919 16:55:27.570570 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4920 16:55:27.573578 MEM_TYPE=3, freq_sel=17
4921 16:55:27.574146 sv_algorithm_assistance_LP4_1600
4922 16:55:27.580374 ============ PULL DRAM RESETB DOWN ============
4923 16:55:27.583343 ========== PULL DRAM RESETB DOWN end =========
4924 16:55:27.586815 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4925 16:55:27.590248 ===================================
4926 16:55:27.593545 LPDDR4 DRAM CONFIGURATION
4927 16:55:27.596730 ===================================
4928 16:55:27.600256 EX_ROW_EN[0] = 0x0
4929 16:55:27.600821 EX_ROW_EN[1] = 0x0
4930 16:55:27.603578 LP4Y_EN = 0x0
4931 16:55:27.604154 WORK_FSP = 0x0
4932 16:55:27.606743 WL = 0x3
4933 16:55:27.607311 RL = 0x3
4934 16:55:27.610433 BL = 0x2
4935 16:55:27.611000 RPST = 0x0
4936 16:55:27.613372 RD_PRE = 0x0
4937 16:55:27.613942 WR_PRE = 0x1
4938 16:55:27.616726 WR_PST = 0x0
4939 16:55:27.617296 DBI_WR = 0x0
4940 16:55:27.620164 DBI_RD = 0x0
4941 16:55:27.623036 OTF = 0x1
4942 16:55:27.626801 ===================================
4943 16:55:27.629849 ===================================
4944 16:55:27.630482 ANA top config
4945 16:55:27.633363 ===================================
4946 16:55:27.636822 DLL_ASYNC_EN = 0
4947 16:55:27.637385 ALL_SLAVE_EN = 1
4948 16:55:27.640248 NEW_RANK_MODE = 1
4949 16:55:27.643000 DLL_IDLE_MODE = 1
4950 16:55:27.646483 LP45_APHY_COMB_EN = 1
4951 16:55:27.649863 TX_ODT_DIS = 1
4952 16:55:27.650467 NEW_8X_MODE = 1
4953 16:55:27.653102 ===================================
4954 16:55:27.656592 ===================================
4955 16:55:27.659588 data_rate = 1866
4956 16:55:27.663025 CKR = 1
4957 16:55:27.666489 DQ_P2S_RATIO = 8
4958 16:55:27.669952 ===================================
4959 16:55:27.673418 CA_P2S_RATIO = 8
4960 16:55:27.676359 DQ_CA_OPEN = 0
4961 16:55:27.676929 DQ_SEMI_OPEN = 0
4962 16:55:27.679012 CA_SEMI_OPEN = 0
4963 16:55:27.682807 CA_FULL_RATE = 0
4964 16:55:27.686087 DQ_CKDIV4_EN = 1
4965 16:55:27.689468 CA_CKDIV4_EN = 1
4966 16:55:27.692463 CA_PREDIV_EN = 0
4967 16:55:27.692945 PH8_DLY = 0
4968 16:55:27.695533 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4969 16:55:27.699025 DQ_AAMCK_DIV = 4
4970 16:55:27.702558 CA_AAMCK_DIV = 4
4971 16:55:27.706031 CA_ADMCK_DIV = 4
4972 16:55:27.709522 DQ_TRACK_CA_EN = 0
4973 16:55:27.712682 CA_PICK = 933
4974 16:55:27.713251 CA_MCKIO = 933
4975 16:55:27.716283 MCKIO_SEMI = 0
4976 16:55:27.719026 PLL_FREQ = 3732
4977 16:55:27.723224 DQ_UI_PI_RATIO = 32
4978 16:55:27.725582 CA_UI_PI_RATIO = 0
4979 16:55:27.728918 ===================================
4980 16:55:27.732587 ===================================
4981 16:55:27.735262 memory_type:LPDDR4
4982 16:55:27.735781 GP_NUM : 10
4983 16:55:27.738909 SRAM_EN : 1
4984 16:55:27.739472 MD32_EN : 0
4985 16:55:27.741876 ===================================
4986 16:55:27.745246 [ANA_INIT] >>>>>>>>>>>>>>
4987 16:55:27.748249 <<<<<< [CONFIGURE PHASE]: ANA_TX
4988 16:55:27.751787 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4989 16:55:27.754968 ===================================
4990 16:55:27.758328 data_rate = 1866,PCW = 0X8f00
4991 16:55:27.761566 ===================================
4992 16:55:27.765193 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4993 16:55:27.771814 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4994 16:55:27.774762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4995 16:55:27.781844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4996 16:55:27.784526 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4997 16:55:27.788175 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4998 16:55:27.788749 [ANA_INIT] flow start
4999 16:55:27.790918 [ANA_INIT] PLL >>>>>>>>
5000 16:55:27.794507 [ANA_INIT] PLL <<<<<<<<
5001 16:55:27.798258 [ANA_INIT] MIDPI >>>>>>>>
5002 16:55:27.798876 [ANA_INIT] MIDPI <<<<<<<<
5003 16:55:27.801235 [ANA_INIT] DLL >>>>>>>>
5004 16:55:27.804701 [ANA_INIT] flow end
5005 16:55:27.807615 ============ LP4 DIFF to SE enter ============
5006 16:55:27.811318 ============ LP4 DIFF to SE exit ============
5007 16:55:27.815004 [ANA_INIT] <<<<<<<<<<<<<
5008 16:55:27.817768 [Flow] Enable top DCM control >>>>>
5009 16:55:27.821702 [Flow] Enable top DCM control <<<<<
5010 16:55:27.824520 Enable DLL master slave shuffle
5011 16:55:27.827832 ==============================================================
5012 16:55:27.831309 Gating Mode config
5013 16:55:27.837848 ==============================================================
5014 16:55:27.838462 Config description:
5015 16:55:27.847570 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5016 16:55:27.854812 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5017 16:55:27.857371 SELPH_MODE 0: By rank 1: By Phase
5018 16:55:27.864175 ==============================================================
5019 16:55:27.867325 GAT_TRACK_EN = 1
5020 16:55:27.870660 RX_GATING_MODE = 2
5021 16:55:27.873897 RX_GATING_TRACK_MODE = 2
5022 16:55:27.877604 SELPH_MODE = 1
5023 16:55:27.880310 PICG_EARLY_EN = 1
5024 16:55:27.883543 VALID_LAT_VALUE = 1
5025 16:55:27.887075 ==============================================================
5026 16:55:27.890340 Enter into Gating configuration >>>>
5027 16:55:27.893428 Exit from Gating configuration <<<<
5028 16:55:27.896947 Enter into DVFS_PRE_config >>>>>
5029 16:55:27.910226 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5030 16:55:27.910853 Exit from DVFS_PRE_config <<<<<
5031 16:55:27.913746 Enter into PICG configuration >>>>
5032 16:55:27.917092 Exit from PICG configuration <<<<
5033 16:55:27.920599 [RX_INPUT] configuration >>>>>
5034 16:55:27.923207 [RX_INPUT] configuration <<<<<
5035 16:55:27.930042 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5036 16:55:27.933545 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5037 16:55:27.940531 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5038 16:55:27.946861 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5039 16:55:27.953294 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 16:55:27.959728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 16:55:27.962935 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5042 16:55:27.966796 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5043 16:55:27.969781 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5044 16:55:27.975988 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5045 16:55:27.979486 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5046 16:55:27.982794 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5047 16:55:27.986123 ===================================
5048 16:55:27.989706 LPDDR4 DRAM CONFIGURATION
5049 16:55:27.992754 ===================================
5050 16:55:27.995949 EX_ROW_EN[0] = 0x0
5051 16:55:27.996415 EX_ROW_EN[1] = 0x0
5052 16:55:27.999411 LP4Y_EN = 0x0
5053 16:55:27.999917 WORK_FSP = 0x0
5054 16:55:28.002849 WL = 0x3
5055 16:55:28.003314 RL = 0x3
5056 16:55:28.006403 BL = 0x2
5057 16:55:28.006978 RPST = 0x0
5058 16:55:28.009327 RD_PRE = 0x0
5059 16:55:28.009790 WR_PRE = 0x1
5060 16:55:28.012579 WR_PST = 0x0
5061 16:55:28.013045 DBI_WR = 0x0
5062 16:55:28.015955 DBI_RD = 0x0
5063 16:55:28.016532 OTF = 0x1
5064 16:55:28.019584 ===================================
5065 16:55:28.026414 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5066 16:55:28.029250 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5067 16:55:28.033067 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5068 16:55:28.035886 ===================================
5069 16:55:28.038904 LPDDR4 DRAM CONFIGURATION
5070 16:55:28.042610 ===================================
5071 16:55:28.045756 EX_ROW_EN[0] = 0x10
5072 16:55:28.046323 EX_ROW_EN[1] = 0x0
5073 16:55:28.049100 LP4Y_EN = 0x0
5074 16:55:28.049660 WORK_FSP = 0x0
5075 16:55:28.052581 WL = 0x3
5076 16:55:28.053155 RL = 0x3
5077 16:55:28.055692 BL = 0x2
5078 16:55:28.056257 RPST = 0x0
5079 16:55:28.058998 RD_PRE = 0x0
5080 16:55:28.059514 WR_PRE = 0x1
5081 16:55:28.062817 WR_PST = 0x0
5082 16:55:28.063419 DBI_WR = 0x0
5083 16:55:28.066138 DBI_RD = 0x0
5084 16:55:28.066775 OTF = 0x1
5085 16:55:28.069535 ===================================
5086 16:55:28.076302 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5087 16:55:28.080770 nWR fixed to 30
5088 16:55:28.083601 [ModeRegInit_LP4] CH0 RK0
5089 16:55:28.084071 [ModeRegInit_LP4] CH0 RK1
5090 16:55:28.086955 [ModeRegInit_LP4] CH1 RK0
5091 16:55:28.090339 [ModeRegInit_LP4] CH1 RK1
5092 16:55:28.090977 match AC timing 9
5093 16:55:28.096429 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5094 16:55:28.100857 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5095 16:55:28.103156 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5096 16:55:28.109969 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5097 16:55:28.113053 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5098 16:55:28.113520 ==
5099 16:55:28.116677 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 16:55:28.119591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 16:55:28.120161 ==
5102 16:55:28.126256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5103 16:55:28.133228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5104 16:55:28.136402 [CA 0] Center 37 (7~68) winsize 62
5105 16:55:28.139564 [CA 1] Center 37 (7~68) winsize 62
5106 16:55:28.142798 [CA 2] Center 35 (4~66) winsize 63
5107 16:55:28.146000 [CA 3] Center 34 (4~65) winsize 62
5108 16:55:28.149696 [CA 4] Center 34 (4~64) winsize 61
5109 16:55:28.152975 [CA 5] Center 33 (3~64) winsize 62
5110 16:55:28.153545
5111 16:55:28.156854 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5112 16:55:28.157423
5113 16:55:28.159249 [CATrainingPosCal] consider 1 rank data
5114 16:55:28.163046 u2DelayCellTimex100 = 270/100 ps
5115 16:55:28.166272 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5116 16:55:28.169523 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5117 16:55:28.172421 CA2 delay=35 (4~66),Diff = 2 PI (12 cell)
5118 16:55:28.175795 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5119 16:55:28.182612 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5120 16:55:28.186084 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5121 16:55:28.186716
5122 16:55:28.189379 CA PerBit enable=1, Macro0, CA PI delay=33
5123 16:55:28.189946
5124 16:55:28.192351 [CBTSetCACLKResult] CA Dly = 33
5125 16:55:28.192828 CS Dly: 6 (0~37)
5126 16:55:28.193270 ==
5127 16:55:28.195422 Dram Type= 6, Freq= 0, CH_0, rank 1
5128 16:55:28.202583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 16:55:28.203155 ==
5130 16:55:28.206032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5131 16:55:28.212309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5132 16:55:28.215776 [CA 0] Center 38 (7~69) winsize 63
5133 16:55:28.219013 [CA 1] Center 38 (8~68) winsize 61
5134 16:55:28.222038 [CA 2] Center 36 (6~66) winsize 61
5135 16:55:28.225425 [CA 3] Center 35 (5~66) winsize 62
5136 16:55:28.228978 [CA 4] Center 34 (4~65) winsize 62
5137 16:55:28.232356 [CA 5] Center 34 (4~64) winsize 61
5138 16:55:28.232934
5139 16:55:28.235774 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5140 16:55:28.236351
5141 16:55:28.238525 [CATrainingPosCal] consider 2 rank data
5142 16:55:28.242072 u2DelayCellTimex100 = 270/100 ps
5143 16:55:28.245278 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5144 16:55:28.251963 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5145 16:55:28.255853 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5146 16:55:28.258399 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5147 16:55:28.261818 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5148 16:55:28.264890 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5149 16:55:28.265467
5150 16:55:28.268516 CA PerBit enable=1, Macro0, CA PI delay=34
5151 16:55:28.269102
5152 16:55:28.271611 [CBTSetCACLKResult] CA Dly = 34
5153 16:55:28.274917 CS Dly: 6 (0~38)
5154 16:55:28.275505
5155 16:55:28.278243 ----->DramcWriteLeveling(PI) begin...
5156 16:55:28.278866 ==
5157 16:55:28.281588 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 16:55:28.285361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 16:55:28.285948 ==
5160 16:55:28.288425 Write leveling (Byte 0): 32 => 32
5161 16:55:28.291430 Write leveling (Byte 1): 28 => 28
5162 16:55:28.294462 DramcWriteLeveling(PI) end<-----
5163 16:55:28.294936
5164 16:55:28.295309 ==
5165 16:55:28.298284 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 16:55:28.301104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 16:55:28.301580 ==
5168 16:55:28.304779 [Gating] SW mode calibration
5169 16:55:28.311530 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5170 16:55:28.317924 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5171 16:55:28.321133 0 14 0 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
5172 16:55:28.324355 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5173 16:55:28.330940 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5174 16:55:28.334203 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 16:55:28.337649 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 16:55:28.344327 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 16:55:28.347568 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5178 16:55:28.350526 0 14 28 | B1->B0 | 3131 2424 | 0 0 | (0 1) (1 0)
5179 16:55:28.357554 0 15 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5180 16:55:28.360649 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 16:55:28.363668 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5182 16:55:28.370303 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 16:55:28.374054 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 16:55:28.376719 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 16:55:28.383563 0 15 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
5186 16:55:28.387285 0 15 28 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
5187 16:55:28.390629 1 0 0 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
5188 16:55:28.396695 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 16:55:28.400215 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5190 16:55:28.403598 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 16:55:28.410908 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 16:55:28.413403 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 16:55:28.416549 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 16:55:28.423246 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5195 16:55:28.426487 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5196 16:55:28.429747 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 16:55:28.436885 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:55:28.440164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:55:28.443124 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:55:28.450430 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:55:28.453739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:55:28.457073 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:55:28.463357 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:55:28.466560 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 16:55:28.469857 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 16:55:28.476198 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 16:55:28.479553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 16:55:28.482814 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 16:55:28.489681 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5210 16:55:28.492995 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5211 16:55:28.495950 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 16:55:28.499318 Total UI for P1: 0, mck2ui 16
5213 16:55:28.502810 best dqsien dly found for B0: ( 1, 2, 26)
5214 16:55:28.506135 Total UI for P1: 0, mck2ui 16
5215 16:55:28.509261 best dqsien dly found for B1: ( 1, 2, 30)
5216 16:55:28.512570 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5217 16:55:28.515957 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5218 16:55:28.516523
5219 16:55:28.522151 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5220 16:55:28.525632 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5221 16:55:28.529057 [Gating] SW calibration Done
5222 16:55:28.529528 ==
5223 16:55:28.532474 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 16:55:28.535730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 16:55:28.536200 ==
5226 16:55:28.536567 RX Vref Scan: 0
5227 16:55:28.536908
5228 16:55:28.538752 RX Vref 0 -> 0, step: 1
5229 16:55:28.539215
5230 16:55:28.542398 RX Delay -80 -> 252, step: 8
5231 16:55:28.545556 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5232 16:55:28.549412 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5233 16:55:28.555570 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5234 16:55:28.559045 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5235 16:55:28.562366 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5236 16:55:28.565735 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5237 16:55:28.568920 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5238 16:55:28.572413 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5239 16:55:28.579028 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5240 16:55:28.581641 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5241 16:55:28.585512 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5242 16:55:28.588843 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5243 16:55:28.591984 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5244 16:55:28.594852 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5245 16:55:28.602176 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5246 16:55:28.605056 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5247 16:55:28.605523 ==
5248 16:55:28.608053 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 16:55:28.612506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 16:55:28.612977 ==
5251 16:55:28.614930 DQS Delay:
5252 16:55:28.615394 DQS0 = 0, DQS1 = 0
5253 16:55:28.615767 DQM Delay:
5254 16:55:28.618512 DQM0 = 105, DQM1 = 90
5255 16:55:28.619080 DQ Delay:
5256 16:55:28.622213 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5257 16:55:28.625457 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5258 16:55:28.628052 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5259 16:55:28.631581 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =99
5260 16:55:28.632157
5261 16:55:28.632531
5262 16:55:28.634672 ==
5263 16:55:28.637931 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 16:55:28.641524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 16:55:28.642104 ==
5266 16:55:28.642537
5267 16:55:28.642889
5268 16:55:28.644715 TX Vref Scan disable
5269 16:55:28.645178 == TX Byte 0 ==
5270 16:55:28.651030 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5271 16:55:28.654516 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5272 16:55:28.655093 == TX Byte 1 ==
5273 16:55:28.661425 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5274 16:55:28.664850 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5275 16:55:28.665327 ==
5276 16:55:28.667541 Dram Type= 6, Freq= 0, CH_0, rank 0
5277 16:55:28.671430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 16:55:28.672008 ==
5279 16:55:28.672385
5280 16:55:28.672731
5281 16:55:28.674115 TX Vref Scan disable
5282 16:55:28.678054 == TX Byte 0 ==
5283 16:55:28.680802 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5284 16:55:28.683861 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5285 16:55:28.687643 == TX Byte 1 ==
5286 16:55:28.690793 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5287 16:55:28.694434 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5288 16:55:28.695022
5289 16:55:28.697480 [DATLAT]
5290 16:55:28.697940 Freq=933, CH0 RK0
5291 16:55:28.698312
5292 16:55:28.701409 DATLAT Default: 0xd
5293 16:55:28.701974 0, 0xFFFF, sum = 0
5294 16:55:28.704248 1, 0xFFFF, sum = 0
5295 16:55:28.704821 2, 0xFFFF, sum = 0
5296 16:55:28.707638 3, 0xFFFF, sum = 0
5297 16:55:28.708215 4, 0xFFFF, sum = 0
5298 16:55:28.710566 5, 0xFFFF, sum = 0
5299 16:55:28.711141 6, 0xFFFF, sum = 0
5300 16:55:28.714376 7, 0xFFFF, sum = 0
5301 16:55:28.714855 8, 0xFFFF, sum = 0
5302 16:55:28.717820 9, 0xFFFF, sum = 0
5303 16:55:28.718431 10, 0x0, sum = 1
5304 16:55:28.720568 11, 0x0, sum = 2
5305 16:55:28.721142 12, 0x0, sum = 3
5306 16:55:28.724074 13, 0x0, sum = 4
5307 16:55:28.724648 best_step = 11
5308 16:55:28.725021
5309 16:55:28.725360 ==
5310 16:55:28.726835 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 16:55:28.734071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 16:55:28.734696 ==
5313 16:55:28.735083 RX Vref Scan: 1
5314 16:55:28.735433
5315 16:55:28.736715 RX Vref 0 -> 0, step: 1
5316 16:55:28.737187
5317 16:55:28.740652 RX Delay -53 -> 252, step: 4
5318 16:55:28.741236
5319 16:55:28.743406 Set Vref, RX VrefLevel [Byte0]: 57
5320 16:55:28.747062 [Byte1]: 51
5321 16:55:28.747647
5322 16:55:28.750211 Final RX Vref Byte 0 = 57 to rank0
5323 16:55:28.753517 Final RX Vref Byte 1 = 51 to rank0
5324 16:55:28.756964 Final RX Vref Byte 0 = 57 to rank1
5325 16:55:28.760007 Final RX Vref Byte 1 = 51 to rank1==
5326 16:55:28.763220 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 16:55:28.766737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 16:55:28.767322 ==
5329 16:55:28.769868 DQS Delay:
5330 16:55:28.770476 DQS0 = 0, DQS1 = 0
5331 16:55:28.773192 DQM Delay:
5332 16:55:28.773769 DQM0 = 107, DQM1 = 92
5333 16:55:28.774151 DQ Delay:
5334 16:55:28.779869 DQ0 =106, DQ1 =106, DQ2 =104, DQ3 =106
5335 16:55:28.783303 DQ4 =108, DQ5 =98, DQ6 =118, DQ7 =116
5336 16:55:28.787339 DQ8 =88, DQ9 =76, DQ10 =92, DQ11 =92
5337 16:55:28.790121 DQ12 =96, DQ13 =92, DQ14 =102, DQ15 =100
5338 16:55:28.790752
5339 16:55:28.791135
5340 16:55:28.796227 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
5341 16:55:28.799599 CH0 RK0: MR19=505, MR18=2521
5342 16:55:28.806386 CH0_RK0: MR19=0x505, MR18=0x2521, DQSOSC=410, MR23=63, INC=64, DEC=42
5343 16:55:28.806972
5344 16:55:28.809525 ----->DramcWriteLeveling(PI) begin...
5345 16:55:28.810005 ==
5346 16:55:28.813132 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 16:55:28.816264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 16:55:28.816845 ==
5349 16:55:28.819559 Write leveling (Byte 0): 33 => 33
5350 16:55:28.823034 Write leveling (Byte 1): 30 => 30
5351 16:55:28.826477 DramcWriteLeveling(PI) end<-----
5352 16:55:28.827053
5353 16:55:28.827428 ==
5354 16:55:28.829497 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 16:55:28.833897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 16:55:28.836317 ==
5357 16:55:28.836897 [Gating] SW mode calibration
5358 16:55:28.845627 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5359 16:55:28.848959 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5360 16:55:28.852930 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 16:55:28.858810 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 16:55:28.861981 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5363 16:55:28.866340 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 16:55:28.872689 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 16:55:28.875832 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 16:55:28.878904 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
5367 16:55:28.885141 0 14 28 | B1->B0 | 2525 2424 | 1 0 | (1 0) (1 0)
5368 16:55:28.888551 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 16:55:28.892030 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 16:55:28.898139 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5371 16:55:28.901360 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 16:55:28.904834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 16:55:28.912361 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 16:55:28.914830 0 15 24 | B1->B0 | 2828 2c2c | 0 0 | (0 0) (0 0)
5375 16:55:28.918271 0 15 28 | B1->B0 | 3939 3e3e | 0 0 | (0 0) (0 0)
5376 16:55:28.925013 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 16:55:28.928280 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:55:28.931371 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 16:55:28.938745 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 16:55:28.941616 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 16:55:28.944353 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 16:55:28.951535 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5383 16:55:28.954983 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5384 16:55:28.958292 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 16:55:28.964340 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:55:28.968259 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:55:28.971507 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:55:28.977803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:55:28.981169 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:55:28.984716 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:55:28.991199 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:55:28.994520 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:55:28.997365 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:55:29.004173 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:55:29.007795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 16:55:29.010593 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 16:55:29.017605 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 16:55:29.020874 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5399 16:55:29.024661 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5400 16:55:29.030465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 16:55:29.030927 Total UI for P1: 0, mck2ui 16
5402 16:55:29.037142 best dqsien dly found for B0: ( 1, 2, 26)
5403 16:55:29.037699 Total UI for P1: 0, mck2ui 16
5404 16:55:29.044038 best dqsien dly found for B1: ( 1, 2, 30)
5405 16:55:29.047124 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5406 16:55:29.050084 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5407 16:55:29.050596
5408 16:55:29.054212 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5409 16:55:29.057075 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5410 16:55:29.060228 [Gating] SW calibration Done
5411 16:55:29.060782 ==
5412 16:55:29.063846 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 16:55:29.066677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 16:55:29.067194 ==
5415 16:55:29.070164 RX Vref Scan: 0
5416 16:55:29.070672
5417 16:55:29.071095 RX Vref 0 -> 0, step: 1
5418 16:55:29.071440
5419 16:55:29.073613 RX Delay -80 -> 252, step: 8
5420 16:55:29.077042 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5421 16:55:29.084103 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5422 16:55:29.086625 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5423 16:55:29.090705 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5424 16:55:29.093460 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5425 16:55:29.096409 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5426 16:55:29.103157 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5427 16:55:29.106766 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5428 16:55:29.110177 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5429 16:55:29.113523 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5430 16:55:29.116972 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5431 16:55:29.120243 iDelay=208, Bit 11, Center 91 (8 ~ 175) 168
5432 16:55:29.127375 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5433 16:55:29.129382 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5434 16:55:29.133098 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5435 16:55:29.136882 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5436 16:55:29.137445 ==
5437 16:55:29.140067 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 16:55:29.142837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 16:55:29.146414 ==
5440 16:55:29.146980 DQS Delay:
5441 16:55:29.147353 DQS0 = 0, DQS1 = 0
5442 16:55:29.149436 DQM Delay:
5443 16:55:29.150003 DQM0 = 105, DQM1 = 92
5444 16:55:29.152719 DQ Delay:
5445 16:55:29.156452 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5446 16:55:29.159683 DQ4 =107, DQ5 =99, DQ6 =115, DQ7 =111
5447 16:55:29.162561 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =91
5448 16:55:29.166217 DQ12 =99, DQ13 =95, DQ14 =99, DQ15 =99
5449 16:55:29.166739
5450 16:55:29.167113
5451 16:55:29.167460 ==
5452 16:55:29.170098 Dram Type= 6, Freq= 0, CH_0, rank 1
5453 16:55:29.172903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5454 16:55:29.173484 ==
5455 16:55:29.173863
5456 16:55:29.174207
5457 16:55:29.175590 TX Vref Scan disable
5458 16:55:29.176060 == TX Byte 0 ==
5459 16:55:29.182428 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5460 16:55:29.185975 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5461 16:55:29.189187 == TX Byte 1 ==
5462 16:55:29.192678 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5463 16:55:29.195732 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5464 16:55:29.196211 ==
5465 16:55:29.198921 Dram Type= 6, Freq= 0, CH_0, rank 1
5466 16:55:29.202425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5467 16:55:29.202906 ==
5468 16:55:29.205355
5469 16:55:29.205915
5470 16:55:29.206296 TX Vref Scan disable
5471 16:55:29.209261 == TX Byte 0 ==
5472 16:55:29.212551 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5473 16:55:29.219088 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5474 16:55:29.219664 == TX Byte 1 ==
5475 16:55:29.222539 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5476 16:55:29.229424 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5477 16:55:29.230006
5478 16:55:29.230442 [DATLAT]
5479 16:55:29.230799 Freq=933, CH0 RK1
5480 16:55:29.231137
5481 16:55:29.232412 DATLAT Default: 0xb
5482 16:55:29.235771 0, 0xFFFF, sum = 0
5483 16:55:29.236349 1, 0xFFFF, sum = 0
5484 16:55:29.238339 2, 0xFFFF, sum = 0
5485 16:55:29.238868 3, 0xFFFF, sum = 0
5486 16:55:29.241911 4, 0xFFFF, sum = 0
5487 16:55:29.242535 5, 0xFFFF, sum = 0
5488 16:55:29.245224 6, 0xFFFF, sum = 0
5489 16:55:29.245802 7, 0xFFFF, sum = 0
5490 16:55:29.248287 8, 0xFFFF, sum = 0
5491 16:55:29.248769 9, 0xFFFF, sum = 0
5492 16:55:29.252025 10, 0x0, sum = 1
5493 16:55:29.252608 11, 0x0, sum = 2
5494 16:55:29.255289 12, 0x0, sum = 3
5495 16:55:29.255864 13, 0x0, sum = 4
5496 16:55:29.258440 best_step = 11
5497 16:55:29.258999
5498 16:55:29.259376 ==
5499 16:55:29.262084 Dram Type= 6, Freq= 0, CH_0, rank 1
5500 16:55:29.265302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5501 16:55:29.265890 ==
5502 16:55:29.266338 RX Vref Scan: 0
5503 16:55:29.266757
5504 16:55:29.268211 RX Vref 0 -> 0, step: 1
5505 16:55:29.268718
5506 16:55:29.272249 RX Delay -53 -> 252, step: 4
5507 16:55:29.278457 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5508 16:55:29.281855 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5509 16:55:29.285056 iDelay=199, Bit 2, Center 102 (19 ~ 186) 168
5510 16:55:29.289439 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5511 16:55:29.291691 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5512 16:55:29.297911 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5513 16:55:29.301498 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5514 16:55:29.304587 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5515 16:55:29.307833 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5516 16:55:29.311158 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5517 16:55:29.318338 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5518 16:55:29.321871 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5519 16:55:29.324933 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5520 16:55:29.327727 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5521 16:55:29.331073 iDelay=199, Bit 14, Center 102 (15 ~ 190) 176
5522 16:55:29.337686 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5523 16:55:29.338165 ==
5524 16:55:29.341507 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 16:55:29.344754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 16:55:29.345328 ==
5527 16:55:29.345706 DQS Delay:
5528 16:55:29.347618 DQS0 = 0, DQS1 = 0
5529 16:55:29.348091 DQM Delay:
5530 16:55:29.350911 DQM0 = 105, DQM1 = 92
5531 16:55:29.351388 DQ Delay:
5532 16:55:29.354491 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =100
5533 16:55:29.357804 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5534 16:55:29.360906 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5535 16:55:29.364577 DQ12 =98, DQ13 =94, DQ14 =102, DQ15 =98
5536 16:55:29.365145
5537 16:55:29.365520
5538 16:55:29.374216 [DQSOSCAuto] RK1, (LSB)MR18= 0x2809, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5539 16:55:29.374845 CH0 RK1: MR19=505, MR18=2809
5540 16:55:29.380839 CH0_RK1: MR19=0x505, MR18=0x2809, DQSOSC=409, MR23=63, INC=64, DEC=43
5541 16:55:29.384036 [RxdqsGatingPostProcess] freq 933
5542 16:55:29.391388 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5543 16:55:29.393582 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 16:55:29.396786 best DQS1 dly(2T, 0.5T) = (0, 10)
5545 16:55:29.400277 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 16:55:29.403384 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5547 16:55:29.407476 best DQS0 dly(2T, 0.5T) = (0, 10)
5548 16:55:29.410118 best DQS1 dly(2T, 0.5T) = (0, 10)
5549 16:55:29.413420 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5550 16:55:29.417104 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5551 16:55:29.417680 Pre-setting of DQS Precalculation
5552 16:55:29.423367 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5553 16:55:29.423927 ==
5554 16:55:29.426964 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 16:55:29.430229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 16:55:29.430737 ==
5557 16:55:29.437298 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5558 16:55:29.443279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5559 16:55:29.447422 [CA 0] Center 37 (7~68) winsize 62
5560 16:55:29.450463 [CA 1] Center 37 (7~68) winsize 62
5561 16:55:29.453883 [CA 2] Center 35 (5~66) winsize 62
5562 16:55:29.457357 [CA 3] Center 34 (4~65) winsize 62
5563 16:55:29.460220 [CA 4] Center 34 (4~65) winsize 62
5564 16:55:29.463785 [CA 5] Center 34 (4~64) winsize 61
5565 16:55:29.464383
5566 16:55:29.467012 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5567 16:55:29.467581
5568 16:55:29.470165 [CATrainingPosCal] consider 1 rank data
5569 16:55:29.474064 u2DelayCellTimex100 = 270/100 ps
5570 16:55:29.476627 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5571 16:55:29.480634 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5572 16:55:29.483507 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5573 16:55:29.486653 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5574 16:55:29.490094 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5575 16:55:29.494173 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5576 16:55:29.494807
5577 16:55:29.499675 CA PerBit enable=1, Macro0, CA PI delay=34
5578 16:55:29.500142
5579 16:55:29.503618 [CBTSetCACLKResult] CA Dly = 34
5580 16:55:29.504123 CS Dly: 6 (0~37)
5581 16:55:29.504498 ==
5582 16:55:29.506474 Dram Type= 6, Freq= 0, CH_1, rank 1
5583 16:55:29.509781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 16:55:29.510417 ==
5585 16:55:29.516521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5586 16:55:29.523837 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5587 16:55:29.526766 [CA 0] Center 37 (7~68) winsize 62
5588 16:55:29.529773 [CA 1] Center 37 (7~68) winsize 62
5589 16:55:29.532747 [CA 2] Center 35 (5~66) winsize 62
5590 16:55:29.537044 [CA 3] Center 35 (5~65) winsize 61
5591 16:55:29.540375 [CA 4] Center 35 (5~65) winsize 61
5592 16:55:29.543095 [CA 5] Center 34 (4~64) winsize 61
5593 16:55:29.543663
5594 16:55:29.546259 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5595 16:55:29.546874
5596 16:55:29.549837 [CATrainingPosCal] consider 2 rank data
5597 16:55:29.552952 u2DelayCellTimex100 = 270/100 ps
5598 16:55:29.556348 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5599 16:55:29.559508 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5600 16:55:29.563070 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5601 16:55:29.566565 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5602 16:55:29.569903 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5603 16:55:29.575906 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5604 16:55:29.576513
5605 16:55:29.579054 CA PerBit enable=1, Macro0, CA PI delay=34
5606 16:55:29.579519
5607 16:55:29.582555 [CBTSetCACLKResult] CA Dly = 34
5608 16:55:29.583177 CS Dly: 7 (0~39)
5609 16:55:29.583739
5610 16:55:29.585720 ----->DramcWriteLeveling(PI) begin...
5611 16:55:29.586220 ==
5612 16:55:29.589454 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 16:55:29.596551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 16:55:29.597145 ==
5615 16:55:29.599022 Write leveling (Byte 0): 25 => 25
5616 16:55:29.602570 Write leveling (Byte 1): 29 => 29
5617 16:55:29.603034 DramcWriteLeveling(PI) end<-----
5618 16:55:29.603406
5619 16:55:29.606037 ==
5620 16:55:29.609279 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 16:55:29.612510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 16:55:29.613148 ==
5623 16:55:29.615787 [Gating] SW mode calibration
5624 16:55:29.622806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5625 16:55:29.626260 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5626 16:55:29.632010 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 16:55:29.635824 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 16:55:29.638584 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 16:55:29.645788 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 16:55:29.648930 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 16:55:29.652383 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5632 16:55:29.659306 0 14 24 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 1)
5633 16:55:29.662438 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5634 16:55:29.665341 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 16:55:29.672304 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 16:55:29.675181 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 16:55:29.678750 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 16:55:29.685761 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 16:55:29.689343 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 16:55:29.691684 0 15 24 | B1->B0 | 2525 2f2f | 0 1 | (0 0) (0 0)
5641 16:55:29.698556 0 15 28 | B1->B0 | 3d3d 4242 | 0 0 | (0 0) (0 0)
5642 16:55:29.701802 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 16:55:29.704973 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:55:29.711828 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 16:55:29.714916 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 16:55:29.718422 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 16:55:29.725360 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5648 16:55:29.728227 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5649 16:55:29.731490 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 16:55:29.738575 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 16:55:29.741596 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:55:29.744958 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:55:29.751453 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:55:29.754971 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:55:29.759122 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:55:29.764667 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:55:29.767792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:55:29.771738 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:55:29.778174 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:55:29.781432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 16:55:29.784366 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 16:55:29.791244 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 16:55:29.794309 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5664 16:55:29.798097 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5665 16:55:29.801133 Total UI for P1: 0, mck2ui 16
5666 16:55:29.804063 best dqsien dly found for B0: ( 1, 2, 20)
5667 16:55:29.808121 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5668 16:55:29.814713 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 16:55:29.817618 Total UI for P1: 0, mck2ui 16
5670 16:55:29.821030 best dqsien dly found for B1: ( 1, 2, 26)
5671 16:55:29.824387 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5672 16:55:29.827355 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5673 16:55:29.827937
5674 16:55:29.831011 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5675 16:55:29.833719 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5676 16:55:29.837067 [Gating] SW calibration Done
5677 16:55:29.837557 ==
5678 16:55:29.840527 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 16:55:29.843991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 16:55:29.844577 ==
5681 16:55:29.847030 RX Vref Scan: 0
5682 16:55:29.847515
5683 16:55:29.850074 RX Vref 0 -> 0, step: 1
5684 16:55:29.850610
5685 16:55:29.851092 RX Delay -80 -> 252, step: 8
5686 16:55:29.857158 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5687 16:55:29.860282 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5688 16:55:29.863751 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5689 16:55:29.867312 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5690 16:55:29.870444 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5691 16:55:29.877080 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5692 16:55:29.882016 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5693 16:55:29.883538 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5694 16:55:29.886584 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5695 16:55:29.890426 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5696 16:55:29.893740 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5697 16:55:29.900004 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5698 16:55:29.903153 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5699 16:55:29.906773 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5700 16:55:29.909694 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5701 16:55:29.913259 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5702 16:55:29.913827 ==
5703 16:55:29.916326 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 16:55:29.922967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 16:55:29.923542 ==
5706 16:55:29.923918 DQS Delay:
5707 16:55:29.926607 DQS0 = 0, DQS1 = 0
5708 16:55:29.927165 DQM Delay:
5709 16:55:29.929432 DQM0 = 102, DQM1 = 95
5710 16:55:29.929901 DQ Delay:
5711 16:55:29.933303 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5712 16:55:29.935849 DQ4 =99, DQ5 =111, DQ6 =115, DQ7 =99
5713 16:55:29.939262 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5714 16:55:29.943518 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =99
5715 16:55:29.944103
5716 16:55:29.944480
5717 16:55:29.944821 ==
5718 16:55:29.945758 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 16:55:29.949292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 16:55:29.950015 ==
5721 16:55:29.950452
5722 16:55:29.953294
5723 16:55:29.953877 TX Vref Scan disable
5724 16:55:29.955910 == TX Byte 0 ==
5725 16:55:29.959060 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5726 16:55:29.962286 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5727 16:55:29.965815 == TX Byte 1 ==
5728 16:55:29.968794 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5729 16:55:29.972856 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5730 16:55:29.973428 ==
5731 16:55:29.976237 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 16:55:29.982256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 16:55:29.982881 ==
5734 16:55:29.983255
5735 16:55:29.983597
5736 16:55:29.983926 TX Vref Scan disable
5737 16:55:29.986676 == TX Byte 0 ==
5738 16:55:29.990494 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 16:55:29.996847 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 16:55:29.997416 == TX Byte 1 ==
5741 16:55:29.999621 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5742 16:55:30.007412 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5743 16:55:30.007983
5744 16:55:30.008356 [DATLAT]
5745 16:55:30.008696 Freq=933, CH1 RK0
5746 16:55:30.009028
5747 16:55:30.009787 DATLAT Default: 0xd
5748 16:55:30.010254 0, 0xFFFF, sum = 0
5749 16:55:30.013020 1, 0xFFFF, sum = 0
5750 16:55:30.016023 2, 0xFFFF, sum = 0
5751 16:55:30.016598 3, 0xFFFF, sum = 0
5752 16:55:30.019003 4, 0xFFFF, sum = 0
5753 16:55:30.019481 5, 0xFFFF, sum = 0
5754 16:55:30.022806 6, 0xFFFF, sum = 0
5755 16:55:30.023377 7, 0xFFFF, sum = 0
5756 16:55:30.025963 8, 0xFFFF, sum = 0
5757 16:55:30.026578 9, 0xFFFF, sum = 0
5758 16:55:30.029186 10, 0x0, sum = 1
5759 16:55:30.029756 11, 0x0, sum = 2
5760 16:55:30.033028 12, 0x0, sum = 3
5761 16:55:30.033615 13, 0x0, sum = 4
5762 16:55:30.035550 best_step = 11
5763 16:55:30.036022
5764 16:55:30.036391 ==
5765 16:55:30.040255 Dram Type= 6, Freq= 0, CH_1, rank 0
5766 16:55:30.042769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5767 16:55:30.043342 ==
5768 16:55:30.043721 RX Vref Scan: 1
5769 16:55:30.044065
5770 16:55:30.046888 RX Vref 0 -> 0, step: 1
5771 16:55:30.047454
5772 16:55:30.049070 RX Delay -53 -> 252, step: 4
5773 16:55:30.049539
5774 16:55:30.052863 Set Vref, RX VrefLevel [Byte0]: 52
5775 16:55:30.055843 [Byte1]: 50
5776 16:55:30.059750
5777 16:55:30.060311 Final RX Vref Byte 0 = 52 to rank0
5778 16:55:30.062199 Final RX Vref Byte 1 = 50 to rank0
5779 16:55:30.065655 Final RX Vref Byte 0 = 52 to rank1
5780 16:55:30.068841 Final RX Vref Byte 1 = 50 to rank1==
5781 16:55:30.072447 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 16:55:30.078783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 16:55:30.079441 ==
5784 16:55:30.079838 DQS Delay:
5785 16:55:30.082321 DQS0 = 0, DQS1 = 0
5786 16:55:30.082932 DQM Delay:
5787 16:55:30.083307 DQM0 = 104, DQM1 = 98
5788 16:55:30.085798 DQ Delay:
5789 16:55:30.088963 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5790 16:55:30.092127 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5791 16:55:30.094935 DQ8 =88, DQ9 =86, DQ10 =102, DQ11 =92
5792 16:55:30.098320 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =104
5793 16:55:30.098831
5794 16:55:30.099219
5795 16:55:30.107919 [DQSOSCAuto] RK0, (LSB)MR18= 0x1932, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5796 16:55:30.108476 CH1 RK0: MR19=505, MR18=1932
5797 16:55:30.115761 CH1_RK0: MR19=0x505, MR18=0x1932, DQSOSC=406, MR23=63, INC=65, DEC=43
5798 16:55:30.116346
5799 16:55:30.118088 ----->DramcWriteLeveling(PI) begin...
5800 16:55:30.118617 ==
5801 16:55:30.121974 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 16:55:30.128521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 16:55:30.129094 ==
5804 16:55:30.131441 Write leveling (Byte 0): 27 => 27
5805 16:55:30.134671 Write leveling (Byte 1): 27 => 27
5806 16:55:30.135268 DramcWriteLeveling(PI) end<-----
5807 16:55:30.135647
5808 16:55:30.138019 ==
5809 16:55:30.141649 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 16:55:30.145120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 16:55:30.145696 ==
5812 16:55:30.148095 [Gating] SW mode calibration
5813 16:55:30.154430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5814 16:55:30.158041 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5815 16:55:30.164546 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5816 16:55:30.167719 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 16:55:30.170998 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 16:55:30.177535 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 16:55:30.181585 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 16:55:30.184232 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 16:55:30.191294 0 14 24 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 1)
5822 16:55:30.194997 0 14 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 0)
5823 16:55:30.197852 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5824 16:55:30.204974 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 16:55:30.207285 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 16:55:30.210655 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 16:55:30.217438 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 16:55:30.220628 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 16:55:30.224637 0 15 24 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
5830 16:55:30.230704 0 15 28 | B1->B0 | 4141 3232 | 1 0 | (0 0) (0 0)
5831 16:55:30.234738 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 16:55:30.236729 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 16:55:30.243463 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 16:55:30.247252 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 16:55:30.250501 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 16:55:30.256830 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 16:55:30.260218 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 16:55:30.263856 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5839 16:55:30.269862 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 16:55:30.273483 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:55:30.276592 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:55:30.282909 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:55:30.286485 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:55:30.289911 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:55:30.296642 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:55:30.299640 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:55:30.302947 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:55:30.309505 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 16:55:30.312773 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 16:55:30.316477 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 16:55:30.323055 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 16:55:30.326147 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 16:55:30.329933 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5854 16:55:30.336144 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5855 16:55:30.339076 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 16:55:30.342663 Total UI for P1: 0, mck2ui 16
5857 16:55:30.346323 best dqsien dly found for B0: ( 1, 2, 28)
5858 16:55:30.349007 Total UI for P1: 0, mck2ui 16
5859 16:55:30.352431 best dqsien dly found for B1: ( 1, 2, 26)
5860 16:55:30.355730 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5861 16:55:30.359895 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5862 16:55:30.360508
5863 16:55:30.362044 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5864 16:55:30.365903 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5865 16:55:30.368696 [Gating] SW calibration Done
5866 16:55:30.369335 ==
5867 16:55:30.372317 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 16:55:30.378708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 16:55:30.379294 ==
5870 16:55:30.379673 RX Vref Scan: 0
5871 16:55:30.380027
5872 16:55:30.382154 RX Vref 0 -> 0, step: 1
5873 16:55:30.382770
5874 16:55:30.385353 RX Delay -80 -> 252, step: 8
5875 16:55:30.388305 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5876 16:55:30.391723 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5877 16:55:30.395066 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5878 16:55:30.398183 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5879 16:55:30.404968 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5880 16:55:30.408548 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5881 16:55:30.411541 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5882 16:55:30.414997 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5883 16:55:30.418174 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5884 16:55:30.424593 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5885 16:55:30.428348 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5886 16:55:30.431368 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5887 16:55:30.435000 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5888 16:55:30.437822 iDelay=200, Bit 13, Center 103 (16 ~ 191) 176
5889 16:55:30.444609 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5890 16:55:30.448314 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5891 16:55:30.448889 ==
5892 16:55:30.451536 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 16:55:30.454256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 16:55:30.454770 ==
5895 16:55:30.457975 DQS Delay:
5896 16:55:30.458582 DQS0 = 0, DQS1 = 0
5897 16:55:30.458957 DQM Delay:
5898 16:55:30.460955 DQM0 = 103, DQM1 = 95
5899 16:55:30.461419 DQ Delay:
5900 16:55:30.464327 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5901 16:55:30.467504 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5902 16:55:30.471001 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =87
5903 16:55:30.477851 DQ12 =107, DQ13 =103, DQ14 =99, DQ15 =107
5904 16:55:30.478471
5905 16:55:30.478848
5906 16:55:30.479188 ==
5907 16:55:30.480930 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 16:55:30.484036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 16:55:30.484615 ==
5910 16:55:30.484992
5911 16:55:30.485338
5912 16:55:30.487218 TX Vref Scan disable
5913 16:55:30.487690 == TX Byte 0 ==
5914 16:55:30.494612 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5915 16:55:30.497241 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5916 16:55:30.497815 == TX Byte 1 ==
5917 16:55:30.503916 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5918 16:55:30.507436 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5919 16:55:30.508011 ==
5920 16:55:30.510219 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 16:55:30.514020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 16:55:30.514646 ==
5923 16:55:30.515025
5924 16:55:30.515371
5925 16:55:30.517122 TX Vref Scan disable
5926 16:55:30.520831 == TX Byte 0 ==
5927 16:55:30.523388 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 16:55:30.526925 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 16:55:30.530716 == TX Byte 1 ==
5930 16:55:30.533998 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5931 16:55:30.536685 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5932 16:55:30.537163
5933 16:55:30.539901 [DATLAT]
5934 16:55:30.540376 Freq=933, CH1 RK1
5935 16:55:30.540752
5936 16:55:30.543496 DATLAT Default: 0xb
5937 16:55:30.543969 0, 0xFFFF, sum = 0
5938 16:55:30.546547 1, 0xFFFF, sum = 0
5939 16:55:30.547029 2, 0xFFFF, sum = 0
5940 16:55:30.550595 3, 0xFFFF, sum = 0
5941 16:55:30.551264 4, 0xFFFF, sum = 0
5942 16:55:30.553782 5, 0xFFFF, sum = 0
5943 16:55:30.554261 6, 0xFFFF, sum = 0
5944 16:55:30.556507 7, 0xFFFF, sum = 0
5945 16:55:30.560193 8, 0xFFFF, sum = 0
5946 16:55:30.560782 9, 0xFFFF, sum = 0
5947 16:55:30.563042 10, 0x0, sum = 1
5948 16:55:30.563526 11, 0x0, sum = 2
5949 16:55:30.563911 12, 0x0, sum = 3
5950 16:55:30.566423 13, 0x0, sum = 4
5951 16:55:30.566911 best_step = 11
5952 16:55:30.567288
5953 16:55:30.570273 ==
5954 16:55:30.570901 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 16:55:30.576918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 16:55:30.577504 ==
5957 16:55:30.577885 RX Vref Scan: 0
5958 16:55:30.578237
5959 16:55:30.579379 RX Vref 0 -> 0, step: 1
5960 16:55:30.579850
5961 16:55:30.583257 RX Delay -53 -> 252, step: 4
5962 16:55:30.586541 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5963 16:55:30.593000 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5964 16:55:30.596252 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5965 16:55:30.599650 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5966 16:55:30.603253 iDelay=199, Bit 4, Center 106 (23 ~ 190) 168
5967 16:55:30.606603 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5968 16:55:30.612730 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5969 16:55:30.616582 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5970 16:55:30.619130 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5971 16:55:30.622959 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5972 16:55:30.627296 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5973 16:55:30.628969 iDelay=199, Bit 11, Center 90 (3 ~ 178) 176
5974 16:55:30.635873 iDelay=199, Bit 12, Center 106 (23 ~ 190) 168
5975 16:55:30.639642 iDelay=199, Bit 13, Center 102 (19 ~ 186) 168
5976 16:55:30.642140 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5977 16:55:30.645732 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5978 16:55:30.649216 ==
5979 16:55:30.652282 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 16:55:30.655808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 16:55:30.656398 ==
5982 16:55:30.656776 DQS Delay:
5983 16:55:30.659205 DQS0 = 0, DQS1 = 0
5984 16:55:30.659677 DQM Delay:
5985 16:55:30.662093 DQM0 = 104, DQM1 = 97
5986 16:55:30.662709 DQ Delay:
5987 16:55:30.665766 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =102
5988 16:55:30.669079 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =102
5989 16:55:30.671912 DQ8 =82, DQ9 =86, DQ10 =98, DQ11 =90
5990 16:55:30.675293 DQ12 =106, DQ13 =102, DQ14 =106, DQ15 =106
5991 16:55:30.675860
5992 16:55:30.676236
5993 16:55:30.685195 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
5994 16:55:30.685766 CH1 RK1: MR19=504, MR18=21FD
5995 16:55:30.692278 CH1_RK1: MR19=0x504, MR18=0x21FD, DQSOSC=411, MR23=63, INC=64, DEC=42
5996 16:55:30.695639 [RxdqsGatingPostProcess] freq 933
5997 16:55:30.701750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 16:55:30.705019 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 16:55:30.708776 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 16:55:30.711787 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 16:55:30.715214 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 16:55:30.718429 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 16:55:30.721282 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 16:55:30.724612 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 16:55:30.728167 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 16:55:30.728767 Pre-setting of DQS Precalculation
6007 16:55:30.734797 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 16:55:30.741080 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 16:55:30.747816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 16:55:30.748389
6011 16:55:30.748763
6012 16:55:30.750925 [Calibration Summary] 1866 Mbps
6013 16:55:30.754612 CH 0, Rank 0
6014 16:55:30.755180 SW Impedance : PASS
6015 16:55:30.757743 DUTY Scan : NO K
6016 16:55:30.761044 ZQ Calibration : PASS
6017 16:55:30.761611 Jitter Meter : NO K
6018 16:55:30.764717 CBT Training : PASS
6019 16:55:30.768055 Write leveling : PASS
6020 16:55:30.768614 RX DQS gating : PASS
6021 16:55:30.770688 RX DQ/DQS(RDDQC) : PASS
6022 16:55:30.774260 TX DQ/DQS : PASS
6023 16:55:30.774873 RX DATLAT : PASS
6024 16:55:30.777939 RX DQ/DQS(Engine): PASS
6025 16:55:30.780927 TX OE : NO K
6026 16:55:30.781485 All Pass.
6027 16:55:30.781865
6028 16:55:30.782206 CH 0, Rank 1
6029 16:55:30.784415 SW Impedance : PASS
6030 16:55:30.787598 DUTY Scan : NO K
6031 16:55:30.788166 ZQ Calibration : PASS
6032 16:55:30.791270 Jitter Meter : NO K
6033 16:55:30.791835 CBT Training : PASS
6034 16:55:30.794287 Write leveling : PASS
6035 16:55:30.797390 RX DQS gating : PASS
6036 16:55:30.797950 RX DQ/DQS(RDDQC) : PASS
6037 16:55:30.800623 TX DQ/DQS : PASS
6038 16:55:30.803711 RX DATLAT : PASS
6039 16:55:30.804176 RX DQ/DQS(Engine): PASS
6040 16:55:30.807307 TX OE : NO K
6041 16:55:30.807878 All Pass.
6042 16:55:30.808246
6043 16:55:30.810801 CH 1, Rank 0
6044 16:55:30.811363 SW Impedance : PASS
6045 16:55:30.813754 DUTY Scan : NO K
6046 16:55:30.817259 ZQ Calibration : PASS
6047 16:55:30.817830 Jitter Meter : NO K
6048 16:55:30.820792 CBT Training : PASS
6049 16:55:30.823649 Write leveling : PASS
6050 16:55:30.824115 RX DQS gating : PASS
6051 16:55:30.827280 RX DQ/DQS(RDDQC) : PASS
6052 16:55:30.830430 TX DQ/DQS : PASS
6053 16:55:30.830995 RX DATLAT : PASS
6054 16:55:30.833539 RX DQ/DQS(Engine): PASS
6055 16:55:30.837798 TX OE : NO K
6056 16:55:30.838409 All Pass.
6057 16:55:30.838804
6058 16:55:30.839155 CH 1, Rank 1
6059 16:55:30.840123 SW Impedance : PASS
6060 16:55:30.843720 DUTY Scan : NO K
6061 16:55:30.844291 ZQ Calibration : PASS
6062 16:55:30.846762 Jitter Meter : NO K
6063 16:55:30.850240 CBT Training : PASS
6064 16:55:30.850760 Write leveling : PASS
6065 16:55:30.853610 RX DQS gating : PASS
6066 16:55:30.854189 RX DQ/DQS(RDDQC) : PASS
6067 16:55:30.856857 TX DQ/DQS : PASS
6068 16:55:30.860593 RX DATLAT : PASS
6069 16:55:30.861158 RX DQ/DQS(Engine): PASS
6070 16:55:30.864067 TX OE : NO K
6071 16:55:30.864640 All Pass.
6072 16:55:30.865010
6073 16:55:30.866735 DramC Write-DBI off
6074 16:55:30.870050 PER_BANK_REFRESH: Hybrid Mode
6075 16:55:30.870736 TX_TRACKING: ON
6076 16:55:30.880351 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 16:55:30.883404 [FAST_K] Save calibration result to emmc
6078 16:55:30.886710 dramc_set_vcore_voltage set vcore to 650000
6079 16:55:30.890208 Read voltage for 400, 6
6080 16:55:30.890817 Vio18 = 0
6081 16:55:30.893641 Vcore = 650000
6082 16:55:30.894206 Vdram = 0
6083 16:55:30.894622 Vddq = 0
6084 16:55:30.894967 Vmddr = 0
6085 16:55:30.899504 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 16:55:30.906422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 16:55:30.906988 MEM_TYPE=3, freq_sel=20
6088 16:55:30.910554 sv_algorithm_assistance_LP4_800
6089 16:55:30.912738 ============ PULL DRAM RESETB DOWN ============
6090 16:55:30.919432 ========== PULL DRAM RESETB DOWN end =========
6091 16:55:30.923026 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 16:55:30.926331 ===================================
6093 16:55:30.929671 LPDDR4 DRAM CONFIGURATION
6094 16:55:30.932673 ===================================
6095 16:55:30.933240 EX_ROW_EN[0] = 0x0
6096 16:55:30.936051 EX_ROW_EN[1] = 0x0
6097 16:55:30.936548 LP4Y_EN = 0x0
6098 16:55:30.939691 WORK_FSP = 0x0
6099 16:55:30.940499 WL = 0x2
6100 16:55:30.942826 RL = 0x2
6101 16:55:30.946139 BL = 0x2
6102 16:55:30.946896 RPST = 0x0
6103 16:55:30.949272 RD_PRE = 0x0
6104 16:55:30.949837 WR_PRE = 0x1
6105 16:55:30.953128 WR_PST = 0x0
6106 16:55:30.953687 DBI_WR = 0x0
6107 16:55:30.956503 DBI_RD = 0x0
6108 16:55:30.957087 OTF = 0x1
6109 16:55:30.959389 ===================================
6110 16:55:30.963233 ===================================
6111 16:55:30.965984 ANA top config
6112 16:55:30.969129 ===================================
6113 16:55:30.969692 DLL_ASYNC_EN = 0
6114 16:55:30.973322 ALL_SLAVE_EN = 1
6115 16:55:30.975563 NEW_RANK_MODE = 1
6116 16:55:30.979321 DLL_IDLE_MODE = 1
6117 16:55:30.979792 LP45_APHY_COMB_EN = 1
6118 16:55:30.981999 TX_ODT_DIS = 1
6119 16:55:30.985712 NEW_8X_MODE = 1
6120 16:55:30.988883 ===================================
6121 16:55:30.992425 ===================================
6122 16:55:30.995168 data_rate = 800
6123 16:55:30.999003 CKR = 1
6124 16:55:31.002130 DQ_P2S_RATIO = 4
6125 16:55:31.005467 ===================================
6126 16:55:31.006045 CA_P2S_RATIO = 4
6127 16:55:31.008892 DQ_CA_OPEN = 0
6128 16:55:31.012250 DQ_SEMI_OPEN = 1
6129 16:55:31.015218 CA_SEMI_OPEN = 1
6130 16:55:31.018694 CA_FULL_RATE = 0
6131 16:55:31.022155 DQ_CKDIV4_EN = 0
6132 16:55:31.022764 CA_CKDIV4_EN = 1
6133 16:55:31.025677 CA_PREDIV_EN = 0
6134 16:55:31.028946 PH8_DLY = 0
6135 16:55:31.031819 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 16:55:31.035204 DQ_AAMCK_DIV = 0
6137 16:55:31.038455 CA_AAMCK_DIV = 0
6138 16:55:31.039017 CA_ADMCK_DIV = 4
6139 16:55:31.041401 DQ_TRACK_CA_EN = 0
6140 16:55:31.046244 CA_PICK = 800
6141 16:55:31.048375 CA_MCKIO = 400
6142 16:55:31.051356 MCKIO_SEMI = 400
6143 16:55:31.054713 PLL_FREQ = 3016
6144 16:55:31.058052 DQ_UI_PI_RATIO = 32
6145 16:55:31.061871 CA_UI_PI_RATIO = 32
6146 16:55:31.065146 ===================================
6147 16:55:31.068200 ===================================
6148 16:55:31.068775 memory_type:LPDDR4
6149 16:55:31.071078 GP_NUM : 10
6150 16:55:31.074908 SRAM_EN : 1
6151 16:55:31.075477 MD32_EN : 0
6152 16:55:31.078569 ===================================
6153 16:55:31.081009 [ANA_INIT] >>>>>>>>>>>>>>
6154 16:55:31.084765 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 16:55:31.088179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 16:55:31.091587 ===================================
6157 16:55:31.094929 data_rate = 800,PCW = 0X7400
6158 16:55:31.097965 ===================================
6159 16:55:31.100935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 16:55:31.104606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 16:55:31.118018 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 16:55:31.121027 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 16:55:31.124751 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 16:55:31.127587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 16:55:31.131240 [ANA_INIT] flow start
6166 16:55:31.134550 [ANA_INIT] PLL >>>>>>>>
6167 16:55:31.135120 [ANA_INIT] PLL <<<<<<<<
6168 16:55:31.137667 [ANA_INIT] MIDPI >>>>>>>>
6169 16:55:31.141231 [ANA_INIT] MIDPI <<<<<<<<
6170 16:55:31.141972 [ANA_INIT] DLL >>>>>>>>
6171 16:55:31.144385 [ANA_INIT] flow end
6172 16:55:31.147950 ============ LP4 DIFF to SE enter ============
6173 16:55:31.150649 ============ LP4 DIFF to SE exit ============
6174 16:55:31.154266 [ANA_INIT] <<<<<<<<<<<<<
6175 16:55:31.157353 [Flow] Enable top DCM control >>>>>
6176 16:55:31.160696 [Flow] Enable top DCM control <<<<<
6177 16:55:31.163905 Enable DLL master slave shuffle
6178 16:55:31.170589 ==============================================================
6179 16:55:31.171192 Gating Mode config
6180 16:55:31.177321 ==============================================================
6181 16:55:31.177896 Config description:
6182 16:55:31.187196 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 16:55:31.193959 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 16:55:31.200231 SELPH_MODE 0: By rank 1: By Phase
6185 16:55:31.206954 ==============================================================
6186 16:55:31.209804 GAT_TRACK_EN = 0
6187 16:55:31.210409 RX_GATING_MODE = 2
6188 16:55:31.213307 RX_GATING_TRACK_MODE = 2
6189 16:55:31.216717 SELPH_MODE = 1
6190 16:55:31.219485 PICG_EARLY_EN = 1
6191 16:55:31.223922 VALID_LAT_VALUE = 1
6192 16:55:31.229634 ==============================================================
6193 16:55:31.232630 Enter into Gating configuration >>>>
6194 16:55:31.236441 Exit from Gating configuration <<<<
6195 16:55:31.239896 Enter into DVFS_PRE_config >>>>>
6196 16:55:31.249806 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 16:55:31.252852 Exit from DVFS_PRE_config <<<<<
6198 16:55:31.255665 Enter into PICG configuration >>>>
6199 16:55:31.259026 Exit from PICG configuration <<<<
6200 16:55:31.262297 [RX_INPUT] configuration >>>>>
6201 16:55:31.265769 [RX_INPUT] configuration <<<<<
6202 16:55:31.268721 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 16:55:31.275505 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 16:55:31.282219 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 16:55:31.288745 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 16:55:31.295200 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 16:55:31.299224 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 16:55:31.305123 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 16:55:31.308405 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 16:55:31.312213 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 16:55:31.314786 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 16:55:31.321522 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 16:55:31.325035 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 16:55:31.328272 ===================================
6215 16:55:31.331545 LPDDR4 DRAM CONFIGURATION
6216 16:55:31.335122 ===================================
6217 16:55:31.335685 EX_ROW_EN[0] = 0x0
6218 16:55:31.338148 EX_ROW_EN[1] = 0x0
6219 16:55:31.338752 LP4Y_EN = 0x0
6220 16:55:31.341408 WORK_FSP = 0x0
6221 16:55:31.344738 WL = 0x2
6222 16:55:31.345204 RL = 0x2
6223 16:55:31.347951 BL = 0x2
6224 16:55:31.348510 RPST = 0x0
6225 16:55:31.351212 RD_PRE = 0x0
6226 16:55:31.351802 WR_PRE = 0x1
6227 16:55:31.355027 WR_PST = 0x0
6228 16:55:31.355587 DBI_WR = 0x0
6229 16:55:31.357849 DBI_RD = 0x0
6230 16:55:31.358449 OTF = 0x1
6231 16:55:31.361110 ===================================
6232 16:55:31.364123 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 16:55:31.371079 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 16:55:31.373899 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 16:55:31.377914 ===================================
6236 16:55:31.380656 LPDDR4 DRAM CONFIGURATION
6237 16:55:31.383861 ===================================
6238 16:55:31.384332 EX_ROW_EN[0] = 0x10
6239 16:55:31.387243 EX_ROW_EN[1] = 0x0
6240 16:55:31.391053 LP4Y_EN = 0x0
6241 16:55:31.391622 WORK_FSP = 0x0
6242 16:55:31.393935 WL = 0x2
6243 16:55:31.394552 RL = 0x2
6244 16:55:31.397481 BL = 0x2
6245 16:55:31.398213 RPST = 0x0
6246 16:55:31.400693 RD_PRE = 0x0
6247 16:55:31.401156 WR_PRE = 0x1
6248 16:55:31.404154 WR_PST = 0x0
6249 16:55:31.404719 DBI_WR = 0x0
6250 16:55:31.407291 DBI_RD = 0x0
6251 16:55:31.407757 OTF = 0x1
6252 16:55:31.411052 ===================================
6253 16:55:31.417206 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 16:55:31.421497 nWR fixed to 30
6255 16:55:31.424831 [ModeRegInit_LP4] CH0 RK0
6256 16:55:31.425397 [ModeRegInit_LP4] CH0 RK1
6257 16:55:31.427620 [ModeRegInit_LP4] CH1 RK0
6258 16:55:31.431868 [ModeRegInit_LP4] CH1 RK1
6259 16:55:31.432448 match AC timing 19
6260 16:55:31.437863 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 16:55:31.441425 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 16:55:31.444218 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 16:55:31.451178 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 16:55:31.454203 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 16:55:31.454803 ==
6266 16:55:31.457604 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 16:55:31.460795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 16:55:31.461372 ==
6269 16:55:31.467288 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 16:55:31.473947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6271 16:55:31.477612 [CA 0] Center 36 (8~64) winsize 57
6272 16:55:31.480567 [CA 1] Center 36 (8~64) winsize 57
6273 16:55:31.483562 [CA 2] Center 36 (8~64) winsize 57
6274 16:55:31.487016 [CA 3] Center 36 (8~64) winsize 57
6275 16:55:31.490812 [CA 4] Center 36 (8~64) winsize 57
6276 16:55:31.493728 [CA 5] Center 36 (8~64) winsize 57
6277 16:55:31.494292
6278 16:55:31.497121 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6279 16:55:31.497687
6280 16:55:31.500133 [CATrainingPosCal] consider 1 rank data
6281 16:55:31.503909 u2DelayCellTimex100 = 270/100 ps
6282 16:55:31.506533 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 16:55:31.509859 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 16:55:31.514015 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 16:55:31.516575 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 16:55:31.520486 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 16:55:31.523189 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 16:55:31.523657
6289 16:55:31.530398 CA PerBit enable=1, Macro0, CA PI delay=36
6290 16:55:31.530970
6291 16:55:31.531345 [CBTSetCACLKResult] CA Dly = 36
6292 16:55:31.533243 CS Dly: 1 (0~32)
6293 16:55:31.533862 ==
6294 16:55:31.537039 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 16:55:31.539965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 16:55:31.540543 ==
6297 16:55:31.546253 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 16:55:31.553222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6299 16:55:31.556793 [CA 0] Center 36 (8~64) winsize 57
6300 16:55:31.559843 [CA 1] Center 36 (8~64) winsize 57
6301 16:55:31.563258 [CA 2] Center 36 (8~64) winsize 57
6302 16:55:31.566807 [CA 3] Center 36 (8~64) winsize 57
6303 16:55:31.567373 [CA 4] Center 36 (8~64) winsize 57
6304 16:55:31.569917 [CA 5] Center 36 (8~64) winsize 57
6305 16:55:31.570515
6306 16:55:31.576650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6307 16:55:31.577216
6308 16:55:31.579745 [CATrainingPosCal] consider 2 rank data
6309 16:55:31.583018 u2DelayCellTimex100 = 270/100 ps
6310 16:55:31.586273 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 16:55:31.589819 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 16:55:31.593002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 16:55:31.595998 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 16:55:31.599491 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 16:55:31.602662 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 16:55:31.603129
6317 16:55:31.605731 CA PerBit enable=1, Macro0, CA PI delay=36
6318 16:55:31.606197
6319 16:55:31.609515 [CBTSetCACLKResult] CA Dly = 36
6320 16:55:31.612875 CS Dly: 1 (0~32)
6321 16:55:31.613465
6322 16:55:31.615811 ----->DramcWriteLeveling(PI) begin...
6323 16:55:31.616285 ==
6324 16:55:31.618952 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 16:55:31.622487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 16:55:31.622959 ==
6327 16:55:31.626323 Write leveling (Byte 0): 40 => 8
6328 16:55:31.629288 Write leveling (Byte 1): 32 => 0
6329 16:55:31.633414 DramcWriteLeveling(PI) end<-----
6330 16:55:31.633983
6331 16:55:31.634390 ==
6332 16:55:31.635915 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 16:55:31.639345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 16:55:31.639925 ==
6335 16:55:31.642197 [Gating] SW mode calibration
6336 16:55:31.649536 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 16:55:31.655769 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 16:55:31.659815 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 16:55:31.662235 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 16:55:31.668999 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 16:55:31.672211 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 16:55:31.675900 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 16:55:31.682389 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 16:55:31.685306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 16:55:31.689172 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 16:55:31.695421 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 16:55:31.698314 Total UI for P1: 0, mck2ui 16
6348 16:55:31.702187 best dqsien dly found for B0: ( 0, 14, 24)
6349 16:55:31.705136 Total UI for P1: 0, mck2ui 16
6350 16:55:31.708340 best dqsien dly found for B1: ( 0, 14, 24)
6351 16:55:31.712522 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 16:55:31.715079 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 16:55:31.715553
6354 16:55:31.718963 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 16:55:31.721411 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 16:55:31.724854 [Gating] SW calibration Done
6357 16:55:31.725418 ==
6358 16:55:31.728346 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 16:55:31.731407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 16:55:31.734666 ==
6361 16:55:31.735131 RX Vref Scan: 0
6362 16:55:31.735495
6363 16:55:31.737995 RX Vref 0 -> 0, step: 1
6364 16:55:31.738496
6365 16:55:31.741083 RX Delay -410 -> 252, step: 16
6366 16:55:31.744360 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6367 16:55:31.748646 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6368 16:55:31.751181 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6369 16:55:31.757937 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6370 16:55:31.761452 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6371 16:55:31.764770 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6372 16:55:31.767891 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6373 16:55:31.774507 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6374 16:55:31.778050 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6375 16:55:31.781193 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6376 16:55:31.784121 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6377 16:55:31.790622 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6378 16:55:31.794289 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6379 16:55:31.797324 iDelay=230, Bit 13, Center -35 (-266 ~ 197) 464
6380 16:55:31.803896 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6381 16:55:31.807245 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6382 16:55:31.807803 ==
6383 16:55:31.811099 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 16:55:31.813944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 16:55:31.814588 ==
6386 16:55:31.817620 DQS Delay:
6387 16:55:31.818080 DQS0 = 27, DQS1 = 43
6388 16:55:31.818480 DQM Delay:
6389 16:55:31.820554 DQM0 = 13, DQM1 = 12
6390 16:55:31.821015 DQ Delay:
6391 16:55:31.823535 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6392 16:55:31.826839 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6393 16:55:31.830151 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6394 16:55:31.833618 DQ12 =16, DQ13 =8, DQ14 =24, DQ15 =16
6395 16:55:31.834182
6396 16:55:31.834613
6397 16:55:31.834956 ==
6398 16:55:31.836990 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 16:55:31.840133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 16:55:31.844014 ==
6401 16:55:31.844579
6402 16:55:31.844945
6403 16:55:31.845287 TX Vref Scan disable
6404 16:55:31.846675 == TX Byte 0 ==
6405 16:55:31.850181 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 16:55:31.853750 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 16:55:31.857081 == TX Byte 1 ==
6408 16:55:31.859986 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6409 16:55:31.863312 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6410 16:55:31.863881 ==
6411 16:55:31.866669 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 16:55:31.873064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 16:55:31.873622 ==
6414 16:55:31.873989
6415 16:55:31.874321
6416 16:55:31.874704 TX Vref Scan disable
6417 16:55:31.876544 == TX Byte 0 ==
6418 16:55:31.879757 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 16:55:31.883409 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 16:55:31.886509 == TX Byte 1 ==
6421 16:55:31.889706 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6422 16:55:31.893393 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6423 16:55:31.896226
6424 16:55:31.896784 [DATLAT]
6425 16:55:31.897148 Freq=400, CH0 RK0
6426 16:55:31.897489
6427 16:55:31.899428 DATLAT Default: 0xf
6428 16:55:31.899889 0, 0xFFFF, sum = 0
6429 16:55:31.902644 1, 0xFFFF, sum = 0
6430 16:55:31.903138 2, 0xFFFF, sum = 0
6431 16:55:31.906237 3, 0xFFFF, sum = 0
6432 16:55:31.909849 4, 0xFFFF, sum = 0
6433 16:55:31.910464 5, 0xFFFF, sum = 0
6434 16:55:31.913207 6, 0xFFFF, sum = 0
6435 16:55:31.913776 7, 0xFFFF, sum = 0
6436 16:55:31.915784 8, 0xFFFF, sum = 0
6437 16:55:31.916251 9, 0xFFFF, sum = 0
6438 16:55:31.919684 10, 0xFFFF, sum = 0
6439 16:55:31.920255 11, 0xFFFF, sum = 0
6440 16:55:31.923079 12, 0xFFFF, sum = 0
6441 16:55:31.923660 13, 0x0, sum = 1
6442 16:55:31.925762 14, 0x0, sum = 2
6443 16:55:31.926229 15, 0x0, sum = 3
6444 16:55:31.929767 16, 0x0, sum = 4
6445 16:55:31.930337 best_step = 14
6446 16:55:31.930764
6447 16:55:31.931104 ==
6448 16:55:31.933066 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 16:55:31.935957 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 16:55:31.938907 ==
6451 16:55:31.939372 RX Vref Scan: 1
6452 16:55:31.939737
6453 16:55:31.942473 RX Vref 0 -> 0, step: 1
6454 16:55:31.943029
6455 16:55:31.945893 RX Delay -327 -> 252, step: 8
6456 16:55:31.946602
6457 16:55:31.949320 Set Vref, RX VrefLevel [Byte0]: 57
6458 16:55:31.952863 [Byte1]: 51
6459 16:55:31.953428
6460 16:55:31.955756 Final RX Vref Byte 0 = 57 to rank0
6461 16:55:31.959057 Final RX Vref Byte 1 = 51 to rank0
6462 16:55:31.962427 Final RX Vref Byte 0 = 57 to rank1
6463 16:55:31.965569 Final RX Vref Byte 1 = 51 to rank1==
6464 16:55:31.968905 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 16:55:31.972132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 16:55:31.972698 ==
6467 16:55:31.975013 DQS Delay:
6468 16:55:31.975473 DQS0 = 28, DQS1 = 48
6469 16:55:31.978619 DQM Delay:
6470 16:55:31.979181 DQM0 = 12, DQM1 = 14
6471 16:55:31.982514 DQ Delay:
6472 16:55:31.983083 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6473 16:55:31.985084 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6474 16:55:31.988632 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6475 16:55:31.991808 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6476 16:55:31.992372
6477 16:55:31.992740
6478 16:55:32.001577 [DQSOSCAuto] RK0, (LSB)MR18= 0xaca3, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 388 ps
6479 16:55:32.004825 CH0 RK0: MR19=C0C, MR18=ACA3
6480 16:55:32.012257 CH0_RK0: MR19=0xC0C, MR18=0xACA3, DQSOSC=388, MR23=63, INC=392, DEC=261
6481 16:55:32.012830 ==
6482 16:55:32.014959 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 16:55:32.018495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 16:55:32.019065 ==
6485 16:55:32.021879 [Gating] SW mode calibration
6486 16:55:32.028434 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 16:55:32.035409 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 16:55:32.038166 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 16:55:32.041163 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 16:55:32.047559 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 16:55:32.051064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 16:55:32.054759 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 16:55:32.060821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 16:55:32.064381 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 16:55:32.067906 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 16:55:32.074132 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 16:55:32.074730 Total UI for P1: 0, mck2ui 16
6498 16:55:32.077628 best dqsien dly found for B0: ( 0, 14, 24)
6499 16:55:32.081292 Total UI for P1: 0, mck2ui 16
6500 16:55:32.084146 best dqsien dly found for B1: ( 0, 14, 24)
6501 16:55:32.091415 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 16:55:32.094154 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 16:55:32.094777
6504 16:55:32.097196 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 16:55:32.100691 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 16:55:32.103421 [Gating] SW calibration Done
6507 16:55:32.103890 ==
6508 16:55:32.107289 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 16:55:32.110626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 16:55:32.111193 ==
6511 16:55:32.113725 RX Vref Scan: 0
6512 16:55:32.114287
6513 16:55:32.114720 RX Vref 0 -> 0, step: 1
6514 16:55:32.115072
6515 16:55:32.116960 RX Delay -410 -> 252, step: 16
6516 16:55:32.123616 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6517 16:55:32.126734 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6518 16:55:32.130085 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6519 16:55:32.133514 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6520 16:55:32.140269 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6521 16:55:32.143141 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6522 16:55:32.146467 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6523 16:55:32.150738 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6524 16:55:32.156576 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6525 16:55:32.159490 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6526 16:55:32.162838 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6527 16:55:32.166667 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6528 16:55:32.173029 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6529 16:55:32.176314 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6530 16:55:32.179645 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6531 16:55:32.186242 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6532 16:55:32.186868 ==
6533 16:55:32.189685 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 16:55:32.193097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 16:55:32.193669 ==
6536 16:55:32.194045 DQS Delay:
6537 16:55:32.196208 DQS0 = 27, DQS1 = 43
6538 16:55:32.196771 DQM Delay:
6539 16:55:32.199634 DQM0 = 9, DQM1 = 15
6540 16:55:32.200200 DQ Delay:
6541 16:55:32.202926 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6542 16:55:32.206474 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6543 16:55:32.209859 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6544 16:55:32.212613 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6545 16:55:32.213180
6546 16:55:32.213554
6547 16:55:32.213891 ==
6548 16:55:32.215983 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 16:55:32.219431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 16:55:32.220027 ==
6551 16:55:32.220412
6552 16:55:32.220751
6553 16:55:32.222519 TX Vref Scan disable
6554 16:55:32.223074 == TX Byte 0 ==
6555 16:55:32.230302 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6556 16:55:32.232673 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6557 16:55:32.233242 == TX Byte 1 ==
6558 16:55:32.239036 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6559 16:55:32.242584 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6560 16:55:32.243188 ==
6561 16:55:32.245674 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 16:55:32.249021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 16:55:32.249493 ==
6564 16:55:32.249860
6565 16:55:32.250200
6566 16:55:32.252057 TX Vref Scan disable
6567 16:55:32.252522 == TX Byte 0 ==
6568 16:55:32.258915 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6569 16:55:32.262950 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6570 16:55:32.263532 == TX Byte 1 ==
6571 16:55:32.268961 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6572 16:55:32.272333 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6573 16:55:32.272919
6574 16:55:32.273300 [DATLAT]
6575 16:55:32.275292 Freq=400, CH0 RK1
6576 16:55:32.275757
6577 16:55:32.276127 DATLAT Default: 0xe
6578 16:55:32.279257 0, 0xFFFF, sum = 0
6579 16:55:32.279785 1, 0xFFFF, sum = 0
6580 16:55:32.282199 2, 0xFFFF, sum = 0
6581 16:55:32.282801 3, 0xFFFF, sum = 0
6582 16:55:32.285424 4, 0xFFFF, sum = 0
6583 16:55:32.288530 5, 0xFFFF, sum = 0
6584 16:55:32.289104 6, 0xFFFF, sum = 0
6585 16:55:32.291835 7, 0xFFFF, sum = 0
6586 16:55:32.292311 8, 0xFFFF, sum = 0
6587 16:55:32.295276 9, 0xFFFF, sum = 0
6588 16:55:32.295852 10, 0xFFFF, sum = 0
6589 16:55:32.298490 11, 0xFFFF, sum = 0
6590 16:55:32.299066 12, 0xFFFF, sum = 0
6591 16:55:32.301896 13, 0x0, sum = 1
6592 16:55:32.302538 14, 0x0, sum = 2
6593 16:55:32.304956 15, 0x0, sum = 3
6594 16:55:32.305425 16, 0x0, sum = 4
6595 16:55:32.308643 best_step = 14
6596 16:55:32.309238
6597 16:55:32.309614 ==
6598 16:55:32.311813 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 16:55:32.314712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 16:55:32.315184 ==
6601 16:55:32.318242 RX Vref Scan: 0
6602 16:55:32.318862
6603 16:55:32.319242 RX Vref 0 -> 0, step: 1
6604 16:55:32.319583
6605 16:55:32.321280 RX Delay -327 -> 252, step: 8
6606 16:55:32.330007 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6607 16:55:32.332348 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6608 16:55:32.335497 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6609 16:55:32.338939 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6610 16:55:32.345719 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6611 16:55:32.348656 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6612 16:55:32.352129 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6613 16:55:32.355407 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6614 16:55:32.362223 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6615 16:55:32.365264 iDelay=217, Bit 9, Center -40 (-263 ~ 184) 448
6616 16:55:32.368782 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6617 16:55:32.374928 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6618 16:55:32.378449 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6619 16:55:32.382119 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6620 16:55:32.385678 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6621 16:55:32.391711 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6622 16:55:32.392278 ==
6623 16:55:32.395053 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 16:55:32.398323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 16:55:32.398940 ==
6626 16:55:32.399316 DQS Delay:
6627 16:55:32.401866 DQS0 = 28, DQS1 = 40
6628 16:55:32.402483 DQM Delay:
6629 16:55:32.404960 DQM0 = 11, DQM1 = 13
6630 16:55:32.405545 DQ Delay:
6631 16:55:32.407994 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6632 16:55:32.411303 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6633 16:55:32.414622 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6634 16:55:32.418654 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6635 16:55:32.419226
6636 16:55:32.419598
6637 16:55:32.424288 [DQSOSCAuto] RK1, (LSB)MR18= 0xb76b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 387 ps
6638 16:55:32.427797 CH0 RK1: MR19=C0C, MR18=B76B
6639 16:55:32.434829 CH0_RK1: MR19=0xC0C, MR18=0xB76B, DQSOSC=387, MR23=63, INC=394, DEC=262
6640 16:55:32.437828 [RxdqsGatingPostProcess] freq 400
6641 16:55:32.444653 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 16:55:32.447693 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 16:55:32.450970 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 16:55:32.454508 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 16:55:32.458070 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 16:55:32.458693 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 16:55:32.460986 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 16:55:32.464255 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 16:55:32.467764 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 16:55:32.471501 Pre-setting of DQS Precalculation
6651 16:55:32.477841 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 16:55:32.478495 ==
6653 16:55:32.480661 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 16:55:32.484280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 16:55:32.484874 ==
6656 16:55:32.490945 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 16:55:32.497741 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6658 16:55:32.500605 [CA 0] Center 36 (8~64) winsize 57
6659 16:55:32.503614 [CA 1] Center 36 (8~64) winsize 57
6660 16:55:32.504104 [CA 2] Center 36 (8~64) winsize 57
6661 16:55:32.506992 [CA 3] Center 36 (8~64) winsize 57
6662 16:55:32.510752 [CA 4] Center 36 (8~64) winsize 57
6663 16:55:32.513936 [CA 5] Center 36 (8~64) winsize 57
6664 16:55:32.514546
6665 16:55:32.517014 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6666 16:55:32.520419
6667 16:55:32.523555 [CATrainingPosCal] consider 1 rank data
6668 16:55:32.524129 u2DelayCellTimex100 = 270/100 ps
6669 16:55:32.530793 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 16:55:32.533547 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 16:55:32.537124 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 16:55:32.540321 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 16:55:32.543573 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 16:55:32.547320 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 16:55:32.547895
6676 16:55:32.550024 CA PerBit enable=1, Macro0, CA PI delay=36
6677 16:55:32.550537
6678 16:55:32.553343 [CBTSetCACLKResult] CA Dly = 36
6679 16:55:32.556567 CS Dly: 1 (0~32)
6680 16:55:32.557138 ==
6681 16:55:32.559893 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 16:55:32.563272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 16:55:32.563853 ==
6684 16:55:32.570163 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 16:55:32.576651 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6686 16:55:32.577229 [CA 0] Center 36 (8~64) winsize 57
6687 16:55:32.579864 [CA 1] Center 36 (8~64) winsize 57
6688 16:55:32.582949 [CA 2] Center 36 (8~64) winsize 57
6689 16:55:32.586408 [CA 3] Center 36 (8~64) winsize 57
6690 16:55:32.589575 [CA 4] Center 36 (8~64) winsize 57
6691 16:55:32.592620 [CA 5] Center 36 (8~64) winsize 57
6692 16:55:32.593119
6693 16:55:32.596063 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6694 16:55:32.596531
6695 16:55:32.599659 [CATrainingPosCal] consider 2 rank data
6696 16:55:32.602717 u2DelayCellTimex100 = 270/100 ps
6697 16:55:32.606380 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 16:55:32.613155 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 16:55:32.616088 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 16:55:32.619422 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 16:55:32.622664 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 16:55:32.625982 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 16:55:32.626592
6704 16:55:32.629753 CA PerBit enable=1, Macro0, CA PI delay=36
6705 16:55:32.630329
6706 16:55:32.633047 [CBTSetCACLKResult] CA Dly = 36
6707 16:55:32.633621 CS Dly: 1 (0~32)
6708 16:55:32.635708
6709 16:55:32.639582 ----->DramcWriteLeveling(PI) begin...
6710 16:55:32.640159 ==
6711 16:55:32.642633 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 16:55:32.646372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 16:55:32.646969 ==
6714 16:55:32.649524 Write leveling (Byte 0): 40 => 8
6715 16:55:32.652540 Write leveling (Byte 1): 32 => 0
6716 16:55:32.655614 DramcWriteLeveling(PI) end<-----
6717 16:55:32.656186
6718 16:55:32.656565 ==
6719 16:55:32.659043 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 16:55:32.662506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 16:55:32.663079 ==
6722 16:55:32.666778 [Gating] SW mode calibration
6723 16:55:32.672382 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 16:55:32.678802 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 16:55:32.682272 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 16:55:32.685442 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 16:55:32.691956 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 16:55:32.695490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 16:55:32.698685 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 16:55:32.705119 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 16:55:32.708740 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 16:55:32.711987 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 16:55:32.718295 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 16:55:32.718909 Total UI for P1: 0, mck2ui 16
6735 16:55:32.725085 best dqsien dly found for B0: ( 0, 14, 24)
6736 16:55:32.725668 Total UI for P1: 0, mck2ui 16
6737 16:55:32.731536 best dqsien dly found for B1: ( 0, 14, 24)
6738 16:55:32.735288 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 16:55:32.738447 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 16:55:32.739018
6741 16:55:32.742232 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 16:55:32.744964 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 16:55:32.748587 [Gating] SW calibration Done
6744 16:55:32.749158 ==
6745 16:55:32.751249 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 16:55:32.754930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 16:55:32.755514 ==
6748 16:55:32.758453 RX Vref Scan: 0
6749 16:55:32.758921
6750 16:55:32.759297 RX Vref 0 -> 0, step: 1
6751 16:55:32.761653
6752 16:55:32.762213 RX Delay -410 -> 252, step: 16
6753 16:55:32.768177 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6754 16:55:32.771968 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6755 16:55:32.774754 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6756 16:55:32.777703 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6757 16:55:32.784416 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6758 16:55:32.787822 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6759 16:55:32.791028 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6760 16:55:32.794229 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6761 16:55:32.801159 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6762 16:55:32.804320 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6763 16:55:32.807904 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6764 16:55:32.813958 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6765 16:55:32.817452 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6766 16:55:32.820697 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6767 16:55:32.823727 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6768 16:55:32.830748 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6769 16:55:32.831323 ==
6770 16:55:32.834241 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 16:55:32.836929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 16:55:32.837409 ==
6773 16:55:32.837783 DQS Delay:
6774 16:55:32.840528 DQS0 = 27, DQS1 = 43
6775 16:55:32.841101 DQM Delay:
6776 16:55:32.843897 DQM0 = 6, DQM1 = 15
6777 16:55:32.844472 DQ Delay:
6778 16:55:32.847081 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6779 16:55:32.850428 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6780 16:55:32.853493 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6781 16:55:32.857079 DQ12 =32, DQ13 =16, DQ14 =16, DQ15 =24
6782 16:55:32.857664
6783 16:55:32.858036
6784 16:55:32.858415 ==
6785 16:55:32.860539 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 16:55:32.863523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 16:55:32.864109 ==
6788 16:55:32.864536
6789 16:55:32.864910
6790 16:55:32.866541 TX Vref Scan disable
6791 16:55:32.870280 == TX Byte 0 ==
6792 16:55:32.873513 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 16:55:32.876789 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 16:55:32.879899 == TX Byte 1 ==
6795 16:55:32.883737 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6796 16:55:32.886124 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6797 16:55:32.886651 ==
6798 16:55:32.889980 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 16:55:32.893157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 16:55:32.896141 ==
6801 16:55:32.896615
6802 16:55:32.896985
6803 16:55:32.897329 TX Vref Scan disable
6804 16:55:32.899792 == TX Byte 0 ==
6805 16:55:32.902841 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 16:55:32.906442 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 16:55:32.910840 == TX Byte 1 ==
6808 16:55:32.912508 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6809 16:55:32.916054 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6810 16:55:32.916545
6811 16:55:32.919554 [DATLAT]
6812 16:55:32.920067 Freq=400, CH1 RK0
6813 16:55:32.920444
6814 16:55:32.922862 DATLAT Default: 0xf
6815 16:55:32.923435 0, 0xFFFF, sum = 0
6816 16:55:32.926088 1, 0xFFFF, sum = 0
6817 16:55:32.926618 2, 0xFFFF, sum = 0
6818 16:55:32.929331 3, 0xFFFF, sum = 0
6819 16:55:32.929917 4, 0xFFFF, sum = 0
6820 16:55:32.932777 5, 0xFFFF, sum = 0
6821 16:55:32.933371 6, 0xFFFF, sum = 0
6822 16:55:32.935870 7, 0xFFFF, sum = 0
6823 16:55:32.936362 8, 0xFFFF, sum = 0
6824 16:55:32.939330 9, 0xFFFF, sum = 0
6825 16:55:32.943313 10, 0xFFFF, sum = 0
6826 16:55:32.943904 11, 0xFFFF, sum = 0
6827 16:55:32.946175 12, 0xFFFF, sum = 0
6828 16:55:32.946799 13, 0x0, sum = 1
6829 16:55:32.949812 14, 0x0, sum = 2
6830 16:55:32.950429 15, 0x0, sum = 3
6831 16:55:32.950936 16, 0x0, sum = 4
6832 16:55:32.953391 best_step = 14
6833 16:55:32.953874
6834 16:55:32.954382 ==
6835 16:55:32.955468 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 16:55:32.958925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 16:55:32.959397 ==
6838 16:55:32.962101 RX Vref Scan: 1
6839 16:55:32.962642
6840 16:55:32.966569 RX Vref 0 -> 0, step: 1
6841 16:55:32.967132
6842 16:55:32.967506 RX Delay -327 -> 252, step: 8
6843 16:55:32.967853
6844 16:55:32.968748 Set Vref, RX VrefLevel [Byte0]: 52
6845 16:55:32.972456 [Byte1]: 50
6846 16:55:32.977890
6847 16:55:32.978499 Final RX Vref Byte 0 = 52 to rank0
6848 16:55:32.981663 Final RX Vref Byte 1 = 50 to rank0
6849 16:55:32.984039 Final RX Vref Byte 0 = 52 to rank1
6850 16:55:32.987706 Final RX Vref Byte 1 = 50 to rank1==
6851 16:55:32.990284 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 16:55:32.997058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 16:55:32.997534 ==
6854 16:55:32.997907 DQS Delay:
6855 16:55:33.000233 DQS0 = 28, DQS1 = 40
6856 16:55:33.000610 DQM Delay:
6857 16:55:33.000946 DQM0 = 7, DQM1 = 13
6858 16:55:33.003906 DQ Delay:
6859 16:55:33.007278 DQ0 =8, DQ1 =4, DQ2 =0, DQ3 =4
6860 16:55:33.007844 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6861 16:55:33.010524 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6862 16:55:33.013909 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6863 16:55:33.014518
6864 16:55:33.014896
6865 16:55:33.023473 [DQSOSCAuto] RK0, (LSB)MR18= 0x98d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 390 ps
6866 16:55:33.026946 CH1 RK0: MR19=C0C, MR18=98D1
6867 16:55:33.033791 CH1_RK0: MR19=0xC0C, MR18=0x98D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6868 16:55:33.034414 ==
6869 16:55:33.036783 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 16:55:33.040090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 16:55:33.040570 ==
6872 16:55:33.043738 [Gating] SW mode calibration
6873 16:55:33.050575 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 16:55:33.056656 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 16:55:33.060364 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 16:55:33.063672 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 16:55:33.070220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 16:55:33.073468 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 16:55:33.076427 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 16:55:33.083343 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 16:55:33.086415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 16:55:33.090508 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 16:55:33.096692 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 16:55:33.097261 Total UI for P1: 0, mck2ui 16
6885 16:55:33.099788 best dqsien dly found for B0: ( 0, 14, 24)
6886 16:55:33.103164 Total UI for P1: 0, mck2ui 16
6887 16:55:33.106513 best dqsien dly found for B1: ( 0, 14, 24)
6888 16:55:33.113392 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 16:55:33.116966 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 16:55:33.117536
6891 16:55:33.119823 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 16:55:33.122539 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 16:55:33.126183 [Gating] SW calibration Done
6894 16:55:33.126809 ==
6895 16:55:33.129691 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 16:55:33.133067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 16:55:33.133635 ==
6898 16:55:33.136188 RX Vref Scan: 0
6899 16:55:33.136754
6900 16:55:33.137205 RX Vref 0 -> 0, step: 1
6901 16:55:33.137562
6902 16:55:33.139130 RX Delay -410 -> 252, step: 16
6903 16:55:33.145784 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6904 16:55:33.149639 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6905 16:55:33.152613 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6906 16:55:33.156313 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6907 16:55:33.162512 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6908 16:55:33.166625 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6909 16:55:33.169442 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6910 16:55:33.172387 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6911 16:55:33.178764 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6912 16:55:33.182169 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6913 16:55:33.185104 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6914 16:55:33.188746 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6915 16:55:33.195393 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6916 16:55:33.198722 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6917 16:55:33.201925 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6918 16:55:33.208610 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6919 16:55:33.209232 ==
6920 16:55:33.211801 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 16:55:33.214896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 16:55:33.215408 ==
6923 16:55:33.215785 DQS Delay:
6924 16:55:33.219417 DQS0 = 35, DQS1 = 43
6925 16:55:33.219879 DQM Delay:
6926 16:55:33.221932 DQM0 = 17, DQM1 = 18
6927 16:55:33.222545 DQ Delay:
6928 16:55:33.225112 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6929 16:55:33.228441 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6930 16:55:33.231770 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6931 16:55:33.234769 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6932 16:55:33.235326
6933 16:55:33.235691
6934 16:55:33.236119 ==
6935 16:55:33.238567 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 16:55:33.242274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 16:55:33.242913 ==
6938 16:55:33.243286
6939 16:55:33.244647
6940 16:55:33.245110 TX Vref Scan disable
6941 16:55:33.248314 == TX Byte 0 ==
6942 16:55:33.251313 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6943 16:55:33.254821 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6944 16:55:33.258465 == TX Byte 1 ==
6945 16:55:33.261301 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6946 16:55:33.264595 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6947 16:55:33.265074 ==
6948 16:55:33.267756 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 16:55:33.271020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 16:55:33.271499 ==
6951 16:55:33.274747
6952 16:55:33.275318
6953 16:55:33.275699 TX Vref Scan disable
6954 16:55:33.278084 == TX Byte 0 ==
6955 16:55:33.280788 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6956 16:55:33.284052 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6957 16:55:33.287601 == TX Byte 1 ==
6958 16:55:33.291480 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6959 16:55:33.294301 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6960 16:55:33.294905
6961 16:55:33.295282 [DATLAT]
6962 16:55:33.297566 Freq=400, CH1 RK1
6963 16:55:33.298142
6964 16:55:33.301070 DATLAT Default: 0xe
6965 16:55:33.301653 0, 0xFFFF, sum = 0
6966 16:55:33.304065 1, 0xFFFF, sum = 0
6967 16:55:33.304548 2, 0xFFFF, sum = 0
6968 16:55:33.307630 3, 0xFFFF, sum = 0
6969 16:55:33.308217 4, 0xFFFF, sum = 0
6970 16:55:33.311134 5, 0xFFFF, sum = 0
6971 16:55:33.311715 6, 0xFFFF, sum = 0
6972 16:55:33.314558 7, 0xFFFF, sum = 0
6973 16:55:33.315146 8, 0xFFFF, sum = 0
6974 16:55:33.317604 9, 0xFFFF, sum = 0
6975 16:55:33.318248 10, 0xFFFF, sum = 0
6976 16:55:33.320378 11, 0xFFFF, sum = 0
6977 16:55:33.323549 12, 0xFFFF, sum = 0
6978 16:55:33.324028 13, 0x0, sum = 1
6979 16:55:33.324412 14, 0x0, sum = 2
6980 16:55:33.326825 15, 0x0, sum = 3
6981 16:55:33.327310 16, 0x0, sum = 4
6982 16:55:33.330522 best_step = 14
6983 16:55:33.331102
6984 16:55:33.331483 ==
6985 16:55:33.333926 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 16:55:33.337024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 16:55:33.337618 ==
6988 16:55:33.340859 RX Vref Scan: 0
6989 16:55:33.341434
6990 16:55:33.341812 RX Vref 0 -> 0, step: 1
6991 16:55:33.343380
6992 16:55:33.343855 RX Delay -327 -> 252, step: 8
6993 16:55:33.351703 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6994 16:55:33.355154 iDelay=217, Bit 1, Center -24 (-239 ~ 192) 432
6995 16:55:33.358062 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6996 16:55:33.364699 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6997 16:55:33.369400 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6998 16:55:33.371515 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6999 16:55:33.374682 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
7000 16:55:33.381575 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7001 16:55:33.385077 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7002 16:55:33.388020 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7003 16:55:33.391225 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7004 16:55:33.398161 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7005 16:55:33.401340 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
7006 16:55:33.404444 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7007 16:55:33.407997 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7008 16:55:33.414286 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7009 16:55:33.414897 ==
7010 16:55:33.417669 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 16:55:33.421622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 16:55:33.422208 ==
7013 16:55:33.422737 DQS Delay:
7014 16:55:33.424462 DQS0 = 32, DQS1 = 36
7015 16:55:33.425059 DQM Delay:
7016 16:55:33.427356 DQM0 = 13, DQM1 = 12
7017 16:55:33.427839 DQ Delay:
7018 16:55:33.431123 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7019 16:55:33.434161 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
7020 16:55:33.437543 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7021 16:55:33.440782 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7022 16:55:33.441364
7023 16:55:33.441857
7024 16:55:33.450816 [DQSOSCAuto] RK1, (LSB)MR18= 0xa952, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7025 16:55:33.451405 CH1 RK1: MR19=C0C, MR18=A952
7026 16:55:33.457789 CH1_RK1: MR19=0xC0C, MR18=0xA952, DQSOSC=388, MR23=63, INC=392, DEC=261
7027 16:55:33.460613 [RxdqsGatingPostProcess] freq 400
7028 16:55:33.467341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 16:55:33.471477 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 16:55:33.474321 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 16:55:33.477107 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 16:55:33.480422 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 16:55:33.483620 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 16:55:33.484195 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 16:55:33.487057 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 16:55:33.490341 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 16:55:33.493653 Pre-setting of DQS Precalculation
7038 16:55:33.500496 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 16:55:33.506682 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 16:55:33.513322 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 16:55:33.513881
7042 16:55:33.514250
7043 16:55:33.516997 [Calibration Summary] 800 Mbps
7044 16:55:33.519700 CH 0, Rank 0
7045 16:55:33.520166 SW Impedance : PASS
7046 16:55:33.523256 DUTY Scan : NO K
7047 16:55:33.526243 ZQ Calibration : PASS
7048 16:55:33.526765 Jitter Meter : NO K
7049 16:55:33.530280 CBT Training : PASS
7050 16:55:33.530893 Write leveling : PASS
7051 16:55:33.533294 RX DQS gating : PASS
7052 16:55:33.536170 RX DQ/DQS(RDDQC) : PASS
7053 16:55:33.536640 TX DQ/DQS : PASS
7054 16:55:33.539682 RX DATLAT : PASS
7055 16:55:33.543458 RX DQ/DQS(Engine): PASS
7056 16:55:33.544025 TX OE : NO K
7057 16:55:33.546957 All Pass.
7058 16:55:33.547522
7059 16:55:33.547900 CH 0, Rank 1
7060 16:55:33.550156 SW Impedance : PASS
7061 16:55:33.550648 DUTY Scan : NO K
7062 16:55:33.552733 ZQ Calibration : PASS
7063 16:55:33.556321 Jitter Meter : NO K
7064 16:55:33.556790 CBT Training : PASS
7065 16:55:33.559475 Write leveling : NO K
7066 16:55:33.563001 RX DQS gating : PASS
7067 16:55:33.563473 RX DQ/DQS(RDDQC) : PASS
7068 16:55:33.566019 TX DQ/DQS : PASS
7069 16:55:33.569466 RX DATLAT : PASS
7070 16:55:33.569931 RX DQ/DQS(Engine): PASS
7071 16:55:33.572833 TX OE : NO K
7072 16:55:33.573362 All Pass.
7073 16:55:33.573848
7074 16:55:33.576403 CH 1, Rank 0
7075 16:55:33.576889 SW Impedance : PASS
7076 16:55:33.578898 DUTY Scan : NO K
7077 16:55:33.583049 ZQ Calibration : PASS
7078 16:55:33.583524 Jitter Meter : NO K
7079 16:55:33.585548 CBT Training : PASS
7080 16:55:33.588932 Write leveling : PASS
7081 16:55:33.589361 RX DQS gating : PASS
7082 16:55:33.592417 RX DQ/DQS(RDDQC) : PASS
7083 16:55:33.595375 TX DQ/DQS : PASS
7084 16:55:33.595798 RX DATLAT : PASS
7085 16:55:33.598873 RX DQ/DQS(Engine): PASS
7086 16:55:33.602431 TX OE : NO K
7087 16:55:33.602934 All Pass.
7088 16:55:33.603292
7089 16:55:33.603621 CH 1, Rank 1
7090 16:55:33.605091 SW Impedance : PASS
7091 16:55:33.609020 DUTY Scan : NO K
7092 16:55:33.609527 ZQ Calibration : PASS
7093 16:55:33.611764 Jitter Meter : NO K
7094 16:55:33.615683 CBT Training : PASS
7095 16:55:33.616213 Write leveling : NO K
7096 16:55:33.618806 RX DQS gating : PASS
7097 16:55:33.619258 RX DQ/DQS(RDDQC) : PASS
7098 16:55:33.621992 TX DQ/DQS : PASS
7099 16:55:33.625866 RX DATLAT : PASS
7100 16:55:33.626619 RX DQ/DQS(Engine): PASS
7101 16:55:33.628306 TX OE : NO K
7102 16:55:33.628733 All Pass.
7103 16:55:33.629072
7104 16:55:33.631857 DramC Write-DBI off
7105 16:55:33.635220 PER_BANK_REFRESH: Hybrid Mode
7106 16:55:33.635742 TX_TRACKING: ON
7107 16:55:33.645100 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 16:55:33.648565 [FAST_K] Save calibration result to emmc
7109 16:55:33.652154 dramc_set_vcore_voltage set vcore to 725000
7110 16:55:33.654963 Read voltage for 1600, 0
7111 16:55:33.655565 Vio18 = 0
7112 16:55:33.658291 Vcore = 725000
7113 16:55:33.658878 Vdram = 0
7114 16:55:33.659220 Vddq = 0
7115 16:55:33.659553 Vmddr = 0
7116 16:55:33.665321 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 16:55:33.671422 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 16:55:33.671950 MEM_TYPE=3, freq_sel=13
7119 16:55:33.674944 sv_algorithm_assistance_LP4_3733
7120 16:55:33.678961 ============ PULL DRAM RESETB DOWN ============
7121 16:55:33.684663 ========== PULL DRAM RESETB DOWN end =========
7122 16:55:33.688250 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 16:55:33.691443 ===================================
7124 16:55:33.694686 LPDDR4 DRAM CONFIGURATION
7125 16:55:33.698401 ===================================
7126 16:55:33.698980 EX_ROW_EN[0] = 0x0
7127 16:55:33.701531 EX_ROW_EN[1] = 0x0
7128 16:55:33.702096 LP4Y_EN = 0x0
7129 16:55:33.704786 WORK_FSP = 0x1
7130 16:55:33.705254 WL = 0x5
7131 16:55:33.707754 RL = 0x5
7132 16:55:33.711381 BL = 0x2
7133 16:55:33.711975 RPST = 0x0
7134 16:55:33.714475 RD_PRE = 0x0
7135 16:55:33.715054 WR_PRE = 0x1
7136 16:55:33.718113 WR_PST = 0x1
7137 16:55:33.718750 DBI_WR = 0x0
7138 16:55:33.721415 DBI_RD = 0x0
7139 16:55:33.722022 OTF = 0x1
7140 16:55:33.724523 ===================================
7141 16:55:33.727492 ===================================
7142 16:55:33.731548 ANA top config
7143 16:55:33.734575 ===================================
7144 16:55:33.735155 DLL_ASYNC_EN = 0
7145 16:55:33.737999 ALL_SLAVE_EN = 0
7146 16:55:33.741271 NEW_RANK_MODE = 1
7147 16:55:33.744715 DLL_IDLE_MODE = 1
7148 16:55:33.745292 LP45_APHY_COMB_EN = 1
7149 16:55:33.747536 TX_ODT_DIS = 0
7150 16:55:33.750908 NEW_8X_MODE = 1
7151 16:55:33.754018 ===================================
7152 16:55:33.757412 ===================================
7153 16:55:33.761553 data_rate = 3200
7154 16:55:33.764614 CKR = 1
7155 16:55:33.767058 DQ_P2S_RATIO = 8
7156 16:55:33.770578 ===================================
7157 16:55:33.771148 CA_P2S_RATIO = 8
7158 16:55:33.774200 DQ_CA_OPEN = 0
7159 16:55:33.777459 DQ_SEMI_OPEN = 0
7160 16:55:33.780527 CA_SEMI_OPEN = 0
7161 16:55:33.784080 CA_FULL_RATE = 0
7162 16:55:33.787132 DQ_CKDIV4_EN = 0
7163 16:55:33.787691 CA_CKDIV4_EN = 0
7164 16:55:33.790163 CA_PREDIV_EN = 0
7165 16:55:33.794578 PH8_DLY = 12
7166 16:55:33.797307 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 16:55:33.800795 DQ_AAMCK_DIV = 4
7168 16:55:33.803694 CA_AAMCK_DIV = 4
7169 16:55:33.804379 CA_ADMCK_DIV = 4
7170 16:55:33.806892 DQ_TRACK_CA_EN = 0
7171 16:55:33.810403 CA_PICK = 1600
7172 16:55:33.813932 CA_MCKIO = 1600
7173 16:55:33.817115 MCKIO_SEMI = 0
7174 16:55:33.820356 PLL_FREQ = 3068
7175 16:55:33.824475 DQ_UI_PI_RATIO = 32
7176 16:55:33.826766 CA_UI_PI_RATIO = 0
7177 16:55:33.830206 ===================================
7178 16:55:33.833569 ===================================
7179 16:55:33.834145 memory_type:LPDDR4
7180 16:55:33.836529 GP_NUM : 10
7181 16:55:33.840206 SRAM_EN : 1
7182 16:55:33.840774 MD32_EN : 0
7183 16:55:33.843345 ===================================
7184 16:55:33.846917 [ANA_INIT] >>>>>>>>>>>>>>
7185 16:55:33.849922 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 16:55:33.853312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 16:55:33.856545 ===================================
7188 16:55:33.859555 data_rate = 3200,PCW = 0X7600
7189 16:55:33.862720 ===================================
7190 16:55:33.866820 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 16:55:33.869723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 16:55:33.876657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 16:55:33.879723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 16:55:33.883299 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 16:55:33.886246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 16:55:33.889846 [ANA_INIT] flow start
7197 16:55:33.892820 [ANA_INIT] PLL >>>>>>>>
7198 16:55:33.893387 [ANA_INIT] PLL <<<<<<<<
7199 16:55:33.896336 [ANA_INIT] MIDPI >>>>>>>>
7200 16:55:33.899876 [ANA_INIT] MIDPI <<<<<<<<
7201 16:55:33.904023 [ANA_INIT] DLL >>>>>>>>
7202 16:55:33.904498 [ANA_INIT] DLL <<<<<<<<
7203 16:55:33.905936 [ANA_INIT] flow end
7204 16:55:33.909047 ============ LP4 DIFF to SE enter ============
7205 16:55:33.912502 ============ LP4 DIFF to SE exit ============
7206 16:55:33.915782 [ANA_INIT] <<<<<<<<<<<<<
7207 16:55:33.918905 [Flow] Enable top DCM control >>>>>
7208 16:55:33.922279 [Flow] Enable top DCM control <<<<<
7209 16:55:33.926280 Enable DLL master slave shuffle
7210 16:55:33.932329 ==============================================================
7211 16:55:33.932811 Gating Mode config
7212 16:55:33.939744 ==============================================================
7213 16:55:33.940314 Config description:
7214 16:55:33.949020 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 16:55:33.955731 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 16:55:33.961736 SELPH_MODE 0: By rank 1: By Phase
7217 16:55:33.965315 ==============================================================
7218 16:55:33.968552 GAT_TRACK_EN = 1
7219 16:55:33.972757 RX_GATING_MODE = 2
7220 16:55:33.975407 RX_GATING_TRACK_MODE = 2
7221 16:55:33.978332 SELPH_MODE = 1
7222 16:55:33.981973 PICG_EARLY_EN = 1
7223 16:55:33.984895 VALID_LAT_VALUE = 1
7224 16:55:33.991742 ==============================================================
7225 16:55:33.994975 Enter into Gating configuration >>>>
7226 16:55:33.998270 Exit from Gating configuration <<<<
7227 16:55:34.002288 Enter into DVFS_PRE_config >>>>>
7228 16:55:34.011535 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 16:55:34.014605 Exit from DVFS_PRE_config <<<<<
7230 16:55:34.018504 Enter into PICG configuration >>>>
7231 16:55:34.021284 Exit from PICG configuration <<<<
7232 16:55:34.024880 [RX_INPUT] configuration >>>>>
7233 16:55:34.025459 [RX_INPUT] configuration <<<<<
7234 16:55:34.031683 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 16:55:34.038264 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 16:55:34.044794 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 16:55:34.047907 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 16:55:34.054738 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 16:55:34.061643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 16:55:34.065188 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 16:55:34.067526 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 16:55:34.074434 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 16:55:34.077676 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 16:55:34.081529 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 16:55:34.087287 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 16:55:34.091075 ===================================
7247 16:55:34.091647 LPDDR4 DRAM CONFIGURATION
7248 16:55:34.093902 ===================================
7249 16:55:34.097844 EX_ROW_EN[0] = 0x0
7250 16:55:34.100922 EX_ROW_EN[1] = 0x0
7251 16:55:34.101491 LP4Y_EN = 0x0
7252 16:55:34.103985 WORK_FSP = 0x1
7253 16:55:34.104448 WL = 0x5
7254 16:55:34.107227 RL = 0x5
7255 16:55:34.107695 BL = 0x2
7256 16:55:34.110717 RPST = 0x0
7257 16:55:34.111180 RD_PRE = 0x0
7258 16:55:34.114230 WR_PRE = 0x1
7259 16:55:34.114863 WR_PST = 0x1
7260 16:55:34.117605 DBI_WR = 0x0
7261 16:55:34.118181 DBI_RD = 0x0
7262 16:55:34.120933 OTF = 0x1
7263 16:55:34.123686 ===================================
7264 16:55:34.127958 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 16:55:34.130784 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 16:55:34.136907 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 16:55:34.140404 ===================================
7268 16:55:34.140976 LPDDR4 DRAM CONFIGURATION
7269 16:55:34.143794 ===================================
7270 16:55:34.146970 EX_ROW_EN[0] = 0x10
7271 16:55:34.150512 EX_ROW_EN[1] = 0x0
7272 16:55:34.151072 LP4Y_EN = 0x0
7273 16:55:34.153541 WORK_FSP = 0x1
7274 16:55:34.154111 WL = 0x5
7275 16:55:34.156904 RL = 0x5
7276 16:55:34.157470 BL = 0x2
7277 16:55:34.159933 RPST = 0x0
7278 16:55:34.160396 RD_PRE = 0x0
7279 16:55:34.163412 WR_PRE = 0x1
7280 16:55:34.163874 WR_PST = 0x1
7281 16:55:34.166733 DBI_WR = 0x0
7282 16:55:34.167197 DBI_RD = 0x0
7283 16:55:34.170162 OTF = 0x1
7284 16:55:34.173262 ===================================
7285 16:55:34.180153 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 16:55:34.180726 ==
7287 16:55:34.183136 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 16:55:34.186881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 16:55:34.187456 ==
7290 16:55:34.189478 [Duty_Offset_Calibration]
7291 16:55:34.189942 B0:2 B1:0 CA:1
7292 16:55:34.190309
7293 16:55:34.192925 [DutyScan_Calibration_Flow] k_type=0
7294 16:55:34.203290
7295 16:55:34.203857 ==CLK 0==
7296 16:55:34.206783 Final CLK duty delay cell = -4
7297 16:55:34.209693 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7298 16:55:34.213213 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7299 16:55:34.216340 [-4] AVG Duty = 4922%(X100)
7300 16:55:34.216902
7301 16:55:34.219619 CH0 CLK Duty spec in!! Max-Min= 218%
7302 16:55:34.223145 [DutyScan_Calibration_Flow] ====Done====
7303 16:55:34.223608
7304 16:55:34.226494 [DutyScan_Calibration_Flow] k_type=1
7305 16:55:34.242926
7306 16:55:34.243479 ==DQS 0 ==
7307 16:55:34.245716 Final DQS duty delay cell = 0
7308 16:55:34.249174 [0] MAX Duty = 5249%(X100), DQS PI = 32
7309 16:55:34.253099 [0] MIN Duty = 4969%(X100), DQS PI = 0
7310 16:55:34.255956 [0] AVG Duty = 5109%(X100)
7311 16:55:34.256524
7312 16:55:34.256896 ==DQS 1 ==
7313 16:55:34.258888 Final DQS duty delay cell = -4
7314 16:55:34.262418 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7315 16:55:34.266016 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7316 16:55:34.269020 [-4] AVG Duty = 5000%(X100)
7317 16:55:34.269590
7318 16:55:34.272657 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7319 16:55:34.273227
7320 16:55:34.275412 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7321 16:55:34.279254 [DutyScan_Calibration_Flow] ====Done====
7322 16:55:34.279862
7323 16:55:34.282507 [DutyScan_Calibration_Flow] k_type=3
7324 16:55:34.300291
7325 16:55:34.300852 ==DQM 0 ==
7326 16:55:34.303188 Final DQM duty delay cell = 0
7327 16:55:34.306986 [0] MAX Duty = 5093%(X100), DQS PI = 26
7328 16:55:34.310017 [0] MIN Duty = 4813%(X100), DQS PI = 50
7329 16:55:34.313590 [0] AVG Duty = 4953%(X100)
7330 16:55:34.314146
7331 16:55:34.314663 ==DQM 1 ==
7332 16:55:34.317019 Final DQM duty delay cell = 0
7333 16:55:34.319683 [0] MAX Duty = 5249%(X100), DQS PI = 30
7334 16:55:34.323239 [0] MIN Duty = 5031%(X100), DQS PI = 8
7335 16:55:34.326673 [0] AVG Duty = 5140%(X100)
7336 16:55:34.327231
7337 16:55:34.329746 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7338 16:55:34.330307
7339 16:55:34.332914 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7340 16:55:34.338211 [DutyScan_Calibration_Flow] ====Done====
7341 16:55:34.338810
7342 16:55:34.340017 [DutyScan_Calibration_Flow] k_type=2
7343 16:55:34.357599
7344 16:55:34.358317 ==DQ 0 ==
7345 16:55:34.360532 Final DQ duty delay cell = 0
7346 16:55:34.364147 [0] MAX Duty = 5125%(X100), DQS PI = 10
7347 16:55:34.366888 [0] MIN Duty = 5000%(X100), DQS PI = 0
7348 16:55:34.367354 [0] AVG Duty = 5062%(X100)
7349 16:55:34.370898
7350 16:55:34.371460 ==DQ 1 ==
7351 16:55:34.374039 Final DQ duty delay cell = 0
7352 16:55:34.376862 [0] MAX Duty = 4969%(X100), DQS PI = 42
7353 16:55:34.380384 [0] MIN Duty = 4875%(X100), DQS PI = 10
7354 16:55:34.380851 [0] AVG Duty = 4922%(X100)
7355 16:55:34.384009
7356 16:55:34.387110 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7357 16:55:34.387674
7358 16:55:34.390752 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7359 16:55:34.393169 [DutyScan_Calibration_Flow] ====Done====
7360 16:55:34.393623 ==
7361 16:55:34.396436 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 16:55:34.400167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 16:55:34.400637 ==
7364 16:55:34.403243 [Duty_Offset_Calibration]
7365 16:55:34.403692 B0:0 B1:-1 CA:2
7366 16:55:34.404051
7367 16:55:34.406390 [DutyScan_Calibration_Flow] k_type=0
7368 16:55:34.417513
7369 16:55:34.418064 ==CLK 0==
7370 16:55:34.420631 Final CLK duty delay cell = 0
7371 16:55:34.423979 [0] MAX Duty = 5156%(X100), DQS PI = 10
7372 16:55:34.427602 [0] MIN Duty = 4938%(X100), DQS PI = 46
7373 16:55:34.430523 [0] AVG Duty = 5047%(X100)
7374 16:55:34.430979
7375 16:55:34.433729 CH1 CLK Duty spec in!! Max-Min= 218%
7376 16:55:34.437098 [DutyScan_Calibration_Flow] ====Done====
7377 16:55:34.437551
7378 16:55:34.440461 [DutyScan_Calibration_Flow] k_type=1
7379 16:55:34.457365
7380 16:55:34.457905 ==DQS 0 ==
7381 16:55:34.460674 Final DQS duty delay cell = 0
7382 16:55:34.463627 [0] MAX Duty = 5124%(X100), DQS PI = 26
7383 16:55:34.467113 [0] MIN Duty = 4969%(X100), DQS PI = 0
7384 16:55:34.470104 [0] AVG Duty = 5046%(X100)
7385 16:55:34.470668
7386 16:55:34.471031 ==DQS 1 ==
7387 16:55:34.473396 Final DQS duty delay cell = 0
7388 16:55:34.477106 [0] MAX Duty = 5187%(X100), DQS PI = 0
7389 16:55:34.480552 [0] MIN Duty = 4844%(X100), DQS PI = 34
7390 16:55:34.483778 [0] AVG Duty = 5015%(X100)
7391 16:55:34.484334
7392 16:55:34.486883 CH1 DQS 0 Duty spec in!! Max-Min= 155%
7393 16:55:34.487338
7394 16:55:34.490185 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7395 16:55:34.493434 [DutyScan_Calibration_Flow] ====Done====
7396 16:55:34.493987
7397 16:55:34.496950 [DutyScan_Calibration_Flow] k_type=3
7398 16:55:34.514624
7399 16:55:34.515225 ==DQM 0 ==
7400 16:55:34.518569 Final DQM duty delay cell = 4
7401 16:55:34.521476 [4] MAX Duty = 5125%(X100), DQS PI = 8
7402 16:55:34.525032 [4] MIN Duty = 5000%(X100), DQS PI = 30
7403 16:55:34.527879 [4] AVG Duty = 5062%(X100)
7404 16:55:34.528436
7405 16:55:34.528796 ==DQM 1 ==
7406 16:55:34.531354 Final DQM duty delay cell = 0
7407 16:55:34.534915 [0] MAX Duty = 5281%(X100), DQS PI = 58
7408 16:55:34.538100 [0] MIN Duty = 4876%(X100), DQS PI = 34
7409 16:55:34.540983 [0] AVG Duty = 5078%(X100)
7410 16:55:34.541540
7411 16:55:34.544714 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7412 16:55:34.545179
7413 16:55:34.547821 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7414 16:55:34.551178 [DutyScan_Calibration_Flow] ====Done====
7415 16:55:34.551741
7416 16:55:34.554178 [DutyScan_Calibration_Flow] k_type=2
7417 16:55:34.572230
7418 16:55:34.572823 ==DQ 0 ==
7419 16:55:34.575828 Final DQ duty delay cell = 0
7420 16:55:34.578212 [0] MAX Duty = 5093%(X100), DQS PI = 22
7421 16:55:34.581730 [0] MIN Duty = 4969%(X100), DQS PI = 46
7422 16:55:34.582300 [0] AVG Duty = 5031%(X100)
7423 16:55:34.585363
7424 16:55:34.585924 ==DQ 1 ==
7425 16:55:34.588190 Final DQ duty delay cell = 0
7426 16:55:34.591363 [0] MAX Duty = 5062%(X100), DQS PI = 0
7427 16:55:34.594931 [0] MIN Duty = 4844%(X100), DQS PI = 30
7428 16:55:34.595578 [0] AVG Duty = 4953%(X100)
7429 16:55:34.596113
7430 16:55:34.601162 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7431 16:55:34.601721
7432 16:55:34.604457 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7433 16:55:34.607748 [DutyScan_Calibration_Flow] ====Done====
7434 16:55:34.611053 nWR fixed to 30
7435 16:55:34.611522 [ModeRegInit_LP4] CH0 RK0
7436 16:55:34.614409 [ModeRegInit_LP4] CH0 RK1
7437 16:55:34.617986 [ModeRegInit_LP4] CH1 RK0
7438 16:55:34.621446 [ModeRegInit_LP4] CH1 RK1
7439 16:55:34.621911 match AC timing 5
7440 16:55:34.627977 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 16:55:34.631057 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 16:55:34.635284 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 16:55:34.641526 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 16:55:34.644618 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 16:55:34.645191 [MiockJmeterHQA]
7446 16:55:34.645565
7447 16:55:34.647744 [DramcMiockJmeter] u1RxGatingPI = 0
7448 16:55:34.651269 0 : 4252, 4027
7449 16:55:34.651845 4 : 4252, 4027
7450 16:55:34.654334 8 : 4252, 4027
7451 16:55:34.654941 12 : 4253, 4027
7452 16:55:34.655320 16 : 4252, 4027
7453 16:55:34.657571 20 : 4253, 4027
7454 16:55:34.658040 24 : 4252, 4027
7455 16:55:34.661205 28 : 4365, 4140
7456 16:55:34.661688 32 : 4252, 4026
7457 16:55:34.663998 36 : 4255, 4030
7458 16:55:34.664418 40 : 4252, 4027
7459 16:55:34.667528 44 : 4363, 4138
7460 16:55:34.668060 48 : 4253, 4027
7461 16:55:34.668439 52 : 4365, 4140
7462 16:55:34.670736 56 : 4253, 4026
7463 16:55:34.671208 60 : 4252, 4027
7464 16:55:34.674203 64 : 4250, 4027
7465 16:55:34.674700 68 : 4255, 4029
7466 16:55:34.677313 72 : 4361, 4138
7467 16:55:34.677785 76 : 4252, 4029
7468 16:55:34.680429 80 : 4361, 4137
7469 16:55:34.680901 84 : 4250, 4026
7470 16:55:34.681274 88 : 4250, 3799
7471 16:55:34.683777 92 : 4250, 0
7472 16:55:34.684405 96 : 4363, 0
7473 16:55:34.687579 100 : 4360, 0
7474 16:55:34.688204 104 : 4363, 0
7475 16:55:34.688586 108 : 4253, 0
7476 16:55:34.690701 112 : 4250, 0
7477 16:55:34.691174 116 : 4252, 0
7478 16:55:34.693920 120 : 4250, 0
7479 16:55:34.694542 124 : 4250, 0
7480 16:55:34.694929 128 : 4252, 0
7481 16:55:34.696994 132 : 4363, 0
7482 16:55:34.697569 136 : 4360, 0
7483 16:55:34.698001 140 : 4363, 0
7484 16:55:34.700683 144 : 4255, 0
7485 16:55:34.701264 148 : 4253, 0
7486 16:55:34.703602 152 : 4250, 0
7487 16:55:34.704075 156 : 4252, 0
7488 16:55:34.704449 160 : 4250, 0
7489 16:55:34.706756 164 : 4250, 0
7490 16:55:34.707227 168 : 4252, 0
7491 16:55:34.710524 172 : 4253, 0
7492 16:55:34.711097 176 : 4250, 0
7493 16:55:34.711480 180 : 4252, 0
7494 16:55:34.713748 184 : 4365, 0
7495 16:55:34.714222 188 : 4360, 0
7496 16:55:34.716728 192 : 4363, 0
7497 16:55:34.717316 196 : 4252, 0
7498 16:55:34.717702 200 : 4253, 4
7499 16:55:34.719997 204 : 4250, 2219
7500 16:55:34.720473 208 : 4250, 4027
7501 16:55:34.723644 212 : 4361, 4137
7502 16:55:34.724223 216 : 4361, 4138
7503 16:55:34.726679 220 : 4250, 4027
7504 16:55:34.727152 224 : 4363, 4140
7505 16:55:34.730016 228 : 4249, 4027
7506 16:55:34.730508 232 : 4250, 4027
7507 16:55:34.733196 236 : 4250, 4027
7508 16:55:34.733667 240 : 4252, 4029
7509 16:55:34.736977 244 : 4250, 4027
7510 16:55:34.737549 248 : 4250, 4027
7511 16:55:34.737930 252 : 4250, 4027
7512 16:55:34.740203 256 : 4252, 4030
7513 16:55:34.740783 260 : 4250, 4027
7514 16:55:34.743587 264 : 4361, 4137
7515 16:55:34.744161 268 : 4361, 4138
7516 16:55:34.746904 272 : 4250, 4027
7517 16:55:34.747375 276 : 4363, 4140
7518 16:55:34.749775 280 : 4250, 4027
7519 16:55:34.750243 284 : 4250, 4026
7520 16:55:34.753078 288 : 4250, 4027
7521 16:55:34.753553 292 : 4252, 4029
7522 16:55:34.756683 296 : 4250, 4027
7523 16:55:34.757260 300 : 4250, 4027
7524 16:55:34.759883 304 : 4250, 4027
7525 16:55:34.760463 308 : 4252, 4029
7526 16:55:34.760844 312 : 4250, 3979
7527 16:55:34.762959 316 : 4361, 2202
7528 16:55:34.763433 320 : 4361, 26
7529 16:55:34.763812
7530 16:55:34.766535 MIOCK jitter meter ch=0
7531 16:55:34.767006
7532 16:55:34.769819 1T = (320-92) = 228 dly cells
7533 16:55:34.776071 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7534 16:55:34.776671 ==
7535 16:55:34.779446 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 16:55:34.782637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 16:55:34.783106 ==
7538 16:55:34.789398 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 16:55:34.792803 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 16:55:34.796676 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 16:55:34.803014 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 16:55:34.812287 [CA 0] Center 42 (12~73) winsize 62
7543 16:55:34.815052 [CA 1] Center 42 (12~72) winsize 61
7544 16:55:34.818522 [CA 2] Center 37 (7~67) winsize 61
7545 16:55:34.821743 [CA 3] Center 37 (7~67) winsize 61
7546 16:55:34.824876 [CA 4] Center 36 (6~66) winsize 61
7547 16:55:34.828362 [CA 5] Center 35 (5~65) winsize 61
7548 16:55:34.828931
7549 16:55:34.831191 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7550 16:55:34.831657
7551 16:55:34.838127 [CATrainingPosCal] consider 1 rank data
7552 16:55:34.838788 u2DelayCellTimex100 = 285/100 ps
7553 16:55:34.845212 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7554 16:55:34.848020 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7555 16:55:34.851473 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7556 16:55:34.854969 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7557 16:55:34.858099 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 16:55:34.861291 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7559 16:55:34.861839
7560 16:55:34.864989 CA PerBit enable=1, Macro0, CA PI delay=35
7561 16:55:34.865563
7562 16:55:34.867968 [CBTSetCACLKResult] CA Dly = 35
7563 16:55:34.870900 CS Dly: 9 (0~40)
7564 16:55:34.874105 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 16:55:34.877747 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 16:55:34.878315 ==
7567 16:55:34.880991 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 16:55:34.887500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 16:55:34.888205 ==
7570 16:55:34.890696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 16:55:34.897361 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 16:55:34.900564 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 16:55:34.907288 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 16:55:34.915211 [CA 0] Center 43 (13~74) winsize 62
7575 16:55:34.918428 [CA 1] Center 43 (13~73) winsize 61
7576 16:55:34.922002 [CA 2] Center 38 (9~68) winsize 60
7577 16:55:34.924753 [CA 3] Center 38 (9~68) winsize 60
7578 16:55:34.928746 [CA 4] Center 37 (7~67) winsize 61
7579 16:55:34.931382 [CA 5] Center 36 (6~66) winsize 61
7580 16:55:34.931859
7581 16:55:34.934566 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 16:55:34.935041
7583 16:55:34.938111 [CATrainingPosCal] consider 2 rank data
7584 16:55:34.941394 u2DelayCellTimex100 = 285/100 ps
7585 16:55:34.948054 CA0 delay=43 (13~73),Diff = 8 PI (27 cell)
7586 16:55:34.951430 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7587 16:55:34.955016 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7588 16:55:34.957901 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7589 16:55:34.961346 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7590 16:55:34.964309 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7591 16:55:34.964788
7592 16:55:34.967815 CA PerBit enable=1, Macro0, CA PI delay=35
7593 16:55:34.968397
7594 16:55:34.971996 [CBTSetCACLKResult] CA Dly = 35
7595 16:55:34.974254 CS Dly: 10 (0~43)
7596 16:55:34.978057 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 16:55:34.980969 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 16:55:34.981630
7599 16:55:34.984218 ----->DramcWriteLeveling(PI) begin...
7600 16:55:34.984848 ==
7601 16:55:34.987632 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 16:55:34.994202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 16:55:34.994843 ==
7604 16:55:34.997255 Write leveling (Byte 0): 38 => 38
7605 16:55:35.001124 Write leveling (Byte 1): 31 => 31
7606 16:55:35.003948 DramcWriteLeveling(PI) end<-----
7607 16:55:35.004430
7608 16:55:35.004809 ==
7609 16:55:35.007284 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 16:55:35.010580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 16:55:35.011362 ==
7612 16:55:35.013612 [Gating] SW mode calibration
7613 16:55:35.020540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 16:55:35.027201 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 16:55:35.030619 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 16:55:35.033353 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 16:55:35.040862 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7618 16:55:35.044314 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7619 16:55:35.047043 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7620 16:55:35.053609 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7621 16:55:35.056935 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7622 16:55:35.060191 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 16:55:35.066649 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7624 16:55:35.070406 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7625 16:55:35.073396 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7626 16:55:35.080031 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7627 16:55:35.082990 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
7628 16:55:35.086832 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
7629 16:55:35.093409 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 16:55:35.096686 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7631 16:55:35.100253 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7632 16:55:35.102937 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7633 16:55:35.109469 1 6 8 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7634 16:55:35.112916 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7635 16:55:35.116263 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7636 16:55:35.122672 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7637 16:55:35.126734 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 16:55:35.129462 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 16:55:35.136493 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 16:55:35.139597 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 16:55:35.142448 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 16:55:35.149373 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 16:55:35.152838 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7644 16:55:35.156355 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 16:55:35.162502 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 16:55:35.165649 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 16:55:35.168997 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:55:35.175606 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:55:35.178698 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:55:35.182613 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 16:55:35.188970 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 16:55:35.191784 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 16:55:35.195376 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 16:55:35.201963 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 16:55:35.205837 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 16:55:35.208471 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 16:55:35.215721 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 16:55:35.218371 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 16:55:35.221750 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 16:55:35.225527 Total UI for P1: 0, mck2ui 16
7661 16:55:35.228447 best dqsien dly found for B0: ( 1, 9, 10)
7662 16:55:35.234705 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7663 16:55:35.238204 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 16:55:35.241558 Total UI for P1: 0, mck2ui 16
7665 16:55:35.244963 best dqsien dly found for B1: ( 1, 9, 18)
7666 16:55:35.249296 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7667 16:55:35.252121 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7668 16:55:35.252690
7669 16:55:35.254978 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7670 16:55:35.261623 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7671 16:55:35.262194 [Gating] SW calibration Done
7672 16:55:35.262613 ==
7673 16:55:35.265072 Dram Type= 6, Freq= 0, CH_0, rank 0
7674 16:55:35.271824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7675 16:55:35.272413 ==
7676 16:55:35.272795 RX Vref Scan: 0
7677 16:55:35.273144
7678 16:55:35.274805 RX Vref 0 -> 0, step: 1
7679 16:55:35.275278
7680 16:55:35.277879 RX Delay 0 -> 252, step: 8
7681 16:55:35.281177 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7682 16:55:35.285205 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7683 16:55:35.288199 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7684 16:55:35.291435 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7685 16:55:35.297752 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7686 16:55:35.301482 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7687 16:55:35.304422 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7688 16:55:35.307513 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7689 16:55:35.310577 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7690 16:55:35.317878 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7691 16:55:35.320794 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7692 16:55:35.324325 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7693 16:55:35.327514 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7694 16:55:35.334285 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7695 16:55:35.337697 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7696 16:55:35.340622 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7697 16:55:35.341190 ==
7698 16:55:35.343693 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 16:55:35.347005 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 16:55:35.347483 ==
7701 16:55:35.350704 DQS Delay:
7702 16:55:35.351267 DQS0 = 0, DQS1 = 0
7703 16:55:35.353895 DQM Delay:
7704 16:55:35.354486 DQM0 = 138, DQM1 = 126
7705 16:55:35.354867 DQ Delay:
7706 16:55:35.360520 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7707 16:55:35.364025 DQ4 =139, DQ5 =127, DQ6 =147, DQ7 =147
7708 16:55:35.367038 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7709 16:55:35.370329 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7710 16:55:35.370837
7711 16:55:35.371217
7712 16:55:35.371562 ==
7713 16:55:35.373555 Dram Type= 6, Freq= 0, CH_0, rank 0
7714 16:55:35.377029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7715 16:55:35.377601 ==
7716 16:55:35.377984
7717 16:55:35.378332
7718 16:55:35.380258 TX Vref Scan disable
7719 16:55:35.383713 == TX Byte 0 ==
7720 16:55:35.386569 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7721 16:55:35.390211 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7722 16:55:35.393925 == TX Byte 1 ==
7723 16:55:35.396740 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7724 16:55:35.400301 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7725 16:55:35.400871 ==
7726 16:55:35.403478 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 16:55:35.410344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 16:55:35.410948 ==
7729 16:55:35.422161
7730 16:55:35.425611 TX Vref early break, caculate TX vref
7731 16:55:35.428848 TX Vref=16, minBit 12, minWin=22, winSum=375
7732 16:55:35.432121 TX Vref=18, minBit 11, minWin=23, winSum=389
7733 16:55:35.435138 TX Vref=20, minBit 0, minWin=24, winSum=394
7734 16:55:35.438346 TX Vref=22, minBit 4, minWin=24, winSum=410
7735 16:55:35.445275 TX Vref=24, minBit 4, minWin=25, winSum=420
7736 16:55:35.447935 TX Vref=26, minBit 1, minWin=26, winSum=427
7737 16:55:35.452054 TX Vref=28, minBit 4, minWin=25, winSum=429
7738 16:55:35.455083 TX Vref=30, minBit 6, minWin=25, winSum=419
7739 16:55:35.458188 TX Vref=32, minBit 0, minWin=25, winSum=411
7740 16:55:35.461623 TX Vref=34, minBit 4, minWin=24, winSum=397
7741 16:55:35.467785 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26
7742 16:55:35.468266
7743 16:55:35.471884 Final TX Range 0 Vref 26
7744 16:55:35.472455
7745 16:55:35.472833 ==
7746 16:55:35.474908 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 16:55:35.478197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 16:55:35.478722 ==
7749 16:55:35.479101
7750 16:55:35.479447
7751 16:55:35.481641 TX Vref Scan disable
7752 16:55:35.487813 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7753 16:55:35.488386 == TX Byte 0 ==
7754 16:55:35.491283 u2DelayCellOfst[0]=13 cells (4 PI)
7755 16:55:35.494392 u2DelayCellOfst[1]=20 cells (6 PI)
7756 16:55:35.498091 u2DelayCellOfst[2]=13 cells (4 PI)
7757 16:55:35.501265 u2DelayCellOfst[3]=13 cells (4 PI)
7758 16:55:35.504385 u2DelayCellOfst[4]=10 cells (3 PI)
7759 16:55:35.507189 u2DelayCellOfst[5]=0 cells (0 PI)
7760 16:55:35.510792 u2DelayCellOfst[6]=20 cells (6 PI)
7761 16:55:35.514059 u2DelayCellOfst[7]=17 cells (5 PI)
7762 16:55:35.517084 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7763 16:55:35.520495 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7764 16:55:35.523802 == TX Byte 1 ==
7765 16:55:35.527407 u2DelayCellOfst[8]=0 cells (0 PI)
7766 16:55:35.530491 u2DelayCellOfst[9]=0 cells (0 PI)
7767 16:55:35.533800 u2DelayCellOfst[10]=6 cells (2 PI)
7768 16:55:35.537295 u2DelayCellOfst[11]=3 cells (1 PI)
7769 16:55:35.541114 u2DelayCellOfst[12]=10 cells (3 PI)
7770 16:55:35.543548 u2DelayCellOfst[13]=10 cells (3 PI)
7771 16:55:35.544029 u2DelayCellOfst[14]=13 cells (4 PI)
7772 16:55:35.546979 u2DelayCellOfst[15]=10 cells (3 PI)
7773 16:55:35.553843 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7774 16:55:35.557275 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7775 16:55:35.560006 DramC Write-DBI on
7776 16:55:35.560493 ==
7777 16:55:35.563682 Dram Type= 6, Freq= 0, CH_0, rank 0
7778 16:55:35.566487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7779 16:55:35.566975 ==
7780 16:55:35.567348
7781 16:55:35.567690
7782 16:55:35.569927 TX Vref Scan disable
7783 16:55:35.570423 == TX Byte 0 ==
7784 16:55:35.576593 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7785 16:55:35.577182 == TX Byte 1 ==
7786 16:55:35.583266 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7787 16:55:35.583848 DramC Write-DBI off
7788 16:55:35.584227
7789 16:55:35.584570 [DATLAT]
7790 16:55:35.586417 Freq=1600, CH0 RK0
7791 16:55:35.586891
7792 16:55:35.587263 DATLAT Default: 0xf
7793 16:55:35.589886 0, 0xFFFF, sum = 0
7794 16:55:35.592938 1, 0xFFFF, sum = 0
7795 16:55:35.593416 2, 0xFFFF, sum = 0
7796 16:55:35.596418 3, 0xFFFF, sum = 0
7797 16:55:35.596999 4, 0xFFFF, sum = 0
7798 16:55:35.600099 5, 0xFFFF, sum = 0
7799 16:55:35.600683 6, 0xFFFF, sum = 0
7800 16:55:35.603008 7, 0xFFFF, sum = 0
7801 16:55:35.603488 8, 0xFFFF, sum = 0
7802 16:55:35.607058 9, 0xFFFF, sum = 0
7803 16:55:35.607639 10, 0xFFFF, sum = 0
7804 16:55:35.609504 11, 0xFFFF, sum = 0
7805 16:55:35.609982 12, 0xFFFF, sum = 0
7806 16:55:35.613201 13, 0xFFFF, sum = 0
7807 16:55:35.613784 14, 0x0, sum = 1
7808 16:55:35.616719 15, 0x0, sum = 2
7809 16:55:35.617306 16, 0x0, sum = 3
7810 16:55:35.619439 17, 0x0, sum = 4
7811 16:55:35.620030 best_step = 15
7812 16:55:35.620411
7813 16:55:35.620759 ==
7814 16:55:35.622946 Dram Type= 6, Freq= 0, CH_0, rank 0
7815 16:55:35.629638 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7816 16:55:35.630220 ==
7817 16:55:35.630662 RX Vref Scan: 1
7818 16:55:35.631018
7819 16:55:35.632448 Set Vref Range= 24 -> 127
7820 16:55:35.632919
7821 16:55:35.636133 RX Vref 24 -> 127, step: 1
7822 16:55:35.636629
7823 16:55:35.637007 RX Delay 19 -> 252, step: 4
7824 16:55:35.639153
7825 16:55:35.639618 Set Vref, RX VrefLevel [Byte0]: 24
7826 16:55:35.642476 [Byte1]: 24
7827 16:55:35.646748
7828 16:55:35.647217 Set Vref, RX VrefLevel [Byte0]: 25
7829 16:55:35.649963 [Byte1]: 25
7830 16:55:35.654632
7831 16:55:35.655197 Set Vref, RX VrefLevel [Byte0]: 26
7832 16:55:35.657615 [Byte1]: 26
7833 16:55:35.661837
7834 16:55:35.662424 Set Vref, RX VrefLevel [Byte0]: 27
7835 16:55:35.665687 [Byte1]: 27
7836 16:55:35.669561
7837 16:55:35.670120 Set Vref, RX VrefLevel [Byte0]: 28
7838 16:55:35.673369 [Byte1]: 28
7839 16:55:35.677282
7840 16:55:35.677848 Set Vref, RX VrefLevel [Byte0]: 29
7841 16:55:35.680521 [Byte1]: 29
7842 16:55:35.685746
7843 16:55:35.686309 Set Vref, RX VrefLevel [Byte0]: 30
7844 16:55:35.687896 [Byte1]: 30
7845 16:55:35.692210
7846 16:55:35.692960 Set Vref, RX VrefLevel [Byte0]: 31
7847 16:55:35.695555 [Byte1]: 31
7848 16:55:35.699606
7849 16:55:35.700073 Set Vref, RX VrefLevel [Byte0]: 32
7850 16:55:35.703129 [Byte1]: 32
7851 16:55:35.707656
7852 16:55:35.708331 Set Vref, RX VrefLevel [Byte0]: 33
7853 16:55:35.710659 [Byte1]: 33
7854 16:55:35.715311
7855 16:55:35.715873 Set Vref, RX VrefLevel [Byte0]: 34
7856 16:55:35.718189 [Byte1]: 34
7857 16:55:35.722520
7858 16:55:35.723104 Set Vref, RX VrefLevel [Byte0]: 35
7859 16:55:35.725862 [Byte1]: 35
7860 16:55:35.730458
7861 16:55:35.731029 Set Vref, RX VrefLevel [Byte0]: 36
7862 16:55:35.733152 [Byte1]: 36
7863 16:55:35.737556
7864 16:55:35.738182 Set Vref, RX VrefLevel [Byte0]: 37
7865 16:55:35.740979 [Byte1]: 37
7866 16:55:35.745074
7867 16:55:35.745547 Set Vref, RX VrefLevel [Byte0]: 38
7868 16:55:35.748496 [Byte1]: 38
7869 16:55:35.752788
7870 16:55:35.753347 Set Vref, RX VrefLevel [Byte0]: 39
7871 16:55:35.756219 [Byte1]: 39
7872 16:55:35.760244
7873 16:55:35.760712 Set Vref, RX VrefLevel [Byte0]: 40
7874 16:55:35.763784 [Byte1]: 40
7875 16:55:35.768008
7876 16:55:35.768483 Set Vref, RX VrefLevel [Byte0]: 41
7877 16:55:35.771169 [Byte1]: 41
7878 16:55:35.775618
7879 16:55:35.776086 Set Vref, RX VrefLevel [Byte0]: 42
7880 16:55:35.778758 [Byte1]: 42
7881 16:55:35.782808
7882 16:55:35.783278 Set Vref, RX VrefLevel [Byte0]: 43
7883 16:55:35.786815 [Byte1]: 43
7884 16:55:35.790630
7885 16:55:35.791123 Set Vref, RX VrefLevel [Byte0]: 44
7886 16:55:35.793981 [Byte1]: 44
7887 16:55:35.798906
7888 16:55:35.799478 Set Vref, RX VrefLevel [Byte0]: 45
7889 16:55:35.801954 [Byte1]: 45
7890 16:55:35.805840
7891 16:55:35.806310 Set Vref, RX VrefLevel [Byte0]: 46
7892 16:55:35.809017 [Byte1]: 46
7893 16:55:35.813754
7894 16:55:35.814317 Set Vref, RX VrefLevel [Byte0]: 47
7895 16:55:35.817035 [Byte1]: 47
7896 16:55:35.821049
7897 16:55:35.821615 Set Vref, RX VrefLevel [Byte0]: 48
7898 16:55:35.824127 [Byte1]: 48
7899 16:55:35.828731
7900 16:55:35.829293 Set Vref, RX VrefLevel [Byte0]: 49
7901 16:55:35.831947 [Byte1]: 49
7902 16:55:35.836196
7903 16:55:35.836759 Set Vref, RX VrefLevel [Byte0]: 50
7904 16:55:35.839361 [Byte1]: 50
7905 16:55:35.843564
7906 16:55:35.844135 Set Vref, RX VrefLevel [Byte0]: 51
7907 16:55:35.846867 [Byte1]: 51
7908 16:55:35.852088
7909 16:55:35.852655 Set Vref, RX VrefLevel [Byte0]: 52
7910 16:55:35.854337 [Byte1]: 52
7911 16:55:35.858882
7912 16:55:35.859456 Set Vref, RX VrefLevel [Byte0]: 53
7913 16:55:35.862118 [Byte1]: 53
7914 16:55:35.866184
7915 16:55:35.866694 Set Vref, RX VrefLevel [Byte0]: 54
7916 16:55:35.869716 [Byte1]: 54
7917 16:55:35.873896
7918 16:55:35.874496 Set Vref, RX VrefLevel [Byte0]: 55
7919 16:55:35.877162 [Byte1]: 55
7920 16:55:35.881709
7921 16:55:35.882278 Set Vref, RX VrefLevel [Byte0]: 56
7922 16:55:35.885234 [Byte1]: 56
7923 16:55:35.889448
7924 16:55:35.890011 Set Vref, RX VrefLevel [Byte0]: 57
7925 16:55:35.892298 [Byte1]: 57
7926 16:55:35.897215
7927 16:55:35.897777 Set Vref, RX VrefLevel [Byte0]: 58
7928 16:55:35.900252 [Byte1]: 58
7929 16:55:35.905559
7930 16:55:35.906126 Set Vref, RX VrefLevel [Byte0]: 59
7931 16:55:35.907831 [Byte1]: 59
7932 16:55:35.912340
7933 16:55:35.912903 Set Vref, RX VrefLevel [Byte0]: 60
7934 16:55:35.914860 [Byte1]: 60
7935 16:55:35.919994
7936 16:55:35.920559 Set Vref, RX VrefLevel [Byte0]: 61
7937 16:55:35.922846 [Byte1]: 61
7938 16:55:35.927271
7939 16:55:35.929883 Set Vref, RX VrefLevel [Byte0]: 62
7940 16:55:35.934344 [Byte1]: 62
7941 16:55:35.934845
7942 16:55:35.937374 Set Vref, RX VrefLevel [Byte0]: 63
7943 16:55:35.940493 [Byte1]: 63
7944 16:55:35.941064
7945 16:55:35.943804 Set Vref, RX VrefLevel [Byte0]: 64
7946 16:55:35.946735 [Byte1]: 64
7947 16:55:35.947381
7948 16:55:35.949781 Set Vref, RX VrefLevel [Byte0]: 65
7949 16:55:35.953008 [Byte1]: 65
7950 16:55:35.956988
7951 16:55:35.957456 Set Vref, RX VrefLevel [Byte0]: 66
7952 16:55:35.960661 [Byte1]: 66
7953 16:55:35.964903
7954 16:55:35.965462 Set Vref, RX VrefLevel [Byte0]: 67
7955 16:55:35.967764 [Byte1]: 67
7956 16:55:35.972138
7957 16:55:35.972606 Set Vref, RX VrefLevel [Byte0]: 68
7958 16:55:35.975471 [Byte1]: 68
7959 16:55:35.979889
7960 16:55:35.980458 Set Vref, RX VrefLevel [Byte0]: 69
7961 16:55:35.983204 [Byte1]: 69
7962 16:55:35.987408
7963 16:55:35.987972 Set Vref, RX VrefLevel [Byte0]: 70
7964 16:55:35.990559 [Byte1]: 70
7965 16:55:35.994953
7966 16:55:35.995419 Set Vref, RX VrefLevel [Byte0]: 71
7967 16:55:35.998488 [Byte1]: 71
7968 16:55:36.002312
7969 16:55:36.002812 Set Vref, RX VrefLevel [Byte0]: 72
7970 16:55:36.006267 [Byte1]: 72
7971 16:55:36.010299
7972 16:55:36.010823 Set Vref, RX VrefLevel [Byte0]: 73
7973 16:55:36.013745 [Byte1]: 73
7974 16:55:36.017807
7975 16:55:36.018339 Set Vref, RX VrefLevel [Byte0]: 74
7976 16:55:36.021399 [Byte1]: 74
7977 16:55:36.025770
7978 16:55:36.026242 Set Vref, RX VrefLevel [Byte0]: 75
7979 16:55:36.028798 [Byte1]: 75
7980 16:55:36.033115
7981 16:55:36.033588 Set Vref, RX VrefLevel [Byte0]: 76
7982 16:55:36.036282 [Byte1]: 76
7983 16:55:36.041203
7984 16:55:36.041764 Final RX Vref Byte 0 = 59 to rank0
7985 16:55:36.044202 Final RX Vref Byte 1 = 62 to rank0
7986 16:55:36.047071 Final RX Vref Byte 0 = 59 to rank1
7987 16:55:36.050798 Final RX Vref Byte 1 = 62 to rank1==
7988 16:55:36.054008 Dram Type= 6, Freq= 0, CH_0, rank 0
7989 16:55:36.060543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7990 16:55:36.061287 ==
7991 16:55:36.061686 DQS Delay:
7992 16:55:36.063240 DQS0 = 0, DQS1 = 0
7993 16:55:36.063713 DQM Delay:
7994 16:55:36.066468 DQM0 = 136, DQM1 = 123
7995 16:55:36.066935 DQ Delay:
7996 16:55:36.070042 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =134
7997 16:55:36.073711 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =144
7998 16:55:36.076599 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7999 16:55:36.079868 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8000 16:55:36.080340
8001 16:55:36.080717
8002 16:55:36.081059
8003 16:55:36.083970 [DramC_TX_OE_Calibration] TA2
8004 16:55:36.086757 Original DQ_B0 (3 6) =30, OEN = 27
8005 16:55:36.089872 Original DQ_B1 (3 6) =30, OEN = 27
8006 16:55:36.093893 24, 0x0, End_B0=24 End_B1=24
8007 16:55:36.096896 25, 0x0, End_B0=25 End_B1=25
8008 16:55:36.097473 26, 0x0, End_B0=26 End_B1=26
8009 16:55:36.099931 27, 0x0, End_B0=27 End_B1=27
8010 16:55:36.103222 28, 0x0, End_B0=28 End_B1=28
8011 16:55:36.106506 29, 0x0, End_B0=29 End_B1=29
8012 16:55:36.107083 30, 0x0, End_B0=30 End_B1=30
8013 16:55:36.109566 31, 0x4141, End_B0=30 End_B1=30
8014 16:55:36.112839 Byte0 end_step=30 best_step=27
8015 16:55:36.116268 Byte1 end_step=30 best_step=27
8016 16:55:36.119319 Byte0 TX OE(2T, 0.5T) = (3, 3)
8017 16:55:36.122956 Byte1 TX OE(2T, 0.5T) = (3, 3)
8018 16:55:36.123521
8019 16:55:36.123913
8020 16:55:36.130150 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
8021 16:55:36.132927 CH0 RK0: MR19=303, MR18=1F1D
8022 16:55:36.139269 CH0_RK0: MR19=0x303, MR18=0x1F1D, DQSOSC=394, MR23=63, INC=23, DEC=15
8023 16:55:36.139843
8024 16:55:36.142886 ----->DramcWriteLeveling(PI) begin...
8025 16:55:36.143364 ==
8026 16:55:36.146427 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 16:55:36.149284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 16:55:36.149759 ==
8029 16:55:36.152899 Write leveling (Byte 0): 39 => 39
8030 16:55:36.156019 Write leveling (Byte 1): 29 => 29
8031 16:55:36.159801 DramcWriteLeveling(PI) end<-----
8032 16:55:36.160369
8033 16:55:36.160743 ==
8034 16:55:36.162503 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 16:55:36.168957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 16:55:36.169752 ==
8037 16:55:36.170164 [Gating] SW mode calibration
8038 16:55:36.178955 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8039 16:55:36.182571 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8040 16:55:36.185972 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 16:55:36.192040 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 16:55:36.195918 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8043 16:55:36.198577 1 4 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (1 1)
8044 16:55:36.205461 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8045 16:55:36.209072 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8046 16:55:36.212443 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8047 16:55:36.218806 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8048 16:55:36.222556 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8049 16:55:36.225128 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8050 16:55:36.232195 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8051 16:55:36.235292 1 5 12 | B1->B0 | 3333 2828 | 1 1 | (1 1) (1 0)
8052 16:55:36.238473 1 5 16 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
8053 16:55:36.245195 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8054 16:55:36.248285 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8055 16:55:36.252671 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8056 16:55:36.258512 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 16:55:36.261364 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8058 16:55:36.264968 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8059 16:55:36.271707 1 6 12 | B1->B0 | 2a2a 4343 | 0 0 | (0 0) (0 0)
8060 16:55:36.274911 1 6 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
8061 16:55:36.278628 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8062 16:55:36.284607 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8063 16:55:36.287963 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 16:55:36.291485 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8065 16:55:36.297966 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8066 16:55:36.301349 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 16:55:36.304181 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8068 16:55:36.310912 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8069 16:55:36.314743 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 16:55:36.317965 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 16:55:36.324417 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 16:55:36.327902 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 16:55:36.331011 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 16:55:36.337664 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 16:55:36.341043 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 16:55:36.344226 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 16:55:36.350808 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 16:55:36.354158 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 16:55:36.357356 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 16:55:36.363855 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 16:55:36.367095 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 16:55:36.370245 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8083 16:55:36.377129 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8084 16:55:36.380524 Total UI for P1: 0, mck2ui 16
8085 16:55:36.383404 best dqsien dly found for B0: ( 1, 9, 8)
8086 16:55:36.386906 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8087 16:55:36.390759 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 16:55:36.393363 Total UI for P1: 0, mck2ui 16
8089 16:55:36.396689 best dqsien dly found for B1: ( 1, 9, 14)
8090 16:55:36.400348 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8091 16:55:36.403752 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8092 16:55:36.404313
8093 16:55:36.409828 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8094 16:55:36.413153 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8095 16:55:36.416739 [Gating] SW calibration Done
8096 16:55:36.417319 ==
8097 16:55:36.420197 Dram Type= 6, Freq= 0, CH_0, rank 1
8098 16:55:36.423198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8099 16:55:36.423808 ==
8100 16:55:36.424295 RX Vref Scan: 0
8101 16:55:36.424750
8102 16:55:36.426432 RX Vref 0 -> 0, step: 1
8103 16:55:36.426930
8104 16:55:36.429559 RX Delay 0 -> 252, step: 8
8105 16:55:36.433072 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8106 16:55:36.436131 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8107 16:55:36.443296 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8108 16:55:36.446107 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8109 16:55:36.449953 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8110 16:55:36.452763 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8111 16:55:36.456017 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8112 16:55:36.462804 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8113 16:55:36.466090 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8114 16:55:36.469772 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8115 16:55:36.472841 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8116 16:55:36.476236 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8117 16:55:36.482388 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8118 16:55:36.485621 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8119 16:55:36.488804 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8120 16:55:36.492611 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8121 16:55:36.495601 ==
8122 16:55:36.496075 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 16:55:36.502007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 16:55:36.502513 ==
8125 16:55:36.502906 DQS Delay:
8126 16:55:36.505212 DQS0 = 0, DQS1 = 0
8127 16:55:36.505702 DQM Delay:
8128 16:55:36.508583 DQM0 = 136, DQM1 = 124
8129 16:55:36.509058 DQ Delay:
8130 16:55:36.511974 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8131 16:55:36.515154 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8132 16:55:36.518700 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8133 16:55:36.522598 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8134 16:55:36.523269
8135 16:55:36.523660
8136 16:55:36.524011 ==
8137 16:55:36.525055 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 16:55:36.531509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 16:55:36.532093 ==
8140 16:55:36.532481
8141 16:55:36.532838
8142 16:55:36.533175 TX Vref Scan disable
8143 16:55:36.535616 == TX Byte 0 ==
8144 16:55:36.539124 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8145 16:55:36.545425 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8146 16:55:36.545906 == TX Byte 1 ==
8147 16:55:36.548386 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8148 16:55:36.555270 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8149 16:55:36.555848 ==
8150 16:55:36.559257 Dram Type= 6, Freq= 0, CH_0, rank 1
8151 16:55:36.562037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8152 16:55:36.562695 ==
8153 16:55:36.575690
8154 16:55:36.579357 TX Vref early break, caculate TX vref
8155 16:55:36.582071 TX Vref=16, minBit 0, minWin=23, winSum=388
8156 16:55:36.585349 TX Vref=18, minBit 8, minWin=23, winSum=401
8157 16:55:36.588900 TX Vref=20, minBit 8, minWin=24, winSum=410
8158 16:55:36.591818 TX Vref=22, minBit 8, minWin=24, winSum=413
8159 16:55:36.595202 TX Vref=24, minBit 0, minWin=25, winSum=424
8160 16:55:36.601696 TX Vref=26, minBit 0, minWin=26, winSum=431
8161 16:55:36.605226 TX Vref=28, minBit 0, minWin=26, winSum=427
8162 16:55:36.608639 TX Vref=30, minBit 0, minWin=26, winSum=424
8163 16:55:36.611766 TX Vref=32, minBit 0, minWin=25, winSum=416
8164 16:55:36.615220 TX Vref=34, minBit 2, minWin=24, winSum=406
8165 16:55:36.621808 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 26
8166 16:55:36.622382
8167 16:55:36.624824 Final TX Range 0 Vref 26
8168 16:55:36.625297
8169 16:55:36.625673 ==
8170 16:55:36.628550 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 16:55:36.631830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 16:55:36.632314 ==
8173 16:55:36.632692
8174 16:55:36.633037
8175 16:55:36.635239 TX Vref Scan disable
8176 16:55:36.641444 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8177 16:55:36.641922 == TX Byte 0 ==
8178 16:55:36.644830 u2DelayCellOfst[0]=13 cells (4 PI)
8179 16:55:36.649055 u2DelayCellOfst[1]=20 cells (6 PI)
8180 16:55:36.651281 u2DelayCellOfst[2]=13 cells (4 PI)
8181 16:55:36.654783 u2DelayCellOfst[3]=13 cells (4 PI)
8182 16:55:36.658244 u2DelayCellOfst[4]=10 cells (3 PI)
8183 16:55:36.661293 u2DelayCellOfst[5]=0 cells (0 PI)
8184 16:55:36.664556 u2DelayCellOfst[6]=20 cells (6 PI)
8185 16:55:36.669107 u2DelayCellOfst[7]=20 cells (6 PI)
8186 16:55:36.671339 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8187 16:55:36.674897 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8188 16:55:36.678260 == TX Byte 1 ==
8189 16:55:36.681714 u2DelayCellOfst[8]=0 cells (0 PI)
8190 16:55:36.684893 u2DelayCellOfst[9]=0 cells (0 PI)
8191 16:55:36.685370 u2DelayCellOfst[10]=6 cells (2 PI)
8192 16:55:36.688221 u2DelayCellOfst[11]=3 cells (1 PI)
8193 16:55:36.691449 u2DelayCellOfst[12]=13 cells (4 PI)
8194 16:55:36.694778 u2DelayCellOfst[13]=13 cells (4 PI)
8195 16:55:36.697742 u2DelayCellOfst[14]=13 cells (4 PI)
8196 16:55:36.701122 u2DelayCellOfst[15]=10 cells (3 PI)
8197 16:55:36.707787 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8198 16:55:36.711084 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8199 16:55:36.711560 DramC Write-DBI on
8200 16:55:36.711917 ==
8201 16:55:36.714196 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 16:55:36.720999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 16:55:36.721578 ==
8204 16:55:36.721933
8205 16:55:36.722251
8206 16:55:36.722575 TX Vref Scan disable
8207 16:55:36.725201 == TX Byte 0 ==
8208 16:55:36.728604 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8209 16:55:36.731792 == TX Byte 1 ==
8210 16:55:36.734944 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8211 16:55:36.738781 DramC Write-DBI off
8212 16:55:36.739208
8213 16:55:36.739546 [DATLAT]
8214 16:55:36.739861 Freq=1600, CH0 RK1
8215 16:55:36.740165
8216 16:55:36.741999 DATLAT Default: 0xf
8217 16:55:36.742455 0, 0xFFFF, sum = 0
8218 16:55:36.745617 1, 0xFFFF, sum = 0
8219 16:55:36.748343 2, 0xFFFF, sum = 0
8220 16:55:36.748778 3, 0xFFFF, sum = 0
8221 16:55:36.751736 4, 0xFFFF, sum = 0
8222 16:55:36.752172 5, 0xFFFF, sum = 0
8223 16:55:36.754708 6, 0xFFFF, sum = 0
8224 16:55:36.755142 7, 0xFFFF, sum = 0
8225 16:55:36.758675 8, 0xFFFF, sum = 0
8226 16:55:36.759110 9, 0xFFFF, sum = 0
8227 16:55:36.761496 10, 0xFFFF, sum = 0
8228 16:55:36.761930 11, 0xFFFF, sum = 0
8229 16:55:36.765319 12, 0xFFFF, sum = 0
8230 16:55:36.765851 13, 0xFFFF, sum = 0
8231 16:55:36.768048 14, 0x0, sum = 1
8232 16:55:36.768486 15, 0x0, sum = 2
8233 16:55:36.771759 16, 0x0, sum = 3
8234 16:55:36.772196 17, 0x0, sum = 4
8235 16:55:36.774682 best_step = 15
8236 16:55:36.775112
8237 16:55:36.775451 ==
8238 16:55:36.778231 Dram Type= 6, Freq= 0, CH_0, rank 1
8239 16:55:36.781782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8240 16:55:36.782310 ==
8241 16:55:36.784761 RX Vref Scan: 0
8242 16:55:36.785189
8243 16:55:36.785534 RX Vref 0 -> 0, step: 1
8244 16:55:36.785857
8245 16:55:36.787909 RX Delay 11 -> 252, step: 4
8246 16:55:36.794978 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8247 16:55:36.797615 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8248 16:55:36.801333 iDelay=191, Bit 2, Center 130 (83 ~ 178) 96
8249 16:55:36.804792 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8250 16:55:36.807639 iDelay=191, Bit 4, Center 134 (87 ~ 182) 96
8251 16:55:36.814439 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8252 16:55:36.817682 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8253 16:55:36.820604 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8254 16:55:36.824007 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8255 16:55:36.827359 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8256 16:55:36.834243 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8257 16:55:36.837232 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8258 16:55:36.840886 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8259 16:55:36.844200 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8260 16:55:36.847672 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8261 16:55:36.854179 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8262 16:55:36.854731 ==
8263 16:55:36.857428 Dram Type= 6, Freq= 0, CH_0, rank 1
8264 16:55:36.860808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8265 16:55:36.861336 ==
8266 16:55:36.861684 DQS Delay:
8267 16:55:36.864147 DQS0 = 0, DQS1 = 0
8268 16:55:36.864672 DQM Delay:
8269 16:55:36.867074 DQM0 = 133, DQM1 = 123
8270 16:55:36.867504 DQ Delay:
8271 16:55:36.870972 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =130
8272 16:55:36.874134 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8273 16:55:36.877467 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =118
8274 16:55:36.880782 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8275 16:55:36.881306
8276 16:55:36.884532
8277 16:55:36.885100
8278 16:55:36.885475 [DramC_TX_OE_Calibration] TA2
8279 16:55:36.887010 Original DQ_B0 (3 6) =30, OEN = 27
8280 16:55:36.890759 Original DQ_B1 (3 6) =30, OEN = 27
8281 16:55:36.893789 24, 0x0, End_B0=24 End_B1=24
8282 16:55:36.897355 25, 0x0, End_B0=25 End_B1=25
8283 16:55:36.900431 26, 0x0, End_B0=26 End_B1=26
8284 16:55:36.901008 27, 0x0, End_B0=27 End_B1=27
8285 16:55:36.904143 28, 0x0, End_B0=28 End_B1=28
8286 16:55:36.907800 29, 0x0, End_B0=29 End_B1=29
8287 16:55:36.910037 30, 0x0, End_B0=30 End_B1=30
8288 16:55:36.913477 31, 0x4141, End_B0=30 End_B1=30
8289 16:55:36.913951 Byte0 end_step=30 best_step=27
8290 16:55:36.917163 Byte1 end_step=30 best_step=27
8291 16:55:36.920225 Byte0 TX OE(2T, 0.5T) = (3, 3)
8292 16:55:36.923957 Byte1 TX OE(2T, 0.5T) = (3, 3)
8293 16:55:36.924530
8294 16:55:36.924906
8295 16:55:36.933266 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8296 16:55:36.933851 CH0 RK1: MR19=303, MR18=220F
8297 16:55:36.939872 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8298 16:55:36.943419 [RxdqsGatingPostProcess] freq 1600
8299 16:55:36.950273 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8300 16:55:36.953252 best DQS0 dly(2T, 0.5T) = (1, 1)
8301 16:55:36.956403 best DQS1 dly(2T, 0.5T) = (1, 1)
8302 16:55:36.959750 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8303 16:55:36.963333 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8304 16:55:36.963852 best DQS0 dly(2T, 0.5T) = (1, 1)
8305 16:55:36.966150 best DQS1 dly(2T, 0.5T) = (1, 1)
8306 16:55:36.969642 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8307 16:55:36.973164 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8308 16:55:36.976410 Pre-setting of DQS Precalculation
8309 16:55:36.983255 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8310 16:55:36.983815 ==
8311 16:55:36.986469 Dram Type= 6, Freq= 0, CH_1, rank 0
8312 16:55:36.989755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 16:55:36.990330 ==
8314 16:55:36.996044 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 16:55:36.999796 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 16:55:37.002565 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 16:55:37.009564 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 16:55:37.018239 [CA 0] Center 40 (11~70) winsize 60
8319 16:55:37.021533 [CA 1] Center 41 (11~71) winsize 61
8320 16:55:37.024791 [CA 2] Center 36 (7~66) winsize 60
8321 16:55:37.028200 [CA 3] Center 36 (7~66) winsize 60
8322 16:55:37.031222 [CA 4] Center 36 (6~67) winsize 62
8323 16:55:37.035066 [CA 5] Center 35 (6~65) winsize 60
8324 16:55:37.035638
8325 16:55:37.038281 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8326 16:55:37.038880
8327 16:55:37.041264 [CATrainingPosCal] consider 1 rank data
8328 16:55:37.044802 u2DelayCellTimex100 = 285/100 ps
8329 16:55:37.050970 CA0 delay=40 (11~70),Diff = 5 PI (17 cell)
8330 16:55:37.054323 CA1 delay=41 (11~71),Diff = 6 PI (20 cell)
8331 16:55:37.058045 CA2 delay=36 (7~66),Diff = 1 PI (3 cell)
8332 16:55:37.061191 CA3 delay=36 (7~66),Diff = 1 PI (3 cell)
8333 16:55:37.063947 CA4 delay=36 (6~67),Diff = 1 PI (3 cell)
8334 16:55:37.067953 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8335 16:55:37.068521
8336 16:55:37.070886 CA PerBit enable=1, Macro0, CA PI delay=35
8337 16:55:37.071355
8338 16:55:37.074215 [CBTSetCACLKResult] CA Dly = 35
8339 16:55:37.077486 CS Dly: 8 (0~39)
8340 16:55:37.081362 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 16:55:37.084636 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 16:55:37.085214 ==
8343 16:55:37.087264 Dram Type= 6, Freq= 0, CH_1, rank 1
8344 16:55:37.090926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8345 16:55:37.094875 ==
8346 16:55:37.097169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8347 16:55:37.100627 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8348 16:55:37.107313 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8349 16:55:37.113822 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8350 16:55:37.121373 [CA 0] Center 41 (12~71) winsize 60
8351 16:55:37.124589 [CA 1] Center 41 (12~71) winsize 60
8352 16:55:37.127624 [CA 2] Center 38 (9~68) winsize 60
8353 16:55:37.131050 [CA 3] Center 37 (8~67) winsize 60
8354 16:55:37.134421 [CA 4] Center 37 (8~67) winsize 60
8355 16:55:37.137760 [CA 5] Center 37 (7~67) winsize 61
8356 16:55:37.138228
8357 16:55:37.141235 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8358 16:55:37.141801
8359 16:55:37.144057 [CATrainingPosCal] consider 2 rank data
8360 16:55:37.147391 u2DelayCellTimex100 = 285/100 ps
8361 16:55:37.154478 CA0 delay=41 (12~70),Diff = 5 PI (17 cell)
8362 16:55:37.157401 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8363 16:55:37.160602 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8364 16:55:37.164192 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8365 16:55:37.167391 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8366 16:55:37.170948 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8367 16:55:37.171502
8368 16:55:37.173750 CA PerBit enable=1, Macro0, CA PI delay=36
8369 16:55:37.174206
8370 16:55:37.177279 [CBTSetCACLKResult] CA Dly = 36
8371 16:55:37.180857 CS Dly: 9 (0~41)
8372 16:55:37.184240 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8373 16:55:37.187016 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8374 16:55:37.187490
8375 16:55:37.191007 ----->DramcWriteLeveling(PI) begin...
8376 16:55:37.191571 ==
8377 16:55:37.194240 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 16:55:37.200525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 16:55:37.201086 ==
8380 16:55:37.203900 Write leveling (Byte 0): 23 => 23
8381 16:55:37.204461 Write leveling (Byte 1): 28 => 28
8382 16:55:37.207281 DramcWriteLeveling(PI) end<-----
8383 16:55:37.207836
8384 16:55:37.210810 ==
8385 16:55:37.211399 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 16:55:37.217273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 16:55:37.217838 ==
8388 16:55:37.220267 [Gating] SW mode calibration
8389 16:55:37.227093 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8390 16:55:37.230506 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8391 16:55:37.236939 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 16:55:37.240559 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 16:55:37.243828 1 4 8 | B1->B0 | 2e2d 3030 | 1 1 | (0 0) (1 1)
8394 16:55:37.250327 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 16:55:37.253343 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8396 16:55:37.256587 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8397 16:55:37.263001 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8398 16:55:37.266816 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8399 16:55:37.270140 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 16:55:37.276422 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8401 16:55:37.279718 1 5 8 | B1->B0 | 2a2a 2828 | 0 0 | (0 0) (1 0)
8402 16:55:37.283134 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8403 16:55:37.289760 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 16:55:37.293663 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 16:55:37.295981 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 16:55:37.303049 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 16:55:37.306339 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 16:55:37.310547 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8409 16:55:37.316267 1 6 8 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
8410 16:55:37.319489 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 16:55:37.322177 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8412 16:55:37.328952 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 16:55:37.332587 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8414 16:55:37.335482 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8415 16:55:37.342918 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 16:55:37.345780 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8417 16:55:37.349298 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8418 16:55:37.355863 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8419 16:55:37.358555 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8420 16:55:37.362543 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 16:55:37.368254 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 16:55:37.371966 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 16:55:37.374814 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 16:55:37.382044 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 16:55:37.384952 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 16:55:37.387859 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 16:55:37.394622 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 16:55:37.398070 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 16:55:37.401978 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 16:55:37.407996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 16:55:37.411858 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 16:55:37.414718 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8433 16:55:37.421322 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8434 16:55:37.424818 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8435 16:55:37.427624 Total UI for P1: 0, mck2ui 16
8436 16:55:37.431239 best dqsien dly found for B0: ( 1, 9, 6)
8437 16:55:37.434722 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 16:55:37.437621 Total UI for P1: 0, mck2ui 16
8439 16:55:37.440976 best dqsien dly found for B1: ( 1, 9, 10)
8440 16:55:37.444723 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8441 16:55:37.447783 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8442 16:55:37.451103
8443 16:55:37.454129 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8444 16:55:37.457631 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8445 16:55:37.461089 [Gating] SW calibration Done
8446 16:55:37.461653 ==
8447 16:55:37.464567 Dram Type= 6, Freq= 0, CH_1, rank 0
8448 16:55:37.467655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8449 16:55:37.468241 ==
8450 16:55:37.468623 RX Vref Scan: 0
8451 16:55:37.470748
8452 16:55:37.471315 RX Vref 0 -> 0, step: 1
8453 16:55:37.471713
8454 16:55:37.474186 RX Delay 0 -> 252, step: 8
8455 16:55:37.477307 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8456 16:55:37.480651 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8457 16:55:37.486917 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8458 16:55:37.490751 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8459 16:55:37.494192 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8460 16:55:37.496718 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8461 16:55:37.500143 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8462 16:55:37.507162 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8463 16:55:37.510962 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8464 16:55:37.513315 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8465 16:55:37.516562 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8466 16:55:37.520126 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8467 16:55:37.526572 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8468 16:55:37.530169 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8469 16:55:37.533221 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8470 16:55:37.536943 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8471 16:55:37.537419 ==
8472 16:55:37.540273 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 16:55:37.546753 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 16:55:37.547327 ==
8475 16:55:37.547706 DQS Delay:
8476 16:55:37.550566 DQS0 = 0, DQS1 = 0
8477 16:55:37.551129 DQM Delay:
8478 16:55:37.551509 DQM0 = 138, DQM1 = 129
8479 16:55:37.553018 DQ Delay:
8480 16:55:37.556758 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =139
8481 16:55:37.559868 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8482 16:55:37.563289 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8483 16:55:37.566457 DQ12 =139, DQ13 =135, DQ14 =135, DQ15 =135
8484 16:55:37.567028
8485 16:55:37.567405
8486 16:55:37.567748 ==
8487 16:55:37.569933 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 16:55:37.576961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 16:55:37.577575 ==
8490 16:55:37.577957
8491 16:55:37.578303
8492 16:55:37.578670 TX Vref Scan disable
8493 16:55:37.579560 == TX Byte 0 ==
8494 16:55:37.583338 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8495 16:55:37.589428 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8496 16:55:37.589997 == TX Byte 1 ==
8497 16:55:37.592787 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8498 16:55:37.599012 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8499 16:55:37.599489 ==
8500 16:55:37.602727 Dram Type= 6, Freq= 0, CH_1, rank 0
8501 16:55:37.605852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8502 16:55:37.606451 ==
8503 16:55:37.618223
8504 16:55:37.621822 TX Vref early break, caculate TX vref
8505 16:55:37.625434 TX Vref=16, minBit 10, minWin=21, winSum=371
8506 16:55:37.628246 TX Vref=18, minBit 10, minWin=22, winSum=379
8507 16:55:37.632018 TX Vref=20, minBit 10, minWin=23, winSum=388
8508 16:55:37.635501 TX Vref=22, minBit 10, minWin=23, winSum=399
8509 16:55:37.641425 TX Vref=24, minBit 10, minWin=24, winSum=411
8510 16:55:37.645404 TX Vref=26, minBit 15, minWin=24, winSum=411
8511 16:55:37.647715 TX Vref=28, minBit 12, minWin=25, winSum=420
8512 16:55:37.651584 TX Vref=30, minBit 0, minWin=25, winSum=410
8513 16:55:37.654859 TX Vref=32, minBit 12, minWin=23, winSum=399
8514 16:55:37.661815 TX Vref=34, minBit 8, minWin=23, winSum=388
8515 16:55:37.665288 [TxChooseVref] Worse bit 12, Min win 25, Win sum 420, Final Vref 28
8516 16:55:37.665857
8517 16:55:37.668188 Final TX Range 0 Vref 28
8518 16:55:37.668759
8519 16:55:37.669135 ==
8520 16:55:37.671067 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 16:55:37.674757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 16:55:37.677818 ==
8523 16:55:37.678432
8524 16:55:37.678827
8525 16:55:37.679176 TX Vref Scan disable
8526 16:55:37.684645 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8527 16:55:37.685219 == TX Byte 0 ==
8528 16:55:37.687866 u2DelayCellOfst[0]=17 cells (5 PI)
8529 16:55:37.691292 u2DelayCellOfst[1]=10 cells (3 PI)
8530 16:55:37.694381 u2DelayCellOfst[2]=0 cells (0 PI)
8531 16:55:37.697798 u2DelayCellOfst[3]=3 cells (1 PI)
8532 16:55:37.700950 u2DelayCellOfst[4]=6 cells (2 PI)
8533 16:55:37.704729 u2DelayCellOfst[5]=17 cells (5 PI)
8534 16:55:37.707244 u2DelayCellOfst[6]=17 cells (5 PI)
8535 16:55:37.710722 u2DelayCellOfst[7]=3 cells (1 PI)
8536 16:55:37.714136 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8537 16:55:37.717613 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8538 16:55:37.721133 == TX Byte 1 ==
8539 16:55:37.724513 u2DelayCellOfst[8]=0 cells (0 PI)
8540 16:55:37.727049 u2DelayCellOfst[9]=3 cells (1 PI)
8541 16:55:37.730515 u2DelayCellOfst[10]=13 cells (4 PI)
8542 16:55:37.733867 u2DelayCellOfst[11]=6 cells (2 PI)
8543 16:55:37.736918 u2DelayCellOfst[12]=17 cells (5 PI)
8544 16:55:37.740635 u2DelayCellOfst[13]=20 cells (6 PI)
8545 16:55:37.741102 u2DelayCellOfst[14]=20 cells (6 PI)
8546 16:55:37.743657 u2DelayCellOfst[15]=17 cells (5 PI)
8547 16:55:37.750276 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8548 16:55:37.753818 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8549 16:55:37.758662 DramC Write-DBI on
8550 16:55:37.759228 ==
8551 16:55:37.760301 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 16:55:37.763674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 16:55:37.764146 ==
8554 16:55:37.764516
8555 16:55:37.764853
8556 16:55:37.767501 TX Vref Scan disable
8557 16:55:37.768064 == TX Byte 0 ==
8558 16:55:37.774252 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8559 16:55:37.774859 == TX Byte 1 ==
8560 16:55:37.777815 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8561 16:55:37.780277 DramC Write-DBI off
8562 16:55:37.780749
8563 16:55:37.781119 [DATLAT]
8564 16:55:37.783165 Freq=1600, CH1 RK0
8565 16:55:37.783631
8566 16:55:37.783997 DATLAT Default: 0xf
8567 16:55:37.786537 0, 0xFFFF, sum = 0
8568 16:55:37.787013 1, 0xFFFF, sum = 0
8569 16:55:37.789952 2, 0xFFFF, sum = 0
8570 16:55:37.793703 3, 0xFFFF, sum = 0
8571 16:55:37.794181 4, 0xFFFF, sum = 0
8572 16:55:37.796455 5, 0xFFFF, sum = 0
8573 16:55:37.796930 6, 0xFFFF, sum = 0
8574 16:55:37.799822 7, 0xFFFF, sum = 0
8575 16:55:37.800411 8, 0xFFFF, sum = 0
8576 16:55:37.803692 9, 0xFFFF, sum = 0
8577 16:55:37.804171 10, 0xFFFF, sum = 0
8578 16:55:37.806480 11, 0xFFFF, sum = 0
8579 16:55:37.806960 12, 0xFFFF, sum = 0
8580 16:55:37.809589 13, 0xFFFF, sum = 0
8581 16:55:37.810065 14, 0x0, sum = 1
8582 16:55:37.812901 15, 0x0, sum = 2
8583 16:55:37.813378 16, 0x0, sum = 3
8584 16:55:37.816811 17, 0x0, sum = 4
8585 16:55:37.817395 best_step = 15
8586 16:55:37.817769
8587 16:55:37.818144 ==
8588 16:55:37.820184 Dram Type= 6, Freq= 0, CH_1, rank 0
8589 16:55:37.825993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8590 16:55:37.826512 ==
8591 16:55:37.826897 RX Vref Scan: 1
8592 16:55:37.827246
8593 16:55:37.829964 Set Vref Range= 24 -> 127
8594 16:55:37.830479
8595 16:55:37.832861 RX Vref 24 -> 127, step: 1
8596 16:55:37.833327
8597 16:55:37.833698 RX Delay 19 -> 252, step: 4
8598 16:55:37.835820
8599 16:55:37.836316 Set Vref, RX VrefLevel [Byte0]: 24
8600 16:55:37.840880 [Byte1]: 24
8601 16:55:37.843844
8602 16:55:37.844413 Set Vref, RX VrefLevel [Byte0]: 25
8603 16:55:37.846828 [Byte1]: 25
8604 16:55:37.850969
8605 16:55:37.851595 Set Vref, RX VrefLevel [Byte0]: 26
8606 16:55:37.854543 [Byte1]: 26
8607 16:55:37.858737
8608 16:55:37.859313 Set Vref, RX VrefLevel [Byte0]: 27
8609 16:55:37.862387 [Byte1]: 27
8610 16:55:37.866608
8611 16:55:37.867185 Set Vref, RX VrefLevel [Byte0]: 28
8612 16:55:37.869408 [Byte1]: 28
8613 16:55:37.874673
8614 16:55:37.875248 Set Vref, RX VrefLevel [Byte0]: 29
8615 16:55:37.880011 [Byte1]: 29
8616 16:55:37.880482
8617 16:55:37.883522 Set Vref, RX VrefLevel [Byte0]: 30
8618 16:55:37.886978 [Byte1]: 30
8619 16:55:37.887451
8620 16:55:37.890469 Set Vref, RX VrefLevel [Byte0]: 31
8621 16:55:37.893488 [Byte1]: 31
8622 16:55:37.894063
8623 16:55:37.897047 Set Vref, RX VrefLevel [Byte0]: 32
8624 16:55:37.900098 [Byte1]: 32
8625 16:55:37.904430
8626 16:55:37.905004 Set Vref, RX VrefLevel [Byte0]: 33
8627 16:55:37.907128 [Byte1]: 33
8628 16:55:37.911953
8629 16:55:37.912528 Set Vref, RX VrefLevel [Byte0]: 34
8630 16:55:37.916173 [Byte1]: 34
8631 16:55:37.919141
8632 16:55:37.919614 Set Vref, RX VrefLevel [Byte0]: 35
8633 16:55:37.922957 [Byte1]: 35
8634 16:55:37.926648
8635 16:55:37.927268 Set Vref, RX VrefLevel [Byte0]: 36
8636 16:55:37.930033 [Byte1]: 36
8637 16:55:37.934060
8638 16:55:37.934556 Set Vref, RX VrefLevel [Byte0]: 37
8639 16:55:37.937834 [Byte1]: 37
8640 16:55:37.942504
8641 16:55:37.943144 Set Vref, RX VrefLevel [Byte0]: 38
8642 16:55:37.945348 [Byte1]: 38
8643 16:55:37.949709
8644 16:55:37.950178 Set Vref, RX VrefLevel [Byte0]: 39
8645 16:55:37.952940 [Byte1]: 39
8646 16:55:37.957401
8647 16:55:37.957967 Set Vref, RX VrefLevel [Byte0]: 40
8648 16:55:37.960777 [Byte1]: 40
8649 16:55:37.964869
8650 16:55:37.965436 Set Vref, RX VrefLevel [Byte0]: 41
8651 16:55:37.968114 [Byte1]: 41
8652 16:55:37.972331
8653 16:55:37.972921 Set Vref, RX VrefLevel [Byte0]: 42
8654 16:55:37.976145 [Byte1]: 42
8655 16:55:37.979827
8656 16:55:37.980396 Set Vref, RX VrefLevel [Byte0]: 43
8657 16:55:37.982904 [Byte1]: 43
8658 16:55:37.987916
8659 16:55:37.988490 Set Vref, RX VrefLevel [Byte0]: 44
8660 16:55:37.990686 [Byte1]: 44
8661 16:55:37.995984
8662 16:55:37.996554 Set Vref, RX VrefLevel [Byte0]: 45
8663 16:55:37.998202 [Byte1]: 45
8664 16:55:38.002523
8665 16:55:38.002996 Set Vref, RX VrefLevel [Byte0]: 46
8666 16:55:38.006128 [Byte1]: 46
8667 16:55:38.010117
8668 16:55:38.010733 Set Vref, RX VrefLevel [Byte0]: 47
8669 16:55:38.013220 [Byte1]: 47
8670 16:55:38.017656
8671 16:55:38.018234 Set Vref, RX VrefLevel [Byte0]: 48
8672 16:55:38.021185 [Byte1]: 48
8673 16:55:38.025355
8674 16:55:38.025929 Set Vref, RX VrefLevel [Byte0]: 49
8675 16:55:38.028483 [Byte1]: 49
8676 16:55:38.033029
8677 16:55:38.033762 Set Vref, RX VrefLevel [Byte0]: 50
8678 16:55:38.036230 [Byte1]: 50
8679 16:55:38.040184
8680 16:55:38.040668 Set Vref, RX VrefLevel [Byte0]: 51
8681 16:55:38.043750 [Byte1]: 51
8682 16:55:38.047825
8683 16:55:38.048396 Set Vref, RX VrefLevel [Byte0]: 52
8684 16:55:38.050984 [Byte1]: 52
8685 16:55:38.055602
8686 16:55:38.056190 Set Vref, RX VrefLevel [Byte0]: 53
8687 16:55:38.058985 [Byte1]: 53
8688 16:55:38.063015
8689 16:55:38.063590 Set Vref, RX VrefLevel [Byte0]: 54
8690 16:55:38.066511 [Byte1]: 54
8691 16:55:38.070795
8692 16:55:38.071366 Set Vref, RX VrefLevel [Byte0]: 55
8693 16:55:38.073948 [Byte1]: 55
8694 16:55:38.078491
8695 16:55:38.079076 Set Vref, RX VrefLevel [Byte0]: 56
8696 16:55:38.081439 [Byte1]: 56
8697 16:55:38.085847
8698 16:55:38.086466 Set Vref, RX VrefLevel [Byte0]: 57
8699 16:55:38.089196 [Byte1]: 57
8700 16:55:38.094007
8701 16:55:38.094629 Set Vref, RX VrefLevel [Byte0]: 58
8702 16:55:38.097303 [Byte1]: 58
8703 16:55:38.101393
8704 16:55:38.101974 Set Vref, RX VrefLevel [Byte0]: 59
8705 16:55:38.104272 [Byte1]: 59
8706 16:55:38.109430
8707 16:55:38.110004 Set Vref, RX VrefLevel [Byte0]: 60
8708 16:55:38.111752 [Byte1]: 60
8709 16:55:38.116107
8710 16:55:38.116605 Set Vref, RX VrefLevel [Byte0]: 61
8711 16:55:38.120002 [Byte1]: 61
8712 16:55:38.123593
8713 16:55:38.124094 Set Vref, RX VrefLevel [Byte0]: 62
8714 16:55:38.127178 [Byte1]: 62
8715 16:55:38.131599
8716 16:55:38.132174 Set Vref, RX VrefLevel [Byte0]: 63
8717 16:55:38.134897 [Byte1]: 63
8718 16:55:38.139050
8719 16:55:38.139522 Set Vref, RX VrefLevel [Byte0]: 64
8720 16:55:38.141985 [Byte1]: 64
8721 16:55:38.146313
8722 16:55:38.146956 Set Vref, RX VrefLevel [Byte0]: 65
8723 16:55:38.149853 [Byte1]: 65
8724 16:55:38.154015
8725 16:55:38.154665 Set Vref, RX VrefLevel [Byte0]: 66
8726 16:55:38.157033 [Byte1]: 66
8727 16:55:38.161707
8728 16:55:38.162460 Set Vref, RX VrefLevel [Byte0]: 67
8729 16:55:38.164679 [Byte1]: 67
8730 16:55:38.169317
8731 16:55:38.169896 Set Vref, RX VrefLevel [Byte0]: 68
8732 16:55:38.172352 [Byte1]: 68
8733 16:55:38.176745
8734 16:55:38.177322 Set Vref, RX VrefLevel [Byte0]: 69
8735 16:55:38.180374 [Byte1]: 69
8736 16:55:38.185464
8737 16:55:38.186039 Set Vref, RX VrefLevel [Byte0]: 70
8738 16:55:38.187929 [Byte1]: 70
8739 16:55:38.191783
8740 16:55:38.192359 Set Vref, RX VrefLevel [Byte0]: 71
8741 16:55:38.195488 [Byte1]: 71
8742 16:55:38.199676
8743 16:55:38.200268 Set Vref, RX VrefLevel [Byte0]: 72
8744 16:55:38.202973 [Byte1]: 72
8745 16:55:38.207335
8746 16:55:38.210129 Set Vref, RX VrefLevel [Byte0]: 73
8747 16:55:38.210763 [Byte1]: 73
8748 16:55:38.214799
8749 16:55:38.215374 Final RX Vref Byte 0 = 52 to rank0
8750 16:55:38.217829 Final RX Vref Byte 1 = 64 to rank0
8751 16:55:38.221300 Final RX Vref Byte 0 = 52 to rank1
8752 16:55:38.224624 Final RX Vref Byte 1 = 64 to rank1==
8753 16:55:38.227963 Dram Type= 6, Freq= 0, CH_1, rank 0
8754 16:55:38.234881 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8755 16:55:38.235476 ==
8756 16:55:38.235857 DQS Delay:
8757 16:55:38.236206 DQS0 = 0, DQS1 = 0
8758 16:55:38.237766 DQM Delay:
8759 16:55:38.238240 DQM0 = 133, DQM1 = 129
8760 16:55:38.241394 DQ Delay:
8761 16:55:38.244687 DQ0 =136, DQ1 =130, DQ2 =122, DQ3 =132
8762 16:55:38.247426 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
8763 16:55:38.251731 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
8764 16:55:38.254532 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =134
8765 16:55:38.255125
8766 16:55:38.255508
8767 16:55:38.255854
8768 16:55:38.257642 [DramC_TX_OE_Calibration] TA2
8769 16:55:38.261506 Original DQ_B0 (3 6) =30, OEN = 27
8770 16:55:38.264264 Original DQ_B1 (3 6) =30, OEN = 27
8771 16:55:38.267713 24, 0x0, End_B0=24 End_B1=24
8772 16:55:38.268199 25, 0x0, End_B0=25 End_B1=25
8773 16:55:38.271244 26, 0x0, End_B0=26 End_B1=26
8774 16:55:38.274199 27, 0x0, End_B0=27 End_B1=27
8775 16:55:38.277517 28, 0x0, End_B0=28 End_B1=28
8776 16:55:38.280585 29, 0x0, End_B0=29 End_B1=29
8777 16:55:38.281314 30, 0x0, End_B0=30 End_B1=30
8778 16:55:38.284875 31, 0x4141, End_B0=30 End_B1=30
8779 16:55:38.287959 Byte0 end_step=30 best_step=27
8780 16:55:38.290500 Byte1 end_step=30 best_step=27
8781 16:55:38.294099 Byte0 TX OE(2T, 0.5T) = (3, 3)
8782 16:55:38.297401 Byte1 TX OE(2T, 0.5T) = (3, 3)
8783 16:55:38.297979
8784 16:55:38.298400
8785 16:55:38.303865 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8786 16:55:38.307242 CH1 RK0: MR19=303, MR18=1523
8787 16:55:38.313621 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8788 16:55:38.314195
8789 16:55:38.316790 ----->DramcWriteLeveling(PI) begin...
8790 16:55:38.317273 ==
8791 16:55:38.320432 Dram Type= 6, Freq= 0, CH_1, rank 1
8792 16:55:38.323732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 16:55:38.324330 ==
8794 16:55:38.327411 Write leveling (Byte 0): 26 => 26
8795 16:55:38.330136 Write leveling (Byte 1): 28 => 28
8796 16:55:38.333799 DramcWriteLeveling(PI) end<-----
8797 16:55:38.334392
8798 16:55:38.334783 ==
8799 16:55:38.336738 Dram Type= 6, Freq= 0, CH_1, rank 1
8800 16:55:38.340433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8801 16:55:38.343816 ==
8802 16:55:38.344382 [Gating] SW mode calibration
8803 16:55:38.350709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8804 16:55:38.356767 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8805 16:55:38.360186 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 16:55:38.366403 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 16:55:38.369899 1 4 8 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
8808 16:55:38.373093 1 4 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 1)
8809 16:55:38.380050 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8810 16:55:38.383134 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8811 16:55:38.386333 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 16:55:38.393093 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 16:55:38.396242 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 16:55:38.400433 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 16:55:38.406530 1 5 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 0) (1 0)
8816 16:55:38.409751 1 5 12 | B1->B0 | 2323 2f2f | 0 0 | (1 0) (0 0)
8817 16:55:38.413008 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8818 16:55:38.419385 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8819 16:55:38.423315 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8820 16:55:38.426095 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 16:55:38.432780 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 16:55:38.436061 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8823 16:55:38.439603 1 6 8 | B1->B0 | 3c3c 2323 | 0 0 | (0 0) (0 0)
8824 16:55:38.446031 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8825 16:55:38.449780 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8826 16:55:38.453025 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8827 16:55:38.459550 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8828 16:55:38.462559 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 16:55:38.466229 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 16:55:38.472397 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8831 16:55:38.475767 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8832 16:55:38.479137 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8833 16:55:38.485514 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 16:55:38.488753 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 16:55:38.492430 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 16:55:38.499027 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 16:55:38.502139 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 16:55:38.505692 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 16:55:38.512228 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 16:55:38.515560 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 16:55:38.518717 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 16:55:38.525665 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 16:55:38.528670 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 16:55:38.531916 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 16:55:38.535210 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 16:55:38.541982 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8847 16:55:38.545183 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8848 16:55:38.548760 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8849 16:55:38.551988 Total UI for P1: 0, mck2ui 16
8850 16:55:38.555187 best dqsien dly found for B1: ( 1, 9, 6)
8851 16:55:38.561846 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 16:55:38.565249 Total UI for P1: 0, mck2ui 16
8853 16:55:38.568371 best dqsien dly found for B0: ( 1, 9, 10)
8854 16:55:38.571694 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8855 16:55:38.575172 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8856 16:55:38.575736
8857 16:55:38.578426 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8858 16:55:38.581376 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8859 16:55:38.585103 [Gating] SW calibration Done
8860 16:55:38.585686 ==
8861 16:55:38.588047 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 16:55:38.591417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 16:55:38.591898 ==
8864 16:55:38.594522 RX Vref Scan: 0
8865 16:55:38.595030
8866 16:55:38.598018 RX Vref 0 -> 0, step: 1
8867 16:55:38.598563
8868 16:55:38.599071 RX Delay 0 -> 252, step: 8
8869 16:55:38.604449 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8870 16:55:38.607728 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8871 16:55:38.610849 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8872 16:55:38.614835 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8873 16:55:38.617547 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8874 16:55:38.624439 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8875 16:55:38.627705 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8876 16:55:38.631118 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
8877 16:55:38.634072 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8878 16:55:38.637561 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8879 16:55:38.644173 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8880 16:55:38.647443 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8881 16:55:38.650770 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8882 16:55:38.653885 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8883 16:55:38.660864 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8884 16:55:38.663999 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8885 16:55:38.664633 ==
8886 16:55:38.667213 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 16:55:38.670666 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 16:55:38.671143 ==
8889 16:55:38.671587 DQS Delay:
8890 16:55:38.674162 DQS0 = 0, DQS1 = 0
8891 16:55:38.674679 DQM Delay:
8892 16:55:38.677236 DQM0 = 137, DQM1 = 132
8893 16:55:38.677701 DQ Delay:
8894 16:55:38.681318 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =135
8895 16:55:38.685389 DQ4 =139, DQ5 =147, DQ6 =139, DQ7 =139
8896 16:55:38.686964 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =127
8897 16:55:38.693856 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143
8898 16:55:38.694330
8899 16:55:38.694752
8900 16:55:38.695098 ==
8901 16:55:38.697115 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 16:55:38.700295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 16:55:38.700772 ==
8904 16:55:38.701145
8905 16:55:38.701577
8906 16:55:38.703526 TX Vref Scan disable
8907 16:55:38.703995 == TX Byte 0 ==
8908 16:55:38.710063 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8909 16:55:38.713430 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8910 16:55:38.714026 == TX Byte 1 ==
8911 16:55:38.721086 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8912 16:55:38.723580 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8913 16:55:38.724161 ==
8914 16:55:38.726453 Dram Type= 6, Freq= 0, CH_1, rank 1
8915 16:55:38.730456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8916 16:55:38.730881 ==
8917 16:55:38.744368
8918 16:55:38.747006 TX Vref early break, caculate TX vref
8919 16:55:38.751213 TX Vref=16, minBit 9, minWin=22, winSum=383
8920 16:55:38.753643 TX Vref=18, minBit 9, minWin=22, winSum=388
8921 16:55:38.756891 TX Vref=20, minBit 9, minWin=23, winSum=396
8922 16:55:38.760723 TX Vref=22, minBit 9, minWin=24, winSum=409
8923 16:55:38.763574 TX Vref=24, minBit 11, minWin=24, winSum=416
8924 16:55:38.770447 TX Vref=26, minBit 8, minWin=25, winSum=417
8925 16:55:38.773678 TX Vref=28, minBit 9, minWin=24, winSum=417
8926 16:55:38.777342 TX Vref=30, minBit 8, minWin=24, winSum=408
8927 16:55:38.780162 TX Vref=32, minBit 0, minWin=24, winSum=405
8928 16:55:38.783233 TX Vref=34, minBit 9, minWin=23, winSum=392
8929 16:55:38.789782 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 26
8930 16:55:38.790400
8931 16:55:38.793380 Final TX Range 0 Vref 26
8932 16:55:38.793888
8933 16:55:38.794270 ==
8934 16:55:38.796657 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 16:55:38.799888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 16:55:38.800393 ==
8937 16:55:38.800772
8938 16:55:38.801122
8939 16:55:38.803185 TX Vref Scan disable
8940 16:55:38.810050 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8941 16:55:38.810705 == TX Byte 0 ==
8942 16:55:38.813120 u2DelayCellOfst[0]=17 cells (5 PI)
8943 16:55:38.816099 u2DelayCellOfst[1]=13 cells (4 PI)
8944 16:55:38.819580 u2DelayCellOfst[2]=0 cells (0 PI)
8945 16:55:38.822956 u2DelayCellOfst[3]=6 cells (2 PI)
8946 16:55:38.826779 u2DelayCellOfst[4]=10 cells (3 PI)
8947 16:55:38.829620 u2DelayCellOfst[5]=20 cells (6 PI)
8948 16:55:38.832742 u2DelayCellOfst[6]=17 cells (5 PI)
8949 16:55:38.837086 u2DelayCellOfst[7]=6 cells (2 PI)
8950 16:55:38.839177 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8951 16:55:38.843018 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8952 16:55:38.845918 == TX Byte 1 ==
8953 16:55:38.849437 u2DelayCellOfst[8]=0 cells (0 PI)
8954 16:55:38.852739 u2DelayCellOfst[9]=0 cells (0 PI)
8955 16:55:38.855936 u2DelayCellOfst[10]=10 cells (3 PI)
8956 16:55:38.856515 u2DelayCellOfst[11]=0 cells (0 PI)
8957 16:55:38.859230 u2DelayCellOfst[12]=10 cells (3 PI)
8958 16:55:38.862716 u2DelayCellOfst[13]=13 cells (4 PI)
8959 16:55:38.866318 u2DelayCellOfst[14]=17 cells (5 PI)
8960 16:55:38.870306 u2DelayCellOfst[15]=13 cells (4 PI)
8961 16:55:38.876058 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8962 16:55:38.879339 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8963 16:55:38.879918 DramC Write-DBI on
8964 16:55:38.880299 ==
8965 16:55:38.882812 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 16:55:38.889100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 16:55:38.889688 ==
8968 16:55:38.890073
8969 16:55:38.890474
8970 16:55:38.892436 TX Vref Scan disable
8971 16:55:38.893018 == TX Byte 0 ==
8972 16:55:38.898929 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8973 16:55:38.899407 == TX Byte 1 ==
8974 16:55:38.902065 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8975 16:55:38.905827 DramC Write-DBI off
8976 16:55:38.906451
8977 16:55:38.906971 [DATLAT]
8978 16:55:38.908972 Freq=1600, CH1 RK1
8979 16:55:38.909590
8980 16:55:38.909974 DATLAT Default: 0xf
8981 16:55:38.912083 0, 0xFFFF, sum = 0
8982 16:55:38.912539 1, 0xFFFF, sum = 0
8983 16:55:38.915182 2, 0xFFFF, sum = 0
8984 16:55:38.915775 3, 0xFFFF, sum = 0
8985 16:55:38.918644 4, 0xFFFF, sum = 0
8986 16:55:38.919127 5, 0xFFFF, sum = 0
8987 16:55:38.921720 6, 0xFFFF, sum = 0
8988 16:55:38.922201 7, 0xFFFF, sum = 0
8989 16:55:38.925442 8, 0xFFFF, sum = 0
8990 16:55:38.926027 9, 0xFFFF, sum = 0
8991 16:55:38.928439 10, 0xFFFF, sum = 0
8992 16:55:38.932132 11, 0xFFFF, sum = 0
8993 16:55:38.932717 12, 0xFFFF, sum = 0
8994 16:55:38.935183 13, 0xFFFF, sum = 0
8995 16:55:38.935666 14, 0x0, sum = 1
8996 16:55:38.938527 15, 0x0, sum = 2
8997 16:55:38.939110 16, 0x0, sum = 3
8998 16:55:38.941518 17, 0x0, sum = 4
8999 16:55:38.942107 best_step = 15
9000 16:55:38.942535
9001 16:55:38.942898 ==
9002 16:55:38.945122 Dram Type= 6, Freq= 0, CH_1, rank 1
9003 16:55:38.947999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9004 16:55:38.948490 ==
9005 16:55:38.951755 RX Vref Scan: 0
9006 16:55:38.952336
9007 16:55:38.955258 RX Vref 0 -> 0, step: 1
9008 16:55:38.955830
9009 16:55:38.956213 RX Delay 19 -> 252, step: 4
9010 16:55:38.962299 iDelay=195, Bit 0, Center 136 (95 ~ 178) 84
9011 16:55:38.965254 iDelay=195, Bit 1, Center 130 (87 ~ 174) 88
9012 16:55:38.968665 iDelay=195, Bit 2, Center 120 (75 ~ 166) 92
9013 16:55:38.972244 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9014 16:55:38.975633 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9015 16:55:38.982159 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9016 16:55:38.984817 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
9017 16:55:38.988312 iDelay=195, Bit 7, Center 132 (87 ~ 178) 92
9018 16:55:38.991383 iDelay=195, Bit 8, Center 114 (67 ~ 162) 96
9019 16:55:38.995006 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9020 16:55:39.001126 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9021 16:55:39.004836 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9022 16:55:39.008510 iDelay=195, Bit 12, Center 140 (91 ~ 190) 100
9023 16:55:39.011351 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9024 16:55:39.014601 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9025 16:55:39.021325 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9026 16:55:39.022002 ==
9027 16:55:39.024358 Dram Type= 6, Freq= 0, CH_1, rank 1
9028 16:55:39.027520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9029 16:55:39.027997 ==
9030 16:55:39.028376 DQS Delay:
9031 16:55:39.031220 DQS0 = 0, DQS1 = 0
9032 16:55:39.031745 DQM Delay:
9033 16:55:39.034385 DQM0 = 133, DQM1 = 131
9034 16:55:39.034971 DQ Delay:
9035 16:55:39.037953 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
9036 16:55:39.040956 DQ4 =134, DQ5 =146, DQ6 =142, DQ7 =132
9037 16:55:39.044313 DQ8 =114, DQ9 =120, DQ10 =132, DQ11 =126
9038 16:55:39.047840 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
9039 16:55:39.051028
9040 16:55:39.051505
9041 16:55:39.051884
9042 16:55:39.052231 [DramC_TX_OE_Calibration] TA2
9043 16:55:39.054059 Original DQ_B0 (3 6) =30, OEN = 27
9044 16:55:39.057876 Original DQ_B1 (3 6) =30, OEN = 27
9045 16:55:39.061136 24, 0x0, End_B0=24 End_B1=24
9046 16:55:39.064366 25, 0x0, End_B0=25 End_B1=25
9047 16:55:39.067052 26, 0x0, End_B0=26 End_B1=26
9048 16:55:39.067537 27, 0x0, End_B0=27 End_B1=27
9049 16:55:39.071247 28, 0x0, End_B0=28 End_B1=28
9050 16:55:39.073971 29, 0x0, End_B0=29 End_B1=29
9051 16:55:39.077168 30, 0x0, End_B0=30 End_B1=30
9052 16:55:39.080893 31, 0x5151, End_B0=30 End_B1=30
9053 16:55:39.083861 Byte0 end_step=30 best_step=27
9054 16:55:39.084442 Byte1 end_step=30 best_step=27
9055 16:55:39.087082 Byte0 TX OE(2T, 0.5T) = (3, 3)
9056 16:55:39.091113 Byte1 TX OE(2T, 0.5T) = (3, 3)
9057 16:55:39.091587
9058 16:55:39.091984
9059 16:55:39.100590 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9060 16:55:39.101196 CH1 RK1: MR19=303, MR18=1C07
9061 16:55:39.107423 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9062 16:55:39.110645 [RxdqsGatingPostProcess] freq 1600
9063 16:55:39.116819 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9064 16:55:39.120511 best DQS0 dly(2T, 0.5T) = (1, 1)
9065 16:55:39.124084 best DQS1 dly(2T, 0.5T) = (1, 1)
9066 16:55:39.128599 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9067 16:55:39.130024 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9068 16:55:39.130664 best DQS0 dly(2T, 0.5T) = (1, 1)
9069 16:55:39.133358 best DQS1 dly(2T, 0.5T) = (1, 1)
9070 16:55:39.136491 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9071 16:55:39.140660 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9072 16:55:39.143358 Pre-setting of DQS Precalculation
9073 16:55:39.149851 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9074 16:55:39.156290 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9075 16:55:39.163469 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9076 16:55:39.164051
9077 16:55:39.164433
9078 16:55:39.166469 [Calibration Summary] 3200 Mbps
9079 16:55:39.167048 CH 0, Rank 0
9080 16:55:39.170271 SW Impedance : PASS
9081 16:55:39.173071 DUTY Scan : NO K
9082 16:55:39.173651 ZQ Calibration : PASS
9083 16:55:39.177048 Jitter Meter : NO K
9084 16:55:39.179921 CBT Training : PASS
9085 16:55:39.180502 Write leveling : PASS
9086 16:55:39.183441 RX DQS gating : PASS
9087 16:55:39.186399 RX DQ/DQS(RDDQC) : PASS
9088 16:55:39.186988 TX DQ/DQS : PASS
9089 16:55:39.189598 RX DATLAT : PASS
9090 16:55:39.193050 RX DQ/DQS(Engine): PASS
9091 16:55:39.193536 TX OE : PASS
9092 16:55:39.195923 All Pass.
9093 16:55:39.196405
9094 16:55:39.196784 CH 0, Rank 1
9095 16:55:39.199735 SW Impedance : PASS
9096 16:55:39.200257 DUTY Scan : NO K
9097 16:55:39.202515 ZQ Calibration : PASS
9098 16:55:39.206230 Jitter Meter : NO K
9099 16:55:39.206855 CBT Training : PASS
9100 16:55:39.209420 Write leveling : PASS
9101 16:55:39.213081 RX DQS gating : PASS
9102 16:55:39.213661 RX DQ/DQS(RDDQC) : PASS
9103 16:55:39.215926 TX DQ/DQS : PASS
9104 16:55:39.216404 RX DATLAT : PASS
9105 16:55:39.219671 RX DQ/DQS(Engine): PASS
9106 16:55:39.222527 TX OE : PASS
9107 16:55:39.223107 All Pass.
9108 16:55:39.223495
9109 16:55:39.223846 CH 1, Rank 0
9110 16:55:39.226289 SW Impedance : PASS
9111 16:55:39.229208 DUTY Scan : NO K
9112 16:55:39.229786 ZQ Calibration : PASS
9113 16:55:39.232430 Jitter Meter : NO K
9114 16:55:39.235757 CBT Training : PASS
9115 16:55:39.236336 Write leveling : PASS
9116 16:55:39.238886 RX DQS gating : PASS
9117 16:55:39.242554 RX DQ/DQS(RDDQC) : PASS
9118 16:55:39.243182 TX DQ/DQS : PASS
9119 16:55:39.245314 RX DATLAT : PASS
9120 16:55:39.249123 RX DQ/DQS(Engine): PASS
9121 16:55:39.249714 TX OE : PASS
9122 16:55:39.252149 All Pass.
9123 16:55:39.252727
9124 16:55:39.253170 CH 1, Rank 1
9125 16:55:39.255502 SW Impedance : PASS
9126 16:55:39.256101 DUTY Scan : NO K
9127 16:55:39.258721 ZQ Calibration : PASS
9128 16:55:39.262224 Jitter Meter : NO K
9129 16:55:39.262831 CBT Training : PASS
9130 16:55:39.265675 Write leveling : PASS
9131 16:55:39.268847 RX DQS gating : PASS
9132 16:55:39.269426 RX DQ/DQS(RDDQC) : PASS
9133 16:55:39.272300 TX DQ/DQS : PASS
9134 16:55:39.275228 RX DATLAT : PASS
9135 16:55:39.275804 RX DQ/DQS(Engine): PASS
9136 16:55:39.278530 TX OE : PASS
9137 16:55:39.279093 All Pass.
9138 16:55:39.279469
9139 16:55:39.281659 DramC Write-DBI on
9140 16:55:39.285425 PER_BANK_REFRESH: Hybrid Mode
9141 16:55:39.285995 TX_TRACKING: ON
9142 16:55:39.295145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9143 16:55:39.301767 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9144 16:55:39.308488 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9145 16:55:39.311903 [FAST_K] Save calibration result to emmc
9146 16:55:39.314612 sync common calibartion params.
9147 16:55:39.318395 sync cbt_mode0:1, 1:1
9148 16:55:39.322058 dram_init: ddr_geometry: 2
9149 16:55:39.322651 dram_init: ddr_geometry: 2
9150 16:55:39.325001 dram_init: ddr_geometry: 2
9151 16:55:39.327928 0:dram_rank_size:100000000
9152 16:55:39.331267 1:dram_rank_size:100000000
9153 16:55:39.335074 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9154 16:55:39.337955 DFS_SHUFFLE_HW_MODE: ON
9155 16:55:39.341070 dramc_set_vcore_voltage set vcore to 725000
9156 16:55:39.344946 Read voltage for 1600, 0
9157 16:55:39.345514 Vio18 = 0
9158 16:55:39.345890 Vcore = 725000
9159 16:55:39.348070 Vdram = 0
9160 16:55:39.348536 Vddq = 0
9161 16:55:39.348909 Vmddr = 0
9162 16:55:39.351174 switch to 3200 Mbps bootup
9163 16:55:39.354611 [DramcRunTimeConfig]
9164 16:55:39.355174 PHYPLL
9165 16:55:39.355552 DPM_CONTROL_AFTERK: ON
9166 16:55:39.357620 PER_BANK_REFRESH: ON
9167 16:55:39.361097 REFRESH_OVERHEAD_REDUCTION: ON
9168 16:55:39.361663 CMD_PICG_NEW_MODE: OFF
9169 16:55:39.364280 XRTWTW_NEW_MODE: ON
9170 16:55:39.367643 XRTRTR_NEW_MODE: ON
9171 16:55:39.368346 TX_TRACKING: ON
9172 16:55:39.370993 RDSEL_TRACKING: OFF
9173 16:55:39.371461 DQS Precalculation for DVFS: ON
9174 16:55:39.374114 RX_TRACKING: OFF
9175 16:55:39.374615 HW_GATING DBG: ON
9176 16:55:39.377515 ZQCS_ENABLE_LP4: ON
9177 16:55:39.377984 RX_PICG_NEW_MODE: ON
9178 16:55:39.380976 TX_PICG_NEW_MODE: ON
9179 16:55:39.384753 ENABLE_RX_DCM_DPHY: ON
9180 16:55:39.387565 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9181 16:55:39.388040 DUMMY_READ_FOR_TRACKING: OFF
9182 16:55:39.391237 !!! SPM_CONTROL_AFTERK: OFF
9183 16:55:39.394749 !!! SPM could not control APHY
9184 16:55:39.397859 IMPEDANCE_TRACKING: ON
9185 16:55:39.398478 TEMP_SENSOR: ON
9186 16:55:39.400751 HW_SAVE_FOR_SR: OFF
9187 16:55:39.401219 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9188 16:55:39.407590 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9189 16:55:39.408161 Read ODT Tracking: ON
9190 16:55:39.410900 Refresh Rate DeBounce: ON
9191 16:55:39.414171 DFS_NO_QUEUE_FLUSH: ON
9192 16:55:39.417143 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9193 16:55:39.417610 ENABLE_DFS_RUNTIME_MRW: OFF
9194 16:55:39.421191 DDR_RESERVE_NEW_MODE: ON
9195 16:55:39.424024 MR_CBT_SWITCH_FREQ: ON
9196 16:55:39.424490 =========================
9197 16:55:39.444138 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9198 16:55:39.447098 dram_init: ddr_geometry: 2
9199 16:55:39.465020 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9200 16:55:39.468629 dram_init: dram init end (result: 0)
9201 16:55:39.475132 DRAM-K: Full calibration passed in 24457 msecs
9202 16:55:39.478141 MRC: failed to locate region type 0.
9203 16:55:39.478667 DRAM rank0 size:0x100000000,
9204 16:55:39.481634 DRAM rank1 size=0x100000000
9205 16:55:39.491961 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9206 16:55:39.498684 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9207 16:55:39.504925 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9208 16:55:39.511579 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9209 16:55:39.514971 DRAM rank0 size:0x100000000,
9210 16:55:39.518694 DRAM rank1 size=0x100000000
9211 16:55:39.519268 CBMEM:
9212 16:55:39.521637 IMD: root @ 0xfffff000 254 entries.
9213 16:55:39.524885 IMD: root @ 0xffffec00 62 entries.
9214 16:55:39.527860 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9215 16:55:39.531431 WARNING: RO_VPD is uninitialized or empty.
9216 16:55:39.538074 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9217 16:55:39.545724 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9218 16:55:39.558321 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9219 16:55:39.569816 BS: romstage times (exec / console): total (unknown) / 23965 ms
9220 16:55:39.570448
9221 16:55:39.570840
9222 16:55:39.579209 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9223 16:55:39.582737 ARM64: Exception handlers installed.
9224 16:55:39.585786 ARM64: Testing exception
9225 16:55:39.589507 ARM64: Done test exception
9226 16:55:39.589982 Enumerating buses...
9227 16:55:39.592681 Show all devs... Before device enumeration.
9228 16:55:39.596258 Root Device: enabled 1
9229 16:55:39.599221 CPU_CLUSTER: 0: enabled 1
9230 16:55:39.599696 CPU: 00: enabled 1
9231 16:55:39.602551 Compare with tree...
9232 16:55:39.603026 Root Device: enabled 1
9233 16:55:39.605789 CPU_CLUSTER: 0: enabled 1
9234 16:55:39.608947 CPU: 00: enabled 1
9235 16:55:39.609516 Root Device scanning...
9236 16:55:39.612400 scan_static_bus for Root Device
9237 16:55:39.615776 CPU_CLUSTER: 0 enabled
9238 16:55:39.619007 scan_static_bus for Root Device done
9239 16:55:39.622534 scan_bus: bus Root Device finished in 8 msecs
9240 16:55:39.623104 done
9241 16:55:39.628643 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9242 16:55:39.632079 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9243 16:55:39.638582 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9244 16:55:39.644897 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9245 16:55:39.645457 Allocating resources...
9246 16:55:39.648596 Reading resources...
9247 16:55:39.651777 Root Device read_resources bus 0 link: 0
9248 16:55:39.654945 DRAM rank0 size:0x100000000,
9249 16:55:39.655513 DRAM rank1 size=0x100000000
9250 16:55:39.661672 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9251 16:55:39.662249 CPU: 00 missing read_resources
9252 16:55:39.668384 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9253 16:55:39.671581 Root Device read_resources bus 0 link: 0 done
9254 16:55:39.674699 Done reading resources.
9255 16:55:39.678040 Show resources in subtree (Root Device)...After reading.
9256 16:55:39.681399 Root Device child on link 0 CPU_CLUSTER: 0
9257 16:55:39.684372 CPU_CLUSTER: 0 child on link 0 CPU: 00
9258 16:55:39.694429 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9259 16:55:39.694911 CPU: 00
9260 16:55:39.700773 Root Device assign_resources, bus 0 link: 0
9261 16:55:39.704324 CPU_CLUSTER: 0 missing set_resources
9262 16:55:39.707643 Root Device assign_resources, bus 0 link: 0 done
9263 16:55:39.711615 Done setting resources.
9264 16:55:39.715259 Show resources in subtree (Root Device)...After assigning values.
9265 16:55:39.717452 Root Device child on link 0 CPU_CLUSTER: 0
9266 16:55:39.724293 CPU_CLUSTER: 0 child on link 0 CPU: 00
9267 16:55:39.730778 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9268 16:55:39.734528 CPU: 00
9269 16:55:39.735091 Done allocating resources.
9270 16:55:39.741354 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9271 16:55:39.741928 Enabling resources...
9272 16:55:39.745070 done.
9273 16:55:39.747202 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9274 16:55:39.750923 Initializing devices...
9275 16:55:39.751492 Root Device init
9276 16:55:39.754086 init hardware done!
9277 16:55:39.754701 0x00000018: ctrlr->caps
9278 16:55:39.757632 52.000 MHz: ctrlr->f_max
9279 16:55:39.760606 0.400 MHz: ctrlr->f_min
9280 16:55:39.761194 0x40ff8080: ctrlr->voltages
9281 16:55:39.764005 sclk: 390625
9282 16:55:39.764566 Bus Width = 1
9283 16:55:39.767049 sclk: 390625
9284 16:55:39.767521 Bus Width = 1
9285 16:55:39.770529 Early init status = 3
9286 16:55:39.773868 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9287 16:55:39.777244 in-header: 03 fc 00 00 01 00 00 00
9288 16:55:39.780497 in-data: 00
9289 16:55:39.784125 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9290 16:55:39.788337 in-header: 03 fd 00 00 00 00 00 00
9291 16:55:39.791165 in-data:
9292 16:55:39.794575 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9293 16:55:39.798558 in-header: 03 fc 00 00 01 00 00 00
9294 16:55:39.801617 in-data: 00
9295 16:55:39.804808 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9296 16:55:39.810167 in-header: 03 fd 00 00 00 00 00 00
9297 16:55:39.813839 in-data:
9298 16:55:39.816788 [SSUSB] Setting up USB HOST controller...
9299 16:55:39.820298 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9300 16:55:39.823297 [SSUSB] phy power-on done.
9301 16:55:39.826890 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9302 16:55:39.833832 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9303 16:55:39.837450 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9304 16:55:39.843460 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9305 16:55:39.850720 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9306 16:55:39.856702 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9307 16:55:39.863517 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9308 16:55:39.869913 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9309 16:55:39.873253 SPM: binary array size = 0x9dc
9310 16:55:39.876533 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9311 16:55:39.883210 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9312 16:55:39.890136 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9313 16:55:39.896199 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9314 16:55:39.899388 configure_display: Starting display init
9315 16:55:39.933396 anx7625_power_on_init: Init interface.
9316 16:55:39.937025 anx7625_disable_pd_protocol: Disabled PD feature.
9317 16:55:39.940234 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9318 16:55:39.967911 anx7625_start_dp_work: Secure OCM version=00
9319 16:55:39.971225 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9320 16:55:39.986942 sp_tx_get_edid_block: EDID Block = 1
9321 16:55:40.089153 Extracted contents:
9322 16:55:40.092154 header: 00 ff ff ff ff ff ff 00
9323 16:55:40.095383 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9324 16:55:40.098733 version: 01 04
9325 16:55:40.101690 basic params: 95 1f 11 78 0a
9326 16:55:40.105263 chroma info: 76 90 94 55 54 90 27 21 50 54
9327 16:55:40.108283 established: 00 00 00
9328 16:55:40.114878 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9329 16:55:40.121877 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9330 16:55:40.124752 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9331 16:55:40.131304 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9332 16:55:40.138040 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9333 16:55:40.141562 extensions: 00
9334 16:55:40.142100 checksum: fb
9335 16:55:40.142697
9336 16:55:40.148076 Manufacturer: IVO Model 57d Serial Number 0
9337 16:55:40.148673 Made week 0 of 2020
9338 16:55:40.151298 EDID version: 1.4
9339 16:55:40.151875 Digital display
9340 16:55:40.154713 6 bits per primary color channel
9341 16:55:40.155301 DisplayPort interface
9342 16:55:40.157742 Maximum image size: 31 cm x 17 cm
9343 16:55:40.161133 Gamma: 220%
9344 16:55:40.161610 Check DPMS levels
9345 16:55:40.167638 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9346 16:55:40.171246 First detailed timing is preferred timing
9347 16:55:40.171834 Established timings supported:
9348 16:55:40.174675 Standard timings supported:
9349 16:55:40.178160 Detailed timings
9350 16:55:40.181076 Hex of detail: 383680a07038204018303c0035ae10000019
9351 16:55:40.188994 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9352 16:55:40.190843 0780 0798 07c8 0820 hborder 0
9353 16:55:40.194180 0438 043b 0447 0458 vborder 0
9354 16:55:40.197666 -hsync -vsync
9355 16:55:40.198244 Did detailed timing
9356 16:55:40.204261 Hex of detail: 000000000000000000000000000000000000
9357 16:55:40.207885 Manufacturer-specified data, tag 0
9358 16:55:40.210916 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9359 16:55:40.213810 ASCII string: InfoVision
9360 16:55:40.217380 Hex of detail: 000000fe00523134304e574635205248200a
9361 16:55:40.220563 ASCII string: R140NWF5 RH
9362 16:55:40.221025 Checksum
9363 16:55:40.224413 Checksum: 0xfb (valid)
9364 16:55:40.227437 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9365 16:55:40.230444 DSI data_rate: 832800000 bps
9366 16:55:40.237629 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9367 16:55:40.240385 anx7625_parse_edid: pixelclock(138800).
9368 16:55:40.243778 hactive(1920), hsync(48), hfp(24), hbp(88)
9369 16:55:40.246956 vactive(1080), vsync(12), vfp(3), vbp(17)
9370 16:55:40.250528 anx7625_dsi_config: config dsi.
9371 16:55:40.257376 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9372 16:55:40.270573 anx7625_dsi_config: success to config DSI
9373 16:55:40.274264 anx7625_dp_start: MIPI phy setup OK.
9374 16:55:40.277483 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9375 16:55:40.280841 mtk_ddp_mode_set invalid vrefresh 60
9376 16:55:40.284166 main_disp_path_setup
9377 16:55:40.284728 ovl_layer_smi_id_en
9378 16:55:40.286891 ovl_layer_smi_id_en
9379 16:55:40.287355 ccorr_config
9380 16:55:40.287723 aal_config
9381 16:55:40.290520 gamma_config
9382 16:55:40.291087 postmask_config
9383 16:55:40.293689 dither_config
9384 16:55:40.296809 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9385 16:55:40.303757 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9386 16:55:40.307384 Root Device init finished in 552 msecs
9387 16:55:40.310434 CPU_CLUSTER: 0 init
9388 16:55:40.316901 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9389 16:55:40.323924 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9390 16:55:40.324493 APU_MBOX 0x190000b0 = 0x10001
9391 16:55:40.326807 APU_MBOX 0x190001b0 = 0x10001
9392 16:55:40.330163 APU_MBOX 0x190005b0 = 0x10001
9393 16:55:40.333859 APU_MBOX 0x190006b0 = 0x10001
9394 16:55:40.339823 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9395 16:55:40.349348 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9396 16:55:40.362034 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9397 16:55:40.368870 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9398 16:55:40.380513 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9399 16:55:40.389588 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9400 16:55:40.392365 CPU_CLUSTER: 0 init finished in 81 msecs
9401 16:55:40.396168 Devices initialized
9402 16:55:40.399906 Show all devs... After init.
9403 16:55:40.400487 Root Device: enabled 1
9404 16:55:40.402977 CPU_CLUSTER: 0: enabled 1
9405 16:55:40.406305 CPU: 00: enabled 1
9406 16:55:40.409501 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9407 16:55:40.412570 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9408 16:55:40.416762 ELOG: NV offset 0x57f000 size 0x1000
9409 16:55:40.422637 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9410 16:55:40.429058 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9411 16:55:40.433006 ELOG: Event(17) added with size 13 at 2023-06-03 16:55:40 UTC
9412 16:55:40.438788 out: cmd=0x121: 03 db 21 01 00 00 00 00
9413 16:55:40.442554 in-header: 03 5a 00 00 2c 00 00 00
9414 16:55:40.455808 in-data: 05 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9415 16:55:40.458645 ELOG: Event(A1) added with size 10 at 2023-06-03 16:55:40 UTC
9416 16:55:40.465711 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9417 16:55:40.472248 ELOG: Event(A0) added with size 9 at 2023-06-03 16:55:40 UTC
9418 16:55:40.474920 elog_add_boot_reason: Logged dev mode boot
9419 16:55:40.482693 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9420 16:55:40.483271 Finalize devices...
9421 16:55:40.485344 Devices finalized
9422 16:55:40.488738 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9423 16:55:40.491717 Writing coreboot table at 0xffe64000
9424 16:55:40.498610 0. 000000000010a000-0000000000113fff: RAMSTAGE
9425 16:55:40.502213 1. 0000000040000000-00000000400fffff: RAM
9426 16:55:40.504900 2. 0000000040100000-000000004032afff: RAMSTAGE
9427 16:55:40.508321 3. 000000004032b000-00000000545fffff: RAM
9428 16:55:40.512006 4. 0000000054600000-000000005465ffff: BL31
9429 16:55:40.517815 5. 0000000054660000-00000000ffe63fff: RAM
9430 16:55:40.521646 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9431 16:55:40.524839 7. 0000000100000000-000000023fffffff: RAM
9432 16:55:40.528065 Passing 5 GPIOs to payload:
9433 16:55:40.534531 NAME | PORT | POLARITY | VALUE
9434 16:55:40.538128 EC in RW | 0x000000aa | low | undefined
9435 16:55:40.541221 EC interrupt | 0x00000005 | low | undefined
9436 16:55:40.547727 TPM interrupt | 0x000000ab | high | undefined
9437 16:55:40.551182 SD card detect | 0x00000011 | high | undefined
9438 16:55:40.557442 speaker enable | 0x00000093 | high | undefined
9439 16:55:40.560977 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9440 16:55:40.564882 in-header: 03 f9 00 00 02 00 00 00
9441 16:55:40.565486 in-data: 02 00
9442 16:55:40.567758 ADC[4]: Raw value=901032 ID=7
9443 16:55:40.571170 ADC[3]: Raw value=213179 ID=1
9444 16:55:40.571767 RAM Code: 0x71
9445 16:55:40.574267 ADC[6]: Raw value=74502 ID=0
9446 16:55:40.577572 ADC[5]: Raw value=212441 ID=1
9447 16:55:40.578154 SKU Code: 0x1
9448 16:55:40.584012 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9449 16:55:40.587845 coreboot table: 964 bytes.
9450 16:55:40.590802 IMD ROOT 0. 0xfffff000 0x00001000
9451 16:55:40.593711 IMD SMALL 1. 0xffffe000 0x00001000
9452 16:55:40.597226 RO MCACHE 2. 0xffffc000 0x00001104
9453 16:55:40.600545 CONSOLE 3. 0xfff7c000 0x00080000
9454 16:55:40.603994 FMAP 4. 0xfff7b000 0x00000452
9455 16:55:40.606802 TIME STAMP 5. 0xfff7a000 0x00000910
9456 16:55:40.610705 VBOOT WORK 6. 0xfff66000 0x00014000
9457 16:55:40.614273 RAMOOPS 7. 0xffe66000 0x00100000
9458 16:55:40.617558 COREBOOT 8. 0xffe64000 0x00002000
9459 16:55:40.618150 IMD small region:
9460 16:55:40.620078 IMD ROOT 0. 0xffffec00 0x00000400
9461 16:55:40.623695 VPD 1. 0xffffeba0 0x0000004c
9462 16:55:40.627307 MMC STATUS 2. 0xffffeb80 0x00000004
9463 16:55:40.634294 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9464 16:55:40.634919 Probing TPM: done!
9465 16:55:40.640422 Connected to device vid:did:rid of 1ae0:0028:00
9466 16:55:40.647407 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9467 16:55:40.654738 Initialized TPM device CR50 revision 0
9468 16:55:40.655319 Checking cr50 for pending updates
9469 16:55:40.660027 Reading cr50 TPM mode
9470 16:55:40.669042 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9471 16:55:40.675045 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9472 16:55:40.715659 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9473 16:55:40.719285 Checking segment from ROM address 0x40100000
9474 16:55:40.722333 Checking segment from ROM address 0x4010001c
9475 16:55:40.728565 Loading segment from ROM address 0x40100000
9476 16:55:40.729148 code (compression=0)
9477 16:55:40.738522 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9478 16:55:40.745287 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9479 16:55:40.745874 it's not compressed!
9480 16:55:40.752152 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9481 16:55:40.758564 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9482 16:55:40.776060 Loading segment from ROM address 0x4010001c
9483 16:55:40.776658 Entry Point 0x80000000
9484 16:55:40.779356 Loaded segments
9485 16:55:40.782454 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9486 16:55:40.789220 Jumping to boot code at 0x80000000(0xffe64000)
9487 16:55:40.795477 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9488 16:55:40.802029 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9489 16:55:40.810013 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9490 16:55:40.813532 Checking segment from ROM address 0x40100000
9491 16:55:40.816551 Checking segment from ROM address 0x4010001c
9492 16:55:40.823025 Loading segment from ROM address 0x40100000
9493 16:55:40.823514 code (compression=1)
9494 16:55:40.830239 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9495 16:55:40.839749 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9496 16:55:40.840335 using LZMA
9497 16:55:40.848999 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9498 16:55:40.855587 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9499 16:55:40.858845 Loading segment from ROM address 0x4010001c
9500 16:55:40.859432 Entry Point 0x54601000
9501 16:55:40.862233 Loaded segments
9502 16:55:40.865159 NOTICE: MT8192 bl31_setup
9503 16:55:40.872238 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9504 16:55:40.876254 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9505 16:55:40.879599 WARNING: region 0:
9506 16:55:40.881788 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9507 16:55:40.882278 WARNING: region 1:
9508 16:55:40.889124 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9509 16:55:40.892071 WARNING: region 2:
9510 16:55:40.895114 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9511 16:55:40.898792 WARNING: region 3:
9512 16:55:40.902089 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9513 16:55:40.905160 WARNING: region 4:
9514 16:55:40.911839 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9515 16:55:40.912334 WARNING: region 5:
9516 16:55:40.915631 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9517 16:55:40.918841 WARNING: region 6:
9518 16:55:40.922263 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9519 16:55:40.925034 WARNING: region 7:
9520 16:55:40.929063 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 16:55:40.935129 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9522 16:55:40.939202 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9523 16:55:40.942135 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9524 16:55:40.948532 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9525 16:55:40.951485 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9526 16:55:40.958342 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9527 16:55:40.962071 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9528 16:55:40.965159 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9529 16:55:40.972171 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9530 16:55:40.974904 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9531 16:55:40.978571 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9532 16:55:40.985063 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9533 16:55:40.988591 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9534 16:55:40.994851 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9535 16:55:40.998091 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9536 16:55:41.001699 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9537 16:55:41.008055 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9538 16:55:41.011536 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9539 16:55:41.014897 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9540 16:55:41.021158 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9541 16:55:41.024763 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9542 16:55:41.031246 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9543 16:55:41.035006 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9544 16:55:41.038575 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9545 16:55:41.044624 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9546 16:55:41.047989 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9547 16:55:41.054999 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9548 16:55:41.058164 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9549 16:55:41.061214 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9550 16:55:41.068270 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9551 16:55:41.071134 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9552 16:55:41.077952 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9553 16:55:41.081212 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9554 16:55:41.084295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9555 16:55:41.087922 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9556 16:55:41.094586 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9557 16:55:41.098067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9558 16:55:41.100911 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9559 16:55:41.104072 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9560 16:55:41.111001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9561 16:55:41.114060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9562 16:55:41.117572 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9563 16:55:41.120623 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9564 16:55:41.128266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9565 16:55:41.130597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9566 16:55:41.134083 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9567 16:55:41.137561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9568 16:55:41.144514 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9569 16:55:41.147509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9570 16:55:41.154194 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9571 16:55:41.157418 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9572 16:55:41.161606 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9573 16:55:41.167781 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9574 16:55:41.170581 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9575 16:55:41.177755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9576 16:55:41.180810 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9577 16:55:41.187139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9578 16:55:41.190613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9579 16:55:41.194392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9580 16:55:41.200861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9581 16:55:41.203535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9582 16:55:41.210986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9583 16:55:41.213477 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9584 16:55:41.220291 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9585 16:55:41.223603 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9586 16:55:41.230693 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9587 16:55:41.233828 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9588 16:55:41.236995 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9589 16:55:41.243769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9590 16:55:41.246876 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9591 16:55:41.253724 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9592 16:55:41.256750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9593 16:55:41.263752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9594 16:55:41.267081 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9595 16:55:41.270932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9596 16:55:41.277308 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9597 16:55:41.280596 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9598 16:55:41.287255 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9599 16:55:41.290333 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9600 16:55:41.296533 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9601 16:55:41.299931 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9602 16:55:41.306860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9603 16:55:41.310021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9604 16:55:41.313413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9605 16:55:41.320086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9606 16:55:41.323504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9607 16:55:41.330169 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9608 16:55:41.333218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9609 16:55:41.340357 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9610 16:55:41.344078 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9611 16:55:41.346417 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9612 16:55:41.353832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9613 16:55:41.356447 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9614 16:55:41.363051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9615 16:55:41.366580 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9616 16:55:41.373399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9617 16:55:41.376824 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9618 16:55:41.380331 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9619 16:55:41.383668 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9620 16:55:41.389939 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9621 16:55:41.393256 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9622 16:55:41.396493 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9623 16:55:41.403091 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9624 16:55:41.406582 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9625 16:55:41.412970 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9626 16:55:41.416946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9627 16:55:41.419723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9628 16:55:41.426253 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9629 16:55:41.429859 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9630 16:55:41.436726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9631 16:55:41.439402 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9632 16:55:41.443720 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9633 16:55:41.449762 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9634 16:55:41.453017 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9635 16:55:41.459927 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9636 16:55:41.463198 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9637 16:55:41.466581 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9638 16:55:41.469324 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9639 16:55:41.476893 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9640 16:55:41.479522 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9641 16:55:41.482853 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9642 16:55:41.489581 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9643 16:55:41.493208 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9644 16:55:41.496356 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9645 16:55:41.499666 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9646 16:55:41.506325 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9647 16:55:41.509521 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9648 16:55:41.516137 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9649 16:55:41.519505 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9650 16:55:41.522650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9651 16:55:41.529581 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9652 16:55:41.532616 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9653 16:55:41.539310 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9654 16:55:41.542865 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9655 16:55:41.546082 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9656 16:55:41.552987 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9657 16:55:41.555697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9658 16:55:41.562829 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9659 16:55:41.566088 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9660 16:55:41.568686 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9661 16:55:41.576278 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9662 16:55:41.578822 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9663 16:55:41.585807 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9664 16:55:41.589092 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9665 16:55:41.592366 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9666 16:55:41.598780 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9667 16:55:41.602146 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9668 16:55:41.605591 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9669 16:55:41.612783 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9670 16:55:41.615928 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9671 16:55:41.622574 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9672 16:55:41.625495 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9673 16:55:41.628777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9674 16:55:41.635404 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9675 16:55:41.638875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9676 16:55:41.645953 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9677 16:55:41.649006 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9678 16:55:41.651793 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9679 16:55:41.658241 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9680 16:55:41.662096 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9681 16:55:41.668575 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9682 16:55:41.671427 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9683 16:55:41.675007 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9684 16:55:41.681364 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9685 16:55:41.685009 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9686 16:55:41.691398 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9687 16:55:41.695286 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9688 16:55:41.699227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9689 16:55:41.705717 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9690 16:55:41.708624 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9691 16:55:41.714825 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9692 16:55:41.717967 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9693 16:55:41.721334 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9694 16:55:41.728032 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9695 16:55:41.731158 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9696 16:55:41.737784 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9697 16:55:41.741358 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9698 16:55:41.744820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9699 16:55:41.751213 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9700 16:55:41.754291 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9701 16:55:41.760632 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9702 16:55:41.764513 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9703 16:55:41.767359 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9704 16:55:41.773977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9705 16:55:41.778057 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9706 16:55:41.784043 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9707 16:55:41.787216 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9708 16:55:41.790517 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9709 16:55:41.797289 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9710 16:55:41.800602 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9711 16:55:41.807089 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9712 16:55:41.810259 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9713 16:55:41.817166 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9714 16:55:41.820461 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9715 16:55:41.822983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9716 16:55:41.830515 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9717 16:55:41.833493 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9718 16:55:41.839776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9719 16:55:41.843186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9720 16:55:41.849893 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9721 16:55:41.853297 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9722 16:55:41.856293 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9723 16:55:41.863215 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9724 16:55:41.866256 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9725 16:55:41.872905 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9726 16:55:41.876766 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9727 16:55:41.882657 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9728 16:55:41.885889 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9729 16:55:41.889398 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9730 16:55:41.896115 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9731 16:55:41.899106 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9732 16:55:41.906451 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9733 16:55:41.909517 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9734 16:55:41.912230 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9735 16:55:41.919335 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9736 16:55:41.922653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9737 16:55:41.929658 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9738 16:55:41.932476 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9739 16:55:41.938879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9740 16:55:41.942887 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9741 16:55:41.945493 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9742 16:55:41.952725 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9743 16:55:41.955560 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9744 16:55:41.962204 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9745 16:55:41.965538 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9746 16:55:41.972076 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9747 16:55:41.975727 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9748 16:55:41.979086 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9749 16:55:41.984849 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9750 16:55:41.988552 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9751 16:55:41.991797 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9752 16:55:41.994975 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9753 16:55:42.001770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9754 16:55:42.005134 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9755 16:55:42.008308 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9756 16:55:42.015222 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9757 16:55:42.018769 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9758 16:55:42.025140 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9759 16:55:42.029170 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9760 16:55:42.031785 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9761 16:55:42.038422 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9762 16:55:42.041747 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9763 16:55:42.044925 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9764 16:55:42.051425 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9765 16:55:42.054945 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9766 16:55:42.058107 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9767 16:55:42.064468 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9768 16:55:42.067981 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9769 16:55:42.071517 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9770 16:55:42.078187 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9771 16:55:42.081136 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9772 16:55:42.087782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9773 16:55:42.091720 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9774 16:55:42.094206 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9775 16:55:42.101354 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9776 16:55:42.104446 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9777 16:55:42.111292 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9778 16:55:42.114437 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9779 16:55:42.117513 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9780 16:55:42.124549 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9781 16:55:42.127318 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9782 16:55:42.131313 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9783 16:55:42.137162 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9784 16:55:42.141164 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9785 16:55:42.143920 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9786 16:55:42.150527 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9787 16:55:42.154287 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9788 16:55:42.160574 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9789 16:55:42.164297 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9790 16:55:42.167102 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9791 16:55:42.170388 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9792 16:55:42.177260 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9793 16:55:42.180215 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9794 16:55:42.183409 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9795 16:55:42.186932 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9796 16:55:42.193396 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9797 16:55:42.196502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9798 16:55:42.199944 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9799 16:55:42.203027 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9800 16:55:42.209841 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9801 16:55:42.213065 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9802 16:55:42.217106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9803 16:55:42.223294 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9804 16:55:42.226975 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9805 16:55:42.230239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9806 16:55:42.236276 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9807 16:55:42.239796 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9808 16:55:42.246585 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9809 16:55:42.249612 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9810 16:55:42.256328 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9811 16:55:42.259995 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9812 16:55:42.262428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9813 16:55:42.269677 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9814 16:55:42.272296 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9815 16:55:42.279404 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9816 16:55:42.282920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9817 16:55:42.289294 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9818 16:55:42.292724 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9819 16:55:42.295906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9820 16:55:42.302309 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9821 16:55:42.305336 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9822 16:55:42.311875 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9823 16:55:42.315298 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9824 16:55:42.321896 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9825 16:55:42.325090 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9826 16:55:42.329245 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9827 16:55:42.335318 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9828 16:55:42.338735 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9829 16:55:42.345347 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9830 16:55:42.348739 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9831 16:55:42.351750 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9832 16:55:42.359059 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9833 16:55:42.362025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9834 16:55:42.368286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9835 16:55:42.371800 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9836 16:55:42.374837 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9837 16:55:42.381775 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9838 16:55:42.384494 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9839 16:55:42.391488 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9840 16:55:42.394743 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9841 16:55:42.400989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9842 16:55:42.404285 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9843 16:55:42.407917 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9844 16:55:42.414326 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9845 16:55:42.418010 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9846 16:55:42.424770 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9847 16:55:42.427658 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9848 16:55:42.431349 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9849 16:55:42.437645 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9850 16:55:42.440884 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9851 16:55:42.447582 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9852 16:55:42.450935 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9853 16:55:42.454275 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9854 16:55:42.461116 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9855 16:55:42.463880 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9856 16:55:42.471026 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9857 16:55:42.474086 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9858 16:55:42.477416 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9859 16:55:42.483762 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9860 16:55:42.487549 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9861 16:55:42.494103 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9862 16:55:42.497859 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9863 16:55:42.503998 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9864 16:55:42.507891 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9865 16:55:42.514115 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9866 16:55:42.517169 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9867 16:55:42.520230 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9868 16:55:42.526923 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9869 16:55:42.530803 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9870 16:55:42.536887 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9871 16:55:42.540055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9872 16:55:42.543396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9873 16:55:42.549820 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9874 16:55:42.553415 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9875 16:55:42.560388 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9876 16:55:42.562841 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9877 16:55:42.569713 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9878 16:55:42.573032 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9879 16:55:42.576554 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9880 16:55:42.583585 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9881 16:55:42.585989 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9882 16:55:42.592968 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9883 16:55:42.596120 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9884 16:55:42.602825 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9885 16:55:42.605716 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9886 16:55:42.612857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9887 16:55:42.615972 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9888 16:55:42.619118 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9889 16:55:42.625949 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9890 16:55:42.629044 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9891 16:55:42.636123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9892 16:55:42.638948 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9893 16:55:42.645325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9894 16:55:42.648853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9895 16:55:42.655011 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9896 16:55:42.658757 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9897 16:55:42.665904 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9898 16:55:42.668259 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9899 16:55:42.673247 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9900 16:55:42.678448 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9901 16:55:42.681607 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9902 16:55:42.688359 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9903 16:55:42.691645 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9904 16:55:42.698294 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9905 16:55:42.701593 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9906 16:55:42.704800 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9907 16:55:42.711526 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9908 16:55:42.715291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9909 16:55:42.721195 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9910 16:55:42.724809 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9911 16:55:42.731264 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9912 16:55:42.734801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9913 16:55:42.741664 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9914 16:55:42.744461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9915 16:55:42.747793 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9916 16:55:42.754137 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9917 16:55:42.757723 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9918 16:55:42.764552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9919 16:55:42.768356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9920 16:55:42.774913 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9921 16:55:42.777972 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9922 16:55:42.780783 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9923 16:55:42.787040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9924 16:55:42.790760 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9925 16:55:42.797619 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9926 16:55:42.800902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9927 16:55:42.807607 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9928 16:55:42.810435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9929 16:55:42.817385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9930 16:55:42.820876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9931 16:55:42.826890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9932 16:55:42.830785 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9933 16:55:42.837140 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9934 16:55:42.840907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9935 16:55:42.847176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9936 16:55:42.850153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9937 16:55:42.856864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9938 16:55:42.860421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9939 16:55:42.866545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9940 16:55:42.870231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9941 16:55:42.876201 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9942 16:55:42.880282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9943 16:55:42.884222 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9944 16:55:42.890556 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9945 16:55:42.896565 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9946 16:55:42.899539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9947 16:55:42.906617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9948 16:55:42.909835 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9949 16:55:42.916535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9950 16:55:42.919817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9951 16:55:42.926643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9952 16:55:42.929259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9953 16:55:42.935806 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9954 16:55:42.939543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9955 16:55:42.943086 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9956 16:55:42.946141 INFO: [APUAPC] vio 0
9957 16:55:42.952664 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9958 16:55:42.955970 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9959 16:55:42.959100 INFO: [APUAPC] D0_APC_0: 0x400510
9960 16:55:42.962392 INFO: [APUAPC] D0_APC_1: 0x0
9961 16:55:42.965866 INFO: [APUAPC] D0_APC_2: 0x1540
9962 16:55:42.968937 INFO: [APUAPC] D0_APC_3: 0x0
9963 16:55:42.972853 INFO: [APUAPC] D1_APC_0: 0xffffffff
9964 16:55:42.975275 INFO: [APUAPC] D1_APC_1: 0xffffffff
9965 16:55:42.978889 INFO: [APUAPC] D1_APC_2: 0x3fffff
9966 16:55:42.982417 INFO: [APUAPC] D1_APC_3: 0x0
9967 16:55:42.985547 INFO: [APUAPC] D2_APC_0: 0xffffffff
9968 16:55:42.988783 INFO: [APUAPC] D2_APC_1: 0xffffffff
9969 16:55:42.992271 INFO: [APUAPC] D2_APC_2: 0x3fffff
9970 16:55:42.992853 INFO: [APUAPC] D2_APC_3: 0x0
9971 16:55:42.998776 INFO: [APUAPC] D3_APC_0: 0xffffffff
9972 16:55:43.001743 INFO: [APUAPC] D3_APC_1: 0xffffffff
9973 16:55:43.005603 INFO: [APUAPC] D3_APC_2: 0x3fffff
9974 16:55:43.006182 INFO: [APUAPC] D3_APC_3: 0x0
9975 16:55:43.008379 INFO: [APUAPC] D4_APC_0: 0xffffffff
9976 16:55:43.015450 INFO: [APUAPC] D4_APC_1: 0xffffffff
9977 16:55:43.018734 INFO: [APUAPC] D4_APC_2: 0x3fffff
9978 16:55:43.019320 INFO: [APUAPC] D4_APC_3: 0x0
9979 16:55:43.021784 INFO: [APUAPC] D5_APC_0: 0xffffffff
9980 16:55:43.025040 INFO: [APUAPC] D5_APC_1: 0xffffffff
9981 16:55:43.028810 INFO: [APUAPC] D5_APC_2: 0x3fffff
9982 16:55:43.031819 INFO: [APUAPC] D5_APC_3: 0x0
9983 16:55:43.034872 INFO: [APUAPC] D6_APC_0: 0xffffffff
9984 16:55:43.038288 INFO: [APUAPC] D6_APC_1: 0xffffffff
9985 16:55:43.041866 INFO: [APUAPC] D6_APC_2: 0x3fffff
9986 16:55:43.044475 INFO: [APUAPC] D6_APC_3: 0x0
9987 16:55:43.048174 INFO: [APUAPC] D7_APC_0: 0xffffffff
9988 16:55:43.051526 INFO: [APUAPC] D7_APC_1: 0xffffffff
9989 16:55:43.054854 INFO: [APUAPC] D7_APC_2: 0x3fffff
9990 16:55:43.058483 INFO: [APUAPC] D7_APC_3: 0x0
9991 16:55:43.061756 INFO: [APUAPC] D8_APC_0: 0xffffffff
9992 16:55:43.064587 INFO: [APUAPC] D8_APC_1: 0xffffffff
9993 16:55:43.068080 INFO: [APUAPC] D8_APC_2: 0x3fffff
9994 16:55:43.070965 INFO: [APUAPC] D8_APC_3: 0x0
9995 16:55:43.074823 INFO: [APUAPC] D9_APC_0: 0xffffffff
9996 16:55:43.077667 INFO: [APUAPC] D9_APC_1: 0xffffffff
9997 16:55:43.081326 INFO: [APUAPC] D9_APC_2: 0x3fffff
9998 16:55:43.085054 INFO: [APUAPC] D9_APC_3: 0x0
9999 16:55:43.087620 INFO: [APUAPC] D10_APC_0: 0xffffffff
10000 16:55:43.091302 INFO: [APUAPC] D10_APC_1: 0xffffffff
10001 16:55:43.094563 INFO: [APUAPC] D10_APC_2: 0x3fffff
10002 16:55:43.097635 INFO: [APUAPC] D10_APC_3: 0x0
10003 16:55:43.102039 INFO: [APUAPC] D11_APC_0: 0xffffffff
10004 16:55:43.104386 INFO: [APUAPC] D11_APC_1: 0xffffffff
10005 16:55:43.107956 INFO: [APUAPC] D11_APC_2: 0x3fffff
10006 16:55:43.111000 INFO: [APUAPC] D11_APC_3: 0x0
10007 16:55:43.114228 INFO: [APUAPC] D12_APC_0: 0xffffffff
10008 16:55:43.118290 INFO: [APUAPC] D12_APC_1: 0xffffffff
10009 16:55:43.121090 INFO: [APUAPC] D12_APC_2: 0x3fffff
10010 16:55:43.124086 INFO: [APUAPC] D12_APC_3: 0x0
10011 16:55:43.127741 INFO: [APUAPC] D13_APC_0: 0xffffffff
10012 16:55:43.131071 INFO: [APUAPC] D13_APC_1: 0xffffffff
10013 16:55:43.134115 INFO: [APUAPC] D13_APC_2: 0x3fffff
10014 16:55:43.137365 INFO: [APUAPC] D13_APC_3: 0x0
10015 16:55:43.140660 INFO: [APUAPC] D14_APC_0: 0xffffffff
10016 16:55:43.144005 INFO: [APUAPC] D14_APC_1: 0xffffffff
10017 16:55:43.147747 INFO: [APUAPC] D14_APC_2: 0x3fffff
10018 16:55:43.150670 INFO: [APUAPC] D14_APC_3: 0x0
10019 16:55:43.154953 INFO: [APUAPC] D15_APC_0: 0xffffffff
10020 16:55:43.157411 INFO: [APUAPC] D15_APC_1: 0xffffffff
10021 16:55:43.160589 INFO: [APUAPC] D15_APC_2: 0x3fffff
10022 16:55:43.163713 INFO: [APUAPC] D15_APC_3: 0x0
10023 16:55:43.167595 INFO: [APUAPC] APC_CON: 0x4
10024 16:55:43.170830 INFO: [NOCDAPC] D0_APC_0: 0x0
10025 16:55:43.173687 INFO: [NOCDAPC] D0_APC_1: 0x0
10026 16:55:43.176745 INFO: [NOCDAPC] D1_APC_0: 0x0
10027 16:55:43.180418 INFO: [NOCDAPC] D1_APC_1: 0xfff
10028 16:55:43.183536 INFO: [NOCDAPC] D2_APC_0: 0x0
10029 16:55:43.186864 INFO: [NOCDAPC] D2_APC_1: 0xfff
10030 16:55:43.187342 INFO: [NOCDAPC] D3_APC_0: 0x0
10031 16:55:43.189989 INFO: [NOCDAPC] D3_APC_1: 0xfff
10032 16:55:43.194476 INFO: [NOCDAPC] D4_APC_0: 0x0
10033 16:55:43.196787 INFO: [NOCDAPC] D4_APC_1: 0xfff
10034 16:55:43.200413 INFO: [NOCDAPC] D5_APC_0: 0x0
10035 16:55:43.203156 INFO: [NOCDAPC] D5_APC_1: 0xfff
10036 16:55:43.207289 INFO: [NOCDAPC] D6_APC_0: 0x0
10037 16:55:43.210076 INFO: [NOCDAPC] D6_APC_1: 0xfff
10038 16:55:43.214085 INFO: [NOCDAPC] D7_APC_0: 0x0
10039 16:55:43.216628 INFO: [NOCDAPC] D7_APC_1: 0xfff
10040 16:55:43.219888 INFO: [NOCDAPC] D8_APC_0: 0x0
10041 16:55:43.223074 INFO: [NOCDAPC] D8_APC_1: 0xfff
10042 16:55:43.223554 INFO: [NOCDAPC] D9_APC_0: 0x0
10043 16:55:43.226574 INFO: [NOCDAPC] D9_APC_1: 0xfff
10044 16:55:43.230014 INFO: [NOCDAPC] D10_APC_0: 0x0
10045 16:55:43.233150 INFO: [NOCDAPC] D10_APC_1: 0xfff
10046 16:55:43.236469 INFO: [NOCDAPC] D11_APC_0: 0x0
10047 16:55:43.240121 INFO: [NOCDAPC] D11_APC_1: 0xfff
10048 16:55:43.243487 INFO: [NOCDAPC] D12_APC_0: 0x0
10049 16:55:43.246589 INFO: [NOCDAPC] D12_APC_1: 0xfff
10050 16:55:43.249965 INFO: [NOCDAPC] D13_APC_0: 0x0
10051 16:55:43.253340 INFO: [NOCDAPC] D13_APC_1: 0xfff
10052 16:55:43.256692 INFO: [NOCDAPC] D14_APC_0: 0x0
10053 16:55:43.259547 INFO: [NOCDAPC] D14_APC_1: 0xfff
10054 16:55:43.262971 INFO: [NOCDAPC] D15_APC_0: 0x0
10055 16:55:43.266458 INFO: [NOCDAPC] D15_APC_1: 0xfff
10056 16:55:43.267032 INFO: [NOCDAPC] APC_CON: 0x4
10057 16:55:43.273094 INFO: [APUAPC] set_apusys_apc done
10058 16:55:43.273664 INFO: [DEVAPC] devapc_init done
10059 16:55:43.280125 INFO: GICv3 without legacy support detected.
10060 16:55:43.283079 INFO: ARM GICv3 driver initialized in EL3
10061 16:55:43.286806 INFO: Maximum SPI INTID supported: 639
10062 16:55:43.289969 INFO: BL31: Initializing runtime services
10063 16:55:43.295971 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10064 16:55:43.299910 INFO: SPM: enable CPC mode
10065 16:55:43.303264 INFO: mcdi ready for mcusys-off-idle and system suspend
10066 16:55:43.309523 INFO: BL31: Preparing for EL3 exit to normal world
10067 16:55:43.312226 INFO: Entry point address = 0x80000000
10068 16:55:43.312700 INFO: SPSR = 0x8
10069 16:55:43.319689
10070 16:55:43.320155
10071 16:55:43.320535
10072 16:55:43.322978 Starting depthcharge on Spherion...
10073 16:55:43.323449
10074 16:55:43.323821 Wipe memory regions:
10075 16:55:43.324254
10076 16:55:43.326708 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10077 16:55:43.327317 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10078 16:55:43.327788 Setting prompt string to ['asurada:']
10079 16:55:43.328224 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10080 16:55:43.328946 [0x00000040000000, 0x00000054600000)
10081 16:55:43.449191
10082 16:55:43.449788 [0x00000054660000, 0x00000080000000)
10083 16:55:43.709287
10084 16:55:43.709851 [0x000000821a7280, 0x000000ffe64000)
10085 16:55:44.454920
10086 16:55:44.455494 [0x00000100000000, 0x00000240000000)
10087 16:55:46.344971
10088 16:55:46.347961 Initializing XHCI USB controller at 0x11200000.
10089 16:55:47.385720
10090 16:55:47.389287 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10091 16:55:47.390003
10092 16:55:47.390617
10093 16:55:47.390986
10094 16:55:47.391797 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10096 16:55:47.493124 asurada: tftpboot 192.168.201.1 10576342/tftp-deploy-a8bjz08n/kernel/image.itb 10576342/tftp-deploy-a8bjz08n/kernel/cmdline
10097 16:55:47.493788 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10098 16:55:47.494280 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10099 16:55:47.498502 tftpboot 192.168.201.1 10576342/tftp-deploy-a8bjz08n/kernel/image.ittp-deploy-a8bjz08n/kernel/cmdline
10100 16:55:47.498985
10101 16:55:47.499359 Waiting for link
10102 16:55:47.659167
10103 16:55:47.659732 R8152: Initializing
10104 16:55:47.660114
10105 16:55:47.662260 Version 9 (ocp_data = 6010)
10106 16:55:47.662873
10107 16:55:47.666070 R8152: Done initializing
10108 16:55:47.666680
10109 16:55:47.667065 Adding net device
10110 16:55:49.607588
10111 16:55:49.608170 done.
10112 16:55:49.608549
10113 16:55:49.608924 MAC: 00:e0:4c:72:2d:d6
10114 16:55:49.609260
10115 16:55:49.612193 Sending DHCP discover... done.
10116 16:55:49.612669
10117 16:55:59.733840 Waiting for reply... R8152: Bulk read error 0xffffffbf
10118 16:55:59.734676
10119 16:55:59.736646 Receive failed.
10120 16:55:59.737108
10121 16:55:59.737720 done.
10122 16:55:59.738303
10123 16:55:59.740733 Sending DHCP request... done.
10124 16:55:59.741281
10125 16:55:59.748153 Waiting for reply... done.
10126 16:55:59.748702
10127 16:55:59.749075 My ip is 192.168.201.21
10128 16:55:59.749413
10129 16:55:59.751111 The DHCP server ip is 192.168.201.1
10130 16:55:59.751674
10131 16:55:59.757970 TFTP server IP predefined by user: 192.168.201.1
10132 16:55:59.758570
10133 16:55:59.765358 Bootfile predefined by user: 10576342/tftp-deploy-a8bjz08n/kernel/image.itb
10134 16:55:59.765953
10135 16:55:59.766695 Sending tftp read request... done.
10136 16:55:59.767520
10137 16:55:59.772426 Waiting for the transfer...
10138 16:55:59.772993
10139 16:56:00.174268 00000000 ################################################################
10140 16:56:00.174880
10141 16:56:00.550870 00080000 ################################################################
10142 16:56:00.551382
10143 16:56:00.938810 00100000 ################################################################
10144 16:56:00.939332
10145 16:56:01.330004 00180000 ################################################################
10146 16:56:01.330560
10147 16:56:01.715646 00200000 ################################################################
10148 16:56:01.716163
10149 16:56:02.089214 00280000 ################################################################
10150 16:56:02.089774
10151 16:56:02.473663 00300000 ################################################################
10152 16:56:02.474214
10153 16:56:02.845218 00380000 ################################################################
10154 16:56:02.845447
10155 16:56:03.216774 00400000 ################################################################
10156 16:56:03.217291
10157 16:56:03.583645 00480000 ################################################################
10158 16:56:03.584227
10159 16:56:03.966275 00500000 ################################################################
10160 16:56:03.966867
10161 16:56:04.370518 00580000 ################################################################
10162 16:56:04.371067
10163 16:56:04.755815 00600000 ################################################################
10164 16:56:04.756432
10165 16:56:05.070301 00680000 ################################################################
10166 16:56:05.070465
10167 16:56:05.366258 00700000 ################################################################
10168 16:56:05.366413
10169 16:56:05.664175 00780000 ################################################################
10170 16:56:05.664312
10171 16:56:05.943806 00800000 ################################################################
10172 16:56:05.943937
10173 16:56:06.193478 00880000 ################################################################
10174 16:56:06.193605
10175 16:56:06.482708 00900000 ################################################################
10176 16:56:06.482839
10177 16:56:06.768338 00980000 ################################################################
10178 16:56:06.768474
10179 16:56:07.138446 00a00000 ################################################################
10180 16:56:07.138948
10181 16:56:07.497788 00a80000 ################################################################
10182 16:56:07.498284
10183 16:56:07.878435 00b00000 ################################################################
10184 16:56:07.878948
10185 16:56:08.278822 00b80000 ################################################################
10186 16:56:08.279364
10187 16:56:08.656164 00c00000 ################################################################
10188 16:56:08.656709
10189 16:56:09.019213 00c80000 ################################################################
10190 16:56:09.019353
10191 16:56:09.317918 00d00000 ################################################################
10192 16:56:09.318050
10193 16:56:09.618248 00d80000 ################################################################
10194 16:56:09.618417
10195 16:56:09.913707 00e00000 ################################################################
10196 16:56:09.913843
10197 16:56:10.197438 00e80000 ################################################################
10198 16:56:10.197575
10199 16:56:10.470692 00f00000 ################################################################
10200 16:56:10.470822
10201 16:56:10.727899 00f80000 ################################################################
10202 16:56:10.728027
10203 16:56:11.027391 01000000 ################################################################
10204 16:56:11.027535
10205 16:56:11.324268 01080000 ################################################################
10206 16:56:11.324402
10207 16:56:11.620942 01100000 ################################################################
10208 16:56:11.621074
10209 16:56:11.920482 01180000 ################################################################
10210 16:56:11.920616
10211 16:56:12.221668 01200000 ################################################################
10212 16:56:12.221796
10213 16:56:12.523298 01280000 ################################################################
10214 16:56:12.523427
10215 16:56:12.825478 01300000 ################################################################
10216 16:56:12.825607
10217 16:56:13.126322 01380000 ################################################################
10218 16:56:13.126507
10219 16:56:13.428193 01400000 ################################################################
10220 16:56:13.428386
10221 16:56:13.728651 01480000 ################################################################
10222 16:56:13.728784
10223 16:56:14.028498 01500000 ################################################################
10224 16:56:14.028628
10225 16:56:14.290050 01580000 ################################################################
10226 16:56:14.290174
10227 16:56:14.583926 01600000 ################################################################
10228 16:56:14.584059
10229 16:56:14.893201 01680000 ################################################################
10230 16:56:14.893687
10231 16:56:15.268462 01700000 ################################################################
10232 16:56:15.268980
10233 16:56:15.641655 01780000 ################################################################
10234 16:56:15.642227
10235 16:56:15.982198 01800000 ################################################################
10236 16:56:15.982371
10237 16:56:16.276793 01880000 ################################################################
10238 16:56:16.276925
10239 16:56:16.573488 01900000 ################################################################
10240 16:56:16.573622
10241 16:56:16.871196 01980000 ################################################################
10242 16:56:16.871336
10243 16:56:17.167518 01a00000 ################################################################
10244 16:56:17.167647
10245 16:56:17.450996 01a80000 ################################################################
10246 16:56:17.451138
10247 16:56:17.654657 01b00000 #################################################### done.
10248 16:56:17.654792
10249 16:56:17.657954 The bootfile was 28734642 bytes long.
10250 16:56:17.661494
10251 16:56:17.661580 Sending tftp read request... done.
10252 16:56:17.661649
10253 16:56:17.664662 Waiting for the transfer...
10254 16:56:17.664838
10255 16:56:17.667992 00000000 # done.
10256 16:56:17.668176
10257 16:56:17.674815 Command line loaded dynamically from TFTP file: 10576342/tftp-deploy-a8bjz08n/kernel/cmdline
10258 16:56:17.675003
10259 16:56:17.694905 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10260 16:56:17.695205
10261 16:56:17.695364 Loading FIT.
10262 16:56:17.695501
10263 16:56:17.698426 Image ramdisk-1 has 18602210 bytes.
10264 16:56:17.698895
10265 16:56:17.701638 Image fdt-1 has 46924 bytes.
10266 16:56:17.702210
10267 16:56:17.705404 Image kernel-1 has 10083474 bytes.
10268 16:56:17.705974
10269 16:56:17.714565 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10270 16:56:17.715121
10271 16:56:17.731039 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10272 16:56:17.731642
10273 16:56:17.737820 Choosing best match conf-1 for compat google,spherion-rev2.
10274 16:56:17.738290
10275 16:56:17.745425 Connected to device vid:did:rid of 1ae0:0028:00
10276 16:56:17.752704
10277 16:56:17.755775 tpm_get_response: command 0x17b, return code 0x0
10278 16:56:17.756249
10279 16:56:17.758996 ec_init: CrosEC protocol v3 supported (256, 248)
10280 16:56:17.763186
10281 16:56:17.766214 tpm_cleanup: add release locality here.
10282 16:56:17.766731
10283 16:56:17.767104 Shutting down all USB controllers.
10284 16:56:17.769816
10285 16:56:17.770433 Removing current net device
10286 16:56:17.770824
10287 16:56:17.776558 Exiting depthcharge with code 4 at timestamp: 63711365
10288 16:56:17.777137
10289 16:56:17.779977 LZMA decompressing kernel-1 to 0x821a6718
10290 16:56:17.780552
10291 16:56:17.782977 LZMA decompressing kernel-1 to 0x40000000
10292 16:56:19.048765
10293 16:56:19.049331 jumping to kernel
10294 16:56:19.050815 end: 2.2.4 bootloader-commands (duration 00:00:36) [common]
10295 16:56:19.051381 start: 2.2.5 auto-login-action (timeout 00:03:50) [common]
10296 16:56:19.051797 Setting prompt string to ['Linux version [0-9]']
10297 16:56:19.052188 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10298 16:56:19.052567 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10299 16:56:19.130383
10300 16:56:19.133413 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10301 16:56:19.138195 start: 2.2.5.1 login-action (timeout 00:03:49) [common]
10302 16:56:19.138845 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10303 16:56:19.139308 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10304 16:56:19.139710 Using line separator: #'\n'#
10305 16:56:19.140072 No login prompt set.
10306 16:56:19.140480 Parsing kernel messages
10307 16:56:19.140803 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10308 16:56:19.141366 [login-action] Waiting for messages, (timeout 00:03:49)
10309 16:56:19.156967 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10310 16:56:19.160399 [ 0.000000] random: crng init done
10311 16:56:19.166740 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10312 16:56:19.169634 [ 0.000000] efi: UEFI not found.
10313 16:56:19.176577 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10314 16:56:19.183095 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10315 16:56:19.193689 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10316 16:56:19.203266 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10317 16:56:19.209663 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10318 16:56:19.216664 [ 0.000000] printk: bootconsole [mtk8250] enabled
10319 16:56:19.222746 [ 0.000000] NUMA: No NUMA configuration found
10320 16:56:19.229738 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10321 16:56:19.232926 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10322 16:56:19.236999 [ 0.000000] Zone ranges:
10323 16:56:19.242974 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10324 16:56:19.246034 [ 0.000000] DMA32 empty
10325 16:56:19.252994 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10326 16:56:19.255398 [ 0.000000] Movable zone start for each node
10327 16:56:19.259065 [ 0.000000] Early memory node ranges
10328 16:56:19.265620 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10329 16:56:19.272998 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10330 16:56:19.278543 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10331 16:56:19.285357 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10332 16:56:19.292077 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10333 16:56:19.298523 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10334 16:56:19.354851 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10335 16:56:19.361166 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10336 16:56:19.368046 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10337 16:56:19.371317 [ 0.000000] psci: probing for conduit method from DT.
10338 16:56:19.378202 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10339 16:56:19.381304 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10340 16:56:19.388081 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10341 16:56:19.390953 [ 0.000000] psci: SMC Calling Convention v1.2
10342 16:56:19.397720 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10343 16:56:19.401738 [ 0.000000] Detected VIPT I-cache on CPU0
10344 16:56:19.408017 [ 0.000000] CPU features: detected: GIC system register CPU interface
10345 16:56:19.414494 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10346 16:56:19.420901 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10347 16:56:19.427161 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10348 16:56:19.437368 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10349 16:56:19.443804 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10350 16:56:19.447175 [ 0.000000] alternatives: applying boot alternatives
10351 16:56:19.453869 [ 0.000000] Fallback order for Node 0: 0
10352 16:56:19.460785 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10353 16:56:19.463805 [ 0.000000] Policy zone: Normal
10354 16:56:19.483899 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10355 16:56:19.493521 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10356 16:56:19.505448 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10357 16:56:19.515133 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10358 16:56:19.522227 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10359 16:56:19.525057 <6>[ 0.000000] software IO TLB: area num 8.
10360 16:56:19.581966 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10361 16:56:19.731150 <6>[ 0.000000] Memory: 7954780K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397988K reserved, 32768K cma-reserved)
10362 16:56:19.737460 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10363 16:56:19.744127 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10364 16:56:19.747095 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10365 16:56:19.754640 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10366 16:56:19.760412 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10367 16:56:19.763857 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10368 16:56:19.773601 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10369 16:56:19.779975 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10370 16:56:19.786802 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10371 16:56:19.794262 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10372 16:56:19.796756 <6>[ 0.000000] GICv3: 608 SPIs implemented
10373 16:56:19.800376 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10374 16:56:19.806785 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10375 16:56:19.810266 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10376 16:56:19.816653 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10377 16:56:19.829926 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10378 16:56:19.843162 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10379 16:56:19.849698 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10380 16:56:19.857611 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10381 16:56:19.870741 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10382 16:56:19.877278 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10383 16:56:19.883696 <6>[ 0.009180] Console: colour dummy device 80x25
10384 16:56:19.893959 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10385 16:56:19.900193 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10386 16:56:19.903929 <6>[ 0.029287] LSM: Security Framework initializing
10387 16:56:19.910311 <6>[ 0.034254] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10388 16:56:19.920811 <6>[ 0.042116] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10389 16:56:19.930549 <6>[ 0.051598] cblist_init_generic: Setting adjustable number of callback queues.
10390 16:56:19.938185 <6>[ 0.059052] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 16:56:19.939792 <6>[ 0.065389] cblist_init_generic: Setting shift to 3 and lim to 1.
10392 16:56:19.946960 <6>[ 0.071835] rcu: Hierarchical SRCU implementation.
10393 16:56:19.953870 <6>[ 0.076849] rcu: Max phase no-delay instances is 1000.
10394 16:56:19.959956 <6>[ 0.083867] EFI services will not be available.
10395 16:56:19.963090 <6>[ 0.088845] smp: Bringing up secondary CPUs ...
10396 16:56:19.971523 <6>[ 0.093895] Detected VIPT I-cache on CPU1
10397 16:56:19.977718 <6>[ 0.093974] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10398 16:56:19.984088 <6>[ 0.094004] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10399 16:56:19.987522 <6>[ 0.094345] Detected VIPT I-cache on CPU2
10400 16:56:19.998133 <6>[ 0.094399] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10401 16:56:20.004364 <6>[ 0.094416] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10402 16:56:20.007217 <6>[ 0.094679] Detected VIPT I-cache on CPU3
10403 16:56:20.014292 <6>[ 0.094728] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10404 16:56:20.020630 <6>[ 0.094743] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10405 16:56:20.023847 <6>[ 0.095048] CPU features: detected: Spectre-v4
10406 16:56:20.030560 <6>[ 0.095054] CPU features: detected: Spectre-BHB
10407 16:56:20.034281 <6>[ 0.095060] Detected PIPT I-cache on CPU4
10408 16:56:20.040270 <6>[ 0.095118] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10409 16:56:20.047390 <6>[ 0.095136] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10410 16:56:20.054004 <6>[ 0.095433] Detected PIPT I-cache on CPU5
10411 16:56:20.060365 <6>[ 0.095495] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10412 16:56:20.066571 <6>[ 0.095512] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10413 16:56:20.070656 <6>[ 0.095798] Detected PIPT I-cache on CPU6
10414 16:56:20.076527 <6>[ 0.095864] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10415 16:56:20.086619 <6>[ 0.095880] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10416 16:56:20.089860 <6>[ 0.096178] Detected PIPT I-cache on CPU7
10417 16:56:20.096401 <6>[ 0.096242] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10418 16:56:20.102961 <6>[ 0.096258] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10419 16:56:20.106475 <6>[ 0.096305] smp: Brought up 1 node, 8 CPUs
10420 16:56:20.112825 <6>[ 0.237677] SMP: Total of 8 processors activated.
10421 16:56:20.116258 <6>[ 0.242599] CPU features: detected: 32-bit EL0 Support
10422 16:56:20.126388 <6>[ 0.247962] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10423 16:56:20.133398 <6>[ 0.256762] CPU features: detected: Common not Private translations
10424 16:56:20.139632 <6>[ 0.263237] CPU features: detected: CRC32 instructions
10425 16:56:20.143279 <6>[ 0.268622] CPU features: detected: RCpc load-acquire (LDAPR)
10426 16:56:20.149323 <6>[ 0.274581] CPU features: detected: LSE atomic instructions
10427 16:56:20.155936 <6>[ 0.280363] CPU features: detected: Privileged Access Never
10428 16:56:20.162750 <6>[ 0.286179] CPU features: detected: RAS Extension Support
10429 16:56:20.169235 <6>[ 0.291822] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10430 16:56:20.172537 <6>[ 0.299040] CPU: All CPU(s) started at EL2
10431 16:56:20.179162 <6>[ 0.303357] alternatives: applying system-wide alternatives
10432 16:56:20.188886 <6>[ 0.314024] devtmpfs: initialized
10433 16:56:20.204226 <6>[ 0.322950] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10434 16:56:20.210858 <6>[ 0.332913] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10435 16:56:20.217275 <6>[ 0.341135] pinctrl core: initialized pinctrl subsystem
10436 16:56:20.221088 <6>[ 0.347792] DMI not present or invalid.
10437 16:56:20.228020 <6>[ 0.352218] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10438 16:56:20.238157 <6>[ 0.359122] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10439 16:56:20.244572 <6>[ 0.366709] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10440 16:56:20.254054 <6>[ 0.374938] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10441 16:56:20.257309 <6>[ 0.383188] audit: initializing netlink subsys (disabled)
10442 16:56:20.267362 <5>[ 0.388892] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10443 16:56:20.273918 <6>[ 0.389606] thermal_sys: Registered thermal governor 'step_wise'
10444 16:56:20.279947 <6>[ 0.396860] thermal_sys: Registered thermal governor 'power_allocator'
10445 16:56:20.283332 <6>[ 0.403117] cpuidle: using governor menu
10446 16:56:20.290296 <6>[ 0.414083] NET: Registered PF_QIPCRTR protocol family
10447 16:56:20.296469 <6>[ 0.419608] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10448 16:56:20.303486 <6>[ 0.426712] ASID allocator initialised with 32768 entries
10449 16:56:20.306972 <6>[ 0.433300] Serial: AMBA PL011 UART driver
10450 16:56:20.316775 <4>[ 0.442037] Trying to register duplicate clock ID: 134
10451 16:56:20.373594 <6>[ 0.501444] KASLR enabled
10452 16:56:20.387683 <6>[ 0.509215] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10453 16:56:20.393689 <6>[ 0.516228] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10454 16:56:20.400509 <6>[ 0.522719] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10455 16:56:20.407839 <6>[ 0.529727] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10456 16:56:20.414086 <6>[ 0.536216] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10457 16:56:20.420416 <6>[ 0.543223] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10458 16:56:20.427100 <6>[ 0.549710] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10459 16:56:20.433407 <6>[ 0.556714] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10460 16:56:20.437391 <6>[ 0.564241] ACPI: Interpreter disabled.
10461 16:56:20.445398 <6>[ 0.570635] iommu: Default domain type: Translated
10462 16:56:20.452219 <6>[ 0.575746] iommu: DMA domain TLB invalidation policy: strict mode
10463 16:56:20.455695 <5>[ 0.582404] SCSI subsystem initialized
10464 16:56:20.462273 <6>[ 0.586573] usbcore: registered new interface driver usbfs
10465 16:56:20.468715 <6>[ 0.592311] usbcore: registered new interface driver hub
10466 16:56:20.472466 <6>[ 0.597862] usbcore: registered new device driver usb
10467 16:56:20.478461 <6>[ 0.603941] pps_core: LinuxPPS API ver. 1 registered
10468 16:56:20.488440 <6>[ 0.609137] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10469 16:56:20.492074 <6>[ 0.618486] PTP clock support registered
10470 16:56:20.495031 <6>[ 0.622727] EDAC MC: Ver: 3.0.0
10471 16:56:20.502807 <6>[ 0.627861] FPGA manager framework
10472 16:56:20.509312 <6>[ 0.631541] Advanced Linux Sound Architecture Driver Initialized.
10473 16:56:20.513185 <6>[ 0.638316] vgaarb: loaded
10474 16:56:20.519069 <6>[ 0.641499] clocksource: Switched to clocksource arch_sys_counter
10475 16:56:20.522188 <5>[ 0.647939] VFS: Disk quotas dquot_6.6.0
10476 16:56:20.528664 <6>[ 0.652122] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10477 16:56:20.531580 <6>[ 0.659315] pnp: PnP ACPI: disabled
10478 16:56:20.540922 <6>[ 0.666083] NET: Registered PF_INET protocol family
10479 16:56:20.550696 <6>[ 0.671669] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10480 16:56:20.562107 <6>[ 0.683964] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10481 16:56:20.572663 <6>[ 0.692779] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10482 16:56:20.578635 <6>[ 0.700750] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10483 16:56:20.585193 <6>[ 0.709452] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10484 16:56:20.597347 <6>[ 0.719203] TCP: Hash tables configured (established 65536 bind 65536)
10485 16:56:20.603957 <6>[ 0.726060] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 16:56:20.610799 <6>[ 0.733259] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10487 16:56:20.617099 <6>[ 0.740965] NET: Registered PF_UNIX/PF_LOCAL protocol family
10488 16:56:20.623737 <6>[ 0.747134] RPC: Registered named UNIX socket transport module.
10489 16:56:20.626814 <6>[ 0.753291] RPC: Registered udp transport module.
10490 16:56:20.633509 <6>[ 0.758226] RPC: Registered tcp transport module.
10491 16:56:20.640660 <6>[ 0.763159] RPC: Registered tcp NFSv4.1 backchannel transport module.
10492 16:56:20.643194 <6>[ 0.769830] PCI: CLS 0 bytes, default 64
10493 16:56:20.646381 <6>[ 0.774182] Unpacking initramfs...
10494 16:56:20.664349 <6>[ 0.786144] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10495 16:56:20.674056 <6>[ 0.794814] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10496 16:56:20.677048 <6>[ 0.803674] kvm [1]: IPA Size Limit: 40 bits
10497 16:56:20.684103 <6>[ 0.808204] kvm [1]: GICv3: no GICV resource entry
10498 16:56:20.687273 <6>[ 0.813227] kvm [1]: disabling GICv2 emulation
10499 16:56:20.693903 <6>[ 0.817915] kvm [1]: GIC system register CPU interface enabled
10500 16:56:20.696797 <6>[ 0.824084] kvm [1]: vgic interrupt IRQ18
10501 16:56:20.703403 <6>[ 0.828447] kvm [1]: VHE mode initialized successfully
10502 16:56:20.710290 <5>[ 0.834929] Initialise system trusted keyrings
10503 16:56:20.717100 <6>[ 0.839727] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10504 16:56:20.724307 <6>[ 0.849948] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10505 16:56:20.731131 <5>[ 0.856357] NFS: Registering the id_resolver key type
10506 16:56:20.734385 <5>[ 0.861663] Key type id_resolver registered
10507 16:56:20.741013 <5>[ 0.866080] Key type id_legacy registered
10508 16:56:20.748083 <6>[ 0.870361] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10509 16:56:20.754747 <6>[ 0.877282] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10510 16:56:20.761217 <6>[ 0.885006] 9p: Installing v9fs 9p2000 file system support
10511 16:56:20.797110 <5>[ 0.922433] Key type asymmetric registered
10512 16:56:20.800452 <5>[ 0.926764] Asymmetric key parser 'x509' registered
10513 16:56:20.810479 <6>[ 0.931908] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10514 16:56:20.813808 <6>[ 0.939525] io scheduler mq-deadline registered
10515 16:56:20.817434 <6>[ 0.944287] io scheduler kyber registered
10516 16:56:20.835812 <6>[ 0.961144] EINJ: ACPI disabled.
10517 16:56:20.867993 <4>[ 0.986802] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 16:56:20.877865 <4>[ 0.997429] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10519 16:56:20.893489 <6>[ 1.018606] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10520 16:56:20.901178 <6>[ 1.026797] printk: console [ttyS0] disabled
10521 16:56:20.929470 <6>[ 1.051474] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10522 16:56:20.936170 <6>[ 1.060953] printk: console [ttyS0] enabled
10523 16:56:20.939248 <6>[ 1.060953] printk: console [ttyS0] enabled
10524 16:56:20.945554 <6>[ 1.069853] printk: bootconsole [mtk8250] disabled
10525 16:56:20.948944 <6>[ 1.069853] printk: bootconsole [mtk8250] disabled
10526 16:56:20.955842 <6>[ 1.081019] SuperH (H)SCI(F) driver initialized
10527 16:56:20.959251 <6>[ 1.086300] msm_serial: driver initialized
10528 16:56:20.973719 <6>[ 1.095298] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10529 16:56:20.982941 <6>[ 1.103849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10530 16:56:20.990085 <6>[ 1.112391] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10531 16:56:20.999679 <6>[ 1.121019] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10532 16:56:21.010150 <6>[ 1.129726] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10533 16:56:21.016250 <6>[ 1.138440] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10534 16:56:21.026378 <6>[ 1.146983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10535 16:56:21.032731 <6>[ 1.155798] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10536 16:56:21.042695 <6>[ 1.164346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10537 16:56:21.054662 <6>[ 1.180133] loop: module loaded
10538 16:56:21.061659 <6>[ 1.186224] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10539 16:56:21.084732 <4>[ 1.209872] mtk-pmic-keys: Failed to locate of_node [id: -1]
10540 16:56:21.091632 <6>[ 1.216889] megasas: 07.719.03.00-rc1
10541 16:56:21.101353 <6>[ 1.226712] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10542 16:56:21.108882 <6>[ 1.232881] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10543 16:56:21.124800 <6>[ 1.249607] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10544 16:56:21.184971 <6>[ 1.303794] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10545 16:56:21.421694 <6>[ 1.546945] Freeing initrd memory: 18160K
10546 16:56:21.434059 <6>[ 1.558474] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10547 16:56:21.445345 <6>[ 1.569659] tun: Universal TUN/TAP device driver, 1.6
10548 16:56:21.447571 <6>[ 1.575732] thunder_xcv, ver 1.0
10549 16:56:21.451659 <6>[ 1.579240] thunder_bgx, ver 1.0
10550 16:56:21.454132 <6>[ 1.582738] nicpf, ver 1.0
10551 16:56:21.464891 <6>[ 1.586783] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10552 16:56:21.467980 <6>[ 1.594259] hns3: Copyright (c) 2017 Huawei Corporation.
10553 16:56:21.474543 <6>[ 1.599851] hclge is initializing
10554 16:56:21.478302 <6>[ 1.603432] e1000: Intel(R) PRO/1000 Network Driver
10555 16:56:21.484860 <6>[ 1.608560] e1000: Copyright (c) 1999-2006 Intel Corporation.
10556 16:56:21.488339 <6>[ 1.614575] e1000e: Intel(R) PRO/1000 Network Driver
10557 16:56:21.494728 <6>[ 1.619791] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10558 16:56:21.500941 <6>[ 1.625977] igb: Intel(R) Gigabit Ethernet Network Driver
10559 16:56:21.508786 <6>[ 1.631627] igb: Copyright (c) 2007-2014 Intel Corporation.
10560 16:56:21.514650 <6>[ 1.637463] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10561 16:56:21.521896 <6>[ 1.643981] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10562 16:56:21.524725 <6>[ 1.650440] sky2: driver version 1.30
10563 16:56:21.531189 <6>[ 1.655434] VFIO - User Level meta-driver version: 0.3
10564 16:56:21.538418 <6>[ 1.663608] usbcore: registered new interface driver usb-storage
10565 16:56:21.545229 <6>[ 1.670060] usbcore: registered new device driver onboard-usb-hub
10566 16:56:21.554072 <6>[ 1.679128] mt6397-rtc mt6359-rtc: registered as rtc0
10567 16:56:21.563951 <6>[ 1.684597] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:56:21 UTC (1685811381)
10568 16:56:21.566957 <6>[ 1.694167] i2c_dev: i2c /dev entries driver
10569 16:56:21.583627 <6>[ 1.705947] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10570 16:56:21.591384 <6>[ 1.716215] sdhci: Secure Digital Host Controller Interface driver
10571 16:56:21.597623 <6>[ 1.722654] sdhci: Copyright(c) Pierre Ossman
10572 16:56:21.604253 <6>[ 1.728041] Synopsys Designware Multimedia Card Interface Driver
10573 16:56:21.608053 <6>[ 1.734632] mmc0: CQHCI version 5.10
10574 16:56:21.613936 <6>[ 1.735190] sdhci-pltfm: SDHCI platform and OF driver helper
10575 16:56:21.621012 <6>[ 1.746499] ledtrig-cpu: registered to indicate activity on CPUs
10576 16:56:21.631825 <6>[ 1.753917] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10577 16:56:21.639172 <6>[ 1.761319] usbcore: registered new interface driver usbhid
10578 16:56:21.642039 <6>[ 1.767146] usbhid: USB HID core driver
10579 16:56:21.648434 <6>[ 1.771385] spi_master spi0: will run message pump with realtime priority
10580 16:56:21.694078 <6>[ 1.812727] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10581 16:56:21.713094 <6>[ 1.828268] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10582 16:56:21.717098 <6>[ 1.841850] mmc0: Command Queue Engine enabled
10583 16:56:21.724192 <6>[ 1.843450] cros-ec-spi spi0.0: Chrome EC device registered
10584 16:56:21.727074 <6>[ 1.846593] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10585 16:56:21.734520 <6>[ 1.859702] mmcblk0: mmc0:0001 DA4128 116 GiB
10586 16:56:21.747216 <6>[ 1.869063] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10587 16:56:21.753967 <6>[ 1.871644] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10588 16:56:21.760301 <6>[ 1.880567] NET: Registered PF_PACKET protocol family
10589 16:56:21.763665 <6>[ 1.885427] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10590 16:56:21.770458 <6>[ 1.889730] 9pnet: Installing 9P2000 support
10591 16:56:21.773667 <6>[ 1.895485] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10592 16:56:21.780416 <5>[ 1.899400] Key type dns_resolver registered
10593 16:56:21.786865 <6>[ 1.905254] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10594 16:56:21.789944 <6>[ 1.909679] registered taskstats version 1
10595 16:56:21.793760 <5>[ 1.920048] Loading compiled-in X.509 certificates
10596 16:56:21.829326 <4>[ 1.946666] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10597 16:56:21.838385 <4>[ 1.957369] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10598 16:56:21.847845 <3>[ 1.970174] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10599 16:56:21.860623 <6>[ 1.985541] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10600 16:56:21.866952 <6>[ 1.992433] xhci-mtk 11200000.usb: xHCI Host Controller
10601 16:56:21.873479 <6>[ 1.997944] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10602 16:56:21.883645 <6>[ 2.005795] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10603 16:56:21.890339 <6>[ 2.015225] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10604 16:56:21.896671 <6>[ 2.021310] xhci-mtk 11200000.usb: xHCI Host Controller
10605 16:56:21.903584 <6>[ 2.026791] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10606 16:56:21.910467 <6>[ 2.034442] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10607 16:56:21.917378 <6>[ 2.042153] hub 1-0:1.0: USB hub found
10608 16:56:21.920355 <6>[ 2.046182] hub 1-0:1.0: 1 port detected
10609 16:56:21.926792 <6>[ 2.050518] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10610 16:56:21.934162 <6>[ 2.059240] hub 2-0:1.0: USB hub found
10611 16:56:21.937324 <6>[ 2.063271] hub 2-0:1.0: 1 port detected
10612 16:56:21.945038 <6>[ 2.070425] mtk-msdc 11f70000.mmc: Got CD GPIO
10613 16:56:21.962642 <6>[ 2.084243] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10614 16:56:21.969169 <6>[ 2.092284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10615 16:56:21.978869 <4>[ 2.100288] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10616 16:56:21.988770 <6>[ 2.109952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10617 16:56:21.995239 <6>[ 2.118034] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10618 16:56:22.002066 <6>[ 2.126070] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10619 16:56:22.011858 <6>[ 2.133987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10620 16:56:22.018655 <6>[ 2.141808] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10621 16:56:22.028589 <6>[ 2.149630] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10622 16:56:22.038872 <6>[ 2.160413] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10623 16:56:22.045250 <6>[ 2.168783] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10624 16:56:22.055193 <6>[ 2.177142] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10625 16:56:22.065915 <6>[ 2.185485] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10626 16:56:22.071768 <6>[ 2.193841] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10627 16:56:22.081658 <6>[ 2.202183] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10628 16:56:22.088298 <6>[ 2.210527] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10629 16:56:22.098412 <6>[ 2.218870] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10630 16:56:22.104517 <6>[ 2.227213] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10631 16:56:22.115009 <6>[ 2.235556] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10632 16:56:22.121523 <6>[ 2.243900] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10633 16:56:22.130861 <6>[ 2.252246] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10634 16:56:22.137627 <6>[ 2.260590] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10635 16:56:22.147706 <6>[ 2.268933] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10636 16:56:22.154603 <6>[ 2.277278] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10637 16:56:22.160888 <6>[ 2.286197] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10638 16:56:22.168373 <6>[ 2.293686] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10639 16:56:22.175533 <6>[ 2.300698] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10640 16:56:22.185543 <6>[ 2.307814] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10641 16:56:22.192245 <6>[ 2.315085] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10642 16:56:22.202231 <6>[ 2.321995] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10643 16:56:22.208923 <6>[ 2.331135] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10644 16:56:22.219181 <6>[ 2.340262] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10645 16:56:22.228454 <6>[ 2.349571] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10646 16:56:22.238510 <6>[ 2.359046] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10647 16:56:22.248419 <6>[ 2.368520] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10648 16:56:22.258852 <6>[ 2.377649] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10649 16:56:22.265281 <6>[ 2.387124] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10650 16:56:22.275195 <6>[ 2.396250] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10651 16:56:22.284684 <6>[ 2.405552] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10652 16:56:22.294576 <6>[ 2.415718] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10653 16:56:22.304998 <6>[ 2.427207] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10654 16:56:22.311716 <6>[ 2.437151] Trying to probe devices needed for running init ...
10655 16:56:22.347183 <6>[ 2.469744] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10656 16:56:22.500315 <6>[ 2.625586] hub 1-1:1.0: USB hub found
10657 16:56:22.503162 <6>[ 2.629947] hub 1-1:1.0: 4 ports detected
10658 16:56:22.628338 <6>[ 2.750102] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10659 16:56:22.654531 <6>[ 2.780171] hub 2-1:1.0: USB hub found
10660 16:56:22.658338 <6>[ 2.784650] hub 2-1:1.0: 3 ports detected
10661 16:56:22.823698 <6>[ 2.945773] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10662 16:56:22.956021 <6>[ 3.081671] hub 1-1.4:1.0: USB hub found
10663 16:56:22.959812 <6>[ 3.086302] hub 1-1.4:1.0: 2 ports detected
10664 16:56:23.036124 <6>[ 3.158031] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10665 16:56:23.255744 <6>[ 3.377773] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10666 16:56:23.447672 <6>[ 3.569775] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10667 16:56:34.600195 <6>[ 14.730416] ALSA device list:
10668 16:56:34.606815 <6>[ 14.733672] No soundcards found.
10669 16:56:34.619069 <6>[ 14.746093] Freeing unused kernel memory: 8384K
10670 16:56:34.622445 <6>[ 14.751026] Run /init as init process
10671 16:56:34.633251 Loading, please wait...
10672 16:56:34.661583 Starting systemd-udevd version 252.6-1
10673 16:56:35.075100 <6>[ 15.198920] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10674 16:56:35.100309 <6>[ 15.227245] remoteproc remoteproc0: scp is available
10675 16:56:35.110465 <4>[ 15.232780] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10676 16:56:35.116973 <6>[ 15.242665] remoteproc remoteproc0: powering up scp
10677 16:56:35.119862 <6>[ 15.243397] mc: Linux media interface: v0.10
10678 16:56:35.126682 <6>[ 15.244319] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10679 16:56:35.136681 <6>[ 15.244409] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10680 16:56:35.147225 <6>[ 15.244427] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10681 16:56:35.156996 <4>[ 15.248065] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10682 16:56:35.163138 <4>[ 15.260894] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 16:56:35.169958 <3>[ 15.268779] remoteproc remoteproc0: request_firmware failed: -2
10684 16:56:35.173116 <6>[ 15.284589] videodev: Linux video capture interface: v2.00
10685 16:56:35.183042 <3>[ 15.288830] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 16:56:35.189852 <4>[ 15.295014] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10687 16:56:35.200556 <3>[ 15.300860] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 16:56:35.206525 <6>[ 15.304081] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10689 16:56:35.213220 <6>[ 15.306959] usbcore: registered new interface driver r8152
10690 16:56:35.216041 <6>[ 15.313029] Bluetooth: Core ver 2.22
10691 16:56:35.223326 <6>[ 15.313135] NET: Registered PF_BLUETOOTH protocol family
10692 16:56:35.226062 <6>[ 15.313138] Bluetooth: HCI device and connection manager initialized
10693 16:56:35.233322 <6>[ 15.313165] Bluetooth: HCI socket layer initialized
10694 16:56:35.239673 <6>[ 15.313172] Bluetooth: L2CAP socket layer initialized
10695 16:56:35.243420 <6>[ 15.313184] Bluetooth: SCO socket layer initialized
10696 16:56:35.252991 <3>[ 15.314657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 16:56:35.260845 <3>[ 15.315214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 16:56:35.267238 <4>[ 15.331776] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10699 16:56:35.273772 <4>[ 15.331776] Fallback method does not support PEC.
10700 16:56:35.280078 <3>[ 15.337858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10701 16:56:35.289902 <3>[ 15.337871] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10702 16:56:35.296839 <3>[ 15.361098] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 16:56:35.303230 <6>[ 15.363188] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10704 16:56:35.310162 <6>[ 15.363199] pci_bus 0000:00: root bus resource [bus 00-ff]
10705 16:56:35.316345 <6>[ 15.363209] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10706 16:56:35.326791 <6>[ 15.363216] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10707 16:56:35.333062 <6>[ 15.363253] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10708 16:56:35.343004 <6>[ 15.363274] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10709 16:56:35.346169 <6>[ 15.363365] pci 0000:00:00.0: supports D1 D2
10710 16:56:35.352962 <6>[ 15.363371] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 16:56:35.359426 <3>[ 15.364837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10712 16:56:35.369340 <6>[ 15.365262] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10713 16:56:35.375775 <6>[ 15.365378] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10714 16:56:35.382129 <6>[ 15.365407] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10715 16:56:35.389274 <6>[ 15.365427] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10716 16:56:35.398654 <6>[ 15.365444] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10717 16:56:35.402637 <6>[ 15.365607] pci 0000:01:00.0: supports D1 D2
10718 16:56:35.408793 <6>[ 15.365611] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10719 16:56:35.415184 <6>[ 15.377547] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10720 16:56:35.425867 <3>[ 15.383268] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 16:56:35.431823 <6>[ 15.391368] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10722 16:56:35.441608 <3>[ 15.392228] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 16:56:35.448268 <3>[ 15.405018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 16:56:35.455245 <6>[ 15.410035] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10725 16:56:35.464986 <6>[ 15.413057] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10726 16:56:35.471340 <3>[ 15.421171] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 16:56:35.481053 <6>[ 15.422588] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10728 16:56:35.491143 <6>[ 15.423041] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10729 16:56:35.497680 <3>[ 15.425805] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10730 16:56:35.504431 <6>[ 15.429917] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10731 16:56:35.515201 <3>[ 15.436773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 16:56:35.523849 <4>[ 15.436806] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10733 16:56:35.530994 <4>[ 15.436815] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10734 16:56:35.540695 <6>[ 15.442520] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10735 16:56:35.546977 <3>[ 15.449633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 16:56:35.554210 <6>[ 15.459544] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10737 16:56:35.563486 <3>[ 15.465843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 16:56:35.570326 <3>[ 15.465852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 16:56:35.580313 <3>[ 15.465858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 16:56:35.583184 <6>[ 15.473389] pci 0000:00:00.0: PCI bridge to [bus 01]
10741 16:56:35.593518 <3>[ 15.477853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 16:56:35.599823 <3>[ 15.477861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 16:56:35.609797 <3>[ 15.477891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 16:56:35.616998 <6>[ 15.484736] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10745 16:56:35.620252 <6>[ 15.493679] r8152 2-1.3:1.0 eth0: v1.12.13
10746 16:56:35.626513 <6>[ 15.501275] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10747 16:56:35.633207 <3>[ 15.533821] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10748 16:56:35.640013 <6>[ 15.535113] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10749 16:56:35.646015 <3>[ 15.645819] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10750 16:56:35.653264 <6>[ 15.655483] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10751 16:56:35.659451 <3>[ 15.663393] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10752 16:56:35.669355 <6>[ 15.791242] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10753 16:56:35.685414 <6>[ 15.811445] usbcore: registered new interface driver cdc_ether
10754 16:56:35.693167 <6>[ 15.819846] usbcore: registered new interface driver r8153_ecm
10755 16:56:35.699437 <6>[ 15.821062] usbcore: registered new interface driver btusb
10756 16:56:35.709629 <5>[ 15.821188] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10757 16:56:35.719137 <4>[ 15.821446] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10758 16:56:35.726152 <3>[ 15.821458] Bluetooth: hci0: Failed to load firmware file (-2)
10759 16:56:35.728966 <3>[ 15.821462] Bluetooth: hci0: Failed to set up firmware (-2)
10760 16:56:35.739235 <4>[ 15.821466] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10761 16:56:35.749422 <6>[ 15.832632] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10762 16:56:35.755560 <5>[ 15.835586] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10763 16:56:35.761958 <4>[ 15.835660] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10764 16:56:35.768715 <6>[ 15.835669] cfg80211: failed to load regulatory.db
10765 16:56:35.775782 <6>[ 15.836218] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10766 16:56:35.782030 <6>[ 15.858662] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10767 16:56:35.795260 <6>[ 15.914257] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10768 16:56:35.801637 <6>[ 15.927031] usbcore: registered new interface driver uvcvideo
10769 16:56:35.840740 <6>[ 15.964015] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10770 16:56:35.847062 <6>[ 15.971531] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10771 16:56:35.871158 <6>[ 15.998267] mt7921e 0000:01:00.0: ASIC revision: 79610010
10772 16:56:35.977912 <4>[ 16.097680] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 16:56:35.980564 Begin: Loading essential drivers ... done.
10774 16:56:35.987284 Begin: Running /scripts/init-premount ... done.
10775 16:56:35.993778 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10776 16:56:36.000496 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10777 16:56:36.007033 Device /sys/class/net/enx00e04c722dd6 found
10778 16:56:36.007599 done.
10779 16:56:36.018122 Begin: Waiting up to 180 secs for any network device to become available ... done.
10780 16:56:36.061940 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10781 16:56:36.099489 <4>[ 16.220048] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 16:56:36.218993 <4>[ 16.339318] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 16:56:36.335255 <4>[ 16.455340] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 16:56:36.450894 <4>[ 16.571234] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 16:56:36.566860 <4>[ 16.687161] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 16:56:36.682298 <4>[ 16.803065] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10787 16:56:36.798811 <4>[ 16.919032] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10788 16:56:36.914425 <4>[ 17.035121] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 16:56:37.030692 <4>[ 17.151002] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10790 16:56:37.089253 <6>[ 17.215105] r8152 2-1.3:1.0 enx00e04c722dd6: carrier on
10791 16:56:37.137775 <3>[ 17.264909] mt7921e 0000:01:00.0: hardware init failed
10792 16:56:38.057333 IP-Config: no response after 2 secs - giving up
10793 16:56:38.093704 IP-Config: enx00e04c722dd6 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10794 16:56:38.097245 IP-Config: enx00e04c722dd6 complete (dhcp from 192.168.201.1):
10795 16:56:38.106312 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10796 16:56:38.113298 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10797 16:56:38.119240 host : mt8192-asurada-spherion-r0-cbg-1
10798 16:56:38.125945 domain : lava-rack
10799 16:56:38.129105 rootserver: 192.168.201.1 rootpath:
10800 16:56:38.129187 filename :
10801 16:56:38.142849 done.
10802 16:56:38.151257 Begin: Running /scripts/nfs-bottom ... done.
10803 16:56:38.170097 Begin: Running /scripts/init-bottom ... done.
10804 16:56:39.405074 <6>[ 19.531732] NET: Registered PF_INET6 protocol family
10805 16:56:39.410732 <6>[ 19.538399] Segment Routing with IPv6
10806 16:56:39.414516 <6>[ 19.542381] In-situ OAM (IOAM) with IPv6
10807 16:56:39.589970 <30>[ 19.690675] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10808 16:56:39.595921 <30>[ 19.722982] systemd[1]: Detected architecture arm64.
10809 16:56:39.603108
10810 16:56:39.606333 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10811 16:56:39.606993
10812 16:56:39.632302 <30>[ 19.759447] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10813 16:56:40.305349 <30>[ 20.429850] systemd[1]: Queued start job for default target graphical.target.
10814 16:56:40.351361 <30>[ 20.475826] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10815 16:56:40.358629 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10816 16:56:40.378579 <30>[ 20.502600] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10817 16:56:40.388165 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10818 16:56:40.406896 <30>[ 20.531228] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10819 16:56:40.416889 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10820 16:56:40.434887 <30>[ 20.558950] systemd[1]: Created slice user.slice - User and Session Slice.
10821 16:56:40.440908 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10822 16:56:40.461171 <30>[ 20.582033] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10823 16:56:40.467912 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10824 16:56:40.489274 <30>[ 20.609965] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10825 16:56:40.495618 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10826 16:56:40.523954 <30>[ 20.638140] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10827 16:56:40.534528 <30>[ 20.657979] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10828 16:56:40.540551 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10829 16:56:40.557967 <30>[ 20.682117] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10830 16:56:40.567604 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10831 16:56:40.582584 <30>[ 20.710149] systemd[1]: Reached target paths.target - Path Units.
10832 16:56:40.589528 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10833 16:56:40.609939 <30>[ 20.734015] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10834 16:56:40.616185 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10835 16:56:40.630618 <30>[ 20.757848] systemd[1]: Reached target slices.target - Slice Units.
10836 16:56:40.640239 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10837 16:56:40.654456 <30>[ 20.782125] systemd[1]: Reached target swap.target - Swaps.
10838 16:56:40.660913 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10839 16:56:40.681698 <30>[ 20.805883] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10840 16:56:40.691361 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10841 16:56:40.710197 <30>[ 20.834441] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10842 16:56:40.719768 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10843 16:56:40.739104 <30>[ 20.863593] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10844 16:56:40.749180 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10845 16:56:40.766846 <30>[ 20.891093] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10846 16:56:40.776705 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10847 16:56:40.794009 <30>[ 20.918156] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10848 16:56:40.800451 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10849 16:56:40.818744 <30>[ 20.943001] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10850 16:56:40.828747 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10851 16:56:40.847868 <30>[ 20.972266] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10852 16:56:40.857731 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10853 16:56:40.873851 <30>[ 20.998081] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10854 16:56:40.883666 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10855 16:56:40.918031 <30>[ 21.042243] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10856 16:56:40.924725 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10857 16:56:40.943896 <30>[ 21.068346] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10858 16:56:40.950314 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10859 16:56:40.972426 <30>[ 21.096535] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10860 16:56:40.978284 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10861 16:56:41.004280 <30>[ 21.122138] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10862 16:56:41.017024 <30>[ 21.141190] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10863 16:56:41.027053 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10864 16:56:41.048313 <30>[ 21.172820] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10865 16:56:41.054629 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10866 16:56:41.076800 <30>[ 21.200841] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10867 16:56:41.082511 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10868 16:56:41.104107 <30>[ 21.228842] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10869 16:56:41.117731 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 21.242032] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10870 16:56:41.121404 l Module drm...
10871 16:56:41.140611 <30>[ 21.265025] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10872 16:56:41.150511 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10873 16:56:41.169009 <30>[ 21.293124] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10874 16:56:41.175090 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10875 16:56:41.200699 <30>[ 21.325257] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10876 16:56:41.208135 Startin<6>[ 21.334510] fuse: init (API version 7.37)
10877 16:56:41.214157 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10878 16:56:41.235381 <30>[ 21.359201] systemd[1]: Starting systemd-journald.service - Journal Service...
10879 16:56:41.241498 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10880 16:56:41.265544 <30>[ 21.390032] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10881 16:56:41.272068 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10882 16:56:41.296080 <30>[ 21.417027] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10883 16:56:41.302604 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10884 16:56:41.325038 <30>[ 21.449131] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10885 16:56:41.334604 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10886 16:56:41.357996 <30>[ 21.482033] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10887 16:56:41.364641 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10888 16:56:41.391289 <3>[ 21.515475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 16:56:41.397593 <30>[ 21.517480] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10890 16:56:41.407722 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10891 16:56:41.425608 <3>[ 21.550236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 16:56:41.435555 <30>[ 21.550244] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10893 16:56:41.442217 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10894 16:56:41.461635 <30>[ 21.586264] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10895 16:56:41.468634 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10896 16:56:41.479073 <3>[ 21.603720] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 16:56:41.489080 <30>[ 21.613400] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10898 16:56:41.499959 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10899 16:56:41.510404 <3>[ 21.633244] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 16:56:41.519569 <30>[ 21.643386] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10901 16:56:41.526259 <30>[ 21.651628] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10902 16:56:41.539590 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c<3>[ 21.664251] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 16:56:41.546492 onfigfs…[0m - Load Kernel Module configfs.
10904 16:56:41.563677 <30>[ 21.686941] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10905 16:56:41.569327 <30>[ 21.694693] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10906 16:56:41.579466 <3>[ 21.697665] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 16:56:41.586536 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10908 16:56:41.604553 <30>[ 21.731138] systemd[1]: modprobe@drm.service: Deactivated successfully.
10909 16:56:41.614348 <3>[ 21.737525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 16:56:41.620891 <30>[ 21.738595] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10911 16:56:41.630270 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10912 16:56:41.646791 <3>[ 21.770451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 16:56:41.656170 <30>[ 21.780586] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10914 16:56:41.666637 <30>[ 21.788592] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10915 16:56:41.676477 [[0;32m OK [0m] Finished [0<3>[ 21.800256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 16:56:41.683243 ;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10917 16:56:41.698911 <30>[ 21.823180] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10918 16:56:41.705881 <30>[ 21.830855] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10919 16:56:41.715619 <3>[ 21.834100] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 16:56:41.722281 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10921 16:56:41.743259 <30>[ 21.867322] systemd[1]: modprobe@loop.service: Deactivated successfully.
10922 16:56:41.749867 <30>[ 21.874794] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10923 16:56:41.756697 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10924 16:56:41.778345 <30>[ 21.902537] systemd[1]: Started systemd-journald.service - Journal Service.
10925 16:56:41.784979 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10926 16:56:41.803808 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10927 16:56:41.823282 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10928 16:56:41.842791 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10929 16:56:41.863106 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10930 16:56:41.910271 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10931 16:56:41.932449 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10932 16:56:41.963117 Starting [0;1;39msystemd-journal-f…h<4>[ 22.081230] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10933 16:56:41.973420 Journal to Pers<3>[ 22.097542] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10934 16:56:41.976389 istent Storage...
10935 16:56:42.026798 Startin<46>[ 22.150718] systemd-journald[298]: Received client request to flush runtime journal.
10936 16:56:42.032253 g [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10937 16:56:42.060904 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10938 16:56:42.270099 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10939 16:56:42.291806 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10940 16:56:42.309351 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10941 16:56:42.325052 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10942 16:56:42.782876 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10943 16:56:43.396578 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10944 16:56:43.413516 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10945 16:56:43.438214 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10946 16:56:43.482064 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10947 16:56:43.559869 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10948 16:56:43.581778 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10949 16:56:43.601632 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10950 16:56:43.661710 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
10951 16:56:43.681319 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10952 16:56:43.700797 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10953 16:56:43.735332 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
10954 16:56:43.749618 See 'systemctl status systemd-binfmt.service' for details.
10955 16:56:43.923830 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10956 16:56:43.978960 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10957 16:56:44.000511 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10958 16:56:44.057226 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10959 16:56:44.180070 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10960 16:56:44.207058 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10961 16:56:44.401218 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10962 16:56:44.495068 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10963 16:56:44.513708 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10964 16:56:44.529716 <6>[ 24.657673] remoteproc remoteproc0: powering up scp
10965 16:56:44.543199 <4>[ 24.668080] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10966 16:56:44.550049 <3>[ 24.677993] remoteproc remoteproc0: request_firmware failed: -2
10967 16:56:44.559593 <3>[ 24.684608] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10968 16:56:44.575127 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10969 16:56:44.605176 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10970 16:56:44.621732 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10971 16:56:44.642127 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10972 16:56:44.666518 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10973 16:56:44.682653 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10974 16:56:44.701260 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10975 16:56:44.721416 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10976 16:56:44.737351 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10977 16:56:44.760706 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10978 16:56:44.780169 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10979 16:56:44.797235 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10980 16:56:44.816711 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10981 16:56:44.836948 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10982 16:56:44.853220 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10983 16:56:44.871779 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10984 16:56:44.889305 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10985 16:56:44.905113 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10986 16:56:44.954197 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10987 16:56:45.020836 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10988 16:56:45.100866 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10989 16:56:45.123477 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10990 16:56:45.143966 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10991 16:56:45.307172 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10992 16:56:45.364332 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10993 16:56:45.387711 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10994 16:56:45.407363 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10995 16:56:45.427390 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10996 16:56:45.445847 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10997 16:56:45.472374 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10998 16:56:45.492065 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10999 16:56:45.516413 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11000 16:56:45.535491 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11001 16:56:45.598996 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11002 16:56:45.616572 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11003 16:56:45.674078 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11004 16:56:45.775291 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11005 16:56:45.852464
11006 16:56:45.852622
11007 16:56:45.856095 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11008 16:56:45.856177
11009 16:56:45.859071 debian-bookworm-arm64 login: root (automatic login)
11010 16:56:45.859154
11011 16:56:45.859220
11012 16:56:46.111962 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
11013 16:56:46.112108
11014 16:56:46.118480 The programs included with the Debian GNU/Linux system are free software;
11015 16:56:46.125197 the exact distribution terms for each program are described in the
11016 16:56:46.128718 individual files in /usr/share/doc/*/copyright.
11017 16:56:46.128837
11018 16:56:46.135150 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11019 16:56:46.138209 permitted by applicable law.
11020 16:56:47.029374 Matched prompt #10: / #
11022 16:56:47.029676 Setting prompt string to ['/ #']
11023 16:56:47.029776 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11025 16:56:47.029980 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11026 16:56:47.030077 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
11027 16:56:47.030153 Setting prompt string to ['/ #']
11028 16:56:47.030217 Forcing a shell prompt, looking for ['/ #']
11030 16:56:47.080632 / #
11031 16:56:47.081072 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11032 16:56:47.081434 Waiting using forced prompt support (timeout 00:02:30)
11033 16:56:47.086468
11034 16:56:47.087293 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11035 16:56:47.087817 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
11037 16:56:47.189170 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb'
11038 16:56:47.195293 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576342/extract-nfsrootfs-3z2080zb'
11040 16:56:47.297158 / # export NFS_SERVER_IP='192.168.201.1'
11041 16:56:47.303435 export NFS_SERVER_IP='192.168.201.1'
11042 16:56:47.304373 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11043 16:56:47.304909 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
11044 16:56:47.305402 end: 2 depthcharge-action (duration 00:01:39) [common]
11045 16:56:47.305887 start: 3 lava-test-retry (timeout 00:07:43) [common]
11046 16:56:47.306407 start: 3.1 lava-test-shell (timeout 00:07:43) [common]
11047 16:56:47.306845 Using namespace: common
11049 16:56:47.408146 / # #
11050 16:56:47.408800 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11051 16:56:47.414714 #
11052 16:56:47.415783 Using /lava-10576342
11054 16:56:47.517191 / # export SHELL=/bin/bash
11055 16:56:47.523830 export SHELL=/bin/bash
11057 16:56:47.625679 / # . /lava-10576342/environment
11058 16:56:47.632257 . /lava-10576342/environment
11060 16:56:47.739049 / # /lava-10576342/bin/lava-test-runner /lava-10576342/0
11061 16:56:47.739705 Test shell timeout: 10s (minimum of the action and connection timeout)
11062 16:56:47.745448 /lava-10576342/bin/lava-test-runner /lava-10576342/0
11063 16:56:47.959872 + export TESTRUN_ID=0_timesync-off
11064 16:56:47.963041 + TESTRUN_ID=0_timesync-off
11065 16:56:47.966722 + cd /lava-10576342/0/tests/0_timesync-off
11066 16:56:47.970035 ++ cat uuid
11067 16:56:47.976806 + UUID=10576342_1.6.2.3.1
11068 16:56:47.977234 + set +x
11069 16:56:47.984127 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10576342_1.6.2.3.1>
11070 16:56:47.984837 Received signal: <STARTRUN> 0_timesync-off 10576342_1.6.2.3.1
11071 16:56:47.985204 Starting test lava.0_timesync-off (10576342_1.6.2.3.1)
11072 16:56:47.985618 Skipping test definition patterns.
11073 16:56:47.987018 + systemctl stop systemd-timesyncd
11074 16:56:48.029174 + set +x
11075 16:56:48.031884 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10576342_1.6.2.3.1>
11076 16:56:48.032567 Received signal: <ENDRUN> 0_timesync-off 10576342_1.6.2.3.1
11077 16:56:48.032969 Ending use of test pattern.
11078 16:56:48.033293 Ending test lava.0_timesync-off (10576342_1.6.2.3.1), duration 0.05
11080 16:56:48.087515 + export TESTRUN_ID=1_kselftest-alsa
11081 16:56:48.090752 + TESTRUN_ID=1_kselftest-alsa
11082 16:56:48.097152 + cd /lava-10576342/0/tests/1_kselftest-alsa
11083 16:56:48.097237 ++ cat uuid
11084 16:56:48.100129 + UUID=10576342_1.6.2.3.5
11085 16:56:48.100213 + set +x
11086 16:56:48.103425 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10576342_1.6.2.3.5>
11087 16:56:48.103683 Received signal: <STARTRUN> 1_kselftest-alsa 10576342_1.6.2.3.5
11088 16:56:48.103758 Starting test lava.1_kselftest-alsa (10576342_1.6.2.3.5)
11089 16:56:48.103839 Skipping test definition patterns.
11090 16:56:48.107134 + cd ./automated/linux/kselftest/
11091 16:56:48.136468 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11092 16:56:48.158245 INFO: install_deps skipped
11093 16:56:48.629124 --2023-06-03 16:56:48-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11094 16:56:48.635293 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11095 16:56:48.777724 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11096 16:56:48.920410 HTTP request sent, awaiting response... 200 OK
11097 16:56:48.923429 Length: 2713064 (2.6M) [application/octet-stream]
11098 16:56:48.927631 Saving to: 'kselftest.tar.xz'
11099 16:56:48.928220
11100 16:56:48.928602
11101 16:56:49.205332 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11102 16:56:49.491377 kselftest.tar.xz 1%[ ] 47.81K 166KB/s
11103 16:56:49.968710 kselftest.tar.xz 8%[> ] 216.08K 373KB/s
11104 16:56:50.265403 kselftest.tar.xz 31%[=====> ] 822.71K 772KB/s
11105 16:56:50.271683 kselftest.tar.xz 92%[=================> ] 2.39M 1.75MB/s
11106 16:56:50.278138 kselftest.tar.xz 100%[===================>] 2.59M 1.89MB/s in 1.4s
11107 16:56:50.278835
11108 16:56:50.507635 2023-06-03 16:56:50 (1.89 MB/s) - 'kselftest.tar.xz' saved [2713064/2713064]
11109 16:56:50.507818
11110 16:56:54.953048 skiplist:
11111 16:56:54.955673 ========================================
11112 16:56:54.958814 ========================================
11113 16:56:54.994318 alsa:mixer-test
11114 16:56:55.011569 ============== Tests to run ===============
11115 16:56:55.011652 alsa:mixer-test
11116 16:56:55.014910 ===========End Tests to run ===============
11117 16:56:55.099389 <12>[ 35.228615] kselftest: Running tests in alsa
11118 16:56:55.107647 TAP version 13
11119 16:56:55.121858 1..1
11120 16:56:55.135237 # selftests: alsa: mixer-test
11121 16:56:55.554887 # TAP version 13
11122 16:56:55.555095 # 1..0
11123 16:56:55.561688 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11124 16:56:55.564755 ok 1 selftests: alsa: mixer-test
11125 16:56:56.209419 alsa_mixer-test pass
11126 16:56:56.240993 + ../../utils/send-to-lava.sh ./output/result.txt
11127 16:56:56.303613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11128 16:56:56.303782 + set +x
11129 16:56:56.304058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11131 16:56:56.309887 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10576342_1.6.2.3.5>
11132 16:56:56.310244 Received signal: <ENDRUN> 1_kselftest-alsa 10576342_1.6.2.3.5
11133 16:56:56.310363 Ending use of test pattern.
11134 16:56:56.310474 Ending test lava.1_kselftest-alsa (10576342_1.6.2.3.5), duration 8.21
11136 16:56:56.313481 <LAVA_TEST_RUNNER EXIT>
11137 16:56:56.313856 ok: lava_test_shell seems to have completed
11138 16:56:56.314003 alsa_mixer-test: pass
11139 16:56:56.314124 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11140 16:56:56.314244 end: 3 lava-test-retry (duration 00:00:09) [common]
11141 16:56:56.314375 start: 4 finalize (timeout 00:07:34) [common]
11142 16:56:56.314488 start: 4.1 power-off (timeout 00:00:30) [common]
11143 16:56:56.314677 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
11144 16:56:56.406050 >> Command sent successfully.
11145 16:56:56.417375 Returned 0 in 0 seconds
11146 16:56:56.518772 end: 4.1 power-off (duration 00:00:00) [common]
11148 16:56:56.520408 start: 4.2 read-feedback (timeout 00:07:34) [common]
11149 16:56:56.521746 Listened to connection for namespace 'common' for up to 1s
11150 16:56:57.522425 Finalising connection for namespace 'common'
11151 16:56:57.523133 Disconnecting from shell: Finalise
11152 16:56:57.523805 / #
11153 16:56:57.624939 end: 4.2 read-feedback (duration 00:00:01) [common]
11154 16:56:57.625825 end: 4 finalize (duration 00:00:01) [common]
11155 16:56:57.626493 Cleaning after the job
11156 16:56:57.627083 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/ramdisk
11157 16:56:57.638777 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/kernel
11158 16:56:57.669929 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/dtb
11159 16:56:57.670308 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/nfsrootfs
11160 16:56:57.750577 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576342/tftp-deploy-a8bjz08n/modules
11161 16:56:57.755892 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576342
11162 16:56:58.264985 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576342
11163 16:56:58.265172 Job finished correctly