Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 16:43:01.302495 lava-dispatcher, installed at version: 2023.03
2 16:43:01.302719 start: 0 validate
3 16:43:01.302849 Start time: 2023-06-03 16:43:01.302841+00:00 (UTC)
4 16:43:01.302982 Using caching service: 'http://localhost/cache/?uri=%s'
5 16:43:01.303114 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 16:43:01.590495 Using caching service: 'http://localhost/cache/?uri=%s'
7 16:43:01.591225 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 16:43:01.875982 Using caching service: 'http://localhost/cache/?uri=%s'
9 16:43:01.876870 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 16:43:19.311609 Using caching service: 'http://localhost/cache/?uri=%s'
11 16:43:19.312584 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:43:19.876872 Using caching service: 'http://localhost/cache/?uri=%s'
13 16:43:19.877102 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.26-1281-g84d5372e0f31%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 16:43:20.174341 validate duration: 18.87
16 16:43:20.175616 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:43:20.176261 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:43:20.176759 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:43:20.177366 Not decompressing ramdisk as can be used compressed.
20 16:43:20.177885 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 16:43:20.178271 saving as /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/ramdisk/initrd.cpio.gz
22 16:43:20.178625 total size: 4665601 (4MB)
23 16:43:23.777351 progress 0% (0MB)
24 16:43:23.779004 progress 5% (0MB)
25 16:43:23.780281 progress 10% (0MB)
26 16:43:23.781596 progress 15% (0MB)
27 16:43:23.782865 progress 20% (0MB)
28 16:43:23.784078 progress 25% (1MB)
29 16:43:23.785372 progress 30% (1MB)
30 16:43:23.786674 progress 35% (1MB)
31 16:43:23.787889 progress 40% (1MB)
32 16:43:23.789310 progress 45% (2MB)
33 16:43:23.790583 progress 50% (2MB)
34 16:43:23.791797 progress 55% (2MB)
35 16:43:23.793018 progress 60% (2MB)
36 16:43:23.794286 progress 65% (2MB)
37 16:43:23.795529 progress 70% (3MB)
38 16:43:23.796782 progress 75% (3MB)
39 16:43:23.798027 progress 80% (3MB)
40 16:43:23.799404 progress 85% (3MB)
41 16:43:23.800631 progress 90% (4MB)
42 16:43:23.801926 progress 95% (4MB)
43 16:43:23.803167 progress 100% (4MB)
44 16:43:23.803337 4MB downloaded in 3.62s (1.23MB/s)
45 16:43:23.803498 end: 1.1.1 http-download (duration 00:00:04) [common]
47 16:43:23.803762 end: 1.1 download-retry (duration 00:00:04) [common]
48 16:43:23.803865 start: 1.2 download-retry (timeout 00:09:56) [common]
49 16:43:23.803965 start: 1.2.1 http-download (timeout 00:09:56) [common]
50 16:43:23.804114 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 16:43:23.804216 saving as /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/kernel/Image
52 16:43:23.804367 total size: 45746688 (43MB)
53 16:43:23.804465 No compression specified
54 16:43:23.806111 progress 0% (0MB)
55 16:43:23.817827 progress 5% (2MB)
56 16:43:23.829417 progress 10% (4MB)
57 16:43:23.842451 progress 15% (6MB)
58 16:43:23.855208 progress 20% (8MB)
59 16:43:23.867819 progress 25% (10MB)
60 16:43:23.880342 progress 30% (13MB)
61 16:43:24.139805 progress 35% (15MB)
62 16:43:24.152259 progress 40% (17MB)
63 16:43:24.164584 progress 45% (19MB)
64 16:43:24.177051 progress 50% (21MB)
65 16:43:24.188696 progress 55% (24MB)
66 16:43:24.200651 progress 60% (26MB)
67 16:43:24.212639 progress 65% (28MB)
68 16:43:24.224859 progress 70% (30MB)
69 16:43:24.237211 progress 75% (32MB)
70 16:43:24.249327 progress 80% (34MB)
71 16:43:24.261128 progress 85% (37MB)
72 16:43:24.272974 progress 90% (39MB)
73 16:43:24.285075 progress 95% (41MB)
74 16:43:24.297092 progress 100% (43MB)
75 16:43:24.297262 43MB downloaded in 0.49s (88.51MB/s)
76 16:43:24.297418 end: 1.2.1 http-download (duration 00:00:00) [common]
78 16:43:24.297687 end: 1.2 download-retry (duration 00:00:00) [common]
79 16:43:24.297777 start: 1.3 download-retry (timeout 00:09:56) [common]
80 16:43:24.297872 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 16:43:24.298017 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 16:43:24.298090 saving as /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/dtb/mt8192-asurada-spherion-r0.dtb
83 16:43:24.298154 total size: 46924 (0MB)
84 16:43:24.298214 No compression specified
85 16:43:24.299346 progress 69% (0MB)
86 16:43:24.299621 progress 100% (0MB)
87 16:43:24.299777 0MB downloaded in 0.00s (27.61MB/s)
88 16:43:24.299902 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:43:24.300138 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:43:24.300226 start: 1.4 download-retry (timeout 00:09:56) [common]
92 16:43:24.300311 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 16:43:24.300425 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 16:43:24.300495 saving as /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/nfsrootfs/full.rootfs.tar
95 16:43:24.300557 total size: 200770336 (191MB)
96 16:43:24.300646 Using unxz to decompress xz
97 16:43:24.304403 progress 0% (0MB)
98 16:43:24.840745 progress 5% (9MB)
99 16:43:25.373458 progress 10% (19MB)
100 16:43:25.972919 progress 15% (28MB)
101 16:43:26.359278 progress 20% (38MB)
102 16:43:26.693193 progress 25% (47MB)
103 16:43:27.312700 progress 30% (57MB)
104 16:43:27.885785 progress 35% (67MB)
105 16:43:28.505738 progress 40% (76MB)
106 16:43:29.098357 progress 45% (86MB)
107 16:43:29.689355 progress 50% (95MB)
108 16:43:30.363589 progress 55% (105MB)
109 16:43:31.060487 progress 60% (114MB)
110 16:43:31.196094 progress 65% (124MB)
111 16:43:31.388198 progress 70% (134MB)
112 16:43:31.486724 progress 75% (143MB)
113 16:43:31.562035 progress 80% (153MB)
114 16:43:31.640006 progress 85% (162MB)
115 16:43:31.739802 progress 90% (172MB)
116 16:43:32.027371 progress 95% (181MB)
117 16:43:32.629157 progress 100% (191MB)
118 16:43:32.633993 191MB downloaded in 8.33s (22.98MB/s)
119 16:43:32.634375 end: 1.4.1 http-download (duration 00:00:08) [common]
121 16:43:32.634794 end: 1.4 download-retry (duration 00:00:08) [common]
122 16:43:32.634921 start: 1.5 download-retry (timeout 00:09:48) [common]
123 16:43:32.635045 start: 1.5.1 http-download (timeout 00:09:48) [common]
124 16:43:32.635216 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 16:43:32.635319 saving as /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/modules/modules.tar
126 16:43:32.635412 total size: 8545664 (8MB)
127 16:43:32.635504 Using unxz to decompress xz
128 16:43:32.933945 progress 0% (0MB)
129 16:43:32.956162 progress 5% (0MB)
130 16:43:32.982814 progress 10% (0MB)
131 16:43:33.010068 progress 15% (1MB)
132 16:43:33.035919 progress 20% (1MB)
133 16:43:33.062502 progress 25% (2MB)
134 16:43:33.088895 progress 30% (2MB)
135 16:43:33.114963 progress 35% (2MB)
136 16:43:33.140502 progress 40% (3MB)
137 16:43:33.166237 progress 45% (3MB)
138 16:43:33.190747 progress 50% (4MB)
139 16:43:33.214290 progress 55% (4MB)
140 16:43:33.239345 progress 60% (4MB)
141 16:43:33.264885 progress 65% (5MB)
142 16:43:33.290587 progress 70% (5MB)
143 16:43:33.318037 progress 75% (6MB)
144 16:43:33.348396 progress 80% (6MB)
145 16:43:33.371045 progress 85% (6MB)
146 16:43:33.396550 progress 90% (7MB)
147 16:43:33.421447 progress 95% (7MB)
148 16:43:33.446137 progress 100% (8MB)
149 16:43:33.451989 8MB downloaded in 0.82s (9.98MB/s)
150 16:43:33.452300 end: 1.5.1 http-download (duration 00:00:01) [common]
152 16:43:33.452583 end: 1.5 download-retry (duration 00:00:01) [common]
153 16:43:33.452682 start: 1.6 prepare-tftp-overlay (timeout 00:09:47) [common]
154 16:43:33.452778 start: 1.6.1 extract-nfsrootfs (timeout 00:09:47) [common]
155 16:43:37.291754 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf
156 16:43:37.291986 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 16:43:37.292125 start: 1.6.2 lava-overlay (timeout 00:09:43) [common]
158 16:43:37.292301 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8
159 16:43:37.292430 makedir: /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin
160 16:43:37.292531 makedir: /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/tests
161 16:43:37.292633 makedir: /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/results
162 16:43:37.292740 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-add-keys
163 16:43:37.292890 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-add-sources
164 16:43:37.293041 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-background-process-start
165 16:43:37.293186 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-background-process-stop
166 16:43:37.293314 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-common-functions
167 16:43:37.293458 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-echo-ipv4
168 16:43:37.293899 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-install-packages
169 16:43:37.294068 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-installed-packages
170 16:43:37.294232 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-os-build
171 16:43:37.294390 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-probe-channel
172 16:43:37.294518 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-probe-ip
173 16:43:37.294642 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-target-ip
174 16:43:37.294766 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-target-mac
175 16:43:37.294888 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-target-storage
176 16:43:37.295012 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-case
177 16:43:37.295136 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-event
178 16:43:37.295257 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-feedback
179 16:43:37.295379 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-raise
180 16:43:37.295501 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-reference
181 16:43:37.295629 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-runner
182 16:43:37.295752 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-set
183 16:43:37.295878 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-test-shell
184 16:43:37.296003 Updating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-add-keys (debian)
185 16:43:37.296165 Updating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-add-sources (debian)
186 16:43:37.296310 Updating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-install-packages (debian)
187 16:43:37.296453 Updating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-installed-packages (debian)
188 16:43:37.296593 Updating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/bin/lava-os-build (debian)
189 16:43:37.296721 Creating /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/environment
190 16:43:37.296822 LAVA metadata
191 16:43:37.296900 - LAVA_JOB_ID=10576287
192 16:43:37.296983 - LAVA_DISPATCHER_IP=192.168.201.1
193 16:43:37.297095 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:43) [common]
194 16:43:37.297164 skipped lava-vland-overlay
195 16:43:37.297240 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 16:43:37.297322 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:43) [common]
197 16:43:37.297383 skipped lava-multinode-overlay
198 16:43:37.297462 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 16:43:37.297579 start: 1.6.2.3 test-definition (timeout 00:09:43) [common]
200 16:43:37.297660 Loading test definitions
201 16:43:37.297762 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:43) [common]
202 16:43:37.297866 Using /lava-10576287 at stage 0
203 16:43:37.298243 uuid=10576287_1.6.2.3.1 testdef=None
204 16:43:37.298353 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 16:43:37.298474 start: 1.6.2.3.2 test-overlay (timeout 00:09:43) [common]
206 16:43:37.299052 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 16:43:37.299284 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:43) [common]
209 16:43:37.300007 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 16:43:37.300245 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:43) [common]
212 16:43:37.300787 runner path: /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/0/tests/0_timesync-off test_uuid 10576287_1.6.2.3.1
213 16:43:37.300942 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 16:43:37.301171 start: 1.6.2.3.5 git-repo-action (timeout 00:09:43) [common]
216 16:43:37.301246 Using /lava-10576287 at stage 0
217 16:43:37.301346 Fetching tests from https://github.com/kernelci/test-definitions.git
218 16:43:37.301425 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/0/tests/1_kselftest-arm64'
219 16:43:40.860124 Running '/usr/bin/git checkout kernelci.org
220 16:43:41.007548 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 16:43:41.008281 uuid=10576287_1.6.2.3.5 testdef=None
222 16:43:41.008447 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 16:43:41.008702 start: 1.6.2.3.6 test-overlay (timeout 00:09:39) [common]
225 16:43:41.009441 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 16:43:41.009884 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:39) [common]
228 16:43:41.010884 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 16:43:41.011122 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:39) [common]
231 16:43:41.012130 runner path: /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/0/tests/1_kselftest-arm64 test_uuid 10576287_1.6.2.3.5
232 16:43:41.012226 BOARD='mt8192-asurada-spherion-r0'
233 16:43:41.012291 BRANCH='cip-gitlab'
234 16:43:41.012352 SKIPFILE='/dev/null'
235 16:43:41.012410 SKIP_INSTALL='True'
236 16:43:41.012481 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 16:43:41.012552 TST_CASENAME=''
238 16:43:41.012606 TST_CMDFILES='arm64'
239 16:43:41.012757 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 16:43:41.012966 Creating lava-test-runner.conf files
242 16:43:41.013030 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10576287/lava-overlay-1sh6_cq8/lava-10576287/0 for stage 0
243 16:43:41.013124 - 0_timesync-off
244 16:43:41.013196 - 1_kselftest-arm64
245 16:43:41.013294 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 16:43:41.013381 start: 1.6.2.4 compress-overlay (timeout 00:09:39) [common]
247 16:43:48.724010 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 16:43:48.724168 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:31) [common]
249 16:43:48.724263 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 16:43:48.724365 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 16:43:48.724458 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:31) [common]
252 16:43:48.839237 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 16:43:48.839605 start: 1.6.4 extract-modules (timeout 00:09:31) [common]
254 16:43:48.839722 extracting modules file /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf
255 16:43:49.039501 extracting modules file /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10576287/extract-overlay-ramdisk-dob07_ts/ramdisk
256 16:43:49.245773 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 16:43:49.245936 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
258 16:43:49.246035 [common] Applying overlay to NFS
259 16:43:49.246105 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10576287/compress-overlay-tx40lyyr/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf
260 16:43:50.156889 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 16:43:50.157049 start: 1.6.6 configure-preseed-file (timeout 00:09:30) [common]
262 16:43:50.157146 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 16:43:50.157238 start: 1.6.7 compress-ramdisk (timeout 00:09:30) [common]
264 16:43:50.157320 Building ramdisk /var/lib/lava/dispatcher/tmp/10576287/extract-overlay-ramdisk-dob07_ts/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10576287/extract-overlay-ramdisk-dob07_ts/ramdisk
265 16:43:50.440684 >> 117799 blocks
266 16:43:52.359534 rename /var/lib/lava/dispatcher/tmp/10576287/extract-overlay-ramdisk-dob07_ts/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/ramdisk/ramdisk.cpio.gz
267 16:43:52.359946 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 16:43:52.360067 start: 1.6.8 prepare-kernel (timeout 00:09:28) [common]
269 16:43:52.360172 start: 1.6.8.1 prepare-fit (timeout 00:09:28) [common]
270 16:43:52.360274 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/kernel/Image'
271 16:44:05.208279 Returned 0 in 12 seconds
272 16:44:05.308893 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/kernel/image.itb
273 16:44:05.622967 output: FIT description: Kernel Image image with one or more FDT blobs
274 16:44:05.623323 output: Created: Sat Jun 3 17:44:05 2023
275 16:44:05.623437 output: Image 0 (kernel-1)
276 16:44:05.623534 output: Description:
277 16:44:05.623635 output: Created: Sat Jun 3 17:44:05 2023
278 16:44:05.623735 output: Type: Kernel Image
279 16:44:05.623828 output: Compression: lzma compressed
280 16:44:05.623920 output: Data Size: 10083474 Bytes = 9847.14 KiB = 9.62 MiB
281 16:44:05.623986 output: Architecture: AArch64
282 16:44:05.624048 output: OS: Linux
283 16:44:05.624106 output: Load Address: 0x00000000
284 16:44:05.624171 output: Entry Point: 0x00000000
285 16:44:05.624264 output: Hash algo: crc32
286 16:44:05.624350 output: Hash value: b48eba69
287 16:44:05.624438 output: Image 1 (fdt-1)
288 16:44:05.624525 output: Description: mt8192-asurada-spherion-r0
289 16:44:05.624610 output: Created: Sat Jun 3 17:44:05 2023
290 16:44:05.624698 output: Type: Flat Device Tree
291 16:44:05.624786 output: Compression: uncompressed
292 16:44:05.624871 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 16:44:05.624959 output: Architecture: AArch64
294 16:44:05.625049 output: Hash algo: crc32
295 16:44:05.625134 output: Hash value: 1df858fa
296 16:44:05.625222 output: Image 2 (ramdisk-1)
297 16:44:05.625311 output: Description: unavailable
298 16:44:05.625395 output: Created: Sat Jun 3 17:44:05 2023
299 16:44:05.625485 output: Type: RAMDisk Image
300 16:44:05.625561 output: Compression: Unknown Compression
301 16:44:05.625619 output: Data Size: 17642121 Bytes = 17228.63 KiB = 16.82 MiB
302 16:44:05.625677 output: Architecture: AArch64
303 16:44:05.625741 output: OS: Linux
304 16:44:05.625799 output: Load Address: unavailable
305 16:44:05.625854 output: Entry Point: unavailable
306 16:44:05.625910 output: Hash algo: crc32
307 16:44:05.625976 output: Hash value: af6533fb
308 16:44:05.626033 output: Default Configuration: 'conf-1'
309 16:44:05.626088 output: Configuration 0 (conf-1)
310 16:44:05.626143 output: Description: mt8192-asurada-spherion-r0
311 16:44:05.626203 output: Kernel: kernel-1
312 16:44:05.626267 output: Init Ramdisk: ramdisk-1
313 16:44:05.626323 output: FDT: fdt-1
314 16:44:05.626379 output: Loadables: kernel-1
315 16:44:05.626438 output:
316 16:44:05.626654 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 16:44:05.626772 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 16:44:05.626886 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 16:44:05.626996 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:15) [common]
320 16:44:05.627080 No LXC device requested
321 16:44:05.627164 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 16:44:05.627266 start: 1.8 deploy-device-env (timeout 00:09:15) [common]
323 16:44:05.627350 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 16:44:05.627421 Checking files for TFTP limit of 4294967296 bytes.
325 16:44:05.627948 end: 1 tftp-deploy (duration 00:00:45) [common]
326 16:44:05.628070 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 16:44:05.628168 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 16:44:05.628305 substitutions:
329 16:44:05.628380 - {DTB}: 10576287/tftp-deploy-7h04q_ty/dtb/mt8192-asurada-spherion-r0.dtb
330 16:44:05.628454 - {INITRD}: 10576287/tftp-deploy-7h04q_ty/ramdisk/ramdisk.cpio.gz
331 16:44:05.628547 - {KERNEL}: 10576287/tftp-deploy-7h04q_ty/kernel/Image
332 16:44:05.628637 - {LAVA_MAC}: None
333 16:44:05.628734 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf
334 16:44:05.628825 - {NFS_SERVER_IP}: 192.168.201.1
335 16:44:05.628912 - {PRESEED_CONFIG}: None
336 16:44:05.629007 - {PRESEED_LOCAL}: None
337 16:44:05.629094 - {RAMDISK}: 10576287/tftp-deploy-7h04q_ty/ramdisk/ramdisk.cpio.gz
338 16:44:05.629184 - {ROOT_PART}: None
339 16:44:05.629280 - {ROOT}: None
340 16:44:05.629367 - {SERVER_IP}: 192.168.201.1
341 16:44:05.629464 - {TEE}: None
342 16:44:05.629553 Parsed boot commands:
343 16:44:05.629612 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 16:44:05.629810 Parsed boot commands: tftpboot 192.168.201.1 10576287/tftp-deploy-7h04q_ty/kernel/image.itb 10576287/tftp-deploy-7h04q_ty/kernel/cmdline
345 16:44:05.629907 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 16:44:05.630021 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 16:44:05.630120 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 16:44:05.630225 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 16:44:05.630306 Not connected, no need to disconnect.
350 16:44:05.630391 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 16:44:05.630501 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 16:44:05.630577 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 16:44:05.634481 Setting prompt string to ['lava-test: # ']
354 16:44:05.634864 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 16:44:05.635019 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 16:44:05.635162 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 16:44:05.635297 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 16:44:05.635641 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 16:44:10.768092 >> Command sent successfully.
360 16:44:10.770426 Returned 0 in 5 seconds
361 16:44:10.870820 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 16:44:10.871288 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 16:44:10.871443 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 16:44:10.871576 Setting prompt string to 'Starting depthcharge on Spherion...'
366 16:44:10.871696 Changing prompt to 'Starting depthcharge on Spherion...'
367 16:44:10.871808 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 16:44:10.872216 [Enter `^Ec?' for help]
369 16:44:11.045603
370 16:44:11.045786
371 16:44:11.045899 F0: 102B 0000
372 16:44:11.045999
373 16:44:11.046100 F3: 1001 0000 [0200]
374 16:44:11.046196
375 16:44:11.048719 F3: 1001 0000
376 16:44:11.048831
377 16:44:11.048939 F7: 102D 0000
378 16:44:11.049034
379 16:44:11.051967 F1: 0000 0000
380 16:44:11.052080
381 16:44:11.052174 V0: 0000 0000 [0001]
382 16:44:11.052280
383 16:44:11.055721 00: 0007 8000
384 16:44:11.055830
385 16:44:11.055934 01: 0000 0000
386 16:44:11.056029
387 16:44:11.056130 BP: 0C00 0209 [0000]
388 16:44:11.058838
389 16:44:11.058940 G0: 1182 0000
390 16:44:11.059045
391 16:44:11.059139 EC: 0000 0021 [4000]
392 16:44:11.062204
393 16:44:11.062305 S7: 0000 0000 [0000]
394 16:44:11.062402
395 16:44:11.066246 CC: 0000 0000 [0001]
396 16:44:11.066357
397 16:44:11.066456 T0: 0000 0040 [010F]
398 16:44:11.066553
399 16:44:11.066644 Jump to BL
400 16:44:11.066739
401 16:44:11.092111
402 16:44:11.092250
403 16:44:11.092355
404 16:44:11.098745 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 16:44:11.102250 ARM64: Exception handlers installed.
406 16:44:11.106733 ARM64: Testing exception
407 16:44:11.109377 ARM64: Done test exception
408 16:44:11.116278 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 16:44:11.126280 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 16:44:11.132996 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 16:44:11.143393 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 16:44:11.150053 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 16:44:11.160304 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 16:44:11.169924 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 16:44:11.176957 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 16:44:11.194797 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 16:44:11.198702 WDT: Last reset was cold boot
418 16:44:11.201393 SPI1(PAD0) initialized at 2873684 Hz
419 16:44:11.205221 SPI5(PAD0) initialized at 992727 Hz
420 16:44:11.208578 VBOOT: Loading verstage.
421 16:44:11.214889 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 16:44:11.219579 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 16:44:11.222874 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 16:44:11.226151 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 16:44:11.232941 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 16:44:11.238887 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 16:44:11.250734 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 16:44:11.250824
429 16:44:11.250893
430 16:44:11.260662 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 16:44:11.263973 ARM64: Exception handlers installed.
432 16:44:11.264061 ARM64: Testing exception
433 16:44:11.267058 ARM64: Done test exception
434 16:44:11.270916 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 16:44:11.277176 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 16:44:11.290651 Probing TPM: . done!
437 16:44:11.290804 TPM ready after 0 ms
438 16:44:11.298283 Connected to device vid:did:rid of 1ae0:0028:00
439 16:44:11.304536 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 16:44:11.365279 Initialized TPM device CR50 revision 0
441 16:44:11.377072 tlcl_send_startup: Startup return code is 0
442 16:44:11.377201 TPM: setup succeeded
443 16:44:11.388305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 16:44:11.397428 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 16:44:11.410012 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 16:44:11.419500 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 16:44:11.422949 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 16:44:11.426229 in-header: 03 07 00 00 08 00 00 00
449 16:44:11.430142 in-data: aa e4 47 04 13 02 00 00
450 16:44:11.433434 Chrome EC: UHEPI supported
451 16:44:11.437639 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 16:44:11.442950 in-header: 03 95 00 00 08 00 00 00
453 16:44:11.446298 in-data: 18 20 20 08 00 00 00 00
454 16:44:11.446382 Phase 1
455 16:44:11.450397 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 16:44:11.457432 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 16:44:11.464900 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 16:44:11.464995 Recovery requested (1009000e)
459 16:44:11.476794 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 16:44:11.480682 tlcl_extend: response is 0
461 16:44:11.489688 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 16:44:11.495445 tlcl_extend: response is 0
463 16:44:11.501945 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 16:44:11.521952 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 16:44:11.528843 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 16:44:11.528933
467 16:44:11.529000
468 16:44:11.539003 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 16:44:11.542279 ARM64: Exception handlers installed.
470 16:44:11.545705 ARM64: Testing exception
471 16:44:11.545789 ARM64: Done test exception
472 16:44:11.567810 pmic_efuse_setting: Set efuses in 11 msecs
473 16:44:11.571199 pmwrap_interface_init: Select PMIF_VLD_RDY
474 16:44:11.577632 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 16:44:11.580920 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 16:44:11.588327 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 16:44:11.592056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 16:44:11.595880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 16:44:11.599793 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 16:44:11.607047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 16:44:11.610874 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 16:44:11.614741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 16:44:11.617943 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 16:44:11.625600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 16:44:11.629387 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 16:44:11.633157 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 16:44:11.640718 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 16:44:11.644255 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 16:44:11.651636 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 16:44:11.655533 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 16:44:11.662982 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 16:44:11.666857 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 16:44:11.674223 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 16:44:11.678088 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 16:44:11.685225 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 16:44:11.692537 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 16:44:11.697227 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 16:44:11.700414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 16:44:11.707511 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 16:44:11.711314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 16:44:11.719084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 16:44:11.722514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 16:44:11.726502 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 16:44:11.730312 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 16:44:11.737378 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 16:44:11.741176 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 16:44:11.748426 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 16:44:11.751823 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 16:44:11.755861 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 16:44:11.764010 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 16:44:11.767281 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 16:44:11.771106 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 16:44:11.775175 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 16:44:11.779174 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 16:44:11.786428 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 16:44:11.789692 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 16:44:11.793544 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 16:44:11.797034 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 16:44:11.800409 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 16:44:11.804608 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 16:44:11.812138 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 16:44:11.815693 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 16:44:11.819717 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 16:44:11.822933 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 16:44:11.830890 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 16:44:11.838645 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 16:44:11.841932 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 16:44:11.852920 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 16:44:11.860386 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 16:44:11.863721 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 16:44:11.867475 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 16:44:11.875320 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 16:44:11.882311 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 16:44:11.885816 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 16:44:11.889813 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 16:44:11.893643 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 16:44:11.905214 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 16:44:11.915136 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 16:44:11.924062 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 16:44:11.933680 [RTC]rtc_get_frequency_meter,154: input=17, output=803
541 16:44:11.943215 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 16:44:11.952902 [RTC]rtc_get_frequency_meter,154: input=16, output=782
543 16:44:11.962922 [RTC]rtc_get_frequency_meter,154: input=17, output=804
544 16:44:11.966116 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 16:44:11.970188 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 16:44:11.974138 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 16:44:11.981380 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 16:44:11.984705 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 16:44:11.988936 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 16:44:11.992640 ADC[4]: Raw value=905834 ID=7
551 16:44:11.992748 ADC[3]: Raw value=213810 ID=1
552 16:44:11.996985 RAM Code: 0x71
553 16:44:12.000220 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 16:44:12.003438 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 16:44:12.015024 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 16:44:12.019284 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 16:44:12.022501 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 16:44:12.026488 in-header: 03 07 00 00 08 00 00 00
559 16:44:12.030395 in-data: aa e4 47 04 13 02 00 00
560 16:44:12.034084 Chrome EC: UHEPI supported
561 16:44:12.037797 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 16:44:12.041627 in-header: 03 95 00 00 08 00 00 00
563 16:44:12.045378 in-data: 18 20 20 08 00 00 00 00
564 16:44:12.049162 MRC: failed to locate region type 0.
565 16:44:12.056227 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 16:44:12.060029 DRAM-K: Running full calibration
567 16:44:12.064189 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 16:44:12.068184 header.status = 0x0
569 16:44:12.072231 header.version = 0x6 (expected: 0x6)
570 16:44:12.072316 header.size = 0xd00 (expected: 0xd00)
571 16:44:12.075522 header.flags = 0x0
572 16:44:12.082969 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 16:44:12.100343 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 16:44:12.108104 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 16:44:12.108223 dram_init: ddr_geometry: 2
576 16:44:12.111404 [EMI] MDL number = 2
577 16:44:12.111495 [EMI] Get MDL freq = 0
578 16:44:12.115512 dram_init: ddr_type: 0
579 16:44:12.115604 is_discrete_lpddr4: 1
580 16:44:12.118956 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 16:44:12.119076
582 16:44:12.119188
583 16:44:12.123002 [Bian_co] ETT version 0.0.0.1
584 16:44:12.126932 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 16:44:12.127026
586 16:44:12.130291 dramc_set_vcore_voltage set vcore to 650000
587 16:44:12.134214 Read voltage for 800, 4
588 16:44:12.134302 Vio18 = 0
589 16:44:12.138112 Vcore = 650000
590 16:44:12.138204 Vdram = 0
591 16:44:12.138294 Vddq = 0
592 16:44:12.138376 Vmddr = 0
593 16:44:12.141765 dram_init: config_dvfs: 1
594 16:44:12.145584 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 16:44:12.153168 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 16:44:12.156917 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 16:44:12.160655 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 16:44:12.164062 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 16:44:12.167703 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 16:44:12.167806 MEM_TYPE=3, freq_sel=18
601 16:44:12.171510 sv_algorithm_assistance_LP4_1600
602 16:44:12.174585 ============ PULL DRAM RESETB DOWN ============
603 16:44:12.181296 ========== PULL DRAM RESETB DOWN end =========
604 16:44:12.184593 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 16:44:12.187771 ===================================
606 16:44:12.192394 LPDDR4 DRAM CONFIGURATION
607 16:44:12.195913 ===================================
608 16:44:12.196027 EX_ROW_EN[0] = 0x0
609 16:44:12.199703 EX_ROW_EN[1] = 0x0
610 16:44:12.199819 LP4Y_EN = 0x0
611 16:44:12.202998 WORK_FSP = 0x0
612 16:44:12.203241 WL = 0x2
613 16:44:12.207078 RL = 0x2
614 16:44:12.207160 BL = 0x2
615 16:44:12.207228 RPST = 0x0
616 16:44:12.210427 RD_PRE = 0x0
617 16:44:12.210595 WR_PRE = 0x1
618 16:44:12.213603 WR_PST = 0x0
619 16:44:12.213713 DBI_WR = 0x0
620 16:44:12.216976 DBI_RD = 0x0
621 16:44:12.217085 OTF = 0x1
622 16:44:12.220391 ===================================
623 16:44:12.223664 ===================================
624 16:44:12.227048 ANA top config
625 16:44:12.230330 ===================================
626 16:44:12.233531 DLL_ASYNC_EN = 0
627 16:44:12.233678 ALL_SLAVE_EN = 1
628 16:44:12.236720 NEW_RANK_MODE = 1
629 16:44:12.240126 DLL_IDLE_MODE = 1
630 16:44:12.243565 LP45_APHY_COMB_EN = 1
631 16:44:12.247426 TX_ODT_DIS = 1
632 16:44:12.247528 NEW_8X_MODE = 1
633 16:44:12.251296 ===================================
634 16:44:12.254403 ===================================
635 16:44:12.257594 data_rate = 1600
636 16:44:12.261079 CKR = 1
637 16:44:12.264230 DQ_P2S_RATIO = 8
638 16:44:12.267930 ===================================
639 16:44:12.268052 CA_P2S_RATIO = 8
640 16:44:12.271094 DQ_CA_OPEN = 0
641 16:44:12.274391 DQ_SEMI_OPEN = 0
642 16:44:12.277627 CA_SEMI_OPEN = 0
643 16:44:12.280801 CA_FULL_RATE = 0
644 16:44:12.284617 DQ_CKDIV4_EN = 1
645 16:44:12.284702 CA_CKDIV4_EN = 1
646 16:44:12.287740 CA_PREDIV_EN = 0
647 16:44:12.291077 PH8_DLY = 0
648 16:44:12.294542 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 16:44:12.297831 DQ_AAMCK_DIV = 4
650 16:44:12.297925 CA_AAMCK_DIV = 4
651 16:44:12.301196 CA_ADMCK_DIV = 4
652 16:44:12.304400 DQ_TRACK_CA_EN = 0
653 16:44:12.307729 CA_PICK = 800
654 16:44:12.311683 CA_MCKIO = 800
655 16:44:12.314455 MCKIO_SEMI = 0
656 16:44:12.318550 PLL_FREQ = 3068
657 16:44:12.318636 DQ_UI_PI_RATIO = 32
658 16:44:12.322006 CA_UI_PI_RATIO = 0
659 16:44:12.325974 ===================================
660 16:44:12.329809 ===================================
661 16:44:12.329917 memory_type:LPDDR4
662 16:44:12.333735 GP_NUM : 10
663 16:44:12.333841 SRAM_EN : 1
664 16:44:12.337722 MD32_EN : 0
665 16:44:12.341133 ===================================
666 16:44:12.341218 [ANA_INIT] >>>>>>>>>>>>>>
667 16:44:12.345203 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 16:44:12.348601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 16:44:12.351767 ===================================
670 16:44:12.355155 data_rate = 1600,PCW = 0X7600
671 16:44:12.358388 ===================================
672 16:44:12.361548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 16:44:12.368531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 16:44:12.371658 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 16:44:12.378763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 16:44:12.382007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 16:44:12.384988 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 16:44:12.385073 [ANA_INIT] flow start
679 16:44:12.388828 [ANA_INIT] PLL >>>>>>>>
680 16:44:12.391918 [ANA_INIT] PLL <<<<<<<<
681 16:44:12.392003 [ANA_INIT] MIDPI >>>>>>>>
682 16:44:12.395090 [ANA_INIT] MIDPI <<<<<<<<
683 16:44:12.398673 [ANA_INIT] DLL >>>>>>>>
684 16:44:12.398758 [ANA_INIT] flow end
685 16:44:12.405531 ============ LP4 DIFF to SE enter ============
686 16:44:12.408743 ============ LP4 DIFF to SE exit ============
687 16:44:12.411834 [ANA_INIT] <<<<<<<<<<<<<
688 16:44:12.415049 [Flow] Enable top DCM control >>>>>
689 16:44:12.415161 [Flow] Enable top DCM control <<<<<
690 16:44:12.418939 Enable DLL master slave shuffle
691 16:44:12.425631 ==============================================================
692 16:44:12.428999 Gating Mode config
693 16:44:12.432383 ==============================================================
694 16:44:12.435615 Config description:
695 16:44:12.445542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 16:44:12.452291 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 16:44:12.455550 SELPH_MODE 0: By rank 1: By Phase
698 16:44:12.462108 ==============================================================
699 16:44:12.465472 GAT_TRACK_EN = 1
700 16:44:12.468740 RX_GATING_MODE = 2
701 16:44:12.468826 RX_GATING_TRACK_MODE = 2
702 16:44:12.471953 SELPH_MODE = 1
703 16:44:12.475603 PICG_EARLY_EN = 1
704 16:44:12.478689 VALID_LAT_VALUE = 1
705 16:44:12.485087 ==============================================================
706 16:44:12.488343 Enter into Gating configuration >>>>
707 16:44:12.492178 Exit from Gating configuration <<<<
708 16:44:12.495494 Enter into DVFS_PRE_config >>>>>
709 16:44:12.505439 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 16:44:12.508778 Exit from DVFS_PRE_config <<<<<
711 16:44:12.512096 Enter into PICG configuration >>>>
712 16:44:12.515408 Exit from PICG configuration <<<<
713 16:44:12.518771 [RX_INPUT] configuration >>>>>
714 16:44:12.522037 [RX_INPUT] configuration <<<<<
715 16:44:12.525413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 16:44:12.532098 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 16:44:12.539184 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 16:44:12.542522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 16:44:12.549384 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 16:44:12.556202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 16:44:12.559475 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 16:44:12.562784 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 16:44:12.569449 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 16:44:12.572657 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 16:44:12.576178 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 16:44:12.582747 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 16:44:12.585870 ===================================
728 16:44:12.585949 LPDDR4 DRAM CONFIGURATION
729 16:44:12.589110 ===================================
730 16:44:12.592265 EX_ROW_EN[0] = 0x0
731 16:44:12.592391 EX_ROW_EN[1] = 0x0
732 16:44:12.596023 LP4Y_EN = 0x0
733 16:44:12.596124 WORK_FSP = 0x0
734 16:44:12.598999 WL = 0x2
735 16:44:12.599078 RL = 0x2
736 16:44:12.602350 BL = 0x2
737 16:44:12.605530 RPST = 0x0
738 16:44:12.605655 RD_PRE = 0x0
739 16:44:12.609275 WR_PRE = 0x1
740 16:44:12.609351 WR_PST = 0x0
741 16:44:12.612395 DBI_WR = 0x0
742 16:44:12.612501 DBI_RD = 0x0
743 16:44:12.615513 OTF = 0x1
744 16:44:12.618786 ===================================
745 16:44:12.622588 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 16:44:12.625853 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 16:44:12.629049 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 16:44:12.632354 ===================================
749 16:44:12.635762 LPDDR4 DRAM CONFIGURATION
750 16:44:12.639083 ===================================
751 16:44:12.642464 EX_ROW_EN[0] = 0x10
752 16:44:12.642566 EX_ROW_EN[1] = 0x0
753 16:44:12.645817 LP4Y_EN = 0x0
754 16:44:12.645892 WORK_FSP = 0x0
755 16:44:12.649019 WL = 0x2
756 16:44:12.649116 RL = 0x2
757 16:44:12.652443 BL = 0x2
758 16:44:12.652572 RPST = 0x0
759 16:44:12.655799 RD_PRE = 0x0
760 16:44:12.656008 WR_PRE = 0x1
761 16:44:12.659104 WR_PST = 0x0
762 16:44:12.659238 DBI_WR = 0x0
763 16:44:12.662382 DBI_RD = 0x0
764 16:44:12.662531 OTF = 0x1
765 16:44:12.665720 ===================================
766 16:44:12.672478 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 16:44:12.677274 nWR fixed to 40
768 16:44:12.680457 [ModeRegInit_LP4] CH0 RK0
769 16:44:12.680536 [ModeRegInit_LP4] CH0 RK1
770 16:44:12.683824 [ModeRegInit_LP4] CH1 RK0
771 16:44:12.687793 [ModeRegInit_LP4] CH1 RK1
772 16:44:12.687872 match AC timing 13
773 16:44:12.694031 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 16:44:12.697544 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 16:44:12.700888 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 16:44:12.707516 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 16:44:12.710858 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 16:44:12.710939 [EMI DOE] emi_dcm 0
779 16:44:12.717264 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 16:44:12.717383 ==
781 16:44:12.720460 Dram Type= 6, Freq= 0, CH_0, rank 0
782 16:44:12.723965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 16:44:12.724048 ==
784 16:44:12.730828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 16:44:12.737582 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 16:44:12.744960 [CA 0] Center 36 (6~67) winsize 62
787 16:44:12.748252 [CA 1] Center 36 (6~67) winsize 62
788 16:44:12.751704 [CA 2] Center 34 (4~65) winsize 62
789 16:44:12.754803 [CA 3] Center 33 (3~64) winsize 62
790 16:44:12.758190 [CA 4] Center 33 (3~64) winsize 62
791 16:44:12.761482 [CA 5] Center 32 (2~62) winsize 61
792 16:44:12.761579
793 16:44:12.764807 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 16:44:12.764892
795 16:44:12.768132 [CATrainingPosCal] consider 1 rank data
796 16:44:12.772141 u2DelayCellTimex100 = 270/100 ps
797 16:44:12.775439 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 16:44:12.778787 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 16:44:12.782174 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 16:44:12.788258 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 16:44:12.791644 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 16:44:12.795411 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 16:44:12.795495
804 16:44:12.798704 CA PerBit enable=1, Macro0, CA PI delay=32
805 16:44:12.798788
806 16:44:12.802371 [CBTSetCACLKResult] CA Dly = 32
807 16:44:12.802470 CS Dly: 5 (0~36)
808 16:44:12.802536 ==
809 16:44:12.805329 Dram Type= 6, Freq= 0, CH_0, rank 1
810 16:44:12.812220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 16:44:12.812319 ==
812 16:44:12.815137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 16:44:12.821989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 16:44:12.830755 [CA 0] Center 36 (6~67) winsize 62
815 16:44:12.834527 [CA 1] Center 36 (6~67) winsize 62
816 16:44:12.837848 [CA 2] Center 34 (3~65) winsize 63
817 16:44:12.841027 [CA 3] Center 33 (3~64) winsize 62
818 16:44:12.844437 [CA 4] Center 33 (3~63) winsize 61
819 16:44:12.847718 [CA 5] Center 32 (2~63) winsize 62
820 16:44:12.847793
821 16:44:12.851128 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 16:44:12.851211
823 16:44:12.854332 [CATrainingPosCal] consider 2 rank data
824 16:44:12.857743 u2DelayCellTimex100 = 270/100 ps
825 16:44:12.861083 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 16:44:12.864493 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 16:44:12.871080 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 16:44:12.874572 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
829 16:44:12.877868 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 16:44:12.881190 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 16:44:12.881275
832 16:44:12.884635 CA PerBit enable=1, Macro0, CA PI delay=32
833 16:44:12.884720
834 16:44:12.887879 [CBTSetCACLKResult] CA Dly = 32
835 16:44:12.887964 CS Dly: 5 (0~37)
836 16:44:12.888032
837 16:44:12.891299 ----->DramcWriteLeveling(PI) begin...
838 16:44:12.891387 ==
839 16:44:12.895381 Dram Type= 6, Freq= 0, CH_0, rank 0
840 16:44:12.899238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 16:44:12.899325 ==
842 16:44:12.903187 Write leveling (Byte 0): 32 => 32
843 16:44:12.907118 Write leveling (Byte 1): 28 => 28
844 16:44:12.909969 DramcWriteLeveling(PI) end<-----
845 16:44:12.910056
846 16:44:12.910124 ==
847 16:44:12.913241 Dram Type= 6, Freq= 0, CH_0, rank 0
848 16:44:12.917204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 16:44:12.917290 ==
850 16:44:12.920434 [Gating] SW mode calibration
851 16:44:12.927954 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 16:44:12.931158 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 16:44:12.937706 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 16:44:12.940908 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 16:44:12.944178 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 16:44:12.951222 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 16:44:12.954638 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 16:44:12.958073 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 16:44:12.964599 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 16:44:12.968057 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 16:44:12.971416 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 16:44:12.978366 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 16:44:12.981081 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 16:44:12.984357 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 16:44:12.988191 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 16:44:12.995054 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 16:44:12.998309 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 16:44:13.000985 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 16:44:13.008160 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 16:44:13.011237 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 16:44:13.014538 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 16:44:13.021148 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 16:44:13.025050 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 16:44:13.028157 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 16:44:13.034380 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 16:44:13.038102 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 16:44:13.041564 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 16:44:13.047740 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 16:44:13.051557 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
880 16:44:13.054880 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
881 16:44:13.061390 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 16:44:13.064639 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 16:44:13.068158 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 16:44:13.071364 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 16:44:13.078163 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 16:44:13.081464 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
887 16:44:13.084799 0 10 8 | B1->B0 | 3232 2626 | 0 0 | (0 1) (0 0)
888 16:44:13.091540 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 16:44:13.094947 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 16:44:13.098350 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 16:44:13.104977 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 16:44:13.108518 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 16:44:13.111762 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 16:44:13.117942 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
895 16:44:13.121825 0 11 8 | B1->B0 | 2e2e 3e3e | 0 1 | (0 0) (0 0)
896 16:44:13.125011 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 16:44:13.131321 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 16:44:13.135241 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 16:44:13.138448 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 16:44:13.141376 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 16:44:13.148281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 16:44:13.151473 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 16:44:13.154661 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 16:44:13.161885 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 16:44:13.165047 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 16:44:13.168309 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 16:44:13.174978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 16:44:13.178189 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 16:44:13.181623 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 16:44:13.188897 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 16:44:13.192188 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 16:44:13.195505 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 16:44:13.202158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 16:44:13.205476 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 16:44:13.208822 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 16:44:13.212145 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 16:44:13.218953 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 16:44:13.222042 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 16:44:13.225275 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 16:44:13.228494 Total UI for P1: 0, mck2ui 16
921 16:44:13.232223 best dqsien dly found for B0: ( 0, 14, 6)
922 16:44:13.238645 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 16:44:13.241797 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 16:44:13.245738 Total UI for P1: 0, mck2ui 16
925 16:44:13.249498 best dqsien dly found for B1: ( 0, 14, 10)
926 16:44:13.252752 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 16:44:13.256362 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 16:44:13.256443
929 16:44:13.259548 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 16:44:13.262756 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 16:44:13.266188 [Gating] SW calibration Done
932 16:44:13.266282 ==
933 16:44:13.269551 Dram Type= 6, Freq= 0, CH_0, rank 0
934 16:44:13.273267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 16:44:13.273375 ==
936 16:44:13.276311 RX Vref Scan: 0
937 16:44:13.276389
938 16:44:13.276462 RX Vref 0 -> 0, step: 1
939 16:44:13.276536
940 16:44:13.279668 RX Delay -130 -> 252, step: 16
941 16:44:13.286515 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
942 16:44:13.290044 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
943 16:44:13.293319 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
944 16:44:13.296526 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
945 16:44:13.299780 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
946 16:44:13.303159 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
947 16:44:13.309859 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
948 16:44:13.313218 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
949 16:44:13.316627 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
950 16:44:13.319966 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
951 16:44:13.323362 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
952 16:44:13.329964 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
953 16:44:13.333193 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
954 16:44:13.336342 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
955 16:44:13.339987 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
956 16:44:13.343116 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
957 16:44:13.346622 ==
958 16:44:13.349764 Dram Type= 6, Freq= 0, CH_0, rank 0
959 16:44:13.352940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 16:44:13.353048 ==
961 16:44:13.353149 DQS Delay:
962 16:44:13.356399 DQS0 = 0, DQS1 = 0
963 16:44:13.356495 DQM Delay:
964 16:44:13.359584 DQM0 = 89, DQM1 = 84
965 16:44:13.359669 DQ Delay:
966 16:44:13.363166 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 16:44:13.366432 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
968 16:44:13.369795 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
969 16:44:13.372857 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
970 16:44:13.372951
971 16:44:13.373028
972 16:44:13.373092 ==
973 16:44:13.376595 Dram Type= 6, Freq= 0, CH_0, rank 0
974 16:44:13.379640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 16:44:13.379732 ==
976 16:44:13.379796
977 16:44:13.379855
978 16:44:13.383441 TX Vref Scan disable
979 16:44:13.386565 == TX Byte 0 ==
980 16:44:13.389634 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
981 16:44:13.392920 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
982 16:44:13.396177 == TX Byte 1 ==
983 16:44:13.399462 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
984 16:44:13.403406 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
985 16:44:13.403522 ==
986 16:44:13.406667 Dram Type= 6, Freq= 0, CH_0, rank 0
987 16:44:13.410015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 16:44:13.410096 ==
989 16:44:13.424642 TX Vref=22, minBit 8, minWin=27, winSum=443
990 16:44:13.427948 TX Vref=24, minBit 9, minWin=27, winSum=450
991 16:44:13.431360 TX Vref=26, minBit 4, minWin=27, winSum=454
992 16:44:13.434642 TX Vref=28, minBit 9, minWin=27, winSum=457
993 16:44:13.437895 TX Vref=30, minBit 8, minWin=28, winSum=458
994 16:44:13.441101 TX Vref=32, minBit 8, minWin=27, winSum=455
995 16:44:13.448237 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 30
996 16:44:13.448421
997 16:44:13.451427 Final TX Range 1 Vref 30
998 16:44:13.451558
999 16:44:13.451623 ==
1000 16:44:13.455008 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 16:44:13.458146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 16:44:13.458268 ==
1003 16:44:13.458342
1004 16:44:13.458405
1005 16:44:13.461282 TX Vref Scan disable
1006 16:44:13.465200 == TX Byte 0 ==
1007 16:44:13.468236 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 16:44:13.471455 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 16:44:13.475313 == TX Byte 1 ==
1010 16:44:13.478571 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1011 16:44:13.481719 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1012 16:44:13.481807
1013 16:44:13.485092 [DATLAT]
1014 16:44:13.485176 Freq=800, CH0 RK0
1015 16:44:13.485242
1016 16:44:13.488098 DATLAT Default: 0xa
1017 16:44:13.488183 0, 0xFFFF, sum = 0
1018 16:44:13.491723 1, 0xFFFF, sum = 0
1019 16:44:13.491812 2, 0xFFFF, sum = 0
1020 16:44:13.494729 3, 0xFFFF, sum = 0
1021 16:44:13.494814 4, 0xFFFF, sum = 0
1022 16:44:13.497967 5, 0xFFFF, sum = 0
1023 16:44:13.498061 6, 0xFFFF, sum = 0
1024 16:44:13.501845 7, 0xFFFF, sum = 0
1025 16:44:13.501935 8, 0xFFFF, sum = 0
1026 16:44:13.505165 9, 0x0, sum = 1
1027 16:44:13.505250 10, 0x0, sum = 2
1028 16:44:13.508492 11, 0x0, sum = 3
1029 16:44:13.508576 12, 0x0, sum = 4
1030 16:44:13.511877 best_step = 10
1031 16:44:13.511961
1032 16:44:13.512026 ==
1033 16:44:13.515136 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 16:44:13.518390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 16:44:13.518472 ==
1036 16:44:13.521625 RX Vref Scan: 1
1037 16:44:13.521708
1038 16:44:13.521811 Set Vref Range= 32 -> 127
1039 16:44:13.521914
1040 16:44:13.525123 RX Vref 32 -> 127, step: 1
1041 16:44:13.525236
1042 16:44:13.528403 RX Delay -79 -> 252, step: 8
1043 16:44:13.528509
1044 16:44:13.531742 Set Vref, RX VrefLevel [Byte0]: 32
1045 16:44:13.535085 [Byte1]: 32
1046 16:44:13.535193
1047 16:44:13.538465 Set Vref, RX VrefLevel [Byte0]: 33
1048 16:44:13.541686 [Byte1]: 33
1049 16:44:13.541772
1050 16:44:13.545201 Set Vref, RX VrefLevel [Byte0]: 34
1051 16:44:13.548395 [Byte1]: 34
1052 16:44:13.552282
1053 16:44:13.552389 Set Vref, RX VrefLevel [Byte0]: 35
1054 16:44:13.555490 [Byte1]: 35
1055 16:44:13.560503
1056 16:44:13.560588 Set Vref, RX VrefLevel [Byte0]: 36
1057 16:44:13.563624 [Byte1]: 36
1058 16:44:13.567518
1059 16:44:13.567631 Set Vref, RX VrefLevel [Byte0]: 37
1060 16:44:13.571402 [Byte1]: 37
1061 16:44:13.575253
1062 16:44:13.575360 Set Vref, RX VrefLevel [Byte0]: 38
1063 16:44:13.578672 [Byte1]: 38
1064 16:44:13.582949
1065 16:44:13.583054 Set Vref, RX VrefLevel [Byte0]: 39
1066 16:44:13.586061 [Byte1]: 39
1067 16:44:13.590687
1068 16:44:13.590773 Set Vref, RX VrefLevel [Byte0]: 40
1069 16:44:13.593899 [Byte1]: 40
1070 16:44:13.597755
1071 16:44:13.597850 Set Vref, RX VrefLevel [Byte0]: 41
1072 16:44:13.600958 [Byte1]: 41
1073 16:44:13.605286
1074 16:44:13.605389 Set Vref, RX VrefLevel [Byte0]: 42
1075 16:44:13.608488 [Byte1]: 42
1076 16:44:13.612533
1077 16:44:13.612616 Set Vref, RX VrefLevel [Byte0]: 43
1078 16:44:13.615963 [Byte1]: 43
1079 16:44:13.619944
1080 16:44:13.620051 Set Vref, RX VrefLevel [Byte0]: 44
1081 16:44:13.623411 [Byte1]: 44
1082 16:44:13.628098
1083 16:44:13.628210 Set Vref, RX VrefLevel [Byte0]: 45
1084 16:44:13.630836 [Byte1]: 45
1085 16:44:13.635429
1086 16:44:13.635536 Set Vref, RX VrefLevel [Byte0]: 46
1087 16:44:13.638627 [Byte1]: 46
1088 16:44:13.642800
1089 16:44:13.642907 Set Vref, RX VrefLevel [Byte0]: 47
1090 16:44:13.646073 [Byte1]: 47
1091 16:44:13.650768
1092 16:44:13.650848 Set Vref, RX VrefLevel [Byte0]: 48
1093 16:44:13.653782 [Byte1]: 48
1094 16:44:13.657760
1095 16:44:13.657846 Set Vref, RX VrefLevel [Byte0]: 49
1096 16:44:13.661174 [Byte1]: 49
1097 16:44:13.665792
1098 16:44:13.665910 Set Vref, RX VrefLevel [Byte0]: 50
1099 16:44:13.668751 [Byte1]: 50
1100 16:44:13.673123
1101 16:44:13.673233 Set Vref, RX VrefLevel [Byte0]: 51
1102 16:44:13.676159 [Byte1]: 51
1103 16:44:13.680733
1104 16:44:13.680811 Set Vref, RX VrefLevel [Byte0]: 52
1105 16:44:13.684104 [Byte1]: 52
1106 16:44:13.688420
1107 16:44:13.688560 Set Vref, RX VrefLevel [Byte0]: 53
1108 16:44:13.691236 [Byte1]: 53
1109 16:44:13.695719
1110 16:44:13.695868 Set Vref, RX VrefLevel [Byte0]: 54
1111 16:44:13.698962 [Byte1]: 54
1112 16:44:13.703413
1113 16:44:13.703517 Set Vref, RX VrefLevel [Byte0]: 55
1114 16:44:13.706287 [Byte1]: 55
1115 16:44:13.710867
1116 16:44:13.710971 Set Vref, RX VrefLevel [Byte0]: 56
1117 16:44:13.714061 [Byte1]: 56
1118 16:44:13.718426
1119 16:44:13.718584 Set Vref, RX VrefLevel [Byte0]: 57
1120 16:44:13.721785 [Byte1]: 57
1121 16:44:13.725995
1122 16:44:13.726098 Set Vref, RX VrefLevel [Byte0]: 58
1123 16:44:13.729222 [Byte1]: 58
1124 16:44:13.733278
1125 16:44:13.733376 Set Vref, RX VrefLevel [Byte0]: 59
1126 16:44:13.736695 [Byte1]: 59
1127 16:44:13.740785
1128 16:44:13.740861 Set Vref, RX VrefLevel [Byte0]: 60
1129 16:44:13.744185 [Byte1]: 60
1130 16:44:13.748799
1131 16:44:13.748900 Set Vref, RX VrefLevel [Byte0]: 61
1132 16:44:13.752287 [Byte1]: 61
1133 16:44:13.756037
1134 16:44:13.756141 Set Vref, RX VrefLevel [Byte0]: 62
1135 16:44:13.759267 [Byte1]: 62
1136 16:44:13.763345
1137 16:44:13.763428 Set Vref, RX VrefLevel [Byte0]: 63
1138 16:44:13.767221 [Byte1]: 63
1139 16:44:13.771188
1140 16:44:13.771267 Set Vref, RX VrefLevel [Byte0]: 64
1141 16:44:13.774252 [Byte1]: 64
1142 16:44:13.778812
1143 16:44:13.778895 Set Vref, RX VrefLevel [Byte0]: 65
1144 16:44:13.781763 [Byte1]: 65
1145 16:44:13.786585
1146 16:44:13.786670 Set Vref, RX VrefLevel [Byte0]: 66
1147 16:44:13.789798 [Byte1]: 66
1148 16:44:13.793810
1149 16:44:13.793894 Set Vref, RX VrefLevel [Byte0]: 67
1150 16:44:13.797045 [Byte1]: 67
1151 16:44:13.801088
1152 16:44:13.801201 Set Vref, RX VrefLevel [Byte0]: 68
1153 16:44:13.804809 [Byte1]: 68
1154 16:44:13.808729
1155 16:44:13.808846 Set Vref, RX VrefLevel [Byte0]: 69
1156 16:44:13.812024 [Byte1]: 69
1157 16:44:13.816434
1158 16:44:13.816515 Set Vref, RX VrefLevel [Byte0]: 70
1159 16:44:13.819609 [Byte1]: 70
1160 16:44:13.824193
1161 16:44:13.824309 Set Vref, RX VrefLevel [Byte0]: 71
1162 16:44:13.827350 [Byte1]: 71
1163 16:44:13.831413
1164 16:44:13.831490 Set Vref, RX VrefLevel [Byte0]: 72
1165 16:44:13.834852 [Byte1]: 72
1166 16:44:13.838943
1167 16:44:13.839060 Set Vref, RX VrefLevel [Byte0]: 73
1168 16:44:13.842226 [Byte1]: 73
1169 16:44:13.846211
1170 16:44:13.849600 Set Vref, RX VrefLevel [Byte0]: 74
1171 16:44:13.849707 [Byte1]: 74
1172 16:44:13.854190
1173 16:44:13.854313 Set Vref, RX VrefLevel [Byte0]: 75
1174 16:44:13.857404 [Byte1]: 75
1175 16:44:13.861458
1176 16:44:13.861579 Final RX Vref Byte 0 = 56 to rank0
1177 16:44:13.865311 Final RX Vref Byte 1 = 59 to rank0
1178 16:44:13.868720 Final RX Vref Byte 0 = 56 to rank1
1179 16:44:13.871604 Final RX Vref Byte 1 = 59 to rank1==
1180 16:44:13.875470 Dram Type= 6, Freq= 0, CH_0, rank 0
1181 16:44:13.878821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1182 16:44:13.882076 ==
1183 16:44:13.882185 DQS Delay:
1184 16:44:13.882282 DQS0 = 0, DQS1 = 0
1185 16:44:13.885033 DQM Delay:
1186 16:44:13.885142 DQM0 = 92, DQM1 = 85
1187 16:44:13.888724 DQ Delay:
1188 16:44:13.888806 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1189 16:44:13.891801 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1190 16:44:13.895625 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =80
1191 16:44:13.898822 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1192 16:44:13.902176
1193 16:44:13.902265
1194 16:44:13.908744 [DQSOSCAuto] RK0, (LSB)MR18= 0x5046, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
1195 16:44:13.912249 CH0 RK0: MR19=606, MR18=5046
1196 16:44:13.918641 CH0_RK0: MR19=0x606, MR18=0x5046, DQSOSC=389, MR23=63, INC=97, DEC=65
1197 16:44:13.918745
1198 16:44:13.922064 ----->DramcWriteLeveling(PI) begin...
1199 16:44:13.922152 ==
1200 16:44:13.925446 Dram Type= 6, Freq= 0, CH_0, rank 1
1201 16:44:13.928742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 16:44:13.928843 ==
1203 16:44:13.932016 Write leveling (Byte 0): 33 => 33
1204 16:44:13.935347 Write leveling (Byte 1): 29 => 29
1205 16:44:13.938595 DramcWriteLeveling(PI) end<-----
1206 16:44:13.938694
1207 16:44:13.938783 ==
1208 16:44:13.942166 Dram Type= 6, Freq= 0, CH_0, rank 1
1209 16:44:13.945567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1210 16:44:13.945656 ==
1211 16:44:13.948933 [Gating] SW mode calibration
1212 16:44:13.955420 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1213 16:44:13.962158 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1214 16:44:13.965400 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1215 16:44:14.009247 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1216 16:44:14.009372 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1217 16:44:14.009631 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 16:44:14.009700 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 16:44:14.009762 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 16:44:14.009822 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 16:44:14.009891 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 16:44:14.009951 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 16:44:14.010017 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 16:44:14.010092 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 16:44:14.053372 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 16:44:14.053680 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 16:44:14.053758 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 16:44:14.053822 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 16:44:14.053884 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 16:44:14.053954 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 16:44:14.054016 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1232 16:44:14.054659 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1233 16:44:14.054731 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 16:44:14.054967 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 16:44:14.057289 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 16:44:14.061202 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 16:44:14.067875 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 16:44:14.070965 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 16:44:14.074396 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 16:44:14.080563 0 9 8 | B1->B0 | 2e2e 2a2a | 0 0 | (0 0) (0 0)
1241 16:44:14.084101 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 16:44:14.087534 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 16:44:14.094087 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 16:44:14.097794 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 16:44:14.101191 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 16:44:14.104255 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 16:44:14.111054 0 10 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1248 16:44:14.114103 0 10 8 | B1->B0 | 2424 2c2c | 0 0 | (1 0) (1 0)
1249 16:44:14.117371 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 16:44:14.124354 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 16:44:14.127543 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 16:44:14.130794 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 16:44:14.138440 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 16:44:14.142370 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 16:44:14.146389 0 11 4 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
1256 16:44:14.149979 0 11 8 | B1->B0 | 3f3f 3b3b | 0 1 | (0 0) (0 0)
1257 16:44:14.153309 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 16:44:14.160128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 16:44:14.163345 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 16:44:14.166904 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 16:44:14.170717 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 16:44:14.177220 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 16:44:14.180510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 16:44:14.183945 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1265 16:44:14.190498 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 16:44:14.193767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 16:44:14.197140 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 16:44:14.203541 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 16:44:14.207417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 16:44:14.210489 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 16:44:14.217416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 16:44:14.220582 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 16:44:14.224264 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 16:44:14.227322 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 16:44:14.234029 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 16:44:14.237287 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 16:44:14.240963 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 16:44:14.247488 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 16:44:14.250637 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 16:44:14.253829 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1281 16:44:14.260378 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 16:44:14.260489 Total UI for P1: 0, mck2ui 16
1283 16:44:14.267160 best dqsien dly found for B0: ( 0, 14, 8)
1284 16:44:14.267270 Total UI for P1: 0, mck2ui 16
1285 16:44:14.273981 best dqsien dly found for B1: ( 0, 14, 8)
1286 16:44:14.277246 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1287 16:44:14.280569 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1288 16:44:14.280673
1289 16:44:14.284438 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1290 16:44:14.287824 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1291 16:44:14.291210 [Gating] SW calibration Done
1292 16:44:14.291315 ==
1293 16:44:14.294405 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 16:44:14.297669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1295 16:44:14.297770 ==
1296 16:44:14.301025 RX Vref Scan: 0
1297 16:44:14.301127
1298 16:44:14.301217 RX Vref 0 -> 0, step: 1
1299 16:44:14.301307
1300 16:44:14.304282 RX Delay -130 -> 252, step: 16
1301 16:44:14.307372 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1302 16:44:14.310836 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1303 16:44:14.317414 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1304 16:44:14.321231 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1305 16:44:14.324159 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1306 16:44:14.327561 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1307 16:44:14.330780 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1308 16:44:14.337756 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1309 16:44:14.341022 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1310 16:44:14.344390 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1311 16:44:14.347773 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1312 16:44:14.351044 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1313 16:44:14.357711 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1314 16:44:14.361577 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1315 16:44:14.364263 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1316 16:44:14.367553 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1317 16:44:14.367700 ==
1318 16:44:14.371115 Dram Type= 6, Freq= 0, CH_0, rank 1
1319 16:44:14.377628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1320 16:44:14.377721 ==
1321 16:44:14.377790 DQS Delay:
1322 16:44:14.377852 DQS0 = 0, DQS1 = 0
1323 16:44:14.380953 DQM Delay:
1324 16:44:14.381030 DQM0 = 93, DQM1 = 84
1325 16:44:14.384210 DQ Delay:
1326 16:44:14.387544 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1327 16:44:14.390817 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1328 16:44:14.394867 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1329 16:44:14.398251 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1330 16:44:14.398336
1331 16:44:14.398420
1332 16:44:14.398499 ==
1333 16:44:14.400992 Dram Type= 6, Freq= 0, CH_0, rank 1
1334 16:44:14.404376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1335 16:44:14.404462 ==
1336 16:44:14.404548
1337 16:44:14.404627
1338 16:44:14.407623 TX Vref Scan disable
1339 16:44:14.407709 == TX Byte 0 ==
1340 16:44:14.414823 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1341 16:44:14.418175 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1342 16:44:14.418261 == TX Byte 1 ==
1343 16:44:14.424872 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1344 16:44:14.428064 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1345 16:44:14.428150 ==
1346 16:44:14.431123 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 16:44:14.434394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 16:44:14.434479 ==
1349 16:44:14.449095 TX Vref=22, minBit 8, minWin=27, winSum=446
1350 16:44:14.452348 TX Vref=24, minBit 10, minWin=27, winSum=449
1351 16:44:14.455523 TX Vref=26, minBit 1, minWin=28, winSum=455
1352 16:44:14.459058 TX Vref=28, minBit 4, minWin=28, winSum=456
1353 16:44:14.462203 TX Vref=30, minBit 2, minWin=28, winSum=459
1354 16:44:14.465437 TX Vref=32, minBit 2, minWin=28, winSum=454
1355 16:44:14.472210 [TxChooseVref] Worse bit 2, Min win 28, Win sum 459, Final Vref 30
1356 16:44:14.472299
1357 16:44:14.475565 Final TX Range 1 Vref 30
1358 16:44:14.475648
1359 16:44:14.475730 ==
1360 16:44:14.478820 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 16:44:14.482183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 16:44:14.482266 ==
1363 16:44:14.482329
1364 16:44:14.482387
1365 16:44:14.485637 TX Vref Scan disable
1366 16:44:14.488772 == TX Byte 0 ==
1367 16:44:14.492170 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1368 16:44:14.495484 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1369 16:44:14.498907 == TX Byte 1 ==
1370 16:44:14.502119 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1371 16:44:14.506036 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1372 16:44:14.506116
1373 16:44:14.509448 [DATLAT]
1374 16:44:14.509551 Freq=800, CH0 RK1
1375 16:44:14.509615
1376 16:44:14.512683 DATLAT Default: 0xa
1377 16:44:14.512820 0, 0xFFFF, sum = 0
1378 16:44:14.515794 1, 0xFFFF, sum = 0
1379 16:44:14.515875 2, 0xFFFF, sum = 0
1380 16:44:14.519176 3, 0xFFFF, sum = 0
1381 16:44:14.519256 4, 0xFFFF, sum = 0
1382 16:44:14.522538 5, 0xFFFF, sum = 0
1383 16:44:14.522618 6, 0xFFFF, sum = 0
1384 16:44:14.525872 7, 0xFFFF, sum = 0
1385 16:44:14.525952 8, 0xFFFF, sum = 0
1386 16:44:14.529282 9, 0x0, sum = 1
1387 16:44:14.529362 10, 0x0, sum = 2
1388 16:44:14.532566 11, 0x0, sum = 3
1389 16:44:14.532670 12, 0x0, sum = 4
1390 16:44:14.535716 best_step = 10
1391 16:44:14.535808
1392 16:44:14.535870 ==
1393 16:44:14.538811 Dram Type= 6, Freq= 0, CH_0, rank 1
1394 16:44:14.542585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1395 16:44:14.542665 ==
1396 16:44:14.545722 RX Vref Scan: 0
1397 16:44:14.545815
1398 16:44:14.545906 RX Vref 0 -> 0, step: 1
1399 16:44:14.545992
1400 16:44:14.548824 RX Delay -95 -> 252, step: 8
1401 16:44:14.556083 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1402 16:44:14.559419 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1403 16:44:14.562800 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1404 16:44:14.565359 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1405 16:44:14.568692 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1406 16:44:14.575765 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1407 16:44:14.578966 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1408 16:44:14.582712 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1409 16:44:14.586064 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1410 16:44:14.589437 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1411 16:44:14.592735 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1412 16:44:14.599420 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1413 16:44:14.602600 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1414 16:44:14.606000 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1415 16:44:14.609316 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1416 16:44:14.616009 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1417 16:44:14.616089 ==
1418 16:44:14.619225 Dram Type= 6, Freq= 0, CH_0, rank 1
1419 16:44:14.622429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1420 16:44:14.622510 ==
1421 16:44:14.622572 DQS Delay:
1422 16:44:14.625821 DQS0 = 0, DQS1 = 0
1423 16:44:14.625923 DQM Delay:
1424 16:44:14.629198 DQM0 = 94, DQM1 = 84
1425 16:44:14.629276 DQ Delay:
1426 16:44:14.632738 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1427 16:44:14.636177 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1428 16:44:14.639305 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1429 16:44:14.642635 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1430 16:44:14.642722
1431 16:44:14.642784
1432 16:44:14.648999 [DQSOSCAuto] RK1, (LSB)MR18= 0x4716, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1433 16:44:14.652581 CH0 RK1: MR19=606, MR18=4716
1434 16:44:14.659507 CH0_RK1: MR19=0x606, MR18=0x4716, DQSOSC=392, MR23=63, INC=96, DEC=64
1435 16:44:14.662698 [RxdqsGatingPostProcess] freq 800
1436 16:44:14.669158 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1437 16:44:14.669271 Pre-setting of DQS Precalculation
1438 16:44:14.675615 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1439 16:44:14.675719 ==
1440 16:44:14.679338 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 16:44:14.682628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 16:44:14.682731 ==
1443 16:44:14.689147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1444 16:44:14.695587 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1445 16:44:14.704037 [CA 0] Center 36 (6~67) winsize 62
1446 16:44:14.707415 [CA 1] Center 36 (6~67) winsize 62
1447 16:44:14.710715 [CA 2] Center 35 (5~66) winsize 62
1448 16:44:14.714141 [CA 3] Center 34 (4~65) winsize 62
1449 16:44:14.716979 [CA 4] Center 34 (4~65) winsize 62
1450 16:44:14.720901 [CA 5] Center 34 (4~64) winsize 61
1451 16:44:14.720975
1452 16:44:14.724067 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1453 16:44:14.724184
1454 16:44:14.727396 [CATrainingPosCal] consider 1 rank data
1455 16:44:14.730593 u2DelayCellTimex100 = 270/100 ps
1456 16:44:14.733950 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1457 16:44:14.737362 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1458 16:44:14.743973 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1459 16:44:14.747307 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1460 16:44:14.750524 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1461 16:44:14.753778 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1462 16:44:14.753853
1463 16:44:14.757587 CA PerBit enable=1, Macro0, CA PI delay=34
1464 16:44:14.757662
1465 16:44:14.760530 [CBTSetCACLKResult] CA Dly = 34
1466 16:44:14.760632 CS Dly: 5 (0~36)
1467 16:44:14.760723 ==
1468 16:44:14.763703 Dram Type= 6, Freq= 0, CH_1, rank 1
1469 16:44:14.770918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1470 16:44:14.771040 ==
1471 16:44:14.773946 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1472 16:44:14.780415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1473 16:44:14.790243 [CA 0] Center 36 (6~67) winsize 62
1474 16:44:14.793447 [CA 1] Center 36 (6~67) winsize 62
1475 16:44:14.796577 [CA 2] Center 35 (5~66) winsize 62
1476 16:44:14.800692 [CA 3] Center 34 (4~65) winsize 62
1477 16:44:14.803966 [CA 4] Center 35 (5~66) winsize 62
1478 16:44:14.807887 [CA 5] Center 34 (4~65) winsize 62
1479 16:44:14.807993
1480 16:44:14.811261 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1481 16:44:14.811364
1482 16:44:14.815320 [CATrainingPosCal] consider 2 rank data
1483 16:44:14.818639 u2DelayCellTimex100 = 270/100 ps
1484 16:44:14.822647 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1485 16:44:14.826014 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1486 16:44:14.829879 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1487 16:44:14.833737 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1488 16:44:14.837169 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1489 16:44:14.840597 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1490 16:44:14.840700
1491 16:44:14.843952 CA PerBit enable=1, Macro0, CA PI delay=34
1492 16:44:14.844088
1493 16:44:14.847261 [CBTSetCACLKResult] CA Dly = 34
1494 16:44:14.847380 CS Dly: 6 (0~38)
1495 16:44:14.847491
1496 16:44:14.850451 ----->DramcWriteLeveling(PI) begin...
1497 16:44:14.850564 ==
1498 16:44:14.853883 Dram Type= 6, Freq= 0, CH_1, rank 0
1499 16:44:14.861200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1500 16:44:14.861315 ==
1501 16:44:14.863807 Write leveling (Byte 0): 27 => 27
1502 16:44:14.863889 Write leveling (Byte 1): 28 => 28
1503 16:44:14.866928 DramcWriteLeveling(PI) end<-----
1504 16:44:14.867041
1505 16:44:14.870779 ==
1506 16:44:14.870862 Dram Type= 6, Freq= 0, CH_1, rank 0
1507 16:44:14.877205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1508 16:44:14.877289 ==
1509 16:44:14.881099 [Gating] SW mode calibration
1510 16:44:14.887103 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1511 16:44:14.890444 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1512 16:44:14.897640 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1513 16:44:14.900794 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1514 16:44:14.904007 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 16:44:14.907145 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 16:44:14.913949 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 16:44:14.917777 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 16:44:14.920599 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 16:44:14.927331 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 16:44:14.930521 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 16:44:14.934460 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 16:44:14.941188 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 16:44:14.944392 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 16:44:14.947734 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 16:44:14.954353 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 16:44:14.957573 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 16:44:14.961061 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 16:44:14.967756 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1529 16:44:14.970770 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1530 16:44:14.974441 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1531 16:44:14.980720 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 16:44:14.984581 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 16:44:14.987881 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 16:44:14.990956 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 16:44:14.997403 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 16:44:15.001304 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 16:44:15.004509 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1538 16:44:15.010793 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1539 16:44:15.014209 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 16:44:15.017482 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 16:44:15.024211 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 16:44:15.027678 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 16:44:15.031010 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 16:44:15.038107 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1545 16:44:15.041303 0 10 4 | B1->B0 | 3131 2d2d | 0 0 | (0 0) (0 1)
1546 16:44:15.044635 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1547 16:44:15.051447 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 16:44:15.054786 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 16:44:15.058046 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 16:44:15.061394 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 16:44:15.068152 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 16:44:15.071464 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1553 16:44:15.074730 0 11 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (0 0)
1554 16:44:15.081130 0 11 8 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
1555 16:44:15.084989 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 16:44:15.087998 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 16:44:15.094950 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 16:44:15.098353 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 16:44:15.101329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 16:44:15.108504 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 16:44:15.111858 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 16:44:15.115012 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1563 16:44:15.121819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 16:44:15.124627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 16:44:15.127942 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 16:44:15.131815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 16:44:15.138501 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 16:44:15.141817 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 16:44:15.145370 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 16:44:15.151988 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 16:44:15.155476 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 16:44:15.158222 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 16:44:15.165463 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 16:44:15.168769 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 16:44:15.171532 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 16:44:15.178171 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1577 16:44:15.182170 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1578 16:44:15.185274 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 16:44:15.188458 Total UI for P1: 0, mck2ui 16
1580 16:44:15.191682 best dqsien dly found for B0: ( 0, 14, 6)
1581 16:44:15.194900 Total UI for P1: 0, mck2ui 16
1582 16:44:15.198738 best dqsien dly found for B1: ( 0, 14, 2)
1583 16:44:15.202068 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1584 16:44:15.205076 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1585 16:44:15.205200
1586 16:44:15.208440 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1587 16:44:15.211755 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1588 16:44:15.214956 [Gating] SW calibration Done
1589 16:44:15.215039 ==
1590 16:44:15.218381 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 16:44:15.224959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 16:44:15.225044 ==
1593 16:44:15.225127 RX Vref Scan: 0
1594 16:44:15.225205
1595 16:44:15.228224 RX Vref 0 -> 0, step: 1
1596 16:44:15.228323
1597 16:44:15.231467 RX Delay -130 -> 252, step: 16
1598 16:44:15.234956 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1599 16:44:15.238904 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1600 16:44:15.242287 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1601 16:44:15.245499 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1602 16:44:15.252391 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1603 16:44:15.254975 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1604 16:44:15.258316 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1605 16:44:15.261790 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1606 16:44:15.265020 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1607 16:44:15.271801 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1608 16:44:15.275116 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1609 16:44:15.278300 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1610 16:44:15.281685 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1611 16:44:15.285070 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1612 16:44:15.291693 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1613 16:44:15.295453 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1614 16:44:15.295538 ==
1615 16:44:15.298408 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 16:44:15.302178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 16:44:15.302262 ==
1618 16:44:15.305309 DQS Delay:
1619 16:44:15.305392 DQS0 = 0, DQS1 = 0
1620 16:44:15.305459 DQM Delay:
1621 16:44:15.308715 DQM0 = 95, DQM1 = 93
1622 16:44:15.308798 DQ Delay:
1623 16:44:15.311882 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1624 16:44:15.315178 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1625 16:44:15.318396 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1626 16:44:15.321522 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1627 16:44:15.321667
1628 16:44:15.321798
1629 16:44:15.324935 ==
1630 16:44:15.325048 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 16:44:15.332053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 16:44:15.332144 ==
1633 16:44:15.332210
1634 16:44:15.332271
1635 16:44:15.332331 TX Vref Scan disable
1636 16:44:15.335890 == TX Byte 0 ==
1637 16:44:15.339110 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1638 16:44:15.342448 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1639 16:44:15.345800 == TX Byte 1 ==
1640 16:44:15.349014 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1641 16:44:15.352084 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1642 16:44:15.355735 ==
1643 16:44:15.359135 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 16:44:15.362456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 16:44:15.362554 ==
1646 16:44:15.374462 TX Vref=22, minBit 0, minWin=26, winSum=435
1647 16:44:15.377790 TX Vref=24, minBit 3, minWin=26, winSum=440
1648 16:44:15.381771 TX Vref=26, minBit 1, minWin=27, winSum=444
1649 16:44:15.385657 TX Vref=28, minBit 1, minWin=27, winSum=447
1650 16:44:15.389162 TX Vref=30, minBit 3, minWin=26, winSum=446
1651 16:44:15.392388 TX Vref=32, minBit 2, minWin=26, winSum=445
1652 16:44:15.398991 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1653 16:44:15.399101
1654 16:44:15.402099 Final TX Range 1 Vref 28
1655 16:44:15.402202
1656 16:44:15.402298 ==
1657 16:44:15.405166 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 16:44:15.408689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 16:44:15.408791 ==
1660 16:44:15.408886
1661 16:44:15.408974
1662 16:44:15.411866 TX Vref Scan disable
1663 16:44:15.415249 == TX Byte 0 ==
1664 16:44:15.419167 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1665 16:44:15.422433 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1666 16:44:15.425729 == TX Byte 1 ==
1667 16:44:15.429141 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 16:44:15.432404 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 16:44:15.432506
1670 16:44:15.435904 [DATLAT]
1671 16:44:15.436005 Freq=800, CH1 RK0
1672 16:44:15.436099
1673 16:44:15.438918 DATLAT Default: 0xa
1674 16:44:15.439020 0, 0xFFFF, sum = 0
1675 16:44:15.442226 1, 0xFFFF, sum = 0
1676 16:44:15.442328 2, 0xFFFF, sum = 0
1677 16:44:15.445444 3, 0xFFFF, sum = 0
1678 16:44:15.445562 4, 0xFFFF, sum = 0
1679 16:44:15.448878 5, 0xFFFF, sum = 0
1680 16:44:15.448983 6, 0xFFFF, sum = 0
1681 16:44:15.452098 7, 0xFFFF, sum = 0
1682 16:44:15.452201 8, 0xFFFF, sum = 0
1683 16:44:15.455323 9, 0x0, sum = 1
1684 16:44:15.455428 10, 0x0, sum = 2
1685 16:44:15.458603 11, 0x0, sum = 3
1686 16:44:15.458704 12, 0x0, sum = 4
1687 16:44:15.458799 best_step = 10
1688 16:44:15.462458
1689 16:44:15.462559 ==
1690 16:44:15.465198 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 16:44:15.468600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 16:44:15.468702 ==
1693 16:44:15.468800 RX Vref Scan: 1
1694 16:44:15.468892
1695 16:44:15.472148 Set Vref Range= 32 -> 127
1696 16:44:15.472252
1697 16:44:15.475358 RX Vref 32 -> 127, step: 1
1698 16:44:15.475459
1699 16:44:15.478596 RX Delay -63 -> 252, step: 8
1700 16:44:15.478697
1701 16:44:15.482026 Set Vref, RX VrefLevel [Byte0]: 32
1702 16:44:15.485470 [Byte1]: 32
1703 16:44:15.485564
1704 16:44:15.488739 Set Vref, RX VrefLevel [Byte0]: 33
1705 16:44:15.491946 [Byte1]: 33
1706 16:44:15.492050
1707 16:44:15.495297 Set Vref, RX VrefLevel [Byte0]: 34
1708 16:44:15.498727 [Byte1]: 34
1709 16:44:15.501900
1710 16:44:15.501999 Set Vref, RX VrefLevel [Byte0]: 35
1711 16:44:15.505547 [Byte1]: 35
1712 16:44:15.509362
1713 16:44:15.509460 Set Vref, RX VrefLevel [Byte0]: 36
1714 16:44:15.513150 [Byte1]: 36
1715 16:44:15.516927
1716 16:44:15.517028 Set Vref, RX VrefLevel [Byte0]: 37
1717 16:44:15.520184 [Byte1]: 37
1718 16:44:15.524477
1719 16:44:15.524578 Set Vref, RX VrefLevel [Byte0]: 38
1720 16:44:15.527867 [Byte1]: 38
1721 16:44:15.531928
1722 16:44:15.532031 Set Vref, RX VrefLevel [Byte0]: 39
1723 16:44:15.535062 [Byte1]: 39
1724 16:44:15.539513
1725 16:44:15.539620 Set Vref, RX VrefLevel [Byte0]: 40
1726 16:44:15.542751 [Byte1]: 40
1727 16:44:15.547461
1728 16:44:15.547543 Set Vref, RX VrefLevel [Byte0]: 41
1729 16:44:15.550718 [Byte1]: 41
1730 16:44:15.554672
1731 16:44:15.554781 Set Vref, RX VrefLevel [Byte0]: 42
1732 16:44:15.558078 [Byte1]: 42
1733 16:44:15.561879
1734 16:44:15.561983 Set Vref, RX VrefLevel [Byte0]: 43
1735 16:44:15.565199 [Byte1]: 43
1736 16:44:15.569892
1737 16:44:15.570001 Set Vref, RX VrefLevel [Byte0]: 44
1738 16:44:15.572591 [Byte1]: 44
1739 16:44:15.577152
1740 16:44:15.577266 Set Vref, RX VrefLevel [Byte0]: 45
1741 16:44:15.580495 [Byte1]: 45
1742 16:44:15.584420
1743 16:44:15.584524 Set Vref, RX VrefLevel [Byte0]: 46
1744 16:44:15.587646 [Byte1]: 46
1745 16:44:15.592389
1746 16:44:15.592503 Set Vref, RX VrefLevel [Byte0]: 47
1747 16:44:15.595628 [Byte1]: 47
1748 16:44:15.599646
1749 16:44:15.599751 Set Vref, RX VrefLevel [Byte0]: 48
1750 16:44:15.602961 [Byte1]: 48
1751 16:44:15.606948
1752 16:44:15.607052 Set Vref, RX VrefLevel [Byte0]: 49
1753 16:44:15.610039 [Byte1]: 49
1754 16:44:15.614665
1755 16:44:15.614749 Set Vref, RX VrefLevel [Byte0]: 50
1756 16:44:15.617762 [Byte1]: 50
1757 16:44:15.622256
1758 16:44:15.622339 Set Vref, RX VrefLevel [Byte0]: 51
1759 16:44:15.625524 [Byte1]: 51
1760 16:44:15.629482
1761 16:44:15.629573 Set Vref, RX VrefLevel [Byte0]: 52
1762 16:44:15.633338 [Byte1]: 52
1763 16:44:15.637353
1764 16:44:15.637440 Set Vref, RX VrefLevel [Byte0]: 53
1765 16:44:15.640622 [Byte1]: 53
1766 16:44:15.644329
1767 16:44:15.644406 Set Vref, RX VrefLevel [Byte0]: 54
1768 16:44:15.647783 [Byte1]: 54
1769 16:44:15.652496
1770 16:44:15.652571 Set Vref, RX VrefLevel [Byte0]: 55
1771 16:44:15.655217 [Byte1]: 55
1772 16:44:15.659470
1773 16:44:15.659577 Set Vref, RX VrefLevel [Byte0]: 56
1774 16:44:15.662920 [Byte1]: 56
1775 16:44:15.667385
1776 16:44:15.667502 Set Vref, RX VrefLevel [Byte0]: 57
1777 16:44:15.670553 [Byte1]: 57
1778 16:44:15.674622
1779 16:44:15.674701 Set Vref, RX VrefLevel [Byte0]: 58
1780 16:44:15.677844 [Byte1]: 58
1781 16:44:15.681808
1782 16:44:15.681915 Set Vref, RX VrefLevel [Byte0]: 59
1783 16:44:15.685171 [Byte1]: 59
1784 16:44:15.689738
1785 16:44:15.689820 Set Vref, RX VrefLevel [Byte0]: 60
1786 16:44:15.693170 [Byte1]: 60
1787 16:44:15.697137
1788 16:44:15.697210 Set Vref, RX VrefLevel [Byte0]: 61
1789 16:44:15.700315 [Byte1]: 61
1790 16:44:15.704336
1791 16:44:15.704410 Set Vref, RX VrefLevel [Byte0]: 62
1792 16:44:15.707754 [Byte1]: 62
1793 16:44:15.712467
1794 16:44:15.712563 Set Vref, RX VrefLevel [Byte0]: 63
1795 16:44:15.715189 [Byte1]: 63
1796 16:44:15.719785
1797 16:44:15.719861 Set Vref, RX VrefLevel [Byte0]: 64
1798 16:44:15.722915 [Byte1]: 64
1799 16:44:15.727060
1800 16:44:15.727133 Set Vref, RX VrefLevel [Byte0]: 65
1801 16:44:15.730195 [Byte1]: 65
1802 16:44:15.734206
1803 16:44:15.734291 Set Vref, RX VrefLevel [Byte0]: 66
1804 16:44:15.737983 [Byte1]: 66
1805 16:44:15.742139
1806 16:44:15.742215 Set Vref, RX VrefLevel [Byte0]: 67
1807 16:44:15.745315 [Byte1]: 67
1808 16:44:15.749253
1809 16:44:15.749354 Set Vref, RX VrefLevel [Byte0]: 68
1810 16:44:15.753025 [Byte1]: 68
1811 16:44:15.757110
1812 16:44:15.757187 Set Vref, RX VrefLevel [Byte0]: 69
1813 16:44:15.760403 [Byte1]: 69
1814 16:44:15.764217
1815 16:44:15.764289 Set Vref, RX VrefLevel [Byte0]: 70
1816 16:44:15.768136 [Byte1]: 70
1817 16:44:15.771892
1818 16:44:15.771976 Set Vref, RX VrefLevel [Byte0]: 71
1819 16:44:15.775289 [Byte1]: 71
1820 16:44:15.779370
1821 16:44:15.779450 Set Vref, RX VrefLevel [Byte0]: 72
1822 16:44:15.782802 [Byte1]: 72
1823 16:44:15.786724
1824 16:44:15.786800 Set Vref, RX VrefLevel [Byte0]: 73
1825 16:44:15.790052 [Byte1]: 73
1826 16:44:15.794914
1827 16:44:15.795001 Set Vref, RX VrefLevel [Byte0]: 74
1828 16:44:15.798172 [Byte1]: 74
1829 16:44:15.801971
1830 16:44:15.802055 Final RX Vref Byte 0 = 56 to rank0
1831 16:44:15.805120 Final RX Vref Byte 1 = 54 to rank0
1832 16:44:15.808400 Final RX Vref Byte 0 = 56 to rank1
1833 16:44:15.812349 Final RX Vref Byte 1 = 54 to rank1==
1834 16:44:15.815053 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 16:44:15.821742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 16:44:15.821827 ==
1837 16:44:15.821895 DQS Delay:
1838 16:44:15.821957 DQS0 = 0, DQS1 = 0
1839 16:44:15.825167 DQM Delay:
1840 16:44:15.825251 DQM0 = 95, DQM1 = 89
1841 16:44:15.828405 DQ Delay:
1842 16:44:15.832076 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1843 16:44:15.835206 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1844 16:44:15.838572 DQ8 =76, DQ9 =80, DQ10 =92, DQ11 =84
1845 16:44:15.841723 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1846 16:44:15.841809
1847 16:44:15.841896
1848 16:44:15.848474 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1849 16:44:15.851685 CH1 RK0: MR19=606, MR18=2F4B
1850 16:44:15.858713 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1851 16:44:15.858799
1852 16:44:15.862119 ----->DramcWriteLeveling(PI) begin...
1853 16:44:15.862230 ==
1854 16:44:15.865405 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 16:44:15.868614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 16:44:15.868696 ==
1857 16:44:15.871973 Write leveling (Byte 0): 27 => 27
1858 16:44:15.875071 Write leveling (Byte 1): 28 => 28
1859 16:44:15.878997 DramcWriteLeveling(PI) end<-----
1860 16:44:15.879081
1861 16:44:15.879148 ==
1862 16:44:15.882180 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 16:44:15.885570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 16:44:15.885656 ==
1865 16:44:15.889069 [Gating] SW mode calibration
1866 16:44:15.895095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 16:44:15.901915 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 16:44:15.905198 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 16:44:15.909137 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1870 16:44:15.915192 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 16:44:15.918475 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 16:44:15.921805 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 16:44:15.928555 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 16:44:15.931962 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 16:44:15.935716 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 16:44:15.942137 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 16:44:15.945815 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 16:44:15.948865 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 16:44:15.952371 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 16:44:15.958856 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 16:44:15.962104 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 16:44:15.965795 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 16:44:15.972356 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 16:44:15.975621 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1885 16:44:15.978911 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1886 16:44:15.985991 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 16:44:15.989103 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 16:44:15.992496 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 16:44:15.999120 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 16:44:16.002520 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 16:44:16.005706 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 16:44:16.012299 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 16:44:16.015692 0 9 4 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (1 1)
1894 16:44:16.019215 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1895 16:44:16.025739 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 16:44:16.029111 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 16:44:16.032566 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 16:44:16.035751 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 16:44:16.042366 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 16:44:16.045747 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
1901 16:44:16.049283 0 10 4 | B1->B0 | 2c2c 3232 | 1 1 | (1 1) (1 0)
1902 16:44:16.055755 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 16:44:16.058886 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 16:44:16.062531 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 16:44:16.069160 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 16:44:16.072185 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 16:44:16.075946 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 16:44:16.082560 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 16:44:16.086011 0 11 4 | B1->B0 | 3737 2e2e | 0 0 | (0 0) (0 0)
1910 16:44:16.089332 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1911 16:44:16.095871 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 16:44:16.098468 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 16:44:16.102349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 16:44:16.108669 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 16:44:16.112074 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 16:44:16.115455 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1917 16:44:16.122131 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1918 16:44:16.125432 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 16:44:16.128643 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 16:44:16.135418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 16:44:16.138740 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 16:44:16.142062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 16:44:16.148549 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 16:44:16.152284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 16:44:16.155421 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 16:44:16.158556 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 16:44:16.165702 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 16:44:16.168996 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 16:44:16.172202 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 16:44:16.178949 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 16:44:16.182256 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 16:44:16.185320 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 16:44:16.192401 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1934 16:44:16.192512 Total UI for P1: 0, mck2ui 16
1935 16:44:16.199176 best dqsien dly found for B1: ( 0, 14, 2)
1936 16:44:16.202668 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 16:44:16.205382 Total UI for P1: 0, mck2ui 16
1938 16:44:16.209209 best dqsien dly found for B0: ( 0, 14, 4)
1939 16:44:16.212646 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 16:44:16.215419 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1941 16:44:16.215521
1942 16:44:16.218811 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 16:44:16.222568 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1944 16:44:16.225817 [Gating] SW calibration Done
1945 16:44:16.225921 ==
1946 16:44:16.229303 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 16:44:16.232690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 16:44:16.232790 ==
1949 16:44:16.235989 RX Vref Scan: 0
1950 16:44:16.236100
1951 16:44:16.238694 RX Vref 0 -> 0, step: 1
1952 16:44:16.238767
1953 16:44:16.238832 RX Delay -130 -> 252, step: 16
1954 16:44:16.245413 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1955 16:44:16.248732 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1956 16:44:16.252589 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1957 16:44:16.255798 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1958 16:44:16.258951 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1959 16:44:16.265664 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1960 16:44:16.269019 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1961 16:44:16.272384 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1962 16:44:16.275553 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1963 16:44:16.279034 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1964 16:44:16.286095 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1965 16:44:16.289259 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1966 16:44:16.292473 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1967 16:44:16.295521 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1968 16:44:16.299401 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1969 16:44:16.305698 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1970 16:44:16.305794 ==
1971 16:44:16.308978 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 16:44:16.312325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 16:44:16.312432 ==
1974 16:44:16.312536 DQS Delay:
1975 16:44:16.316224 DQS0 = 0, DQS1 = 0
1976 16:44:16.316326 DQM Delay:
1977 16:44:16.319656 DQM0 = 93, DQM1 = 92
1978 16:44:16.319768 DQ Delay:
1979 16:44:16.322984 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1980 16:44:16.326063 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1981 16:44:16.329254 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1982 16:44:16.332399 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1983 16:44:16.332502
1984 16:44:16.332575
1985 16:44:16.332639 ==
1986 16:44:16.335818 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 16:44:16.339268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 16:44:16.339371 ==
1989 16:44:16.339464
1990 16:44:16.342767
1991 16:44:16.342867 TX Vref Scan disable
1992 16:44:16.346198 == TX Byte 0 ==
1993 16:44:16.349648 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 16:44:16.353074 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 16:44:16.355742 == TX Byte 1 ==
1996 16:44:16.359696 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 16:44:16.362848 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 16:44:16.362950 ==
1999 16:44:16.366052 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 16:44:16.372634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 16:44:16.372754 ==
2002 16:44:16.384165 TX Vref=22, minBit 1, minWin=26, winSum=442
2003 16:44:16.387584 TX Vref=24, minBit 1, minWin=27, winSum=446
2004 16:44:16.391029 TX Vref=26, minBit 1, minWin=27, winSum=448
2005 16:44:16.394448 TX Vref=28, minBit 2, minWin=27, winSum=451
2006 16:44:16.397671 TX Vref=30, minBit 2, minWin=27, winSum=453
2007 16:44:16.400900 TX Vref=32, minBit 2, minWin=27, winSum=448
2008 16:44:16.408153 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 30
2009 16:44:16.408285
2010 16:44:16.411221 Final TX Range 1 Vref 30
2011 16:44:16.411329
2012 16:44:16.411425 ==
2013 16:44:16.414541 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 16:44:16.417636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 16:44:16.417738 ==
2016 16:44:16.417805
2017 16:44:16.417867
2018 16:44:16.420927 TX Vref Scan disable
2019 16:44:16.424819 == TX Byte 0 ==
2020 16:44:16.427942 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2021 16:44:16.431229 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2022 16:44:16.434488 == TX Byte 1 ==
2023 16:44:16.437783 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2024 16:44:16.441143 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2025 16:44:16.441243
2026 16:44:16.444692 [DATLAT]
2027 16:44:16.444774 Freq=800, CH1 RK1
2028 16:44:16.444839
2029 16:44:16.448096 DATLAT Default: 0xa
2030 16:44:16.448179 0, 0xFFFF, sum = 0
2031 16:44:16.451381 1, 0xFFFF, sum = 0
2032 16:44:16.451466 2, 0xFFFF, sum = 0
2033 16:44:16.454825 3, 0xFFFF, sum = 0
2034 16:44:16.454910 4, 0xFFFF, sum = 0
2035 16:44:16.458166 5, 0xFFFF, sum = 0
2036 16:44:16.458251 6, 0xFFFF, sum = 0
2037 16:44:16.461686 7, 0xFFFF, sum = 0
2038 16:44:16.461770 8, 0xFFFF, sum = 0
2039 16:44:16.464613 9, 0x0, sum = 1
2040 16:44:16.464697 10, 0x0, sum = 2
2041 16:44:16.467787 11, 0x0, sum = 3
2042 16:44:16.467906 12, 0x0, sum = 4
2043 16:44:16.471494 best_step = 10
2044 16:44:16.471593
2045 16:44:16.471658 ==
2046 16:44:16.474820 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 16:44:16.477786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 16:44:16.477898 ==
2049 16:44:16.481118 RX Vref Scan: 0
2050 16:44:16.481201
2051 16:44:16.481281 RX Vref 0 -> 0, step: 1
2052 16:44:16.481343
2053 16:44:16.484975 RX Delay -63 -> 252, step: 8
2054 16:44:16.488091 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2055 16:44:16.494828 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2056 16:44:16.498375 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2057 16:44:16.501583 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2058 16:44:16.504996 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2059 16:44:16.508264 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2060 16:44:16.511193 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2061 16:44:16.518206 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2062 16:44:16.521326 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2063 16:44:16.525293 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2064 16:44:16.528668 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2065 16:44:16.531213 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2066 16:44:16.538458 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2067 16:44:16.541791 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2068 16:44:16.544852 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2069 16:44:16.548424 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2070 16:44:16.548507 ==
2071 16:44:16.551640 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 16:44:16.558493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 16:44:16.558577 ==
2074 16:44:16.558642 DQS Delay:
2075 16:44:16.558702 DQS0 = 0, DQS1 = 0
2076 16:44:16.561185 DQM Delay:
2077 16:44:16.561286 DQM0 = 97, DQM1 = 90
2078 16:44:16.565140 DQ Delay:
2079 16:44:16.568524 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2080 16:44:16.571616 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2081 16:44:16.574724 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2082 16:44:16.578047 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2083 16:44:16.578158
2084 16:44:16.578223
2085 16:44:16.584927 [DQSOSCAuto] RK1, (LSB)MR18= 0x4b15, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2086 16:44:16.587983 CH1 RK1: MR19=606, MR18=4B15
2087 16:44:16.594734 CH1_RK1: MR19=0x606, MR18=0x4B15, DQSOSC=391, MR23=63, INC=96, DEC=64
2088 16:44:16.598591 [RxdqsGatingPostProcess] freq 800
2089 16:44:16.601705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 16:44:16.605133 Pre-setting of DQS Precalculation
2091 16:44:16.611722 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 16:44:16.618199 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 16:44:16.624981 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 16:44:16.625098
2095 16:44:16.625208
2096 16:44:16.628447 [Calibration Summary] 1600 Mbps
2097 16:44:16.628561 CH 0, Rank 0
2098 16:44:16.631470 SW Impedance : PASS
2099 16:44:16.634834 DUTY Scan : NO K
2100 16:44:16.634947 ZQ Calibration : PASS
2101 16:44:16.638160 Jitter Meter : NO K
2102 16:44:16.641536 CBT Training : PASS
2103 16:44:16.641642 Write leveling : PASS
2104 16:44:16.644822 RX DQS gating : PASS
2105 16:44:16.648183 RX DQ/DQS(RDDQC) : PASS
2106 16:44:16.648279 TX DQ/DQS : PASS
2107 16:44:16.651615 RX DATLAT : PASS
2108 16:44:16.651696 RX DQ/DQS(Engine): PASS
2109 16:44:16.654948 TX OE : NO K
2110 16:44:16.655031 All Pass.
2111 16:44:16.655095
2112 16:44:16.658163 CH 0, Rank 1
2113 16:44:16.658246 SW Impedance : PASS
2114 16:44:16.661500 DUTY Scan : NO K
2115 16:44:16.664968 ZQ Calibration : PASS
2116 16:44:16.665060 Jitter Meter : NO K
2117 16:44:16.668426 CBT Training : PASS
2118 16:44:16.671723 Write leveling : PASS
2119 16:44:16.671813 RX DQS gating : PASS
2120 16:44:16.675262 RX DQ/DQS(RDDQC) : PASS
2121 16:44:16.678412 TX DQ/DQS : PASS
2122 16:44:16.678496 RX DATLAT : PASS
2123 16:44:16.682068 RX DQ/DQS(Engine): PASS
2124 16:44:16.682151 TX OE : NO K
2125 16:44:16.685181 All Pass.
2126 16:44:16.685307
2127 16:44:16.685411 CH 1, Rank 0
2128 16:44:16.688153 SW Impedance : PASS
2129 16:44:16.688267 DUTY Scan : NO K
2130 16:44:16.691707 ZQ Calibration : PASS
2131 16:44:16.694973 Jitter Meter : NO K
2132 16:44:16.695056 CBT Training : PASS
2133 16:44:16.698108 Write leveling : PASS
2134 16:44:16.701805 RX DQS gating : PASS
2135 16:44:16.701886 RX DQ/DQS(RDDQC) : PASS
2136 16:44:16.705101 TX DQ/DQS : PASS
2137 16:44:16.708214 RX DATLAT : PASS
2138 16:44:16.708296 RX DQ/DQS(Engine): PASS
2139 16:44:16.711441 TX OE : NO K
2140 16:44:16.711524 All Pass.
2141 16:44:16.711589
2142 16:44:16.714717 CH 1, Rank 1
2143 16:44:16.714799 SW Impedance : PASS
2144 16:44:16.718160 DUTY Scan : NO K
2145 16:44:16.721385 ZQ Calibration : PASS
2146 16:44:16.721492 Jitter Meter : NO K
2147 16:44:16.725361 CBT Training : PASS
2148 16:44:16.725444 Write leveling : PASS
2149 16:44:16.728514 RX DQS gating : PASS
2150 16:44:16.731566 RX DQ/DQS(RDDQC) : PASS
2151 16:44:16.731649 TX DQ/DQS : PASS
2152 16:44:16.735445 RX DATLAT : PASS
2153 16:44:16.738498 RX DQ/DQS(Engine): PASS
2154 16:44:16.738596 TX OE : NO K
2155 16:44:16.741675 All Pass.
2156 16:44:16.741752
2157 16:44:16.741815 DramC Write-DBI off
2158 16:44:16.745216 PER_BANK_REFRESH: Hybrid Mode
2159 16:44:16.745297 TX_TRACKING: ON
2160 16:44:16.749035 [GetDramInforAfterCalByMRR] Vendor 6.
2161 16:44:16.755608 [GetDramInforAfterCalByMRR] Revision 606.
2162 16:44:16.758245 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 16:44:16.758327 MR0 0x3b3b
2164 16:44:16.758390 MR8 0x5151
2165 16:44:16.762096 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 16:44:16.762178
2167 16:44:16.765386 MR0 0x3b3b
2168 16:44:16.765493 MR8 0x5151
2169 16:44:16.768678 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 16:44:16.768759
2171 16:44:16.778256 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 16:44:16.781703 [FAST_K] Save calibration result to emmc
2173 16:44:16.785071 [FAST_K] Save calibration result to emmc
2174 16:44:16.788732 dram_init: config_dvfs: 1
2175 16:44:16.792018 dramc_set_vcore_voltage set vcore to 662500
2176 16:44:16.795296 Read voltage for 1200, 2
2177 16:44:16.795378 Vio18 = 0
2178 16:44:16.795444 Vcore = 662500
2179 16:44:16.798459 Vdram = 0
2180 16:44:16.798542 Vddq = 0
2181 16:44:16.798606 Vmddr = 0
2182 16:44:16.805414 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 16:44:16.808739 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 16:44:16.811962 MEM_TYPE=3, freq_sel=15
2185 16:44:16.815785 sv_algorithm_assistance_LP4_1600
2186 16:44:16.818857 ============ PULL DRAM RESETB DOWN ============
2187 16:44:16.822278 ========== PULL DRAM RESETB DOWN end =========
2188 16:44:16.828926 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 16:44:16.832181 ===================================
2190 16:44:16.832304 LPDDR4 DRAM CONFIGURATION
2191 16:44:16.835269 ===================================
2192 16:44:16.839163 EX_ROW_EN[0] = 0x0
2193 16:44:16.839247 EX_ROW_EN[1] = 0x0
2194 16:44:16.842174 LP4Y_EN = 0x0
2195 16:44:16.845940 WORK_FSP = 0x0
2196 16:44:16.846048 WL = 0x4
2197 16:44:16.849020 RL = 0x4
2198 16:44:16.849121 BL = 0x2
2199 16:44:16.852416 RPST = 0x0
2200 16:44:16.852522 RD_PRE = 0x0
2201 16:44:16.855427 WR_PRE = 0x1
2202 16:44:16.855543 WR_PST = 0x0
2203 16:44:16.858752 DBI_WR = 0x0
2204 16:44:16.858831 DBI_RD = 0x0
2205 16:44:16.862161 OTF = 0x1
2206 16:44:16.865417 ===================================
2207 16:44:16.868763 ===================================
2208 16:44:16.868870 ANA top config
2209 16:44:16.872152 ===================================
2210 16:44:16.875658 DLL_ASYNC_EN = 0
2211 16:44:16.878839 ALL_SLAVE_EN = 0
2212 16:44:16.878922 NEW_RANK_MODE = 1
2213 16:44:16.882062 DLL_IDLE_MODE = 1
2214 16:44:16.885530 LP45_APHY_COMB_EN = 1
2215 16:44:16.888736 TX_ODT_DIS = 1
2216 16:44:16.888819 NEW_8X_MODE = 1
2217 16:44:16.892053 ===================================
2218 16:44:16.895250 ===================================
2219 16:44:16.899012 data_rate = 2400
2220 16:44:16.902307 CKR = 1
2221 16:44:16.905715 DQ_P2S_RATIO = 8
2222 16:44:16.908736 ===================================
2223 16:44:16.912611 CA_P2S_RATIO = 8
2224 16:44:16.915929 DQ_CA_OPEN = 0
2225 16:44:16.916012 DQ_SEMI_OPEN = 0
2226 16:44:16.919002 CA_SEMI_OPEN = 0
2227 16:44:16.922284 CA_FULL_RATE = 0
2228 16:44:16.925471 DQ_CKDIV4_EN = 0
2229 16:44:16.928811 CA_CKDIV4_EN = 0
2230 16:44:16.932170 CA_PREDIV_EN = 0
2231 16:44:16.932257 PH8_DLY = 17
2232 16:44:16.935400 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 16:44:16.939061 DQ_AAMCK_DIV = 4
2234 16:44:16.942087 CA_AAMCK_DIV = 4
2235 16:44:16.945983 CA_ADMCK_DIV = 4
2236 16:44:16.949031 DQ_TRACK_CA_EN = 0
2237 16:44:16.949113 CA_PICK = 1200
2238 16:44:16.952215 CA_MCKIO = 1200
2239 16:44:16.955950 MCKIO_SEMI = 0
2240 16:44:16.959203 PLL_FREQ = 2366
2241 16:44:16.962312 DQ_UI_PI_RATIO = 32
2242 16:44:16.965463 CA_UI_PI_RATIO = 0
2243 16:44:16.969469 ===================================
2244 16:44:16.972160 ===================================
2245 16:44:16.972244 memory_type:LPDDR4
2246 16:44:16.975570 GP_NUM : 10
2247 16:44:16.979496 SRAM_EN : 1
2248 16:44:16.979580 MD32_EN : 0
2249 16:44:16.982129 ===================================
2250 16:44:16.985552 [ANA_INIT] >>>>>>>>>>>>>>
2251 16:44:16.988981 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 16:44:16.992160 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 16:44:16.996050 ===================================
2254 16:44:16.999214 data_rate = 2400,PCW = 0X5b00
2255 16:44:17.002418 ===================================
2256 16:44:17.005716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 16:44:17.008955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 16:44:17.015737 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 16:44:17.018847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 16:44:17.022064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 16:44:17.025325 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 16:44:17.029096 [ANA_INIT] flow start
2263 16:44:17.032201 [ANA_INIT] PLL >>>>>>>>
2264 16:44:17.032283 [ANA_INIT] PLL <<<<<<<<
2265 16:44:17.035681 [ANA_INIT] MIDPI >>>>>>>>
2266 16:44:17.038926 [ANA_INIT] MIDPI <<<<<<<<
2267 16:44:17.042436 [ANA_INIT] DLL >>>>>>>>
2268 16:44:17.042519 [ANA_INIT] DLL <<<<<<<<
2269 16:44:17.045679 [ANA_INIT] flow end
2270 16:44:17.048863 ============ LP4 DIFF to SE enter ============
2271 16:44:17.052090 ============ LP4 DIFF to SE exit ============
2272 16:44:17.055373 [ANA_INIT] <<<<<<<<<<<<<
2273 16:44:17.058805 [Flow] Enable top DCM control >>>>>
2274 16:44:17.061972 [Flow] Enable top DCM control <<<<<
2275 16:44:17.065703 Enable DLL master slave shuffle
2276 16:44:17.068942 ==============================================================
2277 16:44:17.072168 Gating Mode config
2278 16:44:17.078869 ==============================================================
2279 16:44:17.078963 Config description:
2280 16:44:17.088817 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 16:44:17.095573 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 16:44:17.102608 SELPH_MODE 0: By rank 1: By Phase
2283 16:44:17.105687 ==============================================================
2284 16:44:17.109155 GAT_TRACK_EN = 1
2285 16:44:17.112479 RX_GATING_MODE = 2
2286 16:44:17.115774 RX_GATING_TRACK_MODE = 2
2287 16:44:17.119216 SELPH_MODE = 1
2288 16:44:17.122245 PICG_EARLY_EN = 1
2289 16:44:17.125989 VALID_LAT_VALUE = 1
2290 16:44:17.129343 ==============================================================
2291 16:44:17.132378 Enter into Gating configuration >>>>
2292 16:44:17.135558 Exit from Gating configuration <<<<
2293 16:44:17.138897 Enter into DVFS_PRE_config >>>>>
2294 16:44:17.152296 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 16:44:17.152383 Exit from DVFS_PRE_config <<<<<
2296 16:44:17.156079 Enter into PICG configuration >>>>
2297 16:44:17.158905 Exit from PICG configuration <<<<
2298 16:44:17.162181 [RX_INPUT] configuration >>>>>
2299 16:44:17.165988 [RX_INPUT] configuration <<<<<
2300 16:44:17.172427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 16:44:17.175750 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 16:44:17.182299 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 16:44:17.189397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 16:44:17.196116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 16:44:17.202273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 16:44:17.206055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 16:44:17.209152 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 16:44:17.212351 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 16:44:17.215682 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 16:44:17.222370 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 16:44:17.226187 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 16:44:17.229597 ===================================
2313 16:44:17.232778 LPDDR4 DRAM CONFIGURATION
2314 16:44:17.235961 ===================================
2315 16:44:17.236044 EX_ROW_EN[0] = 0x0
2316 16:44:17.239166 EX_ROW_EN[1] = 0x0
2317 16:44:17.239248 LP4Y_EN = 0x0
2318 16:44:17.242694 WORK_FSP = 0x0
2319 16:44:17.242775 WL = 0x4
2320 16:44:17.246033 RL = 0x4
2321 16:44:17.246115 BL = 0x2
2322 16:44:17.249273 RPST = 0x0
2323 16:44:17.249355 RD_PRE = 0x0
2324 16:44:17.252361 WR_PRE = 0x1
2325 16:44:17.255649 WR_PST = 0x0
2326 16:44:17.255730 DBI_WR = 0x0
2327 16:44:17.259380 DBI_RD = 0x0
2328 16:44:17.259462 OTF = 0x1
2329 16:44:17.262795 ===================================
2330 16:44:17.266148 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 16:44:17.269447 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 16:44:17.275956 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 16:44:17.279134 ===================================
2334 16:44:17.282483 LPDDR4 DRAM CONFIGURATION
2335 16:44:17.285826 ===================================
2336 16:44:17.285910 EX_ROW_EN[0] = 0x10
2337 16:44:17.289147 EX_ROW_EN[1] = 0x0
2338 16:44:17.289230 LP4Y_EN = 0x0
2339 16:44:17.292469 WORK_FSP = 0x0
2340 16:44:17.292580 WL = 0x4
2341 16:44:17.295706 RL = 0x4
2342 16:44:17.295788 BL = 0x2
2343 16:44:17.299160 RPST = 0x0
2344 16:44:17.299242 RD_PRE = 0x0
2345 16:44:17.302627 WR_PRE = 0x1
2346 16:44:17.302709 WR_PST = 0x0
2347 16:44:17.305736 DBI_WR = 0x0
2348 16:44:17.305817 DBI_RD = 0x0
2349 16:44:17.309006 OTF = 0x1
2350 16:44:17.312267 ===================================
2351 16:44:17.319323 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 16:44:17.319407 ==
2353 16:44:17.322673 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 16:44:17.326123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 16:44:17.326205 ==
2356 16:44:17.329345 [Duty_Offset_Calibration]
2357 16:44:17.329427 B0:2 B1:1 CA:1
2358 16:44:17.329491
2359 16:44:17.332469 [DutyScan_Calibration_Flow] k_type=0
2360 16:44:17.343188
2361 16:44:17.343345 ==CLK 0==
2362 16:44:17.346162 Final CLK duty delay cell = 0
2363 16:44:17.349551 [0] MAX Duty = 5187%(X100), DQS PI = 24
2364 16:44:17.353242 [0] MIN Duty = 4875%(X100), DQS PI = 0
2365 16:44:17.353346 [0] AVG Duty = 5031%(X100)
2366 16:44:17.353412
2367 16:44:17.356546 CH0 CLK Duty spec in!! Max-Min= 312%
2368 16:44:17.363406 [DutyScan_Calibration_Flow] ====Done====
2369 16:44:17.363492
2370 16:44:17.366455 [DutyScan_Calibration_Flow] k_type=1
2371 16:44:17.380858
2372 16:44:17.381073 ==DQS 0 ==
2373 16:44:17.383989 Final DQS duty delay cell = -4
2374 16:44:17.387187 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2375 16:44:17.391080 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2376 16:44:17.394272 [-4] AVG Duty = 4937%(X100)
2377 16:44:17.394419
2378 16:44:17.394493 ==DQS 1 ==
2379 16:44:17.397801 Final DQS duty delay cell = -4
2380 16:44:17.401052 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2381 16:44:17.404244 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2382 16:44:17.407580 [-4] AVG Duty = 4906%(X100)
2383 16:44:17.407689
2384 16:44:17.410992 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2385 16:44:17.411105
2386 16:44:17.414230 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2387 16:44:17.417284 [DutyScan_Calibration_Flow] ====Done====
2388 16:44:17.417390
2389 16:44:17.421182 [DutyScan_Calibration_Flow] k_type=3
2390 16:44:17.437802
2391 16:44:17.437888 ==DQM 0 ==
2392 16:44:17.441180 Final DQM duty delay cell = 0
2393 16:44:17.444353 [0] MAX Duty = 5156%(X100), DQS PI = 28
2394 16:44:17.448274 [0] MIN Duty = 4906%(X100), DQS PI = 52
2395 16:44:17.448379 [0] AVG Duty = 5031%(X100)
2396 16:44:17.451478
2397 16:44:17.451548 ==DQM 1 ==
2398 16:44:17.454620 Final DQM duty delay cell = 0
2399 16:44:17.458421 [0] MAX Duty = 5125%(X100), DQS PI = 62
2400 16:44:17.461395 [0] MIN Duty = 5031%(X100), DQS PI = 16
2401 16:44:17.461502 [0] AVG Duty = 5078%(X100)
2402 16:44:17.464652
2403 16:44:17.467840 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2404 16:44:17.467945
2405 16:44:17.471706 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2406 16:44:17.474745 [DutyScan_Calibration_Flow] ====Done====
2407 16:44:17.474827
2408 16:44:17.477736 [DutyScan_Calibration_Flow] k_type=2
2409 16:44:17.494648
2410 16:44:17.494808 ==DQ 0 ==
2411 16:44:17.497673 Final DQ duty delay cell = 0
2412 16:44:17.500995 [0] MAX Duty = 5062%(X100), DQS PI = 32
2413 16:44:17.504372 [0] MIN Duty = 4906%(X100), DQS PI = 0
2414 16:44:17.504482 [0] AVG Duty = 4984%(X100)
2415 16:44:17.504581
2416 16:44:17.507671 ==DQ 1 ==
2417 16:44:17.510989 Final DQ duty delay cell = 0
2418 16:44:17.514345 [0] MAX Duty = 5093%(X100), DQS PI = 10
2419 16:44:17.517783 [0] MIN Duty = 4938%(X100), DQS PI = 36
2420 16:44:17.517869 [0] AVG Duty = 5015%(X100)
2421 16:44:17.517932
2422 16:44:17.520908 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2423 16:44:17.521005
2424 16:44:17.524797 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2425 16:44:17.530975 [DutyScan_Calibration_Flow] ====Done====
2426 16:44:17.531059 ==
2427 16:44:17.534177 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 16:44:17.538091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 16:44:17.538174 ==
2430 16:44:17.541343 [Duty_Offset_Calibration]
2431 16:44:17.541432 B0:1 B1:0 CA:0
2432 16:44:17.541497
2433 16:44:17.544868 [DutyScan_Calibration_Flow] k_type=0
2434 16:44:17.553496
2435 16:44:17.553588 ==CLK 0==
2436 16:44:17.556923 Final CLK duty delay cell = -4
2437 16:44:17.560326 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2438 16:44:17.563411 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2439 16:44:17.567285 [-4] AVG Duty = 4969%(X100)
2440 16:44:17.567398
2441 16:44:17.570284 CH1 CLK Duty spec in!! Max-Min= 124%
2442 16:44:17.573550 [DutyScan_Calibration_Flow] ====Done====
2443 16:44:17.573659
2444 16:44:17.576685 [DutyScan_Calibration_Flow] k_type=1
2445 16:44:17.593378
2446 16:44:17.593469 ==DQS 0 ==
2447 16:44:17.596647 Final DQS duty delay cell = 0
2448 16:44:17.600014 [0] MAX Duty = 5094%(X100), DQS PI = 26
2449 16:44:17.603601 [0] MIN Duty = 4844%(X100), DQS PI = 0
2450 16:44:17.603676 [0] AVG Duty = 4969%(X100)
2451 16:44:17.606940
2452 16:44:17.607017 ==DQS 1 ==
2453 16:44:17.610246 Final DQS duty delay cell = 0
2454 16:44:17.613488 [0] MAX Duty = 5187%(X100), DQS PI = 18
2455 16:44:17.616716 [0] MIN Duty = 4969%(X100), DQS PI = 10
2456 16:44:17.616799 [0] AVG Duty = 5078%(X100)
2457 16:44:17.619926
2458 16:44:17.623279 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2459 16:44:17.623362
2460 16:44:17.627005 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2461 16:44:17.630490 [DutyScan_Calibration_Flow] ====Done====
2462 16:44:17.630572
2463 16:44:17.633598 [DutyScan_Calibration_Flow] k_type=3
2464 16:44:17.650321
2465 16:44:17.650421 ==DQM 0 ==
2466 16:44:17.653537 Final DQM duty delay cell = 0
2467 16:44:17.656961 [0] MAX Duty = 5156%(X100), DQS PI = 6
2468 16:44:17.660082 [0] MIN Duty = 5031%(X100), DQS PI = 0
2469 16:44:17.660165 [0] AVG Duty = 5093%(X100)
2470 16:44:17.660248
2471 16:44:17.663506 ==DQM 1 ==
2472 16:44:17.666943 Final DQM duty delay cell = 0
2473 16:44:17.670215 [0] MAX Duty = 5031%(X100), DQS PI = 16
2474 16:44:17.673400 [0] MIN Duty = 4907%(X100), DQS PI = 36
2475 16:44:17.673530 [0] AVG Duty = 4969%(X100)
2476 16:44:17.673615
2477 16:44:17.679987 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2478 16:44:17.680086
2479 16:44:17.683215 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2480 16:44:17.686872 [DutyScan_Calibration_Flow] ====Done====
2481 16:44:17.686956
2482 16:44:17.690044 [DutyScan_Calibration_Flow] k_type=2
2483 16:44:17.705416
2484 16:44:17.705558 ==DQ 0 ==
2485 16:44:17.709210 Final DQ duty delay cell = -4
2486 16:44:17.712388 [-4] MAX Duty = 5094%(X100), DQS PI = 10
2487 16:44:17.715447 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2488 16:44:17.715534 [-4] AVG Duty = 5016%(X100)
2489 16:44:17.719353
2490 16:44:17.719424 ==DQ 1 ==
2491 16:44:17.722040 Final DQ duty delay cell = 0
2492 16:44:17.725460 [0] MAX Duty = 5125%(X100), DQS PI = 20
2493 16:44:17.728847 [0] MIN Duty = 4969%(X100), DQS PI = 12
2494 16:44:17.728934 [0] AVG Duty = 5047%(X100)
2495 16:44:17.732058
2496 16:44:17.735526 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 16:44:17.735608
2498 16:44:17.739384 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2499 16:44:17.742858 [DutyScan_Calibration_Flow] ====Done====
2500 16:44:17.745635 nWR fixed to 30
2501 16:44:17.745733 [ModeRegInit_LP4] CH0 RK0
2502 16:44:17.749163 [ModeRegInit_LP4] CH0 RK1
2503 16:44:17.752586 [ModeRegInit_LP4] CH1 RK0
2504 16:44:17.752732 [ModeRegInit_LP4] CH1 RK1
2505 16:44:17.755740 match AC timing 7
2506 16:44:17.759101 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 16:44:17.762706 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 16:44:17.769151 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 16:44:17.772564 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 16:44:17.779312 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 16:44:17.779406 ==
2512 16:44:17.782600 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 16:44:17.786379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 16:44:17.786465 ==
2515 16:44:17.792651 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 16:44:17.795911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 16:44:17.806030 [CA 0] Center 39 (8~70) winsize 63
2518 16:44:17.809182 [CA 1] Center 39 (8~70) winsize 63
2519 16:44:17.812433 [CA 2] Center 35 (5~66) winsize 62
2520 16:44:17.815597 [CA 3] Center 34 (4~65) winsize 62
2521 16:44:17.819483 [CA 4] Center 33 (3~64) winsize 62
2522 16:44:17.822718 [CA 5] Center 32 (3~62) winsize 60
2523 16:44:17.822826
2524 16:44:17.825849 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2525 16:44:17.825937
2526 16:44:17.829084 [CATrainingPosCal] consider 1 rank data
2527 16:44:17.832489 u2DelayCellTimex100 = 270/100 ps
2528 16:44:17.836282 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2529 16:44:17.839622 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2530 16:44:17.845768 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2531 16:44:17.849573 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2532 16:44:17.852732 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2533 16:44:17.855942 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2534 16:44:17.856023
2535 16:44:17.859361 CA PerBit enable=1, Macro0, CA PI delay=32
2536 16:44:17.859438
2537 16:44:17.862764 [CBTSetCACLKResult] CA Dly = 32
2538 16:44:17.862843 CS Dly: 6 (0~37)
2539 16:44:17.862922 ==
2540 16:44:17.866123 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 16:44:17.872848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 16:44:17.872935 ==
2543 16:44:17.876191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 16:44:17.882925 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2545 16:44:17.891492 [CA 0] Center 38 (8~69) winsize 62
2546 16:44:17.895139 [CA 1] Center 38 (8~69) winsize 62
2547 16:44:17.898338 [CA 2] Center 35 (5~66) winsize 62
2548 16:44:17.901689 [CA 3] Center 34 (4~65) winsize 62
2549 16:44:17.904914 [CA 4] Center 33 (3~64) winsize 62
2550 16:44:17.908443 [CA 5] Center 32 (3~62) winsize 60
2551 16:44:17.908528
2552 16:44:17.911510 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 16:44:17.911588
2554 16:44:17.914891 [CATrainingPosCal] consider 2 rank data
2555 16:44:17.918113 u2DelayCellTimex100 = 270/100 ps
2556 16:44:17.921456 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2557 16:44:17.925248 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2558 16:44:17.931699 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2559 16:44:17.934869 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2560 16:44:17.938076 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2561 16:44:17.941277 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2562 16:44:17.941363
2563 16:44:17.945262 CA PerBit enable=1, Macro0, CA PI delay=32
2564 16:44:17.945348
2565 16:44:17.948501 [CBTSetCACLKResult] CA Dly = 32
2566 16:44:17.948588 CS Dly: 6 (0~38)
2567 16:44:17.948674
2568 16:44:17.951957 ----->DramcWriteLeveling(PI) begin...
2569 16:44:17.955320 ==
2570 16:44:17.955407 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 16:44:17.961764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 16:44:17.961852 ==
2573 16:44:17.964998 Write leveling (Byte 0): 34 => 34
2574 16:44:17.968431 Write leveling (Byte 1): 27 => 27
2575 16:44:17.971765 DramcWriteLeveling(PI) end<-----
2576 16:44:17.971851
2577 16:44:17.971937 ==
2578 16:44:17.975137 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 16:44:17.977972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 16:44:17.978056 ==
2581 16:44:17.981722 [Gating] SW mode calibration
2582 16:44:17.988454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 16:44:17.991739 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 16:44:17.998564 0 15 0 | B1->B0 | 2423 3333 | 1 0 | (0 0) (0 0)
2585 16:44:18.001688 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2586 16:44:18.004783 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 16:44:18.011598 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 16:44:18.014905 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 16:44:18.018454 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 16:44:18.025549 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2591 16:44:18.028240 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2592 16:44:18.031851 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2593 16:44:18.038467 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 16:44:18.041647 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 16:44:18.045370 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 16:44:18.051954 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 16:44:18.055215 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 16:44:18.058532 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2599 16:44:18.061684 1 0 28 | B1->B0 | 2626 4444 | 0 0 | (0 0) (0 0)
2600 16:44:18.068441 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
2601 16:44:18.071717 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 16:44:18.075071 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 16:44:18.081889 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 16:44:18.085134 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 16:44:18.088512 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 16:44:18.095149 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 16:44:18.098606 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 16:44:18.102124 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 16:44:18.108935 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 16:44:18.112128 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 16:44:18.115084 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 16:44:18.122155 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 16:44:18.125268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 16:44:18.128816 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 16:44:18.134983 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 16:44:18.139032 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 16:44:18.142078 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 16:44:18.145180 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 16:44:18.152043 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 16:44:18.155477 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 16:44:18.158933 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 16:44:18.165449 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 16:44:18.169013 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 16:44:18.172257 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 16:44:18.175688 Total UI for P1: 0, mck2ui 16
2626 16:44:18.178994 best dqsien dly found for B0: ( 1, 3, 28)
2627 16:44:18.185727 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 16:44:18.185818 Total UI for P1: 0, mck2ui 16
2629 16:44:18.189086 best dqsien dly found for B1: ( 1, 4, 0)
2630 16:44:18.195690 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2631 16:44:18.199129 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 16:44:18.199211
2633 16:44:18.202530 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2634 16:44:18.205731 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 16:44:18.209134 [Gating] SW calibration Done
2636 16:44:18.209217 ==
2637 16:44:18.239766 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 16:44:18.239913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 16:44:18.240022 ==
2640 16:44:18.240114 RX Vref Scan: 0
2641 16:44:18.240212
2642 16:44:18.240301 RX Vref 0 -> 0, step: 1
2643 16:44:18.240415
2644 16:44:18.240529 RX Delay -40 -> 252, step: 8
2645 16:44:18.240616 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2646 16:44:18.240702 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2647 16:44:18.240818 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 16:44:18.240934 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2649 16:44:18.242102 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2650 16:44:18.245979 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2651 16:44:18.249097 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 16:44:18.255450 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2653 16:44:18.259180 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2654 16:44:18.262231 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2655 16:44:18.265789 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2656 16:44:18.268912 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2657 16:44:18.275480 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2658 16:44:18.279468 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2659 16:44:18.282074 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2660 16:44:18.286020 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2661 16:44:18.286117 ==
2662 16:44:18.289424 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 16:44:18.292251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 16:44:18.296026 ==
2665 16:44:18.296126 DQS Delay:
2666 16:44:18.296223 DQS0 = 0, DQS1 = 0
2667 16:44:18.299377 DQM Delay:
2668 16:44:18.299476 DQM0 = 121, DQM1 = 113
2669 16:44:18.302583 DQ Delay:
2670 16:44:18.306096 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2671 16:44:18.308993 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2672 16:44:18.312190 DQ8 =99, DQ9 =107, DQ10 =115, DQ11 =107
2673 16:44:18.315738 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2674 16:44:18.315823
2675 16:44:18.315907
2676 16:44:18.315987 ==
2677 16:44:18.319029 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 16:44:18.322268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 16:44:18.322354 ==
2680 16:44:18.322439
2681 16:44:18.325500
2682 16:44:18.325623 TX Vref Scan disable
2683 16:44:18.329040 == TX Byte 0 ==
2684 16:44:18.332694 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2685 16:44:18.335773 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2686 16:44:18.339070 == TX Byte 1 ==
2687 16:44:18.342185 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2688 16:44:18.345819 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2689 16:44:18.345903 ==
2690 16:44:18.349368 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 16:44:18.355623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 16:44:18.355709 ==
2693 16:44:18.366688 TX Vref=22, minBit 4, minWin=24, winSum=413
2694 16:44:18.370383 TX Vref=24, minBit 0, minWin=25, winSum=420
2695 16:44:18.373664 TX Vref=26, minBit 7, minWin=25, winSum=426
2696 16:44:18.376797 TX Vref=28, minBit 0, minWin=26, winSum=426
2697 16:44:18.380240 TX Vref=30, minBit 4, minWin=25, winSum=424
2698 16:44:18.383653 TX Vref=32, minBit 0, minWin=26, winSum=424
2699 16:44:18.390149 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
2700 16:44:18.390233
2701 16:44:18.393556 Final TX Range 1 Vref 28
2702 16:44:18.393665
2703 16:44:18.393773 ==
2704 16:44:18.396743 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 16:44:18.400028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 16:44:18.400131 ==
2707 16:44:18.400223
2708 16:44:18.403508
2709 16:44:18.403604 TX Vref Scan disable
2710 16:44:18.406816 == TX Byte 0 ==
2711 16:44:18.410174 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2712 16:44:18.413478 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2713 16:44:18.416600 == TX Byte 1 ==
2714 16:44:18.420064 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2715 16:44:18.423194 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2716 16:44:18.423267
2717 16:44:18.426504 [DATLAT]
2718 16:44:18.426574 Freq=1200, CH0 RK0
2719 16:44:18.426634
2720 16:44:18.430024 DATLAT Default: 0xd
2721 16:44:18.430139 0, 0xFFFF, sum = 0
2722 16:44:18.433149 1, 0xFFFF, sum = 0
2723 16:44:18.433246 2, 0xFFFF, sum = 0
2724 16:44:18.436495 3, 0xFFFF, sum = 0
2725 16:44:18.436579 4, 0xFFFF, sum = 0
2726 16:44:18.439742 5, 0xFFFF, sum = 0
2727 16:44:18.439827 6, 0xFFFF, sum = 0
2728 16:44:18.442988 7, 0xFFFF, sum = 0
2729 16:44:18.446789 8, 0xFFFF, sum = 0
2730 16:44:18.446873 9, 0xFFFF, sum = 0
2731 16:44:18.449929 10, 0xFFFF, sum = 0
2732 16:44:18.450013 11, 0xFFFF, sum = 0
2733 16:44:18.453006 12, 0x0, sum = 1
2734 16:44:18.453096 13, 0x0, sum = 2
2735 16:44:18.456661 14, 0x0, sum = 3
2736 16:44:18.456745 15, 0x0, sum = 4
2737 16:44:18.456819 best_step = 13
2738 16:44:18.456880
2739 16:44:18.459670 ==
2740 16:44:18.462985 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 16:44:18.466794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 16:44:18.466878 ==
2743 16:44:18.466944 RX Vref Scan: 1
2744 16:44:18.467006
2745 16:44:18.469917 Set Vref Range= 32 -> 127
2746 16:44:18.470000
2747 16:44:18.473062 RX Vref 32 -> 127, step: 1
2748 16:44:18.473145
2749 16:44:18.476373 RX Delay -13 -> 252, step: 4
2750 16:44:18.476458
2751 16:44:18.480171 Set Vref, RX VrefLevel [Byte0]: 32
2752 16:44:18.483224 [Byte1]: 32
2753 16:44:18.483309
2754 16:44:18.486661 Set Vref, RX VrefLevel [Byte0]: 33
2755 16:44:18.490096 [Byte1]: 33
2756 16:44:18.490198
2757 16:44:18.493361 Set Vref, RX VrefLevel [Byte0]: 34
2758 16:44:18.496783 [Byte1]: 34
2759 16:44:18.500690
2760 16:44:18.500792 Set Vref, RX VrefLevel [Byte0]: 35
2761 16:44:18.504009 [Byte1]: 35
2762 16:44:18.508674
2763 16:44:18.508758 Set Vref, RX VrefLevel [Byte0]: 36
2764 16:44:18.512011 [Byte1]: 36
2765 16:44:18.516542
2766 16:44:18.516626 Set Vref, RX VrefLevel [Byte0]: 37
2767 16:44:18.520033 [Byte1]: 37
2768 16:44:18.524169
2769 16:44:18.524256 Set Vref, RX VrefLevel [Byte0]: 38
2770 16:44:18.528066 [Byte1]: 38
2771 16:44:18.532194
2772 16:44:18.532274 Set Vref, RX VrefLevel [Byte0]: 39
2773 16:44:18.535610 [Byte1]: 39
2774 16:44:18.540299
2775 16:44:18.540373 Set Vref, RX VrefLevel [Byte0]: 40
2776 16:44:18.543521 [Byte1]: 40
2777 16:44:18.548157
2778 16:44:18.548232 Set Vref, RX VrefLevel [Byte0]: 41
2779 16:44:18.551554 [Byte1]: 41
2780 16:44:18.555963
2781 16:44:18.556036 Set Vref, RX VrefLevel [Byte0]: 42
2782 16:44:18.559189 [Byte1]: 42
2783 16:44:18.564138
2784 16:44:18.564216 Set Vref, RX VrefLevel [Byte0]: 43
2785 16:44:18.567363 [Byte1]: 43
2786 16:44:18.571929
2787 16:44:18.572010 Set Vref, RX VrefLevel [Byte0]: 44
2788 16:44:18.575307 [Byte1]: 44
2789 16:44:18.579716
2790 16:44:18.579797 Set Vref, RX VrefLevel [Byte0]: 45
2791 16:44:18.583075 [Byte1]: 45
2792 16:44:18.587503
2793 16:44:18.587581 Set Vref, RX VrefLevel [Byte0]: 46
2794 16:44:18.591331 [Byte1]: 46
2795 16:44:18.595165
2796 16:44:18.595249 Set Vref, RX VrefLevel [Byte0]: 47
2797 16:44:18.598489 [Byte1]: 47
2798 16:44:18.603166
2799 16:44:18.603267 Set Vref, RX VrefLevel [Byte0]: 48
2800 16:44:18.606569 [Byte1]: 48
2801 16:44:18.611249
2802 16:44:18.611330 Set Vref, RX VrefLevel [Byte0]: 49
2803 16:44:18.614578 [Byte1]: 49
2804 16:44:18.619273
2805 16:44:18.619379 Set Vref, RX VrefLevel [Byte0]: 50
2806 16:44:18.622510 [Byte1]: 50
2807 16:44:18.627161
2808 16:44:18.627276 Set Vref, RX VrefLevel [Byte0]: 51
2809 16:44:18.630500 [Byte1]: 51
2810 16:44:18.634936
2811 16:44:18.635095 Set Vref, RX VrefLevel [Byte0]: 52
2812 16:44:18.638184 [Byte1]: 52
2813 16:44:18.642882
2814 16:44:18.642988 Set Vref, RX VrefLevel [Byte0]: 53
2815 16:44:18.646393 [Byte1]: 53
2816 16:44:18.650848
2817 16:44:18.650948 Set Vref, RX VrefLevel [Byte0]: 54
2818 16:44:18.654107 [Byte1]: 54
2819 16:44:18.658760
2820 16:44:18.658836 Set Vref, RX VrefLevel [Byte0]: 55
2821 16:44:18.661999 [Byte1]: 55
2822 16:44:18.666285
2823 16:44:18.666360 Set Vref, RX VrefLevel [Byte0]: 56
2824 16:44:18.669917 [Byte1]: 56
2825 16:44:18.674471
2826 16:44:18.674569 Set Vref, RX VrefLevel [Byte0]: 57
2827 16:44:18.677725 [Byte1]: 57
2828 16:44:18.682142
2829 16:44:18.682245 Set Vref, RX VrefLevel [Byte0]: 58
2830 16:44:18.685364 [Byte1]: 58
2831 16:44:18.690537
2832 16:44:18.690642 Set Vref, RX VrefLevel [Byte0]: 59
2833 16:44:18.693628 [Byte1]: 59
2834 16:44:18.697909
2835 16:44:18.697979 Set Vref, RX VrefLevel [Byte0]: 60
2836 16:44:18.701363 [Byte1]: 60
2837 16:44:18.706040
2838 16:44:18.706124 Set Vref, RX VrefLevel [Byte0]: 61
2839 16:44:18.709545 [Byte1]: 61
2840 16:44:18.713433
2841 16:44:18.713522 Set Vref, RX VrefLevel [Byte0]: 62
2842 16:44:18.717496 [Byte1]: 62
2843 16:44:18.721584
2844 16:44:18.721692 Set Vref, RX VrefLevel [Byte0]: 63
2845 16:44:18.724913 [Byte1]: 63
2846 16:44:18.729584
2847 16:44:18.729666 Set Vref, RX VrefLevel [Byte0]: 64
2848 16:44:18.733040 [Byte1]: 64
2849 16:44:18.737548
2850 16:44:18.737652 Set Vref, RX VrefLevel [Byte0]: 65
2851 16:44:18.740799 [Byte1]: 65
2852 16:44:18.745447
2853 16:44:18.745569 Set Vref, RX VrefLevel [Byte0]: 66
2854 16:44:18.748797 [Byte1]: 66
2855 16:44:18.753289
2856 16:44:18.753371 Set Vref, RX VrefLevel [Byte0]: 67
2857 16:44:18.756488 [Byte1]: 67
2858 16:44:18.761151
2859 16:44:18.761234 Set Vref, RX VrefLevel [Byte0]: 68
2860 16:44:18.764531 [Byte1]: 68
2861 16:44:18.769087
2862 16:44:18.769169 Set Vref, RX VrefLevel [Byte0]: 69
2863 16:44:18.772257 [Byte1]: 69
2864 16:44:18.777198
2865 16:44:18.777281 Final RX Vref Byte 0 = 60 to rank0
2866 16:44:18.780278 Final RX Vref Byte 1 = 44 to rank0
2867 16:44:18.783583 Final RX Vref Byte 0 = 60 to rank1
2868 16:44:18.786730 Final RX Vref Byte 1 = 44 to rank1==
2869 16:44:18.789955 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 16:44:18.796705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 16:44:18.796790 ==
2872 16:44:18.796856 DQS Delay:
2873 16:44:18.796917 DQS0 = 0, DQS1 = 0
2874 16:44:18.800505 DQM Delay:
2875 16:44:18.800588 DQM0 = 121, DQM1 = 110
2876 16:44:18.803707 DQ Delay:
2877 16:44:18.807044 DQ0 =118, DQ1 =122, DQ2 =120, DQ3 =120
2878 16:44:18.810592 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
2879 16:44:18.813713 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =102
2880 16:44:18.817105 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2881 16:44:18.817189
2882 16:44:18.817254
2883 16:44:18.823698 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2884 16:44:18.827246 CH0 RK0: MR19=404, MR18=160F
2885 16:44:18.833789 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2886 16:44:18.833872
2887 16:44:18.837154 ----->DramcWriteLeveling(PI) begin...
2888 16:44:18.837238 ==
2889 16:44:18.840399 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 16:44:18.843589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 16:44:18.843676 ==
2892 16:44:18.847017 Write leveling (Byte 0): 34 => 34
2893 16:44:18.850264 Write leveling (Byte 1): 30 => 30
2894 16:44:18.853613 DramcWriteLeveling(PI) end<-----
2895 16:44:18.853696
2896 16:44:18.853762 ==
2897 16:44:18.856856 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 16:44:18.863488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 16:44:18.863572 ==
2900 16:44:18.863637 [Gating] SW mode calibration
2901 16:44:18.873432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 16:44:18.876617 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 16:44:18.880313 0 15 0 | B1->B0 | 3232 2f2e | 0 1 | (0 0) (0 0)
2904 16:44:18.886884 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 16:44:18.890342 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 16:44:18.893490 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 16:44:18.900343 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 16:44:18.903592 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 16:44:18.906628 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 16:44:18.913300 0 15 28 | B1->B0 | 3232 3131 | 0 0 | (0 0) (0 0)
2911 16:44:18.916683 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 16:44:18.920582 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 16:44:18.927028 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 16:44:18.930337 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 16:44:18.933798 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 16:44:18.940496 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 16:44:18.943695 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 16:44:18.946915 1 0 28 | B1->B0 | 3f3f 4040 | 0 0 | (0 0) (0 0)
2919 16:44:18.950351 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 16:44:18.957036 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 16:44:18.960342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 16:44:18.964083 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 16:44:18.970799 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 16:44:18.974153 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 16:44:18.977334 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2926 16:44:18.984363 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2927 16:44:18.987433 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2928 16:44:18.990618 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 16:44:18.997736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 16:44:19.001004 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 16:44:19.004107 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 16:44:19.007204 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 16:44:19.013947 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 16:44:19.017354 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 16:44:19.020549 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 16:44:19.027534 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 16:44:19.030891 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 16:44:19.034107 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 16:44:19.040591 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 16:44:19.043935 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 16:44:19.047831 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 16:44:19.054379 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 16:44:19.057645 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2944 16:44:19.060936 Total UI for P1: 0, mck2ui 16
2945 16:44:19.064115 best dqsien dly found for B1: ( 1, 3, 28)
2946 16:44:19.067938 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 16:44:19.071157 Total UI for P1: 0, mck2ui 16
2948 16:44:19.074306 best dqsien dly found for B0: ( 1, 3, 30)
2949 16:44:19.077686 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2950 16:44:19.081071 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2951 16:44:19.081160
2952 16:44:19.084327 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2953 16:44:19.090842 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2954 16:44:19.090919 [Gating] SW calibration Done
2955 16:44:19.090982 ==
2956 16:44:19.094547 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 16:44:19.101383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 16:44:19.101488 ==
2959 16:44:19.101599 RX Vref Scan: 0
2960 16:44:19.101662
2961 16:44:19.104863 RX Vref 0 -> 0, step: 1
2962 16:44:19.104945
2963 16:44:19.108109 RX Delay -40 -> 252, step: 8
2964 16:44:19.111433 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2965 16:44:19.114690 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2966 16:44:19.117887 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2967 16:44:19.121016 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2968 16:44:19.128016 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2969 16:44:19.130967 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2970 16:44:19.134696 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 16:44:19.138115 iDelay=200, Bit 7, Center 131 (64 ~ 199) 136
2972 16:44:19.141417 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2973 16:44:19.144797 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2974 16:44:19.151358 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2975 16:44:19.154628 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2976 16:44:19.158675 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2977 16:44:19.161239 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2978 16:44:19.168607 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2979 16:44:19.171858 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2980 16:44:19.171942 ==
2981 16:44:19.175057 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 16:44:19.178391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 16:44:19.178475 ==
2984 16:44:19.178541 DQS Delay:
2985 16:44:19.181855 DQS0 = 0, DQS1 = 0
2986 16:44:19.181942 DQM Delay:
2987 16:44:19.185268 DQM0 = 122, DQM1 = 111
2988 16:44:19.185351 DQ Delay:
2989 16:44:19.187809 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2990 16:44:19.191268 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =131
2991 16:44:19.195129 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
2992 16:44:19.198273 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2993 16:44:19.201409
2994 16:44:19.201492
2995 16:44:19.201613 ==
2996 16:44:19.204736 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 16:44:19.208438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 16:44:19.208522 ==
2999 16:44:19.208588
3000 16:44:19.208648
3001 16:44:19.211845 TX Vref Scan disable
3002 16:44:19.211928 == TX Byte 0 ==
3003 16:44:19.218401 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3004 16:44:19.221586 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3005 16:44:19.221669 == TX Byte 1 ==
3006 16:44:19.228411 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3007 16:44:19.231422 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3008 16:44:19.231520 ==
3009 16:44:19.234469 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 16:44:19.237926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 16:44:19.238035 ==
3012 16:44:19.250730 TX Vref=22, minBit 5, minWin=24, winSum=410
3013 16:44:19.254071 TX Vref=24, minBit 1, minWin=25, winSum=415
3014 16:44:19.257405 TX Vref=26, minBit 3, minWin=25, winSum=417
3015 16:44:19.260788 TX Vref=28, minBit 12, minWin=25, winSum=423
3016 16:44:19.264122 TX Vref=30, minBit 1, minWin=26, winSum=424
3017 16:44:19.270510 TX Vref=32, minBit 13, minWin=25, winSum=422
3018 16:44:19.274539 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 30
3019 16:44:19.274648
3020 16:44:19.277188 Final TX Range 1 Vref 30
3021 16:44:19.277298
3022 16:44:19.277393 ==
3023 16:44:19.280996 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 16:44:19.284373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 16:44:19.284482 ==
3026 16:44:19.284576
3027 16:44:19.287791
3028 16:44:19.287874 TX Vref Scan disable
3029 16:44:19.291052 == TX Byte 0 ==
3030 16:44:19.294022 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3031 16:44:19.297744 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3032 16:44:19.300934 == TX Byte 1 ==
3033 16:44:19.303942 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3034 16:44:19.307947 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3035 16:44:19.308050
3036 16:44:19.311088 [DATLAT]
3037 16:44:19.311160 Freq=1200, CH0 RK1
3038 16:44:19.311221
3039 16:44:19.314112 DATLAT Default: 0xd
3040 16:44:19.314200 0, 0xFFFF, sum = 0
3041 16:44:19.317333 1, 0xFFFF, sum = 0
3042 16:44:19.317445 2, 0xFFFF, sum = 0
3043 16:44:19.320612 3, 0xFFFF, sum = 0
3044 16:44:19.320683 4, 0xFFFF, sum = 0
3045 16:44:19.324612 5, 0xFFFF, sum = 0
3046 16:44:19.324689 6, 0xFFFF, sum = 0
3047 16:44:19.327802 7, 0xFFFF, sum = 0
3048 16:44:19.327901 8, 0xFFFF, sum = 0
3049 16:44:19.331001 9, 0xFFFF, sum = 0
3050 16:44:19.334439 10, 0xFFFF, sum = 0
3051 16:44:19.334594 11, 0xFFFF, sum = 0
3052 16:44:19.337753 12, 0x0, sum = 1
3053 16:44:19.337898 13, 0x0, sum = 2
3054 16:44:19.337998 14, 0x0, sum = 3
3055 16:44:19.340960 15, 0x0, sum = 4
3056 16:44:19.341104 best_step = 13
3057 16:44:19.341198
3058 16:44:19.341286 ==
3059 16:44:19.344393 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 16:44:19.350786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 16:44:19.350885 ==
3062 16:44:19.350953 RX Vref Scan: 0
3063 16:44:19.351018
3064 16:44:19.354523 RX Vref 0 -> 0, step: 1
3065 16:44:19.354670
3066 16:44:19.357488 RX Delay -13 -> 252, step: 4
3067 16:44:19.361068 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3068 16:44:19.364253 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3069 16:44:19.370846 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3070 16:44:19.374300 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3071 16:44:19.377462 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3072 16:44:19.380736 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3073 16:44:19.384028 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 16:44:19.390777 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3075 16:44:19.394582 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3076 16:44:19.397980 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3077 16:44:19.400713 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3078 16:44:19.404029 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3079 16:44:19.410844 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3080 16:44:19.414169 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3081 16:44:19.417725 iDelay=195, Bit 14, Center 120 (59 ~ 182) 124
3082 16:44:19.420818 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3083 16:44:19.420897 ==
3084 16:44:19.424795 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 16:44:19.428046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 16:44:19.430754 ==
3087 16:44:19.430840 DQS Delay:
3088 16:44:19.430905 DQS0 = 0, DQS1 = 0
3089 16:44:19.434186 DQM Delay:
3090 16:44:19.434259 DQM0 = 120, DQM1 = 109
3091 16:44:19.437883 DQ Delay:
3092 16:44:19.440698 DQ0 =120, DQ1 =120, DQ2 =116, DQ3 =118
3093 16:44:19.444076 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3094 16:44:19.447894 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3095 16:44:19.451024 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =118
3096 16:44:19.451100
3097 16:44:19.451177
3098 16:44:19.457743 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3099 16:44:19.460940 CH0 RK1: MR19=403, MR18=12F3
3100 16:44:19.467857 CH0_RK1: MR19=0x403, MR18=0x12F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3101 16:44:19.471125 [RxdqsGatingPostProcess] freq 1200
3102 16:44:19.477784 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 16:44:19.481059 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 16:44:19.481165 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 16:44:19.484264 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 16:44:19.487621 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 16:44:19.491127 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 16:44:19.494443 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 16:44:19.497734 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 16:44:19.501029 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 16:44:19.504321 Pre-setting of DQS Precalculation
3112 16:44:19.511152 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 16:44:19.511256 ==
3114 16:44:19.514386 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 16:44:19.517502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 16:44:19.517624 ==
3117 16:44:19.524319 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 16:44:19.527487 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 16:44:19.536926 [CA 0] Center 37 (7~68) winsize 62
3120 16:44:19.540652 [CA 1] Center 37 (7~68) winsize 62
3121 16:44:19.544116 [CA 2] Center 35 (5~65) winsize 61
3122 16:44:19.547260 [CA 3] Center 34 (4~65) winsize 62
3123 16:44:19.550197 [CA 4] Center 34 (5~64) winsize 60
3124 16:44:19.554144 [CA 5] Center 33 (3~63) winsize 61
3125 16:44:19.554213
3126 16:44:19.557227 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 16:44:19.557323
3128 16:44:19.560583 [CATrainingPosCal] consider 1 rank data
3129 16:44:19.563947 u2DelayCellTimex100 = 270/100 ps
3130 16:44:19.567252 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 16:44:19.570637 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 16:44:19.577464 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 16:44:19.580530 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3134 16:44:19.584109 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3135 16:44:19.587518 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 16:44:19.587625
3137 16:44:19.590828 CA PerBit enable=1, Macro0, CA PI delay=33
3138 16:44:19.590928
3139 16:44:19.594093 [CBTSetCACLKResult] CA Dly = 33
3140 16:44:19.594192 CS Dly: 7 (0~38)
3141 16:44:19.594284 ==
3142 16:44:19.597428 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 16:44:19.603558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 16:44:19.603659 ==
3145 16:44:19.606935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 16:44:19.614185 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3147 16:44:19.622693 [CA 0] Center 37 (7~68) winsize 62
3148 16:44:19.626622 [CA 1] Center 37 (7~68) winsize 62
3149 16:44:19.629738 [CA 2] Center 35 (5~65) winsize 61
3150 16:44:19.632646 [CA 3] Center 34 (4~65) winsize 62
3151 16:44:19.636456 [CA 4] Center 35 (5~65) winsize 61
3152 16:44:19.639432 [CA 5] Center 34 (4~64) winsize 61
3153 16:44:19.639537
3154 16:44:19.643095 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3155 16:44:19.643206
3156 16:44:19.646444 [CATrainingPosCal] consider 2 rank data
3157 16:44:19.649615 u2DelayCellTimex100 = 270/100 ps
3158 16:44:19.652736 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 16:44:19.656644 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 16:44:19.659922 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3161 16:44:19.666370 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3162 16:44:19.669691 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3163 16:44:19.672961 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3164 16:44:19.673045
3165 16:44:19.676404 CA PerBit enable=1, Macro0, CA PI delay=33
3166 16:44:19.676503
3167 16:44:19.679556 [CBTSetCACLKResult] CA Dly = 33
3168 16:44:19.679638 CS Dly: 8 (0~41)
3169 16:44:19.679703
3170 16:44:19.682713 ----->DramcWriteLeveling(PI) begin...
3171 16:44:19.682797 ==
3172 16:44:19.686445 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 16:44:19.693109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 16:44:19.693218 ==
3175 16:44:19.696428 Write leveling (Byte 0): 26 => 26
3176 16:44:19.699682 Write leveling (Byte 1): 26 => 26
3177 16:44:19.699772 DramcWriteLeveling(PI) end<-----
3178 16:44:19.699854
3179 16:44:19.703197 ==
3180 16:44:19.706472 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 16:44:19.709934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 16:44:19.710034 ==
3183 16:44:19.713243 [Gating] SW mode calibration
3184 16:44:19.720074 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 16:44:19.723515 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 16:44:19.729783 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3187 16:44:19.733095 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 16:44:19.736352 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 16:44:19.743118 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 16:44:19.746326 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 16:44:19.750002 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 16:44:19.756518 0 15 24 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
3193 16:44:19.760001 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3194 16:44:19.763329 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 16:44:19.770046 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 16:44:19.773210 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 16:44:19.776427 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 16:44:19.779652 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 16:44:19.786602 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 16:44:19.789626 1 0 24 | B1->B0 | 2929 3c3b | 1 1 | (0 0) (0 0)
3201 16:44:19.792965 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 16:44:19.800006 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 16:44:19.803409 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 16:44:19.806558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 16:44:19.813256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 16:44:19.816530 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 16:44:19.819951 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 16:44:19.826771 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3209 16:44:19.829990 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 16:44:19.833256 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 16:44:19.840050 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 16:44:19.843556 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 16:44:19.846582 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 16:44:19.853250 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 16:44:19.856840 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 16:44:19.859963 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 16:44:19.863206 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 16:44:19.870297 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 16:44:19.873766 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 16:44:19.877031 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 16:44:19.883452 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 16:44:19.886714 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 16:44:19.890204 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 16:44:19.896700 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 16:44:19.900587 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3226 16:44:19.903600 Total UI for P1: 0, mck2ui 16
3227 16:44:19.907165 best dqsien dly found for B0: ( 1, 3, 24)
3228 16:44:19.910607 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 16:44:19.913292 Total UI for P1: 0, mck2ui 16
3230 16:44:19.916658 best dqsien dly found for B1: ( 1, 3, 26)
3231 16:44:19.920068 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3232 16:44:19.923574 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 16:44:19.923656
3234 16:44:19.926883 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3235 16:44:19.933768 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 16:44:19.933852 [Gating] SW calibration Done
3237 16:44:19.933917 ==
3238 16:44:19.937021 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 16:44:19.943684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 16:44:19.943767 ==
3241 16:44:19.943832 RX Vref Scan: 0
3242 16:44:19.943893
3243 16:44:19.946967 RX Vref 0 -> 0, step: 1
3244 16:44:19.947049
3245 16:44:19.950194 RX Delay -40 -> 252, step: 8
3246 16:44:19.954144 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3247 16:44:19.956835 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3248 16:44:19.960145 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 16:44:19.963828 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3250 16:44:19.970292 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3251 16:44:19.973819 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3252 16:44:19.977100 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3253 16:44:19.980406 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3254 16:44:19.983677 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3255 16:44:19.990466 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3256 16:44:19.993628 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3257 16:44:19.996980 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3258 16:44:20.000436 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 16:44:20.006954 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3260 16:44:20.010663 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3261 16:44:20.013807 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3262 16:44:20.013892 ==
3263 16:44:20.017237 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 16:44:20.020624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 16:44:20.020763 ==
3266 16:44:20.024028 DQS Delay:
3267 16:44:20.024111 DQS0 = 0, DQS1 = 0
3268 16:44:20.024177 DQM Delay:
3269 16:44:20.027242 DQM0 = 120, DQM1 = 117
3270 16:44:20.027325 DQ Delay:
3271 16:44:20.030603 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3272 16:44:20.033792 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3273 16:44:20.040389 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3274 16:44:20.043698 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =127
3275 16:44:20.043781
3276 16:44:20.043846
3277 16:44:20.043906 ==
3278 16:44:20.047012 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 16:44:20.050213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 16:44:20.050296 ==
3281 16:44:20.050362
3282 16:44:20.050449
3283 16:44:20.054149 TX Vref Scan disable
3284 16:44:20.054231 == TX Byte 0 ==
3285 16:44:20.060274 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3286 16:44:20.063639 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3287 16:44:20.063731 == TX Byte 1 ==
3288 16:44:20.070241 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3289 16:44:20.073997 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3290 16:44:20.074080 ==
3291 16:44:20.077111 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 16:44:20.080266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 16:44:20.080344 ==
3294 16:44:20.092756 TX Vref=22, minBit 9, minWin=25, winSum=413
3295 16:44:20.096580 TX Vref=24, minBit 1, minWin=25, winSum=415
3296 16:44:20.099808 TX Vref=26, minBit 9, minWin=25, winSum=425
3297 16:44:20.102939 TX Vref=28, minBit 1, minWin=26, winSum=427
3298 16:44:20.106169 TX Vref=30, minBit 2, minWin=26, winSum=426
3299 16:44:20.109891 TX Vref=32, minBit 9, minWin=25, winSum=425
3300 16:44:20.116069 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
3301 16:44:20.116148
3302 16:44:20.119573 Final TX Range 1 Vref 28
3303 16:44:20.119709
3304 16:44:20.119831 ==
3305 16:44:20.123510 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 16:44:20.126818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 16:44:20.126928 ==
3308 16:44:20.127026
3309 16:44:20.127188
3310 16:44:20.130087 TX Vref Scan disable
3311 16:44:20.132949 == TX Byte 0 ==
3312 16:44:20.136235 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3313 16:44:20.139775 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3314 16:44:20.143108 == TX Byte 1 ==
3315 16:44:20.146283 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3316 16:44:20.149683 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3317 16:44:20.149766
3318 16:44:20.153222 [DATLAT]
3319 16:44:20.153304 Freq=1200, CH1 RK0
3320 16:44:20.153369
3321 16:44:20.156376 DATLAT Default: 0xd
3322 16:44:20.156469 0, 0xFFFF, sum = 0
3323 16:44:20.159639 1, 0xFFFF, sum = 0
3324 16:44:20.159723 2, 0xFFFF, sum = 0
3325 16:44:20.163056 3, 0xFFFF, sum = 0
3326 16:44:20.163140 4, 0xFFFF, sum = 0
3327 16:44:20.166383 5, 0xFFFF, sum = 0
3328 16:44:20.166466 6, 0xFFFF, sum = 0
3329 16:44:20.169767 7, 0xFFFF, sum = 0
3330 16:44:20.169850 8, 0xFFFF, sum = 0
3331 16:44:20.173151 9, 0xFFFF, sum = 0
3332 16:44:20.173237 10, 0xFFFF, sum = 0
3333 16:44:20.177124 11, 0xFFFF, sum = 0
3334 16:44:20.177223 12, 0x0, sum = 1
3335 16:44:20.180351 13, 0x0, sum = 2
3336 16:44:20.180435 14, 0x0, sum = 3
3337 16:44:20.183293 15, 0x0, sum = 4
3338 16:44:20.183376 best_step = 13
3339 16:44:20.183441
3340 16:44:20.183501 ==
3341 16:44:20.187067 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 16:44:20.193361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 16:44:20.193475 ==
3344 16:44:20.193593 RX Vref Scan: 1
3345 16:44:20.193657
3346 16:44:20.196635 Set Vref Range= 32 -> 127
3347 16:44:20.196716
3348 16:44:20.200037 RX Vref 32 -> 127, step: 1
3349 16:44:20.200119
3350 16:44:20.200188 RX Delay -5 -> 252, step: 4
3351 16:44:20.200249
3352 16:44:20.203352 Set Vref, RX VrefLevel [Byte0]: 32
3353 16:44:20.206470 [Byte1]: 32
3354 16:44:20.211071
3355 16:44:20.211145 Set Vref, RX VrefLevel [Byte0]: 33
3356 16:44:20.214170 [Byte1]: 33
3357 16:44:20.218756
3358 16:44:20.218858 Set Vref, RX VrefLevel [Byte0]: 34
3359 16:44:20.222607 [Byte1]: 34
3360 16:44:20.226403
3361 16:44:20.226480 Set Vref, RX VrefLevel [Byte0]: 35
3362 16:44:20.230443 [Byte1]: 35
3363 16:44:20.234458
3364 16:44:20.234535 Set Vref, RX VrefLevel [Byte0]: 36
3365 16:44:20.237758 [Byte1]: 36
3366 16:44:20.242581
3367 16:44:20.242657 Set Vref, RX VrefLevel [Byte0]: 37
3368 16:44:20.245913 [Byte1]: 37
3369 16:44:20.250354
3370 16:44:20.250433 Set Vref, RX VrefLevel [Byte0]: 38
3371 16:44:20.253756 [Byte1]: 38
3372 16:44:20.258368
3373 16:44:20.258453 Set Vref, RX VrefLevel [Byte0]: 39
3374 16:44:20.261420 [Byte1]: 39
3375 16:44:20.265963
3376 16:44:20.266044 Set Vref, RX VrefLevel [Byte0]: 40
3377 16:44:20.269266 [Byte1]: 40
3378 16:44:20.273994
3379 16:44:20.274073 Set Vref, RX VrefLevel [Byte0]: 41
3380 16:44:20.277178 [Byte1]: 41
3381 16:44:20.281869
3382 16:44:20.281952 Set Vref, RX VrefLevel [Byte0]: 42
3383 16:44:20.285100 [Byte1]: 42
3384 16:44:20.289644
3385 16:44:20.289730 Set Vref, RX VrefLevel [Byte0]: 43
3386 16:44:20.292578 [Byte1]: 43
3387 16:44:20.297807
3388 16:44:20.297908 Set Vref, RX VrefLevel [Byte0]: 44
3389 16:44:20.300470 [Byte1]: 44
3390 16:44:20.305428
3391 16:44:20.305505 Set Vref, RX VrefLevel [Byte0]: 45
3392 16:44:20.308642 [Byte1]: 45
3393 16:44:20.313042
3394 16:44:20.313116 Set Vref, RX VrefLevel [Byte0]: 46
3395 16:44:20.316352 [Byte1]: 46
3396 16:44:20.320805
3397 16:44:20.320879 Set Vref, RX VrefLevel [Byte0]: 47
3398 16:44:20.324042 [Byte1]: 47
3399 16:44:20.329041
3400 16:44:20.329115 Set Vref, RX VrefLevel [Byte0]: 48
3401 16:44:20.332336 [Byte1]: 48
3402 16:44:20.336974
3403 16:44:20.337072 Set Vref, RX VrefLevel [Byte0]: 49
3404 16:44:20.340259 [Byte1]: 49
3405 16:44:20.344268
3406 16:44:20.344340 Set Vref, RX VrefLevel [Byte0]: 50
3407 16:44:20.348120 [Byte1]: 50
3408 16:44:20.352069
3409 16:44:20.352146 Set Vref, RX VrefLevel [Byte0]: 51
3410 16:44:20.355943 [Byte1]: 51
3411 16:44:20.360021
3412 16:44:20.360124 Set Vref, RX VrefLevel [Byte0]: 52
3413 16:44:20.364019 [Byte1]: 52
3414 16:44:20.368012
3415 16:44:20.368091 Set Vref, RX VrefLevel [Byte0]: 53
3416 16:44:20.371195 [Byte1]: 53
3417 16:44:20.375716
3418 16:44:20.375791 Set Vref, RX VrefLevel [Byte0]: 54
3419 16:44:20.378911 [Byte1]: 54
3420 16:44:20.383739
3421 16:44:20.383819 Set Vref, RX VrefLevel [Byte0]: 55
3422 16:44:20.387034 [Byte1]: 55
3423 16:44:20.391698
3424 16:44:20.391775 Set Vref, RX VrefLevel [Byte0]: 56
3425 16:44:20.394908 [Byte1]: 56
3426 16:44:20.399674
3427 16:44:20.399778 Set Vref, RX VrefLevel [Byte0]: 57
3428 16:44:20.402835 [Byte1]: 57
3429 16:44:20.407481
3430 16:44:20.407559 Set Vref, RX VrefLevel [Byte0]: 58
3431 16:44:20.410678 [Byte1]: 58
3432 16:44:20.415147
3433 16:44:20.415229 Set Vref, RX VrefLevel [Byte0]: 59
3434 16:44:20.418514 [Byte1]: 59
3435 16:44:20.423085
3436 16:44:20.423255 Set Vref, RX VrefLevel [Byte0]: 60
3437 16:44:20.426522 [Byte1]: 60
3438 16:44:20.431086
3439 16:44:20.431213 Set Vref, RX VrefLevel [Byte0]: 61
3440 16:44:20.434163 [Byte1]: 61
3441 16:44:20.438510
3442 16:44:20.438615 Set Vref, RX VrefLevel [Byte0]: 62
3443 16:44:20.441874 [Byte1]: 62
3444 16:44:20.446458
3445 16:44:20.446542 Set Vref, RX VrefLevel [Byte0]: 63
3446 16:44:20.449761 [Byte1]: 63
3447 16:44:20.454459
3448 16:44:20.454540 Set Vref, RX VrefLevel [Byte0]: 64
3449 16:44:20.457688 [Byte1]: 64
3450 16:44:20.462079
3451 16:44:20.462199 Set Vref, RX VrefLevel [Byte0]: 65
3452 16:44:20.465382 [Byte1]: 65
3453 16:44:20.469983
3454 16:44:20.470080 Set Vref, RX VrefLevel [Byte0]: 66
3455 16:44:20.473354 [Byte1]: 66
3456 16:44:20.477936
3457 16:44:20.478096 Set Vref, RX VrefLevel [Byte0]: 67
3458 16:44:20.481376 [Byte1]: 67
3459 16:44:20.485993
3460 16:44:20.486076 Set Vref, RX VrefLevel [Byte0]: 68
3461 16:44:20.489272 [Byte1]: 68
3462 16:44:20.493936
3463 16:44:20.494072 Final RX Vref Byte 0 = 55 to rank0
3464 16:44:20.497139 Final RX Vref Byte 1 = 48 to rank0
3465 16:44:20.500322 Final RX Vref Byte 0 = 55 to rank1
3466 16:44:20.503551 Final RX Vref Byte 1 = 48 to rank1==
3467 16:44:20.506984 Dram Type= 6, Freq= 0, CH_1, rank 0
3468 16:44:20.510157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3469 16:44:20.513368 ==
3470 16:44:20.513468 DQS Delay:
3471 16:44:20.513588 DQS0 = 0, DQS1 = 0
3472 16:44:20.516799 DQM Delay:
3473 16:44:20.516882 DQM0 = 120, DQM1 = 116
3474 16:44:20.520674 DQ Delay:
3475 16:44:20.523657 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3476 16:44:20.527415 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3477 16:44:20.530141 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3478 16:44:20.534110 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3479 16:44:20.534195
3480 16:44:20.534261
3481 16:44:20.540350 [DQSOSCAuto] RK0, (LSB)MR18= 0xff11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3482 16:44:20.543509 CH1 RK0: MR19=304, MR18=FF11
3483 16:44:20.550458 CH1_RK0: MR19=0x304, MR18=0xFF11, DQSOSC=403, MR23=63, INC=40, DEC=26
3484 16:44:20.550563
3485 16:44:20.553680 ----->DramcWriteLeveling(PI) begin...
3486 16:44:20.553768 ==
3487 16:44:20.556825 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 16:44:20.560144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 16:44:20.563940 ==
3490 16:44:20.564023 Write leveling (Byte 0): 25 => 25
3491 16:44:20.567216 Write leveling (Byte 1): 28 => 28
3492 16:44:20.570509 DramcWriteLeveling(PI) end<-----
3493 16:44:20.570628
3494 16:44:20.570720 ==
3495 16:44:20.573659 Dram Type= 6, Freq= 0, CH_1, rank 1
3496 16:44:20.580778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3497 16:44:20.580865 ==
3498 16:44:20.580932 [Gating] SW mode calibration
3499 16:44:20.590614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3500 16:44:20.593781 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3501 16:44:20.597168 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 16:44:20.604046 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3503 16:44:20.607247 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3504 16:44:20.610534 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3505 16:44:20.617447 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3506 16:44:20.620669 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 16:44:20.623812 0 15 24 | B1->B0 | 2a2a 3333 | 0 1 | (1 0) (1 1)
3508 16:44:20.630627 0 15 28 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 0)
3509 16:44:20.633982 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 16:44:20.637338 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3511 16:44:20.643748 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3512 16:44:20.647064 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3513 16:44:20.650864 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3514 16:44:20.657214 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 16:44:20.660432 1 0 24 | B1->B0 | 4343 2c2c | 0 0 | (0 0) (0 0)
3516 16:44:20.663804 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 16:44:20.667524 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 16:44:20.673915 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3519 16:44:20.677170 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3520 16:44:20.680212 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3521 16:44:20.687002 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3522 16:44:20.690185 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3523 16:44:20.693952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3524 16:44:20.700710 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3525 16:44:20.703802 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 16:44:20.706904 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 16:44:20.713962 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 16:44:20.717392 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 16:44:20.720594 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 16:44:20.726914 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 16:44:20.730626 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 16:44:20.733616 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 16:44:20.740249 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 16:44:20.743498 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 16:44:20.747487 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 16:44:20.753932 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 16:44:20.756875 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 16:44:20.760589 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3539 16:44:20.766904 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3540 16:44:20.770509 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3541 16:44:20.773797 Total UI for P1: 0, mck2ui 16
3542 16:44:20.776940 best dqsien dly found for B1: ( 1, 3, 22)
3543 16:44:20.780332 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 16:44:20.783923 Total UI for P1: 0, mck2ui 16
3545 16:44:20.787175 best dqsien dly found for B0: ( 1, 3, 28)
3546 16:44:20.790635 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3547 16:44:20.793926 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3548 16:44:20.794000
3549 16:44:20.797151 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3550 16:44:20.800341 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3551 16:44:20.803681 [Gating] SW calibration Done
3552 16:44:20.803756 ==
3553 16:44:20.807049 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 16:44:20.813362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 16:44:20.813445 ==
3556 16:44:20.813530 RX Vref Scan: 0
3557 16:44:20.813595
3558 16:44:20.816704 RX Vref 0 -> 0, step: 1
3559 16:44:20.816775
3560 16:44:20.820030 RX Delay -40 -> 252, step: 8
3561 16:44:20.823279 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3562 16:44:20.826545 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3563 16:44:20.829911 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3564 16:44:20.836736 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3565 16:44:20.840539 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3566 16:44:20.843461 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3567 16:44:20.846973 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3568 16:44:20.850277 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3569 16:44:20.853569 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3570 16:44:20.860062 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3571 16:44:20.863878 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3572 16:44:20.867037 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3573 16:44:20.870397 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3574 16:44:20.876872 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3575 16:44:20.880201 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3576 16:44:20.883672 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3577 16:44:20.883760 ==
3578 16:44:20.886781 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 16:44:20.889908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 16:44:20.889990 ==
3581 16:44:20.893179 DQS Delay:
3582 16:44:20.893254 DQS0 = 0, DQS1 = 0
3583 16:44:20.896426 DQM Delay:
3584 16:44:20.896528 DQM0 = 120, DQM1 = 118
3585 16:44:20.896620 DQ Delay:
3586 16:44:20.900367 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3587 16:44:20.903522 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3588 16:44:20.909895 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3589 16:44:20.913224 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3590 16:44:20.913335
3591 16:44:20.913434
3592 16:44:20.913536 ==
3593 16:44:20.916448 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 16:44:20.920244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 16:44:20.920359 ==
3596 16:44:20.920466
3597 16:44:20.920566
3598 16:44:20.922870 TX Vref Scan disable
3599 16:44:20.926696 == TX Byte 0 ==
3600 16:44:20.929978 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3601 16:44:20.933202 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3602 16:44:20.936379 == TX Byte 1 ==
3603 16:44:20.939525 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3604 16:44:20.943312 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3605 16:44:20.943435 ==
3606 16:44:20.946535 Dram Type= 6, Freq= 0, CH_1, rank 1
3607 16:44:20.949731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3608 16:44:20.952960 ==
3609 16:44:20.963448 TX Vref=22, minBit 9, minWin=25, winSum=419
3610 16:44:20.966326 TX Vref=24, minBit 10, minWin=25, winSum=425
3611 16:44:20.969634 TX Vref=26, minBit 9, minWin=26, winSum=430
3612 16:44:20.972913 TX Vref=28, minBit 2, minWin=26, winSum=432
3613 16:44:20.976150 TX Vref=30, minBit 9, minWin=26, winSum=434
3614 16:44:20.983089 TX Vref=32, minBit 9, minWin=26, winSum=431
3615 16:44:20.986112 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3616 16:44:20.986220
3617 16:44:20.989451 Final TX Range 1 Vref 30
3618 16:44:20.989574
3619 16:44:20.989655 ==
3620 16:44:20.993306 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 16:44:20.996644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 16:44:20.996723 ==
3623 16:44:20.999465
3624 16:44:20.999564
3625 16:44:20.999663 TX Vref Scan disable
3626 16:44:21.002707 == TX Byte 0 ==
3627 16:44:21.006623 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3628 16:44:21.009271 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3629 16:44:21.013105 == TX Byte 1 ==
3630 16:44:21.016303 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3631 16:44:21.019718 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3632 16:44:21.022873
3633 16:44:21.022976 [DATLAT]
3634 16:44:21.023080 Freq=1200, CH1 RK1
3635 16:44:21.023180
3636 16:44:21.026127 DATLAT Default: 0xd
3637 16:44:21.026230 0, 0xFFFF, sum = 0
3638 16:44:21.029349 1, 0xFFFF, sum = 0
3639 16:44:21.029451 2, 0xFFFF, sum = 0
3640 16:44:21.033380 3, 0xFFFF, sum = 0
3641 16:44:21.033481 4, 0xFFFF, sum = 0
3642 16:44:21.036706 5, 0xFFFF, sum = 0
3643 16:44:21.036784 6, 0xFFFF, sum = 0
3644 16:44:21.040078 7, 0xFFFF, sum = 0
3645 16:44:21.042673 8, 0xFFFF, sum = 0
3646 16:44:21.042778 9, 0xFFFF, sum = 0
3647 16:44:21.046498 10, 0xFFFF, sum = 0
3648 16:44:21.046605 11, 0xFFFF, sum = 0
3649 16:44:21.049618 12, 0x0, sum = 1
3650 16:44:21.049709 13, 0x0, sum = 2
3651 16:44:21.052653 14, 0x0, sum = 3
3652 16:44:21.052726 15, 0x0, sum = 4
3653 16:44:21.052789 best_step = 13
3654 16:44:21.052849
3655 16:44:21.056466 ==
3656 16:44:21.059779 Dram Type= 6, Freq= 0, CH_1, rank 1
3657 16:44:21.062988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3658 16:44:21.063074 ==
3659 16:44:21.063141 RX Vref Scan: 0
3660 16:44:21.063202
3661 16:44:21.066461 RX Vref 0 -> 0, step: 1
3662 16:44:21.066545
3663 16:44:21.069678 RX Delay -5 -> 252, step: 4
3664 16:44:21.072873 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3665 16:44:21.076509 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3666 16:44:21.082987 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3667 16:44:21.086244 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3668 16:44:21.089480 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3669 16:44:21.092506 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3670 16:44:21.096207 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3671 16:44:21.102734 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3672 16:44:21.106026 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3673 16:44:21.109347 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3674 16:44:21.112993 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3675 16:44:21.116404 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3676 16:44:21.123019 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3677 16:44:21.125999 iDelay=195, Bit 13, Center 122 (63 ~ 182) 120
3678 16:44:21.129186 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3679 16:44:21.132536 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3680 16:44:21.132624 ==
3681 16:44:21.135758 Dram Type= 6, Freq= 0, CH_1, rank 1
3682 16:44:21.143073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3683 16:44:21.143159 ==
3684 16:44:21.143228 DQS Delay:
3685 16:44:21.146266 DQS0 = 0, DQS1 = 0
3686 16:44:21.146347 DQM Delay:
3687 16:44:21.149454 DQM0 = 120, DQM1 = 116
3688 16:44:21.149536 DQ Delay:
3689 16:44:21.152674 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3690 16:44:21.155871 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3691 16:44:21.159079 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3692 16:44:21.162837 DQ12 =126, DQ13 =122, DQ14 =122, DQ15 =124
3693 16:44:21.162942
3694 16:44:21.163041
3695 16:44:21.172635 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3696 16:44:21.172718 CH1 RK1: MR19=403, MR18=13F1
3697 16:44:21.179932 CH1_RK1: MR19=0x403, MR18=0x13F1, DQSOSC=402, MR23=63, INC=40, DEC=27
3698 16:44:21.182854 [RxdqsGatingPostProcess] freq 1200
3699 16:44:21.189230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3700 16:44:21.192437 best DQS0 dly(2T, 0.5T) = (0, 11)
3701 16:44:21.196130 best DQS1 dly(2T, 0.5T) = (0, 11)
3702 16:44:21.199432 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3703 16:44:21.202857 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3704 16:44:21.205945 best DQS0 dly(2T, 0.5T) = (0, 11)
3705 16:44:21.206053 best DQS1 dly(2T, 0.5T) = (0, 11)
3706 16:44:21.209248 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3707 16:44:21.212549 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3708 16:44:21.216341 Pre-setting of DQS Precalculation
3709 16:44:21.222620 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3710 16:44:21.229084 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3711 16:44:21.236020 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3712 16:44:21.236102
3713 16:44:21.236173
3714 16:44:21.239220 [Calibration Summary] 2400 Mbps
3715 16:44:21.239293 CH 0, Rank 0
3716 16:44:21.242389 SW Impedance : PASS
3717 16:44:21.245632 DUTY Scan : NO K
3718 16:44:21.245706 ZQ Calibration : PASS
3719 16:44:21.248940 Jitter Meter : NO K
3720 16:44:21.252503 CBT Training : PASS
3721 16:44:21.252578 Write leveling : PASS
3722 16:44:21.255811 RX DQS gating : PASS
3723 16:44:21.258973 RX DQ/DQS(RDDQC) : PASS
3724 16:44:21.259049 TX DQ/DQS : PASS
3725 16:44:21.262667 RX DATLAT : PASS
3726 16:44:21.265908 RX DQ/DQS(Engine): PASS
3727 16:44:21.265995 TX OE : NO K
3728 16:44:21.269015 All Pass.
3729 16:44:21.269120
3730 16:44:21.269214 CH 0, Rank 1
3731 16:44:21.272369 SW Impedance : PASS
3732 16:44:21.272469 DUTY Scan : NO K
3733 16:44:21.275773 ZQ Calibration : PASS
3734 16:44:21.279152 Jitter Meter : NO K
3735 16:44:21.279239 CBT Training : PASS
3736 16:44:21.282800 Write leveling : PASS
3737 16:44:21.282884 RX DQS gating : PASS
3738 16:44:21.286001 RX DQ/DQS(RDDQC) : PASS
3739 16:44:21.289053 TX DQ/DQS : PASS
3740 16:44:21.289138 RX DATLAT : PASS
3741 16:44:21.292374 RX DQ/DQS(Engine): PASS
3742 16:44:21.295768 TX OE : NO K
3743 16:44:21.295852 All Pass.
3744 16:44:21.295919
3745 16:44:21.295981 CH 1, Rank 0
3746 16:44:21.299651 SW Impedance : PASS
3747 16:44:21.302770 DUTY Scan : NO K
3748 16:44:21.302854 ZQ Calibration : PASS
3749 16:44:21.305918 Jitter Meter : NO K
3750 16:44:21.309262 CBT Training : PASS
3751 16:44:21.309350 Write leveling : PASS
3752 16:44:21.312348 RX DQS gating : PASS
3753 16:44:21.316149 RX DQ/DQS(RDDQC) : PASS
3754 16:44:21.316233 TX DQ/DQS : PASS
3755 16:44:21.319375 RX DATLAT : PASS
3756 16:44:21.319459 RX DQ/DQS(Engine): PASS
3757 16:44:21.322511 TX OE : NO K
3758 16:44:21.322595 All Pass.
3759 16:44:21.322661
3760 16:44:21.325703 CH 1, Rank 1
3761 16:44:21.325787 SW Impedance : PASS
3762 16:44:21.329746 DUTY Scan : NO K
3763 16:44:21.332387 ZQ Calibration : PASS
3764 16:44:21.332470 Jitter Meter : NO K
3765 16:44:21.336198 CBT Training : PASS
3766 16:44:21.339180 Write leveling : PASS
3767 16:44:21.339264 RX DQS gating : PASS
3768 16:44:21.343096 RX DQ/DQS(RDDQC) : PASS
3769 16:44:21.345713 TX DQ/DQS : PASS
3770 16:44:21.345796 RX DATLAT : PASS
3771 16:44:21.349022 RX DQ/DQS(Engine): PASS
3772 16:44:21.352458 TX OE : NO K
3773 16:44:21.352542 All Pass.
3774 16:44:21.352608
3775 16:44:21.352669 DramC Write-DBI off
3776 16:44:21.356375 PER_BANK_REFRESH: Hybrid Mode
3777 16:44:21.359104 TX_TRACKING: ON
3778 16:44:21.366120 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3779 16:44:21.369229 [FAST_K] Save calibration result to emmc
3780 16:44:21.376496 dramc_set_vcore_voltage set vcore to 650000
3781 16:44:21.376583 Read voltage for 600, 5
3782 16:44:21.379034 Vio18 = 0
3783 16:44:21.379119 Vcore = 650000
3784 16:44:21.379185 Vdram = 0
3785 16:44:21.382321 Vddq = 0
3786 16:44:21.382407 Vmddr = 0
3787 16:44:21.385612 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3788 16:44:21.392491 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3789 16:44:21.396055 MEM_TYPE=3, freq_sel=19
3790 16:44:21.399251 sv_algorithm_assistance_LP4_1600
3791 16:44:21.402430 ============ PULL DRAM RESETB DOWN ============
3792 16:44:21.405626 ========== PULL DRAM RESETB DOWN end =========
3793 16:44:21.409492 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3794 16:44:21.412609 ===================================
3795 16:44:21.415978 LPDDR4 DRAM CONFIGURATION
3796 16:44:21.419026 ===================================
3797 16:44:21.422676 EX_ROW_EN[0] = 0x0
3798 16:44:21.422782 EX_ROW_EN[1] = 0x0
3799 16:44:21.425908 LP4Y_EN = 0x0
3800 16:44:21.425984 WORK_FSP = 0x0
3801 16:44:21.429194 WL = 0x2
3802 16:44:21.429296 RL = 0x2
3803 16:44:21.432352 BL = 0x2
3804 16:44:21.432454 RPST = 0x0
3805 16:44:21.435566 RD_PRE = 0x0
3806 16:44:21.435667 WR_PRE = 0x1
3807 16:44:21.438920 WR_PST = 0x0
3808 16:44:21.439019 DBI_WR = 0x0
3809 16:44:21.442925 DBI_RD = 0x0
3810 16:44:21.443034 OTF = 0x1
3811 16:44:21.446113 ===================================
3812 16:44:21.449362 ===================================
3813 16:44:21.452558 ANA top config
3814 16:44:21.455781 ===================================
3815 16:44:21.459059 DLL_ASYNC_EN = 0
3816 16:44:21.459162 ALL_SLAVE_EN = 1
3817 16:44:21.462540 NEW_RANK_MODE = 1
3818 16:44:21.465626 DLL_IDLE_MODE = 1
3819 16:44:21.468978 LP45_APHY_COMB_EN = 1
3820 16:44:21.472207 TX_ODT_DIS = 1
3821 16:44:21.472318 NEW_8X_MODE = 1
3822 16:44:21.475503 ===================================
3823 16:44:21.479276 ===================================
3824 16:44:21.482502 data_rate = 1200
3825 16:44:21.485902 CKR = 1
3826 16:44:21.489082 DQ_P2S_RATIO = 8
3827 16:44:21.492341 ===================================
3828 16:44:21.495518 CA_P2S_RATIO = 8
3829 16:44:21.495619 DQ_CA_OPEN = 0
3830 16:44:21.498670 DQ_SEMI_OPEN = 0
3831 16:44:21.502525 CA_SEMI_OPEN = 0
3832 16:44:21.505587 CA_FULL_RATE = 0
3833 16:44:21.509293 DQ_CKDIV4_EN = 1
3834 16:44:21.512516 CA_CKDIV4_EN = 1
3835 16:44:21.512603 CA_PREDIV_EN = 0
3836 16:44:21.515693 PH8_DLY = 0
3837 16:44:21.519066 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 16:44:21.522213 DQ_AAMCK_DIV = 4
3839 16:44:21.525544 CA_AAMCK_DIV = 4
3840 16:44:21.528734 CA_ADMCK_DIV = 4
3841 16:44:21.528820 DQ_TRACK_CA_EN = 0
3842 16:44:21.532411 CA_PICK = 600
3843 16:44:21.535531 CA_MCKIO = 600
3844 16:44:21.538576 MCKIO_SEMI = 0
3845 16:44:21.541931 PLL_FREQ = 2288
3846 16:44:21.545582 DQ_UI_PI_RATIO = 32
3847 16:44:21.548543 CA_UI_PI_RATIO = 0
3848 16:44:21.551910 ===================================
3849 16:44:21.555095 ===================================
3850 16:44:21.555222 memory_type:LPDDR4
3851 16:44:21.558474 GP_NUM : 10
3852 16:44:21.561673 SRAM_EN : 1
3853 16:44:21.561788 MD32_EN : 0
3854 16:44:21.565040 ===================================
3855 16:44:21.568324 [ANA_INIT] >>>>>>>>>>>>>>
3856 16:44:21.571706 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 16:44:21.575018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 16:44:21.578260 ===================================
3859 16:44:21.581894 data_rate = 1200,PCW = 0X5800
3860 16:44:21.584952 ===================================
3861 16:44:21.588255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 16:44:21.591627 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 16:44:21.598210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 16:44:21.601336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 16:44:21.604529 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 16:44:21.608234 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 16:44:21.611327 [ANA_INIT] flow start
3868 16:44:21.615127 [ANA_INIT] PLL >>>>>>>>
3869 16:44:21.615216 [ANA_INIT] PLL <<<<<<<<
3870 16:44:21.618318 [ANA_INIT] MIDPI >>>>>>>>
3871 16:44:21.621526 [ANA_INIT] MIDPI <<<<<<<<
3872 16:44:21.624871 [ANA_INIT] DLL >>>>>>>>
3873 16:44:21.624955 [ANA_INIT] flow end
3874 16:44:21.628057 ============ LP4 DIFF to SE enter ============
3875 16:44:21.634664 ============ LP4 DIFF to SE exit ============
3876 16:44:21.634750 [ANA_INIT] <<<<<<<<<<<<<
3877 16:44:21.637913 [Flow] Enable top DCM control >>>>>
3878 16:44:21.640891 [Flow] Enable top DCM control <<<<<
3879 16:44:21.644758 Enable DLL master slave shuffle
3880 16:44:21.651030 ==============================================================
3881 16:44:21.654078 Gating Mode config
3882 16:44:21.657414 ==============================================================
3883 16:44:21.660799 Config description:
3884 16:44:21.670651 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3885 16:44:21.677315 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3886 16:44:21.680636 SELPH_MODE 0: By rank 1: By Phase
3887 16:44:21.687637 ==============================================================
3888 16:44:21.690459 GAT_TRACK_EN = 1
3889 16:44:21.694172 RX_GATING_MODE = 2
3890 16:44:21.697616 RX_GATING_TRACK_MODE = 2
3891 16:44:21.697709 SELPH_MODE = 1
3892 16:44:21.700812 PICG_EARLY_EN = 1
3893 16:44:21.703900 VALID_LAT_VALUE = 1
3894 16:44:21.710512 ==============================================================
3895 16:44:21.714105 Enter into Gating configuration >>>>
3896 16:44:21.717318 Exit from Gating configuration <<<<
3897 16:44:21.720445 Enter into DVFS_PRE_config >>>>>
3898 16:44:21.730164 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3899 16:44:21.733577 Exit from DVFS_PRE_config <<<<<
3900 16:44:21.736926 Enter into PICG configuration >>>>
3901 16:44:21.740167 Exit from PICG configuration <<<<
3902 16:44:21.743353 [RX_INPUT] configuration >>>>>
3903 16:44:21.746506 [RX_INPUT] configuration <<<<<
3904 16:44:21.750216 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3905 16:44:21.757092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3906 16:44:21.763489 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3907 16:44:21.770103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3908 16:44:21.776638 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3909 16:44:21.783516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3910 16:44:21.786735 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3911 16:44:21.790077 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3912 16:44:21.793295 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3913 16:44:21.796643 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3914 16:44:21.803236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3915 16:44:21.806344 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3916 16:44:21.809669 ===================================
3917 16:44:21.813054 LPDDR4 DRAM CONFIGURATION
3918 16:44:21.816108 ===================================
3919 16:44:21.816192 EX_ROW_EN[0] = 0x0
3920 16:44:21.819778 EX_ROW_EN[1] = 0x0
3921 16:44:21.819861 LP4Y_EN = 0x0
3922 16:44:21.822964 WORK_FSP = 0x0
3923 16:44:21.823047 WL = 0x2
3924 16:44:21.826106 RL = 0x2
3925 16:44:21.826219 BL = 0x2
3926 16:44:21.829810 RPST = 0x0
3927 16:44:21.829908 RD_PRE = 0x0
3928 16:44:21.833377 WR_PRE = 0x1
3929 16:44:21.836569 WR_PST = 0x0
3930 16:44:21.836668 DBI_WR = 0x0
3931 16:44:21.839811 DBI_RD = 0x0
3932 16:44:21.839893 OTF = 0x1
3933 16:44:21.843099 ===================================
3934 16:44:21.846524 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3935 16:44:21.849827 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3936 16:44:21.856451 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3937 16:44:21.859729 ===================================
3938 16:44:21.862766 LPDDR4 DRAM CONFIGURATION
3939 16:44:21.866550 ===================================
3940 16:44:21.866649 EX_ROW_EN[0] = 0x10
3941 16:44:21.869787 EX_ROW_EN[1] = 0x0
3942 16:44:21.869899 LP4Y_EN = 0x0
3943 16:44:21.873100 WORK_FSP = 0x0
3944 16:44:21.873197 WL = 0x2
3945 16:44:21.876373 RL = 0x2
3946 16:44:21.876472 BL = 0x2
3947 16:44:21.879738 RPST = 0x0
3948 16:44:21.879836 RD_PRE = 0x0
3949 16:44:21.883015 WR_PRE = 0x1
3950 16:44:21.883114 WR_PST = 0x0
3951 16:44:21.886300 DBI_WR = 0x0
3952 16:44:21.886413 DBI_RD = 0x0
3953 16:44:21.889622 OTF = 0x1
3954 16:44:21.892747 ===================================
3955 16:44:21.899308 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3956 16:44:21.902679 nWR fixed to 30
3957 16:44:21.905869 [ModeRegInit_LP4] CH0 RK0
3958 16:44:21.905966 [ModeRegInit_LP4] CH0 RK1
3959 16:44:21.909624 [ModeRegInit_LP4] CH1 RK0
3960 16:44:21.912699 [ModeRegInit_LP4] CH1 RK1
3961 16:44:21.912813 match AC timing 17
3962 16:44:21.919482 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3963 16:44:21.922525 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3964 16:44:21.926340 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3965 16:44:21.932590 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3966 16:44:21.935756 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3967 16:44:21.935841 ==
3968 16:44:21.939002 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 16:44:21.942695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 16:44:21.942781 ==
3971 16:44:21.949007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3972 16:44:21.956115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3973 16:44:21.959383 [CA 0] Center 36 (5~67) winsize 63
3974 16:44:21.962472 [CA 1] Center 36 (5~67) winsize 63
3975 16:44:21.965732 [CA 2] Center 33 (3~64) winsize 62
3976 16:44:21.969014 [CA 3] Center 33 (2~64) winsize 63
3977 16:44:21.972204 [CA 4] Center 33 (2~64) winsize 63
3978 16:44:21.975888 [CA 5] Center 32 (2~63) winsize 62
3979 16:44:21.975981
3980 16:44:21.979201 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3981 16:44:21.979284
3982 16:44:21.981969 [CATrainingPosCal] consider 1 rank data
3983 16:44:21.985920 u2DelayCellTimex100 = 270/100 ps
3984 16:44:21.988612 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3985 16:44:21.992535 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3986 16:44:21.995729 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3987 16:44:21.998958 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3988 16:44:22.002287 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3989 16:44:22.008748 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3990 16:44:22.008837
3991 16:44:22.011828 CA PerBit enable=1, Macro0, CA PI delay=32
3992 16:44:22.011940
3993 16:44:22.015229 [CBTSetCACLKResult] CA Dly = 32
3994 16:44:22.015332 CS Dly: 5 (0~36)
3995 16:44:22.015434 ==
3996 16:44:22.019000 Dram Type= 6, Freq= 0, CH_0, rank 1
3997 16:44:22.022242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3998 16:44:22.025527 ==
3999 16:44:22.028582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4000 16:44:22.035402 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4001 16:44:22.038738 [CA 0] Center 35 (5~66) winsize 62
4002 16:44:22.041840 [CA 1] Center 35 (5~66) winsize 62
4003 16:44:22.045069 [CA 2] Center 34 (3~65) winsize 63
4004 16:44:22.048866 [CA 3] Center 33 (3~64) winsize 62
4005 16:44:22.051849 [CA 4] Center 32 (2~63) winsize 62
4006 16:44:22.055176 [CA 5] Center 32 (2~63) winsize 62
4007 16:44:22.055277
4008 16:44:22.058320 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4009 16:44:22.058405
4010 16:44:22.061663 [CATrainingPosCal] consider 2 rank data
4011 16:44:22.064934 u2DelayCellTimex100 = 270/100 ps
4012 16:44:22.068703 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4013 16:44:22.072013 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4014 16:44:22.075165 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4015 16:44:22.081875 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4016 16:44:22.085147 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4017 16:44:22.088451 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4018 16:44:22.088560
4019 16:44:22.091801 CA PerBit enable=1, Macro0, CA PI delay=32
4020 16:44:22.091899
4021 16:44:22.095118 [CBTSetCACLKResult] CA Dly = 32
4022 16:44:22.095219 CS Dly: 5 (0~36)
4023 16:44:22.095312
4024 16:44:22.098451 ----->DramcWriteLeveling(PI) begin...
4025 16:44:22.098535 ==
4026 16:44:22.101812 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 16:44:22.108334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 16:44:22.108442 ==
4029 16:44:22.111706 Write leveling (Byte 0): 36 => 36
4030 16:44:22.114859 Write leveling (Byte 1): 30 => 30
4031 16:44:22.114942 DramcWriteLeveling(PI) end<-----
4032 16:44:22.118109
4033 16:44:22.118181 ==
4034 16:44:22.121652 Dram Type= 6, Freq= 0, CH_0, rank 0
4035 16:44:22.125265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4036 16:44:22.125342 ==
4037 16:44:22.128589 [Gating] SW mode calibration
4038 16:44:22.134947 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4039 16:44:22.138750 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4040 16:44:22.145053 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4041 16:44:22.148236 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 16:44:22.152027 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 16:44:22.158176 0 9 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (1 1)
4044 16:44:22.161844 0 9 16 | B1->B0 | 3232 2323 | 1 0 | (0 0) (0 0)
4045 16:44:22.165261 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4046 16:44:22.171950 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 16:44:22.175183 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 16:44:22.178320 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 16:44:22.185258 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 16:44:22.188418 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 16:44:22.191708 0 10 12 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
4052 16:44:22.198512 0 10 16 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
4053 16:44:22.202013 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 16:44:22.205170 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 16:44:22.211099 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 16:44:22.214348 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 16:44:22.218197 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 16:44:22.224673 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 16:44:22.228001 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4060 16:44:22.231209 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 16:44:22.237583 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 16:44:22.240833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 16:44:22.244540 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 16:44:22.250919 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 16:44:22.253974 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 16:44:22.257776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 16:44:22.264406 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 16:44:22.267380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 16:44:22.270558 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 16:44:22.277183 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 16:44:22.280906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 16:44:22.284288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 16:44:22.290413 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 16:44:22.293755 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 16:44:22.297664 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4076 16:44:22.300262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 16:44:22.303654 Total UI for P1: 0, mck2ui 16
4078 16:44:22.306912 best dqsien dly found for B0: ( 0, 13, 12)
4079 16:44:22.310256 Total UI for P1: 0, mck2ui 16
4080 16:44:22.313413 best dqsien dly found for B1: ( 0, 13, 14)
4081 16:44:22.317372 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4082 16:44:22.323727 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4083 16:44:22.323809
4084 16:44:22.327189 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4085 16:44:22.330491 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4086 16:44:22.333734 [Gating] SW calibration Done
4087 16:44:22.333824 ==
4088 16:44:22.336963 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 16:44:22.340206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 16:44:22.340288 ==
4091 16:44:22.343631 RX Vref Scan: 0
4092 16:44:22.343722
4093 16:44:22.343787 RX Vref 0 -> 0, step: 1
4094 16:44:22.343847
4095 16:44:22.347082 RX Delay -230 -> 252, step: 16
4096 16:44:22.350065 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4097 16:44:22.356687 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4098 16:44:22.360322 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4099 16:44:22.363413 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4100 16:44:22.366522 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4101 16:44:22.370116 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4102 16:44:22.376730 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4103 16:44:22.380029 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4104 16:44:22.383486 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4105 16:44:22.386773 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4106 16:44:22.393756 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4107 16:44:22.396979 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4108 16:44:22.399998 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4109 16:44:22.403222 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4110 16:44:22.410362 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4111 16:44:22.413694 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4112 16:44:22.413776 ==
4113 16:44:22.417038 Dram Type= 6, Freq= 0, CH_0, rank 0
4114 16:44:22.420442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4115 16:44:22.420524 ==
4116 16:44:22.423616 DQS Delay:
4117 16:44:22.423697 DQS0 = 0, DQS1 = 0
4118 16:44:22.423761 DQM Delay:
4119 16:44:22.426939 DQM0 = 51, DQM1 = 45
4120 16:44:22.427036 DQ Delay:
4121 16:44:22.430394 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4122 16:44:22.433873 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4123 16:44:22.437053 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4124 16:44:22.439815 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4125 16:44:22.439896
4126 16:44:22.439960
4127 16:44:22.440019 ==
4128 16:44:22.443570 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 16:44:22.450172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 16:44:22.450255 ==
4131 16:44:22.450319
4132 16:44:22.450379
4133 16:44:22.450436 TX Vref Scan disable
4134 16:44:22.453319 == TX Byte 0 ==
4135 16:44:22.456398 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4136 16:44:22.463485 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4137 16:44:22.463599 == TX Byte 1 ==
4138 16:44:22.466612 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4139 16:44:22.473203 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4140 16:44:22.473310 ==
4141 16:44:22.476869 Dram Type= 6, Freq= 0, CH_0, rank 0
4142 16:44:22.480098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 16:44:22.480206 ==
4144 16:44:22.480298
4145 16:44:22.480385
4146 16:44:22.483098 TX Vref Scan disable
4147 16:44:22.486689 == TX Byte 0 ==
4148 16:44:22.490102 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4149 16:44:22.493384 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4150 16:44:22.496423 == TX Byte 1 ==
4151 16:44:22.499768 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4152 16:44:22.503054 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4153 16:44:22.503136
4154 16:44:22.503201 [DATLAT]
4155 16:44:22.506741 Freq=600, CH0 RK0
4156 16:44:22.506824
4157 16:44:22.509763 DATLAT Default: 0x9
4158 16:44:22.509844 0, 0xFFFF, sum = 0
4159 16:44:22.513156 1, 0xFFFF, sum = 0
4160 16:44:22.513239 2, 0xFFFF, sum = 0
4161 16:44:22.516488 3, 0xFFFF, sum = 0
4162 16:44:22.516571 4, 0xFFFF, sum = 0
4163 16:44:22.519869 5, 0xFFFF, sum = 0
4164 16:44:22.519953 6, 0xFFFF, sum = 0
4165 16:44:22.523162 7, 0xFFFF, sum = 0
4166 16:44:22.523245 8, 0x0, sum = 1
4167 16:44:22.526531 9, 0x0, sum = 2
4168 16:44:22.526633 10, 0x0, sum = 3
4169 16:44:22.529811 11, 0x0, sum = 4
4170 16:44:22.529920 best_step = 9
4171 16:44:22.529989
4172 16:44:22.530050 ==
4173 16:44:22.533059 Dram Type= 6, Freq= 0, CH_0, rank 0
4174 16:44:22.536329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4175 16:44:22.536410 ==
4176 16:44:22.539720 RX Vref Scan: 1
4177 16:44:22.539819
4178 16:44:22.542972 RX Vref 0 -> 0, step: 1
4179 16:44:22.543080
4180 16:44:22.543177 RX Delay -163 -> 252, step: 8
4181 16:44:22.543265
4182 16:44:22.546048 Set Vref, RX VrefLevel [Byte0]: 60
4183 16:44:22.549240 [Byte1]: 44
4184 16:44:22.553807
4185 16:44:22.553889 Final RX Vref Byte 0 = 60 to rank0
4186 16:44:22.557033 Final RX Vref Byte 1 = 44 to rank0
4187 16:44:22.560709 Final RX Vref Byte 0 = 60 to rank1
4188 16:44:22.564023 Final RX Vref Byte 1 = 44 to rank1==
4189 16:44:22.567219 Dram Type= 6, Freq= 0, CH_0, rank 0
4190 16:44:22.570971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4191 16:44:22.574363 ==
4192 16:44:22.574444 DQS Delay:
4193 16:44:22.574509 DQS0 = 0, DQS1 = 0
4194 16:44:22.577703 DQM Delay:
4195 16:44:22.577816 DQM0 = 53, DQM1 = 46
4196 16:44:22.580665 DQ Delay:
4197 16:44:22.580746 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4198 16:44:22.583836 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4199 16:44:22.587646 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4200 16:44:22.590786 DQ12 =52, DQ13 =48, DQ14 =60, DQ15 =56
4201 16:44:22.590868
4202 16:44:22.593974
4203 16:44:22.601098 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4204 16:44:22.604321 CH0 RK0: MR19=808, MR18=6D5E
4205 16:44:22.610860 CH0_RK0: MR19=0x808, MR18=0x6D5E, DQSOSC=389, MR23=63, INC=173, DEC=115
4206 16:44:22.610964
4207 16:44:22.614009 ----->DramcWriteLeveling(PI) begin...
4208 16:44:22.614092 ==
4209 16:44:22.617135 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 16:44:22.621061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 16:44:22.621143 ==
4212 16:44:22.623741 Write leveling (Byte 0): 35 => 35
4213 16:44:22.627082 Write leveling (Byte 1): 34 => 34
4214 16:44:22.630445 DramcWriteLeveling(PI) end<-----
4215 16:44:22.630526
4216 16:44:22.630590 ==
4217 16:44:22.633778 Dram Type= 6, Freq= 0, CH_0, rank 1
4218 16:44:22.636996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4219 16:44:22.637103 ==
4220 16:44:22.640881 [Gating] SW mode calibration
4221 16:44:22.647447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4222 16:44:22.654079 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4223 16:44:22.657337 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4224 16:44:22.660535 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4225 16:44:22.667259 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4226 16:44:22.670591 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4227 16:44:22.673981 0 9 16 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
4228 16:44:22.680448 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 16:44:22.683968 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 16:44:22.687092 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 16:44:22.693716 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4232 16:44:22.697272 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4233 16:44:22.700442 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4234 16:44:22.707283 0 10 12 | B1->B0 | 2828 2828 | 0 0 | (0 0) (0 0)
4235 16:44:22.710579 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4236 16:44:22.713859 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 16:44:22.720284 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 16:44:22.723821 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 16:44:22.727093 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4240 16:44:22.733799 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4241 16:44:22.737144 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4242 16:44:22.740694 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4243 16:44:22.744190 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4244 16:44:22.750208 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 16:44:22.753626 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 16:44:22.757017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 16:44:22.763694 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 16:44:22.767065 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 16:44:22.770299 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 16:44:22.776829 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 16:44:22.780060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 16:44:22.783555 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 16:44:22.790325 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 16:44:22.793455 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 16:44:22.796659 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 16:44:22.803589 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 16:44:22.806684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 16:44:22.809933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 16:44:22.813342 Total UI for P1: 0, mck2ui 16
4260 16:44:22.816666 best dqsien dly found for B0: ( 0, 13, 10)
4261 16:44:22.819689 Total UI for P1: 0, mck2ui 16
4262 16:44:22.823134 best dqsien dly found for B1: ( 0, 13, 10)
4263 16:44:22.826484 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4264 16:44:22.829645 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4265 16:44:22.833526
4266 16:44:22.836855 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4267 16:44:22.840134 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4268 16:44:22.843329 [Gating] SW calibration Done
4269 16:44:22.843410 ==
4270 16:44:22.846751 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 16:44:22.849819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 16:44:22.849901 ==
4273 16:44:22.849966 RX Vref Scan: 0
4274 16:44:22.850026
4275 16:44:22.853198 RX Vref 0 -> 0, step: 1
4276 16:44:22.853305
4277 16:44:22.856558 RX Delay -230 -> 252, step: 16
4278 16:44:22.859844 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4279 16:44:22.863274 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4280 16:44:22.870094 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4281 16:44:22.873290 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4282 16:44:22.876570 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4283 16:44:22.879607 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4284 16:44:22.886161 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4285 16:44:22.889241 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4286 16:44:22.892660 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4287 16:44:22.896040 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4288 16:44:22.902901 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4289 16:44:22.906470 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4290 16:44:22.909588 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4291 16:44:22.913302 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4292 16:44:22.916550 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4293 16:44:22.923000 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4294 16:44:22.923425 ==
4295 16:44:22.926796 Dram Type= 6, Freq= 0, CH_0, rank 1
4296 16:44:22.930224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4297 16:44:22.930648 ==
4298 16:44:22.931103 DQS Delay:
4299 16:44:22.933381 DQS0 = 0, DQS1 = 0
4300 16:44:22.933843 DQM Delay:
4301 16:44:22.936649 DQM0 = 51, DQM1 = 44
4302 16:44:22.937069 DQ Delay:
4303 16:44:22.939847 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4304 16:44:22.943164 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4305 16:44:22.946970 DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =33
4306 16:44:22.950249 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4307 16:44:22.950675
4308 16:44:22.951005
4309 16:44:22.951312 ==
4310 16:44:22.953561 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 16:44:22.956719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 16:44:22.957157 ==
4313 16:44:22.957555
4314 16:44:22.960024
4315 16:44:22.960441 TX Vref Scan disable
4316 16:44:22.963501 == TX Byte 0 ==
4317 16:44:22.966734 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4318 16:44:22.970012 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4319 16:44:22.973210 == TX Byte 1 ==
4320 16:44:22.977071 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4321 16:44:22.980149 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4322 16:44:22.980574 ==
4323 16:44:22.983159 Dram Type= 6, Freq= 0, CH_0, rank 1
4324 16:44:22.990003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4325 16:44:22.990432 ==
4326 16:44:22.990764
4327 16:44:22.991092
4328 16:44:22.991422 TX Vref Scan disable
4329 16:44:22.994583 == TX Byte 0 ==
4330 16:44:22.997794 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4331 16:44:23.001001 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4332 16:44:23.004265 == TX Byte 1 ==
4333 16:44:23.007886 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4334 16:44:23.010971 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4335 16:44:23.013865
4336 16:44:23.013947 [DATLAT]
4337 16:44:23.014012 Freq=600, CH0 RK1
4338 16:44:23.014072
4339 16:44:23.017430 DATLAT Default: 0x9
4340 16:44:23.017573 0, 0xFFFF, sum = 0
4341 16:44:23.021054 1, 0xFFFF, sum = 0
4342 16:44:23.021138 2, 0xFFFF, sum = 0
4343 16:44:23.024179 3, 0xFFFF, sum = 0
4344 16:44:23.024263 4, 0xFFFF, sum = 0
4345 16:44:23.027454 5, 0xFFFF, sum = 0
4346 16:44:23.030626 6, 0xFFFF, sum = 0
4347 16:44:23.030709 7, 0xFFFF, sum = 0
4348 16:44:23.030775 8, 0x0, sum = 1
4349 16:44:23.033873 9, 0x0, sum = 2
4350 16:44:23.033955 10, 0x0, sum = 3
4351 16:44:23.037143 11, 0x0, sum = 4
4352 16:44:23.037225 best_step = 9
4353 16:44:23.037289
4354 16:44:23.037349 ==
4355 16:44:23.040509 Dram Type= 6, Freq= 0, CH_0, rank 1
4356 16:44:23.047417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4357 16:44:23.047502 ==
4358 16:44:23.047566 RX Vref Scan: 0
4359 16:44:23.047626
4360 16:44:23.050847 RX Vref 0 -> 0, step: 1
4361 16:44:23.050928
4362 16:44:23.054061 RX Delay -163 -> 252, step: 8
4363 16:44:23.057312 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4364 16:44:23.060584 iDelay=205, Bit 1, Center 60 (-75 ~ 196) 272
4365 16:44:23.067678 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4366 16:44:23.071149 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4367 16:44:23.074223 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4368 16:44:23.077382 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4369 16:44:23.080819 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4370 16:44:23.087674 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4371 16:44:23.090759 iDelay=205, Bit 8, Center 36 (-99 ~ 172) 272
4372 16:44:23.093942 iDelay=205, Bit 9, Center 32 (-107 ~ 172) 280
4373 16:44:23.097778 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4374 16:44:23.100871 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4375 16:44:23.107553 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4376 16:44:23.110732 iDelay=205, Bit 13, Center 52 (-83 ~ 188) 272
4377 16:44:23.114083 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4378 16:44:23.117327 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4379 16:44:23.117436 ==
4380 16:44:23.120482 Dram Type= 6, Freq= 0, CH_0, rank 1
4381 16:44:23.127200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 16:44:23.127292 ==
4383 16:44:23.127359 DQS Delay:
4384 16:44:23.130724 DQS0 = 0, DQS1 = 0
4385 16:44:23.130805 DQM Delay:
4386 16:44:23.130868 DQM0 = 55, DQM1 = 46
4387 16:44:23.133668 DQ Delay:
4388 16:44:23.137319 DQ0 =52, DQ1 =60, DQ2 =52, DQ3 =52
4389 16:44:23.140594 DQ4 =56, DQ5 =48, DQ6 =60, DQ7 =64
4390 16:44:23.143820 DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40
4391 16:44:23.147046 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4392 16:44:23.147126
4393 16:44:23.147188
4394 16:44:23.153898 [DQSOSCAuto] RK1, (LSB)MR18= 0x6626, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4395 16:44:23.157101 CH0 RK1: MR19=808, MR18=6626
4396 16:44:23.163745 CH0_RK1: MR19=0x808, MR18=0x6626, DQSOSC=390, MR23=63, INC=172, DEC=114
4397 16:44:23.166981 [RxdqsGatingPostProcess] freq 600
4398 16:44:23.170257 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4399 16:44:23.173650 Pre-setting of DQS Precalculation
4400 16:44:23.180221 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4401 16:44:23.180302 ==
4402 16:44:23.184028 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 16:44:23.187431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 16:44:23.187513 ==
4405 16:44:23.193826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4406 16:44:23.197504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4407 16:44:23.202003 [CA 0] Center 36 (5~67) winsize 63
4408 16:44:23.205057 [CA 1] Center 36 (5~67) winsize 63
4409 16:44:23.208252 [CA 2] Center 34 (4~65) winsize 62
4410 16:44:23.211622 [CA 3] Center 34 (4~65) winsize 62
4411 16:44:23.214837 [CA 4] Center 34 (4~65) winsize 62
4412 16:44:23.218615 [CA 5] Center 34 (3~65) winsize 63
4413 16:44:23.218698
4414 16:44:23.221409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4415 16:44:23.221492
4416 16:44:23.225235 [CATrainingPosCal] consider 1 rank data
4417 16:44:23.228310 u2DelayCellTimex100 = 270/100 ps
4418 16:44:23.231582 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4419 16:44:23.235372 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4420 16:44:23.241574 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4421 16:44:23.245385 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4422 16:44:23.248095 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4423 16:44:23.251458 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4424 16:44:23.251540
4425 16:44:23.255225 CA PerBit enable=1, Macro0, CA PI delay=34
4426 16:44:23.255307
4427 16:44:23.258469 [CBTSetCACLKResult] CA Dly = 34
4428 16:44:23.258552 CS Dly: 6 (0~37)
4429 16:44:23.261542 ==
4430 16:44:23.261638 Dram Type= 6, Freq= 0, CH_1, rank 1
4431 16:44:23.268059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4432 16:44:23.268142 ==
4433 16:44:23.271387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4434 16:44:23.277986 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4435 16:44:23.281826 [CA 0] Center 36 (5~67) winsize 63
4436 16:44:23.285115 [CA 1] Center 36 (5~67) winsize 63
4437 16:44:23.288324 [CA 2] Center 34 (4~65) winsize 62
4438 16:44:23.291734 [CA 3] Center 34 (4~65) winsize 62
4439 16:44:23.294977 [CA 4] Center 35 (4~66) winsize 63
4440 16:44:23.298497 [CA 5] Center 34 (3~65) winsize 63
4441 16:44:23.298589
4442 16:44:23.301446 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4443 16:44:23.301586
4444 16:44:23.305298 [CATrainingPosCal] consider 2 rank data
4445 16:44:23.308453 u2DelayCellTimex100 = 270/100 ps
4446 16:44:23.311705 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4447 16:44:23.315225 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4448 16:44:23.321670 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4449 16:44:23.324819 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4450 16:44:23.328556 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4451 16:44:23.331571 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4452 16:44:23.331661
4453 16:44:23.335418 CA PerBit enable=1, Macro0, CA PI delay=34
4454 16:44:23.335501
4455 16:44:23.338398 [CBTSetCACLKResult] CA Dly = 34
4456 16:44:23.338482 CS Dly: 6 (0~38)
4457 16:44:23.338548
4458 16:44:23.341473 ----->DramcWriteLeveling(PI) begin...
4459 16:44:23.345297 ==
4460 16:44:23.348383 Dram Type= 6, Freq= 0, CH_1, rank 0
4461 16:44:23.351609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4462 16:44:23.351694 ==
4463 16:44:23.354987 Write leveling (Byte 0): 31 => 31
4464 16:44:23.358702 Write leveling (Byte 1): 33 => 33
4465 16:44:23.361958 DramcWriteLeveling(PI) end<-----
4466 16:44:23.362041
4467 16:44:23.362107 ==
4468 16:44:23.364874 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 16:44:23.368076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 16:44:23.368166 ==
4471 16:44:23.371552 [Gating] SW mode calibration
4472 16:44:23.378493 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4473 16:44:23.381844 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4474 16:44:23.388470 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4475 16:44:23.391634 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4476 16:44:23.398256 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4477 16:44:23.401472 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4478 16:44:23.404698 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 16:44:23.407984 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 16:44:23.414739 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 16:44:23.417965 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 16:44:23.421207 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4483 16:44:23.428242 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4484 16:44:23.431569 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4485 16:44:23.434660 0 10 12 | B1->B0 | 3737 3939 | 1 0 | (0 0) (0 0)
4486 16:44:23.441383 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 16:44:23.444323 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 16:44:23.448176 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 16:44:23.454419 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 16:44:23.458363 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4491 16:44:23.460964 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4492 16:44:23.467860 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4493 16:44:23.471504 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4494 16:44:23.474717 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 16:44:23.481162 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 16:44:23.484494 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 16:44:23.487854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 16:44:23.494356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 16:44:23.497533 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 16:44:23.500779 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 16:44:23.507854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 16:44:23.511148 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 16:44:23.514458 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 16:44:23.517726 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 16:44:23.524398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 16:44:23.527544 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 16:44:23.530811 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 16:44:23.537462 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4509 16:44:23.541278 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4510 16:44:23.544361 Total UI for P1: 0, mck2ui 16
4511 16:44:23.547429 best dqsien dly found for B0: ( 0, 13, 8)
4512 16:44:23.551048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 16:44:23.554071 Total UI for P1: 0, mck2ui 16
4514 16:44:23.557909 best dqsien dly found for B1: ( 0, 13, 12)
4515 16:44:23.561011 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4516 16:44:23.567254 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4517 16:44:23.567330
4518 16:44:23.570644 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4519 16:44:23.574437 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4520 16:44:23.577571 [Gating] SW calibration Done
4521 16:44:23.577676 ==
4522 16:44:23.580556 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 16:44:23.584468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 16:44:23.584576 ==
4525 16:44:23.584661 RX Vref Scan: 0
4526 16:44:23.587564
4527 16:44:23.587663 RX Vref 0 -> 0, step: 1
4528 16:44:23.587760
4529 16:44:23.590952 RX Delay -230 -> 252, step: 16
4530 16:44:23.594251 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4531 16:44:23.600646 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4532 16:44:23.603992 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4533 16:44:23.607209 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4534 16:44:23.611045 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4535 16:44:23.613788 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4536 16:44:23.620987 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4537 16:44:23.624215 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4538 16:44:23.627421 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4539 16:44:23.630377 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4540 16:44:23.637495 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4541 16:44:23.640828 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4542 16:44:23.643996 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4543 16:44:23.647315 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4544 16:44:23.650508 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4545 16:44:23.657437 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4546 16:44:23.657574 ==
4547 16:44:23.660422 Dram Type= 6, Freq= 0, CH_1, rank 0
4548 16:44:23.664086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4549 16:44:23.664184 ==
4550 16:44:23.664274 DQS Delay:
4551 16:44:23.667281 DQS0 = 0, DQS1 = 0
4552 16:44:23.667392 DQM Delay:
4553 16:44:23.670367 DQM0 = 47, DQM1 = 46
4554 16:44:23.670440 DQ Delay:
4555 16:44:23.673615 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4556 16:44:23.677391 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4557 16:44:23.680621 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4558 16:44:23.683935 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4559 16:44:23.684049
4560 16:44:23.684153
4561 16:44:23.684253 ==
4562 16:44:23.687110 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 16:44:23.690117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 16:44:23.693730 ==
4565 16:44:23.693816
4566 16:44:23.693883
4567 16:44:23.693968 TX Vref Scan disable
4568 16:44:23.696937 == TX Byte 0 ==
4569 16:44:23.700079 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4570 16:44:23.704078 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4571 16:44:23.707317 == TX Byte 1 ==
4572 16:44:23.710540 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4573 16:44:23.713837 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4574 16:44:23.717083 ==
4575 16:44:23.717182 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 16:44:23.723754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 16:44:23.723837 ==
4578 16:44:23.723902
4579 16:44:23.723962
4580 16:44:23.726940 TX Vref Scan disable
4581 16:44:23.727022 == TX Byte 0 ==
4582 16:44:23.733586 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4583 16:44:23.737378 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4584 16:44:23.737462 == TX Byte 1 ==
4585 16:44:23.743690 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4586 16:44:23.746799 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4587 16:44:23.746882
4588 16:44:23.746947 [DATLAT]
4589 16:44:23.750118 Freq=600, CH1 RK0
4590 16:44:23.750217
4591 16:44:23.750296 DATLAT Default: 0x9
4592 16:44:23.753321 0, 0xFFFF, sum = 0
4593 16:44:23.753405 1, 0xFFFF, sum = 0
4594 16:44:23.757077 2, 0xFFFF, sum = 0
4595 16:44:23.757161 3, 0xFFFF, sum = 0
4596 16:44:23.760368 4, 0xFFFF, sum = 0
4597 16:44:23.760453 5, 0xFFFF, sum = 0
4598 16:44:23.763932 6, 0xFFFF, sum = 0
4599 16:44:23.767090 7, 0xFFFF, sum = 0
4600 16:44:23.767175 8, 0x0, sum = 1
4601 16:44:23.767242 9, 0x0, sum = 2
4602 16:44:23.770334 10, 0x0, sum = 3
4603 16:44:23.770417 11, 0x0, sum = 4
4604 16:44:23.773470 best_step = 9
4605 16:44:23.773606
4606 16:44:23.773686 ==
4607 16:44:23.776481 Dram Type= 6, Freq= 0, CH_1, rank 0
4608 16:44:23.780387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 16:44:23.780470 ==
4610 16:44:23.783688 RX Vref Scan: 1
4611 16:44:23.783769
4612 16:44:23.783835 RX Vref 0 -> 0, step: 1
4613 16:44:23.783896
4614 16:44:23.786736 RX Delay -163 -> 252, step: 8
4615 16:44:23.786840
4616 16:44:23.790099 Set Vref, RX VrefLevel [Byte0]: 55
4617 16:44:23.793295 [Byte1]: 48
4618 16:44:23.797263
4619 16:44:23.797342 Final RX Vref Byte 0 = 55 to rank0
4620 16:44:23.800363 Final RX Vref Byte 1 = 48 to rank0
4621 16:44:23.803829 Final RX Vref Byte 0 = 55 to rank1
4622 16:44:23.807248 Final RX Vref Byte 1 = 48 to rank1==
4623 16:44:23.810384 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 16:44:23.814271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 16:44:23.817530 ==
4626 16:44:23.817620 DQS Delay:
4627 16:44:23.817721 DQS0 = 0, DQS1 = 0
4628 16:44:23.820788 DQM Delay:
4629 16:44:23.820902 DQM0 = 48, DQM1 = 45
4630 16:44:23.824093 DQ Delay:
4631 16:44:23.827263 DQ0 =48, DQ1 =44, DQ2 =36, DQ3 =48
4632 16:44:23.827366 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4633 16:44:23.830684 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4634 16:44:23.833931 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4635 16:44:23.837044
4636 16:44:23.837155
4637 16:44:23.844188 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4638 16:44:23.847419 CH1 RK0: MR19=808, MR18=4C72
4639 16:44:23.853683 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4640 16:44:23.853779
4641 16:44:23.857065 ----->DramcWriteLeveling(PI) begin...
4642 16:44:23.857171 ==
4643 16:44:23.860808 Dram Type= 6, Freq= 0, CH_1, rank 1
4644 16:44:23.863879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4645 16:44:23.863992 ==
4646 16:44:23.866964 Write leveling (Byte 0): 29 => 29
4647 16:44:23.870053 Write leveling (Byte 1): 31 => 31
4648 16:44:23.873773 DramcWriteLeveling(PI) end<-----
4649 16:44:23.873886
4650 16:44:23.873982 ==
4651 16:44:23.876986 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 16:44:23.880597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 16:44:23.880699 ==
4654 16:44:23.883644 [Gating] SW mode calibration
4655 16:44:23.890172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4656 16:44:23.897272 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4657 16:44:23.900372 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4658 16:44:23.903638 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4659 16:44:23.910027 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4660 16:44:23.913164 0 9 12 | B1->B0 | 2b2b 3030 | 0 0 | (1 1) (1 1)
4661 16:44:23.917028 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
4662 16:44:23.923533 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 16:44:23.926909 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 16:44:23.930110 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4665 16:44:23.936648 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4666 16:44:23.939777 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4667 16:44:23.943733 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4668 16:44:23.950059 0 10 12 | B1->B0 | 3a3a 3434 | 0 0 | (0 0) (0 0)
4669 16:44:23.953352 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4670 16:44:23.957060 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 16:44:23.963461 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 16:44:23.966663 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 16:44:23.970354 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 16:44:23.976750 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4675 16:44:23.980547 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4676 16:44:23.983654 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4677 16:44:23.989991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4678 16:44:23.993336 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 16:44:23.997270 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 16:44:24.003559 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 16:44:24.006759 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 16:44:24.010074 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 16:44:24.013269 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 16:44:24.019886 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 16:44:24.023864 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 16:44:24.026486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 16:44:24.033520 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 16:44:24.036957 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 16:44:24.040184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 16:44:24.046647 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 16:44:24.049938 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 16:44:24.053047 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4693 16:44:24.059572 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 16:44:24.063338 Total UI for P1: 0, mck2ui 16
4695 16:44:24.066497 best dqsien dly found for B0: ( 0, 13, 14)
4696 16:44:24.066596 Total UI for P1: 0, mck2ui 16
4697 16:44:24.072932 best dqsien dly found for B1: ( 0, 13, 12)
4698 16:44:24.076732 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4699 16:44:24.079962 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4700 16:44:24.080060
4701 16:44:24.083017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4702 16:44:24.086610 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4703 16:44:24.090084 [Gating] SW calibration Done
4704 16:44:24.090162 ==
4705 16:44:24.093176 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 16:44:24.096378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 16:44:24.096475 ==
4708 16:44:24.099981 RX Vref Scan: 0
4709 16:44:24.100078
4710 16:44:24.100167 RX Vref 0 -> 0, step: 1
4711 16:44:24.100254
4712 16:44:24.103105 RX Delay -230 -> 252, step: 16
4713 16:44:24.109807 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4714 16:44:24.113183 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4715 16:44:24.116974 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4716 16:44:24.120128 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4717 16:44:24.123395 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4718 16:44:24.130154 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4719 16:44:24.133538 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4720 16:44:24.136793 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4721 16:44:24.140008 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4722 16:44:24.143220 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4723 16:44:24.149761 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4724 16:44:24.153429 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4725 16:44:24.156700 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4726 16:44:24.159903 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4727 16:44:24.166414 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4728 16:44:24.169740 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4729 16:44:24.169818 ==
4730 16:44:24.173048 Dram Type= 6, Freq= 0, CH_1, rank 1
4731 16:44:24.176198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4732 16:44:24.176295 ==
4733 16:44:24.179976 DQS Delay:
4734 16:44:24.180071 DQS0 = 0, DQS1 = 0
4735 16:44:24.180160 DQM Delay:
4736 16:44:24.183332 DQM0 = 52, DQM1 = 49
4737 16:44:24.183425 DQ Delay:
4738 16:44:24.185985 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4739 16:44:24.189477 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4740 16:44:24.192555 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4741 16:44:24.196198 DQ12 =57, DQ13 =65, DQ14 =49, DQ15 =65
4742 16:44:24.196296
4743 16:44:24.196389
4744 16:44:24.196476 ==
4745 16:44:24.199210 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 16:44:24.206217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 16:44:24.206291 ==
4748 16:44:24.206356
4749 16:44:24.206414
4750 16:44:24.206471 TX Vref Scan disable
4751 16:44:24.209901 == TX Byte 0 ==
4752 16:44:24.213047 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4753 16:44:24.220064 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4754 16:44:24.220165 == TX Byte 1 ==
4755 16:44:24.222786 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4756 16:44:24.229816 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4757 16:44:24.229889 ==
4758 16:44:24.233065 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 16:44:24.236179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 16:44:24.236278 ==
4761 16:44:24.236355
4762 16:44:24.236417
4763 16:44:24.239452 TX Vref Scan disable
4764 16:44:24.242740 == TX Byte 0 ==
4765 16:44:24.246068 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4766 16:44:24.249262 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4767 16:44:24.253033 == TX Byte 1 ==
4768 16:44:24.256362 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4769 16:44:24.259568 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4770 16:44:24.259666
4771 16:44:24.259756 [DATLAT]
4772 16:44:24.262994 Freq=600, CH1 RK1
4773 16:44:24.263064
4774 16:44:24.263122 DATLAT Default: 0x9
4775 16:44:24.266158 0, 0xFFFF, sum = 0
4776 16:44:24.269591 1, 0xFFFF, sum = 0
4777 16:44:24.269665 2, 0xFFFF, sum = 0
4778 16:44:24.272793 3, 0xFFFF, sum = 0
4779 16:44:24.272862 4, 0xFFFF, sum = 0
4780 16:44:24.276229 5, 0xFFFF, sum = 0
4781 16:44:24.276297 6, 0xFFFF, sum = 0
4782 16:44:24.279413 7, 0xFFFF, sum = 0
4783 16:44:24.279483 8, 0x0, sum = 1
4784 16:44:24.282356 9, 0x0, sum = 2
4785 16:44:24.282450 10, 0x0, sum = 3
4786 16:44:24.282571 11, 0x0, sum = 4
4787 16:44:24.285647 best_step = 9
4788 16:44:24.285749
4789 16:44:24.285842 ==
4790 16:44:24.288998 Dram Type= 6, Freq= 0, CH_1, rank 1
4791 16:44:24.292780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4792 16:44:24.292878 ==
4793 16:44:24.295883 RX Vref Scan: 0
4794 16:44:24.295981
4795 16:44:24.296054 RX Vref 0 -> 0, step: 1
4796 16:44:24.298946
4797 16:44:24.299013 RX Delay -163 -> 252, step: 8
4798 16:44:24.306465 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4799 16:44:24.310110 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4800 16:44:24.313126 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4801 16:44:24.316989 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4802 16:44:24.319877 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4803 16:44:24.326939 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4804 16:44:24.330262 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4805 16:44:24.333555 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4806 16:44:24.337083 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4807 16:44:24.340143 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4808 16:44:24.346538 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4809 16:44:24.349915 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4810 16:44:24.353139 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4811 16:44:24.357108 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4812 16:44:24.363405 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4813 16:44:24.366755 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4814 16:44:24.366859 ==
4815 16:44:24.369807 Dram Type= 6, Freq= 0, CH_1, rank 1
4816 16:44:24.373045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4817 16:44:24.373177 ==
4818 16:44:24.376332 DQS Delay:
4819 16:44:24.376441 DQS0 = 0, DQS1 = 0
4820 16:44:24.376540 DQM Delay:
4821 16:44:24.380448 DQM0 = 48, DQM1 = 45
4822 16:44:24.380547 DQ Delay:
4823 16:44:24.383098 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4824 16:44:24.386918 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =48
4825 16:44:24.390117 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4826 16:44:24.393413 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4827 16:44:24.393546
4828 16:44:24.393625
4829 16:44:24.403418 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c23, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4830 16:44:24.403569 CH1 RK1: MR19=808, MR18=6C23
4831 16:44:24.410069 CH1_RK1: MR19=0x808, MR18=0x6C23, DQSOSC=389, MR23=63, INC=173, DEC=115
4832 16:44:24.413169 [RxdqsGatingPostProcess] freq 600
4833 16:44:24.420268 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4834 16:44:24.423465 Pre-setting of DQS Precalculation
4835 16:44:24.426326 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4836 16:44:24.433011 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4837 16:44:24.443436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4838 16:44:24.443987
4839 16:44:24.444464
4840 16:44:24.446640 [Calibration Summary] 1200 Mbps
4841 16:44:24.447231 CH 0, Rank 0
4842 16:44:24.449892 SW Impedance : PASS
4843 16:44:24.450522 DUTY Scan : NO K
4844 16:44:24.453125 ZQ Calibration : PASS
4845 16:44:24.453704 Jitter Meter : NO K
4846 16:44:24.456955 CBT Training : PASS
4847 16:44:24.460316 Write leveling : PASS
4848 16:44:24.460912 RX DQS gating : PASS
4849 16:44:24.463559 RX DQ/DQS(RDDQC) : PASS
4850 16:44:24.466758 TX DQ/DQS : PASS
4851 16:44:24.467345 RX DATLAT : PASS
4852 16:44:24.469910 RX DQ/DQS(Engine): PASS
4853 16:44:24.473122 TX OE : NO K
4854 16:44:24.473840 All Pass.
4855 16:44:24.474411
4856 16:44:24.474969 CH 0, Rank 1
4857 16:44:24.476657 SW Impedance : PASS
4858 16:44:24.479896 DUTY Scan : NO K
4859 16:44:24.480529 ZQ Calibration : PASS
4860 16:44:24.483154 Jitter Meter : NO K
4861 16:44:24.486439 CBT Training : PASS
4862 16:44:24.486974 Write leveling : PASS
4863 16:44:24.489721 RX DQS gating : PASS
4864 16:44:24.492983 RX DQ/DQS(RDDQC) : PASS
4865 16:44:24.493745 TX DQ/DQS : PASS
4866 16:44:24.496788 RX DATLAT : PASS
4867 16:44:24.497439 RX DQ/DQS(Engine): PASS
4868 16:44:24.499928 TX OE : NO K
4869 16:44:24.500363 All Pass.
4870 16:44:24.500699
4871 16:44:24.503096 CH 1, Rank 0
4872 16:44:24.503513 SW Impedance : PASS
4873 16:44:24.506353 DUTY Scan : NO K
4874 16:44:24.509977 ZQ Calibration : PASS
4875 16:44:24.510386 Jitter Meter : NO K
4876 16:44:24.513293 CBT Training : PASS
4877 16:44:24.516774 Write leveling : PASS
4878 16:44:24.517454 RX DQS gating : PASS
4879 16:44:24.519711 RX DQ/DQS(RDDQC) : PASS
4880 16:44:24.523565 TX DQ/DQS : PASS
4881 16:44:24.524082 RX DATLAT : PASS
4882 16:44:24.526759 RX DQ/DQS(Engine): PASS
4883 16:44:24.529666 TX OE : NO K
4884 16:44:24.530093 All Pass.
4885 16:44:24.530430
4886 16:44:24.530742 CH 1, Rank 1
4887 16:44:24.533589 SW Impedance : PASS
4888 16:44:24.536502 DUTY Scan : NO K
4889 16:44:24.536922 ZQ Calibration : PASS
4890 16:44:24.540076 Jitter Meter : NO K
4891 16:44:24.540649 CBT Training : PASS
4892 16:44:24.543279 Write leveling : PASS
4893 16:44:24.546503 RX DQS gating : PASS
4894 16:44:24.546857 RX DQ/DQS(RDDQC) : PASS
4895 16:44:24.549361 TX DQ/DQS : PASS
4896 16:44:24.553239 RX DATLAT : PASS
4897 16:44:24.553349 RX DQ/DQS(Engine): PASS
4898 16:44:24.556420 TX OE : NO K
4899 16:44:24.556528 All Pass.
4900 16:44:24.556622
4901 16:44:24.559690 DramC Write-DBI off
4902 16:44:24.562893 PER_BANK_REFRESH: Hybrid Mode
4903 16:44:24.562992 TX_TRACKING: ON
4904 16:44:24.572694 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4905 16:44:24.576059 [FAST_K] Save calibration result to emmc
4906 16:44:24.580044 dramc_set_vcore_voltage set vcore to 662500
4907 16:44:24.583280 Read voltage for 933, 3
4908 16:44:24.583375 Vio18 = 0
4909 16:44:24.583450 Vcore = 662500
4910 16:44:24.586448 Vdram = 0
4911 16:44:24.586575 Vddq = 0
4912 16:44:24.586698 Vmddr = 0
4913 16:44:24.593330 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4914 16:44:24.596683 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4915 16:44:24.599754 MEM_TYPE=3, freq_sel=17
4916 16:44:24.602886 sv_algorithm_assistance_LP4_1600
4917 16:44:24.606669 ============ PULL DRAM RESETB DOWN ============
4918 16:44:24.609931 ========== PULL DRAM RESETB DOWN end =========
4919 16:44:24.616538 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4920 16:44:24.619544 ===================================
4921 16:44:24.623221 LPDDR4 DRAM CONFIGURATION
4922 16:44:24.626556 ===================================
4923 16:44:24.627035 EX_ROW_EN[0] = 0x0
4924 16:44:24.629742 EX_ROW_EN[1] = 0x0
4925 16:44:24.630182 LP4Y_EN = 0x0
4926 16:44:24.633180 WORK_FSP = 0x0
4927 16:44:24.633769 WL = 0x3
4928 16:44:24.636292 RL = 0x3
4929 16:44:24.636739 BL = 0x2
4930 16:44:24.639523 RPST = 0x0
4931 16:44:24.640094 RD_PRE = 0x0
4932 16:44:24.643085 WR_PRE = 0x1
4933 16:44:24.643618 WR_PST = 0x0
4934 16:44:24.646078 DBI_WR = 0x0
4935 16:44:24.646515 DBI_RD = 0x0
4936 16:44:24.649704 OTF = 0x1
4937 16:44:24.652795 ===================================
4938 16:44:24.656179 ===================================
4939 16:44:24.656639 ANA top config
4940 16:44:24.659339 ===================================
4941 16:44:24.662939 DLL_ASYNC_EN = 0
4942 16:44:24.666319 ALL_SLAVE_EN = 1
4943 16:44:24.669584 NEW_RANK_MODE = 1
4944 16:44:24.670053 DLL_IDLE_MODE = 1
4945 16:44:24.673033 LP45_APHY_COMB_EN = 1
4946 16:44:24.676003 TX_ODT_DIS = 1
4947 16:44:24.679474 NEW_8X_MODE = 1
4948 16:44:24.682614 ===================================
4949 16:44:24.686391 ===================================
4950 16:44:24.689805 data_rate = 1866
4951 16:44:24.690225 CKR = 1
4952 16:44:24.693134 DQ_P2S_RATIO = 8
4953 16:44:24.696180 ===================================
4954 16:44:24.699648 CA_P2S_RATIO = 8
4955 16:44:24.702893 DQ_CA_OPEN = 0
4956 16:44:24.706235 DQ_SEMI_OPEN = 0
4957 16:44:24.709203 CA_SEMI_OPEN = 0
4958 16:44:24.709767 CA_FULL_RATE = 0
4959 16:44:24.712729 DQ_CKDIV4_EN = 1
4960 16:44:24.715866 CA_CKDIV4_EN = 1
4961 16:44:24.719109 CA_PREDIV_EN = 0
4962 16:44:24.722371 PH8_DLY = 0
4963 16:44:24.725844 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4964 16:44:24.726224 DQ_AAMCK_DIV = 4
4965 16:44:24.729265 CA_AAMCK_DIV = 4
4966 16:44:24.732491 CA_ADMCK_DIV = 4
4967 16:44:24.735734 DQ_TRACK_CA_EN = 0
4968 16:44:24.739608 CA_PICK = 933
4969 16:44:24.742825 CA_MCKIO = 933
4970 16:44:24.745728 MCKIO_SEMI = 0
4971 16:44:24.746199 PLL_FREQ = 3732
4972 16:44:24.749150 DQ_UI_PI_RATIO = 32
4973 16:44:24.752858 CA_UI_PI_RATIO = 0
4974 16:44:24.755872 ===================================
4975 16:44:24.759098 ===================================
4976 16:44:24.762910 memory_type:LPDDR4
4977 16:44:24.763361 GP_NUM : 10
4978 16:44:24.766172 SRAM_EN : 1
4979 16:44:24.769280 MD32_EN : 0
4980 16:44:24.772461 ===================================
4981 16:44:24.772929 [ANA_INIT] >>>>>>>>>>>>>>
4982 16:44:24.775778 <<<<<< [CONFIGURE PHASE]: ANA_TX
4983 16:44:24.778978 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4984 16:44:24.782833 ===================================
4985 16:44:24.786085 data_rate = 1866,PCW = 0X8f00
4986 16:44:24.789140 ===================================
4987 16:44:24.792274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4988 16:44:24.799151 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4989 16:44:24.802354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4990 16:44:24.808826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4991 16:44:24.812089 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4992 16:44:24.815260 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4993 16:44:24.815735 [ANA_INIT] flow start
4994 16:44:24.818901 [ANA_INIT] PLL >>>>>>>>
4995 16:44:24.821909 [ANA_INIT] PLL <<<<<<<<
4996 16:44:24.825840 [ANA_INIT] MIDPI >>>>>>>>
4997 16:44:24.826286 [ANA_INIT] MIDPI <<<<<<<<
4998 16:44:24.828954 [ANA_INIT] DLL >>>>>>>>
4999 16:44:24.832014 [ANA_INIT] flow end
5000 16:44:24.835373 ============ LP4 DIFF to SE enter ============
5001 16:44:24.838239 ============ LP4 DIFF to SE exit ============
5002 16:44:24.842124 [ANA_INIT] <<<<<<<<<<<<<
5003 16:44:24.845352 [Flow] Enable top DCM control >>>>>
5004 16:44:24.848729 [Flow] Enable top DCM control <<<<<
5005 16:44:24.851889 Enable DLL master slave shuffle
5006 16:44:24.855302 ==============================================================
5007 16:44:24.858235 Gating Mode config
5008 16:44:24.865163 ==============================================================
5009 16:44:24.865245 Config description:
5010 16:44:24.874868 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5011 16:44:24.881406 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5012 16:44:24.885260 SELPH_MODE 0: By rank 1: By Phase
5013 16:44:24.891995 ==============================================================
5014 16:44:24.895228 GAT_TRACK_EN = 1
5015 16:44:24.898522 RX_GATING_MODE = 2
5016 16:44:24.901632 RX_GATING_TRACK_MODE = 2
5017 16:44:24.905009 SELPH_MODE = 1
5018 16:44:24.908340 PICG_EARLY_EN = 1
5019 16:44:24.908476 VALID_LAT_VALUE = 1
5020 16:44:24.914875 ==============================================================
5021 16:44:24.918979 Enter into Gating configuration >>>>
5022 16:44:24.921558 Exit from Gating configuration <<<<
5023 16:44:24.924868 Enter into DVFS_PRE_config >>>>>
5024 16:44:24.935232 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5025 16:44:24.938441 Exit from DVFS_PRE_config <<<<<
5026 16:44:24.941399 Enter into PICG configuration >>>>
5027 16:44:24.944744 Exit from PICG configuration <<<<
5028 16:44:24.948131 [RX_INPUT] configuration >>>>>
5029 16:44:24.951409 [RX_INPUT] configuration <<<<<
5030 16:44:24.958035 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5031 16:44:24.961220 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5032 16:44:24.967916 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5033 16:44:24.974601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5034 16:44:24.981077 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5035 16:44:24.987751 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5036 16:44:24.991449 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5037 16:44:24.995001 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5038 16:44:24.998140 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5039 16:44:25.001396 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5040 16:44:25.008061 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5041 16:44:25.011952 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5042 16:44:25.014766 ===================================
5043 16:44:25.018599 LPDDR4 DRAM CONFIGURATION
5044 16:44:25.021233 ===================================
5045 16:44:25.021824 EX_ROW_EN[0] = 0x0
5046 16:44:25.024582 EX_ROW_EN[1] = 0x0
5047 16:44:25.025105 LP4Y_EN = 0x0
5048 16:44:25.028533 WORK_FSP = 0x0
5049 16:44:25.028961 WL = 0x3
5050 16:44:25.031712 RL = 0x3
5051 16:44:25.032236 BL = 0x2
5052 16:44:25.034928 RPST = 0x0
5053 16:44:25.038090 RD_PRE = 0x0
5054 16:44:25.038519 WR_PRE = 0x1
5055 16:44:25.041220 WR_PST = 0x0
5056 16:44:25.041764 DBI_WR = 0x0
5057 16:44:25.044749 DBI_RD = 0x0
5058 16:44:25.045174 OTF = 0x1
5059 16:44:25.048054 ===================================
5060 16:44:25.051321 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5061 16:44:25.058011 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5062 16:44:25.061353 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5063 16:44:25.064514 ===================================
5064 16:44:25.067994 LPDDR4 DRAM CONFIGURATION
5065 16:44:25.071325 ===================================
5066 16:44:25.071782 EX_ROW_EN[0] = 0x10
5067 16:44:25.074491 EX_ROW_EN[1] = 0x0
5068 16:44:25.075010 LP4Y_EN = 0x0
5069 16:44:25.078039 WORK_FSP = 0x0
5070 16:44:25.078121 WL = 0x3
5071 16:44:25.081252 RL = 0x3
5072 16:44:25.081333 BL = 0x2
5073 16:44:25.084408 RPST = 0x0
5074 16:44:25.084496 RD_PRE = 0x0
5075 16:44:25.087522 WR_PRE = 0x1
5076 16:44:25.087611 WR_PST = 0x0
5077 16:44:25.090820 DBI_WR = 0x0
5078 16:44:25.094650 DBI_RD = 0x0
5079 16:44:25.094779 OTF = 0x1
5080 16:44:25.098016 ===================================
5081 16:44:25.104397 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5082 16:44:25.107595 nWR fixed to 30
5083 16:44:25.110984 [ModeRegInit_LP4] CH0 RK0
5084 16:44:25.111056 [ModeRegInit_LP4] CH0 RK1
5085 16:44:25.114194 [ModeRegInit_LP4] CH1 RK0
5086 16:44:25.117442 [ModeRegInit_LP4] CH1 RK1
5087 16:44:25.117545 match AC timing 9
5088 16:44:25.124096 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5089 16:44:25.127379 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5090 16:44:25.130888 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5091 16:44:25.137765 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5092 16:44:25.141201 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5093 16:44:25.141273 ==
5094 16:44:25.144602 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 16:44:25.147825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 16:44:25.147904 ==
5097 16:44:25.154544 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5098 16:44:25.160876 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5099 16:44:25.164299 [CA 0] Center 37 (6~68) winsize 63
5100 16:44:25.168015 [CA 1] Center 37 (7~68) winsize 62
5101 16:44:25.171178 [CA 2] Center 34 (4~65) winsize 62
5102 16:44:25.174552 [CA 3] Center 34 (3~65) winsize 63
5103 16:44:25.177744 [CA 4] Center 33 (2~64) winsize 63
5104 16:44:25.181297 [CA 5] Center 32 (2~63) winsize 62
5105 16:44:25.181400
5106 16:44:25.184267 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5107 16:44:25.184367
5108 16:44:25.187470 [CATrainingPosCal] consider 1 rank data
5109 16:44:25.191267 u2DelayCellTimex100 = 270/100 ps
5110 16:44:25.194358 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5111 16:44:25.197347 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5112 16:44:25.200503 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5113 16:44:25.203840 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5114 16:44:25.207363 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5115 16:44:25.210471 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5116 16:44:25.214535
5117 16:44:25.217740 CA PerBit enable=1, Macro0, CA PI delay=32
5118 16:44:25.217823
5119 16:44:25.220430 [CBTSetCACLKResult] CA Dly = 32
5120 16:44:25.220511 CS Dly: 5 (0~36)
5121 16:44:25.220575 ==
5122 16:44:25.224466 Dram Type= 6, Freq= 0, CH_0, rank 1
5123 16:44:25.227082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 16:44:25.227164 ==
5125 16:44:25.233669 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5126 16:44:25.240552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5127 16:44:25.243885 [CA 0] Center 37 (7~68) winsize 62
5128 16:44:25.247080 [CA 1] Center 37 (7~68) winsize 62
5129 16:44:25.250460 [CA 2] Center 34 (4~65) winsize 62
5130 16:44:25.253711 [CA 3] Center 34 (4~65) winsize 62
5131 16:44:25.257034 [CA 4] Center 33 (2~64) winsize 63
5132 16:44:25.260317 [CA 5] Center 32 (2~62) winsize 61
5133 16:44:25.260426
5134 16:44:25.263861 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5135 16:44:25.263945
5136 16:44:25.266991 [CATrainingPosCal] consider 2 rank data
5137 16:44:25.270171 u2DelayCellTimex100 = 270/100 ps
5138 16:44:25.274127 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5139 16:44:25.277355 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5140 16:44:25.280127 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5141 16:44:25.283728 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5142 16:44:25.290254 CA4 delay=33 (2~64),Diff = 1 PI (6 cell)
5143 16:44:25.294148 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5144 16:44:25.294289
5145 16:44:25.297242 CA PerBit enable=1, Macro0, CA PI delay=32
5146 16:44:25.297400
5147 16:44:25.300901 [CBTSetCACLKResult] CA Dly = 32
5148 16:44:25.301056 CS Dly: 5 (0~37)
5149 16:44:25.301182
5150 16:44:25.303867 ----->DramcWriteLeveling(PI) begin...
5151 16:44:25.303954 ==
5152 16:44:25.307034 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 16:44:25.313318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 16:44:25.313456 ==
5155 16:44:25.316769 Write leveling (Byte 0): 33 => 33
5156 16:44:25.316919 Write leveling (Byte 1): 29 => 29
5157 16:44:25.320318 DramcWriteLeveling(PI) end<-----
5158 16:44:25.320399
5159 16:44:25.323589 ==
5160 16:44:25.323679 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 16:44:25.330255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 16:44:25.330337 ==
5163 16:44:25.333787 [Gating] SW mode calibration
5164 16:44:25.340225 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5165 16:44:25.343425 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5166 16:44:25.349981 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
5167 16:44:25.353205 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 16:44:25.357047 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 16:44:25.363229 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5170 16:44:25.366569 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5171 16:44:25.369639 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5172 16:44:25.376450 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5173 16:44:25.380235 0 14 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 0)
5174 16:44:25.383437 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5175 16:44:25.390066 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 16:44:25.393372 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 16:44:25.396460 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 16:44:25.406052 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5179 16:44:25.407140 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5180 16:44:25.409766 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5181 16:44:25.416511 0 15 28 | B1->B0 | 2a2a 4140 | 0 1 | (0 0) (0 0)
5182 16:44:25.419594 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5183 16:44:25.422915 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 16:44:25.429709 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 16:44:25.433609 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5186 16:44:25.436224 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5187 16:44:25.439524 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5188 16:44:25.446716 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5189 16:44:25.449657 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5190 16:44:25.452965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5191 16:44:25.459980 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 16:44:25.463476 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 16:44:25.466686 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 16:44:25.473166 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 16:44:25.476388 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 16:44:25.479630 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 16:44:25.486603 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 16:44:25.490081 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 16:44:25.493152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 16:44:25.499865 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 16:44:25.502911 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 16:44:25.506531 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 16:44:25.513001 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 16:44:25.516608 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5205 16:44:25.519798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5206 16:44:25.526229 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5207 16:44:25.526670 Total UI for P1: 0, mck2ui 16
5208 16:44:25.533251 best dqsien dly found for B0: ( 1, 2, 26)
5209 16:44:25.536657 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 16:44:25.539875 Total UI for P1: 0, mck2ui 16
5211 16:44:25.543199 best dqsien dly found for B1: ( 1, 2, 30)
5212 16:44:25.546546 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5213 16:44:25.549773 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5214 16:44:25.550234
5215 16:44:25.553258 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5216 16:44:25.556304 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5217 16:44:25.559639 [Gating] SW calibration Done
5218 16:44:25.560061 ==
5219 16:44:25.563001 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 16:44:25.566397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 16:44:25.566869 ==
5222 16:44:25.569503 RX Vref Scan: 0
5223 16:44:25.569916
5224 16:44:25.572877 RX Vref 0 -> 0, step: 1
5225 16:44:25.573446
5226 16:44:25.573845 RX Delay -80 -> 252, step: 8
5227 16:44:25.579420 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5228 16:44:25.582718 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5229 16:44:25.586137 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5230 16:44:25.589583 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5231 16:44:25.592625 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5232 16:44:25.599525 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5233 16:44:25.602611 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5234 16:44:25.605780 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5235 16:44:25.609625 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5236 16:44:25.612819 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5237 16:44:25.616152 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5238 16:44:25.622215 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5239 16:44:25.626273 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5240 16:44:25.629164 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5241 16:44:25.632225 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5242 16:44:25.635457 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5243 16:44:25.635747 ==
5244 16:44:25.638803 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 16:44:25.645399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 16:44:25.645756 ==
5247 16:44:25.646063 DQS Delay:
5248 16:44:25.648636 DQS0 = 0, DQS1 = 0
5249 16:44:25.648841 DQM Delay:
5250 16:44:25.649121 DQM0 = 104, DQM1 = 94
5251 16:44:25.652028 DQ Delay:
5252 16:44:25.655741 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5253 16:44:25.659119 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5254 16:44:25.662130 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5255 16:44:25.665635 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5256 16:44:25.665948
5257 16:44:25.666254
5258 16:44:25.666555 ==
5259 16:44:25.668840 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 16:44:25.672294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 16:44:25.672585 ==
5262 16:44:25.672822
5263 16:44:25.673009
5264 16:44:25.675659 TX Vref Scan disable
5265 16:44:25.678775 == TX Byte 0 ==
5266 16:44:25.682302 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5267 16:44:25.685624 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5268 16:44:25.688958 == TX Byte 1 ==
5269 16:44:25.692188 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5270 16:44:25.695633 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5271 16:44:25.695920 ==
5272 16:44:25.698861 Dram Type= 6, Freq= 0, CH_0, rank 0
5273 16:44:25.702115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5274 16:44:25.702413 ==
5275 16:44:25.705129
5276 16:44:25.705409
5277 16:44:25.705659 TX Vref Scan disable
5278 16:44:25.708897 == TX Byte 0 ==
5279 16:44:25.711908 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5280 16:44:25.719236 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5281 16:44:25.719467 == TX Byte 1 ==
5282 16:44:25.721926 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5283 16:44:25.728717 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5284 16:44:25.729020
5285 16:44:25.729278 [DATLAT]
5286 16:44:25.729563 Freq=933, CH0 RK0
5287 16:44:25.729739
5288 16:44:25.732088 DATLAT Default: 0xd
5289 16:44:25.732379 0, 0xFFFF, sum = 0
5290 16:44:25.735419 1, 0xFFFF, sum = 0
5291 16:44:25.735680 2, 0xFFFF, sum = 0
5292 16:44:25.739045 3, 0xFFFF, sum = 0
5293 16:44:25.742199 4, 0xFFFF, sum = 0
5294 16:44:25.742410 5, 0xFFFF, sum = 0
5295 16:44:25.745385 6, 0xFFFF, sum = 0
5296 16:44:25.745617 7, 0xFFFF, sum = 0
5297 16:44:25.748639 8, 0xFFFF, sum = 0
5298 16:44:25.748844 9, 0xFFFF, sum = 0
5299 16:44:25.751859 10, 0x0, sum = 1
5300 16:44:25.752129 11, 0x0, sum = 2
5301 16:44:25.755261 12, 0x0, sum = 3
5302 16:44:25.755489 13, 0x0, sum = 4
5303 16:44:25.755671 best_step = 11
5304 16:44:25.755858
5305 16:44:25.758618 ==
5306 16:44:25.761740 Dram Type= 6, Freq= 0, CH_0, rank 0
5307 16:44:25.765224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 16:44:25.765452 ==
5309 16:44:25.765676 RX Vref Scan: 1
5310 16:44:25.765849
5311 16:44:25.768365 RX Vref 0 -> 0, step: 1
5312 16:44:25.768597
5313 16:44:25.771719 RX Delay -45 -> 252, step: 4
5314 16:44:25.771947
5315 16:44:25.775034 Set Vref, RX VrefLevel [Byte0]: 60
5316 16:44:25.778453 [Byte1]: 44
5317 16:44:25.778696
5318 16:44:25.782141 Final RX Vref Byte 0 = 60 to rank0
5319 16:44:25.785507 Final RX Vref Byte 1 = 44 to rank0
5320 16:44:25.788842 Final RX Vref Byte 0 = 60 to rank1
5321 16:44:25.792187 Final RX Vref Byte 1 = 44 to rank1==
5322 16:44:25.795519 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 16:44:25.798997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 16:44:25.799228 ==
5325 16:44:25.801589 DQS Delay:
5326 16:44:25.801867 DQS0 = 0, DQS1 = 0
5327 16:44:25.805560 DQM Delay:
5328 16:44:25.805919 DQM0 = 105, DQM1 = 94
5329 16:44:25.806240 DQ Delay:
5330 16:44:25.811993 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5331 16:44:25.815106 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5332 16:44:25.818597 DQ8 =84, DQ9 =84, DQ10 =96, DQ11 =88
5333 16:44:25.821731 DQ12 =98, DQ13 =98, DQ14 =106, DQ15 =102
5334 16:44:25.821980
5335 16:44:25.822191
5336 16:44:25.828722 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5337 16:44:25.832137 CH0 RK0: MR19=505, MR18=332B
5338 16:44:25.838303 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5339 16:44:25.838391
5340 16:44:25.841654 ----->DramcWriteLeveling(PI) begin...
5341 16:44:25.841738 ==
5342 16:44:25.844674 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 16:44:25.848530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 16:44:25.848616 ==
5345 16:44:25.851513 Write leveling (Byte 0): 32 => 32
5346 16:44:25.854622 Write leveling (Byte 1): 29 => 29
5347 16:44:25.858572 DramcWriteLeveling(PI) end<-----
5348 16:44:25.858657
5349 16:44:25.858722 ==
5350 16:44:25.861227 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 16:44:25.864527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 16:44:25.864609 ==
5353 16:44:25.868276 [Gating] SW mode calibration
5354 16:44:25.874848 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5355 16:44:25.881396 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5356 16:44:25.884698 0 14 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
5357 16:44:25.891264 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 16:44:25.894657 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 16:44:25.898011 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5360 16:44:25.901331 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5361 16:44:25.908119 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5362 16:44:25.911447 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5363 16:44:25.914831 0 14 28 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
5364 16:44:25.921155 0 15 0 | B1->B0 | 2525 2626 | 0 0 | (1 0) (0 1)
5365 16:44:25.924940 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 16:44:25.928062 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 16:44:25.934779 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5368 16:44:25.937977 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5369 16:44:25.940909 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5370 16:44:25.947495 0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5371 16:44:25.950817 0 15 28 | B1->B0 | 3838 3635 | 0 1 | (0 0) (0 0)
5372 16:44:25.954423 1 0 0 | B1->B0 | 4646 4444 | 0 1 | (0 0) (0 0)
5373 16:44:25.961216 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 16:44:25.964428 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 16:44:25.967706 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5376 16:44:25.974756 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5377 16:44:25.977947 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5378 16:44:25.981288 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 16:44:25.988022 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5380 16:44:25.991107 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 16:44:25.994543 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 16:44:26.001254 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 16:44:26.004554 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 16:44:26.007782 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 16:44:26.014287 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 16:44:26.017625 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 16:44:26.021169 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 16:44:26.027380 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 16:44:26.031094 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 16:44:26.034439 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 16:44:26.040916 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 16:44:26.044061 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 16:44:26.047375 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 16:44:26.050504 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 16:44:26.057464 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5396 16:44:26.060736 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 16:44:26.064173 Total UI for P1: 0, mck2ui 16
5398 16:44:26.067355 best dqsien dly found for B0: ( 1, 2, 28)
5399 16:44:26.070502 Total UI for P1: 0, mck2ui 16
5400 16:44:26.073679 best dqsien dly found for B1: ( 1, 2, 28)
5401 16:44:26.077408 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5402 16:44:26.080356 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5403 16:44:26.080490
5404 16:44:26.083608 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5405 16:44:26.090464 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5406 16:44:26.090568 [Gating] SW calibration Done
5407 16:44:26.090659 ==
5408 16:44:26.093801 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 16:44:26.100930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 16:44:26.101034 ==
5411 16:44:26.101124 RX Vref Scan: 0
5412 16:44:26.101218
5413 16:44:26.103540 RX Vref 0 -> 0, step: 1
5414 16:44:26.103636
5415 16:44:26.107024 RX Delay -80 -> 252, step: 8
5416 16:44:26.110879 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5417 16:44:26.113996 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5418 16:44:26.117372 iDelay=208, Bit 2, Center 107 (16 ~ 199) 184
5419 16:44:26.124196 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5420 16:44:26.127311 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5421 16:44:26.130375 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5422 16:44:26.133495 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5423 16:44:26.137380 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5424 16:44:26.140817 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5425 16:44:26.147103 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5426 16:44:26.150325 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5427 16:44:26.153558 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5428 16:44:26.156866 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5429 16:44:26.160657 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5430 16:44:26.163986 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5431 16:44:26.170157 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5432 16:44:26.170236 ==
5433 16:44:26.173735 Dram Type= 6, Freq= 0, CH_0, rank 1
5434 16:44:26.176855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5435 16:44:26.176950 ==
5436 16:44:26.177042 DQS Delay:
5437 16:44:26.180364 DQS0 = 0, DQS1 = 0
5438 16:44:26.180469 DQM Delay:
5439 16:44:26.183627 DQM0 = 106, DQM1 = 95
5440 16:44:26.183725 DQ Delay:
5441 16:44:26.187141 DQ0 =107, DQ1 =107, DQ2 =107, DQ3 =103
5442 16:44:26.190277 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5443 16:44:26.193668 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5444 16:44:26.197003 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5445 16:44:26.197089
5446 16:44:26.197183
5447 16:44:26.197272 ==
5448 16:44:26.200263 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 16:44:26.207067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 16:44:26.207176 ==
5451 16:44:26.207273
5452 16:44:26.207368
5453 16:44:26.207459 TX Vref Scan disable
5454 16:44:26.211228 == TX Byte 0 ==
5455 16:44:26.214389 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5456 16:44:26.217840 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5457 16:44:26.220492 == TX Byte 1 ==
5458 16:44:26.223848 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5459 16:44:26.230486 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5460 16:44:26.230569 ==
5461 16:44:26.234305 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 16:44:26.237338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 16:44:26.237426 ==
5464 16:44:26.237501
5465 16:44:26.237605
5466 16:44:26.240440 TX Vref Scan disable
5467 16:44:26.240522 == TX Byte 0 ==
5468 16:44:26.247431 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5469 16:44:26.250509 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5470 16:44:26.250594 == TX Byte 1 ==
5471 16:44:26.257743 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5472 16:44:26.260267 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5473 16:44:26.260351
5474 16:44:26.260416 [DATLAT]
5475 16:44:26.264233 Freq=933, CH0 RK1
5476 16:44:26.264316
5477 16:44:26.264381 DATLAT Default: 0xb
5478 16:44:26.266975 0, 0xFFFF, sum = 0
5479 16:44:26.267060 1, 0xFFFF, sum = 0
5480 16:44:26.270936 2, 0xFFFF, sum = 0
5481 16:44:26.271020 3, 0xFFFF, sum = 0
5482 16:44:26.273919 4, 0xFFFF, sum = 0
5483 16:44:26.274004 5, 0xFFFF, sum = 0
5484 16:44:26.277215 6, 0xFFFF, sum = 0
5485 16:44:26.280404 7, 0xFFFF, sum = 0
5486 16:44:26.280489 8, 0xFFFF, sum = 0
5487 16:44:26.283666 9, 0xFFFF, sum = 0
5488 16:44:26.283750 10, 0x0, sum = 1
5489 16:44:26.287269 11, 0x0, sum = 2
5490 16:44:26.287396 12, 0x0, sum = 3
5491 16:44:26.287565 13, 0x0, sum = 4
5492 16:44:26.290546 best_step = 11
5493 16:44:26.290677
5494 16:44:26.290794 ==
5495 16:44:26.293619 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 16:44:26.297187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 16:44:26.297296 ==
5498 16:44:26.300423 RX Vref Scan: 0
5499 16:44:26.300524
5500 16:44:26.300603 RX Vref 0 -> 0, step: 1
5501 16:44:26.303413
5502 16:44:26.303486 RX Delay -45 -> 252, step: 4
5503 16:44:26.311310 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5504 16:44:26.314676 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5505 16:44:26.317472 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5506 16:44:26.320939 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5507 16:44:26.324274 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5508 16:44:26.330935 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5509 16:44:26.334175 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5510 16:44:26.337476 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5511 16:44:26.340748 iDelay=199, Bit 8, Center 84 (3 ~ 166) 164
5512 16:44:26.344165 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5513 16:44:26.351006 iDelay=199, Bit 10, Center 94 (15 ~ 174) 160
5514 16:44:26.354158 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5515 16:44:26.357764 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5516 16:44:26.361002 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5517 16:44:26.364156 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5518 16:44:26.370891 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5519 16:44:26.370981 ==
5520 16:44:26.374049 Dram Type= 6, Freq= 0, CH_0, rank 1
5521 16:44:26.377368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 16:44:26.377479 ==
5523 16:44:26.377595 DQS Delay:
5524 16:44:26.381154 DQS0 = 0, DQS1 = 0
5525 16:44:26.381235 DQM Delay:
5526 16:44:26.384517 DQM0 = 105, DQM1 = 93
5527 16:44:26.384606 DQ Delay:
5528 16:44:26.387653 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5529 16:44:26.390993 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5530 16:44:26.393929 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5531 16:44:26.397607 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5532 16:44:26.397689
5533 16:44:26.397754
5534 16:44:26.407437 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 407 ps
5535 16:44:26.407537 CH0 RK1: MR19=505, MR18=2D05
5536 16:44:26.413870 CH0_RK1: MR19=0x505, MR18=0x2D05, DQSOSC=407, MR23=63, INC=65, DEC=43
5537 16:44:26.417203 [RxdqsGatingPostProcess] freq 933
5538 16:44:26.423856 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5539 16:44:26.427173 best DQS0 dly(2T, 0.5T) = (0, 10)
5540 16:44:26.430511 best DQS1 dly(2T, 0.5T) = (0, 10)
5541 16:44:26.433905 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5542 16:44:26.437242 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5543 16:44:26.440563 best DQS0 dly(2T, 0.5T) = (0, 10)
5544 16:44:26.440667 best DQS1 dly(2T, 0.5T) = (0, 10)
5545 16:44:26.443899 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5546 16:44:26.447457 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5547 16:44:26.450670 Pre-setting of DQS Precalculation
5548 16:44:26.457034 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5549 16:44:26.457139 ==
5550 16:44:26.460887 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 16:44:26.464023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 16:44:26.464107 ==
5553 16:44:26.470992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5554 16:44:26.477312 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5555 16:44:26.480711 [CA 0] Center 37 (6~68) winsize 63
5556 16:44:26.484102 [CA 1] Center 37 (6~68) winsize 63
5557 16:44:26.487230 [CA 2] Center 34 (4~65) winsize 62
5558 16:44:26.490568 [CA 3] Center 34 (4~65) winsize 62
5559 16:44:26.493798 [CA 4] Center 34 (4~64) winsize 61
5560 16:44:26.497291 [CA 5] Center 33 (3~64) winsize 62
5561 16:44:26.497406
5562 16:44:26.500582 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5563 16:44:26.500693
5564 16:44:26.504085 [CATrainingPosCal] consider 1 rank data
5565 16:44:26.507183 u2DelayCellTimex100 = 270/100 ps
5566 16:44:26.510406 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5567 16:44:26.514033 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5568 16:44:26.517065 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5569 16:44:26.520372 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5570 16:44:26.523750 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5571 16:44:26.527245 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5572 16:44:26.527348
5573 16:44:26.533833 CA PerBit enable=1, Macro0, CA PI delay=33
5574 16:44:26.533920
5575 16:44:26.534001 [CBTSetCACLKResult] CA Dly = 33
5576 16:44:26.537299 CS Dly: 7 (0~38)
5577 16:44:26.537407 ==
5578 16:44:26.539918 Dram Type= 6, Freq= 0, CH_1, rank 1
5579 16:44:26.543387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 16:44:26.543492 ==
5581 16:44:26.550164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5582 16:44:26.556882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5583 16:44:26.559980 [CA 0] Center 36 (6~67) winsize 62
5584 16:44:26.563255 [CA 1] Center 37 (7~68) winsize 62
5585 16:44:26.566546 [CA 2] Center 35 (5~66) winsize 62
5586 16:44:26.569775 [CA 3] Center 34 (4~65) winsize 62
5587 16:44:26.573023 [CA 4] Center 34 (4~65) winsize 62
5588 16:44:26.576822 [CA 5] Center 34 (4~64) winsize 61
5589 16:44:26.576926
5590 16:44:26.579675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5591 16:44:26.579752
5592 16:44:26.582845 [CATrainingPosCal] consider 2 rank data
5593 16:44:26.586243 u2DelayCellTimex100 = 270/100 ps
5594 16:44:26.589647 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5595 16:44:26.592944 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5596 16:44:26.596080 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5597 16:44:26.599541 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5598 16:44:26.602867 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5599 16:44:26.609403 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5600 16:44:26.609520
5601 16:44:26.613127 CA PerBit enable=1, Macro0, CA PI delay=34
5602 16:44:26.613237
5603 16:44:26.615667 [CBTSetCACLKResult] CA Dly = 34
5604 16:44:26.615768 CS Dly: 8 (0~40)
5605 16:44:26.615858
5606 16:44:26.619370 ----->DramcWriteLeveling(PI) begin...
5607 16:44:26.619453 ==
5608 16:44:26.622688 Dram Type= 6, Freq= 0, CH_1, rank 0
5609 16:44:26.629462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5610 16:44:26.629586 ==
5611 16:44:26.632745 Write leveling (Byte 0): 27 => 27
5612 16:44:26.632823 Write leveling (Byte 1): 28 => 28
5613 16:44:26.636173 DramcWriteLeveling(PI) end<-----
5614 16:44:26.636273
5615 16:44:26.639456 ==
5616 16:44:26.639574 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 16:44:26.646171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 16:44:26.646247 ==
5619 16:44:26.649394 [Gating] SW mode calibration
5620 16:44:26.656269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5621 16:44:26.659468 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5622 16:44:26.665723 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 16:44:26.669026 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 16:44:26.672322 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 16:44:26.679233 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 16:44:26.682740 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 16:44:26.685752 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5628 16:44:26.692295 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 0)
5629 16:44:26.695519 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
5630 16:44:26.699231 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 16:44:26.702608 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 16:44:26.709446 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 16:44:26.712689 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 16:44:26.715394 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 16:44:26.722484 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 16:44:26.725602 0 15 24 | B1->B0 | 2525 3030 | 0 0 | (1 1) (0 0)
5637 16:44:26.728975 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5638 16:44:26.735509 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 16:44:26.738738 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 16:44:26.742180 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 16:44:26.749441 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 16:44:26.751951 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 16:44:26.755325 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5644 16:44:26.761890 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5645 16:44:26.765806 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 16:44:26.768996 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 16:44:26.775582 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 16:44:26.778690 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 16:44:26.781967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 16:44:26.788732 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 16:44:26.791747 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 16:44:26.795281 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 16:44:26.802098 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 16:44:26.805444 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 16:44:26.808675 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 16:44:26.815115 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 16:44:26.818418 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 16:44:26.821475 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 16:44:26.828716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 16:44:26.831934 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 16:44:26.834921 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 16:44:26.838528 Total UI for P1: 0, mck2ui 16
5663 16:44:26.841516 best dqsien dly found for B0: ( 1, 2, 24)
5664 16:44:26.844937 Total UI for P1: 0, mck2ui 16
5665 16:44:26.848099 best dqsien dly found for B1: ( 1, 2, 24)
5666 16:44:26.851529 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5667 16:44:26.855005 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5668 16:44:26.855088
5669 16:44:26.858263 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5670 16:44:26.865012 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5671 16:44:26.865094 [Gating] SW calibration Done
5672 16:44:26.865161 ==
5673 16:44:26.868299 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 16:44:26.874674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 16:44:26.874746 ==
5676 16:44:26.874809 RX Vref Scan: 0
5677 16:44:26.874870
5678 16:44:26.878067 RX Vref 0 -> 0, step: 1
5679 16:44:26.878162
5680 16:44:26.881452 RX Delay -80 -> 252, step: 8
5681 16:44:26.884795 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5682 16:44:26.888007 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5683 16:44:26.891300 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5684 16:44:26.895102 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5685 16:44:26.901187 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5686 16:44:26.904487 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5687 16:44:26.908346 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5688 16:44:26.911532 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5689 16:44:26.914713 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5690 16:44:26.918064 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5691 16:44:26.924442 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5692 16:44:26.927604 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5693 16:44:26.931637 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5694 16:44:26.935058 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5695 16:44:26.938169 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5696 16:44:26.944436 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5697 16:44:26.944527 ==
5698 16:44:26.948167 Dram Type= 6, Freq= 0, CH_1, rank 0
5699 16:44:26.951442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5700 16:44:26.951538 ==
5701 16:44:26.951613 DQS Delay:
5702 16:44:26.954678 DQS0 = 0, DQS1 = 0
5703 16:44:26.954779 DQM Delay:
5704 16:44:26.957823 DQM0 = 102, DQM1 = 98
5705 16:44:26.957933 DQ Delay:
5706 16:44:26.961222 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5707 16:44:26.964534 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5708 16:44:26.968033 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5709 16:44:26.971414 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5710 16:44:26.971834
5711 16:44:26.972167
5712 16:44:26.972471 ==
5713 16:44:26.975205 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 16:44:26.981568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 16:44:26.981987 ==
5716 16:44:26.982318
5717 16:44:26.982624
5718 16:44:26.982915 TX Vref Scan disable
5719 16:44:26.985573 == TX Byte 0 ==
5720 16:44:26.988723 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5721 16:44:26.994834 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5722 16:44:26.995258 == TX Byte 1 ==
5723 16:44:26.998037 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5724 16:44:27.004900 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5725 16:44:27.005323 ==
5726 16:44:27.008671 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 16:44:27.011765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 16:44:27.012351 ==
5729 16:44:27.012899
5730 16:44:27.013330
5731 16:44:27.014924 TX Vref Scan disable
5732 16:44:27.015278 == TX Byte 0 ==
5733 16:44:27.021580 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5734 16:44:27.024656 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5735 16:44:27.025212 == TX Byte 1 ==
5736 16:44:27.031654 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5737 16:44:27.034881 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5738 16:44:27.035319
5739 16:44:27.035756 [DATLAT]
5740 16:44:27.038054 Freq=933, CH1 RK0
5741 16:44:27.038489
5742 16:44:27.038969 DATLAT Default: 0xd
5743 16:44:27.041283 0, 0xFFFF, sum = 0
5744 16:44:27.041861 1, 0xFFFF, sum = 0
5745 16:44:27.045037 2, 0xFFFF, sum = 0
5746 16:44:27.045577 3, 0xFFFF, sum = 0
5747 16:44:27.048120 4, 0xFFFF, sum = 0
5748 16:44:27.048566 5, 0xFFFF, sum = 0
5749 16:44:27.051460 6, 0xFFFF, sum = 0
5750 16:44:27.055160 7, 0xFFFF, sum = 0
5751 16:44:27.055665 8, 0xFFFF, sum = 0
5752 16:44:27.058023 9, 0xFFFF, sum = 0
5753 16:44:27.058526 10, 0x0, sum = 1
5754 16:44:27.059012 11, 0x0, sum = 2
5755 16:44:27.061131 12, 0x0, sum = 3
5756 16:44:27.061650 13, 0x0, sum = 4
5757 16:44:27.065102 best_step = 11
5758 16:44:27.065569
5759 16:44:27.066006 ==
5760 16:44:27.067714 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 16:44:27.071842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 16:44:27.072280 ==
5763 16:44:27.074434 RX Vref Scan: 1
5764 16:44:27.074867
5765 16:44:27.075200 RX Vref 0 -> 0, step: 1
5766 16:44:27.077611
5767 16:44:27.078060 RX Delay -45 -> 252, step: 4
5768 16:44:27.078396
5769 16:44:27.081350 Set Vref, RX VrefLevel [Byte0]: 55
5770 16:44:27.084596 [Byte1]: 48
5771 16:44:27.089239
5772 16:44:27.089720 Final RX Vref Byte 0 = 55 to rank0
5773 16:44:27.092452 Final RX Vref Byte 1 = 48 to rank0
5774 16:44:27.095752 Final RX Vref Byte 0 = 55 to rank1
5775 16:44:27.098899 Final RX Vref Byte 1 = 48 to rank1==
5776 16:44:27.102001 Dram Type= 6, Freq= 0, CH_1, rank 0
5777 16:44:27.108872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5778 16:44:27.109311 ==
5779 16:44:27.109700 DQS Delay:
5780 16:44:27.110023 DQS0 = 0, DQS1 = 0
5781 16:44:27.112116 DQM Delay:
5782 16:44:27.112580 DQM0 = 103, DQM1 = 99
5783 16:44:27.115657 DQ Delay:
5784 16:44:27.118801 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5785 16:44:27.122444 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =102
5786 16:44:27.125958 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =94
5787 16:44:27.129079 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5788 16:44:27.129660
5789 16:44:27.130009
5790 16:44:27.135896 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5791 16:44:27.139052 CH1 RK0: MR19=505, MR18=1B32
5792 16:44:27.145754 CH1_RK0: MR19=0x505, MR18=0x1B32, DQSOSC=406, MR23=63, INC=65, DEC=43
5793 16:44:27.146289
5794 16:44:27.149188 ----->DramcWriteLeveling(PI) begin...
5795 16:44:27.149872 ==
5796 16:44:27.152053 Dram Type= 6, Freq= 0, CH_1, rank 1
5797 16:44:27.155828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5798 16:44:27.156260 ==
5799 16:44:27.158826 Write leveling (Byte 0): 28 => 28
5800 16:44:27.162477 Write leveling (Byte 1): 28 => 28
5801 16:44:27.165607 DramcWriteLeveling(PI) end<-----
5802 16:44:27.166072
5803 16:44:27.166417 ==
5804 16:44:27.168772 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 16:44:27.172094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 16:44:27.175345 ==
5807 16:44:27.175771 [Gating] SW mode calibration
5808 16:44:27.185732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5809 16:44:27.188713 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5810 16:44:27.191805 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 16:44:27.198527 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 16:44:27.201804 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 16:44:27.205213 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 16:44:27.211502 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 16:44:27.214891 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5816 16:44:27.218764 0 14 24 | B1->B0 | 2c2c 3131 | 1 1 | (1 0) (1 0)
5817 16:44:27.224852 0 14 28 | B1->B0 | 2323 2525 | 0 0 | (1 0) (1 0)
5818 16:44:27.228059 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 16:44:27.231323 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 16:44:27.238423 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 16:44:27.241457 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 16:44:27.244990 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 16:44:27.252115 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5824 16:44:27.255362 0 15 24 | B1->B0 | 3333 2b2b | 0 0 | (0 0) (0 0)
5825 16:44:27.258340 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5826 16:44:27.264985 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 16:44:27.267971 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 16:44:27.271748 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 16:44:27.278078 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 16:44:27.281410 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 16:44:27.284586 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5832 16:44:27.291735 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5833 16:44:27.294894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 16:44:27.298082 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 16:44:27.304528 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 16:44:27.308492 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 16:44:27.311256 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 16:44:27.314423 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 16:44:27.321335 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 16:44:27.324620 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 16:44:27.327848 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 16:44:27.334682 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 16:44:27.337760 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 16:44:27.341076 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 16:44:27.347599 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 16:44:27.351498 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 16:44:27.354679 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 16:44:27.361311 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5849 16:44:27.364414 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5850 16:44:27.367721 Total UI for P1: 0, mck2ui 16
5851 16:44:27.370626 best dqsien dly found for B1: ( 1, 2, 24)
5852 16:44:27.374706 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 16:44:27.377667 Total UI for P1: 0, mck2ui 16
5854 16:44:27.380849 best dqsien dly found for B0: ( 1, 2, 26)
5855 16:44:27.384327 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5856 16:44:27.387502 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5857 16:44:27.387923
5858 16:44:27.393986 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5859 16:44:27.397626 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5860 16:44:27.400899 [Gating] SW calibration Done
5861 16:44:27.401345 ==
5862 16:44:27.404239 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 16:44:27.407305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 16:44:27.407968 ==
5865 16:44:27.408449 RX Vref Scan: 0
5866 16:44:27.408872
5867 16:44:27.410672 RX Vref 0 -> 0, step: 1
5868 16:44:27.411096
5869 16:44:27.413984 RX Delay -80 -> 252, step: 8
5870 16:44:27.416983 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5871 16:44:27.420252 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5872 16:44:27.427158 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5873 16:44:27.430174 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5874 16:44:27.433978 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5875 16:44:27.437064 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5876 16:44:27.440892 iDelay=208, Bit 6, Center 119 (32 ~ 207) 176
5877 16:44:27.443899 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5878 16:44:27.450982 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5879 16:44:27.453911 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5880 16:44:27.457187 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5881 16:44:27.460685 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5882 16:44:27.463877 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5883 16:44:27.470607 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5884 16:44:27.473693 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5885 16:44:27.477025 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5886 16:44:27.477380 ==
5887 16:44:27.480503 Dram Type= 6, Freq= 0, CH_1, rank 1
5888 16:44:27.483670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5889 16:44:27.483878 ==
5890 16:44:27.486828 DQS Delay:
5891 16:44:27.487071 DQS0 = 0, DQS1 = 0
5892 16:44:27.490016 DQM Delay:
5893 16:44:27.490289 DQM0 = 105, DQM1 = 98
5894 16:44:27.490482 DQ Delay:
5895 16:44:27.493296 DQ0 =107, DQ1 =103, DQ2 =95, DQ3 =99
5896 16:44:27.496929 DQ4 =99, DQ5 =119, DQ6 =119, DQ7 =103
5897 16:44:27.500056 DQ8 =83, DQ9 =91, DQ10 =99, DQ11 =91
5898 16:44:27.507009 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5899 16:44:27.507459
5900 16:44:27.507795
5901 16:44:27.508104 ==
5902 16:44:27.510234 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 16:44:27.513596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 16:44:27.514037 ==
5905 16:44:27.514377
5906 16:44:27.514684
5907 16:44:27.516666 TX Vref Scan disable
5908 16:44:27.517086 == TX Byte 0 ==
5909 16:44:27.523313 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5910 16:44:27.526550 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5911 16:44:27.526973 == TX Byte 1 ==
5912 16:44:27.533213 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 16:44:27.536934 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 16:44:27.537447 ==
5915 16:44:27.540099 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 16:44:27.543282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 16:44:27.543706 ==
5918 16:44:27.546315
5919 16:44:27.546736
5920 16:44:27.547070 TX Vref Scan disable
5921 16:44:27.549901 == TX Byte 0 ==
5922 16:44:27.553773 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5923 16:44:27.556681 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5924 16:44:27.559861 == TX Byte 1 ==
5925 16:44:27.563058 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 16:44:27.566743 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 16:44:27.569748
5928 16:44:27.570174 [DATLAT]
5929 16:44:27.570511 Freq=933, CH1 RK1
5930 16:44:27.570827
5931 16:44:27.573101 DATLAT Default: 0xb
5932 16:44:27.573605 0, 0xFFFF, sum = 0
5933 16:44:27.576431 1, 0xFFFF, sum = 0
5934 16:44:27.576862 2, 0xFFFF, sum = 0
5935 16:44:27.579850 3, 0xFFFF, sum = 0
5936 16:44:27.580277 4, 0xFFFF, sum = 0
5937 16:44:27.582948 5, 0xFFFF, sum = 0
5938 16:44:27.586636 6, 0xFFFF, sum = 0
5939 16:44:27.587062 7, 0xFFFF, sum = 0
5940 16:44:27.589575 8, 0xFFFF, sum = 0
5941 16:44:27.590005 9, 0xFFFF, sum = 0
5942 16:44:27.593577 10, 0x0, sum = 1
5943 16:44:27.594255 11, 0x0, sum = 2
5944 16:44:27.594727 12, 0x0, sum = 3
5945 16:44:27.596745 13, 0x0, sum = 4
5946 16:44:27.597178 best_step = 11
5947 16:44:27.597636
5948 16:44:27.600066 ==
5949 16:44:27.600493 Dram Type= 6, Freq= 0, CH_1, rank 1
5950 16:44:27.606642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5951 16:44:27.607268 ==
5952 16:44:27.607810 RX Vref Scan: 0
5953 16:44:27.608294
5954 16:44:27.609414 RX Vref 0 -> 0, step: 1
5955 16:44:27.609909
5956 16:44:27.613498 RX Delay -53 -> 252, step: 4
5957 16:44:27.616804 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5958 16:44:27.623486 iDelay=203, Bit 1, Center 100 (15 ~ 186) 172
5959 16:44:27.626168 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5960 16:44:27.629918 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5961 16:44:27.633626 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5962 16:44:27.637004 iDelay=203, Bit 5, Center 116 (31 ~ 202) 172
5963 16:44:27.642921 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5964 16:44:27.646883 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5965 16:44:27.649627 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5966 16:44:27.653029 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5967 16:44:27.656422 iDelay=203, Bit 10, Center 98 (11 ~ 186) 176
5968 16:44:27.660135 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5969 16:44:27.666764 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5970 16:44:27.669829 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5971 16:44:27.672946 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5972 16:44:27.676213 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5973 16:44:27.676781 ==
5974 16:44:27.680011 Dram Type= 6, Freq= 0, CH_1, rank 1
5975 16:44:27.686404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5976 16:44:27.686971 ==
5977 16:44:27.687346 DQS Delay:
5978 16:44:27.687694 DQS0 = 0, DQS1 = 0
5979 16:44:27.689727 DQM Delay:
5980 16:44:27.690215 DQM0 = 104, DQM1 = 100
5981 16:44:27.693381 DQ Delay:
5982 16:44:27.696389 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5983 16:44:27.699518 DQ4 =100, DQ5 =116, DQ6 =112, DQ7 =104
5984 16:44:27.702796 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =94
5985 16:44:27.705831 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5986 16:44:27.706251
5987 16:44:27.706581
5988 16:44:27.712768 [DQSOSCAuto] RK1, (LSB)MR18= 0x3004, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5989 16:44:27.716031 CH1 RK1: MR19=505, MR18=3004
5990 16:44:27.722592 CH1_RK1: MR19=0x505, MR18=0x3004, DQSOSC=406, MR23=63, INC=65, DEC=43
5991 16:44:27.726149 [RxdqsGatingPostProcess] freq 933
5992 16:44:27.732730 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5993 16:44:27.735823 best DQS0 dly(2T, 0.5T) = (0, 10)
5994 16:44:27.736265 best DQS1 dly(2T, 0.5T) = (0, 10)
5995 16:44:27.739679 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5996 16:44:27.742704 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5997 16:44:27.746020 best DQS0 dly(2T, 0.5T) = (0, 10)
5998 16:44:27.749684 best DQS1 dly(2T, 0.5T) = (0, 10)
5999 16:44:27.753055 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6000 16:44:27.756169 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6001 16:44:27.759756 Pre-setting of DQS Precalculation
6002 16:44:27.766172 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6003 16:44:27.773156 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6004 16:44:27.779479 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6005 16:44:27.780181
6006 16:44:27.780712
6007 16:44:27.783198 [Calibration Summary] 1866 Mbps
6008 16:44:27.783894 CH 0, Rank 0
6009 16:44:27.786519 SW Impedance : PASS
6010 16:44:27.786974 DUTY Scan : NO K
6011 16:44:27.790307 ZQ Calibration : PASS
6012 16:44:27.793543 Jitter Meter : NO K
6013 16:44:27.794142 CBT Training : PASS
6014 16:44:27.796363 Write leveling : PASS
6015 16:44:27.799475 RX DQS gating : PASS
6016 16:44:27.799947 RX DQ/DQS(RDDQC) : PASS
6017 16:44:27.803192 TX DQ/DQS : PASS
6018 16:44:27.806373 RX DATLAT : PASS
6019 16:44:27.806828 RX DQ/DQS(Engine): PASS
6020 16:44:27.809470 TX OE : NO K
6021 16:44:27.809943 All Pass.
6022 16:44:27.810313
6023 16:44:27.812830 CH 0, Rank 1
6024 16:44:27.813259 SW Impedance : PASS
6025 16:44:27.816457 DUTY Scan : NO K
6026 16:44:27.819632 ZQ Calibration : PASS
6027 16:44:27.820175 Jitter Meter : NO K
6028 16:44:27.822868 CBT Training : PASS
6029 16:44:27.826016 Write leveling : PASS
6030 16:44:27.826598 RX DQS gating : PASS
6031 16:44:27.829357 RX DQ/DQS(RDDQC) : PASS
6032 16:44:27.829846 TX DQ/DQS : PASS
6033 16:44:27.832948 RX DATLAT : PASS
6034 16:44:27.836405 RX DQ/DQS(Engine): PASS
6035 16:44:27.836834 TX OE : NO K
6036 16:44:27.839658 All Pass.
6037 16:44:27.840085
6038 16:44:27.840420 CH 1, Rank 0
6039 16:44:27.842871 SW Impedance : PASS
6040 16:44:27.843299 DUTY Scan : NO K
6041 16:44:27.846471 ZQ Calibration : PASS
6042 16:44:27.849682 Jitter Meter : NO K
6043 16:44:27.850112 CBT Training : PASS
6044 16:44:27.852847 Write leveling : PASS
6045 16:44:27.856254 RX DQS gating : PASS
6046 16:44:27.856682 RX DQ/DQS(RDDQC) : PASS
6047 16:44:27.859518 TX DQ/DQS : PASS
6048 16:44:27.862900 RX DATLAT : PASS
6049 16:44:27.863431 RX DQ/DQS(Engine): PASS
6050 16:44:27.866155 TX OE : NO K
6051 16:44:27.866588 All Pass.
6052 16:44:27.866926
6053 16:44:27.869460 CH 1, Rank 1
6054 16:44:27.870045 SW Impedance : PASS
6055 16:44:27.872724 DUTY Scan : NO K
6056 16:44:27.876353 ZQ Calibration : PASS
6057 16:44:27.876894 Jitter Meter : NO K
6058 16:44:27.880059 CBT Training : PASS
6059 16:44:27.880615 Write leveling : PASS
6060 16:44:27.882972 RX DQS gating : PASS
6061 16:44:27.886069 RX DQ/DQS(RDDQC) : PASS
6062 16:44:27.886496 TX DQ/DQS : PASS
6063 16:44:27.890098 RX DATLAT : PASS
6064 16:44:27.893138 RX DQ/DQS(Engine): PASS
6065 16:44:27.893581 TX OE : NO K
6066 16:44:27.896527 All Pass.
6067 16:44:27.896954
6068 16:44:27.897292 DramC Write-DBI off
6069 16:44:27.900238 PER_BANK_REFRESH: Hybrid Mode
6070 16:44:27.900785 TX_TRACKING: ON
6071 16:44:27.909433 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6072 16:44:27.913408 [FAST_K] Save calibration result to emmc
6073 16:44:27.916611 dramc_set_vcore_voltage set vcore to 650000
6074 16:44:27.919587 Read voltage for 400, 6
6075 16:44:27.920014 Vio18 = 0
6076 16:44:27.922838 Vcore = 650000
6077 16:44:27.923265 Vdram = 0
6078 16:44:27.923605 Vddq = 0
6079 16:44:27.923919 Vmddr = 0
6080 16:44:27.929419 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6081 16:44:27.936696 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6082 16:44:27.937222 MEM_TYPE=3, freq_sel=20
6083 16:44:27.940402 sv_algorithm_assistance_LP4_800
6084 16:44:27.943344 ============ PULL DRAM RESETB DOWN ============
6085 16:44:27.950122 ========== PULL DRAM RESETB DOWN end =========
6086 16:44:27.953143 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6087 16:44:27.956232 ===================================
6088 16:44:27.959520 LPDDR4 DRAM CONFIGURATION
6089 16:44:27.962827 ===================================
6090 16:44:27.963259 EX_ROW_EN[0] = 0x0
6091 16:44:27.966728 EX_ROW_EN[1] = 0x0
6092 16:44:27.967194 LP4Y_EN = 0x0
6093 16:44:27.970009 WORK_FSP = 0x0
6094 16:44:27.970437 WL = 0x2
6095 16:44:27.973171 RL = 0x2
6096 16:44:27.973742 BL = 0x2
6097 16:44:27.976497 RPST = 0x0
6098 16:44:27.979342 RD_PRE = 0x0
6099 16:44:27.979772 WR_PRE = 0x1
6100 16:44:27.983000 WR_PST = 0x0
6101 16:44:27.983564 DBI_WR = 0x0
6102 16:44:27.986177 DBI_RD = 0x0
6103 16:44:27.986606 OTF = 0x1
6104 16:44:27.989828 ===================================
6105 16:44:27.992978 ===================================
6106 16:44:27.993579 ANA top config
6107 16:44:27.995986 ===================================
6108 16:44:27.999667 DLL_ASYNC_EN = 0
6109 16:44:28.002688 ALL_SLAVE_EN = 1
6110 16:44:28.005898 NEW_RANK_MODE = 1
6111 16:44:28.009418 DLL_IDLE_MODE = 1
6112 16:44:28.009958 LP45_APHY_COMB_EN = 1
6113 16:44:28.013151 TX_ODT_DIS = 1
6114 16:44:28.016124 NEW_8X_MODE = 1
6115 16:44:28.019773 ===================================
6116 16:44:28.022915 ===================================
6117 16:44:28.026191 data_rate = 800
6118 16:44:28.029301 CKR = 1
6119 16:44:28.029883 DQ_P2S_RATIO = 4
6120 16:44:28.033116 ===================================
6121 16:44:28.035965 CA_P2S_RATIO = 4
6122 16:44:28.040226 DQ_CA_OPEN = 0
6123 16:44:28.043101 DQ_SEMI_OPEN = 1
6124 16:44:28.046447 CA_SEMI_OPEN = 1
6125 16:44:28.049932 CA_FULL_RATE = 0
6126 16:44:28.050506 DQ_CKDIV4_EN = 0
6127 16:44:28.052837 CA_CKDIV4_EN = 1
6128 16:44:28.056446 CA_PREDIV_EN = 0
6129 16:44:28.059324 PH8_DLY = 0
6130 16:44:28.063251 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6131 16:44:28.065950 DQ_AAMCK_DIV = 0
6132 16:44:28.066373 CA_AAMCK_DIV = 0
6133 16:44:28.070007 CA_ADMCK_DIV = 4
6134 16:44:28.073127 DQ_TRACK_CA_EN = 0
6135 16:44:28.076861 CA_PICK = 800
6136 16:44:28.079936 CA_MCKIO = 400
6137 16:44:28.083125 MCKIO_SEMI = 400
6138 16:44:28.086204 PLL_FREQ = 3016
6139 16:44:28.086762 DQ_UI_PI_RATIO = 32
6140 16:44:28.089445 CA_UI_PI_RATIO = 32
6141 16:44:28.092927 ===================================
6142 16:44:28.096160 ===================================
6143 16:44:28.099046 memory_type:LPDDR4
6144 16:44:28.102822 GP_NUM : 10
6145 16:44:28.103243 SRAM_EN : 1
6146 16:44:28.105960 MD32_EN : 0
6147 16:44:28.109030 ===================================
6148 16:44:28.113025 [ANA_INIT] >>>>>>>>>>>>>>
6149 16:44:28.113498 <<<<<< [CONFIGURE PHASE]: ANA_TX
6150 16:44:28.115937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6151 16:44:28.119295 ===================================
6152 16:44:28.122475 data_rate = 800,PCW = 0X7400
6153 16:44:28.125975 ===================================
6154 16:44:28.129013 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6155 16:44:28.135921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 16:44:28.146284 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6157 16:44:28.152340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6158 16:44:28.156311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6159 16:44:28.159547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6160 16:44:28.159967 [ANA_INIT] flow start
6161 16:44:28.162734 [ANA_INIT] PLL >>>>>>>>
6162 16:44:28.165971 [ANA_INIT] PLL <<<<<<<<
6163 16:44:28.166416 [ANA_INIT] MIDPI >>>>>>>>
6164 16:44:28.169322 [ANA_INIT] MIDPI <<<<<<<<
6165 16:44:28.172521 [ANA_INIT] DLL >>>>>>>>
6166 16:44:28.172941 [ANA_INIT] flow end
6167 16:44:28.179264 ============ LP4 DIFF to SE enter ============
6168 16:44:28.182543 ============ LP4 DIFF to SE exit ============
6169 16:44:28.185733 [ANA_INIT] <<<<<<<<<<<<<
6170 16:44:28.188971 [Flow] Enable top DCM control >>>>>
6171 16:44:28.192819 [Flow] Enable top DCM control <<<<<
6172 16:44:28.193240 Enable DLL master slave shuffle
6173 16:44:28.198766 ==============================================================
6174 16:44:28.202594 Gating Mode config
6175 16:44:28.205701 ==============================================================
6176 16:44:28.209293 Config description:
6177 16:44:28.219542 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6178 16:44:28.225870 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6179 16:44:28.228969 SELPH_MODE 0: By rank 1: By Phase
6180 16:44:28.235867 ==============================================================
6181 16:44:28.238964 GAT_TRACK_EN = 0
6182 16:44:28.242851 RX_GATING_MODE = 2
6183 16:44:28.245905 RX_GATING_TRACK_MODE = 2
6184 16:44:28.246370 SELPH_MODE = 1
6185 16:44:28.248946 PICG_EARLY_EN = 1
6186 16:44:28.252337 VALID_LAT_VALUE = 1
6187 16:44:28.258949 ==============================================================
6188 16:44:28.262888 Enter into Gating configuration >>>>
6189 16:44:28.266092 Exit from Gating configuration <<<<
6190 16:44:28.268769 Enter into DVFS_PRE_config >>>>>
6191 16:44:28.278459 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6192 16:44:28.281850 Exit from DVFS_PRE_config <<<<<
6193 16:44:28.285189 Enter into PICG configuration >>>>
6194 16:44:28.288541 Exit from PICG configuration <<<<
6195 16:44:28.291949 [RX_INPUT] configuration >>>>>
6196 16:44:28.295142 [RX_INPUT] configuration <<<<<
6197 16:44:28.298986 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6198 16:44:28.305422 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6199 16:44:28.311653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6200 16:44:28.318649 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6201 16:44:28.321941 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6202 16:44:28.328512 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6203 16:44:28.331676 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6204 16:44:28.338687 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6205 16:44:28.341864 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6206 16:44:28.345074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6207 16:44:28.348341 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6208 16:44:28.355487 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6209 16:44:28.358527 ===================================
6210 16:44:28.361440 LPDDR4 DRAM CONFIGURATION
6211 16:44:28.365373 ===================================
6212 16:44:28.365481 EX_ROW_EN[0] = 0x0
6213 16:44:28.368104 EX_ROW_EN[1] = 0x0
6214 16:44:28.368233 LP4Y_EN = 0x0
6215 16:44:28.371287 WORK_FSP = 0x0
6216 16:44:28.371363 WL = 0x2
6217 16:44:28.374832 RL = 0x2
6218 16:44:28.374938 BL = 0x2
6219 16:44:28.378201 RPST = 0x0
6220 16:44:28.378303 RD_PRE = 0x0
6221 16:44:28.381623 WR_PRE = 0x1
6222 16:44:28.381738 WR_PST = 0x0
6223 16:44:28.384780 DBI_WR = 0x0
6224 16:44:28.384872 DBI_RD = 0x0
6225 16:44:28.388083 OTF = 0x1
6226 16:44:28.391367 ===================================
6227 16:44:28.394572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6228 16:44:28.398543 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6229 16:44:28.405035 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 16:44:28.408402 ===================================
6231 16:44:28.408487 LPDDR4 DRAM CONFIGURATION
6232 16:44:28.411243 ===================================
6233 16:44:28.415106 EX_ROW_EN[0] = 0x10
6234 16:44:28.418262 EX_ROW_EN[1] = 0x0
6235 16:44:28.418339 LP4Y_EN = 0x0
6236 16:44:28.421409 WORK_FSP = 0x0
6237 16:44:28.421479 WL = 0x2
6238 16:44:28.424528 RL = 0x2
6239 16:44:28.424598 BL = 0x2
6240 16:44:28.427649 RPST = 0x0
6241 16:44:28.427724 RD_PRE = 0x0
6242 16:44:28.431192 WR_PRE = 0x1
6243 16:44:28.431264 WR_PST = 0x0
6244 16:44:28.434397 DBI_WR = 0x0
6245 16:44:28.434468 DBI_RD = 0x0
6246 16:44:28.438293 OTF = 0x1
6247 16:44:28.441360 ===================================
6248 16:44:28.448109 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6249 16:44:28.451169 nWR fixed to 30
6250 16:44:28.454180 [ModeRegInit_LP4] CH0 RK0
6251 16:44:28.454264 [ModeRegInit_LP4] CH0 RK1
6252 16:44:28.457850 [ModeRegInit_LP4] CH1 RK0
6253 16:44:28.460934 [ModeRegInit_LP4] CH1 RK1
6254 16:44:28.461029 match AC timing 19
6255 16:44:28.468192 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6256 16:44:28.470939 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6257 16:44:28.474353 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6258 16:44:28.481039 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6259 16:44:28.484305 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6260 16:44:28.484387 ==
6261 16:44:28.487493 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 16:44:28.490923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 16:44:28.491001 ==
6264 16:44:28.497591 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6265 16:44:28.504430 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6266 16:44:28.507745 [CA 0] Center 36 (8~64) winsize 57
6267 16:44:28.511097 [CA 1] Center 36 (8~64) winsize 57
6268 16:44:28.511197 [CA 2] Center 36 (8~64) winsize 57
6269 16:44:28.514472 [CA 3] Center 36 (8~64) winsize 57
6270 16:44:28.517904 [CA 4] Center 36 (8~64) winsize 57
6271 16:44:28.521058 [CA 5] Center 36 (8~64) winsize 57
6272 16:44:28.521167
6273 16:44:28.524210 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6274 16:44:28.524313
6275 16:44:28.530723 [CATrainingPosCal] consider 1 rank data
6276 16:44:28.530807 u2DelayCellTimex100 = 270/100 ps
6277 16:44:28.537848 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 16:44:28.541028 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 16:44:28.544124 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 16:44:28.547595 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 16:44:28.550667 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 16:44:28.553845 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 16:44:28.553963
6284 16:44:28.557449 CA PerBit enable=1, Macro0, CA PI delay=36
6285 16:44:28.557571
6286 16:44:28.560634 [CBTSetCACLKResult] CA Dly = 36
6287 16:44:28.564479 CS Dly: 1 (0~32)
6288 16:44:28.564590 ==
6289 16:44:28.567441 Dram Type= 6, Freq= 0, CH_0, rank 1
6290 16:44:28.570422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 16:44:28.570534 ==
6292 16:44:28.577056 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6293 16:44:28.580436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6294 16:44:28.583941 [CA 0] Center 36 (8~64) winsize 57
6295 16:44:28.587087 [CA 1] Center 36 (8~64) winsize 57
6296 16:44:28.590382 [CA 2] Center 36 (8~64) winsize 57
6297 16:44:28.593638 [CA 3] Center 36 (8~64) winsize 57
6298 16:44:28.596921 [CA 4] Center 36 (8~64) winsize 57
6299 16:44:28.600121 [CA 5] Center 36 (8~64) winsize 57
6300 16:44:28.600207
6301 16:44:28.604012 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6302 16:44:28.604115
6303 16:44:28.607233 [CATrainingPosCal] consider 2 rank data
6304 16:44:28.610499 u2DelayCellTimex100 = 270/100 ps
6305 16:44:28.613810 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 16:44:28.616993 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 16:44:28.623660 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 16:44:28.626902 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 16:44:28.630074 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 16:44:28.633743 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 16:44:28.633854
6312 16:44:28.636892 CA PerBit enable=1, Macro0, CA PI delay=36
6313 16:44:28.636976
6314 16:44:28.640050 [CBTSetCACLKResult] CA Dly = 36
6315 16:44:28.640165 CS Dly: 1 (0~32)
6316 16:44:28.640263
6317 16:44:28.643913 ----->DramcWriteLeveling(PI) begin...
6318 16:44:28.646958 ==
6319 16:44:28.647048 Dram Type= 6, Freq= 0, CH_0, rank 0
6320 16:44:28.653505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6321 16:44:28.653627 ==
6322 16:44:28.656807 Write leveling (Byte 0): 40 => 8
6323 16:44:28.660087 Write leveling (Byte 1): 40 => 8
6324 16:44:28.660164 DramcWriteLeveling(PI) end<-----
6325 16:44:28.663857
6326 16:44:28.663940 ==
6327 16:44:28.666938 Dram Type= 6, Freq= 0, CH_0, rank 0
6328 16:44:28.670371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6329 16:44:28.670478 ==
6330 16:44:28.673450 [Gating] SW mode calibration
6331 16:44:28.680106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6332 16:44:28.683168 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6333 16:44:28.689940 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 16:44:28.693282 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6335 16:44:28.696440 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 16:44:28.703153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6337 16:44:28.706421 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 16:44:28.709805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 16:44:28.716312 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 16:44:28.719643 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6341 16:44:28.723656 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 16:44:28.726871 Total UI for P1: 0, mck2ui 16
6343 16:44:28.730157 best dqsien dly found for B0: ( 0, 14, 24)
6344 16:44:28.733468 Total UI for P1: 0, mck2ui 16
6345 16:44:28.736622 best dqsien dly found for B1: ( 0, 14, 24)
6346 16:44:28.739723 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6347 16:44:28.742988 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6348 16:44:28.743072
6349 16:44:28.750145 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 16:44:28.753151 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6351 16:44:28.756276 [Gating] SW calibration Done
6352 16:44:28.756360 ==
6353 16:44:28.759965 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 16:44:28.763263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 16:44:28.763347 ==
6356 16:44:28.763431 RX Vref Scan: 0
6357 16:44:28.763509
6358 16:44:28.766530 RX Vref 0 -> 0, step: 1
6359 16:44:28.766613
6360 16:44:28.769544 RX Delay -410 -> 252, step: 16
6361 16:44:28.773281 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6362 16:44:28.776396 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6363 16:44:28.783075 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6364 16:44:28.786744 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6365 16:44:28.789686 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6366 16:44:28.793230 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6367 16:44:28.799676 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6368 16:44:28.803130 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6369 16:44:28.806503 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6370 16:44:28.809583 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6371 16:44:28.816486 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6372 16:44:28.820078 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6373 16:44:28.822781 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6374 16:44:28.826099 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6375 16:44:28.832991 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6376 16:44:28.836233 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6377 16:44:28.836313 ==
6378 16:44:28.839680 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 16:44:28.842842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 16:44:28.842922 ==
6381 16:44:28.846180 DQS Delay:
6382 16:44:28.846259 DQS0 = 27, DQS1 = 35
6383 16:44:28.849987 DQM Delay:
6384 16:44:28.850098 DQM0 = 10, DQM1 = 12
6385 16:44:28.850161 DQ Delay:
6386 16:44:28.852882 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6387 16:44:28.856127 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6388 16:44:28.859898 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6389 16:44:28.863176 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6390 16:44:28.863272
6391 16:44:28.863366
6392 16:44:28.863425 ==
6393 16:44:28.866393 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 16:44:28.872713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 16:44:28.872791 ==
6396 16:44:28.872867
6397 16:44:28.872959
6398 16:44:28.873044 TX Vref Scan disable
6399 16:44:28.876098 == TX Byte 0 ==
6400 16:44:28.879324 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 16:44:28.882583 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 16:44:28.886218 == TX Byte 1 ==
6403 16:44:28.889469 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 16:44:28.892669 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 16:44:28.892748 ==
6406 16:44:28.896439 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 16:44:28.902927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 16:44:28.903017 ==
6409 16:44:28.903122
6410 16:44:28.903212
6411 16:44:28.903297 TX Vref Scan disable
6412 16:44:28.906351 == TX Byte 0 ==
6413 16:44:28.909507 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 16:44:28.912786 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 16:44:28.916053 == TX Byte 1 ==
6416 16:44:28.919408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 16:44:28.922892 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 16:44:28.922973
6419 16:44:28.926175 [DATLAT]
6420 16:44:28.926259 Freq=400, CH0 RK0
6421 16:44:28.926323
6422 16:44:28.929406 DATLAT Default: 0xf
6423 16:44:28.929516 0, 0xFFFF, sum = 0
6424 16:44:28.932777 1, 0xFFFF, sum = 0
6425 16:44:28.932873 2, 0xFFFF, sum = 0
6426 16:44:28.936011 3, 0xFFFF, sum = 0
6427 16:44:28.936104 4, 0xFFFF, sum = 0
6428 16:44:28.939365 5, 0xFFFF, sum = 0
6429 16:44:28.939454 6, 0xFFFF, sum = 0
6430 16:44:28.942709 7, 0xFFFF, sum = 0
6431 16:44:28.942795 8, 0xFFFF, sum = 0
6432 16:44:28.945870 9, 0xFFFF, sum = 0
6433 16:44:28.945968 10, 0xFFFF, sum = 0
6434 16:44:28.949162 11, 0xFFFF, sum = 0
6435 16:44:28.952980 12, 0xFFFF, sum = 0
6436 16:44:28.953077 13, 0x0, sum = 1
6437 16:44:28.956054 14, 0x0, sum = 2
6438 16:44:28.956152 15, 0x0, sum = 3
6439 16:44:28.956220 16, 0x0, sum = 4
6440 16:44:28.959236 best_step = 14
6441 16:44:28.959332
6442 16:44:28.959408 ==
6443 16:44:28.963034 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 16:44:28.966086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 16:44:28.966171 ==
6446 16:44:28.969324 RX Vref Scan: 1
6447 16:44:28.969404
6448 16:44:28.969495 RX Vref 0 -> 0, step: 1
6449 16:44:28.969582
6450 16:44:28.972578 RX Delay -311 -> 252, step: 8
6451 16:44:28.972668
6452 16:44:28.975775 Set Vref, RX VrefLevel [Byte0]: 60
6453 16:44:28.979351 [Byte1]: 44
6454 16:44:28.984434
6455 16:44:28.984534 Final RX Vref Byte 0 = 60 to rank0
6456 16:44:28.987665 Final RX Vref Byte 1 = 44 to rank0
6457 16:44:28.990955 Final RX Vref Byte 0 = 60 to rank1
6458 16:44:28.994065 Final RX Vref Byte 1 = 44 to rank1==
6459 16:44:28.997764 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 16:44:29.004289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 16:44:29.004415 ==
6462 16:44:29.004511 DQS Delay:
6463 16:44:29.007471 DQS0 = 24, DQS1 = 36
6464 16:44:29.007674 DQM Delay:
6465 16:44:29.007853 DQM0 = 7, DQM1 = 13
6466 16:44:29.010685 DQ Delay:
6467 16:44:29.014110 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6468 16:44:29.014281 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6469 16:44:29.017283 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6470 16:44:29.020734 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6471 16:44:29.020923
6472 16:44:29.021166
6473 16:44:29.030759 [DQSOSCAuto] RK0, (LSB)MR18= 0xd0bd, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6474 16:44:29.034197 CH0 RK0: MR19=C0C, MR18=D0BD
6475 16:44:29.041054 CH0_RK0: MR19=0xC0C, MR18=0xD0BD, DQSOSC=384, MR23=63, INC=400, DEC=267
6476 16:44:29.041484 ==
6477 16:44:29.044493 Dram Type= 6, Freq= 0, CH_0, rank 1
6478 16:44:29.047599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6479 16:44:29.048024 ==
6480 16:44:29.050799 [Gating] SW mode calibration
6481 16:44:29.057449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6482 16:44:29.060897 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6483 16:44:29.067339 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 16:44:29.070468 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6485 16:44:29.074355 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 16:44:29.080475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6487 16:44:29.083656 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 16:44:29.087439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 16:44:29.094091 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 16:44:29.097541 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6491 16:44:29.100660 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 16:44:29.103571 Total UI for P1: 0, mck2ui 16
6493 16:44:29.107362 best dqsien dly found for B0: ( 0, 14, 24)
6494 16:44:29.110449 Total UI for P1: 0, mck2ui 16
6495 16:44:29.114296 best dqsien dly found for B1: ( 0, 14, 24)
6496 16:44:29.117386 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6497 16:44:29.120175 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6498 16:44:29.123930
6499 16:44:29.127096 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 16:44:29.130453 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6501 16:44:29.133635 [Gating] SW calibration Done
6502 16:44:29.133931 ==
6503 16:44:29.136901 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 16:44:29.140199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 16:44:29.140606 ==
6506 16:44:29.140962 RX Vref Scan: 0
6507 16:44:29.141316
6508 16:44:29.143767 RX Vref 0 -> 0, step: 1
6509 16:44:29.144176
6510 16:44:29.146914 RX Delay -410 -> 252, step: 16
6511 16:44:29.150191 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6512 16:44:29.157141 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6513 16:44:29.160496 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6514 16:44:29.163622 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6515 16:44:29.166885 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6516 16:44:29.173873 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6517 16:44:29.176793 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6518 16:44:29.180075 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6519 16:44:29.183845 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6520 16:44:29.187111 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6521 16:44:29.193928 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6522 16:44:29.197486 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6523 16:44:29.200798 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6524 16:44:29.207256 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6525 16:44:29.210323 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6526 16:44:29.213550 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6527 16:44:29.213978 ==
6528 16:44:29.217174 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 16:44:29.220185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 16:44:29.220614 ==
6531 16:44:29.223694 DQS Delay:
6532 16:44:29.224309 DQS0 = 19, DQS1 = 35
6533 16:44:29.226789 DQM Delay:
6534 16:44:29.227383 DQM0 = 5, DQM1 = 12
6535 16:44:29.230369 DQ Delay:
6536 16:44:29.231040 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6537 16:44:29.233648 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6538 16:44:29.236900 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6539 16:44:29.240269 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6540 16:44:29.240944
6541 16:44:29.241479
6542 16:44:29.241974 ==
6543 16:44:29.243563 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 16:44:29.250823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 16:44:29.251455 ==
6546 16:44:29.251999
6547 16:44:29.252496
6548 16:44:29.252998 TX Vref Scan disable
6549 16:44:29.254010 == TX Byte 0 ==
6550 16:44:29.257280 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6551 16:44:29.260229 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6552 16:44:29.263405 == TX Byte 1 ==
6553 16:44:29.267207 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6554 16:44:29.270032 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6555 16:44:29.270504 ==
6556 16:44:29.273847 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 16:44:29.280206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 16:44:29.280677 ==
6559 16:44:29.281042
6560 16:44:29.281357
6561 16:44:29.281716 TX Vref Scan disable
6562 16:44:29.283364 == TX Byte 0 ==
6563 16:44:29.286986 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6564 16:44:29.290507 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6565 16:44:29.293575 == TX Byte 1 ==
6566 16:44:29.296503 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6567 16:44:29.300215 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6568 16:44:29.300811
6569 16:44:29.303237 [DATLAT]
6570 16:44:29.303755 Freq=400, CH0 RK1
6571 16:44:29.304233
6572 16:44:29.306426 DATLAT Default: 0xe
6573 16:44:29.306933 0, 0xFFFF, sum = 0
6574 16:44:29.310192 1, 0xFFFF, sum = 0
6575 16:44:29.310689 2, 0xFFFF, sum = 0
6576 16:44:29.313500 3, 0xFFFF, sum = 0
6577 16:44:29.313995 4, 0xFFFF, sum = 0
6578 16:44:29.316616 5, 0xFFFF, sum = 0
6579 16:44:29.317243 6, 0xFFFF, sum = 0
6580 16:44:29.319939 7, 0xFFFF, sum = 0
6581 16:44:29.320525 8, 0xFFFF, sum = 0
6582 16:44:29.323192 9, 0xFFFF, sum = 0
6583 16:44:29.323623 10, 0xFFFF, sum = 0
6584 16:44:29.326952 11, 0xFFFF, sum = 0
6585 16:44:29.329976 12, 0xFFFF, sum = 0
6586 16:44:29.330404 13, 0x0, sum = 1
6587 16:44:29.330748 14, 0x0, sum = 2
6588 16:44:29.333486 15, 0x0, sum = 3
6589 16:44:29.333952 16, 0x0, sum = 4
6590 16:44:29.336586 best_step = 14
6591 16:44:29.337008
6592 16:44:29.337339 ==
6593 16:44:29.340331 Dram Type= 6, Freq= 0, CH_0, rank 1
6594 16:44:29.343559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6595 16:44:29.343986 ==
6596 16:44:29.347016 RX Vref Scan: 0
6597 16:44:29.347435
6598 16:44:29.347767 RX Vref 0 -> 0, step: 1
6599 16:44:29.348077
6600 16:44:29.350097 RX Delay -311 -> 252, step: 8
6601 16:44:29.357999 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6602 16:44:29.361385 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6603 16:44:29.364599 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6604 16:44:29.368232 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6605 16:44:29.374627 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6606 16:44:29.377774 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6607 16:44:29.381338 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6608 16:44:29.384444 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6609 16:44:29.391579 iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432
6610 16:44:29.394770 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6611 16:44:29.397810 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6612 16:44:29.401641 iDelay=217, Bit 11, Center -32 (-247 ~ 184) 432
6613 16:44:29.408017 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6614 16:44:29.411131 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6615 16:44:29.414319 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6616 16:44:29.421318 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6617 16:44:29.421891 ==
6618 16:44:29.424498 Dram Type= 6, Freq= 0, CH_0, rank 1
6619 16:44:29.427727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 16:44:29.428156 ==
6621 16:44:29.428493 DQS Delay:
6622 16:44:29.430956 DQS0 = 24, DQS1 = 36
6623 16:44:29.431407 DQM Delay:
6624 16:44:29.434819 DQM0 = 9, DQM1 = 12
6625 16:44:29.435241 DQ Delay:
6626 16:44:29.437833 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6627 16:44:29.441704 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6628 16:44:29.444626 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6629 16:44:29.447656 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6630 16:44:29.448171
6631 16:44:29.448586
6632 16:44:29.454208 [DQSOSCAuto] RK1, (LSB)MR18= 0xc060, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6633 16:44:29.457334 CH0 RK1: MR19=C0C, MR18=C060
6634 16:44:29.464605 CH0_RK1: MR19=0xC0C, MR18=0xC060, DQSOSC=386, MR23=63, INC=396, DEC=264
6635 16:44:29.467780 [RxdqsGatingPostProcess] freq 400
6636 16:44:29.470944 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6637 16:44:29.474740 best DQS0 dly(2T, 0.5T) = (0, 10)
6638 16:44:29.477424 best DQS1 dly(2T, 0.5T) = (0, 10)
6639 16:44:29.481400 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6640 16:44:29.484683 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6641 16:44:29.487761 best DQS0 dly(2T, 0.5T) = (0, 10)
6642 16:44:29.491082 best DQS1 dly(2T, 0.5T) = (0, 10)
6643 16:44:29.494352 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6644 16:44:29.497572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6645 16:44:29.500675 Pre-setting of DQS Precalculation
6646 16:44:29.503979 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6647 16:44:29.507132 ==
6648 16:44:29.510973 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 16:44:29.513961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 16:44:29.514389 ==
6651 16:44:29.520364 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6652 16:44:29.523955 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6653 16:44:29.527488 [CA 0] Center 36 (8~64) winsize 57
6654 16:44:29.530507 [CA 1] Center 36 (8~64) winsize 57
6655 16:44:29.533754 [CA 2] Center 36 (8~64) winsize 57
6656 16:44:29.537037 [CA 3] Center 36 (8~64) winsize 57
6657 16:44:29.540264 [CA 4] Center 36 (8~64) winsize 57
6658 16:44:29.543552 [CA 5] Center 36 (8~64) winsize 57
6659 16:44:29.543989
6660 16:44:29.546824 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6661 16:44:29.547279
6662 16:44:29.550338 [CATrainingPosCal] consider 1 rank data
6663 16:44:29.553430 u2DelayCellTimex100 = 270/100 ps
6664 16:44:29.557031 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 16:44:29.560197 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 16:44:29.563513 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 16:44:29.567242 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 16:44:29.573721 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 16:44:29.577467 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 16:44:29.577933
6671 16:44:29.580484 CA PerBit enable=1, Macro0, CA PI delay=36
6672 16:44:29.580906
6673 16:44:29.583758 [CBTSetCACLKResult] CA Dly = 36
6674 16:44:29.584183 CS Dly: 1 (0~32)
6675 16:44:29.584519 ==
6676 16:44:29.586952 Dram Type= 6, Freq= 0, CH_1, rank 1
6677 16:44:29.593603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 16:44:29.594033 ==
6679 16:44:29.596849 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6680 16:44:29.603809 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6681 16:44:29.606855 [CA 0] Center 36 (8~64) winsize 57
6682 16:44:29.610150 [CA 1] Center 36 (8~64) winsize 57
6683 16:44:29.613504 [CA 2] Center 36 (8~64) winsize 57
6684 16:44:29.617363 [CA 3] Center 36 (8~64) winsize 57
6685 16:44:29.620443 [CA 4] Center 36 (8~64) winsize 57
6686 16:44:29.623710 [CA 5] Center 36 (8~64) winsize 57
6687 16:44:29.624199
6688 16:44:29.627292 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6689 16:44:29.627778
6690 16:44:29.630495 [CATrainingPosCal] consider 2 rank data
6691 16:44:29.634177 u2DelayCellTimex100 = 270/100 ps
6692 16:44:29.637333 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 16:44:29.640440 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 16:44:29.643579 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 16:44:29.647006 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 16:44:29.650328 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 16:44:29.653543 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 16:44:29.653980
6699 16:44:29.657158 CA PerBit enable=1, Macro0, CA PI delay=36
6700 16:44:29.660240
6701 16:44:29.660665 [CBTSetCACLKResult] CA Dly = 36
6702 16:44:29.663419 CS Dly: 1 (0~32)
6703 16:44:29.663843
6704 16:44:29.667242 ----->DramcWriteLeveling(PI) begin...
6705 16:44:29.667675 ==
6706 16:44:29.670621 Dram Type= 6, Freq= 0, CH_1, rank 0
6707 16:44:29.673888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6708 16:44:29.674332 ==
6709 16:44:29.677194 Write leveling (Byte 0): 40 => 8
6710 16:44:29.680447 Write leveling (Byte 1): 40 => 8
6711 16:44:29.683363 DramcWriteLeveling(PI) end<-----
6712 16:44:29.683998
6713 16:44:29.684702 ==
6714 16:44:29.687164 Dram Type= 6, Freq= 0, CH_1, rank 0
6715 16:44:29.690457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6716 16:44:29.691161 ==
6717 16:44:29.693811 [Gating] SW mode calibration
6718 16:44:29.700244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6719 16:44:29.706859 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6720 16:44:29.710514 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 16:44:29.716962 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6722 16:44:29.720200 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 16:44:29.723451 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6724 16:44:29.727102 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 16:44:29.734070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 16:44:29.736951 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 16:44:29.740075 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6728 16:44:29.746832 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 16:44:29.750131 Total UI for P1: 0, mck2ui 16
6730 16:44:29.753460 best dqsien dly found for B0: ( 0, 14, 24)
6731 16:44:29.756669 Total UI for P1: 0, mck2ui 16
6732 16:44:29.759988 best dqsien dly found for B1: ( 0, 14, 24)
6733 16:44:29.763736 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6734 16:44:29.766340 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6735 16:44:29.766421
6736 16:44:29.770016 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 16:44:29.773032 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6738 16:44:29.776582 [Gating] SW calibration Done
6739 16:44:29.776663 ==
6740 16:44:29.779913 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 16:44:29.783177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 16:44:29.783297 ==
6743 16:44:29.786450 RX Vref Scan: 0
6744 16:44:29.786544
6745 16:44:29.789781 RX Vref 0 -> 0, step: 1
6746 16:44:29.789883
6747 16:44:29.789962 RX Delay -410 -> 252, step: 16
6748 16:44:29.796218 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6749 16:44:29.799442 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6750 16:44:29.803341 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6751 16:44:29.806295 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6752 16:44:29.813497 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6753 16:44:29.816674 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6754 16:44:29.819882 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6755 16:44:29.823359 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6756 16:44:29.829779 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6757 16:44:29.833649 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6758 16:44:29.836876 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6759 16:44:29.840039 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6760 16:44:29.846782 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6761 16:44:29.849974 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6762 16:44:29.853079 iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480
6763 16:44:29.856760 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6764 16:44:29.860122 ==
6765 16:44:29.863297 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 16:44:29.866553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 16:44:29.866974 ==
6768 16:44:29.867306 DQS Delay:
6769 16:44:29.869917 DQS0 = 35, DQS1 = 35
6770 16:44:29.870335 DQM Delay:
6771 16:44:29.873487 DQM0 = 17, DQM1 = 13
6772 16:44:29.873962 DQ Delay:
6773 16:44:29.876528 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6774 16:44:29.880234 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6775 16:44:29.883114 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6776 16:44:29.886816 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =16
6777 16:44:29.886897
6778 16:44:29.886962
6779 16:44:29.887020 ==
6780 16:44:29.889740 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 16:44:29.892802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 16:44:29.892884 ==
6783 16:44:29.892948
6784 16:44:29.893007
6785 16:44:29.896045 TX Vref Scan disable
6786 16:44:29.896126 == TX Byte 0 ==
6787 16:44:29.902629 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 16:44:29.905948 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 16:44:29.906043 == TX Byte 1 ==
6790 16:44:29.913169 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 16:44:29.916445 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 16:44:29.916558 ==
6793 16:44:29.919229 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 16:44:29.922483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 16:44:29.922621 ==
6796 16:44:29.922728
6797 16:44:29.922828
6798 16:44:29.925894 TX Vref Scan disable
6799 16:44:29.926029 == TX Byte 0 ==
6800 16:44:29.932501 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 16:44:29.935823 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 16:44:29.935998 == TX Byte 1 ==
6803 16:44:29.942603 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 16:44:29.946740 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 16:44:29.947042
6806 16:44:29.947279 [DATLAT]
6807 16:44:29.949916 Freq=400, CH1 RK0
6808 16:44:29.950216
6809 16:44:29.950468 DATLAT Default: 0xf
6810 16:44:29.953212 0, 0xFFFF, sum = 0
6811 16:44:29.953669 1, 0xFFFF, sum = 0
6812 16:44:29.956850 2, 0xFFFF, sum = 0
6813 16:44:29.957282 3, 0xFFFF, sum = 0
6814 16:44:29.959769 4, 0xFFFF, sum = 0
6815 16:44:29.960198 5, 0xFFFF, sum = 0
6816 16:44:29.962828 6, 0xFFFF, sum = 0
6817 16:44:29.963257 7, 0xFFFF, sum = 0
6818 16:44:29.966717 8, 0xFFFF, sum = 0
6819 16:44:29.967163 9, 0xFFFF, sum = 0
6820 16:44:29.969985 10, 0xFFFF, sum = 0
6821 16:44:29.973218 11, 0xFFFF, sum = 0
6822 16:44:29.973684 12, 0xFFFF, sum = 0
6823 16:44:29.976398 13, 0x0, sum = 1
6824 16:44:29.976827 14, 0x0, sum = 2
6825 16:44:29.979805 15, 0x0, sum = 3
6826 16:44:29.980235 16, 0x0, sum = 4
6827 16:44:29.980578 best_step = 14
6828 16:44:29.980891
6829 16:44:29.982918 ==
6830 16:44:29.986483 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 16:44:29.989607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 16:44:29.990036 ==
6833 16:44:29.990497 RX Vref Scan: 1
6834 16:44:29.990950
6835 16:44:29.993284 RX Vref 0 -> 0, step: 1
6836 16:44:29.993744
6837 16:44:29.996170 RX Delay -311 -> 252, step: 8
6838 16:44:29.996596
6839 16:44:29.999241 Set Vref, RX VrefLevel [Byte0]: 55
6840 16:44:30.002757 [Byte1]: 48
6841 16:44:30.006126
6842 16:44:30.006546 Final RX Vref Byte 0 = 55 to rank0
6843 16:44:30.009477 Final RX Vref Byte 1 = 48 to rank0
6844 16:44:30.012835 Final RX Vref Byte 0 = 55 to rank1
6845 16:44:30.016518 Final RX Vref Byte 1 = 48 to rank1==
6846 16:44:30.019878 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 16:44:30.026283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 16:44:30.026708 ==
6849 16:44:30.027042 DQS Delay:
6850 16:44:30.029652 DQS0 = 24, DQS1 = 32
6851 16:44:30.030076 DQM Delay:
6852 16:44:30.030407 DQM0 = 6, DQM1 = 11
6853 16:44:30.032962 DQ Delay:
6854 16:44:30.033384 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6855 16:44:30.036173 DQ4 =4, DQ5 =16, DQ6 =12, DQ7 =4
6856 16:44:30.039403 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6857 16:44:30.042751 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6858 16:44:30.043175
6859 16:44:30.043507
6860 16:44:30.052519 [DQSOSCAuto] RK0, (LSB)MR18= 0x92c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6861 16:44:30.056423 CH1 RK0: MR19=C0C, MR18=92C9
6862 16:44:30.059618 CH1_RK0: MR19=0xC0C, MR18=0x92C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6863 16:44:30.062843 ==
6864 16:44:30.065831 Dram Type= 6, Freq= 0, CH_1, rank 1
6865 16:44:30.068715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6866 16:44:30.068798 ==
6867 16:44:30.072508 [Gating] SW mode calibration
6868 16:44:30.079077 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6869 16:44:30.082287 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6870 16:44:30.089083 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 16:44:30.092717 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6872 16:44:30.095863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 16:44:30.102418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6874 16:44:30.105466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 16:44:30.109502 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 16:44:30.116171 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 16:44:30.119290 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6878 16:44:30.122548 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 16:44:30.125777 Total UI for P1: 0, mck2ui 16
6880 16:44:30.129228 best dqsien dly found for B0: ( 0, 14, 24)
6881 16:44:30.132829 Total UI for P1: 0, mck2ui 16
6882 16:44:30.136050 best dqsien dly found for B1: ( 0, 14, 24)
6883 16:44:30.139232 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6884 16:44:30.142527 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6885 16:44:30.142821
6886 16:44:30.149430 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 16:44:30.152818 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6888 16:44:30.153338 [Gating] SW calibration Done
6889 16:44:30.155767 ==
6890 16:44:30.156277 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 16:44:30.163143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 16:44:30.163711 ==
6893 16:44:30.164071 RX Vref Scan: 0
6894 16:44:30.164391
6895 16:44:30.166297 RX Vref 0 -> 0, step: 1
6896 16:44:30.166726
6897 16:44:30.169347 RX Delay -410 -> 252, step: 16
6898 16:44:30.172764 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6899 16:44:30.175490 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6900 16:44:30.182564 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6901 16:44:30.186111 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6902 16:44:30.189363 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6903 16:44:30.192550 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6904 16:44:30.198661 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6905 16:44:30.202335 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6906 16:44:30.205385 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6907 16:44:30.209006 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6908 16:44:30.215752 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6909 16:44:30.218913 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6910 16:44:30.222410 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6911 16:44:30.225718 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6912 16:44:30.232118 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6913 16:44:30.235401 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6914 16:44:30.235477 ==
6915 16:44:30.238751 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 16:44:30.242316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 16:44:30.242482 ==
6918 16:44:30.245696 DQS Delay:
6919 16:44:30.245861 DQS0 = 35, DQS1 = 35
6920 16:44:30.249364 DQM Delay:
6921 16:44:30.249553 DQM0 = 18, DQM1 = 13
6922 16:44:30.249660 DQ Delay:
6923 16:44:30.252729 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6924 16:44:30.255142 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6925 16:44:30.259160 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6926 16:44:30.262290 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6927 16:44:30.262455
6928 16:44:30.262567
6929 16:44:30.262669 ==
6930 16:44:30.265402 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 16:44:30.271902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 16:44:30.272115 ==
6933 16:44:30.272257
6934 16:44:30.272387
6935 16:44:30.272511 TX Vref Scan disable
6936 16:44:30.275312 == TX Byte 0 ==
6937 16:44:30.278769 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6938 16:44:30.281922 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6939 16:44:30.285559 == TX Byte 1 ==
6940 16:44:30.288745 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6941 16:44:30.291845 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6942 16:44:30.292148 ==
6943 16:44:30.295139 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 16:44:30.302069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 16:44:30.302572 ==
6946 16:44:30.302912
6947 16:44:30.303244
6948 16:44:30.303553 TX Vref Scan disable
6949 16:44:30.305798 == TX Byte 0 ==
6950 16:44:30.308499 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6951 16:44:30.311935 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6952 16:44:30.315205 == TX Byte 1 ==
6953 16:44:30.318808 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6954 16:44:30.321674 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6955 16:44:30.322254
6956 16:44:30.325404 [DATLAT]
6957 16:44:30.325982 Freq=400, CH1 RK1
6958 16:44:30.326379
6959 16:44:30.328700 DATLAT Default: 0xe
6960 16:44:30.329290 0, 0xFFFF, sum = 0
6961 16:44:30.331938 1, 0xFFFF, sum = 0
6962 16:44:30.332372 2, 0xFFFF, sum = 0
6963 16:44:30.335259 3, 0xFFFF, sum = 0
6964 16:44:30.335685 4, 0xFFFF, sum = 0
6965 16:44:30.338646 5, 0xFFFF, sum = 0
6966 16:44:30.339125 6, 0xFFFF, sum = 0
6967 16:44:30.341800 7, 0xFFFF, sum = 0
6968 16:44:30.342440 8, 0xFFFF, sum = 0
6969 16:44:30.345264 9, 0xFFFF, sum = 0
6970 16:44:30.348484 10, 0xFFFF, sum = 0
6971 16:44:30.349090 11, 0xFFFF, sum = 0
6972 16:44:30.351837 12, 0xFFFF, sum = 0
6973 16:44:30.352432 13, 0x0, sum = 1
6974 16:44:30.355123 14, 0x0, sum = 2
6975 16:44:30.355628 15, 0x0, sum = 3
6976 16:44:30.356049 16, 0x0, sum = 4
6977 16:44:30.358337 best_step = 14
6978 16:44:30.358820
6979 16:44:30.359236 ==
6980 16:44:30.361589 Dram Type= 6, Freq= 0, CH_1, rank 1
6981 16:44:30.364943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6982 16:44:30.365487 ==
6983 16:44:30.367993 RX Vref Scan: 0
6984 16:44:30.368412
6985 16:44:30.371353 RX Vref 0 -> 0, step: 1
6986 16:44:30.371872
6987 16:44:30.372446 RX Delay -311 -> 252, step: 8
6988 16:44:30.380458 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6989 16:44:30.383687 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6990 16:44:30.386851 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6991 16:44:30.390529 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6992 16:44:30.396629 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6993 16:44:30.400515 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
6994 16:44:30.403852 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6995 16:44:30.407175 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6996 16:44:30.413873 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6997 16:44:30.417123 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6998 16:44:30.420362 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6999 16:44:30.423580 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7000 16:44:30.430179 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7001 16:44:30.433893 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7002 16:44:30.437293 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7003 16:44:30.439942 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7004 16:44:30.443640 ==
7005 16:44:30.446557 Dram Type= 6, Freq= 0, CH_1, rank 1
7006 16:44:30.449857 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7007 16:44:30.450279 ==
7008 16:44:30.450632 DQS Delay:
7009 16:44:30.453268 DQS0 = 28, DQS1 = 36
7010 16:44:30.453712 DQM Delay:
7011 16:44:30.456603 DQM0 = 11, DQM1 = 14
7012 16:44:30.457022 DQ Delay:
7013 16:44:30.459780 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7014 16:44:30.463041 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7015 16:44:30.466500 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7016 16:44:30.469796 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7017 16:44:30.470215
7018 16:44:30.470548
7019 16:44:30.476248 [DQSOSCAuto] RK1, (LSB)MR18= 0xcb5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 384 ps
7020 16:44:30.480036 CH1 RK1: MR19=C0C, MR18=CB5D
7021 16:44:30.486898 CH1_RK1: MR19=0xC0C, MR18=0xCB5D, DQSOSC=384, MR23=63, INC=400, DEC=267
7022 16:44:30.490080 [RxdqsGatingPostProcess] freq 400
7023 16:44:30.496325 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7024 16:44:30.496757 best DQS0 dly(2T, 0.5T) = (0, 10)
7025 16:44:30.499737 best DQS1 dly(2T, 0.5T) = (0, 10)
7026 16:44:30.502868 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7027 16:44:30.506082 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7028 16:44:30.509307 best DQS0 dly(2T, 0.5T) = (0, 10)
7029 16:44:30.512607 best DQS1 dly(2T, 0.5T) = (0, 10)
7030 16:44:30.516650 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7031 16:44:30.518991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7032 16:44:30.523110 Pre-setting of DQS Precalculation
7033 16:44:30.526340 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7034 16:44:30.535755 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7035 16:44:30.542652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7036 16:44:30.542736
7037 16:44:30.542812
7038 16:44:30.545737 [Calibration Summary] 800 Mbps
7039 16:44:30.545810 CH 0, Rank 0
7040 16:44:30.550057 SW Impedance : PASS
7041 16:44:30.550510 DUTY Scan : NO K
7042 16:44:30.552828 ZQ Calibration : PASS
7043 16:44:30.555985 Jitter Meter : NO K
7044 16:44:30.556415 CBT Training : PASS
7045 16:44:30.559379 Write leveling : PASS
7046 16:44:30.562176 RX DQS gating : PASS
7047 16:44:30.562253 RX DQ/DQS(RDDQC) : PASS
7048 16:44:30.566158 TX DQ/DQS : PASS
7049 16:44:30.569440 RX DATLAT : PASS
7050 16:44:30.569557 RX DQ/DQS(Engine): PASS
7051 16:44:30.572792 TX OE : NO K
7052 16:44:30.572875 All Pass.
7053 16:44:30.572939
7054 16:44:30.575948 CH 0, Rank 1
7055 16:44:30.576030 SW Impedance : PASS
7056 16:44:30.579202 DUTY Scan : NO K
7057 16:44:30.582515 ZQ Calibration : PASS
7058 16:44:30.582591 Jitter Meter : NO K
7059 16:44:30.585863 CBT Training : PASS
7060 16:44:30.589140 Write leveling : NO K
7061 16:44:30.589217 RX DQS gating : PASS
7062 16:44:30.592405 RX DQ/DQS(RDDQC) : PASS
7063 16:44:30.592482 TX DQ/DQS : PASS
7064 16:44:30.595968 RX DATLAT : PASS
7065 16:44:30.599179 RX DQ/DQS(Engine): PASS
7066 16:44:30.599282 TX OE : NO K
7067 16:44:30.602426 All Pass.
7068 16:44:30.602509
7069 16:44:30.602574 CH 1, Rank 0
7070 16:44:30.605566 SW Impedance : PASS
7071 16:44:30.605654 DUTY Scan : NO K
7072 16:44:30.608872 ZQ Calibration : PASS
7073 16:44:30.612626 Jitter Meter : NO K
7074 16:44:30.612709 CBT Training : PASS
7075 16:44:30.615724 Write leveling : PASS
7076 16:44:30.619080 RX DQS gating : PASS
7077 16:44:30.619164 RX DQ/DQS(RDDQC) : PASS
7078 16:44:30.622347 TX DQ/DQS : PASS
7079 16:44:30.625382 RX DATLAT : PASS
7080 16:44:30.625500 RX DQ/DQS(Engine): PASS
7081 16:44:30.628886 TX OE : NO K
7082 16:44:30.628964 All Pass.
7083 16:44:30.629029
7084 16:44:30.632634 CH 1, Rank 1
7085 16:44:30.632737 SW Impedance : PASS
7086 16:44:30.635864 DUTY Scan : NO K
7087 16:44:30.639045 ZQ Calibration : PASS
7088 16:44:30.639144 Jitter Meter : NO K
7089 16:44:30.642252 CBT Training : PASS
7090 16:44:30.642336 Write leveling : NO K
7091 16:44:30.645475 RX DQS gating : PASS
7092 16:44:30.649200 RX DQ/DQS(RDDQC) : PASS
7093 16:44:30.649295 TX DQ/DQS : PASS
7094 16:44:30.652467 RX DATLAT : PASS
7095 16:44:30.655599 RX DQ/DQS(Engine): PASS
7096 16:44:30.655676 TX OE : NO K
7097 16:44:30.658795 All Pass.
7098 16:44:30.658869
7099 16:44:30.658932 DramC Write-DBI off
7100 16:44:30.662109 PER_BANK_REFRESH: Hybrid Mode
7101 16:44:30.662186 TX_TRACKING: ON
7102 16:44:30.672019 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7103 16:44:30.675357 [FAST_K] Save calibration result to emmc
7104 16:44:30.678652 dramc_set_vcore_voltage set vcore to 725000
7105 16:44:30.682536 Read voltage for 1600, 0
7106 16:44:30.682612 Vio18 = 0
7107 16:44:30.685827 Vcore = 725000
7108 16:44:30.685901 Vdram = 0
7109 16:44:30.685965 Vddq = 0
7110 16:44:30.689167 Vmddr = 0
7111 16:44:30.692505 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7112 16:44:30.699097 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7113 16:44:30.699201 MEM_TYPE=3, freq_sel=13
7114 16:44:30.702297 sv_algorithm_assistance_LP4_3733
7115 16:44:30.708869 ============ PULL DRAM RESETB DOWN ============
7116 16:44:30.712038 ========== PULL DRAM RESETB DOWN end =========
7117 16:44:30.715762 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7118 16:44:30.719044 ===================================
7119 16:44:30.722298 LPDDR4 DRAM CONFIGURATION
7120 16:44:30.725410 ===================================
7121 16:44:30.725637 EX_ROW_EN[0] = 0x0
7122 16:44:30.728702 EX_ROW_EN[1] = 0x0
7123 16:44:30.731880 LP4Y_EN = 0x0
7124 16:44:30.731961 WORK_FSP = 0x1
7125 16:44:30.735718 WL = 0x5
7126 16:44:30.735799 RL = 0x5
7127 16:44:30.738826 BL = 0x2
7128 16:44:30.738908 RPST = 0x0
7129 16:44:30.742031 RD_PRE = 0x0
7130 16:44:30.742112 WR_PRE = 0x1
7131 16:44:30.745322 WR_PST = 0x1
7132 16:44:30.745403 DBI_WR = 0x0
7133 16:44:30.748476 DBI_RD = 0x0
7134 16:44:30.748558 OTF = 0x1
7135 16:44:30.751749 ===================================
7136 16:44:30.755266 ===================================
7137 16:44:30.758538 ANA top config
7138 16:44:30.761671 ===================================
7139 16:44:30.761753 DLL_ASYNC_EN = 0
7140 16:44:30.765416 ALL_SLAVE_EN = 0
7141 16:44:30.768667 NEW_RANK_MODE = 1
7142 16:44:30.771944 DLL_IDLE_MODE = 1
7143 16:44:30.775148 LP45_APHY_COMB_EN = 1
7144 16:44:30.775230 TX_ODT_DIS = 0
7145 16:44:30.778525 NEW_8X_MODE = 1
7146 16:44:30.781854 ===================================
7147 16:44:30.785212 ===================================
7148 16:44:30.788420 data_rate = 3200
7149 16:44:30.791547 CKR = 1
7150 16:44:30.794959 DQ_P2S_RATIO = 8
7151 16:44:30.798188 ===================================
7152 16:44:30.798269 CA_P2S_RATIO = 8
7153 16:44:30.802071 DQ_CA_OPEN = 0
7154 16:44:30.804956 DQ_SEMI_OPEN = 0
7155 16:44:30.808260 CA_SEMI_OPEN = 0
7156 16:44:30.811619 CA_FULL_RATE = 0
7157 16:44:30.814873 DQ_CKDIV4_EN = 0
7158 16:44:30.814986 CA_CKDIV4_EN = 0
7159 16:44:30.817935 CA_PREDIV_EN = 0
7160 16:44:30.821665 PH8_DLY = 12
7161 16:44:30.824763 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7162 16:44:30.828589 DQ_AAMCK_DIV = 4
7163 16:44:30.831742 CA_AAMCK_DIV = 4
7164 16:44:30.831823 CA_ADMCK_DIV = 4
7165 16:44:30.835095 DQ_TRACK_CA_EN = 0
7166 16:44:30.838439 CA_PICK = 1600
7167 16:44:30.841770 CA_MCKIO = 1600
7168 16:44:30.844948 MCKIO_SEMI = 0
7169 16:44:30.848724 PLL_FREQ = 3068
7170 16:44:30.851983 DQ_UI_PI_RATIO = 32
7171 16:44:30.852081 CA_UI_PI_RATIO = 0
7172 16:44:30.855371 ===================================
7173 16:44:30.858723 ===================================
7174 16:44:30.861714 memory_type:LPDDR4
7175 16:44:30.865335 GP_NUM : 10
7176 16:44:30.865412 SRAM_EN : 1
7177 16:44:30.868683 MD32_EN : 0
7178 16:44:30.871687 ===================================
7179 16:44:30.874728 [ANA_INIT] >>>>>>>>>>>>>>
7180 16:44:30.878087 <<<<<< [CONFIGURE PHASE]: ANA_TX
7181 16:44:30.881435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7182 16:44:30.884615 ===================================
7183 16:44:30.884697 data_rate = 3200,PCW = 0X7600
7184 16:44:30.888005 ===================================
7185 16:44:30.891979 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7186 16:44:30.898621 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 16:44:30.904980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7188 16:44:30.908192 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7189 16:44:30.911258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7190 16:44:30.914642 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7191 16:44:30.917947 [ANA_INIT] flow start
7192 16:44:30.921300 [ANA_INIT] PLL >>>>>>>>
7193 16:44:30.921381 [ANA_INIT] PLL <<<<<<<<
7194 16:44:30.924407 [ANA_INIT] MIDPI >>>>>>>>
7195 16:44:30.927709 [ANA_INIT] MIDPI <<<<<<<<
7196 16:44:30.927788 [ANA_INIT] DLL >>>>>>>>
7197 16:44:30.931412 [ANA_INIT] DLL <<<<<<<<
7198 16:44:30.934672 [ANA_INIT] flow end
7199 16:44:30.937517 ============ LP4 DIFF to SE enter ============
7200 16:44:30.940878 ============ LP4 DIFF to SE exit ============
7201 16:44:30.944658 [ANA_INIT] <<<<<<<<<<<<<
7202 16:44:30.947647 [Flow] Enable top DCM control >>>>>
7203 16:44:30.951349 [Flow] Enable top DCM control <<<<<
7204 16:44:30.954053 Enable DLL master slave shuffle
7205 16:44:30.957980 ==============================================================
7206 16:44:30.960703 Gating Mode config
7207 16:44:30.967170 ==============================================================
7208 16:44:30.967260 Config description:
7209 16:44:30.977432 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7210 16:44:30.984498 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7211 16:44:30.991183 SELPH_MODE 0: By rank 1: By Phase
7212 16:44:30.994961 ==============================================================
7213 16:44:30.997662 GAT_TRACK_EN = 1
7214 16:44:31.000921 RX_GATING_MODE = 2
7215 16:44:31.004385 RX_GATING_TRACK_MODE = 2
7216 16:44:31.007498 SELPH_MODE = 1
7217 16:44:31.011125 PICG_EARLY_EN = 1
7218 16:44:31.014287 VALID_LAT_VALUE = 1
7219 16:44:31.018039 ==============================================================
7220 16:44:31.021225 Enter into Gating configuration >>>>
7221 16:44:31.024740 Exit from Gating configuration <<<<
7222 16:44:31.027914 Enter into DVFS_PRE_config >>>>>
7223 16:44:31.041338 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7224 16:44:31.041873 Exit from DVFS_PRE_config <<<<<
7225 16:44:31.044416 Enter into PICG configuration >>>>
7226 16:44:31.047543 Exit from PICG configuration <<<<
7227 16:44:31.050659 [RX_INPUT] configuration >>>>>
7228 16:44:31.054396 [RX_INPUT] configuration <<<<<
7229 16:44:31.060890 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7230 16:44:31.064143 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7231 16:44:31.070824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7232 16:44:31.077140 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7233 16:44:31.084097 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7234 16:44:31.090700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7235 16:44:31.094317 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7236 16:44:31.097440 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7237 16:44:31.100733 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7238 16:44:31.107356 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7239 16:44:31.110571 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7240 16:44:31.113470 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7241 16:44:31.117455 ===================================
7242 16:44:31.120535 LPDDR4 DRAM CONFIGURATION
7243 16:44:31.123863 ===================================
7244 16:44:31.124463 EX_ROW_EN[0] = 0x0
7245 16:44:31.127109 EX_ROW_EN[1] = 0x0
7246 16:44:31.130355 LP4Y_EN = 0x0
7247 16:44:31.130781 WORK_FSP = 0x1
7248 16:44:31.133739 WL = 0x5
7249 16:44:31.134194 RL = 0x5
7250 16:44:31.137095 BL = 0x2
7251 16:44:31.137663 RPST = 0x0
7252 16:44:31.140367 RD_PRE = 0x0
7253 16:44:31.141050 WR_PRE = 0x1
7254 16:44:31.144107 WR_PST = 0x1
7255 16:44:31.144716 DBI_WR = 0x0
7256 16:44:31.147206 DBI_RD = 0x0
7257 16:44:31.147833 OTF = 0x1
7258 16:44:31.150837 ===================================
7259 16:44:31.154097 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7260 16:44:31.160529 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7261 16:44:31.163720 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 16:44:31.167496 ===================================
7263 16:44:31.170884 LPDDR4 DRAM CONFIGURATION
7264 16:44:31.174020 ===================================
7265 16:44:31.174462 EX_ROW_EN[0] = 0x10
7266 16:44:31.177258 EX_ROW_EN[1] = 0x0
7267 16:44:31.177726 LP4Y_EN = 0x0
7268 16:44:31.180418 WORK_FSP = 0x1
7269 16:44:31.180801 WL = 0x5
7270 16:44:31.183767 RL = 0x5
7271 16:44:31.187008 BL = 0x2
7272 16:44:31.187428 RPST = 0x0
7273 16:44:31.190615 RD_PRE = 0x0
7274 16:44:31.190834 WR_PRE = 0x1
7275 16:44:31.193403 WR_PST = 0x1
7276 16:44:31.193560 DBI_WR = 0x0
7277 16:44:31.197206 DBI_RD = 0x0
7278 16:44:31.197287 OTF = 0x1
7279 16:44:31.200112 ===================================
7280 16:44:31.207037 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7281 16:44:31.207125 ==
7282 16:44:31.210387 Dram Type= 6, Freq= 0, CH_0, rank 0
7283 16:44:31.213545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7284 16:44:31.213641 ==
7285 16:44:31.216811 [Duty_Offset_Calibration]
7286 16:44:31.220097 B0:2 B1:1 CA:1
7287 16:44:31.220220
7288 16:44:31.223242 [DutyScan_Calibration_Flow] k_type=0
7289 16:44:31.231902
7290 16:44:31.231990 ==CLK 0==
7291 16:44:31.235148 Final CLK duty delay cell = 0
7292 16:44:31.238359 [0] MAX Duty = 5187%(X100), DQS PI = 22
7293 16:44:31.241584 [0] MIN Duty = 4907%(X100), DQS PI = 0
7294 16:44:31.241666 [0] AVG Duty = 5047%(X100)
7295 16:44:31.245020
7296 16:44:31.248106 CH0 CLK Duty spec in!! Max-Min= 280%
7297 16:44:31.251372 [DutyScan_Calibration_Flow] ====Done====
7298 16:44:31.251452
7299 16:44:31.254868 [DutyScan_Calibration_Flow] k_type=1
7300 16:44:31.270665
7301 16:44:31.270747 ==DQS 0 ==
7302 16:44:31.274396 Final DQS duty delay cell = -4
7303 16:44:31.277774 [-4] MAX Duty = 5156%(X100), DQS PI = 28
7304 16:44:31.281338 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7305 16:44:31.284572 [-4] AVG Duty = 4906%(X100)
7306 16:44:31.284992
7307 16:44:31.285321 ==DQS 1 ==
7308 16:44:31.287980 Final DQS duty delay cell = 0
7309 16:44:31.291134 [0] MAX Duty = 5187%(X100), DQS PI = 10
7310 16:44:31.295097 [0] MIN Duty = 5031%(X100), DQS PI = 52
7311 16:44:31.298385 [0] AVG Duty = 5109%(X100)
7312 16:44:31.298817
7313 16:44:31.301562 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7314 16:44:31.302037
7315 16:44:31.304570 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7316 16:44:31.308202 [DutyScan_Calibration_Flow] ====Done====
7317 16:44:31.308745
7318 16:44:31.311288 [DutyScan_Calibration_Flow] k_type=3
7319 16:44:31.327820
7320 16:44:31.328257 ==DQM 0 ==
7321 16:44:31.331522 Final DQM duty delay cell = 0
7322 16:44:31.334951 [0] MAX Duty = 5218%(X100), DQS PI = 34
7323 16:44:31.338020 [0] MIN Duty = 4875%(X100), DQS PI = 60
7324 16:44:31.338748 [0] AVG Duty = 5046%(X100)
7325 16:44:31.341217
7326 16:44:31.341902 ==DQM 1 ==
7327 16:44:31.344502 Final DQM duty delay cell = -4
7328 16:44:31.347599 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7329 16:44:31.351044 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7330 16:44:31.354744 [-4] AVG Duty = 4891%(X100)
7331 16:44:31.355289
7332 16:44:31.358005 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7333 16:44:31.358626
7334 16:44:31.361204 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7335 16:44:31.364790 [DutyScan_Calibration_Flow] ====Done====
7336 16:44:31.365388
7337 16:44:31.367749 [DutyScan_Calibration_Flow] k_type=2
7338 16:44:31.385577
7339 16:44:31.386255 ==DQ 0 ==
7340 16:44:31.388625 Final DQ duty delay cell = 0
7341 16:44:31.392458 [0] MAX Duty = 5062%(X100), DQS PI = 26
7342 16:44:31.395126 [0] MIN Duty = 4907%(X100), DQS PI = 0
7343 16:44:31.395662 [0] AVG Duty = 4984%(X100)
7344 16:44:31.396032
7345 16:44:31.398644 ==DQ 1 ==
7346 16:44:31.402467 Final DQ duty delay cell = 0
7347 16:44:31.405740 [0] MAX Duty = 5125%(X100), DQS PI = 6
7348 16:44:31.409076 [0] MIN Duty = 4938%(X100), DQS PI = 34
7349 16:44:31.409502 [0] AVG Duty = 5031%(X100)
7350 16:44:31.409896
7351 16:44:31.412112 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7352 16:44:31.412533
7353 16:44:31.415727 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7354 16:44:31.422388 [DutyScan_Calibration_Flow] ====Done====
7355 16:44:31.422956 ==
7356 16:44:31.425399 Dram Type= 6, Freq= 0, CH_1, rank 0
7357 16:44:31.429042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7358 16:44:31.429468 ==
7359 16:44:31.432091 [Duty_Offset_Calibration]
7360 16:44:31.432505 B0:1 B1:0 CA:0
7361 16:44:31.432832
7362 16:44:31.435380 [DutyScan_Calibration_Flow] k_type=0
7363 16:44:31.444507
7364 16:44:31.444926 ==CLK 0==
7365 16:44:31.448514 Final CLK duty delay cell = -4
7366 16:44:31.451370 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7367 16:44:31.454546 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7368 16:44:31.457941 [-4] AVG Duty = 4922%(X100)
7369 16:44:31.458020
7370 16:44:31.461172 CH1 CLK Duty spec in!! Max-Min= 156%
7371 16:44:31.464356 [DutyScan_Calibration_Flow] ====Done====
7372 16:44:31.464436
7373 16:44:31.467493 [DutyScan_Calibration_Flow] k_type=1
7374 16:44:31.483472
7375 16:44:31.483587 ==DQS 0 ==
7376 16:44:31.487140 Final DQS duty delay cell = 0
7377 16:44:31.490132 [0] MAX Duty = 5094%(X100), DQS PI = 16
7378 16:44:31.493862 [0] MIN Duty = 4844%(X100), DQS PI = 48
7379 16:44:31.497092 [0] AVG Duty = 4969%(X100)
7380 16:44:31.497174
7381 16:44:31.497237 ==DQS 1 ==
7382 16:44:31.500264 Final DQS duty delay cell = -4
7383 16:44:31.503624 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7384 16:44:31.506834 [-4] MIN Duty = 4750%(X100), DQS PI = 8
7385 16:44:31.510099 [-4] AVG Duty = 4859%(X100)
7386 16:44:31.510184
7387 16:44:31.513368 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7388 16:44:31.513450
7389 16:44:31.516760 CH1 DQS 1 Duty spec in!! Max-Min= 219%
7390 16:44:31.520477 [DutyScan_Calibration_Flow] ====Done====
7391 16:44:31.520559
7392 16:44:31.523466 [DutyScan_Calibration_Flow] k_type=3
7393 16:44:31.541169
7394 16:44:31.541260 ==DQM 0 ==
7395 16:44:31.544528 Final DQM duty delay cell = 0
7396 16:44:31.547722 [0] MAX Duty = 5218%(X100), DQS PI = 16
7397 16:44:31.551052 [0] MIN Duty = 4969%(X100), DQS PI = 48
7398 16:44:31.554218 [0] AVG Duty = 5093%(X100)
7399 16:44:31.554299
7400 16:44:31.554364 ==DQM 1 ==
7401 16:44:31.557503 Final DQM duty delay cell = 0
7402 16:44:31.560807 [0] MAX Duty = 5124%(X100), DQS PI = 18
7403 16:44:31.564098 [0] MIN Duty = 4938%(X100), DQS PI = 50
7404 16:44:31.567421 [0] AVG Duty = 5031%(X100)
7405 16:44:31.567503
7406 16:44:31.570465 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7407 16:44:31.570555
7408 16:44:31.574248 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7409 16:44:31.577369 [DutyScan_Calibration_Flow] ====Done====
7410 16:44:31.577452
7411 16:44:31.580706 [DutyScan_Calibration_Flow] k_type=2
7412 16:44:31.596907
7413 16:44:31.597022 ==DQ 0 ==
7414 16:44:31.600467 Final DQ duty delay cell = -4
7415 16:44:31.603642 [-4] MAX Duty = 5062%(X100), DQS PI = 14
7416 16:44:31.606793 [-4] MIN Duty = 4875%(X100), DQS PI = 48
7417 16:44:31.610134 [-4] AVG Duty = 4968%(X100)
7418 16:44:31.610218
7419 16:44:31.610284 ==DQ 1 ==
7420 16:44:31.613479 Final DQ duty delay cell = 0
7421 16:44:31.616756 [0] MAX Duty = 5156%(X100), DQS PI = 18
7422 16:44:31.620705 [0] MIN Duty = 4969%(X100), DQS PI = 8
7423 16:44:31.623303 [0] AVG Duty = 5062%(X100)
7424 16:44:31.623387
7425 16:44:31.627163 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7426 16:44:31.627246
7427 16:44:31.630285 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7428 16:44:31.633256 [DutyScan_Calibration_Flow] ====Done====
7429 16:44:31.636830 nWR fixed to 30
7430 16:44:31.640079 [ModeRegInit_LP4] CH0 RK0
7431 16:44:31.640164 [ModeRegInit_LP4] CH0 RK1
7432 16:44:31.643257 [ModeRegInit_LP4] CH1 RK0
7433 16:44:31.646721 [ModeRegInit_LP4] CH1 RK1
7434 16:44:31.646806 match AC timing 5
7435 16:44:31.653398 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7436 16:44:31.656794 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7437 16:44:31.660141 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7438 16:44:31.666734 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7439 16:44:31.669938 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7440 16:44:31.670037 [MiockJmeterHQA]
7441 16:44:31.670134
7442 16:44:31.673239 [DramcMiockJmeter] u1RxGatingPI = 0
7443 16:44:31.676850 0 : 4363, 4137
7444 16:44:31.676936 4 : 4252, 4027
7445 16:44:31.680035 8 : 4252, 4027
7446 16:44:31.680124 12 : 4252, 4027
7447 16:44:31.680192 16 : 4253, 4027
7448 16:44:31.683384 20 : 4363, 4137
7449 16:44:31.683468 24 : 4252, 4027
7450 16:44:31.686713 28 : 4362, 4137
7451 16:44:31.686797 32 : 4253, 4026
7452 16:44:31.689822 36 : 4252, 4026
7453 16:44:31.689905 40 : 4252, 4027
7454 16:44:31.692925 44 : 4255, 4029
7455 16:44:31.693025 48 : 4249, 4027
7456 16:44:31.693093 52 : 4255, 4029
7457 16:44:31.696718 56 : 4363, 4140
7458 16:44:31.696801 60 : 4252, 4029
7459 16:44:31.699819 64 : 4252, 4030
7460 16:44:31.699902 68 : 4250, 4026
7461 16:44:31.702923 72 : 4363, 4140
7462 16:44:31.703043 76 : 4250, 4027
7463 16:44:31.706644 80 : 4360, 4137
7464 16:44:31.706755 84 : 4250, 4027
7465 16:44:31.706856 88 : 4249, 423
7466 16:44:31.710113 92 : 4253, 0
7467 16:44:31.710264 96 : 4252, 0
7468 16:44:31.710363 100 : 4361, 0
7469 16:44:31.713165 104 : 4250, 0
7470 16:44:31.713271 108 : 4250, 0
7471 16:44:31.716524 112 : 4250, 0
7472 16:44:31.716625 116 : 4249, 0
7473 16:44:31.716694 120 : 4252, 0
7474 16:44:31.719654 124 : 4250, 0
7475 16:44:31.719755 128 : 4249, 0
7476 16:44:31.723648 132 : 4253, 0
7477 16:44:31.723751 136 : 4361, 0
7478 16:44:31.723843 140 : 4249, 0
7479 16:44:31.726245 144 : 4250, 0
7480 16:44:31.726341 148 : 4360, 0
7481 16:44:31.730099 152 : 4361, 0
7482 16:44:31.730170 156 : 4363, 0
7483 16:44:31.730232 160 : 4250, 0
7484 16:44:31.733150 164 : 4250, 0
7485 16:44:31.733277 168 : 4250, 0
7486 16:44:31.736281 172 : 4252, 0
7487 16:44:31.736384 176 : 4250, 0
7488 16:44:31.736482 180 : 4249, 0
7489 16:44:31.739473 184 : 4252, 0
7490 16:44:31.739575 188 : 4361, 0
7491 16:44:31.739668 192 : 4249, 0
7492 16:44:31.743437 196 : 4250, 0
7493 16:44:31.743536 200 : 4250, 0
7494 16:44:31.746628 204 : 4361, 1315
7495 16:44:31.746700 208 : 4361, 4121
7496 16:44:31.749753 212 : 4250, 4027
7497 16:44:31.749858 216 : 4363, 4140
7498 16:44:31.753038 220 : 4249, 4027
7499 16:44:31.753145 224 : 4250, 4026
7500 16:44:31.756063 228 : 4250, 4027
7501 16:44:31.756165 232 : 4252, 4030
7502 16:44:31.756259 236 : 4249, 4027
7503 16:44:31.759914 240 : 4250, 4026
7504 16:44:31.760041 244 : 4250, 4027
7505 16:44:31.763059 248 : 4252, 4030
7506 16:44:31.763167 252 : 4249, 4027
7507 16:44:31.766311 256 : 4361, 4137
7508 16:44:31.766418 260 : 4363, 4137
7509 16:44:31.769627 264 : 4250, 4027
7510 16:44:31.769736 268 : 4363, 4140
7511 16:44:31.772818 272 : 4361, 4137
7512 16:44:31.772918 276 : 4250, 4026
7513 16:44:31.776067 280 : 4250, 4027
7514 16:44:31.776176 284 : 4252, 4030
7515 16:44:31.779844 288 : 4249, 4027
7516 16:44:31.779953 292 : 4250, 4026
7517 16:44:31.780047 296 : 4250, 4027
7518 16:44:31.782800 300 : 4252, 4030
7519 16:44:31.782911 304 : 4249, 4027
7520 16:44:31.786147 308 : 4361, 4107
7521 16:44:31.786251 312 : 4361, 2136
7522 16:44:31.786357
7523 16:44:31.789270 MIOCK jitter meter ch=0
7524 16:44:31.789375
7525 16:44:31.792555 1T = (312-88) = 224 dly cells
7526 16:44:31.799802 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7527 16:44:31.799928 ==
7528 16:44:31.802845 Dram Type= 6, Freq= 0, CH_0, rank 0
7529 16:44:31.806132 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7530 16:44:31.806237 ==
7531 16:44:31.812566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7532 16:44:31.816165 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7533 16:44:31.819430 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7534 16:44:31.826168 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7535 16:44:31.834634 [CA 0] Center 42 (12~73) winsize 62
7536 16:44:31.838197 [CA 1] Center 42 (12~73) winsize 62
7537 16:44:31.841392 [CA 2] Center 38 (8~68) winsize 61
7538 16:44:31.844560 [CA 3] Center 37 (8~67) winsize 60
7539 16:44:31.848201 [CA 4] Center 36 (6~66) winsize 61
7540 16:44:31.851509 [CA 5] Center 35 (6~64) winsize 59
7541 16:44:31.851592
7542 16:44:31.854369 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7543 16:44:31.854476
7544 16:44:31.857669 [CATrainingPosCal] consider 1 rank data
7545 16:44:31.861275 u2DelayCellTimex100 = 290/100 ps
7546 16:44:31.864489 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7547 16:44:31.871064 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7548 16:44:31.874384 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7549 16:44:31.877535 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7550 16:44:31.881370 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7551 16:44:31.884247 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7552 16:44:31.884321
7553 16:44:31.888147 CA PerBit enable=1, Macro0, CA PI delay=35
7554 16:44:31.888228
7555 16:44:31.891306 [CBTSetCACLKResult] CA Dly = 35
7556 16:44:31.894690 CS Dly: 9 (0~40)
7557 16:44:31.897808 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7558 16:44:31.901065 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7559 16:44:31.901142 ==
7560 16:44:31.904631 Dram Type= 6, Freq= 0, CH_0, rank 1
7561 16:44:31.907870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7562 16:44:31.907943 ==
7563 16:44:31.914777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7564 16:44:31.918062 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7565 16:44:31.924345 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7566 16:44:31.927487 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7567 16:44:31.937977 [CA 0] Center 43 (13~73) winsize 61
7568 16:44:31.941067 [CA 1] Center 43 (13~73) winsize 61
7569 16:44:31.944748 [CA 2] Center 38 (8~68) winsize 61
7570 16:44:31.948006 [CA 3] Center 38 (8~68) winsize 61
7571 16:44:31.951380 [CA 4] Center 36 (6~66) winsize 61
7572 16:44:31.954453 [CA 5] Center 35 (6~65) winsize 60
7573 16:44:31.954526
7574 16:44:31.958415 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7575 16:44:31.958532
7576 16:44:31.960898 [CATrainingPosCal] consider 2 rank data
7577 16:44:31.964625 u2DelayCellTimex100 = 290/100 ps
7578 16:44:31.967638 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7579 16:44:31.974557 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7580 16:44:31.978115 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7581 16:44:31.981312 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7582 16:44:31.984515 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7583 16:44:31.987621 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7584 16:44:31.987704
7585 16:44:31.991212 CA PerBit enable=1, Macro0, CA PI delay=35
7586 16:44:31.991294
7587 16:44:31.994419 [CBTSetCACLKResult] CA Dly = 35
7588 16:44:31.997768 CS Dly: 10 (0~42)
7589 16:44:32.001077 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7590 16:44:32.004342 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7591 16:44:32.004425
7592 16:44:32.007521 ----->DramcWriteLeveling(PI) begin...
7593 16:44:32.007605 ==
7594 16:44:32.011229 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 16:44:32.014251 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 16:44:32.017832 ==
7597 16:44:32.017930 Write leveling (Byte 0): 35 => 35
7598 16:44:32.021240 Write leveling (Byte 1): 27 => 27
7599 16:44:32.024501 DramcWriteLeveling(PI) end<-----
7600 16:44:32.024588
7601 16:44:32.024667 ==
7602 16:44:32.027695 Dram Type= 6, Freq= 0, CH_0, rank 0
7603 16:44:32.034477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7604 16:44:32.034562 ==
7605 16:44:32.037904 [Gating] SW mode calibration
7606 16:44:32.044174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7607 16:44:32.047746 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7608 16:44:32.054431 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7609 16:44:32.057683 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7610 16:44:32.060715 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7611 16:44:32.064479 1 4 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)
7612 16:44:32.071139 1 4 16 | B1->B0 | 2424 3737 | 0 1 | (1 1) (1 1)
7613 16:44:32.074478 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7614 16:44:32.077560 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7615 16:44:32.084342 1 4 28 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7616 16:44:32.087708 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7617 16:44:32.090750 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7618 16:44:32.097718 1 5 8 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7619 16:44:32.101119 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7620 16:44:32.104319 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7621 16:44:32.110955 1 5 20 | B1->B0 | 2525 2424 | 0 0 | (1 0) (0 0)
7622 16:44:32.114271 1 5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7623 16:44:32.117961 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7624 16:44:32.124122 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7625 16:44:32.127266 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7626 16:44:32.130502 1 6 8 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
7627 16:44:32.137704 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7628 16:44:32.140602 1 6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
7629 16:44:32.143870 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 16:44:32.150739 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 16:44:32.154028 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7632 16:44:32.157426 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7633 16:44:32.164127 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7634 16:44:32.167383 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 16:44:32.170434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7636 16:44:32.177266 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7637 16:44:32.180774 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 16:44:32.184109 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 16:44:32.190759 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 16:44:32.193978 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 16:44:32.197332 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 16:44:32.203750 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 16:44:32.207077 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 16:44:32.210298 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 16:44:32.213708 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 16:44:32.220151 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 16:44:32.223376 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 16:44:32.226661 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 16:44:32.233305 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 16:44:32.236975 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7651 16:44:32.240429 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7652 16:44:32.246925 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7653 16:44:32.250065 Total UI for P1: 0, mck2ui 16
7654 16:44:32.253075 best dqsien dly found for B0: ( 1, 9, 10)
7655 16:44:32.256948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7656 16:44:32.260031 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7657 16:44:32.263443 Total UI for P1: 0, mck2ui 16
7658 16:44:32.266521 best dqsien dly found for B1: ( 1, 9, 20)
7659 16:44:32.269802 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7660 16:44:32.272969 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7661 16:44:32.276855
7662 16:44:32.279878 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7663 16:44:32.283160 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7664 16:44:32.286956 [Gating] SW calibration Done
7665 16:44:32.287035 ==
7666 16:44:32.289947 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 16:44:32.293124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 16:44:32.293201 ==
7669 16:44:32.296254 RX Vref Scan: 0
7670 16:44:32.296343
7671 16:44:32.296405 RX Vref 0 -> 0, step: 1
7672 16:44:32.296463
7673 16:44:32.299635 RX Delay 0 -> 252, step: 8
7674 16:44:32.302882 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7675 16:44:32.306744 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7676 16:44:32.313289 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7677 16:44:32.316487 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7678 16:44:32.319678 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7679 16:44:32.322946 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7680 16:44:32.326272 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7681 16:44:32.332842 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7682 16:44:32.336639 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7683 16:44:32.339559 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7684 16:44:32.342768 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7685 16:44:32.346513 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7686 16:44:32.352941 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7687 16:44:32.356165 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7688 16:44:32.359806 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7689 16:44:32.363056 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7690 16:44:32.363139 ==
7691 16:44:32.366217 Dram Type= 6, Freq= 0, CH_0, rank 0
7692 16:44:32.370192 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7693 16:44:32.373235 ==
7694 16:44:32.373319 DQS Delay:
7695 16:44:32.373385 DQS0 = 0, DQS1 = 0
7696 16:44:32.376423 DQM Delay:
7697 16:44:32.376532 DQM0 = 137, DQM1 = 129
7698 16:44:32.379635 DQ Delay:
7699 16:44:32.382908 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7700 16:44:32.386111 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7701 16:44:32.389305 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7702 16:44:32.393220 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7703 16:44:32.393327
7704 16:44:32.393430
7705 16:44:32.393535 ==
7706 16:44:32.396281 Dram Type= 6, Freq= 0, CH_0, rank 0
7707 16:44:32.399623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7708 16:44:32.399753 ==
7709 16:44:32.403043
7710 16:44:32.403182
7711 16:44:32.403299 TX Vref Scan disable
7712 16:44:32.406261 == TX Byte 0 ==
7713 16:44:32.409344 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7714 16:44:32.412634 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7715 16:44:32.416002 == TX Byte 1 ==
7716 16:44:32.419316 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7717 16:44:32.422596 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7718 16:44:32.422784 ==
7719 16:44:32.425915 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 16:44:32.432874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 16:44:32.433191 ==
7722 16:44:32.445356
7723 16:44:32.449137 TX Vref early break, caculate TX vref
7724 16:44:32.452286 TX Vref=16, minBit 6, minWin=22, winSum=376
7725 16:44:32.455520 TX Vref=18, minBit 0, minWin=23, winSum=386
7726 16:44:32.458718 TX Vref=20, minBit 0, minWin=24, winSum=403
7727 16:44:32.462303 TX Vref=22, minBit 7, minWin=23, winSum=407
7728 16:44:32.465471 TX Vref=24, minBit 1, minWin=25, winSum=416
7729 16:44:32.472563 TX Vref=26, minBit 1, minWin=25, winSum=424
7730 16:44:32.475649 TX Vref=28, minBit 1, minWin=25, winSum=421
7731 16:44:32.478937 TX Vref=30, minBit 1, minWin=24, winSum=414
7732 16:44:32.482083 TX Vref=32, minBit 1, minWin=24, winSum=407
7733 16:44:32.485443 TX Vref=34, minBit 1, minWin=23, winSum=392
7734 16:44:32.492369 [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26
7735 16:44:32.492794
7736 16:44:32.495509 Final TX Range 0 Vref 26
7737 16:44:32.495932
7738 16:44:32.496266 ==
7739 16:44:32.498552 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 16:44:32.502236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 16:44:32.502661 ==
7742 16:44:32.502993
7743 16:44:32.503297
7744 16:44:32.505419 TX Vref Scan disable
7745 16:44:32.512274 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7746 16:44:32.512699 == TX Byte 0 ==
7747 16:44:32.515279 u2DelayCellOfst[0]=10 cells (3 PI)
7748 16:44:32.518603 u2DelayCellOfst[1]=13 cells (4 PI)
7749 16:44:32.522515 u2DelayCellOfst[2]=10 cells (3 PI)
7750 16:44:32.525165 u2DelayCellOfst[3]=10 cells (3 PI)
7751 16:44:32.529108 u2DelayCellOfst[4]=6 cells (2 PI)
7752 16:44:32.532257 u2DelayCellOfst[5]=0 cells (0 PI)
7753 16:44:32.532681 u2DelayCellOfst[6]=16 cells (5 PI)
7754 16:44:32.535583 u2DelayCellOfst[7]=16 cells (5 PI)
7755 16:44:32.541923 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7756 16:44:32.545337 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7757 16:44:32.545813 == TX Byte 1 ==
7758 16:44:32.548600 u2DelayCellOfst[8]=3 cells (1 PI)
7759 16:44:32.552353 u2DelayCellOfst[9]=0 cells (0 PI)
7760 16:44:32.555232 u2DelayCellOfst[10]=6 cells (2 PI)
7761 16:44:32.558966 u2DelayCellOfst[11]=6 cells (2 PI)
7762 16:44:32.562193 u2DelayCellOfst[12]=10 cells (3 PI)
7763 16:44:32.565328 u2DelayCellOfst[13]=13 cells (4 PI)
7764 16:44:32.568284 u2DelayCellOfst[14]=16 cells (5 PI)
7765 16:44:32.572045 u2DelayCellOfst[15]=10 cells (3 PI)
7766 16:44:32.575191 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7767 16:44:32.578944 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7768 16:44:32.582377 DramC Write-DBI on
7769 16:44:32.582798 ==
7770 16:44:32.585731 Dram Type= 6, Freq= 0, CH_0, rank 0
7771 16:44:32.588957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7772 16:44:32.589626 ==
7773 16:44:32.590262
7774 16:44:32.590736
7775 16:44:32.592215 TX Vref Scan disable
7776 16:44:32.595422 == TX Byte 0 ==
7777 16:44:32.598763 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7778 16:44:32.601785 == TX Byte 1 ==
7779 16:44:32.605305 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7780 16:44:32.605845 DramC Write-DBI off
7781 16:44:32.606267
7782 16:44:32.609038 [DATLAT]
7783 16:44:32.609863 Freq=1600, CH0 RK0
7784 16:44:32.610755
7785 16:44:32.611959 DATLAT Default: 0xf
7786 16:44:32.612443 0, 0xFFFF, sum = 0
7787 16:44:32.615622 1, 0xFFFF, sum = 0
7788 16:44:32.616155 2, 0xFFFF, sum = 0
7789 16:44:32.618507 3, 0xFFFF, sum = 0
7790 16:44:32.619057 4, 0xFFFF, sum = 0
7791 16:44:32.621736 5, 0xFFFF, sum = 0
7792 16:44:32.622324 6, 0xFFFF, sum = 0
7793 16:44:32.625398 7, 0xFFFF, sum = 0
7794 16:44:32.628823 8, 0xFFFF, sum = 0
7795 16:44:32.629340 9, 0xFFFF, sum = 0
7796 16:44:32.631763 10, 0xFFFF, sum = 0
7797 16:44:32.632302 11, 0xFFFF, sum = 0
7798 16:44:32.635287 12, 0xFFFF, sum = 0
7799 16:44:32.635814 13, 0xFFFF, sum = 0
7800 16:44:32.638422 14, 0x0, sum = 1
7801 16:44:32.638961 15, 0x0, sum = 2
7802 16:44:32.641723 16, 0x0, sum = 3
7803 16:44:32.642261 17, 0x0, sum = 4
7804 16:44:32.645550 best_step = 15
7805 16:44:32.646133
7806 16:44:32.646556 ==
7807 16:44:32.648090 Dram Type= 6, Freq= 0, CH_0, rank 0
7808 16:44:32.651439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7809 16:44:32.652020 ==
7810 16:44:32.652507 RX Vref Scan: 1
7811 16:44:32.654651
7812 16:44:32.655133 Set Vref Range= 24 -> 127
7813 16:44:32.655619
7814 16:44:32.658640 RX Vref 24 -> 127, step: 1
7815 16:44:32.659169
7816 16:44:32.661766 RX Delay 19 -> 252, step: 4
7817 16:44:32.662272
7818 16:44:32.664872 Set Vref, RX VrefLevel [Byte0]: 24
7819 16:44:32.668430 [Byte1]: 24
7820 16:44:32.668878
7821 16:44:32.671404 Set Vref, RX VrefLevel [Byte0]: 25
7822 16:44:32.674715 [Byte1]: 25
7823 16:44:32.675364
7824 16:44:32.678563 Set Vref, RX VrefLevel [Byte0]: 26
7825 16:44:32.681483 [Byte1]: 26
7826 16:44:32.685128
7827 16:44:32.685742 Set Vref, RX VrefLevel [Byte0]: 27
7828 16:44:32.688381 [Byte1]: 27
7829 16:44:32.693010
7830 16:44:32.693442 Set Vref, RX VrefLevel [Byte0]: 28
7831 16:44:32.696213 [Byte1]: 28
7832 16:44:32.700864
7833 16:44:32.701294 Set Vref, RX VrefLevel [Byte0]: 29
7834 16:44:32.703493 [Byte1]: 29
7835 16:44:32.707619
7836 16:44:32.707705 Set Vref, RX VrefLevel [Byte0]: 30
7837 16:44:32.711174 [Byte1]: 30
7838 16:44:32.715609
7839 16:44:32.715694 Set Vref, RX VrefLevel [Byte0]: 31
7840 16:44:32.718558 [Byte1]: 31
7841 16:44:32.722941
7842 16:44:32.723053 Set Vref, RX VrefLevel [Byte0]: 32
7843 16:44:32.726166 [Byte1]: 32
7844 16:44:32.730489
7845 16:44:32.730573 Set Vref, RX VrefLevel [Byte0]: 33
7846 16:44:32.733700 [Byte1]: 33
7847 16:44:32.738175
7848 16:44:32.738261 Set Vref, RX VrefLevel [Byte0]: 34
7849 16:44:32.741288 [Byte1]: 34
7850 16:44:32.745371
7851 16:44:32.745457 Set Vref, RX VrefLevel [Byte0]: 35
7852 16:44:32.748747 [Byte1]: 35
7853 16:44:32.753255
7854 16:44:32.753346 Set Vref, RX VrefLevel [Byte0]: 36
7855 16:44:32.756514 [Byte1]: 36
7856 16:44:32.760986
7857 16:44:32.761072 Set Vref, RX VrefLevel [Byte0]: 37
7858 16:44:32.764228 [Byte1]: 37
7859 16:44:32.768238
7860 16:44:32.768321 Set Vref, RX VrefLevel [Byte0]: 38
7861 16:44:32.771432 [Byte1]: 38
7862 16:44:32.775730
7863 16:44:32.775811 Set Vref, RX VrefLevel [Byte0]: 39
7864 16:44:32.779334 [Byte1]: 39
7865 16:44:32.783830
7866 16:44:32.783912 Set Vref, RX VrefLevel [Byte0]: 40
7867 16:44:32.786889 [Byte1]: 40
7868 16:44:32.791220
7869 16:44:32.791322 Set Vref, RX VrefLevel [Byte0]: 41
7870 16:44:32.794206 [Byte1]: 41
7871 16:44:32.798473
7872 16:44:32.798552 Set Vref, RX VrefLevel [Byte0]: 42
7873 16:44:32.801951 [Byte1]: 42
7874 16:44:32.806515
7875 16:44:32.806617 Set Vref, RX VrefLevel [Byte0]: 43
7876 16:44:32.809713 [Byte1]: 43
7877 16:44:32.813689
7878 16:44:32.813795 Set Vref, RX VrefLevel [Byte0]: 44
7879 16:44:32.816701 [Byte1]: 44
7880 16:44:32.821308
7881 16:44:32.821416 Set Vref, RX VrefLevel [Byte0]: 45
7882 16:44:32.824901 [Byte1]: 45
7883 16:44:32.829228
7884 16:44:32.829326 Set Vref, RX VrefLevel [Byte0]: 46
7885 16:44:32.832323 [Byte1]: 46
7886 16:44:32.836736
7887 16:44:32.836818 Set Vref, RX VrefLevel [Byte0]: 47
7888 16:44:32.839933 [Byte1]: 47
7889 16:44:32.843836
7890 16:44:32.843919 Set Vref, RX VrefLevel [Byte0]: 48
7891 16:44:32.847685 [Byte1]: 48
7892 16:44:32.851539
7893 16:44:32.851621 Set Vref, RX VrefLevel [Byte0]: 49
7894 16:44:32.854969 [Byte1]: 49
7895 16:44:32.859531
7896 16:44:32.859613 Set Vref, RX VrefLevel [Byte0]: 50
7897 16:44:32.862688 [Byte1]: 50
7898 16:44:32.866482
7899 16:44:32.866564 Set Vref, RX VrefLevel [Byte0]: 51
7900 16:44:32.870246 [Byte1]: 51
7901 16:44:32.874092
7902 16:44:32.874173 Set Vref, RX VrefLevel [Byte0]: 52
7903 16:44:32.877411 [Byte1]: 52
7904 16:44:32.881582
7905 16:44:32.881664 Set Vref, RX VrefLevel [Byte0]: 53
7906 16:44:32.885465 [Byte1]: 53
7907 16:44:32.889241
7908 16:44:32.889322 Set Vref, RX VrefLevel [Byte0]: 54
7909 16:44:32.893033 [Byte1]: 54
7910 16:44:32.896785
7911 16:44:32.896867 Set Vref, RX VrefLevel [Byte0]: 55
7912 16:44:32.900497 [Byte1]: 55
7913 16:44:32.904680
7914 16:44:32.904776 Set Vref, RX VrefLevel [Byte0]: 56
7915 16:44:32.907827 [Byte1]: 56
7916 16:44:32.912416
7917 16:44:32.912501 Set Vref, RX VrefLevel [Byte0]: 57
7918 16:44:32.915594 [Byte1]: 57
7919 16:44:32.919512
7920 16:44:32.919597 Set Vref, RX VrefLevel [Byte0]: 58
7921 16:44:32.923334 [Byte1]: 58
7922 16:44:32.927294
7923 16:44:32.927389 Set Vref, RX VrefLevel [Byte0]: 59
7924 16:44:32.930394 [Byte1]: 59
7925 16:44:32.935311
7926 16:44:32.935418 Set Vref, RX VrefLevel [Byte0]: 60
7927 16:44:32.938441 [Byte1]: 60
7928 16:44:32.942821
7929 16:44:32.942903 Set Vref, RX VrefLevel [Byte0]: 61
7930 16:44:32.946065 [Byte1]: 61
7931 16:44:32.950432
7932 16:44:32.950515 Set Vref, RX VrefLevel [Byte0]: 62
7933 16:44:32.953582 [Byte1]: 62
7934 16:44:32.957556
7935 16:44:32.957638 Set Vref, RX VrefLevel [Byte0]: 63
7936 16:44:32.960828 [Byte1]: 63
7937 16:44:32.965491
7938 16:44:32.965611 Set Vref, RX VrefLevel [Byte0]: 64
7939 16:44:32.968651 [Byte1]: 64
7940 16:44:32.972472
7941 16:44:32.972554 Set Vref, RX VrefLevel [Byte0]: 65
7942 16:44:32.976409 [Byte1]: 65
7943 16:44:32.980371
7944 16:44:32.980453 Set Vref, RX VrefLevel [Byte0]: 66
7945 16:44:32.983541 [Byte1]: 66
7946 16:44:32.988074
7947 16:44:32.988156 Set Vref, RX VrefLevel [Byte0]: 67
7948 16:44:32.991345 [Byte1]: 67
7949 16:44:32.995267
7950 16:44:32.995348 Set Vref, RX VrefLevel [Byte0]: 68
7951 16:44:32.998902 [Byte1]: 68
7952 16:44:33.002918
7953 16:44:33.003032 Set Vref, RX VrefLevel [Byte0]: 69
7954 16:44:33.006204 [Byte1]: 69
7955 16:44:33.010461
7956 16:44:33.010544 Set Vref, RX VrefLevel [Byte0]: 70
7957 16:44:33.013994 [Byte1]: 70
7958 16:44:33.017972
7959 16:44:33.018066 Set Vref, RX VrefLevel [Byte0]: 71
7960 16:44:33.021262 [Byte1]: 71
7961 16:44:33.025639
7962 16:44:33.025728 Set Vref, RX VrefLevel [Byte0]: 72
7963 16:44:33.028936 [Byte1]: 72
7964 16:44:33.033591
7965 16:44:33.033665 Set Vref, RX VrefLevel [Byte0]: 73
7966 16:44:33.036300 [Byte1]: 73
7967 16:44:33.040702
7968 16:44:33.040771 Set Vref, RX VrefLevel [Byte0]: 74
7969 16:44:33.043992 [Byte1]: 74
7970 16:44:33.048369
7971 16:44:33.048442 Final RX Vref Byte 0 = 57 to rank0
7972 16:44:33.051474 Final RX Vref Byte 1 = 60 to rank0
7973 16:44:33.055161 Final RX Vref Byte 0 = 57 to rank1
7974 16:44:33.058274 Final RX Vref Byte 1 = 60 to rank1==
7975 16:44:33.061408 Dram Type= 6, Freq= 0, CH_0, rank 0
7976 16:44:33.067992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 16:44:33.068076 ==
7978 16:44:33.068148 DQS Delay:
7979 16:44:33.071409 DQS0 = 0, DQS1 = 0
7980 16:44:33.071490 DQM Delay:
7981 16:44:33.071555 DQM0 = 134, DQM1 = 127
7982 16:44:33.074623 DQ Delay:
7983 16:44:33.078475 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7984 16:44:33.081625 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
7985 16:44:33.084966 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7986 16:44:33.088180 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7987 16:44:33.088261
7988 16:44:33.088325
7989 16:44:33.088384
7990 16:44:33.091370 [DramC_TX_OE_Calibration] TA2
7991 16:44:33.094588 Original DQ_B0 (3 6) =30, OEN = 27
7992 16:44:33.097945 Original DQ_B1 (3 6) =30, OEN = 27
7993 16:44:33.101061 24, 0x0, End_B0=24 End_B1=24
7994 16:44:33.101137 25, 0x0, End_B0=25 End_B1=25
7995 16:44:33.104348 26, 0x0, End_B0=26 End_B1=26
7996 16:44:33.108142 27, 0x0, End_B0=27 End_B1=27
7997 16:44:33.111317 28, 0x0, End_B0=28 End_B1=28
7998 16:44:33.114664 29, 0x0, End_B0=29 End_B1=29
7999 16:44:33.114747 30, 0x0, End_B0=30 End_B1=30
8000 16:44:33.117844 31, 0x4141, End_B0=30 End_B1=30
8001 16:44:33.121250 Byte0 end_step=30 best_step=27
8002 16:44:33.124231 Byte1 end_step=30 best_step=27
8003 16:44:33.128107 Byte0 TX OE(2T, 0.5T) = (3, 3)
8004 16:44:33.131473 Byte1 TX OE(2T, 0.5T) = (3, 3)
8005 16:44:33.131560
8006 16:44:33.131626
8007 16:44:33.137854 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
8008 16:44:33.141100 CH0 RK0: MR19=303, MR18=2722
8009 16:44:33.147701 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
8010 16:44:33.147803
8011 16:44:33.150662 ----->DramcWriteLeveling(PI) begin...
8012 16:44:33.150748 ==
8013 16:44:33.154290 Dram Type= 6, Freq= 0, CH_0, rank 1
8014 16:44:33.157366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 16:44:33.157469 ==
8016 16:44:33.160879 Write leveling (Byte 0): 37 => 37
8017 16:44:33.164193 Write leveling (Byte 1): 28 => 28
8018 16:44:33.167288 DramcWriteLeveling(PI) end<-----
8019 16:44:33.167389
8020 16:44:33.167483 ==
8021 16:44:33.170773 Dram Type= 6, Freq= 0, CH_0, rank 1
8022 16:44:33.174017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 16:44:33.174105 ==
8024 16:44:33.177235 [Gating] SW mode calibration
8025 16:44:33.184234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8026 16:44:33.190760 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8027 16:44:33.193896 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 16:44:33.200386 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 16:44:33.203634 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 16:44:33.207320 1 4 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
8031 16:44:33.213688 1 4 16 | B1->B0 | 3131 3535 | 0 0 | (1 1) (0 0)
8032 16:44:33.217467 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 16:44:33.220846 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8034 16:44:33.226978 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8035 16:44:33.230641 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 16:44:33.233884 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 16:44:33.240410 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (1 1)
8038 16:44:33.243637 1 5 12 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
8039 16:44:33.246953 1 5 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8040 16:44:33.250260 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8041 16:44:33.257102 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8042 16:44:33.260628 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8043 16:44:33.263736 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 16:44:33.270442 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8045 16:44:33.273719 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 16:44:33.276951 1 6 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (0 0)
8047 16:44:33.284035 1 6 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
8048 16:44:33.287267 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 16:44:33.290454 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8050 16:44:33.296992 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8051 16:44:33.300875 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 16:44:33.304040 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 16:44:33.310710 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 16:44:33.314074 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8055 16:44:33.317296 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8056 16:44:33.323763 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 16:44:33.326948 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 16:44:33.331123 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 16:44:33.337221 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 16:44:33.340142 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 16:44:33.343382 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 16:44:33.347324 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 16:44:33.353974 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 16:44:33.357106 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 16:44:33.360512 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 16:44:33.366671 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 16:44:33.370204 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 16:44:33.373275 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 16:44:33.380283 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 16:44:33.383403 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8071 16:44:33.386747 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 16:44:33.389926 Total UI for P1: 0, mck2ui 16
8073 16:44:33.393695 best dqsien dly found for B0: ( 1, 9, 12)
8074 16:44:33.400289 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 16:44:33.403529 Total UI for P1: 0, mck2ui 16
8076 16:44:33.406891 best dqsien dly found for B1: ( 1, 9, 14)
8077 16:44:33.410499 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8078 16:44:33.413677 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8079 16:44:33.414098
8080 16:44:33.417049 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8081 16:44:33.420308 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8082 16:44:33.423496 [Gating] SW calibration Done
8083 16:44:33.423918 ==
8084 16:44:33.427233 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 16:44:33.430417 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 16:44:33.430879 ==
8087 16:44:33.433583 RX Vref Scan: 0
8088 16:44:33.434120
8089 16:44:33.436635 RX Vref 0 -> 0, step: 1
8090 16:44:33.437178
8091 16:44:33.437572 RX Delay 0 -> 252, step: 8
8092 16:44:33.443722 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8093 16:44:33.446752 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8094 16:44:33.449933 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8095 16:44:33.453342 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8096 16:44:33.456695 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8097 16:44:33.459954 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8098 16:44:33.466594 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8099 16:44:33.470409 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8100 16:44:33.473740 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8101 16:44:33.476937 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8102 16:44:33.479958 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8103 16:44:33.486650 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8104 16:44:33.490336 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8105 16:44:33.493548 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8106 16:44:33.496541 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8107 16:44:33.503579 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8108 16:44:33.504051 ==
8109 16:44:33.506933 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 16:44:33.510112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 16:44:33.510670 ==
8112 16:44:33.511054 DQS Delay:
8113 16:44:33.513507 DQS0 = 0, DQS1 = 0
8114 16:44:33.513989 DQM Delay:
8115 16:44:33.516719 DQM0 = 136, DQM1 = 128
8116 16:44:33.517139 DQ Delay:
8117 16:44:33.519935 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8118 16:44:33.523075 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8119 16:44:33.526365 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8120 16:44:33.529740 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8121 16:44:33.529822
8122 16:44:33.529886
8123 16:44:33.529944 ==
8124 16:44:33.533324 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 16:44:33.539965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 16:44:33.540048 ==
8127 16:44:33.540112
8128 16:44:33.540171
8129 16:44:33.540227 TX Vref Scan disable
8130 16:44:33.543955 == TX Byte 0 ==
8131 16:44:33.547116 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8132 16:44:33.553444 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8133 16:44:33.553568 == TX Byte 1 ==
8134 16:44:33.556577 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8135 16:44:33.563709 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8136 16:44:33.563791 ==
8137 16:44:33.567013 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 16:44:33.570098 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 16:44:33.570181 ==
8140 16:44:33.583387
8141 16:44:33.586817 TX Vref early break, caculate TX vref
8142 16:44:33.590414 TX Vref=16, minBit 1, minWin=23, winSum=387
8143 16:44:33.593468 TX Vref=18, minBit 1, minWin=23, winSum=396
8144 16:44:33.597139 TX Vref=20, minBit 0, minWin=24, winSum=405
8145 16:44:33.600242 TX Vref=22, minBit 1, minWin=24, winSum=412
8146 16:44:33.603220 TX Vref=24, minBit 1, minWin=25, winSum=416
8147 16:44:33.609957 TX Vref=26, minBit 2, minWin=25, winSum=424
8148 16:44:33.613295 TX Vref=28, minBit 1, minWin=25, winSum=424
8149 16:44:33.616441 TX Vref=30, minBit 0, minWin=26, winSum=422
8150 16:44:33.619652 TX Vref=32, minBit 4, minWin=24, winSum=414
8151 16:44:33.623453 TX Vref=34, minBit 0, minWin=24, winSum=401
8152 16:44:33.630020 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
8153 16:44:33.630103
8154 16:44:33.633403 Final TX Range 0 Vref 30
8155 16:44:33.633485
8156 16:44:33.633556 ==
8157 16:44:33.636713 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 16:44:33.639690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 16:44:33.639777 ==
8160 16:44:33.639863
8161 16:44:33.639948
8162 16:44:33.642846 TX Vref Scan disable
8163 16:44:33.649742 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8164 16:44:33.649833 == TX Byte 0 ==
8165 16:44:33.653212 u2DelayCellOfst[0]=10 cells (3 PI)
8166 16:44:33.656447 u2DelayCellOfst[1]=13 cells (4 PI)
8167 16:44:33.659632 u2DelayCellOfst[2]=10 cells (3 PI)
8168 16:44:33.662911 u2DelayCellOfst[3]=10 cells (3 PI)
8169 16:44:33.666070 u2DelayCellOfst[4]=6 cells (2 PI)
8170 16:44:33.669380 u2DelayCellOfst[5]=0 cells (0 PI)
8171 16:44:33.672693 u2DelayCellOfst[6]=13 cells (4 PI)
8172 16:44:33.675947 u2DelayCellOfst[7]=13 cells (4 PI)
8173 16:44:33.679261 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8174 16:44:33.682540 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8175 16:44:33.686299 == TX Byte 1 ==
8176 16:44:33.689496 u2DelayCellOfst[8]=0 cells (0 PI)
8177 16:44:33.689616 u2DelayCellOfst[9]=0 cells (0 PI)
8178 16:44:33.692743 u2DelayCellOfst[10]=6 cells (2 PI)
8179 16:44:33.696009 u2DelayCellOfst[11]=3 cells (1 PI)
8180 16:44:33.699120 u2DelayCellOfst[12]=13 cells (4 PI)
8181 16:44:33.702696 u2DelayCellOfst[13]=10 cells (3 PI)
8182 16:44:33.705958 u2DelayCellOfst[14]=13 cells (4 PI)
8183 16:44:33.709681 u2DelayCellOfst[15]=10 cells (3 PI)
8184 16:44:33.712801 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8185 16:44:33.719113 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8186 16:44:33.719221 DramC Write-DBI on
8187 16:44:33.719318 ==
8188 16:44:33.722396 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 16:44:33.729695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 16:44:33.730129 ==
8191 16:44:33.730474
8192 16:44:33.730789
8193 16:44:33.731096 TX Vref Scan disable
8194 16:44:33.733787 == TX Byte 0 ==
8195 16:44:33.736999 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8196 16:44:33.740429 == TX Byte 1 ==
8197 16:44:33.743833 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8198 16:44:33.747223 DramC Write-DBI off
8199 16:44:33.747799
8200 16:44:33.748310 [DATLAT]
8201 16:44:33.748781 Freq=1600, CH0 RK1
8202 16:44:33.749238
8203 16:44:33.750304 DATLAT Default: 0xf
8204 16:44:33.750878 0, 0xFFFF, sum = 0
8205 16:44:33.753353 1, 0xFFFF, sum = 0
8206 16:44:33.753825 2, 0xFFFF, sum = 0
8207 16:44:33.757259 3, 0xFFFF, sum = 0
8208 16:44:33.760369 4, 0xFFFF, sum = 0
8209 16:44:33.761075 5, 0xFFFF, sum = 0
8210 16:44:33.763546 6, 0xFFFF, sum = 0
8211 16:44:33.764170 7, 0xFFFF, sum = 0
8212 16:44:33.766744 8, 0xFFFF, sum = 0
8213 16:44:33.767377 9, 0xFFFF, sum = 0
8214 16:44:33.769936 10, 0xFFFF, sum = 0
8215 16:44:33.770578 11, 0xFFFF, sum = 0
8216 16:44:33.773722 12, 0xFFFF, sum = 0
8217 16:44:33.774374 13, 0xFFFF, sum = 0
8218 16:44:33.776841 14, 0x0, sum = 1
8219 16:44:33.777436 15, 0x0, sum = 2
8220 16:44:33.780098 16, 0x0, sum = 3
8221 16:44:33.780834 17, 0x0, sum = 4
8222 16:44:33.783243 best_step = 15
8223 16:44:33.783912
8224 16:44:33.784517 ==
8225 16:44:33.786481 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 16:44:33.789777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 16:44:33.790383 ==
8228 16:44:33.791025 RX Vref Scan: 0
8229 16:44:33.793578
8230 16:44:33.794187 RX Vref 0 -> 0, step: 1
8231 16:44:33.794732
8232 16:44:33.796787 RX Delay 19 -> 252, step: 4
8233 16:44:33.800035 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8234 16:44:33.806726 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8235 16:44:33.809694 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8236 16:44:33.813448 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8237 16:44:33.816576 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8238 16:44:33.820285 iDelay=191, Bit 5, Center 128 (75 ~ 182) 108
8239 16:44:33.826847 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8240 16:44:33.830016 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8241 16:44:33.833361 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8242 16:44:33.836776 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8243 16:44:33.840023 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8244 16:44:33.846433 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8245 16:44:33.849681 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8246 16:44:33.852931 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8247 16:44:33.856659 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8248 16:44:33.859736 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8249 16:44:33.862784 ==
8250 16:44:33.862896 Dram Type= 6, Freq= 0, CH_0, rank 1
8251 16:44:33.869655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8252 16:44:33.869767 ==
8253 16:44:33.869862 DQS Delay:
8254 16:44:33.872861 DQS0 = 0, DQS1 = 0
8255 16:44:33.872959 DQM Delay:
8256 16:44:33.876068 DQM0 = 135, DQM1 = 127
8257 16:44:33.876153 DQ Delay:
8258 16:44:33.879197 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8259 16:44:33.882340 DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =140
8260 16:44:33.886198 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =118
8261 16:44:33.889542 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8262 16:44:33.889643
8263 16:44:33.889737
8264 16:44:33.889826
8265 16:44:33.892824 [DramC_TX_OE_Calibration] TA2
8266 16:44:33.896050 Original DQ_B0 (3 6) =30, OEN = 27
8267 16:44:33.899228 Original DQ_B1 (3 6) =30, OEN = 27
8268 16:44:33.902514 24, 0x0, End_B0=24 End_B1=24
8269 16:44:33.905756 25, 0x0, End_B0=25 End_B1=25
8270 16:44:33.905832 26, 0x0, End_B0=26 End_B1=26
8271 16:44:33.908903 27, 0x0, End_B0=27 End_B1=27
8272 16:44:33.912054 28, 0x0, End_B0=28 End_B1=28
8273 16:44:33.915776 29, 0x0, End_B0=29 End_B1=29
8274 16:44:33.918822 30, 0x0, End_B0=30 End_B1=30
8275 16:44:33.918931 31, 0x4141, End_B0=30 End_B1=30
8276 16:44:33.922165 Byte0 end_step=30 best_step=27
8277 16:44:33.925894 Byte1 end_step=30 best_step=27
8278 16:44:33.928819 Byte0 TX OE(2T, 0.5T) = (3, 3)
8279 16:44:33.932515 Byte1 TX OE(2T, 0.5T) = (3, 3)
8280 16:44:33.932622
8281 16:44:33.932714
8282 16:44:33.939130 [DQSOSCAuto] RK1, (LSB)MR18= 0x230b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8283 16:44:33.942316 CH0 RK1: MR19=303, MR18=230B
8284 16:44:33.948950 CH0_RK1: MR19=0x303, MR18=0x230B, DQSOSC=392, MR23=63, INC=24, DEC=16
8285 16:44:33.952073 [RxdqsGatingPostProcess] freq 1600
8286 16:44:33.958689 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8287 16:44:33.958797 best DQS0 dly(2T, 0.5T) = (1, 1)
8288 16:44:33.961962 best DQS1 dly(2T, 0.5T) = (1, 1)
8289 16:44:33.965597 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8290 16:44:33.969321 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8291 16:44:33.972296 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 16:44:33.975654 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 16:44:33.978936 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 16:44:33.982124 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 16:44:33.985393 Pre-setting of DQS Precalculation
8296 16:44:33.988456 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8297 16:44:33.988559 ==
8298 16:44:33.992425 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 16:44:33.998384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 16:44:33.998464 ==
8301 16:44:34.002228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8302 16:44:34.008701 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8303 16:44:34.011922 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8304 16:44:34.018303 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8305 16:44:34.026282 [CA 0] Center 41 (11~71) winsize 61
8306 16:44:34.029338 [CA 1] Center 41 (12~71) winsize 60
8307 16:44:34.033044 [CA 2] Center 38 (9~68) winsize 60
8308 16:44:34.036466 [CA 3] Center 37 (8~66) winsize 59
8309 16:44:34.039228 [CA 4] Center 37 (8~67) winsize 60
8310 16:44:34.042771 [CA 5] Center 36 (7~66) winsize 60
8311 16:44:34.042866
8312 16:44:34.045889 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8313 16:44:34.045959
8314 16:44:34.049656 [CATrainingPosCal] consider 1 rank data
8315 16:44:34.052943 u2DelayCellTimex100 = 290/100 ps
8316 16:44:34.056313 CA0 delay=41 (11~71),Diff = 5 PI (16 cell)
8317 16:44:34.062931 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8318 16:44:34.066179 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8319 16:44:34.069450 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8320 16:44:34.072523 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8321 16:44:34.076155 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8322 16:44:34.076266
8323 16:44:34.079703 CA PerBit enable=1, Macro0, CA PI delay=36
8324 16:44:34.079789
8325 16:44:34.082960 [CBTSetCACLKResult] CA Dly = 36
8326 16:44:34.086150 CS Dly: 11 (0~42)
8327 16:44:34.089323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8328 16:44:34.092611 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8329 16:44:34.092702 ==
8330 16:44:34.096295 Dram Type= 6, Freq= 0, CH_1, rank 1
8331 16:44:34.099760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8332 16:44:34.099837 ==
8333 16:44:34.106111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8334 16:44:34.109350 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8335 16:44:34.115808 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8336 16:44:34.119036 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8337 16:44:34.129680 [CA 0] Center 42 (12~72) winsize 61
8338 16:44:34.132705 [CA 1] Center 42 (12~72) winsize 61
8339 16:44:34.136258 [CA 2] Center 38 (9~68) winsize 60
8340 16:44:34.139523 [CA 3] Center 38 (8~68) winsize 61
8341 16:44:34.142500 [CA 4] Center 38 (8~68) winsize 61
8342 16:44:34.146056 [CA 5] Center 37 (8~66) winsize 59
8343 16:44:34.146167
8344 16:44:34.149169 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8345 16:44:34.149291
8346 16:44:34.152699 [CATrainingPosCal] consider 2 rank data
8347 16:44:34.155649 u2DelayCellTimex100 = 290/100 ps
8348 16:44:34.159226 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8349 16:44:34.166090 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8350 16:44:34.169367 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8351 16:44:34.172621 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8352 16:44:34.175984 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8353 16:44:34.179122 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8354 16:44:34.179206
8355 16:44:34.182906 CA PerBit enable=1, Macro0, CA PI delay=37
8356 16:44:34.182989
8357 16:44:34.185929 [CBTSetCACLKResult] CA Dly = 37
8358 16:44:34.189581 CS Dly: 12 (0~45)
8359 16:44:34.192610 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8360 16:44:34.195866 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8361 16:44:34.195958
8362 16:44:34.199032 ----->DramcWriteLeveling(PI) begin...
8363 16:44:34.199109 ==
8364 16:44:34.202266 Dram Type= 6, Freq= 0, CH_1, rank 0
8365 16:44:34.206049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8366 16:44:34.209314 ==
8367 16:44:34.209387 Write leveling (Byte 0): 26 => 26
8368 16:44:34.212735 Write leveling (Byte 1): 28 => 28
8369 16:44:34.216109 DramcWriteLeveling(PI) end<-----
8370 16:44:34.216222
8371 16:44:34.216288 ==
8372 16:44:34.219340 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 16:44:34.226147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 16:44:34.226242 ==
8375 16:44:34.226320 [Gating] SW mode calibration
8376 16:44:34.236072 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8377 16:44:34.239195 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8378 16:44:34.243029 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 16:44:34.249505 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 16:44:34.252543 1 4 8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (1 1)
8381 16:44:34.255928 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 16:44:34.263072 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 16:44:34.266167 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 16:44:34.269419 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 16:44:34.276028 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 16:44:34.279289 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 16:44:34.283035 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 16:44:34.289599 1 5 8 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (0 0)
8389 16:44:34.292788 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8390 16:44:34.295972 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8391 16:44:34.302887 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 16:44:34.306057 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 16:44:34.309224 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 16:44:34.316388 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 16:44:34.319497 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 16:44:34.322776 1 6 8 | B1->B0 | 2424 3a39 | 0 1 | (0 0) (0 0)
8397 16:44:34.326117 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8398 16:44:34.332509 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 16:44:34.335877 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 16:44:34.339195 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 16:44:34.346435 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 16:44:34.349573 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 16:44:34.352776 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 16:44:34.359344 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8405 16:44:34.362379 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8406 16:44:34.366122 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 16:44:34.372522 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 16:44:34.375530 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 16:44:34.378914 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 16:44:34.385872 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 16:44:34.389051 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 16:44:34.392391 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 16:44:34.398741 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 16:44:34.402606 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 16:44:34.405568 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 16:44:34.412768 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 16:44:34.415886 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 16:44:34.419167 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 16:44:34.425538 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 16:44:34.428671 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8421 16:44:34.432026 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8422 16:44:34.439259 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 16:44:34.439348 Total UI for P1: 0, mck2ui 16
8424 16:44:34.442504 best dqsien dly found for B0: ( 1, 9, 12)
8425 16:44:34.445817 Total UI for P1: 0, mck2ui 16
8426 16:44:34.449172 best dqsien dly found for B1: ( 1, 9, 10)
8427 16:44:34.452390 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8428 16:44:34.458890 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8429 16:44:34.458971
8430 16:44:34.462009 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8431 16:44:34.465527 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8432 16:44:34.468653 [Gating] SW calibration Done
8433 16:44:34.468732 ==
8434 16:44:34.471892 Dram Type= 6, Freq= 0, CH_1, rank 0
8435 16:44:34.475657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8436 16:44:34.475767 ==
8437 16:44:34.478767 RX Vref Scan: 0
8438 16:44:34.478850
8439 16:44:34.478979 RX Vref 0 -> 0, step: 1
8440 16:44:34.479038
8441 16:44:34.482134 RX Delay 0 -> 252, step: 8
8442 16:44:34.485361 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8443 16:44:34.488539 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8444 16:44:34.495575 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8445 16:44:34.498861 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8446 16:44:34.502177 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8447 16:44:34.505317 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8448 16:44:34.508657 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8449 16:44:34.515045 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8450 16:44:34.518541 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8451 16:44:34.521846 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8452 16:44:34.525394 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8453 16:44:34.528485 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8454 16:44:34.535437 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8455 16:44:34.538717 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8456 16:44:34.541877 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8457 16:44:34.545104 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8458 16:44:34.545206 ==
8459 16:44:34.548325 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 16:44:34.554827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 16:44:34.554929 ==
8462 16:44:34.555022 DQS Delay:
8463 16:44:34.558694 DQS0 = 0, DQS1 = 0
8464 16:44:34.558795 DQM Delay:
8465 16:44:34.562052 DQM0 = 136, DQM1 = 133
8466 16:44:34.562126 DQ Delay:
8467 16:44:34.565404 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8468 16:44:34.568520 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8469 16:44:34.571549 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8470 16:44:34.575189 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8471 16:44:34.575287
8472 16:44:34.575380
8473 16:44:34.575466 ==
8474 16:44:34.578022 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 16:44:34.582044 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 16:44:34.584986 ==
8477 16:44:34.585099
8478 16:44:34.585196
8479 16:44:34.585293 TX Vref Scan disable
8480 16:44:34.588485 == TX Byte 0 ==
8481 16:44:34.591540 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8482 16:44:34.595122 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8483 16:44:34.598412 == TX Byte 1 ==
8484 16:44:34.601538 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8485 16:44:34.604774 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8486 16:44:34.608823 ==
8487 16:44:34.608905 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 16:44:34.614811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 16:44:34.614921 ==
8490 16:44:34.626717
8491 16:44:34.630420 TX Vref early break, caculate TX vref
8492 16:44:34.633517 TX Vref=16, minBit 0, minWin=22, winSum=372
8493 16:44:34.636690 TX Vref=18, minBit 1, minWin=23, winSum=382
8494 16:44:34.639753 TX Vref=20, minBit 0, minWin=24, winSum=396
8495 16:44:34.643607 TX Vref=22, minBit 0, minWin=24, winSum=402
8496 16:44:34.646337 TX Vref=24, minBit 1, minWin=24, winSum=413
8497 16:44:34.653398 TX Vref=26, minBit 0, minWin=25, winSum=423
8498 16:44:34.656772 TX Vref=28, minBit 0, minWin=25, winSum=426
8499 16:44:34.659927 TX Vref=30, minBit 0, minWin=25, winSum=418
8500 16:44:34.663232 TX Vref=32, minBit 0, minWin=24, winSum=409
8501 16:44:34.666576 TX Vref=34, minBit 0, minWin=24, winSum=400
8502 16:44:34.673711 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 28
8503 16:44:34.673827
8504 16:44:34.676878 Final TX Range 0 Vref 28
8505 16:44:34.676991
8506 16:44:34.677081 ==
8507 16:44:34.680053 Dram Type= 6, Freq= 0, CH_1, rank 0
8508 16:44:34.683143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8509 16:44:34.683266 ==
8510 16:44:34.683359
8511 16:44:34.683460
8512 16:44:34.686304 TX Vref Scan disable
8513 16:44:34.693119 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8514 16:44:34.693233 == TX Byte 0 ==
8515 16:44:34.696616 u2DelayCellOfst[0]=20 cells (6 PI)
8516 16:44:34.700132 u2DelayCellOfst[1]=13 cells (4 PI)
8517 16:44:34.703099 u2DelayCellOfst[2]=0 cells (0 PI)
8518 16:44:34.706598 u2DelayCellOfst[3]=10 cells (3 PI)
8519 16:44:34.709976 u2DelayCellOfst[4]=10 cells (3 PI)
8520 16:44:34.713087 u2DelayCellOfst[5]=20 cells (6 PI)
8521 16:44:34.716492 u2DelayCellOfst[6]=20 cells (6 PI)
8522 16:44:34.716600 u2DelayCellOfst[7]=10 cells (3 PI)
8523 16:44:34.723024 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8524 16:44:34.726900 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8525 16:44:34.727017 == TX Byte 1 ==
8526 16:44:34.730168 u2DelayCellOfst[8]=0 cells (0 PI)
8527 16:44:34.733090 u2DelayCellOfst[9]=3 cells (1 PI)
8528 16:44:34.736225 u2DelayCellOfst[10]=10 cells (3 PI)
8529 16:44:34.740258 u2DelayCellOfst[11]=3 cells (1 PI)
8530 16:44:34.743311 u2DelayCellOfst[12]=13 cells (4 PI)
8531 16:44:34.746568 u2DelayCellOfst[13]=16 cells (5 PI)
8532 16:44:34.749504 u2DelayCellOfst[14]=16 cells (5 PI)
8533 16:44:34.753369 u2DelayCellOfst[15]=16 cells (5 PI)
8534 16:44:34.756676 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8535 16:44:34.763330 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8536 16:44:34.763442 DramC Write-DBI on
8537 16:44:34.763539 ==
8538 16:44:34.766800 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 16:44:34.770134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 16:44:34.770209 ==
8541 16:44:34.773393
8542 16:44:34.773489
8543 16:44:34.773620 TX Vref Scan disable
8544 16:44:34.776690 == TX Byte 0 ==
8545 16:44:34.779989 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8546 16:44:34.783208 == TX Byte 1 ==
8547 16:44:34.786393 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8548 16:44:34.786465 DramC Write-DBI off
8549 16:44:34.786526
8550 16:44:34.789533 [DATLAT]
8551 16:44:34.789617 Freq=1600, CH1 RK0
8552 16:44:34.789677
8553 16:44:34.793433 DATLAT Default: 0xf
8554 16:44:34.793562 0, 0xFFFF, sum = 0
8555 16:44:34.796595 1, 0xFFFF, sum = 0
8556 16:44:34.796679 2, 0xFFFF, sum = 0
8557 16:44:34.799673 3, 0xFFFF, sum = 0
8558 16:44:34.799748 4, 0xFFFF, sum = 0
8559 16:44:34.803445 5, 0xFFFF, sum = 0
8560 16:44:34.806585 6, 0xFFFF, sum = 0
8561 16:44:34.806659 7, 0xFFFF, sum = 0
8562 16:44:34.809623 8, 0xFFFF, sum = 0
8563 16:44:34.809699 9, 0xFFFF, sum = 0
8564 16:44:34.813276 10, 0xFFFF, sum = 0
8565 16:44:34.813374 11, 0xFFFF, sum = 0
8566 16:44:34.816477 12, 0xFFFF, sum = 0
8567 16:44:34.816585 13, 0xFFFF, sum = 0
8568 16:44:34.819728 14, 0x0, sum = 1
8569 16:44:34.819833 15, 0x0, sum = 2
8570 16:44:34.823103 16, 0x0, sum = 3
8571 16:44:34.823201 17, 0x0, sum = 4
8572 16:44:34.826428 best_step = 15
8573 16:44:34.826527
8574 16:44:34.826616 ==
8575 16:44:34.829735 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 16:44:34.832819 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 16:44:34.832918 ==
8578 16:44:34.833007 RX Vref Scan: 1
8579 16:44:34.836135
8580 16:44:34.836230 Set Vref Range= 24 -> 127
8581 16:44:34.836320
8582 16:44:34.839346 RX Vref 24 -> 127, step: 1
8583 16:44:34.839445
8584 16:44:34.842546 RX Delay 27 -> 252, step: 4
8585 16:44:34.842643
8586 16:44:34.846334 Set Vref, RX VrefLevel [Byte0]: 24
8587 16:44:34.849598 [Byte1]: 24
8588 16:44:34.849669
8589 16:44:34.852897 Set Vref, RX VrefLevel [Byte0]: 25
8590 16:44:34.856116 [Byte1]: 25
8591 16:44:34.856212
8592 16:44:34.859801 Set Vref, RX VrefLevel [Byte0]: 26
8593 16:44:34.863135 [Byte1]: 26
8594 16:44:34.866428
8595 16:44:34.866510 Set Vref, RX VrefLevel [Byte0]: 27
8596 16:44:34.869806 [Byte1]: 27
8597 16:44:34.874472
8598 16:44:34.874576 Set Vref, RX VrefLevel [Byte0]: 28
8599 16:44:34.877533 [Byte1]: 28
8600 16:44:34.881370
8601 16:44:34.881468 Set Vref, RX VrefLevel [Byte0]: 29
8602 16:44:34.884697 [Byte1]: 29
8603 16:44:34.889134
8604 16:44:34.889237 Set Vref, RX VrefLevel [Byte0]: 30
8605 16:44:34.892285 [Byte1]: 30
8606 16:44:34.896752
8607 16:44:34.896826 Set Vref, RX VrefLevel [Byte0]: 31
8608 16:44:34.899965 [Byte1]: 31
8609 16:44:34.904100
8610 16:44:34.904202 Set Vref, RX VrefLevel [Byte0]: 32
8611 16:44:34.907415 [Byte1]: 32
8612 16:44:34.911714
8613 16:44:34.911814 Set Vref, RX VrefLevel [Byte0]: 33
8614 16:44:34.915093 [Byte1]: 33
8615 16:44:34.919421
8616 16:44:34.919502 Set Vref, RX VrefLevel [Byte0]: 34
8617 16:44:34.922785 [Byte1]: 34
8618 16:44:34.926639
8619 16:44:34.926736 Set Vref, RX VrefLevel [Byte0]: 35
8620 16:44:34.929960 [Byte1]: 35
8621 16:44:34.934467
8622 16:44:34.934572 Set Vref, RX VrefLevel [Byte0]: 36
8623 16:44:34.937487 [Byte1]: 36
8624 16:44:34.942103
8625 16:44:34.942189 Set Vref, RX VrefLevel [Byte0]: 37
8626 16:44:34.945409 [Byte1]: 37
8627 16:44:34.949217
8628 16:44:34.949327 Set Vref, RX VrefLevel [Byte0]: 38
8629 16:44:34.952370 [Byte1]: 38
8630 16:44:34.956680
8631 16:44:34.956772 Set Vref, RX VrefLevel [Byte0]: 39
8632 16:44:34.959895 [Byte1]: 39
8633 16:44:34.964402
8634 16:44:34.964479 Set Vref, RX VrefLevel [Byte0]: 40
8635 16:44:34.968124 [Byte1]: 40
8636 16:44:34.971990
8637 16:44:34.972063 Set Vref, RX VrefLevel [Byte0]: 41
8638 16:44:34.975308 [Byte1]: 41
8639 16:44:34.979220
8640 16:44:34.979293 Set Vref, RX VrefLevel [Byte0]: 42
8641 16:44:34.982415 [Byte1]: 42
8642 16:44:34.987137
8643 16:44:34.987242 Set Vref, RX VrefLevel [Byte0]: 43
8644 16:44:34.990438 [Byte1]: 43
8645 16:44:34.994921
8646 16:44:34.995020 Set Vref, RX VrefLevel [Byte0]: 44
8647 16:44:34.997490 [Byte1]: 44
8648 16:44:35.002164
8649 16:44:35.002242 Set Vref, RX VrefLevel [Byte0]: 45
8650 16:44:35.005070 [Byte1]: 45
8651 16:44:35.009406
8652 16:44:35.009503 Set Vref, RX VrefLevel [Byte0]: 46
8653 16:44:35.012624 [Byte1]: 46
8654 16:44:35.017028
8655 16:44:35.017112 Set Vref, RX VrefLevel [Byte0]: 47
8656 16:44:35.020695 [Byte1]: 47
8657 16:44:35.024549
8658 16:44:35.024657 Set Vref, RX VrefLevel [Byte0]: 48
8659 16:44:35.027756 [Byte1]: 48
8660 16:44:35.032159
8661 16:44:35.032262 Set Vref, RX VrefLevel [Byte0]: 49
8662 16:44:35.035476 [Byte1]: 49
8663 16:44:35.039752
8664 16:44:35.039853 Set Vref, RX VrefLevel [Byte0]: 50
8665 16:44:35.042934 [Byte1]: 50
8666 16:44:35.046938
8667 16:44:35.047037 Set Vref, RX VrefLevel [Byte0]: 51
8668 16:44:35.050444 [Byte1]: 51
8669 16:44:35.054607
8670 16:44:35.054686 Set Vref, RX VrefLevel [Byte0]: 52
8671 16:44:35.057737 [Byte1]: 52
8672 16:44:35.062250
8673 16:44:35.062358 Set Vref, RX VrefLevel [Byte0]: 53
8674 16:44:35.065317 [Byte1]: 53
8675 16:44:35.069888
8676 16:44:35.069999 Set Vref, RX VrefLevel [Byte0]: 54
8677 16:44:35.073007 [Byte1]: 54
8678 16:44:35.077432
8679 16:44:35.077583 Set Vref, RX VrefLevel [Byte0]: 55
8680 16:44:35.080553 [Byte1]: 55
8681 16:44:35.084518
8682 16:44:35.084615 Set Vref, RX VrefLevel [Byte0]: 56
8683 16:44:35.088416 [Byte1]: 56
8684 16:44:35.092386
8685 16:44:35.092495 Set Vref, RX VrefLevel [Byte0]: 57
8686 16:44:35.095643 [Byte1]: 57
8687 16:44:35.100034
8688 16:44:35.100136 Set Vref, RX VrefLevel [Byte0]: 58
8689 16:44:35.103438 [Byte1]: 58
8690 16:44:35.107327
8691 16:44:35.107426 Set Vref, RX VrefLevel [Byte0]: 59
8692 16:44:35.110555 [Byte1]: 59
8693 16:44:35.115009
8694 16:44:35.115116 Set Vref, RX VrefLevel [Byte0]: 60
8695 16:44:35.118138 [Byte1]: 60
8696 16:44:35.122258
8697 16:44:35.122338 Set Vref, RX VrefLevel [Byte0]: 61
8698 16:44:35.125915 [Byte1]: 61
8699 16:44:35.129836
8700 16:44:35.129916 Set Vref, RX VrefLevel [Byte0]: 62
8701 16:44:35.133484 [Byte1]: 62
8702 16:44:35.137913
8703 16:44:35.138014 Set Vref, RX VrefLevel [Byte0]: 63
8704 16:44:35.141077 [Byte1]: 63
8705 16:44:35.144913
8706 16:44:35.145011 Set Vref, RX VrefLevel [Byte0]: 64
8707 16:44:35.148768 [Byte1]: 64
8708 16:44:35.152842
8709 16:44:35.152949 Set Vref, RX VrefLevel [Byte0]: 65
8710 16:44:35.156062 [Byte1]: 65
8711 16:44:35.159944
8712 16:44:35.160046 Set Vref, RX VrefLevel [Byte0]: 66
8713 16:44:35.163550 [Byte1]: 66
8714 16:44:35.167904
8715 16:44:35.168004 Set Vref, RX VrefLevel [Byte0]: 67
8716 16:44:35.171005 [Byte1]: 67
8717 16:44:35.175328
8718 16:44:35.175430 Set Vref, RX VrefLevel [Byte0]: 68
8719 16:44:35.178680 [Byte1]: 68
8720 16:44:35.183197
8721 16:44:35.183311 Set Vref, RX VrefLevel [Byte0]: 69
8722 16:44:35.185773 [Byte1]: 69
8723 16:44:35.190308
8724 16:44:35.190408 Set Vref, RX VrefLevel [Byte0]: 70
8725 16:44:35.193555 [Byte1]: 70
8726 16:44:35.198173
8727 16:44:35.198274 Set Vref, RX VrefLevel [Byte0]: 71
8728 16:44:35.201394 [Byte1]: 71
8729 16:44:35.205284
8730 16:44:35.205397 Set Vref, RX VrefLevel [Byte0]: 72
8731 16:44:35.208609 [Byte1]: 72
8732 16:44:35.213072
8733 16:44:35.213186 Set Vref, RX VrefLevel [Byte0]: 73
8734 16:44:35.216421 [Byte1]: 73
8735 16:44:35.220358
8736 16:44:35.220473 Set Vref, RX VrefLevel [Byte0]: 74
8737 16:44:35.223551 [Byte1]: 74
8738 16:44:35.227853
8739 16:44:35.227954 Final RX Vref Byte 0 = 57 to rank0
8740 16:44:35.231345 Final RX Vref Byte 1 = 57 to rank0
8741 16:44:35.234407 Final RX Vref Byte 0 = 57 to rank1
8742 16:44:35.237643 Final RX Vref Byte 1 = 57 to rank1==
8743 16:44:35.241263 Dram Type= 6, Freq= 0, CH_1, rank 0
8744 16:44:35.247793 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 16:44:35.247876 ==
8746 16:44:35.247941 DQS Delay:
8747 16:44:35.248000 DQS0 = 0, DQS1 = 0
8748 16:44:35.250851 DQM Delay:
8749 16:44:35.250932 DQM0 = 133, DQM1 = 131
8750 16:44:35.254154 DQ Delay:
8751 16:44:35.258072 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8752 16:44:35.261286 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8753 16:44:35.264715 DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122
8754 16:44:35.267998 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8755 16:44:35.268102
8756 16:44:35.268181
8757 16:44:35.268305
8758 16:44:35.271270 [DramC_TX_OE_Calibration] TA2
8759 16:44:35.274267 Original DQ_B0 (3 6) =30, OEN = 27
8760 16:44:35.278132 Original DQ_B1 (3 6) =30, OEN = 27
8761 16:44:35.281199 24, 0x0, End_B0=24 End_B1=24
8762 16:44:35.281300 25, 0x0, End_B0=25 End_B1=25
8763 16:44:35.284380 26, 0x0, End_B0=26 End_B1=26
8764 16:44:35.287725 27, 0x0, End_B0=27 End_B1=27
8765 16:44:35.290927 28, 0x0, End_B0=28 End_B1=28
8766 16:44:35.294117 29, 0x0, End_B0=29 End_B1=29
8767 16:44:35.294200 30, 0x0, End_B0=30 End_B1=30
8768 16:44:35.297402 31, 0x4141, End_B0=30 End_B1=30
8769 16:44:35.300762 Byte0 end_step=30 best_step=27
8770 16:44:35.304634 Byte1 end_step=30 best_step=27
8771 16:44:35.307825 Byte0 TX OE(2T, 0.5T) = (3, 3)
8772 16:44:35.311197 Byte1 TX OE(2T, 0.5T) = (3, 3)
8773 16:44:35.311294
8774 16:44:35.311390
8775 16:44:35.317746 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8776 16:44:35.321058 CH1 RK0: MR19=303, MR18=1724
8777 16:44:35.327675 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8778 16:44:35.327757
8779 16:44:35.330947 ----->DramcWriteLeveling(PI) begin...
8780 16:44:35.331031 ==
8781 16:44:35.334065 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 16:44:35.337672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 16:44:35.337755 ==
8784 16:44:35.340897 Write leveling (Byte 0): 27 => 27
8785 16:44:35.343872 Write leveling (Byte 1): 29 => 29
8786 16:44:35.347109 DramcWriteLeveling(PI) end<-----
8787 16:44:35.347225
8788 16:44:35.347353 ==
8789 16:44:35.350681 Dram Type= 6, Freq= 0, CH_1, rank 1
8790 16:44:35.354135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8791 16:44:35.354217 ==
8792 16:44:35.357656 [Gating] SW mode calibration
8793 16:44:35.363989 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8794 16:44:35.370519 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8795 16:44:35.373829 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 16:44:35.377112 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 16:44:35.383933 1 4 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
8798 16:44:35.387042 1 4 12 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8799 16:44:35.390273 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 16:44:35.397117 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 16:44:35.400626 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8802 16:44:35.403957 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8803 16:44:35.410924 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8804 16:44:35.414288 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8805 16:44:35.417443 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8806 16:44:35.423940 1 5 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 0)
8807 16:44:35.427151 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 16:44:35.430507 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 16:44:35.437019 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 16:44:35.440284 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8811 16:44:35.443532 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 16:44:35.450171 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8813 16:44:35.453777 1 6 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8814 16:44:35.456895 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8815 16:44:35.463767 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 16:44:35.467351 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 16:44:35.470430 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8818 16:44:35.477011 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8819 16:44:35.480896 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8820 16:44:35.484156 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8821 16:44:35.490332 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8822 16:44:35.493431 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8823 16:44:35.497193 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8824 16:44:35.503569 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 16:44:35.506999 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 16:44:35.510358 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 16:44:35.513394 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 16:44:35.520463 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 16:44:35.523753 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 16:44:35.527177 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 16:44:35.533616 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 16:44:35.536889 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 16:44:35.540273 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8834 16:44:35.546808 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8835 16:44:35.550108 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8836 16:44:35.553103 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8837 16:44:35.559770 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8838 16:44:35.563535 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8839 16:44:35.566599 Total UI for P1: 0, mck2ui 16
8840 16:44:35.570251 best dqsien dly found for B1: ( 1, 9, 6)
8841 16:44:35.573294 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8842 16:44:35.580062 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8843 16:44:35.580147 Total UI for P1: 0, mck2ui 16
8844 16:44:35.586407 best dqsien dly found for B0: ( 1, 9, 14)
8845 16:44:35.589774 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8846 16:44:35.593101 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8847 16:44:35.593175
8848 16:44:35.596694 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8849 16:44:35.599672 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8850 16:44:35.603242 [Gating] SW calibration Done
8851 16:44:35.603319 ==
8852 16:44:35.606428 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 16:44:35.610145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 16:44:35.610219 ==
8855 16:44:35.613499 RX Vref Scan: 0
8856 16:44:35.613601
8857 16:44:35.613664 RX Vref 0 -> 0, step: 1
8858 16:44:35.613723
8859 16:44:35.616692 RX Delay 0 -> 252, step: 8
8860 16:44:35.619913 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8861 16:44:35.626443 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8862 16:44:35.629773 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8863 16:44:35.633542 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8864 16:44:35.637037 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8865 16:44:35.640080 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8866 16:44:35.643451 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8867 16:44:35.650104 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8868 16:44:35.653449 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8869 16:44:35.656685 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8870 16:44:35.660011 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8871 16:44:35.663580 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8872 16:44:35.669868 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8873 16:44:35.673546 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8874 16:44:35.676753 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8875 16:44:35.679835 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8876 16:44:35.680058 ==
8877 16:44:35.683387 Dram Type= 6, Freq= 0, CH_1, rank 1
8878 16:44:35.689757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8879 16:44:35.689841 ==
8880 16:44:35.689905 DQS Delay:
8881 16:44:35.693495 DQS0 = 0, DQS1 = 0
8882 16:44:35.693575 DQM Delay:
8883 16:44:35.693638 DQM0 = 136, DQM1 = 133
8884 16:44:35.696686 DQ Delay:
8885 16:44:35.700086 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8886 16:44:35.703302 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8887 16:44:35.706284 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8888 16:44:35.710229 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8889 16:44:35.710302
8890 16:44:35.710364
8891 16:44:35.710421 ==
8892 16:44:35.713279 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 16:44:35.716623 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 16:44:35.719913 ==
8895 16:44:35.720002
8896 16:44:35.720086
8897 16:44:35.720164 TX Vref Scan disable
8898 16:44:35.723083 == TX Byte 0 ==
8899 16:44:35.726403 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8900 16:44:35.729682 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8901 16:44:35.732954 == TX Byte 1 ==
8902 16:44:35.736690 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8903 16:44:35.740014 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8904 16:44:35.743429 ==
8905 16:44:35.746665 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 16:44:35.750045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 16:44:35.750129 ==
8908 16:44:35.762671
8909 16:44:35.765822 TX Vref early break, caculate TX vref
8910 16:44:35.769101 TX Vref=16, minBit 0, minWin=23, winSum=381
8911 16:44:35.772753 TX Vref=18, minBit 0, minWin=23, winSum=390
8912 16:44:35.776364 TX Vref=20, minBit 0, minWin=24, winSum=399
8913 16:44:35.779465 TX Vref=22, minBit 0, minWin=24, winSum=405
8914 16:44:35.782446 TX Vref=24, minBit 0, minWin=25, winSum=413
8915 16:44:35.789086 TX Vref=26, minBit 1, minWin=25, winSum=422
8916 16:44:35.792924 TX Vref=28, minBit 0, minWin=25, winSum=423
8917 16:44:35.795935 TX Vref=30, minBit 15, minWin=25, winSum=416
8918 16:44:35.799117 TX Vref=32, minBit 0, minWin=24, winSum=409
8919 16:44:35.802966 TX Vref=34, minBit 0, minWin=24, winSum=401
8920 16:44:35.806136 TX Vref=36, minBit 0, minWin=24, winSum=393
8921 16:44:35.812585 [TxChooseVref] Worse bit 0, Min win 25, Win sum 423, Final Vref 28
8922 16:44:35.812670
8923 16:44:35.815790 Final TX Range 0 Vref 28
8924 16:44:35.815865
8925 16:44:35.815927 ==
8926 16:44:35.818998 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 16:44:35.823013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 16:44:35.823090 ==
8929 16:44:35.823154
8930 16:44:35.823213
8931 16:44:35.826232 TX Vref Scan disable
8932 16:44:35.832503 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8933 16:44:35.832587 == TX Byte 0 ==
8934 16:44:35.835790 u2DelayCellOfst[0]=16 cells (5 PI)
8935 16:44:35.839085 u2DelayCellOfst[1]=10 cells (3 PI)
8936 16:44:35.842363 u2DelayCellOfst[2]=0 cells (0 PI)
8937 16:44:35.845754 u2DelayCellOfst[3]=6 cells (2 PI)
8938 16:44:35.849630 u2DelayCellOfst[4]=6 cells (2 PI)
8939 16:44:35.852752 u2DelayCellOfst[5]=16 cells (5 PI)
8940 16:44:35.856060 u2DelayCellOfst[6]=16 cells (5 PI)
8941 16:44:35.859475 u2DelayCellOfst[7]=6 cells (2 PI)
8942 16:44:35.862656 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8943 16:44:35.865971 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8944 16:44:35.869347 == TX Byte 1 ==
8945 16:44:35.872505 u2DelayCellOfst[8]=0 cells (0 PI)
8946 16:44:35.872587 u2DelayCellOfst[9]=3 cells (1 PI)
8947 16:44:35.875807 u2DelayCellOfst[10]=10 cells (3 PI)
8948 16:44:35.878994 u2DelayCellOfst[11]=3 cells (1 PI)
8949 16:44:35.882589 u2DelayCellOfst[12]=13 cells (4 PI)
8950 16:44:35.885705 u2DelayCellOfst[13]=16 cells (5 PI)
8951 16:44:35.888949 u2DelayCellOfst[14]=16 cells (5 PI)
8952 16:44:35.892678 u2DelayCellOfst[15]=16 cells (5 PI)
8953 16:44:35.895779 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8954 16:44:35.902537 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8955 16:44:35.902715 DramC Write-DBI on
8956 16:44:35.902863 ==
8957 16:44:35.905547 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 16:44:35.912342 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 16:44:35.912609 ==
8960 16:44:35.912812
8961 16:44:35.912995
8962 16:44:35.913181 TX Vref Scan disable
8963 16:44:35.916166 == TX Byte 0 ==
8964 16:44:35.919526 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8965 16:44:35.922785 == TX Byte 1 ==
8966 16:44:35.926508 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8967 16:44:35.926914 DramC Write-DBI off
8968 16:44:35.929756
8969 16:44:35.930168 [DATLAT]
8970 16:44:35.930475 Freq=1600, CH1 RK1
8971 16:44:35.930767
8972 16:44:35.932833 DATLAT Default: 0xf
8973 16:44:35.933240 0, 0xFFFF, sum = 0
8974 16:44:35.936573 1, 0xFFFF, sum = 0
8975 16:44:35.936969 2, 0xFFFF, sum = 0
8976 16:44:35.939753 3, 0xFFFF, sum = 0
8977 16:44:35.940147 4, 0xFFFF, sum = 0
8978 16:44:35.943040 5, 0xFFFF, sum = 0
8979 16:44:35.946393 6, 0xFFFF, sum = 0
8980 16:44:35.946787 7, 0xFFFF, sum = 0
8981 16:44:35.949621 8, 0xFFFF, sum = 0
8982 16:44:35.950019 9, 0xFFFF, sum = 0
8983 16:44:35.952932 10, 0xFFFF, sum = 0
8984 16:44:35.953325 11, 0xFFFF, sum = 0
8985 16:44:35.956312 12, 0xFFFF, sum = 0
8986 16:44:35.956706 13, 0xFFFF, sum = 0
8987 16:44:35.959486 14, 0x0, sum = 1
8988 16:44:35.959882 15, 0x0, sum = 2
8989 16:44:35.962858 16, 0x0, sum = 3
8990 16:44:35.963254 17, 0x0, sum = 4
8991 16:44:35.966230 best_step = 15
8992 16:44:35.966618
8993 16:44:35.966925 ==
8994 16:44:35.969381 Dram Type= 6, Freq= 0, CH_1, rank 1
8995 16:44:35.972656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8996 16:44:35.973047 ==
8997 16:44:35.973356 RX Vref Scan: 0
8998 16:44:35.976673
8999 16:44:35.977056 RX Vref 0 -> 0, step: 1
9000 16:44:35.977368
9001 16:44:35.979820 RX Delay 19 -> 252, step: 4
9002 16:44:35.983092 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9003 16:44:35.989325 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9004 16:44:35.992881 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9005 16:44:35.996067 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9006 16:44:35.999670 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9007 16:44:36.002801 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9008 16:44:36.005965 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9009 16:44:36.012759 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
9010 16:44:36.016512 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9011 16:44:36.019264 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9012 16:44:36.023040 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9013 16:44:36.026153 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9014 16:44:36.032521 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9015 16:44:36.035671 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9016 16:44:36.039459 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9017 16:44:36.042633 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9018 16:44:36.043019 ==
9019 16:44:36.046204 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 16:44:36.052619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 16:44:36.052798 ==
9022 16:44:36.052864 DQS Delay:
9023 16:44:36.055688 DQS0 = 0, DQS1 = 0
9024 16:44:36.055770 DQM Delay:
9025 16:44:36.055835 DQM0 = 133, DQM1 = 130
9026 16:44:36.058949 DQ Delay:
9027 16:44:36.062214 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9028 16:44:36.065544 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =132
9029 16:44:36.068617 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9030 16:44:36.072511 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9031 16:44:36.072594
9032 16:44:36.072659
9033 16:44:36.072719
9034 16:44:36.074995 [DramC_TX_OE_Calibration] TA2
9035 16:44:36.078412 Original DQ_B0 (3 6) =30, OEN = 27
9036 16:44:36.081707 Original DQ_B1 (3 6) =30, OEN = 27
9037 16:44:36.085049 24, 0x0, End_B0=24 End_B1=24
9038 16:44:36.088858 25, 0x0, End_B0=25 End_B1=25
9039 16:44:36.088942 26, 0x0, End_B0=26 End_B1=26
9040 16:44:36.092118 27, 0x0, End_B0=27 End_B1=27
9041 16:44:36.095149 28, 0x0, End_B0=28 End_B1=28
9042 16:44:36.098314 29, 0x0, End_B0=29 End_B1=29
9043 16:44:36.098398 30, 0x0, End_B0=30 End_B1=30
9044 16:44:36.101940 31, 0x4141, End_B0=30 End_B1=30
9045 16:44:36.105180 Byte0 end_step=30 best_step=27
9046 16:44:36.108902 Byte1 end_step=30 best_step=27
9047 16:44:36.111910 Byte0 TX OE(2T, 0.5T) = (3, 3)
9048 16:44:36.115355 Byte1 TX OE(2T, 0.5T) = (3, 3)
9049 16:44:36.115436
9050 16:44:36.115501
9051 16:44:36.122178 [DQSOSCAuto] RK1, (LSB)MR18= 0x260b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
9052 16:44:36.125121 CH1 RK1: MR19=303, MR18=260B
9053 16:44:36.131906 CH1_RK1: MR19=0x303, MR18=0x260B, DQSOSC=390, MR23=63, INC=24, DEC=16
9054 16:44:36.135227 [RxdqsGatingPostProcess] freq 1600
9055 16:44:36.138303 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9056 16:44:36.141507 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 16:44:36.144766 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 16:44:36.148182 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 16:44:36.151390 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 16:44:36.155142 best DQS0 dly(2T, 0.5T) = (1, 1)
9061 16:44:36.158508 best DQS1 dly(2T, 0.5T) = (1, 1)
9062 16:44:36.161692 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9063 16:44:36.164980 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9064 16:44:36.168399 Pre-setting of DQS Precalculation
9065 16:44:36.171797 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9066 16:44:36.178300 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9067 16:44:36.188659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9068 16:44:36.188742
9069 16:44:36.188807
9070 16:44:36.191471 [Calibration Summary] 3200 Mbps
9071 16:44:36.191553 CH 0, Rank 0
9072 16:44:36.195244 SW Impedance : PASS
9073 16:44:36.195326 DUTY Scan : NO K
9074 16:44:36.198389 ZQ Calibration : PASS
9075 16:44:36.198471 Jitter Meter : NO K
9076 16:44:36.201656 CBT Training : PASS
9077 16:44:36.204933 Write leveling : PASS
9078 16:44:36.205015 RX DQS gating : PASS
9079 16:44:36.208065 RX DQ/DQS(RDDQC) : PASS
9080 16:44:36.211236 TX DQ/DQS : PASS
9081 16:44:36.211334 RX DATLAT : PASS
9082 16:44:36.214953 RX DQ/DQS(Engine): PASS
9083 16:44:36.218087 TX OE : PASS
9084 16:44:36.218170 All Pass.
9085 16:44:36.218235
9086 16:44:36.218294 CH 0, Rank 1
9087 16:44:36.221225 SW Impedance : PASS
9088 16:44:36.224823 DUTY Scan : NO K
9089 16:44:36.224905 ZQ Calibration : PASS
9090 16:44:36.227954 Jitter Meter : NO K
9091 16:44:36.231118 CBT Training : PASS
9092 16:44:36.231200 Write leveling : PASS
9093 16:44:36.234664 RX DQS gating : PASS
9094 16:44:36.237912 RX DQ/DQS(RDDQC) : PASS
9095 16:44:36.237994 TX DQ/DQS : PASS
9096 16:44:36.241546 RX DATLAT : PASS
9097 16:44:36.244769 RX DQ/DQS(Engine): PASS
9098 16:44:36.244852 TX OE : PASS
9099 16:44:36.244917 All Pass.
9100 16:44:36.244978
9101 16:44:36.248105 CH 1, Rank 0
9102 16:44:36.251151 SW Impedance : PASS
9103 16:44:36.251233 DUTY Scan : NO K
9104 16:44:36.254427 ZQ Calibration : PASS
9105 16:44:36.254510 Jitter Meter : NO K
9106 16:44:36.257797 CBT Training : PASS
9107 16:44:36.261064 Write leveling : PASS
9108 16:44:36.261146 RX DQS gating : PASS
9109 16:44:36.264648 RX DQ/DQS(RDDQC) : PASS
9110 16:44:36.267926 TX DQ/DQS : PASS
9111 16:44:36.268009 RX DATLAT : PASS
9112 16:44:36.271430 RX DQ/DQS(Engine): PASS
9113 16:44:36.274655 TX OE : PASS
9114 16:44:36.274737 All Pass.
9115 16:44:36.274802
9116 16:44:36.274861 CH 1, Rank 1
9117 16:44:36.277960 SW Impedance : PASS
9118 16:44:36.281232 DUTY Scan : NO K
9119 16:44:36.281314 ZQ Calibration : PASS
9120 16:44:36.284364 Jitter Meter : NO K
9121 16:44:36.288299 CBT Training : PASS
9122 16:44:36.288381 Write leveling : PASS
9123 16:44:36.291042 RX DQS gating : PASS
9124 16:44:36.294290 RX DQ/DQS(RDDQC) : PASS
9125 16:44:36.294372 TX DQ/DQS : PASS
9126 16:44:36.297556 RX DATLAT : PASS
9127 16:44:36.297638 RX DQ/DQS(Engine): PASS
9128 16:44:36.301468 TX OE : PASS
9129 16:44:36.301573 All Pass.
9130 16:44:36.301638
9131 16:44:36.304650 DramC Write-DBI on
9132 16:44:36.307720 PER_BANK_REFRESH: Hybrid Mode
9133 16:44:36.307803 TX_TRACKING: ON
9134 16:44:36.317886 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9135 16:44:36.324543 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9136 16:44:36.331337 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 16:44:36.337723 [FAST_K] Save calibration result to emmc
9138 16:44:36.337819 sync common calibartion params.
9139 16:44:36.341463 sync cbt_mode0:1, 1:1
9140 16:44:36.344580 dram_init: ddr_geometry: 2
9141 16:44:36.344691 dram_init: ddr_geometry: 2
9142 16:44:36.347850 dram_init: ddr_geometry: 2
9143 16:44:36.350988 0:dram_rank_size:100000000
9144 16:44:36.354521 1:dram_rank_size:100000000
9145 16:44:36.357825 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9146 16:44:36.361228 DFS_SHUFFLE_HW_MODE: ON
9147 16:44:36.364379 dramc_set_vcore_voltage set vcore to 725000
9148 16:44:36.367985 Read voltage for 1600, 0
9149 16:44:36.368067 Vio18 = 0
9150 16:44:36.371077 Vcore = 725000
9151 16:44:36.371161 Vdram = 0
9152 16:44:36.371225 Vddq = 0
9153 16:44:36.371285 Vmddr = 0
9154 16:44:36.374315 switch to 3200 Mbps bootup
9155 16:44:36.377766 [DramcRunTimeConfig]
9156 16:44:36.377848 PHYPLL
9157 16:44:36.377913 DPM_CONTROL_AFTERK: ON
9158 16:44:36.380961 PER_BANK_REFRESH: ON
9159 16:44:36.384302 REFRESH_OVERHEAD_REDUCTION: ON
9160 16:44:36.387592 CMD_PICG_NEW_MODE: OFF
9161 16:44:36.387674 XRTWTW_NEW_MODE: ON
9162 16:44:36.390879 XRTRTR_NEW_MODE: ON
9163 16:44:36.390961 TX_TRACKING: ON
9164 16:44:36.393997 RDSEL_TRACKING: OFF
9165 16:44:36.394079 DQS Precalculation for DVFS: ON
9166 16:44:36.397790 RX_TRACKING: OFF
9167 16:44:36.397872 HW_GATING DBG: ON
9168 16:44:36.401175 ZQCS_ENABLE_LP4: ON
9169 16:44:36.404386 RX_PICG_NEW_MODE: ON
9170 16:44:36.404468 TX_PICG_NEW_MODE: ON
9171 16:44:36.407528 ENABLE_RX_DCM_DPHY: ON
9172 16:44:36.411445 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9173 16:44:36.411527 DUMMY_READ_FOR_TRACKING: OFF
9174 16:44:36.414211 !!! SPM_CONTROL_AFTERK: OFF
9175 16:44:36.418092 !!! SPM could not control APHY
9176 16:44:36.421302 IMPEDANCE_TRACKING: ON
9177 16:44:36.421416 TEMP_SENSOR: ON
9178 16:44:36.424222 HW_SAVE_FOR_SR: OFF
9179 16:44:36.424305 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9180 16:44:36.431088 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9181 16:44:36.431171 Read ODT Tracking: ON
9182 16:44:36.434067 Refresh Rate DeBounce: ON
9183 16:44:36.434149 DFS_NO_QUEUE_FLUSH: ON
9184 16:44:36.437868 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9185 16:44:36.441070 ENABLE_DFS_RUNTIME_MRW: OFF
9186 16:44:36.444020 DDR_RESERVE_NEW_MODE: ON
9187 16:44:36.447520 MR_CBT_SWITCH_FREQ: ON
9188 16:44:36.447602 =========================
9189 16:44:36.467195 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9190 16:44:36.470507 dram_init: ddr_geometry: 2
9191 16:44:36.488487 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9192 16:44:36.491746 dram_init: dram init end (result: 0)
9193 16:44:36.498910 DRAM-K: Full calibration passed in 24428 msecs
9194 16:44:36.502094 MRC: failed to locate region type 0.
9195 16:44:36.502177 DRAM rank0 size:0x100000000,
9196 16:44:36.505394 DRAM rank1 size=0x100000000
9197 16:44:36.515494 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9198 16:44:36.522045 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9199 16:44:36.529014 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9200 16:44:36.535083 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9201 16:44:36.538668 DRAM rank0 size:0x100000000,
9202 16:44:36.541870 DRAM rank1 size=0x100000000
9203 16:44:36.541957 CBMEM:
9204 16:44:36.545315 IMD: root @ 0xfffff000 254 entries.
9205 16:44:36.548510 IMD: root @ 0xffffec00 62 entries.
9206 16:44:36.551993 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9207 16:44:36.555064 WARNING: RO_VPD is uninitialized or empty.
9208 16:44:36.561948 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9209 16:44:36.568848 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9210 16:44:36.582127 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9211 16:44:36.592833 BS: romstage times (exec / console): total (unknown) / 23967 ms
9212 16:44:36.592948
9213 16:44:36.593042
9214 16:44:36.602634 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9215 16:44:36.606541 ARM64: Exception handlers installed.
9216 16:44:36.609783 ARM64: Testing exception
9217 16:44:36.613024 ARM64: Done test exception
9218 16:44:36.613097 Enumerating buses...
9219 16:44:36.616232 Show all devs... Before device enumeration.
9220 16:44:36.619776 Root Device: enabled 1
9221 16:44:36.623147 CPU_CLUSTER: 0: enabled 1
9222 16:44:36.623221 CPU: 00: enabled 1
9223 16:44:36.626448 Compare with tree...
9224 16:44:36.626519 Root Device: enabled 1
9225 16:44:36.629685 CPU_CLUSTER: 0: enabled 1
9226 16:44:36.632987 CPU: 00: enabled 1
9227 16:44:36.633057 Root Device scanning...
9228 16:44:36.636078 scan_static_bus for Root Device
9229 16:44:36.639763 CPU_CLUSTER: 0 enabled
9230 16:44:36.642923 scan_static_bus for Root Device done
9231 16:44:36.646235 scan_bus: bus Root Device finished in 8 msecs
9232 16:44:36.646309 done
9233 16:44:36.652562 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9234 16:44:36.656292 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9235 16:44:36.662583 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9236 16:44:36.665820 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9237 16:44:36.669742 Allocating resources...
9238 16:44:36.669820 Reading resources...
9239 16:44:36.676181 Root Device read_resources bus 0 link: 0
9240 16:44:36.676254 DRAM rank0 size:0x100000000,
9241 16:44:36.679860 DRAM rank1 size=0x100000000
9242 16:44:36.682537 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9243 16:44:36.686225 CPU: 00 missing read_resources
9244 16:44:36.689309 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9245 16:44:36.695680 Root Device read_resources bus 0 link: 0 done
9246 16:44:36.695759 Done reading resources.
9247 16:44:36.702967 Show resources in subtree (Root Device)...After reading.
9248 16:44:36.706110 Root Device child on link 0 CPU_CLUSTER: 0
9249 16:44:36.709402 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 16:44:36.719128 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 16:44:36.719222 CPU: 00
9252 16:44:36.722322 Root Device assign_resources, bus 0 link: 0
9253 16:44:36.726255 CPU_CLUSTER: 0 missing set_resources
9254 16:44:36.729363 Root Device assign_resources, bus 0 link: 0 done
9255 16:44:36.732730 Done setting resources.
9256 16:44:36.739247 Show resources in subtree (Root Device)...After assigning values.
9257 16:44:36.742479 Root Device child on link 0 CPU_CLUSTER: 0
9258 16:44:36.745645 CPU_CLUSTER: 0 child on link 0 CPU: 00
9259 16:44:36.755476 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9260 16:44:36.755560 CPU: 00
9261 16:44:36.759209 Done allocating resources.
9262 16:44:36.762333 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9263 16:44:36.765329 Enabling resources...
9264 16:44:36.765400 done.
9265 16:44:36.772067 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9266 16:44:36.772176 Initializing devices...
9267 16:44:36.775329 Root Device init
9268 16:44:36.775408 init hardware done!
9269 16:44:36.779301 0x00000018: ctrlr->caps
9270 16:44:36.782504 52.000 MHz: ctrlr->f_max
9271 16:44:36.782590 0.400 MHz: ctrlr->f_min
9272 16:44:36.785724 0x40ff8080: ctrlr->voltages
9273 16:44:36.785801 sclk: 390625
9274 16:44:36.789000 Bus Width = 1
9275 16:44:36.789136 sclk: 390625
9276 16:44:36.789232 Bus Width = 1
9277 16:44:36.792499 Early init status = 3
9278 16:44:36.798966 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9279 16:44:36.802233 in-header: 03 fc 00 00 01 00 00 00
9280 16:44:36.802311 in-data: 00
9281 16:44:36.808753 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9282 16:44:36.812032 in-header: 03 fd 00 00 00 00 00 00
9283 16:44:36.815948 in-data:
9284 16:44:36.818561 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9285 16:44:36.822657 in-header: 03 fc 00 00 01 00 00 00
9286 16:44:36.825779 in-data: 00
9287 16:44:36.828928 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9288 16:44:36.834833 in-header: 03 fd 00 00 00 00 00 00
9289 16:44:36.838176 in-data:
9290 16:44:36.841302 [SSUSB] Setting up USB HOST controller...
9291 16:44:36.844579 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9292 16:44:36.847819 [SSUSB] phy power-on done.
9293 16:44:36.851581 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9294 16:44:36.857955 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9295 16:44:36.861447 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9296 16:44:36.868345 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9297 16:44:36.874445 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9298 16:44:36.881468 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9299 16:44:36.888184 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9300 16:44:36.894522 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9301 16:44:36.894621 SPM: binary array size = 0x9dc
9302 16:44:36.901483 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9303 16:44:36.907930 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9304 16:44:36.914414 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9305 16:44:36.917662 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9306 16:44:36.924216 configure_display: Starting display init
9307 16:44:36.957833 anx7625_power_on_init: Init interface.
9308 16:44:36.961469 anx7625_disable_pd_protocol: Disabled PD feature.
9309 16:44:36.964565 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9310 16:44:36.992425 anx7625_start_dp_work: Secure OCM version=00
9311 16:44:36.995616 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9312 16:44:37.010684 sp_tx_get_edid_block: EDID Block = 1
9313 16:44:37.112916 Extracted contents:
9314 16:44:37.116258 header: 00 ff ff ff ff ff ff 00
9315 16:44:37.119964 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9316 16:44:37.123087 version: 01 04
9317 16:44:37.126511 basic params: 95 1f 11 78 0a
9318 16:44:37.129793 chroma info: 76 90 94 55 54 90 27 21 50 54
9319 16:44:37.133154 established: 00 00 00
9320 16:44:37.139465 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9321 16:44:37.142791 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9322 16:44:37.149783 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9323 16:44:37.155927 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9324 16:44:37.162913 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9325 16:44:37.166290 extensions: 00
9326 16:44:37.166760 checksum: fb
9327 16:44:37.167220
9328 16:44:37.169667 Manufacturer: IVO Model 57d Serial Number 0
9329 16:44:37.172698 Made week 0 of 2020
9330 16:44:37.173155 EDID version: 1.4
9331 16:44:37.175722 Digital display
9332 16:44:37.179734 6 bits per primary color channel
9333 16:44:37.180195 DisplayPort interface
9334 16:44:37.182666 Maximum image size: 31 cm x 17 cm
9335 16:44:37.186339 Gamma: 220%
9336 16:44:37.186642 Check DPMS levels
9337 16:44:37.189757 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9338 16:44:37.195913 First detailed timing is preferred timing
9339 16:44:37.196274 Established timings supported:
9340 16:44:37.199638 Standard timings supported:
9341 16:44:37.202708 Detailed timings
9342 16:44:37.206304 Hex of detail: 383680a07038204018303c0035ae10000019
9343 16:44:37.209129 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9344 16:44:37.216073 0780 0798 07c8 0820 hborder 0
9345 16:44:37.219385 0438 043b 0447 0458 vborder 0
9346 16:44:37.222733 -hsync -vsync
9347 16:44:37.223153 Did detailed timing
9348 16:44:37.229613 Hex of detail: 000000000000000000000000000000000000
9349 16:44:37.230037 Manufacturer-specified data, tag 0
9350 16:44:37.236212 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9351 16:44:37.239557 ASCII string: InfoVision
9352 16:44:37.242731 Hex of detail: 000000fe00523134304e574635205248200a
9353 16:44:37.245774 ASCII string: R140NWF5 RH
9354 16:44:37.246180 Checksum
9355 16:44:37.249595 Checksum: 0xfb (valid)
9356 16:44:37.252774 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9357 16:44:37.256078 DSI data_rate: 832800000 bps
9358 16:44:37.262584 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9359 16:44:37.265878 anx7625_parse_edid: pixelclock(138800).
9360 16:44:37.269078 hactive(1920), hsync(48), hfp(24), hbp(88)
9361 16:44:37.272423 vactive(1080), vsync(12), vfp(3), vbp(17)
9362 16:44:37.275743 anx7625_dsi_config: config dsi.
9363 16:44:37.282606 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9364 16:44:37.295311 anx7625_dsi_config: success to config DSI
9365 16:44:37.298595 anx7625_dp_start: MIPI phy setup OK.
9366 16:44:37.301551 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9367 16:44:37.305345 mtk_ddp_mode_set invalid vrefresh 60
9368 16:44:37.308537 main_disp_path_setup
9369 16:44:37.308681 ovl_layer_smi_id_en
9370 16:44:37.311693 ovl_layer_smi_id_en
9371 16:44:37.311810 ccorr_config
9372 16:44:37.311901 aal_config
9373 16:44:37.315037 gamma_config
9374 16:44:37.315150 postmask_config
9375 16:44:37.318717 dither_config
9376 16:44:37.321897 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9377 16:44:37.328640 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9378 16:44:37.331868 Root Device init finished in 553 msecs
9379 16:44:37.331978 CPU_CLUSTER: 0 init
9380 16:44:37.341903 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9381 16:44:37.345283 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9382 16:44:37.348490 APU_MBOX 0x190000b0 = 0x10001
9383 16:44:37.351554 APU_MBOX 0x190001b0 = 0x10001
9384 16:44:37.354714 APU_MBOX 0x190005b0 = 0x10001
9385 16:44:37.358553 APU_MBOX 0x190006b0 = 0x10001
9386 16:44:37.361165 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9387 16:44:37.374435 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9388 16:44:37.386447 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9389 16:44:37.393054 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9390 16:44:37.404950 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9391 16:44:37.413912 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9392 16:44:37.417029 CPU_CLUSTER: 0 init finished in 81 msecs
9393 16:44:37.420251 Devices initialized
9394 16:44:37.424124 Show all devs... After init.
9395 16:44:37.424208 Root Device: enabled 1
9396 16:44:37.427326 CPU_CLUSTER: 0: enabled 1
9397 16:44:37.430572 CPU: 00: enabled 1
9398 16:44:37.433504 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9399 16:44:37.436861 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9400 16:44:37.440568 ELOG: NV offset 0x57f000 size 0x1000
9401 16:44:37.447196 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9402 16:44:37.453670 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9403 16:44:37.457421 ELOG: Event(17) added with size 13 at 2023-06-03 16:44:38 UTC
9404 16:44:37.460681 out: cmd=0x121: 03 db 21 01 00 00 00 00
9405 16:44:37.464084 in-header: 03 f8 00 00 2c 00 00 00
9406 16:44:37.477210 in-data: 67 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 16:44:37.483832 ELOG: Event(A1) added with size 10 at 2023-06-03 16:44:38 UTC
9408 16:44:37.490952 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9409 16:44:37.497388 ELOG: Event(A0) added with size 9 at 2023-06-03 16:44:38 UTC
9410 16:44:37.500971 elog_add_boot_reason: Logged dev mode boot
9411 16:44:37.504013 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9412 16:44:37.507359 Finalize devices...
9413 16:44:37.507432 Devices finalized
9414 16:44:37.513968 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9415 16:44:37.517052 Writing coreboot table at 0xffe64000
9416 16:44:37.520259 0. 000000000010a000-0000000000113fff: RAMSTAGE
9417 16:44:37.523441 1. 0000000040000000-00000000400fffff: RAM
9418 16:44:37.530562 2. 0000000040100000-000000004032afff: RAMSTAGE
9419 16:44:37.533750 3. 000000004032b000-00000000545fffff: RAM
9420 16:44:37.537031 4. 0000000054600000-000000005465ffff: BL31
9421 16:44:37.540304 5. 0000000054660000-00000000ffe63fff: RAM
9422 16:44:37.546727 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9423 16:44:37.550532 7. 0000000100000000-000000023fffffff: RAM
9424 16:44:37.550616 Passing 5 GPIOs to payload:
9425 16:44:37.557040 NAME | PORT | POLARITY | VALUE
9426 16:44:37.560105 EC in RW | 0x000000aa | low | undefined
9427 16:44:37.567062 EC interrupt | 0x00000005 | low | undefined
9428 16:44:37.570521 TPM interrupt | 0x000000ab | high | undefined
9429 16:44:37.573651 SD card detect | 0x00000011 | high | undefined
9430 16:44:37.580414 speaker enable | 0x00000093 | high | undefined
9431 16:44:37.583672 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9432 16:44:37.586994 in-header: 03 f9 00 00 02 00 00 00
9433 16:44:37.587067 in-data: 02 00
9434 16:44:37.590418 ADC[4]: Raw value=904726 ID=7
9435 16:44:37.593640 ADC[3]: Raw value=213810 ID=1
9436 16:44:37.593712 RAM Code: 0x71
9437 16:44:37.596871 ADC[6]: Raw value=75701 ID=0
9438 16:44:37.600128 ADC[5]: Raw value=213072 ID=1
9439 16:44:37.600204 SKU Code: 0x1
9440 16:44:37.606999 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ce97
9441 16:44:37.610570 coreboot table: 964 bytes.
9442 16:44:37.613724 IMD ROOT 0. 0xfffff000 0x00001000
9443 16:44:37.616934 IMD SMALL 1. 0xffffe000 0x00001000
9444 16:44:37.620408 RO MCACHE 2. 0xffffc000 0x00001104
9445 16:44:37.623735 CONSOLE 3. 0xfff7c000 0x00080000
9446 16:44:37.626786 FMAP 4. 0xfff7b000 0x00000452
9447 16:44:37.629892 TIME STAMP 5. 0xfff7a000 0x00000910
9448 16:44:37.633472 VBOOT WORK 6. 0xfff66000 0x00014000
9449 16:44:37.636757 RAMOOPS 7. 0xffe66000 0x00100000
9450 16:44:37.640038 COREBOOT 8. 0xffe64000 0x00002000
9451 16:44:37.640113 IMD small region:
9452 16:44:37.643106 IMD ROOT 0. 0xffffec00 0x00000400
9453 16:44:37.646418 VPD 1. 0xffffeba0 0x0000004c
9454 16:44:37.650102 MMC STATUS 2. 0xffffeb80 0x00000004
9455 16:44:37.656339 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9456 16:44:37.659786 Probing TPM: done!
9457 16:44:37.663511 Connected to device vid:did:rid of 1ae0:0028:00
9458 16:44:37.673608 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9459 16:44:37.677041 Initialized TPM device CR50 revision 0
9460 16:44:37.680197 Checking cr50 for pending updates
9461 16:44:37.683665 Reading cr50 TPM mode
9462 16:44:37.691962 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9463 16:44:37.699230 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9464 16:44:37.739366 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9465 16:44:37.742496 Checking segment from ROM address 0x40100000
9466 16:44:37.745680 Checking segment from ROM address 0x4010001c
9467 16:44:37.752686 Loading segment from ROM address 0x40100000
9468 16:44:37.752768 code (compression=0)
9469 16:44:37.762103 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9470 16:44:37.768687 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9471 16:44:37.768770 it's not compressed!
9472 16:44:37.775688 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9473 16:44:37.782269 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9474 16:44:37.799285 Loading segment from ROM address 0x4010001c
9475 16:44:37.799372 Entry Point 0x80000000
9476 16:44:37.802759 Loaded segments
9477 16:44:37.806131 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9478 16:44:37.812521 Jumping to boot code at 0x80000000(0xffe64000)
9479 16:44:37.819577 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9480 16:44:37.825819 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9481 16:44:37.833709 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9482 16:44:37.837329 Checking segment from ROM address 0x40100000
9483 16:44:37.840610 Checking segment from ROM address 0x4010001c
9484 16:44:37.847410 Loading segment from ROM address 0x40100000
9485 16:44:37.847494 code (compression=1)
9486 16:44:37.853924 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9487 16:44:37.863827 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9488 16:44:37.863915 using LZMA
9489 16:44:37.871988 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9490 16:44:37.879068 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9491 16:44:37.882302 Loading segment from ROM address 0x4010001c
9492 16:44:37.882386 Entry Point 0x54601000
9493 16:44:37.885629 Loaded segments
9494 16:44:37.888418 NOTICE: MT8192 bl31_setup
9495 16:44:37.895750 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9496 16:44:37.898957 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9497 16:44:37.902323 WARNING: region 0:
9498 16:44:37.906259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 16:44:37.906341 WARNING: region 1:
9500 16:44:37.912211 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9501 16:44:37.915575 WARNING: region 2:
9502 16:44:37.919547 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9503 16:44:37.922590 WARNING: region 3:
9504 16:44:37.925835 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9505 16:44:37.929399 WARNING: region 4:
9506 16:44:37.932572 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9507 16:44:37.935801 WARNING: region 5:
9508 16:44:37.938964 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9509 16:44:37.942553 WARNING: region 6:
9510 16:44:37.945822 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 16:44:37.945933 WARNING: region 7:
9512 16:44:37.952875 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 16:44:37.959393 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9514 16:44:37.962551 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9515 16:44:37.966262 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9516 16:44:37.972586 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9517 16:44:37.976046 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9518 16:44:37.979713 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9519 16:44:37.986121 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9520 16:44:37.989248 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9521 16:44:37.992611 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9522 16:44:37.999789 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9523 16:44:38.002957 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9524 16:44:38.006247 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9525 16:44:38.012791 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9526 16:44:38.015990 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9527 16:44:38.023198 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9528 16:44:38.026346 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9529 16:44:38.029466 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9530 16:44:38.036296 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9531 16:44:38.039585 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9532 16:44:38.042723 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9533 16:44:38.049389 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9534 16:44:38.052723 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9535 16:44:38.059511 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9536 16:44:38.062900 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9537 16:44:38.066000 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9538 16:44:38.073112 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9539 16:44:38.076248 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9540 16:44:38.083147 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9541 16:44:38.086261 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9542 16:44:38.090061 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9543 16:44:38.095926 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9544 16:44:38.099902 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9545 16:44:38.103088 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9546 16:44:38.109361 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9547 16:44:38.112758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9548 16:44:38.116716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9549 16:44:38.120060 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9550 16:44:38.126126 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9551 16:44:38.129414 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9552 16:44:38.133275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9553 16:44:38.136362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9554 16:44:38.143000 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9555 16:44:38.146256 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9556 16:44:38.150008 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9557 16:44:38.153163 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9558 16:44:38.159624 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9559 16:44:38.163350 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9560 16:44:38.166682 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9561 16:44:38.173661 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9562 16:44:38.177023 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9563 16:44:38.180182 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9564 16:44:38.186573 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9565 16:44:38.190235 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9566 16:44:38.196939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9567 16:44:38.200185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9568 16:44:38.203491 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9569 16:44:38.210124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9570 16:44:38.213201 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9571 16:44:38.220551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9572 16:44:38.223862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9573 16:44:38.230258 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9574 16:44:38.233467 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9575 16:44:38.240118 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9576 16:44:38.243442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9577 16:44:38.246977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9578 16:44:38.253631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9579 16:44:38.256970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9580 16:44:38.263509 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9581 16:44:38.266622 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9582 16:44:38.270548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9583 16:44:38.277072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9584 16:44:38.280050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9585 16:44:38.286936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9586 16:44:38.290189 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9587 16:44:38.296559 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9588 16:44:38.300431 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9589 16:44:38.303612 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9590 16:44:38.310076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9591 16:44:38.313246 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9592 16:44:38.320397 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9593 16:44:38.323756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9594 16:44:38.330345 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9595 16:44:38.333059 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9596 16:44:38.340362 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9597 16:44:38.343505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9598 16:44:38.346889 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9599 16:44:38.353265 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9600 16:44:38.357031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9601 16:44:38.363784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9602 16:44:38.367000 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9603 16:44:38.370011 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9604 16:44:38.377118 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9605 16:44:38.380293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9606 16:44:38.387020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9607 16:44:38.390174 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9608 16:44:38.396951 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9609 16:44:38.400115 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9610 16:44:38.403508 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9611 16:44:38.407598 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9612 16:44:38.413652 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9613 16:44:38.416929 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9614 16:44:38.420345 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9615 16:44:38.426942 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9616 16:44:38.430288 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9617 16:44:38.436958 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9618 16:44:38.440201 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9619 16:44:38.443476 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9620 16:44:38.450007 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9621 16:44:38.453435 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9622 16:44:38.457147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9623 16:44:38.463420 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9624 16:44:38.466648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9625 16:44:38.473663 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9626 16:44:38.476887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9627 16:44:38.480493 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9628 16:44:38.487351 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9629 16:44:38.490538 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9630 16:44:38.493639 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9631 16:44:38.500854 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9632 16:44:38.503866 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9633 16:44:38.506938 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9634 16:44:38.510865 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9635 16:44:38.513954 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9636 16:44:38.521048 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9637 16:44:38.524195 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9638 16:44:38.530922 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9639 16:44:38.534148 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9640 16:44:38.537448 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9641 16:44:38.543930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9642 16:44:38.547241 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9643 16:44:38.550568 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9644 16:44:38.557158 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9645 16:44:38.560392 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9646 16:44:38.567096 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9647 16:44:38.570461 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9648 16:44:38.574131 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9649 16:44:38.580455 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9650 16:44:38.583994 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9651 16:44:38.590697 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9652 16:44:38.593831 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9653 16:44:38.597103 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9654 16:44:38.603937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9655 16:44:38.607214 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9656 16:44:38.613843 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9657 16:44:38.617313 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9658 16:44:38.620506 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9659 16:44:38.627653 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9660 16:44:38.630375 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9661 16:44:38.634203 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9662 16:44:38.641034 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9663 16:44:38.644196 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9664 16:44:38.650860 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9665 16:44:38.654111 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9666 16:44:38.657375 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9667 16:44:38.664104 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9668 16:44:38.667251 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9669 16:44:38.674365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9670 16:44:38.677408 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9671 16:44:38.680567 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9672 16:44:38.687286 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9673 16:44:38.690537 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9674 16:44:38.693979 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9675 16:44:38.700112 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9676 16:44:38.703955 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9677 16:44:38.710286 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9678 16:44:38.713642 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9679 16:44:38.717291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9680 16:44:38.724059 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9681 16:44:38.727267 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9682 16:44:38.733666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9683 16:44:38.736923 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9684 16:44:38.740239 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9685 16:44:38.747382 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9686 16:44:38.750653 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9687 16:44:38.753957 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9688 16:44:38.760537 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9689 16:44:38.763956 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9690 16:44:38.770262 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9691 16:44:38.773468 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9692 16:44:38.776773 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9693 16:44:38.783380 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9694 16:44:38.787135 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9695 16:44:38.793448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9696 16:44:38.796951 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9697 16:44:38.800134 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9698 16:44:38.807199 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9699 16:44:38.810295 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9700 16:44:38.816622 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9701 16:44:38.819929 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9702 16:44:38.823901 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9703 16:44:38.829885 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9704 16:44:38.833815 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9705 16:44:38.840010 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9706 16:44:38.843321 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9707 16:44:38.846522 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9708 16:44:38.853740 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9709 16:44:38.856986 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9710 16:44:38.863645 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9711 16:44:38.866789 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9712 16:44:38.873309 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9713 16:44:38.876997 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9714 16:44:38.880424 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9715 16:44:38.886892 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9716 16:44:38.890134 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9717 16:44:38.896852 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9718 16:44:38.900034 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9719 16:44:38.903073 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9720 16:44:38.909963 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9721 16:44:38.913560 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9722 16:44:38.919774 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9723 16:44:38.922981 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9724 16:44:38.929651 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9725 16:44:38.933507 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9726 16:44:38.936441 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9727 16:44:38.943323 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9728 16:44:38.946523 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9729 16:44:38.952838 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9730 16:44:38.956206 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9731 16:44:38.959604 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9732 16:44:38.966720 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9733 16:44:38.970054 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9734 16:44:38.976601 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9735 16:44:38.979636 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9736 16:44:38.986341 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9737 16:44:38.989497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9738 16:44:38.992906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9739 16:44:38.999734 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9740 16:44:39.002905 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9741 16:44:39.009670 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9742 16:44:39.012963 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9743 16:44:39.015985 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9744 16:44:39.019603 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9745 16:44:39.022638 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9746 16:44:39.029601 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9747 16:44:39.032849 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9748 16:44:39.036036 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9749 16:44:39.042563 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9750 16:44:39.046209 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9751 16:44:39.049203 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9752 16:44:39.055989 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9753 16:44:39.059219 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9754 16:44:39.065727 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9755 16:44:39.069568 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9756 16:44:39.072915 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9757 16:44:39.078960 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9758 16:44:39.082546 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9759 16:44:39.089131 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9760 16:44:39.092442 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9761 16:44:39.095718 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9762 16:44:39.102319 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9763 16:44:39.105997 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9764 16:44:39.108927 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9765 16:44:39.115964 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9766 16:44:39.118952 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9767 16:44:39.122789 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9768 16:44:39.129005 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9769 16:44:39.132212 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9770 16:44:39.138652 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9771 16:44:39.142037 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9772 16:44:39.145888 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9773 16:44:39.152199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9774 16:44:39.155339 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9775 16:44:39.159251 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9776 16:44:39.165494 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9777 16:44:39.168658 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9778 16:44:39.172095 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9779 16:44:39.179227 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9780 16:44:39.182156 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9781 16:44:39.185397 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9782 16:44:39.192293 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9783 16:44:39.195692 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9784 16:44:39.198967 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9785 16:44:39.202353 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9786 16:44:39.205728 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9787 16:44:39.212217 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9788 16:44:39.215422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9789 16:44:39.218913 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9790 16:44:39.222389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9791 16:44:39.229240 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9792 16:44:39.232272 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9793 16:44:39.235808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9794 16:44:39.242051 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9795 16:44:39.245948 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9796 16:44:39.249216 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9797 16:44:39.255721 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9798 16:44:39.258636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9799 16:44:39.265205 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9800 16:44:39.269033 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9801 16:44:39.275344 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9802 16:44:39.278621 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9803 16:44:39.281852 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9804 16:44:39.288537 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9805 16:44:39.291657 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9806 16:44:39.298876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9807 16:44:39.302072 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9808 16:44:39.305436 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9809 16:44:39.311473 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9810 16:44:39.315300 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9811 16:44:39.322012 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9812 16:44:39.324923 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9813 16:44:39.331550 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9814 16:44:39.334831 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9815 16:44:39.337946 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9816 16:44:39.345052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9817 16:44:39.348204 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9818 16:44:39.351250 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9819 16:44:39.358387 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9820 16:44:39.361566 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9821 16:44:39.367869 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9822 16:44:39.371160 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9823 16:44:39.377727 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9824 16:44:39.381311 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9825 16:44:39.384448 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9826 16:44:39.391667 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9827 16:44:39.394914 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9828 16:44:39.400922 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9829 16:44:39.404582 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9830 16:44:39.408041 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9831 16:44:39.414455 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9832 16:44:39.417723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9833 16:44:39.424356 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9834 16:44:39.427632 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9835 16:44:39.431439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9836 16:44:39.438020 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9837 16:44:39.441255 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9838 16:44:39.447638 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9839 16:44:39.451252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9840 16:44:39.457595 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9841 16:44:39.461383 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9842 16:44:39.464440 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9843 16:44:39.470876 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9844 16:44:39.474012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9845 16:44:39.480620 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9846 16:44:39.484322 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9847 16:44:39.487465 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9848 16:44:39.494502 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9849 16:44:39.497551 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9850 16:44:39.503977 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9851 16:44:39.507236 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9852 16:44:39.511057 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9853 16:44:39.517730 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9854 16:44:39.520922 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9855 16:44:39.527538 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9856 16:44:39.530938 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9857 16:44:39.533975 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9858 16:44:39.540943 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9859 16:44:39.544160 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9860 16:44:39.550507 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9861 16:44:39.554357 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9862 16:44:39.557286 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9863 16:44:39.564448 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9864 16:44:39.567316 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9865 16:44:39.574101 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9866 16:44:39.577368 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9867 16:44:39.580759 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9868 16:44:39.587156 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9869 16:44:39.590448 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9870 16:44:39.597530 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9871 16:44:39.600482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9872 16:44:39.607287 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9873 16:44:39.610646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9874 16:44:39.613943 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9875 16:44:39.620574 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9876 16:44:39.623763 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9877 16:44:39.630404 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9878 16:44:39.634269 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9879 16:44:39.640679 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9880 16:44:39.644012 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9881 16:44:39.650559 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9882 16:44:39.653739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9883 16:44:39.657225 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9884 16:44:39.663892 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9885 16:44:39.667194 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9886 16:44:39.673376 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9887 16:44:39.677118 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9888 16:44:39.683389 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9889 16:44:39.686663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9890 16:44:39.689955 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9891 16:44:39.697114 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9892 16:44:39.700287 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9893 16:44:39.706482 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9894 16:44:39.709703 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9895 16:44:39.716595 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9896 16:44:39.719851 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9897 16:44:39.726326 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9898 16:44:39.730292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9899 16:44:39.733649 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9900 16:44:39.739957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9901 16:44:39.742926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9902 16:44:39.750040 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9903 16:44:39.753297 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9904 16:44:39.759820 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9905 16:44:39.762924 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9906 16:44:39.766736 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9907 16:44:39.773382 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9908 16:44:39.776716 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9909 16:44:39.783325 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9910 16:44:39.786323 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9911 16:44:39.792765 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9912 16:44:39.796019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9913 16:44:39.803079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9914 16:44:39.806280 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9915 16:44:39.809386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9916 16:44:39.816364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9917 16:44:39.819327 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9918 16:44:39.826257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9919 16:44:39.829625 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9920 16:44:39.835993 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9921 16:44:39.839540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9922 16:44:39.842854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9923 16:44:39.849386 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9924 16:44:39.853120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9925 16:44:39.859635 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9926 16:44:39.863048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9927 16:44:39.869730 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9928 16:44:39.872922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9929 16:44:39.879122 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9930 16:44:39.883021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9931 16:44:39.889238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9932 16:44:39.892516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9933 16:44:39.899520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9934 16:44:39.902735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9935 16:44:39.909234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9936 16:44:39.912568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9937 16:44:39.918933 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9938 16:44:39.922597 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9939 16:44:39.928931 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9940 16:44:39.932180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9941 16:44:39.939266 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9942 16:44:39.942521 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9943 16:44:39.949349 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9944 16:44:39.952562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9945 16:44:39.959001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9946 16:44:39.962381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9947 16:44:39.965655 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9948 16:44:39.968994 INFO: [APUAPC] vio 0
9949 16:44:39.975902 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9950 16:44:39.979140 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9951 16:44:39.982063 INFO: [APUAPC] D0_APC_0: 0x400510
9952 16:44:39.985713 INFO: [APUAPC] D0_APC_1: 0x0
9953 16:44:39.988669 INFO: [APUAPC] D0_APC_2: 0x1540
9954 16:44:39.992544 INFO: [APUAPC] D0_APC_3: 0x0
9955 16:44:39.995214 INFO: [APUAPC] D1_APC_0: 0xffffffff
9956 16:44:39.998920 INFO: [APUAPC] D1_APC_1: 0xffffffff
9957 16:44:40.002145 INFO: [APUAPC] D1_APC_2: 0x3fffff
9958 16:44:40.005334 INFO: [APUAPC] D1_APC_3: 0x0
9959 16:44:40.008642 INFO: [APUAPC] D2_APC_0: 0xffffffff
9960 16:44:40.011852 INFO: [APUAPC] D2_APC_1: 0xffffffff
9961 16:44:40.015242 INFO: [APUAPC] D2_APC_2: 0x3fffff
9962 16:44:40.018953 INFO: [APUAPC] D2_APC_3: 0x0
9963 16:44:40.022194 INFO: [APUAPC] D3_APC_0: 0xffffffff
9964 16:44:40.025465 INFO: [APUAPC] D3_APC_1: 0xffffffff
9965 16:44:40.028703 INFO: [APUAPC] D3_APC_2: 0x3fffff
9966 16:44:40.028787 INFO: [APUAPC] D3_APC_3: 0x0
9967 16:44:40.035443 INFO: [APUAPC] D4_APC_0: 0xffffffff
9968 16:44:40.038715 INFO: [APUAPC] D4_APC_1: 0xffffffff
9969 16:44:40.041922 INFO: [APUAPC] D4_APC_2: 0x3fffff
9970 16:44:40.042004 INFO: [APUAPC] D4_APC_3: 0x0
9971 16:44:40.045174 INFO: [APUAPC] D5_APC_0: 0xffffffff
9972 16:44:40.048944 INFO: [APUAPC] D5_APC_1: 0xffffffff
9973 16:44:40.051651 INFO: [APUAPC] D5_APC_2: 0x3fffff
9974 16:44:40.055262 INFO: [APUAPC] D5_APC_3: 0x0
9975 16:44:40.058558 INFO: [APUAPC] D6_APC_0: 0xffffffff
9976 16:44:40.061882 INFO: [APUAPC] D6_APC_1: 0xffffffff
9977 16:44:40.065111 INFO: [APUAPC] D6_APC_2: 0x3fffff
9978 16:44:40.068342 INFO: [APUAPC] D6_APC_3: 0x0
9979 16:44:40.072212 INFO: [APUAPC] D7_APC_0: 0xffffffff
9980 16:44:40.075424 INFO: [APUAPC] D7_APC_1: 0xffffffff
9981 16:44:40.078827 INFO: [APUAPC] D7_APC_2: 0x3fffff
9982 16:44:40.081892 INFO: [APUAPC] D7_APC_3: 0x0
9983 16:44:40.084867 INFO: [APUAPC] D8_APC_0: 0xffffffff
9984 16:44:40.088752 INFO: [APUAPC] D8_APC_1: 0xffffffff
9985 16:44:40.091723 INFO: [APUAPC] D8_APC_2: 0x3fffff
9986 16:44:40.095455 INFO: [APUAPC] D8_APC_3: 0x0
9987 16:44:40.098726 INFO: [APUAPC] D9_APC_0: 0xffffffff
9988 16:44:40.101696 INFO: [APUAPC] D9_APC_1: 0xffffffff
9989 16:44:40.104985 INFO: [APUAPC] D9_APC_2: 0x3fffff
9990 16:44:40.108782 INFO: [APUAPC] D9_APC_3: 0x0
9991 16:44:40.111911 INFO: [APUAPC] D10_APC_0: 0xffffffff
9992 16:44:40.115217 INFO: [APUAPC] D10_APC_1: 0xffffffff
9993 16:44:40.118390 INFO: [APUAPC] D10_APC_2: 0x3fffff
9994 16:44:40.121719 INFO: [APUAPC] D10_APC_3: 0x0
9995 16:44:40.124958 INFO: [APUAPC] D11_APC_0: 0xffffffff
9996 16:44:40.128731 INFO: [APUAPC] D11_APC_1: 0xffffffff
9997 16:44:40.131925 INFO: [APUAPC] D11_APC_2: 0x3fffff
9998 16:44:40.135127 INFO: [APUAPC] D11_APC_3: 0x0
9999 16:44:40.138309 INFO: [APUAPC] D12_APC_0: 0xffffffff
10000 16:44:40.141578 INFO: [APUAPC] D12_APC_1: 0xffffffff
10001 16:44:40.144724 INFO: [APUAPC] D12_APC_2: 0x3fffff
10002 16:44:40.148462 INFO: [APUAPC] D12_APC_3: 0x0
10003 16:44:40.151714 INFO: [APUAPC] D13_APC_0: 0xffffffff
10004 16:44:40.154985 INFO: [APUAPC] D13_APC_1: 0xffffffff
10005 16:44:40.158339 INFO: [APUAPC] D13_APC_2: 0x3fffff
10006 16:44:40.161595 INFO: [APUAPC] D13_APC_3: 0x0
10007 16:44:40.164645 INFO: [APUAPC] D14_APC_0: 0xffffffff
10008 16:44:40.168045 INFO: [APUAPC] D14_APC_1: 0xffffffff
10009 16:44:40.171256 INFO: [APUAPC] D14_APC_2: 0x3fffff
10010 16:44:40.175095 INFO: [APUAPC] D14_APC_3: 0x0
10011 16:44:40.178369 INFO: [APUAPC] D15_APC_0: 0xffffffff
10012 16:44:40.181650 INFO: [APUAPC] D15_APC_1: 0xffffffff
10013 16:44:40.184899 INFO: [APUAPC] D15_APC_2: 0x3fffff
10014 16:44:40.188156 INFO: [APUAPC] D15_APC_3: 0x0
10015 16:44:40.191279 INFO: [APUAPC] APC_CON: 0x4
10016 16:44:40.194467 INFO: [NOCDAPC] D0_APC_0: 0x0
10017 16:44:40.198220 INFO: [NOCDAPC] D0_APC_1: 0x0
10018 16:44:40.201229 INFO: [NOCDAPC] D1_APC_0: 0x0
10019 16:44:40.204965 INFO: [NOCDAPC] D1_APC_1: 0xfff
10020 16:44:40.205047 INFO: [NOCDAPC] D2_APC_0: 0x0
10021 16:44:40.208139 INFO: [NOCDAPC] D2_APC_1: 0xfff
10022 16:44:40.211675 INFO: [NOCDAPC] D3_APC_0: 0x0
10023 16:44:40.214929 INFO: [NOCDAPC] D3_APC_1: 0xfff
10024 16:44:40.217973 INFO: [NOCDAPC] D4_APC_0: 0x0
10025 16:44:40.221367 INFO: [NOCDAPC] D4_APC_1: 0xfff
10026 16:44:40.225235 INFO: [NOCDAPC] D5_APC_0: 0x0
10027 16:44:40.228442 INFO: [NOCDAPC] D5_APC_1: 0xfff
10028 16:44:40.231765 INFO: [NOCDAPC] D6_APC_0: 0x0
10029 16:44:40.234717 INFO: [NOCDAPC] D6_APC_1: 0xfff
10030 16:44:40.234814 INFO: [NOCDAPC] D7_APC_0: 0x0
10031 16:44:40.238476 INFO: [NOCDAPC] D7_APC_1: 0xfff
10032 16:44:40.241654 INFO: [NOCDAPC] D8_APC_0: 0x0
10033 16:44:40.244983 INFO: [NOCDAPC] D8_APC_1: 0xfff
10034 16:44:40.248231 INFO: [NOCDAPC] D9_APC_0: 0x0
10035 16:44:40.251724 INFO: [NOCDAPC] D9_APC_1: 0xfff
10036 16:44:40.254943 INFO: [NOCDAPC] D10_APC_0: 0x0
10037 16:44:40.258131 INFO: [NOCDAPC] D10_APC_1: 0xfff
10038 16:44:40.261255 INFO: [NOCDAPC] D11_APC_0: 0x0
10039 16:44:40.264572 INFO: [NOCDAPC] D11_APC_1: 0xfff
10040 16:44:40.267909 INFO: [NOCDAPC] D12_APC_0: 0x0
10041 16:44:40.271640 INFO: [NOCDAPC] D12_APC_1: 0xfff
10042 16:44:40.275058 INFO: [NOCDAPC] D13_APC_0: 0x0
10043 16:44:40.275140 INFO: [NOCDAPC] D13_APC_1: 0xfff
10044 16:44:40.278290 INFO: [NOCDAPC] D14_APC_0: 0x0
10045 16:44:40.281673 INFO: [NOCDAPC] D14_APC_1: 0xfff
10046 16:44:40.284942 INFO: [NOCDAPC] D15_APC_0: 0x0
10047 16:44:40.288039 INFO: [NOCDAPC] D15_APC_1: 0xfff
10048 16:44:40.291519 INFO: [NOCDAPC] APC_CON: 0x4
10049 16:44:40.294783 INFO: [APUAPC] set_apusys_apc done
10050 16:44:40.297924 INFO: [DEVAPC] devapc_init done
10051 16:44:40.301288 INFO: GICv3 without legacy support detected.
10052 16:44:40.304640 INFO: ARM GICv3 driver initialized in EL3
10053 16:44:40.311423 INFO: Maximum SPI INTID supported: 639
10054 16:44:40.314419 INFO: BL31: Initializing runtime services
10055 16:44:40.321352 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10056 16:44:40.321462 INFO: SPM: enable CPC mode
10057 16:44:40.328284 INFO: mcdi ready for mcusys-off-idle and system suspend
10058 16:44:40.331024 INFO: BL31: Preparing for EL3 exit to normal world
10059 16:44:40.334350 INFO: Entry point address = 0x80000000
10060 16:44:40.338277 INFO: SPSR = 0x8
10061 16:44:40.343801
10062 16:44:40.343882
10063 16:44:40.343952
10064 16:44:40.346729 Starting depthcharge on Spherion...
10065 16:44:40.346833
10066 16:44:40.346912 Wipe memory regions:
10067 16:44:40.346975
10068 16:44:40.347631 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10069 16:44:40.347771 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10070 16:44:40.347869 Setting prompt string to ['asurada:']
10071 16:44:40.347956 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10072 16:44:40.350431 [0x00000040000000, 0x00000054600000)
10073 16:44:40.472477
10074 16:44:40.472615 [0x00000054660000, 0x00000080000000)
10075 16:44:40.733038
10076 16:44:40.733201 [0x000000821a7280, 0x000000ffe64000)
10077 16:44:41.477171
10078 16:44:41.477314 [0x00000100000000, 0x00000240000000)
10079 16:44:43.366399
10080 16:44:43.369507 Initializing XHCI USB controller at 0x11200000.
10081 16:44:44.407768
10082 16:44:44.410817 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10083 16:44:44.410935
10084 16:44:44.411020
10085 16:44:44.411104
10086 16:44:44.411405 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10088 16:44:44.511747 asurada: tftpboot 192.168.201.1 10576287/tftp-deploy-7h04q_ty/kernel/image.itb 10576287/tftp-deploy-7h04q_ty/kernel/cmdline
10089 16:44:44.511901 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10090 16:44:44.512020 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10091 16:44:44.516729 tftpboot 192.168.201.1 10576287/tftp-deploy-7h04q_ty/kernel/image.itbtp-deploy-7h04q_ty/kernel/cmdline
10092 16:44:44.516838
10093 16:44:44.516923 Waiting for link
10094 16:44:44.676984
10095 16:44:44.677136 R8152: Initializing
10096 16:44:44.677230
10097 16:44:44.680106 Version 9 (ocp_data = 6010)
10098 16:44:44.680192
10099 16:44:44.683726 R8152: Done initializing
10100 16:44:44.683811
10101 16:44:44.683895 Adding net device
10102 16:44:46.630179
10103 16:44:46.630763 done.
10104 16:44:46.631248
10105 16:44:46.631701 MAC: 00:e0:4c:78:7a:aa
10106 16:44:46.632146
10107 16:44:46.632915 Sending DHCP discover... done.
10108 16:44:46.633310
10109 16:44:46.636471 Waiting for reply... done.
10110 16:44:46.637055
10111 16:44:46.639472 Sending DHCP request... done.
10112 16:44:46.639965
10113 16:44:46.640565 Waiting for reply... done.
10114 16:44:46.643143
10115 16:44:46.643799 My ip is 192.168.201.12
10116 16:44:46.644282
10117 16:44:46.646505 The DHCP server ip is 192.168.201.1
10118 16:44:46.646992
10119 16:44:46.650279 TFTP server IP predefined by user: 192.168.201.1
10120 16:44:46.650765
10121 16:44:46.656421 Bootfile predefined by user: 10576287/tftp-deploy-7h04q_ty/kernel/image.itb
10122 16:44:46.657017
10123 16:44:46.659387 Sending tftp read request... done.
10124 16:44:46.659871
10125 16:44:46.668092 Waiting for the transfer...
10126 16:44:46.668576
10127 16:44:46.992490 00000000 ################################################################
10128 16:44:46.992668
10129 16:44:47.370940 00080000 ################################################################
10130 16:44:47.371458
10131 16:44:47.691134 00100000 ################################################################
10132 16:44:47.691282
10133 16:44:47.943169 00180000 ################################################################
10134 16:44:47.943310
10135 16:44:48.218594 00200000 ################################################################
10136 16:44:48.218744
10137 16:44:48.476288 00280000 ################################################################
10138 16:44:48.476457
10139 16:44:48.767054 00300000 ################################################################
10140 16:44:48.767190
10141 16:44:49.033058 00380000 ################################################################
10142 16:44:49.033195
10143 16:44:49.310558 00400000 ################################################################
10144 16:44:49.310697
10145 16:44:49.582292 00480000 ################################################################
10146 16:44:49.582431
10147 16:44:49.838199 00500000 ################################################################
10148 16:44:49.838331
10149 16:44:50.090056 00580000 ################################################################
10150 16:44:50.090202
10151 16:44:50.351004 00600000 ################################################################
10152 16:44:50.351141
10153 16:44:50.621117 00680000 ################################################################
10154 16:44:50.621261
10155 16:44:50.886874 00700000 ################################################################
10156 16:44:50.887055
10157 16:44:51.151451 00780000 ################################################################
10158 16:44:51.151584
10159 16:44:51.417660 00800000 ################################################################
10160 16:44:51.417819
10161 16:44:51.670204 00880000 ################################################################
10162 16:44:51.670357
10163 16:44:51.938323 00900000 ################################################################
10164 16:44:51.938477
10165 16:44:52.229603 00980000 ################################################################
10166 16:44:52.229777
10167 16:44:52.476579 00a00000 ################################################################
10168 16:44:52.476739
10169 16:44:52.747179 00a80000 ################################################################
10170 16:44:52.747315
10171 16:44:53.009108 00b00000 ################################################################
10172 16:44:53.009267
10173 16:44:53.275506 00b80000 ################################################################
10174 16:44:53.275665
10175 16:44:53.537680 00c00000 ################################################################
10176 16:44:53.537815
10177 16:44:53.825538 00c80000 ################################################################
10178 16:44:53.825688
10179 16:44:54.106490 00d00000 ################################################################
10180 16:44:54.106622
10181 16:44:54.385199 00d80000 ################################################################
10182 16:44:54.385355
10183 16:44:54.659666 00e00000 ################################################################
10184 16:44:54.659802
10185 16:44:54.914886 00e80000 ################################################################
10186 16:44:54.915018
10187 16:44:55.180630 00f00000 ################################################################
10188 16:44:55.180767
10189 16:44:55.459125 00f80000 ################################################################
10190 16:44:55.459278
10191 16:44:55.719036 01000000 ################################################################
10192 16:44:55.719201
10193 16:44:55.967040 01080000 ################################################################
10194 16:44:55.967204
10195 16:44:56.214839 01100000 ################################################################
10196 16:44:56.215005
10197 16:44:56.479838 01180000 ################################################################
10198 16:44:56.479979
10199 16:44:56.732652 01200000 ################################################################
10200 16:44:56.732788
10201 16:44:56.986812 01280000 ################################################################
10202 16:44:56.986948
10203 16:44:57.239050 01300000 ################################################################
10204 16:44:57.239190
10205 16:44:57.499025 01380000 ################################################################
10206 16:44:57.499160
10207 16:44:57.759273 01400000 ################################################################
10208 16:44:57.759449
10209 16:44:58.013332 01480000 ################################################################
10210 16:44:58.013467
10211 16:44:58.263461 01500000 ################################################################
10212 16:44:58.263608
10213 16:44:58.536465 01580000 ################################################################
10214 16:44:58.536614
10215 16:44:58.819748 01600000 ################################################################
10216 16:44:58.819889
10217 16:44:59.076323 01680000 ################################################################
10218 16:44:59.076470
10219 16:44:59.357342 01700000 ################################################################
10220 16:44:59.357497
10221 16:44:59.616541 01780000 ################################################################
10222 16:44:59.616680
10223 16:44:59.871233 01800000 ################################################################
10224 16:44:59.871371
10225 16:45:00.147330 01880000 ################################################################
10226 16:45:00.147467
10227 16:45:00.422222 01900000 ################################################################
10228 16:45:00.422371
10229 16:45:00.692598 01980000 ################################################################
10230 16:45:00.692738
10231 16:45:00.932690 01a00000 ############################################################### done.
10232 16:45:00.932829
10233 16:45:00.936538 The bootfile was 27774554 bytes long.
10234 16:45:00.936623
10235 16:45:00.939907 Sending tftp read request... done.
10236 16:45:00.939997
10237 16:45:00.943006 Waiting for the transfer...
10238 16:45:00.943102
10239 16:45:00.943177 00000000 # done.
10240 16:45:00.943248
10241 16:45:00.953139 Command line loaded dynamically from TFTP file: 10576287/tftp-deploy-7h04q_ty/kernel/cmdline
10242 16:45:00.953338
10243 16:45:00.969739 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10244 16:45:00.969974
10245 16:45:00.970097 Loading FIT.
10246 16:45:00.970211
10247 16:45:00.972811 Image ramdisk-1 has 17642121 bytes.
10248 16:45:00.972996
10249 16:45:00.976536 Image fdt-1 has 46924 bytes.
10250 16:45:00.976795
10251 16:45:00.979727 Image kernel-1 has 10083474 bytes.
10252 16:45:00.980019
10253 16:45:00.989577 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10254 16:45:00.989978
10255 16:45:01.006508 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10256 16:45:01.007087
10257 16:45:01.010156 Choosing best match conf-1 for compat google,spherion-rev2.
10258 16:45:01.015569
10259 16:45:01.020094 Connected to device vid:did:rid of 1ae0:0028:00
10260 16:45:01.028386
10261 16:45:01.031761 tpm_get_response: command 0x17b, return code 0x0
10262 16:45:01.032356
10263 16:45:01.034884 ec_init: CrosEC protocol v3 supported (256, 248)
10264 16:45:01.039202
10265 16:45:01.042737 tpm_cleanup: add release locality here.
10266 16:45:01.043167
10267 16:45:01.043688 Shutting down all USB controllers.
10268 16:45:01.045654
10269 16:45:01.046082 Removing current net device
10270 16:45:01.046419
10271 16:45:01.052306 Exiting depthcharge with code 4 at timestamp: 49955926
10272 16:45:01.052831
10273 16:45:01.055805 LZMA decompressing kernel-1 to 0x821a6718
10274 16:45:01.056236
10275 16:45:01.059089 LZMA decompressing kernel-1 to 0x40000000
10276 16:45:02.324976
10277 16:45:02.325504 jumping to kernel
10278 16:45:02.326871 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10279 16:45:02.327437 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10280 16:45:02.327829 Setting prompt string to ['Linux version [0-9]']
10281 16:45:02.328181 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10282 16:45:02.328526 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10283 16:45:02.872346
10284 16:45:02.875613 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10285 16:45:02.879149 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10286 16:45:02.879620 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10287 16:45:02.880122 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10288 16:45:02.880520 Using line separator: #'\n'#
10289 16:45:02.880914 No login prompt set.
10290 16:45:02.881237 Parsing kernel messages
10291 16:45:02.881555 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10292 16:45:02.882173 [login-action] Waiting for messages, (timeout 00:04:03)
10293 16:45:02.898559 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1605284-arm64-gcc-10-defconfig-arm64-chromebook-tw8wr) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023
10294 16:45:02.902302 [ 0.000000] random: crng init done
10295 16:45:02.909133 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 16:45:02.912039 [ 0.000000] efi: UEFI not found.
10297 16:45:02.918526 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 16:45:02.925561 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 16:45:02.935508 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 16:45:02.945613 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 16:45:02.948589 [ 0.000000] NUMA: No NUMA configuration found
10302 16:45:02.955158 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10303 16:45:02.962272 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10304 16:45:02.964863 [ 0.000000] Zone ranges:
10305 16:45:02.971762 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10306 16:45:02.975318 [ 0.000000] DMA32 empty
10307 16:45:02.978289 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10308 16:45:02.984832 [ 0.000000] Movable zone start for each node
10309 16:45:02.988702 [ 0.000000] Early memory node ranges
10310 16:45:02.995166 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10311 16:45:03.001725 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10312 16:45:03.008366 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10313 16:45:03.011408 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10314 16:45:03.018036 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10315 16:45:03.024982 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10316 16:45:03.031280 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10317 16:45:03.038394 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10318 16:45:03.044648 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10319 16:45:03.048104 [ 0.000000] psci: probing for conduit method from DT.
10320 16:45:03.054360 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10321 16:45:03.057878 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10322 16:45:03.064231 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10323 16:45:03.067846 [ 0.000000] psci: SMC Calling Convention v1.2
10324 16:45:03.074531 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10325 16:45:03.077287 [ 0.000000] Detected VIPT I-cache on CPU0
10326 16:45:03.084106 [ 0.000000] CPU features: detected: GIC system register CPU interface
10327 16:45:03.091155 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10328 16:45:03.097980 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10329 16:45:03.104157 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10330 16:45:03.110641 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10331 16:45:03.117691 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10332 16:45:03.124478 [ 0.000000] alternatives: applying boot alternatives
10333 16:45:03.127717 [ 0.000000] Fallback order for Node 0: 0
10334 16:45:03.134268 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10335 16:45:03.136909 [ 0.000000] Policy zone: Normal
10336 16:45:03.157117 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10337 16:45:03.166927 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10338 16:45:03.173874 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10339 16:45:03.180395 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10340 16:45:03.186486 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10341 16:45:03.189839 [ 0.000000] software IO TLB: area num 8.
10342 16:45:03.199926 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10343 16:45:03.212999 [ 0.000000] Memory: 7955708K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397060K reserved, 32768K cma-reserved)
10344 16:45:03.219865 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10345 16:45:03.226782 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10346 16:45:03.229966 [ 0.000000] rcu: RCU event tracing is enabled.
10347 16:45:03.236330 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10348 16:45:03.243228 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10349 16:45:03.246415 [ 0.000000] Tracing variant of Tasks RCU enabled.
10350 16:45:03.256045 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10351 16:45:03.263140 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10352 16:45:03.265959 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10353 16:45:03.272251 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10354 16:45:03.275956 [ 0.000000] GICv3: 608 SPIs implemented
10355 16:45:03.279350 [ 0.000000] GICv3: 0 Extended SPIs implemented
10356 16:45:03.285604 [ 0.000000] Root IRQ handler: gic_handle_irq
10357 16:45:03.289112 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10358 16:45:03.295825 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10359 16:45:03.305393 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10360 16:45:03.319007 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10361 16:45:03.326100 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10362 16:45:03.332082 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10363 16:45:03.342166 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10364 16:45:03.352269 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10365 16:45:03.355635 [ 0.000953] Console: colour dummy device 80x25
10366 16:45:03.365573 [ 0.001024] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10367 16:45:03.371567 [ 0.001032] pid_max: default: 32768 minimum: 301
10368 16:45:03.375320 [ 0.001073] LSM: Security Framework initializing
10369 16:45:03.381774 [ 0.001179] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 16:45:03.391463 [ 0.001230] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10371 16:45:03.397690 [ 0.002471] cblist_init_generic: Setting adjustable number of callback queues.
10372 16:45:03.404659 [ 0.002482] cblist_init_generic: Setting shift to 3 and lim to 1.
10373 16:45:03.411378 [ 0.002523] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 16:45:03.414522 [ 0.002629] rcu: Hierarchical SRCU implementation.
10375 16:45:03.421440 [ 0.002631] rcu: Max phase no-delay instances is 1000.
10376 16:45:03.424480 [ 0.004255] EFI services will not be available.
10377 16:45:03.427841 [ 0.004478] smp: Bringing up secondary CPUs ...
10378 16:45:03.434614 [ 0.004771] Detected VIPT I-cache on CPU1
10379 16:45:03.441061 [ 0.004844] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 16:45:03.447838 [ 0.004876] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 16:45:03.451130 [ 0.005223] Detected VIPT I-cache on CPU2
10382 16:45:03.458063 [ 0.005278] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 16:45:03.464401 [ 0.005295] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 16:45:03.468116 [ 0.005560] Detected VIPT I-cache on CPU3
10385 16:45:03.474259 [ 0.005609] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 16:45:03.481323 [ 0.005623] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 16:45:03.487712 [ 0.005917] CPU features: detected: Spectre-v4
10388 16:45:03.491487 [ 0.005922] CPU features: detected: Spectre-BHB
10389 16:45:03.494460 [ 0.005926] Detected PIPT I-cache on CPU4
10390 16:45:03.500949 [ 0.005978] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 16:45:03.507596 [ 0.005993] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 16:45:03.510713 [ 0.006282] Detected PIPT I-cache on CPU5
10393 16:45:03.520945 [ 0.006344] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 16:45:03.524025 [ 0.006361] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 16:45:03.530930 [ 0.006644] Detected PIPT I-cache on CPU6
10396 16:45:03.537369 [ 0.006708] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 16:45:03.544276 [ 0.006724] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 16:45:03.547357 [ 0.007027] Detected PIPT I-cache on CPU7
10399 16:45:03.553730 [ 0.007093] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 16:45:03.560097 [ 0.007109] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 16:45:03.563843 [ 0.007156] smp: Brought up 1 node, 8 CPUs
10402 16:45:03.570581 [ 0.007161] SMP: Total of 8 processors activated.
10403 16:45:03.573778 [ 0.007164] CPU features: detected: 32-bit EL0 Support
10404 16:45:03.583728 [ 0.007167] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 16:45:03.590649 [ 0.007169] CPU features: detected: Common not Private translations
10406 16:45:03.594010 [ 0.007171] CPU features: detected: CRC32 instructions
10407 16:45:03.600148 [ 0.007174] CPU features: detected: RCpc load-acquire (LDAPR)
10408 16:45:03.606953 [ 0.007176] CPU features: detected: LSE atomic instructions
10409 16:45:03.610748 [ 0.007178] CPU features: detected: Privileged Access Never
10410 16:45:03.617067 [ 0.007179] CPU features: detected: RAS Extension Support
10411 16:45:03.623706 [ 0.007182] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 16:45:03.627433 [ 0.007253] CPU: All CPU(s) started at EL2
10413 16:45:03.633774 [ 0.007255] alternatives: applying system-wide alternatives
10414 16:45:03.637314 [ 0.012224] devtmpfs: initialized
10415 16:45:03.646886 [ 0.017464] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 16:45:03.653410 [ 0.017479] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 16:45:03.660501 [ 0.018545] pinctrl core: initialized pinctrl subsystem
10418 16:45:03.663849 [ 0.019731] DMI not present or invalid.
10419 16:45:03.667021 [ 0.020072] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 16:45:03.677068 [ 0.020820] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 16:45:03.683535 [ 0.021046] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 16:45:03.690071 [ 0.021229] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 16:45:03.696822 [ 0.021255] audit: initializing netlink subsys (disabled)
10424 16:45:03.703200 [ 0.021327] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10425 16:45:03.710281 [ 0.022014] thermal_sys: Registered thermal governor 'step_wise'
10426 16:45:03.716985 [ 0.022018] thermal_sys: Registered thermal governor 'power_allocator'
10427 16:45:03.719781 [ 0.022045] cpuidle: using governor menu
10428 16:45:03.726772 [ 0.022109] NET: Registered PF_QIPCRTR protocol family
10429 16:45:03.733795 [ 0.022223] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 16:45:03.736372 [ 0.022319] ASID allocator initialised with 32768 entries
10431 16:45:03.743408 [ 0.023222] Serial: AMBA PL011 UART driver
10432 16:45:03.746614 [ 0.027502] Trying to register duplicate clock ID: 134
10433 16:45:03.749564 [ 0.079501] KASLR enabled
10434 16:45:03.756041 [ 0.084326] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 16:45:03.762891 [ 0.084330] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 16:45:03.769672 [ 0.084335] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 16:45:03.775984 [ 0.084337] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 16:45:03.783825 [ 0.084340] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 16:45:03.789882 [ 0.084342] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 16:45:03.796216 [ 0.084345] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 16:45:03.803019 [ 0.084347] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 16:45:03.806403 [ 0.085322] ACPI: Interpreter disabled.
10443 16:45:03.809588 [ 0.087654] iommu: Default domain type: Translated
10444 16:45:03.816075 [ 0.087658] iommu: DMA domain TLB invalidation policy: strict mode
10445 16:45:03.819165 [ 0.087833] SCSI subsystem initialized
10446 16:45:03.826036 [ 0.088022] usbcore: registered new interface driver usbfs
10447 16:45:03.832541 [ 0.088040] usbcore: registered new interface driver hub
10448 16:45:03.836036 [ 0.088053] usbcore: registered new device driver usb
10449 16:45:03.842640 [ 0.088864] pps_core: LinuxPPS API ver. 1 registered
10450 16:45:03.849130 [ 0.088866] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 16:45:03.855521 [ 0.088872] PTP clock support registered
10452 16:45:03.859336 [ 0.088955] EDAC MC: Ver: 3.0.0
10453 16:45:03.862259 [ 0.090710] FPGA manager framework
10454 16:45:03.865701 [ 0.090750] Advanced Linux Sound Architecture Driver Initialized.
10455 16:45:03.869286 [ 0.091200] vgaarb: loaded
10456 16:45:03.875409 [ 0.091405] clocksource: Switched to clocksource arch_sys_counter
10457 16:45:03.879365 [ 0.091525] VFS: Disk quotas dquot_6.6.0
10458 16:45:03.885985 [ 0.091553] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 16:45:03.888893 [ 0.091657] pnp: PnP ACPI: disabled
10460 16:45:03.895985 [ 0.094490] NET: Registered PF_INET protocol family
10461 16:45:03.902860 [ 0.094966] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 16:45:03.912610 [ 0.099512] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 16:45:03.919343 [ 0.099587] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 16:45:03.925452 [ 0.099601] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 16:45:03.935414 [ 0.100175] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 16:45:03.941903 [ 0.102311] TCP: Hash tables configured (established 65536 bind 65536)
10467 16:45:03.948411 [ 0.102418] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 16:45:03.955747 [ 0.102612] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 16:45:03.958680 [ 0.102873] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 16:45:03.965492 [ 0.103143] RPC: Registered named UNIX socket transport module.
10471 16:45:03.972424 [ 0.103146] RPC: Registered udp transport module.
10472 16:45:03.975059 [ 0.103148] RPC: Registered tcp transport module.
10473 16:45:03.982054 [ 0.103150] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 16:45:03.985419 [ 0.103163] PCI: CLS 0 bytes, default 64
10475 16:45:03.988618 [ 0.103424] Unpacking initramfs...
10476 16:45:03.998165 [ 0.112013] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 16:45:04.005220 [ 0.112230] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 16:45:04.008705 [ 0.112676] kvm [1]: IPA Size Limit: 40 bits
10479 16:45:04.015336 [ 0.112699] kvm [1]: GICv3: no GICV resource entry
10480 16:45:04.018144 [ 0.112703] kvm [1]: disabling GICv2 emulation
10481 16:45:04.025468 [ 0.112716] kvm [1]: GIC system register CPU interface enabled
10482 16:45:04.028525 [ 0.112805] kvm [1]: vgic interrupt IRQ18
10483 16:45:04.035194 [ 0.112906] kvm [1]: VHE mode initialized successfully
10484 16:45:04.038458 [ 0.113778] Initialise system trusted keyrings
10485 16:45:04.045216 [ 0.113872] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 16:45:04.051369 [ 0.117179] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 16:45:04.054617 [ 0.117474] NFS: Registering the id_resolver key type
10488 16:45:04.061648 [ 0.117489] Key type id_resolver registered
10489 16:45:04.064643 [ 0.117491] Key type id_legacy registered
10490 16:45:04.071556 [ 0.117527] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 16:45:04.077683 [ 0.117531] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 16:45:04.084559 [ 0.117635] 9p: Installing v9fs 9p2000 file system support
10493 16:45:04.088333 [ 0.150383] Key type asymmetric registered
10494 16:45:04.091042 [ 0.150387] Asymmetric key parser 'x509' registered
10495 16:45:04.101288 [ 0.150427] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 16:45:04.104375 [ 0.150432] io scheduler mq-deadline registered
10497 16:45:04.107781 [ 0.150436] io scheduler kyber registered
10498 16:45:04.111271 [ 0.162920] EINJ: ACPI disabled.
10499 16:45:04.121263 [ 0.185076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 16:45:04.131067 [ 0.185213] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 16:45:04.137841 [ 0.195273] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 16:45:04.144182 [ 0.196770] printk: console [ttyS0] disabled
10503 16:45:04.150749 [ 0.216914] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 16:45:04.157437 [ 0.861187] Freeing initrd memory: 17224K
10505 16:45:04.160706 [ 0.865490] printk: console [ttyS0] enabled
10506 16:45:04.164047 [ 1.507524] SuperH (H)SCI(F) driver initialized
10507 16:45:04.170974 [ 1.512536] msm_serial: driver initialized
10508 16:45:04.183592 [ 1.521165] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10509 16:45:04.189559 [ 1.529451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10510 16:45:04.199424 [ 1.537733] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10511 16:45:04.209289 [ 1.546103] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10512 16:45:04.216562 [ 1.554547] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10513 16:45:04.226985 [ 1.562999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10514 16:45:04.233144 [ 1.571279] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10515 16:45:04.242820 [ 1.579818] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10516 16:45:04.249907 [ 1.588100] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10517 16:45:04.258478 [ 1.603066] loop: module loaded
10518 16:45:04.267641 [ 1.608678] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10519 16:45:04.289761 [ 1.631279] mtk-pmic-keys: Failed to locate of_node [id: -1]
10520 16:45:04.296058 [ 1.637622] megasas: 07.719.03.00-rc1
10521 16:45:04.304855 [ 1.646763] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10522 16:45:04.314421 [ 1.654772] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10523 16:45:04.321381 [ 1.657652] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10524 16:45:04.330931 [ 1.671612] tun: Universal TUN/TAP device driver, 1.6
10525 16:45:04.338004 [ 1.672647] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 16:45:04.341660 [ 1.677392] thunder_xcv, ver 1.0
10527 16:45:04.342139 [ 1.686070] thunder_bgx, ver 1.0
10528 16:45:04.346557 [ 1.689308] nicpf, ver 1.0
10529 16:45:04.355148 [ 1.693040] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10530 16:45:04.368047 [ 1.700255] hns3: Copyright (c) 2017 Huawei Corporation.
10531 16:45:04.368576 [ 1.705583] hclge is initializing
10532 16:45:04.368913 [ 1.708897] e1000: Intel(R) PRO/1000 Network Driver
10533 16:45:04.374138 [ 1.713766] e1000: Copyright (c) 1999-2006 Intel Corporation.
10534 16:45:04.380883 [ 1.719518] e1000e: Intel(R) PRO/1000 Network Driver
10535 16:45:04.387919 [ 1.724473] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10536 16:45:04.391303 [ 1.730398] igb: Intel(R) Gigabit Ethernet Network Driver
10537 16:45:04.394162 [ 1.735787] igb: Copyright (c) 2007-2014 Intel Corporation.
10538 16:45:04.404559 [ 1.736612] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10539 16:45:04.411092 [ 1.741363] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10540 16:45:04.418157 [ 1.758385] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10541 16:45:04.421149 [ 1.764605] sky2: driver version 1.30
10542 16:45:04.427996 [ 1.769328] VFIO - User Level meta-driver version: 0.3
10543 16:45:04.436406 [ 1.777192] usbcore: registered new interface driver usb-storage
10544 16:45:04.442428 [ 1.783371] usbcore: registered new device driver onboard-usb-hub
10545 16:45:04.450817 [ 1.792132] mt6397-rtc mt6359-rtc: registered as rtc0
10546 16:45:04.460768 [ 1.797336] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-03T16:45:05 UTC (1685810705)
10547 16:45:04.463935 [ 1.806630] i2c_dev: i2c /dev entries driver
10548 16:45:04.479625 [ 1.817938] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10549 16:45:04.486524 [ 1.827908] sdhci: Secure Digital Host Controller Interface driver
10550 16:45:04.493002 [ 1.834082] sdhci: Copyright(c) Pierre Ossman
10551 16:45:04.500166 [ 1.839240] Synopsys Designware Multimedia Card Interface Driver
10552 16:45:04.503465 [ 1.845696] mmc0: CQHCI version 5.10
10553 16:45:04.509497 [ 1.846131] sdhci-pltfm: SDHCI platform and OF driver helper
10554 16:45:04.516543 [ 1.857023] ledtrig-cpu: registered to indicate activity on CPUs
10555 16:45:04.523158 [ 1.864163] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10556 16:45:04.529991 [ 1.871281] usbcore: registered new interface driver usbhid
10557 16:45:04.533727 [ 1.876848] usbhid: USB HID core driver
10558 16:45:04.539905 [ 1.880848] spi_master spi0: will run message pump with realtime priority
10559 16:45:04.582922 [ 1.917698] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10560 16:45:04.597984 [ 1.932569] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10561 16:45:04.605416 [ 1.946907] mmc0: Command Queue Engine enabled
10562 16:45:04.608853 [ 1.947502] cros-ec-spi spi0.0: Chrome EC device registered
10563 16:45:04.616113 [ 1.951373] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10564 16:45:04.622521 [ 1.964105] mmcblk0: mmc0:0001 DA4128 116 GiB
10565 16:45:04.636380 [ 1.974555] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10566 16:45:04.642951 [ 1.979690] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10567 16:45:04.646100 [ 1.985733] NET: Registered PF_PACKET protocol family
10568 16:45:04.653099 [ 1.991451] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10569 16:45:04.656526 [ 1.994431] 9pnet: Installing 9P2000 support
10570 16:45:04.663165 [ 2.000082] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10571 16:45:04.666083 [ 2.003585] Key type dns_resolver registered
10572 16:45:04.673478 [ 2.009326] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10573 16:45:04.676262 [ 2.013296] registered taskstats version 1
10574 16:45:04.683006 [ 2.023141] Loading compiled-in X.509 certificates
10575 16:45:04.714661 [ 2.049507] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10576 16:45:04.724629 [ 2.059960] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10577 16:45:04.734983 [ 2.072546] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10578 16:45:04.746269 [ 2.087805] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10579 16:45:04.753098 [ 2.094255] xhci-mtk 11200000.usb: xHCI Host Controller
10580 16:45:04.759495 [ 2.099495] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10581 16:45:04.769771 [ 2.107087] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10582 16:45:04.775986 [ 2.116252] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10583 16:45:04.779419 [ 2.122071] xhci-mtk 11200000.usb: xHCI Host Controller
10584 16:45:04.789838 [ 2.127293] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10585 16:45:04.796694 [ 2.134686] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10586 16:45:04.799960 [ 2.142146] hub 1-0:1.0: USB hub found
10587 16:45:04.803121 [ 2.145909] hub 1-0:1.0: 1 port detected
10588 16:45:04.812973 [ 2.149981] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10589 16:45:04.816424 [ 2.158321] hub 2-0:1.0: USB hub found
10590 16:45:04.819563 [ 2.162077] hub 2-0:1.0: 1 port detected
10591 16:45:04.827342 [ 2.169165] mtk-msdc 11f70000.mmc: Got CD GPIO
10592 16:45:04.844129 [ 2.182456] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10593 16:45:04.851254 [ 2.190236] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10594 16:45:04.861085 [ 2.197944] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10595 16:45:04.867359 [ 2.207332] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10596 16:45:04.877878 [ 2.215154] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10597 16:45:04.883978 [ 2.222918] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10598 16:45:04.890864 [ 2.230574] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10599 16:45:04.900945 [ 2.238134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10600 16:45:04.908148 [ 2.245695] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10601 16:45:04.917823 [ 2.256170] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10602 16:45:04.924481 [ 2.264279] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10603 16:45:04.934376 [ 2.272362] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10604 16:45:04.940870 [ 2.280444] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10605 16:45:04.951547 [ 2.288526] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10606 16:45:04.957938 [ 2.296611] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10607 16:45:04.964645 [ 2.304694] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10608 16:45:04.974365 [ 2.312776] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10609 16:45:04.981885 [ 2.320858] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10610 16:45:04.991642 [ 2.328941] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10611 16:45:04.998416 [ 2.337023] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10612 16:45:05.008481 [ 2.345105] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10613 16:45:05.014822 [ 2.353196] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10614 16:45:05.021533 [ 2.361281] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10615 16:45:05.031679 [ 2.369367] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10616 16:45:05.037970 [ 2.377988] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10617 16:45:05.044269 [ 2.385138] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10618 16:45:05.051343 [ 2.391919] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10619 16:45:05.057609 [ 2.398759] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10620 16:45:05.064473 [ 2.405785] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10621 16:45:05.075304 [ 2.412424] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10622 16:45:05.084674 [ 2.421303] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10623 16:45:05.091271 [ 2.430170] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10624 16:45:05.101430 [ 2.439212] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10625 16:45:05.112007 [ 2.448426] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10626 16:45:05.121360 [ 2.457640] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10627 16:45:05.128020 [ 2.466506] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10628 16:45:05.137824 [ 2.475719] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10629 16:45:05.147829 [ 2.484585] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10630 16:45:05.158101 [ 2.493626] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10631 16:45:05.168292 [ 2.503531] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10632 16:45:05.174663 [ 2.514682] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10633 16:45:05.182727 [ 2.524305] Trying to probe devices needed for running init ...
10634 16:45:05.206182 [ 2.547873] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10635 16:45:05.236585 [ 2.578117] hub 2-1:1.0: USB hub found
10636 16:45:05.239504 [ 2.582270] hub 2-1:1.0: 3 ports detected
10637 16:45:05.357942 [ 2.699648] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10638 16:45:05.514435 [ 2.855951] hub 1-1:1.0: USB hub found
10639 16:45:05.517735 [ 2.860046] hub 1-1:1.0: 4 ports detected
10640 16:45:05.593672 [ 2.931908] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10641 16:45:05.837071 [ 3.175541] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10642 16:45:05.970087 [ 3.311900] hub 1-1.4:1.0: USB hub found
10643 16:45:05.973917 [ 3.316291] hub 1-1.4:1.0: 2 ports detected
10644 16:45:06.269370 [ 3.607676] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10645 16:45:06.461650 [ 3.799702] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10646 16:45:17.469851 [ 14.816235] ALSA device list:
10647 16:45:17.473327 [ 14.819210] No soundcards found.
10648 16:45:17.488730 [ 14.831371] Freeing unused kernel memory: 8384K
10649 16:45:17.491726 [ 14.836054] Run /init as init process
10650 16:45:17.502555 Loading, please wait...
10651 16:45:17.521912 Starting version 247.3-7+deb11u2
10652 16:45:17.864641 [ 15.204315] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10653 16:45:17.875423 [ 15.214620] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10654 16:45:17.885301 [ 15.223943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10655 16:45:17.891326 [ 15.232399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10656 16:45:17.897811 [ 15.239672] remoteproc remoteproc0: scp is available
10657 16:45:17.905006 [ 15.242270] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10658 16:45:17.911260 [ 15.244461] usbcore: registered new interface driver r8152
10659 16:45:17.918543 [ 15.245350] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10660 16:45:17.928034 [ 15.252755] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10661 16:45:17.934541 [ 15.258139] remoteproc remoteproc0: powering up scp
10662 16:45:17.941295 [ 15.258814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10663 16:45:17.948293 [ 15.258839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10664 16:45:17.957816 [ 15.258852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10665 16:45:17.964719 [ 15.258863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10666 16:45:17.971392 [ 15.258870] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10667 16:45:17.981355 [ 15.258927] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10668 16:45:17.988048 [ 15.258996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 16:45:17.994769 [ 15.259005] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 16:45:18.004708 [ 15.259013] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 16:45:18.011002 [ 15.259082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 16:45:18.017551 [ 15.259090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10673 16:45:18.027593 [ 15.259097] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10674 16:45:18.034103 [ 15.259104] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10675 16:45:18.044022 [ 15.259112] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10676 16:45:18.050735 [ 15.267699] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10677 16:45:18.057463 [ 15.267834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10678 16:45:18.066963 [ 15.276166] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10679 16:45:18.073568 [ 15.277760] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10680 16:45:18.080625 [ 15.277822] usbcore: registered new interface driver cdc_ether
10681 16:45:18.087463 [ 15.284175] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10682 16:45:18.097734 [ 15.284338] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10683 16:45:18.100773 [ 15.288822] remoteproc remoteproc0: request_firmware failed: -2
10684 16:45:18.107150 [ 15.297013] mc: Linux media interface: v0.10
10685 16:45:18.117321 [ 15.400200] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10686 16:45:18.124368 [ 15.404787] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10687 16:45:18.127366 [ 15.404794] pci_bus 0000:00: root bus resource [bus 00-ff]
10688 16:45:18.134496 [ 15.404801] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10689 16:45:18.143669 [ 15.404807] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10690 16:45:18.150843 [ 15.404837] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10691 16:45:18.157700 [ 15.404854] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10692 16:45:18.160915 [ 15.404927] pci 0000:00:00.0: supports D1 D2
10693 16:45:18.168140 [ 15.404931] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10694 16:45:18.177599 [ 15.406693] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10695 16:45:18.180974 [ 15.406840] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10696 16:45:18.190560 [ 15.427895] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10697 16:45:18.194455 [ 15.427895] Fallback method does not support PEC.
10698 16:45:18.204051 [ 15.429360] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10699 16:45:18.210815 [ 15.437263] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10700 16:45:18.213942 [ 15.442130] Bluetooth: Core ver 2.22
10701 16:45:18.220527 [ 15.443070] NET: Registered PF_BLUETOOTH protocol family
10702 16:45:18.226966 [ 15.443074] Bluetooth: HCI device and connection manager initialized
10703 16:45:18.230559 [ 15.443100] Bluetooth: HCI socket layer initialized
10704 16:45:18.236919 [ 15.443105] Bluetooth: L2CAP socket layer initialized
10705 16:45:18.240577 [ 15.443119] Bluetooth: SCO socket layer initialized
10706 16:45:18.250209 [ 15.443717] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10707 16:45:18.256798 [ 15.443736] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10708 16:45:18.260444 [ 15.443882] pci 0000:01:00.0: supports D1 D2
10709 16:45:18.266783 [ 15.450621] videodev: Linux video capture interface: v2.00
10710 16:45:18.273586 [ 15.453989] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10711 16:45:18.280235 [ 15.468066] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 16:45:18.286754 [ 15.479550] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10713 16:45:18.293630 [ 15.503789] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10714 16:45:18.303068 [ 15.505687] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10715 16:45:18.309834 [ 15.510759] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 16:45:18.319934 [ 15.516522] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10717 16:45:18.326514 [ 15.516536] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10718 16:45:18.336007 [ 15.530787] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10719 16:45:18.342705 [ 15.530912] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10720 16:45:18.352498 [ 15.543649] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10721 16:45:18.359298 [ 15.550896] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10722 16:45:18.365688 [ 15.551425] usbcore: registered new interface driver r8153_ecm
10723 16:45:18.372499 [ 15.559659] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10724 16:45:18.379748 [ 15.598326] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10725 16:45:18.385399 [ 15.598510] usbcore: registered new interface driver btusb
10726 16:45:18.395718 [ 15.598904] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10727 16:45:18.402824 [ 15.598917] Bluetooth: hci0: Failed to load firmware file (-2)
10728 16:45:18.405623 [ 15.598923] Bluetooth: hci0: Failed to set up firmware (-2)
10729 16:45:18.415435 [ 15.598927] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10730 16:45:18.422248 [ 15.604102] pci 0000:00:00.0: PCI bridge to [bus 01]
10731 16:45:18.435425 [ 15.609992] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10732 16:45:18.441791 [ 15.613946] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10733 16:45:18.448817 [ 15.620771] usbcore: registered new interface driver uvcvideo
10734 16:45:18.455259 [ 15.621273] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10735 16:45:18.458774 [ 15.627820] r8152 2-1.3:1.0 eth0: v1.12.13
10736 16:45:18.465219 [ 15.629187] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10737 16:45:18.468504 [ 15.635540] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10738 16:45:18.476085 [ 15.819082] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10739 16:45:18.482640 [ 15.825864] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10740 16:45:18.521944 [ 15.861398] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10741 16:45:18.536217 [ 15.879380] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10742 16:45:18.546326 [ 15.886026] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10743 16:45:18.552732 [ 15.894654] cfg80211: failed to load regulatory.db
10744 16:45:18.596606 [ 15.936078] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10745 16:45:18.602556 [ 15.943363] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10746 16:45:18.626798 [ 15.969874] mt7921e 0000:01:00.0: ASIC revision: 79610010
10747 16:45:18.731856 [ 16.067995] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10748 16:45:18.734881 Begin: Loading essential drivers ... done.
10749 16:45:18.737992 Begin: Running /scripts/init-premount ... done.
10750 16:45:18.748181 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10751 16:45:18.754901 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10752 16:45:18.757941 Device /sys/class/net/enx00e04c787aaa found
10753 16:45:18.761381 done.
10754 16:45:18.815627 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10755 16:45:18.853561 [ 16.189747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 16:45:18.969141 [ 16.305443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10757 16:45:19.084831 [ 16.421279] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10758 16:45:19.200844 [ 16.537148] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10759 16:45:19.316594 [ 16.653090] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 16:45:19.432643 [ 16.769033] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10761 16:45:19.548447 [ 16.885013] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10762 16:45:19.664223 [ 17.001049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10763 16:45:19.779874 [ 17.116874] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10764 16:45:19.887231 [ 17.230790] mt7921e 0000:01:00.0: hardware init failed
10765 16:45:19.954106 IP-Config: no response after 2 secs - giving up
10766 16:45:19.988495 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10767 16:45:20.067964 [ 17.411370] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10768 16:45:21.095377 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10769 16:45:21.102115 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10770 16:45:21.108614 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10771 16:45:21.115706 host : mt8192-asurada-spherion-r0-cbg-0
10772 16:45:21.122235 domain : lava-rack
10773 16:45:21.125370 rootserver: 192.168.201.1 rootpath:
10774 16:45:21.128477 filename :
10775 16:45:21.193157 done.
10776 16:45:21.200740 Begin: Running /scripts/nfs-bottom ... done.
10777 16:45:21.217754 Begin: Running /scripts/init-bottom ... done.
10778 16:45:22.307793 [ 19.651078] NET: Registered PF_INET6 protocol family
10779 16:45:22.313755 [ 19.657684] Segment Routing with IPv6
10780 16:45:22.317185 [ 19.661395] In-situ OAM (IOAM) with IPv6
10781 16:45:22.423315 [ 19.750183] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10782 16:45:22.429613 [ 19.773609] systemd[1]: Detected architecture arm64.
10783 16:45:22.450610
10784 16:45:22.453873 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10785 16:45:22.454299
10786 16:45:22.470649 [ 19.814265] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10787 16:45:22.917866 [ 20.258962] systemd[1]: Queued start job for default target Graphical Interface.
10788 16:45:22.968760 [ 20.312662] systemd[1]: Created slice system-getty.slice.
10789 16:45:22.975568 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10790 16:45:22.992300 [ 20.336270] systemd[1]: Created slice system-modprobe.slice.
10791 16:45:22.998576 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10792 16:45:23.016830 [ 20.360830] systemd[1]: Created slice system-serial\x2dgetty.slice.
10793 16:45:23.023456 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10794 16:45:23.040943 [ 20.384756] systemd[1]: Created slice User and Session Slice.
10795 16:45:23.047317 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10796 16:45:23.067521 [ 20.408227] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10797 16:45:23.073997 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10798 16:45:23.091052 [ 20.431828] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10799 16:45:23.097426 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10800 16:45:23.118611 [ 20.455791] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10801 16:45:23.124899 [ 20.467488] systemd[1]: Reached target Local Encrypted Volumes.
10802 16:45:23.131462 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10803 16:45:23.143901 [ 20.488006] systemd[1]: Reached target Paths.
10804 16:45:23.147403 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10805 16:45:23.163434 [ 20.507728] systemd[1]: Reached target Remote File Systems.
10806 16:45:23.170308 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10807 16:45:23.183835 [ 20.527701] systemd[1]: Reached target Slices.
10808 16:45:23.186864 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10809 16:45:23.203769 [ 20.547681] systemd[1]: Reached target Swap.
10810 16:45:23.206986 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10811 16:45:23.223674 [ 20.568017] systemd[1]: Listening on initctl Compatibility Named Pipe.
10812 16:45:23.234134 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10813 16:45:23.240859 [ 20.583077] systemd[1]: Listening on Journal Audit Socket.
10814 16:45:23.246986 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10815 16:45:23.260458 [ 20.604524] systemd[1]: Listening on Journal Socket (/dev/log).
10816 16:45:23.266817 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10817 16:45:23.284231 [ 20.628064] systemd[1]: Listening on Journal Socket.
10818 16:45:23.290724 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10819 16:45:23.304723 [ 20.648530] systemd[1]: Listening on Network Service Netlink Socket.
10820 16:45:23.314557 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10821 16:45:23.330749 [ 20.674418] systemd[1]: Listening on udev Control Socket.
10822 16:45:23.337003 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10823 16:45:23.352293 [ 20.695978] systemd[1]: Listening on udev Kernel Socket.
10824 16:45:23.358464 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10825 16:45:23.407887 [ 20.752015] systemd[1]: Mounting Huge Pages File System...
10826 16:45:23.414775 Mounting [0;1;39mHuge Pages File System[0m...
10827 16:45:23.430169 [ 20.773984] systemd[1]: Mounting POSIX Message Queue File System...
10828 16:45:23.436297 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10829 16:45:23.454088 [ 20.798009] systemd[1]: Mounting Kernel Debug File System...
10830 16:45:23.460264 Mounting [0;1;39mKernel Debug File System[0m...
10831 16:45:23.479233 [ 20.820042] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10832 16:45:23.499116 [ 20.839848] systemd[1]: Starting Create list of static device nodes for the current kernel...
10833 16:45:23.505478 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10834 16:45:23.530554 [ 20.874316] systemd[1]: Starting Load Kernel Module configfs...
10835 16:45:23.536699 Starting [0;1;39mLoad Kernel Module configfs[0m...
10836 16:45:23.558627 [ 20.902334] systemd[1]: Starting Load Kernel Module drm...
10837 16:45:23.564604 Starting [0;1;39mLoad Kernel Module drm[0m...
10838 16:45:23.582195 [ 20.926377] systemd[1]: Starting Load Kernel Module fuse...
10839 16:45:23.588737 Starting [0;1;39mLoad Kernel Module fuse[0m...
10840 16:45:23.615857 [ 20.960194] fuse: init (API version 7.37)
10841 16:45:23.622976 [ 20.960393] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10842 16:45:23.633427 [ 20.977784] systemd[1]: Starting Journal Service...
10843 16:45:23.636823 Starting [0;1;39mJournal Service[0m...
10844 16:45:23.657643 [ 21.001691] systemd[1]: Starting Load Kernel Modules...
10845 16:45:23.663913 Starting [0;1;39mLoad Kernel Modules[0m...
10846 16:45:23.682413 [ 21.023244] systemd[1]: Starting Remount Root and Kernel File Systems...
10847 16:45:23.685680 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10848 16:45:23.706865 [ 21.051215] systemd[1]: Starting Coldplug All udev Devices...
10849 16:45:23.713440 Starting [0;1;39mColdplug All udev Devices[0m...
10850 16:45:23.730490 [ 21.074933] systemd[1]: Mounted Huge Pages File System.
10851 16:45:23.737401 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10852 16:45:23.752049 [ 21.096060] systemd[1]: Mounted POSIX Message Queue File System.
10853 16:45:23.758723 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10854 16:45:23.775720 [ 21.119982] systemd[1]: Mounted Kernel Debug File System.
10855 16:45:23.782427 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10856 16:45:23.800133 [ 21.140510] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10857 16:45:23.806730 [ 21.140569] systemd[1]: Finished Create list of static device nodes for the current kernel.
10858 16:45:23.817010 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10859 16:45:23.829133 [ 21.169611] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10860 16:45:23.836210 [ 21.179258] systemd[1]: modprobe@configfs.service: Succeeded.
10861 16:45:23.842476 [ 21.185844] systemd[1]: Finished Load Kernel Module configfs.
10862 16:45:23.849211 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10863 16:45:23.864688 [ 21.208756] systemd[1]: modprobe@drm.service: Succeeded.
10864 16:45:23.874760 [ 21.209876] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10865 16:45:23.877951 [ 21.214627] systemd[1]: Finished Load Kernel Module drm.
10866 16:45:23.884602 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10867 16:45:23.901002 [ 21.244786] systemd[1]: modprobe@fuse.service: Succeeded.
10868 16:45:23.910778 [ 21.245141] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10869 16:45:23.914366 [ 21.250773] systemd[1]: Finished Load Kernel Module fuse.
10870 16:45:23.920314 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10871 16:45:23.939151 [ 21.280032] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10872 16:45:23.945681 [ 21.280915] systemd[1]: Finished Load Kernel Modules.
10873 16:45:23.948886 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10874 16:45:23.964950 [ 21.308929] systemd[1]: Finished Remount Root and Kernel File Systems.
10875 16:45:23.974618 [ 21.310133] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 16:45:23.981434 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10877 16:45:24.004980 [ 21.345912] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 16:45:24.031366 [ 21.375682] systemd[1]: Mounting FUSE Control File System...
10879 16:45:24.041404 [ 21.377557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 16:45:24.045029 Mounting [0;1;39mFUSE Control File System[0m...
10881 16:45:24.063209 [ 21.406496] systemd[1]: Mounting Kernel Configuration File System...
10882 16:45:24.073089 [ 21.410452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 16:45:24.079345 Mounting [0;1;39mKernel Configuration File System[0m...
10884 16:45:24.099609 [ 21.439908] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10885 16:45:24.109212 [ 21.443687] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 16:45:24.115511 [ 21.448674] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10887 16:45:24.144069 [ 21.488130] systemd[1]: Starting Load/Save Random Seed...
10888 16:45:24.147921 Starting [0;1;39mLoad/Save Random Seed[0m...
10889 16:45:24.166737 [ 21.510719] systemd[1]: Starting Apply Kernel Variables...
10890 16:45:24.173331 Starting [0;1;39mApply Kernel Variables[0m...
10891 16:45:24.191483 [ 21.535368] systemd[1]: Starting Create System Users...
10892 16:45:24.197834 Starting [0;1;39mCreate System Users[0m...
10893 16:45:24.213842 [ 21.557615] systemd[1]: Started Journal Service.
10894 16:45:24.217352 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10895 16:45:24.234101 [ 21.568384] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10896 16:45:24.240677 [ 21.583959] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10897 16:45:24.247299 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10898 16:45:24.265287 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10899 16:45:24.284431 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10900 16:45:24.295874 See 'systemctl status systemd-udev-trigger.service' for details.
10901 16:45:24.312473 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10902 16:45:24.328579 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10903 16:45:24.344541 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10904 16:45:24.380150 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10905 16:45:24.402258 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10906 16:45:24.421391 [ 21.762305] systemd-journald[293]: Received client request to flush runtime journal.
10907 16:45:25.504634 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10908 16:45:25.520196 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10909 16:45:25.539394 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10910 16:45:25.595648 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10911 16:45:25.794806 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10912 16:45:25.831803 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10913 16:45:25.890975 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10914 16:45:25.962127 Starting [0;1;39mNetwork Service[0m...
10915 16:45:26.012721 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10916 16:45:26.068701 Starting [0;1;39mNetwork Time Synchronization[0m...
10917 16:45:26.093103 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10918 16:45:26.245276 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10919 16:45:26.277294 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10920 16:45:26.316128 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10921 16:45:26.336785 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10922 16:45:26.520045 [ 23.864628] remoteproc remoteproc0: powering up scp
10923 16:45:26.555954 [ 23.897134] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10924 16:45:26.562538 [ 23.906815] remoteproc remoteproc0: request_firmware failed: -2
10925 16:45:26.569487 [ 23.912741] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10926 16:45:26.669310 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10927 16:45:26.711102 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10928 16:45:26.727836 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10929 16:45:26.748948 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10930 16:45:26.763204 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10931 16:45:26.783127 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10932 16:45:26.795663 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10933 16:45:26.811220 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10934 16:45:27.493227 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10935 16:45:27.825787 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10936 16:45:27.848586 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10937 16:45:27.868564 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10938 16:45:27.882664 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10939 16:45:27.903529 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10940 16:45:27.915155 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10941 16:45:27.930933 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10942 16:45:27.950639 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10943 16:45:27.995663 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10944 16:45:28.041778 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10945 16:45:28.127888 Starting [0;1;39mUser Login Management[0m...
10946 16:45:28.193168 Starting [0;1;39mNetwork Name Resolution[0m...
10947 16:45:28.211207 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10948 16:45:28.340329 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10949 16:45:28.365188 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10950 16:45:28.387620 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10951 16:45:28.873123 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10952 16:45:28.891660 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10953 16:45:28.914353 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10954 16:45:28.955847 Starting [0;1;39mPermit User Sessions[0m...
10955 16:45:28.981527 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10956 16:45:29.007186 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10957 16:45:29.055519 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10958 16:45:29.071832 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10959 16:45:29.087665 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10960 16:45:29.102810 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10961 16:45:29.139075 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10962 16:45:29.175266 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10963 16:45:29.252296
10964 16:45:29.252448
10965 16:45:29.255310 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10966 16:45:29.255413
10967 16:45:29.258465 debian-bullseye-arm64 login: root (automatic login)
10968 16:45:29.258555
10969 16:45:29.258619
10970 16:45:29.533757 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sat Jun 3 16:27:28 UTC 2023 aarch64
10971 16:45:29.533909
10972 16:45:29.539910 The programs included with the Debian GNU/Linux system are free software;
10973 16:45:29.546780 the exact distribution terms for each program are described in the
10974 16:45:29.549794 individual files in /usr/share/doc/*/copyright.
10975 16:45:29.549887
10976 16:45:29.556660 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10977 16:45:29.556847 permitted by applicable law.
10978 16:45:30.273910 Matched prompt #10: / #
10980 16:45:30.274201 Setting prompt string to ['/ #']
10981 16:45:30.274298 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10983 16:45:30.274496 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10984 16:45:30.274585 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10985 16:45:30.274658 Setting prompt string to ['/ #']
10986 16:45:30.274720 Forcing a shell prompt, looking for ['/ #']
10988 16:45:30.324922 / #
10989 16:45:30.325103 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10990 16:45:30.325207 Waiting using forced prompt support (timeout 00:02:30)
10991 16:45:30.329722
10992 16:45:30.330055 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10993 16:45:30.330165 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10995 16:45:30.430556 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf'
10996 16:45:30.435143 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10576287/extract-nfsrootfs-z4ph1vnf'
10998 16:45:30.535703 / # export NFS_SERVER_IP='192.168.201.1'
10999 16:45:30.540431 export NFS_SERVER_IP='192.168.201.1'
11000 16:45:30.540764 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11001 16:45:30.540874 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
11002 16:45:30.540963 end: 2 depthcharge-action (duration 00:01:25) [common]
11003 16:45:30.541056 start: 3 lava-test-retry (timeout 00:07:50) [common]
11004 16:45:30.541142 start: 3.1 lava-test-shell (timeout 00:07:50) [common]
11005 16:45:30.541219 Using namespace: common
11007 16:45:30.641550 / # #
11008 16:45:30.641751 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11009 16:45:30.646861 #
11010 16:45:30.647197 Using /lava-10576287
11012 16:45:30.747625 / # export SHELL=/bin/bash
11013 16:45:30.752666 export SHELL=/bin/bash
11015 16:45:30.853212 / # . /lava-10576287/environment
11016 16:45:30.858072 . /lava-10576287/environment
11018 16:45:30.963930 / # /lava-10576287/bin/lava-test-runner /lava-10576287/0
11019 16:45:30.964113 Test shell timeout: 10s (minimum of the action and connection timeout)
11020 16:45:30.969247 /lava-10576287/bin/lava-test-runner /lava-10576287/0
11021 16:45:31.170407 + export TESTRUN_ID=0_timesync-off
11022 16:45:31.173941 + TESTRUN_ID=0_timesync-off
11023 16:45:31.177325 + cd /lava-10576287/0/tests/0_timesync-off
11024 16:45:31.180245 ++ cat uuid
11025 16:45:31.180342 + UUID=10576287_1.6.2.3.1
11026 16:45:31.184017 + set +x
11027 16:45:31.187412 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10576287_1.6.2.3.1>
11028 16:45:31.187700 Received signal: <STARTRUN> 0_timesync-off 10576287_1.6.2.3.1
11029 16:45:31.187781 Starting test lava.0_timesync-off (10576287_1.6.2.3.1)
11030 16:45:31.187871 Skipping test definition patterns.
11031 16:45:31.190488 + systemctl stop systemd-timesyncd
11032 16:45:31.211865 + set +x
11033 16:45:31.214824 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10576287_1.6.2.3.1>
11034 16:45:31.215104 Received signal: <ENDRUN> 0_timesync-off 10576287_1.6.2.3.1
11035 16:45:31.215201 Ending use of test pattern.
11036 16:45:31.215267 Ending test lava.0_timesync-off (10576287_1.6.2.3.1), duration 0.03
11038 16:45:31.258557 + export TESTRUN_ID=1_kselftest-arm64
11039 16:45:31.258710 + TESTRUN_ID=1_kselftest-arm64
11040 16:45:31.265330 + cd /lava-10576287/0/tests/1_kselftest-arm64
11041 16:45:31.265456 ++ cat uuid
11042 16:45:31.268272 + UUID=10576287_1.6.2.3.5
11043 16:45:31.268361 + set +x
11044 16:45:31.272291 Received signal: <STARTRUN> 1_kselftest-arm64 10576287_1.6.2.3.5
11045 16:45:31.272385 Starting test lava.1_kselftest-arm64 (10576287_1.6.2.3.5)
11046 16:45:31.272473 Skipping test definition patterns.
11047 16:45:31.275268 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10576287_1.6.2.3.5>
11048 16:45:31.275356 + cd ./automated/linux/kselftest/
11049 16:45:31.305194 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11050 16:45:31.314095 INFO: install_deps skipped
11051 16:45:31.409350 --2023-06-03 16:45:31-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.26-1281-g84d5372e0f31/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11052 16:45:31.416092 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11053 16:45:31.551474 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11054 16:45:31.695973 HTTP request sent, awaiting response... 200 OK
11055 16:45:31.699075 Length: 2713064 (2.6M) [application/octet-stream]
11056 16:45:31.702601 Saving to: 'kselftest.tar.xz'
11057 16:45:31.702697
11058 16:45:31.702763
11059 16:45:31.984854 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11060 16:45:32.274184 kselftest.tar.xz 1%[ ] 46.39K 161KB/s
11061 16:45:32.610862 kselftest.tar.xz 8%[> ] 216.08K 375KB/s
11062 16:45:32.910362 kselftest.tar.xz 30%[=====> ] 807.16K 884KB/s
11063 16:45:33.014689 kselftest.tar.xz 74%[=============> ] 1.92M 1.58MB/s
11064 16:45:33.021398 kselftest.tar.xz 100%[===================>] 2.59M 1.96MB/s in 1.3s
11065 16:45:33.021593
11066 16:45:33.255667 2023-06-03 16:45:33 (1.96 MB/s) - 'kselftest.tar.xz' saved [2713064/2713064]
11067 16:45:33.255819
11068 16:45:38.129272 skiplist:
11069 16:45:38.132130 ========================================
11070 16:45:38.135499 ========================================
11071 16:45:38.166832 arm64:tags_test
11072 16:45:38.169873 arm64:run_tags_test.sh
11073 16:45:38.169971 arm64:fake_sigreturn_bad_magic
11074 16:45:38.172866 arm64:fake_sigreturn_bad_size
11075 16:45:38.176180 arm64:fake_sigreturn_bad_size_for_magic0
11076 16:45:38.179848 arm64:fake_sigreturn_duplicated_fpsimd
11077 16:45:38.183318 arm64:fake_sigreturn_misaligned_sp
11078 16:45:38.186524 arm64:fake_sigreturn_missing_fpsimd
11079 16:45:38.189485 arm64:fake_sigreturn_sme_change_vl
11080 16:45:38.193024 arm64:fake_sigreturn_sve_change_vl
11081 16:45:38.196314 arm64:mangle_pstate_invalid_compat_toggle
11082 16:45:38.199747 arm64:mangle_pstate_invalid_daif_bits
11083 16:45:38.202874 arm64:mangle_pstate_invalid_mode_el1h
11084 16:45:38.206431 arm64:mangle_pstate_invalid_mode_el1t
11085 16:45:38.209548 arm64:mangle_pstate_invalid_mode_el2h
11086 16:45:38.212979 arm64:mangle_pstate_invalid_mode_el2t
11087 16:45:38.216090 arm64:mangle_pstate_invalid_mode_el3h
11088 16:45:38.219711 arm64:mangle_pstate_invalid_mode_el3t
11089 16:45:38.223126 arm64:sme_trap_no_sm
11090 16:45:38.226224 arm64:sme_trap_non_streaming
11091 16:45:38.226307 arm64:sme_trap_za
11092 16:45:38.229943 arm64:sme_vl
11093 16:45:38.230026 arm64:ssve_regs
11094 16:45:38.230090 arm64:sve_regs
11095 16:45:38.232798 arm64:sve_vl
11096 16:45:38.232887 arm64:za_no_regs
11097 16:45:38.236187 arm64:za_regs
11098 16:45:38.236269 arm64:pac
11099 16:45:38.236333 arm64:fp-stress
11100 16:45:38.239725 arm64:sve-ptrace
11101 16:45:38.239808 arm64:sve-probe-vls
11102 16:45:38.243048 arm64:vec-syscfg
11103 16:45:38.243161 arm64:za-fork
11104 16:45:38.246273 arm64:za-ptrace
11105 16:45:38.246355 arm64:check_buffer_fill
11106 16:45:38.249823 arm64:check_child_memory
11107 16:45:38.252978 arm64:check_gcr_el1_cswitch
11108 16:45:38.253061 arm64:check_ksm_options
11109 16:45:38.256365 arm64:check_mmap_options
11110 16:45:38.259366 arm64:check_prctl
11111 16:45:38.259449 arm64:check_tags_inclusion
11112 16:45:38.262920 arm64:check_user_mem
11113 16:45:38.263002 arm64:btitest
11114 16:45:38.266351 arm64:nobtitest
11115 16:45:38.266432 arm64:hwcap
11116 16:45:38.269642 arm64:ptrace
11117 16:45:38.269749 arm64:syscall-abi
11118 16:45:38.269835 arm64:tpidr2
11119 16:45:38.275802 ============== Tests to run ===============
11120 16:45:38.275887 arm64:tags_test
11121 16:45:38.279458 arm64:run_tags_test.sh
11122 16:45:38.282748 arm64:fake_sigreturn_bad_magic
11123 16:45:38.282831 arm64:fake_sigreturn_bad_size
11124 16:45:38.285677 arm64:fake_sigreturn_bad_size_for_magic0
11125 16:45:38.289175 arm64:fake_sigreturn_duplicated_fpsimd
11126 16:45:38.292219 arm64:fake_sigreturn_misaligned_sp
11127 16:45:38.296051 arm64:fake_sigreturn_missing_fpsimd
11128 16:45:38.299005 arm64:fake_sigreturn_sme_change_vl
11129 16:45:38.302402 arm64:fake_sigreturn_sve_change_vl
11130 16:45:38.305772 arm64:mangle_pstate_invalid_compat_toggle
11131 16:45:38.309134 arm64:mangle_pstate_invalid_daif_bits
11132 16:45:38.312134 arm64:mangle_pstate_invalid_mode_el1h
11133 16:45:38.315824 arm64:mangle_pstate_invalid_mode_el1t
11134 16:45:38.322001 arm64:mangle_pstate_invalid_mode_el2h
11135 16:45:38.325708 arm64:mangle_pstate_invalid_mode_el2t
11136 16:45:38.329141 arm64:mangle_pstate_invalid_mode_el3h
11137 16:45:38.331856 arm64:mangle_pstate_invalid_mode_el3t
11138 16:45:38.331939 arm64:sme_trap_no_sm
11139 16:45:38.335674 arm64:sme_trap_non_streaming
11140 16:45:38.335759 arm64:sme_trap_za
11141 16:45:38.338939 arm64:sme_vl
11142 16:45:38.339022 arm64:ssve_regs
11143 16:45:38.342053 arm64:sve_regs
11144 16:45:38.342136 arm64:sve_vl
11145 16:45:38.345425 arm64:za_no_regs
11146 16:45:38.345531 arm64:za_regs
11147 16:45:38.345610 arm64:pac
11148 16:45:38.348730 arm64:fp-stress
11149 16:45:38.348812 arm64:sve-ptrace
11150 16:45:38.351654 arm64:sve-probe-vls
11151 16:45:38.351738 arm64:vec-syscfg
11152 16:45:38.355497 arm64:za-fork
11153 16:45:38.355580 arm64:za-ptrace
11154 16:45:38.358390 arm64:check_buffer_fill
11155 16:45:38.358473 arm64:check_child_memory
11156 16:45:38.361565 arm64:check_gcr_el1_cswitch
11157 16:45:38.365290 arm64:check_ksm_options
11158 16:45:38.365374 arm64:check_mmap_options
11159 16:45:38.368546 arm64:check_prctl
11160 16:45:38.371542 arm64:check_tags_inclusion
11161 16:45:38.371625 arm64:check_user_mem
11162 16:45:38.374856 arm64:btitest
11163 16:45:38.374940 arm64:nobtitest
11164 16:45:38.375042 arm64:hwcap
11165 16:45:38.378498 arm64:ptrace
11166 16:45:38.378580 arm64:syscall-abi
11167 16:45:38.381710 arm64:tpidr2
11168 16:45:38.384849 ===========End Tests to run ===============
11169 16:45:38.519657 [ 35.865484] kselftest: Running tests in arm64
11170 16:45:38.527444 TAP version 13
11171 16:45:38.536950 1..48
11172 16:45:38.548928 # selftests: arm64: tags_test
11173 16:45:38.900988 ok 1 selftests: arm64: tags_test
11174 16:45:38.919267 # selftests: arm64: run_tags_test.sh
11175 16:45:38.968116 # --------------------
11176 16:45:38.971586 # running tags test
11177 16:45:38.971723 # --------------------
11178 16:45:38.974596 # [PASS]
11179 16:45:38.978253 ok 2 selftests: arm64: run_tags_test.sh
11180 16:45:38.989129 # selftests: arm64: fake_sigreturn_bad_magic
11181 16:45:39.037777 # Registered handlers for all signals.
11182 16:45:39.037924 # Detected MINSTKSIGSZ:4720
11183 16:45:39.041407 # Testcase initialized.
11184 16:45:39.044566 # uc context validated.
11185 16:45:39.047691 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11186 16:45:39.051325 # Handled SIG_COPYCTX
11187 16:45:39.051425 # Available space:3568
11188 16:45:39.057963 # Using badly built context - ERR: BAD MAGIC !
11189 16:45:39.064388 # SIG_OK -- SP:0xFFFFE8D63620 si_addr@:0xffffe8d63620 si_code:2 token@:0xffffe8d623c0 offset:-4704
11190 16:45:39.067273 # ==>> completed. PASS(1)
11191 16:45:39.074146 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11192 16:45:39.080833 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFE8D623C0
11193 16:45:39.083902 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11194 16:45:39.090389 # selftests: arm64: fake_sigreturn_bad_size
11195 16:45:39.101956 # Registered handlers for all signals.
11196 16:45:39.102083 # Detected MINSTKSIGSZ:4720
11197 16:45:39.105361 # Testcase initialized.
11198 16:45:39.108242 # uc context validated.
11199 16:45:39.111732 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11200 16:45:39.114836 # Handled SIG_COPYCTX
11201 16:45:39.114923 # Available space:3568
11202 16:45:39.118204 # uc context validated.
11203 16:45:39.124967 # Using badly built context - ERR: Bad size for esr_context
11204 16:45:39.131468 # SIG_OK -- SP:0xFFFFD1DD1FA0 si_addr@:0xffffd1dd1fa0 si_code:2 token@:0xffffd1dd0d40 offset:-4704
11205 16:45:39.134618 # ==>> completed. PASS(1)
11206 16:45:39.141295 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11207 16:45:39.147794 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD1DD0D40
11208 16:45:39.151307 ok 4 selftests: arm64: fake_sigreturn_bad_size
11209 16:45:39.158022 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11210 16:45:39.167604 # Registered handlers for all signals.
11211 16:45:39.167805 # Detected MINSTKSIGSZ:4720
11212 16:45:39.170986 # Testcase initialized.
11213 16:45:39.174165 # uc context validated.
11214 16:45:39.177237 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11215 16:45:39.180861 # Handled SIG_COPYCTX
11216 16:45:39.180986 # Available space:3568
11217 16:45:39.187695 # Using badly built context - ERR: Bad size for terminator
11218 16:45:39.197136 # SIG_OK -- SP:0xFFFFCDA95790 si_addr@:0xffffcda95790 si_code:2 token@:0xffffcda94530 offset:-4704
11219 16:45:39.197331 # ==>> completed. PASS(1)
11220 16:45:39.207076 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11221 16:45:39.214232 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDA94530
11222 16:45:39.217432 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11223 16:45:39.223993 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11224 16:45:39.236520 # Registered handlers for all signals.
11225 16:45:39.236680 # Detected MINSTKSIGSZ:4720
11226 16:45:39.239506 # Testcase initialized.
11227 16:45:39.243159 # uc context validated.
11228 16:45:39.246244 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11229 16:45:39.249840 # Handled SIG_COPYCTX
11230 16:45:39.249927 # Available space:3568
11231 16:45:39.256699 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11232 16:45:39.266352 # SIG_OK -- SP:0xFFFFF6780B40 si_addr@:0xfffff6780b40 si_code:2 token@:0xfffff677f8e0 offset:-4704
11233 16:45:39.266466 # ==>> completed. PASS(1)
11234 16:45:39.275959 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11235 16:45:39.283170 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF677F8E0
11236 16:45:39.286245 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11237 16:45:39.289208 # selftests: arm64: fake_sigreturn_misaligned_sp
11238 16:45:39.303132 # Registered handlers for all signals.
11239 16:45:39.303264 # Detected MINSTKSIGSZ:4720
11240 16:45:39.306216 # Testcase initialized.
11241 16:45:39.309064 # uc context validated.
11242 16:45:39.312644 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11243 16:45:39.316099 # Handled SIG_COPYCTX
11244 16:45:39.322426 # SIG_OK -- SP:0xFFFFFA247223 si_addr@:0xfffffa247223 si_code:2 token@:0xfffffa247223 offset:0
11245 16:45:39.325805 # ==>> completed. PASS(1)
11246 16:45:39.332356 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11247 16:45:39.339492 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFA247223
11248 16:45:39.345500 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11249 16:45:39.349059 # selftests: arm64: fake_sigreturn_missing_fpsimd
11250 16:45:39.364807 # Registered handlers for all signals.
11251 16:45:39.364933 # Detected MINSTKSIGSZ:4720
11252 16:45:39.368378 # Testcase initialized.
11253 16:45:39.371458 # uc context validated.
11254 16:45:39.375021 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11255 16:45:39.377945 # Handled SIG_COPYCTX
11256 16:45:39.381786 # Mangling template header. Spare space:4096
11257 16:45:39.384705 # Using badly built context - ERR: Missing FPSIMD
11258 16:45:39.395052 # SIG_OK -- SP:0xFFFFC5CCE2D0 si_addr@:0xffffc5cce2d0 si_code:2 token@:0xffffc5ccd070 offset:-4704
11259 16:45:39.397877 # ==>> completed. PASS(1)
11260 16:45:39.404412 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11261 16:45:39.411385 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC5CCD070
11262 16:45:39.415028 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11263 16:45:39.421470 # selftests: arm64: fake_sigreturn_sme_change_vl
11264 16:45:39.428652 # Registered handlers for all signals.
11265 16:45:39.428778 # Detected MINSTKSIGSZ:4720
11266 16:45:39.432159 # ==>> completed. SKIP.
11267 16:45:39.438518 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11268 16:45:39.441931 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11269 16:45:39.448654 # selftests: arm64: fake_sigreturn_sve_change_vl
11270 16:45:39.493134 # Registered handlers for all signals.
11271 16:45:39.493272 # Detected MINSTKSIGSZ:4720
11272 16:45:39.496227 # ==>> completed. SKIP.
11273 16:45:39.499807 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11274 16:45:39.506311 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11275 16:45:39.512759 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11276 16:45:39.556350 # Registered handlers for all signals.
11277 16:45:39.556498 # Detected MINSTKSIGSZ:4720
11278 16:45:39.559818 # Testcase initialized.
11279 16:45:39.562793 # uc context validated.
11280 16:45:39.562921 # Handled SIG_TRIG
11281 16:45:39.572745 # SIG_OK -- SP:0xFFFFFAC87600 si_addr@:0xfffffac87600 si_code:2 token@:(nil) offset:-281474889184768
11282 16:45:39.576327 # ==>> completed. PASS(1)
11283 16:45:39.582834 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11284 16:45:39.589834 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11285 16:45:39.592826 # selftests: arm64: mangle_pstate_invalid_daif_bits
11286 16:45:39.616692 # Registered handlers for all signals.
11287 16:45:39.616798 # Detected MINSTKSIGSZ:4720
11288 16:45:39.619604 # Testcase initialized.
11289 16:45:39.623158 # uc context validated.
11290 16:45:39.623243 # Handled SIG_TRIG
11291 16:45:39.633018 # SIG_OK -- SP:0xFFFFE699B510 si_addr@:0xffffe699b510 si_code:2 token@:(nil) offset:-281474550576400
11292 16:45:39.636649 # ==>> completed. PASS(1)
11293 16:45:39.642674 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11294 16:45:39.646218 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11295 16:45:39.652776 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11296 16:45:39.677894 # Registered handlers for all signals.
11297 16:45:39.678014 # Detected MINSTKSIGSZ:4720
11298 16:45:39.681716 # Testcase initialized.
11299 16:45:39.684647 # uc context validated.
11300 16:45:39.684732 # Handled SIG_TRIG
11301 16:45:39.694831 # SIG_OK -- SP:0xFFFFCE77D5C0 si_addr@:0xffffce77d5c0 si_code:2 token@:(nil) offset:-281474145703360
11302 16:45:39.697930 # ==>> completed. PASS(1)
11303 16:45:39.704802 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11304 16:45:39.708285 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11305 16:45:39.714260 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11306 16:45:39.739942 # Registered handlers for all signals.
11307 16:45:39.740060 # Detected MINSTKSIGSZ:4720
11308 16:45:39.743085 # Testcase initialized.
11309 16:45:39.746662 # uc context validated.
11310 16:45:39.746745 # Handled SIG_TRIG
11311 16:45:39.756113 # SIG_OK -- SP:0xFFFFEF5CA9D0 si_addr@:0xffffef5ca9d0 si_code:2 token@:(nil) offset:-281474697570768
11312 16:45:39.759382 # ==>> completed. PASS(1)
11313 16:45:39.766353 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11314 16:45:39.769388 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11315 16:45:39.776228 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11316 16:45:39.802109 # Registered handlers for all signals.
11317 16:45:39.802226 # Detected MINSTKSIGSZ:4720
11318 16:45:39.805161 # Testcase initialized.
11319 16:45:39.808391 # uc context validated.
11320 16:45:39.808473 # Handled SIG_TRIG
11321 16:45:39.818454 # SIG_OK -- SP:0xFFFFD04CDC20 si_addr@:0xffffd04cdc20 si_code:2 token@:(nil) offset:-281474176441376
11322 16:45:39.821575 # ==>> completed. PASS(1)
11323 16:45:39.828272 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11324 16:45:39.832006 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11325 16:45:39.838361 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11326 16:45:39.864283 # Registered handlers for all signals.
11327 16:45:39.864379 # Detected MINSTKSIGSZ:4720
11328 16:45:39.867467 # Testcase initialized.
11329 16:45:39.870886 # uc context validated.
11330 16:45:39.870973 # Handled SIG_TRIG
11331 16:45:39.880734 # SIG_OK -- SP:0xFFFFE830B700 si_addr@:0xffffe830b700 si_code:2 token@:(nil) offset:-281474577250048
11332 16:45:39.884259 # ==>> completed. PASS(1)
11333 16:45:39.890964 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11334 16:45:39.893901 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11335 16:45:39.900967 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11336 16:45:39.926767 # Registered handlers for all signals.
11337 16:45:39.926913 # Detected MINSTKSIGSZ:4720
11338 16:45:39.930531 # Testcase initialized.
11339 16:45:39.933461 # uc context validated.
11340 16:45:39.933584 # Handled SIG_TRIG
11341 16:45:39.943669 # SIG_OK -- SP:0xFFFFE244BAF0 si_addr@:0xffffe244baf0 si_code:2 token@:(nil) offset:-281474477898480
11342 16:45:39.946768 # ==>> completed. PASS(1)
11343 16:45:39.953354 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11344 16:45:39.956979 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11345 16:45:39.963626 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11346 16:45:39.986791 # Registered handlers for all signals.
11347 16:45:39.986943 # Detected MINSTKSIGSZ:4720
11348 16:45:39.990187 # Testcase initialized.
11349 16:45:39.993304 # uc context validated.
11350 16:45:39.993414 # Handled SIG_TRIG
11351 16:45:40.003199 # SIG_OK -- SP:0xFFFFF53C4AD0 si_addr@:0xfffff53c4ad0 si_code:2 token@:(nil) offset:-281474796112592
11352 16:45:40.006942 # ==>> completed. PASS(1)
11353 16:45:40.013173 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11354 16:45:40.016327 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11355 16:45:40.020277 # selftests: arm64: sme_trap_no_sm
11356 16:45:40.050074 # Registered handlers for all signals.
11357 16:45:40.050217 # Detected MINSTKSIGSZ:4720
11358 16:45:40.053860 # ==>> completed. SKIP.
11359 16:45:40.063279 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11360 16:45:40.067002 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11361 16:45:40.069998 # selftests: arm64: sme_trap_non_streaming
11362 16:45:40.111912 # Registered handlers for all signals.
11363 16:45:40.112058 # Detected MINSTKSIGSZ:4720
11364 16:45:40.114852 # ==>> completed. SKIP.
11365 16:45:40.124979 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11366 16:45:40.131707 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11367 16:45:40.134838 # selftests: arm64: sme_trap_za
11368 16:45:40.174359 # Registered handlers for all signals.
11369 16:45:40.174497 # Detected MINSTKSIGSZ:4720
11370 16:45:40.177672 # Testcase initialized.
11371 16:45:40.187503 # SIG_OK -- SP:0xFFFFE7E3BE90 si_addr@:0xaaaae8362510 si_code:1 token@:(nil) offset:-187651017024784
11372 16:45:40.187594 # ==>> completed. PASS(1)
11373 16:45:40.194446 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11374 16:45:40.197735 ok 21 selftests: arm64: sme_trap_za
11375 16:45:40.200589 # selftests: arm64: sme_vl
11376 16:45:40.235979 # Registered handlers for all signals.
11377 16:45:40.236141 # Detected MINSTKSIGSZ:4720
11378 16:45:40.238950 # ==>> completed. SKIP.
11379 16:45:40.245667 # # SME VL :: Check that we get the right SME VL reported
11380 16:45:40.248740 ok 22 selftests: arm64: sme_vl # SKIP
11381 16:45:40.248824 # selftests: arm64: ssve_regs
11382 16:45:40.295095 # Registered handlers for all signals.
11383 16:45:40.295245 # Detected MINSTKSIGSZ:4720
11384 16:45:40.298113 # ==>> completed. SKIP.
11385 16:45:40.305273 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11386 16:45:40.308305 ok 23 selftests: arm64: ssve_regs # SKIP
11387 16:45:40.311219 # selftests: arm64: sve_regs
11388 16:45:40.356921 # Registered handlers for all signals.
11389 16:45:40.357071 # Detected MINSTKSIGSZ:4720
11390 16:45:40.360262 # ==>> completed. SKIP.
11391 16:45:40.366932 # # SVE registers :: Check that we get the right SVE registers reported
11392 16:45:40.370071 ok 24 selftests: arm64: sve_regs # SKIP
11393 16:45:40.373044 # selftests: arm64: sve_vl
11394 16:45:40.418722 # Registered handlers for all signals.
11395 16:45:40.418841 # Detected MINSTKSIGSZ:4720
11396 16:45:40.422383 # ==>> completed. SKIP.
11397 16:45:40.425405 # # SVE VL :: Check that we get the right SVE VL reported
11398 16:45:40.428852 ok 25 selftests: arm64: sve_vl # SKIP
11399 16:45:40.433115 # selftests: arm64: za_no_regs
11400 16:45:40.483004 # Registered handlers for all signals.
11401 16:45:40.483107 # Detected MINSTKSIGSZ:4720
11402 16:45:40.486795 # ==>> completed. SKIP.
11403 16:45:40.493422 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11404 16:45:40.496465 ok 26 selftests: arm64: za_no_regs # SKIP
11405 16:45:40.499479 # selftests: arm64: za_regs
11406 16:45:40.544822 # Registered handlers for all signals.
11407 16:45:40.544958 # Detected MINSTKSIGSZ:4720
11408 16:45:40.548000 # ==>> completed. SKIP.
11409 16:45:40.554793 # # ZA register :: Check that we get the right ZA registers reported
11410 16:45:40.557770 ok 27 selftests: arm64: za_regs # SKIP
11411 16:45:40.557883 # selftests: arm64: pac
11412 16:45:40.605229 # TAP version 13
11413 16:45:40.605358 # 1..7
11414 16:45:40.608829 # # Starting 7 tests from 1 test cases.
11415 16:45:40.611768 # # RUN global.corrupt_pac ...
11416 16:45:40.614913 # # SKIP PAUTH not enabled
11417 16:45:40.618211 # # OK global.corrupt_pac
11418 16:45:40.621529 # ok 1 # SKIP PAUTH not enabled
11419 16:45:40.628639 # # RUN global.pac_instructions_not_nop ...
11420 16:45:40.631691 # # SKIP PAUTH not enabled
11421 16:45:40.634756 # # OK global.pac_instructions_not_nop
11422 16:45:40.638240 # ok 2 # SKIP PAUTH not enabled
11423 16:45:40.645102 # # RUN global.pac_instructions_not_nop_generic ...
11424 16:45:40.648072 # # SKIP Generic PAUTH not enabled
11425 16:45:40.651185 # # OK global.pac_instructions_not_nop_generic
11426 16:45:40.658024 # ok 3 # SKIP Generic PAUTH not enabled
11427 16:45:40.661791 # # RUN global.single_thread_different_keys ...
11428 16:45:40.664858 # # SKIP PAUTH not enabled
11429 16:45:40.671181 # # OK global.single_thread_different_keys
11430 16:45:40.671293 # ok 4 # SKIP PAUTH not enabled
11431 16:45:40.677953 # # RUN global.exec_changed_keys ...
11432 16:45:40.681547 # # SKIP PAUTH not enabled
11433 16:45:40.684720 # # OK global.exec_changed_keys
11434 16:45:40.687920 # ok 5 # SKIP PAUTH not enabled
11435 16:45:40.691557 # # RUN global.context_switch_keep_keys ...
11436 16:45:40.694548 # # SKIP PAUTH not enabled
11437 16:45:40.701038 # # OK global.context_switch_keep_keys
11438 16:45:40.701151 # ok 6 # SKIP PAUTH not enabled
11439 16:45:40.707962 # # RUN global.context_switch_keep_keys_generic ...
11440 16:45:40.711040 # # SKIP Generic PAUTH not enabled
11441 16:45:40.717985 # # OK global.context_switch_keep_keys_generic
11442 16:45:40.721301 # ok 7 # SKIP Generic PAUTH not enabled
11443 16:45:40.724405 # # PASSED: 7 / 7 tests passed.
11444 16:45:40.728178 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11445 16:45:40.731410 ok 28 selftests: arm64: pac
11446 16:45:40.734631 # selftests: arm64: fp-stress
11447 16:45:48.697400 [ 46.047489] vpu: disabling
11448 16:45:48.700319 [ 46.050288] vproc2: disabling
11449 16:45:48.703737 [ 46.053311] vproc1: disabling
11450 16:45:48.706962 [ 46.056337] vaud18: disabling
11451 16:45:48.710571 [ 46.059562] vsram_others: disabling
11452 16:45:48.713590 [ 46.063216] va09: disabling
11453 16:45:48.717277 [ 46.066084] vsram_md: disabling
11454 16:45:48.720307 [ 46.069346] Vgpu: disabling
11455 16:45:50.692256 # TAP version 13
11456 16:45:50.692413 # 1..16
11457 16:45:50.695278 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11458 16:45:50.698759 # # Will run for 10s
11459 16:45:50.698848 # # Started FPSIMD-0-0
11460 16:45:50.702367 # # Started FPSIMD-0-1
11461 16:45:50.705561 # # Started FPSIMD-1-0
11462 16:45:50.705645 # # Started FPSIMD-1-1
11463 16:45:50.708672 # # Started FPSIMD-2-0
11464 16:45:50.708754 # # Started FPSIMD-2-1
11465 16:45:50.711804 # # Started FPSIMD-3-0
11466 16:45:50.715758 # # Started FPSIMD-3-1
11467 16:45:50.715841 # # Started FPSIMD-4-0
11468 16:45:50.718700 # # Started FPSIMD-4-1
11469 16:45:50.721933 # # Started FPSIMD-5-0
11470 16:45:50.722015 # # Started FPSIMD-5-1
11471 16:45:50.725078 # # Started FPSIMD-6-0
11472 16:45:50.725161 # # Started FPSIMD-6-1
11473 16:45:50.728952 # # Started FPSIMD-7-0
11474 16:45:50.732060 # # Started FPSIMD-7-1
11475 16:45:50.735206 # # FPSIMD-1-0: Vector length: 128 bits
11476 16:45:50.735289 # # FPSIMD-1-0: PID: 1133
11477 16:45:50.742287 # # FPSIMD-1-1: Vector length: 128 bits
11478 16:45:50.742370 # # FPSIMD-1-1: PID: 1134
11479 16:45:50.745271 # # FPSIMD-0-0: Vector length: 128 bits
11480 16:45:50.748351 # # FPSIMD-0-0: PID: 1131
11481 16:45:50.752076 # # FPSIMD-0-1: Vector length: 128 bits
11482 16:45:50.755099 # # FPSIMD-0-1: PID: 1132
11483 16:45:50.758604 # # FPSIMD-2-1: Vector length: 128 bits
11484 16:45:50.761934 # # FPSIMD-2-1: PID: 1136
11485 16:45:50.765053 # # FPSIMD-4-0: Vector length: 128 bits
11486 16:45:50.765149 # # FPSIMD-4-0: PID: 1139
11487 16:45:50.768638 # # FPSIMD-4-1: Vector length: 128 bits
11488 16:45:50.771691 # # FPSIMD-4-1: PID: 1140
11489 16:45:50.775033 # # FPSIMD-3-0: Vector length: 128 bits
11490 16:45:50.778602 # # FPSIMD-3-0: PID: 1137
11491 16:45:50.781859 # # FPSIMD-3-1: Vector length: 128 bits
11492 16:45:50.784996 # # FPSIMD-3-1: PID: 1138
11493 16:45:50.788043 # # FPSIMD-2-0: Vector length: 128 bits
11494 16:45:50.791626 # # FPSIMD-2-0: PID: 1135
11495 16:45:50.795113 # # FPSIMD-6-1: Vector length: 128 bits
11496 16:45:50.795196 # # FPSIMD-6-1: PID: 1144
11497 16:45:50.798293 # # FPSIMD-6-0: Vector length: 128 bits
11498 16:45:50.801199 # # FPSIMD-6-0: PID: 1143
11499 16:45:50.804877 # # FPSIMD-5-1: Vector length: 128 bits
11500 16:45:50.807948 # # FPSIMD-5-1: PID: 1142
11501 16:45:50.811564 # # FPSIMD-7-0: Vector length: 128 bits
11502 16:45:50.814721 # # FPSIMD-7-0: PID: 1145
11503 16:45:50.818368 # # FPSIMD-5-0: Vector length: 128 bits
11504 16:45:50.818484 # # FPSIMD-5-0: PID: 1141
11505 16:45:50.821451 # # FPSIMD-7-1: Vector length: 128 bits
11506 16:45:50.825258 # # FPSIMD-7-1: PID: 1146
11507 16:45:50.828421 # # Finishing up...
11508 16:45:50.834853 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=675080, signals=10
11509 16:45:50.841157 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=912635, signals=10
11510 16:45:50.847934 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=662941, signals=10
11511 16:45:50.854956 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=769232, signals=10
11512 16:45:50.861400 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=571529, signals=10
11513 16:45:50.871019 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=985662, signals=10
11514 16:45:50.877381 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=855418, signals=10
11515 16:45:50.877474 # ok 1 FPSIMD-0-0
11516 16:45:50.881099 # ok 2 FPSIMD-0-1
11517 16:45:50.881174 # ok 3 FPSIMD-1-0
11518 16:45:50.884434 # ok 4 FPSIMD-1-1
11519 16:45:50.884516 # ok 5 FPSIMD-2-0
11520 16:45:50.887699 # ok 6 FPSIMD-2-1
11521 16:45:50.887782 # ok 7 FPSIMD-3-0
11522 16:45:50.890607 # ok 8 FPSIMD-3-1
11523 16:45:50.890721 # ok 9 FPSIMD-4-0
11524 16:45:50.894403 # ok 10 FPSIMD-4-1
11525 16:45:50.894556 # ok 11 FPSIMD-5-0
11526 16:45:50.897701 # ok 12 FPSIMD-5-1
11527 16:45:50.897798 # ok 13 FPSIMD-6-0
11528 16:45:50.900601 # ok 14 FPSIMD-6-1
11529 16:45:50.900682 # ok 15 FPSIMD-7-0
11530 16:45:50.904120 # ok 16 FPSIMD-7-1
11531 16:45:50.910684 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1013820, signals=9
11532 16:45:50.917307 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1019562, signals=10
11533 16:45:50.926920 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=443086, signals=10
11534 16:45:50.933682 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1571102, signals=9
11535 16:45:50.940781 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1291257, signals=9
11536 16:45:50.947167 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=405244, signals=9
11537 16:45:50.953866 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=448557, signals=10
11538 16:45:50.960599 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=660558, signals=10
11539 16:45:50.966943 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=509626, signals=10
11540 16:45:50.973665 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11541 16:45:50.977212 ok 29 selftests: arm64: fp-stress
11542 16:45:50.980859 # selftests: arm64: sve-ptrace
11543 16:45:50.980945 # TAP version 13
11544 16:45:50.981010 # 1..4104
11545 16:45:50.983742 # ok 2 # SKIP SVE not available
11546 16:45:50.986917 # # Planned tests != run tests (4104 != 1)
11547 16:45:50.993844 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11548 16:45:50.996897 ok 30 selftests: arm64: sve-ptrace # SKIP
11549 16:45:51.000069 # selftests: arm64: sve-probe-vls
11550 16:45:51.000156 # TAP version 13
11551 16:45:51.003894 # 1..2
11552 16:45:51.003978 # ok 2 # SKIP SVE not available
11553 16:45:51.010603 # # Planned tests != run tests (2 != 1)
11554 16:45:51.013447 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11555 16:45:51.016993 ok 31 selftests: arm64: sve-probe-vls # SKIP
11556 16:45:51.020316 # selftests: arm64: vec-syscfg
11557 16:45:51.023471 # TAP version 13
11558 16:45:51.023560 # 1..20
11559 16:45:51.027038 # ok 1 # SKIP SVE not supported
11560 16:45:51.027124 # ok 2 # SKIP SVE not supported
11561 16:45:51.030454 # ok 3 # SKIP SVE not supported
11562 16:45:51.033424 # ok 4 # SKIP SVE not supported
11563 16:45:51.037024 # ok 5 # SKIP SVE not supported
11564 16:45:51.040186 # ok 6 # SKIP SVE not supported
11565 16:45:51.043387 # ok 7 # SKIP SVE not supported
11566 16:45:51.046699 # ok 8 # SKIP SVE not supported
11567 16:45:51.050356 # ok 9 # SKIP SVE not supported
11568 16:45:51.050445 # ok 10 # SKIP SVE not supported
11569 16:45:51.053661 # ok 11 # SKIP SME not supported
11570 16:45:51.056694 # ok 12 # SKIP SME not supported
11571 16:45:51.060527 # ok 13 # SKIP SME not supported
11572 16:45:51.063678 # ok 14 # SKIP SME not supported
11573 16:45:51.066922 # ok 15 # SKIP SME not supported
11574 16:45:51.069910 # ok 16 # SKIP SME not supported
11575 16:45:51.073268 # ok 17 # SKIP SME not supported
11576 16:45:51.077038 # ok 18 # SKIP SME not supported
11577 16:45:51.077131 # ok 19 # SKIP SME not supported
11578 16:45:51.079946 # ok 20 # SKIP SME not supported
11579 16:45:51.086495 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11580 16:45:51.089945 ok 32 selftests: arm64: vec-syscfg
11581 16:45:51.093028 # selftests: arm64: za-fork
11582 16:45:51.093117 # TAP version 13
11583 16:45:51.093201 # 1..1
11584 16:45:51.096857 # # PID: 1217
11585 16:45:51.096952 # # SME support not present
11586 16:45:51.099977 # ok 0 skipped
11587 16:45:51.103016 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11588 16:45:51.106295 ok 33 selftests: arm64: za-fork
11589 16:45:51.110049 # selftests: arm64: za-ptrace
11590 16:45:51.110129 # TAP version 13
11591 16:45:51.113071 # 1..1
11592 16:45:51.116252 # ok 2 # SKIP SME not available
11593 16:45:51.119726 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11594 16:45:51.123422 ok 34 selftests: arm64: za-ptrace # SKIP
11595 16:45:51.126095 # selftests: arm64: check_buffer_fill
11596 16:45:51.129704 # # SKIP: MTE features unavailable
11597 16:45:51.132770 ok 35 selftests: arm64: check_buffer_fill # SKIP
11598 16:45:51.139350 # selftests: arm64: check_child_memory
11599 16:45:51.139453 # # SKIP: MTE features unavailable
11600 16:45:51.145993 ok 36 selftests: arm64: check_child_memory # SKIP
11601 16:45:51.149900 # selftests: arm64: check_gcr_el1_cswitch
11602 16:45:51.186356 # # SKIP: MTE features unavailable
11603 16:45:51.192497 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11604 16:45:51.204465 # selftests: arm64: check_ksm_options
11605 16:45:51.246835 # # SKIP: MTE features unavailable
11606 16:45:51.253889 ok 38 selftests: arm64: check_ksm_options # SKIP
11607 16:45:51.265841 # selftests: arm64: check_mmap_options
11608 16:45:51.308073 # # SKIP: MTE features unavailable
11609 16:45:51.315003 ok 39 selftests: arm64: check_mmap_options # SKIP
11610 16:45:51.324066 # selftests: arm64: check_prctl
11611 16:45:51.370935 # TAP version 13
11612 16:45:51.371100 # 1..5
11613 16:45:51.373873 # ok 1 check_basic_read
11614 16:45:51.373950 # ok 2 NONE
11615 16:45:51.377431 # ok 3 # SKIP SYNC
11616 16:45:51.377571 # ok 4 # SKIP ASYNC
11617 16:45:51.380580 # ok 5 # SKIP SYNC+ASYNC
11618 16:45:51.384300 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11619 16:45:51.387677 ok 40 selftests: arm64: check_prctl
11620 16:45:51.390682 # selftests: arm64: check_tags_inclusion
11621 16:45:51.435050 # # SKIP: MTE features unavailable
11622 16:45:51.442546 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11623 16:45:51.450594 # selftests: arm64: check_user_mem
11624 16:45:51.496033 # # SKIP: MTE features unavailable
11625 16:45:51.502521 ok 42 selftests: arm64: check_user_mem # SKIP
11626 16:45:51.511347 # selftests: arm64: btitest
11627 16:45:51.555630 # TAP version 13
11628 16:45:51.555777 # 1..18
11629 16:45:51.559451 # # HWCAP_PACA not present
11630 16:45:51.562252 # # HWCAP2_BTI not present
11631 16:45:51.562362 # # Test binary built for BTI
11632 16:45:51.568823 # ok 1 nohint_func/call_using_br_x0 # SKIP
11633 16:45:51.572394 # ok 1 nohint_func/call_using_br_x16 # SKIP
11634 16:45:51.575737 # ok 1 nohint_func/call_using_blr # SKIP
11635 16:45:51.579002 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11636 16:45:51.582423 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11637 16:45:51.585599 # ok 1 bti_none_func/call_using_blr # SKIP
11638 16:45:51.592092 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11639 16:45:51.595585 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11640 16:45:51.598795 # ok 1 bti_c_func/call_using_blr # SKIP
11641 16:45:51.602011 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11642 16:45:51.605778 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11643 16:45:51.608939 # ok 1 bti_j_func/call_using_blr # SKIP
11644 16:45:51.611949 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11645 16:45:51.618607 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11646 16:45:51.622178 # ok 1 bti_jc_func/call_using_blr # SKIP
11647 16:45:51.625736 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11648 16:45:51.629049 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11649 16:45:51.631970 # ok 1 paciasp_func/call_using_blr # SKIP
11650 16:45:51.638996 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11651 16:45:51.642215 # # WARNING - EXPECTED TEST COUNT WRONG
11652 16:45:51.645229 ok 43 selftests: arm64: btitest
11653 16:45:51.645337 # selftests: arm64: nobtitest
11654 16:45:51.648392 # TAP version 13
11655 16:45:51.648495 # 1..18
11656 16:45:51.651751 # # HWCAP_PACA not present
11657 16:45:51.655302 # # HWCAP2_BTI not present
11658 16:45:51.658409 # # Test binary not built for BTI
11659 16:45:51.661529 # ok 1 nohint_func/call_using_br_x0 # SKIP
11660 16:45:51.665030 # ok 1 nohint_func/call_using_br_x16 # SKIP
11661 16:45:51.668696 # ok 1 nohint_func/call_using_blr # SKIP
11662 16:45:51.671671 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11663 16:45:51.675142 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11664 16:45:51.682029 # ok 1 bti_none_func/call_using_blr # SKIP
11665 16:45:51.685358 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11666 16:45:51.688392 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11667 16:45:51.691892 # ok 1 bti_c_func/call_using_blr # SKIP
11668 16:45:51.695227 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11669 16:45:51.698260 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11670 16:45:51.701651 # ok 1 bti_j_func/call_using_blr # SKIP
11671 16:45:51.705260 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11672 16:45:51.711487 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11673 16:45:51.714790 # ok 1 bti_jc_func/call_using_blr # SKIP
11674 16:45:51.718519 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11675 16:45:51.721312 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11676 16:45:51.724857 # ok 1 paciasp_func/call_using_blr # SKIP
11677 16:45:51.731390 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11678 16:45:51.734662 # # WARNING - EXPECTED TEST COUNT WRONG
11679 16:45:51.738426 ok 44 selftests: arm64: nobtitest
11680 16:45:51.738512 # selftests: arm64: hwcap
11681 16:45:51.741770 # TAP version 13
11682 16:45:51.741855 # 1..28
11683 16:45:51.744809 # ok 1 cpuinfo_match_RNG
11684 16:45:51.748060 # # SIGILL reported for RNG
11685 16:45:51.748145 # ok 2 # SKIP sigill_RNG
11686 16:45:51.751190 # ok 3 cpuinfo_match_SME
11687 16:45:51.751306 # ok 4 sigill_SME
11688 16:45:51.755052 # ok 5 cpuinfo_match_SVE
11689 16:45:51.757995 # ok 6 sigill_SVE
11690 16:45:51.758082 # ok 7 cpuinfo_match_SVE 2
11691 16:45:51.761784 # # SIGILL reported for SVE 2
11692 16:45:51.764989 # ok 8 # SKIP sigill_SVE 2
11693 16:45:51.768062 # ok 9 cpuinfo_match_SVE AES
11694 16:45:51.771123 # # SIGILL reported for SVE AES
11695 16:45:51.771209 # ok 10 # SKIP sigill_SVE AES
11696 16:45:51.774612 # ok 11 cpuinfo_match_SVE2 PMULL
11697 16:45:51.778098 # # SIGILL reported for SVE2 PMULL
11698 16:45:51.781175 # ok 12 # SKIP sigill_SVE2 PMULL
11699 16:45:51.784861 # ok 13 cpuinfo_match_SVE2 BITPERM
11700 16:45:51.787892 # # SIGILL reported for SVE2 BITPERM
11701 16:45:51.791498 # ok 14 # SKIP sigill_SVE2 BITPERM
11702 16:45:51.794437 # ok 15 cpuinfo_match_SVE2 SHA3
11703 16:45:51.798268 # # SIGILL reported for SVE2 SHA3
11704 16:45:51.801323 # ok 16 # SKIP sigill_SVE2 SHA3
11705 16:45:51.801412 # ok 17 cpuinfo_match_SVE2 SM4
11706 16:45:51.804480 # # SIGILL reported for SVE2 SM4
11707 16:45:51.807733 # ok 18 # SKIP sigill_SVE2 SM4
11708 16:45:51.811378 # ok 19 cpuinfo_match_SVE2 I8MM
11709 16:45:51.814484 # # SIGILL reported for SVE2 I8MM
11710 16:45:51.817699 # ok 20 # SKIP sigill_SVE2 I8MM
11711 16:45:51.820864 # ok 21 cpuinfo_match_SVE2 F32MM
11712 16:45:51.824565 # # SIGILL reported for SVE2 F32MM
11713 16:45:51.827738 # ok 22 # SKIP sigill_SVE2 F32MM
11714 16:45:51.827829 # ok 23 cpuinfo_match_SVE2 F64MM
11715 16:45:51.830663 # # SIGILL reported for SVE2 F64MM
11716 16:45:51.834331 # ok 24 # SKIP sigill_SVE2 F64MM
11717 16:45:51.837319 # ok 25 cpuinfo_match_SVE2 BF16
11718 16:45:51.840854 # # SIGILL reported for SVE2 BF16
11719 16:45:51.844408 # ok 26 # SKIP sigill_SVE2 BF16
11720 16:45:51.847596 # ok 27 cpuinfo_match_SVE2 EBF16
11721 16:45:51.850927 # ok 28 # SKIP sigill_SVE2 EBF16
11722 16:45:51.853888 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11723 16:45:51.857089 ok 45 selftests: arm64: hwcap
11724 16:45:51.860884 # selftests: arm64: ptrace
11725 16:45:51.860965 # TAP version 13
11726 16:45:51.863946 # 1..7
11727 16:45:51.864052 # # Parent is 1446, child is 1447
11728 16:45:51.867013 # ok 1 read_tpidr_one
11729 16:45:51.870323 # ok 2 write_tpidr_one
11730 16:45:51.870408 # ok 3 verify_tpidr_one
11731 16:45:51.873964 # ok 4 count_tpidrs
11732 16:45:51.874041 # ok 5 tpidr2_write
11733 16:45:51.877673 # ok 6 tpidr2_read
11734 16:45:51.880695 # ok 7 write_tpidr_only
11735 16:45:51.883922 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11736 16:45:51.887406 ok 46 selftests: arm64: ptrace
11737 16:45:51.890575 # selftests: arm64: syscall-abi
11738 16:45:51.890670 # TAP version 13
11739 16:45:51.890736 # 1..2
11740 16:45:51.893476 # ok 1 getpid() FPSIMD
11741 16:45:51.897277 # ok 2 sched_yield() FPSIMD
11742 16:45:51.900383 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11743 16:45:51.903884 ok 47 selftests: arm64: syscall-abi
11744 16:45:51.906961 # selftests: arm64: tpidr2
11745 16:45:51.910745 # TAP version 13
11746 16:45:51.910836 # 1..5
11747 16:45:51.910901 # # PID: 1482
11748 16:45:51.913807 # # SME support not present
11749 16:45:51.917110 # ok 0 skipped, TPIDR2 not supported
11750 16:45:51.920345 # ok 1 skipped, TPIDR2 not supported
11751 16:45:51.923395 # ok 2 skipped, TPIDR2 not supported
11752 16:45:51.927082 # ok 3 skipped, TPIDR2 not supported
11753 16:45:51.930264 # ok 4 skipped, TPIDR2 not supported
11754 16:45:51.933675 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11755 16:45:51.936602 ok 48 selftests: arm64: tpidr2
11756 16:45:52.375077 arm64_tags_test pass
11757 16:45:52.378764 arm64_run_tags_test_sh pass
11758 16:45:52.381868 arm64_fake_sigreturn_bad_magic pass
11759 16:45:52.385602 arm64_fake_sigreturn_bad_size pass
11760 16:45:52.388744 arm64_fake_sigreturn_bad_size_for_magic0 pass
11761 16:45:52.391845 arm64_fake_sigreturn_duplicated_fpsimd pass
11762 16:45:52.395103 arm64_fake_sigreturn_misaligned_sp pass
11763 16:45:52.398703 arm64_fake_sigreturn_missing_fpsimd pass
11764 16:45:52.402053 arm64_fake_sigreturn_sme_change_vl skip
11765 16:45:52.404931 arm64_fake_sigreturn_sve_change_vl skip
11766 16:45:52.411477 arm64_mangle_pstate_invalid_compat_toggle pass
11767 16:45:52.415199 arm64_mangle_pstate_invalid_daif_bits pass
11768 16:45:52.418884 arm64_mangle_pstate_invalid_mode_el1h pass
11769 16:45:52.421871 arm64_mangle_pstate_invalid_mode_el1t pass
11770 16:45:52.425018 arm64_mangle_pstate_invalid_mode_el2h pass
11771 16:45:52.428010 arm64_mangle_pstate_invalid_mode_el2t pass
11772 16:45:52.435164 arm64_mangle_pstate_invalid_mode_el3h pass
11773 16:45:52.438193 arm64_mangle_pstate_invalid_mode_el3t pass
11774 16:45:52.438278 arm64_sme_trap_no_sm skip
11775 16:45:52.441864 arm64_sme_trap_non_streaming skip
11776 16:45:52.444950 arm64_sme_trap_za pass
11777 16:45:52.448048 arm64_sme_vl skip
11778 16:45:52.448133 arm64_ssve_regs skip
11779 16:45:52.451610 arm64_sve_regs skip
11780 16:45:52.451694 arm64_sve_vl skip
11781 16:45:52.454737 arm64_za_no_regs skip
11782 16:45:52.454818 arm64_za_regs skip
11783 16:45:52.458404 arm64_pac_PAUTH_not_enabled skip
11784 16:45:52.461763 arm64_pac_PAUTH_not_enabled skip
11785 16:45:52.464803 arm64_pac_Generic_PAUTH_not_enabled skip
11786 16:45:52.468421 arm64_pac_PAUTH_not_enabled skip
11787 16:45:52.471489 arm64_pac_PAUTH_not_enabled skip
11788 16:45:52.474918 arm64_pac_PAUTH_not_enabled skip
11789 16:45:52.477898 arm64_pac_Generic_PAUTH_not_enabled skip
11790 16:45:52.477980 arm64_pac pass
11791 16:45:52.481467 arm64_fp-stress_FPSIMD-0-0 pass
11792 16:45:52.484607 arm64_fp-stress_FPSIMD-0-1 pass
11793 16:45:52.488216 arm64_fp-stress_FPSIMD-1-0 pass
11794 16:45:52.491596 arm64_fp-stress_FPSIMD-1-1 pass
11795 16:45:52.495006 arm64_fp-stress_FPSIMD-2-0 pass
11796 16:45:52.498031 arm64_fp-stress_FPSIMD-2-1 pass
11797 16:45:52.498114 arm64_fp-stress_FPSIMD-3-0 pass
11798 16:45:52.501232 arm64_fp-stress_FPSIMD-3-1 pass
11799 16:45:52.504518 arm64_fp-stress_FPSIMD-4-0 pass
11800 16:45:52.507688 arm64_fp-stress_FPSIMD-4-1 pass
11801 16:45:52.511364 arm64_fp-stress_FPSIMD-5-0 pass
11802 16:45:52.514566 arm64_fp-stress_FPSIMD-5-1 pass
11803 16:45:52.517681 arm64_fp-stress_FPSIMD-6-0 pass
11804 16:45:52.517764 arm64_fp-stress_FPSIMD-6-1 pass
11805 16:45:52.520962 arm64_fp-stress_FPSIMD-7-0 pass
11806 16:45:52.524631 arm64_fp-stress_FPSIMD-7-1 pass
11807 16:45:52.528032 arm64_fp-stress pass
11808 16:45:52.531190 arm64_sve-ptrace_SVE_not_available skip
11809 16:45:52.531272 arm64_sve-ptrace skip
11810 16:45:52.537380 arm64_sve-probe-vls_SVE_not_available skip
11811 16:45:52.537461 arm64_sve-probe-vls skip
11812 16:45:52.540913 arm64_vec-syscfg_SVE_not_supported skip
11813 16:45:52.544330 arm64_vec-syscfg_SVE_not_supported skip
11814 16:45:52.547817 arm64_vec-syscfg_SVE_not_supported skip
11815 16:45:52.554485 arm64_vec-syscfg_SVE_not_supported skip
11816 16:45:52.557454 arm64_vec-syscfg_SVE_not_supported skip
11817 16:45:52.561270 arm64_vec-syscfg_SVE_not_supported skip
11818 16:45:52.564383 arm64_vec-syscfg_SVE_not_supported skip
11819 16:45:52.567660 arm64_vec-syscfg_SVE_not_supported skip
11820 16:45:52.571366 arm64_vec-syscfg_SVE_not_supported skip
11821 16:45:52.574311 arm64_vec-syscfg_SVE_not_supported skip
11822 16:45:52.577421 arm64_vec-syscfg_SME_not_supported skip
11823 16:45:52.580910 arm64_vec-syscfg_SME_not_supported skip
11824 16:45:52.583939 arm64_vec-syscfg_SME_not_supported skip
11825 16:45:52.587534 arm64_vec-syscfg_SME_not_supported skip
11826 16:45:52.590524 arm64_vec-syscfg_SME_not_supported skip
11827 16:45:52.594083 arm64_vec-syscfg_SME_not_supported skip
11828 16:45:52.600776 arm64_vec-syscfg_SME_not_supported skip
11829 16:45:52.603992 arm64_vec-syscfg_SME_not_supported skip
11830 16:45:52.607163 arm64_vec-syscfg_SME_not_supported skip
11831 16:45:52.610930 arm64_vec-syscfg_SME_not_supported skip
11832 16:45:52.611013 arm64_vec-syscfg pass
11833 16:45:52.614119 arm64_za-fork_skipped pass
11834 16:45:52.617220 arm64_za-fork pass
11835 16:45:52.620446 arm64_za-ptrace_SME_not_available skip
11836 16:45:52.620529 arm64_za-ptrace skip
11837 16:45:52.623621 arm64_check_buffer_fill skip
11838 16:45:52.627420 arm64_check_child_memory skip
11839 16:45:52.630198 arm64_check_gcr_el1_cswitch skip
11840 16:45:52.630282 arm64_check_ksm_options skip
11841 16:45:52.633954 arm64_check_mmap_options skip
11842 16:45:52.637142 arm64_check_prctl_check_basic_read pass
11843 16:45:52.640112 arm64_check_prctl_NONE pass
11844 16:45:52.643920 arm64_check_prctl_SYNC skip
11845 16:45:52.646913 arm64_check_prctl_ASYNC skip
11846 16:45:52.650771 arm64_check_prctl_SYNC_ASYNC skip
11847 16:45:52.650884 arm64_check_prctl pass
11848 16:45:52.653716 arm64_check_tags_inclusion skip
11849 16:45:52.657193 arm64_check_user_mem skip
11850 16:45:52.660327 arm64_btitest_nohint_func_call_using_br_x0 skip
11851 16:45:52.663394 arm64_btitest_nohint_func_call_using_br_x16 skip
11852 16:45:52.670155 arm64_btitest_nohint_func_call_using_blr skip
11853 16:45:52.673398 arm64_btitest_bti_none_func_call_using_br_x0 skip
11854 16:45:52.677006 arm64_btitest_bti_none_func_call_using_br_x16 skip
11855 16:45:52.683267 arm64_btitest_bti_none_func_call_using_blr skip
11856 16:45:52.686955 arm64_btitest_bti_c_func_call_using_br_x0 skip
11857 16:45:52.689921 arm64_btitest_bti_c_func_call_using_br_x16 skip
11858 16:45:52.693145 arm64_btitest_bti_c_func_call_using_blr skip
11859 16:45:52.699763 arm64_btitest_bti_j_func_call_using_br_x0 skip
11860 16:45:52.703388 arm64_btitest_bti_j_func_call_using_br_x16 skip
11861 16:45:52.706432 arm64_btitest_bti_j_func_call_using_blr skip
11862 16:45:52.710060 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11863 16:45:52.716245 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11864 16:45:52.719960 arm64_btitest_bti_jc_func_call_using_blr skip
11865 16:45:52.723294 arm64_btitest_paciasp_func_call_using_br_x0 skip
11866 16:45:52.729716 arm64_btitest_paciasp_func_call_using_br_x16 skip
11867 16:45:52.733134 arm64_btitest_paciasp_func_call_using_blr skip
11868 16:45:52.733229 arm64_btitest pass
11869 16:45:52.739771 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11870 16:45:52.743169 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11871 16:45:52.746253 arm64_nobtitest_nohint_func_call_using_blr skip
11872 16:45:52.753000 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11873 16:45:52.756092 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11874 16:45:52.759689 arm64_nobtitest_bti_none_func_call_using_blr skip
11875 16:45:52.766016 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11876 16:45:52.769760 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11877 16:45:52.772770 arm64_nobtitest_bti_c_func_call_using_blr skip
11878 16:45:52.779593 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11879 16:45:52.782695 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11880 16:45:52.785917 arm64_nobtitest_bti_j_func_call_using_blr skip
11881 16:45:52.792882 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11882 16:45:52.795873 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11883 16:45:52.799332 arm64_nobtitest_bti_jc_func_call_using_blr skip
11884 16:45:52.805739 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11885 16:45:52.809313 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11886 16:45:52.812425 arm64_nobtitest_paciasp_func_call_using_blr skip
11887 16:45:52.816073 arm64_nobtitest pass
11888 16:45:52.819227 arm64_hwcap_cpuinfo_match_RNG pass
11889 16:45:52.822364 arm64_hwcap_sigill_RNG skip
11890 16:45:52.825630 arm64_hwcap_cpuinfo_match_SME pass
11891 16:45:52.825728 arm64_hwcap_sigill_SME pass
11892 16:45:52.829362 arm64_hwcap_cpuinfo_match_SVE pass
11893 16:45:52.832601 arm64_hwcap_sigill_SVE pass
11894 16:45:52.835814 arm64_hwcap_cpuinfo_match_SVE_2 pass
11895 16:45:52.838913 arm64_hwcap_sigill_SVE_2 skip
11896 16:45:52.842768 arm64_hwcap_cpuinfo_match_SVE_AES pass
11897 16:45:52.845798 arm64_hwcap_sigill_SVE_AES skip
11898 16:45:52.848975 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11899 16:45:52.852104 arm64_hwcap_sigill_SVE2_PMULL skip
11900 16:45:52.855688 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11901 16:45:52.858823 arm64_hwcap_sigill_SVE2_BITPERM skip
11902 16:45:52.861871 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11903 16:45:52.865651 arm64_hwcap_sigill_SVE2_SHA3 skip
11904 16:45:52.868588 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11905 16:45:52.872092 arm64_hwcap_sigill_SVE2_SM4 skip
11906 16:45:52.875455 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11907 16:45:52.878597 arm64_hwcap_sigill_SVE2_I8MM skip
11908 16:45:52.882067 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11909 16:45:52.885035 arm64_hwcap_sigill_SVE2_F32MM skip
11910 16:45:52.888318 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11911 16:45:52.892032 arm64_hwcap_sigill_SVE2_F64MM skip
11912 16:45:52.895316 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11913 16:45:52.898572 arm64_hwcap_sigill_SVE2_BF16 skip
11914 16:45:52.901643 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11915 16:45:52.905050 arm64_hwcap_sigill_SVE2_EBF16 skip
11916 16:45:52.908043 arm64_hwcap pass
11917 16:45:52.911792 arm64_ptrace_read_tpidr_one pass
11918 16:45:52.914627 arm64_ptrace_write_tpidr_one pass
11919 16:45:52.918438 arm64_ptrace_verify_tpidr_one pass
11920 16:45:52.918521 arm64_ptrace_count_tpidrs pass
11921 16:45:52.921378 arm64_ptrace_tpidr2_write pass
11922 16:45:52.924598 arm64_ptrace_tpidr2_read pass
11923 16:45:52.927928 arm64_ptrace_write_tpidr_only pass
11924 16:45:52.928030 arm64_ptrace pass
11925 16:45:52.931775 arm64_syscall-abi_getpid_FPSIMD pass
11926 16:45:52.938044 arm64_syscall-abi_sched_yield_FPSIMD pass
11927 16:45:52.938130 arm64_syscall-abi pass
11928 16:45:52.941157 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11929 16:45:52.948058 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11930 16:45:52.951492 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11931 16:45:52.954453 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11932 16:45:52.961048 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11933 16:45:52.961155 arm64_tpidr2 pass
11934 16:45:52.964170 + ../../utils/send-to-lava.sh ./output/result.txt
11935 16:45:52.971077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
11936 16:45:52.971382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
11938 16:45:52.977746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
11939 16:45:52.978003 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
11941 16:45:52.984367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
11942 16:45:52.984621 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
11944 16:45:52.991088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
11945 16:45:52.991379 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
11947 16:45:52.997853 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
11949 16:45:53.000820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
11950 16:45:53.007107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
11951 16:45:53.007403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
11953 16:45:53.013730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
11954 16:45:53.013982 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
11956 16:45:53.020502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
11957 16:45:53.020776 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
11959 16:45:53.027187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
11960 16:45:53.027475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
11962 16:45:53.053798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
11963 16:45:53.054097 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
11965 16:45:53.087399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
11966 16:45:53.087732 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
11968 16:45:53.122194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
11969 16:45:53.122498 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
11971 16:45:53.153414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
11972 16:45:53.153793 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
11974 16:45:53.191324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
11975 16:45:53.191640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
11977 16:45:53.225309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
11978 16:45:53.225661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
11980 16:45:53.266461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
11981 16:45:53.266769 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
11983 16:45:53.297775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
11984 16:45:53.298062 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
11986 16:45:53.336230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
11987 16:45:53.336547 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
11989 16:45:53.366100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
11990 16:45:53.366407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
11992 16:45:53.399915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
11994 16:45:53.403031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
11995 16:45:53.442950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
11996 16:45:53.443251 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
11998 16:45:53.478001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
11999 16:45:53.478305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12001 16:45:53.522574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12002 16:45:53.522882 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12004 16:45:53.557287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12005 16:45:53.557597 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12007 16:45:53.587960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12008 16:45:53.588341 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12010 16:45:53.628848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12011 16:45:53.629158 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12013 16:45:53.660186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12014 16:45:53.660496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12016 16:45:53.695399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12017 16:45:53.695709 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12019 16:45:53.723607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12021 16:45:53.726671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12022 16:45:53.754327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12023 16:45:53.754691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12025 16:45:53.782085 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12027 16:45:53.784822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12028 16:45:53.819319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12030 16:45:53.822775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12031 16:45:53.851915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12033 16:45:53.855485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12034 16:45:53.889366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12035 16:45:53.889691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12037 16:45:53.922164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12038 16:45:53.922497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12040 16:45:53.954805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12041 16:45:53.955126 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12043 16:45:53.988318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12044 16:45:53.988632 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12046 16:45:54.026122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12047 16:45:54.026452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12049 16:45:54.057669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12050 16:45:54.057978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12052 16:45:54.089433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12053 16:45:54.089783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12055 16:45:54.117849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12056 16:45:54.118181 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12058 16:45:54.151470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12059 16:45:54.151860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12061 16:45:54.183808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12062 16:45:54.184132 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12064 16:45:54.224422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12065 16:45:54.224774 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12067 16:45:54.262709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12068 16:45:54.263017 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12070 16:45:54.296190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12071 16:45:54.296507 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12073 16:45:54.339306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12074 16:45:54.339631 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12076 16:45:54.376040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12077 16:45:54.376356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12079 16:45:54.407218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12080 16:45:54.407572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12082 16:45:54.446988 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12083 16:45:54.447316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12085 16:45:54.481351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12086 16:45:54.481705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12088 16:45:54.519290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12089 16:45:54.519640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12091 16:45:54.558023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12092 16:45:54.558352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12094 16:45:54.593870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12095 16:45:54.594184 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12097 16:45:54.632028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12098 16:45:54.632350 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12100 16:45:54.670116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12101 16:45:54.670422 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12103 16:45:54.706492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12104 16:45:54.706804 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12106 16:45:54.746526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12107 16:45:54.746855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12109 16:45:54.783236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12110 16:45:54.783571 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12112 16:45:54.822697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12113 16:45:54.823014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12115 16:45:54.854769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12116 16:45:54.855092 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12118 16:45:54.896087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12119 16:45:54.896410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12121 16:45:54.928299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12122 16:45:54.928653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12124 16:45:54.968059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12125 16:45:54.968386 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12127 16:45:55.006080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12128 16:45:55.006388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12130 16:45:55.044959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12131 16:45:55.045284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12133 16:45:55.078293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12134 16:45:55.078579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12136 16:45:55.113884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12137 16:45:55.114196 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12139 16:45:55.144461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12140 16:45:55.144779 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12142 16:45:55.174814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12143 16:45:55.175131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12145 16:45:55.214585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12146 16:45:55.214922 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12148 16:45:55.249640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12149 16:45:55.249994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12151 16:45:55.290744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12152 16:45:55.291086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12154 16:45:55.323628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12155 16:45:55.323966 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12157 16:45:55.360190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12158 16:45:55.360521 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12160 16:45:55.391165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12161 16:45:55.391478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12163 16:45:55.429243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12164 16:45:55.429567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12166 16:45:55.460676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12167 16:45:55.460960 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12169 16:45:55.498922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12170 16:45:55.499198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12172 16:45:55.537420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12173 16:45:55.537855 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12175 16:45:55.570309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12176 16:45:55.570665 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12178 16:45:55.603484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12179 16:45:55.603807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12181 16:45:55.639964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12182 16:45:55.640313 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12184 16:45:55.672205 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12186 16:45:55.675007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12187 16:45:55.709746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12188 16:45:55.710053 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12190 16:45:55.743611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12191 16:45:55.743916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12193 16:45:55.779943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12194 16:45:55.780258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12196 16:45:55.811420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12197 16:45:55.811778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12199 16:45:55.851161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12200 16:45:55.851487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12202 16:45:55.885251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12203 16:45:55.885568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12205 16:45:55.920407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12207 16:45:55.923820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12208 16:45:55.955656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12209 16:45:55.955980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12211 16:45:55.986730 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12213 16:45:55.989758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12214 16:45:56.024449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12215 16:45:56.024733 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12217 16:45:56.061790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12218 16:45:56.062086 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12220 16:45:56.095596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12221 16:45:56.095888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12223 16:45:56.127910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12224 16:45:56.128200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12226 16:45:56.159791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12227 16:45:56.160083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12229 16:45:56.196610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12230 16:45:56.196895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12232 16:45:56.232285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12233 16:45:56.232579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12235 16:45:56.269718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12236 16:45:56.270010 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12238 16:45:56.304836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12239 16:45:56.305119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12241 16:45:56.341312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12242 16:45:56.341609 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12244 16:45:56.372613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12245 16:45:56.372913 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12247 16:45:56.405677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12248 16:45:56.405968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12250 16:45:56.442229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12251 16:45:56.442524 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12253 16:45:56.478899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12254 16:45:56.479191 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12256 16:45:56.511959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12257 16:45:56.512258 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12259 16:45:56.545908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12260 16:45:56.546224 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12262 16:45:56.579293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12263 16:45:56.579579 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12265 16:45:56.621564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12266 16:45:56.621866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12268 16:45:56.654278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12269 16:45:56.654575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12271 16:45:56.698509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12272 16:45:56.698802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12274 16:45:56.737894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12275 16:45:56.738193 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12277 16:45:56.778109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12278 16:45:56.778395 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12280 16:45:56.816064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12281 16:45:56.816336 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12283 16:45:56.854377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12284 16:45:56.854689 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12286 16:45:56.898731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12287 16:45:56.899035 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12289 16:45:56.936282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12290 16:45:56.936594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12292 16:45:56.986729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12293 16:45:56.987014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12295 16:45:57.023419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12296 16:45:57.023685 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12298 16:45:57.065449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12299 16:45:57.065738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12301 16:45:57.100965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12302 16:45:57.101250 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12304 16:45:57.141457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12305 16:45:57.141784 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12307 16:45:57.175215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12308 16:45:57.175475 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12310 16:45:57.208710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12311 16:45:57.208997 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12313 16:45:57.245388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12314 16:45:57.245705 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12316 16:45:57.274639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12317 16:45:57.274916 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12319 16:45:57.309681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12320 16:45:57.309965 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12322 16:45:57.343209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12323 16:45:57.343497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12325 16:45:57.385803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12326 16:45:57.386073 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12328 16:45:57.417049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12329 16:45:57.417311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12331 16:45:57.459742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12332 16:45:57.460056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12334 16:45:57.499581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12335 16:45:57.499888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12337 16:45:57.542528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12338 16:45:57.542842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12340 16:45:57.587747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12341 16:45:57.588054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12343 16:45:57.630474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12344 16:45:57.630783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12346 16:45:57.674596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12347 16:45:57.674908 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12349 16:45:57.715411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12350 16:45:57.715711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12352 16:45:57.749612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12353 16:45:57.749895 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12355 16:45:57.790621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12356 16:45:57.790900 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12358 16:45:57.821928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12359 16:45:57.822188 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12361 16:45:57.862298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12362 16:45:57.862562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12364 16:45:57.898010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12365 16:45:57.898272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12367 16:45:57.932179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12368 16:45:57.932451 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12370 16:45:57.963947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12371 16:45:57.964211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12373 16:45:58.002361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12374 16:45:58.002627 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12376 16:45:58.030214 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12378 16:45:58.033095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12379 16:45:58.064518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12380 16:45:58.064778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12382 16:45:58.095373 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12384 16:45:58.098277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12385 16:45:58.130018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12386 16:45:58.130311 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12388 16:45:58.163514 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12390 16:45:58.166580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12391 16:45:58.198973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12392 16:45:58.199234 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12394 16:45:58.239080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12395 16:45:58.239356 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12397 16:45:58.273425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12398 16:45:58.273690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12400 16:45:58.313245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12401 16:45:58.313531 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12403 16:45:58.349220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12404 16:45:58.349543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12406 16:45:58.380768 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12408 16:45:58.383725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12409 16:45:58.426485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12410 16:45:58.426745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12412 16:45:58.459690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12413 16:45:58.459961 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12415 16:45:58.490899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12416 16:45:58.491175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12418 16:45:58.527006 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12420 16:45:58.530051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12421 16:45:58.559890 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12423 16:45:58.562972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12424 16:45:58.602025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12425 16:45:58.602294 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12427 16:45:58.630974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12428 16:45:58.631231 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12430 16:45:58.667018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12431 16:45:58.667286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12433 16:45:58.706177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12434 16:45:58.706440 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12436 16:45:58.740884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12437 16:45:58.741151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12439 16:45:58.776599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12440 16:45:58.776860 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12442 16:45:58.822134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12443 16:45:58.822398 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12445 16:45:58.856488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12446 16:45:58.856751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12448 16:45:58.886149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12449 16:45:58.886406 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12451 16:45:58.924849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12452 16:45:58.925111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12454 16:45:58.962325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12455 16:45:58.962588 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12457 16:45:58.994383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12458 16:45:58.994644 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12460 16:45:59.036569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12461 16:45:59.036840 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12463 16:45:59.069421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12464 16:45:59.069724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12466 16:45:59.108371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12467 16:45:59.108480 + set +x
12468 16:45:59.108747 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12470 16:45:59.114572 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10576287_1.6.2.3.5>
12471 16:45:59.114836 Received signal: <ENDRUN> 1_kselftest-arm64 10576287_1.6.2.3.5
12472 16:45:59.114908 Ending use of test pattern.
12473 16:45:59.114969 Ending test lava.1_kselftest-arm64 (10576287_1.6.2.3.5), duration 27.84
12475 16:45:59.118298 <LAVA_TEST_RUNNER EXIT>
12476 16:45:59.118550 ok: lava_test_shell seems to have completed
12477 16:45:59.119544 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12478 16:45:59.119688 end: 3.1 lava-test-shell (duration 00:00:29) [common]
12479 16:45:59.119776 end: 3 lava-test-retry (duration 00:00:29) [common]
12480 16:45:59.119865 start: 4 finalize (timeout 00:07:21) [common]
12481 16:45:59.119952 start: 4.1 power-off (timeout 00:00:30) [common]
12482 16:45:59.120108 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
12483 16:45:59.195849 >> Command sent successfully.
12484 16:45:59.198243 Returned 0 in 0 seconds
12485 16:45:59.298609 end: 4.1 power-off (duration 00:00:00) [common]
12487 16:45:59.299045 start: 4.2 read-feedback (timeout 00:07:21) [common]
12488 16:45:59.299355 Listened to connection for namespace 'common' for up to 1s
12489 16:46:00.300265 Finalising connection for namespace 'common'
12490 16:46:00.300457 Disconnecting from shell: Finalise
12491 16:46:00.300546 / #
12492 16:46:00.400850 end: 4.2 read-feedback (duration 00:00:01) [common]
12493 16:46:00.401051 end: 4 finalize (duration 00:00:01) [common]
12494 16:46:00.401212 Cleaning after the job
12495 16:46:00.401354 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/ramdisk
12496 16:46:00.403471 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/kernel
12497 16:46:00.412432 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/dtb
12498 16:46:00.412649 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/nfsrootfs
12499 16:46:00.481881 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10576287/tftp-deploy-7h04q_ty/modules
12500 16:46:00.487650 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10576287
12501 16:46:01.038604 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10576287
12502 16:46:01.038841 Job finished correctly